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-rw-r--r--arch/blackfin/mach-bf533/head.S48
1 files changed, 0 insertions, 48 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 184296bee3c9..d59db86195b6 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -35,54 +35,6 @@
35#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
36#endif 36#endif
37 37
38.extern _bf53x_relocate_l1_mem
39
40__INIT
41
42ENTRY(_mach_early_start)
43 p0.h = hi(FIO_MASKA_C);
44 p0.l = lo(FIO_MASKA_C);
45 r0 = 0xFFFF(Z);
46 w[p0] = r0.L; /* Disable all interrupts */
47 ssync;
48
49 p0.h = hi(FIO_MASKB_C);
50 p0.l = lo(FIO_MASKB_C);
51 r0 = 0xFFFF(Z);
52 w[p0] = r0.L; /* Disable all interrupts */
53 ssync;
54
55 /* Initialise UART - when booting from u-boot, the UART is not disabled
56 * so if we dont initalize here, our serial console gets hosed */
57 p0.h = hi(BFIN_UART_LCR);
58 p0.l = lo(BFIN_UART_LCR);
59 r0 = 0x0(Z);
60 w[p0] = r0.L; /* To enable DLL writes */
61 ssync;
62
63 p0.h = hi(BFIN_UART_DLL);
64 p0.l = lo(BFIN_UART_DLL);
65 r0 = 0x0(Z);
66 w[p0] = r0.L;
67 ssync;
68
69 p0.h = hi(BFIN_UART_DLH);
70 p0.l = lo(BFIN_UART_DLH);
71 r0 = 0x00(Z);
72 w[p0] = r0.L;
73 ssync;
74
75 p0.h = hi(BFIN_UART_GCTL);
76 p0.l = lo(BFIN_UART_GCTL);
77 r0 = 0x0(Z);
78 w[p0] = r0.L; /* To enable UART clock */
79 ssync;
80
81 rts;
82ENDPROC(_mach_early_start)
83
84__FINIT
85
86.section .l1.text 38.section .l1.text
87#ifdef CONFIG_BFIN_KERNEL_CLOCK 39#ifdef CONFIG_BFIN_KERNEL_CLOCK
88ENTRY(_start_dma_code) 40ENTRY(_start_dma_code)