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-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c15
1 files changed, 1 insertions, 14 deletions
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 644be5e5ab6f..8ec42ba35b9e 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -20,6 +20,7 @@
20#endif 20#endif
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <asm/bfin5xx_spi.h> 22#include <asm/bfin5xx_spi.h>
23#include <asm/portmux.h>
23 24
24/* 25/*
25 * Name the Board for the /proc/cpuinfo 26 * Name the Board for the /proc/cpuinfo
@@ -107,20 +108,6 @@ static struct platform_device dm9000_device2 = {
107 108
108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 109#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
109static struct bfin5xx_spi_chip mmc_spi_chip_info = { 110static struct bfin5xx_spi_chip mmc_spi_chip_info = {
110/*
111 * CPOL (Clock Polarity)
112 * 0 - Active high SCK
113 * 1 - Active low SCK
114 * CPHA (Clock Phase) Selects transfer format and operation mode
115 * 0 - SCLK toggles from middle of the first data bit, slave select
116 * pins controlled by hardware.
117 * 1 - SCLK toggles from beginning of first data bit, slave select
118 * pins controller by user software.
119 * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
120 * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
121 * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
122 */
123 .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
124 .enable_dma = 0, /* if 1 - block!!! */ 111 .enable_dma = 0, /* if 1 - block!!! */
125 .bits_per_word = 8, 112 .bits_per_word = 8,
126}; 113};