diff options
Diffstat (limited to 'arch/blackfin/mach-bf527')
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index 3e000756aacd..09475034c6a1 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h | |||
| @@ -749,51 +749,6 @@ | |||
| 749 | #define FFE 0x20 /* Force Framing Error On Transmit */ | 749 | #define FFE 0x20 /* Force Framing Error On Transmit */ |
| 750 | 750 | ||
| 751 | 751 | ||
| 752 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ | ||
| 753 | /* SPI_CTL Masks */ | ||
| 754 | #define TIMOD 0x0003 /* Transfer Initiate Mode */ | ||
| 755 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ | ||
| 756 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | ||
| 757 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | ||
| 758 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | ||
| 759 | #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ | ||
| 760 | #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ | ||
| 761 | #define PSSE 0x0010 /* Slave-Select Input Enable */ | ||
| 762 | #define EMISO 0x0020 /* Enable MISO As Output */ | ||
| 763 | #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ | ||
| 764 | #define LSBF 0x0200 /* LSB First */ | ||
| 765 | #define CPHA 0x0400 /* Clock Phase */ | ||
| 766 | #define CPOL 0x0800 /* Clock Polarity */ | ||
| 767 | #define MSTR 0x1000 /* Master/Slave* */ | ||
| 768 | #define WOM 0x2000 /* Write Open Drain Master */ | ||
| 769 | #define SPE 0x4000 /* SPI Enable */ | ||
| 770 | |||
| 771 | /* SPI_FLG Masks */ | ||
| 772 | #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ | ||
| 773 | #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ | ||
| 774 | #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ | ||
| 775 | #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ | ||
| 776 | #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ | ||
| 777 | #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ | ||
| 778 | #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ | ||
| 779 | #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ | ||
| 780 | #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ | ||
| 781 | #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ | ||
| 782 | #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ | ||
| 783 | #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ | ||
| 784 | #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ | ||
| 785 | #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ | ||
| 786 | |||
| 787 | /* SPI_STAT Masks */ | ||
| 788 | #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ | ||
| 789 | #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ | ||
| 790 | #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ | ||
| 791 | #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ | ||
| 792 | #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ | ||
| 793 | #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ | ||
| 794 | #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ | ||
| 795 | |||
| 796 | |||
| 797 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ | 752 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ |
| 798 | /* TIMER_ENABLE Masks */ | 753 | /* TIMER_ENABLE Masks */ |
| 799 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | 754 | #define TIMEN0 0x0001 /* Enable Timer 0 */ |