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-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h160
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bf527.h21
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h27
-rw-r--r--arch/blackfin/mach-bf527/include/mach/portmux.h4
4 files changed, 163 insertions, 49 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index b7b166f4f064..62373e61c585 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -7,12 +7,24 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List 10 * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
11 * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
11 */ 12 */
12 13
13#ifndef _MACH_ANOMALY_H_ 14#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_ 15#define _MACH_ANOMALY_H_
15 16
17#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
18# define ANOMALY_BF526 1
19#else
20# define ANOMALY_BF526 0
21#endif
22#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
23# define ANOMALY_BF527 1
24#else
25# define ANOMALY_BF527 0
26#endif
27
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 28/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1) 29#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 30/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
@@ -23,68 +35,124 @@
23#define ANOMALY_05000245 (1) 35#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 36/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1) 37#define ANOMALY_05000265 (1)
26/* New Feature: EMAC TX DMA Word Alignment */ 38/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
27#define ANOMALY_05000285 (1) 39#define ANOMALY_05000310 (1)
28/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 40/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
29#define ANOMALY_05000312 (1) 41#define ANOMALY_05000312 (ANOMALY_BF527)
42/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
43#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
30/* Incorrect Access of OTP_STATUS During otp_write() Function */ 44/* Incorrect Access of OTP_STATUS During otp_write() Function */
31#define ANOMALY_05000328 (1) 45#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
32/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 46/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
33#define ANOMALY_05000337 (1) 47#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
34/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 48/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
35#define ANOMALY_05000341 (1) 49#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
36/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ 50/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
37#define ANOMALY_05000342 (1) 51#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
38/* USB Calibration Value Is Not Initialized */ 52/* USB Calibration Value Is Not Initialized */
39#define ANOMALY_05000346 (1) 53#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
54/* USB Calibration Value to use */
55#define ANOMALY_05000346_value 0xE510
40/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ 56/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
41#define ANOMALY_05000347 (1) 57#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
42/* Security Features Are Not Functional */ 58/* Security Features Are Not Functional */
43#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) 59#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
60/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
61#define ANOMALY_05000353 (ANOMALY_BF526)
44/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 62/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
45#define ANOMALY_05000355 (1) 63#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
46/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 64/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
47#define ANOMALY_05000357 (1) 65#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
48/* Incorrect Revision Number in DSPID Register */ 66/* Incorrect Revision Number in DSPID Register */
49#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) 67#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
50/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 68/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
51#define ANOMALY_05000366 (1) 69#define ANOMALY_05000366 (1)
52/* New Feature: Higher Default CCLK Rate */ 70/* Incorrect Default CSEL Value in PLL_DIV */
53#define ANOMALY_05000368 (1) 71#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
54/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 72/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
55#define ANOMALY_05000371 (1) 73#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
56/* Authentication Fails To Initiate */ 74/* Authentication Fails To Initiate */
57#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) 75#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
58/* Data Read From L3 Memory by USB DMA May be Corrupted */ 76/* Data Read From L3 Memory by USB DMA May be Corrupted */
59#define ANOMALY_05000380 (1) 77#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
60/* USB Full-speed Mode not Fully Tested */ 78/* 8-Bit NAND Flash Boot Mode Not Functional */
61#define ANOMALY_05000381 (1) 79#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
62/* New Feature: Boot from OTP Memory */ 80/* Host Must Not Read Back During Host DMA Boot */
63#define ANOMALY_05000385 (1) 81#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
64/* New Feature: bfrom_SysControl() Routine */ 82/* Boot from OTP Memory Not Functional */
65#define ANOMALY_05000386 (1) 83#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
66/* New Feature: Programmable Preboot Settings */ 84/* bfrom_SysControl() Firmware Routine Not Functional */
67#define ANOMALY_05000387 (1) 85#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
86/* Programmable Preboot Settings Not Functional */
87#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
88/* CRC32 Checksum Support Not Functional */
89#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
68/* Reset Vector Must Not Be in SDRAM Memory Space */ 90/* Reset Vector Must Not Be in SDRAM Memory Space */
69#define ANOMALY_05000389 (1) 91#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
70/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ 92/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
71#define ANOMALY_05000392 (1) 93#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
72/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ 94/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
73#define ANOMALY_05000393 (1) 95#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
74/* New Feature: Log Buffer Functionality */ 96/* Log Buffer Not Functional */
75#define ANOMALY_05000394 (1) 97#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
76/* New Feature: Hook Routine Functionality */ 98/* Hook Routine Not Functional */
77#define ANOMALY_05000395 (1) 99#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
78/* New Feature: Header Indirect Bit */ 100/* Header Indirect Bit Not Functional */
79#define ANOMALY_05000396 (1) 101#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
80/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ 102/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
81#define ANOMALY_05000397 (1) 103#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
82/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ 104/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
83#define ANOMALY_05000398 (1) 105#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
84/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ 106/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
85#define ANOMALY_05000399 (1) 107#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
86/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ 108/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
87#define ANOMALY_05000401 (1) 109#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
110/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
111#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
112/* Lockbox SESR Disallows Certain User Interrupts */
113#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
114/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
115#define ANOMALY_05000405 (1)
116/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
117#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
118/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
119#define ANOMALY_05000408 (1)
120/* Lockbox firmware leaves MDMA0 channel enabled */
121#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
122/* Incorrect Default Internal Voltage Regulator Setting */
123#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
124/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
125#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
126/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
127#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
128/* DEB2_URGENT Bit Not Functional */
129#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
130/* Speculative Fetches Can Cause Undesired External FIFO Operations */
131#define ANOMALY_05000416 (1)
132/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
133#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
134/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
135#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
136/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
137#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
138/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
139#define ANOMALY_05000421 (1)
140/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
141#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
142/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
143#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
144/* Internal Voltage Regulator Not Trimmed */
145#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
146/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
147#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
148/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
149#define ANOMALY_05000426 (1)
150/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
151#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
152/* Software System Reset Corrupts PLL_LOCKCNT Register */
153#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
154/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
155#define ANOMALY_05000432 (ANOMALY_BF526)
88 156
89/* Anomalies that don't exist on this proc */ 157/* Anomalies that don't exist on this proc */
90#define ANOMALY_05000125 (0) 158#define ANOMALY_05000125 (0)
@@ -97,6 +165,8 @@
97#define ANOMALY_05000263 (0) 165#define ANOMALY_05000263 (0)
98#define ANOMALY_05000266 (0) 166#define ANOMALY_05000266 (0)
99#define ANOMALY_05000273 (0) 167#define ANOMALY_05000273 (0)
168#define ANOMALY_05000285 (0)
169#define ANOMALY_05000307 (0)
100#define ANOMALY_05000311 (0) 170#define ANOMALY_05000311 (0)
101#define ANOMALY_05000323 (0) 171#define ANOMALY_05000323 (0)
102#define ANOMALY_05000363 (0) 172#define ANOMALY_05000363 (0)
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
index 056eb4b9cd25..144f08d3f8ea 100644
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ b/arch/blackfin/mach-bf527/include/mach/bf527.h
@@ -30,8 +30,6 @@
30#ifndef __MACH_BF527_H__ 30#ifndef __MACH_BF527_H__
31#define __MACH_BF527_H__ 31#define __MACH_BF527_H__
32 32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF) 33#define OFFSET_(x) ((x) & 0x0000FFFF)
36 34
37/*some misc defines*/ 35/*some misc defines*/
@@ -112,16 +110,31 @@
112 110
113#ifdef CONFIG_BF527 111#ifdef CONFIG_BF527
114#define CPU "BF527" 112#define CPU "BF527"
113#define CPUID 0x27e4
114#endif
115#ifdef CONFIG_BF526
116#define CPU "BF526"
117#define CPUID 0x27e4
115#endif 118#endif
116#ifdef CONFIG_BF525 119#ifdef CONFIG_BF525
117#define CPU "BF525" 120#define CPU "BF525"
121#define CPUID 0x27e4
122#endif
123#ifdef CONFIG_BF524
124#define CPU "BF524"
125#define CPUID 0x27e4
126#endif
127#ifdef CONFIG_BF523
128#define CPU "BF523"
129#define CPUID 0x27e4
118#endif 130#endif
119#ifdef CONFIG_BF522 131#ifdef CONFIG_BF522
120#define CPU "BF522" 132#define CPU "BF522"
133#define CPUID 0x27e4
121#endif 134#endif
135
122#ifndef CPU 136#ifndef CPU
123#define CPU "UNKNOWN" 137#error Unknown CPU type - This kernel doesn't seem to be configured properly
124#define CPUID 0x0
125#endif 138#endif
126 139
127#endif /* __MACH_BF527_H__ */ 140#endif /* __MACH_BF527_H__ */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 6ac2ed7026eb..68b55d03fedf 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -1840,6 +1840,33 @@
1840 1840
1841#define DPRESCALE 0xf /* Load Counter Register */ 1841#define DPRESCALE 0xf /* Load Counter Register */
1842 1842
1843/* CNT_COMMAND bit field options */
1844
1845#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
1846#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
1847#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
1848
1849#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
1850#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
1851#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
1852
1853#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
1854#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
1855#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
1856
1857/* CNT_CONFIG bit field options */
1858
1859#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
1860#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
1861#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
1862#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
1863#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
1864
1865#define BNDMODE_COMP 0x0000 /* boundary compare mode */
1866#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
1867#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1868#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1869
1843/* Bit masks for OTP_CONTROL */ 1870/* Bit masks for OTP_CONTROL */
1844 1871
1845#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ 1872#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
index ae4d205bfcf5..7f6da2c386bb 100644
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf527/include/mach/portmux.h
@@ -67,6 +67,10 @@
67#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) 67#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
68#endif 68#endif
69 69
70#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
71#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
72#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
73
70#define P_HWAIT (P_DONTCARE) 74#define P_HWAIT (P_DONTCARE)
71 75
72#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) 76#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 18:39:16 -0500