diff options
Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach/pll.h')
-rw-r--r-- | arch/blackfin/mach-bf527/include/mach/pll.h | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h new file mode 100644 index 000000000000..24f1d7c02325 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/pll.h | |||
@@ -0,0 +1,63 @@ | |||
1 | /* | ||
2 | * Copyright 2007-2008 Analog Devices Inc. | ||
3 | * | ||
4 | * Licensed under the GPL-2 or later | ||
5 | */ | ||
6 | |||
7 | #ifndef _MACH_PLL_H | ||
8 | #define _MACH_PLL_H | ||
9 | |||
10 | #include <asm/blackfin.h> | ||
11 | #include <asm/irqflags.h> | ||
12 | |||
13 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
14 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
15 | { | ||
16 | unsigned long flags, iwr0, iwr1; | ||
17 | |||
18 | if (val == bfin_read_PLL_CTL()) | ||
19 | return; | ||
20 | |||
21 | flags = hard_local_irq_save(); | ||
22 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
23 | iwr0 = bfin_read32(SIC_IWR0); | ||
24 | iwr1 = bfin_read32(SIC_IWR1); | ||
25 | /* Only allow PPL Wakeup) */ | ||
26 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
27 | bfin_write32(SIC_IWR1, 0); | ||
28 | |||
29 | bfin_write16(PLL_CTL, val); | ||
30 | SSYNC(); | ||
31 | asm("IDLE;"); | ||
32 | |||
33 | bfin_write32(SIC_IWR0, iwr0); | ||
34 | bfin_write32(SIC_IWR1, iwr1); | ||
35 | hard_local_irq_restore(flags); | ||
36 | } | ||
37 | |||
38 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
39 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
40 | { | ||
41 | unsigned long flags, iwr0, iwr1; | ||
42 | |||
43 | if (val == bfin_read_VR_CTL()) | ||
44 | return; | ||
45 | |||
46 | flags = hard_local_irq_save(); | ||
47 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
48 | iwr0 = bfin_read32(SIC_IWR0); | ||
49 | iwr1 = bfin_read32(SIC_IWR1); | ||
50 | /* Only allow PPL Wakeup) */ | ||
51 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
52 | bfin_write32(SIC_IWR1, 0); | ||
53 | |||
54 | bfin_write16(VR_CTL, val); | ||
55 | SSYNC(); | ||
56 | asm("IDLE;"); | ||
57 | |||
58 | bfin_write32(SIC_IWR0, iwr0); | ||
59 | bfin_write32(SIC_IWR1, iwr1); | ||
60 | hard_local_irq_restore(flags); | ||
61 | } | ||
62 | |||
63 | #endif /* _MACH_PLL_H */ | ||