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Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach/irq.h')
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 4e2b3f2020e5..8ea660d8151f 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -96,14 +96,14 @@
96#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 96#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
97#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 97#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
98#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 98#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
99#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ 99#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
100#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ 100#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
101#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ 101#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
102#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ 102#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
103#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ 103#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
104#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ 104#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
105#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ 105#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
106#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ 106#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
107#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ 107#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
108#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ 108#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
109#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ 109#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
@@ -227,14 +227,14 @@
227#define IRQ_PORTH_INTB_POS 28 227#define IRQ_PORTH_INTB_POS 28
228 228
229/* IAR4 BIT FIELDS */ 229/* IAR4 BIT FIELDS */
230#define IRQ_TMR0_POS 0 230#define IRQ_TIMER0_POS 0
231#define IRQ_TMR1_POS 4 231#define IRQ_TIMER1_POS 4
232#define IRQ_TMR2_POS 8 232#define IRQ_TIMER2_POS 8
233#define IRQ_TMR3_POS 12 233#define IRQ_TIMER3_POS 12
234#define IRQ_TMR4_POS 16 234#define IRQ_TIMER4_POS 16
235#define IRQ_TMR5_POS 20 235#define IRQ_TIMER5_POS 20
236#define IRQ_TMR6_POS 24 236#define IRQ_TIMER6_POS 24
237#define IRQ_TMR7_POS 28 237#define IRQ_TIMER7_POS 28
238 238
239/* IAR5 BIT FIELDS */ 239/* IAR5 BIT FIELDS */
240#define IRQ_PORTG_INTA_POS 0 240#define IRQ_PORTG_INTA_POS 0