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1/*
2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
19#define ANOMALY_05000119 (1)
20/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
21#define ANOMALY_05000122 (1)
22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
23#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1)
26/* New Feature: EMAC TX DMA Word Alignment */
27#define ANOMALY_05000285 (1)
28/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
29#define ANOMALY_05000312 (1)
30/* Incorrect Access of OTP_STATUS During otp_write() Function */
31#define ANOMALY_05000328 (1)
32/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
33#define ANOMALY_05000337 (1)
34/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
35#define ANOMALY_05000341 (1)
36/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
37#define ANOMALY_05000342 (1)
38/* USB Calibration Value Is Not Initialized */
39#define ANOMALY_05000346 (1)
40/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
41#define ANOMALY_05000347 (1)
42/* Security Features Are Not Functional */
43#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
44/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
45#define ANOMALY_05000355 (1)
46/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
47#define ANOMALY_05000357 (1)
48/* Incorrect Revision Number in DSPID Register */
49#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
50/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
51#define ANOMALY_05000366 (1)
52/* New Feature: Higher Default CCLK Rate */
53#define ANOMALY_05000368 (1)
54/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
55#define ANOMALY_05000371 (1)
56/* Authentication Fails To Initiate */
57#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
58/* Data Read From L3 Memory by USB DMA May be Corrupted */
59#define ANOMALY_05000380 (1)
60/* USB Full-speed Mode not Fully Tested */
61#define ANOMALY_05000381 (1)
62/* New Feature: Boot from OTP Memory */
63#define ANOMALY_05000385 (1)
64/* New Feature: bfrom_SysControl() Routine */
65#define ANOMALY_05000386 (1)
66/* New Feature: Programmable Preboot Settings */
67#define ANOMALY_05000387 (1)
68/* Reset Vector Must Not Be in SDRAM Memory Space */
69#define ANOMALY_05000389 (1)
70/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
71#define ANOMALY_05000392 (1)
72/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
73#define ANOMALY_05000393 (1)
74/* New Feature: Log Buffer Functionality */
75#define ANOMALY_05000394 (1)
76/* New Feature: Hook Routine Functionality */
77#define ANOMALY_05000395 (1)
78/* New Feature: Header Indirect Bit */
79#define ANOMALY_05000396 (1)
80/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
81#define ANOMALY_05000397 (1)
82/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
83#define ANOMALY_05000398 (1)
84/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
85#define ANOMALY_05000399 (1)
86/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
87#define ANOMALY_05000401 (1)
88
89/* Anomalies that don't exist on this proc */
90#define ANOMALY_05000125 (0)
91#define ANOMALY_05000158 (0)
92#define ANOMALY_05000183 (0)
93#define ANOMALY_05000198 (0)
94#define ANOMALY_05000230 (0)
95#define ANOMALY_05000244 (0)
96#define ANOMALY_05000261 (0)
97#define ANOMALY_05000263 (0)
98#define ANOMALY_05000266 (0)
99#define ANOMALY_05000273 (0)
100#define ANOMALY_05000311 (0)
101#define ANOMALY_05000323 (0)
102#define ANOMALY_05000363 (0)
103
104#endif