diff options
Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach/anomaly.h')
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/anomaly.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index c438ca89d8c9..3f9052687fa8 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file should be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List | 10 | * - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List |
| 11 | * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List | 11 | * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| @@ -176,7 +176,7 @@ | |||
| 176 | #define ANOMALY_05000443 (1) | 176 | #define ANOMALY_05000443 (1) |
| 177 | /* The WURESET Bit in the SYSCR Register is not Functional */ | 177 | /* The WURESET Bit in the SYSCR Register is not Functional */ |
| 178 | #define ANOMALY_05000445 (1) | 178 | #define ANOMALY_05000445 (1) |
| 179 | /* USB DMA Short Packet Data Corruption */ | 179 | /* USB DMA Mode 1 Short Packet Data Corruption */ |
| 180 | #define ANOMALY_05000450 (1) | 180 | #define ANOMALY_05000450 (1) |
| 181 | /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ | 181 | /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ |
| 182 | #define ANOMALY_05000451 (1) | 182 | #define ANOMALY_05000451 (1) |
| @@ -186,12 +186,20 @@ | |||
| 186 | #define ANOMALY_05000456 (1) | 186 | #define ANOMALY_05000456 (1) |
| 187 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ | 187 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ |
| 188 | #define ANOMALY_05000457 (1) | 188 | #define ANOMALY_05000457 (1) |
| 189 | /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ | ||
| 190 | #define ANOMALY_05000460 (1) | ||
| 189 | /* False Hardware Error when RETI Points to Invalid Memory */ | 191 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 190 | #define ANOMALY_05000461 (1) | 192 | #define ANOMALY_05000461 (1) |
| 193 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ | ||
| 194 | #define ANOMALY_05000462 (1) | ||
| 191 | /* USB Rx DMA hang */ | 195 | /* USB Rx DMA hang */ |
| 192 | #define ANOMALY_05000465 (1) | 196 | #define ANOMALY_05000465 (1) |
| 197 | /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ | ||
| 198 | #define ANOMALY_05000466 (1) | ||
| 193 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ | 199 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ |
| 194 | #define ANOMALY_05000467 (1) | 200 | #define ANOMALY_05000467 (1) |
| 201 | /* PLL Latches Incorrect Settings During Reset */ | ||
| 202 | #define ANOMALY_05000469 (1) | ||
| 195 | 203 | ||
| 196 | /* Anomalies that don't exist on this proc */ | 204 | /* Anomalies that don't exist on this proc */ |
| 197 | #define ANOMALY_05000099 (0) | 205 | #define ANOMALY_05000099 (0) |
| @@ -238,6 +246,7 @@ | |||
| 238 | #define ANOMALY_05000362 (1) | 246 | #define ANOMALY_05000362 (1) |
| 239 | #define ANOMALY_05000363 (0) | 247 | #define ANOMALY_05000363 (0) |
| 240 | #define ANOMALY_05000400 (0) | 248 | #define ANOMALY_05000400 (0) |
| 249 | #define ANOMALY_05000402 (0) | ||
| 241 | #define ANOMALY_05000412 (0) | 250 | #define ANOMALY_05000412 (0) |
| 242 | #define ANOMALY_05000447 (0) | 251 | #define ANOMALY_05000447 (0) |
| 243 | #define ANOMALY_05000448 (0) | 252 | #define ANOMALY_05000448 (0) |