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1/*
2 * File: arch/blackfin/mach-bf527/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF537
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <linux/init.h>
32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
35#if CONFIG_BFIN_KERNEL_CLOCK
36#include <asm/mach-common/clocks.h>
37#include <asm/mach/mem_init.h>
38#endif
39
40.global __rambase
41.global __ramstart
42.global __ramend
43.extern ___bss_stop
44.extern ___bss_start
45.extern _bf53x_relocate_l1_mem
46
47#define INITIAL_STACK 0xFFB01000
48
49__INIT
50
51ENTRY(__start)
52 /* R0: argument of command line string, passed from uboot, save it */
53 R7 = R0;
54 /* Enable Cycle Counter and Nesting Of Interrupts */
55#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
56 R0 = SYSCFG_SNEN;
57#else
58 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
59#endif
60 SYSCFG = R0;
61 R0 = 0;
62
63 /* Clear Out All the data and pointer Registers */
64 R1 = R0;
65 R2 = R0;
66 R3 = R0;
67 R4 = R0;
68 R5 = R0;
69 R6 = R0;
70
71 P0 = R0;
72 P1 = R0;
73 P2 = R0;
74 P3 = R0;
75 P4 = R0;
76 P5 = R0;
77
78 LC0 = r0;
79 LC1 = r0;
80 L0 = r0;
81 L1 = r0;
82 L2 = r0;
83 L3 = r0;
84
85 /* Clear Out All the DAG Registers */
86 B0 = r0;
87 B1 = r0;
88 B2 = r0;
89 B3 = r0;
90
91 I0 = r0;
92 I1 = r0;
93 I2 = r0;
94 I3 = r0;
95
96 M0 = r0;
97 M1 = r0;
98 M2 = r0;
99 M3 = r0;
100
101 trace_buffer_init(p0,r0);
102 P0 = R1;
103 R0 = R1;
104
105 /* Turn off the icache */
106 p0.l = LO(IMEM_CONTROL);
107 p0.h = HI(IMEM_CONTROL);
108 R1 = [p0];
109 R0 = ~ENICPLB;
110 R0 = R0 & R1;
111
112 /* Anomaly 05000125 */
113#if ANOMALY_05000125
114 CLI R2;
115 SSYNC;
116#endif
117 [p0] = R0;
118 SSYNC;
119#if ANOMALY_05000125
120 STI R2;
121#endif
122
123 /* Turn off the dcache */
124 p0.l = LO(DMEM_CONTROL);
125 p0.h = HI(DMEM_CONTROL);
126 R1 = [p0];
127 R0 = ~ENDCPLB;
128 R0 = R0 & R1;
129
130 /* Anomaly 05000125 */
131#if ANOMALY_05000125
132 CLI R2;
133 SSYNC;
134#endif
135 [p0] = R0;
136 SSYNC;
137#if ANOMALY_05000125
138 STI R2;
139#endif
140
141
142#if defined(CONFIG_BF527)
143 p0.h = hi(EMAC_SYSTAT);
144 p0.l = lo(EMAC_SYSTAT);
145 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
146 R0.l = 0xFFFF;
147 [P0] = R0;
148 SSYNC;
149#endif
150
151 /* Initialise UART - when booting from u-boot, the UART is not disabled
152 * so if we dont initalize here, our serial console gets hosed */
153 p0.h = hi(UART1_LCR);
154 p0.l = lo(UART1_LCR);
155 r0 = 0x0(Z);
156 w[p0] = r0.L; /* To enable DLL writes */
157 ssync;
158
159 p0.h = hi(UART1_DLL);
160 p0.l = lo(UART1_DLL);
161 r0 = 0x0(Z);
162 w[p0] = r0.L;
163 ssync;
164
165 p0.h = hi(UART1_DLH);
166 p0.l = lo(UART1_DLH);
167 r0 = 0x00(Z);
168 w[p0] = r0.L;
169 ssync;
170
171 p0.h = hi(UART1_GCTL);
172 p0.l = lo(UART1_GCTL);
173 r0 = 0x0(Z);
174 w[p0] = r0.L; /* To enable UART clock */
175 ssync;
176
177 /* Initialize stack pointer */
178 sp.l = lo(INITIAL_STACK);
179 sp.h = hi(INITIAL_STACK);
180 fp = sp;
181 usp = sp;
182
183#ifdef CONFIG_EARLY_PRINTK
184 SP += -12;
185 call _init_early_exception_vectors;
186 SP += 12;
187#endif
188
189 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
190 call _bf53x_relocate_l1_mem;
191#if CONFIG_BFIN_KERNEL_CLOCK
192 call _start_dma_code;
193#endif
194
195 /* Code for initializing Async memory banks */
196
197 p2.h = hi(EBIU_AMBCTL1);
198 p2.l = lo(EBIU_AMBCTL1);
199 r0.h = hi(AMBCTL1VAL);
200 r0.l = lo(AMBCTL1VAL);
201 [p2] = r0;
202 ssync;
203
204 p2.h = hi(EBIU_AMBCTL0);
205 p2.l = lo(EBIU_AMBCTL0);
206 r0.h = hi(AMBCTL0VAL);
207 r0.l = lo(AMBCTL0VAL);
208 [p2] = r0;
209 ssync;
210
211 p2.h = hi(EBIU_AMGCTL);
212 p2.l = lo(EBIU_AMGCTL);
213 r0 = AMGCTLVAL;
214 w[p2] = r0;
215 ssync;
216
217 /* This section keeps the processor in supervisor mode
218 * during kernel boot. Switches to user mode at end of boot.
219 * See page 3-9 of Hardware Reference manual for documentation.
220 */
221
222 /* EVT15 = _real_start */
223
224 p0.l = lo(EVT15);
225 p0.h = hi(EVT15);
226 p1.l = _real_start;
227 p1.h = _real_start;
228 [p0] = p1;
229 csync;
230
231 p0.l = lo(IMASK);
232 p0.h = hi(IMASK);
233 p1.l = IMASK_IVG15;
234 p1.h = 0x0;
235 [p0] = p1;
236 csync;
237
238 raise 15;
239 p0.l = .LWAIT_HERE;
240 p0.h = .LWAIT_HERE;
241 reti = p0;
242#if ANOMALY_05000281
243 nop; nop; nop;
244#endif
245 rti;
246
247.LWAIT_HERE:
248 jump .LWAIT_HERE;
249ENDPROC(__start)
250
251ENTRY(_real_start)
252 [ -- sp ] = reti;
253 p0.l = lo(WDOG_CTL);
254 p0.h = hi(WDOG_CTL);
255 r0 = 0xAD6(z);
256 w[p0] = r0; /* watchdog off for now */
257 ssync;
258
259 /* Code update for BSS size == 0
260 * Zero out the bss region.
261 */
262
263 p1.l = ___bss_start;
264 p1.h = ___bss_start;
265 p2.l = ___bss_stop;
266 p2.h = ___bss_stop;
267 r0 = 0;
268 p2 -= p1;
269 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
270.L_clear_bss:
271 B[p1++] = r0;
272
273 /* In case there is a NULL pointer reference
274 * Zero out region before stext
275 */
276
277 p1.l = 0x0;
278 p1.h = 0x0;
279 r0.l = __stext;
280 r0.h = __stext;
281 r0 = r0 >> 1;
282 p2 = r0;
283 r0 = 0;
284 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
285.L_clear_zero:
286 W[p1++] = r0;
287
288 /* pass the uboot arguments to the global value command line */
289 R0 = R7;
290 call _cmdline_init;
291
292 p1.l = __rambase;
293 p1.h = __rambase;
294 r0.l = __sdata;
295 r0.h = __sdata;
296 [p1] = r0;
297
298 p1.l = __ramstart;
299 p1.h = __ramstart;
300 p3.l = ___bss_stop;
301 p3.h = ___bss_stop;
302
303 r1 = p3;
304 [p1] = r1;
305
306 /*
307 * load the current thread pointer and stack
308 */
309 r1.l = _init_thread_union;
310 r1.h = _init_thread_union;
311
312 r2.l = 0x2000;
313 r2.h = 0x0000;
314 r1 = r1 + r2;
315 sp = r1;
316 usp = sp;
317 fp = sp;
318 jump.l _start_kernel;
319ENDPROC(_real_start)
320
321__FINIT
322
323.section .l1.text
324#if CONFIG_BFIN_KERNEL_CLOCK
325ENTRY(_start_dma_code)
326
327 /* Enable PHY CLK buffer output */
328 p0.h = hi(VR_CTL);
329 p0.l = lo(VR_CTL);
330 r0.l = w[p0];
331 bitset(r0, 14);
332 w[p0] = r0.l;
333 ssync;
334
335 p0.h = hi(SIC_IWR0);
336 p0.l = lo(SIC_IWR0);
337 r0.l = 0x1;
338 r0.h = 0x0;
339 [p0] = r0;
340 SSYNC;
341
342 /*
343 * Set PLL_CTL
344 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
345 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
346 * - [7] = output delay (add 200ps of delay to mem signals)
347 * - [6] = input delay (add 200ps of input delay to mem signals)
348 * - [5] = PDWN : 1=All Clocks off
349 * - [3] = STOPCK : 1=Core Clock off
350 * - [1] = PLL_OFF : 1=Disable Power to PLL
351 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
352 * all other bits set to zero
353 */
354
355 p0.h = hi(PLL_LOCKCNT);
356 p0.l = lo(PLL_LOCKCNT);
357 r0 = 0x300(Z);
358 w[p0] = r0.l;
359 ssync;
360
361 P2.H = hi(EBIU_SDGCTL);
362 P2.L = lo(EBIU_SDGCTL);
363 R0 = [P2];
364 BITSET (R0, 24);
365 [P2] = R0;
366 SSYNC;
367
368 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
369 r0 = r0 << 9; /* Shift it over, */
370 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
371 r0 = r1 | r0;
372 r1 = PLL_BYPASS; /* Bypass the PLL? */
373 r1 = r1 << 8; /* Shift it over */
374 r0 = r1 | r0; /* add them all together */
375
376 p0.h = hi(PLL_CTL);
377 p0.l = lo(PLL_CTL); /* Load the address */
378 cli r2; /* Disable interrupts */
379 ssync;
380 w[p0] = r0.l; /* Set the value */
381 idle; /* Wait for the PLL to stablize */
382 sti r2; /* Enable interrupts */
383
384.Lcheck_again:
385 p0.h = hi(PLL_STAT);
386 p0.l = lo(PLL_STAT);
387 R0 = W[P0](Z);
388 CC = BITTST(R0,5);
389 if ! CC jump .Lcheck_again;
390
391 /* Configure SCLK & CCLK Dividers */
392 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
393 p0.h = hi(PLL_DIV);
394 p0.l = lo(PLL_DIV);
395 w[p0] = r0.l;
396 ssync;
397
398 p0.l = lo(EBIU_SDRRC);
399 p0.h = hi(EBIU_SDRRC);
400 r0 = mem_SDRRC;
401 w[p0] = r0.l;
402 ssync;
403
404 p0.l = LO(EBIU_SDBCTL);
405 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
406 r0 = mem_SDBCTL;
407 w[p0] = r0.l;
408 ssync;
409
410 P2.H = hi(EBIU_SDGCTL);
411 P2.L = lo(EBIU_SDGCTL);
412 R0 = [P2];
413 BITCLR (R0, 24);
414 p0.h = hi(EBIU_SDSTAT);
415 p0.l = lo(EBIU_SDSTAT);
416 r2.l = w[p0];
417 cc = bittst(r2,3);
418 if !cc jump .Lskip;
419 NOP;
420 BITSET (R0, 23);
421.Lskip:
422 [P2] = R0;
423 SSYNC;
424
425 R0.L = lo(mem_SDGCTL);
426 R0.H = hi(mem_SDGCTL);
427 R1 = [p2];
428 R1 = R1 | R0;
429 [P2] = R1;
430 SSYNC;
431
432 p0.h = hi(SIC_IWR0);
433 p0.l = lo(SIC_IWR0);
434 r0.l = lo(IWR_ENABLE_ALL);
435 r0.h = hi(IWR_ENABLE_ALL);
436 [p0] = r0;
437 SSYNC;
438
439 RTS;
440ENDPROC(_start_dma_code)
441#endif /* CONFIG_BFIN_KERNEL_CLOCK */
442
443.data
444
445/*
446 * Set up the usable of RAM stuff. Size of RAM is determined then
447 * an initial stack set up at the end.
448 */
449
450.align 4
451__rambase:
452.long 0
453__ramstart:
454.long 0
455__ramend:
456.long 0
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