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-rw-r--r--arch/blackfin/mach-bf527/boards/Kconfig10
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile2
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c870
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c36
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c30
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c49
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c1008
7 files changed, 1987 insertions, 18 deletions
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
index b14c28810a44..1cc2667c10f1 100644
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ b/arch/blackfin/mach-bf527/boards/Kconfig
@@ -24,4 +24,14 @@ config BFIN526_EZBRD
24 help 24 help
25 BF526-EZBRD/EZKIT Lite board support. 25 BF526-EZBRD/EZKIT Lite board support.
26 26
27config BFIN527_AD7160EVAL
28 bool "BF527-AD7160-EVAL"
29 help
30 BF527-AD7160-EVAL board support.
31
32config BFIN527_TLL6527M
33 bool "The Learning Labs TLL6527M"
34 help
35 TLL6527M V1.0 platform support
36
27endchoice 37endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
index 51a5817c4a90..1d67da9f05ac 100644
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ b/arch/blackfin/mach-bf527/boards/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o 6obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o 7obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o 8obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
9obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
10obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
new file mode 100644
index 000000000000..fc767ac76381
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -0,0 +1,870 @@
1/*
2 * Copyright 2004-20010 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/i2c.h>
17#include <linux/irq.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <linux/leds.h>
21#include <linux/input.h>
22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h>
24#include <asm/reboot.h>
25#include <asm/nand.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
28
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
40static struct resource musb_resources[] = {
41 [0] = {
42 .start = 0xffc03800,
43 .end = 0xffc03cff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = { /* general IRQ */
47 .start = IRQ_USB_INT0,
48 .end = IRQ_USB_INT0,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 },
51 [2] = { /* DMA IRQ */
52 .start = IRQ_USB_DMA,
53 .end = IRQ_USB_DMA,
54 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
55 },
56};
57
58static struct musb_hdrc_config musb_config = {
59 .multipoint = 0,
60 .dyn_fifo = 0,
61 .soft_con = 1,
62 .dma = 1,
63 .num_eps = 8,
64 .dma_channels = 8,
65 .gpio_vrsel = GPIO_PG13,
66 /* Some custom boards need to be active low, just set it to "0"
67 * if it is the case.
68 */
69 .gpio_vrsel_active = 1,
70};
71
72static struct musb_hdrc_platform_data musb_plat = {
73#if defined(CONFIG_USB_MUSB_OTG)
74 .mode = MUSB_OTG,
75#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
76 .mode = MUSB_HOST,
77#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
78 .mode = MUSB_PERIPHERAL,
79#endif
80 .config = &musb_config,
81};
82
83static u64 musb_dmamask = ~(u32)0;
84
85static struct platform_device musb_device = {
86 .name = "musb_hdrc",
87 .id = 0,
88 .dev = {
89 .dma_mask = &musb_dmamask,
90 .coherent_dma_mask = 0xffffffff,
91 .platform_data = &musb_plat,
92 },
93 .num_resources = ARRAY_SIZE(musb_resources),
94 .resource = musb_resources,
95};
96#endif
97
98#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
99static struct resource bf52x_ra158z_resources[] = {
100 {
101 .start = IRQ_PPI_ERROR,
102 .end = IRQ_PPI_ERROR,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device bf52x_ra158z_device = {
108 .name = "bfin-ra158z",
109 .id = -1,
110 .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
111 .resource = bf52x_ra158z_resources,
112};
113#endif
114
115#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
116static struct mtd_partition ad7160eval_partitions[] = {
117 {
118 .name = "bootloader(nor)",
119 .size = 0x40000,
120 .offset = 0,
121 }, {
122 .name = "linux kernel(nor)",
123 .size = 0x1C0000,
124 .offset = MTDPART_OFS_APPEND,
125 }, {
126 .name = "file system(nor)",
127 .size = MTDPART_SIZ_FULL,
128 .offset = MTDPART_OFS_APPEND,
129 }
130};
131
132static struct physmap_flash_data ad7160eval_flash_data = {
133 .width = 2,
134 .parts = ad7160eval_partitions,
135 .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
136};
137
138static struct resource ad7160eval_flash_resource = {
139 .start = 0x20000000,
140 .end = 0x203fffff,
141 .flags = IORESOURCE_MEM,
142};
143
144static struct platform_device ad7160eval_flash_device = {
145 .name = "physmap-flash",
146 .id = 0,
147 .dev = {
148 .platform_data = &ad7160eval_flash_data,
149 },
150 .num_resources = 1,
151 .resource = &ad7160eval_flash_resource,
152};
153#endif
154
155#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
156static struct mtd_partition partition_info[] = {
157 {
158 .name = "linux kernel(nand)",
159 .offset = 0,
160 .size = 4 * 1024 * 1024,
161 },
162 {
163 .name = "file system(nand)",
164 .offset = MTDPART_OFS_APPEND,
165 .size = MTDPART_SIZ_FULL,
166 },
167};
168
169static struct bf5xx_nand_platform bf5xx_nand_platform = {
170 .data_width = NFC_NWIDTH_8,
171 .partitions = partition_info,
172 .nr_partitions = ARRAY_SIZE(partition_info),
173 .rd_dly = 3,
174 .wr_dly = 3,
175};
176
177static struct resource bf5xx_nand_resources[] = {
178 {
179 .start = NFC_CTL,
180 .end = NFC_DATA_RD + 2,
181 .flags = IORESOURCE_MEM,
182 },
183 {
184 .start = CH_NFC,
185 .end = CH_NFC,
186 .flags = IORESOURCE_IRQ,
187 },
188};
189
190static struct platform_device bf5xx_nand_device = {
191 .name = "bf5xx-nand",
192 .id = 0,
193 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
194 .resource = bf5xx_nand_resources,
195 .dev = {
196 .platform_data = &bf5xx_nand_platform,
197 },
198};
199#endif
200
201#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
202static struct platform_device rtc_device = {
203 .name = "rtc-bfin",
204 .id = -1,
205};
206#endif
207
208#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
209#include <linux/bfin_mac.h>
210static const unsigned short bfin_mac_peripherals[] = P_RMII0;
211
212static struct bfin_phydev_platform_data bfin_phydev_data[] = {
213 {
214 .addr = 1,
215 .irq = IRQ_MAC_PHYINT,
216 },
217};
218
219static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
220 .phydev_number = 1,
221 .phydev_data = bfin_phydev_data,
222 .phy_mode = PHY_INTERFACE_MODE_RMII,
223 .mac_peripherals = bfin_mac_peripherals,
224};
225
226static struct platform_device bfin_mii_bus = {
227 .name = "bfin_mii_bus",
228 .dev = {
229 .platform_data = &bfin_mii_bus_data,
230 }
231};
232
233static struct platform_device bfin_mac_device = {
234 .name = "bfin_mac",
235 .dev = {
236 .platform_data = &bfin_mii_bus,
237 }
238};
239#endif
240
241
242#if defined(CONFIG_MTD_M25P80) \
243 || defined(CONFIG_MTD_M25P80_MODULE)
244static struct mtd_partition bfin_spi_flash_partitions[] = {
245 {
246 .name = "bootloader(spi)",
247 .size = 0x00040000,
248 .offset = 0,
249 .mask_flags = MTD_CAP_ROM
250 }, {
251 .name = "linux kernel(spi)",
252 .size = MTDPART_SIZ_FULL,
253 .offset = MTDPART_OFS_APPEND,
254 }
255};
256
257static struct flash_platform_data bfin_spi_flash_data = {
258 .name = "m25p80",
259 .parts = bfin_spi_flash_partitions,
260 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
261 .type = "m25p16",
262};
263
264/* SPI flash chip (m25p64) */
265static struct bfin5xx_spi_chip spi_flash_chip_info = {
266 .enable_dma = 0, /* use dma transfer with this chip*/
267 .bits_per_word = 8,
268};
269#endif
270
271#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
272 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
273static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
274 .enable_dma = 0,
275 .bits_per_word = 16,
276};
277#endif
278
279#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
280static struct bfin5xx_spi_chip mmc_spi_chip_info = {
281 .enable_dma = 0,
282 .bits_per_word = 8,
283};
284#endif
285
286#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
287static struct bfin5xx_spi_chip spidev_chip_info = {
288 .enable_dma = 0,
289 .bits_per_word = 8,
290};
291#endif
292
293#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
294static struct platform_device bfin_i2s = {
295 .name = "bfin-i2s",
296 .id = CONFIG_SND_BF5XX_SPORT_NUM,
297 /* TODO: add platform data here */
298};
299#endif
300
301#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
302static struct platform_device bfin_tdm = {
303 .name = "bfin-tdm",
304 .id = CONFIG_SND_BF5XX_SPORT_NUM,
305 /* TODO: add platform data here */
306};
307#endif
308
309static struct spi_board_info bfin_spi_board_info[] __initdata = {
310#if defined(CONFIG_MTD_M25P80) \
311 || defined(CONFIG_MTD_M25P80_MODULE)
312 {
313 /* the modalias must be the same as spi device driver name */
314 .modalias = "m25p80", /* Name of spi_driver for this device */
315 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
316 .bus_num = 0, /* Framework bus number */
317 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
318 .platform_data = &bfin_spi_flash_data,
319 .controller_data = &spi_flash_chip_info,
320 .mode = SPI_MODE_3,
321 },
322#endif
323#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
324 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
325 {
326 .modalias = "ad183x",
327 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
328 .bus_num = 0,
329 .chip_select = 4,
330 .controller_data = &ad1836_spi_chip_info,
331 },
332#endif
333#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
334 {
335 .modalias = "mmc_spi",
336 .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
337 .bus_num = 0,
338 .chip_select = GPIO_PH3 + MAX_CTRL_CS,
339 .controller_data = &mmc_spi_chip_info,
340 .mode = SPI_MODE_3,
341 },
342#endif
343#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
344 {
345 .modalias = "spidev",
346 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
347 .bus_num = 0,
348 .chip_select = 1,
349 .controller_data = &spidev_chip_info,
350 },
351#endif
352};
353
354#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
355/* SPI controller data */
356static struct bfin5xx_spi_master bfin_spi0_info = {
357 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
358 .enable_dma = 1, /* master has the ability to do dma transfer */
359 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
360};
361
362/* SPI (0) */
363static struct resource bfin_spi0_resource[] = {
364 [0] = {
365 .start = SPI0_REGBASE,
366 .end = SPI0_REGBASE + 0xFF,
367 .flags = IORESOURCE_MEM,
368 },
369 [1] = {
370 .start = CH_SPI,
371 .end = CH_SPI,
372 .flags = IORESOURCE_DMA,
373 },
374 [2] = {
375 .start = IRQ_SPI,
376 .end = IRQ_SPI,
377 .flags = IORESOURCE_IRQ,
378 },
379};
380
381static struct platform_device bfin_spi0_device = {
382 .name = "bfin-spi",
383 .id = 0, /* Bus number */
384 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
385 .resource = bfin_spi0_resource,
386 .dev = {
387 .platform_data = &bfin_spi0_info, /* Passed to driver */
388 },
389};
390#endif /* spi master and devices */
391
392#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
393#ifdef CONFIG_SERIAL_BFIN_UART0
394static struct resource bfin_uart0_resources[] = {
395 {
396 .start = UART0_THR,
397 .end = UART0_GCTL+2,
398 .flags = IORESOURCE_MEM,
399 },
400 {
401 .start = IRQ_UART0_RX,
402 .end = IRQ_UART0_RX+1,
403 .flags = IORESOURCE_IRQ,
404 },
405 {
406 .start = IRQ_UART0_ERROR,
407 .end = IRQ_UART0_ERROR,
408 .flags = IORESOURCE_IRQ,
409 },
410 {
411 .start = CH_UART0_TX,
412 .end = CH_UART0_TX,
413 .flags = IORESOURCE_DMA,
414 },
415 {
416 .start = CH_UART0_RX,
417 .end = CH_UART0_RX,
418 .flags = IORESOURCE_DMA,
419 },
420};
421
422unsigned short bfin_uart0_peripherals[] = {
423 P_UART0_TX, P_UART0_RX, 0
424};
425
426static struct platform_device bfin_uart0_device = {
427 .name = "bfin-uart",
428 .id = 0,
429 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
430 .resource = bfin_uart0_resources,
431 .dev = {
432 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
433 },
434};
435#endif
436#ifdef CONFIG_SERIAL_BFIN_UART1
437static struct resource bfin_uart1_resources[] = {
438 {
439 .start = UART1_THR,
440 .end = UART1_GCTL+2,
441 .flags = IORESOURCE_MEM,
442 },
443 {
444 .start = IRQ_UART1_RX,
445 .end = IRQ_UART1_RX+1,
446 .flags = IORESOURCE_IRQ,
447 },
448 {
449 .start = IRQ_UART1_ERROR,
450 .end = IRQ_UART1_ERROR,
451 .flags = IORESOURCE_IRQ,
452 },
453 {
454 .start = CH_UART1_TX,
455 .end = CH_UART1_TX,
456 .flags = IORESOURCE_DMA,
457 },
458 {
459 .start = CH_UART1_RX,
460 .end = CH_UART1_RX,
461 .flags = IORESOURCE_DMA,
462 },
463#ifdef CONFIG_BFIN_UART1_CTSRTS
464 { /* CTS pin */
465 .start = GPIO_PF9,
466 .end = GPIO_PF9,
467 .flags = IORESOURCE_IO,
468 },
469 { /* RTS pin */
470 .start = GPIO_PF10,
471 .end = GPIO_PF10,
472 .flags = IORESOURCE_IO,
473 },
474#endif
475};
476
477unsigned short bfin_uart1_peripherals[] = {
478 P_UART1_TX, P_UART1_RX, 0
479};
480
481static struct platform_device bfin_uart1_device = {
482 .name = "bfin-uart",
483 .id = 1,
484 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
485 .resource = bfin_uart1_resources,
486 .dev = {
487 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
488 },
489};
490#endif
491#endif
492
493#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
494#ifdef CONFIG_BFIN_SIR0
495static struct resource bfin_sir0_resources[] = {
496 {
497 .start = 0xFFC00400,
498 .end = 0xFFC004FF,
499 .flags = IORESOURCE_MEM,
500 },
501 {
502 .start = IRQ_UART0_RX,
503 .end = IRQ_UART0_RX+1,
504 .flags = IORESOURCE_IRQ,
505 },
506 {
507 .start = CH_UART0_RX,
508 .end = CH_UART0_RX+1,
509 .flags = IORESOURCE_DMA,
510 },
511};
512
513static struct platform_device bfin_sir0_device = {
514 .name = "bfin_sir",
515 .id = 0,
516 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
517 .resource = bfin_sir0_resources,
518};
519#endif
520#ifdef CONFIG_BFIN_SIR1
521static struct resource bfin_sir1_resources[] = {
522 {
523 .start = 0xFFC02000,
524 .end = 0xFFC020FF,
525 .flags = IORESOURCE_MEM,
526 },
527 {
528 .start = IRQ_UART1_RX,
529 .end = IRQ_UART1_RX+1,
530 .flags = IORESOURCE_IRQ,
531 },
532 {
533 .start = CH_UART1_RX,
534 .end = CH_UART1_RX+1,
535 .flags = IORESOURCE_DMA,
536 },
537};
538
539static struct platform_device bfin_sir1_device = {
540 .name = "bfin_sir",
541 .id = 1,
542 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
543 .resource = bfin_sir1_resources,
544};
545#endif
546#endif
547
548#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
549#include <linux/input/ad7160.h>
550static const struct ad7160_platform_data bfin_ad7160_ts_info = {
551 .sensor_x_res = 854,
552 .sensor_y_res = 480,
553 .pressure = 100,
554 .filter_coef = 3,
555 .coord_pref = AD7160_ORIG_TOP_LEFT,
556 .first_touch_window = 5,
557 .move_window = 3,
558 .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
559 AD7160_EMIT_ABS_MT_PRESSURE |
560 AD7160_TRACKING_ID_ASCENDING,
561 .finger_act_ctrl = 0x64,
562 .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
563 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
564 AD7160_HAPTIC_SLOT_B(60) |
565 AD7160_HAPTIC_SLOT_B_LVL_LOW,
566
567 .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
568 AD7160_HAPTIC_SLOT_A_LVL_HIGH |
569 AD7160_HAPTIC_SLOT_B(80) |
570 AD7160_HAPTIC_SLOT_B_LVL_LOW |
571 AD7160_HAPTIC_SLOT_C(120) |
572 AD7160_HAPTIC_SLOT_C_LVL_HIGH |
573 AD7160_HAPTIC_SLOT_D(30) |
574 AD7160_HAPTIC_SLOT_D_LVL_LOW,
575};
576#endif
577
578#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
579static struct resource bfin_twi0_resource[] = {
580 [0] = {
581 .start = TWI0_REGBASE,
582 .end = TWI0_REGBASE,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 .start = IRQ_TWI,
587 .end = IRQ_TWI,
588 .flags = IORESOURCE_IRQ,
589 },
590};
591
592static struct platform_device i2c_bfin_twi_device = {
593 .name = "i2c-bfin-twi",
594 .id = 0,
595 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
596 .resource = bfin_twi0_resource,
597};
598#endif
599
600static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
601#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
602 {
603 I2C_BOARD_INFO("ad7160", 0x33),
604 .irq = IRQ_PH1,
605 .platform_data = (void *)&bfin_ad7160_ts_info,
606 },
607#endif
608};
609
610#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
611#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
612static struct resource bfin_sport0_uart_resources[] = {
613 {
614 .start = SPORT0_TCR1,
615 .end = SPORT0_MRCS3+4,
616 .flags = IORESOURCE_MEM,
617 },
618 {
619 .start = IRQ_SPORT0_RX,
620 .end = IRQ_SPORT0_RX+1,
621 .flags = IORESOURCE_IRQ,
622 },
623 {
624 .start = IRQ_SPORT0_ERROR,
625 .end = IRQ_SPORT0_ERROR,
626 .flags = IORESOURCE_IRQ,
627 },
628};
629
630unsigned short bfin_sport0_peripherals[] = {
631 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
632 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
633};
634
635static struct platform_device bfin_sport0_uart_device = {
636 .name = "bfin-sport-uart",
637 .id = 0,
638 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
639 .resource = bfin_sport0_uart_resources,
640 .dev = {
641 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
642 },
643};
644#endif
645#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
646static struct resource bfin_sport1_uart_resources[] = {
647 {
648 .start = SPORT1_TCR1,
649 .end = SPORT1_MRCS3+4,
650 .flags = IORESOURCE_MEM,
651 },
652 {
653 .start = IRQ_SPORT1_RX,
654 .end = IRQ_SPORT1_RX+1,
655 .flags = IORESOURCE_IRQ,
656 },
657 {
658 .start = IRQ_SPORT1_ERROR,
659 .end = IRQ_SPORT1_ERROR,
660 .flags = IORESOURCE_IRQ,
661 },
662};
663
664unsigned short bfin_sport1_peripherals[] = {
665 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
666 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
667};
668
669static struct platform_device bfin_sport1_uart_device = {
670 .name = "bfin-sport-uart",
671 .id = 1,
672 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
673 .resource = bfin_sport1_uart_resources,
674 .dev = {
675 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
676 },
677};
678#endif
679#endif
680
681#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
682#include <asm/bfin_rotary.h>
683
684static struct bfin_rotary_platform_data bfin_rotary_data = {
685 /*.rotary_up_key = KEY_UP,*/
686 /*.rotary_down_key = KEY_DOWN,*/
687 .rotary_rel_code = REL_WHEEL,
688 .rotary_button_key = KEY_ENTER,
689 .debounce = 10, /* 0..17 */
690 .mode = ROT_QUAD_ENC | ROT_DEBE,
691};
692
693static struct resource bfin_rotary_resources[] = {
694 {
695 .start = IRQ_CNT,
696 .end = IRQ_CNT,
697 .flags = IORESOURCE_IRQ,
698 },
699};
700
701static struct platform_device bfin_rotary_device = {
702 .name = "bfin-rotary",
703 .id = -1,
704 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
705 .resource = bfin_rotary_resources,
706 .dev = {
707 .platform_data = &bfin_rotary_data,
708 },
709};
710#endif
711
712static const unsigned int cclk_vlev_datasheet[] = {
713 VRPAIR(VLEV_100, 400000000),
714 VRPAIR(VLEV_105, 426000000),
715 VRPAIR(VLEV_110, 500000000),
716 VRPAIR(VLEV_115, 533000000),
717 VRPAIR(VLEV_120, 600000000),
718};
719
720static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
721 .tuple_tab = cclk_vlev_datasheet,
722 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
723 .vr_settling_time = 25 /* us */,
724};
725
726static struct platform_device bfin_dpmc = {
727 .name = "bfin dpmc",
728 .dev = {
729 .platform_data = &bfin_dmpc_vreg_data,
730 },
731};
732
733static struct platform_device *stamp_devices[] __initdata = {
734
735 &bfin_dpmc,
736
737#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
738 &bf5xx_nand_device,
739#endif
740
741#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
742 &rtc_device,
743#endif
744
745#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
746 &musb_device,
747#endif
748
749#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
750 &bfin_mii_bus,
751 &bfin_mac_device,
752#endif
753
754#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
755 &bfin_spi0_device,
756#endif
757
758#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
759#ifdef CONFIG_SERIAL_BFIN_UART0
760 &bfin_uart0_device,
761#endif
762#ifdef CONFIG_SERIAL_BFIN_UART1
763 &bfin_uart1_device,
764#endif
765#endif
766
767#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
768 &bf52x_ra158z_device,
769#endif
770
771#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
772#ifdef CONFIG_BFIN_SIR0
773 &bfin_sir0_device,
774#endif
775#ifdef CONFIG_BFIN_SIR1
776 &bfin_sir1_device,
777#endif
778#endif
779
780#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
781 &i2c_bfin_twi_device,
782#endif
783
784#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
785#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
786 &bfin_sport0_uart_device,
787#endif
788#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
789 &bfin_sport1_uart_device,
790#endif
791#endif
792
793#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
794 &bfin_rotary_device,
795#endif
796
797#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
798 &ad7160eval_flash_device,
799#endif
800
801#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
802 &bfin_i2s,
803#endif
804
805#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
806 &bfin_tdm,
807#endif
808};
809
810static int __init ad7160eval_init(void)
811{
812 printk(KERN_INFO "%s(): registering device resources\n", __func__);
813 i2c_register_board_info(0, bfin_i2c_board_info,
814 ARRAY_SIZE(bfin_i2c_board_info));
815 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
816 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
817 return 0;
818}
819
820arch_initcall(ad7160eval_init);
821
822static struct platform_device *ad7160eval_early_devices[] __initdata = {
823#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
824#ifdef CONFIG_SERIAL_BFIN_UART0
825 &bfin_uart0_device,
826#endif
827#ifdef CONFIG_SERIAL_BFIN_UART1
828 &bfin_uart1_device,
829#endif
830#endif
831
832#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
833#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
834 &bfin_sport0_uart_device,
835#endif
836#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
837 &bfin_sport1_uart_device,
838#endif
839#endif
840};
841
842void __init native_machine_early_platform_add_devices(void)
843{
844 printk(KERN_INFO "register early platform devices\n");
845 early_platform_add_devices(ad7160eval_early_devices,
846 ARRAY_SIZE(ad7160eval_early_devices));
847}
848
849void native_machine_restart(char *cmd)
850{
851 /* workaround reboot hang when booting from SPI */
852 if ((bfin_read_SYSCR() & 0x7) == 0x3)
853 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
854}
855
856void bfin_get_ether_addr(char *addr)
857{
858 /* the MAC is stored in OTP memory page 0xDF */
859 u32 ret;
860 u64 otp_mac;
861 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
862
863 ret = otp_read(0xDF, 0x00, &otp_mac);
864 if (!(ret & 0x1)) {
865 char *otp_mac_p = (char *)&otp_mac;
866 for (ret = 0; ret < 6; ++ret)
867 addr[ret] = otp_mac_p[5 - ret];
868 }
869}
870EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 645ba5c8077b..2c31af7a320a 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -273,13 +273,35 @@ static struct platform_device dm9000_device = {
273#endif 273#endif
274 274
275#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 275#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
276#include <linux/bfin_mac.h>
277static const unsigned short bfin_mac_peripherals[] = P_RMII0;
278
279static struct bfin_phydev_platform_data bfin_phydev_data[] = {
280 {
281 .addr = 1,
282 .irq = IRQ_MAC_PHYINT,
283 },
284};
285
286static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
287 .phydev_number = 1,
288 .phydev_data = bfin_phydev_data,
289 .phy_mode = PHY_INTERFACE_MODE_RMII,
290 .mac_peripherals = bfin_mac_peripherals,
291};
292
276static struct platform_device bfin_mii_bus = { 293static struct platform_device bfin_mii_bus = {
277 .name = "bfin_mii_bus", 294 .name = "bfin_mii_bus",
295 .dev = {
296 .platform_data = &bfin_mii_bus_data,
297 }
278}; 298};
279 299
280static struct platform_device bfin_mac_device = { 300static struct platform_device bfin_mac_device = {
281 .name = "bfin_mac", 301 .name = "bfin_mac",
282 .dev.platform_data = &bfin_mii_bus, 302 .dev = {
303 .platform_data = &bfin_mii_bus,
304 }
283}; 305};
284#endif 306#endif
285 307
@@ -342,8 +364,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
342}; 364};
343#endif 365#endif
344 366
345#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 367#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
346 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 368 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
347static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 369static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
348 .enable_dma = 0, 370 .enable_dma = 0,
349 .bits_per_word = 16, 371 .bits_per_word = 16,
@@ -420,13 +442,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
420 }, 442 },
421#endif 443#endif
422 444
423#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 445#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
424 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 446 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
425 { 447 {
426 .modalias = "ad1836", 448 .modalias = "ad183x",
427 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 449 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
428 .bus_num = 0, 450 .bus_num = 0,
429 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 451 .chip_select = 4,
430 .controller_data = &ad1836_spi_chip_info, 452 .controller_data = &ad1836_spi_chip_info,
431 }, 453 },
432#endif 454#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index c975fe88eba3..9a736a850c5c 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -137,8 +137,12 @@ static struct platform_device ezbrd_flash_device = {
137#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 137#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
138static struct mtd_partition partition_info[] = { 138static struct mtd_partition partition_info[] = {
139 { 139 {
140 .name = "linux kernel(nand)", 140 .name = "bootloader(nand)",
141 .offset = 0, 141 .offset = 0,
142 .size = 0x40000,
143 }, {
144 .name = "linux kernel(nand)",
145 .offset = MTDPART_OFS_APPEND,
142 .size = 4 * 1024 * 1024, 146 .size = 4 * 1024 * 1024,
143 }, 147 },
144 { 148 {
@@ -189,13 +193,35 @@ static struct platform_device rtc_device = {
189 193
190 194
191#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 195#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
196#include <linux/bfin_mac.h>
197static const unsigned short bfin_mac_peripherals[] = P_RMII0;
198
199static struct bfin_phydev_platform_data bfin_phydev_data[] = {
200 {
201 .addr = 1,
202 .irq = IRQ_MAC_PHYINT,
203 },
204};
205
206static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
207 .phydev_number = 1,
208 .phydev_data = bfin_phydev_data,
209 .phy_mode = PHY_INTERFACE_MODE_RMII,
210 .mac_peripherals = bfin_mac_peripherals,
211};
212
192static struct platform_device bfin_mii_bus = { 213static struct platform_device bfin_mii_bus = {
193 .name = "bfin_mii_bus", 214 .name = "bfin_mii_bus",
215 .dev = {
216 .platform_data = &bfin_mii_bus_data,
217 }
194}; 218};
195 219
196static struct platform_device bfin_mac_device = { 220static struct platform_device bfin_mac_device = {
197 .name = "bfin_mac", 221 .name = "bfin_mac",
198 .dev.platform_data = &bfin_mii_bus, 222 .dev = {
223 .platform_data = &bfin_mii_bus,
224 }
199}; 225};
200#endif 226#endif
201 227
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 87b41e994ba3..9222bc00bbd3 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -222,8 +222,12 @@ static struct platform_device ezkit_flash_device = {
222#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 222#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
223static struct mtd_partition partition_info[] = { 223static struct mtd_partition partition_info[] = {
224 { 224 {
225 .name = "linux kernel(nand)", 225 .name = "bootloader(nand)",
226 .offset = 0, 226 .offset = 0,
227 .size = 0x40000,
228 }, {
229 .name = "linux kernel(nand)",
230 .offset = MTDPART_OFS_APPEND,
227 .size = 4 * 1024 * 1024, 231 .size = 4 * 1024 * 1024,
228 }, 232 },
229 { 233 {
@@ -362,13 +366,35 @@ static struct platform_device dm9000_device = {
362#endif 366#endif
363 367
364#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 368#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
369#include <linux/bfin_mac.h>
370static const unsigned short bfin_mac_peripherals[] = P_RMII0;
371
372static struct bfin_phydev_platform_data bfin_phydev_data[] = {
373 {
374 .addr = 1,
375 .irq = IRQ_MAC_PHYINT,
376 },
377};
378
379static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
380 .phydev_number = 1,
381 .phydev_data = bfin_phydev_data,
382 .phy_mode = PHY_INTERFACE_MODE_RMII,
383 .mac_peripherals = bfin_mac_peripherals,
384};
385
365static struct platform_device bfin_mii_bus = { 386static struct platform_device bfin_mii_bus = {
366 .name = "bfin_mii_bus", 387 .name = "bfin_mii_bus",
388 .dev = {
389 .platform_data = &bfin_mii_bus_data,
390 }
367}; 391};
368 392
369static struct platform_device bfin_mac_device = { 393static struct platform_device bfin_mac_device = {
370 .name = "bfin_mac", 394 .name = "bfin_mac",
371 .dev.platform_data = &bfin_mii_bus, 395 .dev = {
396 .platform_data = &bfin_mii_bus,
397 }
372}; 398};
373#endif 399#endif
374 400
@@ -431,8 +457,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
431}; 457};
432#endif 458#endif
433 459
434#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 460#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
435 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 461 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
436static struct bfin5xx_spi_chip ad1836_spi_chip_info = { 462static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
437 .enable_dma = 0, 463 .enable_dma = 0,
438 .bits_per_word = 16, 464 .bits_per_word = 16,
@@ -547,13 +573,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
547 }, 573 },
548#endif 574#endif
549 575
550#if defined(CONFIG_SND_BLACKFIN_AD183X) \ 576#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
551 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) 577 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
552 { 578 {
553 .modalias = "ad1836", 579 .modalias = "ad183x",
554 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 580 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
555 .bus_num = 0, 581 .bus_num = 0,
556 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, 582 .chip_select = 4,
557 .controller_data = &ad1836_spi_chip_info, 583 .controller_data = &ad1836_spi_chip_info,
558 }, 584 },
559#endif 585#endif
@@ -883,7 +909,7 @@ static struct adp5520_keys_platform_data adp5520_keys_data = {
883}; 909};
884 910
885 /* 911 /*
886 * ADP5520/5501 Multifuction Device Init Data 912 * ADP5520/5501 Multifunction Device Init Data
887 */ 913 */
888 914
889static struct adp5520_platform_data adp5520_pdev_data = { 915static struct adp5520_platform_data adp5520_pdev_data = {
@@ -929,6 +955,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
929 I2C_BOARD_INFO("ssm2602", 0x1b), 955 I2C_BOARD_INFO("ssm2602", 0x1b),
930 }, 956 },
931#endif 957#endif
958#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
959 {
960 I2C_BOARD_INFO("ad5252", 0x2f),
961 },
962#endif
932}; 963};
933 964
934#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 965#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
new file mode 100644
index 000000000000..9ec575729e2c
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -0,0 +1,1008 @@
1/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
2 * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
3 * Author: Ashish Gupta
4 *
5 * Copyright: 2010 - The Learning Labs Inc.
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/i2c.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/usb/musb.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h>
26#include <asm/nand.h>
27#include <asm/portmux.h>
28#include <asm/dpmc.h>
29
30#if defined(CONFIG_TOUCHSCREEN_AD7879) \
31 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
32#include <linux/spi/ad7879.h>
33#define LCD_BACKLIGHT_GPIO 0x40
34/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
35 * LCD Backlight Enable
36 */
37#endif
38
39/*
40 * Name the Board for the /proc/cpuinfo
41 */
42const char bfin_board_name[] = "TLL6527M";
43/*
44 * Driver needs to know address, irq and flag pin.
45 */
46
47#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
48static struct resource musb_resources[] = {
49 [0] = {
50 .start = 0xffc03800,
51 .end = 0xffc03cff,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = { /* general IRQ */
55 .start = IRQ_USB_INT0,
56 .end = IRQ_USB_INT0,
57 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
58 },
59 [2] = { /* DMA IRQ */
60 .start = IRQ_USB_DMA,
61 .end = IRQ_USB_DMA,
62 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
63 },
64};
65
66static struct musb_hdrc_config musb_config = {
67 .multipoint = 0,
68 .dyn_fifo = 0,
69 .soft_con = 1,
70 .dma = 1,
71 .num_eps = 8,
72 .dma_channels = 8,
73 /*.gpio_vrsel = GPIO_PG13,*/
74 /* Some custom boards need to be active low, just set it to "0"
75 * if it is the case.
76 */
77 .gpio_vrsel_active = 1,
78};
79
80static struct musb_hdrc_platform_data musb_plat = {
81#if defined(CONFIG_USB_MUSB_OTG)
82 .mode = MUSB_OTG,
83#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
84 .mode = MUSB_HOST,
85#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
86 .mode = MUSB_PERIPHERAL,
87#endif
88 .config = &musb_config,
89};
90
91static u64 musb_dmamask = ~(u32)0;
92
93static struct platform_device musb_device = {
94 .name = "musb_hdrc",
95 .id = 0,
96 .dev = {
97 .dma_mask = &musb_dmamask,
98 .coherent_dma_mask = 0xffffffff,
99 .platform_data = &musb_plat,
100 },
101 .num_resources = ARRAY_SIZE(musb_resources),
102 .resource = musb_resources,
103};
104#endif
105
106#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
107#include <asm/bfin-lq035q1.h>
108
109static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
110 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
111 .ppi_mode = USE_RGB565_16_BIT_PPI,
112 .use_bl = 1,
113 .gpio_bl = LCD_BACKLIGHT_GPIO,
114};
115
116static struct resource bfin_lq035q1_resources[] = {
117 {
118 .start = IRQ_PPI_ERROR,
119 .end = IRQ_PPI_ERROR,
120 .flags = IORESOURCE_IRQ,
121 },
122};
123
124static struct platform_device bfin_lq035q1_device = {
125 .name = "bfin-lq035q1",
126 .id = -1,
127 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
128 .resource = bfin_lq035q1_resources,
129 .dev = {
130 .platform_data = &bfin_lq035q1_data,
131 },
132};
133#endif
134
135#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
136static struct mtd_partition tll6527m_partitions[] = {
137 {
138 .name = "bootloader(nor)",
139 .size = 0xA0000,
140 .offset = 0,
141 }, {
142 .name = "linux kernel(nor)",
143 .size = 0xD00000,
144 .offset = MTDPART_OFS_APPEND,
145 }, {
146 .name = "file system(nor)",
147 .size = MTDPART_SIZ_FULL,
148 .offset = MTDPART_OFS_APPEND,
149 }
150};
151
152static struct physmap_flash_data tll6527m_flash_data = {
153 .width = 2,
154 .parts = tll6527m_partitions,
155 .nr_parts = ARRAY_SIZE(tll6527m_partitions),
156};
157
158static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
159
160static struct resource tll6527m_flash_resource[] = {
161 {
162 .name = "cfi_probe",
163 .start = 0x20000000,
164 .end = 0x201fffff,
165 .flags = IORESOURCE_MEM,
166 }, {
167 .start = (unsigned long)tll6527m_flash_gpios,
168 .end = ARRAY_SIZE(tll6527m_flash_gpios),
169 .flags = IORESOURCE_IRQ,
170 }
171};
172
173static struct platform_device tll6527m_flash_device = {
174 .name = "gpio-addr-flash",
175 .id = 0,
176 .dev = {
177 .platform_data = &tll6527m_flash_data,
178 },
179 .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
180 .resource = tll6527m_flash_resource,
181};
182#endif
183
184#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
185/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
186 * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
187 * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
188 * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
189 */
190#include <linux/gpio-decoder.h>
191#define EXP_GPIO_SPISEL_BASE 0x64
192static unsigned gpio_addr_inputs[] = {
193 GPIO_PG1, GPIO_PH9, GPIO_PH10
194};
195
196static struct gpio_decoder_platfrom_data spi_decoded_cs = {
197 .base = EXP_GPIO_SPISEL_BASE,
198 .input_addrs = gpio_addr_inputs,
199 .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
200 .default_output = 0,
201/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
202};
203
204static struct platform_device spi_decoded_gpio = {
205 .name = "gpio-decoder",
206 .id = 0,
207 .dev = {
208 .platform_data = &spi_decoded_cs,
209 },
210};
211
212#else
213#define EXP_GPIO_SPISEL_BASE 0x0
214
215#endif
216
217#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
218#include <linux/input/adxl34x.h>
219static const struct adxl34x_platform_data adxl345_info = {
220 .x_axis_offset = 0,
221 .y_axis_offset = 0,
222 .z_axis_offset = 0,
223 .tap_threshold = 0x31,
224 .tap_duration = 0x10,
225 .tap_latency = 0x60,
226 .tap_window = 0xF0,
227 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
228 .act_axis_control = 0xFF,
229 .activity_threshold = 5,
230 .inactivity_threshold = 2,
231 .inactivity_time = 2,
232 .free_fall_threshold = 0x7,
233 .free_fall_time = 0x20,
234 .data_rate = 0x8,
235 .data_range = ADXL_FULL_RES,
236
237 .ev_type = EV_ABS,
238 .ev_code_x = ABS_X, /* EV_REL */
239 .ev_code_y = ABS_Y, /* EV_REL */
240 .ev_code_z = ABS_Z, /* EV_REL */
241
242 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
243
244/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
245 .ev_code_act_inactivity = KEY_A, /* EV_KEY */
246 .use_int2 = 1,
247 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
248 .fifo_mode = ADXL_FIFO_STREAM,
249};
250#endif
251
252#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
253static struct platform_device rtc_device = {
254 .name = "rtc-bfin",
255 .id = -1,
256};
257#endif
258
259#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
260#include <linux/bfin_mac.h>
261static const unsigned short bfin_mac_peripherals[] = P_RMII0;
262
263static struct bfin_phydev_platform_data bfin_phydev_data[] = {
264 {
265 .addr = 1,
266 .irq = IRQ_MAC_PHYINT,
267 },
268};
269
270static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
271 .phydev_number = 1,
272 .phydev_data = bfin_phydev_data,
273 .phy_mode = PHY_INTERFACE_MODE_RMII,
274 .mac_peripherals = bfin_mac_peripherals,
275};
276
277static struct platform_device bfin_mii_bus = {
278 .name = "bfin_mii_bus",
279 .dev = {
280 .platform_data = &bfin_mii_bus_data,
281 }
282};
283
284static struct platform_device bfin_mac_device = {
285 .name = "bfin_mac",
286 .dev = {
287 .platform_data = &bfin_mii_bus,
288 }
289};
290#endif
291
292#if defined(CONFIG_MTD_M25P80) \
293 || defined(CONFIG_MTD_M25P80_MODULE)
294static struct mtd_partition bfin_spi_flash_partitions[] = {
295 {
296 .name = "bootloader(spi)",
297 .size = 0x00040000,
298 .offset = 0,
299 .mask_flags = MTD_CAP_ROM
300 }, {
301 .name = "linux kernel(spi)",
302 .size = MTDPART_SIZ_FULL,
303 .offset = MTDPART_OFS_APPEND,
304 }
305};
306
307static struct flash_platform_data bfin_spi_flash_data = {
308 .name = "m25p80",
309 .parts = bfin_spi_flash_partitions,
310 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
311 .type = "m25p16",
312};
313
314/* SPI flash chip (m25p64) */
315static struct bfin5xx_spi_chip spi_flash_chip_info = {
316 .enable_dma = 0, /* use dma transfer with this chip*/
317 .bits_per_word = 8,
318};
319#endif
320
321#if defined(CONFIG_BFIN_SPI_ADC) \
322 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
323/* SPI ADC chip */
324static struct bfin5xx_spi_chip spi_adc_chip_info = {
325 .enable_dma = 0, /* use dma transfer with this chip*/
326/*
327 * tll6527m V1.0 does not support native spi slave selects
328 * hence DMA mode will not be useful since the ADC needs
329 * CS to toggle for each sample and cs_change_per_word
330 * seems to be removed from spi_bfin5xx.c
331 */
332 .bits_per_word = 16,
333};
334#endif
335
336#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
337static struct bfin5xx_spi_chip mmc_spi_chip_info = {
338 .enable_dma = 0,
339 .bits_per_word = 8,
340};
341#endif
342
343#if defined(CONFIG_TOUCHSCREEN_AD7879) \
344 || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
345static const struct ad7879_platform_data bfin_ad7879_ts_info = {
346 .model = 7879, /* Model = AD7879 */
347 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
348 .pressure_max = 10000,
349 .pressure_min = 0,
350 .first_conversion_delay = 3,
351 /* wait 512us before do a first conversion */
352 .acquisition_time = 1, /* 4us acquisition time per sample */
353 .median = 2, /* do 8 measurements */
354 .averaging = 1,
355 /* take the average of 4 middle samples */
356 .pen_down_acc_interval = 255, /* 9.4 ms */
357 .gpio_export = 1, /* configure AUX as GPIO output*/
358 .gpio_base = LCD_BACKLIGHT_GPIO,
359};
360#endif
361
362#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
363 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
364static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
365 .enable_dma = 0,
366 .bits_per_word = 16,
367};
368#endif
369
370#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
371static struct bfin5xx_spi_chip spidev_chip_info = {
372 .enable_dma = 0,
373 .bits_per_word = 8,
374};
375#endif
376
377#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
378static struct platform_device bfin_i2s = {
379 .name = "bfin-i2s",
380 .id = CONFIG_SND_BF5XX_SPORT_NUM,
381 /* TODO: add platform data here */
382};
383#endif
384
385#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
386static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
387 .enable_dma = 0,
388 .bits_per_word = 8,
389};
390#endif
391
392#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
393static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
394 .enable_dma = 0,
395 .bits_per_word = 8,
396};
397
398static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
399 .enable_dma = 0,
400 .bits_per_word = 8,
401};
402
403#include <linux/spi/mcp23s08.h>
404static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
405 .chip[0].is_present = true,
406 .base = 0x30,
407};
408static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
409 .chip[2].is_present = true,
410 .base = 0x38,
411};
412#endif
413
414static struct spi_board_info bfin_spi_board_info[] __initdata = {
415#if defined(CONFIG_MTD_M25P80) \
416 || defined(CONFIG_MTD_M25P80_MODULE)
417 {
418 /* the modalias must be the same as spi device driver name */
419 .modalias = "m25p80", /* Name of spi_driver for this device */
420 .max_speed_hz = 25000000,
421 /* max spi clock (SCK) speed in HZ */
422 .bus_num = 0, /* Framework bus number */
423 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
424 /* Can be connected to TLL6527M GPIO connector */
425 /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
426 .platform_data = &bfin_spi_flash_data,
427 .controller_data = &spi_flash_chip_info,
428 .mode = SPI_MODE_3,
429 },
430#endif
431
432#if defined(CONFIG_BFIN_SPI_ADC)
433 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
434 {
435 .modalias = "bfin_spi_adc",
436 /* Name of spi_driver for this device */
437 .max_speed_hz = 10000000,
438 /* max spi clock (SCK) speed in HZ */
439 .bus_num = 0, /* Framework bus number */
440 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
441 /* Framework chip select. */
442 .platform_data = NULL, /* No spi_driver specific config */
443 .controller_data = &spi_adc_chip_info,
444 .mode = SPI_MODE_0,
445 },
446#endif
447
448#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
449 {
450 .modalias = "mmc_spi",
451/*
452 * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
453 * SPI buffer limitations
454 */
455 .max_speed_hz = 10000000,
456 /* max spi clock (SCK) speed in HZ */
457 .bus_num = 0,
458 .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
459 .controller_data = &mmc_spi_chip_info,
460 .mode = SPI_MODE_0,
461 },
462#endif
463#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
464 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
465 {
466 .modalias = "ad7879",
467 .platform_data = &bfin_ad7879_ts_info,
468 .irq = IRQ_PH14,
469 .max_speed_hz = 5000000,
470 /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0,
472 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
473 .controller_data = &spi_ad7879_chip_info,
474 .mode = SPI_CPHA | SPI_CPOL,
475 },
476#endif
477#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
478 {
479 .modalias = "spidev",
480 .max_speed_hz = 10000000,
481 /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
482 .bus_num = 0,
483 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
484 .mode = SPI_CPHA | SPI_CPOL,
485 .controller_data = &spidev_chip_info,
486 },
487#endif
488#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
489 {
490 .modalias = "bfin-lq035q1-spi",
491 .max_speed_hz = 20000000,
492 .bus_num = 0,
493 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
494 .controller_data = &lq035q1_spi_chip_info,
495 .mode = SPI_CPHA | SPI_CPOL,
496 },
497#endif
498#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
499 {
500 .modalias = "mcp23s08",
501 .platform_data = &bfin_mcp23s08_sys_gpio_info,
502 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
503 .bus_num = 0,
504 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
505 .controller_data = &spi_mcp23s08_sys_chip_info,
506 .mode = SPI_CPHA | SPI_CPOL,
507 },
508 {
509 .modalias = "mcp23s08",
510 .platform_data = &bfin_mcp23s08_usr_gpio_info,
511 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
512 .bus_num = 0,
513 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
514 .controller_data = &spi_mcp23s08_usr_chip_info,
515 .mode = SPI_CPHA | SPI_CPOL,
516 },
517#endif
518};
519
520#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
521/* SPI controller data */
522static struct bfin5xx_spi_master bfin_spi0_info = {
523 .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
524 /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
525 .enable_dma = 1, /* master has the ability to do dma transfer */
526 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
527};
528
529/* SPI (0) */
530static struct resource bfin_spi0_resource[] = {
531 [0] = {
532 .start = SPI0_REGBASE,
533 .end = SPI0_REGBASE + 0xFF,
534 .flags = IORESOURCE_MEM,
535 },
536 [1] = {
537 .start = CH_SPI,
538 .end = CH_SPI,
539 .flags = IORESOURCE_DMA,
540 },
541 [2] = {
542 .start = IRQ_SPI,
543 .end = IRQ_SPI,
544 .flags = IORESOURCE_IRQ,
545 },
546};
547
548static struct platform_device bfin_spi0_device = {
549 .name = "bfin-spi",
550 .id = 0, /* Bus number */
551 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
552 .resource = bfin_spi0_resource,
553 .dev = {
554 .platform_data = &bfin_spi0_info, /* Passed to driver */
555 },
556};
557#endif /* spi master and devices */
558
559#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
560#ifdef CONFIG_SERIAL_BFIN_UART0
561static struct resource bfin_uart0_resources[] = {
562 {
563 .start = UART0_THR,
564 .end = UART0_GCTL+2,
565 .flags = IORESOURCE_MEM,
566 },
567 {
568 .start = IRQ_UART0_RX,
569 .end = IRQ_UART0_RX+1,
570 .flags = IORESOURCE_IRQ,
571 },
572 {
573 .start = IRQ_UART0_ERROR,
574 .end = IRQ_UART0_ERROR,
575 .flags = IORESOURCE_IRQ,
576 },
577 {
578 .start = CH_UART0_TX,
579 .end = CH_UART0_TX,
580 .flags = IORESOURCE_DMA,
581 },
582 {
583 .start = CH_UART0_RX,
584 .end = CH_UART0_RX,
585 .flags = IORESOURCE_DMA,
586 },
587};
588
589unsigned short bfin_uart0_peripherals[] = {
590 P_UART0_TX, P_UART0_RX, 0
591};
592
593static struct platform_device bfin_uart0_device = {
594 .name = "bfin-uart",
595 .id = 0,
596 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
597 .resource = bfin_uart0_resources,
598 .dev = {
599 .platform_data = &bfin_uart0_peripherals,
600 /* Passed to driver */
601 },
602};
603#endif
604#ifdef CONFIG_SERIAL_BFIN_UART1
605static struct resource bfin_uart1_resources[] = {
606 {
607 .start = UART1_THR,
608 .end = UART1_GCTL+2,
609 .flags = IORESOURCE_MEM,
610 },
611 {
612 .start = IRQ_UART1_RX,
613 .end = IRQ_UART1_RX+1,
614 .flags = IORESOURCE_IRQ,
615 },
616 {
617 .start = IRQ_UART1_ERROR,
618 .end = IRQ_UART1_ERROR,
619 .flags = IORESOURCE_IRQ,
620 },
621 {
622 .start = CH_UART1_TX,
623 .end = CH_UART1_TX,
624 .flags = IORESOURCE_DMA,
625 },
626 {
627 .start = CH_UART1_RX,
628 .end = CH_UART1_RX,
629 .flags = IORESOURCE_DMA,
630 },
631#ifdef CONFIG_BFIN_UART1_CTSRTS
632 { /* CTS pin */
633 .start = GPIO_PF9,
634 .end = GPIO_PF9,
635 .flags = IORESOURCE_IO,
636 },
637 { /* RTS pin */
638 .start = GPIO_PF10,
639 .end = GPIO_PF10,
640 .flags = IORESOURCE_IO,
641 },
642#endif
643};
644
645unsigned short bfin_uart1_peripherals[] = {
646 P_UART1_TX, P_UART1_RX, 0
647};
648
649static struct platform_device bfin_uart1_device = {
650 .name = "bfin-uart",
651 .id = 1,
652 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
653 .resource = bfin_uart1_resources,
654 .dev = {
655 .platform_data = &bfin_uart1_peripherals,
656 /* Passed to driver */
657 },
658};
659#endif
660#endif
661
662#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
663#ifdef CONFIG_BFIN_SIR0
664static struct resource bfin_sir0_resources[] = {
665 {
666 .start = 0xFFC00400,
667 .end = 0xFFC004FF,
668 .flags = IORESOURCE_MEM,
669 },
670 {
671 .start = IRQ_UART0_RX,
672 .end = IRQ_UART0_RX+1,
673 .flags = IORESOURCE_IRQ,
674 },
675 {
676 .start = CH_UART0_RX,
677 .end = CH_UART0_RX+1,
678 .flags = IORESOURCE_DMA,
679 },
680};
681
682static struct platform_device bfin_sir0_device = {
683 .name = "bfin_sir",
684 .id = 0,
685 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
686 .resource = bfin_sir0_resources,
687};
688#endif
689#ifdef CONFIG_BFIN_SIR1
690static struct resource bfin_sir1_resources[] = {
691 {
692 .start = 0xFFC02000,
693 .end = 0xFFC020FF,
694 .flags = IORESOURCE_MEM,
695 },
696 {
697 .start = IRQ_UART1_RX,
698 .end = IRQ_UART1_RX+1,
699 .flags = IORESOURCE_IRQ,
700 },
701 {
702 .start = CH_UART1_RX,
703 .end = CH_UART1_RX+1,
704 .flags = IORESOURCE_DMA,
705 },
706};
707
708static struct platform_device bfin_sir1_device = {
709 .name = "bfin_sir",
710 .id = 1,
711 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
712 .resource = bfin_sir1_resources,
713};
714#endif
715#endif
716
717#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
718static struct resource bfin_twi0_resource[] = {
719 [0] = {
720 .start = TWI0_REGBASE,
721 .end = TWI0_REGBASE,
722 .flags = IORESOURCE_MEM,
723 },
724 [1] = {
725 .start = IRQ_TWI,
726 .end = IRQ_TWI,
727 .flags = IORESOURCE_IRQ,
728 },
729};
730
731static struct platform_device i2c_bfin_twi_device = {
732 .name = "i2c-bfin-twi",
733 .id = 0,
734 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
735 .resource = bfin_twi0_resource,
736};
737#endif
738
739static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
740#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
741 {
742 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
743 },
744#endif
745
746#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
747 {
748 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
749 },
750#endif
751#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \
752 || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
753 {
754 I2C_BOARD_INFO("ad7879", 0x2C),
755 .irq = IRQ_PH14,
756 .platform_data = (void *)&bfin_ad7879_ts_info,
757 },
758#endif
759#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
760 {
761 I2C_BOARD_INFO("ssm2602", 0x1b),
762 },
763#endif
764 {
765 I2C_BOARD_INFO("adm1192", 0x2e),
766 },
767
768 {
769 I2C_BOARD_INFO("ltc3576", 0x09),
770 },
771#if defined(CONFIG_INPUT_ADXL34X_I2C) \
772 || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
773 {
774 I2C_BOARD_INFO("adxl34x", 0x53),
775 .irq = IRQ_PH13,
776 .platform_data = (void *)&adxl345_info,
777 },
778#endif
779};
780
781#if defined(CONFIG_SERIAL_BFIN_SPORT) \
782 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
783#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
784static struct resource bfin_sport0_uart_resources[] = {
785 {
786 .start = SPORT0_TCR1,
787 .end = SPORT0_MRCS3+4,
788 .flags = IORESOURCE_MEM,
789 },
790 {
791 .start = IRQ_SPORT0_RX,
792 .end = IRQ_SPORT0_RX+1,
793 .flags = IORESOURCE_IRQ,
794 },
795 {
796 .start = IRQ_SPORT0_ERROR,
797 .end = IRQ_SPORT0_ERROR,
798 .flags = IORESOURCE_IRQ,
799 },
800};
801
802unsigned short bfin_sport0_peripherals[] = {
803 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
804 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
805};
806
807static struct platform_device bfin_sport0_uart_device = {
808 .name = "bfin-sport-uart",
809 .id = 0,
810 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
811 .resource = bfin_sport0_uart_resources,
812 .dev = {
813 .platform_data = &bfin_sport0_peripherals,
814 /* Passed to driver */
815 },
816};
817#endif
818#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
819static struct resource bfin_sport1_uart_resources[] = {
820 {
821 .start = SPORT1_TCR1,
822 .end = SPORT1_MRCS3+4,
823 .flags = IORESOURCE_MEM,
824 },
825 {
826 .start = IRQ_SPORT1_RX,
827 .end = IRQ_SPORT1_RX+1,
828 .flags = IORESOURCE_IRQ,
829 },
830 {
831 .start = IRQ_SPORT1_ERROR,
832 .end = IRQ_SPORT1_ERROR,
833 .flags = IORESOURCE_IRQ,
834 },
835};
836
837unsigned short bfin_sport1_peripherals[] = {
838 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
839 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
840};
841
842static struct platform_device bfin_sport1_uart_device = {
843 .name = "bfin-sport-uart",
844 .id = 1,
845 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
846 .resource = bfin_sport1_uart_resources,
847 .dev = {
848 .platform_data = &bfin_sport1_peripherals,
849 /* Passed to driver */
850 },
851};
852#endif
853#endif
854
855static const unsigned int cclk_vlev_datasheet[] = {
856 VRPAIR(VLEV_100, 400000000),
857 VRPAIR(VLEV_105, 426000000),
858 VRPAIR(VLEV_110, 500000000),
859 VRPAIR(VLEV_115, 533000000),
860 VRPAIR(VLEV_120, 600000000),
861};
862
863static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
864 .tuple_tab = cclk_vlev_datasheet,
865 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
866 .vr_settling_time = 25 /* us */,
867};
868
869static struct platform_device bfin_dpmc = {
870 .name = "bfin dpmc",
871 .dev = {
872 .platform_data = &bfin_dmpc_vreg_data,
873 },
874};
875
876static struct platform_device *tll6527m_devices[] __initdata = {
877
878 &bfin_dpmc,
879
880#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
881 &rtc_device,
882#endif
883
884#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
885 &musb_device,
886#endif
887
888#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
889 &bfin_mii_bus,
890 &bfin_mac_device,
891#endif
892
893#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
894 &bfin_spi0_device,
895#endif
896
897#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
898 &bfin_lq035q1_device,
899#endif
900
901#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
902#ifdef CONFIG_SERIAL_BFIN_UART0
903 &bfin_uart0_device,
904#endif
905#ifdef CONFIG_SERIAL_BFIN_UART1
906 &bfin_uart1_device,
907#endif
908#endif
909
910#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
911#ifdef CONFIG_BFIN_SIR0
912 &bfin_sir0_device,
913#endif
914#ifdef CONFIG_BFIN_SIR1
915 &bfin_sir1_device,
916#endif
917#endif
918
919#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
920 &i2c_bfin_twi_device,
921#endif
922
923#if defined(CONFIG_SERIAL_BFIN_SPORT) \
924 || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
925#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
926 &bfin_sport0_uart_device,
927#endif
928#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
929 &bfin_sport1_uart_device,
930#endif
931#endif
932
933#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
934 &tll6527m_flash_device,
935#endif
936
937#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
938 &bfin_i2s,
939#endif
940
941#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
942 &spi_decoded_gpio,
943#endif
944};
945
946static int __init tll6527m_init(void)
947{
948 printk(KERN_INFO "%s(): registering device resources\n", __func__);
949 i2c_register_board_info(0, bfin_i2c_board_info,
950 ARRAY_SIZE(bfin_i2c_board_info));
951 platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
952 spi_register_board_info(bfin_spi_board_info,
953 ARRAY_SIZE(bfin_spi_board_info));
954 return 0;
955}
956
957arch_initcall(tll6527m_init);
958
959static struct platform_device *tll6527m_early_devices[] __initdata = {
960#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
961#ifdef CONFIG_SERIAL_BFIN_UART0
962 &bfin_uart0_device,
963#endif
964#ifdef CONFIG_SERIAL_BFIN_UART1
965 &bfin_uart1_device,
966#endif
967#endif
968
969#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
970#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
971 &bfin_sport0_uart_device,
972#endif
973#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
974 &bfin_sport1_uart_device,
975#endif
976#endif
977};
978
979void __init native_machine_early_platform_add_devices(void)
980{
981 printk(KERN_INFO "register early platform devices\n");
982 early_platform_add_devices(tll6527m_early_devices,
983 ARRAY_SIZE(tll6527m_early_devices));
984}
985
986void native_machine_restart(char *cmd)
987{
988 /* workaround reboot hang when booting from SPI */
989 if ((bfin_read_SYSCR() & 0x7) == 0x3)
990 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
991}
992
993void bfin_get_ether_addr(char *addr)
994{
995 /* the MAC is stored in OTP memory page 0xDF */
996 u32 ret;
997 u64 otp_mac;
998 u32 (*otp_read)(u32 page, u32 flags,
999 u64 *page_content) = (void *)0xEF00001A;
1000
1001 ret = otp_read(0xDF, 0x00, &otp_mac);
1002 if (!(ret & 0x1)) {
1003 char *otp_mac_p = (char *)&otp_mac;
1004 for (ret = 0; ret < 6; ++ret)
1005 addr[ret] = otp_mac_p[5 - ret];
1006 }
1007}
1008EXPORT_SYMBOL(bfin_get_ether_addr);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 03:25:43 -0500