diff options
Diffstat (limited to 'arch/blackfin/mach-bf518')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | 8 |
2 files changed, 6 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h index e16969f24ffd..71eff1f13b5e 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h | |||
| @@ -377,16 +377,10 @@ | |||
| 377 | 377 | ||
| 378 | 378 | ||
| 379 | /* DMA Traffic Control Registers */ | 379 | /* DMA Traffic Control Registers */ |
| 380 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | 380 | #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) |
| 381 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) | 381 | #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) |
| 382 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | 382 | #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) |
| 383 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) | 383 | #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) |
| 384 | |||
| 385 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 386 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | ||
| 387 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) | ||
| 388 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | ||
| 389 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) | ||
| 390 | 384 | ||
| 391 | /* DMA Controller */ | 385 | /* DMA Controller */ |
| 392 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | 386 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index e816c63a5a5f..1ac16e7f7b76 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | |||
| @@ -215,12 +215,8 @@ | |||
| 215 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | 215 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ |
| 216 | 216 | ||
| 217 | /* DMA Traffic Control Registers */ | 217 | /* DMA Traffic Control Registers */ |
| 218 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | 218 | #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
| 219 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | 219 | #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
| 220 | |||
| 221 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 222 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
| 223 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
| 224 | 220 | ||
| 225 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | 221 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ |
| 226 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | 222 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |