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Diffstat (limited to 'arch/blackfin/mach-bf518/include/mach/irq.h')
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index e5062f107ae2..3ff0f093313d 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -98,14 +98,14 @@
98#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 98#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
99#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */ 99#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
100#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 100#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
101#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ 101#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
102#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ 102#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
103#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ 103#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
104#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ 104#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
105#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ 105#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
106#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ 106#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
107#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ 107#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
108#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ 108#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
109#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ 109#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
110#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ 110#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
111#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ 111#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
@@ -230,14 +230,14 @@
230#define IRQ_PORTH_INTB_POS 28 230#define IRQ_PORTH_INTB_POS 28
231 231
232/* IAR4 BIT FIELDS */ 232/* IAR4 BIT FIELDS */
233#define IRQ_TMR0_POS 0 233#define IRQ_TIMER0_POS 0
234#define IRQ_TMR1_POS 4 234#define IRQ_TIMER1_POS 4
235#define IRQ_TMR2_POS 8 235#define IRQ_TIMER2_POS 8
236#define IRQ_TMR3_POS 12 236#define IRQ_TIMER3_POS 12
237#define IRQ_TMR4_POS 16 237#define IRQ_TIMER4_POS 16
238#define IRQ_TMR5_POS 20 238#define IRQ_TIMER5_POS 20
239#define IRQ_TMR6_POS 24 239#define IRQ_TIMER6_POS 24
240#define IRQ_TMR7_POS 28 240#define IRQ_TIMER7_POS 28
241 241
242/* IAR5 BIT FIELDS */ 242/* IAR5 BIT FIELDS */
243#define IRQ_PORTG_INTA_POS 0 243#define IRQ_PORTG_INTA_POS 0