3 files changed, 107 insertions, 35 deletions

diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index c006a44527bf..36193eed9a1f 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
 
         printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
 
-#ifdef CONFIG_BFIN_ICACHE
+#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
         i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
 #endif
 
-#ifdef CONFIG_BFIN_DCACHE
+#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
         d_cache = CPLB_L1_CHBL;
-#ifdef CONFIG_BFIN_WT
+#ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH
         d_cache |= CPLB_L1_AOW | CPLB_WT;
 #endif
 #endif
@@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
         /* Cover L2 memory */
 #if L2_LENGTH > 0
         dcplb_tbl[cpu][i_d].addr = L2_START;
-        dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
+        dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
         icplb_tbl[cpu][i_i].addr = L2_START;
-        icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
+        icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
 #endif
 
         first_mask_dcplb = i_d;
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 784923e52a9a..bcdfe9b0b71f 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -150,15 +150,19 @@ static noinline int dcplb_miss(unsigned int cpu)
         nr_dcplb_miss[cpu]++;
 
         d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_DCACHE
+#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
         if (bfin_addr_dcacheable(addr)) {
                 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#ifdef CONFIG_BFIN_WT
+# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
                 d_data |= CPLB_L1_AOW | CPLB_WT;
-#endif
+# endif
         }
 #endif
-        if (addr >= physical_mem_end) {
+
+        if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
+                addr = L2_START;
+                d_data = L2_DMEMORY;
+        } else if (addr >= physical_mem_end) {
                 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
                     && (status & FAULT_USERSUPV)) {
                         addr &= ~0x3fffff;
@@ -235,7 +239,7 @@ static noinline int icplb_miss(unsigned int cpu)
 
         i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
 
-#ifdef CONFIG_BFIN_ICACHE
+#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
         /*
          * Normal RAM, and possibly the reserved memory area, are
          * cacheable.
@@ -245,7 +249,10 @@ static noinline int icplb_miss(unsigned int cpu)
                 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
 #endif
 
-        if (addr >= physical_mem_end) {
+        if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
+                addr = L2_START;
+                i_data = L2_IMEMORY;
+        } else if (addr >= physical_mem_end) {
                 if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
                     && (status & FAULT_USERSUPV)) {
                         addr &= ~(1 * 1024 * 1024 - 1);
@@ -365,13 +372,18 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
         local_irq_save_hw(flags);
         current_rwx_mask[cpu] = masks;
 
-        d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_DCACHE
-        d_data |= CPLB_L1_CHBL;
-#ifdef CONFIG_BFIN_WT
-        d_data |= CPLB_L1_AOW | CPLB_WT;
-#endif
+        if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
+                addr = L2_START;
+                d_data = L2_DMEMORY;
+        } else {
+                d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
+#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
+                d_data |= CPLB_L1_CHBL;
+# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
+                d_data |= CPLB_L1_AOW | CPLB_WT;
+# endif
 #endif
+        }
 
         disable_dcplb();
         for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index b2782eae31e1..8d7892820130 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -117,15 +117,49 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
          */
 #ifdef CONFIG_BFIN_ICACHE
         printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
+        printk(KERN_INFO "  External memory:"
+# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
+               " cacheable"
+# else
+               " uncacheable"
+# endif
+               " in instruction cache\n");
+        if (L2_LENGTH)
+                printk(KERN_INFO "  L2 SRAM        :"
+# ifdef CONFIG_BFIN_L2_ICACHEABLE
+                       " cacheable"
+# else
+                       " uncacheable"
+# endif
+                       " in instruction cache\n");
+
+#else
+        printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
 #endif
+
 #ifdef CONFIG_BFIN_DCACHE
-        printk(KERN_INFO "Data Cache Enabled for CPU%u"
-# if defined CONFIG_BFIN_WB
-                " (write-back)"
-# elif defined CONFIG_BFIN_WT
-                " (write-through)"
+        printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
+        printk(KERN_INFO "  External memory:"
+# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
+               " cacheable (write-back)"
+# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
+               " cacheable (write-through)"
+# else
+               " uncacheable"
+# endif
+               " in data cache\n");
+        if (L2_LENGTH)
+                printk(KERN_INFO "  L2 SRAM        :"
+# if defined CONFIG_BFIN_L2_WRITEBACK
+                       " cacheable (write-back)"
+# elif defined CONFIG_BFIN_L2_WRITETHROUGH
+                       " cacheable (write-through)"
+# else
+                       " uncacheable"
 # endif
-                "\n", cpu);
+                       " in data cache\n");
+#else
+        printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
 #endif
 }
 
@@ -516,7 +550,7 @@ static __init void memory_setup(void)
             && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
                 mtd_size =
                     PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
-#  if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
+#  if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
         /* Due to a Hardware Anomaly we need to limit the size of usable
          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -544,7 +578,7 @@ static __init void memory_setup(void)
         dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
 #endif                          /* CONFIG_MTD_UCLINUX */
 
-#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
+#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
         /* Due to a Hardware Anomaly we need to limit the size of usable
          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -1158,16 +1192,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 icache_size = 0;
 
         seq_printf(m, "cache size\t: %d KB(L1 icache) "
-                "%d KB(L1 dcache%s) %d KB(L2 cache)\n",
-                icache_size, dcache_size,
-#if defined CONFIG_BFIN_WB
-                "-wb"
-#elif defined CONFIG_BFIN_WT
-                "-wt"
-#endif
-                "", 0);
-
+                "%d KB(L1 dcache) %d KB(L2 cache)\n",
+                icache_size, dcache_size, 0);
         seq_printf(m, "%s\n", cache);
+        seq_printf(m, "external memory\t: "
+#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
+                   "cacheable"
+#else
+                   "uncacheable"
+#endif
+                   " in instruction cache\n");
+        seq_printf(m, "external memory\t: "
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
+                      "cacheable (write-back)"
+#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
+                      "cacheable (write-through)"
+#else
+                      "uncacheable"
+#endif
+                      " in data cache\n");
 
         if (icache_size)
                 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
@@ -1240,8 +1283,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         if (cpu_num != num_possible_cpus() - 1)
                 return 0;
 
-        if (L2_LENGTH)
+        if (L2_LENGTH) {
                 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
+                seq_printf(m, "L2 SRAM\t\t: "
+#if defined(CONFIG_BFIN_L2_ICACHEABLE)
+                              "cacheable"
+#else
+                              "uncacheable"
+#endif
+                              " in instruction cache\n");
+                seq_printf(m, "L2 SRAM\t\t: "
+#if defined(CONFIG_BFIN_L2_WRITEBACK)
+                              "cacheable (write-back)"
+#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
+                              "cacheable (write-through)"
+#else
+                              "uncacheable"
+#endif
+                              " in data cache\n");
+        }
         seq_printf(m, "board name\t: %s\n", bfin_board_name);
         seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
                  physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);