7 files changed, 282 insertions, 76 deletions

diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
index 40c2ed61258e..b612324fb8da 100644
--- a/arch/blackfin/kernel/bfin_dma.c
+++ b/arch/blackfin/kernel/bfin_dma.c
@@ -45,9 +45,15 @@ static int __init blackfin_dma_init(void)
                 atomic_set(&dma_ch[i].chan_status, 0);
                 dma_ch[i].regs = dma_io_base_addr[i];
         }
+#ifdef CH_MEM_STREAM3_SRC
+        /* Mark MEMDMA Channel 3 as requested since we're using it internally */
+        request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
+        request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
+#else
         /* Mark MEMDMA Channel 0 as requested since we're using it internally */
         request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
         request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
+#endif
 
 #if defined(CONFIG_DEB_DMA_URGENT)
         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
@@ -204,6 +210,7 @@ EXPORT_SYMBOL(free_dma);
 # ifndef MAX_DMA_SUSPEND_CHANNELS
 #  define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
 # endif
+# ifndef CONFIG_BF60x
 int blackfin_dma_suspend(void)
 {
         int i;
@@ -213,7 +220,6 @@ int blackfin_dma_suspend(void)
                         printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
                         return -EBUSY;
                 }
-
                 if (i < MAX_DMA_SUSPEND_CHANNELS)
                         dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
         }
@@ -230,7 +236,6 @@ void blackfin_dma_resume(void)
 
         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
                 dma_ch[i].regs->cfg = 0;
-
                 if (i < MAX_DMA_SUSPEND_CHANNELS)
                         dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
         }
@@ -238,6 +243,16 @@ void blackfin_dma_resume(void)
         bfin_write_DMAC_TC_PER(0x0111);
 #endif
 }
+# else
+int blackfin_dma_suspend(void)
+{
+        return 0;
+}
+
+void blackfin_dma_resume(void)
+{
+}
+#endif
 #endif
 
 /**
@@ -279,10 +294,10 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
                         src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
                 }
 
-                if (!bfin_read16(&src_ch->cfg))
+                if (!DMA_MMR_READ(&src_ch->cfg))
                         break;
-                else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
-                        bfin_write16(&src_ch->cfg, 0);
+                else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
+                        DMA_MMR_WRITE(&src_ch->cfg, 0);
                         break;
                 }
         }
@@ -295,22 +310,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
 
         /* Destination */
         bfin_write32(&dst_ch->start_addr, dst);
-        bfin_write16(&dst_ch->x_count, size >> 2);
-        bfin_write16(&dst_ch->x_modify, 1 << 2);
-        bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
+        DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
+        DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
+        DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
 
         /* Source */
         bfin_write32(&src_ch->start_addr, src);
-        bfin_write16(&src_ch->x_count, size >> 2);
-        bfin_write16(&src_ch->x_modify, 1 << 2);
-        bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
+        DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
+        DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
+        DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
 
         /* Enable */
-        bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
-        bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
+        DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
+        DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
 
         /* Since we are atomic now, don't use the workaround ssync */
         __builtin_bfin_ssync();
+
+#ifdef CONFIG_BF60x
+        /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
+         * transfer DDR data to L1 SRAM may corrupt data.
+         * Should be reverted after this issue is root caused.
+         */
+        while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
+                continue;
+#endif
 }
 
 void __init early_dma_memcpy_done(void)
@@ -336,6 +360,42 @@ void __init early_dma_memcpy_done(void)
         __builtin_bfin_ssync();
 }
 
+#ifdef CH_MEM_STREAM3_SRC
+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
+#else
+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
+#endif
+
 /**
  *      __dma_memcpy - program the MDMA registers
  *
@@ -358,8 +418,8 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
          */
         __builtin_bfin_ssync();
 
-        if (bfin_read_MDMA_S0_CONFIG())
-                while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+        if (bfin_read_MDMA_S_CONFIG())
+                while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
                         continue;
 
         if (conf & DMA2D) {
@@ -374,39 +434,42 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
                 u32 shift = abs(dmod) >> 1;
                 size_t ycnt = cnt >> (16 - shift);
                 cnt = 1 << (16 - shift);
-                bfin_write_MDMA_D0_Y_COUNT(ycnt);
-                bfin_write_MDMA_S0_Y_COUNT(ycnt);
-                bfin_write_MDMA_D0_Y_MODIFY(dmod);
-                bfin_write_MDMA_S0_Y_MODIFY(smod);
+                bfin_write_MDMA_D_Y_COUNT(ycnt);
+                bfin_write_MDMA_S_Y_COUNT(ycnt);
+                bfin_write_MDMA_D_Y_MODIFY(dmod);
+                bfin_write_MDMA_S_Y_MODIFY(smod);
         }
 
-        bfin_write_MDMA_D0_START_ADDR(daddr);
-        bfin_write_MDMA_D0_X_COUNT(cnt);
-        bfin_write_MDMA_D0_X_MODIFY(dmod);
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        bfin_write_MDMA_D_START_ADDR(daddr);
+        bfin_write_MDMA_D_X_COUNT(cnt);
+        bfin_write_MDMA_D_X_MODIFY(dmod);
+        bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
 
-        bfin_write_MDMA_S0_START_ADDR(saddr);
-        bfin_write_MDMA_S0_X_COUNT(cnt);
-        bfin_write_MDMA_S0_X_MODIFY(smod);
-        bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        bfin_write_MDMA_S_START_ADDR(saddr);
+        bfin_write_MDMA_S_X_COUNT(cnt);
+        bfin_write_MDMA_S_X_MODIFY(smod);
+        bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
 
-        bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
+        bfin_write_MDMA_S_CONFIG(DMAEN | conf);
+        if (conf & DMA2D)
+                bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
+        else
+                bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
 
         spin_unlock_irqrestore(&mdma_lock, flags);
 
         SSYNC();
 
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
-                if (bfin_read_MDMA_S0_CONFIG())
+        while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
+                if (bfin_read_MDMA_S_CONFIG())
                         continue;
                 else
                         return;
 
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
 
-        bfin_write_MDMA_S0_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
+        bfin_write_MDMA_S_CONFIG(0);
+        bfin_write_MDMA_D_CONFIG(0);
 }
 
 /**
@@ -448,8 +511,10 @@ static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
         }
         size >>= shift;
 
+#ifndef DMA_MMR_SIZE_32
         if (size > 0x10000)
                 conf |= DMA2D;
+#endif
 
         __dma_memcpy(dst, mod, src, mod, size, conf);
 
@@ -488,6 +553,9 @@ EXPORT_SYMBOL(dma_memcpy);
  */
 void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
 {
+#ifdef DMA_MMR_SIZE_32
+        _dma_memcpy(pdst, psrc, size);
+#else
         size_t bulk, rest;
 
         bulk = size & ~0xffff;
@@ -495,6 +563,7 @@ void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
         if (bulk)
                 _dma_memcpy(pdst, psrc, bulk);
         _dma_memcpy(pdst + bulk, psrc + bulk, rest);
+#endif
         return pdst;
 }
 EXPORT_SYMBOL(dma_memcpy_nocache);
@@ -514,14 +583,14 @@ void *safe_dma_memcpy(void *dst, const void *src, size_t size)
 }
 EXPORT_SYMBOL(safe_dma_memcpy);
 
-static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
+static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
                      u16 size, u16 dma_size)
 {
         blackfin_dcache_flush_range(buf, buf + len * size);
         __dma_memcpy(addr, 0, buf, size, len, dma_size);
 }
 
-static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
+static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
                     u16 size, u16 dma_size)
 {
         blackfin_dcache_invalidate_range(buf, buf + len * size);
@@ -529,7 +598,7 @@ static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
 }
 
 #define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
-void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
+void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
 { \
         _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
 } \
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 02796b88443d..c6e800998126 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -58,7 +58,7 @@ static struct gpio_port_t * const gpio_array[] = {
         (struct gpio_port_t *) FIO0_FLAG_D,
         (struct gpio_port_t *) FIO1_FLAG_D,
         (struct gpio_port_t *) FIO2_FLAG_D,
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x) 
         (struct gpio_port_t *)PORTA_FER,
         (struct gpio_port_t *)PORTB_FER,
         (struct gpio_port_t *)PORTC_FER,
@@ -66,6 +66,7 @@ static struct gpio_port_t * const gpio_array[] = {
         (struct gpio_port_t *)PORTE_FER,
         (struct gpio_port_t *)PORTF_FER,
         (struct gpio_port_t *)PORTG_FER,
+#elif defined(CONFIG_BF54x) 
         (struct gpio_port_t *)PORTH_FER,
         (struct gpio_port_t *)PORTI_FER,
         (struct gpio_port_t *)PORTJ_FER,
@@ -210,7 +211,7 @@ static void port_setup(unsigned gpio, unsigned short usage)
         else
                 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
         SSYNC();
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
         if (usage == GPIO_USAGE)
                 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
         else
@@ -299,7 +300,7 @@ static void portmux_setup(unsigned short per)
         pmux |= (function << offset);
         bfin_write_PORT_MUX(pmux);
 }
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 inline void portmux_setup(unsigned short per)
 {
         u16 ident = P_IDENT(per);
@@ -377,7 +378,7 @@ static int portmux_group_check(unsigned short per)
 }
 #endif
 
-#ifndef CONFIG_BF54x
+#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
 /***********************************************************
 *
 * FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -680,7 +681,7 @@ void bfin_gpio_pm_hibernate_restore(void)
 
 
 #endif
-#else /* CONFIG_BF54x */
+#else /* CONFIG_BF54x || CONFIG_BF60x */
 #ifdef CONFIG_PM
 
 int bfin_pm_standby_ctrl(unsigned ctrl)
@@ -726,7 +727,7 @@ unsigned short get_gpio_dir(unsigned gpio)
 }
 EXPORT_SYMBOL(get_gpio_dir);
 
-#endif /* CONFIG_BF54x */
+#endif /* CONFIG_BF54x || CONFIG_BF60x */
 
 /***********************************************************
 *
@@ -783,7 +784,7 @@ int peripheral_request(unsigned short per, const char *label)
                  * be requested and used by several drivers
                  */
 
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
                 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
 #else
                 if (!(per & P_MAYSHARE)) {
@@ -937,7 +938,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
                 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
                        " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
         }
-#ifndef CONFIG_BF54x
+#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
         else {  /* Reset POLAR setting when acquiring a gpio for the first time */
                 set_gpio_polar(gpio, 0);
         }
@@ -1110,7 +1111,7 @@ void bfin_gpio_irq_free(unsigned gpio)
 
 static inline void __bfin_gpio_direction_input(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
         gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
 #else
         gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
@@ -1138,13 +1139,13 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
 
 void bfin_gpio_irq_prepare(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
         unsigned long flags;
 #endif
 
         port_setup(gpio, GPIO_USAGE);
 
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
         flags = hard_local_irq_save();
         __bfin_gpio_direction_input(gpio);
         hard_local_irq_restore(flags);
@@ -1173,7 +1174,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
 
         gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
         gpio_set_value(gpio, value);
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
         gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
 #else
         gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
@@ -1188,7 +1189,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
 
 int bfin_gpio_get_value(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
         return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
 #else
         unsigned long flags;
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index 92f664826281..01232a13470d 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -105,6 +105,7 @@ DEFINE_SYSREG(seqstat, , );
 DEFINE_SYSREG(syscfg, , CSYNC());
 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
 
+#ifndef CONFIG_BF60x
 /*
  * CAN
  */
@@ -223,8 +224,10 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
         __DMA(CURR_DESC_PTR, curr_desc_ptr);
         __DMA(CURR_ADDR, curr_addr);
         __DMA(IRQ_STATUS, irq_status);
+#ifndef CONFIG_BF60x
         if (strcmp(pfx, "IMDMA") != 0)
                 __DMA(PERIPHERAL_MAP, peripheral_map);
+#endif
         __DMA(CURR_X_COUNT, curr_x_count);
         __DMA(CURR_Y_COUNT, curr_y_count);
 }
@@ -568,7 +571,7 @@ bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
 #endif
 }
 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
-
+#endif /* CONFIG_BF60x */
 /*
  * The actual debugfs generation
  */
@@ -740,7 +743,7 @@ static int __init bfin_debug_mmrs_init(void)
         D32(WPDACNT0);
         D32(WPDACNT1);
         D32(WPSTAT);
-
+#ifndef CONFIG_BF60x
         /* System MMRs */
 #ifdef ATAPI_CONTROL
         parent = debugfs_create_dir("atapi", top);
@@ -1873,7 +1876,7 @@ static int __init bfin_debug_mmrs_init(void)
 
         }
 #endif  /* BF54x */
-
+#endif /* CONFIG_BF60x */
         debug_mmrs_dentry = top;
 
         return 0;
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index c0f4fe287eb6..2e3994b20169 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -95,7 +95,9 @@ void cpu_idle(void)
                         idle();
                 rcu_idle_exit();
                 tick_nohz_idle_exit();
-                schedule_preempt_disabled();
+                preempt_enable_no_resched();
+                schedule();
+                preempt_disable();
         }
 }
 
@@ -329,12 +331,16 @@ int in_mem_const(unsigned long addr, unsigned long size,
 {
         return in_mem_const_off(addr, size, 0, const_addr, const_size);
 }
+#ifdef CONFIG_BF60x
+#define ASYNC_ENABLED(bnum, bctlnum)    1
+#else
 #define ASYNC_ENABLED(bnum, bctlnum) \
 ({ \
         (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
         bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
         1; \
 })
+#endif
 /*
  * We can't read EBIU banks that aren't enabled or we end up hanging
  * on the access to the async space.  Make sure we validate accesses
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index b0434f89e8de..5272e6eefd92 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -22,6 +22,7 @@
 __attribute__ ((__l1_text__, __noreturn__))
 static void bfin_reset(void)
 {
+#ifndef CONFIG_BF60x
         if (!ANOMALY_05000353 && !ANOMALY_05000386)
                 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
 
@@ -57,7 +58,6 @@ static void bfin_reset(void)
         if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
                 bfin_read_SWRST();
 #endif
-
         /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
          * though as the System state is all reset now.
          */
@@ -72,6 +72,10 @@ static void bfin_reset(void)
         while (1)
                 /* Issue core reset */
                 asm("raise 1");
+#else
+        while (1)
+                bfin_write_RCU0_CTL(0x1);
+#endif
 }
 
 __attribute__((weak))
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 2ad747e909fb..c113cfa459a7 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -25,6 +25,7 @@
 #include <asm/cacheflush.h>
 #include <asm/blackfin.h>
 #include <asm/cplbinit.h>
+#include <asm/clocks.h>
 #include <asm/div64.h>
 #include <asm/cpu.h>
 #include <asm/fixed_code.h>
@@ -550,7 +551,6 @@ static __init void memory_setup(void)
 {
 #ifdef CONFIG_MTD_UCLINUX
         unsigned long mtd_phys = 0;
-        unsigned long n;
 #endif
         unsigned long max_mem;
 
@@ -594,9 +594,9 @@ static __init void memory_setup(void)
         mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
 
 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
-        n = ext2_image_size((void *)(mtd_phys + 0x400));
-        if (n)
-                mtd_size = PAGE_ALIGN(n * 1024);
+        if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
+                mtd_size =
+                    PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
 # endif
 
 # if defined(CONFIG_CRAMFS)
@@ -612,7 +612,8 @@ static __init void memory_setup(void)
 
                 /* ROM_FS is XIP, so if we found it, we need to limit memory */
                 if (memory_end > max_mem) {
-                        pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
+                        pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
+                                (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
                         memory_end = max_mem;
                 }
         }
@@ -642,7 +643,8 @@ static __init void memory_setup(void)
          * doesn't exist, or we don't need to - then dont.
          */
         if (memory_end > max_mem) {
-                pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
+                pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
+                                (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
                 memory_end = max_mem;
         }
 
@@ -661,8 +663,8 @@ static __init void memory_setup(void)
         init_mm.end_data = (unsigned long)_edata;
         init_mm.brk = (unsigned long)0;
 
-        printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
-        printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
+        printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
+        printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
 
         printk(KERN_INFO "Memory map:\n"
                "  fixedcode = 0x%p-0x%p\n"
@@ -705,7 +707,7 @@ void __init find_min_max_pfn(void)
         int i;
 
         max_pfn = 0;
-        min_low_pfn = memory_end;
+        min_low_pfn = PFN_DOWN(memory_end);
 
         for (i = 0; i < bfin_memmap.nr_map; i++) {
                 unsigned long start, end;
@@ -748,8 +750,7 @@ static __init void setup_bootmem_allocator(void)
         /* pfn of the first usable page frame after kernel image*/
         if (min_low_pfn < memory_start >> PAGE_SHIFT)
                 min_low_pfn = memory_start >> PAGE_SHIFT;
-
-        start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
+        start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
         end_pfn = memory_end >> PAGE_SHIFT;
 
         /*
@@ -794,8 +795,8 @@ static __init void setup_bootmem_allocator(void)
         }
 
         /* reserve memory before memory_start, including bootmap */
-        reserve_bootmem(PAGE_OFFSET,
-                memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
+        reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
+                memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
                 BOOTMEM_DEFAULT);
 }
 
@@ -844,13 +845,40 @@ static inline int __init get_mem_size(void)
                 break;
         }
         switch (ddrctl & 0x30000) {
-                case DEVWD_4:  ret *= 2;
-                case DEVWD_8:  ret *= 2;
-                case DEVWD_16: break;
+        case DEVWD_4:
+                ret *= 2;
+        case DEVWD_8:
+                ret *= 2;
+        case DEVWD_16:
+                break;
         }
         if ((ddrctl & 0xc000) == 0x4000)
                 ret *= 2;
         return ret;
+#elif defined(CONFIG_BF60x)
+        u32 ddrctl = bfin_read_DDR0_CFG();
+        int ret;
+        switch (ddrctl & 0xf00) {
+        case DEVSZ_64:
+                ret = 64 / 8;
+                break;
+        case DEVSZ_128:
+                ret = 128 / 8;
+                break;
+        case DEVSZ_256:
+                ret = 256 / 8;
+                break;
+        case DEVSZ_512:
+                ret = 512 / 8;
+                break;
+        case DEVSZ_1G:
+                ret = 1024 / 8;
+                break;
+        case DEVSZ_2G:
+                ret = 2048 / 8;
+                break;
+        }
+        return ret;
 #endif
         BUG();
 }
@@ -864,12 +892,14 @@ void __init setup_arch(char **cmdline_p)
 {
         u32 mmr;
         unsigned long sclk, cclk;
+        struct clk *clk;
 
         native_machine_early_platform_add_devices();
 
         enable_shadow_console();
 
         /* Check to make sure we are running on the right processor */
+        mmr =  bfin_cpuid();
         if (unlikely(CPUID != bfin_cpuid()))
                 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
                         CPU, bfin_cpuid(), bfin_revid());
@@ -890,6 +920,10 @@ void __init setup_arch(char **cmdline_p)
 
         memset(&bfin_memmap, 0, sizeof(bfin_memmap));
 
+#ifdef CONFIG_BF60x
+        /* Should init clock device before parse command early */
+        clk_init();
+#endif
         /* If the user does not specify things on the command line, use
          * what the bootloader set things up as
          */
@@ -904,6 +938,7 @@ void __init setup_arch(char **cmdline_p)
 
         memory_setup();
 
+#ifndef CONFIG_BF60x
         /* Initialize Async memory banks */
         bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
         bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
@@ -913,6 +948,7 @@ void __init setup_arch(char **cmdline_p)
         bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
         bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
 #endif
+#endif
 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
         bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
         bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
@@ -921,8 +957,24 @@ void __init setup_arch(char **cmdline_p)
                                         ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
 #endif
 
+#ifdef CONFIG_BF60x
+        clk = clk_get(NULL, "CCLK");
+        if (!IS_ERR(clk)) {
+                cclk = clk_get_rate(clk);
+                clk_put(clk);
+        } else
+                cclk = 0;
+
+        clk = clk_get(NULL, "SCLK0");
+        if (!IS_ERR(clk)) {
+                sclk = clk_get_rate(clk);
+                clk_put(clk);
+        } else
+                sclk = 0;
+#else
         cclk = get_cclk();
         sclk = get_sclk();
+#endif
 
         if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
                 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
@@ -938,7 +990,7 @@ void __init setup_arch(char **cmdline_p)
         printk(KERN_INFO "Hardware Trace %s and %sabled\n",
                 (mmr & 0x1) ? "active" : "off",
                 (mmr & 0x2) ? "en" : "dis");
-
+#ifndef CONFIG_BF60x
         mmr = bfin_read_SYSCR();
         printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
 
@@ -980,7 +1032,7 @@ void __init setup_arch(char **cmdline_p)
                 printk(KERN_INFO "Recovering from Watchdog event\n");
         else if (_bfin_swrst & RESET_SOFTWARE)
                 printk(KERN_NOTICE "Reset caused by Software reset\n");
-
+#endif
         printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
         if (bfin_compiled_revid() == 0xffff)
                 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
@@ -1060,10 +1112,12 @@ subsys_initcall(topology_init);
 
 /* Get the input clock frequency */
 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
+#ifndef CONFIG_BF60x
 static u_long get_clkin_hz(void)
 {
         return cached_clkin_hz;
 }
+#endif
 static int __init early_init_clkin_hz(char *buf)
 {
         cached_clkin_hz = simple_strtoul(buf, NULL, 0);
@@ -1075,6 +1129,7 @@ static int __init early_init_clkin_hz(char *buf)
 }
 early_param("clkin_hz=", early_init_clkin_hz);
 
+#ifndef CONFIG_BF60x
 /* Get the voltage input multiplier */
 static u_long get_vco(void)
 {
@@ -1097,10 +1152,23 @@ static u_long get_vco(void)
         cached_vco *= msel;
         return cached_vco;
 }
+#endif
 
 /* Get the Core clock */
 u_long get_cclk(void)
 {
+#ifdef CONFIG_BF60x
+        struct clk *cclk;
+        u_long cclk_rate;
+
+        cclk = clk_get(NULL, "CCLK");
+        if (IS_ERR(cclk))
+                return 0;
+
+        cclk_rate = clk_get_rate(cclk);
+        clk_put(cclk);
+        return cclk_rate;
+#else
         static u_long cached_cclk_pll_div, cached_cclk;
         u_long csel, ssel;
 
@@ -1120,12 +1188,66 @@ u_long get_cclk(void)
         else
                 cached_cclk = get_vco() >> csel;
         return cached_cclk;
+#endif
 }
 EXPORT_SYMBOL(get_cclk);
 
+#ifdef CONFIG_BF60x
+/* Get the bf60x clock of SCLK0 domain */
+u_long get_sclk0(void)
+{
+        struct clk *sclk0;
+        u_long sclk0_rate;
+
+        sclk0 = clk_get(NULL, "SCLK0");
+        if (IS_ERR(sclk0))
+                return 0;
+
+        sclk0_rate = clk_get_rate(sclk0);
+        clk_put(sclk0);
+        return sclk0_rate;
+}
+EXPORT_SYMBOL(get_sclk0);
+
+/* Get the bf60x clock of SCLK1 domain */
+u_long get_sclk1(void)
+{
+        struct clk *sclk1;
+        u_long sclk1_rate;
+
+        sclk1 = clk_get(NULL, "SCLK1");
+        if (IS_ERR(sclk1))
+                return 0;
+
+        sclk1_rate = clk_get_rate(sclk1);
+        clk_put(sclk1);
+        return sclk1_rate;
+}
+EXPORT_SYMBOL(get_sclk1);
+
+/* Get the bf60x DRAM clock */
+u_long get_dclk(void)
+{
+        struct clk *dclk;
+        u_long dclk_rate;
+
+        dclk = clk_get(NULL, "DCLK");
+        if (IS_ERR(dclk))
+                return 0;
+
+        dclk_rate = clk_get_rate(dclk);
+        clk_put(dclk);
+        return dclk_rate;
+}
+EXPORT_SYMBOL(get_dclk);
+#endif
+
 /* Get the System clock */
 u_long get_sclk(void)
 {
+#ifdef CONFIG_BF60x
+        return get_sclk0();
+#else
         static u_long cached_sclk;
         u_long ssel;
 
@@ -1146,6 +1268,7 @@ u_long get_sclk(void)
 
         cached_sclk = get_vco() / ssel;
         return cached_sclk;
+#endif
 }
 EXPORT_SYMBOL(get_sclk);
 
diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c
index 557e9fef406a..aeb8343eeb03 100644
--- a/arch/blackfin/kernel/shadow_console.c
+++ b/arch/blackfin/kernel/shadow_console.c
@@ -15,9 +15,9 @@
 #include <asm/irq_handler.h>
 #include <asm/early_printk.h>
 
-#define SHADOW_CONSOLE_START            (0x500)
-#define SHADOW_CONSOLE_END              (0x1000)
-#define SHADOW_CONSOLE_MAGIC_LOC        (0x4F0)
+#define SHADOW_CONSOLE_START            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
+#define SHADOW_CONSOLE_END              (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
+#define SHADOW_CONSOLE_MAGIC_LOC        (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
 #define SHADOW_CONSOLE_MAGIC            (0xDEADBEEF)
 
 static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;