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-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c29
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c6
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c23
-rw-r--r--arch/blackfin/kernel/process.c14
-rw-r--r--arch/blackfin/kernel/ptrace.c1
-rw-r--r--arch/blackfin/kernel/setup.c44
-rw-r--r--arch/blackfin/kernel/sys_bfin.c1
-rw-r--r--arch/blackfin/kernel/traps.c9
8 files changed, 65 insertions, 62 deletions
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index e0bf8cc06907..9f9b82816652 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -253,32 +253,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
253 BUG_ON(src % 4); 253 BUG_ON(src % 4);
254 BUG_ON(size % 4); 254 BUG_ON(size % 4);
255 255
256 /* Force a sync in case a previous config reset on this channel
257 * occurred. This is needed so subsequent writes to DMA registers
258 * are not spuriously lost/corrupted.
259 */
260 __builtin_bfin_ssync();
261
262 src_ch = 0; 256 src_ch = 0;
263 /* Find an avalible memDMA channel */ 257 /* Find an avalible memDMA channel */
264 while (1) { 258 while (1) {
265 if (!src_ch || src_ch == (struct dma_register *)MDMA_S1_NEXT_DESC_PTR) { 259 if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
266 dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
267 src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
268 } else {
269 dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; 260 dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
270 src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; 261 src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
262 } else {
263 dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
264 src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
271 } 265 }
272 266
273 if (!bfin_read16(&src_ch->cfg)) { 267 if (!bfin_read16(&src_ch->cfg))
268 break;
269 else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
270 bfin_write16(&src_ch->cfg, 0);
274 break; 271 break;
275 } else {
276 if (bfin_read16(&src_ch->irq_status) & DMA_DONE)
277 bfin_write16(&src_ch->cfg, 0);
278 } 272 }
279
280 } 273 }
281 274
275 /* Force a sync in case a previous config reset on this channel
276 * occurred. This is needed so subsequent writes to DMA registers
277 * are not spuriously lost/corrupted.
278 */
279 __builtin_bfin_ssync();
280
282 /* Destination */ 281 /* Destination */
283 bfin_write32(&dst_ch->start_addr, dst); 282 bfin_write32(&dst_ch->start_addr, dst);
284 bfin_write16(&dst_ch->x_count, size >> 2); 283 bfin_write16(&dst_ch->x_count, size >> 2);
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index beffa00a93c3..6b9446271371 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -686,14 +686,12 @@ void bfin_gpio_pm_hibernate_restore(void)
686 *port_fer[bank] = gpio_bank_saved[bank].fer; 686 *port_fer[bank] = gpio_bank_saved[bank].fer;
687#endif 687#endif
688 gpio_array[bank]->inen = gpio_bank_saved[bank].inen; 688 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
689 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
690 & gpio_bank_saved[bank].dir;
689 gpio_array[bank]->dir = gpio_bank_saved[bank].dir; 691 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
690 gpio_array[bank]->polar = gpio_bank_saved[bank].polar; 692 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
691 gpio_array[bank]->edge = gpio_bank_saved[bank].edge; 693 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
692 gpio_array[bank]->both = gpio_bank_saved[bank].both; 694 gpio_array[bank]->both = gpio_bank_saved[bank].both;
693
694 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
695 | gpio_bank_saved[bank].dir;
696
697 gpio_array[bank]->maska = gpio_bank_saved[bank].maska; 695 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
698 } 696 }
699 AWA_DUMMY_READ(maska); 697 AWA_DUMMY_READ(maska);
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index d6c067782e63..685f160a5a36 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
72 } 72 }
73 73
74 /* Cover L1 memory. One 4M area for code and data each is enough. */ 74 /* Cover L1 memory. One 4M area for code and data each is enough. */
75 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { 75 if (cpu == 0) {
76 d_tbl[i_d].addr = L1_DATA_A_START; 76 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
77 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; 77 d_tbl[i_d].addr = L1_DATA_A_START;
78 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
79 }
80 i_tbl[i_i].addr = L1_CODE_START;
81 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
78 } 82 }
79 i_tbl[i_i].addr = L1_CODE_START; 83#ifdef CONFIG_SMP
80 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; 84 else {
81 85 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
86 d_tbl[i_d].addr = COREB_L1_DATA_A_START;
87 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
88 }
89 i_tbl[i_i].addr = COREB_L1_CODE_START;
90 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
91 }
92#endif
82 first_switched_dcplb = i_d; 93 first_switched_dcplb = i_d;
83 first_switched_icplb = i_i; 94 first_switched_icplb = i_i;
84 95
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 79cad0ac5892..9da36bab7ccb 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -361,7 +361,7 @@ static inline
361int in_mem_const(unsigned long addr, unsigned long size, 361int in_mem_const(unsigned long addr, unsigned long size,
362 unsigned long const_addr, unsigned long const_size) 362 unsigned long const_addr, unsigned long const_size)
363{ 363{
364 return in_mem_const_off(addr, 0, size, const_addr, const_size); 364 return in_mem_const_off(addr, size, 0, const_addr, const_size);
365} 365}
366#define IN_ASYNC(bnum, bctlnum) \ 366#define IN_ASYNC(bnum, bctlnum) \
367({ \ 367({ \
@@ -390,13 +390,13 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size)
390 if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) 390 if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
391 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 391 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
392#ifdef COREB_L1_CODE_START 392#ifdef COREB_L1_CODE_START
393 if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) 393 if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
394 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; 394 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
395 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) 395 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
396 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; 396 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
397 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) 397 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
398 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 398 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
399 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) 399 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
400 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; 400 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
401#endif 401#endif
402 if (in_mem_const(addr, size, L2_START, L2_LENGTH)) 402 if (in_mem_const(addr, size, L2_START, L2_LENGTH))
@@ -472,13 +472,13 @@ int _access_ok(unsigned long addr, unsigned long size)
472 if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) 472 if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
473 return 1; 473 return 1;
474#ifdef COREB_L1_CODE_START 474#ifdef COREB_L1_CODE_START
475 if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) 475 if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
476 return 1; 476 return 1;
477 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) 477 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
478 return 1; 478 return 1;
479 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) 479 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
480 return 1; 480 return 1;
481 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) 481 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
482 return 1; 482 return 1;
483#endif 483#endif
484 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) 484 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index d76618db50df..6a387eec6b65 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -31,7 +31,6 @@
31#include <linux/sched.h> 31#include <linux/sched.h>
32#include <linux/mm.h> 32#include <linux/mm.h>
33#include <linux/smp.h> 33#include <linux/smp.h>
34#include <linux/smp_lock.h>
35#include <linux/errno.h> 34#include <linux/errno.h>
36#include <linux/ptrace.h> 35#include <linux/ptrace.h>
37#include <linux/user.h> 36#include <linux/user.h>
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 6136c33e919f..6225edae488e 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -168,7 +168,6 @@ void __cpuinit bfin_setup_cpudata(unsigned int cpu)
168 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); 168 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
169 169
170 cpudata->idle = current; 170 cpudata->idle = current;
171 cpudata->loops_per_jiffy = loops_per_jiffy;
172 cpudata->imemctl = bfin_read_IMEM_CONTROL(); 171 cpudata->imemctl = bfin_read_IMEM_CONTROL();
173 cpudata->dmemctl = bfin_read_DMEM_CONTROL(); 172 cpudata->dmemctl = bfin_read_DMEM_CONTROL();
174} 173}
@@ -568,17 +567,23 @@ static __init void memory_setup(void)
568# endif /* ANOMALY_05000263 */ 567# endif /* ANOMALY_05000263 */
569# endif /* CONFIG_ROMFS_FS */ 568# endif /* CONFIG_ROMFS_FS */
570 569
571 memory_end -= mtd_size; 570 /* Since the default MTD_UCLINUX has no magic number, we just blindly
572 571 * read 8 past the end of the kernel's image, and look at it.
573 if (mtd_size == 0) { 572 * When no image is attached, mtd_size is set to a random number
574 console_init(); 573 * Do some basic sanity checks before operating on things
575 panic("Don't boot kernel without rootfs attached."); 574 */
575 if (mtd_size == 0 || memory_end <= mtd_size) {
576 pr_emerg("Could not find valid ram mtd attached.\n");
577 } else {
578 memory_end -= mtd_size;
579
580 /* Relocate MTD image to the top of memory after the uncached memory area */
581 uclinux_ram_map.phys = memory_mtd_start = memory_end;
582 uclinux_ram_map.size = mtd_size;
583 pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
584 _end, mtd_size, (void *)memory_mtd_start);
585 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
576 } 586 }
577
578 /* Relocate MTD image to the top of memory after the uncached memory area */
579 uclinux_ram_map.phys = memory_mtd_start = memory_end;
580 uclinux_ram_map.size = mtd_size;
581 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
582#endif /* CONFIG_MTD_UCLINUX */ 587#endif /* CONFIG_MTD_UCLINUX */
583 588
584#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) 589#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
@@ -868,13 +873,6 @@ void __init setup_arch(char **cmdline_p)
868 else 873 else
869 printk(KERN_CONT "and Disabled\n"); 874 printk(KERN_CONT "and Disabled\n");
870 875
871#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
872 /* we need to initialize the Flashrom device here since we might
873 * do things with flash early on in the boot
874 */
875 flash_probe();
876#endif
877
878 printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF); 876 printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
879 877
880 /* Newer parts mirror SWRST bits in SYSCR */ 878 /* Newer parts mirror SWRST bits in SYSCR */
@@ -938,10 +936,6 @@ void __init setup_arch(char **cmdline_p)
938 CPU, bfin_revid()); 936 CPU, bfin_revid());
939 } 937 }
940 938
941 /* We can't run on BF548-0.1 due to ANOMALY 05000448 */
942 if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
943 panic("You can't run on this processor due to 05000448");
944
945 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); 939 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
946 940
947 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", 941 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
@@ -1164,9 +1158,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1164 sclk/1000000, sclk%1000000); 1158 sclk/1000000, sclk%1000000);
1165 seq_printf(m, "bogomips\t: %lu.%02lu\n" 1159 seq_printf(m, "bogomips\t: %lu.%02lu\n"
1166 "Calibration\t: %lu loops\n", 1160 "Calibration\t: %lu loops\n",
1167 (cpudata->loops_per_jiffy * HZ) / 500000, 1161 (loops_per_jiffy * HZ) / 500000,
1168 ((cpudata->loops_per_jiffy * HZ) / 5000) % 100, 1162 ((loops_per_jiffy * HZ) / 5000) % 100,
1169 (cpudata->loops_per_jiffy * HZ)); 1163 (loops_per_jiffy * HZ));
1170 1164
1171 /* Check Cache configutation */ 1165 /* Check Cache configutation */
1172 switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { 1166 switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index a8f1329c15a4..3da60fb13ce4 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -29,7 +29,6 @@
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */ 30 */
31 31
32#include <linux/smp_lock.h>
33#include <linux/spinlock.h> 32#include <linux/spinlock.h>
34#include <linux/sem.h> 33#include <linux/sem.h>
35#include <linux/msg.h> 34#include <linux/msg.h>
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 8a1caf2bb5b9..bf2b2d1f8ae5 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -570,11 +570,12 @@ asmlinkage void trap_c(struct pt_regs *fp)
570 if (kernel_mode_regs(fp) || (current && !current->mm)) { 570 if (kernel_mode_regs(fp) || (current && !current->mm)) {
571 console_verbose(); 571 console_verbose();
572 oops_in_progress = 1; 572 oops_in_progress = 1;
573 if (strerror)
574 verbose_printk(strerror);
575 } 573 }
576 574
577 if (sig != SIGTRAP) { 575 if (sig != SIGTRAP) {
576 if (strerror)
577 verbose_printk(strerror);
578
578 dump_bfin_process(fp); 579 dump_bfin_process(fp);
579 dump_bfin_mem(fp); 580 dump_bfin_mem(fp);
580 show_regs(fp); 581 show_regs(fp);
@@ -619,7 +620,9 @@ asmlinkage void trap_c(struct pt_regs *fp)
619 force_sig_info(sig, &info, current); 620 force_sig_info(sig, &info, current);
620 } 621 }
621 622
622 if (ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) 623 if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) ||
624 (ANOMALY_05000281 && trapnr == VEC_HWERR) ||
625 (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL)))
623 fp->pc = SAFE_USER_INSTRUCTION; 626 fp->pc = SAFE_USER_INSTRUCTION;
624 627
625 traps_done: 628 traps_done: