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Diffstat (limited to 'arch/blackfin/kernel/setup.c')
-rw-r--r--arch/blackfin/kernel/setup.c100
1 files changed, 61 insertions, 39 deletions
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 8dcd76e87ed5..34fbf93cc118 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -498,7 +498,7 @@ EXPORT_SYMBOL(get_sclk);
498 */ 498 */
499static int show_cpuinfo(struct seq_file *m, void *v) 499static int show_cpuinfo(struct seq_file *m, void *v)
500{ 500{
501 char *cpu, *mmu, *fpu, *name; 501 char *cpu, *mmu, *fpu, *name, vendor[20], cache[30];
502 uint32_t revid; 502 uint32_t revid;
503 503
504 u_long cclk = 0, sclk = 0; 504 u_long cclk = 0, sclk = 0;
@@ -513,65 +513,78 @@ static int show_cpuinfo(struct seq_file *m, void *v)
513 cclk = get_cclk(); 513 cclk = get_cclk();
514 sclk = get_sclk(); 514 sclk = get_sclk();
515 515
516 seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n" 516 switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
517 "MMU:\t\t%s\n" 517 case(0xca):
518 "FPU:\t\t%s\n" 518 strcpy(vendor, "AnalogDevices");
519 "Core Clock:\t%9lu Hz\n" 519 break;
520 "System Clock:\t%9lu Hz\n" 520 default:
521 "BogoMips:\t%lu.%02lu\n" 521 strcpy(vendor, "unknown");
522 "Calibration:\t%lu loops\n", 522 }
523 cpu, revid, mmu, fpu,
524 cclk,
525 sclk,
526 (loops_per_jiffy * HZ) / 500000,
527 ((loops_per_jiffy * HZ) / 5000) % 100,
528 (loops_per_jiffy * HZ));
529 seq_printf(m, "Board Name:\t%s\n", name);
530 seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
531 seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
532 if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
533 seq_printf(m, "I-CACHE:\tON\n");
534 else
535 seq_printf(m, "I-CACHE:\tOFF\n");
536 if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
537 seq_printf(m, "D-CACHE:\tON"
538#if defined CONFIG_BFIN_WB
539 " (write-back)"
540#elif defined CONFIG_BFIN_WT
541 " (write-through)"
542#endif
543 "\n");
544 else
545 seq_printf(m, "D-CACHE:\tOFF\n");
546
547 523
524 seq_printf(m, "processor\t: %d\n"
525 "vendor_id\t: %s\n"
526 "cpu family\t: 0x%x\n"
527 "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK)\n"
528 "stepping\t: %d\n",
529 0,
530 vendor,
531 (bfin_read_CHIPID() & CHIPID_FAMILY),
532 cpu, cclk/1000000, sclk/1000000,
533 revid);
534
535 seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
536 cclk/1000000, cclk%1000000,
537 sclk/1000000, sclk%1000000);
538 seq_printf(m, "bogomips\t: %lu.%02lu\n"
539 "Calibration\t: %lu loops\n",
540 (loops_per_jiffy * HZ) / 500000,
541 ((loops_per_jiffy * HZ) / 5000) % 100,
542 (loops_per_jiffy * HZ));
543
544 /* Check Cache configutation */
548 switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) { 545 switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
549 case ACACHE_BSRAM: 546 case ACACHE_BSRAM:
550 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n"); 547 strcpy(cache, "dbank-A/B\t: cache/sram");
551 dcache_size = 16; 548 dcache_size = 16;
552 dsup_banks = 1; 549 dsup_banks = 1;
553 break; 550 break;
554 case ACACHE_BCACHE: 551 case ACACHE_BCACHE:
555 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n"); 552 strcpy(cache, "dbank-A/B\t: cache/cache");
556 dcache_size = 32; 553 dcache_size = 32;
557 dsup_banks = 2; 554 dsup_banks = 2;
558 break; 555 break;
559 case ASRAM_BSRAM: 556 case ASRAM_BSRAM:
560 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n"); 557 strcpy(cache, "dbank-A/B\t: sram/sram");
561 dcache_size = 0; 558 dcache_size = 0;
562 dsup_banks = 0; 559 dsup_banks = 0;
563 break; 560 break;
564 default: 561 default:
562 strcpy(cache, "unknown");
563 dcache_size = 0;
564 dsup_banks = 0;
565 break; 565 break;
566 } 566 }
567 567
568 /* Is it turned on? */
569 if (!((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE)))
570 dcache_size = 0;
568 571
569 seq_printf(m, "I-CACHE Size:\t%dKB\n", BFIN_ICACHESIZE / 1024); 572 seq_printf(m, "cache size\t: %d KB(L1 icache) "
570 seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size); 573 "%d KB(L1 dcache-%s) %d KB(L2 cache)\n",
571 seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n", 574 BFIN_ICACHESIZE / 1024, dcache_size,
575#if defined CONFIG_BFIN_WB
576 "wb"
577#elif defined CONFIG_BFIN_WT
578 "wt"
579#endif
580 , 0);
581
582 seq_printf(m, "%s\n", cache);
583
584 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
572 BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES); 585 BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
573 seq_printf(m, 586 seq_printf(m,
574 "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", 587 "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
575 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, 588 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
576 BFIN_DLINES); 589 BFIN_DLINES);
577#ifdef CONFIG_BFIN_ICACHE_LOCK 590#ifdef CONFIG_BFIN_ICACHE_LOCK
@@ -625,6 +638,15 @@ static int show_cpuinfo(struct seq_file *m, void *v)
625 seq_printf(m, "No Ways are locked\n"); 638 seq_printf(m, "No Ways are locked\n");
626 } 639 }
627#endif 640#endif
641
642 seq_printf(m, "board name\t: %s\n", name);
643 seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
644 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
645 seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
646 ((int)memory_end - (int)_stext) >> 10,
647 _stext,
648 (void *)memory_end);
649
628 return 0; 650 return 0;
629} 651}
630 652