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-rw-r--r--arch/blackfin/kernel/setup.c248
1 files changed, 128 insertions, 120 deletions
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 02dc74301920..a24fa1ab802b 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -61,7 +61,7 @@ EXPORT_SYMBOL(memory_mtd_start);
61EXPORT_SYMBOL(mtd_size); 61EXPORT_SYMBOL(mtd_size);
62#endif 62#endif
63 63
64char command_line[COMMAND_LINE_SIZE]; 64char __initdata command_line[COMMAND_LINE_SIZE];
65 65
66#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) 66#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67static void generate_cpl_tables(void); 67static void generate_cpl_tables(void);
@@ -90,7 +90,7 @@ void __init bf53x_cache_init(void)
90#endif 90#endif
91} 91}
92 92
93void bf53x_relocate_l1_mem(void) 93void __init bf53x_relocate_l1_mem(void)
94{ 94{
95 unsigned long l1_code_length; 95 unsigned long l1_code_length;
96 unsigned long l1_data_a_length; 96 unsigned long l1_data_a_length;
@@ -205,7 +205,6 @@ void __init setup_arch(char **cmdline_p)
205#endif 205#endif
206 206
207#if defined(CONFIG_CMDLINE_BOOL) 207#if defined(CONFIG_CMDLINE_BOOL)
208 memset(command_line, 0, sizeof(command_line));
209 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line)); 208 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
210 command_line[sizeof(command_line) - 1] = 0; 209 command_line[sizeof(command_line) - 1] = 0;
211#endif 210#endif
@@ -213,7 +212,7 @@ void __init setup_arch(char **cmdline_p)
213 /* Keep a copy of command line */ 212 /* Keep a copy of command line */
214 *cmdline_p = &command_line[0]; 213 *cmdline_p = &command_line[0];
215 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); 214 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
216 boot_command_line[COMMAND_LINE_SIZE - 1] = 0; 215 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
217 216
218 /* setup memory defaults from the user config */ 217 /* setup memory defaults from the user config */
219 physical_mem_end = 0; 218 physical_mem_end = 0;
@@ -411,7 +410,7 @@ static int __init topology_init(void)
411subsys_initcall(topology_init); 410subsys_initcall(topology_init);
412 411
413#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) 412#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
414u16 lock_kernel_check(u32 start, u32 end) 413static u16 __init lock_kernel_check(u32 start, u32 end)
415{ 414{
416 if ((start <= (u32) _stext && end >= (u32) _end) 415 if ((start <= (u32) _stext && end >= (u32) _end)
417 || (start >= (u32) _stext && end <= (u32) _end)) 416 || (start >= (u32) _stext && end <= (u32) _end))
@@ -471,6 +470,67 @@ close_cplbtab(struct cplb_tab *table)
471 return 0; 470 return 0;
472} 471}
473 472
473/* helper function */
474static void __fill_code_cplbtab(struct cplb_tab *t, int i,
475 u32 a_start, u32 a_end)
476{
477 if (cplb_data[i].psize) {
478 fill_cplbtab(t,
479 cplb_data[i].start,
480 cplb_data[i].end,
481 cplb_data[i].psize,
482 cplb_data[i].i_conf);
483 } else {
484#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
485 if (i == SDRAM_KERN) {
486 fill_cplbtab(t,
487 cplb_data[i].start,
488 cplb_data[i].end,
489 SIZE_4M,
490 cplb_data[i].i_conf);
491 } else {
492#endif
493 fill_cplbtab(t,
494 cplb_data[i].start,
495 a_start,
496 SIZE_1M,
497 cplb_data[i].i_conf);
498 fill_cplbtab(t,
499 a_start,
500 a_end,
501 SIZE_4M,
502 cplb_data[i].i_conf);
503 fill_cplbtab(t, a_end,
504 cplb_data[i].end,
505 SIZE_1M,
506 cplb_data[i].i_conf);
507 }
508 }
509}
510
511static void __fill_data_cplbtab(struct cplb_tab *t, int i,
512 u32 a_start, u32 a_end)
513{
514 if (cplb_data[i].psize) {
515 fill_cplbtab(t,
516 cplb_data[i].start,
517 cplb_data[i].end,
518 cplb_data[i].psize,
519 cplb_data[i].d_conf);
520 } else {
521 fill_cplbtab(t,
522 cplb_data[i].start,
523 a_start, SIZE_1M,
524 cplb_data[i].d_conf);
525 fill_cplbtab(t, a_start,
526 a_end, SIZE_4M,
527 cplb_data[i].d_conf);
528 fill_cplbtab(t, a_end,
529 cplb_data[i].end,
530 SIZE_1M,
531 cplb_data[i].d_conf);
532 }
533}
474static void __init generate_cpl_tables(void) 534static void __init generate_cpl_tables(void)
475{ 535{
476 536
@@ -540,130 +600,78 @@ static void __init generate_cpl_tables(void)
540 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; 600 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
541 601
542 for (i = ZERO_P; i <= L2_MEM; i++) { 602 for (i = ZERO_P; i <= L2_MEM; i++) {
603 if (!cplb_data[i].valid)
604 continue;
543 605
544 if (cplb_data[i].valid) { 606 as_1m = cplb_data[i].start % SIZE_1M;
545 607
546 as_1m = cplb_data[i].start % SIZE_1M; 608 /*
609 * We need to make sure all sections are properly 1M aligned
610 * However between Kernel Memory and the Kernel mtd section,
611 * depending on the rootfs size, there can be overlapping
612 * memory areas.
613 */
547 614
548 /* We need to make sure all sections are properly 1M aligned 615 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
549 * However between Kernel Memory and the Kernel mtd section, depending on the
550 * rootfs size, there can be overlapping memory areas.
551 */
552
553 if (as_1m && i!=L1I_MEM && i!=L1D_MEM) {
554#ifdef CONFIG_MTD_UCLINUX 616#ifdef CONFIG_MTD_UCLINUX
555 if (i == SDRAM_RAM_MTD) { 617 if (i == SDRAM_RAM_MTD) {
556 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start) 618 if ((cplb_data[SDRAM_KERN].end + 1) >
557 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M; 619 cplb_data[SDRAM_RAM_MTD].start)
558 else 620 cplb_data[SDRAM_RAM_MTD].start =
559 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)); 621 (cplb_data[i].start &
560 } else 622 (-2*SIZE_1M)) + SIZE_1M;
623 else
624 cplb_data[SDRAM_RAM_MTD].start =
625 (cplb_data[i].start &
626 (-2*SIZE_1M));
627 } else
561#endif 628#endif
562 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n", 629 printk(KERN_WARNING
563 cplb_data[i].name, cplb_data[i].start); 630 "Unaligned Start of %s at 0x%X\n",
564 } 631 cplb_data[i].name, cplb_data[i].start);
632 }
565 633
566 as = cplb_data[i].start % SIZE_4M; 634 as = cplb_data[i].start % SIZE_4M;
567 ae = cplb_data[i].end % SIZE_4M; 635 ae = cplb_data[i].end % SIZE_4M;
568
569 if (as)
570 a_start = cplb_data[i].start + (SIZE_4M - (as));
571 else
572 a_start = cplb_data[i].start;
573
574 a_end = cplb_data[i].end - ae;
575
576 for (j = INITIAL_T; j <= SWITCH_T; j++) {
577
578 switch (j) {
579 case INITIAL_T:
580 if (cplb_data[i].attr & INITIAL_T) {
581 t_i = &cplb.init_i;
582 t_d = &cplb.init_d;
583 process = 1;
584 } else
585 process = 0;
586 break;
587 case SWITCH_T:
588 if (cplb_data[i].attr & SWITCH_T) {
589 t_i = &cplb.switch_i;
590 t_d = &cplb.switch_d;
591 process = 1;
592 } else
593 process = 0;
594 break;
595 default:
596 process = 0;
597 break;
598 }
599 636
600 if (process) { 637 if (as)
601 if (cplb_data[i].attr & I_CPLB) { 638 a_start = cplb_data[i].start + (SIZE_4M - (as));
602 639 else
603 if (cplb_data[i].psize) { 640 a_start = cplb_data[i].start;
604 fill_cplbtab(t_i,
605 cplb_data[i].start,
606 cplb_data[i].end,
607 cplb_data[i].psize,
608 cplb_data[i].i_conf);
609 } else {
610 /*icplb_table */
611#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
612 if (i == SDRAM_KERN) {
613 fill_cplbtab(t_i,
614 cplb_data[i].start,
615 cplb_data[i].end,
616 SIZE_4M,
617 cplb_data[i].i_conf);
618 } else
619#endif
620 {
621 fill_cplbtab(t_i,
622 cplb_data[i].start,
623 a_start,
624 SIZE_1M,
625 cplb_data[i].i_conf);
626 fill_cplbtab(t_i,
627 a_start,
628 a_end,
629 SIZE_4M,
630 cplb_data[i].i_conf);
631 fill_cplbtab(t_i, a_end,
632 cplb_data[i].end,
633 SIZE_1M,
634 cplb_data[i].i_conf);
635 }
636 }
637 641
638 } 642 a_end = cplb_data[i].end - ae;
639 if (cplb_data[i].attr & D_CPLB) {
640
641 if (cplb_data[i].psize) {
642 fill_cplbtab(t_d,
643 cplb_data[i].start,
644 cplb_data[i].end,
645 cplb_data[i].psize,
646 cplb_data[i].d_conf);
647 } else {
648/*dcplb_table*/
649 fill_cplbtab(t_d,
650 cplb_data[i].start,
651 a_start, SIZE_1M,
652 cplb_data[i].d_conf);
653 fill_cplbtab(t_d, a_start,
654 a_end, SIZE_4M,
655 cplb_data[i].d_conf);
656 fill_cplbtab(t_d, a_end,
657 cplb_data[i].end,
658 SIZE_1M,
659 cplb_data[i].d_conf);
660 643
661 } 644 for (j = INITIAL_T; j <= SWITCH_T; j++) {
662 645
663 } 646 switch (j) {
664 } 647 case INITIAL_T:
648 if (cplb_data[i].attr & INITIAL_T) {
649 t_i = &cplb.init_i;
650 t_d = &cplb.init_d;
651 process = 1;
652 } else
653 process = 0;
654 break;
655 case SWITCH_T:
656 if (cplb_data[i].attr & SWITCH_T) {
657 t_i = &cplb.switch_i;
658 t_d = &cplb.switch_d;
659 process = 1;
660 } else
661 process = 0;
662 break;
663 default:
664 process = 0;
665 break;
665 } 666 }
666 667
668 if (!process)
669 continue;
670 if (cplb_data[i].attr & I_CPLB)
671 __fill_code_cplbtab(t_i, i, a_start, a_end);
672
673 if (cplb_data[i].attr & D_CPLB)
674 __fill_data_cplbtab(t_d, i, a_start, a_end);
667 } 675 }
668 } 676 }
669 677
@@ -681,7 +689,7 @@ static void __init generate_cpl_tables(void)
681 689
682#endif 690#endif
683 691
684static inline u_long get_vco(void) 692static u_long get_vco(void)
685{ 693{
686 u_long msel; 694 u_long msel;
687 u_long vco; 695 u_long vco;
@@ -889,8 +897,8 @@ struct seq_operations cpuinfo_op = {
889 .show = show_cpuinfo, 897 .show = show_cpuinfo,
890}; 898};
891 899
892void cmdline_init(unsigned long r0) 900void __init cmdline_init(const char *r0)
893{ 901{
894 if (r0) 902 if (r0)
895 strncpy(command_line, (char *)r0, COMMAND_LINE_SIZE); 903 strncpy(command_line, r0, COMMAND_LINE_SIZE);
896} 904}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 20:06:28 -0500