diff options
Diffstat (limited to 'arch/blackfin/kernel/cplbinit.c')
-rw-r--r-- | arch/blackfin/kernel/cplbinit.c | 42 |
1 files changed, 26 insertions, 16 deletions
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c index 959b510c5ffb..6320bc45fbba 100644 --- a/arch/blackfin/kernel/cplbinit.c +++ b/arch/blackfin/kernel/cplbinit.c | |||
@@ -64,7 +64,7 @@ static struct cplb_desc cplb_data[] = { | |||
64 | #else | 64 | #else |
65 | .valid = 0, | 65 | .valid = 0, |
66 | #endif | 66 | #endif |
67 | .name = "ZERO Pointer Saveguard", | 67 | .name = "Zero Pointer Guard Page", |
68 | }, | 68 | }, |
69 | { | 69 | { |
70 | .start = L1_CODE_START, | 70 | .start = L1_CODE_START, |
@@ -95,20 +95,20 @@ static struct cplb_desc cplb_data[] = { | |||
95 | .end = 0, /* dynamic */ | 95 | .end = 0, /* dynamic */ |
96 | .psize = 0, | 96 | .psize = 0, |
97 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | 97 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, |
98 | .i_conf = SDRAM_IGENERIC, | 98 | .i_conf = SDRAM_IGENERIC, |
99 | .d_conf = SDRAM_DGENERIC, | 99 | .d_conf = SDRAM_DGENERIC, |
100 | .valid = 1, | 100 | .valid = 1, |
101 | .name = "SDRAM Kernel", | 101 | .name = "Kernel Memory", |
102 | }, | 102 | }, |
103 | { | 103 | { |
104 | .start = 0, /* dynamic */ | 104 | .start = 0, /* dynamic */ |
105 | .end = 0, /* dynamic */ | 105 | .end = 0, /* dynamic */ |
106 | .psize = 0, | 106 | .psize = 0, |
107 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | 107 | .attr = INITIAL_T | SWITCH_T | D_CPLB, |
108 | .i_conf = SDRAM_IGENERIC, | 108 | .i_conf = SDRAM_IGENERIC, |
109 | .d_conf = SDRAM_DNON_CHBL, | 109 | .d_conf = SDRAM_DNON_CHBL, |
110 | .valid = 1, | 110 | .valid = 1, |
111 | .name = "SDRAM RAM MTD", | 111 | .name = "uClinux MTD Memory", |
112 | }, | 112 | }, |
113 | { | 113 | { |
114 | .start = 0, /* dynamic */ | 114 | .start = 0, /* dynamic */ |
@@ -117,7 +117,7 @@ static struct cplb_desc cplb_data[] = { | |||
117 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | 117 | .attr = INITIAL_T | SWITCH_T | D_CPLB, |
118 | .d_conf = SDRAM_DNON_CHBL, | 118 | .d_conf = SDRAM_DNON_CHBL, |
119 | .valid = 1, | 119 | .valid = 1, |
120 | .name = "SDRAM Uncached DMA ZONE", | 120 | .name = "Uncached DMA Zone", |
121 | }, | 121 | }, |
122 | { | 122 | { |
123 | .start = 0, /* dynamic */ | 123 | .start = 0, /* dynamic */ |
@@ -127,7 +127,7 @@ static struct cplb_desc cplb_data[] = { | |||
127 | .i_conf = 0, /* dynamic */ | 127 | .i_conf = 0, /* dynamic */ |
128 | .d_conf = 0, /* dynamic */ | 128 | .d_conf = 0, /* dynamic */ |
129 | .valid = 1, | 129 | .valid = 1, |
130 | .name = "SDRAM Reserved Memory", | 130 | .name = "Reserved Memory", |
131 | }, | 131 | }, |
132 | { | 132 | { |
133 | .start = ASYNC_BANK0_BASE, | 133 | .start = ASYNC_BANK0_BASE, |
@@ -136,14 +136,14 @@ static struct cplb_desc cplb_data[] = { | |||
136 | .attr = SWITCH_T | D_CPLB, | 136 | .attr = SWITCH_T | D_CPLB, |
137 | .d_conf = SDRAM_EBIU, | 137 | .d_conf = SDRAM_EBIU, |
138 | .valid = 1, | 138 | .valid = 1, |
139 | .name = "ASYNC Memory", | 139 | .name = "Asynchronous Memory Banks", |
140 | }, | 140 | }, |
141 | { | 141 | { |
142 | #if defined(CONFIG_BF561) | 142 | #ifdef L2_START |
143 | .start = L2_SRAM, | 143 | .start = L2_START, |
144 | .end = L2_SRAM_END, | 144 | .end = L2_START + L2_LENGTH, |
145 | .psize = SIZE_1M, | 145 | .psize = SIZE_1M, |
146 | .attr = SWITCH_T | D_CPLB, | 146 | .attr = SWITCH_T | I_CPLB | D_CPLB, |
147 | .i_conf = L2_MEMORY, | 147 | .i_conf = L2_MEMORY, |
148 | .d_conf = L2_MEMORY, | 148 | .d_conf = L2_MEMORY, |
149 | .valid = 1, | 149 | .valid = 1, |
@@ -151,7 +151,17 @@ static struct cplb_desc cplb_data[] = { | |||
151 | .valid = 0, | 151 | .valid = 0, |
152 | #endif | 152 | #endif |
153 | .name = "L2 Memory", | 153 | .name = "L2 Memory", |
154 | } | 154 | }, |
155 | { | ||
156 | .start = BOOT_ROM_START, | ||
157 | .end = BOOT_ROM_START + BOOT_ROM_LENGTH, | ||
158 | .psize = SIZE_1M, | ||
159 | .attr = SWITCH_T | I_CPLB | D_CPLB, | ||
160 | .i_conf = SDRAM_IGENERIC, | ||
161 | .d_conf = SDRAM_DGENERIC, | ||
162 | .valid = 1, | ||
163 | .name = "On-Chip BootROM", | ||
164 | }, | ||
155 | }; | 165 | }; |
156 | 166 | ||
157 | static u16 __init lock_kernel_check(u32 start, u32 end) | 167 | static u16 __init lock_kernel_check(u32 start, u32 end) |
@@ -343,7 +353,7 @@ void __init generate_cpl_tables(void) | |||
343 | else | 353 | else |
344 | cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; | 354 | cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; |
345 | 355 | ||
346 | for (i = ZERO_P; i <= L2_MEM; i++) { | 356 | for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) { |
347 | if (!cplb_data[i].valid) | 357 | if (!cplb_data[i].valid) |
348 | continue; | 358 | continue; |
349 | 359 | ||