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-rw-r--r--arch/blackfin/kernel/cplb-nompu/Makefile8
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cacheinit.c67
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbhdlr.S130
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinfo.c208
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c437
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbmgr.S646
6 files changed, 1496 insertions, 0 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
new file mode 100644
index 000000000000..d36ea9b5382e
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/Makefile
@@ -0,0 +1,8 @@
1#
2# arch/blackfin/kernel/cplb-nompu/Makefile
3#
4
5obj-y := cplbinit.o cacheinit.o cplbhdlr.o cplbmgr.o
6
7obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
8
diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
new file mode 100644
index 000000000000..62cbba7364b0
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
@@ -0,0 +1,67 @@
1/*
2 * Copyright 2004-2007 Analog Devices Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see the file COPYING, or write
16 * to the Free Software Foundation, Inc.,
17 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <linux/cpu.h>
21
22#include <asm/cacheflush.h>
23#include <asm/blackfin.h>
24#include <asm/cplb.h>
25#include <asm/cplbinit.h>
26
27#if defined(CONFIG_BFIN_ICACHE)
28void bfin_icache_init(void)
29{
30 unsigned long *table = icplb_table;
31 unsigned long ctrl;
32 int i;
33
34 for (i = 0; i < MAX_CPLBS; i++) {
35 unsigned long addr = *table++;
36 unsigned long data = *table++;
37 if (addr == (unsigned long)-1)
38 break;
39 bfin_write32(ICPLB_ADDR0 + i * 4, addr);
40 bfin_write32(ICPLB_DATA0 + i * 4, data);
41 }
42 ctrl = bfin_read_IMEM_CONTROL();
43 ctrl |= IMC | ENICPLB;
44 bfin_write_IMEM_CONTROL(ctrl);
45}
46#endif
47
48#if defined(CONFIG_BFIN_DCACHE)
49void bfin_dcache_init(void)
50{
51 unsigned long *table = dcplb_table;
52 unsigned long ctrl;
53 int i;
54
55 for (i = 0; i < MAX_CPLBS; i++) {
56 unsigned long addr = *table++;
57 unsigned long data = *table++;
58 if (addr == (unsigned long)-1)
59 break;
60 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
61 bfin_write32(DCPLB_DATA0 + i * 4, data);
62 }
63 ctrl = bfin_read_DMEM_CONTROL();
64 ctrl |= DMEM_CNTR;
65 bfin_write_DMEM_CONTROL(ctrl);
66}
67#endif
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
new file mode 100644
index 000000000000..2788532de72b
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
@@ -0,0 +1,130 @@
1/*
2 * File: arch/blackfin/mach-common/cplbhdlr.S
3 * Based on:
4 * Author: LG Soft India
5 *
6 * Created: ?
7 * Description: CPLB exception handler
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <asm/cplb.h>
32#include <asm/entry.h>
33
34#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
35.section .l1.text
36#else
37.text
38#endif
39
40.type _cplb_mgr, STT_FUNC;
41.type _panic_cplb_error, STT_FUNC;
42
43.align 2
44
45ENTRY(__cplb_hdr)
46 R2 = SEQSTAT;
47
48 /* Mask the contents of SEQSTAT and leave only EXCAUSE in R2 */
49 R2 <<= 26;
50 R2 >>= 26;
51
52 R1 = 0x23; /* Data access CPLB protection violation */
53 CC = R2 == R1;
54 IF !CC JUMP .Lnot_data_write;
55 R0 = 2; /* is a write to data space*/
56 JUMP .Lis_icplb_miss;
57
58.Lnot_data_write:
59 R1 = 0x2C; /* CPLB miss on an instruction fetch */
60 CC = R2 == R1;
61 R0 = 0; /* is_data_miss == False*/
62 IF CC JUMP .Lis_icplb_miss;
63
64 R1 = 0x26;
65 CC = R2 == R1;
66 IF !CC JUMP .Lunknown;
67
68 R0 = 1; /* is_data_miss == True*/
69
70.Lis_icplb_miss:
71
72#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
73# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE)
74 R1 = CPLB_ENABLE_ICACHE;
75# endif
76# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
77 R1 = CPLB_ENABLE_DCACHE;
78# endif
79# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
80 R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
81# endif
82#else
83 R1 = 0;
84#endif
85
86 [--SP] = RETS;
87 CALL _cplb_mgr;
88 RETS = [SP++];
89 CC = R0 == 0;
90 IF !CC JUMP .Lnot_replaced;
91 RTS;
92
93/*
94 * Diagnostic exception handlers
95 */
96.Lunknown:
97 R0 = CPLB_UNKNOWN_ERR;
98 JUMP .Lcplb_error;
99
100.Lnot_replaced:
101 CC = R0 == CPLB_NO_UNLOCKED;
102 IF !CC JUMP .Lnext_check;
103 R0 = CPLB_NO_UNLOCKED;
104 JUMP .Lcplb_error;
105
106.Lnext_check:
107 CC = R0 == CPLB_NO_ADDR_MATCH;
108 IF !CC JUMP .Lnext_check2;
109 R0 = CPLB_NO_ADDR_MATCH;
110 JUMP .Lcplb_error;
111
112.Lnext_check2:
113 CC = R0 == CPLB_PROT_VIOL;
114 IF !CC JUMP .Lstrange_return_from_cplb_mgr;
115 R0 = CPLB_PROT_VIOL;
116 JUMP .Lcplb_error;
117
118.Lstrange_return_from_cplb_mgr:
119 IDLE;
120 CSYNC;
121 JUMP .Lstrange_return_from_cplb_mgr;
122
123.Lcplb_error:
124 R1 = sp;
125 SP += -12;
126 call _panic_cplb_error;
127 SP += 12;
128 JUMP _handle_bad_cplb;
129
130ENDPROC(__cplb_hdr)
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c
new file mode 100644
index 000000000000..a4f0b428a34d
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c
@@ -0,0 +1,208 @@
1/*
2 * File: arch/blackfin/mach-common/cplbinfo.c
3 * Based on:
4 * Author: Sonic Zhang <sonic.zhang@analog.com>
5 *
6 * Created: Jan. 2005
7 * Description: Display CPLB status
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/proc_fs.h>
34#include <linux/uaccess.h>
35
36#include <asm/current.h>
37#include <asm/system.h>
38#include <asm/cplb.h>
39#include <asm/blackfin.h>
40
41#define CPLB_I 1
42#define CPLB_D 2
43
44#define SYNC_SYS SSYNC()
45#define SYNC_CORE CSYNC()
46
47#define CPLB_BIT_PAGESIZE 0x30000
48
49static int page_size_table[4] = {
50 0x00000400, /* 1K */
51 0x00001000, /* 4K */
52 0x00100000, /* 1M */
53 0x00400000 /* 4M */
54};
55
56static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" };
57
58static int cplb_find_entry(unsigned long *cplb_addr,
59 unsigned long *cplb_data, unsigned long addr,
60 unsigned long data)
61{
62 int ii;
63
64 for (ii = 0; ii < 16; ii++)
65 if (addr >= cplb_addr[ii] && addr < cplb_addr[ii] +
66 page_size_table[(cplb_data[ii] & CPLB_BIT_PAGESIZE) >> 16]
67 && (cplb_data[ii] == data))
68 return ii;
69
70 return -1;
71}
72
73static char *cplb_print_entry(char *buf, int type)
74{
75 unsigned long *p_addr = dpdt_table;
76 unsigned long *p_data = dpdt_table + 1;
77 unsigned long *p_icount = dpdt_swapcount_table;
78 unsigned long *p_ocount = dpdt_swapcount_table + 1;
79 unsigned long *cplb_addr = (unsigned long *)DCPLB_ADDR0;
80 unsigned long *cplb_data = (unsigned long *)DCPLB_DATA0;
81 int entry = 0, used_cplb = 0;
82
83 if (type == CPLB_I) {
84 buf += sprintf(buf, "Instruction CPLB entry:\n");
85 p_addr = ipdt_table;
86 p_data = ipdt_table + 1;
87 p_icount = ipdt_swapcount_table;
88 p_ocount = ipdt_swapcount_table + 1;
89 cplb_addr = (unsigned long *)ICPLB_ADDR0;
90 cplb_data = (unsigned long *)ICPLB_DATA0;
91 } else
92 buf += sprintf(buf, "Data CPLB entry:\n");
93
94 buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\tiCount\toCount\n");
95
96 while (*p_addr != 0xffffffff) {
97 entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data);
98 if (entry >= 0)
99 used_cplb |= 1 << entry;
100
101 buf +=
102 sprintf(buf,
103 "0x%08lx\t0x%05lx\t%s\t%c\t%c\t%2d\t%ld\t%ld\n",
104 *p_addr, *p_data,
105 page_size_string_table[(*p_data & 0x30000) >> 16],
106 (*p_data & CPLB_VALID) ? 'Y' : 'N',
107 (*p_data & CPLB_LOCK) ? 'Y' : 'N', entry, *p_icount,
108 *p_ocount);
109
110 p_addr += 2;
111 p_data += 2;
112 p_icount += 2;
113 p_ocount += 2;
114 }
115
116 if (used_cplb != 0xffff) {
117 buf += sprintf(buf, "Unused/mismatched CPLBs:\n");
118
119 for (entry = 0; entry < 16; entry++)
120 if (0 == ((1 << entry) & used_cplb)) {
121 int flags = cplb_data[entry];
122 buf +=
123 sprintf(buf,
124 "%2d: 0x%08lx\t0x%05x\t%s\t%c\t%c\n",
125 entry, cplb_addr[entry], flags,
126 page_size_string_table[(flags &
127 0x30000) >>
128 16],
129 (flags & CPLB_VALID) ? 'Y' : 'N',
130 (flags & CPLB_LOCK) ? 'Y' : 'N');
131 }
132 }
133
134 buf += sprintf(buf, "\n");
135
136 return buf;
137}
138
139static int cplbinfo_proc_output(char *buf)
140{
141 char *p;
142
143 p = buf;
144
145 p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
146
147 if (bfin_read_IMEM_CONTROL() & ENICPLB)
148 p = cplb_print_entry(p, CPLB_I);
149 else
150 p += sprintf(p, "Instruction CPLB is disabled.\n\n");
151
152 if (bfin_read_DMEM_CONTROL() & ENDCPLB)
153 p = cplb_print_entry(p, CPLB_D);
154 else
155 p += sprintf(p, "Data CPLB is disabled.\n");
156
157 return p - buf;
158}
159
160static int cplbinfo_read_proc(char *page, char **start, off_t off,
161 int count, int *eof, void *data)
162{
163 int len;
164
165 len = cplbinfo_proc_output(page);
166 if (len <= off + count)
167 *eof = 1;
168 *start = page + off;
169 len -= off;
170 if (len > count)
171 len = count;
172 if (len < 0)
173 len = 0;
174 return len;
175}
176
177static int cplbinfo_write_proc(struct file *file, const char __user *buffer,
178 unsigned long count, void *data)
179{
180 printk(KERN_INFO "Reset the CPLB swap in/out counts.\n");
181 memset(ipdt_swapcount_table, 0, MAX_SWITCH_I_CPLBS * sizeof(unsigned long));
182 memset(dpdt_swapcount_table, 0, MAX_SWITCH_D_CPLBS * sizeof(unsigned long));
183
184 return count;
185}
186
187static int __init cplbinfo_init(void)
188{
189 struct proc_dir_entry *entry;
190
191 entry = create_proc_entry("cplbinfo", 0, NULL);
192 if (!entry)
193 return -ENOMEM;
194
195 entry->read_proc = cplbinfo_read_proc;
196 entry->write_proc = cplbinfo_write_proc;
197 entry->data = NULL;
198
199 return 0;
200}
201
202static void __exit cplbinfo_exit(void)
203{
204 remove_proc_entry("cplbinfo", NULL);
205}
206
207module_init(cplbinfo_init);
208module_exit(cplbinfo_exit);
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
new file mode 100644
index 000000000000..6320bc45fbba
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -0,0 +1,437 @@
1/*
2 * Blackfin CPLB initialization
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23#include <linux/module.h>
24
25#include <asm/blackfin.h>
26#include <asm/cplb.h>
27#include <asm/cplbinit.h>
28
29u_long icplb_table[MAX_CPLBS + 1];
30u_long dcplb_table[MAX_CPLBS + 1];
31
32#ifdef CONFIG_CPLB_SWITCH_TAB_L1
33# define PDT_ATTR __attribute__((l1_data))
34#else
35# define PDT_ATTR
36#endif
37
38u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
39u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
40
41#ifdef CONFIG_CPLB_INFO
42u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
43u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
44#endif
45
46struct s_cplb {
47 struct cplb_tab init_i;
48 struct cplb_tab init_d;
49 struct cplb_tab switch_i;
50 struct cplb_tab switch_d;
51};
52
53#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
54static struct cplb_desc cplb_data[] = {
55 {
56 .start = 0,
57 .end = SIZE_1K,
58 .psize = SIZE_1K,
59 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
60 .i_conf = SDRAM_OOPS,
61 .d_conf = SDRAM_OOPS,
62#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
63 .valid = 1,
64#else
65 .valid = 0,
66#endif
67 .name = "Zero Pointer Guard Page",
68 },
69 {
70 .start = L1_CODE_START,
71 .end = L1_CODE_START + L1_CODE_LENGTH,
72 .psize = SIZE_4M,
73 .attr = INITIAL_T | SWITCH_T | I_CPLB,
74 .i_conf = L1_IMEMORY,
75 .d_conf = 0,
76 .valid = 1,
77 .name = "L1 I-Memory",
78 },
79 {
80 .start = L1_DATA_A_START,
81 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
82 .psize = SIZE_4M,
83 .attr = INITIAL_T | SWITCH_T | D_CPLB,
84 .i_conf = 0,
85 .d_conf = L1_DMEMORY,
86#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
87 .valid = 1,
88#else
89 .valid = 0,
90#endif
91 .name = "L1 D-Memory",
92 },
93 {
94 .start = 0,
95 .end = 0, /* dynamic */
96 .psize = 0,
97 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
98 .i_conf = SDRAM_IGENERIC,
99 .d_conf = SDRAM_DGENERIC,
100 .valid = 1,
101 .name = "Kernel Memory",
102 },
103 {
104 .start = 0, /* dynamic */
105 .end = 0, /* dynamic */
106 .psize = 0,
107 .attr = INITIAL_T | SWITCH_T | D_CPLB,
108 .i_conf = SDRAM_IGENERIC,
109 .d_conf = SDRAM_DNON_CHBL,
110 .valid = 1,
111 .name = "uClinux MTD Memory",
112 },
113 {
114 .start = 0, /* dynamic */
115 .end = 0, /* dynamic */
116 .psize = SIZE_1M,
117 .attr = INITIAL_T | SWITCH_T | D_CPLB,
118 .d_conf = SDRAM_DNON_CHBL,
119 .valid = 1,
120 .name = "Uncached DMA Zone",
121 },
122 {
123 .start = 0, /* dynamic */
124 .end = 0, /* dynamic */
125 .psize = 0,
126 .attr = SWITCH_T | D_CPLB,
127 .i_conf = 0, /* dynamic */
128 .d_conf = 0, /* dynamic */
129 .valid = 1,
130 .name = "Reserved Memory",
131 },
132 {
133 .start = ASYNC_BANK0_BASE,
134 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
135 .psize = 0,
136 .attr = SWITCH_T | D_CPLB,
137 .d_conf = SDRAM_EBIU,
138 .valid = 1,
139 .name = "Asynchronous Memory Banks",
140 },
141 {
142#ifdef L2_START
143 .start = L2_START,
144 .end = L2_START + L2_LENGTH,
145 .psize = SIZE_1M,
146 .attr = SWITCH_T | I_CPLB | D_CPLB,
147 .i_conf = L2_MEMORY,
148 .d_conf = L2_MEMORY,
149 .valid = 1,
150#else
151 .valid = 0,
152#endif
153 .name = "L2 Memory",
154 },
155 {
156 .start = BOOT_ROM_START,
157 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
158 .psize = SIZE_1M,
159 .attr = SWITCH_T | I_CPLB | D_CPLB,
160 .i_conf = SDRAM_IGENERIC,
161 .d_conf = SDRAM_DGENERIC,
162 .valid = 1,
163 .name = "On-Chip BootROM",
164 },
165};
166
167static u16 __init lock_kernel_check(u32 start, u32 end)
168{
169 if ((end <= (u32) _end && end >= (u32)_stext) ||
170 (start <= (u32) _end && start >= (u32)_stext))
171 return IN_KERNEL;
172 return 0;
173}
174
175static unsigned short __init
176fill_cplbtab(struct cplb_tab *table,
177 unsigned long start, unsigned long end,
178 unsigned long block_size, unsigned long cplb_data)
179{
180 int i;
181
182 switch (block_size) {
183 case SIZE_4M:
184 i = 3;
185 break;
186 case SIZE_1M:
187 i = 2;
188 break;
189 case SIZE_4K:
190 i = 1;
191 break;
192 case SIZE_1K:
193 default:
194 i = 0;
195 break;
196 }
197
198 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
199
200 while ((start < end) && (table->pos < table->size)) {
201
202 table->tab[table->pos++] = start;
203
204 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
205 table->tab[table->pos++] =
206 cplb_data | CPLB_LOCK | CPLB_DIRTY;
207 else
208 table->tab[table->pos++] = cplb_data;
209
210 start += block_size;
211 }
212 return 0;
213}
214
215static unsigned short __init
216close_cplbtab(struct cplb_tab *table)
217{
218
219 while (table->pos < table->size) {
220
221 table->tab[table->pos++] = 0;
222 table->tab[table->pos++] = 0; /* !CPLB_VALID */
223 }
224 return 0;
225}
226
227/* helper function */
228static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
229{
230 if (cplb_data[i].psize) {
231 fill_cplbtab(t,
232 cplb_data[i].start,
233 cplb_data[i].end,
234 cplb_data[i].psize,
235 cplb_data[i].i_conf);
236 } else {
237#if defined(CONFIG_BFIN_ICACHE)
238 if (ANOMALY_05000263 && i == SDRAM_KERN) {
239 fill_cplbtab(t,
240 cplb_data[i].start,
241 cplb_data[i].end,
242 SIZE_4M,
243 cplb_data[i].i_conf);
244 } else
245#endif
246 {
247 fill_cplbtab(t,
248 cplb_data[i].start,
249 a_start,
250 SIZE_1M,
251 cplb_data[i].i_conf);
252 fill_cplbtab(t,
253 a_start,
254 a_end,
255 SIZE_4M,
256 cplb_data[i].i_conf);
257 fill_cplbtab(t, a_end,
258 cplb_data[i].end,
259 SIZE_1M,
260 cplb_data[i].i_conf);
261 }
262 }
263}
264
265static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
266{
267 if (cplb_data[i].psize) {
268 fill_cplbtab(t,
269 cplb_data[i].start,
270 cplb_data[i].end,
271 cplb_data[i].psize,
272 cplb_data[i].d_conf);
273 } else {
274 fill_cplbtab(t,
275 cplb_data[i].start,
276 a_start, SIZE_1M,
277 cplb_data[i].d_conf);
278 fill_cplbtab(t, a_start,
279 a_end, SIZE_4M,
280 cplb_data[i].d_conf);
281 fill_cplbtab(t, a_end,
282 cplb_data[i].end,
283 SIZE_1M,
284 cplb_data[i].d_conf);
285 }
286}
287
288void __init generate_cpl_tables(void)
289{
290
291 u16 i, j, process;
292 u32 a_start, a_end, as, ae, as_1m;
293
294 struct cplb_tab *t_i = NULL;
295 struct cplb_tab *t_d = NULL;
296 struct s_cplb cplb;
297
298 cplb.init_i.size = MAX_CPLBS;
299 cplb.init_d.size = MAX_CPLBS;
300 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
301 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
302
303 cplb.init_i.pos = 0;
304 cplb.init_d.pos = 0;
305 cplb.switch_i.pos = 0;
306 cplb.switch_d.pos = 0;
307
308 cplb.init_i.tab = icplb_table;
309 cplb.init_d.tab = dcplb_table;
310 cplb.switch_i.tab = ipdt_table;
311 cplb.switch_d.tab = dpdt_table;
312
313 cplb_data[SDRAM_KERN].end = memory_end;
314
315#ifdef CONFIG_MTD_UCLINUX
316 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
317 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
318 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
319# if defined(CONFIG_ROMFS_FS)
320 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
321
322 /*
323 * The ROMFS_FS size is often not multiple of 1MB.
324 * This can cause multiple CPLB sets covering the same memory area.
325 * This will then cause multiple CPLB hit exceptions.
326 * Workaround: We ensure a contiguous memory area by extending the kernel
327 * memory section over the mtd section.
328 * For ROMFS_FS memory must be covered with ICPLBs anyways.
329 * So there is no difference between kernel and mtd memory setup.
330 */
331
332 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
333 cplb_data[SDRAM_RAM_MTD].valid = 0;
334
335# endif
336#else
337 cplb_data[SDRAM_RAM_MTD].valid = 0;
338#endif
339
340 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
341 cplb_data[SDRAM_DMAZ].end = _ramend;
342
343 cplb_data[RES_MEM].start = _ramend;
344 cplb_data[RES_MEM].end = physical_mem_end;
345
346 if (reserved_mem_dcache_on)
347 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
348 else
349 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
350
351 if (reserved_mem_icache_on)
352 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
353 else
354 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
355
356 for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
357 if (!cplb_data[i].valid)
358 continue;
359
360 as_1m = cplb_data[i].start % SIZE_1M;
361
362 /* We need to make sure all sections are properly 1M aligned
363 * However between Kernel Memory and the Kernel mtd section, depending on the
364 * rootfs size, there can be overlapping memory areas.
365 */
366
367 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
368#ifdef CONFIG_MTD_UCLINUX
369 if (i == SDRAM_RAM_MTD) {
370 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
371 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
372 else
373 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
374 } else
375#endif
376 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
377 cplb_data[i].name, cplb_data[i].start);
378 }
379
380 as = cplb_data[i].start % SIZE_4M;
381 ae = cplb_data[i].end % SIZE_4M;
382
383 if (as)
384 a_start = cplb_data[i].start + (SIZE_4M - (as));
385 else
386 a_start = cplb_data[i].start;
387
388 a_end = cplb_data[i].end - ae;
389
390 for (j = INITIAL_T; j <= SWITCH_T; j++) {
391
392 switch (j) {
393 case INITIAL_T:
394 if (cplb_data[i].attr & INITIAL_T) {
395 t_i = &cplb.init_i;
396 t_d = &cplb.init_d;
397 process = 1;
398 } else
399 process = 0;
400 break;
401 case SWITCH_T:
402 if (cplb_data[i].attr & SWITCH_T) {
403 t_i = &cplb.switch_i;
404 t_d = &cplb.switch_d;
405 process = 1;
406 } else
407 process = 0;
408 break;
409 default:
410 process = 0;
411 break;
412 }
413
414 if (!process)
415 continue;
416 if (cplb_data[i].attr & I_CPLB)
417 __fill_code_cplbtab(t_i, i, a_start, a_end);
418
419 if (cplb_data[i].attr & D_CPLB)
420 __fill_data_cplbtab(t_d, i, a_start, a_end);
421 }
422 }
423
424/* close tables */
425
426 close_cplbtab(&cplb.init_i);
427 close_cplbtab(&cplb.init_d);
428
429 cplb.init_i.tab[cplb.init_i.pos] = -1;
430 cplb.init_d.tab[cplb.init_d.pos] = -1;
431 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
432 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
433
434}
435
436#endif
437
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
new file mode 100644
index 000000000000..f5cf3accef37
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
@@ -0,0 +1,646 @@
1/*
2 * File: arch/blackfin/mach-common/cplbmgtr.S
3 * Based on:
4 * Author: LG Soft India
5 *
6 * Created: ?
7 * Description: CPLB replacement routine for CPLB mismatch
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
31 * is_data_miss==2 => Mark as Dirty, write to the clean data page
32 * is_data_miss==1 => Replace a data CPLB.
33 * is_data_miss==0 => Replace an instruction CPLB.
34 *
35 * Returns:
36 * CPLB_RELOADED => Successfully updated CPLB table.
37 * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.
38 * This indicates that the CPLBs in the configuration
39 * tablei are badly configured, as this should never
40 * occur.
41 * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the
42 * exception, is not covered by any of the CPLBs in
43 * the configuration table. The application is
44 * presumably misbehaving.
45 * CPLB_PROT_VIOL => The address being accessed, that triggered the
46 * exception, was not a first-write to a clean Write
47 * Back Data page, and so presumably is a genuine
48 * violation of the page's protection attributes.
49 * The application is misbehaving.
50 */
51
52#include <linux/linkage.h>
53#include <asm/blackfin.h>
54#include <asm/cplb.h>
55
56#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
57.section .l1.text
58#else
59.text
60#endif
61
62.align 2;
63ENTRY(_cplb_mgr)
64
65 [--SP]=( R7:4,P5:3 );
66
67 CC = R0 == 2;
68 IF CC JUMP .Ldcplb_write;
69
70 CC = R0 == 0;
71 IF !CC JUMP .Ldcplb_miss_compare;
72
73 /* ICPLB Miss Exception. We need to choose one of the
74 * currently-installed CPLBs, and replace it with one
75 * from the configuration table.
76 */
77
78 /* A multi-word instruction can cross a page boundary. This means the
79 * first part of the instruction can be in a valid page, but the
80 * second part is not, and hence generates the instruction miss.
81 * However, the fault address is for the start of the instruction,
82 * not the part that's in the bad page. Therefore, we have to check
83 * whether the fault address applies to a page that is already present
84 * in the table.
85 */
86
87 P4.L = LO(ICPLB_FAULT_ADDR);
88 P4.H = HI(ICPLB_FAULT_ADDR);
89
90 P1 = 16;
91 P5.L = _page_size_table;
92 P5.H = _page_size_table;
93
94 P0.L = LO(ICPLB_DATA0);
95 P0.H = HI(ICPLB_DATA0);
96 R4 = [P4]; /* Get faulting address*/
97 R6 = 64; /* Advance past the fault address, which*/
98 R6 = R6 + R4; /* we'll use if we find a match*/
99 R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */
100
101 R5 = 0;
102.Lisearch:
103
104 R1 = [P0-0x100]; /* Address for this CPLB */
105
106 R0 = [P0++]; /* Info for this CPLB*/
107 CC = BITTST(R0,0); /* Is the CPLB valid?*/
108 IF !CC JUMP .Lnomatch; /* Skip it, if not.*/
109 CC = R4 < R1(IU); /* If fault address less than page start*/
110 IF CC JUMP .Lnomatch; /* then skip this one.*/
111 R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
112 P1 = R2;
113 P1 = P5 + (P1<<2); /* index into page-size table*/
114 R2 = [P1]; /* Get the page size*/
115 R1 = R1 + R2; /* and add to page start, to get page end*/
116 CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
117 IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
118 IF !CC JUMP .Lisearch_done;
119.Lnomatch:
120 /* Go around again*/
121 R5 += 1;
122 CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
123 IF !CC JUMP .Lisearch;
124
125.Lisearch_done:
126 I0 = R4; /* Fault address we'll search for*/
127
128 /* set up pointers */
129 P0.L = LO(ICPLB_DATA0);
130 P0.H = HI(ICPLB_DATA0);
131
132 /* The replacement procedure for ICPLBs */
133
134 P4.L = LO(IMEM_CONTROL);
135 P4.H = HI(IMEM_CONTROL);
136
137 /* Turn off CPLBs while we work, necessary according to HRM before
138 * modifying CPLB descriptors
139 */
140 R5 = [P4]; /* Control Register*/
141 BITCLR(R5,ENICPLB_P);
142 CLI R1;
143 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
144 .align 8;
145 [P4] = R5;
146 SSYNC;
147 STI R1;
148
149 R1 = -1; /* end point comparison */
150 R3 = 16; /* counter */
151
152 /* Search through CPLBs for first non-locked entry */
153 /* Overwrite it by moving everyone else up by 1 */
154.Licheck_lock:
155 R0 = [P0++];
156 R3 = R3 + R1;
157 CC = R3 == R1;
158 IF CC JUMP .Lall_locked;
159 CC = BITTST(R0, 0); /* an invalid entry is good */
160 IF !CC JUMP .Lifound_victim;
161 CC = BITTST(R0,1); /* but a locked entry isn't */
162 IF CC JUMP .Licheck_lock;
163
164.Lifound_victim:
165#ifdef CONFIG_CPLB_INFO
166 R7 = [P0 - 0x104];
167 P2.L = _ipdt_table;
168 P2.H = _ipdt_table;
169 P3.L = _ipdt_swapcount_table;
170 P3.H = _ipdt_swapcount_table;
171 P3 += -4;
172.Licount:
173 R2 = [P2]; /* address from config table */
174 P2 += 8;
175 P3 += 8;
176 CC = R2==-1;
177 IF CC JUMP .Licount_done;
178 CC = R7==R2;
179 IF !CC JUMP .Licount;
180 R7 = [P3];
181 R7 += 1;
182 [P3] = R7;
183 CSYNC;
184.Licount_done:
185#endif
186 LC0=R3;
187 LSETUP(.Lis_move,.Lie_move) LC0;
188.Lis_move:
189 R0 = [P0];
190 [P0 - 4] = R0;
191 R0 = [P0 - 0x100];
192 [P0-0x104] = R0;
193.Lie_move:
194 P0+=4;
195
196 /* Clear ICPLB_DATA15, in case we don't find a replacement
197 * otherwise, we would have a duplicate entry, and will crash
198 */
199 R0 = 0;
200 [P0 - 4] = R0;
201
202 /* We've made space in the ICPLB table, so that ICPLB15
203 * is now free to be overwritten. Next, we have to determine
204 * which CPLB we need to install, from the configuration
205 * table. This is a matter of getting the start-of-page
206 * addresses and page-lengths from the config table, and
207 * determining whether the fault address falls within that
208 * range.
209 */
210
211 P2.L = _ipdt_table;
212 P2.H = _ipdt_table;
213#ifdef CONFIG_CPLB_INFO
214 P3.L = _ipdt_swapcount_table;
215 P3.H = _ipdt_swapcount_table;
216 P3 += -8;
217#endif
218 P0.L = _page_size_table;
219 P0.H = _page_size_table;
220
221 /* Retrieve our fault address (which may have been advanced
222 * because the faulting instruction crossed a page boundary).
223 */
224
225 R0 = I0;
226
227 /* An extraction pattern, to get the page-size bits from
228 * the CPLB data entry. Bits 16-17, so two bits at posn 16.
229 */
230
231 R1 = ((16<<8)|2);
232.Linext: R4 = [P2++]; /* address from config table */
233 R2 = [P2++]; /* data from config table */
234#ifdef CONFIG_CPLB_INFO
235 P3 += 8;
236#endif
237
238 CC = R4 == -1; /* End of config table*/
239 IF CC JUMP .Lno_page_in_table;
240
241 /* See if failed address > start address */
242 CC = R4 <= R0(IU);
243 IF !CC JUMP .Linext;
244
245 /* extract page size (17:16)*/
246 R3 = EXTRACT(R2, R1.L) (Z);
247
248 /* add page size to addr to get range */
249
250 P5 = R3;
251 P5 = P0 + (P5 << 2); /* scaled, for int access*/
252 R3 = [P5];
253 R3 = R3 + R4;
254
255 /* See if failed address < (start address + page size) */
256 CC = R0 < R3(IU);
257 IF !CC JUMP .Linext;
258
259 /* We've found a CPLB in the config table that covers
260 * the faulting address, so install this CPLB into the
261 * last entry of the table.
262 */
263
264 P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */
265 P1.H = HI(ICPLB_DATA15);
266 [P1] = R2;
267 [P1-0x100] = R4;
268#ifdef CONFIG_CPLB_INFO
269 R3 = [P3];
270 R3 += 1;
271 [P3] = R3;
272#endif
273
274 /* P4 points to IMEM_CONTROL, and R5 contains its old
275 * value, after we disabled ICPLBS. Re-enable them.
276 */
277
278 BITSET(R5,ENICPLB_P);
279 CLI R2;
280 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
281 .align 8;
282 [P4] = R5;
283 SSYNC;
284 STI R2;
285
286 ( R7:4,P5:3 ) = [SP++];
287 R0 = CPLB_RELOADED;
288 RTS;
289
290/* FAILED CASES*/
291.Lno_page_in_table:
292 R0 = CPLB_NO_ADDR_MATCH;
293 JUMP .Lfail_ret;
294
295.Lall_locked:
296 R0 = CPLB_NO_UNLOCKED;
297 JUMP .Lfail_ret;
298
299.Lprot_violation:
300 R0 = CPLB_PROT_VIOL;
301
302.Lfail_ret:
303 /* Make sure we turn protection/cache back on, even in the failing case */
304 BITSET(R5,ENICPLB_P);
305 CLI R2;
306 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
307 .align 8;
308 [P4] = R5;
309 SSYNC;
310 STI R2;
311
312 ( R7:4,P5:3 ) = [SP++];
313 RTS;
314
315.Ldcplb_write:
316
317 /* if a DCPLB is marked as write-back (CPLB_WT==0), and
318 * it is clean (CPLB_DIRTY==0), then a write to the
319 * CPLB's page triggers a protection violation. We have to
320 * mark the CPLB as dirty, to indicate that there are
321 * pending writes associated with the CPLB.
322 */
323
324 P4.L = LO(DCPLB_STATUS);
325 P4.H = HI(DCPLB_STATUS);
326 P3.L = LO(DCPLB_DATA0);
327 P3.H = HI(DCPLB_DATA0);
328 R5 = [P4];
329
330 /* A protection violation can be caused by more than just writes
331 * to a clean WB page, so we have to ensure that:
332 * - It's a write
333 * - to a clean WB page
334 * - and is allowed in the mode the access occurred.
335 */
336
337 CC = BITTST(R5, 16); /* ensure it was a write*/
338 IF !CC JUMP .Lprot_violation;
339
340 /* to check the rest, we have to retrieve the DCPLB.*/
341
342 /* The low half of DCPLB_STATUS is a bit mask*/
343
344 R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
345 R3 = 30; /* so we can use this to determine the offset*/
346 R2.L = SIGNBITS R2;
347 R2 = R2.L (Z); /* into the DCPLB table.*/
348 R3 = R3 - R2;
349 P4 = R3;
350 P3 = P3 + (P4<<2);
351 R3 = [P3]; /* Retrieve the CPLB*/
352
353 /* Now we can check whether it's a clean WB page*/
354
355 CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
356 IF CC JUMP .Lprot_violation;
357 CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
358 IF CC JUMP .Lprot_violation;
359
360 /* Check whether the write is allowed in the mode that was active.*/
361
362 R2 = 1<<3; /* checking write in user mode*/
363 CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
364 R5 = CC;
365 R2 <<= R5; /* if was super, check write in super mode*/
366 R2 = R3 & R2;
367 CC = R2 == 0;
368 IF CC JUMP .Lprot_violation;
369
370 /* It's a genuine write-to-clean-page.*/
371
372 BITSET(R3, 7); /* mark as dirty*/
373 [P3] = R3; /* and write back.*/
374 NOP;
375 CSYNC;
376 ( R7:4,P5:3 ) = [SP++];
377 R0 = CPLB_RELOADED;
378 RTS;
379
380.Ldcplb_miss_compare:
381
382 /* Data CPLB Miss event. We need to choose a CPLB to
383 * evict, and then locate a new CPLB to install from the
384 * config table, that covers the faulting address.
385 */
386
387 P1.L = LO(DCPLB_DATA15);
388 P1.H = HI(DCPLB_DATA15);
389
390 P4.L = LO(DCPLB_FAULT_ADDR);
391 P4.H = HI(DCPLB_FAULT_ADDR);
392 R4 = [P4];
393 I0 = R4;
394
395 /* The replacement procedure for DCPLBs*/
396
397 R6 = R1; /* Save for later*/
398
399 /* Turn off CPLBs while we work.*/
400 P4.L = LO(DMEM_CONTROL);
401 P4.H = HI(DMEM_CONTROL);
402 R5 = [P4];
403 BITCLR(R5,ENDCPLB_P);
404 CLI R0;
405 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
406 .align 8;
407 [P4] = R5;
408 SSYNC;
409 STI R0;
410
411 /* Start looking for a CPLB to evict. Our order of preference
412 * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
413 * are no good.
414 */
415
416 I1.L = LO(DCPLB_DATA0);
417 I1.H = HI(DCPLB_DATA0);
418 P1 = 2;
419 P2 = 16;
420 I2.L = _dcplb_preference;
421 I2.H = _dcplb_preference;
422 LSETUP(.Lsdsearch1, .Ledsearch1) LC0 = P1;
423.Lsdsearch1:
424 R0 = [I2++]; /* Get the bits we're interested in*/
425 P0 = I1; /* Go back to start of table*/
426 LSETUP (.Lsdsearch2, .Ledsearch2) LC1 = P2;
427.Lsdsearch2:
428 R1 = [P0++]; /* Fetch each installed CPLB in turn*/
429 R2 = R1 & R0; /* and test for interesting bits.*/
430 CC = R2 == 0; /* If none are set, it'll do.*/
431 IF !CC JUMP .Lskip_stack_check;
432
433 R2 = [P0 - 0x104]; /* R2 - PageStart */
434 P3.L = _page_size_table; /* retrieve end address */
435 P3.H = _page_size_table; /* retrieve end address */
436 R3 = 0x1002; /* 16th - position, 2 bits -length */
437#if ANOMALY_05000209
438 nop; /* Anomaly 05000209 */
439#endif
440 R7 = EXTRACT(R1,R3.l);
441 R7 = R7 << 2; /* Page size index offset */
442 P5 = R7;
443 P3 = P3 + P5;
444 R7 = [P3]; /* page size in bytes */
445
446 R7 = R2 + R7; /* R7 - PageEnd */
447 R4 = SP; /* Test SP is in range */
448
449 CC = R7 < R4; /* if PageEnd < SP */
450 IF CC JUMP .Ldfound_victim;
451 R3 = 0x284; /* stack length from start of trap till
452 * the point.
453 * 20 stack locations for future modifications
454 */
455 R4 = R4 + R3;
456 CC = R4 < R2; /* if SP + stacklen < PageStart */
457 IF CC JUMP .Ldfound_victim;
458.Lskip_stack_check:
459
460.Ledsearch2: NOP;
461.Ledsearch1: NOP;
462
463 /* If we got here, we didn't find a DCPLB we considered
464 * replacable, which means all of them were locked.
465 */
466
467 JUMP .Lall_locked;
468.Ldfound_victim:
469
470#ifdef CONFIG_CPLB_INFO
471 R7 = [P0 - 0x104];
472 P2.L = _dpdt_table;
473 P2.H = _dpdt_table;
474 P3.L = _dpdt_swapcount_table;
475 P3.H = _dpdt_swapcount_table;
476 P3 += -4;
477.Ldicount:
478 R2 = [P2];
479 P2 += 8;
480 P3 += 8;
481 CC = R2==-1;
482 IF CC JUMP .Ldicount_done;
483 CC = R7==R2;
484 IF !CC JUMP .Ldicount;
485 R7 = [P3];
486 R7 += 1;
487 [P3] = R7;
488.Ldicount_done:
489#endif
490
491 /* Clean down the hardware loops*/
492 R2 = 0;
493 LC1 = R2;
494 LC0 = R2;
495
496 /* There's a suitable victim in [P0-4] (because we've
497 * advanced already).
498 */
499
500.LDdoverwrite:
501
502 /* [P0-4] is a suitable victim CPLB, so we want to
503 * overwrite it by moving all the following CPLBs
504 * one space closer to the start.
505 */
506
507 R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */
508 R1.H = HI(DCPLB_DATA16);
509 R0 = P0;
510
511 /* If the victim happens to be in DCPLB15,
512 * we don't need to move anything.
513 */
514
515 CC = R1 == R0;
516 IF CC JUMP .Lde_moved;
517 R1 = R1 - R0;
518 R1 >>= 2;
519 P1 = R1;
520 LSETUP(.Lds_move, .Lde_move) LC0=P1;
521.Lds_move:
522 R0 = [P0++]; /* move data */
523 [P0 - 8] = R0;
524 R0 = [P0-0x104] /* move address */
525.Lde_move:
526 [P0-0x108] = R0;
527
528.Lde_moved:
529 NOP;
530
531 /* Clear DCPLB_DATA15, in case we don't find a replacement
532 * otherwise, we would have a duplicate entry, and will crash
533 */
534 R0 = 0;
535 [P0 - 0x4] = R0;
536
537 /* We've now made space in DCPLB15 for the new CPLB to be
538 * installed. The next stage is to locate a CPLB in the
539 * config table that covers the faulting address.
540 */
541
542 R0 = I0; /* Our faulting address */
543
544 P2.L = _dpdt_table;
545 P2.H = _dpdt_table;
546#ifdef CONFIG_CPLB_INFO
547 P3.L = _dpdt_swapcount_table;
548 P3.H = _dpdt_swapcount_table;
549 P3 += -8;
550#endif
551
552 P1.L = _page_size_table;
553 P1.H = _page_size_table;
554
555 /* An extraction pattern, to retrieve bits 17:16.*/
556
557 R1 = (16<<8)|2;
558.Ldnext: R4 = [P2++]; /* address */
559 R2 = [P2++]; /* data */
560#ifdef CONFIG_CPLB_INFO
561 P3 += 8;
562#endif
563
564 CC = R4 == -1;
565 IF CC JUMP .Lno_page_in_table;
566
567 /* See if failed address > start address */
568 CC = R4 <= R0(IU);
569 IF !CC JUMP .Ldnext;
570
571 /* extract page size (17:16)*/
572 R3 = EXTRACT(R2, R1.L) (Z);
573
574 /* add page size to addr to get range */
575
576 P5 = R3;
577 P5 = P1 + (P5 << 2);
578 R3 = [P5];
579 R3 = R3 + R4;
580
581 /* See if failed address < (start address + page size) */
582 CC = R0 < R3(IU);
583 IF !CC JUMP .Ldnext;
584
585 /* We've found the CPLB that should be installed, so
586 * write it into CPLB15, masking off any caching bits
587 * if necessary.
588 */
589
590 P1.L = LO(DCPLB_DATA15);
591 P1.H = HI(DCPLB_DATA15);
592
593 /* If the DCPLB has cache bits set, but caching hasn't
594 * been enabled, then we want to mask off the cache-in-L1
595 * bit before installing. Moreover, if caching is off, we
596 * also want to ensure that the DCPLB has WT mode set, rather
597 * than WB, since WB pages still trigger first-write exceptions
598 * even when not caching is off, and the page isn't marked as
599 * cachable. Finally, we could mark the page as clean, not dirty,
600 * but we choose to leave that decision to the user; if the user
601 * chooses to have a CPLB pre-defined as dirty, then they always
602 * pay the cost of flushing during eviction, but don't pay the
603 * cost of first-write exceptions to mark the page as dirty.
604 */
605
606#ifdef CONFIG_BFIN_WT
607 BITSET(R6, 14); /* Set WT*/
608#endif
609
610 [P1] = R2;
611 [P1-0x100] = R4;
612#ifdef CONFIG_CPLB_INFO
613 R3 = [P3];
614 R3 += 1;
615 [P3] = R3;
616#endif
617
618 /* We've installed the CPLB, so re-enable CPLBs. P4
619 * points to DMEM_CONTROL, and R5 is the value we
620 * last wrote to it, when we were disabling CPLBs.
621 */
622
623 BITSET(R5,ENDCPLB_P);
624 CLI R2;
625 .align 8;
626 [P4] = R5;
627 SSYNC;
628 STI R2;
629
630 ( R7:4,P5:3 ) = [SP++];
631 R0 = CPLB_RELOADED;
632 RTS;
633ENDPROC(_cplb_mgr)
634
635.data
636.align 4;
637_page_size_table:
638.byte4 0x00000400; /* 1K */
639.byte4 0x00001000; /* 4K */
640.byte4 0x00100000; /* 1M */
641.byte4 0x00400000; /* 4M */
642
643.align 4;
644_dcplb_preference:
645.byte4 0x00000001; /* valid bit */
646.byte4 0x00000002; /* lock bit */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 17:00:36 -0500