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-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 685f160a5a36..5d8ad503f82a 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -36,7 +36,7 @@ int first_switched_icplb PDT_ATTR;
36int first_switched_dcplb PDT_ATTR; 36int first_switched_dcplb PDT_ATTR;
37 37
38struct cplb_boundary dcplb_bounds[9] PDT_ATTR; 38struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
39struct cplb_boundary icplb_bounds[7] PDT_ATTR; 39struct cplb_boundary icplb_bounds[9] PDT_ATTR;
40 40
41int icplb_nr_bounds PDT_ATTR; 41int icplb_nr_bounds PDT_ATTR;
42int dcplb_nr_bounds PDT_ATTR; 42int dcplb_nr_bounds PDT_ATTR;
@@ -167,14 +167,21 @@ void __init generate_cplb_tables_all(void)
167 icplb_bounds[i_i++].data = (reserved_mem_icache_on ? 167 icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
168 SDRAM_IGENERIC : SDRAM_INON_CHBL); 168 SDRAM_IGENERIC : SDRAM_INON_CHBL);
169 } 169 }
170 /* Addressing hole up to the async bank. */
171 icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
172 icplb_bounds[i_i++].data = 0;
173 /* ASYNC banks. */
174 icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
175 icplb_bounds[i_i++].data = SDRAM_EBIU;
170 /* Addressing hole up to BootROM. */ 176 /* Addressing hole up to BootROM. */
171 icplb_bounds[i_i].eaddr = BOOT_ROM_START; 177 icplb_bounds[i_i].eaddr = BOOT_ROM_START;
172 icplb_bounds[i_i++].data = 0; 178 icplb_bounds[i_i++].data = 0;
173 /* BootROM -- largest one should be less than 1 meg. */ 179 /* BootROM -- largest one should be less than 1 meg. */
174 icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); 180 icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
175 icplb_bounds[i_i++].data = SDRAM_IGENERIC; 181 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
182
176 if (L2_LENGTH) { 183 if (L2_LENGTH) {
177 /* Addressing hole up to L2 SRAM, including the async bank. */ 184 /* Addressing hole up to L2 SRAM. */
178 icplb_bounds[i_i].eaddr = L2_START; 185 icplb_bounds[i_i].eaddr = L2_START;
179 icplb_bounds[i_i++].data = 0; 186 icplb_bounds[i_i++].data = 0;
180 /* L2 SRAM. */ 187 /* L2 SRAM. */