1 files changed, 4 insertions, 2 deletions

diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
index d5a86c3017f7..a082681faa8e 100644
--- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
@@ -30,13 +30,14 @@ void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
         unsigned long ctrl;
         int i;
 
-        SSYNC();
         for (i = 0; i < MAX_CPLBS; i++) {
                 bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
                 bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
         }
         ctrl = bfin_read_IMEM_CONTROL();
         ctrl |= IMC | ENICPLB;
+        /* CSYNC to ensure load store ordering */
+        CSYNC();
         bfin_write_IMEM_CONTROL(ctrl);
         SSYNC();
 }
@@ -48,7 +49,6 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
         unsigned long ctrl;
         int i;
 
-        SSYNC();
         for (i = 0; i < MAX_CPLBS; i++) {
                 bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
                 bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
@@ -63,6 +63,8 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
          *  to port B
          */
         ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
+        /* CSYNC to ensure load store ordering */
+        CSYNC();
         bfin_write_DMEM_CONTROL(ctrl);
         SSYNC();
 }