2 files changed, 132 insertions, 97 deletions
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index b558908e1c79..9626cf7e4251 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -1,7 +1,7 @@
 /*
- * bfin_sport.h - userspace header for bfin sport driver
+ * bfin_sport.h - interface to Blackfin SPORTs
 *
- * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */
@@ -9,16 +9,6 @@
 #ifndef __BFIN_SPORT_H__
 #define __BFIN_SPORT_H__
-#ifdef __KERNEL__
-#include <linux/cdev.h>
-#include <linux/mutex.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#endif
-#define SPORT_MAJOR     237
-#define SPORT_NR_DEVS   2
 /* Sport mode: it can be set to TDM, i2s or others */
 #define NORM_MODE       0x0
 #define TDM_MODE        0x1
@@ -35,7 +25,7 @@ struct sport_config {
        unsigned int mode:3;
        /* if TDM mode is selected, channels must be set */
-        int channels;           /* Must be in 8 units */
+        int channels;   /* Must be in 8 units */
        unsigned int frame_delay:4;     /* Delay between frame sync pulse and first bit */
        /* I2S mode */
@@ -69,94 +59,137 @@ struct sport_config {
 #ifdef __KERNEL__
-struct sport_register {
+#include <linux/types.h>
-        unsigned short tcr1;
-        unsigned short reserved0;
-        unsigned short tcr2;
-        unsigned short reserved1;
-        unsigned short tclkdiv;
-        unsigned short reserved2;
-        unsigned short tfsdiv;
-        unsigned short reserved3;
-        unsigned long tx;
-        unsigned long reserved_l0;
-        unsigned long rx;
-        unsigned long reserved_l1;
-        unsigned short rcr1;
-        unsigned short reserved4;
-        unsigned short rcr2;
-        unsigned short reserved5;
-        unsigned short rclkdiv;
-        unsigned short reserved6;
-        unsigned short rfsdiv;
-        unsigned short reserved7;
-        unsigned short stat;
-        unsigned short reserved8;
-        unsigned short chnl;
-        unsigned short reserved9;
-        unsigned short mcmc1;
-        unsigned short reserved10;
-        unsigned short mcmc2;
-        unsigned short reserved11;
-        unsigned long mtcs0;
-        unsigned long mtcs1;
-        unsigned long mtcs2;
-        unsigned long mtcs3;
-        unsigned long mrcs0;
-        unsigned long mrcs1;
-        unsigned long mrcs2;
-        unsigned long mrcs3;
-};
-struct sport_dev {
-        struct cdev cdev;       /* Char device structure */
-        int sport_num;
-        int dma_rx_chan;
+/*
-        int dma_tx_chan;
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
-        int rx_irq;
+ */
-        unsigned char *rx_buf;  /* Buffer store the received data */
+#define __BFP(m) u16 m; u16 __pad_##m
-        int rx_len;             /* How many bytes will be received */
+struct sport_register {
-        int rx_received;        /* How many bytes has been received */
+        __BFP(tcr1);
+        __BFP(tcr2);
-        int tx_irq;
+        __BFP(tclkdiv);
-        const unsigned char *tx_buf;
+        __BFP(tfsdiv);
-        int tx_len;
+        union {
-        int tx_sent;
+                u32 tx32;
+                u16 tx16;
-        int err_irq;
+        };
+        u32 __pad_tx;
-        struct mutex mutex;     /* mutual exclusion semaphore */
+        union {
-        struct task_struct *task;
+                u32 rx32;       /* use the anomaly wrapper below */
+                u16 rx16;
-        wait_queue_head_t waitq;
+        };
-        int     wait_con;
+        u32 __pad_rx;
-        struct sport_register *regs;
+        __BFP(rcr1);
-        struct sport_config config;
+        __BFP(rcr2);
+        __BFP(rclkdiv);
+        __BFP(rfsdiv);
+        __BFP(stat);
+        __BFP(chnl);
+        __BFP(mcmc1);
+        __BFP(mcmc2);
+        u32 mtcs0;
+        u32 mtcs1;
+        u32 mtcs2;
+        u32 mtcs3;
+        u32 mrcs0;
+        u32 mrcs1;
+        u32 mrcs2;
+        u32 mrcs3;
 };
+#undef __BFP
+#define bfin_read_sport_rx32(base) \
+({ \
+        struct sport_register *__mmrs = (void *)base; \
+        u32 __ret; \
+        unsigned long flags; \
+        if (ANOMALY_05000473) \
+                local_irq_save(flags); \
+        __ret = __mmrs->rx32; \
+        if (ANOMALY_05000473) \
+                local_irq_restore(flags); \
+        __ret; \
+})
 #endif
-#define SPORT_TCR1      0
+/* Workaround defBF*.h SPORT MMRs till they get cleansed */
-#define SPORT_TCR2      1
+#undef DTYPE_NORM
-#define SPORT_TCLKDIV   2
+#undef SLEN
-#define SPORT_TFSDIV    3
+#undef SP_WOFF
-#define SPORT_RCR1      8
+#undef SP_WSIZE
-#define SPORT_RCR2      9
-#define SPORT_RCLKDIV   10
+/* SPORT_TCR1 Masks */
-#define SPORT_RFSDIV    11
+#define TSPEN           0x0001  /* TX enable */
-#define SPORT_CHANNEL   13
+#define ITCLK           0x0002  /* Internal TX Clock Select */
-#define SPORT_MCMC1     14
+#define TDTYPE          0x000C  /* TX Data Formatting Select */
-#define SPORT_MCMC2     15
+#define DTYPE_NORM      0x0000  /* Data Format Normal */
-#define SPORT_MTCS0     16
+#define DTYPE_ULAW      0x0008  /* Compand Using u-Law */
-#define SPORT_MTCS1     17
+#define DTYPE_ALAW      0x000C  /* Compand Using A-Law */
-#define SPORT_MTCS2     18
+#define TLSBIT          0x0010  /* TX Bit Order */
-#define SPORT_MTCS3     19
+#define ITFS            0x0200  /* Internal TX Frame Sync Select */
-#define SPORT_MRCS0     20
+#define TFSR            0x0400  /* TX Frame Sync Required Select */
-#define SPORT_MRCS1     21
+#define DITFS           0x0800  /* Data Independent TX Frame Sync Select */
-#define SPORT_MRCS2     22
+#define LTFS            0x1000  /* Low TX Frame Sync Select */
-#define SPORT_MRCS3     23
+#define LATFS           0x2000  /* Late TX Frame Sync Select */
+#define TCKFE           0x4000  /* TX Clock Falling Edge Select */
+/* SPORT_TCR2 Masks */
+#define SLEN            0x001F  /* SPORT TX Word Length (2 - 31) */
+#define DP_SLEN(x)      BFIN_DEPOSIT(SLEN, x)
+#define EX_SLEN(x)      BFIN_EXTRACT(SLEN, x)
+#define TXSE            0x0100  /* TX Secondary Enable */
+#define TSFSE           0x0200  /* TX Stereo Frame Sync Enable */
+#define TRFST           0x0400  /* TX Right-First Data Order */
+/* SPORT_RCR1 Masks */
+#define RSPEN           0x0001  /* RX enable */
+#define IRCLK           0x0002  /* Internal RX Clock Select */
+#define RDTYPE          0x000C  /* RX Data Formatting Select */
+/* DTYPE_* defined above */
+#define RLSBIT          0x0010  /* RX Bit Order */
+#define IRFS            0x0200  /* Internal RX Frame Sync Select */
+#define RFSR            0x0400  /* RX Frame Sync Required Select */
+#define LRFS            0x1000  /* Low RX Frame Sync Select */
+#define LARFS           0x2000  /* Late RX Frame Sync Select */
+#define RCKFE           0x4000  /* RX Clock Falling Edge Select */
+/* SPORT_RCR2 Masks */
+/* SLEN defined above */
+#define RXSE            0x0100  /* RX Secondary Enable */
+#define RSFSE           0x0200  /* RX Stereo Frame Sync Enable */
+#define RRFST           0x0400  /* Right-First Data Order */
+/* SPORT_STAT Masks */
+#define RXNE            0x0001  /* RX FIFO Not Empty Status */
+#define RUVF            0x0002  /* RX Underflow Status */
+#define ROVF            0x0004  /* RX Overflow Status */
+#define TXF             0x0008  /* TX FIFO Full Status */
+#define TUVF            0x0010  /* TX Underflow Status */
+#define TOVF            0x0020  /* TX Overflow Status */
+#define TXHRE           0x0040  /* TX Hold Register Empty */
+/* SPORT_MCMC1 Masks */
+#define SP_WOFF         0x03FF  /* Multichannel Window Offset Field */
+#define DP_SP_WOFF(x)   BFIN_DEPOSIT(SP_WOFF, x)
+#define EX_SP_WOFF(x)   BFIN_EXTRACT(SP_WOFF, x)
+#define SP_WSIZE        0xF000  /* Multichannel Window Size Field */
+#define DP_SP_WSIZE(x)  BFIN_DEPOSIT(SP_WSIZE, x)
+#define EX_SP_WSIZE(x)  BFIN_EXTRACT(SP_WSIZE, x)
+/* SPORT_MCMC2 Masks */
+#define MCCRM           0x0003  /* Multichannel Clock Recovery Mode */
+#define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing */
+#define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing */
+#define MCMEN           0x0010  /* Multichannel Frame Mode Enable */
+#define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
+#define MFD             0xF000  /* Multichannel Frame Delay */
+#define DP_MFD(x)       BFIN_DEPOSIT(MFD, x)
+#define EX_MFD(x)       BFIN_EXTRACT(MFD, x)
 #endif
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 25906468622f..e521f8eb260a 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -12,6 +12,8 @@
 #include <mach/anomaly.h>
 #define MK_BMSK_(x) (1<<x)
+#define BFIN_DEPOSIT(mask, x)   (((x) << __ffs(mask)) & (mask))
+#define BFIN_EXTRACT(mask, x)   (((x) & (mask)) >> __ffs(mask))
 #ifndef __ASSEMBLY__

diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h index b558908e1c79..9626cf7e4251 100644 --- a/arch/blackfin/include/asm/bfin_sport.h +++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -1,7 +1,7 @@
1	/*	1	/*
2	* bfin_sport.h - userspace header for bfin sport driver	2	* bfin_sport.h - interface to Blackfin SPORTs
3	*	3	*
4	* Copyright 2004-2008 Analog Devices Inc.	4	* Copyright 2004-2009 Analog Devices Inc.
5	*	5	*
6	* Licensed under the GPL-2 or later.	6	* Licensed under the GPL-2 or later.
7	*/	7	*/
@@ -9,16 +9,6 @@
9	#ifndef __BFIN_SPORT_H__	9	#ifndef __BFIN_SPORT_H__
10	#define __BFIN_SPORT_H__	10	#define __BFIN_SPORT_H__
11		11
12	#ifdef __KERNEL__
13	#include <linux/cdev.h>
14	#include <linux/mutex.h>
15	#include <linux/sched.h>
16	#include <linux/wait.h>
17	#endif
18
19	#define SPORT_MAJOR 237
20	#define SPORT_NR_DEVS 2
21
22	/* Sport mode: it can be set to TDM, i2s or others */	12	/* Sport mode: it can be set to TDM, i2s or others */
23	#define NORM_MODE 0x0	13	#define NORM_MODE 0x0
24	#define TDM_MODE 0x1	14	#define TDM_MODE 0x1
@@ -35,7 +25,7 @@ struct sport_config {
35	unsigned int mode:3;	25	unsigned int mode:3;
36		26
37	/* if TDM mode is selected, channels must be set */	27	/* if TDM mode is selected, channels must be set */
38	int channels; /* Must be in 8 units */	28	int channels; /* Must be in 8 units */
39	unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */	29	unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
40		30
41	/* I2S mode */	31	/* I2S mode */
@@ -69,94 +59,137 @@ struct sport_config {
69		59
70	#ifdef __KERNEL__	60	#ifdef __KERNEL__
71		61
72	struct sport_register {	62	#include <linux/types.h>
73	unsigned short tcr1;
74	unsigned short reserved0;
75	unsigned short tcr2;
76	unsigned short reserved1;
77	unsigned short tclkdiv;
78	unsigned short reserved2;
79	unsigned short tfsdiv;
80	unsigned short reserved3;
81	unsigned long tx;
82	unsigned long reserved_l0;
83	unsigned long rx;
84	unsigned long reserved_l1;
85	unsigned short rcr1;
86	unsigned short reserved4;
87	unsigned short rcr2;
88	unsigned short reserved5;
89	unsigned short rclkdiv;
90	unsigned short reserved6;
91	unsigned short rfsdiv;
92	unsigned short reserved7;
93	unsigned short stat;
94	unsigned short reserved8;
95	unsigned short chnl;
96	unsigned short reserved9;
97	unsigned short mcmc1;
98	unsigned short reserved10;
99	unsigned short mcmc2;
100	unsigned short reserved11;
101	unsigned long mtcs0;
102	unsigned long mtcs1;
103	unsigned long mtcs2;
104	unsigned long mtcs3;
105	unsigned long mrcs0;
106	unsigned long mrcs1;
107	unsigned long mrcs2;
108	unsigned long mrcs3;
109	};
110
111	struct sport_dev {
112	struct cdev cdev; /* Char device structure */
113
114	int sport_num;
115		63
116	int dma_rx_chan;	64	/*
117	int dma_tx_chan;	65	* All Blackfin system MMRs are padded to 32bits even if the register
118		66	* itself is only 16bits. So use a helper macro to streamline this.
119	int rx_irq;	67	*/
120	unsigned char rx_buf; / Buffer store the received data */	68	#define __BFP(m) u16 m; u16 __pad_##m
121	int rx_len; /* How many bytes will be received */	69	struct sport_register {
122	int rx_received; /* How many bytes has been received */	70	__BFP(tcr1);
123		71	__BFP(tcr2);
124	int tx_irq;	72	__BFP(tclkdiv);
125	const unsigned char *tx_buf;	73	__BFP(tfsdiv);
126	int tx_len;	74	union {
127	int tx_sent;	75	u32 tx32;
128		76	u16 tx16;
129	int err_irq;	77	};
130		78	u32 __pad_tx;
131	struct mutex mutex; /* mutual exclusion semaphore */	79	union {
132	struct task_struct *task;	80	u32 rx32; /* use the anomaly wrapper below */
133		81	u16 rx16;
134	wait_queue_head_t waitq;	82	};
135	int wait_con;	83	u32 __pad_rx;
136	struct sport_register *regs;	84	__BFP(rcr1);
137	struct sport_config config;	85	__BFP(rcr2);
		86	__BFP(rclkdiv);
		87	__BFP(rfsdiv);
		88	__BFP(stat);
		89	__BFP(chnl);
		90	__BFP(mcmc1);
		91	__BFP(mcmc2);
		92	u32 mtcs0;
		93	u32 mtcs1;
		94	u32 mtcs2;
		95	u32 mtcs3;
		96	u32 mrcs0;
		97	u32 mrcs1;
		98	u32 mrcs2;
		99	u32 mrcs3;
138	};	100	};
		101	#undef __BFP
		102
		103	#define bfin_read_sport_rx32(base) \
		104	({ \
		105	struct sport_register __mmrs = (void )base; \
		106	u32 __ret; \
		107	unsigned long flags; \
		108	if (ANOMALY_05000473) \
		109	local_irq_save(flags); \
		110	__ret = __mmrs->rx32; \
		111	if (ANOMALY_05000473) \
		112	local_irq_restore(flags); \
		113	__ret; \
		114	})
139		115
140	#endif	116	#endif
141		117
142	#define SPORT_TCR1 0	118	/* Workaround defBF.h SPORT MMRs till they get cleansed /
143	#define SPORT_TCR2 1	119	#undef DTYPE_NORM
144	#define SPORT_TCLKDIV 2	120	#undef SLEN
145	#define SPORT_TFSDIV 3	121	#undef SP_WOFF
146	#define SPORT_RCR1 8	122	#undef SP_WSIZE
147	#define SPORT_RCR2 9	123
148	#define SPORT_RCLKDIV 10	124	/* SPORT_TCR1 Masks */
149	#define SPORT_RFSDIV 11	125	#define TSPEN 0x0001 /* TX enable */
150	#define SPORT_CHANNEL 13	126	#define ITCLK 0x0002 /* Internal TX Clock Select */
151	#define SPORT_MCMC1 14	127	#define TDTYPE 0x000C /* TX Data Formatting Select */
152	#define SPORT_MCMC2 15	128	#define DTYPE_NORM 0x0000 /* Data Format Normal */
153	#define SPORT_MTCS0 16	129	#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
154	#define SPORT_MTCS1 17	130	#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
155	#define SPORT_MTCS2 18	131	#define TLSBIT 0x0010 /* TX Bit Order */
156	#define SPORT_MTCS3 19	132	#define ITFS 0x0200 /* Internal TX Frame Sync Select */
157	#define SPORT_MRCS0 20	133	#define TFSR 0x0400 /* TX Frame Sync Required Select */
158	#define SPORT_MRCS1 21	134	#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
159	#define SPORT_MRCS2 22	135	#define LTFS 0x1000 /* Low TX Frame Sync Select */
160	#define SPORT_MRCS3 23	136	#define LATFS 0x2000 /* Late TX Frame Sync Select */
		137	#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
		138
		139	/* SPORT_TCR2 Masks */
		140	#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
		141	#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
		142	#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
		143	#define TXSE 0x0100 /* TX Secondary Enable */
		144	#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
		145	#define TRFST 0x0400 /* TX Right-First Data Order */
		146
		147	/* SPORT_RCR1 Masks */
		148	#define RSPEN 0x0001 /* RX enable */
		149	#define IRCLK 0x0002 /* Internal RX Clock Select */
		150	#define RDTYPE 0x000C /* RX Data Formatting Select */
		151	/* DTYPE_* defined above */
		152	#define RLSBIT 0x0010 /* RX Bit Order */
		153	#define IRFS 0x0200 /* Internal RX Frame Sync Select */
		154	#define RFSR 0x0400 /* RX Frame Sync Required Select */
		155	#define LRFS 0x1000 /* Low RX Frame Sync Select */
		156	#define LARFS 0x2000 /* Late RX Frame Sync Select */
		157	#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
		158
		159	/* SPORT_RCR2 Masks */
		160	/* SLEN defined above */
		161	#define RXSE 0x0100 /* RX Secondary Enable */
		162	#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
		163	#define RRFST 0x0400 /* Right-First Data Order */
		164
		165	/* SPORT_STAT Masks */
		166	#define RXNE 0x0001 /* RX FIFO Not Empty Status */
		167	#define RUVF 0x0002 /* RX Underflow Status */
		168	#define ROVF 0x0004 /* RX Overflow Status */
		169	#define TXF 0x0008 /* TX FIFO Full Status */
		170	#define TUVF 0x0010 /* TX Underflow Status */
		171	#define TOVF 0x0020 /* TX Overflow Status */
		172	#define TXHRE 0x0040 /* TX Hold Register Empty */
		173
		174	/* SPORT_MCMC1 Masks */
		175	#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
		176	#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
		177	#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
		178	#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
		179	#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
		180	#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
		181
		182	/* SPORT_MCMC2 Masks */
		183	#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
		184	#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
		185	#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
		186	#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
		187	#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
		188	#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
		189	#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
		190	#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
		191	#define MFD 0xF000 /* Multichannel Frame Delay */
		192	#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
		193	#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
161		194
162	#endif	195	#endif


diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h index 25906468622f..e521f8eb260a 100644 --- a/arch/blackfin/include/asm/def_LPBlackfin.h +++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -12,6 +12,8 @@
12	#include <mach/anomaly.h>	12	#include <mach/anomaly.h>
13		13
14	#define MK_BMSK_(x) (1<<x)	14	#define MK_BMSK_(x) (1<<x)
		15	#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
		16	#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
15		17
16	#ifndef __ASSEMBLY__	18	#ifndef __ASSEMBLY__
17		19