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-rw-r--r--arch/blackfin/include/asm/blackfin.h1
-rw-r--r--arch/blackfin/include/asm/cache.h4
-rw-r--r--arch/blackfin/include/asm/cacheflush.h10
-rw-r--r--arch/blackfin/include/asm/cplb.h32
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h13
-rw-r--r--arch/blackfin/include/asm/ipipe.h11
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h30
-rw-r--r--arch/blackfin/include/asm/irq.h7
-rw-r--r--arch/blackfin/include/asm/irqflags.h164
-rw-r--r--arch/blackfin/include/asm/mem_init.h88
-rw-r--r--arch/blackfin/include/asm/mem_map.h97
-rw-r--r--arch/blackfin/include/asm/system.h4
-rw-r--r--arch/blackfin/include/asm/traps.h4
-rw-r--r--arch/blackfin/include/asm/uaccess.h22
-rw-r--r--arch/blackfin/include/asm/unistd.h3
15 files changed, 381 insertions, 109 deletions
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index 8bb2cb139756..4d4439583396 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -86,6 +86,7 @@ static inline void CSYNC(void)
86 86
87#endif /* __ASSEMBLY__ */ 87#endif /* __ASSEMBLY__ */
88 88
89#include <asm/mem_map.h>
89#include <mach/blackfin.h> 90#include <mach/blackfin.h>
90#include <asm/bfin-global.h> 91#include <asm/bfin-global.h>
91 92
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 2ef669ed9222..477050ad5c53 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -35,10 +35,10 @@
35 35
36#if defined(CONFIG_SMP) && \ 36#if defined(CONFIG_SMP) && \
37 !defined(CONFIG_BFIN_CACHE_COHERENT) 37 !defined(CONFIG_BFIN_CACHE_COHERENT)
38# if defined(CONFIG_BFIN_ICACHE) 38# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
39# define __ARCH_SYNC_CORE_ICACHE 39# define __ARCH_SYNC_CORE_ICACHE
40# endif 40# endif
41# if defined(CONFIG_BFIN_DCACHE) 41# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
42# define __ARCH_SYNC_CORE_DCACHE 42# define __ARCH_SYNC_CORE_DCACHE
43# endif 43# endif
44#ifndef __ASSEMBLY__ 44#ifndef __ASSEMBLY__
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 5c17dee53b5d..7e55549e180f 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void);
56 56
57static inline void flush_icache_range(unsigned start, unsigned end) 57static inline void flush_icache_range(unsigned start, unsigned end)
58{ 58{
59#if defined(CONFIG_BFIN_WB) 59#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
60 blackfin_dcache_flush_range(start, end); 60 blackfin_dcache_flush_range(start, end);
61#endif 61#endif
62 62
@@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \
87#else 87#else
88# define invalidate_dcache_range(start,end) do { } while (0) 88# define invalidate_dcache_range(start,end) do { } while (0)
89#endif 89#endif
90#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) 90#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
91# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) 91# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
92# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) 92# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
93#else 93#else
94# define flush_dcache_range(start,end) do { } while (0) 94# define flush_dcache_range(start,end) do { } while (0)
95# define flush_dcache_page(page) do { } while (0) 95# define flush_dcache_page(page) do { } while (0)
@@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on;
100 100
101static inline int bfin_addr_dcacheable(unsigned long addr) 101static inline int bfin_addr_dcacheable(unsigned long addr)
102{ 102{
103#ifdef CONFIG_BFIN_DCACHE 103#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
104 if (addr < (_ramend - DMA_UNCACHED_REGION)) 104 if (addr < (_ramend - DMA_UNCACHED_REGION))
105 return 1; 105 return 1;
106#endif 106#endif
@@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr)
109 addr >= _ramend && addr < physical_mem_end) 109 addr >= _ramend && addr < physical_mem_end)
110 return 1; 110 return 1;
111 111
112#ifndef CONFIG_BFIN_L2_NOT_CACHED 112#ifdef CONFIG_BFIN_L2_DCACHEABLE
113 if (addr >= L2_START && addr < L2_START + L2_LENGTH) 113 if (addr >= L2_START && addr < L2_START + L2_LENGTH)
114 return 1; 114 return 1;
115#endif 115#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index a75a6a9f0949..c5dacf8f8cf9 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -37,8 +37,6 @@
37#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) 37#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
38#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) 38#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
39 39
40/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
41
42#if ANOMALY_05000158 40#if ANOMALY_05000158
43#define ANOMALY_05000158_WORKAROUND 0x200 41#define ANOMALY_05000158_WORKAROUND 0x200
44#else 42#else
@@ -47,10 +45,12 @@
47 45
48#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) 46#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
49 47
50#ifdef CONFIG_BFIN_WB /*Write Back Policy */ 48#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
51#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) 49#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
52#else /*Write Through */ 50#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
53#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) 51#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
52#else
53#define SDRAM_DGENERIC (CPLB_COMMON)
54#endif 54#endif
55 55
56#define SDRAM_DNON_CHBL (CPLB_COMMON) 56#define SDRAM_DNON_CHBL (CPLB_COMMON)
@@ -61,21 +61,23 @@
61 61
62#ifdef CONFIG_SMP 62#ifdef CONFIG_SMP
63#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) 63#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
64#define L2_IMEMORY (CPLB_COMMON) 64#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
65#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) 65#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
66 66
67#else 67#else
68#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) 68#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
69#define L2_IMEMORY (SDRAM_IGENERIC) 69# if defined(CONFIG_BFIN_L2_ICACHEABLE)
70 70# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
71# if defined(CONFIG_BFIN_L2_WB) 71# else
72# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) 72# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
73# elif defined(CONFIG_BFIN_L2_WT) 73# endif
74# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) 74
75# elif defined(CONFIG_BFIN_L2_NOT_CACHED) 75# if defined(CONFIG_BFIN_L2_WRITEBACK)
76# define L2_DMEMORY (CPLB_COMMON) 76# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
77# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
78# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
77# else 79# else
78# define L2_DMEMORY (0) 80# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
79# endif 81# endif
80#endif /* CONFIG_SMP */ 82#endif /* CONFIG_SMP */
81 83
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index d7d9148e433c..ed6b1f3cccce 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -95,4 +95,17 @@ static inline void dma_sync_single_for_device(struct device *dev,
95 enum dma_data_direction dir) 95 enum dma_data_direction dir)
96{ 96{
97} 97}
98
99static inline void dma_sync_sg_for_cpu(struct device *dev,
100 struct scatterlist *sg,
101 int nents, enum dma_data_direction dir)
102{
103}
104
105static inline void dma_sync_sg_for_device(struct device *dev,
106 struct scatterlist *sg,
107 int nents, enum dma_data_direction dir)
108{
109}
110
98#endif /* _BLACKFIN_DMA_MAPPING_H */ 111#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index bbe1c3726b69..87ba9ad399cb 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37 37
38#define IPIPE_ARCH_STRING "1.10-00" 38#define IPIPE_ARCH_STRING "1.11-00"
39#define IPIPE_MAJOR_NUMBER 1 39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 10 40#define IPIPE_MINOR_NUMBER 11
41#define IPIPE_PATCH_NUMBER 0 41#define IPIPE_PATCH_NUMBER 0
42 42
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -207,7 +207,7 @@ void ipipe_init_irq_threads(void);
207 207
208int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); 208int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
209 209
210#ifdef CONFIG_GENERIC_CLOCKEVENTS 210#ifdef CONFIG_TICKSOURCE_CORETMR
211#define IRQ_SYSTMR IRQ_CORETMR 211#define IRQ_SYSTMR IRQ_CORETMR
212#define IRQ_PRIOTMR IRQ_CORETMR 212#define IRQ_PRIOTMR IRQ_CORETMR
213#else 213#else
@@ -240,8 +240,13 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
240#define ipipe_init_irq_threads() do { } while (0) 240#define ipipe_init_irq_threads() do { } while (0)
241#define ipipe_start_irq_thread(irq, desc) 0 241#define ipipe_start_irq_thread(irq, desc) 0
242 242
243#ifndef CONFIG_TICKSOURCE_GPTMR0
243#define IRQ_SYSTMR IRQ_CORETMR 244#define IRQ_SYSTMR IRQ_CORETMR
244#define IRQ_PRIOTMR IRQ_CORETMR 245#define IRQ_PRIOTMR IRQ_CORETMR
246#else
247#define IRQ_SYSTMR IRQ_TIMER0
248#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
249#endif
245 250
246#define __ipipe_root_tick_p(regs) 1 251#define __ipipe_root_tick_p(regs) 1
247 252
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index 3e8acbd1a3be..490098f532a7 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -51,23 +51,23 @@
51 51
52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
53 53
54static inline void __ipipe_stall_root(void) 54#define __ipipe_stall_root() \
55{ 55 do { \
56 volatile unsigned long *p = &__ipipe_root_status; 56 volatile unsigned long *p = &__ipipe_root_status; \
57 set_bit(0, p); 57 set_bit(0, p); \
58} 58 } while (0)
59 59
60static inline unsigned long __ipipe_test_and_stall_root(void) 60#define __ipipe_test_and_stall_root() \
61{ 61 ({ \
62 volatile unsigned long *p = &__ipipe_root_status; 62 volatile unsigned long *p = &__ipipe_root_status; \
63 return test_and_set_bit(0, p); 63 test_and_set_bit(0, p); \
64} 64 })
65 65
66static inline unsigned long __ipipe_test_root(void) 66#define __ipipe_test_root() \
67{ 67 ({ \
68 const unsigned long *p = &__ipipe_root_status; 68 const unsigned long *p = &__ipipe_root_status; \
69 return test_bit(0, p); 69 test_bit(0, p); \
70} 70 })
71 71
72#endif /* !__ASSEMBLY__ */ 72#endif /* !__ASSEMBLY__ */
73 73
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 9a7f63a83c47..42a15f5ce0d0 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -22,13 +22,6 @@
22/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ 22/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
23#include <mach/irq.h> 23#include <mach/irq.h>
24 24
25/* Xenomai IPIPE helpers */
26#define local_irq_restore_hw(x) local_irq_restore(x)
27#define local_irq_save_hw(x) local_irq_save(x)
28#define local_irq_enable_hw(x) local_irq_enable(x)
29#define local_irq_disable_hw(x) local_irq_disable(x)
30#define irqs_disabled_hw(x) irqs_disabled(x)
31
32#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) 25#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
33# define NOP_PAD_ANOMALY_05000244 "nop; nop;" 26# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
34#else 27#else
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 139cba4651b1..9b19a19d9ae9 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -31,6 +31,150 @@ static inline unsigned long bfin_cli(void)
31 return flags; 31 return flags;
32} 32}
33 33
34#ifdef CONFIG_IPIPE
35
36#include <linux/ipipe_base.h>
37#include <linux/ipipe_trace.h>
38
39#ifdef CONFIG_DEBUG_HWERR
40# define bfin_no_irqs 0x3f
41#else
42# define bfin_no_irqs 0x1f
43#endif
44
45#define raw_local_irq_disable() \
46 do { \
47 ipipe_check_context(ipipe_root_domain); \
48 __ipipe_stall_root(); \
49 barrier(); \
50 } while (0)
51
52static inline void raw_local_irq_enable(void)
53{
54 barrier();
55 ipipe_check_context(ipipe_root_domain);
56 __ipipe_unstall_root();
57}
58
59#define raw_local_save_flags_ptr(x) \
60 do { \
61 *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \
62 } while (0)
63
64#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x))
65
66#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs)
67
68#define raw_local_irq_save_ptr(x) \
69 do { \
70 *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \
71 barrier(); \
72 } while (0)
73
74#define raw_local_irq_save(x) \
75 do { \
76 ipipe_check_context(ipipe_root_domain); \
77 raw_local_irq_save_ptr(&(x)); \
78 } while (0)
79
80static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
81{
82 /*
83 * Merge virtual and real interrupt mask bits into a single
84 * 32bit word.
85 */
86 return (real & ~(1 << 31)) | ((virt != 0) << 31);
87}
88
89static inline int raw_demangle_irq_bits(unsigned long *x)
90{
91 int virt = (*x & (1 << 31)) != 0;
92 *x &= ~(1L << 31);
93 return virt;
94}
95
96static inline void local_irq_disable_hw_notrace(void)
97{
98 bfin_cli();
99}
100
101static inline void local_irq_enable_hw_notrace(void)
102{
103 bfin_sti(bfin_irq_flags);
104}
105
106#define local_save_flags_hw(flags) \
107 do { \
108 (flags) = bfin_read_IMASK(); \
109 } while (0)
110
111#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0)
112
113#define irqs_disabled_hw() \
114 ({ \
115 unsigned long flags; \
116 local_save_flags_hw(flags); \
117 irqs_disabled_flags_hw(flags); \
118 })
119
120static inline void local_irq_save_ptr_hw(unsigned long *flags)
121{
122 *flags = bfin_cli();
123#ifdef CONFIG_DEBUG_HWERR
124 bfin_sti(0x3f);
125#endif
126}
127
128#define local_irq_save_hw_notrace(flags) \
129 do { \
130 local_irq_save_ptr_hw(&(flags)); \
131 } while (0)
132
133static inline void local_irq_restore_hw_notrace(unsigned long flags)
134{
135 if (!irqs_disabled_flags_hw(flags))
136 local_irq_enable_hw_notrace();
137}
138
139#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
140# define local_irq_disable_hw() \
141 do { \
142 if (!irqs_disabled_hw()) { \
143 local_irq_disable_hw_notrace(); \
144 ipipe_trace_begin(0x80000000); \
145 } \
146 } while (0)
147# define local_irq_enable_hw() \
148 do { \
149 if (irqs_disabled_hw()) { \
150 ipipe_trace_end(0x80000000); \
151 local_irq_enable_hw_notrace(); \
152 } \
153 } while (0)
154# define local_irq_save_hw(flags) \
155 do { \
156 local_save_flags_hw(flags); \
157 if (!irqs_disabled_flags_hw(flags)) { \
158 local_irq_disable_hw_notrace(); \
159 ipipe_trace_begin(0x80000001); \
160 } \
161 } while (0)
162# define local_irq_restore_hw(flags) \
163 do { \
164 if (!irqs_disabled_flags_hw(flags)) { \
165 ipipe_trace_end(0x80000001); \
166 local_irq_enable_hw_notrace(); \
167 } \
168 } while (0)
169#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
170# define local_irq_disable_hw() local_irq_disable_hw_notrace()
171# define local_irq_enable_hw() local_irq_enable_hw_notrace()
172# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags)
173# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags)
174#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
175
176#else /* CONFIG_IPIPE */
177
34static inline void raw_local_irq_disable(void) 178static inline void raw_local_irq_disable(void)
35{ 179{
36 bfin_cli(); 180 bfin_cli();
@@ -44,12 +188,6 @@ static inline void raw_local_irq_enable(void)
44 188
45#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) 189#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0)
46 190
47static inline void raw_local_irq_restore(unsigned long flags)
48{
49 if (!raw_irqs_disabled_flags(flags))
50 raw_local_irq_enable();
51}
52
53static inline unsigned long __raw_local_irq_save(void) 191static inline unsigned long __raw_local_irq_save(void)
54{ 192{
55 unsigned long flags = bfin_cli(); 193 unsigned long flags = bfin_cli();
@@ -60,4 +198,18 @@ static inline unsigned long __raw_local_irq_save(void)
60} 198}
61#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) 199#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
62 200
201#define local_irq_save_hw(flags) raw_local_irq_save(flags)
202#define local_irq_restore_hw(flags) raw_local_irq_restore(flags)
203#define local_irq_enable_hw() raw_local_irq_enable()
204#define local_irq_disable_hw() raw_local_irq_disable()
205#define irqs_disabled_hw() irqs_disabled()
206
207#endif /* !CONFIG_IPIPE */
208
209static inline void raw_local_irq_restore(unsigned long flags)
210{
211 if (!raw_irqs_disabled_flags(flags))
212 raw_local_irq_enable();
213}
214
63#endif 215#endif
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 61f7487fbf12..4179e329b9c9 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -59,7 +59,7 @@
59#define SDRAM_tRP TRP_1 59#define SDRAM_tRP TRP_1
60#define SDRAM_tRP_num 1 60#define SDRAM_tRP_num 1
61#define SDRAM_tRAS TRAS_4 61#define SDRAM_tRAS TRAS_4
62#define SDRAM_tRAS_num 3 62#define SDRAM_tRAS_num 4
63#define SDRAM_tRCD TRCD_1 63#define SDRAM_tRCD TRCD_1
64#define SDRAM_tWR TWR_2 64#define SDRAM_tWR TWR_2
65#endif 65#endif
@@ -89,6 +89,85 @@
89#endif 89#endif
90#endif 90#endif
91 91
92/*
93 * The BF526-EZ-Board changed SDRAM chips between revisions,
94 * so we use below timings to accommodate both.
95 */
96#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
97#if (CONFIG_SCLK_HZ > 119402985)
98#define SDRAM_tRP TRP_2
99#define SDRAM_tRP_num 2
100#define SDRAM_tRAS TRAS_8
101#define SDRAM_tRAS_num 8
102#define SDRAM_tRCD TRCD_2
103#define SDRAM_tWR TWR_2
104#endif
105#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
106#define SDRAM_tRP TRP_2
107#define SDRAM_tRP_num 2
108#define SDRAM_tRAS TRAS_7
109#define SDRAM_tRAS_num 7
110#define SDRAM_tRCD TRCD_2
111#define SDRAM_tWR TWR_2
112#endif
113#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
114#define SDRAM_tRP TRP_2
115#define SDRAM_tRP_num 2
116#define SDRAM_tRAS TRAS_6
117#define SDRAM_tRAS_num 6
118#define SDRAM_tRCD TRCD_2
119#define SDRAM_tWR TWR_2
120#endif
121#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
122#define SDRAM_tRP TRP_2
123#define SDRAM_tRP_num 2
124#define SDRAM_tRAS TRAS_5
125#define SDRAM_tRAS_num 5
126#define SDRAM_tRCD TRCD_2
127#define SDRAM_tWR TWR_2
128#endif
129#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
130#define SDRAM_tRP TRP_2
131#define SDRAM_tRP_num 2
132#define SDRAM_tRAS TRAS_4
133#define SDRAM_tRAS_num 4
134#define SDRAM_tRCD TRCD_2
135#define SDRAM_tWR TWR_2
136#endif
137#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
138#define SDRAM_tRP TRP_2
139#define SDRAM_tRP_num 2
140#define SDRAM_tRAS TRAS_4
141#define SDRAM_tRAS_num 4
142#define SDRAM_tRCD TRCD_1
143#define SDRAM_tWR TWR_2
144#endif
145#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
146#define SDRAM_tRP TRP_2
147#define SDRAM_tRP_num 2
148#define SDRAM_tRAS TRAS_3
149#define SDRAM_tRAS_num 3
150#define SDRAM_tRCD TRCD_1
151#define SDRAM_tWR TWR_2
152#endif
153#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
154#define SDRAM_tRP TRP_1
155#define SDRAM_tRP_num 1
156#define SDRAM_tRAS TRAS_3
157#define SDRAM_tRAS_num 3
158#define SDRAM_tRCD TRCD_1
159#define SDRAM_tWR TWR_2
160#endif
161#if (CONFIG_SCLK_HZ <= 29850746)
162#define SDRAM_tRP TRP_1
163#define SDRAM_tRP_num 1
164#define SDRAM_tRAS TRAS_2
165#define SDRAM_tRAS_num 2
166#define SDRAM_tRCD TRCD_1
167#define SDRAM_tWR TWR_2
168#endif
169#endif
170
92#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ 171#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
93 defined(CONFIG_MEM_MT48LC8M32B2B5_7) 172 defined(CONFIG_MEM_MT48LC8M32B2B5_7)
94 /*SDRAM INFORMATION: */ 173 /*SDRAM INFORMATION: */
@@ -109,6 +188,13 @@
109#define SDRAM_CL CL_3 188#define SDRAM_CL CL_3
110#endif 189#endif
111 190
191#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
192 /*SDRAM INFORMATION: */
193#define SDRAM_Tref 64 /* Refresh period in milliseconds */
194#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
195#define SDRAM_CL CL_2
196#endif
197
112 198
113#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC 199#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
114/* Equation from section 17 (p17-46) of BF533 HRM */ 200/* Equation from section 17 (p17-46) of BF533 HRM */
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
index e92b31051bb7..5e21627c9ba2 100644
--- a/arch/blackfin/include/asm/mem_map.h
+++ b/arch/blackfin/include/asm/mem_map.h
@@ -1,87 +1,84 @@
1/* 1/*
2 * mem_map.h 2 * Common Blackfin memory map
3 * Common header file for blackfin family of processors.
4 * 3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
5 */ 6 */
6 7
7#ifndef _MEM_MAP_H_ 8#ifndef __BFIN_MEM_MAP_H__
8#define _MEM_MAP_H_ 9#define __BFIN_MEM_MAP_H__
9 10
10#include <mach/mem_map.h> 11#include <mach/mem_map.h>
11 12
12#ifndef __ASSEMBLY__ 13/* Every Blackfin so far has MMRs like this */
14#ifndef COREMMR_BASE
15# define COREMMR_BASE 0xFFE00000
16#endif
17#ifndef SYSMMR_BASE
18# define SYSMMR_BASE 0xFFC00000
19#endif
13 20
14#ifdef CONFIG_SMP 21/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
15static inline ulong get_l1_scratch_start_cpu(int cpu) 22#ifndef L1_SCRATCH_START
16{ 23# define L1_SCRATCH_START 0xFFB00000
17 return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; 24# define L1_SCRATCH_LENGTH 0x1000
18} 25#endif
19static inline ulong get_l1_code_start_cpu(int cpu)
20{
21 return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START;
22}
23static inline ulong get_l1_data_a_start_cpu(int cpu)
24{
25 return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
26}
27static inline ulong get_l1_data_b_start_cpu(int cpu)
28{
29 return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
30}
31 26
32static inline ulong get_l1_scratch_start(void) 27/* Most parts lack on-chip L2 SRAM */
33{ 28#ifndef L2_START
34 return get_l1_scratch_start_cpu(blackfin_core_id()); 29# define L2_START 0
35} 30# define L2_LENGTH 0
36static inline ulong get_l1_code_start(void) 31#endif
37{ 32
38 return get_l1_code_start_cpu(blackfin_core_id()); 33/* Most parts lack on-chip L1 ROM */
39} 34#ifndef L1_ROM_START
40static inline ulong get_l1_data_a_start(void) 35# define L1_ROM_START 0
41{ 36# define L1_ROM_LENGTH 0
42 return get_l1_data_a_start_cpu(blackfin_core_id()); 37#endif
43} 38
44static inline ulong get_l1_data_b_start(void) 39/* Allow wonky SMP ports to override this */
45{ 40#ifndef GET_PDA_SAFE
46 return get_l1_data_b_start_cpu(blackfin_core_id()); 41# define GET_PDA_SAFE(preg) \
47} 42 preg.l = _cpu_pda; \
43 preg.h = _cpu_pda;
44# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
48 45
49#else /* !CONFIG_SMP */ 46# ifndef __ASSEMBLY__
50 47
51static inline ulong get_l1_scratch_start_cpu(int cpu) 48static inline unsigned long get_l1_scratch_start_cpu(int cpu)
52{ 49{
53 return L1_SCRATCH_START; 50 return L1_SCRATCH_START;
54} 51}
55static inline ulong get_l1_code_start_cpu(int cpu) 52static inline unsigned long get_l1_code_start_cpu(int cpu)
56{ 53{
57 return L1_CODE_START; 54 return L1_CODE_START;
58} 55}
59static inline ulong get_l1_data_a_start_cpu(int cpu) 56static inline unsigned long get_l1_data_a_start_cpu(int cpu)
60{ 57{
61 return L1_DATA_A_START; 58 return L1_DATA_A_START;
62} 59}
63static inline ulong get_l1_data_b_start_cpu(int cpu) 60static inline unsigned long get_l1_data_b_start_cpu(int cpu)
64{ 61{
65 return L1_DATA_B_START; 62 return L1_DATA_B_START;
66} 63}
67static inline ulong get_l1_scratch_start(void) 64static inline unsigned long get_l1_scratch_start(void)
68{ 65{
69 return get_l1_scratch_start_cpu(0); 66 return get_l1_scratch_start_cpu(0);
70} 67}
71static inline ulong get_l1_code_start(void) 68static inline unsigned long get_l1_code_start(void)
72{ 69{
73 return get_l1_code_start_cpu(0); 70 return get_l1_code_start_cpu(0);
74} 71}
75static inline ulong get_l1_data_a_start(void) 72static inline unsigned long get_l1_data_a_start(void)
76{ 73{
77 return get_l1_data_a_start_cpu(0); 74 return get_l1_data_a_start_cpu(0);
78} 75}
79static inline ulong get_l1_data_b_start(void) 76static inline unsigned long get_l1_data_b_start(void)
80{ 77{
81 return get_l1_data_b_start_cpu(0); 78 return get_l1_data_b_start_cpu(0);
82} 79}
83 80
84#endif /* CONFIG_SMP */ 81# endif /* __ASSEMBLY__ */
85#endif /* __ASSEMBLY__ */ 82#endif /* !GET_PDA_SAFE */
86 83
87#endif /* _MEM_MAP_H_ */ 84#endif
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index 294dbda24164..85e8f16cf8c2 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -135,11 +135,13 @@ struct __xchg_dummy {
135}; 135};
136#define __xg(x) ((volatile struct __xchg_dummy *)(x)) 136#define __xg(x) ((volatile struct __xchg_dummy *)(x))
137 137
138#include <mach/blackfin.h>
139
138static inline unsigned long __xchg(unsigned long x, volatile void *ptr, 140static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
139 int size) 141 int size)
140{ 142{
141 unsigned long tmp = 0; 143 unsigned long tmp = 0;
142 unsigned long flags = 0; 144 unsigned long flags;
143 145
144 local_irq_save_hw(flags); 146 local_irq_save_hw(flags);
145 147
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
index 34f7295fb070..3cdc454cde23 100644
--- a/arch/blackfin/include/asm/traps.h
+++ b/arch/blackfin/include/asm/traps.h
@@ -111,9 +111,7 @@
111 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" 111 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
112#define EXC_0x2A(level) \ 112#define EXC_0x2A(level) \
113 "Instruction fetch misaligned address violation\n" \ 113 "Instruction fetch misaligned address violation\n" \
114 level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ 114 level " - Attempted misaligned instruction cache fetch.\n"
115 level " exception, the return address provided in RETX is the destination address which is\n" \
116 level " misaligned, rather than the address of the offending instruction.\n"
117#define EXC_0x2B(level) \ 115#define EXC_0x2B(level) \
118 "CPLB protection violation\n" \ 116 "CPLB protection violation\n" \
119 level " - Illegal instruction fetch access (memory protection violation).\n" 117 level " - Illegal instruction fetch access (memory protection violation).\n"
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
index 8894e9ffbb57..2f469a1f80fb 100644
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -265,4 +265,26 @@ __clear_user(void *to, unsigned long n)
265 265
266#define clear_user(to, n) __clear_user(to, n) 266#define clear_user(to, n) __clear_user(to, n)
267 267
268/* How to interpret these return values:
269 * CORE: can be accessed by core load or dma memcpy
270 * CORE_ONLY: can only be accessed by core load
271 * DMA: can only be accessed by dma memcpy
272 * IDMA: can only be accessed by interprocessor dma memcpy (BF561)
273 * ITEST: can be accessed by isram memcpy or dma memcpy
274 */
275enum {
276 BFIN_MEM_ACCESS_CORE = 0,
277 BFIN_MEM_ACCESS_CORE_ONLY,
278 BFIN_MEM_ACCESS_DMA,
279 BFIN_MEM_ACCESS_IDMA,
280 BFIN_MEM_ACCESS_ITEST,
281};
282/**
283 * bfin_mem_access_type() - what kind of memory access is required
284 * @addr: the address to check
285 * @size: number of bytes needed
286 * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above)
287 */
288int bfin_mem_access_type(unsigned long addr, unsigned long size);
289
268#endif /* _BLACKFIN_UACCESS_H */ 290#endif /* _BLACKFIN_UACCESS_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index da35133c171d..c8e7ee4768cd 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -381,8 +381,9 @@
381#define __NR_preadv 366 381#define __NR_preadv 366
382#define __NR_pwritev 367 382#define __NR_pwritev 367
383#define __NR_rt_tgsigqueueinfo 368 383#define __NR_rt_tgsigqueueinfo 368
384#define __NR_perf_counter_open 369
384 385
385#define __NR_syscall 369 386#define __NR_syscall 370
386#define NR_syscalls __NR_syscall 387#define NR_syscalls __NR_syscall
387 388
388/* Old optional stuff no one actually uses */ 389/* Old optional stuff no one actually uses */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 22:57:15 -0500