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-rw-r--r--arch/blackfin/include/asm/bfin_dma.h91
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h275
-rw-r--r--arch/blackfin/include/asm/bitops.h2
-rw-r--r--arch/blackfin/include/asm/cache.h2
-rw-r--r--arch/blackfin/include/asm/cacheflush.h3
-rw-r--r--arch/blackfin/include/asm/dma.h37
-rw-r--r--arch/blackfin/include/asm/dpmc.h2
-rw-r--r--arch/blackfin/include/asm/io.h268
-rw-r--r--arch/blackfin/include/asm/irqflags.h3
-rw-r--r--arch/blackfin/include/asm/processor.h4
-rw-r--r--arch/blackfin/include/asm/spinlock.h28
-rw-r--r--arch/blackfin/include/mach-common/pll.h86
-rw-r--r--arch/blackfin/include/mach-common/ports-a.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-b.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-c.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-d.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-e.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-f.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-g.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-h.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-i.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-j.h25
22 files changed, 769 insertions, 282 deletions
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
new file mode 100644
index 000000000000..d51120744148
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -0,0 +1,91 @@
1/*
2 * bfin_dma.h - Blackfin DMA defines/structures/etc...
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_DMA_H__
10#define __ASM_BFIN_DMA_H__
11
12#include <linux/types.h>
13
14/* DMA_CONFIG Masks */
15#define DMAEN 0x0001 /* DMA Channel Enable */
16#define WNR 0x0002 /* Channel Direction (W/R*) */
17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
18#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
19#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
20#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
21#define RESTART 0x0020 /* DMA Buffer Clear */
22#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
23#define DI_EN 0x0080 /* Data Interrupt Enable */
24#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
25#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
26#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
27#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
28#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
29#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
30#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
31#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
32#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
33#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
34#define NDSIZE 0x0f00 /* Next Descriptor Size */
35#define DMAFLOW 0x7000 /* Flow Control */
36#define DMAFLOW_STOP 0x0000 /* Stop Mode */
37#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
38#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
39#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
40#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
41
42/* DMA_IRQ_STATUS Masks */
43#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
44#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
45#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
46#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
47
48/*
49 * All Blackfin system MMRs are padded to 32bits even if the register
50 * itself is only 16bits. So use a helper macro to streamline this.
51 */
52#define __BFP(m) u16 m; u16 __pad_##m
53
54/*
55 * bfin dma registers layout
56 */
57struct bfin_dma_regs {
58 u32 next_desc_ptr;
59 u32 start_addr;
60 __BFP(config);
61 u32 __pad0;
62 __BFP(x_count);
63 __BFP(x_modify);
64 __BFP(y_count);
65 __BFP(y_modify);
66 u32 curr_desc_ptr;
67 u32 curr_addr;
68 __BFP(irq_status);
69 __BFP(peripheral_map);
70 __BFP(curr_x_count);
71 u32 __pad1;
72 __BFP(curr_y_count);
73 u32 __pad2;
74};
75
76/*
77 * bfin handshake mdma registers layout
78 */
79struct bfin_hmdma_regs {
80 __BFP(control);
81 __BFP(ecinit);
82 __BFP(bcinit);
83 __BFP(ecurgent);
84 __BFP(ecoverflow);
85 __BFP(ecount);
86 __BFP(bcount);
87};
88
89#undef __BFP
90
91#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644
index 000000000000..1ff9f1468c02
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,275 @@
1/*
2 * bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_ASM_SERIAL_H__
10#define __BFIN_ASM_SERIAL_H__
11
12#include <linux/serial_core.h>
13#include <mach/anomaly.h>
14#include <mach/bfin_serial.h>
15
16#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
17 defined(CONFIG_BFIN_UART1_CTSRTS) || \
18 defined(CONFIG_BFIN_UART2_CTSRTS) || \
19 defined(CONFIG_BFIN_UART3_CTSRTS)
20# ifdef BFIN_UART_BF54X_STYLE
21# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
22# else
23# define CONFIG_SERIAL_BFIN_CTSRTS
24# endif
25#endif
26
27struct circ_buf;
28struct timer_list;
29struct work_struct;
30
31struct bfin_serial_port {
32 struct uart_port port;
33 unsigned int old_status;
34 int status_irq;
35#ifndef BFIN_UART_BF54X_STYLE
36 unsigned int lsr;
37#endif
38#ifdef CONFIG_SERIAL_BFIN_DMA
39 int tx_done;
40 int tx_count;
41 struct circ_buf rx_dma_buf;
42 struct timer_list rx_dma_timer;
43 int rx_dma_nrows;
44 unsigned int tx_dma_channel;
45 unsigned int rx_dma_channel;
46 struct work_struct tx_dma_workqueue;
47#elif ANOMALY_05000363
48 unsigned int anomaly_threshold;
49#endif
50#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
51 int scts;
52#endif
53#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
54 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
55 int cts_pin;
56 int rts_pin;
57#endif
58};
59
60/* UART_LCR Masks */
61#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
62#define STB 0x04 /* Stop Bits */
63#define PEN 0x08 /* Parity Enable */
64#define EPS 0x10 /* Even Parity Select */
65#define STP 0x20 /* Stick Parity */
66#define SB 0x40 /* Set Break */
67#define DLAB 0x80 /* Divisor Latch Access */
68
69/* UART_LSR Masks */
70#define DR 0x01 /* Data Ready */
71#define OE 0x02 /* Overrun Error */
72#define PE 0x04 /* Parity Error */
73#define FE 0x08 /* Framing Error */
74#define BI 0x10 /* Break Interrupt */
75#define THRE 0x20 /* THR Empty */
76#define TEMT 0x40 /* TSR and UART_THR Empty */
77#define TFI 0x80 /* Transmission Finished Indicator */
78
79/* UART_IER Masks */
80#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
81#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
82#define ELSI 0x04 /* Enable RX Status Interrupt */
83#define EDSSI 0x08 /* Enable Modem Status Interrupt */
84#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
85#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
86#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
87
88/* UART_MCR Masks */
89#define XOFF 0x01 /* Transmitter Off */
90#define MRTS 0x02 /* Manual Request To Send */
91#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
92#define RFRT 0x08 /* Receive FIFO RTS Threshold */
93#define LOOP_ENA 0x10 /* Loopback Mode Enable */
94#define FCPOL 0x20 /* Flow Control Pin Polarity */
95#define ARTS 0x40 /* Automatic Request To Send */
96#define ACTS 0x80 /* Automatic Clear To Send */
97
98/* UART_MSR Masks */
99#define SCTS 0x01 /* Sticky CTS */
100#define CTS 0x10 /* Clear To Send */
101#define RFCS 0x20 /* Receive FIFO Count Status */
102
103/* UART_GCTL Masks */
104#define UCEN 0x01 /* Enable UARTx Clocks */
105#define IREN 0x02 /* Enable IrDA Mode */
106#define TPOLC 0x04 /* IrDA TX Polarity Change */
107#define RPOLC 0x08 /* IrDA RX Polarity Change */
108#define FPE 0x10 /* Force Parity Error On Transmit */
109#define FFE 0x20 /* Force Framing Error On Transmit */
110
111#ifdef BFIN_UART_BF54X_STYLE
112# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
113# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
114# define OFFSET_GCTL 0x08 /* Global Control Register */
115# define OFFSET_LCR 0x0C /* Line Control Register */
116# define OFFSET_MCR 0x10 /* Modem Control Register */
117# define OFFSET_LSR 0x14 /* Line Status Register */
118# define OFFSET_MSR 0x18 /* Modem Status Register */
119# define OFFSET_SCR 0x1C /* SCR Scratch Register */
120# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
121# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
122# define OFFSET_THR 0x28 /* Transmit Holding register */
123# define OFFSET_RBR 0x2C /* Receive Buffer register */
124#else /* BF533 style */
125# define OFFSET_THR 0x00 /* Transmit Holding register */
126# define OFFSET_RBR 0x00 /* Receive Buffer register */
127# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
128# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
129# define OFFSET_IER 0x04 /* Interrupt Enable Register */
130# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
131# define OFFSET_LCR 0x0C /* Line Control Register */
132# define OFFSET_MCR 0x10 /* Modem Control Register */
133# define OFFSET_LSR 0x14 /* Line Status Register */
134# define OFFSET_MSR 0x18 /* Modem Status Register */
135# define OFFSET_SCR 0x1C /* SCR Scratch Register */
136# define OFFSET_GCTL 0x24 /* Global Control Register */
137/* code should not need IIR, so force build error if they use it */
138# undef OFFSET_IIR
139#endif
140
141/*
142 * All Blackfin system MMRs are padded to 32bits even if the register
143 * itself is only 16bits. So use a helper macro to streamline this.
144 */
145#define __BFP(m) u16 m; u16 __pad_##m
146struct bfin_uart_regs {
147#ifdef BFIN_UART_BF54X_STYLE
148 __BFP(dll);
149 __BFP(dlh);
150 __BFP(gctl);
151 __BFP(lcr);
152 __BFP(mcr);
153 __BFP(lsr);
154 __BFP(msr);
155 __BFP(scr);
156 __BFP(ier_set);
157 __BFP(ier_clear);
158 __BFP(thr);
159 __BFP(rbr);
160#else
161 union {
162 u16 dll;
163 u16 thr;
164 const u16 rbr;
165 };
166 const u16 __pad0;
167 union {
168 u16 dlh;
169 u16 ier;
170 };
171 const u16 __pad1;
172 const __BFP(iir);
173 __BFP(lcr);
174 __BFP(mcr);
175 __BFP(lsr);
176 __BFP(msr);
177 __BFP(scr);
178 const u32 __pad2;
179 __BFP(gctl);
180#endif
181};
182#undef __BFP
183
184#ifndef port_membase
185# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
186#endif
187
188#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
189#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
190#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
191#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
192#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
193#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
194#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
195
196#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
197#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
198#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
199#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
200#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
201#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
202
203#ifdef BFIN_UART_BF54X_STYLE
204
205#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
206#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
207#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
208
209#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
210#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
211
212#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
213#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
214#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
215
216/* This handles hard CTS/RTS */
217#define BFIN_UART_CTSRTS_HARD
218#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
219#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
220#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
221#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
222#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
223#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
224
225#else /* BF533 style */
226
227#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
228#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
229#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
230#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
231
232#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
233#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
234
235#ifndef put_lsr_cache
236# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
237#endif
238#ifndef get_lsr_cache
239# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr)
240#endif
241
242/* The hardware clears the LSR bits upon read, so we need to cache
243 * some of the more fun bits in software so they don't get lost
244 * when checking the LSR in other code paths (TX).
245 */
246static inline void UART_CLEAR_LSR(void *p)
247{
248 put_lsr_cache(p, 0);
249 bfin_write16(port_membase(p) + OFFSET_LSR, -1);
250}
251static inline unsigned int UART_GET_LSR(void *p)
252{
253 unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
254 put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
255 return lsr | get_lsr_cache(p);
256}
257static inline void UART_PUT_LSR(void *p, uint16_t val)
258{
259 put_lsr_cache(p, get_lsr_cache(p) & ~val);
260}
261
262/* This handles soft CTS/RTS */
263#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
264#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
265#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
266#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
267#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
268
269#endif
270
271#ifndef BFIN_UART_TX_FIFO_SIZE
272# define BFIN_UART_TX_FIFO_SIZE 2
273#endif
274
275#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 3f7ef4d97791..29f4fd886174 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -108,7 +108,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
108#define smp_mb__before_clear_bit() barrier() 108#define smp_mb__before_clear_bit() barrier()
109#define smp_mb__after_clear_bit() barrier() 109#define smp_mb__after_clear_bit() barrier()
110 110
111#define test_bit __skip_test_bit
111#include <asm-generic/bitops/non-atomic.h> 112#include <asm-generic/bitops/non-atomic.h>
113#undef test_bit
112 114
113#endif /* CONFIG_SMP */ 115#endif /* CONFIG_SMP */
114 116
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index bd0641a267f1..568885a2c286 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -7,6 +7,8 @@
7#ifndef __ARCH_BLACKFIN_CACHE_H 7#ifndef __ARCH_BLACKFIN_CACHE_H
8#define __ARCH_BLACKFIN_CACHE_H 8#define __ARCH_BLACKFIN_CACHE_H
9 9
10#include <linux/linkage.h> /* for asmlinkage */
11
10/* 12/*
11 * Bytes per L1 cache line 13 * Bytes per L1 cache line
12 * Blackfin loads 32 bytes for cache 14 * Blackfin loads 32 bytes for cache
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 2666ff8ea952..77135b62818e 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -11,6 +11,9 @@
11 11
12#include <asm/blackfin.h> /* for SSYNC() */ 12#include <asm/blackfin.h> /* for SSYNC() */
13#include <asm/sections.h> /* for _ramend */ 13#include <asm/sections.h> /* for _ramend */
14#ifdef CONFIG_SMP
15#include <asm/smp.h>
16#endif
14 17
15extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); 18extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
16extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); 19extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index eedf3ca65ba2..d9dbc1a53534 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -14,40 +14,7 @@
14#include <asm/blackfin.h> 14#include <asm/blackfin.h>
15#include <asm/page.h> 15#include <asm/page.h>
16#include <asm-generic/dma.h> 16#include <asm-generic/dma.h>
17 17#include <asm/bfin_dma.h>
18/* DMA_CONFIG Masks */
19#define DMAEN 0x0001 /* DMA Channel Enable */
20#define WNR 0x0002 /* Channel Direction (W/R*) */
21#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
22#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
23#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
24#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
25#define RESTART 0x0020 /* DMA Buffer Clear */
26#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
27#define DI_EN 0x0080 /* Data Interrupt Enable */
28#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
29#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
30#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
31#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
32#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
33#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
34#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
35#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
36#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
37#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
38#define NDSIZE 0x0f00 /* Next Descriptor Size */
39#define DMAFLOW 0x7000 /* Flow Control */
40#define DMAFLOW_STOP 0x0000 /* Stop Mode */
41#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
42#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
43#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
44#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
45
46/* DMA_IRQ_STATUS Masks */
47#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
48#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
49#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
50#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
51 18
52/*------------------------- 19/*-------------------------
53 * config reg bits value 20 * config reg bits value
@@ -149,7 +116,7 @@ void blackfin_dma_resume(void);
149* DMA API's 116* DMA API's
150*******************************************************************************/ 117*******************************************************************************/
151extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; 118extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
152extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS]; 119extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
153extern int channel2irq(unsigned int channel); 120extern int channel2irq(unsigned int channel);
154 121
155static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) 122static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index efcc3aebeae4..3047120cfcff 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,8 @@
9#ifndef _BLACKFIN_DPMC_H_ 9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_
11 11
12#include <mach/pll.h>
13
12/* PLL_CTL Masks */ 14/* PLL_CTL Masks */
13#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 15#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
14#define PLL_OFF 0x0002 /* PLL Not Powered */ 16#define PLL_OFF 0x0002 /* PLL Not Powered */
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 234fbac17ec1..dccae26805b0 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,148 +7,48 @@
7#ifndef _BFIN_IO_H 7#ifndef _BFIN_IO_H
8#define _BFIN_IO_H 8#define _BFIN_IO_H
9 9
10#ifdef __KERNEL__
11
12#ifndef __ASSEMBLY__
13#include <linux/types.h>
14#endif
15#include <linux/compiler.h> 10#include <linux/compiler.h>
16 11#include <linux/types.h>
17/* 12#include <asm/byteorder.h>
18 * These are for ISA/PCI shared memory _only_ and should never be used 13
19 * on any other type of memory, including Zorro memory. They are meant to 14#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
20 * access the bus in the bus byte order which is little-endian!. 15static inline type __raw_read##size(const volatile void __iomem *addr) \
21 * 16{ \
22 * readX/writeX() are used to access memory mapped devices. On some 17 unsigned int val; \
23 * architectures the memory mapped IO stuff needs to be accessed 18 int tmp; \
24 * differently. On the bfin architecture, we just read/write the 19 __asm__ __volatile__ ( \
25 * memory location directly. 20 "cli %1;" \
26 */ 21 "NOP; NOP; SSYNC;" \
27#ifndef __ASSEMBLY__ 22 "%0 = "#asm" [%2] "#asm_sign";" \
28 23 "sti %1;" \
29static inline unsigned char readb(const volatile void __iomem *addr) 24 : "=d"(val), "=d"(tmp) \
30{ 25 : "a"(addr) \
31 unsigned int val; 26 ); \
32 int tmp; 27 return (type) val; \
33
34 __asm__ __volatile__ (
35 "cli %1;"
36 "NOP; NOP; SSYNC;"
37 "%0 = b [%2] (z);"
38 "sti %1;"
39 : "=d"(val), "=d"(tmp)
40 : "a"(addr)
41 );
42
43 return (unsigned char) val;
44}
45
46static inline unsigned short readw(const volatile void __iomem *addr)
47{
48 unsigned int val;
49 int tmp;
50
51 __asm__ __volatile__ (
52 "cli %1;"
53 "NOP; NOP; SSYNC;"
54 "%0 = w [%2] (z);"
55 "sti %1;"
56 : "=d"(val), "=d"(tmp)
57 : "a"(addr)
58 );
59
60 return (unsigned short) val;
61}
62
63static inline unsigned int readl(const volatile void __iomem *addr)
64{
65 unsigned int val;
66 int tmp;
67
68 __asm__ __volatile__ (
69 "cli %1;"
70 "NOP; NOP; SSYNC;"
71 "%0 = [%2];"
72 "sti %1;"
73 : "=d"(val), "=d"(tmp)
74 : "a"(addr)
75 );
76
77 return val;
78} 28}
79 29DECLARE_BFIN_RAW_READX(b, u8, b, (z))
80#endif /* __ASSEMBLY__ */ 30#define __raw_readb __raw_readb
81 31DECLARE_BFIN_RAW_READX(w, u16, w, (z))
82#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) 32#define __raw_readw __raw_readw
83#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) 33DECLARE_BFIN_RAW_READX(l, u32, , )
84#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) 34#define __raw_readl __raw_readl
85
86#define __raw_readb readb
87#define __raw_readw readw
88#define __raw_readl readl
89#define __raw_writeb writeb
90#define __raw_writew writew
91#define __raw_writel writel
92#define memset_io(a, b, c) memset((void *)(a), (b), (c))
93#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
94#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
95
96/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
97#define __io(port) ((void *)(unsigned long)(port))
98
99#define inb(port) readb(__io(port))
100#define inw(port) readw(__io(port))
101#define inl(port) readl(__io(port))
102#define outb(x, port) writeb(x, __io(port))
103#define outw(x, port) writew(x, __io(port))
104#define outl(x, port) writel(x, __io(port))
105
106#define inb_p(port) inb(__io(port))
107#define inw_p(port) inw(__io(port))
108#define inl_p(port) inl(__io(port))
109#define outb_p(x, port) outb(x, __io(port))
110#define outw_p(x, port) outw(x, __io(port))
111#define outl_p(x, port) outl(x, __io(port))
112
113#define ioread8_rep(a, d, c) readsb(a, d, c)
114#define ioread16_rep(a, d, c) readsw(a, d, c)
115#define ioread32_rep(a, d, c) readsl(a, d, c)
116#define iowrite8_rep(a, s, c) writesb(a, s, c)
117#define iowrite16_rep(a, s, c) writesw(a, s, c)
118#define iowrite32_rep(a, s, c) writesl(a, s, c)
119
120#define ioread8(x) readb(x)
121#define ioread16(x) readw(x)
122#define ioread32(x) readl(x)
123#define iowrite8(val, x) writeb(val, x)
124#define iowrite16(val, x) writew(val, x)
125#define iowrite32(val, x) writel(val, x)
126
127/**
128 * I/O write barrier
129 *
130 * Ensure ordering of I/O space writes. This will make sure that writes
131 * following the barrier will arrive after all previous writes.
132 */
133#define mmiowb() do { SSYNC(); wmb(); } while (0)
134
135#define IO_SPACE_LIMIT 0xffffffff
136
137/* Values for nocacheflag and cmode */
138#define IOMAP_NOCACHE_SER 1
139
140#ifndef __ASSEMBLY__
141 35
142extern void outsb(unsigned long port, const void *addr, unsigned long count); 36extern void outsb(unsigned long port, const void *addr, unsigned long count);
143extern void outsw(unsigned long port, const void *addr, unsigned long count); 37extern void outsw(unsigned long port, const void *addr, unsigned long count);
144extern void outsw_8(unsigned long port, const void *addr, unsigned long count); 38extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
145extern void outsl(unsigned long port, const void *addr, unsigned long count); 39extern void outsl(unsigned long port, const void *addr, unsigned long count);
40#define outsb outsb
41#define outsw outsw
42#define outsl outsl
146 43
147extern void insb(unsigned long port, void *addr, unsigned long count); 44extern void insb(unsigned long port, void *addr, unsigned long count);
148extern void insw(unsigned long port, void *addr, unsigned long count); 45extern void insw(unsigned long port, void *addr, unsigned long count);
149extern void insw_8(unsigned long port, void *addr, unsigned long count); 46extern void insw_8(unsigned long port, void *addr, unsigned long count);
150extern void insl(unsigned long port, void *addr, unsigned long count); 47extern void insl(unsigned long port, void *addr, unsigned long count);
151extern void insl_16(unsigned long port, void *addr, unsigned long count); 48extern void insl_16(unsigned long port, void *addr, unsigned long count);
49#define insb insb
50#define insw insw
51#define insl insl
152 52
153extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); 53extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
154extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); 54extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
158extern void dma_insw(unsigned long port, void *addr, unsigned short count); 58extern void dma_insw(unsigned long port, void *addr, unsigned short count);
159extern void dma_insl(unsigned long port, void *addr, unsigned short count); 59extern void dma_insl(unsigned long port, void *addr, unsigned short count);
160 60
161static inline void readsl(const void __iomem *addr, void *buf, int len) 61/**
162{ 62 * I/O write barrier
163 insl((unsigned long)addr, buf, len); 63 *
164} 64 * Ensure ordering of I/O space writes. This will make sure that writes
165 65 * following the barrier will arrive after all previous writes.
166static inline void readsw(const void __iomem *addr, void *buf, int len)
167{
168 insw((unsigned long)addr, buf, len);
169}
170
171static inline void readsb(const void __iomem *addr, void *buf, int len)
172{
173 insb((unsigned long)addr, buf, len);
174}
175
176static inline void writesl(const void __iomem *addr, const void *buf, int len)
177{
178 outsl((unsigned long)addr, buf, len);
179}
180
181static inline void writesw(const void __iomem *addr, const void *buf, int len)
182{
183 outsw((unsigned long)addr, buf, len);
184}
185
186static inline void writesb(const void __iomem *addr, const void *buf, int len)
187{
188 outsb((unsigned long)addr, buf, len);
189}
190
191/*
192 * Map some physical address range into the kernel address space.
193 */
194static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
195 int cacheflag)
196{
197 return (void __iomem *)physaddr;
198}
199
200/*
201 * Unmap a ioremap()ed region again
202 */
203static inline void iounmap(void *addr)
204{
205}
206
207/*
208 * __iounmap unmaps nearly everything, so be careful
209 * it doesn't free currently pointer/page tables anymore but it
210 * wans't used anyway and might be added later.
211 */
212static inline void __iounmap(void *addr, unsigned long size)
213{
214}
215
216/*
217 * Set new cache mode for some kernel address space.
218 * The caller must push data for that range itself, if such data may already
219 * be in the cache.
220 */ 66 */
221static inline void kernel_set_cachemode(void *addr, unsigned long size, 67#define mmiowb() do { SSYNC(); wmb(); } while (0)
222 int cmode)
223{
224}
225
226static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
227{
228 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
229}
230static inline void __iomem *ioremap_nocache(unsigned long physaddr,
231 unsigned long size)
232{
233 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
234}
235 68
236extern void blkfin_inv_cache_all(void); 69#include <asm-generic/io.h>
237 70
238#endif 71#endif
239
240#define ioport_map(port, nr) ((void __iomem*)(port))
241#define ioport_unmap(addr)
242
243/* Pages to physical address... */
244#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
245
246#define phys_to_virt(vaddr) ((void *) (vaddr))
247#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
248
249#define virt_to_bus virt_to_phys
250#define bus_to_virt phys_to_virt
251
252/*
253 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
254 * access
255 */
256#define xlate_dev_mem_ptr(p) __va(p)
257
258/*
259 * Convert a virtual cached pointer to an uncached pointer
260 */
261#define xlate_dev_kmem_ptr(p) p
262
263#endif /* __KERNEL__ */
264
265#endif /* _BFIN_IO_H */
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 41c4d70544ef..3365cb97f539 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -13,9 +13,6 @@
13#ifdef CONFIG_SMP 13#ifdef CONFIG_SMP
14# include <asm/pda.h> 14# include <asm/pda.h>
15# include <asm/processor.h> 15# include <asm/processor.h>
16/* Forward decl needed due to cdef inter dependencies */
17static inline uint32_t __pure bfin_dspid(void);
18# define blackfin_core_id() (bfin_dspid() & 0xff)
19# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask 16# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
20#else 17#else
21extern unsigned long bfin_irq_flags; 18extern unsigned long bfin_irq_flags;
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
index aea880274de7..8af7772e84cc 100644
--- a/arch/blackfin/include/asm/processor.h
+++ b/arch/blackfin/include/asm/processor.h
@@ -14,7 +14,7 @@
14#define current_text_addr() ({ __label__ _l; _l: &&_l;}) 14#define current_text_addr() ({ __label__ _l; _l: &&_l;})
15 15
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17#include <asm/blackfin.h> 17#include <mach/blackfin.h>
18 18
19static inline unsigned long rdusp(void) 19static inline unsigned long rdusp(void)
20{ 20{
@@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void)
134 return bfin_read_DSPID(); 134 return bfin_read_DSPID();
135} 135}
136 136
137#define blackfin_core_id() (bfin_dspid() & 0xff)
138
137static inline uint32_t __pure bfin_compiled_revid(void) 139static inline uint32_t __pure bfin_compiled_revid(void)
138{ 140{
139#if defined(CONFIG_BF_REV_0_0) 141#if defined(CONFIG_BF_REV_0_0)
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1942ccfedbe0..1f286e71c21f 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
17asmlinkage void __raw_spin_lock_asm(volatile int *ptr); 17asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
18asmlinkage int __raw_spin_trylock_asm(volatile int *ptr); 18asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
19asmlinkage void __raw_spin_unlock_asm(volatile int *ptr); 19asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
20asmlinkage void arch_read_lock_asm(volatile int *ptr); 20asmlinkage void __raw_read_lock_asm(volatile int *ptr);
21asmlinkage int arch_read_trylock_asm(volatile int *ptr); 21asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
22asmlinkage void arch_read_unlock_asm(volatile int *ptr); 22asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
23asmlinkage void arch_write_lock_asm(volatile int *ptr); 23asmlinkage void __raw_write_lock_asm(volatile int *ptr);
24asmlinkage int arch_write_trylock_asm(volatile int *ptr); 24asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
25asmlinkage void arch_write_unlock_asm(volatile int *ptr); 25asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
26 26
27static inline int arch_spin_is_locked(arch_spinlock_t *lock) 27static inline int arch_spin_is_locked(arch_spinlock_t *lock)
28{ 28{
@@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw)
64 64
65static inline void arch_read_lock(arch_rwlock_t *rw) 65static inline void arch_read_lock(arch_rwlock_t *rw)
66{ 66{
67 arch_read_lock_asm(&rw->lock); 67 __raw_read_lock_asm(&rw->lock);
68} 68}
69 69
70#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
71
70static inline int arch_read_trylock(arch_rwlock_t *rw) 72static inline int arch_read_trylock(arch_rwlock_t *rw)
71{ 73{
72 return arch_read_trylock_asm(&rw->lock); 74 return __raw_read_trylock_asm(&rw->lock);
73} 75}
74 76
75static inline void arch_read_unlock(arch_rwlock_t *rw) 77static inline void arch_read_unlock(arch_rwlock_t *rw)
76{ 78{
77 arch_read_unlock_asm(&rw->lock); 79 __raw_read_unlock_asm(&rw->lock);
78} 80}
79 81
80static inline void arch_write_lock(arch_rwlock_t *rw) 82static inline void arch_write_lock(arch_rwlock_t *rw)
81{ 83{
82 arch_write_lock_asm(&rw->lock); 84 __raw_write_lock_asm(&rw->lock);
83} 85}
84 86
87#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
88
85static inline int arch_write_trylock(arch_rwlock_t *rw) 89static inline int arch_write_trylock(arch_rwlock_t *rw)
86{ 90{
87 return arch_write_trylock_asm(&rw->lock); 91 return __raw_write_trylock_asm(&rw->lock);
88} 92}
89 93
90static inline void arch_write_unlock(arch_rwlock_t *rw) 94static inline void arch_write_unlock(arch_rwlock_t *rw)
91{ 95{
92 arch_write_unlock_asm(&rw->lock); 96 __raw_write_unlock_asm(&rw->lock);
93} 97}
94 98
95#define arch_spin_relax(lock) cpu_relax() 99#define arch_spin_relax(lock) cpu_relax()
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
new file mode 100644
index 000000000000..382178b361af
--- /dev/null
+++ b/arch/blackfin/include/mach-common/pll.h
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_COMMON_PLL_H
8#define _MACH_COMMON_PLL_H
9
10#ifndef __ASSEMBLY__
11
12#include <asm/blackfin.h>
13#include <asm/irqflags.h>
14
15#ifndef bfin_iwr_restore
16static inline void
17bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
18{
19#ifdef SIC_IWR
20 bfin_write_SIC_IWR(iwr0);
21#else
22 bfin_write_SIC_IWR0(iwr0);
23# ifdef SIC_IWR1
24 bfin_write_SIC_IWR1(iwr1);
25# endif
26# ifdef SIC_IWR2
27 bfin_write_SIC_IWR2(iwr2);
28# endif
29#endif
30}
31#endif
32
33#ifndef bfin_iwr_save
34static inline void
35bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
36 unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
37{
38#ifdef SIC_IWR
39 *iwr0 = bfin_read_SIC_IWR();
40#else
41 *iwr0 = bfin_read_SIC_IWR0();
42# ifdef SIC_IWR1
43 *iwr1 = bfin_read_SIC_IWR1();
44# endif
45# ifdef SIC_IWR2
46 *iwr2 = bfin_read_SIC_IWR2();
47# endif
48#endif
49 bfin_iwr_restore(niwr0, niwr1, niwr2);
50}
51#endif
52
53static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
54{
55 unsigned long flags, iwr0, iwr1, iwr2;
56
57 if (val == bfin_read_PLL_CTL())
58 return;
59
60 flags = hard_local_irq_save();
61 /* Enable the PLL Wakeup bit in SIC IWR */
62 bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
63
64 bfin_write16(addr, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_iwr_restore(iwr0, iwr1, iwr2);
69 hard_local_irq_restore(flags);
70}
71
72/* Writing to PLL_CTL initiates a PLL relock sequence */
73static inline void bfin_write_PLL_CTL(unsigned int val)
74{
75 _bfin_write_pll_relock(PLL_CTL, val);
76}
77
78/* Writing to VR_CTL initiates a PLL relock sequence */
79static inline void bfin_write_VR_CTL(unsigned int val)
80{
81 _bfin_write_pll_relock(VR_CTL, val);
82}
83
84#endif
85
86#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
new file mode 100644
index 000000000000..9f78a761c40a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-a.h
@@ -0,0 +1,25 @@
1/*
2 * Port A Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_A__
6#define __BFIN_PERIPHERAL_PORT_A__
7
8#define PA0 (1 << 0)
9#define PA1 (1 << 1)
10#define PA2 (1 << 2)
11#define PA3 (1 << 3)
12#define PA4 (1 << 4)
13#define PA5 (1 << 5)
14#define PA6 (1 << 6)
15#define PA7 (1 << 7)
16#define PA8 (1 << 8)
17#define PA9 (1 << 9)
18#define PA10 (1 << 10)
19#define PA11 (1 << 11)
20#define PA12 (1 << 12)
21#define PA13 (1 << 13)
22#define PA14 (1 << 14)
23#define PA15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
new file mode 100644
index 000000000000..b81702f09ec6
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-b.h
@@ -0,0 +1,25 @@
1/*
2 * Port B Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_B__
6#define __BFIN_PERIPHERAL_PORT_B__
7
8#define PB0 (1 << 0)
9#define PB1 (1 << 1)
10#define PB2 (1 << 2)
11#define PB3 (1 << 3)
12#define PB4 (1 << 4)
13#define PB5 (1 << 5)
14#define PB6 (1 << 6)
15#define PB7 (1 << 7)
16#define PB8 (1 << 8)
17#define PB9 (1 << 9)
18#define PB10 (1 << 10)
19#define PB11 (1 << 11)
20#define PB12 (1 << 12)
21#define PB13 (1 << 13)
22#define PB14 (1 << 14)
23#define PB15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
new file mode 100644
index 000000000000..3cc665e0ba08
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-c.h
@@ -0,0 +1,25 @@
1/*
2 * Port C Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_C__
6#define __BFIN_PERIPHERAL_PORT_C__
7
8#define PC0 (1 << 0)
9#define PC1 (1 << 1)
10#define PC2 (1 << 2)
11#define PC3 (1 << 3)
12#define PC4 (1 << 4)
13#define PC5 (1 << 5)
14#define PC6 (1 << 6)
15#define PC7 (1 << 7)
16#define PC8 (1 << 8)
17#define PC9 (1 << 9)
18#define PC10 (1 << 10)
19#define PC11 (1 << 11)
20#define PC12 (1 << 12)
21#define PC13 (1 << 13)
22#define PC14 (1 << 14)
23#define PC15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
new file mode 100644
index 000000000000..868c6a01f1b2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-d.h
@@ -0,0 +1,25 @@
1/*
2 * Port D Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_D__
6#define __BFIN_PERIPHERAL_PORT_D__
7
8#define PD0 (1 << 0)
9#define PD1 (1 << 1)
10#define PD2 (1 << 2)
11#define PD3 (1 << 3)
12#define PD4 (1 << 4)
13#define PD5 (1 << 5)
14#define PD6 (1 << 6)
15#define PD7 (1 << 7)
16#define PD8 (1 << 8)
17#define PD9 (1 << 9)
18#define PD10 (1 << 10)
19#define PD11 (1 << 11)
20#define PD12 (1 << 12)
21#define PD13 (1 << 13)
22#define PD14 (1 << 14)
23#define PD15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
new file mode 100644
index 000000000000..c88b0d0dd443
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-e.h
@@ -0,0 +1,25 @@
1/*
2 * Port E Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_E__
6#define __BFIN_PERIPHERAL_PORT_E__
7
8#define PE0 (1 << 0)
9#define PE1 (1 << 1)
10#define PE2 (1 << 2)
11#define PE3 (1 << 3)
12#define PE4 (1 << 4)
13#define PE5 (1 << 5)
14#define PE6 (1 << 6)
15#define PE7 (1 << 7)
16#define PE8 (1 << 8)
17#define PE9 (1 << 9)
18#define PE10 (1 << 10)
19#define PE11 (1 << 11)
20#define PE12 (1 << 12)
21#define PE13 (1 << 13)
22#define PE14 (1 << 14)
23#define PE15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
new file mode 100644
index 000000000000..d6af20633278
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-f.h
@@ -0,0 +1,25 @@
1/*
2 * Port F Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_F__
6#define __BFIN_PERIPHERAL_PORT_F__
7
8#define PF0 (1 << 0)
9#define PF1 (1 << 1)
10#define PF2 (1 << 2)
11#define PF3 (1 << 3)
12#define PF4 (1 << 4)
13#define PF5 (1 << 5)
14#define PF6 (1 << 6)
15#define PF7 (1 << 7)
16#define PF8 (1 << 8)
17#define PF9 (1 << 9)
18#define PF10 (1 << 10)
19#define PF11 (1 << 11)
20#define PF12 (1 << 12)
21#define PF13 (1 << 13)
22#define PF14 (1 << 14)
23#define PF15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
new file mode 100644
index 000000000000..09355d333c0e
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-g.h
@@ -0,0 +1,25 @@
1/*
2 * Port G Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_G__
6#define __BFIN_PERIPHERAL_PORT_G__
7
8#define PG0 (1 << 0)
9#define PG1 (1 << 1)
10#define PG2 (1 << 2)
11#define PG3 (1 << 3)
12#define PG4 (1 << 4)
13#define PG5 (1 << 5)
14#define PG6 (1 << 6)
15#define PG7 (1 << 7)
16#define PG8 (1 << 8)
17#define PG9 (1 << 9)
18#define PG10 (1 << 10)
19#define PG11 (1 << 11)
20#define PG12 (1 << 12)
21#define PG13 (1 << 13)
22#define PG14 (1 << 14)
23#define PG15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
new file mode 100644
index 000000000000..fa3910c6fbd4
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-h.h
@@ -0,0 +1,25 @@
1/*
2 * Port H Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_H__
6#define __BFIN_PERIPHERAL_PORT_H__
7
8#define PH0 (1 << 0)
9#define PH1 (1 << 1)
10#define PH2 (1 << 2)
11#define PH3 (1 << 3)
12#define PH4 (1 << 4)
13#define PH5 (1 << 5)
14#define PH6 (1 << 6)
15#define PH7 (1 << 7)
16#define PH8 (1 << 8)
17#define PH9 (1 << 9)
18#define PH10 (1 << 10)
19#define PH11 (1 << 11)
20#define PH12 (1 << 12)
21#define PH13 (1 << 13)
22#define PH14 (1 << 14)
23#define PH15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
new file mode 100644
index 000000000000..f176f08af624
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-i.h
@@ -0,0 +1,25 @@
1/*
2 * Port I Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_I__
6#define __BFIN_PERIPHERAL_PORT_I__
7
8#define PI0 (1 << 0)
9#define PI1 (1 << 1)
10#define PI2 (1 << 2)
11#define PI3 (1 << 3)
12#define PI4 (1 << 4)
13#define PI5 (1 << 5)
14#define PI6 (1 << 6)
15#define PI7 (1 << 7)
16#define PI8 (1 << 8)
17#define PI9 (1 << 9)
18#define PI10 (1 << 10)
19#define PI11 (1 << 11)
20#define PI12 (1 << 12)
21#define PI13 (1 << 13)
22#define PI14 (1 << 14)
23#define PI15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
new file mode 100644
index 000000000000..924123ecec5a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-j.h
@@ -0,0 +1,25 @@
1/*
2 * Port J Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_J__
6#define __BFIN_PERIPHERAL_PORT_J__
7
8#define PJ0 (1 << 0)
9#define PJ1 (1 << 1)
10#define PJ2 (1 << 2)
11#define PJ3 (1 << 3)
12#define PJ4 (1 << 4)
13#define PJ5 (1 << 5)
14#define PJ6 (1 << 6)
15#define PJ7 (1 << 7)
16#define PJ8 (1 << 8)
17#define PJ9 (1 << 9)
18#define PJ10 (1 << 10)
19#define PJ11 (1 << 11)
20#define PJ12 (1 << 12)
21#define PJ13 (1 << 13)
22#define PJ14 (1 << 14)
23#define PJ15 (1 << 15)
24
25#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 21:16:57 -0500