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-rw-r--r--arch/blackfin/include/asm/bfin-global.h5
-rw-r--r--arch/blackfin/include/asm/bfin6xx_spi.h258
-rw-r--r--arch/blackfin/include/asm/bfin_crc.h139
-rw-r--r--arch/blackfin/include/asm/bfin_dma.h84
-rw-r--r--arch/blackfin/include/asm/bfin_pfmon.h2
-rw-r--r--arch/blackfin/include/asm/bfin_ppi.h128
-rw-r--r--arch/blackfin/include/asm/bfin_rotary.h1
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h182
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h1
-rw-r--r--arch/blackfin/include/asm/bfin_sport3.h107
-rw-r--r--arch/blackfin/include/asm/bfin_twi.h142
-rw-r--r--arch/blackfin/include/asm/blackfin.h8
-rw-r--r--arch/blackfin/include/asm/clkdev.h14
-rw-r--r--arch/blackfin/include/asm/clocks.h23
-rw-r--r--arch/blackfin/include/asm/cplb.h4
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h6
-rw-r--r--arch/blackfin/include/asm/dma.h137
-rw-r--r--arch/blackfin/include/asm/dpmc.h656
-rw-r--r--arch/blackfin/include/asm/fixed_code.h30
-rw-r--r--arch/blackfin/include/asm/gpio.h44
-rw-r--r--arch/blackfin/include/asm/gptimers.h104
-rw-r--r--arch/blackfin/include/asm/irqflags.h6
-rw-r--r--arch/blackfin/include/asm/page.h5
-rw-r--r--arch/blackfin/include/asm/pda.h2
-rw-r--r--arch/blackfin/include/asm/pm.h31
-rw-r--r--arch/blackfin/include/asm/unistd.h2
26 files changed, 2057 insertions, 64 deletions
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 17bcbf60bcae..608be5e6d25c 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu);
35 35
36extern unsigned long get_cclk(void); 36extern unsigned long get_cclk(void);
37extern unsigned long get_sclk(void); 37extern unsigned long get_sclk(void);
38#ifdef CONFIG_BF60x
39extern unsigned long get_sclk0(void);
40extern unsigned long get_sclk1(void);
41extern unsigned long get_dclk(void);
42#endif
38extern unsigned long sclk_to_usecs(unsigned long sclk); 43extern unsigned long sclk_to_usecs(unsigned long sclk);
39extern unsigned long usecs_to_sclk(unsigned long usecs); 44extern unsigned long usecs_to_sclk(unsigned long usecs);
40 45
diff --git a/arch/blackfin/include/asm/bfin6xx_spi.h b/arch/blackfin/include/asm/bfin6xx_spi.h
new file mode 100644
index 000000000000..89370b653dcd
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin6xx_spi.h
@@ -0,0 +1,258 @@
1/*
2 * Analog Devices SPI3 controller driver
3 *
4 * Copyright (c) 2011 Analog Devices Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef _SPI_CHANNEL_H_
21#define _SPI_CHANNEL_H_
22
23#include <linux/types.h>
24
25/* SPI_CONTROL */
26#define SPI_CTL_EN 0x00000001 /* Enable */
27#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
28#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
29#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
30#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
31#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
32#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
33#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */
34#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */
35#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */
36#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */
37#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */
38#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */
39#define SPI_CTL_LSBF 0x00001000 /* LSB First */
40#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */
41#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */
42#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */
43#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */
44#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */
45#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
46#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
47#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */
48#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */
49#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */
50#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */
51#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */
52#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */
53/* SPI_RX_CONTROL */
54#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */
55#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */
56#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */
57#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */
58#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */
59#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */
60#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */
61#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */
62#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */
63#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */
64#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */
65#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */
66#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */
67#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */
68#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */
69#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */
70#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */
71#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */
72#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */
73#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */
74#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */
75#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */
76/* SPI_TX_CONTROL */
77#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */
78#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */
79#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */
80#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */
81#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */
82#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */
83#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */
84#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */
85#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */
86#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */
87#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */
88#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */
89#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */
90#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */
91#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */
92#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */
93#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */
94#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */
95#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */
96#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */
97#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */
98#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */
99/* SPI_CLOCK */
100#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */
101/* SPI_DELAY */
102#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */
103#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */
104#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */
105/* SPI_SSEL */
106#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */
107#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */
108#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */
109#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */
110#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */
111#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */
112#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */
113#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */
114#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */
115#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */
116#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */
117#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */
118#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */
119#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */
120/* SPI_RWC */
121#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */
122/* SPI_RWCR */
123#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */
124/* SPI_TWC */
125#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */
126/* SPI_TWCR */
127#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */
128/* SPI_IMASK */
129#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
130#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
131#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
132#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
133#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
134#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
135#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */
136#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */
137#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */
138#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
139/* SPI_IMASKCL */
140#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
141#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
142#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
143#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
144#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
145#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
146#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */
147#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */
148#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */
149#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
150/* SPI_IMASKST */
151#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
152#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
153#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
154#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
155#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
156#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
157#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */
158#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */
159#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */
160#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
161/* SPI_STATUS */
162#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */
163#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */
164#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */
165#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */
166#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */
167#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */
168#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */
169#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */
170#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */
171#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */
172#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */
173#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */
174#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */
175#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */
176#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */
177#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */
178#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */
179#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */
180#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */
181#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */
182#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */
183#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */
184#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */
185#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */
186#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */
187#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */
188/* SPI_ILAT */
189#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
190#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
191#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */
192#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */
193#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */
194#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */
195#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */
196#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */
197#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */
198#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */
199/* SPI_ILATCL */
200#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
201#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
202#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */
203#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */
204#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */
205#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */
206#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */
207#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */
208#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */
209#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
210
211/*
212 * bfin spi3 registers layout
213 */
214struct bfin_spi_regs {
215 u32 revid;
216 u32 control;
217 u32 rx_control;
218 u32 tx_control;
219 u32 clock;
220 u32 delay;
221 u32 ssel;
222 u32 rwc;
223 u32 rwcr;
224 u32 twc;
225 u32 twcr;
226 u32 reserved0;
227 u32 emask;
228 u32 emaskcl;
229 u32 emaskst;
230 u32 reserved1;
231 u32 status;
232 u32 elat;
233 u32 elatcl;
234 u32 reserved2;
235 u32 rfifo;
236 u32 reserved3;
237 u32 tfifo;
238};
239
240#define MAX_CTRL_CS 8 /* cs in spi controller */
241
242/* device.platform_data for SSP controller devices */
243struct bfin6xx_spi_master {
244 u16 num_chipselect;
245 u16 pin_req[7];
246};
247
248/* spi_board_info.controller_data for SPI slave devices,
249 * copied to spi_device.platform_data ... mostly for dma tuning
250 */
251struct bfin6xx_spi_chip {
252 u32 control;
253 u16 cs_chg_udelay; /* Some devices require 16-bit delays */
254 u32 tx_dummy_val; /* tx value for rx only transfer */
255 bool enable_dma;
256};
257
258#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h
new file mode 100644
index 000000000000..3deb4452ceed
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_crc.h
@@ -0,0 +1,139 @@
1/*
2 * bfin_crc.h - interface to Blackfin CRC controllers
3 *
4 * Copyright 2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_CRC_H__
10#define __BFIN_CRC_H__
11
12/* Function driver which use hardware crc must initialize the structure */
13struct crc_info {
14 /* Input data address */
15 unsigned char *in_addr;
16 /* Output data address */
17 unsigned char *out_addr;
18 /* Input or output bytes */
19 unsigned long datasize;
20 union {
21 /* CRC to compare with that of input buffer */
22 unsigned long crc_compare;
23 /* Value to compare with input data */
24 unsigned long val_verify;
25 /* Value to fill */
26 unsigned long val_fill;
27 };
28 /* Value to program the 32b CRC Polynomial */
29 unsigned long crc_poly;
30 union {
31 /* CRC calculated from the input data */
32 unsigned long crc_result;
33 /* First failed position to verify input data */
34 unsigned long pos_verify;
35 };
36 /* CRC mirror flags */
37 unsigned int bitmirr:1;
38 unsigned int bytmirr:1;
39 unsigned int w16swp:1;
40 unsigned int fdsel:1;
41 unsigned int rsltmirr:1;
42 unsigned int polymirr:1;
43 unsigned int cmpmirr:1;
44};
45
46/* Userspace interface */
47#define CRC_IOC_MAGIC 'C'
48#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int)
49#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int)
50#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int)
51#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int)
52
53
54#ifdef __KERNEL__
55
56#include <linux/types.h>
57#include <linux/spinlock.h>
58#include <linux/miscdevice.h>
59
60struct crc_register {
61 u32 control;
62 u32 datacnt;
63 u32 datacntrld;
64 u32 __pad_1[2];
65 u32 compare;
66 u32 fillval;
67 u32 datafifo;
68 u32 intren;
69 u32 intrenset;
70 u32 intrenclr;
71 u32 poly;
72 u32 __pad_2[4];
73 u32 status;
74 u32 datacntcap;
75 u32 __pad_3;
76 u32 result;
77 u32 curresult;
78 u32 __pad_4[3];
79 u32 revid;
80};
81
82struct bfin_crc {
83 struct miscdevice mdev;
84 struct list_head list;
85 int irq;
86 int dma_ch_src;
87 int dma_ch_dest;
88 volatile struct crc_register *regs;
89 struct crc_info *info;
90 struct mutex mutex;
91 struct completion c;
92 unsigned short opmode;
93 char name[20];
94};
95
96/* CRC_STATUS Masks */
97#define CMPERR 0x00000002 /* Compare error */
98#define DCNTEXP 0x00000010 /* datacnt register expired */
99#define IBR 0x00010000 /* Input buffer ready */
100#define OBR 0x00020000 /* Output buffer ready */
101#define IRR 0x00040000 /* Immediate result readt */
102#define LUTDONE 0x00080000 /* Look-up table generation done */
103#define FSTAT 0x00700000 /* FIFO status */
104#define MAX_FIFO 4 /* Max fifo size */
105
106/* CRC_CONTROL Masks */
107#define BLKEN 0x00000001 /* Block enable */
108#define OPMODE 0x000000F0 /* Operation mode */
109#define OPMODE_OFFSET 4 /* Operation mode mask offset*/
110#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */
111#define MODE_DATA_FILL 2 /* MTM data fill */
112#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */
113#define MODE_DATA_VERIFY 4 /* MSM data verify */
114#define AUTOCLRZ 0x00000100 /* Auto clear to zero */
115#define AUTOCLRF 0x00000200 /* Auto clear to one */
116#define OBRSTALL 0x00001000 /* Stall on output buffer ready */
117#define IRRSTALL 0x00002000 /* Stall on immediate result ready */
118#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */
119#define BITMIRR_OFFSET 16 /* Mirror bits offset */
120#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */
121#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */
122#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */
123#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */
124#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */
125#define FDSEL_OFFSET 19 /* Mirror FIFO offset */
126#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */
127#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */
128#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */
129#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */
130#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */
131#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */
132
133/* CRC_INTREN Masks */
134#define CMPERRI 0x02 /* CRC_ERROR_INTR */
135#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */
136
137#endif
138
139#endif
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
index d51120744148..6319f4e49083 100644
--- a/arch/blackfin/include/asm/bfin_dma.h
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -15,12 +15,55 @@
15#define DMAEN 0x0001 /* DMA Channel Enable */ 15#define DMAEN 0x0001 /* DMA Channel Enable */
16#define WNR 0x0002 /* Channel Direction (W/R*) */ 16#define WNR 0x0002 /* Channel Direction (W/R*) */
17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ 17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
18#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
19
20#ifdef CONFIG_BF60x
21
22#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
23#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
24#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
25#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
26#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
27#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
28#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
29#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
30#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
31#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
32#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
33#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
34#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
35#define DI_EN DI_EN_X /* Data Interrupt Enable */
36#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
37#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
38#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
39#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
40#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
41#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
42#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
43#define NDSIZE 0x00070000 /* Next Descriptor Size */
44#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
45#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
46#define DMAFLOW_LARGE DMAFLOW_LIST
47#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
48#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
49#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
50#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
51#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
52#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
53#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
54
55#else
56
57#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
58#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
18#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ 59#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
19#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ 60#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
20#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ 61#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
21#define RESTART 0x0020 /* DMA Buffer Clear */ 62#define RESTART 0x0020 /* DMA Buffer Clear */
22#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ 63#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
23#define DI_EN 0x0080 /* Data Interrupt Enable */ 64#define DI_EN 0x0080 /* Data Interrupt Enable */
65#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
66#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
24#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 67#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
25#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 68#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
26#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 69#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
@@ -32,18 +75,26 @@
32#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 75#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
33#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 76#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
34#define NDSIZE 0x0f00 /* Next Descriptor Size */ 77#define NDSIZE 0x0f00 /* Next Descriptor Size */
35#define DMAFLOW 0x7000 /* Flow Control */ 78#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
36#define DMAFLOW_STOP 0x0000 /* Stop Mode */
37#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
38#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 79#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
39#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 80#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
40#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 81#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
82#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
83#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
84
85#endif
86#define DMAFLOW 0x7000 /* Flow Control */
87#define DMAFLOW_STOP 0x0000 /* Stop Mode */
88#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
41 89
42/* DMA_IRQ_STATUS Masks */ 90/* DMA_IRQ_STATUS Masks */
43#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ 91#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
44#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ 92#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
45#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ 93#ifdef CONFIG_BF60x
46#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ 94#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
95#else
96#define DMA_PIRQ 0
97#endif
47 98
48/* 99/*
49 * All Blackfin system MMRs are padded to 32bits even if the register 100 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -57,6 +108,26 @@
57struct bfin_dma_regs { 108struct bfin_dma_regs {
58 u32 next_desc_ptr; 109 u32 next_desc_ptr;
59 u32 start_addr; 110 u32 start_addr;
111#ifdef CONFIG_BF60x
112 u32 cfg;
113 u32 x_count;
114 u32 x_modify;
115 u32 y_count;
116 u32 y_modify;
117 u32 pad1;
118 u32 pad2;
119 u32 curr_desc_ptr;
120 u32 prev_desc_ptr;
121 u32 curr_addr;
122 u32 irq_status;
123 u32 curr_x_count;
124 u32 curr_y_count;
125 u32 pad3;
126 u32 bw_limit_count;
127 u32 curr_bw_limit_count;
128 u32 bw_monitor_count;
129 u32 curr_bw_monitor_count;
130#else
60 __BFP(config); 131 __BFP(config);
61 u32 __pad0; 132 u32 __pad0;
62 __BFP(x_count); 133 __BFP(x_count);
@@ -71,8 +142,10 @@ struct bfin_dma_regs {
71 u32 __pad1; 142 u32 __pad1;
72 __BFP(curr_y_count); 143 __BFP(curr_y_count);
73 u32 __pad2; 144 u32 __pad2;
145#endif
74}; 146};
75 147
148#ifndef CONFIG_BF60x
76/* 149/*
77 * bfin handshake mdma registers layout 150 * bfin handshake mdma registers layout
78 */ 151 */
@@ -85,6 +158,7 @@ struct bfin_hmdma_regs {
85 __BFP(ecount); 158 __BFP(ecount);
86 __BFP(bcount); 159 __BFP(bcount);
87}; 160};
161#endif
88 162
89#undef __BFP 163#undef __BFP
90 164
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
index accd47e2db40..bf52e1f32257 100644
--- a/arch/blackfin/include/asm/bfin_pfmon.h
+++ b/arch/blackfin/include/asm/bfin_pfmon.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright 2005-2011 Analog Devices Inc. 4 * Copyright 2005-2011 Analog Devices Inc.
5 * 5 *
6 * Licensed under the ADI BSD license or GPL-2 (or later). 6 * Licensed under the Clear BSD license or GPL-2 (or later).
7 */ 7 */
8 8
9#ifndef __ASM_BFIN_PFMON_H__ 9#ifndef __ASM_BFIN_PFMON_H__
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
index 3be05faa2c65..a4e872e16e75 100644
--- a/arch/blackfin/include/asm/bfin_ppi.h
+++ b/arch/blackfin/include/asm/bfin_ppi.h
@@ -10,6 +10,7 @@
10#define __ASM_BFIN_PPI_H__ 10#define __ASM_BFIN_PPI_H__
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13#include <asm/blackfin.h>
13 14
14/* 15/*
15 * All Blackfin system MMRs are padded to 32bits even if the register 16 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -48,6 +49,133 @@ struct bfin_eppi_regs {
48 u32 clip; 49 u32 clip;
49}; 50};
50 51
52/*
53 * bfin eppi3 registers layout
54 */
55struct bfin_eppi3_regs {
56 u32 stat;
57 u32 hcnt;
58 u32 hdly;
59 u32 vcnt;
60 u32 vdly;
61 u32 frame;
62 u32 line;
63 u32 clkdiv;
64 u32 ctl;
65 u32 fs1_wlhb;
66 u32 fs1_paspl;
67 u32 fs2_wlvb;
68 u32 fs2_palpf;
69 u32 imsk;
70 u32 oddclip;
71 u32 evenclip;
72 u32 fs1_dly;
73 u32 fs2_dly;
74 u32 ctl2;
75};
76
51#undef __BFP 77#undef __BFP
52 78
79#ifdef EPPI0_CTL2
80#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
81#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
82#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
83#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
84#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
85#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
86#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
87#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
88#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
89#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
90
91#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
92
93#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
94
95#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
96
97#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
98
99#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
100
101#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
102
103#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
104
105#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
106#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
107#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
108#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
109#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
110#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
111#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
112#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
113#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
114#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
115#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
116#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
117#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
118#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
119#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
120#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
121#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
122#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
123#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
124#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
125#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
126#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
127#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
128#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
129#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
130#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
131#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
132#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
133#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
134#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
135#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
136#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
137#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
138#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
139#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
140#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
141#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
142#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
143#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
144#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
145#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
146#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
147#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
148#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
149#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
150#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
151#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
152#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
153#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
154#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
155
156#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
157#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
158#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
159#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
160
161#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
162#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
163
164#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
165#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
166#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
167#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
168#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
169#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
170#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
171#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
172
173#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
174#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
175
176#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
177#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
178
179#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
180#endif
53#endif 181#endif
diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h
index 0b6910bdc57f..8895a750c70c 100644
--- a/arch/blackfin/include/asm/bfin_rotary.h
+++ b/arch/blackfin/include/asm/bfin_rotary.h
@@ -39,6 +39,7 @@ struct bfin_rotary_platform_data {
39 unsigned int rotary_rel_code; 39 unsigned int rotary_rel_code;
40 unsigned short debounce; /* 0..17 */ 40 unsigned short debounce; /* 0..17 */
41 unsigned short mode; 41 unsigned short mode;
42 unsigned short pm_wakeup;
42}; 43};
43 44
44/* CNT_CONFIG bitmasks */ 45/* CNT_CONFIG bitmasks */
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 68bcc3d119b6..8597158010b5 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -18,7 +18,7 @@
18 defined(CONFIG_BFIN_UART1_CTSRTS) || \ 18 defined(CONFIG_BFIN_UART1_CTSRTS) || \
19 defined(CONFIG_BFIN_UART2_CTSRTS) || \ 19 defined(CONFIG_BFIN_UART2_CTSRTS) || \
20 defined(CONFIG_BFIN_UART3_CTSRTS) 20 defined(CONFIG_BFIN_UART3_CTSRTS)
21# ifdef BFIN_UART_BF54X_STYLE 21# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
22# define CONFIG_SERIAL_BFIN_HARD_CTSRTS 22# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
23# else 23# else
24# define CONFIG_SERIAL_BFIN_CTSRTS 24# define CONFIG_SERIAL_BFIN_CTSRTS
@@ -58,14 +58,69 @@ struct bfin_serial_port {
58#endif 58#endif
59}; 59};
60 60
61#ifdef BFIN_UART_BF60X_STYLE
62
63/* UART_CTL Masks */
64#define UCEN 0x1 /* Enable UARTx Clocks */
65#define LOOP_ENA 0x2 /* Loopback Mode Enable */
66#define UMOD_MDB 0x10 /* Enable MDB Mode */
67#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
68#define UMOD_MASK 0x30 /* Uart Mode Mask */
69#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
70#define WLS_MASK 0x300 /* Word length Select Mask */
71#define WLS_OFFSET 8 /* Word length Select Offset */
72#define STB 0x1000 /* Stop Bits */
73#define STBH 0x2000 /* Half Stop Bits */
74#define PEN 0x4000 /* Parity Enable */
75#define EPS 0x8000 /* Even Parity Select */
76#define STP 0x10000 /* Stick Parity */
77#define FPE 0x20000 /* Force Parity Error On Transmit */
78#define FFE 0x40000 /* Force Framing Error On Transmit */
79#define SB 0x80000 /* Set Break */
80#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
81#define FCPOL 0x400000 /* Flow Control Pin Polarity */
82#define RPOLC 0x800000 /* IrDA RX Polarity Change */
83#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
84#define MRTS 0x2000000 /* Manual Request To Send */
85#define XOFF 0x4000000 /* Transmitter Off */
86#define ARTS 0x8000000 /* Automatic Request To Send */
87#define ACTS 0x10000000 /* Automatic Clear To Send */
88#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
89#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
90
91/* UART_STAT Masks */
92#define DR 0x01 /* Data Ready */
93#define OE 0x02 /* Overrun Error */
94#define PE 0x04 /* Parity Error */
95#define FE 0x08 /* Framing Error */
96#define BI 0x10 /* Break Interrupt */
97#define THRE 0x20 /* THR Empty */
98#define TEMT 0x80 /* TSR and UART_THR Empty */
99#define TFI 0x100 /* Transmission Finished Indicator */
100
101#define ASTKY 0x200 /* Address Sticky */
102#define ADDR 0x400 /* Address bit status */
103#define RO 0x800 /* Reception Ongoing */
104#define SCTS 0x1000 /* Sticky CTS */
105#define CTS 0x10000 /* Clear To Send */
106#define RFCS 0x20000 /* Receive FIFO Count Status */
107
108/* UART_CLOCK Masks */
109#define EDBO 0x80000000 /* Enable Devide by One */
110
111#else /* BFIN_UART_BF60X_STYLE */
112
61/* UART_LCR Masks */ 113/* UART_LCR Masks */
62#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 114#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
115#define WLS_MASK 0x03 /* Word length Select Mask */
116#define WLS_OFFSET 0 /* Word length Select Offset */
63#define STB 0x04 /* Stop Bits */ 117#define STB 0x04 /* Stop Bits */
64#define PEN 0x08 /* Parity Enable */ 118#define PEN 0x08 /* Parity Enable */
65#define EPS 0x10 /* Even Parity Select */ 119#define EPS 0x10 /* Even Parity Select */
66#define STP 0x20 /* Stick Parity */ 120#define STP 0x20 /* Stick Parity */
67#define SB 0x40 /* Set Break */ 121#define SB 0x40 /* Set Break */
68#define DLAB 0x80 /* Divisor Latch Access */ 122#define DLAB 0x80 /* Divisor Latch Access */
123#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
69 124
70/* UART_LSR Masks */ 125/* UART_LSR Masks */
71#define DR 0x01 /* Data Ready */ 126#define DR 0x01 /* Data Ready */
@@ -77,15 +132,6 @@ struct bfin_serial_port {
77#define TEMT 0x40 /* TSR and UART_THR Empty */ 132#define TEMT 0x40 /* TSR and UART_THR Empty */
78#define TFI 0x80 /* Transmission Finished Indicator */ 133#define TFI 0x80 /* Transmission Finished Indicator */
79 134
80/* UART_IER Masks */
81#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
82#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
83#define ELSI 0x04 /* Enable RX Status Interrupt */
84#define EDSSI 0x08 /* Enable Modem Status Interrupt */
85#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
86#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
87#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
88
89/* UART_MCR Masks */ 135/* UART_MCR Masks */
90#define XOFF 0x01 /* Transmitter Off */ 136#define XOFF 0x01 /* Transmitter Off */
91#define MRTS 0x02 /* Manual Request To Send */ 137#define MRTS 0x02 /* Manual Request To Send */
@@ -103,13 +149,36 @@ struct bfin_serial_port {
103 149
104/* UART_GCTL Masks */ 150/* UART_GCTL Masks */
105#define UCEN 0x01 /* Enable UARTx Clocks */ 151#define UCEN 0x01 /* Enable UARTx Clocks */
106#define IREN 0x02 /* Enable IrDA Mode */ 152#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
153#define UMOD_MASK 0x02 /* Uart Mode Mask */
107#define TPOLC 0x04 /* IrDA TX Polarity Change */ 154#define TPOLC 0x04 /* IrDA TX Polarity Change */
108#define RPOLC 0x08 /* IrDA RX Polarity Change */ 155#define RPOLC 0x08 /* IrDA RX Polarity Change */
109#define FPE 0x10 /* Force Parity Error On Transmit */ 156#define FPE 0x10 /* Force Parity Error On Transmit */
110#define FFE 0x20 /* Force Framing Error On Transmit */ 157#define FFE 0x20 /* Force Framing Error On Transmit */
111 158
112#ifdef BFIN_UART_BF54X_STYLE 159#endif /* BFIN_UART_BF60X_STYLE */
160
161/* UART_IER Masks */
162#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
163#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
164#define ELSI 0x04 /* Enable RX Status Interrupt */
165#define EDSSI 0x08 /* Enable Modem Status Interrupt */
166#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
167#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
168#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
169
170#if defined(BFIN_UART_BF60X_STYLE)
171# define OFFSET_REDIV 0x00 /* Version ID Register */
172# define OFFSET_CTL 0x04 /* Control Register */
173# define OFFSET_STAT 0x08 /* Status Register */
174# define OFFSET_SCR 0x0C /* SCR Scratch Register */
175# define OFFSET_CLK 0x10 /* Clock Rate Register */
176# define OFFSET_IER 0x14 /* Interrupt Enable Register */
177# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
178# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
179# define OFFSET_RBR 0x20 /* Receive Buffer register */
180# define OFFSET_THR 0x24 /* Transmit Holding register */
181#elif defined(BFIN_UART_BF54X_STYLE)
113# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 182# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
114# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 183# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
115# define OFFSET_GCTL 0x08 /* Global Control Register */ 184# define OFFSET_GCTL 0x08 /* Global Control Register */
@@ -145,7 +214,23 @@ struct bfin_serial_port {
145 */ 214 */
146#define __BFP(m) u16 m; u16 __pad_##m 215#define __BFP(m) u16 m; u16 __pad_##m
147struct bfin_uart_regs { 216struct bfin_uart_regs {
148#ifdef BFIN_UART_BF54X_STYLE 217#if defined(BFIN_UART_BF60X_STYLE)
218 u32 revid;
219 u32 ctl;
220 u32 stat;
221 u32 scr;
222 u32 clk;
223 u32 ier;
224 u32 ier_set;
225 u32 ier_clear;
226 u32 rbr;
227 u32 thr;
228 u32 taip;
229 u32 tsr;
230 u32 rsr;
231 u32 txdiv;
232 u32 rxdiv;
233#elif defined(BFIN_UART_BF54X_STYLE)
149 __BFP(dll); 234 __BFP(dll);
150 __BFP(dlh); 235 __BFP(dlh);
151 __BFP(gctl); 236 __BFP(gctl);
@@ -182,13 +267,70 @@ struct bfin_uart_regs {
182}; 267};
183#undef __BFP 268#undef __BFP
184 269
270#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
271
272/*
185#ifndef port_membase 273#ifndef port_membase
186# define port_membase(p) 0 274# define port_membase(p) 0
187#endif 275#endif
276*/
277#ifdef BFIN_UART_BF60X_STYLE
278
279#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
280#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
281#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
282#define UART_GET_GCTL(p) UART_GET_CTL(p)
283#define UART_GET_LCR(p) UART_GET_CTL(p)
284#define UART_GET_MCR(p) UART_GET_CTL(p)
285#if ANOMALY_05001001
286#define UART_GET_STAT(p) \
287({ \
288 u32 __ret; \
289 unsigned long flags; \
290 flags = hard_local_irq_save(); \
291 __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
292 hard_local_irq_restore(flags); \
293 __ret; \
294})
295#else
296#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
297#endif
298#define UART_GET_MSR(p) UART_GET_STAT(p)
299
300#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
301#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
302#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
303#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
304#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
305#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
306#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
307
308#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
309#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
310#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
311
312#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
313#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
314
315#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
316#define UART_GET_LSR(p) UART_GET_STAT(p)
317#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
318
319/* This handles hard CTS/RTS */
320#define BFIN_UART_CTSRTS_HARD
321#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
322#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
323#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
324#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
325#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
326#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
327
328#else /* BFIN_UART_BF60X_STYLE */
188 329
189#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) 330#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
190#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) 331#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
191#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) 332#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
333#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
192#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) 334#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
193#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) 335#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
194#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) 336#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
@@ -197,6 +339,11 @@ struct bfin_uart_regs {
197#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) 339#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
198#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) 340#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
199#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) 341#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
342#define UART_PUT_CLK(p, v) do \
343{\
344UART_PUT_DLL(p, v & 0xFF); \
345UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
346
200#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) 347#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
201#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) 348#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
202#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) 349#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
@@ -233,12 +380,17 @@ struct bfin_uart_regs {
233#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) 380#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
234#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) 381#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
235 382
383#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
384#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
385
386/*
236#ifndef put_lsr_cache 387#ifndef put_lsr_cache
237# define put_lsr_cache(p, v) 388# define put_lsr_cache(p, v)
238#endif 389#endif
239#ifndef get_lsr_cache 390#ifndef get_lsr_cache
240# define get_lsr_cache(p) 0 391# define get_lsr_cache(p) 0
241#endif 392#endif
393*/
242 394
243/* The hardware clears the LSR bits upon read, so we need to cache 395/* The hardware clears the LSR bits upon read, so we need to cache
244 * some of the more fun bits in software so they don't get lost 396 * some of the more fun bits in software so they don't get lost
@@ -267,7 +419,9 @@ static inline void UART_PUT_LSR(void *p, uint16_t val)
267#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 419#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
268#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 420#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
269 421
270#endif 422#endif /* BFIN_UART_BF54X_STYLE */
423
424#endif /* BFIN_UART_BF60X_STYLE */
271 425
272#ifndef BFIN_UART_TX_FIFO_SIZE 426#ifndef BFIN_UART_TX_FIFO_SIZE
273# define BFIN_UART_TX_FIFO_SIZE 2 427# define BFIN_UART_TX_FIFO_SIZE 2
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index 0afcfbd54a82..f8907ea6b5b6 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -24,6 +24,7 @@
24struct sport_config { 24struct sport_config {
25 /* TDM (multichannels), I2S or other mode */ 25 /* TDM (multichannels), I2S or other mode */
26 unsigned int mode:3; 26 unsigned int mode:3;
27 unsigned int polled; /* use poll instead of irq when set */
27 28
28 /* if TDM mode is selected, channels must be set */ 29 /* if TDM mode is selected, channels must be set */
29 int channels; /* Must be in 8 units */ 30 int channels; /* Must be in 8 units */
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h
new file mode 100644
index 000000000000..03c00220d69b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_sport3.h
@@ -0,0 +1,107 @@
1/*
2 * bfin_sport - Analog Devices BF6XX SPORT registers
3 *
4 * Copyright (c) 2012 Analog Devices Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef _BFIN_SPORT3_H_
21#define _BFIN_SPORT3_H_
22
23#include <linux/types.h>
24
25#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
26#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
27#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
28#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
29#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
30#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
31#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
32#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
33#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
34#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
35#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
36#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
37#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
38#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
39#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
40#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
41#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
42#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
43#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
44#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrrupt enable select */
45#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
46#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
47#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
48#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
49#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
50#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
51#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
52#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
53#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
54#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
55#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
56#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
57#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
58
59#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
60#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
61
62#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
63#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
64#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
65#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
66#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
67
68#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
69#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
70
71#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
72#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
73#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
74#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
75#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
76#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
77
78#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
79
80#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
81#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
82#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
83
84struct sport_register {
85 u32 spctl;
86 u32 div;
87 u32 spmctl;
88 u32 spcs0;
89 u32 spcs1;
90 u32 spcs2;
91 u32 spcs3;
92 u32 spcnt;
93 u32 sperrctl;
94 u32 spmstat;
95 u32 spctl2;
96 u32 txa;
97 u32 rxa;
98 u32 txb;
99 u32 rxb;
100 u32 revid;
101};
102
103struct bfin_snd_platform_data {
104 const unsigned short *pin_req;
105};
106
107#endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index e767d649dfc4..2f3339a47626 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -10,6 +10,7 @@
10#define __ASM_BFIN_TWI_H__ 10#define __ASM_BFIN_TWI_H__
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/i2c.h>
13 14
14/* 15/*
15 * All Blackfin system MMRs are padded to 32bits even if the register 16 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -42,4 +43,145 @@ struct bfin_twi_regs {
42 43
43#undef __BFP 44#undef __BFP
44 45
46struct bfin_twi_iface {
47 int irq;
48 spinlock_t lock;
49 char read_write;
50 u8 command;
51 u8 *transPtr;
52 int readNum;
53 int writeNum;
54 int cur_mode;
55 int manual_stop;
56 int result;
57 struct i2c_adapter adap;
58 struct completion complete;
59 struct i2c_msg *pmsg;
60 int msg_num;
61 int cur_msg;
62 u16 saved_clkdiv;
63 u16 saved_control;
64 struct bfin_twi_regs *regs_base;
65};
66
67#define DEFINE_TWI_REG(reg_name, reg) \
68static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
69 { return iface->regs_base->reg; } \
70static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
71 { iface->regs_base->reg = v; }
72
73DEFINE_TWI_REG(CLKDIV, clkdiv)
74DEFINE_TWI_REG(CONTROL, control)
75DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
76DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
77DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
78DEFINE_TWI_REG(MASTER_CTL, master_ctl)
79DEFINE_TWI_REG(MASTER_STAT, master_stat)
80DEFINE_TWI_REG(MASTER_ADDR, master_addr)
81DEFINE_TWI_REG(INT_STAT, int_stat)
82DEFINE_TWI_REG(INT_MASK, int_mask)
83DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
84DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
85DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
86DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
87#if !ANOMALY_05001001
88DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
89DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
90#else
91static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
92{
93 u16 ret;
94 unsigned long flags;
95
96 flags = hard_local_irq_save();
97 ret = iface->regs_base->rcv_data8;
98 hard_local_irq_restore(flags);
99
100 return ret;
101}
102
103static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
104{
105 u16 ret;
106 unsigned long flags;
107
108 flags = hard_local_irq_save();
109 ret = iface->regs_base->rcv_data16;
110 hard_local_irq_restore(flags);
111
112 return ret;
113}
114#endif
115
116
117/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
118/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
119#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
120#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
121
122/* TWI_PRESCALE Masks */
123#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
124#define TWI_ENA 0x0080 /* TWI Enable */
125#define SCCB 0x0200 /* SCCB Compatibility Enable */
126
127/* TWI_SLAVE_CTL Masks */
128#define SEN 0x0001 /* Slave Enable */
129#define SADD_LEN 0x0002 /* Slave Address Length */
130#define STDVAL 0x0004 /* Slave Transmit Data Valid */
131#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
132#define GEN 0x0010 /* General Call Address Matching Enabled */
133
134/* TWI_SLAVE_STAT Masks */
135#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
136#define GCALL 0x0002 /* General Call Indicator */
137
138/* TWI_MASTER_CTL Masks */
139#define MEN 0x0001 /* Master Mode Enable */
140#define MADD_LEN 0x0002 /* Master Address Length */
141#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
142#define FAST 0x0008 /* Use Fast Mode Timing Specs */
143#define STOP 0x0010 /* Issue Stop Condition */
144#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
145#define DCNT 0x3FC0 /* Data Bytes To Transfer */
146#define SDAOVR 0x4000 /* Serial Data Override */
147#define SCLOVR 0x8000 /* Serial Clock Override */
148
149/* TWI_MASTER_STAT Masks */
150#define MPROG 0x0001 /* Master Transfer In Progress */
151#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
152#define ANAK 0x0004 /* Address Not Acknowledged */
153#define DNAK 0x0008 /* Data Not Acknowledged */
154#define BUFRDERR 0x0010 /* Buffer Read Error */
155#define BUFWRERR 0x0020 /* Buffer Write Error */
156#define SDASEN 0x0040 /* Serial Data Sense */
157#define SCLSEN 0x0080 /* Serial Clock Sense */
158#define BUSBUSY 0x0100 /* Bus Busy Indicator */
159
160/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
161#define SINIT 0x0001 /* Slave Transfer Initiated */
162#define SCOMP 0x0002 /* Slave Transfer Complete */
163#define SERR 0x0004 /* Slave Transfer Error */
164#define SOVF 0x0008 /* Slave Overflow */
165#define MCOMP 0x0010 /* Master Transfer Complete */
166#define MERR 0x0020 /* Master Transfer Error */
167#define XMTSERV 0x0040 /* Transmit FIFO Service */
168#define RCVSERV 0x0080 /* Receive FIFO Service */
169
170/* TWI_FIFO_CTRL Masks */
171#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
172#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
173#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
174#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
175
176/* TWI_FIFO_STAT Masks */
177#define XMTSTAT 0x0003 /* Transmit FIFO Status */
178#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
179#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
180#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
181
182#define RCVSTAT 0x000C /* Receive FIFO Status */
183#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
184#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
185#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
186
45#endif 187#endif
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index 7be5368c0512..f111f366d758 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -63,20 +63,16 @@ static inline void CSYNC(void)
63 63
64#if ANOMALY_05000312 || ANOMALY_05000244 64#if ANOMALY_05000312 || ANOMALY_05000244
65#define SSYNC(scratch) \ 65#define SSYNC(scratch) \
66do { \
67 cli scratch; \ 66 cli scratch; \
68 nop; nop; nop; \ 67 nop; nop; nop; \
69 SSYNC; \ 68 SSYNC; \
70 sti scratch; \ 69 sti scratch;
71} while (0)
72 70
73#define CSYNC(scratch) \ 71#define CSYNC(scratch) \
74do { \
75 cli scratch; \ 72 cli scratch; \
76 nop; nop; nop; \ 73 nop; nop; nop; \
77 CSYNC; \ 74 CSYNC; \
78 sti scratch; \ 75 sti scratch;
79} while (0)
80 76
81#else 77#else
82#define SSYNC(scratch) SSYNC; 78#define SSYNC(scratch) SSYNC;
diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h
new file mode 100644
index 000000000000..9053beda8c50
--- /dev/null
+++ b/arch/blackfin/include/asm/clkdev.h
@@ -0,0 +1,14 @@
1#ifndef __ASM_CLKDEV__H_
2#define __ASM_CLKDEV__H_
3
4#include <linux/slab.h>
5
6static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
7{
8 return kzalloc(size, GFP_KERNEL);
9}
10
11#define __clk_put(clk)
12#define __clk_get(clk) ({ 1; })
13
14#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
index 6f0b61852f58..9b3c85b3c288 100644
--- a/arch/blackfin/include/asm/clocks.h
+++ b/arch/blackfin/include/asm/clocks.h
@@ -48,4 +48,27 @@
48# define CONFIG_VCO_MULT 0 48# define CONFIG_VCO_MULT 0
49#endif 49#endif
50 50
51#include <linux/clk.h>
52
53struct clk_ops {
54 unsigned long (*get_rate)(struct clk *clk);
55 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
56 int (*set_rate)(struct clk *clk, unsigned long rate);
57 int (*enable)(struct clk *clk);
58 int (*disable)(struct clk *clk);
59};
60
61struct clk {
62 struct clk *parent;
63 const char *name;
64 unsigned long rate;
65 spinlock_t lock;
66 u32 flags;
67 const struct clk_ops *ops;
68 void __iomem *reg;
69 u32 mask;
70 u32 shift;
71};
72
73int clk_init(void);
51#endif 74#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index fda96261ed62..5c37f620c4b3 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -62,6 +62,10 @@
62#define SIZE_4K 0x00001000 /* 4K */ 62#define SIZE_4K 0x00001000 /* 4K */
63#define SIZE_1M 0x00100000 /* 1M */ 63#define SIZE_1M 0x00100000 /* 1M */
64#define SIZE_4M 0x00400000 /* 4M */ 64#define SIZE_4M 0x00400000 /* 4M */
65#define SIZE_16K 0x00004000 /* 16K */
66#define SIZE_64K 0x00010000 /* 64K */
67#define SIZE_16M 0x01000000 /* 16M */
68#define SIZE_64M 0x04000000 /* 64M */
65 69
66#define MAX_CPLBS 16 70#define MAX_CPLBS 16
67 71
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 823679011457..fe0ca03a1cb2 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright 2005-2008 Analog Devices Inc. 4 * Copyright 2005-2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the ADI BSD license or GPL-2 (or later). 6 * Licensed under the Clear BSD license or GPL-2 (or later).
7 */ 7 */
8 8
9#ifndef _DEF_LPBLACKFIN_H 9#ifndef _DEF_LPBLACKFIN_H
@@ -622,6 +622,10 @@ do { \
622#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 622#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
623#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 623#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
624#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ 624#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
625#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
626#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
627#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
628#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
625#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not 629#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
626 * mapped to L1 630 * mapped to L1
627 */ 631 */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index dac0c97242bb..40e9c2bbc6e3 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -22,12 +22,22 @@
22#define DATA_SIZE_8 0 22#define DATA_SIZE_8 0
23#define DATA_SIZE_16 1 23#define DATA_SIZE_16 1
24#define DATA_SIZE_32 2 24#define DATA_SIZE_32 2
25#ifdef CONFIG_BF60x
26#define DATA_SIZE_64 3
27#endif
25 28
26#define DMA_FLOW_STOP 0 29#define DMA_FLOW_STOP 0
27#define DMA_FLOW_AUTO 1 30#define DMA_FLOW_AUTO 1
31#ifdef CONFIG_BF60x
32#define DMA_FLOW_LIST 4
33#define DMA_FLOW_ARRAY 5
34#define DMA_FLOW_LIST_DEMAND 6
35#define DMA_FLOW_ARRAY_DEMAND 7
36#else
28#define DMA_FLOW_ARRAY 4 37#define DMA_FLOW_ARRAY 4
29#define DMA_FLOW_SMALL 6 38#define DMA_FLOW_SMALL 6
30#define DMA_FLOW_LARGE 7 39#define DMA_FLOW_LARGE 7
40#endif
31 41
32#define DIMENSION_LINEAR 0 42#define DIMENSION_LINEAR 0
33#define DIMENSION_2D 1 43#define DIMENSION_2D 1
@@ -36,26 +46,80 @@
36#define DIR_WRITE 1 46#define DIR_WRITE 1
37 47
38#define INTR_DISABLE 0 48#define INTR_DISABLE 0
49#ifdef CONFIG_BF60x
50#define INTR_ON_PERI 1
51#endif
39#define INTR_ON_BUF 2 52#define INTR_ON_BUF 2
40#define INTR_ON_ROW 3 53#define INTR_ON_ROW 3
41 54
42#define DMA_NOSYNC_KEEP_DMA_BUF 0 55#define DMA_NOSYNC_KEEP_DMA_BUF 0
43#define DMA_SYNC_RESTART 1 56#define DMA_SYNC_RESTART 1
44 57
58#ifdef DMA_MMR_SIZE_32
59#define DMA_MMR_SIZE_TYPE long
60#define DMA_MMR_READ bfin_read32
61#define DMA_MMR_WRITE bfin_write32
62#else
63#define DMA_MMR_SIZE_TYPE short
64#define DMA_MMR_READ bfin_read16
65#define DMA_MMR_WRITE bfin_write16
66#endif
67
68struct dma_desc_array {
69 unsigned long start_addr;
70 unsigned DMA_MMR_SIZE_TYPE cfg;
71 unsigned DMA_MMR_SIZE_TYPE x_count;
72 DMA_MMR_SIZE_TYPE x_modify;
73} __attribute__((packed));
74
45struct dmasg { 75struct dmasg {
46 void *next_desc_addr; 76 void *next_desc_addr;
47 unsigned long start_addr; 77 unsigned long start_addr;
48 unsigned short cfg; 78 unsigned DMA_MMR_SIZE_TYPE cfg;
49 unsigned short x_count; 79 unsigned DMA_MMR_SIZE_TYPE x_count;
50 short x_modify; 80 DMA_MMR_SIZE_TYPE x_modify;
51 unsigned short y_count; 81 unsigned DMA_MMR_SIZE_TYPE y_count;
52 short y_modify; 82 DMA_MMR_SIZE_TYPE y_modify;
53} __attribute__((packed)); 83} __attribute__((packed));
54 84
55struct dma_register { 85struct dma_register {
56 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ 86 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
57 unsigned long start_addr; /* DMA Start address register */ 87 unsigned long start_addr; /* DMA Start address register */
88#ifdef CONFIG_BF60x
89 unsigned long cfg; /* DMA Configuration register */
58 90
91 unsigned long x_count; /* DMA x_count register */
92
93 long x_modify; /* DMA x_modify register */
94
95 unsigned long y_count; /* DMA y_count register */
96
97 long y_modify; /* DMA y_modify register */
98
99 unsigned long reserved;
100 unsigned long reserved2;
101
102 void *curr_desc_ptr; /* DMA Current Descriptor Pointer
103 register */
104 void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
105 register */
106 unsigned long curr_addr_ptr; /* DMA Current Address Pointer
107 register */
108 unsigned long irq_status; /* DMA irq status register */
109
110 unsigned long curr_x_count; /* DMA Current x-count register */
111
112 unsigned long curr_y_count; /* DMA Current y-count register */
113
114 unsigned long reserved3;
115
116 unsigned long bw_limit_count; /* DMA band width limit count register */
117 unsigned long curr_bw_limit_count; /* DMA Current band width limit
118 count register */
119 unsigned long bw_monitor_count; /* DMA band width limit count register */
120 unsigned long curr_bw_monitor_count; /* DMA Current band width limit
121 count register */
122#else
59 unsigned short cfg; /* DMA Configuration register */ 123 unsigned short cfg; /* DMA Configuration register */
60 unsigned short dummy1; /* DMA Configuration register */ 124 unsigned short dummy1; /* DMA Configuration register */
61 125
@@ -92,6 +156,7 @@ struct dma_register {
92 unsigned short dummy9; 156 unsigned short dummy9;
93 157
94 unsigned long reserved3; 158 unsigned long reserved3;
159#endif
95 160
96}; 161};
97 162
@@ -131,23 +196,23 @@ static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
131{ 196{
132 dma_ch[channel].regs->curr_desc_ptr = addr; 197 dma_ch[channel].regs->curr_desc_ptr = addr;
133} 198}
134static inline void set_dma_x_count(unsigned int channel, unsigned short x_count) 199static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
135{ 200{
136 dma_ch[channel].regs->x_count = x_count; 201 dma_ch[channel].regs->x_count = x_count;
137} 202}
138static inline void set_dma_y_count(unsigned int channel, unsigned short y_count) 203static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
139{ 204{
140 dma_ch[channel].regs->y_count = y_count; 205 dma_ch[channel].regs->y_count = y_count;
141} 206}
142static inline void set_dma_x_modify(unsigned int channel, short x_modify) 207static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
143{ 208{
144 dma_ch[channel].regs->x_modify = x_modify; 209 dma_ch[channel].regs->x_modify = x_modify;
145} 210}
146static inline void set_dma_y_modify(unsigned int channel, short y_modify) 211static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
147{ 212{
148 dma_ch[channel].regs->y_modify = y_modify; 213 dma_ch[channel].regs->y_modify = y_modify;
149} 214}
150static inline void set_dma_config(unsigned int channel, unsigned short config) 215static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
151{ 216{
152 dma_ch[channel].regs->cfg = config; 217 dma_ch[channel].regs->cfg = config;
153} 218}
@@ -156,23 +221,55 @@ static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
156 dma_ch[channel].regs->curr_addr_ptr = addr; 221 dma_ch[channel].regs->curr_addr_ptr = addr;
157} 222}
158 223
159static inline unsigned short 224#ifdef CONFIG_BF60x
225static inline unsigned long
226set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
227 char dma_mode, char mem_width, char syncmode, char peri_width)
228{
229 unsigned long config = 0;
230
231 switch (intr_mode) {
232 case INTR_ON_BUF:
233 if (dma_mode == DIMENSION_2D)
234 config = DI_EN_Y;
235 else
236 config = DI_EN_X;
237 break;
238 case INTR_ON_ROW:
239 config = DI_EN_X;
240 break;
241 case INTR_ON_PERI:
242 config = DI_EN_P;
243 break;
244 };
245
246 return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
247 (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
248}
249#endif
250
251static inline unsigned DMA_MMR_SIZE_TYPE
160set_bfin_dma_config(char direction, char flow_mode, 252set_bfin_dma_config(char direction, char flow_mode,
161 char intr_mode, char dma_mode, char width, char syncmode) 253 char intr_mode, char dma_mode, char mem_width, char syncmode)
162{ 254{
163 return (direction << 1) | (width << 2) | (dma_mode << 4) | 255#ifdef CONFIG_BF60x
256 return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
257 mem_width, syncmode, mem_width);
258#else
259 return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
164 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); 260 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
261#endif
165} 262}
166 263
167static inline unsigned short get_dma_curr_irqstat(unsigned int channel) 264static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
168{ 265{
169 return dma_ch[channel].regs->irq_status; 266 return dma_ch[channel].regs->irq_status;
170} 267}
171static inline unsigned short get_dma_curr_xcount(unsigned int channel) 268static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
172{ 269{
173 return dma_ch[channel].regs->curr_x_count; 270 return dma_ch[channel].regs->curr_x_count;
174} 271}
175static inline unsigned short get_dma_curr_ycount(unsigned int channel) 272static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
176{ 273{
177 return dma_ch[channel].regs->curr_y_count; 274 return dma_ch[channel].regs->curr_y_count;
178} 275}
@@ -184,7 +281,7 @@ static inline void *get_dma_curr_desc_ptr(unsigned int channel)
184{ 281{
185 return dma_ch[channel].regs->curr_desc_ptr; 282 return dma_ch[channel].regs->curr_desc_ptr;
186} 283}
187static inline unsigned short get_dma_config(unsigned int channel) 284static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
188{ 285{
189 return dma_ch[channel].regs->cfg; 286 return dma_ch[channel].regs->cfg;
190} 287}
@@ -203,8 +300,8 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
203 300
204 dma_ch[channel].regs->next_desc_ptr = sg; 301 dma_ch[channel].regs->next_desc_ptr = sg;
205 dma_ch[channel].regs->cfg = 302 dma_ch[channel].regs->cfg =
206 (dma_ch[channel].regs->cfg & ~(0xf << 8)) | 303 (dma_ch[channel].regs->cfg & ~NDSIZE) |
207 ((ndsize & 0xf) << 8); 304 ((ndsize << NDSIZE_OFFSET) & NDSIZE);
208} 305}
209 306
210static inline int dma_channel_active(unsigned int channel) 307static inline int dma_channel_active(unsigned int channel)
@@ -239,7 +336,7 @@ static inline void dma_enable_irq(unsigned int channel)
239} 336}
240static inline void clear_dma_irqstat(unsigned int channel) 337static inline void clear_dma_irqstat(unsigned int channel)
241{ 338{
242 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR; 339 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
243} 340}
244 341
245void *dma_memcpy(void *dest, const void *src, size_t count); 342void *dma_memcpy(void *dest, const void *src, size_t count);
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index c4ec959dad78..e91eae8330a6 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,651 @@
9#ifndef _BLACKFIN_DPMC_H_ 9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_
11 11
12#ifdef __ASSEMBLY__
13#define PM_REG0 R7
14#define PM_REG1 R6
15#define PM_REG2 R5
16#define PM_REG3 R4
17#define PM_REG4 R3
18#define PM_REG5 R2
19#define PM_REG6 R1
20#define PM_REG7 R0
21#define PM_REG8 P5
22#define PM_REG9 P4
23#define PM_REG10 P3
24#define PM_REG11 P2
25#define PM_REG12 P1
26#define PM_REG13 P0
27
28#define PM_REGSET0 R7:7
29#define PM_REGSET1 R7:6
30#define PM_REGSET2 R7:5
31#define PM_REGSET3 R7:4
32#define PM_REGSET4 R7:3
33#define PM_REGSET5 R7:2
34#define PM_REGSET6 R7:1
35#define PM_REGSET7 R7:0
36#define PM_REGSET8 R7:0, P5:5
37#define PM_REGSET9 R7:0, P5:4
38#define PM_REGSET10 R7:0, P5:3
39#define PM_REGSET11 R7:0, P5:2
40#define PM_REGSET12 R7:0, P5:1
41#define PM_REGSET13 R7:0, P5:0
42
43#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
44#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
45#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
46#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
47#define PM_PUSH(n, x) PM_REG##n = [FP++];
48#define PM_POP(n, x) [FP--] = PM_REG##n;
49#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
50#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
51#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
52#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
53#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
54#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
55
56 .macro bfin_init_pm_bench_cycles
57#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
58 R4 = 0;
59 CYCLES = R4;
60 CYCLES2 = R4;
61 R4 = SYSCFG;
62 BITSET(R4, 1);
63 SYSCFG = R4;
64#endif
65 .endm
66
67 .macro bfin_cpu_reg_save
68 /*
69 * Save the core regs early so we can blow them away when
70 * saving/restoring MMR states
71 */
72 [--sp] = (R7:0, P5:0);
73 [--sp] = fp;
74 [--sp] = usp;
75
76 [--sp] = i0;
77 [--sp] = i1;
78 [--sp] = i2;
79 [--sp] = i3;
80
81 [--sp] = m0;
82 [--sp] = m1;
83 [--sp] = m2;
84 [--sp] = m3;
85
86 [--sp] = l0;
87 [--sp] = l1;
88 [--sp] = l2;
89 [--sp] = l3;
90
91 [--sp] = b0;
92 [--sp] = b1;
93 [--sp] = b2;
94 [--sp] = b3;
95 [--sp] = a0.x;
96 [--sp] = a0.w;
97 [--sp] = a1.x;
98 [--sp] = a1.w;
99
100 [--sp] = LC0;
101 [--sp] = LC1;
102 [--sp] = LT0;
103 [--sp] = LT1;
104 [--sp] = LB0;
105 [--sp] = LB1;
106
107 /* We can't push RETI directly as that'll change IPEND[4] */
108 r7 = RETI;
109 [--sp] = RETS;
110 [--sp] = ASTAT;
111#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
112 [--sp] = CYCLES;
113 [--sp] = CYCLES2;
114#endif
115 [--sp] = SYSCFG;
116 [--sp] = RETX;
117 [--sp] = SEQSTAT;
118 [--sp] = r7;
119
120 /* Save first func arg in M3 */
121 M3 = R0;
122 .endm
123
124 .macro bfin_cpu_reg_restore
125 /* Restore Core Registers */
126 RETI = [sp++];
127 SEQSTAT = [sp++];
128 RETX = [sp++];
129 SYSCFG = [sp++];
130#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
131 CYCLES2 = [sp++];
132 CYCLES = [sp++];
133#endif
134 ASTAT = [sp++];
135 RETS = [sp++];
136
137 LB1 = [sp++];
138 LB0 = [sp++];
139 LT1 = [sp++];
140 LT0 = [sp++];
141 LC1 = [sp++];
142 LC0 = [sp++];
143
144 a1.w = [sp++];
145 a1.x = [sp++];
146 a0.w = [sp++];
147 a0.x = [sp++];
148 b3 = [sp++];
149 b2 = [sp++];
150 b1 = [sp++];
151 b0 = [sp++];
152
153 l3 = [sp++];
154 l2 = [sp++];
155 l1 = [sp++];
156 l0 = [sp++];
157
158 m3 = [sp++];
159 m2 = [sp++];
160 m1 = [sp++];
161 m0 = [sp++];
162
163 i3 = [sp++];
164 i2 = [sp++];
165 i1 = [sp++];
166 i0 = [sp++];
167
168 usp = [sp++];
169 fp = [sp++];
170 (R7:0, P5:0) = [sp++];
171
172 .endm
173
174 .macro bfin_sys_mmr_save
175 /* Save system MMRs */
176 FP.H = hi(SYSMMR_BASE);
177 FP.L = lo(SYSMMR_BASE);
178#ifdef SIC_IMASK0
179 PM_SYS_PUSH(0, SIC_IMASK0)
180 PM_SYS_PUSH(1, SIC_IMASK1)
181# ifdef SIC_IMASK2
182 PM_SYS_PUSH(2, SIC_IMASK2)
183# endif
184#else
185# ifdef SIC_IMASK
186 PM_SYS_PUSH(0, SIC_IMASK)
187# endif
188#endif
189
190#ifdef SIC_IAR0
191 PM_SYS_PUSH(3, SIC_IAR0)
192 PM_SYS_PUSH(4, SIC_IAR1)
193 PM_SYS_PUSH(5, SIC_IAR2)
194#endif
195#ifdef SIC_IAR3
196 PM_SYS_PUSH(6, SIC_IAR3)
197#endif
198#ifdef SIC_IAR4
199 PM_SYS_PUSH(7, SIC_IAR4)
200 PM_SYS_PUSH(8, SIC_IAR5)
201 PM_SYS_PUSH(9, SIC_IAR6)
202#endif
203#ifdef SIC_IAR7
204 PM_SYS_PUSH(10, SIC_IAR7)
205#endif
206#ifdef SIC_IAR8
207 PM_SYS_PUSH(11, SIC_IAR8)
208 PM_SYS_PUSH(12, SIC_IAR9)
209 PM_SYS_PUSH(13, SIC_IAR10)
210#endif
211 PM_PUSH_SYNC(13)
212#ifdef SIC_IAR11
213 PM_SYS_PUSH(0, SIC_IAR11)
214#endif
215
216#ifdef SIC_IWR
217 PM_SYS_PUSH(1, SIC_IWR)
218#endif
219#ifdef SIC_IWR0
220 PM_SYS_PUSH(1, SIC_IWR0)
221#endif
222#ifdef SIC_IWR1
223 PM_SYS_PUSH(2, SIC_IWR1)
224#endif
225#ifdef SIC_IWR2
226 PM_SYS_PUSH(3, SIC_IWR2)
227#endif
228
229#ifdef PINT0_ASSIGN
230 PM_SYS_PUSH(4, PINT0_MASK_SET)
231 PM_SYS_PUSH(5, PINT1_MASK_SET)
232 PM_SYS_PUSH(6, PINT2_MASK_SET)
233 PM_SYS_PUSH(7, PINT3_MASK_SET)
234 PM_SYS_PUSH(8, PINT0_ASSIGN)
235 PM_SYS_PUSH(9, PINT1_ASSIGN)
236 PM_SYS_PUSH(10, PINT2_ASSIGN)
237 PM_SYS_PUSH(11, PINT3_ASSIGN)
238 PM_SYS_PUSH(12, PINT0_INVERT_SET)
239 PM_SYS_PUSH(13, PINT1_INVERT_SET)
240 PM_PUSH_SYNC(13)
241 PM_SYS_PUSH(0, PINT2_INVERT_SET)
242 PM_SYS_PUSH(1, PINT3_INVERT_SET)
243 PM_SYS_PUSH(2, PINT0_EDGE_SET)
244 PM_SYS_PUSH(3, PINT1_EDGE_SET)
245 PM_SYS_PUSH(4, PINT2_EDGE_SET)
246 PM_SYS_PUSH(5, PINT3_EDGE_SET)
247#endif
248
249#ifdef SYSCR
250 PM_SYS_PUSH16(6, SYSCR)
251#endif
252
253#ifdef EBIU_AMGCTL
254 PM_SYS_PUSH16(7, EBIU_AMGCTL)
255 PM_SYS_PUSH(8, EBIU_AMBCTL0)
256 PM_SYS_PUSH(9, EBIU_AMBCTL1)
257#endif
258#ifdef EBIU_FCTL
259 PM_SYS_PUSH(10, EBIU_MBSCTL)
260 PM_SYS_PUSH(11, EBIU_MODE)
261 PM_SYS_PUSH(12, EBIU_FCTL)
262 PM_PUSH_SYNC(12)
263#else
264 PM_PUSH_SYNC(9)
265#endif
266 .endm
267
268
269 .macro bfin_sys_mmr_restore
270/* Restore System MMRs */
271 FP.H = hi(SYSMMR_BASE);
272 FP.L = lo(SYSMMR_BASE);
273
274#ifdef EBIU_FCTL
275 PM_POP_SYNC(12)
276 PM_SYS_POP(12, EBIU_FCTL)
277 PM_SYS_POP(11, EBIU_MODE)
278 PM_SYS_POP(10, EBIU_MBSCTL)
279#else
280 PM_POP_SYNC(9)
281#endif
282
283#ifdef EBIU_AMBCTL
284 PM_SYS_POP(9, EBIU_AMBCTL1)
285 PM_SYS_POP(8, EBIU_AMBCTL0)
286 PM_SYS_POP16(7, EBIU_AMGCTL)
287#endif
288
289#ifdef SYSCR
290 PM_SYS_POP16(6, SYSCR)
291#endif
292
293#ifdef PINT0_ASSIGN
294 PM_SYS_POP(5, PINT3_EDGE_SET)
295 PM_SYS_POP(4, PINT2_EDGE_SET)
296 PM_SYS_POP(3, PINT1_EDGE_SET)
297 PM_SYS_POP(2, PINT0_EDGE_SET)
298 PM_SYS_POP(1, PINT3_INVERT_SET)
299 PM_SYS_POP(0, PINT2_INVERT_SET)
300 PM_POP_SYNC(13)
301 PM_SYS_POP(13, PINT1_INVERT_SET)
302 PM_SYS_POP(12, PINT0_INVERT_SET)
303 PM_SYS_POP(11, PINT3_ASSIGN)
304 PM_SYS_POP(10, PINT2_ASSIGN)
305 PM_SYS_POP(9, PINT1_ASSIGN)
306 PM_SYS_POP(8, PINT0_ASSIGN)
307 PM_SYS_POP(7, PINT3_MASK_SET)
308 PM_SYS_POP(6, PINT2_MASK_SET)
309 PM_SYS_POP(5, PINT1_MASK_SET)
310 PM_SYS_POP(4, PINT0_MASK_SET)
311#endif
312
313#ifdef SIC_IWR2
314 PM_SYS_POP(3, SIC_IWR2)
315#endif
316#ifdef SIC_IWR1
317 PM_SYS_POP(2, SIC_IWR1)
318#endif
319#ifdef SIC_IWR0
320 PM_SYS_POP(1, SIC_IWR0)
321#endif
322#ifdef SIC_IWR
323 PM_SYS_POP(1, SIC_IWR)
324#endif
325
326#ifdef SIC_IAR11
327 PM_SYS_POP(0, SIC_IAR11)
328#endif
329 PM_POP_SYNC(13)
330#ifdef SIC_IAR8
331 PM_SYS_POP(13, SIC_IAR10)
332 PM_SYS_POP(12, SIC_IAR9)
333 PM_SYS_POP(11, SIC_IAR8)
334#endif
335#ifdef SIC_IAR7
336 PM_SYS_POP(10, SIC_IAR7)
337#endif
338#ifdef SIC_IAR6
339 PM_SYS_POP(9, SIC_IAR6)
340 PM_SYS_POP(8, SIC_IAR5)
341 PM_SYS_POP(7, SIC_IAR4)
342#endif
343#ifdef SIC_IAR3
344 PM_SYS_POP(6, SIC_IAR3)
345#endif
346#ifdef SIC_IAR0
347 PM_SYS_POP(5, SIC_IAR2)
348 PM_SYS_POP(4, SIC_IAR1)
349 PM_SYS_POP(3, SIC_IAR0)
350#endif
351#ifdef SIC_IMASK0
352# ifdef SIC_IMASK2
353 PM_SYS_POP(2, SIC_IMASK2)
354# endif
355 PM_SYS_POP(1, SIC_IMASK1)
356 PM_SYS_POP(0, SIC_IMASK0)
357#else
358# ifdef SIC_IMASK
359 PM_SYS_POP(0, SIC_IMASK)
360# endif
361#endif
362 .endm
363
364 .macro bfin_core_mmr_save
365 /* Save Core MMRs */
366 I0.H = hi(COREMMR_BASE);
367 I0.L = lo(COREMMR_BASE);
368 I1 = I0;
369 I2 = I0;
370 I3 = I0;
371 B0 = I0;
372 B1 = I0;
373 B2 = I0;
374 B3 = I0;
375 I1.L = lo(DCPLB_ADDR0);
376 I2.L = lo(DCPLB_DATA0);
377 I3.L = lo(ICPLB_ADDR0);
378 B0.L = lo(ICPLB_DATA0);
379 B1.L = lo(EVT2);
380 B2.L = lo(IMASK);
381 B3.L = lo(TCNTL);
382
383 /* Event Vectors */
384 FP = B1;
385 PM_PUSH(0, EVT2)
386 PM_PUSH(1, EVT3)
387 FP += 4; /* EVT4 */
388 PM_PUSH(2, EVT5)
389 PM_PUSH(3, EVT6)
390 PM_PUSH(4, EVT7)
391 PM_PUSH(5, EVT8)
392 PM_PUSH_SYNC(5)
393
394 PM_PUSH(0, EVT9)
395 PM_PUSH(1, EVT10)
396 PM_PUSH(2, EVT11)
397 PM_PUSH(3, EVT12)
398 PM_PUSH(4, EVT13)
399 PM_PUSH(5, EVT14)
400 PM_PUSH(6, EVT15)
401
402 /* CEC */
403 FP = B2;
404 PM_PUSH(7, IMASK)
405 FP += 4; /* IPEND */
406 PM_PUSH(8, ILAT)
407 PM_PUSH(9, IPRIO)
408
409 /* Core Timer */
410 FP = B3;
411 PM_PUSH(10, TCNTL)
412 PM_PUSH(11, TPERIOD)
413 PM_PUSH(12, TSCALE)
414 PM_PUSH(13, TCOUNT)
415 PM_PUSH_SYNC(13)
416
417 /* Misc non-contiguous registers */
418 FP = I0;
419 PM_CORE_PUSH(0, DMEM_CONTROL);
420 PM_CORE_PUSH(1, IMEM_CONTROL);
421 PM_CORE_PUSH(2, TBUFCTL);
422 PM_PUSH_SYNC(2)
423
424 /* DCPLB Addr */
425 FP = I1;
426 PM_PUSH(0, DCPLB_ADDR0)
427 PM_PUSH(1, DCPLB_ADDR1)
428 PM_PUSH(2, DCPLB_ADDR2)
429 PM_PUSH(3, DCPLB_ADDR3)
430 PM_PUSH(4, DCPLB_ADDR4)
431 PM_PUSH(5, DCPLB_ADDR5)
432 PM_PUSH(6, DCPLB_ADDR6)
433 PM_PUSH(7, DCPLB_ADDR7)
434 PM_PUSH(8, DCPLB_ADDR8)
435 PM_PUSH(9, DCPLB_ADDR9)
436 PM_PUSH(10, DCPLB_ADDR10)
437 PM_PUSH(11, DCPLB_ADDR11)
438 PM_PUSH(12, DCPLB_ADDR12)
439 PM_PUSH(13, DCPLB_ADDR13)
440 PM_PUSH_SYNC(13)
441 PM_PUSH(0, DCPLB_ADDR14)
442 PM_PUSH(1, DCPLB_ADDR15)
443
444 /* DCPLB Data */
445 FP = I2;
446 PM_PUSH(2, DCPLB_DATA0)
447 PM_PUSH(3, DCPLB_DATA1)
448 PM_PUSH(4, DCPLB_DATA2)
449 PM_PUSH(5, DCPLB_DATA3)
450 PM_PUSH(6, DCPLB_DATA4)
451 PM_PUSH(7, DCPLB_DATA5)
452 PM_PUSH(8, DCPLB_DATA6)
453 PM_PUSH(9, DCPLB_DATA7)
454 PM_PUSH(10, DCPLB_DATA8)
455 PM_PUSH(11, DCPLB_DATA9)
456 PM_PUSH(12, DCPLB_DATA10)
457 PM_PUSH(13, DCPLB_DATA11)
458 PM_PUSH_SYNC(13)
459 PM_PUSH(0, DCPLB_DATA12)
460 PM_PUSH(1, DCPLB_DATA13)
461 PM_PUSH(2, DCPLB_DATA14)
462 PM_PUSH(3, DCPLB_DATA15)
463
464 /* ICPLB Addr */
465 FP = I3;
466 PM_PUSH(4, ICPLB_ADDR0)
467 PM_PUSH(5, ICPLB_ADDR1)
468 PM_PUSH(6, ICPLB_ADDR2)
469 PM_PUSH(7, ICPLB_ADDR3)
470 PM_PUSH(8, ICPLB_ADDR4)
471 PM_PUSH(9, ICPLB_ADDR5)
472 PM_PUSH(10, ICPLB_ADDR6)
473 PM_PUSH(11, ICPLB_ADDR7)
474 PM_PUSH(12, ICPLB_ADDR8)
475 PM_PUSH(13, ICPLB_ADDR9)
476 PM_PUSH_SYNC(13)
477 PM_PUSH(0, ICPLB_ADDR10)
478 PM_PUSH(1, ICPLB_ADDR11)
479 PM_PUSH(2, ICPLB_ADDR12)
480 PM_PUSH(3, ICPLB_ADDR13)
481 PM_PUSH(4, ICPLB_ADDR14)
482 PM_PUSH(5, ICPLB_ADDR15)
483
484 /* ICPLB Data */
485 FP = B0;
486 PM_PUSH(6, ICPLB_DATA0)
487 PM_PUSH(7, ICPLB_DATA1)
488 PM_PUSH(8, ICPLB_DATA2)
489 PM_PUSH(9, ICPLB_DATA3)
490 PM_PUSH(10, ICPLB_DATA4)
491 PM_PUSH(11, ICPLB_DATA5)
492 PM_PUSH(12, ICPLB_DATA6)
493 PM_PUSH(13, ICPLB_DATA7)
494 PM_PUSH_SYNC(13)
495 PM_PUSH(0, ICPLB_DATA8)
496 PM_PUSH(1, ICPLB_DATA9)
497 PM_PUSH(2, ICPLB_DATA10)
498 PM_PUSH(3, ICPLB_DATA11)
499 PM_PUSH(4, ICPLB_DATA12)
500 PM_PUSH(5, ICPLB_DATA13)
501 PM_PUSH(6, ICPLB_DATA14)
502 PM_PUSH(7, ICPLB_DATA15)
503 PM_PUSH_SYNC(7)
504 .endm
505
506 .macro bfin_core_mmr_restore
507 /* Restore Core MMRs */
508 I0.H = hi(COREMMR_BASE);
509 I0.L = lo(COREMMR_BASE);
510 I1 = I0;
511 I2 = I0;
512 I3 = I0;
513 B0 = I0;
514 B1 = I0;
515 B2 = I0;
516 B3 = I0;
517 I1.L = lo(DCPLB_ADDR15);
518 I2.L = lo(DCPLB_DATA15);
519 I3.L = lo(ICPLB_ADDR15);
520 B0.L = lo(ICPLB_DATA15);
521 B1.L = lo(EVT15);
522 B2.L = lo(IPRIO);
523 B3.L = lo(TCOUNT);
524
525 /* ICPLB Data */
526 FP = B0;
527 PM_POP_SYNC(7)
528 PM_POP(7, ICPLB_DATA15)
529 PM_POP(6, ICPLB_DATA14)
530 PM_POP(5, ICPLB_DATA13)
531 PM_POP(4, ICPLB_DATA12)
532 PM_POP(3, ICPLB_DATA11)
533 PM_POP(2, ICPLB_DATA10)
534 PM_POP(1, ICPLB_DATA9)
535 PM_POP(0, ICPLB_DATA8)
536 PM_POP_SYNC(13)
537 PM_POP(13, ICPLB_DATA7)
538 PM_POP(12, ICPLB_DATA6)
539 PM_POP(11, ICPLB_DATA5)
540 PM_POP(10, ICPLB_DATA4)
541 PM_POP(9, ICPLB_DATA3)
542 PM_POP(8, ICPLB_DATA2)
543 PM_POP(7, ICPLB_DATA1)
544 PM_POP(6, ICPLB_DATA0)
545
546 /* ICPLB Addr */
547 FP = I3;
548 PM_POP(5, ICPLB_ADDR15)
549 PM_POP(4, ICPLB_ADDR14)
550 PM_POP(3, ICPLB_ADDR13)
551 PM_POP(2, ICPLB_ADDR12)
552 PM_POP(1, ICPLB_ADDR11)
553 PM_POP(0, ICPLB_ADDR10)
554 PM_POP_SYNC(13)
555 PM_POP(13, ICPLB_ADDR9)
556 PM_POP(12, ICPLB_ADDR8)
557 PM_POP(11, ICPLB_ADDR7)
558 PM_POP(10, ICPLB_ADDR6)
559 PM_POP(9, ICPLB_ADDR5)
560 PM_POP(8, ICPLB_ADDR4)
561 PM_POP(7, ICPLB_ADDR3)
562 PM_POP(6, ICPLB_ADDR2)
563 PM_POP(5, ICPLB_ADDR1)
564 PM_POP(4, ICPLB_ADDR0)
565
566 /* DCPLB Data */
567 FP = I2;
568 PM_POP(3, DCPLB_DATA15)
569 PM_POP(2, DCPLB_DATA14)
570 PM_POP(1, DCPLB_DATA13)
571 PM_POP(0, DCPLB_DATA12)
572 PM_POP_SYNC(13)
573 PM_POP(13, DCPLB_DATA11)
574 PM_POP(12, DCPLB_DATA10)
575 PM_POP(11, DCPLB_DATA9)
576 PM_POP(10, DCPLB_DATA8)
577 PM_POP(9, DCPLB_DATA7)
578 PM_POP(8, DCPLB_DATA6)
579 PM_POP(7, DCPLB_DATA5)
580 PM_POP(6, DCPLB_DATA4)
581 PM_POP(5, DCPLB_DATA3)
582 PM_POP(4, DCPLB_DATA2)
583 PM_POP(3, DCPLB_DATA1)
584 PM_POP(2, DCPLB_DATA0)
585
586 /* DCPLB Addr */
587 FP = I1;
588 PM_POP(1, DCPLB_ADDR15)
589 PM_POP(0, DCPLB_ADDR14)
590 PM_POP_SYNC(13)
591 PM_POP(13, DCPLB_ADDR13)
592 PM_POP(12, DCPLB_ADDR12)
593 PM_POP(11, DCPLB_ADDR11)
594 PM_POP(10, DCPLB_ADDR10)
595 PM_POP(9, DCPLB_ADDR9)
596 PM_POP(8, DCPLB_ADDR8)
597 PM_POP(7, DCPLB_ADDR7)
598 PM_POP(6, DCPLB_ADDR6)
599 PM_POP(5, DCPLB_ADDR5)
600 PM_POP(4, DCPLB_ADDR4)
601 PM_POP(3, DCPLB_ADDR3)
602 PM_POP(2, DCPLB_ADDR2)
603 PM_POP(1, DCPLB_ADDR1)
604 PM_POP(0, DCPLB_ADDR0)
605
606
607 /* Misc non-contiguous registers */
608
609 /* icache & dcache will enable later
610 drop IMEM_CONTROL, DMEM_CONTROL pop
611 */
612 FP = I0;
613 PM_POP_SYNC(2)
614 PM_CORE_POP(2, TBUFCTL)
615 PM_CORE_POP(1, IMEM_CONTROL)
616 PM_CORE_POP(0, DMEM_CONTROL)
617
618 /* Core Timer */
619 FP = B3;
620 R0 = 0x1;
621 [FP - 0xC] = R0;
622
623 PM_POP_SYNC(13)
624 FP = B3;
625 PM_POP(13, TCOUNT)
626 PM_POP(12, TSCALE)
627 PM_POP(11, TPERIOD)
628 PM_POP(10, TCNTL)
629
630 /* CEC */
631 FP = B2;
632 PM_POP(9, IPRIO)
633 PM_POP(8, ILAT)
634 FP += -4; /* IPEND */
635 PM_POP(7, IMASK)
636
637 /* Event Vectors */
638 FP = B1;
639 PM_POP(6, EVT15)
640 PM_POP(5, EVT14)
641 PM_POP(4, EVT13)
642 PM_POP(3, EVT12)
643 PM_POP(2, EVT11)
644 PM_POP(1, EVT10)
645 PM_POP(0, EVT9)
646 PM_POP_SYNC(5)
647 PM_POP(5, EVT8)
648 PM_POP(4, EVT7)
649 PM_POP(3, EVT6)
650 PM_POP(2, EVT5)
651 FP += -4; /* EVT4 */
652 PM_POP(1, EVT3)
653 PM_POP(0, EVT2)
654 .endm
655#endif
656
12#include <mach/pll.h> 657#include <mach/pll.h>
13 658
14/* PLL_CTL Masks */ 659/* PLL_CTL Masks */
@@ -98,6 +743,16 @@
98#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 743#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
99#endif 744#endif
100 745
746#ifdef CONFIG_BF60x
747#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */
748#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */
749#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */
750#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
751#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
752#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
753#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */
754#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */
755#else
101#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 756#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
102#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ 757#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
103#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ 758#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
@@ -113,6 +768,7 @@
113#else 768#else
114#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ 769#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
115#endif 770#endif
771#endif
116 772
117#ifndef __ASSEMBLY__ 773#ifndef __ASSEMBLY__
118 774
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
index 73fe53e7fd24..5395088b2d0e 100644
--- a/arch/blackfin/include/asm/fixed_code.h
+++ b/arch/blackfin/include/asm/fixed_code.h
@@ -29,24 +29,28 @@ extern void sigreturn_stub(void);
29#endif 29#endif
30#endif 30#endif
31 31
32#define FIXED_CODE_START 0x400 32#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
33#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
34#endif
35
36#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
33 37
34#define SIGRETURN_STUB 0x400 38#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
35 39
36#define ATOMIC_SEQS_START 0x410 40#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
37 41
38#define ATOMIC_XCHG32 0x410 42#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
39#define ATOMIC_CAS32 0x420 43#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
40#define ATOMIC_ADD32 0x430 44#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
41#define ATOMIC_SUB32 0x440 45#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
42#define ATOMIC_IOR32 0x450 46#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
43#define ATOMIC_AND32 0x460 47#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
44#define ATOMIC_XOR32 0x470 48#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
45 49
46#define ATOMIC_SEQS_END 0x480 50#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
47 51
48#define SAFE_USER_INSTRUCTION 0x480 52#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
49 53
50#define FIXED_CODE_END 0x490 54#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
51 55
52#endif 56#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 12d3571b5232..3d84d96f7c2c 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -26,6 +26,7 @@
26#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
27 27
28#include <linux/compiler.h> 28#include <linux/compiler.h>
29#include <linux/gpio.h>
29 30
30/*********************************************************** 31/***********************************************************
31* 32*
@@ -244,6 +245,49 @@ static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
244 return -EINVAL; 245 return -EINVAL;
245} 246}
246 247
248static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
249{
250 int err;
251
252 err = bfin_gpio_request(gpio, label);
253 if (err)
254 return err;
255
256 if (flags & GPIOF_DIR_IN)
257 err = bfin_gpio_direction_input(gpio);
258 else
259 err = bfin_gpio_direction_output(gpio,
260 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
261
262 if (err)
263 bfin_gpio_free(gpio);
264
265 return err;
266}
267
268static inline int gpio_request_array(const struct gpio *array, size_t num)
269{
270 int i, err;
271
272 for (i = 0; i < num; i++, array++) {
273 err = gpio_request_one(array->gpio, array->flags, array->label);
274 if (err)
275 goto err_free;
276 }
277 return 0;
278
279err_free:
280 while (i--)
281 bfin_gpio_free((--array)->gpio);
282 return err;
283}
284
285static inline void gpio_free_array(const struct gpio *array, size_t num)
286{
287 while (num--)
288 bfin_gpio_free((array++)->gpio);
289}
290
247static inline int __gpio_get_value(unsigned gpio) 291static inline int __gpio_get_value(unsigned gpio)
248{ 292{
249 return bfin_gpio_get_value(gpio); 293 return bfin_gpio_get_value(gpio);
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 38bddcb190c8..381e3d621a4c 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -44,6 +44,13 @@
44# define TIMER_GROUP2 1 44# define TIMER_GROUP2 1
45#endif 45#endif
46/* 46/*
47 * BF609: 8 timers:
48 */
49#if defined(CONFIG_BF60x)
50# define MAX_BLACKFIN_GPTIMERS 8
51# define TIMER0_GROUP_REG TIMER_RUN
52#endif
53/*
47 * All others: 3 timers: 54 * All others: 3 timers:
48 */ 55 */
49#define TIMER_GROUP1 0 56#define TIMER_GROUP1 0
@@ -104,6 +111,72 @@
104# define FS2_TIMER_BIT TIMER1bit 111# define FS2_TIMER_BIT TIMER1bit
105#endif 112#endif
106 113
114#ifdef CONFIG_BF60x
115/*
116 * Timer Configuration Register Bits
117 */
118#define TIMER_EMU_RUN 0x8000
119#define TIMER_BPER_EN 0x4000
120#define TIMER_BWID_EN 0x2000
121#define TIMER_BDLY_EN 0x1000
122#define TIMER_OUT_DIS 0x0800
123#define TIMER_TIN_SEL 0x0400
124#define TIMER_CLK_SEL 0x0300
125#define TIMER_CLK_SCLK 0x0000
126#define TIMER_CLK_ALT_CLK0 0x0100
127#define TIMER_CLK_ALT_CLK1 0x0300
128#define TIMER_PULSE_HI 0x0080
129#define TIMER_SLAVE_TRIG 0x0040
130#define TIMER_IRQ_MODE 0x0030
131#define TIMER_IRQ_ACT_EDGE 0x0000
132#define TIMER_IRQ_DLY 0x0010
133#define TIMER_IRQ_WID_DLY 0x0020
134#define TIMER_IRQ_PER 0x0030
135#define TIMER_MODE 0x000f
136#define TIMER_MODE_WDOG_P 0x0008
137#define TIMER_MODE_WDOG_W 0x0009
138#define TIMER_MODE_PWM_CONT 0x000c
139#define TIMER_MODE_PWM 0x000d
140#define TIMER_MODE_WDTH 0x000a
141#define TIMER_MODE_WDTH_D 0x000b
142#define TIMER_MODE_EXT_CLK 0x000e
143#define TIMER_MODE_PININT 0x000f
144
145/*
146 * Timer Status Register Bits
147 */
148#define TIMER_STATUS_TIMIL0 0x0001
149#define TIMER_STATUS_TIMIL1 0x0002
150#define TIMER_STATUS_TIMIL2 0x0004
151#define TIMER_STATUS_TIMIL3 0x0008
152#define TIMER_STATUS_TIMIL4 0x0010
153#define TIMER_STATUS_TIMIL5 0x0020
154#define TIMER_STATUS_TIMIL6 0x0040
155#define TIMER_STATUS_TIMIL7 0x0080
156
157#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
158#define TIMER_STATUS_TOVF1 0x0002
159#define TIMER_STATUS_TOVF2 0x0004
160#define TIMER_STATUS_TOVF3 0x0008
161#define TIMER_STATUS_TOVF4 0x0010
162#define TIMER_STATUS_TOVF5 0x0020
163#define TIMER_STATUS_TOVF6 0x0040
164#define TIMER_STATUS_TOVF7 0x0080
165
166/*
167 * Timer Slave Enable Status : write 1 to clear
168 */
169#define TIMER_STATUS_TRUN0 0x0001
170#define TIMER_STATUS_TRUN1 0x0002
171#define TIMER_STATUS_TRUN2 0x0004
172#define TIMER_STATUS_TRUN3 0x0008
173#define TIMER_STATUS_TRUN4 0x0010
174#define TIMER_STATUS_TRUN5 0x0020
175#define TIMER_STATUS_TRUN6 0x0040
176#define TIMER_STATUS_TRUN7 0x0080
177
178#else
179
107/* 180/*
108 * Timer Configuration Register Bits 181 * Timer Configuration Register Bits
109 */ 182 */
@@ -170,12 +243,18 @@
170#define TIMER_STATUS_TRUN10 0x4000 243#define TIMER_STATUS_TRUN10 0x4000
171#define TIMER_STATUS_TRUN11 0x8000 244#define TIMER_STATUS_TRUN11 0x8000
172 245
246#endif
247
173/* The actual gptimer API */ 248/* The actual gptimer API */
174 249
175void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); 250void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
176uint32_t get_gptimer_pwidth(unsigned int timer_id); 251uint32_t get_gptimer_pwidth(unsigned int timer_id);
177void set_gptimer_period(unsigned int timer_id, uint32_t period); 252void set_gptimer_period(unsigned int timer_id, uint32_t period);
178uint32_t get_gptimer_period(unsigned int timer_id); 253uint32_t get_gptimer_period(unsigned int timer_id);
254#ifdef CONFIG_BF60x
255void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
256uint32_t get_gptimer_delay(unsigned int timer_id);
257#endif
179uint32_t get_gptimer_count(unsigned int timer_id); 258uint32_t get_gptimer_count(unsigned int timer_id);
180int get_gptimer_intr(unsigned int timer_id); 259int get_gptimer_intr(unsigned int timer_id);
181void clear_gptimer_intr(unsigned int timer_id); 260void clear_gptimer_intr(unsigned int timer_id);
@@ -217,16 +296,41 @@ struct bfin_gptimer_regs {
217 u32 counter; 296 u32 counter;
218 u32 period; 297 u32 period;
219 u32 width; 298 u32 width;
299#ifdef CONFIG_BF60x
300 u32 delay;
301#endif
220}; 302};
221 303
222/* 304/*
223 * bfin group timer registers layout 305 * bfin group timer registers layout
224 */ 306 */
307#ifndef CONFIG_BF60x
225struct bfin_gptimer_group_regs { 308struct bfin_gptimer_group_regs {
226 __BFP(enable); 309 __BFP(enable);
227 __BFP(disable); 310 __BFP(disable);
228 u32 status; 311 u32 status;
229}; 312};
313#else
314struct bfin_gptimer_group_regs {
315 __BFP(run);
316 __BFP(enable);
317 __BFP(disable);
318 __BFP(stop_cfg);
319 __BFP(stop_cfg_set);
320 __BFP(stop_cfg_clr);
321 __BFP(data_imsk);
322 __BFP(stat_imsk);
323 __BFP(tr_msk);
324 __BFP(tr_ie);
325 __BFP(data_ilat);
326 __BFP(stat_ilat);
327 __BFP(err_status);
328 __BFP(bcast_per);
329 __BFP(bcast_wid);
330 __BFP(bcast_dly);
331
332};
333#endif
230 334
231#undef __BFP 335#undef __BFP
232 336
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 43eb4749de3d..07aff230a812 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -67,7 +67,11 @@ static inline notrace unsigned long __hard_local_irq_save(void)
67 67
68static inline notrace int hard_irqs_disabled_flags(unsigned long flags) 68static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
69{ 69{
70#ifdef CONFIG_BF60x
71 return (flags & IMASK_IVG11) == 0;
72#else
70 return (flags & ~0x3f) == 0; 73 return (flags & ~0x3f) == 0;
74#endif
71} 75}
72 76
73static inline notrace int hard_irqs_disabled(void) 77static inline notrace int hard_irqs_disabled(void)
@@ -224,7 +228,7 @@ static inline notrace void hard_local_irq_restore(unsigned long flags)
224 * Direct interface to linux/irqflags.h. 228 * Direct interface to linux/irqflags.h.
225 */ 229 */
226#define arch_local_save_flags() hard_local_save_flags() 230#define arch_local_save_flags() hard_local_save_flags()
227#define arch_local_irq_save(flags) __hard_local_irq_save() 231#define arch_local_irq_save() __hard_local_irq_save()
228#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags) 232#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
229#define arch_local_irq_enable() __hard_local_irq_enable() 233#define arch_local_irq_enable() __hard_local_irq_enable()
230#define arch_local_irq_disable() __hard_local_irq_disable() 234#define arch_local_irq_disable() __hard_local_irq_disable()
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index 7202404966f6..b93474d5be75 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -7,14 +7,15 @@
7#ifndef _BLACKFIN_PAGE_H 7#ifndef _BLACKFIN_PAGE_H
8#define _BLACKFIN_PAGE_H 8#define _BLACKFIN_PAGE_H
9 9
10#include <asm-generic/page.h> 10#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
11#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) 11#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
12 12
13#define VM_DATA_DEFAULT_FLAGS \ 13#define VM_DATA_DEFAULT_FLAGS \
14 (VM_READ | VM_WRITE | \ 14 (VM_READ | VM_WRITE | \
15 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ 15 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
16 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 16 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
17 17
18#include <asm-generic/page.h>
18#include <asm-generic/memory_model.h> 19#include <asm-generic/memory_model.h>
19#include <asm-generic/getorder.h> 20#include <asm-generic/getorder.h>
20 21
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
index 28c2498c9c98..68d6f6618f2a 100644
--- a/arch/blackfin/include/asm/pda.h
+++ b/arch/blackfin/include/asm/pda.h
@@ -13,7 +13,9 @@
13#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
14 14
15struct blackfin_pda { /* Per-processor Data Area */ 15struct blackfin_pda { /* Per-processor Data Area */
16#ifdef CONFIG_SMP
16 struct blackfin_pda *next; 17 struct blackfin_pda *next;
18#endif
17 19
18 unsigned long syscfg; 20 unsigned long syscfg;
19#ifdef CONFIG_SMP 21#ifdef CONFIG_SMP
diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h
new file mode 100644
index 000000000000..f72239bf3638
--- /dev/null
+++ b/arch/blackfin/include/asm/pm.h
@@ -0,0 +1,31 @@
1/*
2 * Blackfin bf609 power management
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2
7 */
8
9#ifndef __PM_H__
10#define __PM_H__
11
12#include <linux/suspend.h>
13
14struct bfin_cpu_pm_fns {
15 void (*save)(unsigned long *);
16 void (*restore)(unsigned long *);
17 int (*valid)(suspend_state_t state);
18 void (*enter)(suspend_state_t state);
19 int (*prepare)(void);
20 void (*finish)(void);
21};
22
23extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
24
25# ifdef CONFIG_BFIN_COREB
26void bfin_coreb_start(void);
27void bfin_coreb_stop(void);
28void bfin_coreb_reset(void);
29# endif
30
31#endif
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 75ec9df5318b..3287222cba34 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -11,7 +11,7 @@
11 */ 11 */
12#define __NR_restart_syscall 0 12#define __NR_restart_syscall 0
13#define __NR_exit 1 13#define __NR_exit 1
14#define __NR_fork 2 14 /* 2 __NR_fork not supported on nommu */
15#define __NR_read 3 15#define __NR_read 3
16#define __NR_write 4 16#define __NR_write 4
17#define __NR_open 5 17#define __NR_open 5
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