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-rw-r--r--arch/blackfin/include/asm/context.S39
-rw-r--r--arch/blackfin/include/asm/cplb-mpu.h62
-rw-r--r--arch/blackfin/include/asm/cplb.h4
-rw-r--r--arch/blackfin/include/asm/cplbinit.h108
-rw-r--r--arch/blackfin/include/asm/entry.h2
5 files changed, 79 insertions, 136 deletions
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
index 9ce21f68e914..16561ab18b38 100644
--- a/arch/blackfin/include/asm/context.S
+++ b/arch/blackfin/include/asm/context.S
@@ -357,3 +357,42 @@
357 SYSCFG = [sp++]; 357 SYSCFG = [sp++];
358 csync; 358 csync;
359.endm 359.endm
360
361.macro save_context_cplb
362 [--sp] = (R7:0, P5:0);
363 [--sp] = fp;
364
365 [--sp] = a0.x;
366 [--sp] = a0.w;
367 [--sp] = a1.x;
368 [--sp] = a1.w;
369
370 [--sp] = LC0;
371 [--sp] = LC1;
372 [--sp] = LT0;
373 [--sp] = LT1;
374 [--sp] = LB0;
375 [--sp] = LB1;
376
377 [--sp] = RETS;
378.endm
379
380.macro restore_context_cplb
381 RETS = [sp++];
382
383 LB1 = [sp++];
384 LB0 = [sp++];
385 LT1 = [sp++];
386 LT0 = [sp++];
387 LC1 = [sp++];
388 LC0 = [sp++];
389
390 a1.w = [sp++];
391 a1.x = [sp++];
392 a0.w = [sp++];
393 a0.x = [sp++];
394
395 fp = [sp++];
396
397 (R7:0, P5:0) = [SP++];
398.endm
diff --git a/arch/blackfin/include/asm/cplb-mpu.h b/arch/blackfin/include/asm/cplb-mpu.h
deleted file mode 100644
index 80680ad7a378..000000000000
--- a/arch/blackfin/include/asm/cplb-mpu.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#ifndef __ASM_BFIN_CPLB_MPU_H
30#define __ASM_BFIN_CPLB_MPU_H
31#include <linux/threads.h>
32
33struct cplb_entry {
34 unsigned long data, addr;
35};
36
37struct mem_region {
38 unsigned long start, end;
39 unsigned long dcplb_data;
40 unsigned long icplb_data;
41};
42
43extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
44extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
45extern int first_switched_icplb;
46extern int first_mask_dcplb;
47extern int first_switched_dcplb;
48
49extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
50extern int nr_dcplb_prot[], nr_cplb_flush[];
51
52extern int page_mask_order;
53extern int page_mask_nelts;
54
55extern unsigned long *current_rwx_mask[NR_CPUS];
56
57extern void flush_switched_cplbs(unsigned int);
58extern void set_mask_dcplbs(unsigned long *, unsigned int);
59
60extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
61
62#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index 5f7545d06200..ad566ff9ad16 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -116,4 +116,8 @@
116#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID 116#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
117#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL 117#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
118 118
119#define FAULT_RW (1 << 16)
120#define FAULT_USERSUPV (1 << 17)
121#define FAULT_CPLBBITS 0x0000ffff
122
119#endif /* _CPLB_H */ 123#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
index 2aeec87d24e1..05b14a631d0c 100644
--- a/arch/blackfin/include/asm/cplbinit.h
+++ b/arch/blackfin/include/asm/cplbinit.h
@@ -32,96 +32,56 @@
32 32
33#include <asm/blackfin.h> 33#include <asm/blackfin.h>
34#include <asm/cplb.h> 34#include <asm/cplb.h>
35#include <linux/threads.h>
35 36
36#ifdef CONFIG_MPU 37#ifdef CONFIG_CPLB_SWITCH_TAB_L1
37 38# define PDT_ATTR __attribute__((l1_data))
38#include <asm/cplb-mpu.h>
39extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
40extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
41
42#else 39#else
40# define PDT_ATTR
41#endif
43 42
44#define INITIAL_T 0x1 43struct cplb_entry {
45#define SWITCH_T 0x2 44 unsigned long data, addr;
46#define I_CPLB 0x4 45};
47#define D_CPLB 0x8
48 46
49#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ 47struct cplb_boundary {
50 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) 48 unsigned long eaddr; /* End of this region. */
49 unsigned long data; /* CPLB data value. */
50};
51 51
52#define CPLB_MEM CONFIG_MAX_MEM_SIZE 52extern struct cplb_boundary dcplb_bounds[];
53extern struct cplb_boundary icplb_bounds[];
54extern int dcplb_nr_bounds, icplb_nr_bounds;
53 55
54/* 56extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
55* Number of required data CPLB switchtable entries 57extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
56* MEMSIZE / 4 (we mostly install 4M page size CPLBs 58extern int first_switched_icplb;
57* approx 16 for smaller 1MB page size CPLBs for allignment purposes 59extern int first_switched_dcplb;
58* 1 for L1 Data Memory
59* possibly 1 for L2 Data Memory
60* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
61* 1 for ASYNC Memory
62*/
63#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
64 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
65 60
66/* 61extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
67* Number of required instruction CPLB switchtable entries 62extern int nr_dcplb_prot[], nr_cplb_flush[];
68* MEMSIZE / 4 (we mostly install 4M page size CPLBs
69* approx 12 for smaller 1MB page size CPLBs for allignment purposes
70* 1 for L1 Instruction Memory
71* possibly 1 for L2 Instruction Memory
72* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
73*/
74#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
75
76/* Number of CPLB table entries, used for cplb-nompu. */
77#define CPLB_TBL_ENTRIES (16 * 4)
78
79enum {
80 ZERO_P, L1I_MEM, L1D_MEM, L2_MEM, SDRAM_KERN, SDRAM_RAM_MTD, SDRAM_DMAZ,
81 RES_MEM, ASYNC_MEM, OCB_ROM
82};
83 63
84struct cplb_desc { 64#ifdef CONFIG_MPU
85 u32 start; /* start address */
86 u32 end; /* end address */
87 u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
88 u16 attr;/* attributes */
89 u16 i_conf;/* I-CPLB DATA */
90 u16 d_conf;/* D-CPLB DATA */
91 u16 valid;/* valid */
92 const s8 name[30];/* name */
93};
94 65
95struct cplb_tab { 66extern int first_mask_dcplb;
96 u_long *tab;
97 u16 pos;
98 u16 size;
99};
100 67
101extern u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1]; 68extern int page_mask_order;
102extern u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1]; 69extern int page_mask_nelts;
103 70
104/* Till here we are discussing about the static memory management model. 71extern unsigned long *current_rwx_mask[NR_CPUS];
105 * However, the operating envoronments commonly define more CPLB
106 * descriptors to cover the entire addressable memory than will fit into
107 * the available on-chip 16 CPLB MMRs. When this happens, the below table
108 * will be used which will hold all the potentially required CPLB descriptors
109 *
110 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
111 */
112 72
113extern u_long ipdt_tables[NR_CPUS][MAX_SWITCH_I_CPLBS+1]; 73extern void flush_switched_cplbs(unsigned int);
114extern u_long dpdt_tables[NR_CPUS][MAX_SWITCH_D_CPLBS+1]; 74extern void set_mask_dcplbs(unsigned long *, unsigned int);
115#ifdef CONFIG_CPLB_INFO 75
116extern u_long ipdt_swapcount_tables[NR_CPUS][MAX_SWITCH_I_CPLBS]; 76extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
117extern u_long dpdt_swapcount_tables[NR_CPUS][MAX_SWITCH_D_CPLBS];
118#endif
119extern void bfin_icache_init(u_long icplbs[]);
120extern void bfin_dcache_init(u_long dcplbs[]);
121 77
122#endif /* CONFIG_MPU */ 78#endif /* CONFIG_MPU */
123 79
80extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
81extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
82
124#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) 83#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
84extern void generate_cplb_tables_all(void);
125extern void generate_cplb_tables_cpu(unsigned int cpu); 85extern void generate_cplb_tables_cpu(unsigned int cpu);
126#endif 86#endif
127#endif 87#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
index c4f721e0d00d..d94e4f5139d2 100644
--- a/arch/blackfin/include/asm/entry.h
+++ b/arch/blackfin/include/asm/entry.h
@@ -53,9 +53,11 @@
53/* This one pushes RETI without using CLI. Interrupts are enabled. */ 53/* This one pushes RETI without using CLI. Interrupts are enabled. */
54#define SAVE_CONTEXT_SYSCALL save_context_syscall 54#define SAVE_CONTEXT_SYSCALL save_context_syscall
55#define SAVE_CONTEXT save_context_with_interrupts 55#define SAVE_CONTEXT save_context_with_interrupts
56#define SAVE_CONTEXT_CPLB save_context_cplb
56 57
57#define RESTORE_ALL_SYS restore_context_no_interrupts 58#define RESTORE_ALL_SYS restore_context_no_interrupts
58#define RESTORE_CONTEXT restore_context_with_interrupts 59#define RESTORE_CONTEXT restore_context_with_interrupts
60#define RESTORE_CONTEXT_CPLB restore_context_cplb
59 61
60#endif /* __ASSEMBLY__ */ 62#endif /* __ASSEMBLY__ */
61#endif /* __BFIN_ENTRY_H */ 63#endif /* __BFIN_ENTRY_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 19:50:09 -0500