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Diffstat (limited to 'arch/blackfin/include/asm/ipipe.h')
-rw-r--r--arch/blackfin/include/asm/ipipe.h26
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 343b56361ec9..bbe1c3726b69 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37 37
38#define IPIPE_ARCH_STRING "1.9-00" 38#define IPIPE_ARCH_STRING "1.10-00"
39#define IPIPE_MAJOR_NUMBER 1 39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 9 40#define IPIPE_MINOR_NUMBER 10
41#define IPIPE_PATCH_NUMBER 0 41#define IPIPE_PATCH_NUMBER 0
42 42
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -54,10 +54,11 @@ do { \
54 54
55#define task_hijacked(p) \ 55#define task_hijacked(p) \
56 ({ \ 56 ({ \
57 int __x__ = ipipe_current_domain != ipipe_root_domain; \ 57 int __x__ = __ipipe_root_domain_p; \
58 /* We would need to clear the SYNC flag for the root domain */ \ 58 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
59 /* over the current processor in SMP mode. */ \ 59 if (__x__) \
60 local_irq_enable_hw(); __x__; \ 60 local_irq_enable_hw(); \
61 !__x__; \
61 }) 62 })
62 63
63struct ipipe_domain; 64struct ipipe_domain;
@@ -179,23 +180,24 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
179 180
180#define __ipipe_run_isr(ipd, irq) \ 181#define __ipipe_run_isr(ipd, irq) \
181 do { \ 182 do { \
182 if (ipd == ipipe_root_domain) { \ 183 if (!__ipipe_pipeline_head_p(ipd)) \
183 local_irq_enable_hw(); \ 184 local_irq_enable_hw(); \
184 if (ipipe_virtual_irq_p(irq)) \ 185 if (ipd == ipipe_root_domain) { \
186 if (unlikely(ipipe_virtual_irq_p(irq))) { \
187 irq_enter(); \
185 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ 188 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
186 else \ 189 irq_exit(); \
190 } else \
187 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ 191 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
188 local_irq_disable_hw(); \
189 } else { \ 192 } else { \
190 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 193 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
191 local_irq_enable_nohead(ipd); \
192 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ 194 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
193 /* Attempt to exit the outer interrupt level before \ 195 /* Attempt to exit the outer interrupt level before \
194 * starting the deferred IRQ processing. */ \ 196 * starting the deferred IRQ processing. */ \
195 local_irq_disable_nohead(ipd); \
196 __ipipe_run_irqtail(); \ 197 __ipipe_run_irqtail(); \
197 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 198 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
198 } \ 199 } \
200 local_irq_disable_hw(); \
199 } while (0) 201 } while (0)
200 202
201#define __ipipe_syscall_watched_p(p, sc) \ 203#define __ipipe_syscall_watched_p(p, sc) \