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-rw-r--r--arch/blackfin/include/asm/ipipe.h278
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1/* -*- linux-c -*-
2 * include/asm-blackfin/ipipe.h
3 *
4 * Copyright (C) 2002-2007 Philippe Gerum.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
9 * USA; either version 2 of the License, or (at your option) any later
10 * version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __ASM_BLACKFIN_IPIPE_H
23#define __ASM_BLACKFIN_IPIPE_H
24
25#ifdef CONFIG_IPIPE
26
27#include <linux/cpumask.h>
28#include <linux/list.h>
29#include <linux/threads.h>
30#include <linux/irq.h>
31#include <linux/ipipe_percpu.h>
32#include <asm/ptrace.h>
33#include <asm/irq.h>
34#include <asm/bitops.h>
35#include <asm/atomic.h>
36#include <asm/traps.h>
37
38#define IPIPE_ARCH_STRING "1.8-00"
39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 8
41#define IPIPE_PATCH_NUMBER 0
42
43#ifdef CONFIG_SMP
44#error "I-pipe/blackfin: SMP not implemented"
45#else /* !CONFIG_SMP */
46#define ipipe_processor_id() 0
47#endif /* CONFIG_SMP */
48
49#define prepare_arch_switch(next) \
50do { \
51 ipipe_schedule_notify(current, next); \
52 local_irq_disable_hw(); \
53} while (0)
54
55#define task_hijacked(p) \
56 ({ \
57 int __x__ = ipipe_current_domain != ipipe_root_domain; \
58 /* We would need to clear the SYNC flag for the root domain */ \
59 /* over the current processor in SMP mode. */ \
60 local_irq_enable_hw(); __x__; \
61 })
62
63struct ipipe_domain;
64
65struct ipipe_sysinfo {
66
67 int ncpus; /* Number of CPUs on board */
68 u64 cpufreq; /* CPU frequency (in Hz) */
69
70 /* Arch-dependent block */
71
72 struct {
73 unsigned tmirq; /* Timer tick IRQ */
74 u64 tmfreq; /* Timer frequency */
75 } archdep;
76};
77
78#define ipipe_read_tsc(t) \
79 ({ \
80 unsigned long __cy2; \
81 __asm__ __volatile__ ("1: %0 = CYCLES2\n" \
82 "%1 = CYCLES\n" \
83 "%2 = CYCLES2\n" \
84 "CC = %2 == %0\n" \
85 "if ! CC jump 1b\n" \
86 : "=r" (((unsigned long *)&t)[1]), \
87 "=r" (((unsigned long *)&t)[0]), \
88 "=r" (__cy2) \
89 : /*no input*/ : "CC"); \
90 t; \
91 })
92
93#define ipipe_cpu_freq() __ipipe_core_clock
94#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
95#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
96
97/* Private interface -- Internal use only */
98
99#define __ipipe_check_platform() do { } while (0)
100
101#define __ipipe_init_platform() do { } while (0)
102
103extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
104
105extern unsigned long __ipipe_irq_lvmask;
106
107extern struct ipipe_domain ipipe_root;
108
109/* enable/disable_irqdesc _must_ be used in pairs. */
110
111void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
112 unsigned irq);
113
114void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
115 unsigned irq);
116
117#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq))
118
119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
120
121#define __ipipe_lock_root() \
122 set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
123
124#define __ipipe_unlock_root() \
125 clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
126
127void __ipipe_enable_pipeline(void);
128
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130
131#define __ipipe_sync_pipeline(syncmask) \
132 do { \
133 struct ipipe_domain *ipd = ipipe_current_domain; \
134 if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
135 __ipipe_sync_stage(syncmask); \
136 } while (0)
137
138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
139
140int __ipipe_get_irq_priority(unsigned irq);
141
142int __ipipe_get_irqthread_priority(unsigned irq);
143
144void __ipipe_stall_root_raw(void);
145
146void __ipipe_unstall_root_raw(void);
147
148void __ipipe_serial_debug(const char *fmt, ...);
149
150DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
151
152extern unsigned long __ipipe_core_clock;
153
154extern unsigned long __ipipe_freq_scale;
155
156extern unsigned long __ipipe_irq_tail_hook;
157
158static inline unsigned long __ipipe_ffnz(unsigned long ul)
159{
160 return ffs(ul) - 1;
161}
162
163#define __ipipe_run_irqtail() /* Must be a macro */ \
164 do { \
165 asmlinkage void __ipipe_call_irqtail(void); \
166 unsigned long __pending; \
167 CSYNC(); \
168 __pending = bfin_read_IPEND(); \
169 if (__pending & 0x8000) { \
170 __pending &= ~0x8010; \
171 if (__pending && (__pending & (__pending - 1)) == 0) \
172 __ipipe_call_irqtail(); \
173 } \
174 } while (0)
175
176#define __ipipe_run_isr(ipd, irq) \
177 do { \
178 if (ipd == ipipe_root_domain) { \
179 /* \
180 * Note: the I-pipe implements a threaded interrupt model on \
181 * this arch for Linux external IRQs. The interrupt handler we \
182 * call here only wakes up the associated IRQ thread. \
183 */ \
184 if (ipipe_virtual_irq_p(irq)) { \
185 /* No irqtail here; virtual interrupts have no effect \
186 on IPEND so there is no need for processing \
187 deferral. */ \
188 local_irq_enable_nohead(ipd); \
189 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
190 local_irq_disable_nohead(ipd); \
191 } else \
192 /* \
193 * No need to run the irqtail here either; \
194 * we can't be preempted by hw IRQs, so \
195 * non-Linux IRQs cannot stack over the short \
196 * thread wakeup code. Which in turn means \
197 * that no irqtail condition could be pending \
198 * for domains above Linux in the pipeline. \
199 */ \
200 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
201 } else { \
202 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
203 local_irq_enable_nohead(ipd); \
204 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
205 /* Attempt to exit the outer interrupt level before \
206 * starting the deferred IRQ processing. */ \
207 local_irq_disable_nohead(ipd); \
208 __ipipe_run_irqtail(); \
209 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
210 } \
211 } while (0)
212
213#define __ipipe_syscall_watched_p(p, sc) \
214 (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls)
215
216void ipipe_init_irq_threads(void);
217
218int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219
220#define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS)
221#define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS)
222
223#define IRQ_SYSTMR IRQ_TIMER0
224#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
225
226#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533)
227#define PRIO_GPIODEMUX(irq) CONFIG_PFA
228#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
229#define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA
230#elif defined(CONFIG_BF52x)
231#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
232 (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
233 (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
234 -1)
235#elif defined(CONFIG_BF561)
236#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
237 (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
238 (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
239 -1)
240#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
241#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
242#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
243#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
244#elif defined(CONFIG_BF54x)
245#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
246 (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
247 (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
248 (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
249 -1)
250#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
251#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
252#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
253#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
254#else
255# error "no PRIO_GPIODEMUX() for this part"
256#endif
257
258#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
259
260#else /* !CONFIG_IPIPE */
261
262#define task_hijacked(p) 0
263#define ipipe_trap_notify(t, r) 0
264
265#define __ipipe_stall_root_raw() do { } while (0)
266#define __ipipe_unstall_root_raw() do { } while (0)
267
268#define ipipe_init_irq_threads() do { } while (0)
269#define ipipe_start_irq_thread(irq, desc) 0
270
271#define IRQ_SYSTMR IRQ_CORETMR
272#define IRQ_PRIOTMR IRQ_CORETMR
273
274#define __ipipe_root_tick_p(regs) 1
275
276#endif /* !CONFIG_IPIPE */
277
278#endif /* !__ASM_BLACKFIN_IPIPE_H */
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