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-rw-r--r--arch/blackfin/include/asm/cplbinit.h108
1 files changed, 34 insertions, 74 deletions
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
index 2aeec87d24e1..05b14a631d0c 100644
--- a/arch/blackfin/include/asm/cplbinit.h
+++ b/arch/blackfin/include/asm/cplbinit.h
@@ -32,96 +32,56 @@
32 32
33#include <asm/blackfin.h> 33#include <asm/blackfin.h>
34#include <asm/cplb.h> 34#include <asm/cplb.h>
35#include <linux/threads.h>
35 36
36#ifdef CONFIG_MPU 37#ifdef CONFIG_CPLB_SWITCH_TAB_L1
37 38# define PDT_ATTR __attribute__((l1_data))
38#include <asm/cplb-mpu.h>
39extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
40extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
41
42#else 39#else
40# define PDT_ATTR
41#endif
43 42
44#define INITIAL_T 0x1 43struct cplb_entry {
45#define SWITCH_T 0x2 44 unsigned long data, addr;
46#define I_CPLB 0x4 45};
47#define D_CPLB 0x8
48 46
49#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ 47struct cplb_boundary {
50 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) 48 unsigned long eaddr; /* End of this region. */
49 unsigned long data; /* CPLB data value. */
50};
51 51
52#define CPLB_MEM CONFIG_MAX_MEM_SIZE 52extern struct cplb_boundary dcplb_bounds[];
53extern struct cplb_boundary icplb_bounds[];
54extern int dcplb_nr_bounds, icplb_nr_bounds;
53 55
54/* 56extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
55* Number of required data CPLB switchtable entries 57extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
56* MEMSIZE / 4 (we mostly install 4M page size CPLBs 58extern int first_switched_icplb;
57* approx 16 for smaller 1MB page size CPLBs for allignment purposes 59extern int first_switched_dcplb;
58* 1 for L1 Data Memory
59* possibly 1 for L2 Data Memory
60* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
61* 1 for ASYNC Memory
62*/
63#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
64 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
65 60
66/* 61extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
67* Number of required instruction CPLB switchtable entries 62extern int nr_dcplb_prot[], nr_cplb_flush[];
68* MEMSIZE / 4 (we mostly install 4M page size CPLBs
69* approx 12 for smaller 1MB page size CPLBs for allignment purposes
70* 1 for L1 Instruction Memory
71* possibly 1 for L2 Instruction Memory
72* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
73*/
74#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
75
76/* Number of CPLB table entries, used for cplb-nompu. */
77#define CPLB_TBL_ENTRIES (16 * 4)
78
79enum {
80 ZERO_P, L1I_MEM, L1D_MEM, L2_MEM, SDRAM_KERN, SDRAM_RAM_MTD, SDRAM_DMAZ,
81 RES_MEM, ASYNC_MEM, OCB_ROM
82};
83 63
84struct cplb_desc { 64#ifdef CONFIG_MPU
85 u32 start; /* start address */
86 u32 end; /* end address */
87 u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
88 u16 attr;/* attributes */
89 u16 i_conf;/* I-CPLB DATA */
90 u16 d_conf;/* D-CPLB DATA */
91 u16 valid;/* valid */
92 const s8 name[30];/* name */
93};
94 65
95struct cplb_tab { 66extern int first_mask_dcplb;
96 u_long *tab;
97 u16 pos;
98 u16 size;
99};
100 67
101extern u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1]; 68extern int page_mask_order;
102extern u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1]; 69extern int page_mask_nelts;
103 70
104/* Till here we are discussing about the static memory management model. 71extern unsigned long *current_rwx_mask[NR_CPUS];
105 * However, the operating envoronments commonly define more CPLB
106 * descriptors to cover the entire addressable memory than will fit into
107 * the available on-chip 16 CPLB MMRs. When this happens, the below table
108 * will be used which will hold all the potentially required CPLB descriptors
109 *
110 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
111 */
112 72
113extern u_long ipdt_tables[NR_CPUS][MAX_SWITCH_I_CPLBS+1]; 73extern void flush_switched_cplbs(unsigned int);
114extern u_long dpdt_tables[NR_CPUS][MAX_SWITCH_D_CPLBS+1]; 74extern void set_mask_dcplbs(unsigned long *, unsigned int);
115#ifdef CONFIG_CPLB_INFO 75
116extern u_long ipdt_swapcount_tables[NR_CPUS][MAX_SWITCH_I_CPLBS]; 76extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
117extern u_long dpdt_swapcount_tables[NR_CPUS][MAX_SWITCH_D_CPLBS];
118#endif
119extern void bfin_icache_init(u_long icplbs[]);
120extern void bfin_dcache_init(u_long dcplbs[]);
121 77
122#endif /* CONFIG_MPU */ 78#endif /* CONFIG_MPU */
123 79
80extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
81extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
82
124#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) 83#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
84extern void generate_cplb_tables_all(void);
125extern void generate_cplb_tables_cpu(unsigned int cpu); 85extern void generate_cplb_tables_cpu(unsigned int cpu);
126#endif 86#endif
127#endif 87#endif
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