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-rw-r--r--arch/blackfin/include/asm/cacheflush.h40
1 files changed, 21 insertions, 19 deletions
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 1b040f5b4feb..94697f0f6f40 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -30,7 +30,8 @@
30#ifndef _BLACKFIN_CACHEFLUSH_H 30#ifndef _BLACKFIN_CACHEFLUSH_H
31#define _BLACKFIN_CACHEFLUSH_H 31#define _BLACKFIN_CACHEFLUSH_H
32 32
33extern void blackfin_icache_dcache_flush_range(unsigned long start_address, unsigned long end_address); 33#include <asm/blackfin.h> /* for SSYNC() */
34
34extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); 35extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
35extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); 36extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
36extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); 37extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
@@ -54,32 +55,28 @@ extern void blackfin_invalidate_entire_dcache(void);
54 55
55static inline void flush_icache_range(unsigned start, unsigned end) 56static inline void flush_icache_range(unsigned start, unsigned end)
56{ 57{
57#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE) 58#if defined(CONFIG_BFIN_WB)
58 59 blackfin_dcache_flush_range(start, end);
59# if defined(CONFIG_BFIN_WT) 60#endif
60 blackfin_icache_flush_range((start), (end));
61 flush_icache_range_others(start, end);
62# else
63 blackfin_icache_dcache_flush_range((start), (end));
64# endif
65
66#else
67 61
68# if defined(CONFIG_BFIN_ICACHE) 62 /* Make sure all write buffers in the data side of the core
69 blackfin_icache_flush_range((start), (end)); 63 * are flushed before trying to invalidate the icache. This
64 * needs to be after the data flush and before the icache
65 * flush so that the SSYNC does the right thing in preventing
66 * the instruction prefetcher from hitting things in cached
67 * memory at the wrong time -- it runs much further ahead than
68 * the pipeline.
69 */
70 SSYNC();
71#if defined(CONFIG_BFIN_ICACHE)
72 blackfin_icache_flush_range(start, end);
70 flush_icache_range_others(start, end); 73 flush_icache_range_others(start, end);
71# endif
72# if defined(CONFIG_BFIN_DCACHE)
73 blackfin_dcache_flush_range((start), (end));
74# endif
75
76#endif 74#endif
77} 75}
78 76
79#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 77#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
80do { memcpy(dst, src, len); \ 78do { memcpy(dst, src, len); \
81 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ 79 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
82 flush_icache_range_others((unsigned long) (dst), (unsigned long) (dst) + (len));\
83} while (0) 80} while (0)
84 81
85#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) 82#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
@@ -111,6 +108,11 @@ static inline int bfin_addr_dcachable(unsigned long addr)
111 addr >= _ramend && addr < physical_mem_end) 108 addr >= _ramend && addr < physical_mem_end)
112 return 1; 109 return 1;
113 110
111#ifndef CONFIG_BFIN_L2_NOT_CACHED
112 if (addr >= L2_START && addr < L2_START + L2_LENGTH)
113 return 1;
114#endif
115
114 return 0; 116 return 0;
115} 117}
116 118