diff options
Diffstat (limited to 'arch/avr32/mach-at32ap/time-tc.c')
-rw-r--r-- | arch/avr32/mach-at32ap/time-tc.c | 217 |
1 files changed, 217 insertions, 0 deletions
diff --git a/arch/avr32/mach-at32ap/time-tc.c b/arch/avr32/mach-at32ap/time-tc.c new file mode 100644 index 000000000000..7ac0e94d8ed5 --- /dev/null +++ b/arch/avr32/mach-at32ap/time-tc.c | |||
@@ -0,0 +1,217 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2004-2007 Atmel Corporation | ||
3 | * | ||
4 | * Based on MIPS implementation arch/mips/kernel/time.c | ||
5 | * Copyright 2001 MontaVista Software Inc. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/clk.h> | ||
13 | #include <linux/clocksource.h> | ||
14 | #include <linux/time.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/irq.h> | ||
18 | #include <linux/kernel_stat.h> | ||
19 | #include <linux/errno.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/profile.h> | ||
22 | #include <linux/sysdev.h> | ||
23 | #include <linux/err.h> | ||
24 | |||
25 | #include <asm/div64.h> | ||
26 | #include <asm/sysreg.h> | ||
27 | #include <asm/io.h> | ||
28 | #include <asm/sections.h> | ||
29 | |||
30 | #include <asm/arch/time.h> | ||
31 | |||
32 | /* how many counter cycles in a jiffy? */ | ||
33 | static u32 cycles_per_jiffy; | ||
34 | |||
35 | /* the count value for the next timer interrupt */ | ||
36 | static u32 expirelo; | ||
37 | |||
38 | /* the I/O registers of the TC module */ | ||
39 | static void __iomem *ioregs; | ||
40 | |||
41 | cycle_t read_cycle_count(void) | ||
42 | { | ||
43 | return (cycle_t)timer_read(ioregs, 0, CV); | ||
44 | } | ||
45 | |||
46 | struct clocksource clocksource_avr32 = { | ||
47 | .name = "avr32", | ||
48 | .rating = 342, | ||
49 | .read = read_cycle_count, | ||
50 | .mask = CLOCKSOURCE_MASK(16), | ||
51 | .shift = 16, | ||
52 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
53 | }; | ||
54 | |||
55 | static void avr32_timer_ack(void) | ||
56 | { | ||
57 | u16 count = expirelo; | ||
58 | |||
59 | /* Ack this timer interrupt and set the next one, use a u16 | ||
60 | * variable so it will wrap around correctly */ | ||
61 | count += cycles_per_jiffy; | ||
62 | expirelo = count; | ||
63 | timer_write(ioregs, 0, RC, expirelo); | ||
64 | |||
65 | /* Check to see if we have missed any timer interrupts */ | ||
66 | count = timer_read(ioregs, 0, CV); | ||
67 | if ((count - expirelo) < 0x7fff) { | ||
68 | expirelo = count + cycles_per_jiffy; | ||
69 | timer_write(ioregs, 0, RC, expirelo); | ||
70 | } | ||
71 | } | ||
72 | |||
73 | u32 avr32_hpt_read(void) | ||
74 | { | ||
75 | return timer_read(ioregs, 0, CV); | ||
76 | } | ||
77 | |||
78 | static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk) | ||
79 | { | ||
80 | unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2; | ||
81 | unsigned int divs[] = { 4, 8, 16, 32 }; | ||
82 | int divs_size = sizeof(divs) / sizeof(*divs); | ||
83 | int i = 0; | ||
84 | unsigned long count_hz; | ||
85 | unsigned long shift; | ||
86 | unsigned long mult; | ||
87 | int clock_div = -1; | ||
88 | u64 tmp; | ||
89 | |||
90 | shift = clocksource_avr32.shift; | ||
91 | |||
92 | do { | ||
93 | count_hz = clk_get_rate(pclk) / divs[i]; | ||
94 | mult = clocksource_hz2mult(count_hz, shift); | ||
95 | clocksource_avr32.mult = mult; | ||
96 | |||
97 | tmp = TICK_NSEC; | ||
98 | tmp <<= shift; | ||
99 | tmp += mult / 2; | ||
100 | do_div(tmp, mult); | ||
101 | |||
102 | cycles_per_jiffy = tmp; | ||
103 | } while (cycles_per_jiffy > cycles_max && ++i < divs_size); | ||
104 | |||
105 | clock_div = i + 1; | ||
106 | |||
107 | if (clock_div > divs_size) { | ||
108 | pr_debug("timer: could not calculate clock divider\n"); | ||
109 | return -EFAULT; | ||
110 | } | ||
111 | |||
112 | /* Set the clock divider */ | ||
113 | timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div)); | ||
114 | |||
115 | return 0; | ||
116 | } | ||
117 | |||
118 | int avr32_hpt_init(unsigned int count) | ||
119 | { | ||
120 | struct resource *regs; | ||
121 | struct clk *pclk; | ||
122 | int irq = -1; | ||
123 | int ret = 0; | ||
124 | |||
125 | ret = -ENXIO; | ||
126 | |||
127 | irq = platform_get_irq(&at32_systc0_device, 0); | ||
128 | if (irq < 0) { | ||
129 | pr_debug("timer: could not get irq\n"); | ||
130 | goto out_error; | ||
131 | } | ||
132 | |||
133 | pclk = clk_get(&at32_systc0_device.dev, "pclk"); | ||
134 | if (IS_ERR(pclk)) { | ||
135 | pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk)); | ||
136 | goto out_error; | ||
137 | } | ||
138 | |||
139 | regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0); | ||
140 | if (!regs) { | ||
141 | pr_debug("timer: could not get resource\n"); | ||
142 | goto out_error_clk; | ||
143 | } | ||
144 | |||
145 | ioregs = ioremap(regs->start, regs->end - regs->start + 1); | ||
146 | if (!ioregs) { | ||
147 | pr_debug("timer: could not get ioregs\n"); | ||
148 | goto out_error_clk; | ||
149 | } | ||
150 | |||
151 | ret = avr32_timer_calc_div_and_set_jiffies(pclk); | ||
152 | if (ret) | ||
153 | goto out_error_io; | ||
154 | |||
155 | ret = setup_irq(irq, &timer_irqaction); | ||
156 | if (ret) { | ||
157 | pr_debug("timer: could not request irq %d: %d\n", | ||
158 | irq, ret); | ||
159 | goto out_error_io; | ||
160 | } | ||
161 | |||
162 | expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1) | ||
163 | * cycles_per_jiffy; | ||
164 | |||
165 | /* Enable clock and interrupts on RC compare */ | ||
166 | timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN)); | ||
167 | timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS)); | ||
168 | /* Set cycles to first interrupt */ | ||
169 | timer_write(ioregs, 0, RC, expirelo); | ||
170 | |||
171 | printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n", | ||
172 | ioregs, irq); | ||
173 | |||
174 | return 0; | ||
175 | |||
176 | out_error_io: | ||
177 | iounmap(ioregs); | ||
178 | out_error_clk: | ||
179 | clk_put(pclk); | ||
180 | out_error: | ||
181 | return ret; | ||
182 | } | ||
183 | |||
184 | int avr32_hpt_start(void) | ||
185 | { | ||
186 | timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG)); | ||
187 | return 0; | ||
188 | } | ||
189 | |||
190 | irqreturn_t timer_interrupt(int irq, void *dev_id) | ||
191 | { | ||
192 | unsigned int sr = timer_read(ioregs, 0, SR); | ||
193 | |||
194 | if (sr & TIMER_BIT(SR_CPCS)) { | ||
195 | /* ack timer interrupt and try to set next interrupt */ | ||
196 | avr32_timer_ack(); | ||
197 | |||
198 | /* | ||
199 | * Call the generic timer interrupt handler | ||
200 | */ | ||
201 | write_seqlock(&xtime_lock); | ||
202 | do_timer(1); | ||
203 | write_sequnlock(&xtime_lock); | ||
204 | |||
205 | /* | ||
206 | * In UP mode, we call local_timer_interrupt() to do profiling | ||
207 | * and process accounting. | ||
208 | * | ||
209 | * SMP is not supported yet. | ||
210 | */ | ||
211 | local_timer_interrupt(irq, dev_id); | ||
212 | |||
213 | return IRQ_HANDLED; | ||
214 | } | ||
215 | |||
216 | return IRQ_NONE; | ||
217 | } | ||