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Diffstat (limited to 'arch/avr32/mach-at32ap/at32ap7000.c')
-rw-r--r--arch/avr32/mach-at32ap/at32ap7000.c144
1 files changed, 111 insertions, 33 deletions
diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
index c1e477ec7576..bc235507c5c7 100644
--- a/arch/avr32/mach-at32ap/at32ap7000.c
+++ b/arch/avr32/mach-at32ap/at32ap7000.c
@@ -8,6 +8,7 @@
8#include <linux/clk.h> 8#include <linux/clk.h>
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/spi/spi.h>
11 12
12#include <asm/io.h> 13#include <asm/io.h>
13 14
@@ -310,8 +311,6 @@ static void genclk_mode(struct clk *clk, int enabled)
310{ 311{
311 u32 control; 312 u32 control;
312 313
313 BUG_ON(clk->index > 7);
314
315 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 314 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
316 if (enabled) 315 if (enabled)
317 control |= SM_BIT(CEN); 316 control |= SM_BIT(CEN);
@@ -325,11 +324,6 @@ static unsigned long genclk_get_rate(struct clk *clk)
325 u32 control; 324 u32 control;
326 unsigned long div = 1; 325 unsigned long div = 1;
327 326
328 BUG_ON(clk->index > 7);
329
330 if (!clk->parent)
331 return 0;
332
333 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 327 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
334 if (control & SM_BIT(DIVEN)) 328 if (control & SM_BIT(DIVEN))
335 div = 2 * (SM_BFEXT(DIV, control) + 1); 329 div = 2 * (SM_BFEXT(DIV, control) + 1);
@@ -342,11 +336,6 @@ static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
342 u32 control; 336 u32 control;
343 unsigned long parent_rate, actual_rate, div; 337 unsigned long parent_rate, actual_rate, div;
344 338
345 BUG_ON(clk->index > 7);
346
347 if (!clk->parent)
348 return 0;
349
350 parent_rate = clk->parent->get_rate(clk->parent); 339 parent_rate = clk->parent->get_rate(clk->parent);
351 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 340 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
352 341
@@ -373,11 +362,8 @@ int genclk_set_parent(struct clk *clk, struct clk *parent)
373{ 362{
374 u32 control; 363 u32 control;
375 364
376 BUG_ON(clk->index > 7);
377
378 printk("clk %s: new parent %s (was %s)\n", 365 printk("clk %s: new parent %s (was %s)\n",
379 clk->name, parent->name, 366 clk->name, parent->name, clk->parent->name);
380 clk->parent ? clk->parent->name : "(null)");
381 367
382 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); 368 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
383 369
@@ -399,6 +385,22 @@ int genclk_set_parent(struct clk *clk, struct clk *parent)
399 return 0; 385 return 0;
400} 386}
401 387
388static void __init genclk_init_parent(struct clk *clk)
389{
390 u32 control;
391 struct clk *parent;
392
393 BUG_ON(clk->index > 7);
394
395 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
396 if (control & SM_BIT(OSCSEL))
397 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
398 else
399 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
400
401 clk->parent = parent;
402}
403
402/* -------------------------------------------------------------------- 404/* --------------------------------------------------------------------
403 * System peripherals 405 * System peripherals
404 * -------------------------------------------------------------------- */ 406 * -------------------------------------------------------------------- */
@@ -750,8 +752,41 @@ static struct resource atmel_spi1_resource[] = {
750DEFINE_DEV(atmel_spi, 1); 752DEFINE_DEV(atmel_spi, 1);
751DEV_CLK(spi_clk, atmel_spi1, pba, 1); 753DEV_CLK(spi_clk, atmel_spi1, pba, 1);
752 754
753struct platform_device *__init at32_add_device_spi(unsigned int id) 755static void
756at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
757 unsigned int n, const u8 *pins)
758{
759 unsigned int pin, mode;
760
761 for (; n; n--, b++) {
762 b->bus_num = bus_num;
763 if (b->chip_select >= 4)
764 continue;
765 pin = (unsigned)b->controller_data;
766 if (!pin) {
767 pin = pins[b->chip_select];
768 b->controller_data = (void *)pin;
769 }
770 mode = AT32_GPIOF_OUTPUT;
771 if (!(b->mode & SPI_CS_HIGH))
772 mode |= AT32_GPIOF_HIGH;
773 at32_select_gpio(pin, mode);
774 }
775}
776
777struct platform_device *__init
778at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
754{ 779{
780 /*
781 * Manage the chipselects as GPIOs, normally using the same pins
782 * the SPI controller expects; but boards can use other pins.
783 */
784 static u8 __initdata spi0_pins[] =
785 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
786 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
787 static u8 __initdata spi1_pins[] =
788 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
789 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
755 struct platform_device *pdev; 790 struct platform_device *pdev;
756 791
757 switch (id) { 792 switch (id) {
@@ -760,14 +795,7 @@ struct platform_device *__init at32_add_device_spi(unsigned int id)
760 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */ 795 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
761 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ 796 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
762 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ 797 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
763 798 at32_spi_setup_slaves(0, b, n, spi0_pins);
764 /* NPCS[2:0] */
765 at32_select_gpio(GPIO_PIN_PA(3),
766 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
767 at32_select_gpio(GPIO_PIN_PA(4),
768 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
769 at32_select_gpio(GPIO_PIN_PA(5),
770 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
771 break; 799 break;
772 800
773 case 1: 801 case 1:
@@ -775,20 +803,14 @@ struct platform_device *__init at32_add_device_spi(unsigned int id)
775 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */ 803 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
776 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ 804 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
777 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ 805 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
778 806 at32_spi_setup_slaves(1, b, n, spi1_pins);
779 /* NPCS[2:0] */
780 at32_select_gpio(GPIO_PIN_PB(2),
781 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
782 at32_select_gpio(GPIO_PIN_PB(3),
783 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
784 at32_select_gpio(GPIO_PIN_PB(4),
785 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
786 break; 807 break;
787 808
788 default: 809 default:
789 return NULL; 810 return NULL;
790 } 811 }
791 812
813 spi_register_board_info(b, n);
792 platform_device_register(pdev); 814 platform_device_register(pdev);
793 return pdev; 815 return pdev;
794} 816}
@@ -872,6 +894,50 @@ at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
872 return pdev; 894 return pdev;
873} 895}
874 896
897/* --------------------------------------------------------------------
898 * GCLK
899 * -------------------------------------------------------------------- */
900static struct clk gclk0 = {
901 .name = "gclk0",
902 .mode = genclk_mode,
903 .get_rate = genclk_get_rate,
904 .set_rate = genclk_set_rate,
905 .set_parent = genclk_set_parent,
906 .index = 0,
907};
908static struct clk gclk1 = {
909 .name = "gclk1",
910 .mode = genclk_mode,
911 .get_rate = genclk_get_rate,
912 .set_rate = genclk_set_rate,
913 .set_parent = genclk_set_parent,
914 .index = 1,
915};
916static struct clk gclk2 = {
917 .name = "gclk2",
918 .mode = genclk_mode,
919 .get_rate = genclk_get_rate,
920 .set_rate = genclk_set_rate,
921 .set_parent = genclk_set_parent,
922 .index = 2,
923};
924static struct clk gclk3 = {
925 .name = "gclk3",
926 .mode = genclk_mode,
927 .get_rate = genclk_get_rate,
928 .set_rate = genclk_set_rate,
929 .set_parent = genclk_set_parent,
930 .index = 3,
931};
932static struct clk gclk4 = {
933 .name = "gclk4",
934 .mode = genclk_mode,
935 .get_rate = genclk_get_rate,
936 .set_rate = genclk_set_rate,
937 .set_parent = genclk_set_parent,
938 .index = 4,
939};
940
875struct clk *at32_clock_list[] = { 941struct clk *at32_clock_list[] = {
876 &osc32k, 942 &osc32k,
877 &osc0, 943 &osc0,
@@ -908,6 +974,11 @@ struct clk *at32_clock_list[] = {
908 &atmel_spi1_spi_clk, 974 &atmel_spi1_spi_clk,
909 &lcdc0_hclk, 975 &lcdc0_hclk,
910 &lcdc0_pixclk, 976 &lcdc0_pixclk,
977 &gclk0,
978 &gclk1,
979 &gclk2,
980 &gclk3,
981 &gclk4,
911}; 982};
912unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list); 983unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
913 984
@@ -936,6 +1007,13 @@ void __init at32_clock_init(void)
936 if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC)) 1007 if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
937 pll1.parent = &osc1; 1008 pll1.parent = &osc1;
938 1009
1010 genclk_init_parent(&gclk0);
1011 genclk_init_parent(&gclk1);
1012 genclk_init_parent(&gclk2);
1013 genclk_init_parent(&gclk3);
1014 genclk_init_parent(&gclk4);
1015 genclk_init_parent(&lcdc0_pixclk);
1016
939 /* 1017 /*
940 * Turn on all clocks that have at least one user already, and 1018 * Turn on all clocks that have at least one user already, and
941 * turn off everything else. We only do this for module 1019 * turn off everything else. We only do this for module