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-rw-r--r--arch/arm/Kconfig23
-rw-r--r--arch/arm/Kconfig.debug80
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/boot/bootp/Makefile2
-rw-r--r--arch/arm/boot/compressed/Makefile2
-rw-r--r--arch/arm/boot/dts/Makefile35
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi8
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts5
-rw-r--r--arch/arm/boot/dts/am335x-boneblack.dts5
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi18
-rw-r--r--arch/arm/boot/dts/am4372.dtsi13
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts6
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts6
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts10
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn104.dts12
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts47
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi4
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi23
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi6
-rw-r--r--arch/arm/boot/dts/armada-xp-netgear-rn2120.dts6
-rw-r--r--arch/arm/boot/dts/at91-sama5d4ek.dts260
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi47
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts2
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi4
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi4
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts8
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi1
-rw-r--r--arch/arm/boot/dts/bcm63138.dtsi134
-rw-r--r--arch/arm/boot/dts/bcm963138dvt.dts30
-rw-r--r--arch/arm/boot/dts/berlin2q-marvell-dmp.dts4
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi17
-rw-r--r--arch/arm/boot/dts/cros-adc-thermistors.dtsi44
-rw-r--r--arch/arm/boot/dts/da850-evm.dts72
-rw-r--r--arch/arm/boot/dts/da850.dtsi19
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts2
-rw-r--r--arch/arm/boot/dts/dra7.dtsi25
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts120
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi5
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi8
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts8
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts8
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts22
-rw-r--r--arch/arm/boot/dts/exynos5250-cros-common.dtsi164
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts18
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts195
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi15
-rw-r--r--arch/arm/boot/dts/exynos5260-xyref5260.dts18
-rw-r--r--arch/arm/boot/dts/exynos5410-smdk5410.dts18
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts19
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts482
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts16
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts472
-rw-r--r--arch/arm/boot/dts/hip04-d01.dts32
-rw-r--r--arch/arm/boot/dts/hip04.dtsi267
-rw-r--r--arch/arm/boot/dts/imx1-ads.dts152
-rw-r--r--arch/arm/boot/dts/imx1-apf9328.dts129
-rw-r--r--arch/arm/boot/dts/imx1-pinfunc.h302
-rw-r--r--arch/arm/boot/dts/imx1.dtsi266
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts4
-rw-r--r--arch/arm/boot/dts/imx25-pinfunc.h33
-rw-r--r--arch/arm/boot/dts/imx25.dtsi4
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts17
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts4
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10055.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10056.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10057.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10058.dts4
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts4
-rw-r--r--arch/arm/boot/dts/imx28-m28cu3.dts4
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts4
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts107
-rw-r--r--arch/arm/boot/dts/imx28.dtsi43
-rw-r--r--arch/arm/boot/dts/imx35.dtsi1
-rw-r--r--arch/arm/boot/dts/imx50.dtsi2
-rw-r--r--arch/arm/boot/dts/imx51.dtsi3
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts2
-rw-r--r--arch/arm/boot/dts/imx53.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6dl-gw552x.dts20
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts203
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts203
-rw-r--r--arch/arm/boot/dts/imx6q-gw552x.dts24
-rw-r--r--arch/arm/boot/dts/imx6q-hummingboard.dts21
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi192
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi314
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi338
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi278
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw552x.dtsi267
-rw-r--r--arch/arm/boot/dts/imx6qdl-hummingboard.dtsi200
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi38
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi45
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi24
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts104
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi31
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts93
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi9
-rw-r--r--arch/arm/boot/dts/k2e.dtsi13
-rw-r--r--arch/arm/boot/dts/k2hk.dtsi56
-rw-r--r--arch/arm/boot/dts/k2l.dtsi46
-rw-r--r--arch/arm/boot/dts/keystone.dtsi10
-rw-r--r--arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts16
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6281-a.dts43
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts26
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts (renamed from arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts)18
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6281.dtsi27
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi4
-rw-r--r--arch/arm/boot/dts/meson.dtsi110
-rw-r--r--arch/arm/boot/dts/meson6-atv1200.dts66
-rw-r--r--arch/arm/boot/dts/meson6.dtsi78
-rw-r--r--arch/arm/boot/dts/mt6589-aquaris5.dts5
-rw-r--r--arch/arm/boot/dts/mt6589.dtsi4
-rw-r--r--arch/arm/boot/dts/omap2.dtsi1
-rw-r--r--arch/arm/boot/dts/omap2420-n810.dts7
-rw-r--r--arch/arm/boot/dts/omap2420-n8x0-common.dtsi6
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts4
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi (renamed from arch/arm/boot/dts/omap3-gta04.dts)150
-rw-r--r--arch/arm/boot/dts/omap3-gta04a3.dts48
-rw-r--r--arch/arm/boot/dts/omap3-gta04a4.dts13
-rw-r--r--arch/arm/boot/dts/omap3-gta04a5.dts17
-rw-r--r--arch/arm/boot/dts/omap3-ha-common.dtsi88
-rw-r--r--arch/arm/boot/dts/omap3-ha-lcd.dts165
-rw-r--r--arch/arm/boot/dts/omap3-ha.dts28
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts5
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts54
-rw-r--r--arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi5
-rw-r--r--arch/arm/boot/dts/omap3-tao3530.dtsi337
-rw-r--r--arch/arm/boot/dts/omap3-thunder.dts129
-rw-r--r--arch/arm/boot/dts/omap3.dtsi8
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi3
-rw-r--r--arch/arm/boot/dts/omap4-panda-es.dts5
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts5
-rw-r--r--arch/arm/boot/dts/omap4.dtsi15
-rw-r--r--arch/arm/boot/dts/omap5-cm-t54.dts272
-rw-r--r--arch/arm/boot/dts/omap5-sbc-t54.dts8
-rw-r--r--arch/arm/boot/dts/omap5.dtsi46
-rw-r--r--arch/arm/boot/dts/pxa2xx.dtsi4
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts43
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi183
-rw-r--r--arch/arm/boot/dts/qcom-apq8074-dragonboard.dts21
-rw-r--r--arch/arm/boot/dts/qcom-apq8084-ifc6540.dts23
-rw-r--r--arch/arm/boot/dts/qcom-apq8084-mtp.dts6
-rw-r--r--arch/arm/boot/dts/qcom-apq8084.dtsi51
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-ap148.dts85
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi1
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi250
-rw-r--r--arch/arm/boot/dts/qcom-msm8660-surf.dts42
-rw-r--r--arch/arm/boot/dts/qcom-msm8660.dtsi93
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts27
-rw-r--r--arch/arm/boot/dts/qcom-msm8960.dtsi87
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi15
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts4
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi6
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts283
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts276
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi220
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi6
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts4
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi58
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts44
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi159
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts35
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts41
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi140
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts47
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi531
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts15
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi67
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts90
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi91
-rw-r--r--arch/arm/boot/dts/rk3288-evb-act8846.dts10
-rw-r--r--arch/arm/boot/dts/rk3288-evb-rk808.dts132
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi87
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi380
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi126
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi37
-rw-r--r--arch/arm/boot/dts/sama5d3_can.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi30
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi4
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi1240
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi1
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts8
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi36
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi11
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi11
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts7
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dtsi13
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts4
-rw-r--r--arch/arm/boot/dts/socfpga_vt.dts9
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi18
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi6
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi19
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi17
-rw-r--r--arch/arm/boot/dts/sun5i-a13-hsg-h702.dts130
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi17
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi56
-rw-r--r--arch/arm/boot/dts/sun7i-a20-hummingbird.dts236
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts137
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi102
-rw-r--r--arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts41
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi237
-rw-r--r--arch/arm/boot/dts/sunxi-common-regulators.dtsi7
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi5
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1.dts98
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-big.dts1136
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts18
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi100
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi5
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi5
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi36
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi36
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts23
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts31
-rw-r--r--arch/arm/boot/dts/vf610-colibri-eval-v3.dts46
-rw-r--r--arch/arm/boot/dts/vf610-colibri.dtsi (renamed from arch/arm/boot/dts/vf610-colibri.dts)22
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts26
-rw-r--r--arch/arm/boot/dts/vf610.dtsi60
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi19
-rw-r--r--arch/arm/boot/dts/zynq-parallella.dts27
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts18
-rw-r--r--arch/arm/boot/dts/zynq-zc706.dts12
-rw-r--r--arch/arm/boot/dts/zynq-zed.dts14
-rw-r--r--arch/arm/common/scoop.c10
-rw-r--r--arch/arm/configs/ape6evm_defconfig9
-rw-r--r--arch/arm/configs/at91_dt_defconfig35
-rw-r--r--arch/arm/configs/at91sam9260_9g20_defconfig13
-rw-r--r--arch/arm/configs/at91sam9261_9g10_defconfig5
-rw-r--r--arch/arm/configs/at91sam9263_defconfig13
-rw-r--r--arch/arm/configs/at91sam9g45_defconfig19
-rw-r--r--arch/arm/configs/at91sam9rl_defconfig19
-rw-r--r--arch/arm/configs/bcm2835_defconfig1
-rw-r--r--arch/arm/configs/bcm_defconfig1
-rw-r--r--arch/arm/configs/bockw_defconfig3
-rw-r--r--arch/arm/configs/clps711x_defconfig4
-rw-r--r--arch/arm/configs/ep93xx_defconfig1
-rw-r--r--arch/arm/configs/ezx_defconfig1
-rw-r--r--arch/arm/configs/hisi_defconfig (renamed from arch/arm/configs/hi3xxx_defconfig)13
-rw-r--r--arch/arm/configs/imote2_defconfig1
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig16
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig10
-rw-r--r--arch/arm/configs/koelsch_defconfig17
-rw-r--r--arch/arm/configs/kzm9g_defconfig1
-rw-r--r--arch/arm/configs/lager_defconfig8
-rw-r--r--arch/arm/configs/lpc32xx_defconfig2
-rw-r--r--arch/arm/configs/marzen_defconfig1
-rw-r--r--arch/arm/configs/multi_v7_defconfig40
-rw-r--r--arch/arm/configs/mvebu_v7_defconfig68
-rw-r--r--arch/arm/configs/omap2plus_defconfig79
-rw-r--r--arch/arm/configs/pxa3xx_defconfig1
-rw-r--r--arch/arm/configs/qcom_defconfig14
-rw-r--r--arch/arm/configs/sama5_defconfig19
-rw-r--r--arch/arm/configs/shmobile_defconfig16
-rw-r--r--arch/arm/configs/sunxi_defconfig4
-rw-r--r--arch/arm/configs/tegra_defconfig5
-rw-r--r--arch/arm/configs/versatile_defconfig1
-rw-r--r--arch/arm/crypto/sha1-armv7-neon.S39
-rw-r--r--arch/arm/include/asm/arch_timer.h25
-rw-r--r--arch/arm/include/asm/atomic.h307
-rw-r--r--arch/arm/include/asm/cacheflush.h1
-rw-r--r--arch/arm/include/asm/dma-mapping.h16
-rw-r--r--arch/arm/include/asm/ftrace.h2
-rw-r--r--arch/arm/include/asm/io.h1
-rw-r--r--arch/arm/include/asm/irq_work.h11
-rw-r--r--arch/arm/include/asm/kvm_emulate.h5
-rw-r--r--arch/arm/include/asm/kvm_host.h23
-rw-r--r--arch/arm/include/asm/kvm_mmu.h11
-rw-r--r--arch/arm/include/asm/mcpm.h5
-rw-r--r--arch/arm/include/asm/pgtable-2level.h2
-rw-r--r--arch/arm/include/asm/pgtable-3level.h15
-rw-r--r--arch/arm/include/asm/pgtable.h6
-rw-r--r--arch/arm/include/asm/smp.h6
-rw-r--r--arch/arm/include/asm/syscall.h8
-rw-r--r--arch/arm/include/asm/tlb.h38
-rw-r--r--arch/arm/include/asm/tls.h2
-rw-r--r--arch/arm/include/debug/bcm63xx.S33
-rw-r--r--arch/arm/include/debug/meson.S35
-rw-r--r--arch/arm/include/uapi/asm/kvm.h2
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-rw-r--r--arch/arm/mach-shmobile/setup-r8a7791.c7
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7794.c33
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c6
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c21
-rw-r--r--arch/arm/mach-shmobile/timer.c30
-rw-r--r--arch/arm/mach-spear/Kconfig9
-rw-r--r--arch/arm/mach-sunxi/sunxi.c76
-rw-r--r--arch/arm/mach-tegra/flowctrl.c44
-rw-r--r--arch/arm/mach-tegra/flowctrl.h2
-rw-r--r--arch/arm/mach-tegra/tegra.c2
-rw-r--r--arch/arm/mach-vt8500/vt8500.c2
-rw-r--r--arch/arm/mach-zynq/Makefile3
-rw-r--r--arch/arm/mach-zynq/common.c13
-rw-r--r--arch/arm/mach-zynq/common.h16
-rw-r--r--arch/arm/mach-zynq/hotplug.c47
-rw-r--r--arch/arm/mach-zynq/platsmp.c41
-rw-r--r--arch/arm/mach-zynq/pm.c83
-rw-r--r--arch/arm/mach-zynq/slcr.c43
-rw-r--r--arch/arm/mm/alignment.c3
-rw-r--r--arch/arm/mm/cache-l2x0.c121
-rw-r--r--arch/arm/mm/dma-mapping.c210
-rw-r--r--arch/arm/mm/flush.c15
-rw-r--r--arch/arm/mm/idmap.c2
-rw-r--r--arch/arm/mm/init.c7
-rw-r--r--arch/arm/mm/mmu.c4
-rw-r--r--arch/arm/mm/proc-v7-3level.S4
-rw-r--r--arch/arm/mm/proc-v7.S2
-rw-r--r--arch/arm/net/bpf_jit_32.c37
-rw-r--r--arch/arm/net/bpf_jit_32.h14
-rw-r--r--arch/arm/plat-omap/dma.c737
-rw-r--r--arch/arm/plat-orion/common.c2
-rw-r--r--arch/arm/plat-pxa/ssp.c1
616 files changed, 18265 insertions, 9560 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 32cbbd565902..89c4b5ccc68d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -14,6 +14,7 @@ config ARM
14 select CLONE_BACKWARDS 14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE) 15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ALLOCATOR
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 18 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 19 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP 20 select GENERIC_IDLE_POLL_SETUP
@@ -24,6 +25,7 @@ config ARM
24 select GENERIC_SMP_IDLE_THREAD 25 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER 26 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER 27 select GENERIC_STRNLEN_USER
28 select HANDLE_DOMAIN_IRQ
27 select HARDIRQS_SW_RESEND 29 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 30 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 31 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
@@ -60,6 +62,7 @@ config ARM
60 select HAVE_PERF_EVENTS 62 select HAVE_PERF_EVENTS
61 select HAVE_PERF_REGS 63 select HAVE_PERF_REGS
62 select HAVE_PERF_USER_STACK_DUMP 64 select HAVE_PERF_USER_STACK_DUMP
65 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
63 select HAVE_REGS_AND_STACK_ACCESS_API 66 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS 67 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_UID16 68 select HAVE_UID16
@@ -387,6 +390,7 @@ config ARCH_CLPS711X
387 select CPU_ARM720T 390 select CPU_ARM720T
388 select GENERIC_CLOCKEVENTS 391 select GENERIC_CLOCKEVENTS
389 select MFD_SYSCON 392 select MFD_SYSCON
393 select SOC_BUS
390 help 394 help
391 Support for Cirrus Logic 711x/721x/731x based boards. 395 Support for Cirrus Logic 711x/721x/731x based boards.
392 396
@@ -650,6 +654,7 @@ config ARCH_SHMOBILE_LEGACY
650 select ARCH_SHMOBILE 654 select ARCH_SHMOBILE
651 select ARM_PATCH_PHYS_VIRT if MMU 655 select ARM_PATCH_PHYS_VIRT if MMU
652 select CLKDEV_LOOKUP 656 select CLKDEV_LOOKUP
657 select CPU_V7
653 select GENERIC_CLOCKEVENTS 658 select GENERIC_CLOCKEVENTS
654 select HAVE_ARM_SCU if SMP 659 select HAVE_ARM_SCU if SMP
655 select HAVE_ARM_TWD if SMP 660 select HAVE_ARM_TWD if SMP
@@ -660,6 +665,7 @@ config ARCH_SHMOBILE_LEGACY
660 select NO_IOPORT_MAP 665 select NO_IOPORT_MAP
661 select PINCTRL 666 select PINCTRL
662 select PM_GENERIC_DOMAINS if PM 667 select PM_GENERIC_DOMAINS if PM
668 select SH_CLK_CPG
663 select SPARSE_IRQ 669 select SPARSE_IRQ
664 help 670 help
665 Support for Renesas ARM SoC platforms using a non-multiplatform 671 Support for Renesas ARM SoC platforms using a non-multiplatform
@@ -888,6 +894,8 @@ source "arch/arm/mach-keystone/Kconfig"
888 894
889source "arch/arm/mach-ks8695/Kconfig" 895source "arch/arm/mach-ks8695/Kconfig"
890 896
897source "arch/arm/mach-meson/Kconfig"
898
891source "arch/arm/mach-msm/Kconfig" 899source "arch/arm/mach-msm/Kconfig"
892 900
893source "arch/arm/mach-moxart/Kconfig" 901source "arch/arm/mach-moxart/Kconfig"
@@ -1405,6 +1413,15 @@ config MCPM
1405 for (multi-)cluster based systems, such as big.LITTLE based 1413 for (multi-)cluster based systems, such as big.LITTLE based
1406 systems. 1414 systems.
1407 1415
1416config MCPM_QUAD_CLUSTER
1417 bool
1418 depends on MCPM
1419 help
1420 To avoid wasting resources unnecessarily, MCPM only supports up
1421 to 2 clusters by default.
1422 Platforms with 3 or 4 clusters that use MCPM must select this
1423 option to allow the additional clusters to be managed.
1424
1408config BIG_LITTLE 1425config BIG_LITTLE
1409 bool "big.LITTLE support (Experimental)" 1426 bool "big.LITTLE support (Experimental)"
1410 depends on CPU_V7 && SMP 1427 depends on CPU_V7 && SMP
@@ -1644,6 +1661,10 @@ config ARCH_SELECT_MEMORY_MODEL
1644config HAVE_ARCH_PFN_VALID 1661config HAVE_ARCH_PFN_VALID
1645 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1662 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1646 1663
1664config HAVE_GENERIC_RCU_GUP
1665 def_bool y
1666 depends on ARM_LPAE
1667
1647config HIGHMEM 1668config HIGHMEM
1648 bool "High Memory Support" 1669 bool "High Memory Support"
1649 depends on MMU 1670 depends on MMU
@@ -1758,7 +1779,7 @@ config XEN_DOM0
1758 depends on XEN 1779 depends on XEN
1759 1780
1760config XEN 1781config XEN
1761 bool "Xen guest support on ARM (EXPERIMENTAL)" 1782 bool "Xen guest support on ARM"
1762 depends on ARM && AEABI && OF 1783 depends on ARM && AEABI && OF
1763 depends on CPU_V7 && !CPU_V6 1784 depends on CPU_V7 && !CPU_V6
1764 depends on !GENERIC_ATOMIC64 1785 depends on !GENERIC_ATOMIC64
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b11ad54f8d17..03dc4c1a8736 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -101,6 +101,10 @@ choice
101 bool "Kernel low-level debugging on 9263 and 9g45" 101 bool "Kernel low-level debugging on 9263 and 9g45"
102 depends on HAVE_AT91_DBGU1 102 depends on HAVE_AT91_DBGU1
103 103
104 config AT91_DEBUG_LL_DBGU2
105 bool "Kernel low-level debugging on sama5d4"
106 depends on HAVE_AT91_DBGU2
107
104 config DEBUG_BCM2835 108 config DEBUG_BCM2835
105 bool "Kernel low-level debugging on BCM2835 PL011 UART" 109 bool "Kernel low-level debugging on BCM2835 PL011 UART"
106 depends on ARCH_BCM2835 110 depends on ARCH_BCM2835
@@ -122,6 +126,11 @@ choice
122 mobile SoCs in the Kona family of chips (e.g. bcm28155, 126 mobile SoCs in the Kona family of chips (e.g. bcm28155,
123 bcm11351, etc...) 127 bcm11351, etc...)
124 128
129 config DEBUG_BCM63XX
130 bool "Kernel low-level debugging on BCM63XX UART"
131 depends on ARCH_BCM_63XX
132 select DEBUG_UART_BCM63XX
133
125 config DEBUG_BERLIN_UART 134 config DEBUG_BERLIN_UART
126 bool "Marvell Berlin SoC Debug UART" 135 bool "Marvell Berlin SoC Debug UART"
127 depends on ARCH_BERLIN 136 depends on ARCH_BERLIN
@@ -147,7 +156,7 @@ choice
147 config DEBUG_CNS3XXX 156 config DEBUG_CNS3XXX
148 bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" 157 bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
149 depends on ARCH_CNS3XXX 158 depends on ARCH_CNS3XXX
150 select DEBUG_UART_PL01X 159 select DEBUG_UART_8250
151 help 160 help
152 Say Y here if you want the debug print routines to direct 161 Say Y here if you want the debug print routines to direct
153 their output to the CNS3xxx UART0. 162 their output to the CNS3xxx UART0.
@@ -223,14 +232,6 @@ choice
223 Say Y here if you want kernel low-level debugging support 232 Say Y here if you want kernel low-level debugging support
224 on HI3716 UART. 233 on HI3716 UART.
225 234
226 config DEBUG_HIX5HD2_UART
227 bool "Hisilicon Hix5hd2 Debug UART"
228 depends on ARCH_HIX5HD2
229 select DEBUG_UART_PL01X
230 help
231 Say Y here if you want kernel low-level debugging support
232 on Hix5hd2 UART.
233
234 config DEBUG_HIGHBANK_UART 235 config DEBUG_HIGHBANK_UART
235 bool "Kernel low-level debugging messages via Highbank UART" 236 bool "Kernel low-level debugging messages via Highbank UART"
236 depends on ARCH_HIGHBANK 237 depends on ARCH_HIGHBANK
@@ -239,6 +240,22 @@ choice
239 Say Y here if you want the debug print routines to direct 240 Say Y here if you want the debug print routines to direct
240 their output to the UART on Highbank based devices. 241 their output to the UART on Highbank based devices.
241 242
243 config DEBUG_HIP04_UART
244 bool "Hisilicon HiP04 Debug UART"
245 depends on ARCH_HIP04
246 select DEBUG_UART_8250
247 help
248 Say Y here if you want kernel low-level debugging support
249 on HIP04 UART.
250
251 config DEBUG_HIX5HD2_UART
252 bool "Hisilicon Hix5hd2 Debug UART"
253 depends on ARCH_HIX5HD2
254 select DEBUG_UART_PL01X
255 help
256 Say Y here if you want kernel low-level debugging support
257 on Hix5hd2 UART.
258
242 config DEBUG_IMX1_UART 259 config DEBUG_IMX1_UART
243 bool "i.MX1 Debug UART" 260 bool "i.MX1 Debug UART"
244 depends on SOC_IMX1 261 depends on SOC_IMX1
@@ -348,6 +365,13 @@ choice
348 Say Y here if you want the debug print routines to direct 365 Say Y here if you want the debug print routines to direct
349 their output to UART1 serial port on KEYSTONE2 devices. 366 their output to UART1 serial port on KEYSTONE2 devices.
350 367
368 config DEBUG_MESON_UARTAO
369 bool "Kernel low-level debugging via Meson6 UARTAO"
370 depends on ARCH_MESON
371 help
372 Say Y here if you want kernel low-lever debugging support
373 on Amlogic Meson6 based platforms on the UARTAO.
374
351 config DEBUG_MMP_UART2 375 config DEBUG_MMP_UART2
352 bool "Kernel low-level debugging message via MMP UART2" 376 bool "Kernel low-level debugging message via MMP UART2"
353 depends on ARCH_MMP 377 depends on ARCH_MMP
@@ -834,6 +858,14 @@ choice
834 Say Y here if you want kernel low-level debugging support 858 Say Y here if you want kernel low-level debugging support
835 on Ux500 based platforms. 859 on Ux500 based platforms.
836 860
861 config DEBUG_MT6589_UART0
862 bool "Mediatek mt6589 UART0"
863 depends on ARCH_MEDIATEK
864 select DEBUG_UART_8250
865 help
866 Say Y here if you want kernel low-level debugging support
867 for Mediatek mt6589 based platforms on UART0.
868
837 config DEBUG_VEXPRESS_UART0_DETECT 869 config DEBUG_VEXPRESS_UART0_DETECT
838 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" 870 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
839 depends on ARCH_VEXPRESS && CPU_CP15_MMU 871 depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -1011,6 +1043,7 @@ config DEBUG_LL_INCLUDE
1011 string 1043 string
1012 default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 1044 default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
1013 default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2 1045 default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
1046 default "debug/meson.S" if DEBUG_MESON_UARTAO
1014 default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X 1047 default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
1015 default "debug/exynos.S" if DEBUG_EXYNOS_UART 1048 default "debug/exynos.S" if DEBUG_EXYNOS_UART
1016 default "debug/efm32.S" if DEBUG_LL_UART_EFM32 1049 default "debug/efm32.S" if DEBUG_LL_UART_EFM32
@@ -1038,6 +1071,7 @@ config DEBUG_LL_INCLUDE
1038 default "debug/vf.S" if DEBUG_VF_UART 1071 default "debug/vf.S" if DEBUG_VF_UART
1039 default "debug/vt8500.S" if DEBUG_VT8500_UART0 1072 default "debug/vt8500.S" if DEBUG_VT8500_UART0
1040 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 1073 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
1074 default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX
1041 default "mach/debug-macro.S" 1075 default "mach/debug-macro.S"
1042 1076
1043# Compatibility options for PL01x 1077# Compatibility options for PL01x
@@ -1057,6 +1091,10 @@ config DEBUG_UART_8250
1057 ARCH_IOP33X || ARCH_IXP4XX || \ 1091 ARCH_IOP33X || ARCH_IXP4XX || \
1058 ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC 1092 ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC
1059 1093
1094# Compatibility options for BCM63xx
1095config DEBUG_UART_BCM63XX
1096 def_bool ARCH_BCM_63XX
1097
1060config DEBUG_UART_PHYS 1098config DEBUG_UART_PHYS
1061 hex "Physical base address of debug UART" 1099 hex "Physical base address of debug UART"
1062 default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 1100 default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
@@ -1068,13 +1106,14 @@ config DEBUG_UART_PHYS
1068 default 0x02530c00 if DEBUG_KEYSTONE_UART0 1106 default 0x02530c00 if DEBUG_KEYSTONE_UART0
1069 default 0x02531000 if DEBUG_KEYSTONE_UART1 1107 default 0x02531000 if DEBUG_KEYSTONE_UART1
1070 default 0x03010fe0 if ARCH_RPC 1108 default 0x03010fe0 if ARCH_RPC
1071 default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \ 1109 default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
1072 DEBUG_VEXPRESS_UART0_CA9 1110 DEBUG_VEXPRESS_UART0_CA9
1073 default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT 1111 default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
1074 default 0x10124000 if DEBUG_RK3X_UART0 1112 default 0x10124000 if DEBUG_RK3X_UART0
1075 default 0x10126000 if DEBUG_RK3X_UART1 1113 default 0x10126000 if DEBUG_RK3X_UART1
1076 default 0x101f1000 if ARCH_VERSATILE 1114 default 0x101f1000 if ARCH_VERSATILE
1077 default 0x101fb000 if DEBUG_NOMADIK_UART 1115 default 0x101fb000 if DEBUG_NOMADIK_UART
1116 default 0x11006000 if DEBUG_MT6589_UART0
1078 default 0x16000000 if ARCH_INTEGRATOR 1117 default 0x16000000 if ARCH_INTEGRATOR
1079 default 0x18000300 if DEBUG_BCM_5301X 1118 default 0x18000300 if DEBUG_BCM_5301X
1080 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 1119 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
@@ -1093,7 +1132,9 @@ config DEBUG_UART_PHYS
1093 DEBUG_S3C2410_UART1) 1132 DEBUG_S3C2410_UART1)
1094 default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ 1133 default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
1095 DEBUG_S3C2410_UART2) 1134 DEBUG_S3C2410_UART2)
1135 default 0x78000000 if DEBUG_CNS3XXX
1096 default 0x7c0003f8 if FOOTBRIDGE 1136 default 0x7c0003f8 if FOOTBRIDGE
1137 default 0x78000000 if DEBUG_CNS3XXX
1097 default 0x80070000 if DEBUG_IMX23_UART 1138 default 0x80070000 if DEBUG_IMX23_UART
1098 default 0x80074000 if DEBUG_IMX28_UART 1139 default 0x80074000 if DEBUG_IMX28_UART
1099 default 0x80230000 if DEBUG_PICOXCELL_UART 1140 default 0x80230000 if DEBUG_PICOXCELL_UART
@@ -1106,9 +1147,11 @@ config DEBUG_UART_PHYS
1106 default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN 1147 default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
1107 default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX 1148 default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
1108 default 0xd0012000 if DEBUG_MVEBU_UART 1149 default 0xd0012000 if DEBUG_MVEBU_UART
1150 default 0xc81004c0 if DEBUG_MESON_UARTAO
1109 default 0xd4017000 if DEBUG_MMP_UART2 1151 default 0xd4017000 if DEBUG_MMP_UART2
1110 default 0xd4018000 if DEBUG_MMP_UART3 1152 default 0xd4018000 if DEBUG_MMP_UART3
1111 default 0xe0000000 if ARCH_SPEAR13XX 1153 default 0xe0000000 if ARCH_SPEAR13XX
1154 default 0xe4007000 if DEBUG_HIP04_UART
1112 default 0xf0000be0 if ARCH_EBSA110 1155 default 0xf0000be0 if ARCH_EBSA110
1113 default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE 1156 default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
1114 default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \ 1157 default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
@@ -1122,21 +1165,23 @@ config DEBUG_UART_PHYS
1122 default 0xffc02000 if DEBUG_SOCFPGA_UART 1165 default 0xffc02000 if DEBUG_SOCFPGA_UART
1123 default 0xffd82340 if ARCH_IOP13XX 1166 default 0xffd82340 if ARCH_IOP13XX
1124 default 0xfff36000 if DEBUG_HIGHBANK_UART 1167 default 0xfff36000 if DEBUG_HIGHBANK_UART
1168 default 0xfffe8600 if DEBUG_UART_BCM63XX
1125 default 0xfffff700 if ARCH_IOP33X 1169 default 0xfffff700 if ARCH_IOP33X
1126 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ 1170 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1127 DEBUG_LL_UART_EFM32 || \ 1171 DEBUG_LL_UART_EFM32 || \
1128 DEBUG_UART_8250 || DEBUG_UART_PL01X || \ 1172 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1129 DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART 1173 DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
1174 DEBUG_UART_BCM63XX
1130 1175
1131config DEBUG_UART_VIRT 1176config DEBUG_UART_VIRT
1132 hex "Virtual base address of debug UART" 1177 hex "Virtual base address of debug UART"
1133 default 0xe0010fe0 if ARCH_RPC 1178 default 0xe0010fe0 if ARCH_RPC
1134 default 0xe1000000 if DEBUG_MSM_UART 1179 default 0xe1000000 if DEBUG_MSM_UART
1135 default 0xf0000be0 if ARCH_EBSA110 1180 default 0xf0000be0 if ARCH_EBSA110
1136 default 0xf0009000 if DEBUG_CNS3XXX
1137 default 0xf01fb000 if DEBUG_NOMADIK_UART 1181 default 0xf01fb000 if DEBUG_NOMADIK_UART
1138 default 0xf0201000 if DEBUG_BCM2835 1182 default 0xf0201000 if DEBUG_BCM2835
1139 default 0xf1000300 if DEBUG_BCM_5301X 1183 default 0xf1000300 if DEBUG_BCM_5301X
1184 default 0xf1006000 if DEBUG_MT6589_UART0
1140 default 0xf11f1000 if ARCH_VERSATILE 1185 default 0xf11f1000 if ARCH_VERSATILE
1141 default 0xf1600000 if ARCH_INTEGRATOR 1186 default 0xf1600000 if ARCH_INTEGRATOR
1142 default 0xf1c28000 if DEBUG_SUNXI_UART0 1187 default 0xf1c28000 if DEBUG_SUNXI_UART0
@@ -1152,16 +1197,20 @@ config DEBUG_UART_VIRT
1152 default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ 1197 default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
1153 DEBUG_S3C2410_UART2) 1198 DEBUG_S3C2410_UART2)
1154 default 0xf7fc9000 if DEBUG_BERLIN_UART 1199 default 0xf7fc9000 if DEBUG_BERLIN_UART
1200 default 0xf8007000 if DEBUG_HIP04_UART
1155 default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 1201 default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
1156 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 1202 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
1157 default 0xfa71e000 if DEBUG_QCOM_UARTDM 1203 default 0xfa71e000 if DEBUG_QCOM_UARTDM
1204 default 0xfb002000 if DEBUG_CNS3XXX
1158 default 0xfb009000 if DEBUG_REALVIEW_STD_PORT 1205 default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
1159 default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT 1206 default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
1207 default 0xfcfe8600 if DEBUG_UART_BCM63XX
1160 default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX 1208 default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
1161 default 0xfd000000 if ARCH_SPEAR13XX 1209 default 0xfd000000 if ARCH_SPEAR13XX
1162 default 0xfd012000 if ARCH_MV78XX0 1210 default 0xfd012000 if ARCH_MV78XX0
1163 default 0xfde12000 if ARCH_DOVE 1211 default 0xfde12000 if ARCH_DOVE
1164 default 0xfe012000 if ARCH_ORION5X 1212 default 0xfe012000 if ARCH_ORION5X
1213 default 0xf31004c0 if DEBUG_MESON_UARTAO
1165 default 0xfe017000 if DEBUG_MMP_UART2 1214 default 0xfe017000 if DEBUG_MMP_UART2
1166 default 0xfe018000 if DEBUG_MMP_UART3 1215 default 0xfe018000 if DEBUG_MMP_UART3
1167 default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART 1216 default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
@@ -1193,8 +1242,9 @@ config DEBUG_UART_VIRT
1193 default 0xff003000 if DEBUG_U300_UART 1242 default 0xff003000 if DEBUG_U300_UART
1194 default DEBUG_UART_PHYS if !MMU 1243 default DEBUG_UART_PHYS if !MMU
1195 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ 1244 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1196 DEBUG_UART_8250 || DEBUG_UART_PL01X || \ 1245 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1197 DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART 1246 DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
1247 DEBUG_UART_BCM63XX
1198 1248
1199config DEBUG_UART_8250_SHIFT 1249config DEBUG_UART_8250_SHIFT
1200 int "Register offset shift for the 8250 debug UART" 1250 int "Register offset shift for the 8250 debug UART"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0ce9d0f71f2a..dceb0441b1a6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_EBSA110) += ebsa110
157machine-$(CONFIG_ARCH_EFM32) += efm32 157machine-$(CONFIG_ARCH_EFM32) += efm32
158machine-$(CONFIG_ARCH_EP93XX) += ep93xx 158machine-$(CONFIG_ARCH_EP93XX) += ep93xx
159machine-$(CONFIG_ARCH_EXYNOS) += exynos 159machine-$(CONFIG_ARCH_EXYNOS) += exynos
160machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
160machine-$(CONFIG_ARCH_GEMINI) += gemini 161machine-$(CONFIG_ARCH_GEMINI) += gemini
161machine-$(CONFIG_ARCH_HIGHBANK) += highbank 162machine-$(CONFIG_ARCH_HIGHBANK) += highbank
162machine-$(CONFIG_ARCH_HISI) += hisi 163machine-$(CONFIG_ARCH_HISI) += hisi
@@ -168,6 +169,7 @@ machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
168machine-$(CONFIG_ARCH_KEYSTONE) += keystone 169machine-$(CONFIG_ARCH_KEYSTONE) += keystone
169machine-$(CONFIG_ARCH_KS8695) += ks8695 170machine-$(CONFIG_ARCH_KS8695) += ks8695
170machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx 171machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
172machine-$(CONFIG_ARCH_MESON) += meson
171machine-$(CONFIG_ARCH_MMP) += mmp 173machine-$(CONFIG_ARCH_MMP) += mmp
172machine-$(CONFIG_ARCH_MOXART) += moxart 174machine-$(CONFIG_ARCH_MOXART) += moxart
173machine-$(CONFIG_ARCH_MSM) += msm 175machine-$(CONFIG_ARCH_MSM) += msm
@@ -205,7 +207,6 @@ machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
205machine-$(CONFIG_ARCH_VT8500) += vt8500 207machine-$(CONFIG_ARCH_VT8500) += vt8500
206machine-$(CONFIG_ARCH_W90X900) += w90x900 208machine-$(CONFIG_ARCH_W90X900) += w90x900
207machine-$(CONFIG_ARCH_ZYNQ) += zynq 209machine-$(CONFIG_ARCH_ZYNQ) += zynq
208machine-$(CONFIG_FOOTBRIDGE) += footbridge
209machine-$(CONFIG_PLAT_SPEAR) += spear 210machine-$(CONFIG_PLAT_SPEAR) += spear
210 211
211# Platform directory name. This list is sorted alphanumerically 212# Platform directory name. This list is sorted alphanumerically
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index c394e305447c..5761f0039133 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -5,6 +5,8 @@
5# architecture-specific flags and dependencies. 5# architecture-specific flags and dependencies.
6# 6#
7 7
8GCOV_PROFILE := n
9
8LDFLAGS_bootp :=-p --no-undefined -X \ 10LDFLAGS_bootp :=-p --no-undefined -X \
9 --defsym initrd_phys=$(INITRD_PHYS) \ 11 --defsym initrd_phys=$(INITRD_PHYS) \
10 --defsym params_phys=$(PARAMS_PHYS) -T 12 --defsym params_phys=$(PARAMS_PHYS) -T
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 76a50ecae1c3..3ea230aa94b7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -37,6 +37,8 @@ ifeq ($(CONFIG_ARM_VIRT_EXT),y)
37OBJS += hyp-stub.o 37OBJS += hyp-stub.o
38endif 38endif
39 39
40GCOV_PROFILE := n
41
40# 42#
41# Architecture dependencies 43# Architecture dependencies
42# 44#
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3ddeb9..7c80af906897 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,11 +48,14 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
48dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb 48dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
49dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 49dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb 50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
51# sama5d4
52dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
51 53
52dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
53dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb 55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
54dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
55dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb 57dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
58dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
56dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 59dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
57 bcm21664-garnet.dtb 60 bcm21664-garnet.dtb
58dtb-$(CONFIG_ARCH_BERLIN) += \ 61dtb-$(CONFIG_ARCH_BERLIN) += \
@@ -90,6 +93,7 @@ dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
90dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb 93dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
91dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 94dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
92 ecx-2000.dtb 95 ecx-2000.dtb
96dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
93dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 97dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
94 integratorcp.dtb 98 integratorcp.dtb
95dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ 99dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
@@ -144,8 +148,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
144 kirkwood-openrd-client.dtb \ 148 kirkwood-openrd-client.dtb \
145 kirkwood-openrd-ultimate.dtb \ 149 kirkwood-openrd-ultimate.dtb \
146 kirkwood-rd88f6192.dtb \ 150 kirkwood-rd88f6192.dtb \
147 kirkwood-rd88f6281-a0.dtb \ 151 kirkwood-rd88f6281-z0.dtb \
148 kirkwood-rd88f6281-a1.dtb \ 152 kirkwood-rd88f6281-a.dtb \
149 kirkwood-rs212.dtb \ 153 kirkwood-rs212.dtb \
150 kirkwood-rs409.dtb \ 154 kirkwood-rs409.dtb \
151 kirkwood-rs411.dtb \ 155 kirkwood-rs411.dtb \
@@ -159,8 +163,11 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
159 kirkwood-ts419-6282.dtb 163 kirkwood-ts419-6282.dtb
160dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 164dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
161dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 165dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
166dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
162dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 167dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
163dtb-$(CONFIG_ARCH_MXC) += \ 168dtb-$(CONFIG_ARCH_MXC) += \
169 imx1-ads.dtb \
170 imx1-apf9328.dtb \
164 imx25-eukrea-mbimxsd25-baseboard.dtb \ 171 imx25-eukrea-mbimxsd25-baseboard.dtb \
165 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ 172 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
166 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ 173 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
@@ -199,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
199 imx6dl-gw52xx.dtb \ 206 imx6dl-gw52xx.dtb \
200 imx6dl-gw53xx.dtb \ 207 imx6dl-gw53xx.dtb \
201 imx6dl-gw54xx.dtb \ 208 imx6dl-gw54xx.dtb \
209 imx6dl-gw552x.dtb \
202 imx6dl-hummingboard.dtb \ 210 imx6dl-hummingboard.dtb \
203 imx6dl-nitrogen6x.dtb \ 211 imx6dl-nitrogen6x.dtb \
204 imx6dl-phytec-pbab01.dtb \ 212 imx6dl-phytec-pbab01.dtb \
@@ -223,6 +231,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
223 imx6q-gw53xx.dtb \ 231 imx6q-gw53xx.dtb \
224 imx6q-gw5400-a.dtb \ 232 imx6q-gw5400-a.dtb \
225 imx6q-gw54xx.dtb \ 233 imx6q-gw54xx.dtb \
234 imx6q-gw552x.dtb \
235 imx6q-hummingboard.dtb \
226 imx6q-nitrogen6x.dtb \ 236 imx6q-nitrogen6x.dtb \
227 imx6q-phytec-pbab01.dtb \ 237 imx6q-phytec-pbab01.dtb \
228 imx6q-rex-pro.dtb \ 238 imx6q-rex-pro.dtb \
@@ -240,7 +250,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
240 imx6q-tx6q-1110.dtb \ 250 imx6q-tx6q-1110.dtb \
241 imx6sl-evk.dtb \ 251 imx6sl-evk.dtb \
242 imx6sx-sdb.dtb \ 252 imx6sx-sdb.dtb \
243 vf610-colibri.dtb \ 253 vf610-colibri-eval-v3.dtb \
244 vf610-cosmic.dtb \ 254 vf610-cosmic.dtb \
245 vf610-twr.dtb 255 vf610-twr.dtb
246dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 256dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
@@ -286,7 +296,11 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
286 omap3-devkit8000.dtb \ 296 omap3-devkit8000.dtb \
287 omap3-evm.dtb \ 297 omap3-evm.dtb \
288 omap3-evm-37xx.dtb \ 298 omap3-evm-37xx.dtb \
289 omap3-gta04.dtb \ 299 omap3-gta04a3.dtb \
300 omap3-gta04a4.dtb \
301 omap3-gta04a5.dtb \
302 omap3-ha.dtb \
303 omap3-ha-lcd.dtb \
290 omap3-igep0020.dtb \ 304 omap3-igep0020.dtb \
291 omap3-igep0030.dtb \ 305 omap3-igep0030.dtb \
292 omap3-ldp.dtb \ 306 omap3-ldp.dtb \
@@ -309,6 +323,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
309 omap3-sbc-t3517.dtb \ 323 omap3-sbc-t3517.dtb \
310 omap3-sbc-t3530.dtb \ 324 omap3-sbc-t3530.dtb \
311 omap3-sbc-t3730.dtb \ 325 omap3-sbc-t3730.dtb \
326 omap3-thunder.dtb \
312 omap3-zoom3.dtb 327 omap3-zoom3.dtb
313dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ 328dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
314 am335x-bone.dtb \ 329 am335x-bone.dtb \
@@ -341,7 +356,9 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
341dtb-$(CONFIG_ARCH_QCOM) += \ 356dtb-$(CONFIG_ARCH_QCOM) += \
342 qcom-apq8064-ifc6410.dtb \ 357 qcom-apq8064-ifc6410.dtb \
343 qcom-apq8074-dragonboard.dtb \ 358 qcom-apq8074-dragonboard.dtb \
359 qcom-apq8084-ifc6540.dtb \
344 qcom-apq8084-mtp.dtb \ 360 qcom-apq8084-mtp.dtb \
361 qcom-ipq8064-ap148.dtb \
345 qcom-msm8660-surf.dtb \ 362 qcom-msm8660-surf.dtb \
346 qcom-msm8960-cdp.dtb 363 qcom-msm8960-cdp.dtb
347dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 364dtb-$(CONFIG_ARCH_ROCKCHIP) += \
@@ -361,7 +378,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
361 r8a7740-armadillo800eva.dtb \ 378 r8a7740-armadillo800eva.dtb \
362 r8a7778-bockw.dtb \ 379 r8a7778-bockw.dtb \
363 r8a7778-bockw-reference.dtb \ 380 r8a7778-bockw-reference.dtb \
364 r8a7740-armadillo800eva-reference.dtb \
365 r8a7779-marzen.dtb \ 381 r8a7779-marzen.dtb \
366 r8a7791-koelsch.dtb \ 382 r8a7791-koelsch.dtb \
367 r8a7790-lager.dtb \ 383 r8a7790-lager.dtb \
@@ -372,10 +388,12 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
372 sh7372-mackerel.dtb 388 sh7372-mackerel.dtb
373dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ 389dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
374 r7s72100-genmai.dtb \ 390 r7s72100-genmai.dtb \
391 r8a7740-armadillo800eva.dtb \
375 r8a7791-henninger.dtb \ 392 r8a7791-henninger.dtb \
376 r8a7791-koelsch.dtb \ 393 r8a7791-koelsch.dtb \
377 r8a7790-lager.dtb \ 394 r8a7790-lager.dtb \
378 r8a7779-marzen.dtb 395 r8a7779-marzen.dtb \
396 r8a7794-alt.dtb
379dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ 397dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
380 socfpga_cyclone5_socdk.dtb \ 398 socfpga_cyclone5_socdk.dtb \
381 socfpga_cyclone5_sockit.dtb \ 399 socfpga_cyclone5_sockit.dtb \
@@ -406,6 +424,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
406dtb-$(CONFIG_MACH_SUN5I) += \ 424dtb-$(CONFIG_MACH_SUN5I) += \
407 sun5i-a10s-olinuxino-micro.dtb \ 425 sun5i-a10s-olinuxino-micro.dtb \
408 sun5i-a10s-r7-tv-dongle.dtb \ 426 sun5i-a10s-r7-tv-dongle.dtb \
427 sun5i-a13-hsg-h702.dtb \
409 sun5i-a13-olinuxino.dtb \ 428 sun5i-a13-olinuxino.dtb \
410 sun5i-a13-olinuxino-micro.dtb 429 sun5i-a13-olinuxino-micro.dtb
411dtb-$(CONFIG_MACH_SUN6I) += \ 430dtb-$(CONFIG_MACH_SUN6I) += \
@@ -416,7 +435,9 @@ dtb-$(CONFIG_MACH_SUN6I) += \
416dtb-$(CONFIG_MACH_SUN7I) += \ 435dtb-$(CONFIG_MACH_SUN7I) += \
417 sun7i-a20-cubieboard2.dtb \ 436 sun7i-a20-cubieboard2.dtb \
418 sun7i-a20-cubietruck.dtb \ 437 sun7i-a20-cubietruck.dtb \
438 sun7i-a20-hummingbird.dtb \
419 sun7i-a20-i12-tvbox.dtb \ 439 sun7i-a20-i12-tvbox.dtb \
440 sun7i-a20-olinuxino-lime.dtb \
420 sun7i-a20-olinuxino-micro.dtb \ 441 sun7i-a20-olinuxino-micro.dtb \
421 sun7i-a20-pcduino3.dtb 442 sun7i-a20-pcduino3.dtb
422dtb-$(CONFIG_MACH_SUN8I) += \ 443dtb-$(CONFIG_MACH_SUN8I) += \
@@ -440,6 +461,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
440 tegra114-roth.dtb \ 461 tegra114-roth.dtb \
441 tegra114-tn7.dtb \ 462 tegra114-tn7.dtb \
442 tegra124-jetson-tk1.dtb \ 463 tegra124-jetson-tk1.dtb \
464 tegra124-nyan-big.dtb \
443 tegra124-venice2.dtb 465 tegra124-venice2.dtb
444dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 466dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
445dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 467dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
@@ -491,6 +513,7 @@ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
491 dove-d2plug.dtb \ 513 dove-d2plug.dtb \
492 dove-d3plug.dtb \ 514 dove-d3plug.dtb \
493 dove-dove-db.dtb 515 dove-dove-db.dtb
516dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb
494 517
495targets += dtbs dtbs_install 518targets += dtbs dtbs_install
496targets += $(dtb-y) 519targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index bde1777b62be..6cc25ed912ee 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -7,9 +7,6 @@
7 */ 7 */
8 8
9/ { 9/ {
10 model = "TI AM335x BeagleBone";
11 compatible = "ti,am335x-bone", "ti,am33xx";
12
13 cpus { 10 cpus {
14 cpu@0 { 11 cpu@0 {
15 cpu0-supply = <&dcdc2_reg>; 12 cpu0-supply = <&dcdc2_reg>;
@@ -227,6 +224,7 @@
227&tps { 224&tps {
228 regulators { 225 regulators {
229 dcdc1_reg: regulator@0 { 226 dcdc1_reg: regulator@0 {
227 regulator-name = "vdds_dpr";
230 regulator-always-on; 228 regulator-always-on;
231 }; 229 };
232 230
@@ -249,18 +247,22 @@
249 }; 247 };
250 248
251 ldo1_reg: regulator@3 { 249 ldo1_reg: regulator@3 {
250 regulator-name = "vio,vrtc,vdds";
252 regulator-always-on; 251 regulator-always-on;
253 }; 252 };
254 253
255 ldo2_reg: regulator@4 { 254 ldo2_reg: regulator@4 {
255 regulator-name = "vdd_3v3aux";
256 regulator-always-on; 256 regulator-always-on;
257 }; 257 };
258 258
259 ldo3_reg: regulator@5 { 259 ldo3_reg: regulator@5 {
260 regulator-name = "vdd_1v8";
260 regulator-always-on; 261 regulator-always-on;
261 }; 262 };
262 263
263 ldo4_reg: regulator@6 { 264 ldo4_reg: regulator@6 {
265 regulator-name = "vdd_3v3a";
264 regulator-always-on; 266 regulator-always-on;
265 }; 267 };
266 }; 268 };
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 94ee427a6db1..83d40f7655e5 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -10,6 +10,11 @@
10#include "am33xx.dtsi" 10#include "am33xx.dtsi"
11#include "am335x-bone-common.dtsi" 11#include "am335x-bone-common.dtsi"
12 12
13/ {
14 model = "TI AM335x BeagleBone";
15 compatible = "ti,am335x-bone", "ti,am33xx";
16};
17
13&ldo3_reg { 18&ldo3_reg {
14 regulator-min-microvolt = <1800000>; 19 regulator-min-microvolt = <1800000>;
15 regulator-max-microvolt = <3300000>; 20 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 305975d3f531..901739fcb85a 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -10,6 +10,11 @@
10#include "am33xx.dtsi" 10#include "am33xx.dtsi"
11#include "am335x-bone-common.dtsi" 11#include "am335x-bone-common.dtsi"
12 12
13/ {
14 model = "TI AM335x BeagleBone Black";
15 compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
16};
17
13&ldo3_reg { 18&ldo3_reg {
14 regulator-min-microvolt = <1800000>; 19 regulator-min-microvolt = <1800000>;
15 regulator-max-microvolt = <1800000>; 20 regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 3a0a161342ba..831810583823 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -132,11 +132,15 @@
132 }; 132 };
133 }; 133 };
134 134
135 cm: syscon@44e10000 {
136 compatible = "ti,am33xx-controlmodule", "syscon";
137 reg = <0x44e10000 0x800>;
138 };
139
135 intc: interrupt-controller@48200000 { 140 intc: interrupt-controller@48200000 {
136 compatible = "ti,omap2-intc"; 141 compatible = "ti,am33xx-intc";
137 interrupt-controller; 142 interrupt-controller;
138 #interrupt-cells = <1>; 143 #interrupt-cells = <1>;
139 ti,intc-size = <128>;
140 reg = <0x48200000 0x1000>; 144 reg = <0x48200000 0x1000>;
141 }; 145 };
142 146
@@ -354,6 +358,10 @@
354 ti,hwmods = "mailbox"; 358 ti,hwmods = "mailbox";
355 ti,mbox-num-users = <4>; 359 ti,mbox-num-users = <4>;
356 ti,mbox-num-fifos = <8>; 360 ti,mbox-num-fifos = <8>;
361 mbox_wkupm3: wkup_m3 {
362 ti,mbox-tx = <0 0 0>;
363 ti,mbox-rx = <0 0 3>;
364 };
357 }; 365 };
358 366
359 timer1: timer@44e31000 { 367 timer1: timer@44e31000 {
@@ -696,6 +704,7 @@
696 */ 704 */
697 interrupts = <40 41 42 43>; 705 interrupts = <40 41 42 43>;
698 ranges; 706 ranges;
707 syscon = <&cm>;
699 status = "disabled"; 708 status = "disabled";
700 709
701 davinci_mdio: mdio@4a101000 { 710 davinci_mdio: mdio@4a101000 {
@@ -726,9 +735,8 @@
726 }; 735 };
727 736
728 ocmcram: ocmcram@40300000 { 737 ocmcram: ocmcram@40300000 {
729 compatible = "ti,am3352-ocmcram"; 738 compatible = "mmio-sram";
730 reg = <0x40300000 0x10000>; 739 reg = <0x40300000 0x10000>; /* 64k */
731 ti,hwmods = "ocmcram";
732 }; 740 };
733 741
734 wkup_m3: wkup_m3@44d00000 { 742 wkup_m3: wkup_m3@44d00000 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 8689949bdba3..46660ffd2b65 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -58,10 +58,12 @@
58 }; 58 };
59 59
60 am43xx_pinmux: pinmux@44e10800 { 60 am43xx_pinmux: pinmux@44e10800 {
61 compatible = "pinctrl-single"; 61 compatible = "ti,am437-padconf", "pinctrl-single";
62 reg = <0x44e10800 0x31c>; 62 reg = <0x44e10800 0x31c>;
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <0>; 64 #size-cells = <0>;
65 #interrupt-cells = <1>;
66 interrupt-controller;
65 pinctrl-single,register-width = <32>; 67 pinctrl-single,register-width = <32>;
66 pinctrl-single,function-mask = <0xffffffff>; 68 pinctrl-single,function-mask = <0xffffffff>;
67 }; 69 };
@@ -168,6 +170,10 @@
168 ti,hwmods = "mailbox"; 170 ti,hwmods = "mailbox";
169 ti,mbox-num-users = <4>; 171 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <8>; 172 ti,mbox-num-fifos = <8>;
173 mbox_wkupm3: wkup_m3 {
174 ti,mbox-tx = <0 0 0>;
175 ti,mbox-rx = <0 0 3>;
176 };
171 }; 177 };
172 178
173 timer1: timer@44e31000 { 179 timer1: timer@44e31000 {
@@ -885,6 +891,11 @@
885 clock-names = "fck"; 891 clock-names = "fck";
886 }; 892 };
887 }; 893 };
894
895 ocmcram: ocmcram@40300000 {
896 compatible = "mmio-sram";
897 reg = <0x40300000 0x40000>; /* 256k */
898 };
888 }; 899 };
889}; 900};
890 901
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 416f4e5a69c1..a495e5821ab8 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -43,6 +43,8 @@
43 }; 43 };
44 44
45 mdio { 45 mdio {
46 pinctrl-0 = <&mdio_pins>;
47 pinctrl-names = "default";
46 phy0: ethernet-phy@0 { 48 phy0: ethernet-phy@0 {
47 reg = <0>; 49 reg = <0>;
48 }; 50 };
@@ -53,11 +55,15 @@
53 }; 55 };
54 56
55 ethernet@70000 { 57 ethernet@70000 {
58 pinctrl-0 = <&ge0_rgmii_pins>;
59 pinctrl-names = "default";
56 status = "okay"; 60 status = "okay";
57 phy = <&phy0>; 61 phy = <&phy0>;
58 phy-mode = "rgmii-id"; 62 phy-mode = "rgmii-id";
59 }; 63 };
60 ethernet@74000 { 64 ethernet@74000 {
65 pinctrl-0 = <&ge1_rgmii_pins>;
66 pinctrl-names = "default";
61 status = "okay"; 67 status = "okay";
62 phy = <&phy1>; 68 phy = <&phy1>;
63 phy-mode = "rgmii-id"; 69 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 097df7d8f0f6..2b6d24e0d1e8 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -91,6 +91,8 @@
91 }; 91 };
92 92
93 mdio { 93 mdio {
94 pinctrl-0 = <&mdio_pins>;
95 pinctrl-names = "default";
94 phy0: ethernet-phy@0 { 96 phy0: ethernet-phy@0 {
95 reg = <0>; 97 reg = <0>;
96 }; 98 };
@@ -100,11 +102,15 @@
100 }; 102 };
101 }; 103 };
102 ethernet@70000 { 104 ethernet@70000 {
105 pinctrl-0 = <&ge0_rgmii_pins>;
106 pinctrl-names = "default";
103 status = "okay"; 107 status = "okay";
104 phy = <&phy0>; 108 phy = <&phy0>;
105 phy-mode = "rgmii-id"; 109 phy-mode = "rgmii-id";
106 }; 110 };
107 ethernet@74000 { 111 ethernet@74000 {
112 pinctrl-0 = <&ge1_rgmii_pins>;
113 pinctrl-names = "default";
108 status = "okay"; 114 status = "okay";
109 phy = <&phy1>; 115 phy = <&phy1>;
110 phy-mode = "rgmii-id"; 116 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index d6d572e5af32..3aebd93cc33c 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -101,12 +101,16 @@
101 }; 101 };
102 102
103 mdio { 103 mdio {
104 pinctrl-0 = <&mdio_pins>;
105 pinctrl-names = "default";
104 phy0: ethernet-phy@0 { /* Marvell 88E1318 */ 106 phy0: ethernet-phy@0 { /* Marvell 88E1318 */
105 reg = <0>; 107 reg = <0>;
106 }; 108 };
107 }; 109 };
108 110
109 ethernet@74000 { 111 ethernet@74000 {
112 pinctrl-0 = <&ge1_rgmii_pins>;
113 pinctrl-names = "default";
110 status = "okay"; 114 status = "okay";
111 phy = <&phy0>; 115 phy = <&phy0>;
112 phy-mode = "rgmii-id"; 116 phy-mode = "rgmii-id";
@@ -122,7 +126,7 @@
122 status = "okay"; 126 status = "okay";
123 127
124 isl12057: isl12057@68 { 128 isl12057: isl12057@68 {
125 compatible = "isl,isl12057"; 129 compatible = "isil,isl12057";
126 reg = <0x68>; 130 reg = <0x68>;
127 }; 131 };
128 132
@@ -143,6 +147,10 @@
143 marvell,nand-enable-arbiter; 147 marvell,nand-enable-arbiter;
144 nand-on-flash-bbt; 148 nand-on-flash-bbt;
145 149
150 /* Use Hardware BCH ECC */
151 nand-ecc-strength = <4>;
152 nand-ecc-step-size = <512>;
153
146 partition@0 { 154 partition@0 {
147 label = "u-boot"; 155 label = "u-boot";
148 reg = <0x0000000 0x180000>; /* 1.5MB */ 156 reg = <0x0000000 0x180000>; /* 1.5MB */
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index c5fe8b5dcdc7..c2f414bb9aba 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -86,6 +86,8 @@
86 }; 86 };
87 87
88 mdio { 88 mdio {
89 pinctrl-0 = <&mdio_pins>;
90 pinctrl-names = "default";
89 phy0: ethernet-phy@0 { /* Marvell 88E1318 */ 91 phy0: ethernet-phy@0 { /* Marvell 88E1318 */
90 reg = <0>; 92 reg = <0>;
91 }; 93 };
@@ -96,12 +98,16 @@
96 }; 98 };
97 99
98 ethernet@70000 { 100 ethernet@70000 {
101 pinctrl-0 = <&ge0_rgmii_pins>;
102 pinctrl-names = "default";
99 status = "okay"; 103 status = "okay";
100 phy = <&phy0>; 104 phy = <&phy0>;
101 phy-mode = "rgmii-id"; 105 phy-mode = "rgmii-id";
102 }; 106 };
103 107
104 ethernet@74000 { 108 ethernet@74000 {
109 pinctrl-0 = <&ge1_rgmii_pins>;
110 pinctrl-names = "default";
105 status = "okay"; 111 status = "okay";
106 phy = <&phy1>; 112 phy = <&phy1>;
107 phy-mode = "rgmii-id"; 113 phy-mode = "rgmii-id";
@@ -117,7 +123,7 @@
117 status = "okay"; 123 status = "okay";
118 124
119 isl12057: isl12057@68 { 125 isl12057: isl12057@68 {
120 compatible = "isl,isl12057"; 126 compatible = "isil,isl12057";
121 reg = <0x68>; 127 reg = <0x68>;
122 }; 128 };
123 129
@@ -145,6 +151,10 @@
145 marvell,nand-enable-arbiter; 151 marvell,nand-enable-arbiter;
146 nand-on-flash-bbt; 152 nand-on-flash-bbt;
147 153
154 /* Use Hardware BCH ECC */
155 nand-ecc-strength = <4>;
156 nand-ecc-step-size = <512>;
157
148 partition@0 { 158 partition@0 {
149 label = "u-boot"; 159 label = "u-boot";
150 reg = <0x0000000 0x180000>; /* 1.5MB */ 160 reg = <0x0000000 0x180000>; /* 1.5MB */
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 4169f4096ea3..f57a8f841498 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -9,6 +9,15 @@
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 *
13 * Note: this Device Tree assumes that the bootloader has remapped the
14 * internal registers to 0xf1000000 (instead of the default
15 * 0xd0000000). The 0xf1000000 is the default used by the recent,
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
17 * boards were delivered with an older version of the bootloader that
18 * left internal registers mapped at 0xd0000000. If you are in this
19 * situation, you should either update your bootloader (preferred
20 * solution) or the below Device Tree should be adjusted.
12 */ 21 */
13 22
14/dts-v1/; 23/dts-v1/;
@@ -30,7 +39,7 @@
30 }; 39 };
31 40
32 soc { 41 soc {
33 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 42 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
34 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; 43 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
35 44
36 pcie-controller { 45 pcie-controller {
@@ -50,6 +59,18 @@
50 }; 59 };
51 60
52 internal-regs { 61 internal-regs {
62 pinctrl {
63 fan_pins: fan-pins {
64 marvell,pins = "mpp8";
65 marvell,function = "gpio";
66 };
67
68 led_pins: led-pins {
69 marvell,pins = "mpp32";
70 marvell,function = "gpio";
71 };
72 };
73
53 serial@12000 { 74 serial@12000 {
54 status = "okay"; 75 status = "okay";
55 }; 76 };
@@ -59,6 +80,8 @@
59 }; 80 };
60 81
61 mdio { 82 mdio {
83 pinctrl-0 = <&mdio_pins>;
84 pinctrl-names = "default";
62 phy0: ethernet-phy@0 { 85 phy0: ethernet-phy@0 {
63 reg = <0>; 86 reg = <0>;
64 }; 87 };
@@ -74,6 +97,8 @@
74 phy-mode = "sgmii"; 97 phy-mode = "sgmii";
75 }; 98 };
76 ethernet@74000 { 99 ethernet@74000 {
100 pinctrl-0 = <&ge1_rgmii_pins>;
101 pinctrl-names = "default";
77 status = "okay"; 102 status = "okay";
78 phy = <&phy1>; 103 phy = <&phy1>;
79 phy-mode = "rgmii-id"; 104 phy-mode = "rgmii-id";
@@ -106,6 +131,26 @@
106 }; 131 };
107 }; 132 };
108 133
134 gpio-fan {
135 compatible = "gpio-fan";
136 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
137 gpio-fan,speed-map = <0 0 3000 1>;
138 pinctrl-0 = <&fan_pins>;
139 pinctrl-names = "default";
140 };
141
142 gpio_leds {
143 compatible = "gpio-leds";
144 pinctrl-names = "default";
145 pinctrl-0 = <&led_pins>;
146
147 sw_led {
148 label = "370rd:green:sw";
149 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
150 default-state = "keep";
151 };
152 };
153
109 nand@d0000 { 154 nand@d0000 {
110 status = "okay"; 155 status = "okay";
111 num-cs = <1>; 156 num-cs = <1>;
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 23227e0027ec..83286ec9702c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -110,7 +110,7 @@
110 }; 110 };
111 111
112 spi0: spi@10600 { 112 spi0: spi@10600 {
113 compatible = "marvell,orion-spi"; 113 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
114 reg = <0x10600 0x28>; 114 reg = <0x10600 0x28>;
115 #address-cells = <1>; 115 #address-cells = <1>;
116 #size-cells = <0>; 116 #size-cells = <0>;
@@ -121,7 +121,7 @@
121 }; 121 };
122 122
123 spi1: spi@10680 { 123 spi1: spi@10680 {
124 compatible = "marvell,orion-spi"; 124 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
125 reg = <0x10680 0x28>; 125 reg = <0x10680 0x28>;
126 #address-cells = <1>; 126 #address-cells = <1>;
127 #size-cells = <0>; 127 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 21b588b6f6bd..6b3c23b1e138 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -151,6 +151,25 @@
151 "mpp62", "mpp60", "mpp58"; 151 "mpp62", "mpp60", "mpp58";
152 marvell,function = "audio"; 152 marvell,function = "audio";
153 }; 153 };
154
155 mdio_pins: mdio-pins {
156 marvell,pins = "mpp17", "mpp18";
157 marvell,function = "ge";
158 };
159
160 ge0_rgmii_pins: ge0-rgmii-pins {
161 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
162 "mpp9", "mpp10", "mpp11", "mpp12",
163 "mpp13", "mpp14", "mpp15", "mpp16";
164 marvell,function = "ge0";
165 };
166
167 ge1_rgmii_pins: ge1-rgmii-pins {
168 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
169 "mpp23", "mpp24", "mpp25", "mpp26",
170 "mpp27", "mpp28", "mpp29", "mpp30";
171 marvell,function = "ge1";
172 };
154 }; 173 };
155 174
156 gpio0: gpio@18100 { 175 gpio0: gpio@18100 {
@@ -206,6 +225,10 @@
206 status = "okay"; 225 status = "okay";
207 }; 226 };
208 227
228 sscg@18330 {
229 reg = <0x18330 0x4>;
230 };
231
209 interrupt-controller@20000 { 232 interrupt-controller@20000 {
210 reg = <0x20a00 0x1d0>, <0x21870 0x58>; 233 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
211 }; 234 };
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index c1e49e7bf0fa..de6571445cef 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -185,6 +185,12 @@
185 }; 185 };
186 }; 186 };
187 187
188 rtc@10300 {
189 compatible = "marvell,orion-rtc";
190 reg = <0x10300 0x20>;
191 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
192 };
193
188 spi0: spi@10600 { 194 spi0: spi@10600 {
189 compatible = "marvell,orion-spi"; 195 compatible = "marvell,orion-spi";
190 reg = <0x10600 0x50>; 196 reg = <0x10600 0x50>;
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 0cf999abc4ed..7d8f32873e82 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -174,7 +174,7 @@
174 status = "okay"; 174 status = "okay";
175 175
176 isl12057: isl12057@68 { 176 isl12057: isl12057@68 {
177 compatible = "isl,isl12057"; 177 compatible = "isil,isl12057";
178 reg = <0x68>; 178 reg = <0x68>;
179 }; 179 };
180 180
@@ -223,6 +223,10 @@
223 marvell,nand-enable-arbiter; 223 marvell,nand-enable-arbiter;
224 nand-on-flash-bbt; 224 nand-on-flash-bbt;
225 225
226 /* Use Hardware BCH ECC */
227 nand-ecc-strength = <4>;
228 nand-ecc-step-size = <512>;
229
226 partition@0 { 230 partition@0 {
227 label = "u-boot"; 231 label = "u-boot";
228 reg = <0x0000000 0x180000>; /* 1.5MB */ 232 reg = <0x0000000 0x180000>; /* 1.5MB */
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index 000000000000..b5b84006469e
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,260 @@
1/*
2 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This library is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45/dts-v1/;
46#include "sama5d4.dtsi"
47
48/ {
49 model = "Atmel SAMA5D4-EK";
50 compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
51
52 chosen {
53 bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
54 };
55
56 memory {
57 reg = <0x20000000 0x20000000>;
58 };
59
60 clocks {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 main_clock: clock@0 {
66 compatible = "atmel,osc", "fixed-clock";
67 clock-frequency = <12000000>;
68 };
69
70 slow_xtal {
71 clock-frequency = <32768>;
72 };
73
74 main_xtal {
75 clock-frequency = <12000000>;
76 };
77 };
78
79 ahb {
80 apb {
81 lcd_bus@f0000000 {
82 status = "okay";
83
84 lcd@f0000000 {
85 status = "okay";
86 };
87
88 lcdovl1@f0000140 {
89 status = "okay";
90 };
91
92 lcdovl2@f0000240 {
93 status = "okay";
94 };
95
96 lcdheo1@f0000340 {
97 status = "okay";
98 };
99 };
100
101 adc0: adc@fc034000 {
102 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
103 atmel,adc-vref = <3300>;
104 /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
105 status = "okay"; /* Enable ADC IIO support */
106 };
107
108 mmc0: mmc@f8000000 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
111 slot@1 {
112 reg = <1>;
113 bus-width = <4>;
114 cd-gpios = <&pioE 5 0>;
115 };
116 };
117
118 spi0: spi@f8010000 {
119 cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
120 status = "okay";
121 m25p80@0 {
122 compatible = "atmel,at25df321a";
123 spi-max-frequency = <50000000>;
124 reg = <0>;
125 };
126 };
127
128 i2c0: i2c@f8014000 {
129 status = "okay";
130 };
131
132 macb0: ethernet@f8020000 {
133 phy-mode = "rmii";
134 status = "okay";
135 };
136
137 mmc1: mmc@fc000000 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
140 status = "okay";
141 slot@0 {
142 reg = <0>;
143 bus-width = <4>;
144 cd-gpios = <&pioE 6 0>;
145 };
146 };
147
148 usart2: serial@fc008000 {
149 status = "okay";
150 };
151
152 usart3: serial@fc00c000 {
153 status = "okay";
154 };
155
156 usart4: serial@fc010000 {
157 status = "okay";
158 };
159
160 watchdog@fc068640 {
161 status = "okay";
162 };
163
164 pinctrl@fc06a000 {
165 board {
166 pinctrl_mmc0_cd: mmc0_cd {
167 atmel,pins =
168 <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
169 };
170 pinctrl_mmc1_cd: mmc1_cd {
171 atmel,pins =
172 <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
173 };
174 pinctrl_usba_vbus: usba_vbus {
175 atmel,pins =
176 <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
177 };
178 pinctrl_key_gpio: key_gpio_0 {
179 atmel,pins =
180 <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
181 };
182 };
183 };
184 };
185
186 usb0: gadget@00400000 {
187 atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_usba_vbus>;
190 status = "okay";
191 };
192
193 usb1: ohci@00500000 {
194 num-ports = <3>;
195 atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
196 &pioE 11 GPIO_ACTIVE_LOW
197 &pioE 12 GPIO_ACTIVE_LOW
198 >;
199 status = "okay";
200 };
201
202 usb2: ehci@00600000 {
203 status = "okay";
204 };
205
206 nand0: nand@80000000 {
207 nand-bus-width = <8>;
208 nand-ecc-mode = "hw";
209 nand-on-flash-bbt;
210 atmel,has-pmecc;
211 status = "okay";
212
213 at91bootstrap@0 {
214 label = "at91bootstrap";
215 reg = <0x0 0x40000>;
216 };
217
218 bootloader@40000 {
219 label = "bootloader";
220 reg = <0x40000 0x80000>;
221 };
222
223 bootloaderenv@c0000 {
224 label = "bootloader env";
225 reg = <0xc0000 0xc0000>;
226 };
227
228 dtb@180000 {
229 label = "device tree";
230 reg = <0x180000 0x80000>;
231 };
232
233 kernel@200000 {
234 label = "kernel";
235 reg = <0x200000 0x600000>;
236 };
237
238 rootfs@800000 {
239 label = "rootfs";
240 reg = <0x800000 0x0f800000>;
241 };
242 };
243 };
244
245 gpio_keys {
246 compatible = "gpio-keys";
247 #address-cells = <1>;
248 #size-cells = <0>;
249
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_key_gpio>;
252
253 pb_user1 {
254 label = "pb_user1";
255 gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
256 linux,code = <0x100>;
257 gpio-key,wakeup;
258 };
259 };
260};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index bb23c2d33cf8..d68b3c4862bc 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -345,10 +345,14 @@
345 }; 345 };
346 }; 346 };
347 347
348 ramc: ramc@ffffe200 { 348 ramc0: ramc@ffffe200 {
349 compatible = "atmel,at91sam9260-sdramc"; 349 compatible = "atmel,at91sam9260-sdramc";
350 reg = <0xffffe200 0x200 350 reg = <0xffffe200 0x200>;
351 0xffffe800 0x200>; 351 };
352
353 ramc1: ramc@ffffe800 {
354 compatible = "atmel,at91sam9260-sdramc";
355 reg = <0xffffe800 0x200>;
352 }; 356 };
353 357
354 pit: timer@fffffd30 { 358 pit: timer@fffffd30 {
@@ -834,6 +838,7 @@
834 compatible = "atmel,hsmci"; 838 compatible = "atmel,hsmci";
835 reg = <0xfff80000 0x600>; 839 reg = <0xfff80000 0x600>;
836 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 840 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
841 pinctrl-names = "default";
837 #address-cells = <1>; 842 #address-cells = <1>;
838 #size-cells = <0>; 843 #size-cells = <0>;
839 clocks = <&mci0_clk>; 844 clocks = <&mci0_clk>;
@@ -845,6 +850,7 @@
845 compatible = "atmel,hsmci"; 850 compatible = "atmel,hsmci";
846 reg = <0xfff84000 0x600>; 851 reg = <0xfff84000 0x600>;
847 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 852 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
853 pinctrl-names = "default";
848 #address-cells = <1>; 854 #address-cells = <1>;
849 #size-cells = <0>; 855 #size-cells = <0>;
850 clocks = <&mci1_clk>; 856 clocks = <&mci1_clk>;
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 4e0abbd9d655..a50ee587a7af 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -22,6 +22,10 @@
22 compatible = "atmel,at91sam9g20-i2c"; 22 compatible = "atmel,at91sam9g20-i2c";
23 }; 23 };
24 24
25 ssc0: ssc@fffbc000 {
26 compatible = "atmel,at91sam9rl-ssc";
27 };
28
25 adc0: adc@fffe0000 { 29 adc0: adc@fffe0000 {
26 atmel,adc-startup-time = <40>; 30 atmel,adc-startup-time = <40>;
27 }; 31 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 932a669156af..d3f65130a1f8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -96,8 +96,14 @@
96 96
97 ramc0: ramc@ffffe400 { 97 ramc0: ramc@ffffe400 {
98 compatible = "atmel,at91sam9g45-ddramc"; 98 compatible = "atmel,at91sam9g45-ddramc";
99 reg = <0xffffe400 0x200 99 reg = <0xffffe400 0x200>;
100 0xffffe600 0x200>; 100 clocks = <&ddrck>;
101 clock-names = "ddrck";
102 };
103
104 ramc1: ramc@ffffe600 {
105 compatible = "atmel,at91sam9g45-ddramc";
106 reg = <0xffffe600 0x200>;
101 clocks = <&ddrck>; 107 clocks = <&ddrck>;
102 clock-names = "ddrck"; 108 clock-names = "ddrck";
103 }; 109 };
@@ -159,7 +165,7 @@
159 compatible = "atmel,at91rm9200-clk-master"; 165 compatible = "atmel,at91rm9200-clk-master";
160 #clock-cells = <0>; 166 #clock-cells = <0>;
161 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 167 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
162 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>; 168 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
163 atmel,clk-output-range = <0 133333333>; 169 atmel,clk-output-range = <0 133333333>;
164 atmel,clk-divisors = <1 2 4 3>; 170 atmel,clk-divisors = <1 2 4 3>;
165 }; 171 };
@@ -175,7 +181,7 @@
175 #address-cells = <1>; 181 #address-cells = <1>;
176 #size-cells = <0>; 182 #size-cells = <0>;
177 interrupt-parent = <&pmc>; 183 interrupt-parent = <&pmc>;
178 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>; 184 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
179 185
180 prog0: prog0 { 186 prog0: prog0 {
181 #clock-cells = <0>; 187 #clock-cells = <0>;
@@ -1159,6 +1165,39 @@
1159 atmel,can-isoc; 1165 atmel,can-isoc;
1160 }; 1166 };
1161 }; 1167 };
1168
1169 sckc@fffffd50 {
1170 compatible = "atmel,at91sam9x5-sckc";
1171 reg = <0xfffffd50 0x4>;
1172
1173 slow_osc: slow_osc {
1174 compatible = "atmel,at91sam9x5-clk-slow-osc";
1175 #clock-cells = <0>;
1176 atmel,startup-time-usec = <1200000>;
1177 clocks = <&slow_xtal>;
1178 };
1179
1180 slow_rc_osc: slow_rc_osc {
1181 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1182 #clock-cells = <0>;
1183 atmel,startup-time-usec = <75>;
1184 clock-frequency = <32768>;
1185 clock-accuracy = <50000000>;
1186 };
1187
1188 clk32k: slck {
1189 compatible = "atmel,at91sam9x5-clk-slow";
1190 #clock-cells = <0>;
1191 clocks = <&slow_rc_osc &slow_osc>;
1192 };
1193 };
1194
1195 rtc@fffffdb0 {
1196 compatible = "atmel,at91rm9200-rtc";
1197 reg = <0xfffffdb0 0x30>;
1198 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1199 status = "disabled";
1200 };
1162 }; 1201 };
1163 1202
1164 fb0: fb@0x00500000 { 1203 fb0: fb@0x00500000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 96ccc7de4f0a..d8dd22651090 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -160,6 +160,10 @@
160 pinctrl-names = "default"; 160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_pwm_leds>; 161 pinctrl-0 = <&pinctrl_pwm_leds>;
162 }; 162 };
163
164 rtc@fffffdb0 {
165 status = "okay";
166 };
163 }; 167 };
164 168
165 fb0: fb@0x00500000 { 169 fb0: fb@0x00500000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 2bfac310dbec..68eb9aded164 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -87,6 +87,8 @@
87 ramc0: ramc@ffffe800 { 87 ramc0: ramc@ffffe800 {
88 compatible = "atmel,at91sam9g45-ddramc"; 88 compatible = "atmel,at91sam9g45-ddramc";
89 reg = <0xffffe800 0x200>; 89 reg = <0xffffe800 0x200>;
90 clocks = <&ddrck>;
91 clock-names = "ddrck";
90 }; 92 };
91 93
92 pmc: pmc@fffffc00 { 94 pmc: pmc@fffffc00 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 83d723711ae1..13bb24ea971a 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -136,6 +136,8 @@
136 }; 136 };
137 137
138 usb0: ohci@00500000 { 138 usb0: ohci@00500000 {
139 num-ports = <1>;
140 atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>;
139 status = "okay"; 141 status = "okay";
140 }; 142 };
141 }; 143 };
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index ab56c8b81dfa..f0b4352650ed 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -204,7 +204,7 @@
204 }; 204 };
205 205
206 ssc0: ssc@fffc0000 { 206 ssc0: ssc@fffc0000 {
207 compatible = "atmel,at91rm9200-ssc"; 207 compatible = "atmel,at91sam9rl-ssc";
208 reg = <0xfffc0000 0x4000>; 208 reg = <0xfffc0000 0x4000>;
209 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 209 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
210 pinctrl-names = "default"; 210 pinctrl-names = "default";
@@ -213,7 +213,7 @@
213 }; 213 };
214 214
215 ssc1: ssc@fffc4000 { 215 ssc1: ssc@fffc4000 {
216 compatible = "atmel,at91rm9200-ssc"; 216 compatible = "atmel,at91sam9rl-ssc";
217 reg = <0xfffc4000 0x4000>; 217 reg = <0xfffc4000 0x4000>;
218 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 218 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
219 pinctrl-names = "default"; 219 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e1a5c70b885c..726274f7959b 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -95,6 +95,8 @@
95 ramc0: ramc@ffffe800 { 95 ramc0: ramc@ffffe800 {
96 compatible = "atmel,at91sam9g45-ddramc"; 96 compatible = "atmel,at91sam9g45-ddramc";
97 reg = <0xffffe800 0x200>; 97 reg = <0xffffe800 0x200>;
98 clocks = <&ddrck>;
99 clock-names = "ddrck";
98 }; 100 };
99 101
100 pmc: pmc@fffffc00 { 102 pmc: pmc@fffffc00 {
@@ -966,7 +968,7 @@
966 adc0: adc@f804c000 { 968 adc0: adc@f804c000 {
967 #address-cells = <1>; 969 #address-cells = <1>;
968 #size-cells = <0>; 970 #size-cells = <0>;
969 compatible = "atmel,at91sam9260-adc"; 971 compatible = "atmel,at91sam9x5-adc";
970 reg = <0xf804c000 0x100>; 972 reg = <0xf804c000 0x100>;
971 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; 973 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
972 clocks = <&adc_clk>, 974 clocks = <&adc_clk>,
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 2a3b1c1313a0..58a0d60b95f1 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -23,7 +23,7 @@
23 23
24&gpio { 24&gpio {
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&gpioout &alt0 &alt3>; 26 pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
27 27
28 gpioout: gpioout { 28 gpioout: gpioout {
29 brcm,pins = <6>; 29 brcm,pins = <6>;
@@ -39,6 +39,12 @@
39 brcm,pins = <48 49 50 51 52 53>; 39 brcm,pins = <48 49 50 51 52 53>;
40 brcm,function = <7>; /* alt3 */ 40 brcm,function = <7>; /* alt3 */
41 }; 41 };
42
43 /* I2S interface */
44 alt2: alt2 {
45 brcm,pins = <28 29 30 31>;
46 brcm,function = <6>; /* alt2 */
47 };
42}; 48};
43 49
44&i2c0 { 50&i2c0 {
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index b8473c43e888..3342cb1407bc 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -99,6 +99,7 @@
99 dmas = <&dma 2>, 99 dmas = <&dma 2>,
100 <&dma 3>; 100 <&dma 3>;
101 dma-names = "tx", "rx"; 101 dma-names = "tx", "rx";
102 status = "disabled";
102 }; 103 };
103 104
104 spi: spi@7e204000 { 105 spi: spi@7e204000 {
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
new file mode 100644
index 000000000000..f3bb2dd6269e
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -0,0 +1,134 @@
1/*
2 * Broadcom BCM63138 DSL SoCs Device Tree
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7
8#include "skeleton.dtsi"
9
10/ {
11 compatible = "brcm,bcm63138";
12 model = "Broadcom BCM63138 DSL SoC";
13 interrupt-parent = <&gic>;
14
15 aliases {
16 uart0 = &serial0;
17 uart1 = &serial1;
18 };
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
28 reg = <0>;
29 };
30
31 cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
35 reg = <1>;
36 };
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 arm_timer_clk: arm_timer_clk {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <500000000>;
47 };
48
49 periph_clk: periph_clk {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
53 clock-output-names = "periph";
54 };
55 };
56
57 /* ARM bus */
58 axi@80000000 {
59 compatible = "simple-bus";
60 ranges = <0 0x80000000 0x784000>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63
64 L2: cache-controller@1d000 {
65 compatible = "arm,pl310-cache";
66 reg = <0x1d000 0x1000>;
67 cache-unified;
68 cache-level = <2>;
69 cache-sets = <16>;
70 cache-size = <0x80000>;
71 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
72 };
73
74 scu: scu@1e000 {
75 compatible = "arm,cortex-a9-scu";
76 reg = <0x1e000 0x100>;
77 };
78
79 gic: interrupt-controller@1e100 {
80 compatible = "arm,cortex-a9-gic";
81 reg = <0x1f000 0x1000
82 0x1e100 0x100>;
83 #interrupt-cells = <3>;
84 #address-cells = <0>;
85 interrupt-controller;
86 };
87
88 global_timer: timer@1e200 {
89 compatible = "arm,cortex-a9-global-timer";
90 reg = <0x1e200 0x20>;
91 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&arm_timer_clk>;
93 };
94
95 local_timer: local-timer@1e600 {
96 compatible = "arm,cortex-a9-twd-timer";
97 reg = <0x1e600 0x20>;
98 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&arm_timer_clk>;
100 };
101
102 twd_watchdog: watchdog@1e620 {
103 compatible = "arm,cortex-a9-twd-wdt";
104 reg = <0x1e620 0x20>;
105 interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
106 };
107 };
108
109 /* Legacy UBUS base */
110 ubus@fffe8000 {
111 compatible = "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0 0xfffe8000 0x8100>;
115
116 serial0: serial@600 {
117 compatible = "brcm,bcm6345-uart";
118 reg = <0x600 0x1b>;
119 interrupts = <GIC_SPI 32 0>;
120 clocks = <&periph_clk>;
121 clock-names = "periph";
122 status = "disabled";
123 };
124
125 serial1: serial@620 {
126 compatible = "brcm,bcm6345-uart";
127 reg = <0x620 0x1b>;
128 interrupts = <GIC_SPI 33 0>;
129 clocks = <&periph_clk>;
130 clock-names = "periph";
131 status = "disabled";
132 };
133 };
134};
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
new file mode 100644
index 000000000000..69c93395ecd2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -0,0 +1,30 @@
1/*
2 * Broadcom BCM63138 Reference Board DTS
3 */
4
5/dts-v1/;
6
7#include "bcm63138.dtsi"
8
9/ {
10 compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
11 model = "Broadcom BCM963138DVT";
12
13 chosen {
14 bootargs = "console=ttyS0,115200";
15 stdout-path = &serial0;
16 };
17
18 memory {
19 reg = <0x0 0x08000000>;
20 };
21
22};
23
24&serial0 {
25 status = "okay";
26};
27
28&serial1 {
29 status = "okay";
30};
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index a357ce02a64e..ea1f99b8eed6 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -45,3 +45,7 @@
45&uart0 { 45&uart0 {
46 status = "okay"; 46 status = "okay";
47}; 47};
48
49&eth0 {
50 status = "okay";
51};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 400c40fceccc..891d56b03922 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -114,6 +114,23 @@
114 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
115 }; 115 };
116 116
117 eth0: ethernet@b90000 {
118 compatible = "marvell,pxa168-eth";
119 reg = <0xb90000 0x10000>;
120 clocks = <&chip CLKID_GETH0>;
121 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
122 /* set by bootloader */
123 local-mac-address = [00 00 00 00 00 00];
124 #address-cells = <1>;
125 #size-cells = <0>;
126 phy-handle = <&ethphy0>;
127 status = "disabled";
128
129 ethphy0: ethernet-phy@0 {
130 reg = <0>;
131 };
132 };
133
117 cpu-ctrl@dd0000 { 134 cpu-ctrl@dd0000 {
118 compatible = "marvell,berlin-cpu-ctrl"; 135 compatible = "marvell,berlin-cpu-ctrl";
119 reg = <0xdd0000 0x10000>; 136 reg = <0xdd0000 0x10000>;
diff --git a/arch/arm/boot/dts/cros-adc-thermistors.dtsi b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
new file mode 100644
index 000000000000..acd4fe1833f2
--- /dev/null
+++ b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
@@ -0,0 +1,44 @@
1/*
2 * Thermistor dts fragment for devices that use Thermistors as
3 * children of the IIO based ADC.
4 *
5 * Currently, used by Exynos5420 based Peach PIT and
6 * Exynos5800 based Peach PI.
7 *
8 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15&adc {
16 ncp15wb473@3 {
17 compatible = "murata,ncp15wb473";
18 pullup-uv = <1800000>;
19 pullup-ohm = <47000>;
20 pulldown-ohm = <0>;
21 io-channels = <&adc 3>;
22 };
23 ncp15wb473@4 {
24 compatible = "murata,ncp15wb473";
25 pullup-uv = <1800000>;
26 pullup-ohm = <47000>;
27 pulldown-ohm = <0>;
28 io-channels = <&adc 4>;
29 };
30 ncp15wb473@5 {
31 compatible = "murata,ncp15wb473";
32 pullup-uv = <1800000>;
33 pullup-ohm = <47000>;
34 pulldown-ohm = <0>;
35 io-channels = <&adc 5>;
36 };
37 ncp15wb473@6 {
38 compatible = "murata,ncp15wb473";
39 pullup-uv = <1800000>;
40 pullup-ohm = <47000>;
41 pulldown-ohm = <0>;
42 io-channels = <&adc 6>;
43 };
44};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 1e11e5a5f723..4f935ad9f27b 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -17,6 +17,18 @@
17 soc { 17 soc {
18 pmx_core: pinmux@1c14120 { 18 pmx_core: pinmux@1c14120 {
19 status = "okay"; 19 status = "okay";
20
21 mcasp0_pins: pinmux_mcasp0_pins {
22 pinctrl-single,bits = <
23 /*
24 * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
25 * AFSR, AMUTE
26 */
27 0x00 0x11111111 0xffffffff
28 /* AXR11, AXR12 */
29 0x04 0x00011000 0x000ff000
30 >;
31 };
20 }; 32 };
21 serial0: serial@1c42000 { 33 serial0: serial@1c42000 {
22 status = "okay"; 34 status = "okay";
@@ -39,6 +51,20 @@
39 tps: tps@48 { 51 tps: tps@48 {
40 reg = <0x48>; 52 reg = <0x48>;
41 }; 53 };
54 tlv320aic3106: tlv320aic3106@18 {
55 #sound-dai-cells = <0>;
56 compatible = "ti,tlv320aic3106";
57 reg = <0x18>;
58 status = "okay";
59
60 /* Regulators */
61 IOVDD-supply = <&vdcdc2_reg>;
62 /* Derived from VBAT: Baseboard 3.3V / 1.8V */
63 AVDD-supply = <&vbat>;
64 DRVDD-supply = <&vbat>;
65 DVDD-supply = <&vbat>;
66 };
67
42 }; 68 };
43 wdt: wdt@1c21000 { 69 wdt: wdt@1c21000 {
44 status = "okay"; 70 status = "okay";
@@ -117,6 +143,33 @@
117 regulator-max-microvolt = <5000000>; 143 regulator-max-microvolt = <5000000>;
118 regulator-boot-on; 144 regulator-boot-on;
119 }; 145 };
146
147 sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,name = "DA850/OMAP-L138 EVM";
150 simple-audio-card,widgets =
151 "Line", "Line In",
152 "Line", "Line Out";
153 simple-audio-card,routing =
154 "LINE1L", "Line In",
155 "LINE1R", "Line In",
156 "Line Out", "LLOUT",
157 "Line Out", "RLOUT";
158 simple-audio-card,format = "dsp_b";
159 simple-audio-card,bitclock-master = <&link0_codec>;
160 simple-audio-card,frame-master = <&link0_codec>;
161 simple-audio-card,bitclock-inversion;
162
163 simple-audio-card,cpu {
164 sound-dai = <&mcasp0>;
165 system-clock-frequency = <24576000>;
166 };
167
168 link0_codec: simple-audio-card,codec {
169 sound-dai = <&tlv320aic3106>;
170 system-clock-frequency = <24576000>;
171 };
172 };
120}; 173};
121 174
122/include/ "tps6507x.dtsi" 175/include/ "tps6507x.dtsi"
@@ -170,3 +223,22 @@
170 }; 223 };
171 }; 224 };
172}; 225};
226
227&mcasp0 {
228 #sound-dai-cells = <0>;
229 status = "okay";
230 pinctrl-names = "default";
231 pinctrl-0 = <&mcasp0_pins>;
232
233 op-mode = <0>; /* MCASP_IIS_MODE */
234 tdm-slots = <2>;
235 /* 4 serializer */
236 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
237 0 0 0 0
238 0 0 0 0
239 0 0 0 1
240 2 0 0 0
241 >;
242 tx-num-evt = <32>;
243 rx-num-evt = <32>;
244};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index b695548dbb4e..0bd98cd00816 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -150,6 +150,12 @@
150 }; 150 };
151 151
152 }; 152 };
153 edma0: edma@01c00000 {
154 compatible = "ti,edma3";
155 reg = <0x0 0x10000>;
156 interrupts = <11 13 12>;
157 #dma-cells = <1>;
158 };
153 serial0: serial@1c42000 { 159 serial0: serial@1c42000 {
154 compatible = "ns16550a"; 160 compatible = "ns16550a";
155 reg = <0x42000 0x100>; 161 reg = <0x42000 0x100>;
@@ -270,6 +276,19 @@
270 ti,davinci-gpio-unbanked = <0>; 276 ti,davinci-gpio-unbanked = <0>;
271 status = "disabled"; 277 status = "disabled";
272 }; 278 };
279
280 mcasp0: mcasp@01d00000 {
281 compatible = "ti,da830-mcasp-audio";
282 reg = <0x100000 0x2000>,
283 <0x102000 0x400000>;
284 reg-names = "mpu", "dat";
285 interrupts = <54>;
286 interrupt-names = "common";
287 status = "disabled";
288 dmas = <&edma0 1>,
289 <&edma0 0>;
290 dma-names = "tx", "rx";
291 };
273 }; 292 };
274 nand_cs3@62000000 { 293 nand_cs3@62000000 {
275 compatible = "ti,davinci-nand"; 294 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index b40cdadb1f87..c6ce6258434f 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -323,6 +323,8 @@
323 status = "okay"; 323 status = "okay";
324 pinctrl-names = "default"; 324 pinctrl-names = "default";
325 pinctrl-0 = <&uart1_pins>; 325 pinctrl-0 = <&uart1_pins>;
326 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
327 <&dra7_pmx_core 0x3e0>;
326}; 328};
327 329
328&uart2 { 330&uart2 {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d678152db4cb..9cc98436a982 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -89,6 +89,7 @@
89 prm: prm@4ae06000 { 89 prm: prm@4ae06000 {
90 compatible = "ti,dra7-prm"; 90 compatible = "ti,dra7-prm";
91 reg = <0x4ae06000 0x3000>; 91 reg = <0x4ae06000 0x3000>;
92 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
92 93
93 prm_clocks: clocks { 94 prm_clocks: clocks {
94 #address-cells = <1>; 95 #address-cells = <1>;
@@ -217,10 +218,12 @@
217 }; 218 };
218 219
219 dra7_pmx_core: pinmux@4a003400 { 220 dra7_pmx_core: pinmux@4a003400 {
220 compatible = "pinctrl-single"; 221 compatible = "ti,dra7-padconf", "pinctrl-single";
221 reg = <0x4a003400 0x0464>; 222 reg = <0x4a003400 0x0464>;
222 #address-cells = <1>; 223 #address-cells = <1>;
223 #size-cells = <0>; 224 #size-cells = <0>;
225 #interrupt-cells = <1>;
226 interrupt-controller;
224 pinctrl-single,register-width = <32>; 227 pinctrl-single,register-width = <32>;
225 pinctrl-single,function-mask = <0x3fffffff>; 228 pinctrl-single,function-mask = <0x3fffffff>;
226 }; 229 };
@@ -328,7 +331,7 @@
328 uart1: serial@4806a000 { 331 uart1: serial@4806a000 {
329 compatible = "ti,omap4-uart"; 332 compatible = "ti,omap4-uart";
330 reg = <0x4806a000 0x100>; 333 reg = <0x4806a000 0x100>;
331 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 334 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
332 ti,hwmods = "uart1"; 335 ti,hwmods = "uart1";
333 clock-frequency = <48000000>; 336 clock-frequency = <48000000>;
334 status = "disabled"; 337 status = "disabled";
@@ -337,7 +340,7 @@
337 uart2: serial@4806c000 { 340 uart2: serial@4806c000 {
338 compatible = "ti,omap4-uart"; 341 compatible = "ti,omap4-uart";
339 reg = <0x4806c000 0x100>; 342 reg = <0x4806c000 0x100>;
340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 343 interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
341 ti,hwmods = "uart2"; 344 ti,hwmods = "uart2";
342 clock-frequency = <48000000>; 345 clock-frequency = <48000000>;
343 status = "disabled"; 346 status = "disabled";
@@ -346,7 +349,7 @@
346 uart3: serial@48020000 { 349 uart3: serial@48020000 {
347 compatible = "ti,omap4-uart"; 350 compatible = "ti,omap4-uart";
348 reg = <0x48020000 0x100>; 351 reg = <0x48020000 0x100>;
349 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
350 ti,hwmods = "uart3"; 353 ti,hwmods = "uart3";
351 clock-frequency = <48000000>; 354 clock-frequency = <48000000>;
352 status = "disabled"; 355 status = "disabled";
@@ -355,7 +358,7 @@
355 uart4: serial@4806e000 { 358 uart4: serial@4806e000 {
356 compatible = "ti,omap4-uart"; 359 compatible = "ti,omap4-uart";
357 reg = <0x4806e000 0x100>; 360 reg = <0x4806e000 0x100>;
358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 361 interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "uart4"; 362 ti,hwmods = "uart4";
360 clock-frequency = <48000000>; 363 clock-frequency = <48000000>;
361 status = "disabled"; 364 status = "disabled";
@@ -364,7 +367,7 @@
364 uart5: serial@48066000 { 367 uart5: serial@48066000 {
365 compatible = "ti,omap4-uart"; 368 compatible = "ti,omap4-uart";
366 reg = <0x48066000 0x100>; 369 reg = <0x48066000 0x100>;
367 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 370 interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
368 ti,hwmods = "uart5"; 371 ti,hwmods = "uart5";
369 clock-frequency = <48000000>; 372 clock-frequency = <48000000>;
370 status = "disabled"; 373 status = "disabled";
@@ -373,7 +376,7 @@
373 uart6: serial@48068000 { 376 uart6: serial@48068000 {
374 compatible = "ti,omap4-uart"; 377 compatible = "ti,omap4-uart";
375 reg = <0x48068000 0x100>; 378 reg = <0x48068000 0x100>;
376 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 379 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
377 ti,hwmods = "uart6"; 380 ti,hwmods = "uart6";
378 clock-frequency = <48000000>; 381 clock-frequency = <48000000>;
379 status = "disabled"; 382 status = "disabled";
@@ -382,7 +385,7 @@
382 uart7: serial@48420000 { 385 uart7: serial@48420000 {
383 compatible = "ti,omap4-uart"; 386 compatible = "ti,omap4-uart";
384 reg = <0x48420000 0x100>; 387 reg = <0x48420000 0x100>;
385 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 388 interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
386 ti,hwmods = "uart7"; 389 ti,hwmods = "uart7";
387 clock-frequency = <48000000>; 390 clock-frequency = <48000000>;
388 status = "disabled"; 391 status = "disabled";
@@ -391,7 +394,7 @@
391 uart8: serial@48422000 { 394 uart8: serial@48422000 {
392 compatible = "ti,omap4-uart"; 395 compatible = "ti,omap4-uart";
393 reg = <0x48422000 0x100>; 396 reg = <0x48422000 0x100>;
394 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
395 ti,hwmods = "uart8"; 398 ti,hwmods = "uart8";
396 clock-frequency = <48000000>; 399 clock-frequency = <48000000>;
397 status = "disabled"; 400 status = "disabled";
@@ -400,7 +403,7 @@
400 uart9: serial@48424000 { 403 uart9: serial@48424000 {
401 compatible = "ti,omap4-uart"; 404 compatible = "ti,omap4-uart";
402 reg = <0x48424000 0x100>; 405 reg = <0x48424000 0x100>;
403 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 406 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
404 ti,hwmods = "uart9"; 407 ti,hwmods = "uart9";
405 clock-frequency = <48000000>; 408 clock-frequency = <48000000>;
406 status = "disabled"; 409 status = "disabled";
@@ -409,7 +412,7 @@
409 uart10: serial@4ae2b000 { 412 uart10: serial@4ae2b000 {
410 compatible = "ti,omap4-uart"; 413 compatible = "ti,omap4-uart";
411 reg = <0x4ae2b000 0x100>; 414 reg = <0x4ae2b000 0x100>;
412 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 415 interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
413 ti,hwmods = "uart10"; 416 ti,hwmods = "uart10";
414 clock-frequency = <48000000>; 417 clock-frequency = <48000000>;
415 status = "disabled"; 418 status = "disabled";
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 514702348818..41074288adfa 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -19,6 +19,126 @@
19 }; 19 };
20}; 20};
21 21
22&dra7_pmx_core {
23 i2c1_pins: pinmux_i2c1_pins {
24 pinctrl-single,pins = <
25 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
26 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
27 >;
28 };
29};
30
31&i2c1 {
32 status = "okay";
33 pinctrl-names = "default";
34 pinctrl-0 = <&i2c1_pins>;
35 clock-frequency = <400000>;
36
37 tps65917: tps65917@58 {
38 compatible = "ti,tps65917";
39 reg = <0x58>;
40
41 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
42 interrupt-parent = <&gic>;
43 interrupt-controller;
44 #interrupt-cells = <2>;
45
46 ti,system-power-controller;
47
48 tps65917_pmic {
49 compatible = "ti,tps65917-pmic";
50
51 regulators {
52 smps1_reg: smps1 {
53 /* VDD_MPU */
54 regulator-name = "smps1";
55 regulator-min-microvolt = <850000>;
56 regulator-max-microvolt = <1250000>;
57 regulator-always-on;
58 regulator-boot-on;
59 };
60
61 smps2_reg: smps2 {
62 /* VDD_CORE */
63 regulator-name = "smps2";
64 regulator-min-microvolt = <850000>;
65 regulator-max-microvolt = <1030000>;
66 regulator-boot-on;
67 regulator-always-on;
68 };
69
70 smps3_reg: smps3 {
71 /* VDD_GPU IVA DSPEVE */
72 regulator-name = "smps3";
73 regulator-min-microvolt = <850000>;
74 regulator-max-microvolt = <1250000>;
75 regulator-boot-on;
76 regulator-always-on;
77 };
78
79 smps4_reg: smps4 {
80 /* VDDS1V8 */
81 regulator-name = "smps4";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
84 regulator-always-on;
85 regulator-boot-on;
86 };
87
88 smps5_reg: smps5 {
89 /* VDD_DDR */
90 regulator-name = "smps5";
91 regulator-min-microvolt = <1350000>;
92 regulator-max-microvolt = <1350000>;
93 regulator-boot-on;
94 regulator-always-on;
95 };
96
97 ldo1_reg: ldo1 {
98 /* LDO1_OUT --> SDIO */
99 regulator-name = "ldo1";
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <3300000>;
102 regulator-boot-on;
103 };
104
105 ldo2_reg: ldo2 {
106 /* LDO2_OUT --> TP1017 (UNUSED) */
107 regulator-name = "ldo2";
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <3300000>;
110 };
111
112 ldo3_reg: ldo3 {
113 /* VDDA_1V8_PHY */
114 regulator-name = "ldo3";
115 regulator-min-microvolt = <1800000>;
116 regulator-max-microvolt = <1800000>;
117 regulator-boot-on;
118 regulator-always-on;
119 };
120
121 ldo5_reg: ldo5 {
122 /* VDDA_1V8_PLL */
123 regulator-name = "ldo5";
124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <1800000>;
126 regulator-always-on;
127 regulator-boot-on;
128 };
129
130 ldo4_reg: ldo4 {
131 /* VDDA_3V_USB: VDDA_USBHS33 */
132 regulator-name = "ldo4";
133 regulator-min-microvolt = <3300000>;
134 regulator-max-microvolt = <3300000>;
135 regulator-boot-on;
136 };
137 };
138 };
139 };
140};
141
22&uart1 { 142&uart1 {
23 status = "okay"; 143 status = "okay";
24}; 144};
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index f1ec22f6ebf4..e5a3d23a3df1 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -22,4 +22,9 @@
22 reg = <0>; 22 reg = <0>;
23 }; 23 };
24 }; 24 };
25
26 pmu {
27 compatible = "arm,cortex-a15-pmu";
28 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
29 };
25}; 30};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index a4e8bb9f95c0..3be544c4891f 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -38,4 +38,10 @@
38 reg = <1>; 38 reg = <1>;
39 }; 39 };
40 }; 40 };
41
42 pmu {
43 compatible = "arm,cortex-a15-pmu";
44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
46 };
41}; 47};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index adadaf97ac01..c697ff01ae8d 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -54,17 +54,13 @@
54 status = "okay"; 54 status = "okay";
55 55
56 num-slots = <1>; 56 num-slots = <1>;
57 supports-highspeed;
58 broken-cd; 57 broken-cd;
59 card-detect-delay = <200>; 58 card-detect-delay = <200>;
60 samsung,dw-mshc-ciu-div = <3>; 59 samsung,dw-mshc-ciu-div = <3>;
61 samsung,dw-mshc-sdr-timing = <2 3>; 60 samsung,dw-mshc-sdr-timing = <2 3>;
62 samsung,dw-mshc-ddr-timing = <1 2>; 61 samsung,dw-mshc-ddr-timing = <1 2>;
63 62 bus-width = <8>;
64 slot@0 { 63 cap-mmc-highspeed;
65 reg = <0>;
66 bus-width = <8>;
67 };
68 }; 64 };
69 65
70 watchdog@10060000 { 66 watchdog@10060000 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index e925c9fbfb07..de15114fd07c 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -137,17 +137,13 @@
137 status = "okay"; 137 status = "okay";
138 138
139 num-slots = <1>; 139 num-slots = <1>;
140 supports-highspeed;
141 broken-cd; 140 broken-cd;
142 card-detect-delay = <200>; 141 card-detect-delay = <200>;
143 samsung,dw-mshc-ciu-div = <3>; 142 samsung,dw-mshc-ciu-div = <3>;
144 samsung,dw-mshc-sdr-timing = <2 3>; 143 samsung,dw-mshc-sdr-timing = <2 3>;
145 samsung,dw-mshc-ddr-timing = <1 2>; 144 samsung,dw-mshc-ddr-timing = <1 2>;
146 145 bus-width = <8>;
147 slot@0 { 146 cap-mmc-highspeed;
148 reg = <0>;
149 bus-width = <8>;
150 };
151 }; 147 };
152 148
153 codec@13400000 { 149 codec@13400000 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4561e0..5e066cd87f66 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -520,7 +520,6 @@
520 520
521 mmc@12550000 { 521 mmc@12550000 {
522 num-slots = <1>; 522 num-slots = <1>;
523 supports-highspeed;
524 broken-cd; 523 broken-cd;
525 non-removable; 524 non-removable;
526 card-detect-delay = <200>; 525 card-detect-delay = <200>;
@@ -532,11 +531,8 @@
532 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 531 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
533 pinctrl-names = "default"; 532 pinctrl-names = "default";
534 status = "okay"; 533 status = "okay";
535 534 bus-width = <8>;
536 slot@0 { 535 cap-mmc-highspeed;
537 reg = <0>;
538 bus-width = <8>;
539 };
540 }; 536 };
541 537
542 serial@13800000 { 538 serial@13800000 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f50d15b..3acd97eb6630 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -401,7 +401,6 @@
401 mmc_0: mmc@12200000 { 401 mmc_0: mmc@12200000 {
402 status = "okay"; 402 status = "okay";
403 num-slots = <1>; 403 num-slots = <1>;
404 supports-highspeed;
405 broken-cd; 404 broken-cd;
406 card-detect-delay = <200>; 405 card-detect-delay = <200>;
407 samsung,dw-mshc-ciu-div = <3>; 406 samsung,dw-mshc-ciu-div = <3>;
@@ -410,17 +409,13 @@
410 vmmc-supply = <&mmc_reg>; 409 vmmc-supply = <&mmc_reg>;
411 pinctrl-names = "default"; 410 pinctrl-names = "default";
412 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 411 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
413 412 bus-width = <8>;
414 slot@0 { 413 cap-mmc-highspeed;
415 reg = <0>;
416 bus-width = <8>;
417 };
418 }; 414 };
419 415
420 mmc_2: mmc@12220000 { 416 mmc_2: mmc@12220000 {
421 status = "okay"; 417 status = "okay";
422 num-slots = <1>; 418 num-slots = <1>;
423 supports-highspeed;
424 card-detect-delay = <200>; 419 card-detect-delay = <200>;
425 samsung,dw-mshc-ciu-div = <3>; 420 samsung,dw-mshc-ciu-div = <3>;
426 samsung,dw-mshc-sdr-timing = <2 3>; 421 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -428,12 +423,9 @@
428 vmmc-supply = <&mmc_reg>; 423 vmmc-supply = <&mmc_reg>;
429 pinctrl-names = "default"; 424 pinctrl-names = "default";
430 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 425 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
431 426 bus-width = <4>;
432 slot@0 { 427 disable-wp;
433 reg = <0>; 428 cap-sd-highspeed;
434 bus-width = <4>;
435 disable-wp;
436 };
437 }; 429 };
438 430
439 i2s0: i2s@03830000 { 431 i2s0: i2s@03830000 {
@@ -570,8 +562,4 @@
570 connect-gpios = <&gpd1 7 1>; 562 connect-gpios = <&gpd1 7 1>;
571 }; 563 };
572 }; 564 };
573
574 usb@12110000 {
575 usb-phy = <&usb2_phy>;
576 };
577}; 565};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
deleted file mode 100644
index e603e9c70142..000000000000
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * Common device tree include for all Exynos 5250 boards based off of Daisy.
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/ {
12 aliases {
13 };
14
15 memory {
16 reg = <0x40000000 0x80000000>;
17 };
18
19 chosen {
20 };
21
22 pinctrl@11400000 {
23 /*
24 * Disabled pullups since external part has its own pullups and
25 * double-pulling gets us out of spec in some cases.
26 */
27 i2c2_bus: i2c2-bus {
28 samsung,pin-pud = <0>;
29 };
30 };
31
32 i2c@12C60000 {
33 status = "okay";
34 samsung,i2c-sda-delay = <100>;
35 samsung,i2c-max-bus-freq = <378000>;
36 };
37
38 i2c@12C70000 {
39 status = "okay";
40 samsung,i2c-sda-delay = <100>;
41 samsung,i2c-max-bus-freq = <378000>;
42 };
43
44 i2c@12C80000 {
45 status = "okay";
46 samsung,i2c-sda-delay = <100>;
47 samsung,i2c-max-bus-freq = <66000>;
48
49 hdmiddc@50 {
50 compatible = "samsung,exynos4210-hdmiddc";
51 reg = <0x50>;
52 };
53 };
54
55 i2c@12C90000 {
56 status = "okay";
57 samsung,i2c-sda-delay = <100>;
58 samsung,i2c-max-bus-freq = <66000>;
59 };
60
61 i2c@12CA0000 {
62 status = "okay";
63 samsung,i2c-sda-delay = <100>;
64 samsung,i2c-max-bus-freq = <66000>;
65 };
66
67 i2c@12CB0000 {
68 status = "okay";
69 samsung,i2c-sda-delay = <100>;
70 samsung,i2c-max-bus-freq = <66000>;
71 };
72
73 i2c@12CD0000 {
74 status = "okay";
75 samsung,i2c-sda-delay = <100>;
76 samsung,i2c-max-bus-freq = <66000>;
77 };
78
79 i2c@12CE0000 {
80 status = "okay";
81 samsung,i2c-sda-delay = <100>;
82 samsung,i2c-max-bus-freq = <378000>;
83
84 hdmiphy: hdmiphy@38 {
85 compatible = "samsung,exynos4212-hdmiphy";
86 reg = <0x38>;
87 };
88 };
89
90 mmc@12200000 {
91 num-slots = <1>;
92 supports-highspeed;
93 broken-cd;
94 card-detect-delay = <200>;
95 samsung,dw-mshc-ciu-div = <3>;
96 samsung,dw-mshc-sdr-timing = <2 3>;
97 samsung,dw-mshc-ddr-timing = <1 2>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
100
101 slot@0 {
102 reg = <0>;
103 bus-width = <8>;
104 };
105 };
106
107 mmc@12220000 {
108 num-slots = <1>;
109 supports-highspeed;
110 card-detect-delay = <200>;
111 samsung,dw-mshc-ciu-div = <3>;
112 samsung,dw-mshc-sdr-timing = <2 3>;
113 samsung,dw-mshc-ddr-timing = <1 2>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
116
117 slot@0 {
118 reg = <0>;
119 bus-width = <4>;
120 wp-gpios = <&gpc2 1 0>;
121 };
122 };
123
124 mmc@12230000 {
125 num-slots = <1>;
126 supports-highspeed;
127 broken-cd;
128 card-detect-delay = <200>;
129 samsung,dw-mshc-ciu-div = <3>;
130 samsung,dw-mshc-sdr-timing = <2 3>;
131 samsung,dw-mshc-ddr-timing = <1 2>;
132 /* See board-specific dts files for pin setup */
133
134 slot@0 {
135 reg = <0>;
136 bus-width = <4>;
137 };
138 };
139
140 spi_1: spi@12d30000 {
141 status = "okay";
142 samsung,spi-src-clk = <0>;
143 num-cs = <1>;
144 };
145
146 hdmi {
147 hpd-gpio = <&gpx3 7 0>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&hdmi_hpd_irq>;
150 phy = <&hdmiphy>;
151 ddc = <&i2c_2>;
152 };
153
154 gpio-keys {
155 compatible = "gpio-keys";
156
157 power {
158 label = "Power";
159 gpios = <&gpx1 3 1>;
160 linux,code = <116>; /* KEY_POWER */
161 gpio-key,wakeup;
162 };
163 };
164};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35adae565..6a0f4c0ff763 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -284,7 +284,6 @@
284 mmc@12200000 { 284 mmc@12200000 {
285 status = "okay"; 285 status = "okay";
286 num-slots = <1>; 286 num-slots = <1>;
287 supports-highspeed;
288 broken-cd; 287 broken-cd;
289 card-detect-delay = <200>; 288 card-detect-delay = <200>;
290 samsung,dw-mshc-ciu-div = <3>; 289 samsung,dw-mshc-ciu-div = <3>;
@@ -292,29 +291,22 @@
292 samsung,dw-mshc-ddr-timing = <1 2>; 291 samsung,dw-mshc-ddr-timing = <1 2>;
293 pinctrl-names = "default"; 292 pinctrl-names = "default";
294 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 293 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
295 294 bus-width = <8>;
296 slot@0 { 295 cap-mmc-highspeed;
297 reg = <0>;
298 bus-width = <8>;
299 };
300 }; 296 };
301 297
302 mmc@12220000 { 298 mmc@12220000 {
303 status = "okay"; 299 status = "okay";
304 num-slots = <1>; 300 num-slots = <1>;
305 supports-highspeed;
306 card-detect-delay = <200>; 301 card-detect-delay = <200>;
307 samsung,dw-mshc-ciu-div = <3>; 302 samsung,dw-mshc-ciu-div = <3>;
308 samsung,dw-mshc-sdr-timing = <2 3>; 303 samsung,dw-mshc-sdr-timing = <2 3>;
309 samsung,dw-mshc-ddr-timing = <1 2>; 304 samsung,dw-mshc-ddr-timing = <1 2>;
310 pinctrl-names = "default"; 305 pinctrl-names = "default";
311 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 306 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
312 307 bus-width = <4>;
313 slot@0 { 308 disable-wp;
314 reg = <0>; 309 cap-sd-highspeed;
315 bus-width = <4>;
316 disable-wp;
317 };
318 }; 310 };
319 311
320 spi_1: spi@12d30000 { 312 spi_1: spi@12d30000 {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c4116541..e51fcef884a4 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
9*/ 9*/
10 10
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/gpio/gpio.h>
12#include "exynos5250.dtsi" 13#include "exynos5250.dtsi"
13#include "exynos5250-cros-common.dtsi"
14 14
15/ { 15/ {
16 model = "Google Snow"; 16 model = "Google Snow";
@@ -20,6 +20,13 @@
20 i2c104 = &i2c_104; 20 i2c104 = &i2c_104;
21 }; 21 };
22 22
23 memory {
24 reg = <0x40000000 0x80000000>;
25 };
26
27 chosen {
28 };
29
23 rtc@101E0000 { 30 rtc@101E0000 {
24 status = "okay"; 31 status = "okay";
25 }; 32 };
@@ -93,6 +100,13 @@
93 gpio-keys { 100 gpio-keys {
94 compatible = "gpio-keys"; 101 compatible = "gpio-keys";
95 102
103 power {
104 label = "Power";
105 gpios = <&gpx1 3 1>;
106 linux,code = <116>; /* KEY_POWER */
107 gpio-key,wakeup;
108 };
109
96 lid-switch { 110 lid-switch {
97 label = "Lid"; 111 label = "Lid";
98 gpios = <&gpx3 5 1>; 112 gpios = <&gpx3 5 1>;
@@ -181,7 +195,7 @@
181 dcdc3 { 195 dcdc3 {
182 ti,enable-ext-control; 196 ti,enable-ext-control;
183 }; 197 };
184 fet1 { 198 fet1: fet1 {
185 regulator-name = "vcd_led"; 199 regulator-name = "vcd_led";
186 ti,overcurrent-wait = <3>; 200 ti,overcurrent-wait = <3>;
187 }; 201 };
@@ -204,7 +218,7 @@
204 regulator-always-on; 218 regulator-always-on;
205 ti,overcurrent-wait = <3>; 219 ti,overcurrent-wait = <3>;
206 }; 220 };
207 fet6 { 221 fet6: fet6 {
208 regulator-name = "lcd_vdd"; 222 regulator-name = "lcd_vdd";
209 ti,overcurrent-wait = <3>; 223 ti,overcurrent-wait = <3>;
210 }; 224 };
@@ -226,26 +240,6 @@
226 }; 240 };
227 }; 241 };
228 242
229 mmc@12200000 {
230 status = "okay";
231 };
232
233 mmc@12220000 {
234 status = "okay";
235 };
236
237 /*
238 * On Snow we've got SIP WiFi and so can keep drive strengths low to
239 * reduce EMI.
240 */
241 mmc@12230000 {
242 status = "okay";
243 slot@0 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
246 };
247 };
248
249 i2c@12CD0000 { 243 i2c@12CD0000 {
250 max98095: codec@11 { 244 max98095: codec@11 {
251 compatible = "maxim,max98095"; 245 compatible = "maxim,max98095";
@@ -253,6 +247,15 @@
253 pinctrl-0 = <&max98095_en>; 247 pinctrl-0 = <&max98095_en>;
254 pinctrl-names = "default"; 248 pinctrl-names = "default";
255 }; 249 };
250
251 ptn3460: lvds-bridge@20 {
252 compatible = "nxp,ptn3460";
253 reg = <0x20>;
254 powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
255 reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
256 edid-emulation = <5>;
257 panel = <&panel>;
258 };
256 }; 259 };
257 260
258 i2s0: i2s@03830000 { 261 i2s0: i2s@03830000 {
@@ -294,17 +297,24 @@
294 }; 297 };
295 298
296 hdmi { 299 hdmi {
300 hpd-gpio = <&gpx3 7 0>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&hdmi_hpd_irq>;
303 phy = <&hdmiphy>;
304 ddc = <&i2c_2>;
297 hdmi-en-supply = <&tps65090_fet7>; 305 hdmi-en-supply = <&tps65090_fet7>;
298 vdd-supply = <&ldo8_reg>; 306 vdd-supply = <&ldo8_reg>;
299 vdd_osc-supply = <&ldo10_reg>; 307 vdd_osc-supply = <&ldo10_reg>;
300 vdd_pll-supply = <&ldo8_reg>; 308 vdd_pll-supply = <&ldo8_reg>;
301 }; 309 };
302 310
303 backlight { 311 backlight: backlight {
304 compatible = "pwm-backlight"; 312 compatible = "pwm-backlight";
305 pwms = <&pwm 0 1000000 0>; 313 pwms = <&pwm 0 1000000 0>;
306 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 314 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
307 default-brightness-level = <7>; 315 default-brightness-level = <7>;
316 enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
317 power-supply = <&fet1>;
308 pinctrl-0 = <&pwm0_out>; 318 pinctrl-0 = <&pwm0_out>;
309 pinctrl-names = "default"; 319 pinctrl-names = "default";
310 }; 320 };
@@ -314,6 +324,12 @@
314 samsung,invert-vclk; 324 samsung,invert-vclk;
315 }; 325 };
316 326
327 panel: panel {
328 compatible = "auo,b116xw03";
329 power-supply = <&fet6>;
330 backlight = <&backlight>;
331 };
332
317 dp-controller@145B0000 { 333 dp-controller@145B0000 {
318 status = "okay"; 334 status = "okay";
319 pinctrl-names = "default"; 335 pinctrl-names = "default";
@@ -325,26 +341,15 @@
325 samsung,link-rate = <0x0a>; 341 samsung,link-rate = <0x0a>;
326 samsung,lane-count = <2>; 342 samsung,lane-count = <2>;
327 samsung,hpd-gpio = <&gpx0 7 0>; 343 samsung,hpd-gpio = <&gpx0 7 0>;
328 344 bridge = <&ptn3460>;
329 display-timings {
330 native-mode = <&timing1>;
331
332 timing1: timing@1 {
333 clock-frequency = <70589280>;
334 hactive = <1366>;
335 vactive = <768>;
336 hfront-porch = <40>;
337 hback-porch = <40>;
338 hsync-len = <32>;
339 vback-porch = <10>;
340 vfront-porch = <12>;
341 vsync-len = <6>;
342 };
343 };
344 }; 345 };
345}; 346};
346 347
347&i2c_0 { 348&i2c_0 {
349 status = "okay";
350 samsung,i2c-sda-delay = <100>;
351 samsung,i2c-max-bus-freq = <378000>;
352
348 max77686@09 { 353 max77686@09 {
349 compatible = "maxim,max77686"; 354 compatible = "maxim,max77686";
350 interrupt-parent = <&gpx3>; 355 interrupt-parent = <&gpx3>;
@@ -491,6 +496,10 @@
491}; 496};
492 497
493&i2c_1 { 498&i2c_1 {
499 status = "okay";
500 samsung,i2c-sda-delay = <100>;
501 samsung,i2c-max-bus-freq = <378000>;
502
494 trackpad { 503 trackpad {
495 reg = <0x67>; 504 reg = <0x67>;
496 compatible = "cypress,cyapa"; 505 compatible = "cypress,cyapa";
@@ -500,6 +509,106 @@
500 }; 509 };
501}; 510};
502 511
512/*
513 * Disabled pullups since external part has its own pullups and
514 * double-pulling gets us out of spec in some cases.
515 */
516&i2c2_bus {
517 samsung,pin-pud = <0>;
518};
519
520&i2c_2 {
521 status = "okay";
522 samsung,i2c-sda-delay = <100>;
523 samsung,i2c-max-bus-freq = <66000>;
524
525 hdmiddc@50 {
526 compatible = "samsung,exynos4210-hdmiddc";
527 reg = <0x50>;
528 };
529};
530
531&i2c_3 {
532 status = "okay";
533 samsung,i2c-sda-delay = <100>;
534 samsung,i2c-max-bus-freq = <66000>;
535};
536
537&i2c_4 {
538 status = "okay";
539 samsung,i2c-sda-delay = <100>;
540 samsung,i2c-max-bus-freq = <66000>;
541};
542
543&i2c_5 {
544 status = "okay";
545 samsung,i2c-sda-delay = <100>;
546 samsung,i2c-max-bus-freq = <66000>;
547};
548
549&i2c_7 {
550 status = "okay";
551 samsung,i2c-sda-delay = <100>;
552 samsung,i2c-max-bus-freq = <66000>;
553};
554
555&i2c_8 {
556 status = "okay";
557 samsung,i2c-sda-delay = <100>;
558 samsung,i2c-max-bus-freq = <378000>;
559
560 hdmiphy: hdmiphy@38 {
561 compatible = "samsung,exynos4212-hdmiphy";
562 reg = <0x38>;
563 };
564};
565
566&mmc_0 {
567 status = "okay";
568 num-slots = <1>;
569 broken-cd;
570 card-detect-delay = <200>;
571 samsung,dw-mshc-ciu-div = <3>;
572 samsung,dw-mshc-sdr-timing = <2 3>;
573 samsung,dw-mshc-ddr-timing = <1 2>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
576 bus-width = <8>;
577 cap-mmc-highspeed;
578};
579
580&mmc_2 {
581 status = "okay";
582 num-slots = <1>;
583 card-detect-delay = <200>;
584 samsung,dw-mshc-ciu-div = <3>;
585 samsung,dw-mshc-sdr-timing = <2 3>;
586 samsung,dw-mshc-ddr-timing = <1 2>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
589 bus-width = <4>;
590 wp-gpios = <&gpc2 1 0>;
591 cap-sd-highspeed;
592};
593
594/*
595 * On Snow we've got SIP WiFi and so can keep drive strengths low to
596 * reduce EMI.
597 */
598&mmc_3 {
599 status = "okay";
600 num-slots = <1>;
601 broken-cd;
602 card-detect-delay = <200>;
603 samsung,dw-mshc-ciu-div = <3>;
604 samsung,dw-mshc-sdr-timing = <2 3>;
605 samsung,dw-mshc-ddr-timing = <1 2>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
608 bus-width = <4>;
609 cap-sd-highspeed;
610};
611
503&pinctrl_0 { 612&pinctrl_0 {
504 max77686_irq: max77686-irq { 613 max77686_irq: max77686-irq {
505 samsung,pins = "gpx3-2"; 614 samsung,pins = "gpx3-2";
@@ -509,4 +618,10 @@
509 }; 618 };
510}; 619};
511 620
621&spi_1 {
622 status = "okay";
623 samsung,spi-src-clk = <0>;
624 num-cs = <1>;
625};
626
512#include "cros-ec-keyboard.dtsi" 627#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1eff37bd..f21b9aa00fbb 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -603,21 +603,6 @@
603 }; 603 };
604 }; 604 };
605 605
606 usb2_phy: usbphy@12130000 {
607 compatible = "samsung,exynos5250-usb2phy";
608 reg = <0x12130000 0x100>;
609 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
610 clock-names = "ext_xtal", "usbhost";
611 #address-cells = <1>;
612 #size-cells = <1>;
613 ranges;
614
615 usbphy-sys {
616 reg = <0x10040704 0x8>,
617 <0x10050230 0x4>;
618 };
619 };
620
621 usb2_phy_gen: phy@12130000 { 606 usb2_phy_gen: phy@12130000 {
622 compatible = "samsung,exynos5250-usb2-phy"; 607 compatible = "samsung,exynos5250-usb2-phy";
623 reg = <0x12130000 0x100>; 608 reg = <0x12130000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 8c84ab27c19b..a803b605051b 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -69,7 +69,7 @@
69 num-slots = <1>; 69 num-slots = <1>;
70 broken-cd; 70 broken-cd;
71 bypass-smu; 71 bypass-smu;
72 supports-highspeed; 72 cap-mmc-highspeed;
73 supports-hs200-mode; /* 200 Mhz */ 73 supports-hs200-mode; /* 200 Mhz */
74 card-detect-delay = <200>; 74 card-detect-delay = <200>;
75 samsung,dw-mshc-ciu-div = <3>; 75 samsung,dw-mshc-ciu-div = <3>;
@@ -77,27 +77,19 @@
77 samsung,dw-mshc-ddr-timing = <0 2>; 77 samsung,dw-mshc-ddr-timing = <0 2>;
78 pinctrl-names = "default"; 78 pinctrl-names = "default";
79 pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; 79 pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
80 80 bus-width = <8>;
81 slot@0 {
82 reg = <0>;
83 bus-width = <8>;
84 };
85}; 81};
86 82
87&mmc_2 { 83&mmc_2 {
88 status = "okay"; 84 status = "okay";
89 num-slots = <1>; 85 num-slots = <1>;
90 supports-highspeed; 86 cap-sd-highspeed;
91 card-detect-delay = <200>; 87 card-detect-delay = <200>;
92 samsung,dw-mshc-ciu-div = <3>; 88 samsung,dw-mshc-ciu-div = <3>;
93 samsung,dw-mshc-sdr-timing = <2 3>; 89 samsung,dw-mshc-sdr-timing = <2 3>;
94 samsung,dw-mshc-ddr-timing = <1 2>; 90 samsung,dw-mshc-ddr-timing = <1 2>;
95 pinctrl-names = "default"; 91 pinctrl-names = "default";
96 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; 92 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
97 93 bus-width = <4>;
98 slot@0 { 94 disable-wp;
99 reg = <0>;
100 bus-width = <4>;
101 disable-wp;
102 };
103}; 95};
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 7275bbd6fc4b..be3e02530b42 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -40,33 +40,25 @@
40&mmc_0 { 40&mmc_0 {
41 status = "okay"; 41 status = "okay";
42 num-slots = <1>; 42 num-slots = <1>;
43 supports-highspeed; 43 cap-mmc-highspeed;
44 broken-cd; 44 broken-cd;
45 card-detect-delay = <200>; 45 card-detect-delay = <200>;
46 samsung,dw-mshc-ciu-div = <3>; 46 samsung,dw-mshc-ciu-div = <3>;
47 samsung,dw-mshc-sdr-timing = <2 3>; 47 samsung,dw-mshc-sdr-timing = <2 3>;
48 samsung,dw-mshc-ddr-timing = <1 2>; 48 samsung,dw-mshc-ddr-timing = <1 2>;
49 49 bus-width = <8>;
50 slot@0 {
51 reg = <0>;
52 bus-width = <8>;
53 };
54}; 50};
55 51
56&mmc_2 { 52&mmc_2 {
57 status = "okay"; 53 status = "okay";
58 num-slots = <1>; 54 num-slots = <1>;
59 supports-highspeed; 55 cap-sd-highspeed;
60 card-detect-delay = <200>; 56 card-detect-delay = <200>;
61 samsung,dw-mshc-ciu-div = <3>; 57 samsung,dw-mshc-ciu-div = <3>;
62 samsung,dw-mshc-sdr-timing = <2 3>; 58 samsung,dw-mshc-sdr-timing = <2 3>;
63 samsung,dw-mshc-ddr-timing = <1 2>; 59 samsung,dw-mshc-ddr-timing = <1 2>;
64 60 bus-width = <4>;
65 slot@0 { 61 disable-wp;
66 reg = <0>;
67 bus-width = <4>;
68 disable-wp;
69 };
70}; 62};
71 63
72&uart0 { 64&uart0 {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 434fd9d3e09d..4f2df61c1cfc 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -50,7 +50,6 @@
50 mmc@12200000 { 50 mmc@12200000 {
51 status = "okay"; 51 status = "okay";
52 broken-cd; 52 broken-cd;
53 supports-highspeed;
54 card-detect-delay = <200>; 53 card-detect-delay = <200>;
55 samsung,dw-mshc-ciu-div = <3>; 54 samsung,dw-mshc-ciu-div = <3>;
56 samsung,dw-mshc-sdr-timing = <0 4>; 55 samsung,dw-mshc-sdr-timing = <0 4>;
@@ -58,28 +57,22 @@
58 pinctrl-names = "default"; 57 pinctrl-names = "default";
59 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 58 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
60 vmmc-supply = <&ldo10_reg>; 59 vmmc-supply = <&ldo10_reg>;
61 60 bus-width = <8>;
62 slot@0 { 61 cap-mmc-highspeed;
63 reg = <0>;
64 bus-width = <8>;
65 };
66 }; 62 };
67 63
68 mmc@12220000 { 64 mmc@12220000 {
69 status = "okay"; 65 status = "okay";
70 supports-highspeed;
71 card-detect-delay = <200>; 66 card-detect-delay = <200>;
72 samsung,dw-mshc-ciu-div = <3>; 67 samsung,dw-mshc-ciu-div = <3>;
73 samsung,dw-mshc-sdr-timing = <2 3>; 68 samsung,dw-mshc-sdr-timing = <2 3>;
74 samsung,dw-mshc-ddr-timing = <1 2>; 69 samsung,dw-mshc-ddr-timing = <1 2>;
75 pinctrl-names = "default"; 70 pinctrl-names = "default";
76 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 71 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
77 vmmc-supply = <&ldo10_reg>; 72 vmmc-supply = <&ldo19_reg>;
78 73 vqmmc-supply = <&ldo13_reg>;
79 slot@0 { 74 bus-width = <4>;
80 reg = <0>; 75 cap-sd-highspeed;
81 bus-width = <4>;
82 };
83 }; 76 };
84 77
85 hsi2c_4: i2c@12CA0000 { 78 hsi2c_4: i2c@12CA0000 {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 228a6b1e0aa1..9a233828539c 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -11,6 +11,7 @@
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/input/input.h> 12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
14#include "exynos5420.dtsi" 15#include "exynos5420.dtsi"
15 16
16/ { 17/ {
@@ -30,11 +31,12 @@
30 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; 31 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
31 }; 32 };
32 33
33 backlight { 34 backlight: backlight {
34 compatible = "pwm-backlight"; 35 compatible = "pwm-backlight";
35 pwms = <&pwm 0 1000000 0>; 36 pwms = <&pwm 0 1000000 0>;
36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 37 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
37 default-brightness-level = <7>; 38 default-brightness-level = <7>;
39 power-supply = <&tps65090_fet1>;
38 pinctrl-0 = <&pwm0_out>; 40 pinctrl-0 = <&pwm0_out>;
39 pinctrl-names = "default"; 41 pinctrl-names = "default";
40 }; 42 };
@@ -100,6 +102,17 @@
100 regulator-boot-on; 102 regulator-boot-on;
101 regulator-always-on; 103 regulator-always-on;
102 }; 104 };
105
106 panel: panel {
107 compatible = "auo,b116xw03";
108 power-supply = <&tps65090_fet6>;
109 backlight = <&backlight>;
110 };
111};
112
113&adc {
114 status = "okay";
115 vdd-supply = <&ldo9_reg>;
103}; 116};
104 117
105&dp { 118&dp {
@@ -113,22 +126,7 @@
113 samsung,link-rate = <0x06>; 126 samsung,link-rate = <0x06>;
114 samsung,lane-count = <2>; 127 samsung,lane-count = <2>;
115 samsung,hpd-gpio = <&gpx2 6 0>; 128 samsung,hpd-gpio = <&gpx2 6 0>;
116 129 bridge = <&ps8625>;
117 display-timings {
118 native-mode = <&timing1>;
119
120 timing1: timing@1 {
121 clock-frequency = <70589280>;
122 hactive = <1366>;
123 vactive = <768>;
124 hfront-porch = <40>;
125 hback-porch = <40>;
126 hsync-len = <32>;
127 vback-porch = <10>;
128 vfront-porch = <12>;
129 vsync-len = <6>;
130 };
131 };
132}; 130};
133 131
134&fimd { 132&fimd {
@@ -142,10 +140,348 @@
142 pinctrl-names = "default"; 140 pinctrl-names = "default";
143 pinctrl-0 = <&hdmi_hpd_irq>; 141 pinctrl-0 = <&hdmi_hpd_irq>;
144 ddc = <&i2c_2>; 142 ddc = <&i2c_2>;
143
144 hdmi-en-supply = <&tps65090_fet7>;
145 vdd-supply = <&ldo8_reg>;
146 vdd_osc-supply = <&ldo10_reg>;
147 vdd_pll-supply = <&ldo8_reg>;
148};
149
150&hsi2c_4 {
151 status = "okay";
152 clock-frequency = <400000>;
153
154 max77802-pmic@9 {
155 compatible = "maxim,max77802";
156 interrupt-parent = <&gpx3>;
157 interrupts = <1 IRQ_TYPE_NONE>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
160 <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
161 wakeup-source;
162 reg = <0x9>;
163 #clock-cells = <1>;
164
165 inb1-supply = <&tps65090_dcdc2>;
166 inb2-supply = <&tps65090_dcdc1>;
167 inb3-supply = <&tps65090_dcdc2>;
168 inb4-supply = <&tps65090_dcdc2>;
169 inb5-supply = <&tps65090_dcdc1>;
170 inb6-supply = <&tps65090_dcdc2>;
171 inb7-supply = <&tps65090_dcdc1>;
172 inb8-supply = <&tps65090_dcdc1>;
173 inb9-supply = <&tps65090_dcdc1>;
174 inb10-supply = <&tps65090_dcdc1>;
175
176 inl1-supply = <&buck5_reg>;
177 inl2-supply = <&buck7_reg>;
178 inl3-supply = <&buck9_reg>;
179 inl4-supply = <&buck9_reg>;
180 inl5-supply = <&buck9_reg>;
181 inl6-supply = <&tps65090_dcdc2>;
182 inl7-supply = <&buck9_reg>;
183 inl9-supply = <&tps65090_dcdc2>;
184 inl10-supply = <&buck7_reg>;
185
186 regulators {
187 buck1_reg: BUCK1 {
188 regulator-name = "vdd_mif";
189 regulator-min-microvolt = <800000>;
190 regulator-max-microvolt = <1300000>;
191 regulator-always-on;
192 regulator-boot-on;
193 regulator-ramp-delay = <12500>;
194 };
195
196 buck2_reg: BUCK2 {
197 regulator-name = "vdd_arm";
198 regulator-min-microvolt = <800000>;
199 regulator-max-microvolt = <1500000>;
200 regulator-always-on;
201 regulator-boot-on;
202 regulator-ramp-delay = <12500>;
203 };
204
205 buck3_reg: BUCK3 {
206 regulator-name = "vdd_int";
207 regulator-min-microvolt = <800000>;
208 regulator-max-microvolt = <1400000>;
209 regulator-always-on;
210 regulator-boot-on;
211 regulator-ramp-delay = <12500>;
212 };
213
214 buck4_reg: BUCK4 {
215 regulator-name = "vdd_g3d";
216 regulator-min-microvolt = <700000>;
217 regulator-max-microvolt = <1400000>;
218 regulator-always-on;
219 regulator-boot-on;
220 regulator-ramp-delay = <12500>;
221 };
222
223 buck5_reg: BUCK5 {
224 regulator-name = "vdd_1v2";
225 regulator-min-microvolt = <1200000>;
226 regulator-max-microvolt = <1200000>;
227 regulator-always-on;
228 regulator-boot-on;
229 };
230
231 buck6_reg: BUCK6 {
232 regulator-name = "vdd_kfc";
233 regulator-min-microvolt = <800000>;
234 regulator-max-microvolt = <1500000>;
235 regulator-always-on;
236 regulator-boot-on;
237 regulator-ramp-delay = <12500>;
238 };
239
240 buck7_reg: BUCK7 {
241 regulator-name = "vdd_1v35";
242 regulator-min-microvolt = <1350000>;
243 regulator-max-microvolt = <1350000>;
244 regulator-always-on;
245 regulator-boot-on;
246 };
247
248 buck8_reg: BUCK8 {
249 regulator-name = "vdd_emmc";
250 regulator-min-microvolt = <2850000>;
251 regulator-max-microvolt = <2850000>;
252 regulator-always-on;
253 regulator-boot-on;
254 };
255
256 buck9_reg: BUCK9 {
257 regulator-name = "vdd_2v";
258 regulator-min-microvolt = <2000000>;
259 regulator-max-microvolt = <2000000>;
260 regulator-always-on;
261 regulator-boot-on;
262 };
263
264 buck10_reg: BUCK10 {
265 regulator-name = "vdd_1v8";
266 regulator-min-microvolt = <1800000>;
267 regulator-max-microvolt = <1800000>;
268 regulator-always-on;
269 regulator-boot-on;
270 };
271
272 ldo1_reg: LDO1 {
273 regulator-name = "vdd_1v0";
274 regulator-min-microvolt = <1000000>;
275 regulator-max-microvolt = <1000000>;
276 regulator-always-on;
277 };
278
279 ldo2_reg: LDO2 {
280 regulator-name = "vdd_1v2_2";
281 regulator-min-microvolt = <1200000>;
282 regulator-max-microvolt = <1200000>;
283 };
284
285 ldo3_reg: LDO3 {
286 regulator-name = "vdd_1v8_3";
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <1800000>;
289 regulator-always-on;
290 };
291
292 vqmmc_sdcard: ldo4_reg: LDO4 {
293 regulator-name = "vdd_sd";
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <2800000>;
296 regulator-always-on;
297 };
298
299 ldo5_reg: LDO5 {
300 regulator-name = "vdd_1v8_5";
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <1800000>;
303 regulator-always-on;
304 };
305
306 ldo6_reg: LDO6 {
307 regulator-name = "vdd_1v8_6";
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <1800000>;
310 regulator-always-on;
311 };
312
313 ldo7_reg: LDO7 {
314 regulator-name = "vdd_1v8_7";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <1800000>;
317 };
318
319 ldo8_reg: LDO8 {
320 regulator-name = "vdd_ldo8";
321 regulator-min-microvolt = <1000000>;
322 regulator-max-microvolt = <1000000>;
323 regulator-always-on;
324 };
325
326 ldo9_reg: LDO9 {
327 regulator-name = "vdd_ldo9";
328 regulator-min-microvolt = <1800000>;
329 regulator-max-microvolt = <1800000>;
330 regulator-always-on;
331 };
332
333 ldo10_reg: LDO10 {
334 regulator-name = "vdd_ldo10";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <1800000>;
337 regulator-always-on;
338 };
339
340 ldo11_reg: LDO11 {
341 regulator-name = "vdd_ldo11";
342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <1800000>;
344 regulator-always-on;
345 };
346
347 ldo12_reg: LDO12 {
348 regulator-name = "vdd_ldo12";
349 regulator-min-microvolt = <3000000>;
350 regulator-max-microvolt = <3000000>;
351 regulator-always-on;
352 };
353
354 ldo13_reg: LDO13 {
355 regulator-name = "vdd_ldo13";
356 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>;
358 regulator-always-on;
359 };
360
361 ldo14_reg: LDO14 {
362 regulator-name = "vdd_ldo14";
363 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>;
365 regulator-always-on;
366 };
367
368 ldo15_reg: LDO15 {
369 regulator-name = "vdd_ldo15";
370 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>;
372 regulator-always-on;
373 };
374
375 ldo17_reg: LDO17 {
376 regulator-name = "vdd_g3ds";
377 regulator-min-microvolt = <900000>;
378 regulator-max-microvolt = <1400000>;
379 regulator-always-on;
380 };
381
382 ldo18_reg: LDO18 {
383 regulator-name = "ldo_18";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 };
387
388 ldo19_reg: LDO19 {
389 regulator-name = "ldo_19";
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <1800000>;
392 };
393
394 ldo20_reg: LDO20 {
395 regulator-name = "ldo_20";
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <1800000>;
398 regulator-always-on;
399 };
400
401 ldo21_reg: LDO21 {
402 regulator-name = "ldo_21";
403 regulator-min-microvolt = <2800000>;
404 regulator-max-microvolt = <2800000>;
405 };
406
407 ldo23_reg: LDO23 {
408 regulator-name = "ldo_23";
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
411 };
412 ldo24_reg: LDO24 {
413 regulator-name = "ldo_24";
414 regulator-min-microvolt = <2800000>;
415 regulator-max-microvolt = <2800000>;
416 };
417
418 ldo25_reg: LDO25 {
419 regulator-name = "ldo_25";
420 regulator-min-microvolt = <3300000>;
421 regulator-max-microvolt = <3300000>;
422 };
423
424 ldo26_reg: LDO26 {
425 regulator-name = "ldo_26";
426 regulator-min-microvolt = <1200000>;
427 regulator-max-microvolt = <1200000>;
428 };
429
430 ldo27_reg: LDO27 {
431 regulator-name = "ldo_27";
432 regulator-min-microvolt = <1200000>;
433 regulator-max-microvolt = <1200000>;
434 };
435
436 ldo28_reg: LDO28 {
437 regulator-name = "ldo_28";
438 regulator-min-microvolt = <1800000>;
439 regulator-max-microvolt = <1800000>;
440 };
441
442 ldo29_reg: LDO29 {
443 regulator-name = "ldo_29";
444 regulator-min-microvolt = <1800000>;
445 regulator-max-microvolt = <1800000>;
446 };
447
448 ldo30_reg: LDO30 {
449 regulator-name = "vdd_mifs";
450 regulator-min-microvolt = <1000000>;
451 regulator-max-microvolt = <1000000>;
452 regulator-always-on;
453 };
454
455 ldo32_reg: LDO32 {
456 regulator-name = "ldo_32";
457 regulator-min-microvolt = <3000000>;
458 regulator-max-microvolt = <3000000>;
459 };
460
461 ldo33_reg: LDO33 {
462 regulator-name = "ldo_33";
463 regulator-min-microvolt = <2800000>;
464 regulator-max-microvolt = <2800000>;
465 };
466
467 ldo34_reg: LDO34 {
468 regulator-name = "ldo_34";
469 regulator-min-microvolt = <3000000>;
470 regulator-max-microvolt = <3000000>;
471 };
472
473 ldo35_reg: LDO35 {
474 regulator-name = "ldo_35";
475 regulator-min-microvolt = <1200000>;
476 regulator-max-microvolt = <1200000>;
477 };
478 };
479 };
145}; 480};
146 481
147&hsi2c_7 { 482&hsi2c_7 {
148 status = "okay"; 483 status = "okay";
484 clock-frequency = <400000>;
149 485
150 max98090: codec@10 { 486 max98090: codec@10 {
151 compatible = "maxim,max98090"; 487 compatible = "maxim,max98090";
@@ -155,6 +491,44 @@
155 pinctrl-names = "default"; 491 pinctrl-names = "default";
156 pinctrl-0 = <&max98090_irq>; 492 pinctrl-0 = <&max98090_irq>;
157 }; 493 };
494
495 light-sensor@44 {
496 compatible = "isil,isl29018";
497 reg = <0x44>;
498 vcc-supply = <&tps65090_fet5>;
499 };
500
501 ps8625: lvds-bridge@48 {
502 compatible = "parade,ps8625";
503 reg = <0x48>;
504 sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
505 reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
506 lane-count = <2>;
507 panel = <&panel>;
508 use-external-pwm;
509 };
510};
511
512&hsi2c_8 {
513 status = "okay";
514 clock-frequency = <333000>;
515
516 /* Atmel mXT336S */
517 trackpad@4b {
518 compatible = "atmel,maxtouch";
519 reg = <0x4b>;
520 interrupt-parent = <&gpx1>;
521 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
522 wakeup-source;
523 pinctrl-names = "default";
524 pinctrl-0 = <&trackpad_irq>;
525 linux,gpio-keymap = <KEY_RESERVED
526 KEY_RESERVED
527 KEY_RESERVED /* GPIO0 */
528 KEY_RESERVED /* GPIO1 */
529 KEY_RESERVED /* GPIO2 */
530 BTN_LEFT>; /* GPIO3 */
531 };
158}; 532};
159 533
160&hsi2c_9 { 534&hsi2c_9 {
@@ -187,7 +561,7 @@
187 num-slots = <1>; 561 num-slots = <1>;
188 broken-cd; 562 broken-cd;
189 caps2-mmc-hs200-1_8v; 563 caps2-mmc-hs200-1_8v;
190 supports-highspeed; 564 cap-mmc-highspeed;
191 non-removable; 565 non-removable;
192 card-detect-delay = <200>; 566 card-detect-delay = <200>;
193 clock-frequency = <400000000>; 567 clock-frequency = <400000000>;
@@ -196,17 +570,13 @@
196 samsung,dw-mshc-ddr-timing = <0 2>; 570 samsung,dw-mshc-ddr-timing = <0 2>;
197 pinctrl-names = "default"; 571 pinctrl-names = "default";
198 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 572 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
199 573 bus-width = <8>;
200 slot@0 {
201 reg = <0>;
202 bus-width = <8>;
203 };
204}; 574};
205 575
206&mmc_2 { 576&mmc_2 {
207 status = "okay"; 577 status = "okay";
208 num-slots = <1>; 578 num-slots = <1>;
209 supports-highspeed; 579 cap-sd-highspeed;
210 card-detect-delay = <200>; 580 card-detect-delay = <200>;
211 clock-frequency = <400000000>; 581 clock-frequency = <400000000>;
212 samsung,dw-mshc-ciu-div = <3>; 582 samsung,dw-mshc-ciu-div = <3>;
@@ -214,11 +584,7 @@
214 samsung,dw-mshc-ddr-timing = <1 2>; 584 samsung,dw-mshc-ddr-timing = <1 2>;
215 pinctrl-names = "default"; 585 pinctrl-names = "default";
216 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 586 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
217 587 bus-width = <4>;
218 slot@0 {
219 reg = <0>;
220 bus-width = <4>;
221 };
222}; 588};
223 589
224 590
@@ -249,6 +615,13 @@
249 samsung,pin-drv = <0>; 615 samsung,pin-drv = <0>;
250 }; 616 };
251 617
618 trackpad_irq: trackpad-irq {
619 samsung,pins = "gpx1-1";
620 samsung,pin-function = <0xf>;
621 samsung,pin-pud = <0>;
622 samsung,pin-drv = <0>;
623 };
624
252 power_key_irq: power-key-irq { 625 power_key_irq: power-key-irq {
253 samsung,pins = "gpx1-2"; 626 samsung,pins = "gpx1-2";
254 samsung,pin-function = <0>; 627 samsung,pin-function = <0>;
@@ -277,12 +650,42 @@
277 samsung,pin-drv = <0>; 650 samsung,pin-drv = <0>;
278 }; 651 };
279 652
653 max77802_irq: max77802-irq {
654 samsung,pins = "gpx3-1";
655 samsung,pin-function = <0>;
656 samsung,pin-pud = <0>;
657 samsung,pin-drv = <0>;
658 };
659
280 hdmi_hpd_irq: hdmi-hpd-irq { 660 hdmi_hpd_irq: hdmi-hpd-irq {
281 samsung,pins = "gpx3-7"; 661 samsung,pins = "gpx3-7";
282 samsung,pin-function = <0>; 662 samsung,pin-function = <0>;
283 samsung,pin-pud = <1>; 663 samsung,pin-pud = <1>;
284 samsung,pin-drv = <0>; 664 samsung,pin-drv = <0>;
285 }; 665 };
666
667 pmic_dvs_1: pmic-dvs-1 {
668 samsung,pins = "gpy7-6";
669 samsung,pin-function = <1>;
670 samsung,pin-pud = <0>;
671 samsung,pin-drv = <0>;
672 };
673};
674
675&pinctrl_2 {
676 pmic_dvs_2: pmic-dvs-2 {
677 samsung,pins = "gpj4-2";
678 samsung,pin-function = <1>;
679 samsung,pin-pud = <0>;
680 samsung,pin-drv = <0>;
681 };
682
683 pmic_dvs_3: pmic-dvs-3 {
684 samsung,pins = "gpj4-3";
685 samsung,pin-function = <1>;
686 samsung,pin-pud = <0>;
687 samsung,pin-drv = <0>;
688 };
286}; 689};
287 690
288&pinctrl_3 { 691&pinctrl_3 {
@@ -312,6 +715,14 @@
312 samsung,pin-pud = <0>; 715 samsung,pin-pud = <0>;
313 samsung,pin-drv = <0>; 716 samsung,pin-drv = <0>;
314 }; 717 };
718
719 pmic_selb: pmic-selb {
720 samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
721 "gph0-6";
722 samsung,pin-function = <1>;
723 samsung,pin-pud = <0>;
724 samsung,pin-drv = <0>;
725 };
315}; 726};
316 727
317&rtc { 728&rtc {
@@ -365,12 +776,12 @@
365 vsys2-supply = <&vbat>; 776 vsys2-supply = <&vbat>;
366 vsys3-supply = <&vbat>; 777 vsys3-supply = <&vbat>;
367 infet1-supply = <&vbat>; 778 infet1-supply = <&vbat>;
368 infet2-supply = <&vbat>; 779 infet2-supply = <&tps65090_dcdc1>;
369 infet3-supply = <&vbat>; 780 infet3-supply = <&tps65090_dcdc2>;
370 infet4-supply = <&vbat>; 781 infet4-supply = <&tps65090_dcdc2>;
371 infet5-supply = <&vbat>; 782 infet5-supply = <&tps65090_dcdc2>;
372 infet6-supply = <&vbat>; 783 infet6-supply = <&tps65090_dcdc2>;
373 infet7-supply = <&vbat>; 784 infet7-supply = <&tps65090_dcdc1>;
374 vsys-l1-supply = <&vbat>; 785 vsys-l1-supply = <&vbat>;
375 vsys-l2-supply = <&vbat>; 786 vsys-l2-supply = <&vbat>;
376 787
@@ -445,3 +856,4 @@
445}; 856};
446 857
447#include "cros-ec-keyboard.dtsi" 858#include "cros-ec-keyboard.dtsi"
859#include "cros-adc-thermistors.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6052aa9c5659..8be3d7b489ff 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -76,34 +76,26 @@
76 mmc@12200000 { 76 mmc@12200000 {
77 status = "okay"; 77 status = "okay";
78 broken-cd; 78 broken-cd;
79 supports-highspeed;
80 card-detect-delay = <200>; 79 card-detect-delay = <200>;
81 samsung,dw-mshc-ciu-div = <3>; 80 samsung,dw-mshc-ciu-div = <3>;
82 samsung,dw-mshc-sdr-timing = <0 4>; 81 samsung,dw-mshc-sdr-timing = <0 4>;
83 samsung,dw-mshc-ddr-timing = <0 2>; 82 samsung,dw-mshc-ddr-timing = <0 2>;
84 pinctrl-names = "default"; 83 pinctrl-names = "default";
85 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 84 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
86 85 bus-width = <8>;
87 slot@0 { 86 cap-mmc-highspeed;
88 reg = <0>;
89 bus-width = <8>;
90 };
91 }; 87 };
92 88
93 mmc@12220000 { 89 mmc@12220000 {
94 status = "okay"; 90 status = "okay";
95 supports-highspeed;
96 card-detect-delay = <200>; 91 card-detect-delay = <200>;
97 samsung,dw-mshc-ciu-div = <3>; 92 samsung,dw-mshc-ciu-div = <3>;
98 samsung,dw-mshc-sdr-timing = <2 3>; 93 samsung,dw-mshc-sdr-timing = <2 3>;
99 samsung,dw-mshc-ddr-timing = <1 2>; 94 samsung,dw-mshc-ddr-timing = <1 2>;
100 pinctrl-names = "default"; 95 pinctrl-names = "default";
101 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 96 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
102 97 bus-width = <4>;
103 slot@0 { 98 cap-sd-highspeed;
104 reg = <0>;
105 bus-width = <4>;
106 };
107 }; 99 };
108 100
109 dp-controller@145B0000 { 101 dp-controller@145B0000 {
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3ee48bbe05f..1d31c8132558 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -11,6 +11,7 @@
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/input/input.h> 12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
14#include "exynos5800.dtsi" 15#include "exynos5800.dtsi"
15 16
16/ { 17/ {
@@ -28,11 +29,13 @@
28 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; 29 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
29 }; 30 };
30 31
31 backlight { 32 backlight: backlight {
32 compatible = "pwm-backlight"; 33 compatible = "pwm-backlight";
33 pwms = <&pwm 0 1000000 0>; 34 pwms = <&pwm 0 1000000 0>;
34 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 35 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
35 default-brightness-level = <7>; 36 default-brightness-level = <7>;
37 enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
38 power-supply = <&tps65090_fet1>;
36 pinctrl-0 = <&pwm0_out>; 39 pinctrl-0 = <&pwm0_out>;
37 pinctrl-names = "default"; 40 pinctrl-names = "default";
38 }; 41 };
@@ -98,6 +101,17 @@
98 regulator-boot-on; 101 regulator-boot-on;
99 regulator-always-on; 102 regulator-always-on;
100 }; 103 };
104
105 panel: panel {
106 compatible = "auo,b133htn01";
107 power-supply = <&tps65090_fet6>;
108 backlight = <&backlight>;
109 };
110};
111
112&adc {
113 status = "okay";
114 vdd-supply = <&ldo9_reg>;
101}; 115};
102 116
103&dp { 117&dp {
@@ -111,22 +125,7 @@
111 samsung,link-rate = <0x0a>; 125 samsung,link-rate = <0x0a>;
112 samsung,lane-count = <2>; 126 samsung,lane-count = <2>;
113 samsung,hpd-gpio = <&gpx2 6 0>; 127 samsung,hpd-gpio = <&gpx2 6 0>;
114 128 panel = <&panel>;
115 display-timings {
116 native-mode = <&timing1>;
117
118 timing1: timing@1 {
119 clock-frequency = <150660000>;
120 hactive = <1920>;
121 vactive = <1080>;
122 hfront-porch = <60>;
123 hback-porch = <172>;
124 hsync-len = <80>;
125 vback-porch = <25>;
126 vfront-porch = <10>;
127 vsync-len = <10>;
128 };
129 };
130}; 129};
131 130
132&fimd { 131&fimd {
@@ -140,10 +139,348 @@
140 pinctrl-names = "default"; 139 pinctrl-names = "default";
141 pinctrl-0 = <&hdmi_hpd_irq>; 140 pinctrl-0 = <&hdmi_hpd_irq>;
142 ddc = <&i2c_2>; 141 ddc = <&i2c_2>;
142
143 hdmi-en-supply = <&tps65090_fet7>;
144 vdd-supply = <&ldo8_reg>;
145 vdd_osc-supply = <&ldo10_reg>;
146 vdd_pll-supply = <&ldo8_reg>;
147};
148
149&hsi2c_4 {
150 status = "okay";
151 clock-frequency = <400000>;
152
153 max77802-pmic@9 {
154 compatible = "maxim,max77802";
155 interrupt-parent = <&gpx3>;
156 interrupts = <1 IRQ_TYPE_NONE>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&max77802_irq>, <&pmic_selb>,
159 <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>;
160 wakeup-source;
161 reg = <0x9>;
162 #clock-cells = <1>;
163
164 inb1-supply = <&tps65090_dcdc2>;
165 inb2-supply = <&tps65090_dcdc1>;
166 inb3-supply = <&tps65090_dcdc2>;
167 inb4-supply = <&tps65090_dcdc2>;
168 inb5-supply = <&tps65090_dcdc1>;
169 inb6-supply = <&tps65090_dcdc2>;
170 inb7-supply = <&tps65090_dcdc1>;
171 inb8-supply = <&tps65090_dcdc1>;
172 inb9-supply = <&tps65090_dcdc1>;
173 inb10-supply = <&tps65090_dcdc1>;
174
175 inl1-supply = <&buck5_reg>;
176 inl2-supply = <&buck7_reg>;
177 inl3-supply = <&buck9_reg>;
178 inl4-supply = <&buck9_reg>;
179 inl5-supply = <&buck9_reg>;
180 inl6-supply = <&tps65090_dcdc2>;
181 inl7-supply = <&buck9_reg>;
182 inl9-supply = <&tps65090_dcdc2>;
183 inl10-supply = <&buck7_reg>;
184
185 regulators {
186 buck1_reg: BUCK1 {
187 regulator-name = "vdd_mif";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <1300000>;
190 regulator-always-on;
191 regulator-boot-on;
192 regulator-ramp-delay = <12500>;
193 };
194
195 buck2_reg: BUCK2 {
196 regulator-name = "vdd_arm";
197 regulator-min-microvolt = <800000>;
198 regulator-max-microvolt = <1500000>;
199 regulator-always-on;
200 regulator-boot-on;
201 regulator-ramp-delay = <12500>;
202 };
203
204 buck3_reg: BUCK3 {
205 regulator-name = "vdd_int";
206 regulator-min-microvolt = <800000>;
207 regulator-max-microvolt = <1400000>;
208 regulator-always-on;
209 regulator-boot-on;
210 regulator-ramp-delay = <12500>;
211 };
212
213 buck4_reg: BUCK4 {
214 regulator-name = "vdd_g3d";
215 regulator-min-microvolt = <700000>;
216 regulator-max-microvolt = <1400000>;
217 regulator-always-on;
218 regulator-boot-on;
219 regulator-ramp-delay = <12500>;
220 };
221
222 buck5_reg: BUCK5 {
223 regulator-name = "vdd_1v2";
224 regulator-min-microvolt = <1200000>;
225 regulator-max-microvolt = <1200000>;
226 regulator-always-on;
227 regulator-boot-on;
228 };
229
230 buck6_reg: BUCK6 {
231 regulator-name = "vdd_kfc";
232 regulator-min-microvolt = <800000>;
233 regulator-max-microvolt = <1500000>;
234 regulator-always-on;
235 regulator-boot-on;
236 regulator-ramp-delay = <12500>;
237 };
238
239 buck7_reg: BUCK7 {
240 regulator-name = "vdd_1v35";
241 regulator-min-microvolt = <1350000>;
242 regulator-max-microvolt = <1350000>;
243 regulator-always-on;
244 regulator-boot-on;
245 };
246
247 buck8_reg: BUCK8 {
248 regulator-name = "vdd_emmc";
249 regulator-min-microvolt = <2850000>;
250 regulator-max-microvolt = <2850000>;
251 regulator-always-on;
252 regulator-boot-on;
253 };
254
255 buck9_reg: BUCK9 {
256 regulator-name = "vdd_2v";
257 regulator-min-microvolt = <2000000>;
258 regulator-max-microvolt = <2000000>;
259 regulator-always-on;
260 regulator-boot-on;
261 };
262
263 buck10_reg: BUCK10 {
264 regulator-name = "vdd_1v8";
265 regulator-min-microvolt = <1800000>;
266 regulator-max-microvolt = <1800000>;
267 regulator-always-on;
268 regulator-boot-on;
269 };
270
271 ldo1_reg: LDO1 {
272 regulator-name = "vdd_1v0";
273 regulator-min-microvolt = <1000000>;
274 regulator-max-microvolt = <1000000>;
275 regulator-always-on;
276 };
277
278 ldo2_reg: LDO2 {
279 regulator-name = "vdd_1v2_2";
280 regulator-min-microvolt = <1200000>;
281 regulator-max-microvolt = <1200000>;
282 };
283
284 ldo3_reg: LDO3 {
285 regulator-name = "vdd_1v8_3";
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <1800000>;
288 regulator-always-on;
289 };
290
291 vqmmc_sdcard: ldo4_reg: LDO4 {
292 regulator-name = "vdd_sd";
293 regulator-min-microvolt = <1800000>;
294 regulator-max-microvolt = <2800000>;
295 regulator-always-on;
296 };
297
298 ldo5_reg: LDO5 {
299 regulator-name = "vdd_1v8_5";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <1800000>;
302 regulator-always-on;
303 };
304
305 ldo6_reg: LDO6 {
306 regulator-name = "vdd_1v8_6";
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <1800000>;
309 regulator-always-on;
310 };
311
312 ldo7_reg: LDO7 {
313 regulator-name = "vdd_1v8_7";
314 regulator-min-microvolt = <1800000>;
315 regulator-max-microvolt = <1800000>;
316 };
317
318 ldo8_reg: LDO8 {
319 regulator-name = "vdd_ldo8";
320 regulator-min-microvolt = <1000000>;
321 regulator-max-microvolt = <1000000>;
322 regulator-always-on;
323 };
324
325 ldo9_reg: LDO9 {
326 regulator-name = "vdd_ldo9";
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <1800000>;
329 regulator-always-on;
330 };
331
332 ldo10_reg: LDO10 {
333 regulator-name = "vdd_ldo10";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 regulator-always-on;
337 };
338
339 ldo11_reg: LDO11 {
340 regulator-name = "vdd_ldo11";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
343 regulator-always-on;
344 };
345
346 ldo12_reg: LDO12 {
347 regulator-name = "vdd_ldo12";
348 regulator-min-microvolt = <3000000>;
349 regulator-max-microvolt = <3000000>;
350 regulator-always-on;
351 };
352
353 ldo13_reg: LDO13 {
354 regulator-name = "vdd_ldo13";
355 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <1800000>;
357 regulator-always-on;
358 };
359
360 ldo14_reg: LDO14 {
361 regulator-name = "vdd_ldo14";
362 regulator-min-microvolt = <1800000>;
363 regulator-max-microvolt = <1800000>;
364 regulator-always-on;
365 };
366
367 ldo15_reg: LDO15 {
368 regulator-name = "vdd_ldo15";
369 regulator-min-microvolt = <1000000>;
370 regulator-max-microvolt = <1000000>;
371 regulator-always-on;
372 };
373
374 ldo17_reg: LDO17 {
375 regulator-name = "vdd_g3ds";
376 regulator-min-microvolt = <900000>;
377 regulator-max-microvolt = <1400000>;
378 regulator-always-on;
379 };
380
381 ldo18_reg: LDO18 {
382 regulator-name = "ldo_18";
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>;
385 };
386
387 ldo19_reg: LDO19 {
388 regulator-name = "ldo_19";
389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <1800000>;
391 };
392
393 ldo20_reg: LDO20 {
394 regulator-name = "ldo_20";
395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <1800000>;
397 regulator-always-on;
398 };
399
400 ldo21_reg: LDO21 {
401 regulator-name = "ldo_21";
402 regulator-min-microvolt = <2800000>;
403 regulator-max-microvolt = <2800000>;
404 };
405
406 ldo23_reg: LDO23 {
407 regulator-name = "ldo_23";
408 regulator-min-microvolt = <3300000>;
409 regulator-max-microvolt = <3300000>;
410 };
411 ldo24_reg: LDO24 {
412 regulator-name = "ldo_24";
413 regulator-min-microvolt = <2800000>;
414 regulator-max-microvolt = <2800000>;
415 };
416
417 ldo25_reg: LDO25 {
418 regulator-name = "ldo_25";
419 regulator-min-microvolt = <3300000>;
420 regulator-max-microvolt = <3300000>;
421 };
422
423 ldo26_reg: LDO26 {
424 regulator-name = "ldo_26";
425 regulator-min-microvolt = <1200000>;
426 regulator-max-microvolt = <1200000>;
427 };
428
429 ldo27_reg: LDO27 {
430 regulator-name = "ldo_27";
431 regulator-min-microvolt = <1200000>;
432 regulator-max-microvolt = <1200000>;
433 };
434
435 ldo28_reg: LDO28 {
436 regulator-name = "ldo_28";
437 regulator-min-microvolt = <1800000>;
438 regulator-max-microvolt = <1800000>;
439 };
440
441 ldo29_reg: LDO29 {
442 regulator-name = "ldo_29";
443 regulator-min-microvolt = <1800000>;
444 regulator-max-microvolt = <1800000>;
445 };
446
447 ldo30_reg: LDO30 {
448 regulator-name = "vdd_mifs";
449 regulator-min-microvolt = <1000000>;
450 regulator-max-microvolt = <1000000>;
451 regulator-always-on;
452 };
453
454 ldo32_reg: LDO32 {
455 regulator-name = "ldo_32";
456 regulator-min-microvolt = <3000000>;
457 regulator-max-microvolt = <3000000>;
458 };
459
460 ldo33_reg: LDO33 {
461 regulator-name = "ldo_33";
462 regulator-min-microvolt = <2800000>;
463 regulator-max-microvolt = <2800000>;
464 };
465
466 ldo34_reg: LDO34 {
467 regulator-name = "ldo_34";
468 regulator-min-microvolt = <3000000>;
469 regulator-max-microvolt = <3000000>;
470 };
471
472 ldo35_reg: LDO35 {
473 regulator-name = "ldo_35";
474 regulator-min-microvolt = <1200000>;
475 regulator-max-microvolt = <1200000>;
476 };
477 };
478 };
143}; 479};
144 480
145&hsi2c_7 { 481&hsi2c_7 {
146 status = "okay"; 482 status = "okay";
483 clock-frequency = <400000>;
147 484
148 max98091: codec@10 { 485 max98091: codec@10 {
149 compatible = "maxim,max98091"; 486 compatible = "maxim,max98091";
@@ -153,6 +490,33 @@
153 pinctrl-names = "default"; 490 pinctrl-names = "default";
154 pinctrl-0 = <&max98091_irq>; 491 pinctrl-0 = <&max98091_irq>;
155 }; 492 };
493
494 light-sensor@44 {
495 compatible = "isil,isl29018";
496 reg = <0x44>;
497 vcc-supply = <&tps65090_fet5>;
498 };
499};
500
501&hsi2c_8 {
502 status = "okay";
503 clock-frequency = <333000>;
504 /* Atmel mXT540S */
505 trackpad@4b {
506 compatible = "atmel,maxtouch";
507 reg = <0x4b>;
508 interrupt-parent = <&gpx1>;
509 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
510 wakeup-source;
511 pinctrl-names = "default";
512 pinctrl-0 = <&trackpad_irq>;
513 linux,gpio-keymap = <KEY_RESERVED
514 KEY_RESERVED
515 KEY_RESERVED /* GPIO 0 */
516 KEY_RESERVED /* GPIO 1 */
517 BTN_LEFT /* GPIO 2 */
518 KEY_RESERVED>; /* GPIO 3 */
519 };
156}; 520};
157 521
158&hsi2c_9 { 522&hsi2c_9 {
@@ -185,7 +549,7 @@
185 num-slots = <1>; 549 num-slots = <1>;
186 broken-cd; 550 broken-cd;
187 caps2-mmc-hs200-1_8v; 551 caps2-mmc-hs200-1_8v;
188 supports-highspeed; 552 cap-mmc-highspeed;
189 non-removable; 553 non-removable;
190 card-detect-delay = <200>; 554 card-detect-delay = <200>;
191 clock-frequency = <400000000>; 555 clock-frequency = <400000000>;
@@ -194,17 +558,13 @@
194 samsung,dw-mshc-ddr-timing = <0 2>; 558 samsung,dw-mshc-ddr-timing = <0 2>;
195 pinctrl-names = "default"; 559 pinctrl-names = "default";
196 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 560 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
197 561 bus-width = <8>;
198 slot@0 {
199 reg = <0>;
200 bus-width = <8>;
201 };
202}; 562};
203 563
204&mmc_2 { 564&mmc_2 {
205 status = "okay"; 565 status = "okay";
206 num-slots = <1>; 566 num-slots = <1>;
207 supports-highspeed; 567 cap-sd-highspeed;
208 card-detect-delay = <200>; 568 card-detect-delay = <200>;
209 clock-frequency = <400000000>; 569 clock-frequency = <400000000>;
210 samsung,dw-mshc-ciu-div = <3>; 570 samsung,dw-mshc-ciu-div = <3>;
@@ -212,11 +572,7 @@
212 samsung,dw-mshc-ddr-timing = <1 2>; 572 samsung,dw-mshc-ddr-timing = <1 2>;
213 pinctrl-names = "default"; 573 pinctrl-names = "default";
214 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 574 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
215 575 bus-width = <4>;
216 slot@0 {
217 reg = <0>;
218 bus-width = <4>;
219 };
220}; 576};
221 577
222 578
@@ -247,6 +603,13 @@
247 samsung,pin-drv = <0>; 603 samsung,pin-drv = <0>;
248 }; 604 };
249 605
606 trackpad_irq: trackpad-irq {
607 samsung,pins = "gpx1-1";
608 samsung,pin-function = <0xf>;
609 samsung,pin-pud = <0>;
610 samsung,pin-drv = <0>;
611 };
612
250 power_key_irq: power-key-irq { 613 power_key_irq: power-key-irq {
251 samsung,pins = "gpx1-2"; 614 samsung,pins = "gpx1-2";
252 samsung,pin-function = <0>; 615 samsung,pin-function = <0>;
@@ -275,12 +638,42 @@
275 samsung,pin-drv = <0>; 638 samsung,pin-drv = <0>;
276 }; 639 };
277 640
641 max77802_irq: max77802-irq {
642 samsung,pins = "gpx3-1";
643 samsung,pin-function = <0>;
644 samsung,pin-pud = <0>;
645 samsung,pin-drv = <0>;
646 };
647
278 hdmi_hpd_irq: hdmi-hpd-irq { 648 hdmi_hpd_irq: hdmi-hpd-irq {
279 samsung,pins = "gpx3-7"; 649 samsung,pins = "gpx3-7";
280 samsung,pin-function = <0>; 650 samsung,pin-function = <0>;
281 samsung,pin-pud = <1>; 651 samsung,pin-pud = <1>;
282 samsung,pin-drv = <0>; 652 samsung,pin-drv = <0>;
283 }; 653 };
654
655 pmic_dvs_1: pmic-dvs-1 {
656 samsung,pins = "gpy7-6";
657 samsung,pin-function = <1>;
658 samsung,pin-pud = <0>;
659 samsung,pin-drv = <0>;
660 };
661};
662
663&pinctrl_2 {
664 pmic_dvs_2: pmic-dvs-2 {
665 samsung,pins = "gpj4-2";
666 samsung,pin-function = <1>;
667 samsung,pin-pud = <0>;
668 samsung,pin-drv = <0>;
669 };
670
671 pmic_dvs_3: pmic-dvs-3 {
672 samsung,pins = "gpj4-3";
673 samsung,pin-function = <1>;
674 samsung,pin-pud = <0>;
675 samsung,pin-drv = <0>;
676 };
284}; 677};
285 678
286&pinctrl_3 { 679&pinctrl_3 {
@@ -310,6 +703,14 @@
310 samsung,pin-pud = <0>; 703 samsung,pin-pud = <0>;
311 samsung,pin-drv = <0>; 704 samsung,pin-drv = <0>;
312 }; 705 };
706
707 pmic_selb: pmic-selb {
708 samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5",
709 "gph0-6";
710 samsung,pin-function = <1>;
711 samsung,pin-pud = <0>;
712 samsung,pin-drv = <0>;
713 };
313}; 714};
314 715
315&rtc { 716&rtc {
@@ -363,12 +764,12 @@
363 vsys2-supply = <&vbat>; 764 vsys2-supply = <&vbat>;
364 vsys3-supply = <&vbat>; 765 vsys3-supply = <&vbat>;
365 infet1-supply = <&vbat>; 766 infet1-supply = <&vbat>;
366 infet2-supply = <&vbat>; 767 infet2-supply = <&tps65090_dcdc1>;
367 infet3-supply = <&vbat>; 768 infet3-supply = <&tps65090_dcdc2>;
368 infet4-supply = <&vbat>; 769 infet4-supply = <&tps65090_dcdc2>;
369 infet5-supply = <&vbat>; 770 infet5-supply = <&tps65090_dcdc2>;
370 infet6-supply = <&vbat>; 771 infet6-supply = <&tps65090_dcdc2>;
371 infet7-supply = <&vbat>; 772 infet7-supply = <&tps65090_dcdc1>;
372 vsys-l1-supply = <&vbat>; 773 vsys-l1-supply = <&vbat>;
373 vsys-l2-supply = <&vbat>; 774 vsys-l2-supply = <&vbat>;
374 775
@@ -443,3 +844,4 @@
443}; 844};
444 845
445#include "cros-ec-keyboard.dtsi" 846#include "cros-ec-keyboard.dtsi"
847#include "cros-adc-thermistors.dtsi"
diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
new file mode 100644
index 000000000000..40a9e33c2654
--- /dev/null
+++ b/arch/arm/boot/dts/hip04-d01.dts
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2013-2014 Linaro Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
12#include "hip04.dtsi"
13
14/ {
15 /* memory bus is 64-bit */
16 #address-cells = <2>;
17 #size-cells = <2>;
18 model = "Hisilicon D01 Development Board";
19 compatible = "hisilicon,hip04-d01";
20
21 memory@00000000,10000000 {
22 device_type = "memory";
23 reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
24 <0x00000004 0xc0000000 0x00000003 0x40000000>;
25 };
26
27 soc {
28 uart0: uart@4007000 {
29 status = "ok";
30 };
31 };
32};
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
new file mode 100644
index 000000000000..93b6c909e991
--- /dev/null
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -0,0 +1,267 @@
1/*
2 * Hisilicon Ltd. HiP04 SoC
3 *
4 * Copyright (C) 2013-2014 Hisilicon Ltd.
5 * Copyright (C) 2013-2014 Linaro Ltd.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/ {
15 /* memory bus is 64-bit */
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &uart0;
21 };
22
23 bootwrapper {
24 compatible = "hisilicon,hip04-bootwrapper";
25 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu-map {
33 cluster0 {
34 core0 {
35 cpu = <&CPU0>;
36 };
37 core1 {
38 cpu = <&CPU1>;
39 };
40 core2 {
41 cpu = <&CPU2>;
42 };
43 core3 {
44 cpu = <&CPU3>;
45 };
46 };
47 cluster1 {
48 core0 {
49 cpu = <&CPU4>;
50 };
51 core1 {
52 cpu = <&CPU5>;
53 };
54 core2 {
55 cpu = <&CPU6>;
56 };
57 core3 {
58 cpu = <&CPU7>;
59 };
60 };
61 cluster2 {
62 core0 {
63 cpu = <&CPU8>;
64 };
65 core1 {
66 cpu = <&CPU9>;
67 };
68 core2 {
69 cpu = <&CPU10>;
70 };
71 core3 {
72 cpu = <&CPU11>;
73 };
74 };
75 cluster3 {
76 core0 {
77 cpu = <&CPU12>;
78 };
79 core1 {
80 cpu = <&CPU13>;
81 };
82 core2 {
83 cpu = <&CPU14>;
84 };
85 core3 {
86 cpu = <&CPU15>;
87 };
88 };
89 };
90 CPU0: cpu@0 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a15";
93 reg = <0>;
94 };
95 CPU1: cpu@1 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a15";
98 reg = <1>;
99 };
100 CPU2: cpu@2 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a15";
103 reg = <2>;
104 };
105 CPU3: cpu@3 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a15";
108 reg = <3>;
109 };
110 CPU4: cpu@100 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a15";
113 reg = <0x100>;
114 };
115 CPU5: cpu@101 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a15";
118 reg = <0x101>;
119 };
120 CPU6: cpu@102 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a15";
123 reg = <0x102>;
124 };
125 CPU7: cpu@103 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a15";
128 reg = <0x103>;
129 };
130 CPU8: cpu@200 {
131 device_type = "cpu";
132 compatible = "arm,cortex-a15";
133 reg = <0x200>;
134 };
135 CPU9: cpu@201 {
136 device_type = "cpu";
137 compatible = "arm,cortex-a15";
138 reg = <0x201>;
139 };
140 CPU10: cpu@202 {
141 device_type = "cpu";
142 compatible = "arm,cortex-a15";
143 reg = <0x202>;
144 };
145 CPU11: cpu@203 {
146 device_type = "cpu";
147 compatible = "arm,cortex-a15";
148 reg = <0x203>;
149 };
150 CPU12: cpu@300 {
151 device_type = "cpu";
152 compatible = "arm,cortex-a15";
153 reg = <0x300>;
154 };
155 CPU13: cpu@301 {
156 device_type = "cpu";
157 compatible = "arm,cortex-a15";
158 reg = <0x301>;
159 };
160 CPU14: cpu@302 {
161 device_type = "cpu";
162 compatible = "arm,cortex-a15";
163 reg = <0x302>;
164 };
165 CPU15: cpu@303 {
166 device_type = "cpu";
167 compatible = "arm,cortex-a15";
168 reg = <0x303>;
169 };
170 };
171
172 timer {
173 compatible = "arm,armv7-timer";
174 interrupt-parent = <&gic>;
175 interrupts = <1 13 0xf08>,
176 <1 14 0xf08>,
177 <1 11 0xf08>,
178 <1 10 0xf08>;
179 };
180
181 clk_50m: clk_50m {
182 #clock-cells = <0>;
183 compatible = "fixed-clock";
184 clock-frequency = <50000000>;
185 };
186
187 clk_168m: clk_168m {
188 #clock-cells = <0>;
189 compatible = "fixed-clock";
190 clock-frequency = <168000000>;
191 };
192
193 soc {
194 /* It's a 32-bit SoC. */
195 #address-cells = <1>;
196 #size-cells = <1>;
197 compatible = "simple-bus";
198 interrupt-parent = <&gic>;
199 ranges = <0 0 0xe0000000 0x10000000>;
200
201 gic: interrupt-controller@c01000 {
202 compatible = "hisilicon,hip04-intc";
203 #interrupt-cells = <3>;
204 #address-cells = <0>;
205 interrupt-controller;
206 interrupts = <1 9 0xf04>;
207
208 reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
209 <0xc04000 0x2000>, <0xc06000 0x2000>;
210 };
211
212 sysctrl: sysctrl {
213 compatible = "hisilicon,sysctrl";
214 reg = <0x3e00000 0x00100000>;
215 };
216
217 fabric: fabric {
218 compatible = "hisilicon,hip04-fabric";
219 reg = <0x302a000 0x1000>;
220 };
221
222 dual_timer0: dual_timer@3000000 {
223 compatible = "arm,sp804", "arm,primecell";
224 reg = <0x3000000 0x1000>;
225 interrupts = <0 224 4>;
226 clocks = <&clk_50m>, <&clk_50m>;
227 clock-names = "apb_pclk";
228 };
229
230 arm-pmu {
231 compatible = "arm,cortex-a15-pmu";
232 interrupts = <0 64 4>,
233 <0 65 4>,
234 <0 66 4>,
235 <0 67 4>,
236 <0 68 4>,
237 <0 69 4>,
238 <0 70 4>,
239 <0 71 4>,
240 <0 72 4>,
241 <0 73 4>,
242 <0 74 4>,
243 <0 75 4>,
244 <0 76 4>,
245 <0 77 4>,
246 <0 78 4>,
247 <0 79 4>;
248 };
249
250 uart0: uart@4007000 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x4007000 0x1000>;
253 interrupts = <0 381 4>;
254 clocks = <&clk_168m>;
255 clock-names = "uartclk";
256 reg-shift = <2>;
257 status = "disabled";
258 };
259
260 sata0: sata@a000000 {
261 compatible = "hisilicon,hisi-ahci";
262 reg = <0xa000000 0x1000000>;
263 interrupts = <0 372 4>;
264 };
265
266 };
267};
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
new file mode 100644
index 000000000000..af4eee5794aa
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -0,0 +1,152 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx1.dtsi"
14
15/ {
16 model = "Freescale MX1 ADS";
17 compatible = "fsl,imx1ads", "fsl,imx1";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x08000000 0x04000000>;
25 };
26
27 clocks {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 clk32 {
32 compatible = "fsl,imx-clk32", "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32000>;
35 };
36 };
37};
38
39&cspi1 {
40 pinctrl-0 = <&pinctrl_cspi1>;
41 fsl,spi-num-chipselects = <1>;
42 cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
43 status = "okay";
44};
45
46&i2c {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_i2c>;
49 status = "okay";
50
51 extgpio0: pcf8575@22 {
52 compatible = "nxp,pcf8575";
53 reg = <0x22>;
54 gpio-controller;
55 #gpio-cells = <2>;
56 };
57
58 extgpio1: pcf8575@24 {
59 compatible = "nxp,pcf8575";
60 reg = <0x24>;
61 gpio-controller;
62 #gpio-cells = <2>;
63 };
64};
65
66&uart1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_uart1>;
69 fsl,uart-has-rtscts;
70 status = "okay";
71};
72
73&uart2 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_uart2>;
76 fsl,uart-has-rtscts;
77 status = "okay";
78};
79
80&weim {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_weim>;
83 status = "okay";
84
85 nor: nor@0,0 {
86 compatible = "cfi-flash";
87 reg = <0 0x00000000 0x02000000>;
88 bank-width = <4>;
89 fsl,weim-cs-timing = <0x00003e00 0x00000801>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92 };
93};
94
95&iomuxc {
96 imx1-ads {
97 pinctrl_cspi1: cspi1grp {
98 fsl,pins = <
99 MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
100 MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
101 MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
102 MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
103 MX1_PAD_SPI1_SS__GPIO3_15 0x0
104 >;
105 };
106
107 pinctrl_i2c: i2cgrp {
108 fsl,pins = <
109 MX1_PAD_I2C_SCL__I2C_SCL 0x0
110 MX1_PAD_I2C_SDA__I2C_SDA 0x0
111 >;
112 };
113
114 pinctrl_uart1: uart1grp {
115 fsl,pins = <
116 MX1_PAD_UART1_TXD__UART1_TXD 0x0
117 MX1_PAD_UART1_RXD__UART1_RXD 0x0
118 MX1_PAD_UART1_CTS__UART1_CTS 0x0
119 MX1_PAD_UART1_RTS__UART1_RTS 0x0
120 >;
121 };
122
123 pinctrl_uart2: uart2grp {
124 fsl,pins = <
125 MX1_PAD_UART2_TXD__UART2_TXD 0x0
126 MX1_PAD_UART2_RXD__UART2_RXD 0x0
127 MX1_PAD_UART2_CTS__UART2_CTS 0x0
128 MX1_PAD_UART2_RTS__UART2_RTS 0x0
129 >;
130 };
131
132 pinctrl_weim: weimgrp {
133 fsl,pins = <
134 MX1_PAD_A0__A0 0x0
135 MX1_PAD_A16__A16 0x0
136 MX1_PAD_A17__A17 0x0
137 MX1_PAD_A18__A18 0x0
138 MX1_PAD_A19__A19 0x0
139 MX1_PAD_A20__A20 0x0
140 MX1_PAD_A21__A21 0x0
141 MX1_PAD_A22__A22 0x0
142 MX1_PAD_A23__A23 0x0
143 MX1_PAD_A24__A24 0x0
144 MX1_PAD_BCLK__BCLK 0x0
145 MX1_PAD_CS4__CS4 0x0
146 MX1_PAD_DTACK__DTACK 0x0
147 MX1_PAD_ECB__ECB 0x0
148 MX1_PAD_LBA__LBA 0x0
149 >;
150 };
151 };
152};
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
new file mode 100644
index 000000000000..07d92fb40e6f
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx1.dtsi"
14
15/ {
16 model = "Armadeus APF9328";
17 compatible = "armadeus,imx1-apf9328", "fsl,imx1";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x08000000 0x00800000>;
25 };
26};
27
28&i2c {
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2c>;
31 status = "okay";
32};
33
34&uart1 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_uart1>;
37 fsl,uart-has-rtscts;
38 status = "okay";
39};
40
41&uart2 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_uart2>;
44 fsl,uart-has-rtscts;
45 status = "okay";
46};
47
48&weim {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_weim>;
51 status = "okay";
52
53 nor: nor@0,0 {
54 compatible = "cfi-flash";
55 reg = <0 0x00000000 0x02000000>;
56 bank-width = <2>;
57 fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 };
61
62 eth: eth@4,c00000 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_eth>;
65 compatible = "davicom,dm9000";
66 reg = <
67 4 0x00c00000 0x2
68 4 0x00c00002 0x2
69 >;
70 interrupt-parent = <&gpio2>;
71 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
72 fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
73 };
74};
75
76&iomuxc {
77 imx1-apf9328 {
78 pinctrl_eth: ethgrp {
79 fsl,pins = <
80 MX1_PAD_SIM_SVEN__GPIO2_14 0x0
81 >;
82 };
83
84 pinctrl_i2c: i2cgrp {
85 fsl,pins = <
86 MX1_PAD_I2C_SCL__I2C_SCL 0x0
87 MX1_PAD_I2C_SDA__I2C_SDA 0x0
88 >;
89 };
90
91 pinctrl_uart1: uart1grp {
92 fsl,pins = <
93 MX1_PAD_UART1_TXD__UART1_TXD 0x0
94 MX1_PAD_UART1_RXD__UART1_RXD 0x0
95 MX1_PAD_UART1_CTS__UART1_CTS 0x0
96 MX1_PAD_UART1_RTS__UART1_RTS 0x0
97 >;
98 };
99
100 pinctrl_uart2: uart2grp {
101 fsl,pins = <
102 MX1_PAD_UART2_TXD__UART2_TXD 0x0
103 MX1_PAD_UART2_RXD__UART2_RXD 0x0
104 MX1_PAD_UART2_CTS__UART2_CTS 0x0
105 MX1_PAD_UART2_RTS__UART2_RTS 0x0
106 >;
107 };
108
109 pinctrl_weim: weimgrp {
110 fsl,pins = <
111 MX1_PAD_A0__A0 0x0
112 MX1_PAD_A16__A16 0x0
113 MX1_PAD_A17__A17 0x0
114 MX1_PAD_A18__A18 0x0
115 MX1_PAD_A19__A19 0x0
116 MX1_PAD_A20__A20 0x0
117 MX1_PAD_A21__A21 0x0
118 MX1_PAD_A22__A22 0x0
119 MX1_PAD_A23__A23 0x0
120 MX1_PAD_A24__A24 0x0
121 MX1_PAD_BCLK__BCLK 0x0
122 MX1_PAD_CS4__CS4 0x0
123 MX1_PAD_DTACK__DTACK 0x0
124 MX1_PAD_ECB__ECB 0x0
125 MX1_PAD_LBA__LBA 0x0
126 >;
127 };
128 };
129};
diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h
new file mode 100644
index 000000000000..22bec8b87680
--- /dev/null
+++ b/arch/arm/boot/dts/imx1-pinfunc.h
@@ -0,0 +1,302 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __DTS_IMX1_PINFUNC_H
13#define __DTS_IMX1_PINFUNC_H
14
15/*
16 * The pin function ID is a tuple of
17 * <pin mux_id>
18 * mux_id consists of
19 * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
20 *
21 * function: 0 - Primary function
22 * 1 - Alternate function
23 * 2 - GPIO
24 * direction: 0 - Input
25 * 1 - Output
26 * gpio_oconf: 0 - A_IN
27 * 1 - B_IN
28 * 2 - A_OUT
29 * 3 - Data Register
30 * gpio_iconfa/b: 0 - GPIO_IN
31 * 1 - Interrupt Status Register
32 * 2 - 0
33 * 3 - 1
34 *
35 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
36 * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
37 * number on the specific port (between 0 and 31).
38 */
39
40#define MX1_PAD_A24__A24 0x00 0x004
41#define MX1_PAD_A24__GPIO1_0 0x00 0x032
42#define MX1_PAD_A24__SPI2_CLK 0x00 0x006
43#define MX1_PAD_TIN__TIN 0x01 0x000
44#define MX1_PAD_TIN__GPIO1_1 0x01 0x032
45#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022
46#define MX1_PAD_PWMO__PWMO 0x02 0x004
47#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032
48#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004
49#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032
50#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000
51#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032
52#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000
53#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032
54#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000
55#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032
56#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000
57#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032
58#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000
59#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032
60#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000
61#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032
62#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000
63#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032
64#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000
65#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032
66#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000
67#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032
68#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000
69#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032
70#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000
71#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032
72#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000
73#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032
74#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004
75#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032
76#define MX1_PAD_DTACK__DTACK 0x11 0x000
77#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032
78#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002
79#define MX1_PAD_DTACK__A25 0x11 0x016
80#define MX1_PAD_BCLK__BCLK 0x12 0x004
81#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032
82#define MX1_PAD_LBA__LBA 0x13 0x004
83#define MX1_PAD_LBA__GPIO1_19 0x13 0x032
84#define MX1_PAD_ECB__ECB 0x14 0x000
85#define MX1_PAD_ECB__GPIO1_20 0x14 0x032
86#define MX1_PAD_A0__A0 0x15 0x004
87#define MX1_PAD_A0__GPIO1_21 0x15 0x032
88#define MX1_PAD_CS4__CS4 0x16 0x004
89#define MX1_PAD_CS4__GPIO1_22 0x16 0x032
90#define MX1_PAD_CS5__CS5 0x17 0x004
91#define MX1_PAD_CS5__GPIO1_23 0x17 0x032
92#define MX1_PAD_A16__A16 0x18 0x004
93#define MX1_PAD_A16__GPIO1_24 0x18 0x032
94#define MX1_PAD_A17__A17 0x19 0x004
95#define MX1_PAD_A17__GPIO1_25 0x19 0x032
96#define MX1_PAD_A18__A18 0x1a 0x004
97#define MX1_PAD_A18__GPIO1_26 0x1a 0x032
98#define MX1_PAD_A19__A19 0x1b 0x004
99#define MX1_PAD_A19__GPIO1_27 0x1b 0x032
100#define MX1_PAD_A20__A20 0x1c 0x004
101#define MX1_PAD_A20__GPIO1_28 0x1c 0x032
102#define MX1_PAD_A21__A21 0x1d 0x004
103#define MX1_PAD_A21__GPIO1_29 0x1d 0x032
104#define MX1_PAD_A22__A22 0x1e 0x004
105#define MX1_PAD_A22__GPIO1_30 0x1e 0x032
106#define MX1_PAD_A23__A23 0x1f 0x004
107#define MX1_PAD_A23__GPIO1_31 0x1f 0x032
108#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000
109#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001
110#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032
111#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000
112#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001
113#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032
114#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000
115#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001
116#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032
117#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000
118#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001
119#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032
120#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004
121#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005
122#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032
123#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000
124#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005
125#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032
126#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004
127#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001
128#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032
129#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000
130#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001
131#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032
132#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000
133#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001
134#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032
135#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000
136#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005
137#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032
138#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004
139#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001
140#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032
141#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004
142#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001
143#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032
144#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004
145#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032
146#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004
147#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032
148#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000
149#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032
150#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004
151#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032
152#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000
153#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032
154#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000
155#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032
156#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004
157#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032
158#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004
159#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032
160#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004
161#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032
162#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000
163#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032
164#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004
165#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032
166#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000
167#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032
168#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000
169#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032
170#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000
171#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032
172#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000
173#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032
174#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004
175#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032
176#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000
177#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032
178#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000
179#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032
180#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004
181#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032
182#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000
183#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032
184#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004
185#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032
186#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000
187#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032
188#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000
189#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032
190#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004
191#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032
192#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000
193#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032
194#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000
195#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032
196#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004
197#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032
198#define MX1_PAD_BT13__BT13 0x53 0x004
199#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001
200#define MX1_PAD_BT13__GPIO3_19 0x53 0x032
201#define MX1_PAD_BT12__BT12 0x54 0x004
202#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001
203#define MX1_PAD_BT12__GPIO3_20 0x54 0x032
204#define MX1_PAD_BT11__BT11 0x55 0x004
205#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001
206#define MX1_PAD_BT11__GPIO3_21 0x55 0x032
207#define MX1_PAD_BT10__BT10 0x56 0x004
208#define MX1_PAD_BT10__SSI2_TX 0x56 0x001
209#define MX1_PAD_BT10__GPIO3_22 0x56 0x032
210#define MX1_PAD_BT9__BT9 0x57 0x004
211#define MX1_PAD_BT9__SSI2_RX 0x57 0x001
212#define MX1_PAD_BT9__GPIO3_23 0x57 0x032
213#define MX1_PAD_BT8__BT8 0x58 0x004
214#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001
215#define MX1_PAD_BT8__GPIO3_24 0x58 0x032
216#define MX1_PAD_BT8__UART3_RI 0x58 0x016
217#define MX1_PAD_BT7__BT7 0x59 0x004
218#define MX1_PAD_BT7__GPIO3_25 0x59 0x032
219#define MX1_PAD_BT7__UART3_DSR 0x59 0x016
220#define MX1_PAD_BT6__BT6 0x5a 0x004
221#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032
222#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016
223#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022
224#define MX1_PAD_BT5__BT5 0x5b 0x000
225#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032
226#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016
227#define MX1_PAD_BT4__BT4 0x5c 0x000
228#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032
229#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016
230#define MX1_PAD_BT3__BT3 0x5d 0x000
231#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032
232#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022
233#define MX1_PAD_BT2__BT2 0x5e 0x004
234#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032
235#define MX1_PAD_BT2__UART3_TX 0x5e 0x016
236#define MX1_PAD_BT1__BT1 0x5f 0x000
237#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032
238#define MX1_PAD_BT1__UART3_RX 0x5f 0x022
239#define MX1_PAD_LSCLK__LSCLK 0x66 0x004
240#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032
241#define MX1_PAD_REV__REV 0x67 0x004
242#define MX1_PAD_REV__UART2_DTR 0x67 0x001
243#define MX1_PAD_REV__GPIO4_7 0x67 0x032
244#define MX1_PAD_REV__SPI2_CLK 0x67 0x006
245#define MX1_PAD_CLS__CLS 0x68 0x004
246#define MX1_PAD_CLS__UART2_DCD 0x68 0x005
247#define MX1_PAD_CLS__GPIO4_8 0x68 0x032
248#define MX1_PAD_CLS__SPI2_SS 0x68 0x002
249#define MX1_PAD_PS__PS 0x69 0x004
250#define MX1_PAD_PS__UART2_RI 0x69 0x005
251#define MX1_PAD_PS__GPIO4_9 0x69 0x032
252#define MX1_PAD_PS__SPI2_RXD 0x69 0x022
253#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004
254#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005
255#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032
256#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006
257#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004
258#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032
259#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012
260#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004
261#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032
262#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004
263#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032
264#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004
265#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032
266#define MX1_PAD_LD0__LD0 0x6f 0x004
267#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032
268#define MX1_PAD_LD1__LD1 0x70 0x004
269#define MX1_PAD_LD1__GPIO4_16 0x70 0x032
270#define MX1_PAD_LD2__LD2 0x71 0x004
271#define MX1_PAD_LD2__GPIO4_17 0x71 0x032
272#define MX1_PAD_LD3__LD3 0x72 0x004
273#define MX1_PAD_LD3__GPIO4_18 0x72 0x032
274#define MX1_PAD_LD4__LD4 0x73 0x004
275#define MX1_PAD_LD4__GPIO4_19 0x73 0x032
276#define MX1_PAD_LD5__LD5 0x74 0x004
277#define MX1_PAD_LD5__GPIO4_20 0x74 0x032
278#define MX1_PAD_LD6__LD6 0x75 0x004
279#define MX1_PAD_LD6__GPIO4_21 0x75 0x032
280#define MX1_PAD_LD7__LD7 0x76 0x004
281#define MX1_PAD_LD7__GPIO4_22 0x76 0x032
282#define MX1_PAD_LD8__LD8 0x77 0x004
283#define MX1_PAD_LD8__GPIO4_23 0x77 0x032
284#define MX1_PAD_LD9__LD9 0x78 0x004
285#define MX1_PAD_LD9__GPIO4_24 0x78 0x032
286#define MX1_PAD_LD10__LD10 0x79 0x004
287#define MX1_PAD_LD10__GPIO4_25 0x79 0x032
288#define MX1_PAD_LD11__LD11 0x7a 0x004
289#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032
290#define MX1_PAD_LD12__LD12 0x7b 0x004
291#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032
292#define MX1_PAD_LD13__LD13 0x7c 0x004
293#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032
294#define MX1_PAD_LD14__LD14 0x7d 0x004
295#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032
296#define MX1_PAD_LD15__LD15 0x7e 0x004
297#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032
298#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000
299#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032
300#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006
301
302#endif
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
new file mode 100644
index 000000000000..22f5d1db5b31
--- /dev/null
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -0,0 +1,266 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "skeleton.dtsi"
13#include "imx1-pinfunc.h"
14
15#include <dt-bindings/clock/imx1-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19/ {
20 aliases {
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 i2c0 = &i2c;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 spi0 = &cspi1;
30 spi1 = &cspi2;
31 };
32
33 aitc: aitc-interrupt-controller@00223000 {
34 compatible = "fsl,imx1-aitc", "fsl,avic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x00223000 0x1000>;
38 };
39
40 cpus {
41 #size-cells = <0>;
42 #address-cells = <1>;
43
44 cpu: cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,arm920t";
47 operating-points = <200000 1900000>;
48 clock-latency = <62500>;
49 clocks = <&clks IMX1_CLK_MCU>;
50 voltage-tolerance = <5>;
51 };
52 };
53
54 soc {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
58 interrupt-parent = <&aitc>;
59 ranges;
60
61 aipi@00200000 {
62 compatible = "fsl,aipi-bus", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x00200000 0x10000>;
66 ranges;
67
68 gpt1: timer@00202000 {
69 compatible = "fsl,imx1-gpt";
70 reg = <0x00202000 0x1000>;
71 interrupts = <59>;
72 clocks = <&clks IMX1_CLK_HCLK>,
73 <&clks IMX1_CLK_PER1>;
74 clock-names = "ipg", "per";
75 };
76
77 gpt2: timer@00203000 {
78 compatible = "fsl,imx1-gpt";
79 reg = <0x00203000 0x1000>;
80 interrupts = <58>;
81 clocks = <&clks IMX1_CLK_HCLK>,
82 <&clks IMX1_CLK_PER1>;
83 clock-names = "ipg", "per";
84 };
85
86 fb: fb@00205000 {
87 compatible = "fsl,imx1-fb";
88 reg = <0x00205000 0x1000>;
89 interrupts = <14>;
90 clocks = <&clks IMX1_CLK_DUMMY>,
91 <&clks IMX1_CLK_DUMMY>,
92 <&clks IMX1_CLK_PER2>;
93 clock-names = "ipg", "ahb", "per";
94 status = "disabled";
95 };
96
97 uart1: serial@00206000 {
98 compatible = "fsl,imx1-uart";
99 reg = <0x00206000 0x1000>;
100 interrupts = <30 29 26>;
101 clocks = <&clks IMX1_CLK_HCLK>,
102 <&clks IMX1_CLK_PER1>;
103 clock-names = "ipg", "per";
104 status = "disabled";
105 };
106
107 uart2: serial@00207000 {
108 compatible = "fsl,imx1-uart";
109 reg = <0x00207000 0x1000>;
110 interrupts = <24 23 20>;
111 clocks = <&clks IMX1_CLK_HCLK>,
112 <&clks IMX1_CLK_PER1>;
113 clock-names = "ipg", "per";
114 status = "disabled";
115 };
116
117 pwm: pwm@00208000 {
118 #pwm-cells = <2>;
119 compatible = "fsl,imx1-pwm";
120 reg = <0x00208000 0x1000>;
121 interrupts = <34>;
122 clocks = <&clks IMX1_CLK_DUMMY>,
123 <&clks IMX1_CLK_PER1>;
124 clock-names = "ipg", "per";
125 };
126
127 dma: dma@00209000 {
128 compatible = "fsl,imx1-dma";
129 reg = <0x00209000 0x1000>;
130 interrupts = <61 60>;
131 clocks = <&clks IMX1_CLK_HCLK>,
132 <&clks IMX1_CLK_DMA_GATE>;
133 clock-names = "ipg", "ahb";
134 #dma-cells = <1>;
135 };
136
137 uart3: serial@0020a000 {
138 compatible = "fsl,imx1-uart";
139 reg = <0x0020a000 0x1000>;
140 interrupts = <54 4 1>;
141 clocks = <&clks IMX1_CLK_UART3_GATE>,
142 <&clks IMX1_CLK_PER1>;
143 clock-names = "ipg", "per";
144 status = "disabled";
145 };
146 };
147
148 aipi@00210000 {
149 compatible = "fsl,aipi-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x00210000 0x10000>;
153 ranges;
154
155 cspi1: cspi@00213000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,imx1-cspi";
159 reg = <0x00213000 0x1000>;
160 interrupts = <41>;
161 clocks = <&clks IMX1_CLK_DUMMY>,
162 <&clks IMX1_CLK_PER1>;
163 clock-names = "ipg", "per";
164 status = "disabled";
165 };
166
167 i2c: i2c@00217000 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 compatible = "fsl,imx1-i2c";
171 reg = <0x00217000 0x1000>;
172 interrupts = <39>;
173 clocks = <&clks IMX1_CLK_HCLK>;
174 status = "disabled";
175 };
176
177 cspi2: cspi@00219000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx1-cspi";
181 reg = <0x00219000 0x1000>;
182 interrupts = <40>;
183 clocks = <&clks IMX1_CLK_DUMMY>,
184 <&clks IMX1_CLK_PER1>;
185 clock-names = "ipg", "per";
186 status = "disabled";
187 };
188
189 clks: ccm@0021b000 {
190 compatible = "fsl,imx1-ccm";
191 reg = <0x0021b000 0x1000>;
192 #clock-cells = <1>;
193 };
194
195 iomuxc: iomuxc@0021c000 {
196 compatible = "fsl,imx1-iomuxc";
197 reg = <0x0021c000 0x1000>;
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges;
201
202 gpio1: gpio@0021c000 {
203 compatible = "fsl,imx1-gpio";
204 reg = <0x0021c000 0x100>;
205 interrupts = <11>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 };
211
212 gpio2: gpio@0021c100 {
213 compatible = "fsl,imx1-gpio";
214 reg = <0x0021c100 0x100>;
215 interrupts = <12>;
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 };
221
222 gpio3: gpio@0021c200 {
223 compatible = "fsl,imx1-gpio";
224 reg = <0x0021c200 0x100>;
225 interrupts = <13>;
226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 };
231
232 gpio4: gpio@0021c300 {
233 compatible = "fsl,imx1-gpio";
234 reg = <0x0021c300 0x100>;
235 interrupts = <62>;
236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
241 };
242 };
243
244 weim: weim@00220000 {
245 #address-cells = <2>;
246 #size-cells = <1>;
247 compatible = "fsl,imx1-weim";
248 reg = <0x00220000 0x1000>;
249 clocks = <&clks IMX1_CLK_DUMMY>;
250 ranges = <
251 0 0 0x10000000 0x02000000
252 1 0 0x12000000 0x01000000
253 2 0 0x13000000 0x01000000
254 3 0 0x14000000 0x01000000
255 4 0 0x15000000 0x01000000
256 5 0 0x16000000 0x01000000
257 >;
258 status = "disabled";
259 };
260
261 esram: esram@00300000 {
262 compatible = "mmio-sram";
263 reg = <0x00300000 0x20000>;
264 };
265 };
266};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index a33f66c11b73..57e29977ba06 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -60,10 +60,10 @@
60 pinctrl-names = "default"; 60 pinctrl-names = "default";
61 pinctrl-0 = <&lcdif_24bit_pins_a>; 61 pinctrl-0 = <&lcdif_24bit_pins_a>;
62 lcd-supply = <&reg_lcd_3v3>; 62 lcd-supply = <&reg_lcd_3v3>;
63 display = <&display>; 63 display = <&display0>;
64 status = "okay"; 64 status = "okay";
65 65
66 display: display { 66 display0: display0 {
67 bits-per-pixel = <32>; 67 bits-per-pixel = <32>;
68 bus-width = <24>; 68 bus-width = <24>;
69 69
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 9238a95d8e62..88eebb15da6a 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -247,6 +247,7 @@
247#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 247#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
248 248
249#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 249#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
250#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000
250#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 251#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
251#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 252#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
252 253
@@ -260,6 +261,7 @@
260#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 261#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
261 262
262#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 263#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
264#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
263#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 265#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
264#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 266#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
265 267
@@ -269,31 +271,46 @@
269#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 271#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
270 272
271#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 273#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
274#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
272#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 275#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
273#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 276#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
274 277
275#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 278#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
279#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
276#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 280#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
277 281
278#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 282#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
283#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001
279#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 284#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
280 285
281#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 286#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
287#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
282#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 288#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
289#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
283 290
284#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 291#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
292#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
285#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 293#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
294#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
286 295
287#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 296#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
297#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
298#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
288#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 299#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
289 300
290#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 301#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
302#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
303#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
291#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 304#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
292 305
293#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 306#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
307#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
308#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
294#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 309#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
295 310
296#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 311#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
312#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
313#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
297#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 314#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
298 315
299#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 316#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
@@ -303,18 +320,24 @@
303#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 320#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
304 321
305#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 322#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
323#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000
306#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 324#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
307 325
308#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 326#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
327#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000
309#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 328#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
310 329
311#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 330#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
331#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000
312#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 332#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
313 333
314#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 334#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
335#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001
336#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000
315#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 337#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
316 338
317#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 339#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
340#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000
318#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 341#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
319 342
320#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 343#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
@@ -328,6 +351,7 @@
328 351
329#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 352#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
330#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 353#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
354#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000
331#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 355#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
332 356
333#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 357#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
@@ -342,6 +366,7 @@
342 366
343#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 367#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
344#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 368#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
369#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
345#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 370#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
346 371
347#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 372#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
@@ -349,14 +374,17 @@
349#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 374#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
350 375
351#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 376#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
377#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001
352#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 378#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
353#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 379#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
354 380
355#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 381#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
382#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001
356#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 383#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
357#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 384#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
358 385
359#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 386#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
387#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001
360#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 388#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
361 389
362#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 390#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
@@ -457,14 +485,15 @@
457#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 485#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
458 486
459#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 487#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
460#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
461#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 488#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
462 489
463#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 490#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
464#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 491#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
492#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
465#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 493#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
466 494
467#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 495#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
496#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
468#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 497#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
469 498
470#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 499#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index c1740396b2c9..58d3c3cf2923 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -239,6 +239,7 @@
239 }; 239 };
240 240
241 ssi2: ssi@50014000 { 241 ssi2: ssi@50014000 {
242 #sound-dai-cells = <0>;
242 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; 243 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
243 reg = <0x50014000 0x4000>; 244 reg = <0x50014000 0x4000>;
244 interrupts = <11>; 245 interrupts = <11>;
@@ -274,6 +275,7 @@
274 }; 275 };
275 276
276 ssi1: ssi@50034000 { 277 ssi1: ssi@50034000 {
278 #sound-dai-cells = <0>;
277 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; 279 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
278 reg = <0x50034000 0x4000>; 280 reg = <0x50034000 0x4000>;
279 interrupts = <12>; 281 interrupts = <12>;
@@ -453,7 +455,7 @@
453 }; 455 };
454 456
455 sdma: sdma@53fd4000 { 457 sdma: sdma@53fd4000 {
456 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; 458 compatible = "fsl,imx25-sdma";
457 reg = <0x53fd4000 0x4000>; 459 reg = <0x53fd4000 0x4000>;
458 clocks = <&clks 112>, <&clks 68>; 460 clocks = <&clks 112>, <&clks 68>;
459 clock-names = "ipg", "ahb"; 461 clock-names = "ipg", "ahb";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 2b6d489dae69..da306c5dd678 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -67,6 +67,16 @@
67 pinctrl-names = "default"; 67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; 68 pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
69 status = "okay"; 69 status = "okay";
70
71 adc@0 {
72 compatible = "maxim,max1027";
73 reg = <0>;
74 interrupt-parent = <&gpio5>;
75 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_max1027>;
78 spi-max-frequency = <10000000>;
79 };
70}; 80};
71 81
72&cspi2 { 82&cspi2 {
@@ -189,6 +199,13 @@
189 >; 199 >;
190 }; 200 };
191 201
202 pinctrl_max1027: max1027 {
203 fsl,pins = <
204 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
205 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
206 >;
207 };
208
192 pinctrl_pwm: pwmgrp { 209 pinctrl_pwm: pwmgrp {
193 fsl,pins = < 210 fsl,pins = <
194 MX27_PAD_PWMO__PWMO 0x0 211 MX27_PAD_PWMO__PWMO 0x0
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 221cac4fb2cd..1f38a052ad4b 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -83,10 +83,10 @@
83 pinctrl-names = "default"; 83 pinctrl-names = "default";
84 pinctrl-0 = <&lcdif_16bit_pins_a 84 pinctrl-0 = <&lcdif_16bit_pins_a
85 &lcdif_pins_apf28dev>; 85 &lcdif_pins_apf28dev>;
86 display = <&display>; 86 display = <&display0>;
87 status = "okay"; 87 status = "okay";
88 88
89 display: display { 89 display0: display0 {
90 bits-per-pixel = <16>; 90 bits-per-pixel = <16>;
91 bus-width = <16>; 91 bus-width = <16>;
92 92
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index e1ce9179db63..1092b761d7ac 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -94,10 +94,10 @@
94 pinctrl-names = "default"; 94 pinctrl-names = "default";
95 pinctrl-0 = <&lcdif_24bit_pins_a 95 pinctrl-0 = <&lcdif_24bit_pins_a
96 &lcdif_pins_apx4>; 96 &lcdif_pins_apx4>;
97 display = <&display>; 97 display = <&display0>;
98 status = "okay"; 98 status = "okay";
99 99
100 display: display { 100 display0: display0 {
101 bits-per-pixel = <32>; 101 bits-per-pixel = <32>;
102 bus-width = <24>; 102 bus-width = <24>;
103 103
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 7d51459de5e8..ef944b6d4f01 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -177,10 +177,10 @@
177 pinctrl-0 = <&lcdif_18bit_pins_cfa10049 177 pinctrl-0 = <&lcdif_18bit_pins_cfa10049
178 &lcdif_pins_cfa10049 178 &lcdif_pins_cfa10049
179 &lcdif_pins_cfa10049_pullup>; 179 &lcdif_pins_cfa10049_pullup>;
180 display = <&display>; 180 display = <&display0>;
181 status = "okay"; 181 status = "okay";
182 182
183 display: display { 183 display0: display0 {
184 bits-per-pixel = <32>; 184 bits-per-pixel = <32>;
185 bus-width = <18>; 185 bus-width = <18>;
186 186
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
index c3900e7ba331..6a34114bec29 100644
--- a/arch/arm/boot/dts/imx28-cfa10055.dts
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -92,10 +92,10 @@
92 pinctrl-0 = <&lcdif_18bit_pins_cfa10055 92 pinctrl-0 = <&lcdif_18bit_pins_cfa10055
93 &lcdif_pins_cfa10055 93 &lcdif_pins_cfa10055
94 &lcdif_pins_cfa10055_pullup>; 94 &lcdif_pins_cfa10055_pullup>;
95 display = <&display>; 95 display = <&display0>;
96 status = "okay"; 96 status = "okay";
97 97
98 display: display { 98 display0: display0 {
99 bits-per-pixel = <32>; 99 bits-per-pixel = <32>;
100 bus-width = <18>; 100 bus-width = <18>;
101 101
diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts
index cef959a97219..ba6495ca44d2 100644
--- a/arch/arm/boot/dts/imx28-cfa10056.dts
+++ b/arch/arm/boot/dts/imx28-cfa10056.dts
@@ -64,10 +64,10 @@
64 pinctrl-0 = <&lcdif_24bit_pins_a 64 pinctrl-0 = <&lcdif_24bit_pins_a
65 &lcdif_pins_cfa10056 65 &lcdif_pins_cfa10056
66 &lcdif_pins_cfa10056_pullup >; 66 &lcdif_pins_cfa10056_pullup >;
67 display = <&display>; 67 display = <&display0>;
68 status = "okay"; 68 status = "okay";
69 69
70 display: display { 70 display0: display0 {
71 bits-per-pixel = <32>; 71 bits-per-pixel = <32>;
72 bus-width = <24>; 72 bus-width = <24>;
73 73
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index c4e00ce4b6da..5df0b24eaf59 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -78,10 +78,10 @@
78 pinctrl-names = "default"; 78 pinctrl-names = "default";
79 pinctrl-0 = <&lcdif_18bit_pins_cfa10057 79 pinctrl-0 = <&lcdif_18bit_pins_cfa10057
80 &lcdif_pins_cfa10057>; 80 &lcdif_pins_cfa10057>;
81 display = <&display>; 81 display = <&display0>;
82 status = "okay"; 82 status = "okay";
83 83
84 display: display { 84 display0: display0 {
85 bits-per-pixel = <32>; 85 bits-per-pixel = <32>;
86 bus-width = <18>; 86 bus-width = <18>;
87 87
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 7c9cc783f0d1..f5c6dce34abe 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -51,10 +51,10 @@
51 pinctrl-names = "default"; 51 pinctrl-names = "default";
52 pinctrl-0 = <&lcdif_24bit_pins_a 52 pinctrl-0 = <&lcdif_24bit_pins_a
53 &lcdif_pins_cfa10058>; 53 &lcdif_pins_cfa10058>;
54 display = <&display>; 54 display = <&display0>;
55 status = "okay"; 55 status = "okay";
56 56
57 display: display { 57 display0: display0 {
58 bits-per-pixel = <32>; 58 bits-per-pixel = <32>;
59 bus-width = <24>; 59 bus-width = <24>;
60 60
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index e4cc44c98585..09664fcf5afb 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -124,10 +124,10 @@
124 pinctrl-0 = <&lcdif_24bit_pins_a 124 pinctrl-0 = <&lcdif_24bit_pins_a
125 &lcdif_pins_evk>; 125 &lcdif_pins_evk>;
126 lcd-supply = <&reg_lcd_3v3>; 126 lcd-supply = <&reg_lcd_3v3>;
127 display = <&display>; 127 display = <&display0>;
128 status = "okay"; 128 status = "okay";
129 129
130 display: display { 130 display0: display0 {
131 bits-per-pixel = <32>; 131 bits-per-pixel = <32>;
132 bus-width = <24>; 132 bus-width = <24>;
133 133
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 9348ce59dda4..2df63bee6f4e 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -115,10 +115,10 @@
115 pinctrl-names = "default"; 115 pinctrl-names = "default";
116 pinctrl-0 = <&lcdif_24bit_pins_a 116 pinctrl-0 = <&lcdif_24bit_pins_a
117 &lcdif_pins_m28>; 117 &lcdif_pins_m28>;
118 display = <&display>; 118 display = <&display0>;
119 status = "okay"; 119 status = "okay";
120 120
121 display: display0 { 121 display0: display0 {
122 bits-per-pixel = <32>; 122 bits-per-pixel = <32>;
123 bus-width = <24>; 123 bus-width = <24>;
124 124
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index b3c09ae3b928..e35cc6ba3ca6 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -81,10 +81,10 @@
81 pinctrl-names = "default"; 81 pinctrl-names = "default";
82 pinctrl-0 = <&lcdif_24bit_pins_a 82 pinctrl-0 = <&lcdif_24bit_pins_a
83 &lcdif_pins_m28>; 83 &lcdif_pins_m28>;
84 display = <&display>; 84 display = <&display0>;
85 status = "okay"; 85 status = "okay";
86 86
87 display: display { 87 display0: display0 {
88 bits-per-pixel = <16>; 88 bits-per-pixel = <16>;
89 bus-width = <18>; 89 bus-width = <18>;
90 90
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index e14bd86f3e99..a5b27c85a91c 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -21,12 +21,15 @@
21 aliases { 21 aliases {
22 can0 = &can0; 22 can0 = &can0;
23 can1 = &can1; 23 can1 = &can1;
24 display = &display; 24 display = &display0;
25 ds1339 = &ds1339; 25 ds1339 = &ds1339;
26 gpio5 = &gpio5; 26 gpio5 = &gpio5;
27 lcdif = &lcdif; 27 lcdif = &lcdif;
28 lcdif_23bit_pins = &tx28_lcdif_23bit_pins; 28 lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
29 lcdif_24bit_pins = &lcdif_24bit_pins_a; 29 lcdif_24bit_pins = &lcdif_24bit_pins_a;
30 reg_can_xcvr = &reg_can_xcvr;
31 spi_gpio = &spi_gpio;
32 spi_mxs = &ssp3;
30 stk5led = &user_led; 33 stk5led = &user_led;
31 usbotg = &usb0; 34 usbotg = &usb0;
32 }; 35 };
@@ -37,7 +40,7 @@
37 40
38 onewire { 41 onewire {
39 compatible = "w1-gpio"; 42 compatible = "w1-gpio";
40 gpios = <&gpio2 7 0>; 43 gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
41 status = "disabled"; 44 status = "disabled";
42 }; 45 };
43 46
@@ -52,7 +55,7 @@
52 regulator-name = "usb0_vbus"; 55 regulator-name = "usb0_vbus";
53 regulator-min-microvolt = <5000000>; 56 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>;
55 gpio = <&gpio0 18 0>; 58 gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
56 enable-active-high; 59 enable-active-high;
57 }; 60 };
58 61
@@ -62,7 +65,7 @@
62 regulator-name = "usb1_vbus"; 65 regulator-name = "usb1_vbus";
63 regulator-min-microvolt = <5000000>; 66 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>;
65 gpio = <&gpio3 27 0>; 68 gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
66 enable-active-high; 69 enable-active-high;
67 }; 70 };
68 71
@@ -90,7 +93,7 @@
90 regulator-name = "CAN XCVR"; 93 regulator-name = "CAN XCVR";
91 regulator-min-microvolt = <3300000>; 94 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>; 95 regulator-max-microvolt = <3300000>;
93 gpio = <&gpio1 0 0>; 96 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
94 pinctrl-names = "default"; 97 pinctrl-names = "default";
95 pinctrl-0 = <&tx28_flexcan_xcvr_pins>; 98 pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
96 }; 99 };
@@ -101,7 +104,7 @@
101 regulator-name = "LCD POWER"; 104 regulator-name = "LCD POWER";
102 regulator-min-microvolt = <3300000>; 105 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>; 106 regulator-max-microvolt = <3300000>;
104 gpio = <&gpio1 31 0>; 107 gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
105 enable-active-high; 108 enable-active-high;
106 }; 109 };
107 110
@@ -111,7 +114,7 @@
111 regulator-name = "LCD RESET"; 114 regulator-name = "LCD RESET";
112 regulator-min-microvolt = <3300000>; 115 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>;
114 gpio = <&gpio3 30 0>; 117 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
115 startup-delay-us = <300000>; 118 startup-delay-us = <300000>;
116 enable-active-high; 119 enable-active-high;
117 regulator-always-on; 120 regulator-always-on;
@@ -143,7 +146,7 @@
143 146
144 user_led: user { 147 user_led: user {
145 label = "Heartbeat"; 148 label = "Heartbeat";
146 gpios = <&gpio4 10 0>; 149 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
147 linux,default-trigger = "heartbeat"; 150 linux,default-trigger = "heartbeat";
148 }; 151 };
149 }; 152 };
@@ -172,16 +175,16 @@
172 matrix_keypad: matrix-keypad@0 { 175 matrix_keypad: matrix-keypad@0 {
173 compatible = "gpio-matrix-keypad"; 176 compatible = "gpio-matrix-keypad";
174 col-gpios = < 177 col-gpios = <
175 &gpio5 0 0 178 &gpio5 0 GPIO_ACTIVE_HIGH
176 &gpio5 1 0 179 &gpio5 1 GPIO_ACTIVE_HIGH
177 &gpio5 2 0 180 &gpio5 2 GPIO_ACTIVE_HIGH
178 &gpio5 3 0 181 &gpio5 3 GPIO_ACTIVE_HIGH
179 >; 182 >;
180 row-gpios = < 183 row-gpios = <
181 &gpio5 4 0 184 &gpio5 4 GPIO_ACTIVE_HIGH
182 &gpio5 5 0 185 &gpio5 5 GPIO_ACTIVE_HIGH
183 &gpio5 6 0 186 &gpio5 6 GPIO_ACTIVE_HIGH
184 &gpio5 7 0 187 &gpio5 7 GPIO_ACTIVE_HIGH
185 >; 188 >;
186 /* sample keymap */ 189 /* sample keymap */
187 linux,keymap = < 190 linux,keymap = <
@@ -203,6 +206,44 @@
203 col-scan-delay-us = <5000>; 206 col-scan-delay-us = <5000>;
204 linux,no-autorepeat; 207 linux,no-autorepeat;
205 }; 208 };
209
210 spi_gpio: spi-gpio {
211 compatible = "spi-gpio";
212 #address-cells = <1>;
213 #size-cells = <0>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&tx28_spi_gpio_pins>;
216
217 gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>;
218 gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>;
219 gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>;
220 num-chipselects = <3>;
221 cs-gpios = <
222 &gpio2 27 GPIO_ACTIVE_LOW
223 &gpio3 8 GPIO_ACTIVE_LOW
224 &gpio3 9 GPIO_ACTIVE_LOW
225 >;
226 /* enable this and disable ssp3 below, if you need full duplex SPI transfer */
227 status = "disabled";
228
229 spi@0 {
230 compatible = "spidev";
231 reg = <0>;
232 spi-max-frequency = <57600000>;
233 };
234
235 spi@1 {
236 compatible = "spidev";
237 reg = <1>;
238 spi-max-frequency = <57600000>;
239 };
240
241 spi@2 {
242 compatible = "spidev";
243 reg = <2>;
244 spi-max-frequency = <57600000>;
245 };
246 };
206}; 247};
207 248
208/* 2nd TX-Std UART - (A)UART1 */ 249/* 2nd TX-Std UART - (A)UART1 */
@@ -284,8 +325,8 @@
284 pinctrl-0 = <&tx28_edt_ft5x06_pins>; 325 pinctrl-0 = <&tx28_edt_ft5x06_pins>;
285 interrupt-parent = <&gpio2>; 326 interrupt-parent = <&gpio2>;
286 interrupts = <5 0>; 327 interrupts = <5 0>;
287 reset-gpios = <&gpio2 6 1>; 328 reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
288 wake-gpios = <&gpio4 9 0>; 329 wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
289 }; 330 };
290 331
291 touchscreen: tsc2007@48 { 332 touchscreen: tsc2007@48 {
@@ -295,7 +336,7 @@
295 pinctrl-0 = <&tx28_tsc2007_pins>; 336 pinctrl-0 = <&tx28_tsc2007_pins>;
296 interrupt-parent = <&gpio3>; 337 interrupt-parent = <&gpio3>;
297 interrupts = <20 0>; 338 interrupts = <20 0>;
298 pendown-gpio = <&gpio3 20 1>; 339 pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
299 ti,x-plate-ohms = /bits/ 16 <660>; 340 ti,x-plate-ohms = /bits/ 16 <660>;
300 }; 341 };
301 342
@@ -309,10 +350,10 @@
309 pinctrl-names = "default"; 350 pinctrl-names = "default";
310 pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; 351 pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>;
311 lcd-supply = <&reg_lcd>; 352 lcd-supply = <&reg_lcd>;
312 display = <&display>; 353 display = <&display0>;
313 status = "okay"; 354 status = "okay";
314 355
315 display: display@0 { 356 display0: display0 {
316 bits-per-pixel = <32>; 357 bits-per-pixel = <32>;
317 bus-width = <24>; 358 bus-width = <24>;
318 display-timings { 359 display-timings {
@@ -558,6 +599,20 @@
558 fsl,pull-up = <MXS_PULL_DISABLE>; 599 fsl,pull-up = <MXS_PULL_DISABLE>;
559 }; 600 };
560 601
602 tx28_spi_gpio_pins: spi-gpiogrp {
603 fsl,pinmux-ids = <
604 MX28_PAD_AUART2_RX__GPIO_3_8
605 MX28_PAD_AUART2_TX__GPIO_3_9
606 MX28_PAD_SSP3_SCK__GPIO_2_24
607 MX28_PAD_SSP3_MOSI__GPIO_2_25
608 MX28_PAD_SSP3_MISO__GPIO_2_26
609 MX28_PAD_SSP3_SS0__GPIO_2_27
610 >;
611 fsl,drive-strength = <MXS_DRIVE_8mA>;
612 fsl,voltage = <MXS_VOLTAGE_HIGH>;
613 fsl,pull-up = <MXS_PULL_DISABLE>;
614 };
615
561 tx28_tsc2007_pins: tx28-tsc2007-pins { 616 tx28_tsc2007_pins: tx28-tsc2007-pins {
562 fsl,pinmux-ids = < 617 fsl,pinmux-ids = <
563 MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ 618 MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
@@ -619,17 +674,23 @@
619 clock-frequency = <57600000>; 674 clock-frequency = <57600000>;
620 status = "okay"; 675 status = "okay";
621 676
622 spidev0: spi@0 { 677 spi@0 {
623 compatible = "spidev"; 678 compatible = "spidev";
624 reg = <0>; 679 reg = <0>;
625 spi-max-frequency = <57600000>; 680 spi-max-frequency = <57600000>;
626 }; 681 };
627 682
628 spidev1: spi@1 { 683 spi@1 {
629 compatible = "spidev"; 684 compatible = "spidev";
630 reg = <1>; 685 reg = <1>;
631 spi-max-frequency = <57600000>; 686 spi-max-frequency = <57600000>;
632 }; 687 };
688
689 spi@2 {
690 compatible = "spidev";
691 reg = <2>;
692 spi-max-frequency = <57600000>;
693 };
633}; 694};
634 695
635&usb0 { 696&usb0 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index a95cc5358ff4..47f68ac868d4 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -489,6 +489,38 @@
489 fsl,pull-up = <MXS_PULL_DISABLE>; 489 fsl,pull-up = <MXS_PULL_DISABLE>;
490 }; 490 };
491 491
492 mmc1_4bit_pins_a: mmc1-4bit@0 {
493 reg = <0>;
494 fsl,pinmux-ids = <
495 MX28_PAD_GPMI_D00__SSP1_D0
496 MX28_PAD_GPMI_D01__SSP1_D1
497 MX28_PAD_GPMI_D02__SSP1_D2
498 MX28_PAD_GPMI_D03__SSP1_D3
499 MX28_PAD_GPMI_RDY1__SSP1_CMD
500 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
501 MX28_PAD_GPMI_WRN__SSP1_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_8mA>;
504 fsl,voltage = <MXS_VOLTAGE_HIGH>;
505 fsl,pull-up = <MXS_PULL_ENABLE>;
506 };
507
508 mmc1_cd_cfg: mmc1-cd-cfg {
509 fsl,pinmux-ids = <
510 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
511 >;
512 fsl,pull-up = <MXS_PULL_DISABLE>;
513 };
514
515 mmc1_sck_cfg: mmc1-sck-cfg {
516 fsl,pinmux-ids = <
517 MX28_PAD_GPMI_WRN__SSP1_SCK
518 >;
519 fsl,drive-strength = <MXS_DRIVE_12mA>;
520 fsl,pull-up = <MXS_PULL_DISABLE>;
521 };
522
523
492 mmc2_4bit_pins_a: mmc2-4bit@0 { 524 mmc2_4bit_pins_a: mmc2-4bit@0 {
493 reg = <0>; 525 reg = <0>;
494 fsl,pinmux-ids = < 526 fsl,pinmux-ids = <
@@ -553,6 +585,17 @@
553 fsl,pull-up = <MXS_PULL_ENABLE>; 585 fsl,pull-up = <MXS_PULL_ENABLE>;
554 }; 586 };
555 587
588 i2c1_pins_b: i2c1@1 {
589 reg = <1>;
590 fsl,pinmux-ids = <
591 MX28_PAD_AUART2_CTS__I2C1_SCL
592 MX28_PAD_AUART2_RTS__I2C1_SDA
593 >;
594 fsl,drive-strength = <MXS_DRIVE_8mA>;
595 fsl,voltage = <MXS_VOLTAGE_HIGH>;
596 fsl,pull-up = <MXS_PULL_ENABLE>;
597 };
598
556 saif0_pins_a: saif0@0 { 599 saif0_pins_a: saif0@0 {
557 reg = <0>; 600 reg = <0>;
558 fsl,pinmux-ids = < 601 fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 442e216ca9d9..6932928f3b45 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -114,6 +114,7 @@
114 }; 114 };
115 115
116 ssi1: ssi@43fa0000 { 116 ssi1: ssi@43fa0000 {
117 #sound-dai-cells = <0>;
117 compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; 118 compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
118 reg = <0x43fa0000 0x4000>; 119 reg = <0x43fa0000 0x4000>;
119 interrupts = <11>; 120 interrupts = <11>;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index c0e0f60ab6b2..620b0f030591 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -145,6 +145,7 @@
145 }; 145 };
146 146
147 ssi2: ssi@50014000 { 147 ssi2: ssi@50014000 {
148 #sound-dai-cells = <0>;
148 compatible = "fsl,imx50-ssi", 149 compatible = "fsl,imx50-ssi",
149 "fsl,imx51-ssi", 150 "fsl,imx51-ssi",
150 "fsl,imx21-ssi"; 151 "fsl,imx21-ssi";
@@ -454,6 +455,7 @@
454 }; 455 };
455 456
456 ssi1: ssi@63fcc000 { 457 ssi1: ssi@63fcc000 {
458 #sound-dai-cells = <0>;
457 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", 459 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
458 "fsl,imx21-ssi"; 460 "fsl,imx21-ssi";
459 reg = <0x63fcc000 0x4000>; 461 reg = <0x63fcc000 0x4000>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 17c05a6fa776..92660e1fe1fc 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -210,6 +210,7 @@
210 }; 210 };
211 211
212 ssi2: ssi@70014000 { 212 ssi2: ssi@70014000 {
213 #sound-dai-cells = <0>;
213 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
214 reg = <0x70014000 0x4000>; 215 reg = <0x70014000 0x4000>;
215 interrupts = <30>; 216 interrupts = <30>;
@@ -499,6 +500,7 @@
499 }; 500 };
500 501
501 ssi1: ssi@83fcc000 { 502 ssi1: ssi@83fcc000 {
503 #sound-dai-cells = <0>;
502 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 504 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
503 reg = <0x83fcc000 0x4000>; 505 reg = <0x83fcc000 0x4000>;
504 interrupts = <29>; 506 interrupts = <29>;
@@ -554,6 +556,7 @@
554 }; 556 };
555 557
556 ssi3: ssi@83fe8000 { 558 ssi3: ssi@83fe8000 {
559 #sound-dai-cells = <0>;
557 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 560 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
558 reg = <0x83fe8000 0x4000>; 561 reg = <0x83fe8000 0x4000>;
559 interrupts = <96>; 562 interrupts = <96>;
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 5ec1590ff7bc..1d325576bcc0 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -265,7 +265,7 @@
265 }; 265 };
266 266
267 pmic: dialog@48 { 267 pmic: dialog@48 {
268 compatible = "dialog,da9053", "dialog,da9052"; 268 compatible = "dlg,da9053", "dlg,da9052";
269 reg = <0x48>; 269 reg = <0x48>;
270 }; 270 };
271}; 271};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 6b675a02066f..f91725b2e8ab 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -221,6 +221,7 @@
221 }; 221 };
222 222
223 ssi2: ssi@50014000 { 223 ssi2: ssi@50014000 {
224 #sound-dai-cells = <0>;
224 compatible = "fsl,imx53-ssi", 225 compatible = "fsl,imx53-ssi",
225 "fsl,imx51-ssi", 226 "fsl,imx51-ssi",
226 "fsl,imx21-ssi"; 227 "fsl,imx21-ssi";
@@ -669,6 +670,7 @@
669 }; 670 };
670 671
671 ssi1: ssi@63fcc000 { 672 ssi1: ssi@63fcc000 {
673 #sound-dai-cells = <0>;
672 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 674 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
673 "fsl,imx21-ssi"; 675 "fsl,imx21-ssi";
674 reg = <0x63fcc000 0x4000>; 676 reg = <0x63fcc000 0x4000>;
@@ -696,6 +698,7 @@
696 }; 698 };
697 699
698 ssi3: ssi@63fe8000 { 700 ssi3: ssi@63fe8000 {
701 #sound-dai-cells = <0>;
699 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 702 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
700 "fsl,imx21-ssi"; 703 "fsl,imx21-ssi";
701 reg = <0x63fe8000 0x4000>; 704 reg = <0x63fe8000 0x4000>;
@@ -752,5 +755,10 @@
752 reg = <0xf8000000 0x20000>; 755 reg = <0xf8000000 0x20000>;
753 clocks = <&clks IMX5_CLK_OCRAM>; 756 clocks = <&clks IMX5_CLK_OCRAM>;
754 }; 757 };
758
759 pmu {
760 compatible = "arm,cortex-a8-pmu";
761 interrupts = <77>;
762 };
755 }; 763 };
756}; 764};
diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/imx6dl-gw552x.dts
new file mode 100644
index 000000000000..a4b700cef188
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw552x.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include "imx6dl.dtsi"
15#include "imx6qdl-gw552x.dtsi"
16
17/ {
18 model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
19 compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
20};
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 71598546087f..44a0e6736bb1 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,206 +1,13 @@
1/* 1/*
2 * Copyright (C) 2013,2014 Russell King 2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King
3 */ 4 */
4/dts-v1/; 5/dts-v1/;
5 6
6#include "imx6dl.dtsi" 7#include "imx6dl.dtsi"
7#include "imx6qdl-microsom.dtsi" 8#include "imx6qdl-hummingboard.dtsi"
8#include "imx6qdl-microsom-ar8035.dtsi"
9 9
10/ { 10/ {
11 model = "SolidRun HummingBoard DL/Solo"; 11 model = "SolidRun HummingBoard Solo/DualLite";
12 compatible = "solidrun,hummingboard", "fsl,imx6dl"; 12 compatible = "solidrun,hummingboard/dl", "fsl,imx6dl";
13
14 chosen {
15 stdout-path = &uart1;
16 };
17
18 ir_recv: ir-receiver {
19 compatible = "gpio-ir-receiver";
20 gpios = <&gpio1 2 1>;
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
23 };
24
25 regulators {
26 compatible = "simple-bus";
27
28 reg_3p3v: 3p3v {
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-always-on;
34 };
35
36 reg_usbh1_vbus: usb-h1-vbus {
37 compatible = "regulator-fixed";
38 enable-active-high;
39 gpio = <&gpio1 0 0>;
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
42 regulator-name = "usb_h1_vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 };
46
47 reg_usbotg_vbus: usb-otg-vbus {
48 compatible = "regulator-fixed";
49 enable-active-high;
50 gpio = <&gpio3 22 0>;
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
53 regulator-name = "usb_otg_vbus";
54 regulator-min-microvolt = <5000000>;
55 regulator-max-microvolt = <5000000>;
56 };
57 };
58
59 sound-spdif {
60 compatible = "fsl,imx-audio-spdif";
61 model = "On-board SPDIF";
62 /* IMX6 doesn't implement this yet */
63 spdif-controller = <&spdif>;
64 spdif-out;
65 };
66};
67
68&can1 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
71 status = "okay";
72};
73
74&hdmi {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
77 ddc-i2c-bus = <&i2c2>;
78 status = "okay";
79};
80
81&i2c1 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
84
85 /*
86 * Not fitted on Carrier-1 board... yet
87 status = "okay";
88
89 rtc: pcf8523@68 {
90 compatible = "nxp,pcf8523";
91 reg = <0x68>;
92 };
93 */
94};
95
96&i2c2 {
97 clock-frequency = <100000>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
100 status = "okay";
101};
102
103&iomuxc {
104 hummingboard {
105 pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
106 fsl,pins = <
107 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
108 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
109 >;
110 };
111
112 pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
113 fsl,pins = <
114 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
115 >;
116 };
117
118 pinctrl_hummingboard_hdmi: hummingboard-hdmi {
119 fsl,pins = <
120 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
121 >;
122 };
123
124 pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
125 fsl,pins = <
126 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
127 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
128 >;
129 };
130
131 pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
132 fsl,pins = <
133 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
134 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
135 >;
136 };
137
138 pinctrl_hummingboard_spdif: hummingboard-spdif {
139 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
140 };
141
142 pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
143 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
144 };
145
146 pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
147 /*
148 * Similar to pinctrl_usbotg_2, but we want it
149 * pulled down for a fixed host connection.
150 */
151 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
152 };
153
154 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
155 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
156 };
157
158 pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
159 fsl,pins = <
160 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
161 >;
162 };
163
164 pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
165 fsl,pins = <
166 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
167 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
168 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
169 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
170 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
171 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
172 >;
173 };
174 };
175};
176
177&spdif {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_hummingboard_spdif>;
180 status = "okay";
181};
182
183&usbh1 {
184 disable-over-current;
185 vbus-supply = <&reg_usbh1_vbus>;
186 status = "okay";
187};
188
189&usbotg {
190 disable-over-current;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
193 vbus-supply = <&reg_usbotg_vbus>;
194 status = "okay";
195};
196
197&usdhc2 {
198 pinctrl-names = "default";
199 pinctrl-0 = <
200 &pinctrl_hummingboard_usdhc2_aux
201 &pinctrl_hummingboard_usdhc2
202 >;
203 vmmc-supply = <&reg_3p3v>;
204 cd-gpios = <&gpio1 4 0>;
205 status = "okay";
206}; 13};
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 22e6f8e657d2..822ffb231c57 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include <dt-bindings/gpio/gpio.h>
13#include "imx6q.dtsi" 14#include "imx6q.dtsi"
14 15
15/ { 16/ {
@@ -18,7 +19,6 @@
18 19
19 /* these are used by bootloader for disabling nodes */ 20 /* these are used by bootloader for disabling nodes */
20 aliases { 21 aliases {
21 ethernet0 = &fec;
22 ethernet1 = &eth1; 22 ethernet1 = &eth1;
23 i2c0 = &i2c1; 23 i2c0 = &i2c1;
24 i2c1 = &i2c2; 24 i2c1 = &i2c2;
@@ -26,12 +26,10 @@
26 led0 = &led0; 26 led0 = &led0;
27 led1 = &led1; 27 led1 = &led1;
28 led2 = &led2; 28 led2 = &led2;
29 sky2 = &eth1;
30 ssi0 = &ssi1; 29 ssi0 = &ssi1;
31 spi0 = &ecspi1; 30 spi0 = &ecspi1;
32 usb0 = &usbh1; 31 usb0 = &usbh1;
33 usb1 = &usbotg; 32 usb1 = &usbotg;
34 usdhc2 = &usdhc3;
35 }; 33 };
36 34
37 chosen { 35 chosen {
@@ -40,23 +38,25 @@
40 38
41 leds { 39 leds {
42 compatible = "gpio-leds"; 40 compatible = "gpio-leds";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_gpio_leds>;
43 43
44 led0: user1 { 44 led0: user1 {
45 label = "user1"; 45 label = "user1";
46 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 46 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */
47 default-state = "on"; 47 default-state = "on";
48 linux,default-trigger = "heartbeat"; 48 linux,default-trigger = "heartbeat";
49 }; 49 };
50 50
51 led1: user2 { 51 led1: user2 {
52 label = "user2"; 52 label = "user2";
53 gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ 53 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */
54 default-state = "off"; 54 default-state = "off";
55 }; 55 };
56 56
57 led2: user3 { 57 led2: user3 {
58 label = "user3"; 58 label = "user3";
59 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ 59 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */
60 default-state = "off"; 60 default-state = "off";
61 }; 61 };
62 }; 62 };
@@ -67,7 +67,9 @@
67 67
68 pps { 68 pps {
69 compatible = "pps-gpio"; 69 compatible = "pps-gpio";
70 gpios = <&gpio1 5 0>; 70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_gpio_leds>;
72 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
71 status = "okay"; 73 status = "okay";
72 }; 74 };
73 75
@@ -109,7 +111,7 @@
109 regulator-name = "usb_otg_vbus"; 111 regulator-name = "usb_otg_vbus";
110 regulator-min-microvolt = <5000000>; 112 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>;
112 gpio = <&gpio3 22 0>; 114 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
113 enable-active-high; 115 enable-active-high;
114 }; 116 };
115 }; 117 };
@@ -137,7 +139,7 @@
137 139
138&ecspi1 { 140&ecspi1 {
139 fsl,spi-num-chipselects = <1>; 141 fsl,spi-num-chipselects = <1>;
140 cs-gpios = <&gpio3 19 0>; 142 cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
141 pinctrl-names = "default"; 143 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_ecspi1>; 144 pinctrl-0 = <&pinctrl_ecspi1>;
143 status = "okay"; 145 status = "okay";
@@ -153,7 +155,7 @@
153 pinctrl-names = "default"; 155 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_enet>; 156 pinctrl-0 = <&pinctrl_enet>;
155 phy-mode = "rgmii"; 157 phy-mode = "rgmii";
156 phy-reset-gpios = <&gpio1 30 0>; 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
157 status = "okay"; 159 status = "okay";
158}; 160};
159 161
@@ -199,11 +201,6 @@
199 #gpio-cells = <2>; 201 #gpio-cells = <2>;
200 }; 202 };
201 203
202 hwmon: gsc@29 {
203 compatible = "gw,gsp";
204 reg = <0x29>;
205 };
206
207 rtc: ds1672@68 { 204 rtc: ds1672@68 {
208 compatible = "dallas,ds1672"; 205 compatible = "dallas,ds1672";
209 reg = <0x68>; 206 reg = <0x68>;
@@ -314,16 +311,6 @@
314 }; 311 };
315 }; 312 };
316 }; 313 };
317
318 pciswitch: pex8609@3f {
319 compatible = "plx,pex8609";
320 reg = <0x3f>;
321 };
322
323 pciclkgen: si52147@6b {
324 compatible = "sil,si52147";
325 reg = <0x6b>;
326 };
327}; 314};
328 315
329&i2c3 { 316&i2c3 {
@@ -345,51 +332,73 @@
345 VDDIO-supply = <&reg_3p3v>; 332 VDDIO-supply = <&reg_3p3v>;
346 }; 333 };
347 334
348 hdmiin: adv7611@4c {
349 compatible = "adi,adv7611";
350 reg = <0x4c>;
351 };
352
353 touchscreen: egalax_ts@04 { 335 touchscreen: egalax_ts@04 {
354 compatible = "eeti,egalax_ts"; 336 compatible = "eeti,egalax_ts";
355 reg = <0x04>; 337 reg = <0x04>;
356 interrupt-parent = <&gpio7>; 338 interrupt-parent = <&gpio7>;
357 interrupts = <12 2>; /* gpio7_12 active low */ 339 interrupts = <12 2>;
358 wakeup-gpios = <&gpio7 12 0>; 340 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
359 }; 341 };
342};
360 343
361 videoout: adv7393@2a { 344&ldb {
362 compatible = "adi,adv7393"; 345 status = "okay";
363 reg = <0x2a>; 346};
364 }; 347
348&pcie {
349 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
350 status = "okay";
365 351
366 videoin: adv7180@20 { 352 eth1: sky2@8 { /* MAC/PHY on bus 8 */
367 compatible = "adi,adv7180"; 353 compatible = "marvell,sky2";
368 reg = <0x20>;
369 }; 354 };
370}; 355};
371 356
372&iomuxc { 357&ssi1 {
358 status = "okay";
359};
360
361&uart1 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_uart1>;
364 status = "okay";
365};
366
367&uart2 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_uart2>;
370 status = "okay";
371};
372
373&uart5 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_uart5>;
376 status = "okay";
377};
378
379&usbotg {
380 vbus-supply = <&reg_usb_otg_vbus>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_usbotg>;
383 disable-over-current;
384 status = "okay";
385};
386
387&usbh1 {
388 vbus-supply = <&reg_usb_h1_vbus>;
389 status = "okay";
390};
391
392&usdhc3 {
373 pinctrl-names = "default"; 393 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_hog>; 394 pinctrl-0 = <&pinctrl_usdhc3>;
395 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
396 vmmc-supply = <&reg_3p3v>;
397 status = "okay";
398};
375 399
400&iomuxc {
376 imx6q-gw5400-a { 401 imx6q-gw5400-a {
377 pinctrl_hog: hoggrp {
378 fsl,pins = <
379 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
380 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
381 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
382 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
383 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
384 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */
385 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */
386 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
387 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */
388 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
389 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */
390 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
391 >;
392 };
393 402
394 pinctrl_audmux: audmuxgrp { 403 pinctrl_audmux: audmuxgrp {
395 fsl,pins = < 404 fsl,pins = <
@@ -397,6 +406,7 @@
397 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 406 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
398 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 407 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
399 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 408 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
409 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
400 >; 410 >;
401 }; 411 };
402 412
@@ -405,6 +415,7 @@
405 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 415 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
406 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 416 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
407 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 417 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
418 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */
408 >; 419 >;
409 }; 420 };
410 421
@@ -429,6 +440,14 @@
429 >; 440 >;
430 }; 441 };
431 442
443 pinctrl_gpio_leds: gpioledsgrp {
444 fsl,pins = <
445 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */
446 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */
447 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */
448 >;
449 };
450
432 pinctrl_i2c1: i2c1grp { 451 pinctrl_i2c1: i2c1grp {
433 fsl,pins = < 452 fsl,pins = <
434 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 453 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
@@ -450,6 +469,19 @@
450 >; 469 >;
451 }; 470 };
452 471
472 pinctrl_pcie: pciegrp {
473 fsl,pins = <
474 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
475 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
476 >;
477 };
478
479 pinctrl_pps: ppsgrp {
480 fsl,pins = <
481 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */
482 >;
483 };
484
453 pinctrl_uart1: uart1grp { 485 pinctrl_uart1: uart1grp {
454 fsl,pins = < 486 fsl,pins = <
455 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 487 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@@ -474,6 +506,7 @@
474 pinctrl_usbotg: usbotggrp { 506 pinctrl_usbotg: usbotggrp {
475 fsl,pins = < 507 fsl,pins = <
476 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 508 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
509 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
477 >; 510 >;
478 }; 511 };
479 512
@@ -489,59 +522,3 @@
489 }; 522 };
490 }; 523 };
491}; 524};
492
493&ldb {
494 status = "okay";
495};
496
497&pcie {
498 reset-gpio = <&gpio1 29 0>;
499 status = "okay";
500
501 eth1: sky2@8 { /* MAC/PHY on bus 8 */
502 compatible = "marvell,sky2";
503 };
504};
505
506&ssi1 {
507 status = "okay";
508};
509
510&uart1 {
511 pinctrl-names = "default";
512 pinctrl-0 = <&pinctrl_uart1>;
513 status = "okay";
514};
515
516&uart2 {
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_uart2>;
519 status = "okay";
520};
521
522&uart5 {
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_uart5>;
525 status = "okay";
526};
527
528&usbotg {
529 vbus-supply = <&reg_usb_otg_vbus>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_usbotg>;
532 disable-over-current;
533 status = "okay";
534};
535
536&usbh1 {
537 vbus-supply = <&reg_usb_h1_vbus>;
538 status = "okay";
539};
540
541&usdhc3 {
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_usdhc3>;
544 cd-gpios = <&gpio7 0 0>;
545 vmmc-supply = <&reg_3p3v>;
546 status = "okay";
547};
diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/imx6q-gw552x.dts
new file mode 100644
index 000000000000..f87a8fa6e04d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw552x.dts
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include "imx6q.dtsi"
15#include "imx6qdl-gw552x.dtsi"
16
17/ {
18 model = "Gateworks Ventana i.MX6 Dual/Quad GW552X";
19 compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q";
20};
21
22&sata {
23 status = "okay";
24};
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
new file mode 100644
index 000000000000..c2bf8476ce45
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
3 * Based on dt work by Russell King
4 */
5/dts-v1/;
6
7#include "imx6q.dtsi"
8#include "imx6qdl-hummingboard.dtsi"
9
10/ {
11 model = "SolidRun HummingBoard Dual/Quad";
12 compatible = "solidrun,hummingboard/q", "fsl,imx6q";
13};
14
15&sata {
16 status = "okay";
17 fsl,transmit-level-mV = <1025>;
18 fsl,transmit-boost-mdB = <3330>;
19 fsl,transmit-atten-16ths = <9>;
20 fsl,receive-eq-mdB = <3000>;
21};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 0db15af41cb1..f2867c4b34a8 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -9,11 +9,11 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 led0 = &led0; 17 led0 = &led0;
18 led1 = &led1; 18 led1 = &led1;
19 nand = &gpmi; 19 nand = &gpmi;
@@ -27,17 +27,19 @@
27 27
28 leds { 28 leds {
29 compatible = "gpio-leds"; 29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_gpio_leds>;
30 32
31 led0: user1 { 33 led0: user1 {
32 label = "user1"; 34 label = "user1";
33 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 35 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
34 default-state = "on"; 36 default-state = "on";
35 linux,default-trigger = "heartbeat"; 37 linux,default-trigger = "heartbeat";
36 }; 38 };
37 39
38 led1: user2 { 40 led1: user2 {
39 label = "user2"; 41 label = "user2";
40 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 42 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
41 default-state = "off"; 43 default-state = "off";
42 }; 44 };
43 }; 45 };
@@ -48,7 +50,9 @@
48 50
49 pps { 51 pps {
50 compatible = "pps-gpio"; 52 compatible = "pps-gpio";
51 gpios = <&gpio1 26 0>; 53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_pps>;
55 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
52 status = "okay"; 56 status = "okay";
53 }; 57 };
54 58
@@ -81,7 +85,7 @@
81 regulator-name = "usb_otg_vbus"; 85 regulator-name = "usb_otg_vbus";
82 regulator-min-microvolt = <5000000>; 86 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>;
84 gpio = <&gpio3 22 0>; 88 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
85 enable-active-high; 89 enable-active-high;
86 }; 90 };
87 }; 91 };
@@ -91,7 +95,7 @@
91 pinctrl-names = "default"; 95 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_enet>; 96 pinctrl-0 = <&pinctrl_enet>;
93 phy-mode = "rgmii"; 97 phy-mode = "rgmii";
94 phy-reset-gpios = <&gpio1 30 0>; 98 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
95 status = "okay"; 99 status = "okay";
96}; 100};
97 101
@@ -143,11 +147,6 @@
143 #gpio-cells = <2>; 147 #gpio-cells = <2>;
144 }; 148 };
145 149
146 hwmon: gsc@29 {
147 compatible = "gw,gsp";
148 reg = <0x29>;
149 };
150
151 rtc: ds1672@68 { 150 rtc: ds1672@68 {
152 compatible = "dallas,ds1672"; 151 compatible = "dallas,ds1672";
153 reg = <0x68>; 152 reg = <0x68>;
@@ -159,53 +158,6 @@
159 pinctrl-names = "default"; 158 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c2>; 159 pinctrl-0 = <&pinctrl_i2c2>;
161 status = "okay"; 160 status = "okay";
162
163 pmic: ltc3676@3c {
164 compatible = "lltc,ltc3676";
165 reg = <0x3c>;
166
167 regulators {
168 sw1_reg: ltc3676__sw1 {
169 regulator-min-microvolt = <1175000>;
170 regulator-max-microvolt = <1175000>;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174
175 sw2_reg: ltc3676__sw2 {
176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <1800000>;
178 regulator-boot-on;
179 regulator-always-on;
180 };
181
182 sw3_reg: ltc3676__sw3 {
183 regulator-min-microvolt = <1175000>;
184 regulator-max-microvolt = <1175000>;
185 regulator-boot-on;
186 regulator-always-on;
187 };
188
189 sw4_reg: ltc3676__sw4 {
190 regulator-min-microvolt = <1500000>;
191 regulator-max-microvolt = <1500000>;
192 regulator-boot-on;
193 regulator-always-on;
194 };
195
196 ldo2_reg: ltc3676__ldo2 {
197 regulator-min-microvolt = <2500000>;
198 regulator-max-microvolt = <2500000>;
199 regulator-boot-on;
200 regulator-always-on;
201 };
202
203 ldo4_reg: ltc3676__ldo4 {
204 regulator-min-microvolt = <3000000>;
205 regulator-max-microvolt = <3000000>;
206 };
207 };
208 };
209}; 161};
210 162
211&i2c3 { 163&i2c3 {
@@ -213,31 +165,53 @@
213 pinctrl-names = "default"; 165 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c3>; 166 pinctrl-0 = <&pinctrl_i2c3>;
215 status = "okay"; 167 status = "okay";
168};
216 169
217 videoin: adv7180@20 { 170&pcie {
218 compatible = "adi,adv7180"; 171 pinctrl-names = "default";
219 reg = <0x20>; 172 pinctrl-0 = <&pinctrl_pcie>;
220 }; 173 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
174 status = "okay";
221}; 175};
222 176
223&iomuxc { 177&uart1 {
224 pinctrl-names = "default"; 178 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_hog>; 179 pinctrl-0 = <&pinctrl_uart1>;
180 status = "okay";
181};
226 182
227 imx6qdl-gw51xx { 183&uart2 {
228 pinctrl_hog: hoggrp { 184 pinctrl-names = "default";
229 fsl,pins = < 185 pinctrl-0 = <&pinctrl_uart2>;
230 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ 186 status = "okay";
231 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ 187};
232 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
233 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
234 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
235 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */
236 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
237 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
238 >;
239 };
240 188
189&uart3 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart3>;
192 status = "okay";
193};
194
195&uart5 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart5>;
198 status = "okay";
199};
200
201&usbotg {
202 vbus-supply = <&reg_usb_otg_vbus>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usbotg>;
205 disable-over-current;
206 status = "okay";
207};
208
209&usbh1 {
210 status = "okay";
211};
212
213&iomuxc {
214 imx6qdl-gw51xx {
241 pinctrl_enet: enetgrp { 215 pinctrl_enet: enetgrp {
242 fsl,pins = < 216 fsl,pins = <
243 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 217 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
@@ -256,6 +230,14 @@
256 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 230 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
257 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 231 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
258 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 232 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
233 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
234 >;
235 };
236
237 pinctrl_gpio_leds: gpioledsgrp {
238 fsl,pins = <
239 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
240 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
259 >; 241 >;
260 }; 242 };
261 243
@@ -301,6 +283,18 @@
301 >; 283 >;
302 }; 284 };
303 285
286 pinctrl_pcie: pciegrp {
287 fsl,pins = <
288 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
289 >;
290 };
291
292 pinctrl_pps: ppsgrp {
293 fsl,pins = <
294 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
295 >;
296 };
297
304 pinctrl_uart1: uart1grp { 298 pinctrl_uart1: uart1grp {
305 fsl,pins = < 299 fsl,pins = <
306 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 300 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@@ -332,48 +326,8 @@
332 pinctrl_usbotg: usbotggrp { 326 pinctrl_usbotg: usbotggrp {
333 fsl,pins = < 327 fsl,pins = <
334 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 328 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
329 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
335 >; 330 >;
336 }; 331 };
337 }; 332 };
338}; 333};
339
340&pcie {
341 reset-gpio = <&gpio1 0 0>;
342 status = "okay";
343};
344
345&uart1 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_uart1>;
348 status = "okay";
349};
350
351&uart2 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_uart2>;
354 status = "okay";
355};
356
357&uart3 {
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_uart3>;
360 status = "okay";
361};
362
363&uart5 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart5>;
366 status = "okay";
367};
368
369&usbotg {
370 vbus-supply = <&reg_usb_otg_vbus>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_usbotg>;
373 disable-over-current;
374 status = "okay";
375};
376
377&usbh1 {
378 status = "okay";
379};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 234e7b755232..d3c0bf5c84e3 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -9,10 +9,11 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 ethernet0 = &fec;
16 led0 = &led0; 17 led0 = &led0;
17 led1 = &led1; 18 led1 = &led1;
18 led2 = &led2; 19 led2 = &led2;
@@ -20,7 +21,6 @@
20 ssi0 = &ssi1; 21 ssi0 = &ssi1;
21 usb0 = &usbh1; 22 usb0 = &usbh1;
22 usb1 = &usbotg; 23 usb1 = &usbotg;
23 usdhc2 = &usdhc3;
24 }; 24 };
25 25
26 chosen { 26 chosen {
@@ -36,23 +36,25 @@
36 36
37 leds { 37 leds {
38 compatible = "gpio-leds"; 38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
39 41
40 led0: user1 { 42 led0: user1 {
41 label = "user1"; 43 label = "user1";
42 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
43 default-state = "on"; 45 default-state = "on";
44 linux,default-trigger = "heartbeat"; 46 linux,default-trigger = "heartbeat";
45 }; 47 };
46 48
47 led1: user2 { 49 led1: user2 {
48 label = "user2"; 50 label = "user2";
49 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
50 default-state = "off"; 52 default-state = "off";
51 }; 53 };
52 54
53 led2: user3 { 55 led2: user3 {
54 label = "user3"; 56 label = "user3";
55 gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ 57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
56 default-state = "off"; 58 default-state = "off";
57 }; 59 };
58 }; 60 };
@@ -63,7 +65,9 @@
63 65
64 pps { 66 pps {
65 compatible = "pps-gpio"; 67 compatible = "pps-gpio";
66 gpios = <&gpio1 26 0>; 68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
67 status = "okay"; 71 status = "okay";
68 }; 72 };
69 73
@@ -115,7 +119,7 @@
115 regulator-name = "usb_otg_vbus"; 119 regulator-name = "usb_otg_vbus";
116 regulator-min-microvolt = <5000000>; 120 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>; 121 regulator-max-microvolt = <5000000>;
118 gpio = <&gpio3 22 0>; 122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
119 enable-active-high; 123 enable-active-high;
120 }; 124 };
121 }; 125 };
@@ -141,11 +145,17 @@
141 status = "okay"; 145 status = "okay";
142}; 146};
143 147
148&can1 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_flexcan1>;
151 status = "okay";
152};
153
144&fec { 154&fec {
145 pinctrl-names = "default"; 155 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_enet>; 156 pinctrl-0 = <&pinctrl_enet>;
147 phy-mode = "rgmii"; 157 phy-mode = "rgmii";
148 phy-reset-gpios = <&gpio1 30 0>; 158 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
149 status = "okay"; 159 status = "okay";
150}; 160};
151 161
@@ -197,11 +207,6 @@
197 #gpio-cells = <2>; 207 #gpio-cells = <2>;
198 }; 208 };
199 209
200 hwmon: gsc@29 {
201 compatible = "gw,gsp";
202 reg = <0x29>;
203 };
204
205 rtc: ds1672@68 { 210 rtc: ds1672@68 {
206 compatible = "dallas,ds1672"; 211 compatible = "dallas,ds1672";
207 reg = <0x68>; 212 reg = <0x68>;
@@ -213,65 +218,6 @@
213 pinctrl-names = "default"; 218 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c2>; 219 pinctrl-0 = <&pinctrl_i2c2>;
215 status = "okay"; 220 status = "okay";
216
217 pciswitch: pex8609@3f {
218 compatible = "plx,pex8609";
219 reg = <0x3f>;
220 };
221
222 pmic: ltc3676@3c {
223 compatible = "lltc,ltc3676";
224 reg = <0x3c>;
225
226 regulators {
227 sw1_reg: ltc3676__sw1 {
228 regulator-min-microvolt = <1175000>;
229 regulator-max-microvolt = <1175000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233
234 sw2_reg: ltc3676__sw2 {
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <1800000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 sw3_reg: ltc3676__sw3 {
242 regulator-min-microvolt = <1175000>;
243 regulator-max-microvolt = <1175000>;
244 regulator-boot-on;
245 regulator-always-on;
246 };
247
248 sw4_reg: ltc3676__sw4 {
249 regulator-min-microvolt = <1500000>;
250 regulator-max-microvolt = <1500000>;
251 regulator-boot-on;
252 regulator-always-on;
253 };
254
255 ldo2_reg: ltc3676__ldo2 {
256 regulator-min-microvolt = <2500000>;
257 regulator-max-microvolt = <2500000>;
258 regulator-boot-on;
259 regulator-always-on;
260 };
261
262 ldo3_reg: ltc3676__ldo3 {
263 regulator-min-microvolt = <1800000>;
264 regulator-max-microvolt = <1800000>;
265 regulator-boot-on;
266 regulator-always-on;
267 };
268
269 ldo4_reg: ltc3676__ldo4 {
270 regulator-min-microvolt = <3000000>;
271 regulator-max-microvolt = <3000000>;
272 };
273 };
274 };
275}; 221};
276 222
277&i2c3 { 223&i2c3 {
@@ -280,11 +226,6 @@
280 pinctrl-0 = <&pinctrl_i2c3>; 226 pinctrl-0 = <&pinctrl_i2c3>;
281 status = "okay"; 227 status = "okay";
282 228
283 accelerometer: fxos8700@1e {
284 compatible = "fsl,fxos8700";
285 reg = <0x13>;
286 };
287
288 codec: sgtl5000@0a { 229 codec: sgtl5000@0a {
289 compatible = "fsl,sgtl5000"; 230 compatible = "fsl,sgtl5000";
290 reg = <0x0a>; 231 reg = <0x0a>;
@@ -297,49 +238,101 @@
297 compatible = "eeti,egalax_ts"; 238 compatible = "eeti,egalax_ts";
298 reg = <0x04>; 239 reg = <0x04>;
299 interrupt-parent = <&gpio7>; 240 interrupt-parent = <&gpio7>;
300 interrupts = <12 2>; /* gpio7_12 active low */ 241 interrupts = <12 2>;
301 wakeup-gpios = <&gpio7 12 0>; 242 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
302 }; 243 };
244};
245
246&ldb {
247 status = "okay";
303 248
304 videoin: adv7180@20 { 249 lvds-channel@0 {
305 compatible = "adi,adv7180"; 250 fsl,data-mapping = "spwg";
306 reg = <0x20>; 251 fsl,data-width = <18>;
252 status = "okay";
253
254 display-timings {
255 native-mode = <&timing0>;
256 timing0: hsd100pxn1 {
257 clock-frequency = <65000000>;
258 hactive = <1024>;
259 vactive = <768>;
260 hback-porch = <220>;
261 hfront-porch = <40>;
262 vback-porch = <21>;
263 vfront-porch = <7>;
264 hsync-len = <60>;
265 vsync-len = <10>;
266 };
267 };
307 }; 268 };
308}; 269};
309 270
310&iomuxc { 271&pcie {
311 pinctrl-names = "default"; 272 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_hog>; 273 pinctrl-0 = <&pinctrl_pcie>;
274 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
275 status = "okay";
276};
313 277
314 imx6qdl-gw52xx { 278&pwm4 {
315 pinctrl_hog: hoggrp { 279 pinctrl-names = "default";
316 fsl,pins = < 280 pinctrl-0 = <&pinctrl_pwm4>;
317 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ 281 status = "okay";
318 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ 282};
319 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ 283
320 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ 284&ssi1 {
321 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ 285 fsl,mode = "i2s-slave";
322 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ 286 status = "okay";
323 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ 287};
324 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ 288
325 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 289&uart1 {
326 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ 290 pinctrl-names = "default";
327 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ 291 pinctrl-0 = <&pinctrl_uart1>;
328 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ 292 status = "okay";
329 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ 293};
330 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ 294
331 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ 295&uart2 {
332 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ 296 pinctrl-names = "default";
333 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ 297 pinctrl-0 = <&pinctrl_uart2>;
334 >; 298 status = "okay";
335 }; 299};
300
301&uart5 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_uart5>;
304 status = "okay";
305};
306
307&usbotg {
308 vbus-supply = <&reg_usb_otg_vbus>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_usbotg>;
311 disable-over-current;
312 status = "okay";
313};
314
315&usbh1 {
316 status = "okay";
317};
318
319&usdhc3 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_usdhc3>;
322 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
323 vmmc-supply = <&reg_3p3v>;
324 status = "okay";
325};
336 326
327&iomuxc {
328 imx6qdl-gw52xx {
337 pinctrl_audmux: audmuxgrp { 329 pinctrl_audmux: audmuxgrp {
338 fsl,pins = < 330 fsl,pins = <
339 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 331 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
340 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 332 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
341 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 333 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
342 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 334 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
335 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
343 >; 336 >;
344 }; 337 };
345 338
@@ -361,6 +354,23 @@
361 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 354 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
362 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 355 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
363 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 356 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
357 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
358 >;
359 };
360
361 pinctrl_flexcan1: flexcan1grp {
362 fsl,pins = <
363 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
364 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
365 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
366 >;
367 };
368
369 pinctrl_gpio_leds: gpioledsgrp {
370 fsl,pins = <
371 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
372 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
373 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
364 >; 374 >;
365 }; 375 };
366 376
@@ -406,6 +416,18 @@
406 >; 416 >;
407 }; 417 };
408 418
419 pinctrl_pcie: pciegrp {
420 fsl,pins = <
421 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
422 >;
423 };
424
425 pinctrl_pps: ppsgrp {
426 fsl,pins = <
427 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
428 >;
429 };
430
409 pinctrl_pwm4: pwm4grp { 431 pinctrl_pwm4: pwm4grp {
410 fsl,pins = < 432 fsl,pins = <
411 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 433 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -436,6 +458,7 @@
436 pinctrl_usbotg: usbotggrp { 458 pinctrl_usbotg: usbotggrp {
437 fsl,pins = < 459 fsl,pins = <
438 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 460 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
461 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
439 >; 462 >;
440 }; 463 };
441 464
@@ -447,85 +470,8 @@
447 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 470 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
448 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 471 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
449 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 472 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
473 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
450 >; 474 >;
451 }; 475 };
452 }; 476 };
453}; 477};
454
455&ldb {
456 status = "okay";
457
458 lvds-channel@0 {
459 fsl,data-mapping = "spwg";
460 fsl,data-width = <18>;
461 status = "okay";
462
463 display-timings {
464 native-mode = <&timing0>;
465 timing0: hsd100pxn1 {
466 clock-frequency = <65000000>;
467 hactive = <1024>;
468 vactive = <768>;
469 hback-porch = <220>;
470 hfront-porch = <40>;
471 vback-porch = <21>;
472 vfront-porch = <7>;
473 hsync-len = <60>;
474 vsync-len = <10>;
475 };
476 };
477 };
478};
479
480&pcie {
481 reset-gpio = <&gpio1 29 0>;
482 status = "okay";
483};
484
485&pwm4 {
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_pwm4>;
488 status = "okay";
489};
490
491&ssi1 {
492 status = "okay";
493};
494
495&uart1 {
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_uart1>;
498 status = "okay";
499};
500
501&uart2 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_uart2>;
504 status = "okay";
505};
506
507&uart5 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_uart5>;
510 status = "okay";
511};
512
513&usbotg {
514 vbus-supply = <&reg_usb_otg_vbus>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_usbotg>;
517 disable-over-current;
518 status = "okay";
519};
520
521&usbh1 {
522 status = "okay";
523};
524
525&usdhc3 {
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_usdhc3>;
528 cd-gpios = <&gpio7 0 0>;
529 vmmc-supply = <&reg_3p3v>;
530 status = "okay";
531};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 143f84f7812c..cade1bdc97e9 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -9,21 +9,19 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 ethernet1 = &eth1; 17 ethernet1 = &eth1;
18 led0 = &led0; 18 led0 = &led0;
19 led1 = &led1; 19 led1 = &led1;
20 led2 = &led2; 20 led2 = &led2;
21 nand = &gpmi; 21 nand = &gpmi;
22 sky2 = &eth1;
23 ssi0 = &ssi1; 22 ssi0 = &ssi1;
24 usb0 = &usbh1; 23 usb0 = &usbh1;
25 usb1 = &usbotg; 24 usb1 = &usbotg;
26 usdhc2 = &usdhc3;
27 }; 25 };
28 26
29 chosen { 27 chosen {
@@ -39,23 +37,25 @@
39 37
40 leds { 38 leds {
41 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
42 42
43 led0: user1 { 43 led0: user1 {
44 label = "user1"; 44 label = "user1";
45 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 45 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
46 default-state = "on"; 46 default-state = "on";
47 linux,default-trigger = "heartbeat"; 47 linux,default-trigger = "heartbeat";
48 }; 48 };
49 49
50 led1: user2 { 50 led1: user2 {
51 label = "user2"; 51 label = "user2";
52 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 52 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
53 default-state = "off"; 53 default-state = "off";
54 }; 54 };
55 55
56 led2: user3 { 56 led2: user3 {
57 label = "user3"; 57 label = "user3";
58 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ 58 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
59 default-state = "off"; 59 default-state = "off";
60 }; 60 };
61 }; 61 };
@@ -66,7 +66,9 @@
66 66
67 pps { 67 pps {
68 compatible = "pps-gpio"; 68 compatible = "pps-gpio";
69 gpios = <&gpio1 26 0>; 69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
70 status = "okay"; 72 status = "okay";
71 }; 73 };
72 74
@@ -118,7 +120,7 @@
118 regulator-name = "usb_otg_vbus"; 120 regulator-name = "usb_otg_vbus";
119 regulator-min-microvolt = <5000000>; 121 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>; 122 regulator-max-microvolt = <5000000>;
121 gpio = <&gpio3 22 0>; 123 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
122 enable-active-high; 124 enable-active-high;
123 }; 125 };
124 }; 126 };
@@ -154,7 +156,7 @@
154 pinctrl-names = "default"; 156 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_enet>; 157 pinctrl-0 = <&pinctrl_enet>;
156 phy-mode = "rgmii"; 158 phy-mode = "rgmii";
157 phy-reset-gpios = <&gpio1 30 0>; 159 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
158 status = "okay"; 160 status = "okay";
159}; 161};
160 162
@@ -206,11 +208,6 @@
206 #gpio-cells = <2>; 208 #gpio-cells = <2>;
207 }; 209 };
208 210
209 hwmon: gsc@29 {
210 compatible = "gw,gsp";
211 reg = <0x29>;
212 };
213
214 rtc: ds1672@68 { 211 rtc: ds1672@68 {
215 compatible = "dallas,ds1672"; 212 compatible = "dallas,ds1672";
216 reg = <0x68>; 213 reg = <0x68>;
@@ -222,77 +219,6 @@
222 pinctrl-names = "default"; 219 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c2>; 220 pinctrl-0 = <&pinctrl_i2c2>;
224 status = "okay"; 221 status = "okay";
225
226 pciclkgen: si53156@6b {
227 compatible = "sil,si53156";
228 reg = <0x6b>;
229 };
230
231 pciswitch: pex8606@3f {
232 compatible = "plx,pex8606";
233 reg = <0x3f>;
234 };
235
236 pmic: ltc3676@3c {
237 compatible = "lltc,ltc3676";
238 reg = <0x3c>;
239
240 regulators {
241 /* VDD_SOC */
242 sw1_reg: ltc3676__sw1 {
243 regulator-min-microvolt = <1175000>;
244 regulator-max-microvolt = <1175000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 /* VDD_1P8 */
250 sw2_reg: ltc3676__sw2 {
251 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <1800000>;
253 regulator-boot-on;
254 regulator-always-on;
255 };
256
257 /* VDD_ARM */
258 sw3_reg: ltc3676__sw3 {
259 regulator-min-microvolt = <1175000>;
260 regulator-max-microvolt = <1175000>;
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 /* VDD_DDR */
266 sw4_reg: ltc3676__sw4 {
267 regulator-min-microvolt = <1500000>;
268 regulator-max-microvolt = <1500000>;
269 regulator-boot-on;
270 regulator-always-on;
271 };
272
273 /* VDD_2P5 */
274 ldo2_reg: ltc3676__ldo2 {
275 regulator-min-microvolt = <2500000>;
276 regulator-max-microvolt = <2500000>;
277 regulator-boot-on;
278 regulator-always-on;
279 };
280
281 /* VDD_1P8 */
282 ldo3_reg: ltc3676__ldo3 {
283 regulator-min-microvolt = <1800000>;
284 regulator-max-microvolt = <1800000>;
285 regulator-boot-on;
286 regulator-always-on;
287 };
288
289 /* VDD_HIGH */
290 ldo4_reg: ltc3676__ldo4 {
291 regulator-min-microvolt = <3000000>;
292 regulator-max-microvolt = <3000000>;
293 };
294 };
295 };
296}; 222};
297 223
298&i2c3 { 224&i2c3 {
@@ -301,11 +227,6 @@
301 pinctrl-0 = <&pinctrl_i2c3>; 227 pinctrl-0 = <&pinctrl_i2c3>;
302 status = "okay"; 228 status = "okay";
303 229
304 accelerometer: fxos8700@1e {
305 compatible = "fsl,fxos8700";
306 reg = <0x1e>;
307 };
308
309 codec: sgtl5000@0a { 230 codec: sgtl5000@0a {
310 compatible = "fsl,sgtl5000"; 231 compatible = "fsl,sgtl5000";
311 reg = <0x0a>; 232 reg = <0x0a>;
@@ -314,65 +235,110 @@
314 VDDIO-supply = <&reg_3p3v>; 235 VDDIO-supply = <&reg_3p3v>;
315 }; 236 };
316 237
317 hdmiin: adv7611@4c {
318 compatible = "adi,adv7611";
319 reg = <0x4c>;
320 };
321
322 touchscreen: egalax_ts@04 { 238 touchscreen: egalax_ts@04 {
323 compatible = "eeti,egalax_ts"; 239 compatible = "eeti,egalax_ts";
324 reg = <0x04>; 240 reg = <0x04>;
325 interrupt-parent = <&gpio1>; 241 interrupt-parent = <&gpio1>;
326 interrupts = <11 2>; /* gpio1_11 active low */ 242 interrupts = <11 2>;
327 wakeup-gpios = <&gpio1 11 0>; 243 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
328 }; 244 };
245};
329 246
330 videoout: adv7393@2a { 247&ldb {
331 compatible = "adi,adv7393"; 248 status = "okay";
332 reg = <0x2a>; 249
250 lvds-channel@1 {
251 fsl,data-mapping = "spwg";
252 fsl,data-width = <18>;
253 status = "okay";
254
255 display-timings {
256 native-mode = <&timing0>;
257 timing0: hsd100pxn1 {
258 clock-frequency = <65000000>;
259 hactive = <1024>;
260 vactive = <768>;
261 hback-porch = <220>;
262 hfront-porch = <40>;
263 vback-porch = <21>;
264 vfront-porch = <7>;
265 hsync-len = <60>;
266 vsync-len = <10>;
267 };
268 };
333 }; 269 };
270};
334 271
335 videoin: adv7180@20 { 272&pcie {
336 compatible = "adi,adv7180"; 273 pinctrl-names = "default";
337 reg = <0x20>; 274 pinctrl-0 = <&pinctrl_pcie>;
275 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
276 status = "okay";
277
278 eth1: sky2@8 { /* MAC/PHY on bus 8 */
279 compatible = "marvell,sky2";
338 }; 280 };
339}; 281};
340 282
341&iomuxc { 283&pwm4 {
342 pinctrl-names = "default"; 284 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_hog>; 285 pinctrl-0 = <&pinctrl_pwm4>;
286 status = "okay";
287};
344 288
345 imx6qdl-gw53xx { 289&ssi1 {
346 pinctrl_hog: hoggrp { 290 fsl,mode = "i2s-slave";
347 fsl,pins = < 291 status = "okay";
348 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ 292};
349 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ 293
350 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ 294&uart1 {
351 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ 295 pinctrl-names = "default";
352 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ 296 pinctrl-0 = <&pinctrl_uart1>;
353 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ 297 status = "okay";
354 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ 298};
355 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 299
356 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ 300&uart2 {
357 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ 301 pinctrl-names = "default";
358 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ 302 pinctrl-0 = <&pinctrl_uart2>;
359 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ 303 status = "okay";
360 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ 304};
361 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
362 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */
363 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
364 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
365 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */
366 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */
367 >;
368 };
369 305
306&uart5 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart5>;
309 status = "okay";
310};
311
312&usbotg {
313 vbus-supply = <&reg_usb_otg_vbus>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usbotg>;
316 disable-over-current;
317 status = "okay";
318};
319
320&usbh1 {
321 vbus-supply = <&reg_usb_h1_vbus>;
322 status = "okay";
323};
324
325&usdhc3 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_usdhc3>;
328 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
329 vmmc-supply = <&reg_3p3v>;
330 status = "okay";
331};
332
333&iomuxc {
334 imx6qdl-gw53xx {
370 pinctrl_audmux: audmuxgrp { 335 pinctrl_audmux: audmuxgrp {
371 fsl,pins = < 336 fsl,pins = <
372 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 337 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
373 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 338 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
374 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 339 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
375 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 340 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
341 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
376 >; 342 >;
377 }; 343 };
378 344
@@ -399,8 +365,17 @@
399 365
400 pinctrl_flexcan1: flexcan1grp { 366 pinctrl_flexcan1: flexcan1grp {
401 fsl,pins = < 367 fsl,pins = <
402 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 368 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
403 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 369 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
370 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
371 >;
372 };
373
374 pinctrl_gpio_leds: gpioledsgrp {
375 fsl,pins = <
376 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
377 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
378 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
404 >; 379 >;
405 }; 380 };
406 381
@@ -446,6 +421,19 @@
446 >; 421 >;
447 }; 422 };
448 423
424 pinctrl_pcie: pciegrp {
425 fsl,pins = <
426 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
427 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
428 >;
429 };
430
431 pinctrl_pps: ppsgrp {
432 fsl,pins = <
433 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
434 >;
435 };
436
449 pinctrl_pwm4: pwm4grp { 437 pinctrl_pwm4: pwm4grp {
450 fsl,pins = < 438 fsl,pins = <
451 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 439 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -476,6 +464,8 @@
476 pinctrl_usbotg: usbotggrp { 464 pinctrl_usbotg: usbotggrp {
477 fsl,pins = < 465 fsl,pins = <
478 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 466 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
467 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
468 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
479 >; 469 >;
480 }; 470 };
481 471
@@ -487,90 +477,8 @@
487 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 477 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
488 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 478 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
489 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 479 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
480 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
490 >; 481 >;
491 }; 482 };
492 }; 483 };
493}; 484};
494
495&ldb {
496 status = "okay";
497
498 lvds-channel@1 {
499 fsl,data-mapping = "spwg";
500 fsl,data-width = <18>;
501 status = "okay";
502
503 display-timings {
504 native-mode = <&timing0>;
505 timing0: hsd100pxn1 {
506 clock-frequency = <65000000>;
507 hactive = <1024>;
508 vactive = <768>;
509 hback-porch = <220>;
510 hfront-porch = <40>;
511 vback-porch = <21>;
512 vfront-porch = <7>;
513 hsync-len = <60>;
514 vsync-len = <10>;
515 };
516 };
517 };
518};
519
520&pcie {
521 reset-gpio = <&gpio1 29 0>;
522 status = "okay";
523
524 eth1: sky2@8 { /* MAC/PHY on bus 8 */
525 compatible = "marvell,sky2";
526 };
527};
528
529&pwm4 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_pwm4>;
532 status = "okay";
533};
534
535&ssi1 {
536 status = "okay";
537};
538
539&uart1 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_uart1>;
542 status = "okay";
543};
544
545&uart2 {
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_uart2>;
548 status = "okay";
549};
550
551&uart5 {
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_uart5>;
554 status = "okay";
555};
556
557&usbotg {
558 vbus-supply = <&reg_usb_otg_vbus>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_usbotg>;
561 disable-over-current;
562 status = "okay";
563};
564
565&usbh1 {
566 vbus-supply = <&reg_usb_h1_vbus>;
567 status = "okay";
568};
569
570&usdhc3 {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_usdhc3>;
573 cd-gpios = <&gpio7 0 0>;
574 vmmc-supply = <&reg_3p3v>;
575 status = "okay";
576};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 16e7ad3d98ad..cf13239a1619 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -9,21 +9,19 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/gpio/gpio.h>
13
12/ { 14/ {
13 /* these are used by bootloader for disabling nodes */ 15 /* these are used by bootloader for disabling nodes */
14 aliases { 16 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 ethernet1 = &eth1; 17 ethernet1 = &eth1;
18 led0 = &led0; 18 led0 = &led0;
19 led1 = &led1; 19 led1 = &led1;
20 led2 = &led2; 20 led2 = &led2;
21 nand = &gpmi; 21 nand = &gpmi;
22 sky2 = &eth1;
23 ssi0 = &ssi1; 22 ssi0 = &ssi1;
24 usb0 = &usbh1; 23 usb0 = &usbh1;
25 usb1 = &usbotg; 24 usb1 = &usbotg;
26 usdhc2 = &usdhc3;
27 }; 25 };
28 26
29 chosen { 27 chosen {
@@ -39,23 +37,25 @@
39 37
40 leds { 38 leds {
41 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
42 42
43 led0: user1 { 43 led0: user1 {
44 label = "user1"; 44 label = "user1";
45 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ 45 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
46 default-state = "on"; 46 default-state = "on";
47 linux,default-trigger = "heartbeat"; 47 linux,default-trigger = "heartbeat";
48 }; 48 };
49 49
50 led1: user2 { 50 led1: user2 {
51 label = "user2"; 51 label = "user2";
52 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ 52 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
53 default-state = "off"; 53 default-state = "off";
54 }; 54 };
55 55
56 led2: user3 { 56 led2: user3 {
57 label = "user3"; 57 label = "user3";
58 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ 58 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
59 default-state = "off"; 59 default-state = "off";
60 }; 60 };
61 }; 61 };
@@ -66,7 +66,9 @@
66 66
67 pps { 67 pps {
68 compatible = "pps-gpio"; 68 compatible = "pps-gpio";
69 gpios = <&gpio1 26 0>; 69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
70 status = "okay"; 72 status = "okay";
71 }; 73 };
72 74
@@ -108,7 +110,7 @@
108 regulator-name = "usb_otg_vbus"; 110 regulator-name = "usb_otg_vbus";
109 regulator-min-microvolt = <5000000>; 111 regulator-min-microvolt = <5000000>;
110 regulator-max-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>;
111 gpio = <&gpio3 22 0>; 113 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
112 enable-active-high; 114 enable-active-high;
113 }; 115 };
114 }; 116 };
@@ -144,7 +146,7 @@
144 pinctrl-names = "default"; 146 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_enet>; 147 pinctrl-0 = <&pinctrl_enet>;
146 phy-mode = "rgmii"; 148 phy-mode = "rgmii";
147 phy-reset-gpios = <&gpio1 30 0>; 149 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
148 status = "okay"; 150 status = "okay";
149}; 151};
150 152
@@ -196,11 +198,6 @@
196 #gpio-cells = <2>; 198 #gpio-cells = <2>;
197 }; 199 };
198 200
199 hwmon: gsc@29 {
200 compatible = "gw,gsp";
201 reg = <0x29>;
202 };
203
204 rtc: ds1672@68 { 201 rtc: ds1672@68 {
205 compatible = "dallas,ds1672"; 202 compatible = "dallas,ds1672";
206 reg = <0x68>; 203 reg = <0x68>;
@@ -311,16 +308,6 @@
311 }; 308 };
312 }; 309 };
313 }; 310 };
314
315 pciswitch: pex8609@3f {
316 compatible = "plx,pex8609";
317 reg = <0x3f>;
318 };
319
320 pciclkgen: si52147@6b {
321 compatible = "sil,si52147";
322 reg = <0x6b>;
323 };
324}; 311};
325 312
326&i2c3 { 313&i2c3 {
@@ -329,11 +316,6 @@
329 pinctrl-0 = <&pinctrl_i2c3>; 316 pinctrl-0 = <&pinctrl_i2c3>;
330 status = "okay"; 317 status = "okay";
331 318
332 accelerometer: fxos8700@1e {
333 compatible = "fsl,fxos8700";
334 reg = <0x1e>;
335 };
336
337 codec: sgtl5000@0a { 319 codec: sgtl5000@0a {
338 compatible = "fsl,sgtl5000"; 320 compatible = "fsl,sgtl5000";
339 reg = <0x0a>; 321 reg = <0x0a>;
@@ -342,59 +324,115 @@
342 VDDIO-supply = <&reg_3p3v>; 324 VDDIO-supply = <&reg_3p3v>;
343 }; 325 };
344 326
345 hdmiin: adv7611@4c {
346 compatible = "adi,adv7611";
347 reg = <0x4c>;
348 };
349
350 touchscreen: egalax_ts@04 { 327 touchscreen: egalax_ts@04 {
351 compatible = "eeti,egalax_ts"; 328 compatible = "eeti,egalax_ts";
352 reg = <0x04>; 329 reg = <0x04>;
353 interrupt-parent = <&gpio7>; 330 interrupt-parent = <&gpio7>;
354 interrupts = <12 2>; /* gpio7_12 active low */ 331 interrupts = <12 2>;
355 wakeup-gpios = <&gpio7 12 0>; 332 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
356 }; 333 };
334};
357 335
358 videoout: adv7393@2a { 336&ldb {
359 compatible = "adi,adv7393"; 337 status = "okay";
360 reg = <0x2a>; 338
339 lvds-channel@1 {
340 fsl,data-mapping = "spwg";
341 fsl,data-width = <18>;
342 status = "okay";
343
344 display-timings {
345 native-mode = <&timing0>;
346 timing0: hsd100pxn1 {
347 clock-frequency = <65000000>;
348 hactive = <1024>;
349 vactive = <768>;
350 hback-porch = <220>;
351 hfront-porch = <40>;
352 vback-porch = <21>;
353 vfront-porch = <7>;
354 hsync-len = <60>;
355 vsync-len = <10>;
356 };
357 };
361 }; 358 };
359};
360
361&pcie {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pcie>;
364 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
365 status = "okay";
362 366
363 videoin: adv7180@20 { 367 eth1: sky2@8 { /* MAC/PHY on bus 8 */
364 compatible = "adi,adv7180"; 368 compatible = "marvell,sky2";
365 reg = <0x20>;
366 }; 369 };
367}; 370};
368 371
369&iomuxc { 372&pwm4 {
370 pinctrl-names = "default"; 373 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_hog>; 374 pinctrl-0 = <&pinctrl_pwm4>;
375 status = "okay";
376};
372 377
373 imx6qdl-gw54xx { 378&ssi1 {
374 pinctrl_hog: hoggrp { 379 fsl,mode = "i2s-slave";
375 fsl,pins = < 380 status = "okay";
376 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ 381};
377 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ 382
378 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ 383&ssi2 {
379 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ 384 fsl,mode = "i2s-slave";
380 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ 385 status = "okay";
381 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 386};
382 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ 387
383 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ 388&uart1 {
384 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ 389 pinctrl-names = "default";
385 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ 390 pinctrl-0 = <&pinctrl_uart1>;
386 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ 391 status = "okay";
387 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ 392};
388 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ 393
389 >; 394&uart2 {
390 }; 395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_uart2>;
397 status = "okay";
398};
399
400&uart5 {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_uart5>;
403 status = "okay";
404};
405
406&usbotg {
407 vbus-supply = <&reg_usb_otg_vbus>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_usbotg>;
410 disable-over-current;
411 status = "okay";
412};
413
414&usbh1 {
415 vbus-supply = <&reg_usb_h1_vbus>;
416 status = "okay";
417};
418
419&usdhc3 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_usdhc3>;
422 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
423 vmmc-supply = <&reg_3p3v>;
424 status = "okay";
425};
391 426
427&iomuxc {
428 imx6qdl-gw54xx {
392 pinctrl_audmux: audmuxgrp { 429 pinctrl_audmux: audmuxgrp {
393 fsl,pins = < 430 fsl,pins = <
394 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 431 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
395 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 432 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
396 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 433 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
397 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 434 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
435 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
398 >; 436 >;
399 }; 437 };
400 438
@@ -421,8 +459,17 @@
421 459
422 pinctrl_flexcan1: flexcan1grp { 460 pinctrl_flexcan1: flexcan1grp {
423 fsl,pins = < 461 fsl,pins = <
424 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 462 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
425 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 463 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
464 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
465 >;
466 };
467
468 pinctrl_gpio_leds: gpioledsgrp {
469 fsl,pins = <
470 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
471 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
472 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
426 >; 473 >;
427 }; 474 };
428 475
@@ -468,6 +515,19 @@
468 >; 515 >;
469 }; 516 };
470 517
518 pinctrl_pcie: pciegrp {
519 fsl,pins = <
520 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
521 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
522 >;
523 };
524
525 pinctrl_pps: ppsgrp {
526 fsl,pins = <
527 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
528 >;
529 };
530
471 pinctrl_pwm4: pwm4grp { 531 pinctrl_pwm4: pwm4grp {
472 fsl,pins = < 532 fsl,pins = <
473 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 533 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -498,6 +558,7 @@
498 pinctrl_usbotg: usbotggrp { 558 pinctrl_usbotg: usbotggrp {
499 fsl,pins = < 559 fsl,pins = <
500 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 560 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
561 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
501 >; 562 >;
502 }; 563 };
503 564
@@ -513,90 +574,3 @@
513 }; 574 };
514 }; 575 };
515}; 576};
516
517&ldb {
518 status = "okay";
519
520 lvds-channel@1 {
521 fsl,data-mapping = "spwg";
522 fsl,data-width = <18>;
523 status = "okay";
524
525 display-timings {
526 native-mode = <&timing0>;
527 timing0: hsd100pxn1 {
528 clock-frequency = <65000000>;
529 hactive = <1024>;
530 vactive = <768>;
531 hback-porch = <220>;
532 hfront-porch = <40>;
533 vback-porch = <21>;
534 vfront-porch = <7>;
535 hsync-len = <60>;
536 vsync-len = <10>;
537 };
538 };
539 };
540};
541
542&pcie {
543 reset-gpio = <&gpio1 29 0>;
544 status = "okay";
545
546 eth1: sky2@8 { /* MAC/PHY on bus 8 */
547 compatible = "marvell,sky2";
548 };
549};
550
551&pwm4 {
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_pwm4>;
554 status = "okay";
555};
556
557&ssi1 {
558 status = "okay";
559};
560
561&ssi2 {
562 status = "okay";
563};
564
565&uart1 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_uart1>;
568 status = "okay";
569};
570
571&uart2 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_uart2>;
574 status = "okay";
575};
576
577&uart5 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_uart5>;
580 status = "okay";
581};
582
583&usbotg {
584 vbus-supply = <&reg_usb_otg_vbus>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pinctrl_usbotg>;
587 disable-over-current;
588 status = "okay";
589};
590
591&usbh1 {
592 vbus-supply = <&reg_usb_h1_vbus>;
593 status = "okay";
594};
595
596&usdhc3 {
597 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_usdhc3>;
599 cd-gpios = <&gpio7 0 0>;
600 vmmc-supply = <&reg_3p3v>;
601 status = "okay";
602};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
new file mode 100644
index 000000000000..5c6587f6c420
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 usb0 = &usbh1;
22 usb1 = &usbotg;
23 };
24
25 chosen {
26 bootargs = "console=ttymxc1,115200";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpio_leds>;
33
34 led0: user1 {
35 label = "user1";
36 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
37 default-state = "on";
38 linux,default-trigger = "heartbeat";
39 };
40
41 led1: user2 {
42 label = "user2";
43 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
44 default-state = "off";
45 };
46
47 led2: user3 {
48 label = "user3";
49 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
50 default-state = "off";
51 };
52 };
53
54 memory {
55 reg = <0x10000000 0x20000000>;
56 };
57
58 regulators {
59 compatible = "simple-bus";
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 reg_1p0v: regulator@0 {
64 compatible = "regulator-fixed";
65 reg = <0>;
66 regulator-name = "1P0V";
67 regulator-min-microvolt = <1000000>;
68 regulator-max-microvolt = <1000000>;
69 regulator-always-on;
70 };
71
72 reg_3p3v: regulator@2 {
73 compatible = "regulator-fixed";
74 reg = <2>;
75 regulator-name = "3P3V";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
80
81 reg_5p0v: regulator@3 {
82 compatible = "regulator-fixed";
83 reg = <3>;
84 regulator-name = "5P0V";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 regulator-always-on;
88 };
89 };
90};
91
92&gpmi {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_gpmi_nand>;
95 status = "okay";
96};
97
98&hdmi {
99 ddc-i2c-bus = <&i2c3>;
100 status = "okay";
101};
102
103&i2c1 {
104 clock-frequency = <100000>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c1>;
107 status = "okay";
108
109 eeprom1: eeprom@50 {
110 compatible = "atmel,24c02";
111 reg = <0x50>;
112 pagesize = <16>;
113 };
114
115 eeprom2: eeprom@51 {
116 compatible = "atmel,24c02";
117 reg = <0x51>;
118 pagesize = <16>;
119 };
120
121 eeprom3: eeprom@52 {
122 compatible = "atmel,24c02";
123 reg = <0x52>;
124 pagesize = <16>;
125 };
126
127 eeprom4: eeprom@53 {
128 compatible = "atmel,24c02";
129 reg = <0x53>;
130 pagesize = <16>;
131 };
132
133 gpio: pca9555@23 {
134 compatible = "nxp,pca9555";
135 reg = <0x23>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 };
139
140 rtc: ds1672@68 {
141 compatible = "dallas,ds1672";
142 reg = <0x68>;
143 };
144};
145
146&i2c2 {
147 clock-frequency = <100000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c2>;
150 status = "okay";
151};
152
153&i2c3 {
154 clock-frequency = <100000>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c3>;
157 status = "okay";
158};
159
160&pcie {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_pcie>;
163 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
164 status = "okay";
165};
166
167&uart2 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
170 status = "okay";
171};
172
173&uart3 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart3>;
176 status = "okay";
177};
178
179&uart5 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_uart5>;
182 status = "okay"; };
183
184&usbh1 {
185 status = "okay";
186};
187
188&iomuxc {
189 imx6qdl-gw552x {
190 pinctrl_gpio_leds: gpioledsgrp {
191 fsl,pins = <
192 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
193 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
194 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
195 >;
196 };
197
198 pinctrl_gpmi_nand: gpminandgrp {
199 fsl,pins = <
200 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
201 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
202 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
203 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
204 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
205 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
206 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
207 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
208 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
209 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
210 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
211 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
212 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
213 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
214 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
215 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
216 >;
217 };
218
219 pinctrl_i2c1: i2c1grp {
220 fsl,pins = <
221 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
222 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
223 >;
224 };
225
226 pinctrl_i2c2: i2c2grp {
227 fsl,pins = <
228 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
229 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
230 >;
231 };
232
233 pinctrl_i2c3: i2c3grp {
234 fsl,pins = <
235 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
236 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
237 >;
238 };
239
240 pinctrl_pcie: pciegrp {
241 fsl,pins = <
242 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
243 >;
244 };
245
246 pinctrl_uart2: uart2grp {
247 fsl,pins = <
248 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
249 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
250 >;
251 };
252
253 pinctrl_uart3: uart3grp {
254 fsl,pins = <
255 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
256 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
257 >;
258 };
259
260 pinctrl_uart5: uart5grp {
261 fsl,pins = <
262 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
263 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
264 >;
265 };
266 };
267};
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
new file mode 100644
index 000000000000..62841e85a91e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -0,0 +1,200 @@
1/*
2 * Copyright (C) 2013,2014 Russell King
3 */
4#include "imx6qdl-microsom.dtsi"
5#include "imx6qdl-microsom-ar8035.dtsi"
6
7/ {
8 chosen {
9 stdout-path = &uart1;
10 };
11
12 ir_recv: ir-receiver {
13 compatible = "gpio-ir-receiver";
14 gpios = <&gpio3 5 1>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
17 };
18
19 regulators {
20 compatible = "simple-bus";
21
22 reg_3p3v: 3p3v {
23 compatible = "regulator-fixed";
24 regulator-name = "3P3V";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 regulator-always-on;
28 };
29
30 reg_usbh1_vbus: usb-h1-vbus {
31 compatible = "regulator-fixed";
32 enable-active-high;
33 gpio = <&gpio1 0 0>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
36 regulator-name = "usb_h1_vbus";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 };
40
41 reg_usbotg_vbus: usb-otg-vbus {
42 compatible = "regulator-fixed";
43 enable-active-high;
44 gpio = <&gpio3 22 0>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
47 regulator-name = "usb_otg_vbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 };
51 };
52
53 sound-spdif {
54 compatible = "fsl,imx-audio-spdif";
55 model = "On-board SPDIF";
56 /* IMX6 doesn't implement this yet */
57 spdif-controller = <&spdif>;
58 spdif-out;
59 };
60};
61
62&can1 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
65 status = "okay";
66};
67
68&hdmi {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
71 ddc-i2c-bus = <&i2c2>;
72 status = "okay";
73};
74
75&i2c1 {
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
78
79 /*
80 * Not fitted on Carrier-1 board... yet
81 status = "okay";
82
83 rtc: pcf8523@68 {
84 compatible = "nxp,pcf8523";
85 reg = <0x68>;
86 };
87 */
88};
89
90&i2c2 {
91 clock-frequency = <100000>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
94 status = "okay";
95};
96
97&iomuxc {
98 hummingboard {
99 pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
100 fsl,pins = <
101 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
102 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
103 >;
104 };
105
106 pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
107 fsl,pins = <
108 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
109 >;
110 };
111
112 pinctrl_hummingboard_hdmi: hummingboard-hdmi {
113 fsl,pins = <
114 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
115 >;
116 };
117
118 pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
119 fsl,pins = <
120 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
121 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
122 >;
123 };
124
125 pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
126 fsl,pins = <
127 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
128 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
129 >;
130 };
131
132 pinctrl_hummingboard_spdif: hummingboard-spdif {
133 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
134 };
135
136 pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
137 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
138 };
139
140 pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
141 /*
142 * Similar to pinctrl_usbotg_2, but we want it
143 * pulled down for a fixed host connection.
144 */
145 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
146 };
147
148 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
149 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
150 };
151
152 pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
153 fsl,pins = <
154 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
155 >;
156 };
157
158 pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
159 fsl,pins = <
160 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
161 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
162 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
163 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
164 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
165 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
166 >;
167 };
168 };
169};
170
171&spdif {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_hummingboard_spdif>;
174 status = "okay";
175};
176
177&usbh1 {
178 disable-over-current;
179 vbus-supply = <&reg_usbh1_vbus>;
180 status = "okay";
181};
182
183&usbotg {
184 disable-over-current;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
187 vbus-supply = <&reg_usbotg_vbus>;
188 status = "okay";
189};
190
191&usdhc2 {
192 pinctrl-names = "default";
193 pinctrl-0 = <
194 &pinctrl_hummingboard_usdhc2_aux
195 &pinctrl_hummingboard_usdhc2
196 >;
197 vmmc-supply = <&reg_3p3v>;
198 cd-gpios = <&gpio1 4 0>;
199 status = "okay";
200};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 42ff525ebe13..08218120e770 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -174,6 +174,11 @@
174 status = "okay"; 174 status = "okay";
175}; 175};
176 176
177&hdmi {
178 ddc-i2c-bus = <&i2c2>;
179 status = "okay";
180};
181
177&i2c1 { 182&i2c1 {
178 clock-frequency = <100000>; 183 clock-frequency = <100000>;
179 pinctrl-names = "default"; 184 pinctrl-names = "default";
@@ -187,6 +192,25 @@
187 VDDA-supply = <&reg_2p5v>; 192 VDDA-supply = <&reg_2p5v>;
188 VDDIO-supply = <&reg_3p3v>; 193 VDDIO-supply = <&reg_3p3v>;
189 }; 194 };
195
196 rtc: rtc@6f {
197 compatible = "isil,isl1208";
198 reg = <0x6f>;
199 };
200};
201
202&i2c2 {
203 clock-frequency = <100000>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_i2c2>;
206 status = "okay";
207};
208
209&i2c3 {
210 clock-frequency = <100000>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_i2c3>;
213 status = "okay";
190}; 214};
191 215
192&iomuxc { 216&iomuxc {
@@ -266,6 +290,20 @@
266 >; 290 >;
267 }; 291 };
268 292
293 pinctrl_i2c2: i2c2grp {
294 fsl,pins = <
295 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
296 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
297 >;
298 };
299
300 pinctrl_i2c3: i2c3grp {
301 fsl,pins = <
302 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
303 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
304 >;
305 };
306
269 pinctrl_pwm1: pwm1grp { 307 pinctrl_pwm1: pwm1grp {
270 fsl,pins = < 308 fsl,pins = <
271 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 309 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 2694aa84e187..0e50bb0a6b94 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -83,7 +83,7 @@
83 }; 83 };
84 84
85 pmic@58 { 85 pmic@58 {
86 compatible = "dialog,da9063"; 86 compatible = "dlg,da9063";
87 reg = <0x58>; 87 reg = <0x58>;
88 interrupt-parent = <&gpio4>; 88 interrupt-parent = <&gpio4>;
89 interrupts = <17 0x8>; /* active-low GPIO4_17 */ 89 interrupts = <17 0x8>; /* active-low GPIO4_17 */
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index ec43dde78525..baf2f00d519a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -54,6 +54,19 @@
54 gpio = <&gpio4 10 0>; 54 gpio = <&gpio4 10 0>;
55 enable-active-high; 55 enable-active-high;
56 }; 56 };
57
58 reg_pcie: regulator@3 {
59 compatible = "regulator-fixed";
60 reg = <3>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_pcie_reg>;
63 regulator-name = "MPCIE_3V3";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 gpio = <&gpio3 19 0>;
67 regulator-always-on;
68 enable-active-high;
69 };
57 }; 70 };
58 71
59 gpio-keys { 72 gpio-keys {
@@ -314,15 +327,15 @@
314 imx6qdl-sabresd { 327 imx6qdl-sabresd {
315 pinctrl_hog: hoggrp { 328 pinctrl_hog: hoggrp {
316 fsl,pins = < 329 fsl,pins = <
317 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 330 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
318 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 331 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
319 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 332 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
320 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 333 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
321 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 334 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
322 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 335 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
323 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 336 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
324 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 337 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
325 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 338 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
326 >; 339 >;
327 }; 340 };
328 341
@@ -367,9 +380,9 @@
367 380
368 pinctrl_gpio_keys: gpio_keysgrp { 381 pinctrl_gpio_keys: gpio_keysgrp {
369 fsl,pins = < 382 fsl,pins = <
370 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 383 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
371 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 384 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
372 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 385 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
373 >; 386 >;
374 }; 387 };
375 388
@@ -396,7 +409,13 @@
396 409
397 pinctrl_pcie: pciegrp { 410 pinctrl_pcie: pciegrp {
398 fsl,pins = < 411 fsl,pins = <
399 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 412 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
413 >;
414 };
415
416 pinctrl_pcie_reg: pciereggrp {
417 fsl,pins = <
418 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
400 >; 419 >;
401 }; 420 };
402 421
@@ -468,7 +487,7 @@
468 gpio_leds { 487 gpio_leds {
469 pinctrl_gpio_leds: gpioledsgrp { 488 pinctrl_gpio_leds: gpioledsgrp {
470 fsl,pins = < 489 fsl,pins = <
471 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 490 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
472 >; 491 >;
473 }; 492 };
474 }; 493 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index c701af958006..9596ed5867e6 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -137,7 +137,9 @@
137 137
138 pcie: pcie@0x01000000 { 138 pcie: pcie@0x01000000 {
139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; 139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
140 reg = <0x01ffc000 0x4000>; /* DBI */ 140 reg = <0x01ffc000 0x04000>,
141 <0x01f00000 0x80000>;
142 reg-names = "dbi", "config";
141 #address-cells = <3>; 143 #address-cells = <3>;
142 #size-cells = <2>; 144 #size-cells = <2>;
143 device_type = "pci"; 145 device_type = "pci";
@@ -273,11 +275,14 @@
273 }; 275 };
274 276
275 ssi1: ssi@02028000 { 277 ssi1: ssi@02028000 {
278 #sound-dai-cells = <0>;
276 compatible = "fsl,imx6q-ssi", 279 compatible = "fsl,imx6q-ssi",
277 "fsl,imx51-ssi"; 280 "fsl,imx51-ssi";
278 reg = <0x02028000 0x4000>; 281 reg = <0x02028000 0x4000>;
279 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 282 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; 283 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
284 <&clks IMX6QDL_CLK_SSI1>;
285 clock-names = "ipg", "baud";
281 dmas = <&sdma 37 1 0>, 286 dmas = <&sdma 37 1 0>,
282 <&sdma 38 1 0>; 287 <&sdma 38 1 0>;
283 dma-names = "rx", "tx"; 288 dma-names = "rx", "tx";
@@ -286,11 +291,14 @@
286 }; 291 };
287 292
288 ssi2: ssi@0202c000 { 293 ssi2: ssi@0202c000 {
294 #sound-dai-cells = <0>;
289 compatible = "fsl,imx6q-ssi", 295 compatible = "fsl,imx6q-ssi",
290 "fsl,imx51-ssi"; 296 "fsl,imx51-ssi";
291 reg = <0x0202c000 0x4000>; 297 reg = <0x0202c000 0x4000>;
292 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 298 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; 299 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
300 <&clks IMX6QDL_CLK_SSI2>;
301 clock-names = "ipg", "baud";
294 dmas = <&sdma 41 1 0>, 302 dmas = <&sdma 41 1 0>,
295 <&sdma 42 1 0>; 303 <&sdma 42 1 0>;
296 dma-names = "rx", "tx"; 304 dma-names = "rx", "tx";
@@ -299,11 +307,14 @@
299 }; 307 };
300 308
301 ssi3: ssi@02030000 { 309 ssi3: ssi@02030000 {
310 #sound-dai-cells = <0>;
302 compatible = "fsl,imx6q-ssi", 311 compatible = "fsl,imx6q-ssi",
303 "fsl,imx51-ssi"; 312 "fsl,imx51-ssi";
304 reg = <0x02030000 0x4000>; 313 reg = <0x02030000 0x4000>;
305 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 314 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; 315 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
316 <&clks IMX6QDL_CLK_SSI3>;
317 clock-names = "ipg", "baud";
307 dmas = <&sdma 45 1 0>, 318 dmas = <&sdma 45 1 0>,
308 <&sdma 46 1 0>; 319 <&sdma 46 1 0>;
309 dma-names = "rx", "tx"; 320 dma-names = "rx", "tx";
@@ -396,8 +407,9 @@
396 reg = <0x02098000 0x4000>; 407 reg = <0x02098000 0x4000>;
397 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 408 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 409 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
399 <&clks IMX6QDL_CLK_GPT_IPG_PER>; 410 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
400 clock-names = "ipg", "per"; 411 <&clks IMX6QDL_CLK_GPT_3M>;
412 clock-names = "ipg", "per", "osc_per";
401 }; 413 };
402 414
403 gpio1: gpio@0209c000 { 415 gpio1: gpio@0209c000 {
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 3f9e041c0252..898d14fd765f 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -20,6 +20,13 @@
20 reg = <0x80000000 0x40000000>; 20 reg = <0x80000000 0x40000000>;
21 }; 21 };
22 22
23 backlight {
24 compatible = "pwm-backlight";
25 pwms = <&pwm1 0 5000000>;
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
28 };
29
23 leds { 30 leds {
24 compatible = "gpio-leds"; 31 compatible = "gpio-leds";
25 pinctrl-names = "default"; 32 pinctrl-names = "default";
@@ -74,6 +81,14 @@
74 regulator-max-microvolt = <4325000>; 81 regulator-max-microvolt = <4325000>;
75 regulator-boot-on; 82 regulator-boot-on;
76 }; 83 };
84
85 reg_lcd_3v3: regulator@4 {
86 compatible = "regulator-fixed";
87 reg = <4>;
88 regulator-name = "lcd-3v3";
89 gpio = <&gpio4 3 0>;
90 enable-active-high;
91 };
77 }; 92 };
78 93
79 sound { 94 sound {
@@ -329,12 +344,6 @@
329 >; 344 >;
330 }; 345 };
331 346
332 pinctrl_led: ledgrp {
333 fsl,pins = <
334 MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
335 >;
336 };
337
338 pinctrl_kpp: kppgrp { 347 pinctrl_kpp: kppgrp {
339 fsl,pins = < 348 fsl,pins = <
340 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 349 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
@@ -346,6 +355,51 @@
346 >; 355 >;
347 }; 356 };
348 357
358 pinctrl_lcd: lcdgrp {
359 fsl,pins = <
360 MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
361 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
362 MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
363 MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
364 MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
365 MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
366 MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
367 MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
368 MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
369 MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
370 MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
371 MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
372 MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
373 MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
374 MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
375 MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
376 MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
377 MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
378 MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
379 MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
380 MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
381 MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
382 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
383 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
384 MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
385 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
386 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
387 MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
388 >;
389 };
390
391 pinctrl_led: ledgrp {
392 fsl,pins = <
393 MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
394 >;
395 };
396
397 pinctrl_pwm1: pwmgrp {
398 fsl,pins = <
399 MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
400 >;
401 };
402
349 pinctrl_uart1: uart1grp { 403 pinctrl_uart1: uart1grp {
350 fsl,pins = < 404 fsl,pins = <
351 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 405 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
@@ -488,6 +542,44 @@
488 status = "okay"; 542 status = "okay";
489}; 543};
490 544
545&lcdif {
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_lcd>;
548 lcd-supply = <&reg_lcd_3v3>;
549 display = <&display0>;
550 status = "okay";
551
552 display0: display0 {
553 bits-per-pixel = <32>;
554 bus-width = <24>;
555
556 display-timings {
557 native-mode = <&timing0>;
558 timing0: timing0 {
559 clock-frequency = <33500000>;
560 hactive = <800>;
561 vactive = <480>;
562 hback-porch = <89>;
563 hfront-porch = <164>;
564 vback-porch = <23>;
565 vfront-porch = <10>;
566 hsync-len = <10>;
567 vsync-len = <10>;
568 hsync-active = <0>;
569 vsync-active = <0>;
570 de-active = <1>;
571 pixelclk-active = <0>;
572 };
573 };
574 };
575};
576
577&pwm1 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_pwm1>;
580 status = "okay";
581};
582
491&ssi2 { 583&ssi2 {
492 status = "okay"; 584 status = "okay";
493}; 585};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c75800ca8b35..dfd83e6d8087 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -226,11 +226,14 @@
226 }; 226 };
227 227
228 ssi1: ssi@02028000 { 228 ssi1: ssi@02028000 {
229 #sound-dai-cells = <0>;
229 compatible = "fsl,imx6sl-ssi", 230 compatible = "fsl,imx6sl-ssi",
230 "fsl,imx51-ssi"; 231 "fsl,imx51-ssi";
231 reg = <0x02028000 0x4000>; 232 reg = <0x02028000 0x4000>;
232 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 233 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SL_CLK_SSI1>; 234 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
235 <&clks IMX6SL_CLK_SSI1>;
236 clock-names = "ipg", "baud";
234 dmas = <&sdma 37 1 0>, 237 dmas = <&sdma 37 1 0>,
235 <&sdma 38 1 0>; 238 <&sdma 38 1 0>;
236 dma-names = "rx", "tx"; 239 dma-names = "rx", "tx";
@@ -239,11 +242,14 @@
239 }; 242 };
240 243
241 ssi2: ssi@0202c000 { 244 ssi2: ssi@0202c000 {
245 #sound-dai-cells = <0>;
242 compatible = "fsl,imx6sl-ssi", 246 compatible = "fsl,imx6sl-ssi",
243 "fsl,imx51-ssi"; 247 "fsl,imx51-ssi";
244 reg = <0x0202c000 0x4000>; 248 reg = <0x0202c000 0x4000>;
245 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 249 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clks IMX6SL_CLK_SSI2>; 250 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
251 <&clks IMX6SL_CLK_SSI2>;
252 clock-names = "ipg", "baud";
247 dmas = <&sdma 41 1 0>, 253 dmas = <&sdma 41 1 0>,
248 <&sdma 42 1 0>; 254 <&sdma 42 1 0>;
249 dma-names = "rx", "tx"; 255 dma-names = "rx", "tx";
@@ -252,11 +258,14 @@
252 }; 258 };
253 259
254 ssi3: ssi@02030000 { 260 ssi3: ssi@02030000 {
261 #sound-dai-cells = <0>;
255 compatible = "fsl,imx6sl-ssi", 262 compatible = "fsl,imx6sl-ssi",
256 "fsl,imx51-ssi"; 263 "fsl,imx51-ssi";
257 reg = <0x02030000 0x4000>; 264 reg = <0x02030000 0x4000>;
258 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 265 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clks IMX6SL_CLK_SSI3>; 266 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
267 <&clks IMX6SL_CLK_SSI3>;
268 clock-names = "ipg", "baud";
260 dmas = <&sdma 45 1 0>, 269 dmas = <&sdma 45 1 0>,
261 <&sdma 46 1 0>; 270 <&sdma 46 1 0>;
262 dma-names = "rx", "tx"; 271 dma-names = "rx", "tx";
@@ -529,6 +538,14 @@
529 }; 538 };
530 }; 539 };
531 540
541 tempmon: tempmon {
542 compatible = "fsl,imx6q-tempmon";
543 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
544 fsl,tempmon = <&anatop>;
545 fsl,tempmon-data = <&ocotp>;
546 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
547 };
548
532 usbphy1: usbphy@020c9000 { 549 usbphy1: usbphy@020c9000 {
533 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 550 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
534 reg = <0x020c9000 0x1000>; 551 reg = <0x020c9000 0x1000>;
@@ -627,8 +644,14 @@
627 }; 644 };
628 645
629 lcdif: lcdif@020f8000 { 646 lcdif: lcdif@020f8000 {
647 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
630 reg = <0x020f8000 0x4000>; 648 reg = <0x020f8000 0x4000>;
631 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 649 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
651 <&clks IMX6SL_CLK_LCDIF_AXI>,
652 <&clks IMX6SL_CLK_DUMMY>;
653 clock-names = "pix", "axi", "disp_axi";
654 status = "disabled";
632 }; 655 };
633 656
634 dcp: dcp@020fc000 { 657 dcp: dcp@020fc000 {
@@ -784,7 +807,7 @@
784 }; 807 };
785 808
786 ocotp: ocotp@021bc000 { 809 ocotp: ocotp@021bc000 {
787 compatible = "fsl,imx6sl-ocotp"; 810 compatible = "fsl,imx6sl-ocotp", "syscon";
788 reg = <0x021bc000 0x4000>; 811 reg = <0x021bc000 0x4000>;
789 }; 812 };
790 813
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index a3980d970590..82d6b34527b7 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -24,6 +24,13 @@
24 reg = <0x80000000 0x40000000>; 24 reg = <0x80000000 0x40000000>;
25 }; 25 };
26 26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
32 };
33
27 gpio-keys { 34 gpio-keys {
28 compatible = "gpio-keys"; 35 compatible = "gpio-keys";
29 pinctrl-names = "default"; 36 pinctrl-names = "default";
@@ -90,6 +97,14 @@
90 regulator-min-microvolt = <5000000>; 97 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>; 98 regulator-max-microvolt = <5000000>;
92 }; 99 };
100
101 reg_lcd_3v3: regulator@4 {
102 compatible = "regulator-fixed";
103 reg = <4>;
104 regulator-name = "lcd-3v3";
105 gpio = <&gpio3 27 0>;
106 enable-active-high;
107 };
93 }; 108 };
94 109
95 sound { 110 sound {
@@ -251,6 +266,44 @@
251 }; 266 };
252}; 267};
253 268
269&lcdif1 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_lcd>;
272 lcd-supply = <&reg_lcd_3v3>;
273 display = <&display0>;
274 status = "okay";
275
276 display0: display0 {
277 bits-per-pixel = <16>;
278 bus-width = <24>;
279
280 display-timings {
281 native-mode = <&timing0>;
282 timing0: timing0 {
283 clock-frequency = <33500000>;
284 hactive = <800>;
285 vactive = <480>;
286 hback-porch = <89>;
287 hfront-porch = <164>;
288 vback-porch = <23>;
289 vfront-porch = <10>;
290 hsync-len = <10>;
291 vsync-len = <10>;
292 hsync-active = <0>;
293 vsync-active = <0>;
294 de-active = <1>;
295 pixelclk-active = <0>;
296 };
297 };
298 };
299};
300
301&pwm3 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_pwm3>;
304 status = "okay";
305};
306
254&ssi2 { 307&ssi2 {
255 status = "okay"; 308 status = "okay";
256}; 309};
@@ -365,6 +418,46 @@
365 >; 418 >;
366 }; 419 };
367 420
421 pinctrl_lcd: lcdgrp {
422 fsl,pins = <
423 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
424 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
425 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
426 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
427 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
428 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
429 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
430 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
431 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
432 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
433 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
434 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
435 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
436 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
437 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
438 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
439 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
440 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
441 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
442 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
443 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
444 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
445 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
446 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
447 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
448 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
449 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
450 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
451 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
452 >;
453 };
454
455 pinctrl_pwm3: pwm3grp-1 {
456 fsl,pins = <
457 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
458 >;
459 };
460
368 pinctrl_vcc_sd3: vccsd3grp { 461 pinctrl_vcc_sd3: vccsd3grp {
369 fsl,pins = < 462 fsl,pins = <
370 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 463 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f4b9da65bc0f..f3e88c03b1e4 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -298,6 +298,7 @@
298 }; 298 };
299 299
300 ssi1: ssi@02028000 { 300 ssi1: ssi@02028000 {
301 #sound-dai-cells = <0>;
301 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 302 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
302 reg = <0x02028000 0x4000>; 303 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 304 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -311,6 +312,7 @@
311 }; 312 };
312 313
313 ssi2: ssi@0202c000 { 314 ssi2: ssi@0202c000 {
315 #sound-dai-cells = <0>;
314 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 316 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
315 reg = <0x0202c000 0x4000>; 317 reg = <0x0202c000 0x4000>;
316 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 318 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -324,6 +326,7 @@
324 }; 326 };
325 327
326 ssi3: ssi@02030000 { 328 ssi3: ssi@02030000 {
329 #sound-dai-cells = <0>;
327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 330 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
328 reg = <0x02030000 0x4000>; 331 reg = <0x02030000 0x4000>;
329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 332 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -418,7 +421,7 @@
418 reg = <0x02098000 0x4000>; 421 reg = <0x02098000 0x4000>;
419 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 422 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 423 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
421 <&clks IMX6SX_CLK_GPT_SERIAL>; 424 <&clks IMX6SX_CLK_GPT_3M>;
422 clock-names = "ipg", "per"; 425 clock-names = "ipg", "per";
423 }; 426 };
424 427
@@ -776,6 +779,8 @@
776 <&clks IMX6SX_CLK_ENET_PTP>; 779 <&clks IMX6SX_CLK_ENET_PTP>;
777 clock-names = "ipg", "ahb", "ptp", 780 clock-names = "ipg", "ahb", "ptp",
778 "enet_clk_ref", "enet_out"; 781 "enet_clk_ref", "enet_out";
782 fsl,num-tx-queues=<3>;
783 fsl,num-rx-queues=<3>;
779 status = "disabled"; 784 status = "disabled";
780 }; 785 };
781 786
@@ -1062,6 +1067,7 @@
1062 }; 1067 };
1063 1068
1064 lcdif1: lcdif@02220000 { 1069 lcdif1: lcdif@02220000 {
1070 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1065 reg = <0x02220000 0x4000>; 1071 reg = <0x02220000 0x4000>;
1066 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1072 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1073 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
@@ -1072,6 +1078,7 @@
1072 }; 1078 };
1073 1079
1074 lcdif2: lcdif@02224000 { 1080 lcdif2: lcdif@02224000 {
1081 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1075 reg = <0x02224000 0x4000>; 1082 reg = <0x02224000 0x4000>;
1076 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1084 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index 03d01909525b..c358b4b9a073 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -67,6 +67,8 @@
67 clock-names = "usb"; 67 clock-names = "usb";
68 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; 68 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
69 ranges; 69 ranges;
70 dma-coherent;
71 dma-ranges;
70 status = "disabled"; 72 status = "disabled";
71 73
72 dwc3@25010000 { 74 dwc3@25010000 {
@@ -76,5 +78,16 @@
76 usb-phy = <&usb1_phy>, <&usb1_phy>; 78 usb-phy = <&usb1_phy>, <&usb1_phy>;
77 }; 79 };
78 }; 80 };
81
82 dspgpio0: keystone_dsp_gpio@02620240 {
83 compatible = "ti,keystone-dsp-gpio";
84 gpio-controller;
85 #gpio-cells = <2>;
86 gpio,syscon-dev = <&devctrl 0x240>;
87 };
79 }; 88 };
80}; 89};
90
91&mdio {
92 reg = <0x24200f00 0x100>;
93};
diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi
index c73899c73118..d721f4b737f7 100644
--- a/arch/arm/boot/dts/k2hk.dtsi
+++ b/arch/arm/boot/dts/k2hk.dtsi
@@ -42,5 +42,61 @@
42 42
43 soc { 43 soc {
44 /include/ "k2hk-clocks.dtsi" 44 /include/ "k2hk-clocks.dtsi"
45
46 dspgpio0: keystone_dsp_gpio@02620240 {
47 compatible = "ti,keystone-dsp-gpio";
48 gpio-controller;
49 #gpio-cells = <2>;
50 gpio,syscon-dev = <&devctrl 0x240>;
51 };
52
53 dspgpio1: keystone_dsp_gpio@2620244 {
54 compatible = "ti,keystone-dsp-gpio";
55 gpio-controller;
56 #gpio-cells = <2>;
57 gpio,syscon-dev = <&devctrl 0x244>;
58 };
59
60 dspgpio2: keystone_dsp_gpio@2620248 {
61 compatible = "ti,keystone-dsp-gpio";
62 gpio-controller;
63 #gpio-cells = <2>;
64 gpio,syscon-dev = <&devctrl 0x248>;
65 };
66
67 dspgpio3: keystone_dsp_gpio@262024c {
68 compatible = "ti,keystone-dsp-gpio";
69 gpio-controller;
70 #gpio-cells = <2>;
71 gpio,syscon-dev = <&devctrl 0x24c>;
72 };
73
74 dspgpio4: keystone_dsp_gpio@2620250 {
75 compatible = "ti,keystone-dsp-gpio";
76 gpio-controller;
77 #gpio-cells = <2>;
78 gpio,syscon-dev = <&devctrl 0x250>;
79 };
80
81 dspgpio5: keystone_dsp_gpio@2620254 {
82 compatible = "ti,keystone-dsp-gpio";
83 gpio-controller;
84 #gpio-cells = <2>;
85 gpio,syscon-dev = <&devctrl 0x254>;
86 };
87
88 dspgpio6: keystone_dsp_gpio@2620258 {
89 compatible = "ti,keystone-dsp-gpio";
90 gpio-controller;
91 #gpio-cells = <2>;
92 gpio,syscon-dev = <&devctrl 0x258>;
93 };
94
95 dspgpio7: keystone_dsp_gpio@262025c {
96 compatible = "ti,keystone-dsp-gpio";
97 gpio-controller;
98 #gpio-cells = <2>;
99 gpio,syscon-dev = <&devctrl 0x25c>;
100 };
45 }; 101 };
46}; 102};
diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi
index 1f7f479589e1..e32c3baa77b8 100644
--- a/arch/arm/boot/dts/k2l.dtsi
+++ b/arch/arm/boot/dts/k2l.dtsi
@@ -51,5 +51,51 @@
51 clocks = <&clkuart3>; 51 clocks = <&clkuart3>;
52 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; 52 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
53 }; 53 };
54
55 dspgpio0: keystone_dsp_gpio@02620240 {
56 compatible = "ti,keystone-dsp-gpio";
57 gpio-controller;
58 #gpio-cells = <2>;
59 gpio,syscon-dev = <&devctrl 0x240>;
60 };
61
62 dspgpio1: keystone_dsp_gpio@2620244 {
63 compatible = "ti,keystone-dsp-gpio";
64 gpio-controller;
65 #gpio-cells = <2>;
66 gpio,syscon-dev = <&devctrl 0x244>;
67 };
68
69 dspgpio2: keystone_dsp_gpio@2620248 {
70 compatible = "ti,keystone-dsp-gpio";
71 gpio-controller;
72 #gpio-cells = <2>;
73 gpio,syscon-dev = <&devctrl 0x248>;
74 };
75
76 dspgpio3: keystone_dsp_gpio@262024c {
77 compatible = "ti,keystone-dsp-gpio";
78 gpio-controller;
79 #gpio-cells = <2>;
80 gpio,syscon-dev = <&devctrl 0x24c>;
81 };
54 }; 82 };
55}; 83};
84
85&spi0 {
86 ti,davinci-spi-num-cs = <5>;
87};
88
89&spi1 {
90 ti,davinci-spi-num-cs = <3>;
91};
92
93&spi2 {
94 ti,davinci-spi-num-cs = <5>;
95 /* Pin muxed. Enabled and configured by Bootloader */
96 status = "disabled";
97};
98
99&mdio {
100 reg = <0x26200f00 0x100>;
101};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 9e31fe7d31f8..5d3e83fa2242 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -172,7 +172,7 @@
172 compatible = "ti,keystone-usbphy"; 172 compatible = "ti,keystone-usbphy";
173 #address-cells = <1>; 173 #address-cells = <1>;
174 #size-cells = <1>; 174 #size-cells = <1>;
175 reg = <0x2620738 32>; 175 reg = <0x2620738 24>;
176 status = "disabled"; 176 status = "disabled";
177 }; 177 };
178 178
@@ -277,5 +277,13 @@
277 clock-names = "fck"; 277 clock-names = "fck";
278 bus_freq = <2500000>; 278 bus_freq = <2500000>;
279 }; 279 };
280
281 kirq0: keystone_irq@26202a0 {
282 compatible = "ti,keystone-irq";
283 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
284 interrupt-controller;
285 #interrupt-cells = <1>;
286 ti,syscon-dev = <&devctrl 0x2a0>;
287 };
280 }; 288 };
281}; 289};
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 8f76d28759a3..f82827d6fcff 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -123,11 +123,11 @@
123 123
124 dsa@0 { 124 dsa@0 {
125 compatible = "marvell,dsa"; 125 compatible = "marvell,dsa";
126 #address-cells = <2>; 126 #address-cells = <1>;
127 #size-cells = <0>; 127 #size-cells = <0>;
128 128
129 dsa,ethernet = <&eth0>; 129 dsa,ethernet = <&eth0port>;
130 dsa,mii-bus = <&ethphy0>; 130 dsa,mii-bus = <&mdio>;
131 131
132 switch@0 { 132 switch@0 {
133 #address-cells = <1>; 133 #address-cells = <1>;
@@ -169,17 +169,13 @@
169 169
170&mdio { 170&mdio {
171 status = "okay"; 171 status = "okay";
172
173 ethphy0: ethernet-phy@ff {
174 reg = <0xff>; /* No phy attached */
175 speed = <1000>;
176 duplex = <1>;
177 };
178}; 172};
179 173
180&eth0 { 174&eth0 {
181 status = "okay"; 175 status = "okay";
176
182 ethernet0-port@0 { 177 ethernet0-port@0 {
183 phy-handle = <&ethphy0>; 178 speed = <1000>;
179 duplex = <1>;
184 }; 180 };
185}; 181};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts
new file mode 100644
index 000000000000..f2e08b3b33ea
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts
@@ -0,0 +1,43 @@
1/*
2 * Marvell RD88F6181 A Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions for the board with the A0 or
11 * higher stepping of the SoC. The ethernet switch does not have a
12 * "wan" port.
13 */
14
15/dts-v1/;
16#include "kirkwood-rd88f6281.dtsi"
17
18/ {
19 model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
20 compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
21
22 dsa@0 {
23 switch@0 {
24 reg = <10 0>; /* MDIO address 10, switch 0 in tree */
25 };
26 };
27};
28
29&mdio {
30 status = "okay";
31
32 ethphy1: ethernet-phy@11 {
33 reg = <11>;
34 };
35};
36
37&eth1 {
38 status = "okay";
39
40 ethernet1-port@0 {
41 phy-handle = <&ethphy1>;
42 };
43};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
deleted file mode 100644
index a803bbb70bc8..000000000000
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Marvell RD88F6181 A0 Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions for the board with the A0 variant of
11 * the SoC. The ethernet switch does not have a "wan" port.
12 */
13
14/dts-v1/;
15#include "kirkwood-rd88f6281.dtsi"
16
17/ {
18 model = "Marvell RD88f6281 Reference design, with A0 SoC";
19 compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
20
21 dsa@0 {
22 switch@0 {
23 reg = <10 0>; /* MDIO address 10, switch 0 in tree */
24 };
25 };
26}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
index baeebbf1d8c7..f4272b64ed7f 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Marvell RD88F6181 A1 Board descrition 2 * Marvell RD88F6181 Z0 stepping descrition
3 * 3 *
4 * Andrew Lunn <andrew@lunn.ch> 4 * Andrew Lunn <andrew@lunn.ch>
5 * 5 *
@@ -7,17 +7,17 @@
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 * 9 *
10 * This file contains the definitions for the board with the A1 variant of 10 * This file contains the definitions for the board using the Z0
11 * the SoC. The ethernet switch has a "wan" port. 11 * stepping of the SoC. The ethernet switch has a "wan" port.
12 */ 12*/
13 13
14/dts-v1/; 14/dts-v1/;
15 15
16#include "kirkwood-rd88f6281.dtsi" 16#include "kirkwood-rd88f6281.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell RD88f6281 Reference design, with A1 SoC"; 19 model = "Marvell RD88f6281 Reference design, with Z0 SoC";
20 compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; 20 compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
21 21
22 dsa@0 { 22 dsa@0 {
23 switch@0 { 23 switch@0 {
@@ -28,4 +28,8 @@
28 }; 28 };
29 }; 29 };
30 }; 30 };
31}; \ No newline at end of file 31};
32
33&eth1 {
34 status = "disabled";
35};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
index 26cf0e0ccefd..d195e884b3b5 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -37,7 +37,6 @@
37 37
38 ocp@f1000000 { 38 ocp@f1000000 {
39 pinctrl: pin-controller@10000 { 39 pinctrl: pin-controller@10000 {
40 pinctrl-0 = <&pmx_sdio_cd>;
41 pinctrl-names = "default"; 40 pinctrl-names = "default";
42 41
43 pmx_sdio_cd: pmx-sdio-cd { 42 pmx_sdio_cd: pmx-sdio-cd {
@@ -69,8 +68,8 @@
69 #address-cells = <2>; 68 #address-cells = <2>;
70 #size-cells = <0>; 69 #size-cells = <0>;
71 70
72 dsa,ethernet = <&eth0>; 71 dsa,ethernet = <&eth0port>;
73 dsa,mii-bus = <&ethphy1>; 72 dsa,mii-bus = <&mdio>;
74 73
75 switch@0 { 74 switch@0 {
76 #address-cells = <1>; 75 #address-cells = <1>;
@@ -119,35 +118,19 @@
119 }; 118 };
120 119
121 partition@300000 { 120 partition@300000 {
122 label = "data"; 121 label = "rootfs";
123 reg = <0x0300000 0x500000>; 122 reg = <0x0300000 0x500000>;
124 }; 123 };
125}; 124};
126 125
127&mdio { 126&mdio {
128 status = "okay"; 127 status = "okay";
129
130 ethphy0: ethernet-phy@0 {
131 reg = <0>;
132 };
133
134 ethphy1: ethernet-phy@ff {
135 reg = <0xff>; /* No PHY attached */
136 speed = <1000>;
137 duple = <1>;
138 };
139}; 128};
140 129
141&eth0 { 130&eth0 {
142 status = "okay"; 131 status = "okay";
143 ethernet0-port@0 { 132 ethernet0-port@0 {
144 phy-handle = <&ethphy0>; 133 speed = <1000>;
145 }; 134 duplex = <1>;
146};
147
148&eth1 {
149 status = "okay";
150 ethernet1-port@0 {
151 phy-handle = <&ethphy1>;
152 }; 135 };
153}; 136};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index afc640cd80c5..464f09a1a4a5 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -309,7 +309,7 @@
309 marvell,tx-checksum-limit = <1600>; 309 marvell,tx-checksum-limit = <1600>;
310 status = "disabled"; 310 status = "disabled";
311 311
312 ethernet0-port@0 { 312 eth0port: ethernet0-port@0 {
313 compatible = "marvell,kirkwood-eth-port"; 313 compatible = "marvell,kirkwood-eth-port";
314 reg = <0>; 314 reg = <0>;
315 interrupts = <11>; 315 interrupts = <11>;
@@ -342,7 +342,7 @@
342 pinctrl-names = "default"; 342 pinctrl-names = "default";
343 status = "disabled"; 343 status = "disabled";
344 344
345 ethernet1-port@0 { 345 eth1port: ethernet1-port@0 {
346 compatible = "marvell,kirkwood-eth-port"; 346 compatible = "marvell,kirkwood-eth-port";
347 reg = <0>; 347 reg = <0>;
348 interrupts = <15>; 348 interrupts = <15>;
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
new file mode 100644
index 000000000000..e6539ea5a711
--- /dev/null
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -0,0 +1,110 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/include/ "skeleton.dtsi"
49
50/ {
51 interrupt-parent = <&gic>;
52
53 gic: interrupt-controller@c4301000 {
54 compatible = "arm,cortex-a9-gic";
55 reg = <0xc4301000 0x1000>,
56 <0xc4300100 0x0100>;
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 };
60
61 timer@c1109940 {
62 compatible = "amlogic,meson6-timer";
63 reg = <0xc1109940 0x14>;
64 interrupts = <0 10 1>;
65 };
66
67 soc {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges;
72
73 wdt: watchdog@c1109900 {
74 compatible = "amlogic,meson6-wdt";
75 reg = <0xc1109900 0x8>;
76 };
77
78 uart_AO: serial@c81004c0 {
79 compatible = "amlogic,meson-uart";
80 reg = <0xc81004c0 0x14>;
81 interrupts = <0 90 1>;
82 clocks = <&clk81>;
83 status = "disabled";
84 };
85
86 uart_A: serial@c81084c0 {
87 compatible = "amlogic,meson-uart";
88 reg = <0xc81084c0 0x14>;
89 interrupts = <0 90 1>;
90 clocks = <&clk81>;
91 status = "disabled";
92 };
93
94 uart_B: serial@c81084dc {
95 compatible = "amlogic,meson-uart";
96 reg = <0xc81084dc 0x14>;
97 interrupts = <0 90 1>;
98 clocks = <&clk81>;
99 status = "disabled";
100 };
101
102 uart_C: serial@c8108700 {
103 compatible = "amlogic,meson-uart";
104 reg = <0xc8108700 0x14>;
105 interrupts = <0 90 1>;
106 clocks = <&clk81>;
107 status = "disabled";
108 };
109 };
110}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
new file mode 100644
index 000000000000..dc2541faf1ec
--- /dev/null
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -0,0 +1,66 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49/include/ "meson6.dtsi"
50
51/ {
52 model = "Geniatech ATV1200";
53 compatible = "geniatech,atv1200";
54
55 aliases {
56 serial0 = &uart_AO;
57 };
58
59 memory {
60 reg = <0x40000000 0x80000000>;
61 };
62};
63
64&uart_AO {
65 status = "okay";
66};
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
new file mode 100644
index 000000000000..4ba49127779f
--- /dev/null
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/include/ "meson.dtsi"
49
50/ {
51 model = "Amlogic Meson6 SoC";
52 compatible = "amlogic,meson6";
53
54 interrupt-parent = <&gic>;
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 cpu@200 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a9";
63 reg = <0x200>;
64 };
65
66 cpu@201 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a9";
69 reg = <0x201>;
70 };
71 };
72
73 clk81: clk@0 {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <200000000>;
77 };
78}; /* end of / */
diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts
index 443b4467de15..0da047013120 100644
--- a/arch/arm/boot/dts/mt6589-aquaris5.dts
+++ b/arch/arm/boot/dts/mt6589-aquaris5.dts
@@ -18,6 +18,11 @@
18 18
19/ { 19/ {
20 model = "bq Aquaris5"; 20 model = "bq Aquaris5";
21 compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
22
23 chosen {
24 bootargs = "earlyprintk";
25 };
21 26
22 memory { 27 memory {
23 reg = <0x80000000 0x40000000>; 28 reg = <0x80000000 0x40000000>;
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index d0297a051549..e3c7600ddb38 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -81,8 +81,8 @@
81 clock-names = "system-clk", "rtc-clk"; 81 clock-names = "system-clk", "rtc-clk";
82 }; 82 };
83 83
84 gic: interrupt-controller@10212000 { 84 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a15-gic"; 85 compatible = "arm,cortex-a7-gic";
86 interrupt-controller; 86 interrupt-controller;
87 #interrupt-cells = <3>; 87 #interrupt-cells = <3>;
88 reg = <0x10211000 0x1000>, 88 reg = <0x10211000 0x1000>,
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 8f8c07da4ac1..59d1c297bb30 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -75,7 +75,6 @@
75 compatible = "ti,omap2-intc"; 75 compatible = "ti,omap2-intc";
76 interrupt-controller; 76 interrupt-controller;
77 #interrupt-cells = <1>; 77 #interrupt-cells = <1>;
78 ti,intc-size = <96>;
79 reg = <0x480FE000 0x1000>; 78 reg = <0x480FE000 0x1000>;
80 }; 79 };
81 80
diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts
index 21baec154b78..b604d26bd48c 100644
--- a/arch/arm/boot/dts/omap2420-n810.dts
+++ b/arch/arm/boot/dts/omap2420-n810.dts
@@ -6,3 +6,10 @@
6 model = "Nokia N810"; 6 model = "Nokia N810";
7 compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; 7 compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";
8}; 8};
9
10&i2c2 {
11 aic3x@18 {
12 compatible = "tlv320aic3x";
13 reg = <0x18>;
14 };
15};
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 89608b206519..24c50db2a478 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -27,6 +27,12 @@
27 27
28&i2c1 { 28&i2c1 {
29 clock-frequency = <400000>; 29 clock-frequency = <400000>;
30
31 pmic@72 {
32 compatible = "menelaus";
33 reg = <0x72>;
34 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
35 };
30}; 36};
31 37
32&i2c2 { 38&i2c2 {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 9be3c1266378..ae89aad01595 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -159,6 +159,14 @@
159 ti,hwmods = "mailbox"; 159 ti,hwmods = "mailbox";
160 ti,mbox-num-users = <4>; 160 ti,mbox-num-users = <4>;
161 ti,mbox-num-fifos = <6>; 161 ti,mbox-num-fifos = <6>;
162 mbox_dsp: dsp {
163 ti,mbox-tx = <0 0 0>;
164 ti,mbox-rx = <1 0 0>;
165 };
166 mbox_iva: iva {
167 ti,mbox-tx = <2 1 3>;
168 ti,mbox-rx = <3 1 3>;
169 };
162 }; 170 };
163 171
164 timer1: timer@48028000 { 172 timer1: timer@48028000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 1a00f15d9096..b56d71611026 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -249,6 +249,10 @@
249 ti,hwmods = "mailbox"; 249 ti,hwmods = "mailbox";
250 ti,mbox-num-users = <4>; 250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <6>; 251 ti,mbox-num-fifos = <6>;
252 mbox_dsp: dsp {
253 ti,mbox-tx = <0 0 0>;
254 ti,mbox-rx = <1 0 0>;
255 };
252 }; 256 };
253 257
254 timer1: timer@49018000 { 258 timer1: timer@49018000 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 1becefce821b..06a8aec4e6ea 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -174,8 +174,8 @@
174 174
175 uart3_pins: pinmux_uart3_pins { 175 uart3_pins: pinmux_uart3_pins {
176 pinctrl-single,pins = < 176 pinctrl-single,pins = <
177 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 177 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
178 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ 178 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
179 >; 179 >;
180 }; 180 };
181 181
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dtsi
index 021311f7964b..fd34f913ace3 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -26,6 +26,10 @@
26 reg = <0x80000000 0x20000000>; /* 512 MB */ 26 reg = <0x80000000 0x20000000>; /* 512 MB */
27 }; 27 };
28 28
29 aliases {
30 display0 = &lcd;
31 };
32
29 gpio-keys { 33 gpio-keys {
30 compatible = "gpio-keys"; 34 compatible = "gpio-keys";
31 35
@@ -74,9 +78,30 @@
74 }; 78 };
75 }; 79 };
76 }; 80 };
81
82 hsusb2_phy: hsusb2_phy {
83 compatible = "usb-nop-xceiv";
84 reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
85 };
77}; 86};
78 87
79&omap3_pmx_core { 88&omap3_pmx_core {
89 pinctrl-names = "default";
90 pinctrl-0 = <
91 &hsusb2_pins
92 >;
93
94 hsusb2_pins: pinmux_hsusb2_pins {
95 pinctrl-single,pins = <
96 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
97 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
98 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
99 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
100 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
101 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
102 >;
103 };
104
80 uart1_pins: pinmux_uart1_pins { 105 uart1_pins: pinmux_uart1_pins {
81 pinctrl-single,pins = < 106 pinctrl-single,pins = <
82 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 107 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
@@ -141,12 +166,31 @@
141 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 166 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
142 >; 167 >;
143 }; 168 };
169};
170
171&omap3_pmx_core2 {
172 pinctrl-names = "default";
173 pinctrl-0 = <
174 &hsusb2_2_pins
175 >;
176
177 hsusb2_2_pins: pinmux_hsusb2_2_pins {
178 pinctrl-single,pins = <
179 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
180 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
181 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
182 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
183 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
184 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
185 >;
186 };
144 187
145 spi_gpio_pins: spi_gpio_pinmux { 188 spi_gpio_pins: spi_gpio_pinmux {
146 pinctrl-single,pins = <0x5a8 (PIN_OUTPUT | MUX_MODE4) /* clk */ 189 pinctrl-single,pins = <
147 0x5b6 (PIN_OUTPUT | MUX_MODE4) /* cs */ 190 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */
148 0x5b8 (PIN_OUTPUT | MUX_MODE4) /* tx */ 191 OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */
149 0x5b4 (PIN_INPUT | MUX_MODE4) /* rx */ 192 OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */
193 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */
150 >; 194 >;
151 }; 195 };
152}; 196};
@@ -196,6 +240,9 @@
196 #size-cells = <0>; 240 #size-cells = <0>;
197 reg = <0x45>; 241 reg = <0x45>;
198 242
243 gpio-controller;
244 #gpio-cells = <2>;
245
199 gta04_led0: red_aux@0 { 246 gta04_led0: red_aux@0 {
200 label = "gta04:red:aux"; 247 label = "gta04:red:aux";
201 reg = <0x0>; 248 reg = <0x0>;
@@ -216,11 +263,16 @@
216 label = "gta04:green:power"; 263 label = "gta04:green:power";
217 reg = <0x4>; 264 reg = <0x4>;
218 }; 265 };
266
267 wifi_reset: wifi_reset@6 {
268 reg = <0x6>;
269 compatible = "gpio";
270 };
219 }; 271 };
220 272
221 /* compass aka magnetometer */ 273 /* compass aka magnetometer */
222 hmc5843@1e { 274 hmc5843@1e {
223 compatible = "honeywell,hmc5843"; 275 compatible = "honeywell,hmc5883l";
224 reg = <0x1e>; 276 reg = <0x1e>;
225 }; 277 };
226 278
@@ -248,6 +300,14 @@
248 power = <50>; 300 power = <50>;
249}; 301};
250 302
303&usbhshost {
304 port2-mode = "ehci-phy";
305};
306
307&usbhsehci {
308 phys = <0 &hsusb2_phy>;
309};
310
251&mmc1 { 311&mmc1 {
252 pinctrl-names = "default"; 312 pinctrl-names = "default";
253 pinctrl-0 = <&mmc1_pins>; 313 pinctrl-0 = <&mmc1_pins>;
@@ -286,11 +346,37 @@
286 bb_uamp = <150>; 346 bb_uamp = <150>;
287}; 347};
288 348
349/* spare */
350&vaux1 {
351 regulator-min-microvolt = <2500000>;
352 regulator-max-microvolt = <3000000>;
353};
354
355/* sensors */
356&vaux2 {
357 regulator-min-microvolt = <2800000>;
358 regulator-max-microvolt = <2800000>;
359 regulator-always-on;
360};
361
362/* camera */
363&vaux3 {
364 regulator-min-microvolt = <2500000>;
365 regulator-max-microvolt = <2500000>;
366};
367
368/* WLAN/BT */
289&vaux4 { 369&vaux4 {
290 regulator-min-microvolt = <2800000>; 370 regulator-min-microvolt = <2800000>;
291 regulator-max-microvolt = <3150000>; 371 regulator-max-microvolt = <3150000>;
292}; 372};
293 373
374/* GPS LNA */
375&vsim {
376 regulator-min-microvolt = <2800000>;
377 regulator-max-microvolt = <3150000>;
378};
379
294/* Needed to power the DPI pins */ 380/* Needed to power the DPI pins */
295&vpll2 { 381&vpll2 {
296 regulator-always-on; 382 regulator-always-on;
@@ -309,3 +395,57 @@
309 }; 395 };
310 }; 396 };
311}; 397};
398
399&gpmc {
400 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
401
402 nand@0,0 {
403 reg = <0 0 0>; /* CS0, offset 0 */
404 nand-bus-width = <16>;
405 ti,nand-ecc-opt = "bch8";
406
407 gpmc,sync-clk-ps = <0>;
408 gpmc,cs-on-ns = <0>;
409 gpmc,cs-rd-off-ns = <44>;
410 gpmc,cs-wr-off-ns = <44>;
411 gpmc,adv-on-ns = <6>;
412 gpmc,adv-rd-off-ns = <34>;
413 gpmc,adv-wr-off-ns = <44>;
414 gpmc,we-off-ns = <40>;
415 gpmc,oe-off-ns = <54>;
416 gpmc,access-ns = <64>;
417 gpmc,rd-cycle-ns = <82>;
418 gpmc,wr-cycle-ns = <82>;
419 gpmc,wr-access-ns = <40>;
420 gpmc,wr-data-mux-bus-ns = <0>;
421 gpmc,device-width = <2>;
422
423 #address-cells = <1>;
424 #size-cells = <1>;
425
426 x-loader@0 {
427 label = "X-Loader";
428 reg = <0 0x80000>;
429 };
430
431 bootloaders@80000 {
432 label = "U-Boot";
433 reg = <0x80000 0x1e0000>;
434 };
435
436 bootloaders_env@260000 {
437 label = "U-Boot Env";
438 reg = <0x260000 0x20000>;
439 };
440
441 kernel@280000 {
442 label = "Kernel";
443 reg = <0x280000 0x400000>;
444 };
445
446 filesystem@680000 {
447 label = "File System";
448 reg = <0x680000 0xf980000>;
449 };
450 };
451};
diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/omap3-gta04a3.dts
new file mode 100644
index 000000000000..3099a892cf50
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a3.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap3-gta04.dtsi"
10
11/ {
12 model = "Goldelico GTA04A3";
13};
14
15&i2c2 {
16
17 /* alternate accelerometer that might be installed on some GTA04A3 boards */
18 lis302@1d {
19 compatible = "st,lis331dlh", "st,lis3lv02d";
20 reg = <0x1d>;
21 interrupt-parent = <&gpio3>;
22 interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
23 Vdd-supply = <&vaux2>;
24 Vdd_IO-supply = <&vaux2>;
25
26 st,click-single-x;
27 st,click-single-y;
28 st,click-single-z;
29 st,click-thresh-x = <8>;
30 st,click-thresh-y = <8>;
31 st,click-thresh-z = <10>;
32 st,click-click-time-limit = <9>;
33 st,click-latency = <50>;
34 st,irq1-click;
35 st,wakeup-x-lo;
36 st,wakeup-x-hi;
37 st,wakeup-y-lo;
38 st,wakeup-y-hi;
39 st,wakeup-z-lo;
40 st,wakeup-z-hi;
41 st,min-limit-x = <32>;
42 st,min-limit-y = <3>;
43 st,min-limit-z = <3>;
44 st,max-limit-x = <3>;
45 st,max-limit-y = <32>;
46 st,max-limit-z = <32>;
47 };
48};
diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/omap3-gta04a4.dts
new file mode 100644
index 000000000000..c918bb1f0529
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a4.dts
@@ -0,0 +1,13 @@
1/*
2 * Copyright (C) 2014 Marek Belisko <marek@goldelico.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap3-gta04.dtsi"
10
11/ {
12 model = "Goldelico GTA04A4";
13};
diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts
new file mode 100644
index 000000000000..52b386f6865b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a5.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap3-gta04.dtsi"
10
11/ {
12 model = "Goldelico GTA04A5";
13
14 sound {
15 ti,jack-det-gpio = <&twl_gpio 2 0>; /* GTA04A5 only */
16 };
17};
diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi
new file mode 100644
index 000000000000..bd66545ef954
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha-common.dtsi
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-tao3530.dtsi"
11
12/ {
13 gpio_poweroff {
14 pinctrl-names = "default";
15 pinctrl-0 = <&poweroff_pins>;
16
17 compatible = "gpio-poweroff";
18 gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */
19 };
20};
21
22&omap3_pmx_core {
23 sound2_pins: pinmux_sound2_pins {
24 pinctrl-single,pins = <
25 OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */
26 >;
27 };
28
29 led_blue_pins: pinmux_led_blue_pins {
30 pinctrl-single,pins = <
31 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */
32 >;
33 };
34
35 led_green_pins: pinmux_led_green_pins {
36 pinctrl-single,pins = <
37 OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */
38 >;
39 };
40
41 led_red_pins: pinmux_led_red_pins {
42 pinctrl-single,pins = <
43 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */
44 >;
45 };
46
47 poweroff_pins: pinmux_poweroff_pins {
48 pinctrl-single,pins = <
49 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */
50 >;
51 };
52
53 powerdown_input_pins: pinmux_powerdown_input_pins {
54 pinctrl-single,pins = <
55 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */
56 >;
57 };
58
59 fpga_boot0_pins: fpga_boot0_pins {
60 pinctrl-single,pins = <
61 OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */
62 OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */
63 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */
64 OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */
65 >;
66 };
67
68 fpga_boot1_pins: fpga_boot1_pins {
69 pinctrl-single,pins = <
70 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */
71 OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */
72 OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */
73 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */
74 >;
75 };
76};
77
78/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
79&i2c2 {
80 status = "disabled";
81};
82
83&i2c3 {
84 clock-frequency = <100000>;
85
86 pinctrl-names = "default";
87 pinctrl-0 = <&i2c3_pins>;
88};
diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts
new file mode 100644
index 000000000000..11aa28d73f3a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha-lcd.dts
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-ha-common.dtsi"
11
12/ {
13 model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM";
14 compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
15};
16
17&omap3_pmx_core {
18 pinctrl-names = "default";
19 pinctrl-0 = <
20 &hsusbb2_pins
21 &powerdown_input_pins
22 &fpga_boot0_pins
23 &fpga_boot1_pins
24 &led_blue_pins
25 &led_green_pins
26 &led_red_pins
27 &touchscreen_wake_pins
28 >;
29
30 touchscreen_irq_pins: pinmux_touchscreen_irq_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */
33 >;
34 };
35
36 touchscreen_wake_pins: pinmux_touchscreen_wake_pins {
37 pinctrl-single,pins = <
38 OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */
39 >;
40 };
41
42 dss_dpi_pins: pinmux_dss_dpi_pins {
43 pinctrl-single,pins = <
44 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
45 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
46 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
47 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
48 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
49 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
50 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
51 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
52 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
53 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
54 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
55 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
56 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
57 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
58 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
59 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
60 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
61 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
62 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
63 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
64 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
65 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
66 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
67 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
68 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
69 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
70 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
71 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
72 >;
73 };
74
75 lte430_pins: pinmux_lte430_pins {
76 pinctrl-single,pins = <
77 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
78 >;
79 };
80
81 backlight_pins: pinmux_backlight_pins {
82 pinctrl-single,pins = <
83 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
84 >;
85 };
86};
87
88/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
89&i2c2 {
90 status = "disabled";
91};
92
93&i2c3 {
94 clock-frequency = <100000>;
95
96 pinctrl-names = "default";
97 pinctrl-0 = <&i2c3_pins>;
98};
99
100/* Needed to power the DPI pins */
101&vpll2 {
102 regulator-always-on;
103};
104
105&dss {
106 status = "ok";
107
108 pinctrl-names = "default";
109 pinctrl-0 = <&dss_dpi_pins>;
110
111 port {
112 dpi_out: endpoint {
113 remote-endpoint = <&lcd_in>;
114 data-lines = <24>;
115 };
116 };
117};
118
119/ {
120 aliases {
121 display0 = &lcd0;
122 };
123
124 lcd0: display@0 {
125 compatible = "panel-dpi";
126 label = "lcd";
127
128 pinctrl-names = "default";
129 pinctrl-0 = <&lte430_pins>;
130 enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */
131
132 port {
133 lcd_in: endpoint {
134 remote-endpoint = <&dpi_out>;
135 };
136 };
137
138 panel-timing {
139 clock-frequency = <31250000>;
140 hactive = <800>;
141 vactive = <480>;
142 hfront-porch = <40>;
143 hback-porch = <86>;
144 hsync-len = <1>;
145 vback-porch = <30>;
146 vfront-porch = <13>;
147 vsync-len = <3>;
148
149 hsync-active = <0>;
150 vsync-active = <0>;
151 de-active = <1>;
152 pixelclk-active = <1>;
153 };
154 };
155
156 backlight {
157 compatible = "gpio-backlight";
158
159 pinctrl-names = "default";
160 pinctrl-0 = <&backlight_pins>;
161 gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */
162
163 default-on;
164 };
165};
diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts
new file mode 100644
index 000000000000..fde325688fb9
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ha.dts
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-ha-common.dtsi"
11
12/ {
13 model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM";
14 compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
15};
16
17&omap3_pmx_core {
18 pinctrl-names = "default";
19 pinctrl-0 = <
20 &hsusbb2_pins
21 &powerdown_input_pins
22 &fpga_boot0_pins
23 &fpga_boot1_pins
24 &led_blue_pins
25 &led_green_pins
26 &led_red_pins
27 >;
28};
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index af272c156e21..72dca0b7904d 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -159,6 +159,11 @@
159 reg = <0x48>; 159 reg = <0x48>;
160 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 160 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
161 interrupt-parent = <&intc>; 161 interrupt-parent = <&intc>;
162
163 twl_power: power {
164 compatible = "ti,twl4030-power-idle";
165 ti,use_poweroff;
166 };
162 }; 167 };
163}; 168};
164 169
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 4361777a08d8..9b0494a8ab45 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -134,24 +134,32 @@
134 >; 134 >;
135 }; 135 };
136 136
137 ethernet_pins: pinmux_ethernet_pins {
138 pinctrl-single,pins = <
139 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
140 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
141 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
142 >;
143 };
144
137 i2c1_pins: pinmux_i2c1_pins { 145 i2c1_pins: pinmux_i2c1_pins {
138 pinctrl-single,pins = < 146 pinctrl-single,pins = <
139 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ 147 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
140 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ 148 0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
141 >; 149 >;
142 }; 150 };
143 151
144 i2c2_pins: pinmux_i2c2_pins { 152 i2c2_pins: pinmux_i2c2_pins {
145 pinctrl-single,pins = < 153 pinctrl-single,pins = <
146 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ 154 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
147 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ 155 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
148 >; 156 >;
149 }; 157 };
150 158
151 i2c3_pins: pinmux_i2c3_pins { 159 i2c3_pins: pinmux_i2c3_pins {
152 pinctrl-single,pins = < 160 pinctrl-single,pins = <
153 0x192 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ 161 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
154 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ 162 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
155 >; 163 >;
156 }; 164 };
157 165
@@ -578,6 +586,8 @@
578 586
579&gpmc { 587&gpmc {
580 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ 588 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
589 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
590 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
581 591
582 /* gpio-irq for dma: 65 */ 592 /* gpio-irq for dma: 65 */
583 593
@@ -646,6 +656,38 @@
646 reg = <0x004c0000 0x0fb40000>; 656 reg = <0x004c0000 0x0fb40000>;
647 }; 657 };
648 }; 658 };
659
660 ethernet@gpmc {
661 compatible = "smsc,lan91c94";
662 interrupt-parent = <&gpio2>;
663 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
664 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
665 bank-width = <2>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&ethernet_pins>;
668 gpmc,device-width = <2>;
669 gpmc,sync-clk-ps = <0>;
670 gpmc,cs-on-ns = <0>;
671 gpmc,cs-rd-off-ns = <48>;
672 gpmc,cs-wr-off-ns = <24>;
673 gpmc,adv-on-ns = <0>;
674 gpmc,adv-rd-off-ns = <0>;
675 gpmc,adv-wr-off-ns = <0>;
676 gpmc,we-on-ns = <12>;
677 gpmc,we-off-ns = <18>;
678 gpmc,oe-on-ns = <12>;
679 gpmc,oe-off-ns = <48>;
680 gpmc,page-burst-access-ns = <0>;
681 gpmc,access-ns = <42>;
682 gpmc,rd-cycle-ns = <180>;
683 gpmc,wr-cycle-ns = <180>;
684 gpmc,bus-turnaround-ns = <0>;
685 gpmc,cycle2cycle-delay-ns = <0>;
686 gpmc,wait-monitoring-ns = <0>;
687 gpmc,clk-activation-ns = <0>;
688 gpmc,wr-access-ns = <0>;
689 gpmc,wr-data-mux-bus-ns = <12>;
690 };
649}; 691};
650 692
651&mcspi1 { 693&mcspi1 {
diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
index 5831bcc52966..520453d95704 100644
--- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
@@ -36,8 +36,8 @@
36 36
37 uart3_pins: pinmux_uart3_pins { 37 uart3_pins: pinmux_uart3_pins {
38 pinctrl-single,pins = < 38 pinctrl-single,pins = <
39 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 39 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
40 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 40 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
41 >; 41 >;
42 }; 42 };
43}; 43};
@@ -88,6 +88,7 @@
88}; 88};
89 89
90&uart3 { 90&uart3 {
91 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
91 pinctrl-names = "default"; 92 pinctrl-names = "default";
92 pinctrl-0 = <&uart3_pins>; 93 pinctrl-0 = <&uart3_pins>;
93}; 94};
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
new file mode 100644
index 000000000000..b30f387d3a83
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -0,0 +1,337 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/dts-v1/;
10
11#include "omap34xx-hs.dtsi"
12
13/ {
14 cpus {
15 cpu@0 {
16 cpu0-supply = <&vcc>;
17 };
18 };
19
20 memory {
21 device_type = "memory";
22 reg = <0x80000000 0x10000000>; /* 256 MB */
23 };
24
25 /* HS USB Port 2 Power */
26 hsusb2_power: hsusb2_power_reg {
27 compatible = "regulator-fixed";
28 regulator-name = "hsusb2_vbus";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
32 startup-delay-us = <70000>;
33 };
34
35 /* HS USB Host PHY on PORT 2 */
36 hsusb2_phy: hsusb2_phy {
37 compatible = "usb-nop-xceiv";
38 reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */
39 vcc-supply = <&hsusb2_power>;
40 };
41
42 sound {
43 compatible = "ti,omap-twl4030";
44 ti,model = "omap3beagle";
45
46 /* McBSP2 is used for onboard sound, same as on beagle */
47 ti,mcbsp = <&mcbsp2>;
48 ti,codec = <&twl_audio>;
49 };
50
51 /* Regulator to enable/switch the vcc of the Wifi module */
52 mmc2_sdio_poweron: regulator-mmc2-sdio-poweron {
53 compatible = "regulator-fixed";
54 regulator-name = "regulator-mmc2-sdio-poweron";
55 regulator-min-microvolt = <3150000>;
56 regulator-max-microvolt = <3150000>;
57 gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */
58 enable-active-low;
59 startup-delay-us = <10000>;
60 };
61};
62
63&omap3_pmx_core {
64 hsusbb2_pins: pinmux_hsusbb2_pins {
65 pinctrl-single,pins = <
66 OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
67 OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
68 OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
69 OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
70 OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
71 OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
72 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
73 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
74 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
75 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
76 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
77 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
78 >;
79 };
80
81 mmc1_pins: pinmux_mmc1_pins {
82 pinctrl-single,pins = <
83 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
84 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
85 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
86 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
87 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
88 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
89 OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
90 OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
91 OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
92 OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
93 >;
94 };
95
96 mmc2_pins: pinmux_mmc2_pins {
97 pinctrl-single,pins = <
98 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
99 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
100 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
101 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
102 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
103 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
104 >;
105 };
106
107 /* wlan GPIO output for WLAN_EN */
108 wlan_gpio: pinmux_wlan_gpio {
109 pinctrl-single,pins = <
110 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */
111 >;
112 };
113
114 uart3_pins: pinmux_uart3_pins {
115 pinctrl-single,pins = <
116 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
117 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
118 >;
119 };
120
121 i2c3_pins: pinmux_i2c3_pins {
122 pinctrl-single,pins = <
123 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */
124 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */
125 >;
126 };
127
128 mcspi1_pins: pinmux_mcspi1_pins {
129 pinctrl-single,pins = <
130 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
131 OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
132 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
133 OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
134 >;
135 };
136
137 mcspi3_pins: pinmux_mcspi3_pins {
138 pinctrl-single,pins = <
139 OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */
140 OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */
141 OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */
142 OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */
143 >;
144 };
145
146 mcbsp3_pins: pinmux_mcbsp3_pins {
147 pinctrl-single,pins = <
148 OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */
149 OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */
150 OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */
151 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */
152 >;
153 };
154};
155
156/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */
157&mcbsp1 {
158 status = "disabled";
159};
160
161&mcbsp2 {
162 status = "okay";
163};
164
165&i2c1 {
166 clock-frequency = <2600000>;
167
168 twl: twl@48 {
169 reg = <0x48>;
170 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
171 interrupt-parent = <&intc>;
172
173 twl_audio: audio {
174 compatible = "ti,twl4030-audio";
175 codec {
176 };
177 };
178 };
179};
180
181&i2c3 {
182 clock-frequency = <100000>;
183
184 pinctrl-names = "default";
185 pinctrl-0 = <&i2c3_pins>;
186};
187
188&mcspi1 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&mcspi1_pins>;
191
192 spidev@0 {
193 compatible = "spidev";
194 spi-max-frequency = <48000000>;
195 reg = <0>;
196 spi-cpha;
197 };
198};
199
200&mcspi3 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&mcspi3_pins>;
203
204 spidev@0 {
205 compatible = "spidev";
206 spi-max-frequency = <48000000>;
207 reg = <0>;
208 spi-cpha;
209 };
210};
211
212#include "twl4030.dtsi"
213#include "twl4030_omap3.dtsi"
214
215&mmc1 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&mmc1_pins>;
218 vmmc-supply = <&vmmc1>;
219 vmmc_aux-supply = <&vsim>;
220 cd-gpios = <&twl_gpio 0 0>;
221 bus-width = <8>;
222};
223
224// WiFi (Marvell 88W8686) on MMC2/SDIO
225&mmc2 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&mmc2_pins>;
228 vmmc-supply = <&mmc2_sdio_poweron>;
229 non-removable;
230 bus-width = <4>;
231 cap-power-off-card;
232};
233
234&mmc3 {
235 status = "disabled";
236};
237
238&usbhshost {
239 port2-mode = "ehci-phy";
240};
241
242&usbhsehci {
243 phys = <0 &hsusb2_phy>;
244};
245
246&twl_gpio {
247 ti,use-leds;
248 /* pullups: BIT(1) */
249 ti,pullups = <0x000002>;
250 /*
251 * pulldowns:
252 * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
253 * BIT(15), BIT(16), BIT(17)
254 */
255 ti,pulldowns = <0x03a1c4>;
256};
257
258&uart3 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&uart3_pins>;
261};
262
263&mcbsp3 {
264 status = "okay";
265 pinctrl-names = "default";
266 pinctrl-0 = <&mcbsp3_pins>;
267};
268
269&gpmc {
270 ranges = <0 0 0x00000000 0x01000000>;
271
272 nand@0,0 {
273 reg = <0 0 0>; /* CS0, offset 0 */
274 nand-bus-width = <16>;
275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
276 ti,nand-ecc-opt = "sw";
277
278 gpmc,cs-on-ns = <0>;
279 gpmc,cs-rd-off-ns = <36>;
280 gpmc,cs-wr-off-ns = <36>;
281 gpmc,adv-on-ns = <6>;
282 gpmc,adv-rd-off-ns = <24>;
283 gpmc,adv-wr-off-ns = <36>;
284 gpmc,oe-on-ns = <6>;
285 gpmc,oe-off-ns = <48>;
286 gpmc,we-on-ns = <6>;
287 gpmc,we-off-ns = <30>;
288 gpmc,rd-cycle-ns = <72>;
289 gpmc,wr-cycle-ns = <72>;
290 gpmc,access-ns = <54>;
291 gpmc,wr-access-ns = <30>;
292
293 #address-cells = <1>;
294 #size-cells = <1>;
295
296 x-loader@0 {
297 label = "X-Loader";
298 reg = <0 0x80000>;
299 };
300
301 bootloaders@80000 {
302 label = "U-Boot";
303 reg = <0x80000 0x1e0000>;
304 };
305
306 bootloaders_env@260000 {
307 label = "U-Boot Env";
308 reg = <0x260000 0x20000>;
309 };
310
311 kernel@280000 {
312 label = "Kernel";
313 reg = <0x280000 0x400000>;
314 };
315
316 filesystem@680000 {
317 label = "File System";
318 reg = <0x680000 0xf980000>;
319 };
320 };
321};
322
323&usb_otg_hs {
324 interface-type = <0>;
325 usb-phy = <&usb2_phy>;
326 phys = <&usb2_phy>;
327 phy-names = "usb2-phy";
328 mode = <3>;
329 power = <50>;
330};
331
332&vaux2 {
333 regulator-name = "vdd_ehci";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 regulator-always-on;
337};
diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts
new file mode 100644
index 000000000000..d659515ab9b8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-thunder.dts
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "omap3-tao3530.dtsi"
11
12/ {
13 model = "TI OMAP3 Thunder baseboard with TAO3530 SOM";
14 compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
15};
16
17&omap3_pmx_core {
18 dss_dpi_pins: pinmux_dss_dpi_pins {
19 pinctrl-single,pins = <
20 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
21 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
22 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
23 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
24 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
25 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
26 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
27 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
28 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
29 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
30 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
31 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
32 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
33 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
34 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
35 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
36 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
37 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
38 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
39 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
40 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
41 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
42 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
43 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
44 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
45 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
46 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
47 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
48 >;
49 };
50
51 lte430_pins: pinmux_lte430_pins {
52 pinctrl-single,pins = <
53 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
54 >;
55 };
56
57 backlight_pins: pinmux_backlight_pins {
58 pinctrl-single,pins = <
59 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
60 >;
61 };
62};
63
64/* Needed to power the DPI pins */
65&vpll2 {
66 regulator-always-on;
67};
68
69&dss {
70 status = "ok";
71
72 pinctrl-names = "default";
73 pinctrl-0 = <&dss_dpi_pins>;
74
75 port {
76 dpi_out: endpoint {
77 remote-endpoint = <&lcd_in>;
78 data-lines = <24>;
79 };
80 };
81};
82
83/ {
84 aliases {
85 display0 = &lcd0;
86 };
87
88 lcd0: display@0 {
89 compatible = "samsung,lte430wq-f0c", "panel-dpi";
90 label = "lcd";
91
92 pinctrl-names = "default";
93 pinctrl-0 = <&lte430_pins>;
94 enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */
95
96 port {
97 lcd_in: endpoint {
98 remote-endpoint = <&dpi_out>;
99 };
100 };
101
102 panel-timing {
103 clock-frequency = <9000000>;
104 hactive = <480>;
105 vactive = <272>;
106 hfront-porch = <3>;
107 hback-porch = <2>;
108 hsync-len = <42>;
109 vback-porch = <2>;
110 vfront-porch = <3>;
111 vsync-len = <11>;
112
113 hsync-active = <0>;
114 vsync-active = <0>;
115 de-active = <1>;
116 pixelclk-active = <1>;
117 };
118 };
119
120 backlight {
121 compatible = "gpio-backlight";
122
123 pinctrl-names = "default";
124 pinctrl-0 = <&backlight_pins>;
125 gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */
126
127 default-on;
128 };
129};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 575a49bf968d..d0e884d3a737 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -97,6 +97,7 @@
97 prm: prm@48306000 { 97 prm: prm@48306000 {
98 compatible = "ti,omap3-prm"; 98 compatible = "ti,omap3-prm";
99 reg = <0x48306000 0x4000>; 99 reg = <0x48306000 0x4000>;
100 interrupts = <11>;
100 101
101 prm_clocks: clocks { 102 prm_clocks: clocks {
102 #address-cells = <1>; 103 #address-cells = <1>;
@@ -140,10 +141,9 @@
140 }; 141 };
141 142
142 intc: interrupt-controller@48200000 { 143 intc: interrupt-controller@48200000 {
143 compatible = "ti,omap2-intc"; 144 compatible = "ti,omap3-intc";
144 interrupt-controller; 145 interrupt-controller;
145 #interrupt-cells = <1>; 146 #interrupt-cells = <1>;
146 ti,intc-size = <96>;
147 reg = <0x48200000 0x1000>; 147 reg = <0x48200000 0x1000>;
148 }; 148 };
149 149
@@ -334,6 +334,10 @@
334 interrupts = <26>; 334 interrupts = <26>;
335 ti,mbox-num-users = <2>; 335 ti,mbox-num-users = <2>;
336 ti,mbox-num-fifos = <2>; 336 ti,mbox-num-fifos = <2>;
337 mbox_dsp: dsp {
338 ti,mbox-tx = <0 0 0>;
339 ti,mbox-rx = <1 0 0>;
340 };
337 }; 341 };
338 342
339 mcspi1: spi@48098000 { 343 mcspi1: spi@48098000 {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 8cfa3c8a72b0..150513506c19 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -8,9 +8,6 @@
8#include "elpida_ecb240abacn.dtsi" 8#include "elpida_ecb240abacn.dtsi"
9 9
10/ { 10/ {
11 model = "TI OMAP4 PandaBoard";
12 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
13
14 memory { 11 memory {
15 device_type = "memory"; 12 device_type = "memory";
16 reg = <0x80000000 0x40000000>; /* 1 GB */ 13 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 816d1c95b592..2f1dabcc6adf 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -10,6 +10,11 @@
10#include "omap4460.dtsi" 10#include "omap4460.dtsi"
11#include "omap4-panda-common.dtsi" 11#include "omap4-panda-common.dtsi"
12 12
13/ {
14 model = "TI OMAP4 PandaBoard-ES";
15 compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
16};
17
13/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ 18/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
14&sound { 19&sound {
15 ti,model = "PandaBoardES"; 20 ti,model = "PandaBoardES";
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 6189a8b77d7f..a0e28b2e254e 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -9,3 +9,8 @@
9 9
10#include "omap443x.dtsi" 10#include "omap443x.dtsi"
11#include "omap4-panda-common.dtsi" 11#include "omap4-panda-common.dtsi"
12
13/ {
14 model = "TI OMAP4 PandaBoard";
15 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
16};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 69408b53200d..878c979203d0 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -81,6 +81,7 @@
81 mpu { 81 mpu {
82 compatible = "ti,omap4-mpu"; 82 compatible = "ti,omap4-mpu";
83 ti,hwmods = "mpu"; 83 ti,hwmods = "mpu";
84 sram = <&ocmcram>;
84 }; 85 };
85 86
86 dsp { 87 dsp {
@@ -129,6 +130,7 @@
129 prm: prm@4a306000 { 130 prm: prm@4a306000 {
130 compatible = "ti,omap4-prm"; 131 compatible = "ti,omap4-prm";
131 reg = <0x4a306000 0x3000>; 132 reg = <0x4a306000 0x3000>;
133 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
132 134
133 prm_clocks: clocks { 135 prm_clocks: clocks {
134 #address-cells = <1>; 136 #address-cells = <1>;
@@ -208,6 +210,11 @@
208 }; 210 };
209 }; 211 };
210 212
213 ocmcram: ocmcram@40304000 {
214 compatible = "mmio-sram";
215 reg = <0x40304000 0xa000>; /* 40k */
216 };
217
211 sdma: dma-controller@4a056000 { 218 sdma: dma-controller@4a056000 {
212 compatible = "ti,omap4430-sdma"; 219 compatible = "ti,omap4430-sdma";
213 reg = <0x4a056000 0x1000>; 220 reg = <0x4a056000 0x1000>;
@@ -656,6 +663,14 @@
656 ti,hwmods = "mailbox"; 663 ti,hwmods = "mailbox";
657 ti,mbox-num-users = <3>; 664 ti,mbox-num-users = <3>;
658 ti,mbox-num-fifos = <8>; 665 ti,mbox-num-fifos = <8>;
666 mbox_ipu: mbox_ipu {
667 ti,mbox-tx = <0 0 0>;
668 ti,mbox-rx = <1 0 0>;
669 };
670 mbox_dsp: mbox_dsp {
671 ti,mbox-tx = <3 0 0>;
672 ti,mbox-rx = <2 0 0>;
673 };
659 }; 674 };
660 675
661 timer1: timer@4a318000 { 676 timer1: timer@4a318000 {
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index 429471aa7a1f..b54b271e153b 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -16,6 +16,12 @@
16 reg = <0x80000000 0x7F000000>; /* 2048 MB */ 16 reg = <0x80000000 0x7F000000>; /* 2048 MB */
17 }; 17 };
18 18
19 aliases {
20 display0 = &hdmi0;
21 display1 = &dvi0;
22 display2 = &lcd0;
23 };
24
19 vmmcsd_fixed: fixed-regulator-mmcsd { 25 vmmcsd_fixed: fixed-regulator-mmcsd {
20 compatible = "regulator-fixed"; 26 compatible = "regulator-fixed";
21 regulator-name = "vmmcsd_fixed"; 27 regulator-name = "vmmcsd_fixed";
@@ -45,6 +51,13 @@
45 enable-active-high; 51 enable-active-high;
46 }; 52 };
47 53
54 ads7846reg: ads7846-reg {
55 compatible = "regulator-fixed";
56 regulator-name = "ads7846-reg";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 };
60
48 /* HS USB Host PHY on PORT 2 */ 61 /* HS USB Host PHY on PORT 2 */
49 hsusb2_phy: hsusb2_phy { 62 hsusb2_phy: hsusb2_phy {
50 compatible = "usb-nop-xceiv"; 63 compatible = "usb-nop-xceiv";
@@ -66,6 +79,105 @@
66 default-state = "off"; 79 default-state = "off";
67 }; 80 };
68 }; 81 };
82
83 lcd0: display {
84 compatible = "startek,startek-kd050c", "panel-dpi";
85 label = "lcd";
86
87 pinctrl-names = "default";
88 pinctrl-0 = <&lcd_pins>;
89
90 enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
91
92 panel-timing {
93 clock-frequency = <33000000>;
94 hactive = <800>;
95 vactive = <480>;
96 hfront-porch = <40>;
97 hback-porch = <40>;
98 hsync-len = <43>;
99 vback-porch = <29>;
100 vfront-porch = <13>;
101 vsync-len = <3>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <1>;
106 };
107
108 port {
109 lcd_in: endpoint {
110 remote-endpoint = <&dpi_lcd_out>;
111 };
112 };
113 };
114
115 hdmi0: connector@0 {
116 compatible = "hdmi-connector";
117 label = "hdmi";
118
119 type = "a";
120
121 pinctrl-names = "default";
122 pinctrl-0 = <&hdmi_conn_pins>;
123
124 hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
125
126 port {
127 hdmi_connector_in: endpoint {
128 remote-endpoint = <&hdmi_out>;
129 };
130 };
131 };
132
133 tfp410: encoder@0 {
134 compatible = "ti,tfp410";
135
136 ports {
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 port@0 {
141 reg = <0>;
142
143 tfp410_in: endpoint@0 {
144 remote-endpoint = <&dpi_dvi_out>;
145 };
146 };
147
148 port@1 {
149 reg = <1>;
150
151 tfp410_out: endpoint@0 {
152 remote-endpoint = <&dvi_connector_in>;
153 };
154 };
155 };
156 };
157
158 dvi0: connector@1 {
159 compatible = "dvi-connector";
160 label = "dvi";
161
162 digital;
163
164 ddc-i2c-bus = <&i2c2>;
165
166 port {
167 dvi_connector_in: endpoint {
168 remote-endpoint = <&tfp410_out>;
169 };
170 };
171 };
172};
173
174&omap5_pmx_wkup {
175
176 ads7846_pins: pinmux_ads7846_pins {
177 pinctrl-single,pins = <
178 0x02 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */
179 >;
180 };
69}; 181};
70 182
71&omap5_pmx_core { 183&omap5_pmx_core {
@@ -88,6 +200,13 @@
88 >; 200 >;
89 }; 201 };
90 202
203 i2c2_pins: pinmux_i2c2_pins {
204 pinctrl-single,pins = <
205 OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
206 OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
207 >;
208 };
209
91 mmc1_pins: pinmux_mmc1_pins { 210 mmc1_pins: pinmux_mmc1_pins {
92 pinctrl-single,pins = < 211 pinctrl-single,pins = <
93 OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ 212 OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */
@@ -127,8 +246,8 @@
127 246
128 wlan_gpios_pins: pinmux_wlan_gpios_pins { 247 wlan_gpios_pins: pinmux_wlan_gpios_pins {
129 pinctrl-single,pins = < 248 pinctrl-single,pins = <
130 OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */ 249 OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */
131 OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */ 250 OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */
132 >; 251 >;
133 }; 252 };
134 253
@@ -144,6 +263,104 @@
144 OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ 263 OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */
145 >; 264 >;
146 }; 265 };
266
267 dss_hdmi_pins: pinmux_dss_hdmi_pins {
268 pinctrl-single,pins = <
269 OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */
270 OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */
271 OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */
272 >;
273 };
274
275 lcd_pins: pinmux_lcd_pins {
276 pinctrl-single,pins = <
277 OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */
278 >;
279 };
280
281 hdmi_conn_pins: pinmux_hdmi_conn_pins {
282 pinctrl-single,pins = <
283 OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
284 >;
285 };
286
287 dss_dpi_pins: pinmux_dss_dpi_pins {
288 pinctrl-single,pins = <
289 OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */
290 OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */
291 OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */
292 OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */
293 OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */
294 OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */
295 OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */
296 OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */
297 OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */
298 OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */
299 OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */
300 OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */
301 OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */
302 OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */
303 OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */
304 OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */
305 OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */
306 OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */
307 OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */
308 OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */
309 OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */
310 OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */
311 OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */
312 OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */
313 OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */
314 OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */
315 OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */
316 OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */
317 >;
318 };
319
320 mcspi2_pins: pinmux_mcspi1_pins {
321 pinctrl-single,pins = <
322 OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
323 OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
324 OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */
325 OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */
326 >;
327 };
328};
329
330&mcspi2 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&mcspi2_pins>;
333
334 /* touch controller */
335 ads7846@0 {
336 pinctrl-names = "default";
337 pinctrl-0 = <&ads7846_pins>;
338
339 compatible = "ti,ads7846";
340 vcc-supply = <&ads7846reg>;
341
342 reg = <0>; /* CS0 */
343 spi-max-frequency = <1500000>;
344
345 interrupt-parent = <&gpio1>;
346 interrupts = <15 0>; /* gpio1_wk15 */
347 pendown-gpio = <&gpio1 15 0>;
348
349
350 ti,x-min = /bits/ 16 <0x0>;
351 ti,x-max = /bits/ 16 <0x0fff>;
352 ti,y-min = /bits/ 16 <0x0>;
353 ti,y-max = /bits/ 16 <0x0fff>;
354
355 ti,x-plate-ohms = /bits/ 16 <180>;
356 ti,pressure-max = /bits/ 16 <255>;
357
358 ti,debounce-max = /bits/ 16 <30>;
359 ti,debounce-tol = /bits/ 16 <10>;
360 ti,debounce-rep = /bits/ 16 <1>;
361
362 linux,wakeup;
363 };
147}; 364};
148 365
149&mmc1 { 366&mmc1 {
@@ -398,6 +615,13 @@
398 }; 615 };
399}; 616};
400 617
618&i2c2 {
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c2_pins>;
621
622 clock-frequency = <100000>;
623};
624
401&usbhshost { 625&usbhshost {
402 port2-mode = "ehci-hsic"; 626 port2-mode = "ehci-hsic";
403 port3-mode = "ehci-hsic"; 627 port3-mode = "ehci-hsic";
@@ -407,6 +631,50 @@
407 phys = <0 &hsusb2_phy &hsusb3_phy>; 631 phys = <0 &hsusb2_phy &hsusb3_phy>;
408}; 632};
409 633
634&usb3 {
635 extcon = <&extcon_usb3>;
636 vbus-supply = <&smps10_out1_reg>;
637};
638
410&cpu0 { 639&cpu0 {
411 cpu0-supply = <&smps123_reg>; 640 cpu0-supply = <&smps123_reg>;
412}; 641};
642
643&dss {
644 status = "ok";
645
646 pinctrl-names = "default";
647 pinctrl-0 = <&dss_dpi_pins>;
648
649 port {
650 dpi_dvi_out: endpoint@0 {
651 remote-endpoint = <&tfp410_in>;
652 data-lines = <24>;
653 };
654
655 dpi_lcd_out: endpoint@1 {
656 remote-endpoint = <&lcd_in>;
657 data-lines = <24>;
658 };
659 };
660};
661
662&dsi2 {
663 status = "ok";
664 vdd-supply = <&ldo4_reg>;
665};
666
667&hdmi {
668 status = "ok";
669 vdda-supply = <&ldo4_reg>;
670
671 pinctrl-names = "default";
672 pinctrl-0 = <&dss_hdmi_pins>;
673
674 port {
675 hdmi_out: endpoint {
676 remote-endpoint = <&hdmi_connector_in>;
677 lanes = <1 0 3 2 5 4 7 6>;
678 };
679 };
680};
diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts
index aa98fea3f2b3..337bbbc01a35 100644
--- a/arch/arm/boot/dts/omap5-sbc-t54.dts
+++ b/arch/arm/boot/dts/omap5-sbc-t54.dts
@@ -1,11 +1,11 @@
1/* 1/*
2 * Suppport for CompuLab SBC-T54 with CM-T54 2 * Suppport for CompuLab CM-T54 on SB-T54 baseboard
3 */ 3 */
4 4
5#include "omap5-cm-t54.dts" 5#include "omap5-cm-t54.dts"
6 6
7/ { 7/ {
8 model = "CompuLab SBC-T54 with CM-T54"; 8 model = "CompuLab CM-T54 on SB-T54";
9 compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; 9 compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5";
10}; 10};
11 11
@@ -19,8 +19,8 @@
19 19
20 mmc1_aux_pins: pinmux_mmc1_aux_pins { 20 mmc1_aux_pins: pinmux_mmc1_aux_pins {
21 pinctrl-single,pins = < 21 pinctrl-single,pins = <
22 OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */ 22 OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */
23 OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */ 23 OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */
24 >; 24 >;
25 }; 25 };
26}; 26};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc8df1739f39..256b7f69e45b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -104,8 +104,9 @@
104 soc { 104 soc {
105 compatible = "ti,omap-infra"; 105 compatible = "ti,omap-infra";
106 mpu { 106 mpu {
107 compatible = "ti,omap5-mpu"; 107 compatible = "ti,omap4-mpu";
108 ti,hwmods = "mpu"; 108 ti,hwmods = "mpu";
109 sram = <&ocmcram>;
109 }; 110 };
110 }; 111 };
111 112
@@ -131,6 +132,7 @@
131 prm: prm@4ae06000 { 132 prm: prm@4ae06000 {
132 compatible = "ti,omap5-prm"; 133 compatible = "ti,omap5-prm";
133 reg = <0x4ae06000 0x3000>; 134 reg = <0x4ae06000 0x3000>;
135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
134 136
135 prm_clocks: clocks { 137 prm_clocks: clocks {
136 #address-cells = <1>; 138 #address-cells = <1>;
@@ -187,18 +189,22 @@
187 }; 189 };
188 190
189 omap5_pmx_core: pinmux@4a002840 { 191 omap5_pmx_core: pinmux@4a002840 {
190 compatible = "ti,omap4-padconf", "pinctrl-single"; 192 compatible = "ti,omap5-padconf", "pinctrl-single";
191 reg = <0x4a002840 0x01b6>; 193 reg = <0x4a002840 0x01b6>;
192 #address-cells = <1>; 194 #address-cells = <1>;
193 #size-cells = <0>; 195 #size-cells = <0>;
196 #interrupt-cells = <1>;
197 interrupt-controller;
194 pinctrl-single,register-width = <16>; 198 pinctrl-single,register-width = <16>;
195 pinctrl-single,function-mask = <0x7fff>; 199 pinctrl-single,function-mask = <0x7fff>;
196 }; 200 };
197 omap5_pmx_wkup: pinmux@4ae0c840 { 201 omap5_pmx_wkup: pinmux@4ae0c840 {
198 compatible = "ti,omap4-padconf", "pinctrl-single"; 202 compatible = "ti,omap5-padconf", "pinctrl-single";
199 reg = <0x4ae0c840 0x0038>; 203 reg = <0x4ae0c840 0x0038>;
200 #address-cells = <1>; 204 #address-cells = <1>;
201 #size-cells = <0>; 205 #size-cells = <0>;
206 #interrupt-cells = <1>;
207 interrupt-controller;
202 pinctrl-single,register-width = <16>; 208 pinctrl-single,register-width = <16>;
203 pinctrl-single,function-mask = <0x7fff>; 209 pinctrl-single,function-mask = <0x7fff>;
204 }; 210 };
@@ -219,6 +225,11 @@
219 }; 225 };
220 }; 226 };
221 227
228 ocmcram: ocmcram@40300000 {
229 compatible = "mmio-sram";
230 reg = <0x40300000 0x20000>; /* 128k */
231 };
232
222 sdma: dma-controller@4a056000 { 233 sdma: dma-controller@4a056000 {
223 compatible = "ti,omap4430-sdma"; 234 compatible = "ti,omap4430-sdma";
224 reg = <0x4a056000 0x1000>; 235 reg = <0x4a056000 0x1000>;
@@ -447,7 +458,7 @@
447 uart1: serial@4806a000 { 458 uart1: serial@4806a000 {
448 compatible = "ti,omap4-uart"; 459 compatible = "ti,omap4-uart";
449 reg = <0x4806a000 0x100>; 460 reg = <0x4806a000 0x100>;
450 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 461 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
451 ti,hwmods = "uart1"; 462 ti,hwmods = "uart1";
452 clock-frequency = <48000000>; 463 clock-frequency = <48000000>;
453 }; 464 };
@@ -455,7 +466,7 @@
455 uart2: serial@4806c000 { 466 uart2: serial@4806c000 {
456 compatible = "ti,omap4-uart"; 467 compatible = "ti,omap4-uart";
457 reg = <0x4806c000 0x100>; 468 reg = <0x4806c000 0x100>;
458 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 469 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
459 ti,hwmods = "uart2"; 470 ti,hwmods = "uart2";
460 clock-frequency = <48000000>; 471 clock-frequency = <48000000>;
461 }; 472 };
@@ -463,7 +474,7 @@
463 uart3: serial@48020000 { 474 uart3: serial@48020000 {
464 compatible = "ti,omap4-uart"; 475 compatible = "ti,omap4-uart";
465 reg = <0x48020000 0x100>; 476 reg = <0x48020000 0x100>;
466 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 477 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
467 ti,hwmods = "uart3"; 478 ti,hwmods = "uart3";
468 clock-frequency = <48000000>; 479 clock-frequency = <48000000>;
469 }; 480 };
@@ -471,7 +482,7 @@
471 uart4: serial@4806e000 { 482 uart4: serial@4806e000 {
472 compatible = "ti,omap4-uart"; 483 compatible = "ti,omap4-uart";
473 reg = <0x4806e000 0x100>; 484 reg = <0x4806e000 0x100>;
474 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 485 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
475 ti,hwmods = "uart4"; 486 ti,hwmods = "uart4";
476 clock-frequency = <48000000>; 487 clock-frequency = <48000000>;
477 }; 488 };
@@ -479,7 +490,7 @@
479 uart5: serial@48066000 { 490 uart5: serial@48066000 {
480 compatible = "ti,omap4-uart"; 491 compatible = "ti,omap4-uart";
481 reg = <0x48066000 0x100>; 492 reg = <0x48066000 0x100>;
482 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 493 interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
483 ti,hwmods = "uart5"; 494 ti,hwmods = "uart5";
484 clock-frequency = <48000000>; 495 clock-frequency = <48000000>;
485 }; 496 };
@@ -487,7 +498,7 @@
487 uart6: serial@48068000 { 498 uart6: serial@48068000 {
488 compatible = "ti,omap4-uart"; 499 compatible = "ti,omap4-uart";
489 reg = <0x48068000 0x100>; 500 reg = <0x48068000 0x100>;
490 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 501 interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
491 ti,hwmods = "uart6"; 502 ti,hwmods = "uart6";
492 clock-frequency = <48000000>; 503 clock-frequency = <48000000>;
493 }; 504 };
@@ -642,6 +653,14 @@
642 ti,hwmods = "mailbox"; 653 ti,hwmods = "mailbox";
643 ti,mbox-num-users = <3>; 654 ti,mbox-num-users = <3>;
644 ti,mbox-num-fifos = <8>; 655 ti,mbox-num-fifos = <8>;
656 mbox_ipu: mbox_ipu {
657 ti,mbox-tx = <0 0 0>;
658 ti,mbox-rx = <1 0 0>;
659 };
660 mbox_dsp: mbox_dsp {
661 ti,mbox-tx = <3 0 0>;
662 ti,mbox-rx = <2 0 0>;
663 };
645 }; 664 };
646 665
647 timer1: timer@4ae18000 { 666 timer1: timer@4ae18000 {
@@ -945,6 +964,15 @@
945 clock-names = "fck"; 964 clock-names = "fck";
946 }; 965 };
947 966
967 rfbi: encoder@58002000 {
968 compatible = "ti,omap5-rfbi";
969 reg = <0x58002000 0x100>;
970 status = "disabled";
971 ti,hwmods = "dss_rfbi";
972 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
973 clock-names = "fck", "ick";
974 };
975
948 dsi1: encoder@58004000 { 976 dsi1: encoder@58004000 {
949 compatible = "ti,omap5-dsi"; 977 compatible = "ti,omap5-dsi";
950 reg = <0x58004000 0x200>, 978 reg = <0x58004000 0x200>,
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index a5e90f078aa9..c08f84629aa9 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -113,14 +113,14 @@
113 }; 113 };
114 114
115 usb0: ohci@4c000000 { 115 usb0: ohci@4c000000 {
116 compatible = "mrvl,pxa-ohci"; 116 compatible = "marvell,pxa-ohci";
117 reg = <0x4c000000 0x10000>; 117 reg = <0x4c000000 0x10000>;
118 interrupts = <3>; 118 interrupts = <3>;
119 status = "disabled"; 119 status = "disabled";
120 }; 120 };
121 121
122 mmc0: mmc@41100000 { 122 mmc0: mmc@41100000 {
123 compatible = "mrvl,pxa-mmc"; 123 compatible = "marvell,pxa-mmc";
124 reg = <0x41100000 0x1000>; 124 reg = <0x41100000 0x1000>;
125 interrupts = <23>; 125 interrupts = <23>;
126 status = "disabled"; 126 status = "disabled";
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 7c2441d526bc..b396c8311b27 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -5,6 +5,33 @@
5 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; 5 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
6 6
7 soc { 7 soc {
8 pinctrl@800000 {
9 i2c1_pins: i2c1 {
10 mux {
11 pins = "gpio20", "gpio21";
12 function = "gsbi1";
13 };
14 };
15 };
16
17 gsbi@12440000 {
18 status = "okay";
19 qcom,mode = <GSBI_PROT_I2C>;
20
21 i2c@12460000 {
22 status = "okay";
23 clock-frequency = <200000>;
24 pinctrl-0 = <&i2c1_pins>;
25 pinctrl-names = "default";
26
27 eeprom: eeprom@52 {
28 compatible = "atmel,24c128";
29 reg = <0x52>;
30 pagesize = <32>;
31 };
32 };
33 };
34
8 gsbi@16600000 { 35 gsbi@16600000 {
9 status = "ok"; 36 status = "ok";
10 qcom,mode = <GSBI_PROT_I2C_UART>; 37 qcom,mode = <GSBI_PROT_I2C_UART>;
@@ -12,5 +39,21 @@
12 status = "ok"; 39 status = "ok";
13 }; 40 };
14 }; 41 };
42
43 amba {
44 /* eMMC */
45 sdcc1: sdcc@12400000 {
46 status = "okay";
47 };
48
49 /* External micro SD card */
50 sdcc3: sdcc@12180000 {
51 status = "okay";
52 };
53 /* WLAN */
54 sdcc4: sdcc@121c0000 {
55 status = "okay";
56 };
57 };
15 }; 58 };
16}; 59};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92bf793622c3..b3154c071652 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -2,7 +2,9 @@
2 2
3#include "skeleton.dtsi" 3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
5#include <dt-bindings/soc/qcom,gsbi.h> 6#include <dt-bindings/soc/qcom,gsbi.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
6 8
7/ { 9/ {
8 model = "Qualcomm APQ8064"; 10 model = "Qualcomm APQ8064";
@@ -70,6 +72,34 @@
70 ranges; 72 ranges;
71 compatible = "simple-bus"; 73 compatible = "simple-bus";
72 74
75 tlmm_pinmux: pinctrl@800000 {
76 compatible = "qcom,apq8064-pinctrl";
77 reg = <0x800000 0x4000>;
78
79 gpio-controller;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupt-cells = <2>;
83 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
84
85 pinctrl-names = "default";
86 pinctrl-0 = <&ps_hold>;
87
88 sdc4_gpios: sdc4-gpios {
89 pios {
90 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
91 function = "sdc4";
92 };
93 };
94
95 ps_hold: ps_hold {
96 mux {
97 pins = "gpio78";
98 function = "ps_hold";
99 };
100 };
101 };
102
73 intc: interrupt-controller@2000000 { 103 intc: interrupt-controller@2000000 {
74 compatible = "qcom,msm-qgic2"; 104 compatible = "qcom,msm-qgic2";
75 interrupt-controller; 105 interrupt-controller;
@@ -133,6 +163,48 @@
133 regulator; 163 regulator;
134 }; 164 };
135 165
166 gsbi1: gsbi@12440000 {
167 status = "disabled";
168 compatible = "qcom,gsbi-v1.0.0";
169 reg = <0x12440000 0x100>;
170 clocks = <&gcc GSBI1_H_CLK>;
171 clock-names = "iface";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175
176 i2c1: i2c@12460000 {
177 compatible = "qcom,i2c-qup-v1.1.1";
178 reg = <0x12460000 0x1000>;
179 interrupts = <0 194 IRQ_TYPE_NONE>;
180 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
181 clock-names = "core", "iface";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 };
185 };
186
187 gsbi2: gsbi@12480000 {
188 status = "disabled";
189 compatible = "qcom,gsbi-v1.0.0";
190 reg = <0x12480000 0x100>;
191 clocks = <&gcc GSBI2_H_CLK>;
192 clock-names = "iface";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 ranges;
196
197 i2c2: i2c@124a0000 {
198 compatible = "qcom,i2c-qup-v1.1.1";
199 reg = <0x124a0000 0x1000>;
200 interrupts = <0 196 IRQ_TYPE_NONE>;
201 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
202 clock-names = "core", "iface";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 };
206 };
207
136 gsbi7: gsbi@16600000 { 208 gsbi7: gsbi@16600000 {
137 status = "disabled"; 209 status = "disabled";
138 compatible = "qcom,gsbi-v1.0.0"; 210 compatible = "qcom,gsbi-v1.0.0";
@@ -166,5 +238,116 @@
166 #clock-cells = <1>; 238 #clock-cells = <1>;
167 #reset-cells = <1>; 239 #reset-cells = <1>;
168 }; 240 };
241
242 mmcc: clock-controller@4000000 {
243 compatible = "qcom,mmcc-apq8064";
244 reg = <0x4000000 0x1000>;
245 #clock-cells = <1>;
246 #reset-cells = <1>;
247 };
248
249 /* Temporary fixed regulator */
250 vsdcc_fixed: vsdcc-regulator {
251 compatible = "regulator-fixed";
252 regulator-name = "SDCC Power";
253 regulator-min-microvolt = <2700000>;
254 regulator-max-microvolt = <2700000>;
255 regulator-always-on;
256 };
257
258 sdcc1bam:dma@12402000{
259 compatible = "qcom,bam-v1.3.0";
260 reg = <0x12402000 0x8000>;
261 interrupts = <0 98 0>;
262 clocks = <&gcc SDC1_H_CLK>;
263 clock-names = "bam_clk";
264 #dma-cells = <1>;
265 qcom,ee = <0>;
266 };
267
268 sdcc3bam:dma@12182000{
269 compatible = "qcom,bam-v1.3.0";
270 reg = <0x12182000 0x8000>;
271 interrupts = <0 96 0>;
272 clocks = <&gcc SDC3_H_CLK>;
273 clock-names = "bam_clk";
274 #dma-cells = <1>;
275 qcom,ee = <0>;
276 };
277
278 sdcc4bam:dma@121c2000{
279 compatible = "qcom,bam-v1.3.0";
280 reg = <0x121c2000 0x8000>;
281 interrupts = <0 95 0>;
282 clocks = <&gcc SDC4_H_CLK>;
283 clock-names = "bam_clk";
284 #dma-cells = <1>;
285 qcom,ee = <0>;
286 };
287
288 amba {
289 compatible = "arm,amba-bus";
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293 sdcc1: sdcc@12400000 {
294 status = "disabled";
295 compatible = "arm,pl18x", "arm,primecell";
296 arm,primecell-periphid = <0x00051180>;
297 reg = <0x12400000 0x2000>;
298 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
299 interrupt-names = "cmd_irq";
300 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
301 clock-names = "mclk", "apb_pclk";
302 bus-width = <8>;
303 max-frequency = <96000000>;
304 non-removable;
305 cap-sd-highspeed;
306 cap-mmc-highspeed;
307 vmmc-supply = <&vsdcc_fixed>;
308 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
309 dma-names = "tx", "rx";
310 };
311
312 sdcc3: sdcc@12180000 {
313 compatible = "arm,pl18x", "arm,primecell";
314 arm,primecell-periphid = <0x00051180>;
315 status = "disabled";
316 reg = <0x12180000 0x2000>;
317 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-names = "cmd_irq";
319 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
320 clock-names = "mclk", "apb_pclk";
321 bus-width = <4>;
322 cap-sd-highspeed;
323 cap-mmc-highspeed;
324 max-frequency = <192000000>;
325 no-1-8-v;
326 vmmc-supply = <&vsdcc_fixed>;
327 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
328 dma-names = "tx", "rx";
329 };
330
331 sdcc4: sdcc@121c0000 {
332 compatible = "arm,pl18x", "arm,primecell";
333 arm,primecell-periphid = <0x00051180>;
334 status = "disabled";
335 reg = <0x121c0000 0x2000>;
336 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
337 interrupt-names = "cmd_irq";
338 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
339 clock-names = "mclk", "apb_pclk";
340 bus-width = <4>;
341 cap-sd-highspeed;
342 cap-mmc-highspeed;
343 max-frequency = <48000000>;
344 vmmc-supply = <&vsdcc_fixed>;
345 vqmmc-supply = <&vsdcc_fixed>;
346 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
347 dma-names = "tx", "rx";
348 pinctrl-names = "default";
349 pinctrl-0 = <&sdc4_gpios>;
350 };
351 };
169 }; 352 };
170}; 353};
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index b4dfb01fe6fb..47370494d0f8 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -22,6 +22,13 @@
22 22
23 23
24 pinctrl@fd510000 { 24 pinctrl@fd510000 {
25 i2c11_pins: i2c11 {
26 mux {
27 pins = "gpio83", "gpio84";
28 function = "blsp_i2c11";
29 };
30 };
31
25 spi8_default: spi8_default { 32 spi8_default: spi8_default {
26 mosi { 33 mosi {
27 pins = "gpio45"; 34 pins = "gpio45";
@@ -41,5 +48,19 @@
41 }; 48 };
42 }; 49 };
43 }; 50 };
51
52 i2c@f9967000 {
53 status = "okay";
54 clock-frequency = <200000>;
55 pinctrl-0 = <&i2c11_pins>;
56 pinctrl-names = "default";
57
58 eeprom: eeprom@52 {
59 compatible = "atmel,24c128";
60 reg = <0x52>;
61 pagesize = <32>;
62 read-only;
63 };
64 };
44 }; 65 };
45}; 66};
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
new file mode 100644
index 000000000000..c9ff10821ad9
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -0,0 +1,23 @@
1#include "qcom-apq8084.dtsi"
2
3/ {
4 model = "Qualcomm APQ8084/IFC6540";
5 compatible = "qcom,apq8084-ifc6540", "qcom,apq8084";
6
7 soc {
8 serial@f995e000 {
9 status = "okay";
10 };
11
12 sdhci@f9824900 {
13 bus-width = <8>;
14 non-removable;
15 status = "okay";
16 };
17
18 sdhci@f98a4900 {
19 cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
20 bus-width = <4>;
21 };
22 };
23};
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
index 9dae3878b71d..8ecec58a9ff6 100644
--- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -3,4 +3,10 @@
3/ { 3/ {
4 model = "Qualcomm APQ 8084-MTP"; 4 model = "Qualcomm APQ 8084-MTP";
5 compatible = "qcom,apq8084-mtp", "qcom,apq8084"; 5 compatible = "qcom,apq8084-mtp", "qcom,apq8084";
6
7 soc {
8 serial@f995e000 {
9 status = "okay";
10 };
11 };
6}; 12};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index e3e009a5912b..1f130bc16858 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -2,6 +2,9 @@
2 2
3#include "skeleton.dtsi" 3#include "skeleton.dtsi"
4 4
5#include <dt-bindings/clock/qcom,gcc-apq8084.h>
6#include <dt-bindings/gpio/gpio.h>
7
5/ { 8/ {
6 model = "Qualcomm APQ 8084"; 9 model = "Qualcomm APQ 8084";
7 compatible = "qcom,apq8084"; 10 compatible = "qcom,apq8084";
@@ -175,5 +178,53 @@
175 compatible = "qcom,pshold"; 178 compatible = "qcom,pshold";
176 reg = <0xfc4ab000 0x4>; 179 reg = <0xfc4ab000 0x4>;
177 }; 180 };
181
182 gcc: clock-controller@fc400000 {
183 compatible = "qcom,gcc-apq8084";
184 #clock-cells = <1>;
185 #reset-cells = <1>;
186 reg = <0xfc400000 0x4000>;
187 };
188
189 tlmm: pinctrl@fd510000 {
190 compatible = "qcom,apq8084-pinctrl";
191 reg = <0xfd510000 0x4000>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
196 interrupts = <0 208 0>;
197 };
198
199 serial@f995e000 {
200 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
201 reg = <0xf995e000 0x1000>;
202 interrupts = <0 114 0x0>;
203 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
204 clock-names = "core", "iface";
205 status = "disabled";
206 };
207
208 sdhci@f9824900 {
209 compatible = "qcom,sdhci-msm-v4";
210 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
211 reg-names = "hc_mem", "core_mem";
212 interrupts = <0 123 0>, <0 138 0>;
213 interrupt-names = "hc_irq", "pwr_irq";
214 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
215 clock-names = "core", "iface";
216 status = "disabled";
217 };
218
219 sdhci@f98a4900 {
220 compatible = "qcom,sdhci-msm-v4";
221 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
222 reg-names = "hc_mem", "core_mem";
223 interrupts = <0 125 0>, <0 221 0>;
224 interrupt-names = "hc_irq", "pwr_irq";
225 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
226 clock-names = "core", "iface";
227 status = "disabled";
228 };
178 }; 229 };
179}; 230};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
new file mode 100644
index 000000000000..95e64955fb8e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -0,0 +1,85 @@
1#include "qcom-ipq8064-v1.0.dtsi"
2
3/ {
4 model = "Qualcomm IPQ8064/AP148";
5 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
6
7 reserved-memory {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges;
11 rsvd@41200000 {
12 reg = <0x41200000 0x300000>;
13 no-map;
14 };
15 };
16
17 soc {
18 pinmux@800000 {
19 i2c4_pins: i2c4_pinmux {
20 pins = "gpio12", "gpio13";
21 function = "gsbi4";
22 bias-disable;
23 };
24
25 spi_pins: spi_pins {
26 mux {
27 pins = "gpio18", "gpio19", "gpio21";
28 function = "gsbi5";
29 drive-strength = <10>;
30 bias-none;
31 };
32 };
33 };
34
35 gsbi@16300000 {
36 qcom,mode = <GSBI_PROT_I2C_UART>;
37 status = "ok";
38 serial@16340000 {
39 status = "ok";
40 };
41
42 i2c4: i2c@16380000 {
43 status = "ok";
44
45 clock-frequency = <200000>;
46
47 pinctrl-0 = <&i2c4_pins>;
48 pinctrl-names = "default";
49 };
50 };
51
52 gsbi5: gsbi@1a200000 {
53 qcom,mode = <GSBI_PROT_SPI>;
54 status = "ok";
55
56 spi4: spi@1a280000 {
57 status = "ok";
58 spi-max-frequency = <50000000>;
59
60 pinctrl-0 = <&spi_pins>;
61 pinctrl-names = "default";
62
63 cs-gpios = <&qcom_pinmux 20 0>;
64
65 flash: m25p80@0 {
66 compatible = "s25fl256s1";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 spi-max-frequency = <50000000>;
70 reg = <0>;
71
72 partition@0 {
73 label = "rootfs";
74 reg = <0x0 0x1000000>;
75 };
76
77 partition@1 {
78 label = "scratch";
79 reg = <0x1000000 0x1000000>;
80 };
81 };
82 };
83 };
84 };
85};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
new file mode 100644
index 000000000000..7093b075e408
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -0,0 +1 @@
#include "qcom-ipq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
new file mode 100644
index 000000000000..244f857f0e6f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -0,0 +1,250 @@
1/dts-v1/;
2
3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5#include <dt-bindings/soc/qcom,gsbi.h>
6
7/ {
8 model = "Qualcomm IPQ8064";
9 compatible = "qcom,ipq8064";
10 interrupt-parent = <&intc>;
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@0 {
17 compatible = "qcom,krait";
18 enable-method = "qcom,kpss-acc-v1";
19 device_type = "cpu";
20 reg = <0>;
21 next-level-cache = <&L2>;
22 qcom,acc = <&acc0>;
23 qcom,saw = <&saw0>;
24 };
25
26 cpu@1 {
27 compatible = "qcom,krait";
28 enable-method = "qcom,kpss-acc-v1";
29 device_type = "cpu";
30 reg = <1>;
31 next-level-cache = <&L2>;
32 qcom,acc = <&acc1>;
33 qcom,saw = <&saw1>;
34 };
35
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 };
40 };
41
42 cpu-pmu {
43 compatible = "qcom,krait-pmu";
44 interrupts = <1 10 0x304>;
45 };
46
47 reserved-memory {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51
52 nss@40000000 {
53 reg = <0x40000000 0x1000000>;
54 no-map;
55 };
56
57 smem@41000000 {
58 reg = <0x41000000 0x200000>;
59 no-map;
60 };
61 };
62
63 soc: soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67 compatible = "simple-bus";
68
69 qcom_pinmux: pinmux@800000 {
70 compatible = "qcom,ipq8064-pinctrl";
71 reg = <0x800000 0x4000>;
72
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 interrupts = <0 32 0x4>;
78 };
79
80 intc: interrupt-controller@2000000 {
81 compatible = "qcom,msm-qgic2";
82 interrupt-controller;
83 #interrupt-cells = <3>;
84 reg = <0x02000000 0x1000>,
85 <0x02002000 0x1000>;
86 };
87
88 timer@200a000 {
89 compatible = "qcom,kpss-timer", "qcom,msm-timer";
90 interrupts = <1 1 0x301>,
91 <1 2 0x301>,
92 <1 3 0x301>;
93 reg = <0x0200a000 0x100>;
94 clock-frequency = <25000000>,
95 <32768>;
96 cpu-offset = <0x80000>;
97 };
98
99 acc0: clock-controller@2088000 {
100 compatible = "qcom,kpss-acc-v1";
101 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
102 };
103
104 acc1: clock-controller@2098000 {
105 compatible = "qcom,kpss-acc-v1";
106 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
107 };
108
109 saw0: regulator@2089000 {
110 compatible = "qcom,saw2";
111 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
112 regulator;
113 };
114
115 saw1: regulator@2099000 {
116 compatible = "qcom,saw2";
117 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
118 regulator;
119 };
120
121 gsbi2: gsbi@12480000 {
122 compatible = "qcom,gsbi-v1.0.0";
123 reg = <0x12480000 0x100>;
124 clocks = <&gcc GSBI2_H_CLK>;
125 clock-names = "iface";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges;
129 status = "disabled";
130
131 serial@12490000 {
132 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
133 reg = <0x12490000 0x1000>,
134 <0x12480000 0x1000>;
135 interrupts = <0 195 0x0>;
136 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
137 clock-names = "core", "iface";
138 status = "disabled";
139 };
140
141 i2c@124a0000 {
142 compatible = "qcom,i2c-qup-v1.1.1";
143 reg = <0x124a0000 0x1000>;
144 interrupts = <0 196 0>;
145
146 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
147 clock-names = "core", "iface";
148 status = "disabled";
149
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 };
155
156 gsbi4: gsbi@16300000 {
157 compatible = "qcom,gsbi-v1.0.0";
158 reg = <0x16300000 0x100>;
159 clocks = <&gcc GSBI4_H_CLK>;
160 clock-names = "iface";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164 status = "disabled";
165
166 serial@16340000 {
167 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
168 reg = <0x16340000 0x1000>,
169 <0x16300000 0x1000>;
170 interrupts = <0 152 0x0>;
171 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
172 clock-names = "core", "iface";
173 status = "disabled";
174 };
175
176 i2c@16380000 {
177 compatible = "qcom,i2c-qup-v1.1.1";
178 reg = <0x16380000 0x1000>;
179 interrupts = <0 153 0>;
180
181 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
182 clock-names = "core", "iface";
183 status = "disabled";
184
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188 };
189
190 gsbi5: gsbi@1a200000 {
191 compatible = "qcom,gsbi-v1.0.0";
192 reg = <0x1a200000 0x100>;
193 clocks = <&gcc GSBI5_H_CLK>;
194 clock-names = "iface";
195 #address-cells = <1>;
196 #size-cells = <1>;
197 ranges;
198 status = "disabled";
199
200 serial@1a240000 {
201 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
202 reg = <0x1a240000 0x1000>,
203 <0x1a200000 0x1000>;
204 interrupts = <0 154 0x0>;
205 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
206 clock-names = "core", "iface";
207 status = "disabled";
208 };
209
210 i2c@1a280000 {
211 compatible = "qcom,i2c-qup-v1.1.1";
212 reg = <0x1a280000 0x1000>;
213 interrupts = <0 155 0>;
214
215 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
216 clock-names = "core", "iface";
217 status = "disabled";
218
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 spi@1a280000 {
224 compatible = "qcom,spi-qup-v1.1.1";
225 reg = <0x1a280000 0x1000>;
226 interrupts = <0 155 0>;
227
228 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
229 clock-names = "core", "iface";
230 status = "disabled";
231
232 #address-cells = <1>;
233 #size-cells = <0>;
234 };
235 };
236
237 qcom,ssbi@500000 {
238 compatible = "qcom,ssbi";
239 reg = <0x00500000 0x1000>;
240 qcom,controller-type = "pmic-arbiter";
241 };
242
243 gcc: clock-controller@900000 {
244 compatible = "qcom,gcc-ipq8064";
245 reg = <0x00900000 0x4000>;
246 #clock-cells = <1>;
247 #reset-cells = <1>;
248 };
249 };
250};
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 45180adfadf1..e0883c376248 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -1,3 +1,5 @@
1#include <dt-bindings/input/input.h>
2
1#include "qcom-msm8660.dtsi" 3#include "qcom-msm8660.dtsi"
2 4
3/ { 5/ {
@@ -12,5 +14,45 @@
12 status = "ok"; 14 status = "ok";
13 }; 15 };
14 }; 16 };
17
18 amba {
19 /* eMMC */
20 sdcc1: sdcc@12400000 {
21 status = "okay";
22 };
23
24 /* External micro SD card */
25 sdcc3: sdcc@12180000 {
26 status = "okay";
27 };
28 };
29 };
30};
31
32&pmicintc {
33 keypad@148 {
34 linux,keymap = <
35 MATRIX_KEY(0, 0, KEY_FN_F1)
36 MATRIX_KEY(0, 1, KEY_UP)
37 MATRIX_KEY(0, 2, KEY_LEFT)
38 MATRIX_KEY(0, 3, KEY_VOLUMEUP)
39 MATRIX_KEY(1, 0, KEY_FN_F2)
40 MATRIX_KEY(1, 1, KEY_RIGHT)
41 MATRIX_KEY(1, 2, KEY_DOWN)
42 MATRIX_KEY(1, 3, KEY_VOLUMEDOWN)
43 MATRIX_KEY(2, 3, KEY_ENTER)
44 MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS)
45 MATRIX_KEY(4, 1, KEY_UP)
46 MATRIX_KEY(4, 2, KEY_LEFT)
47 MATRIX_KEY(4, 3, KEY_HOME)
48 MATRIX_KEY(4, 4, KEY_FN_F3)
49 MATRIX_KEY(5, 0, KEY_CAMERA)
50 MATRIX_KEY(5, 1, KEY_RIGHT)
51 MATRIX_KEY(5, 2, KEY_DOWN)
52 MATRIX_KEY(5, 3, KEY_BACK)
53 MATRIX_KEY(5, 4, KEY_MENU)
54 >;
55 keypad,num-rows = <6>;
56 keypad,num-columns = <5>;
15 }; 57 };
16}; 58};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 53837aaa2f72..0affd6193f56 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -2,6 +2,7 @@
2 2
3/include/ "skeleton.dtsi" 3/include/ "skeleton.dtsi"
4 4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8660.h> 6#include <dt-bindings/clock/qcom,gcc-msm8660.h>
6#include <dt-bindings/soc/qcom,gsbi.h> 7#include <dt-bindings/soc/qcom,gsbi.h>
7 8
@@ -103,6 +104,98 @@
103 compatible = "qcom,ssbi"; 104 compatible = "qcom,ssbi";
104 reg = <0x500000 0x1000>; 105 reg = <0x500000 0x1000>;
105 qcom,controller-type = "pmic-arbiter"; 106 qcom,controller-type = "pmic-arbiter";
107
108 pmicintc: pmic@0 {
109 compatible = "qcom,pm8058";
110 interrupt-parent = <&msmgpio>;
111 interrupts = <88 8>;
112 #interrupt-cells = <2>;
113 interrupt-controller;
114 #address-cells = <1>;
115 #size-cells = <0>;
116
117 pwrkey@1c {
118 compatible = "qcom,pm8058-pwrkey";
119 reg = <0x1c>;
120 interrupt-parent = <&pmicintc>;
121 interrupts = <50 1>, <51 1>;
122 debounce = <15625>;
123 pull-up;
124 };
125
126 keypad@148 {
127 compatible = "qcom,pm8058-keypad";
128 reg = <0x148>;
129 interrupt-parent = <&pmicintc>;
130 interrupts = <74 1>, <75 1>;
131 debounce = <15>;
132 scan-delay = <32>;
133 row-hold = <91500>;
134 };
135
136 rtc@11d {
137 compatible = "qcom,pm8058-rtc";
138 interrupt-parent = <&pmicintc>;
139 interrupts = <39 1>;
140 reg = <0x11d>;
141 allow-set-time;
142 };
143
144 vibrator@4a {
145 compatible = "qcom,pm8058-vib";
146 reg = <0x4a>;
147 };
148 };
149 };
150
151 /* Temporary fixed regulator */
152 vsdcc_fixed: vsdcc-regulator {
153 compatible = "regulator-fixed";
154 regulator-name = "SDCC Power";
155 regulator-min-microvolt = <2700000>;
156 regulator-max-microvolt = <2700000>;
157 regulator-always-on;
158 };
159
160 amba {
161 compatible = "arm,amba-bus";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165 sdcc1: sdcc@12400000 {
166 status = "disabled";
167 compatible = "arm,pl18x", "arm,primecell";
168 arm,primecell-periphid = <0x00051180>;
169 reg = <0x12400000 0x8000>;
170 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "cmd_irq";
172 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
173 clock-names = "mclk", "apb_pclk";
174 bus-width = <8>;
175 max-frequency = <48000000>;
176 non-removable;
177 cap-sd-highspeed;
178 cap-mmc-highspeed;
179 vmmc-supply = <&vsdcc_fixed>;
180 };
181
182 sdcc3: sdcc@12180000 {
183 compatible = "arm,pl18x", "arm,primecell";
184 arm,primecell-periphid = <0x00051180>;
185 status = "disabled";
186 reg = <0x12180000 0x8000>;
187 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-names = "cmd_irq";
189 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
190 clock-names = "mclk", "apb_pclk";
191 bus-width = <4>;
192 cap-sd-highspeed;
193 cap-mmc-highspeed;
194 max-frequency = <48000000>;
195 no-1-8-v;
196 vmmc-supply = <&vsdcc_fixed>;
197 };
106 }; 198 };
107 }; 199 };
200
108}; 201};
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 8f75cc4c8340..7f70fae90959 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -1,3 +1,5 @@
1#include <dt-bindings/input/input.h>
2
1#include "qcom-msm8960.dtsi" 3#include "qcom-msm8960.dtsi"
2 4
3/ { 5/ {
@@ -12,5 +14,30 @@
12 status = "ok"; 14 status = "ok";
13 }; 15 };
14 }; 16 };
17
18 amba {
19 /* eMMC */
20 sdcc1: sdcc@12400000 {
21 status = "okay";
22 };
23
24 /* External micro SD card */
25 sdcc3: sdcc@12180000 {
26 status = "okay";
27 };
28 };
29 };
30};
31
32&pmicintc {
33 keypad@148 {
34 linux,keymap = <
35 MATRIX_KEY(0, 0, KEY_VOLUMEUP)
36 MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
37 MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
38 MATRIX_KEY(0, 3, KEY_CAMERA)
39 >;
40 keypad,num-rows = <1>;
41 keypad,num-columns = <5>;
15 }; 42 };
16}; 43};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 5303e53e34dc..e1b0d5cd9e3c 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -2,6 +2,7 @@
2 2
3/include/ "skeleton.dtsi" 3/include/ "skeleton.dtsi"
4 4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/soc/qcom,gsbi.h> 7#include <dt-bindings/soc/qcom,gsbi.h>
7 8
@@ -143,6 +144,43 @@
143 compatible = "qcom,ssbi"; 144 compatible = "qcom,ssbi";
144 reg = <0x500000 0x1000>; 145 reg = <0x500000 0x1000>;
145 qcom,controller-type = "pmic-arbiter"; 146 qcom,controller-type = "pmic-arbiter";
147
148 pmicintc: pmic@0 {
149 compatible = "qcom,pm8921";
150 interrupt-parent = <&msmgpio>;
151 interrupts = <104 8>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 pwrkey@1c {
158 compatible = "qcom,pm8921-pwrkey";
159 reg = <0x1c>;
160 interrupt-parent = <&pmicintc>;
161 interrupts = <50 1>, <51 1>;
162 debounce = <15625>;
163 pull-up;
164 };
165
166 keypad@148 {
167 compatible = "qcom,pm8921-keypad";
168 reg = <0x148>;
169 interrupt-parent = <&pmicintc>;
170 interrupts = <74 1>, <75 1>;
171 debounce = <15>;
172 scan-delay = <32>;
173 row-hold = <91500>;
174 };
175
176 rtc@11d {
177 compatible = "qcom,pm8921-rtc";
178 interrupt-parent = <&pmicintc>;
179 interrupts = <39 1>;
180 reg = <0x11d>;
181 allow-set-time;
182 };
183 };
146 }; 184 };
147 185
148 rng@1a500000 { 186 rng@1a500000 {
@@ -151,5 +189,54 @@
151 clocks = <&gcc PRNG_CLK>; 189 clocks = <&gcc PRNG_CLK>;
152 clock-names = "core"; 190 clock-names = "core";
153 }; 191 };
192
193 /* Temporary fixed regulator */
194 vsdcc_fixed: vsdcc-regulator {
195 compatible = "regulator-fixed";
196 regulator-name = "SDCC Power";
197 regulator-min-microvolt = <2700000>;
198 regulator-max-microvolt = <2700000>;
199 regulator-always-on;
200 };
201
202 amba {
203 compatible = "arm,amba-bus";
204 #address-cells = <1>;
205 #size-cells = <1>;
206 ranges;
207 sdcc1: sdcc@12400000 {
208 status = "disabled";
209 compatible = "arm,pl18x", "arm,primecell";
210 arm,primecell-periphid = <0x00051180>;
211 reg = <0x12400000 0x8000>;
212 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-names = "cmd_irq";
214 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
215 clock-names = "mclk", "apb_pclk";
216 bus-width = <8>;
217 max-frequency = <96000000>;
218 non-removable;
219 cap-sd-highspeed;
220 cap-mmc-highspeed;
221 vmmc-supply = <&vsdcc_fixed>;
222 };
223
224 sdcc3: sdcc@12180000 {
225 compatible = "arm,pl18x", "arm,primecell";
226 arm,primecell-periphid = <0x00051180>;
227 status = "disabled";
228 reg = <0x12180000 0x8000>;
229 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-names = "cmd_irq";
231 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
232 clock-names = "mclk", "apb_pclk";
233 bus-width = <4>;
234 cap-sd-highspeed;
235 cap-mmc-highspeed;
236 max-frequency = <192000000>;
237 no-1-8-v;
238 vmmc-supply = <&vsdcc_fixed>;
239 };
240 };
154 }; 241 };
155}; 242};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 69dca2aca25a..e265ec16a787 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,8 +1,8 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include "skeleton.dtsi" 3#include <dt-bindings/interrupt-controller/irq.h>
4
5#include <dt-bindings/clock/qcom,gcc-msm8974.h> 4#include <dt-bindings/clock/qcom,gcc-msm8974.h>
5#include "skeleton.dtsi"
6 6
7/ { 7/ {
8 model = "Qualcomm MSM8974"; 8 model = "Qualcomm MSM8974";
@@ -236,5 +236,16 @@
236 #interrupt-cells = <2>; 236 #interrupt-cells = <2>;
237 interrupts = <0 208 0>; 237 interrupts = <0 208 0>;
238 }; 238 };
239
240 blsp_i2c11: i2c@f9967000 {
241 status = "disable";
242 compatible = "qcom,i2c-qup-v2.1.1";
243 reg = <0xf9967000 0x1000>;
244 interrupts = <0 105 IRQ_TYPE_NONE>;
245 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
246 clock-names = "core", "iface";
247 #address-cells = <1>;
248 #size-cells = <0>;
249 };
239 }; 250 };
240}; 251};
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 20705467f4c9..a3ed23c0a8f5 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -43,6 +43,10 @@
43 clock-frequency = <48000000>; 43 clock-frequency = <48000000>;
44}; 44};
45 45
46&mtu2 {
47 status = "ok";
48};
49
46&i2c2 { 50&i2c2 {
47 status = "okay"; 51 status = "okay";
48 clock-frequency = <400000>; 52 clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index bdee22541189..801a556e264b 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -229,6 +229,16 @@
229 status = "disabled"; 229 status = "disabled";
230 }; 230 };
231 231
232 mtu2: timer@fcff0000 {
233 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
234 reg = <0xfcff0000 0x400>;
235 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "tgi0a";
237 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
238 clock-names = "fck";
239 status = "disabled";
240 };
241
232 scif0: serial@e8007000 { 242 scif0: serial@e8007000 {
233 compatible = "renesas,scif-r7s72100", "renesas,scif"; 243 compatible = "renesas,scif-r7s72100", "renesas,scif";
234 reg = <0xe8007000 64>; 244 reg = <0xe8007000 64>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index d8ec5058c351..ef152e384822 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -51,7 +51,7 @@
51 }; 51 };
52 52
53 irqc0: interrupt-controller@e61c0000 { 53 irqc0: interrupt-controller@e61c0000 {
54 compatible = "renesas,irqc"; 54 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
55 #interrupt-cells = <2>; 55 #interrupt-cells = <2>;
56 interrupt-controller; 56 interrupt-controller;
57 reg = <0 0xe61c0000 0 0x200>; 57 reg = <0 0xe61c0000 0 0x200>;
@@ -90,7 +90,7 @@
90 }; 90 };
91 91
92 irqc1: interrupt-controller@e61c0200 { 92 irqc1: interrupt-controller@e61c0200 {
93 compatible = "renesas,irqc"; 93 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
94 #interrupt-cells = <2>; 94 #interrupt-cells = <2>;
95 interrupt-controller; 95 interrupt-controller;
96 reg = <0 0xe61c0200 0 0x200>; 96 reg = <0 0xe61c0200 0 0x200>;
@@ -165,7 +165,7 @@
165 }; 165 };
166 166
167 thermal@e61f0000 { 167 thermal@e61f0000 {
168 compatible = "renesas,rcar-thermal"; 168 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
169 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 169 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
170 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 170 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
171 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 171 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
deleted file mode 100644
index ee9e7d5c97a9..000000000000
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * Reference Device Tree Source for the armadillo 800 eva board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7740.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/pwm/pwm.h>
17
18/ {
19 model = "armadillo 800 eva reference";
20 compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
21
22 aliases {
23 serial1 = &scifa1;
24 };
25
26 chosen {
27 bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
28 };
29
30 memory {
31 device_type = "memory";
32 reg = <0x40000000 0x20000000>;
33 };
34
35 reg_3p3v: regulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-3.3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 regulator-boot-on;
42 };
43
44 vcc_sdhi0: regulator@1 {
45 compatible = "regulator-fixed";
46
47 regulator-name = "SDHI0 Vcc";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50
51 gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
55 vccq_sdhi0: regulator@2 {
56 compatible = "regulator-gpio";
57
58 regulator-name = "SDHI0 VccQ";
59 regulator-min-microvolt = <1800000>;
60 regulator-max-microvolt = <3300000>;
61 vin-supply = <&vcc_sdhi0>;
62
63 enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
64 gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
65 states = <3300000 0
66 1800000 1>;
67
68 enable-active-high;
69 };
70
71 reg_5p0v: regulator@3 {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-5.0V";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 regulator-always-on;
77 regulator-boot-on;
78 };
79
80 gpio-keys {
81 compatible = "gpio-keys";
82
83 power-key {
84 gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
85 linux,code = <KEY_POWER>;
86 label = "SW3";
87 gpio-key,wakeup;
88 };
89
90 back-key {
91 gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
92 linux,code = <KEY_BACK>;
93 label = "SW4";
94 };
95
96 menu-key {
97 gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_MENU>;
99 label = "SW5";
100 };
101
102 home-key {
103 gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
104 linux,code = <KEY_HOME>;
105 label = "SW6";
106 };
107 };
108
109 leds {
110 compatible = "gpio-leds";
111 led3 {
112 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
113 label = "LED3";
114 };
115 led4 {
116 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
117 label = "LED4";
118 };
119 led5 {
120 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
121 label = "LED5";
122 };
123 led6 {
124 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
125 label = "LED6";
126 };
127 };
128
129 i2c2: i2c@2 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "i2c-gpio";
133 gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
134 &pfc 91 GPIO_ACTIVE_HIGH /* scl */
135 >;
136 i2c-gpio,delay-us = <5>;
137 };
138
139 backlight {
140 compatible = "pwm-backlight";
141 pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
142 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
143 default-brightness-level = <9>;
144 pinctrl-0 = <&backlight_pins>;
145 pinctrl-names = "default";
146 power-supply = <&reg_5p0v>;
147 enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
148 };
149
150 sound {
151 compatible = "simple-audio-card";
152
153 simple-audio-card,format = "i2s";
154
155 simple-audio-card,cpu {
156 sound-dai = <&sh_fsi2 0>;
157 bitclock-inversion;
158 };
159
160 simple-audio-card,codec {
161 sound-dai = <&wm8978>;
162 bitclock-master;
163 frame-master;
164 system-clock-frequency = <12288000>;
165 };
166 };
167};
168
169&ether {
170 pinctrl-0 = <&ether_pins>;
171 pinctrl-names = "default";
172
173 phy-handle = <&phy0>;
174 status = "ok";
175
176 phy0: ethernet-phy@0 {
177 reg = <0>;
178 };
179};
180
181&i2c0 {
182 status = "okay";
183 touchscreen@55 {
184 compatible = "sitronix,st1232";
185 reg = <0x55>;
186 interrupt-parent = <&irqpin1>;
187 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
188 pinctrl-0 = <&st1232_pins>;
189 pinctrl-names = "default";
190 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
191 };
192
193 wm8978: wm8978@1a {
194 #sound-dai-cells = <0>;
195 compatible = "wlf,wm8978";
196 reg = <0x1a>;
197 };
198};
199
200&i2c2 {
201 status = "okay";
202 rtc@30 {
203 compatible = "sii,s35390a";
204 reg = <0x30>;
205 };
206};
207
208&pfc {
209 ether_pins: ether {
210 renesas,groups = "gether_mii", "gether_int";
211 renesas,function = "gether";
212 };
213
214 scifa1_pins: serial1 {
215 renesas,groups = "scifa1_data";
216 renesas,function = "scifa1";
217 };
218
219 st1232_pins: touchscreen {
220 renesas,groups = "intc_irq10";
221 renesas,function = "intc";
222 };
223
224 backlight_pins: backlight {
225 renesas,groups = "tpu0_to2_1";
226 renesas,function = "tpu0";
227 };
228
229 mmc0_pins: mmc0 {
230 renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
231 renesas,function = "mmc0";
232 };
233
234 sdhi0_pins: sd0 {
235 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
236 renesas,function = "sdhi0";
237 };
238
239 fsia_pins: sounda {
240 renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
241 "fsia_data_in_1", "fsia_data_out_0";
242 renesas,function = "fsia";
243 };
244};
245
246&tpu {
247 status = "okay";
248};
249
250&mmcif0 {
251 pinctrl-0 = <&mmc0_pins>;
252 pinctrl-names = "default";
253
254 vmmc-supply = <&reg_3p3v>;
255 bus-width = <8>;
256 non-removable;
257 status = "okay";
258};
259
260&scifa1 {
261 pinctrl-0 = <&scifa1_pins>;
262 pinctrl-names = "default";
263
264 status = "okay";
265};
266
267&sdhi0 {
268 pinctrl-0 = <&sdhi0_pins>;
269 pinctrl-names = "default";
270
271 vmmc-supply = <&vcc_sdhi0>;
272 vqmmc-supply = <&vccq_sdhi0>;
273 bus-width = <4>;
274 cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
275 status = "okay";
276};
277
278&sh_fsi2 {
279 pinctrl-0 = <&fsia_pins>;
280 pinctrl-names = "default";
281
282 status = "okay";
283};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index a06a11e1a840..effb7b46f131 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -10,10 +10,18 @@
10 10
11/dts-v1/; 11/dts-v1/;
12#include "r8a7740.dtsi" 12#include "r8a7740.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/pwm/pwm.h>
13 17
14/ { 18/ {
15 model = "armadillo 800 eva"; 19 model = "armadillo 800 eva";
16 compatible = "renesas,armadillo800eva"; 20 compatible = "renesas,armadillo800eva", "renesas,r8a7740";
21
22 aliases {
23 serial1 = &scifa1;
24 };
17 25
18 chosen { 26 chosen {
19 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 27 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
@@ -23,4 +31,270 @@
23 device_type = "memory"; 31 device_type = "memory";
24 reg = <0x40000000 0x20000000>; 32 reg = <0x40000000 0x20000000>;
25 }; 33 };
34
35 reg_3p3v: regulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-3.3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 regulator-boot-on;
42 };
43
44 vcc_sdhi0: regulator@1 {
45 compatible = "regulator-fixed";
46
47 regulator-name = "SDHI0 Vcc";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50
51 gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
55 vccq_sdhi0: regulator@2 {
56 compatible = "regulator-gpio";
57
58 regulator-name = "SDHI0 VccQ";
59 regulator-min-microvolt = <1800000>;
60 regulator-max-microvolt = <3300000>;
61 vin-supply = <&vcc_sdhi0>;
62
63 enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
64 gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
65 states = <3300000 0
66 1800000 1>;
67
68 enable-active-high;
69 };
70
71 reg_5p0v: regulator@3 {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-5.0V";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 regulator-always-on;
77 regulator-boot-on;
78 };
79
80 gpio-keys {
81 compatible = "gpio-keys";
82
83 power-key {
84 gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
85 linux,code = <KEY_POWER>;
86 label = "SW3";
87 gpio-key,wakeup;
88 };
89
90 back-key {
91 gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
92 linux,code = <KEY_BACK>;
93 label = "SW4";
94 };
95
96 menu-key {
97 gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_MENU>;
99 label = "SW5";
100 };
101
102 home-key {
103 gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
104 linux,code = <KEY_HOME>;
105 label = "SW6";
106 };
107 };
108
109 leds {
110 compatible = "gpio-leds";
111 led3 {
112 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
113 label = "LED3";
114 };
115 led4 {
116 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
117 label = "LED4";
118 };
119 led5 {
120 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
121 label = "LED5";
122 };
123 led6 {
124 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
125 label = "LED6";
126 };
127 };
128
129 i2c2: i2c@2 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "i2c-gpio";
133 gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
134 &pfc 91 GPIO_ACTIVE_HIGH /* scl */
135 >;
136 i2c-gpio,delay-us = <5>;
137 };
138
139 backlight {
140 compatible = "pwm-backlight";
141 pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
142 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
143 default-brightness-level = <9>;
144 pinctrl-0 = <&backlight_pins>;
145 pinctrl-names = "default";
146 power-supply = <&reg_5p0v>;
147 enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
148 };
149
150 sound {
151 compatible = "simple-audio-card";
152
153 simple-audio-card,format = "i2s";
154
155 simple-audio-card,cpu {
156 sound-dai = <&sh_fsi2 0>;
157 bitclock-inversion;
158 };
159
160 simple-audio-card,codec {
161 sound-dai = <&wm8978>;
162 bitclock-master;
163 frame-master;
164 system-clock-frequency = <12288000>;
165 };
166 };
167};
168
169&ether {
170 pinctrl-0 = <&ether_pins>;
171 pinctrl-names = "default";
172
173 phy-handle = <&phy0>;
174 status = "ok";
175
176 phy0: ethernet-phy@0 {
177 reg = <0>;
178 };
179};
180
181&extal1_clk {
182 clock-frequency = <25000000>;
183};
184&extal2_clk {
185 clock-frequency = <48000000>;
186};
187&fsibck_clk {
188 clock-frequency = <12288000>;
189};
190&cpg_clocks {
191 renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
192};
193
194&cmt1 {
195 status = "ok";
196};
197
198&i2c0 {
199 status = "okay";
200 touchscreen@55 {
201 compatible = "sitronix,st1232";
202 reg = <0x55>;
203 interrupt-parent = <&irqpin1>;
204 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
205 pinctrl-0 = <&st1232_pins>;
206 pinctrl-names = "default";
207 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
208 };
209
210 wm8978: wm8978@1a {
211 #sound-dai-cells = <0>;
212 compatible = "wlf,wm8978";
213 reg = <0x1a>;
214 };
215};
216
217&i2c2 {
218 status = "okay";
219 rtc@30 {
220 compatible = "sii,s35390a";
221 reg = <0x30>;
222 };
223};
224
225&pfc {
226 ether_pins: ether {
227 renesas,groups = "gether_mii", "gether_int";
228 renesas,function = "gether";
229 };
230
231 scifa1_pins: serial1 {
232 renesas,groups = "scifa1_data";
233 renesas,function = "scifa1";
234 };
235
236 st1232_pins: touchscreen {
237 renesas,groups = "intc_irq10";
238 renesas,function = "intc";
239 };
240
241 backlight_pins: backlight {
242 renesas,groups = "tpu0_to2_1";
243 renesas,function = "tpu0";
244 };
245
246 mmc0_pins: mmc0 {
247 renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
248 renesas,function = "mmc0";
249 };
250
251 sdhi0_pins: sd0 {
252 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
253 renesas,function = "sdhi0";
254 };
255
256 fsia_pins: sounda {
257 renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
258 "fsia_data_in_1", "fsia_data_out_0";
259 renesas,function = "fsia";
260 };
261};
262
263&tpu {
264 status = "okay";
265};
266
267&mmcif0 {
268 pinctrl-0 = <&mmc0_pins>;
269 pinctrl-names = "default";
270
271 vmmc-supply = <&reg_3p3v>;
272 bus-width = <8>;
273 non-removable;
274 status = "okay";
275};
276
277&scifa1 {
278 pinctrl-0 = <&scifa1_pins>;
279 pinctrl-names = "default";
280
281 status = "okay";
282};
283
284&sdhi0 {
285 pinctrl-0 = <&sdhi0_pins>;
286 pinctrl-names = "default";
287
288 vmmc-supply = <&vcc_sdhi0>;
289 vqmmc-supply = <&vccq_sdhi0>;
290 bus-width = <4>;
291 cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
292 status = "okay";
293};
294
295&sh_fsi2 {
296 pinctrl-0 = <&fsia_pins>;
297 pinctrl-names = "default";
298
299 status = "okay";
26}; 300};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index bda18fb3d9e5..d46c213a17ad 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -10,6 +10,7 @@
10 10
11/include/ "skeleton.dtsi" 11/include/ "skeleton.dtsi"
12 12
13#include <dt-bindings/clock/r8a7740-clock.h>
13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
14 15
15/ { 16/ {
@@ -40,6 +41,18 @@
40 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 41 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
41 }; 42 };
42 43
44 cmt1: timer@e6138000 {
45 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
46 reg = <0xe6138000 0x170>;
47 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
49 clock-names = "fck";
50
51 renesas,channels-mask = <0x3f>;
52
53 status = "disabled";
54 };
55
43 /* irqpin0: IRQ0 - IRQ7 */ 56 /* irqpin0: IRQ0 - IRQ7 */
44 irqpin0: irqpin@e6900000 { 57 irqpin0: irqpin@e6900000 {
45 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 58 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
@@ -125,7 +138,7 @@
125 reg = <0xe9a00000 0x800>, 138 reg = <0xe9a00000 0x800>,
126 <0xe9a01800 0x800>; 139 <0xe9a01800 0x800>;
127 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 140 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
128 /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */ 141 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
129 phy-mode = "mii"; 142 phy-mode = "mii";
130 #address-cells = <1>; 143 #address-cells = <1>;
131 #size-cells = <0>; 144 #size-cells = <0>;
@@ -141,6 +154,7 @@
141 0 202 IRQ_TYPE_LEVEL_HIGH 154 0 202 IRQ_TYPE_LEVEL_HIGH
142 0 203 IRQ_TYPE_LEVEL_HIGH 155 0 203 IRQ_TYPE_LEVEL_HIGH
143 0 204 IRQ_TYPE_LEVEL_HIGH>; 156 0 204 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
144 status = "disabled"; 158 status = "disabled";
145 }; 159 };
146 160
@@ -153,6 +167,7 @@
153 0 71 IRQ_TYPE_LEVEL_HIGH 167 0 71 IRQ_TYPE_LEVEL_HIGH
154 0 72 IRQ_TYPE_LEVEL_HIGH 168 0 72 IRQ_TYPE_LEVEL_HIGH
155 0 73 IRQ_TYPE_LEVEL_HIGH>; 169 0 73 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
156 status = "disabled"; 171 status = "disabled";
157 }; 172 };
158 173
@@ -160,6 +175,8 @@
160 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 175 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
161 reg = <0xe6c40000 0x100>; 176 reg = <0xe6c40000 0x100>;
162 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 177 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
179 clock-names = "sci_ick";
163 status = "disabled"; 180 status = "disabled";
164 }; 181 };
165 182
@@ -167,6 +184,8 @@
167 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 184 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
168 reg = <0xe6c50000 0x100>; 185 reg = <0xe6c50000 0x100>;
169 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 186 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
188 clock-names = "sci_ick";
170 status = "disabled"; 189 status = "disabled";
171 }; 190 };
172 191
@@ -174,6 +193,8 @@
174 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 193 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
175 reg = <0xe6c60000 0x100>; 194 reg = <0xe6c60000 0x100>;
176 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
197 clock-names = "sci_ick";
177 status = "disabled"; 198 status = "disabled";
178 }; 199 };
179 200
@@ -181,6 +202,8 @@
181 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 202 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
182 reg = <0xe6c70000 0x100>; 203 reg = <0xe6c70000 0x100>;
183 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 204 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
206 clock-names = "sci_ick";
184 status = "disabled"; 207 status = "disabled";
185 }; 208 };
186 209
@@ -188,6 +211,8 @@
188 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 211 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
189 reg = <0xe6c80000 0x100>; 212 reg = <0xe6c80000 0x100>;
190 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 213 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
215 clock-names = "sci_ick";
191 status = "disabled"; 216 status = "disabled";
192 }; 217 };
193 218
@@ -195,6 +220,8 @@
195 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 220 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
196 reg = <0xe6cb0000 0x100>; 221 reg = <0xe6cb0000 0x100>;
197 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 222 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
224 clock-names = "sci_ick";
198 status = "disabled"; 225 status = "disabled";
199 }; 226 };
200 227
@@ -202,6 +229,8 @@
202 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 229 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
203 reg = <0xe6cc0000 0x100>; 230 reg = <0xe6cc0000 0x100>;
204 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 231 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
233 clock-names = "sci_ick";
205 status = "disabled"; 234 status = "disabled";
206 }; 235 };
207 236
@@ -209,6 +238,8 @@
209 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 238 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
210 reg = <0xe6cd0000 0x100>; 239 reg = <0xe6cd0000 0x100>;
211 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
242 clock-names = "sci_ick";
212 status = "disabled"; 243 status = "disabled";
213 }; 244 };
214 245
@@ -216,6 +247,8 @@
216 compatible = "renesas,scifb-r8a7740", "renesas,scifb"; 247 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
217 reg = <0xe6c30000 0x100>; 248 reg = <0xe6c30000 0x100>;
218 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 249 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
251 clock-names = "sci_ick";
219 status = "disabled"; 252 status = "disabled";
220 }; 253 };
221 254
@@ -239,6 +272,7 @@
239 tpu: pwm@e6600000 { 272 tpu: pwm@e6600000 {
240 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 273 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
241 reg = <0xe6600000 0x100>; 274 reg = <0xe6600000 0x100>;
275 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
242 status = "disabled"; 276 status = "disabled";
243 #pwm-cells = <3>; 277 #pwm-cells = <3>;
244 }; 278 };
@@ -248,6 +282,7 @@
248 reg = <0xe6bd0000 0x100>; 282 reg = <0xe6bd0000 0x100>;
249 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 283 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
250 0 57 IRQ_TYPE_LEVEL_HIGH>; 284 0 57 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
251 status = "disabled"; 286 status = "disabled";
252 }; 287 };
253 288
@@ -257,6 +292,7 @@
257 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH 292 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
258 0 118 IRQ_TYPE_LEVEL_HIGH 293 0 118 IRQ_TYPE_LEVEL_HIGH
259 0 119 IRQ_TYPE_LEVEL_HIGH>; 294 0 119 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
260 cap-sd-highspeed; 296 cap-sd-highspeed;
261 cap-sdio-irq; 297 cap-sdio-irq;
262 status = "disabled"; 298 status = "disabled";
@@ -268,6 +304,7 @@
268 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH 304 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
269 0 122 IRQ_TYPE_LEVEL_HIGH 305 0 122 IRQ_TYPE_LEVEL_HIGH
270 0 123 IRQ_TYPE_LEVEL_HIGH>; 306 0 123 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
271 cap-sd-highspeed; 308 cap-sd-highspeed;
272 cap-sdio-irq; 309 cap-sdio-irq;
273 status = "disabled"; 310 status = "disabled";
@@ -279,6 +316,7 @@
279 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH 316 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
280 0 126 IRQ_TYPE_LEVEL_HIGH 317 0 126 IRQ_TYPE_LEVEL_HIGH
281 0 127 IRQ_TYPE_LEVEL_HIGH>; 318 0 127 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
282 cap-sd-highspeed; 320 cap-sd-highspeed;
283 cap-sdio-irq; 321 cap-sdio-irq;
284 status = "disabled"; 322 status = "disabled";
@@ -289,6 +327,186 @@
289 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; 327 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
290 reg = <0xfe1f0000 0x400>; 328 reg = <0xfe1f0000 0x400>;
291 interrupts = <0 9 0x4>; 329 interrupts = <0 9 0x4>;
330 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
292 status = "disabled"; 331 status = "disabled";
293 }; 332 };
333
334 clocks {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 ranges;
338
339 /* External root clock */
340 extalr_clk: extalr_clk {
341 compatible = "fixed-clock";
342 #clock-cells = <0>;
343 clock-frequency = <32768>;
344 clock-output-names = "extalr";
345 };
346 extal1_clk: extal1_clk {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <0>;
350 clock-output-names = "extal1";
351 };
352 extal2_clk: extal2_clk {
353 compatible = "fixed-clock";
354 #clock-cells = <0>;
355 clock-frequency = <0>;
356 clock-output-names = "extal2";
357 };
358 dv_clk: dv_clk {
359 compatible = "fixed-clock";
360 #clock-cells = <0>;
361 clock-frequency = <27000000>;
362 clock-output-names = "dv";
363 };
364 fsiack_clk: fsiack_clk {
365 compatible = "fixed-clock";
366 #clock-cells = <0>;
367 clock-frequency = <0>;
368 clock-output-names = "fsiack";
369 };
370 fsibck_clk: fsibck_clk {
371 compatible = "fixed-clock";
372 #clock-cells = <0>;
373 clock-frequency = <0>;
374 clock-output-names = "fsibck";
375 };
376
377 /* Special CPG clocks */
378 cpg_clocks: cpg_clocks@e6150000 {
379 compatible = "renesas,r8a7740-cpg-clocks";
380 reg = <0xe6150000 0x10000>;
381 clocks = <&extal1_clk>, <&extalr_clk>;
382 #clock-cells = <1>;
383 clock-output-names = "system", "pllc0", "pllc1",
384 "pllc2", "r",
385 "usb24s",
386 "i", "zg", "b", "m1", "hp",
387 "hpp", "usbp", "s", "zb", "m3",
388 "cp";
389 };
390
391 /* Variable factor clocks (DIV6) */
392 sub_clk: sub_clk@e6150080 {
393 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
394 reg = <0xe6150080 4>;
395 clocks = <&pllc1_div2_clk>;
396 #clock-cells = <0>;
397 clock-output-names = "sub";
398 };
399
400 /* Fixed factor clocks */
401 pllc1_div2_clk: pllc1_div2_clk {
402 compatible = "fixed-factor-clock";
403 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
404 #clock-cells = <0>;
405 clock-div = <2>;
406 clock-mult = <1>;
407 clock-output-names = "pllc1_div2";
408 };
409 extal1_div2_clk: extal1_div2_clk {
410 compatible = "fixed-factor-clock";
411 clocks = <&extal1_clk>;
412 #clock-cells = <0>;
413 clock-div = <2>;
414 clock-mult = <1>;
415 clock-output-names = "extal1_div2";
416 };
417
418 /* Gate clocks */
419 subck_clks: subck_clks@e6150080 {
420 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
421 reg = <0xe6150080 4>;
422 clocks = <&sub_clk>, <&sub_clk>;
423 #clock-cells = <1>;
424 renesas,clock-indices = <
425 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
426 >;
427 clock-output-names =
428 "subck", "subck2";
429 };
430 mstp1_clks: mstp1_clks@e6150134 {
431 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
432 reg = <0xe6150134 4>, <0xe6150038 4>;
433 clocks = <&cpg_clocks R8A7740_CLK_S>,
434 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
435 <&cpg_clocks R8A7740_CLK_B>,
436 <&sub_clk>, <&sub_clk>,
437 <&cpg_clocks R8A7740_CLK_B>;
438 #clock-cells = <1>;
439 renesas,clock-indices = <
440 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
441 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
442 R8A7740_CLK_LCDC0
443 >;
444 clock-output-names =
445 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
446 "tmu1", "lcdc0";
447 };
448 mstp2_clks: mstp2_clks@e6150138 {
449 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
450 reg = <0xe6150138 4>, <0xe6150040 4>;
451 clocks = <&sub_clk>, <&sub_clk>,
452 <&cpg_clocks R8A7740_CLK_HP>,
453 <&cpg_clocks R8A7740_CLK_HP>,
454 <&cpg_clocks R8A7740_CLK_HP>,
455 <&cpg_clocks R8A7740_CLK_HP>,
456 <&sub_clk>, <&sub_clk>, <&sub_clk>,
457 <&sub_clk>, <&sub_clk>, <&sub_clk>,
458 <&sub_clk>;
459 #clock-cells = <1>;
460 renesas,clock-indices = <
461 R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
462 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
463 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
464 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
465 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
466 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
467 R8A7740_CLK_SCIFA4
468 >;
469 clock-output-names =
470 "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
471 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
472 "scifa2", "scifa3", "scifa4";
473 };
474 mstp3_clks: mstp3_clks@e615013c {
475 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
476 reg = <0xe615013c 4>, <0xe6150048 4>;
477 clocks = <&cpg_clocks R8A7740_CLK_R>,
478 <&cpg_clocks R8A7740_CLK_HP>,
479 <&sub_clk>,
480 <&cpg_clocks R8A7740_CLK_HP>,
481 <&cpg_clocks R8A7740_CLK_HP>,
482 <&cpg_clocks R8A7740_CLK_HP>,
483 <&cpg_clocks R8A7740_CLK_HP>,
484 <&cpg_clocks R8A7740_CLK_HP>,
485 <&cpg_clocks R8A7740_CLK_HP>;
486 #clock-cells = <1>;
487 renesas,clock-indices = <
488 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
489 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
490 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
491 >;
492 clock-output-names =
493 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
494 "mmc", "gether", "tpu0";
495 };
496 mstp4_clks: mstp4_clks@e6150140 {
497 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
498 reg = <0xe6150140 4>, <0xe615004c 4>;
499 clocks = <&cpg_clocks R8A7740_CLK_HP>,
500 <&cpg_clocks R8A7740_CLK_HP>,
501 <&cpg_clocks R8A7740_CLK_HP>,
502 <&cpg_clocks R8A7740_CLK_HP>;
503 #clock-cells = <1>;
504 renesas,clock-indices = <
505 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
506 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
507 >;
508 clock-output-names =
509 "usbhost", "sdhi2", "usbfunc", "usphy";
510 };
511 };
294}; 512};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ecfdf4b01b5a..315ec62cb96b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -23,8 +23,14 @@
23 interrupt-parent = <&gic>; 23 interrupt-parent = <&gic>;
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
26 cpu@0 { 29 cpu@0 {
30 device_type = "cpu";
27 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 reg = <0>;
33 clock-frequency = <800000000>;
28 }; 34 };
29 }; 35 };
30 36
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 5745555df943..c160404e4d40 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -78,6 +78,10 @@
78 clock-frequency = <31250000>; 78 clock-frequency = <31250000>;
79}; 79};
80 80
81&tmu0 {
82 status = "okay";
83};
84
81&pfc { 85&pfc {
82 lan0_pins: lan0 { 86 lan0_pins: lan0 {
83 intc { 87 intc {
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 58d0d952d60e..7cfba9aa1b41 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -199,7 +199,6 @@
199 scif0: serial@ffe40000 { 199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif"; 200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>; 201 reg = <0xffe40000 0x100>;
202 interrupt-parent = <&gic>;
203 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 202 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cpg_clocks R8A7779_CLK_P>; 203 clocks = <&cpg_clocks R8A7779_CLK_P>;
205 clock-names = "sci_ick"; 204 clock-names = "sci_ick";
@@ -209,7 +208,6 @@
209 scif1: serial@ffe41000 { 208 scif1: serial@ffe41000 {
210 compatible = "renesas,scif-r8a7779", "renesas,scif"; 209 compatible = "renesas,scif-r8a7779", "renesas,scif";
211 reg = <0xffe41000 0x100>; 210 reg = <0xffe41000 0x100>;
212 interrupt-parent = <&gic>;
213 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cpg_clocks R8A7779_CLK_P>; 212 clocks = <&cpg_clocks R8A7779_CLK_P>;
215 clock-names = "sci_ick"; 213 clock-names = "sci_ick";
@@ -219,7 +217,6 @@
219 scif2: serial@ffe42000 { 217 scif2: serial@ffe42000 {
220 compatible = "renesas,scif-r8a7779", "renesas,scif"; 218 compatible = "renesas,scif-r8a7779", "renesas,scif";
221 reg = <0xffe42000 0x100>; 219 reg = <0xffe42000 0x100>;
222 interrupt-parent = <&gic>;
223 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; 220 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cpg_clocks R8A7779_CLK_P>; 221 clocks = <&cpg_clocks R8A7779_CLK_P>;
225 clock-names = "sci_ick"; 222 clock-names = "sci_ick";
@@ -229,7 +226,6 @@
229 scif3: serial@ffe43000 { 226 scif3: serial@ffe43000 {
230 compatible = "renesas,scif-r8a7779", "renesas,scif"; 227 compatible = "renesas,scif-r8a7779", "renesas,scif";
231 reg = <0xffe43000 0x100>; 228 reg = <0xffe43000 0x100>;
232 interrupt-parent = <&gic>;
233 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; 229 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cpg_clocks R8A7779_CLK_P>; 230 clocks = <&cpg_clocks R8A7779_CLK_P>;
235 clock-names = "sci_ick"; 231 clock-names = "sci_ick";
@@ -239,7 +235,6 @@
239 scif4: serial@ffe44000 { 235 scif4: serial@ffe44000 {
240 compatible = "renesas,scif-r8a7779", "renesas,scif"; 236 compatible = "renesas,scif-r8a7779", "renesas,scif";
241 reg = <0xffe44000 0x100>; 237 reg = <0xffe44000 0x100>;
242 interrupt-parent = <&gic>;
243 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg_clocks R8A7779_CLK_P>; 239 clocks = <&cpg_clocks R8A7779_CLK_P>;
245 clock-names = "sci_ick"; 240 clock-names = "sci_ick";
@@ -249,7 +244,6 @@
249 scif5: serial@ffe45000 { 244 scif5: serial@ffe45000 {
250 compatible = "renesas,scif-r8a7779", "renesas,scif"; 245 compatible = "renesas,scif-r8a7779", "renesas,scif";
251 reg = <0xffe45000 0x100>; 246 reg = <0xffe45000 0x100>;
252 interrupt-parent = <&gic>;
253 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cpg_clocks R8A7779_CLK_P>; 248 clocks = <&cpg_clocks R8A7779_CLK_P>;
255 clock-names = "sci_ick"; 249 clock-names = "sci_ick";
@@ -262,10 +256,52 @@
262 }; 256 };
263 257
264 thermal@ffc48000 { 258 thermal@ffc48000 {
265 compatible = "renesas,rcar-thermal"; 259 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
266 reg = <0xffc48000 0x38>; 260 reg = <0xffc48000 0x38>;
267 }; 261 };
268 262
263 tmu0: timer@ffd80000 {
264 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
265 reg = <0xffd80000 0x30>;
266 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
267 <0 33 IRQ_TYPE_LEVEL_HIGH>,
268 <0 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
270 clock-names = "fck";
271
272 #renesas,channels = <3>;
273
274 status = "disabled";
275 };
276
277 tmu1: timer@ffd81000 {
278 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
279 reg = <0xffd81000 0x30>;
280 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
281 <0 37 IRQ_TYPE_LEVEL_HIGH>,
282 <0 38 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
284 clock-names = "fck";
285
286 #renesas,channels = <3>;
287
288 status = "disabled";
289 };
290
291 tmu2: timer@ffd82000 {
292 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
293 reg = <0xffd82000 0x30>;
294 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
295 <0 41 IRQ_TYPE_LEVEL_HIGH>,
296 <0 42 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
298 clock-names = "fck";
299
300 #renesas,channels = <3>;
301
302 status = "disabled";
303 };
304
269 sata: sata@fc600000 { 305 sata: sata@fc600000 {
270 compatible = "renesas,rcar-sata"; 306 compatible = "renesas,rcar-sata";
271 reg = <0xfc600000 0x2000>; 307 reg = <0xfc600000 0x2000>;
@@ -404,10 +440,10 @@
404 /* Gate clocks */ 440 /* Gate clocks */
405 mstp0_clks: clocks@ffc80030 { 441 mstp0_clks: clocks@ffc80030 {
406 compatible = "renesas,r8a7779-mstp-clocks", 442 compatible = "renesas,r8a7779-mstp-clocks",
407 "renesas,cpg-mstp-clocks"; 443 "renesas,cpg-mstp-clocks";
408 reg = <0xffc80030 4>; 444 reg = <0xffc80030 4>;
409 clocks = <&cpg_clocks R8A7779_CLK_S>, 445 clocks = <&cpg_clocks R8A7779_CLK_S>,
410 <&cpg_clocks R8A7779_CLK_P>, 446 <&cpg_clocks R8A7779_CLK_P>,
411 <&cpg_clocks R8A7779_CLK_P>, 447 <&cpg_clocks R8A7779_CLK_P>,
412 <&cpg_clocks R8A7779_CLK_P>, 448 <&cpg_clocks R8A7779_CLK_P>,
413 <&cpg_clocks R8A7779_CLK_S>, 449 <&cpg_clocks R8A7779_CLK_S>,
@@ -441,7 +477,7 @@
441 }; 477 };
442 mstp1_clks: clocks@ffc80034 { 478 mstp1_clks: clocks@ffc80034 {
443 compatible = "renesas,r8a7779-mstp-clocks", 479 compatible = "renesas,r8a7779-mstp-clocks",
444 "renesas,cpg-mstp-clocks"; 480 "renesas,cpg-mstp-clocks";
445 reg = <0xffc80034 4>, <0xffc80044 4>; 481 reg = <0xffc80034 4>, <0xffc80044 4>;
446 clocks = <&cpg_clocks R8A7779_CLK_P>, 482 clocks = <&cpg_clocks R8A7779_CLK_P>,
447 <&cpg_clocks R8A7779_CLK_P>, 483 <&cpg_clocks R8A7779_CLK_P>,
@@ -470,7 +506,7 @@
470 }; 506 };
471 mstp3_clks: clocks@ffc8003c { 507 mstp3_clks: clocks@ffc8003c {
472 compatible = "renesas,r8a7779-mstp-clocks", 508 compatible = "renesas,r8a7779-mstp-clocks",
473 "renesas,cpg-mstp-clocks"; 509 "renesas,cpg-mstp-clocks";
474 reg = <0xffc8003c 4>; 510 reg = <0xffc8003c 4>;
475 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 511 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
476 <&s4_clk>, <&s4_clk>; 512 <&s4_clk>, <&s4_clk>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 856b4236b674..69098b906b39 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -32,7 +32,7 @@
32 reg = <0 0x40000000 0 0x40000000>; 32 reg = <0 0x40000000 0 0x40000000>;
33 }; 33 };
34 34
35 memory@180000000 { 35 memory@140000000 {
36 device_type = "memory"; 36 device_type = "memory";
37 reg = <1 0x40000000 0 0xc0000000>; 37 reg = <1 0x40000000 0 0xc0000000>;
38 }; 38 };
@@ -234,6 +234,11 @@
234 renesas,groups = "usb2"; 234 renesas,groups = "usb2";
235 renesas,function = "usb2"; 235 renesas,function = "usb2";
236 }; 236 };
237
238 vin1_pins: vin {
239 renesas,groups = "vin1_data8", "vin1_clk";
240 renesas,function = "vin1";
241 };
237}; 242};
238 243
239&ether { 244&ether {
@@ -252,6 +257,10 @@
252 }; 257 };
253}; 258};
254 259
260&cmt0 {
261 status = "ok";
262};
263
255&mmcif1 { 264&mmcif1 {
256 pinctrl-0 = <&mmc1_pins>; 265 pinctrl-0 = <&mmc1_pins>;
257 pinctrl-names = "default"; 266 pinctrl-names = "default";
@@ -366,6 +375,19 @@
366 status = "ok"; 375 status = "ok";
367 pinctrl-0 = <&iic2_pins>; 376 pinctrl-0 = <&iic2_pins>;
368 pinctrl-names = "default"; 377 pinctrl-names = "default";
378
379 composite-in@20 {
380 compatible = "adi,adv7180";
381 reg = <0x20>;
382 remote = <&vin1>;
383
384 port {
385 adv7180: endpoint {
386 bus-width = <8>;
387 remote-endpoint = <&vin1ep0>;
388 };
389 };
390 };
369}; 391};
370 392
371&iic3 { 393&iic3 {
@@ -374,7 +396,7 @@
374 status = "okay"; 396 status = "okay";
375 397
376 vdd_dvfs: regulator@68 { 398 vdd_dvfs: regulator@68 {
377 compatible = "diasemi,da9210"; 399 compatible = "dlg,da9210";
378 reg = <0x68>; 400 reg = <0x68>;
379 401
380 regulator-min-microvolt = <1000000>; 402 regulator-min-microvolt = <1000000>;
@@ -401,3 +423,21 @@
401 pinctrl-0 = <&usb2_pins>; 423 pinctrl-0 = <&usb2_pins>;
402 pinctrl-names = "default"; 424 pinctrl-names = "default";
403}; 425};
426
427/* composite video input */
428&vin1 {
429 pinctrl-0 = <&vin1_pins>;
430 pinctrl-names = "default";
431
432 status = "ok";
433
434 port {
435 #address-cells = <1>;
436 #size-cells = <0>;
437
438 vin1ep0: endpoint {
439 remote-endpoint = <&adv7180>;
440 bus-width = <8>;
441 };
442 };
443};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d9ddecbb859c..d0e17733dc1a 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -33,6 +33,10 @@
33 spi2 = &msiof1; 33 spi2 = &msiof1;
34 spi3 = &msiof2; 34 spi3 = &msiof2;
35 spi4 = &msiof3; 35 spi4 = &msiof3;
36 vin0 = &vin0;
37 vin1 = &vin1;
38 vin2 = &vin2;
39 vin3 = &vin3;
36 }; 40 };
37 41
38 cpus { 42 cpus {
@@ -206,6 +210,38 @@
206 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 210 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
207 }; 211 };
208 212
213 cmt0: timer@ffca0000 {
214 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
215 reg = <0 0xffca0000 0 0x1004>;
216 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
217 <0 143 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
219 clock-names = "fck";
220
221 renesas,channels-mask = <0x60>;
222
223 status = "disabled";
224 };
225
226 cmt1: timer@e6130000 {
227 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
228 reg = <0 0xe6130000 0 0x1004>;
229 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
230 <0 121 IRQ_TYPE_LEVEL_HIGH>,
231 <0 122 IRQ_TYPE_LEVEL_HIGH>,
232 <0 123 IRQ_TYPE_LEVEL_HIGH>,
233 <0 124 IRQ_TYPE_LEVEL_HIGH>,
234 <0 125 IRQ_TYPE_LEVEL_HIGH>,
235 <0 126 IRQ_TYPE_LEVEL_HIGH>,
236 <0 127 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
238 clock-names = "fck";
239
240 renesas,channels-mask = <0xff>;
241
242 status = "disabled";
243 };
244
209 irqc0: interrupt-controller@e61c0000 { 245 irqc0: interrupt-controller@e61c0000 {
210 compatible = "renesas,irqc-r8a7790", "renesas,irqc"; 246 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
211 #interrupt-cells = <2>; 247 #interrupt-cells = <2>;
@@ -217,6 +253,65 @@
217 <0 3 IRQ_TYPE_LEVEL_HIGH>; 253 <0 3 IRQ_TYPE_LEVEL_HIGH>;
218 }; 254 };
219 255
256 dmac0: dma-controller@e6700000 {
257 compatible = "renesas,rcar-dmac";
258 reg = <0 0xe6700000 0 0x20000>;
259 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
260 0 200 IRQ_TYPE_LEVEL_HIGH
261 0 201 IRQ_TYPE_LEVEL_HIGH
262 0 202 IRQ_TYPE_LEVEL_HIGH
263 0 203 IRQ_TYPE_LEVEL_HIGH
264 0 204 IRQ_TYPE_LEVEL_HIGH
265 0 205 IRQ_TYPE_LEVEL_HIGH
266 0 206 IRQ_TYPE_LEVEL_HIGH
267 0 207 IRQ_TYPE_LEVEL_HIGH
268 0 208 IRQ_TYPE_LEVEL_HIGH
269 0 209 IRQ_TYPE_LEVEL_HIGH
270 0 210 IRQ_TYPE_LEVEL_HIGH
271 0 211 IRQ_TYPE_LEVEL_HIGH
272 0 212 IRQ_TYPE_LEVEL_HIGH
273 0 213 IRQ_TYPE_LEVEL_HIGH
274 0 214 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "error",
276 "ch0", "ch1", "ch2", "ch3",
277 "ch4", "ch5", "ch6", "ch7",
278 "ch8", "ch9", "ch10", "ch11",
279 "ch12", "ch13", "ch14";
280 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
281 clock-names = "fck";
282 #dma-cells = <1>;
283 dma-channels = <15>;
284 };
285
286 dmac1: dma-controller@e6720000 {
287 compatible = "renesas,rcar-dmac";
288 reg = <0 0xe6720000 0 0x20000>;
289 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
290 0 216 IRQ_TYPE_LEVEL_HIGH
291 0 217 IRQ_TYPE_LEVEL_HIGH
292 0 218 IRQ_TYPE_LEVEL_HIGH
293 0 219 IRQ_TYPE_LEVEL_HIGH
294 0 308 IRQ_TYPE_LEVEL_HIGH
295 0 309 IRQ_TYPE_LEVEL_HIGH
296 0 310 IRQ_TYPE_LEVEL_HIGH
297 0 311 IRQ_TYPE_LEVEL_HIGH
298 0 312 IRQ_TYPE_LEVEL_HIGH
299 0 313 IRQ_TYPE_LEVEL_HIGH
300 0 314 IRQ_TYPE_LEVEL_HIGH
301 0 315 IRQ_TYPE_LEVEL_HIGH
302 0 316 IRQ_TYPE_LEVEL_HIGH
303 0 317 IRQ_TYPE_LEVEL_HIGH
304 0 318 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
311 clock-names = "fck";
312 #dma-cells = <1>;
313 dma-channels = <15>;
314 };
220 i2c0: i2c@e6508000 { 315 i2c0: i2c@e6508000 {
221 #address-cells = <1>; 316 #address-cells = <1>;
222 #size-cells = <0>; 317 #size-cells = <0>;
@@ -473,6 +568,38 @@
473 status = "disabled"; 568 status = "disabled";
474 }; 569 };
475 570
571 vin0: video@e6ef0000 {
572 compatible = "renesas,vin-r8a7790";
573 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
574 reg = <0 0xe6ef0000 0 0x1000>;
575 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
576 status = "disabled";
577 };
578
579 vin1: video@e6ef1000 {
580 compatible = "renesas,vin-r8a7790";
581 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
582 reg = <0 0xe6ef1000 0 0x1000>;
583 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
584 status = "disabled";
585 };
586
587 vin2: video@e6ef2000 {
588 compatible = "renesas,vin-r8a7790";
589 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
590 reg = <0 0xe6ef2000 0 0x1000>;
591 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
592 status = "disabled";
593 };
594
595 vin3: video@e6ef3000 {
596 compatible = "renesas,vin-r8a7790";
597 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
598 reg = <0 0xe6ef3000 0 0x1000>;
599 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
600 status = "disabled";
601 };
602
476 clocks { 603 clocks {
477 #address-cells = <2>; 604 #address-cells = <2>;
478 #size-cells = <2>; 605 #size-cells = <2>;
@@ -741,33 +868,36 @@
741 mstp1_clks: mstp1_clks@e6150134 { 868 mstp1_clks: mstp1_clks@e6150134 {
742 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 869 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
743 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 870 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
744 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 871 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
745 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, 872 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
746 <&zs_clk>; 873 <&zs_clk>;
747 #clock-cells = <1>; 874 #clock-cells = <1>;
748 renesas,clock-indices = < 875 renesas,clock-indices = <
749 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 876 R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
750 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 877 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
751 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S 878 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
752 >; 879 >;
753 clock-output-names = 880 clock-output-names =
754 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 881 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
755 "vsp1-du0", "vsp1-rt", "vsp1-sy"; 882 "vsp1-du0", "vsp1-rt", "vsp1-sy";
756 }; 883 };
757 mstp2_clks: mstp2_clks@e6150138 { 884 mstp2_clks: mstp2_clks@e6150138 {
758 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 885 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
759 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 886 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
760 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 887 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
761 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; 888 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
889 <&zs_clk>;
762 #clock-cells = <1>; 890 #clock-cells = <1>;
763 renesas,clock-indices = < 891 renesas,clock-indices = <
764 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 892 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
765 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 893 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
766 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 894 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
895 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
767 >; 896 >;
768 clock-output-names = 897 clock-output-names =
769 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 898 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
770 "scifb1", "msiof1", "msiof3", "scifb2"; 899 "scifb1", "msiof1", "msiof3", "scifb2",
900 "sys-dmac1", "sys-dmac0";
771 }; 901 };
772 mstp3_clks: mstp3_clks@e615013c { 902 mstp3_clks: mstp3_clks@e615013c {
773 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 903 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -884,6 +1014,8 @@
884 reg = <0 0xe6b10000 0 0x2c>; 1014 reg = <0 0xe6b10000 0 0x2c>;
885 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 1015 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; 1016 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1017 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1018 dma-names = "tx", "rx";
887 num-cs = <1>; 1019 num-cs = <1>;
888 #address-cells = <1>; 1020 #address-cells = <1>;
889 #size-cells = <0>; 1021 #size-cells = <0>;
@@ -892,9 +1024,11 @@
892 1024
893 msiof0: spi@e6e20000 { 1025 msiof0: spi@e6e20000 {
894 compatible = "renesas,msiof-r8a7790"; 1026 compatible = "renesas,msiof-r8a7790";
895 reg = <0 0xe6e20000 0 0x0064>; 1027 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
896 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 1028 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; 1029 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1030 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1031 dma-names = "tx", "rx";
898 #address-cells = <1>; 1032 #address-cells = <1>;
899 #size-cells = <0>; 1033 #size-cells = <0>;
900 status = "disabled"; 1034 status = "disabled";
@@ -902,9 +1036,11 @@
902 1036
903 msiof1: spi@e6e10000 { 1037 msiof1: spi@e6e10000 {
904 compatible = "renesas,msiof-r8a7790"; 1038 compatible = "renesas,msiof-r8a7790";
905 reg = <0 0xe6e10000 0 0x0064>; 1039 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
906 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; 1040 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; 1041 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1042 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1043 dma-names = "tx", "rx";
908 #address-cells = <1>; 1044 #address-cells = <1>;
909 #size-cells = <0>; 1045 #size-cells = <0>;
910 status = "disabled"; 1046 status = "disabled";
@@ -912,9 +1048,11 @@
912 1048
913 msiof2: spi@e6e00000 { 1049 msiof2: spi@e6e00000 {
914 compatible = "renesas,msiof-r8a7790"; 1050 compatible = "renesas,msiof-r8a7790";
915 reg = <0 0xe6e00000 0 0x0064>; 1051 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
916 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 1052 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; 1053 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1054 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1055 dma-names = "tx", "rx";
918 #address-cells = <1>; 1056 #address-cells = <1>;
919 #size-cells = <0>; 1057 #size-cells = <0>;
920 status = "disabled"; 1058 status = "disabled";
@@ -922,9 +1060,11 @@
922 1060
923 msiof3: spi@e6c90000 { 1061 msiof3: spi@e6c90000 {
924 compatible = "renesas,msiof-r8a7790"; 1062 compatible = "renesas,msiof-r8a7790";
925 reg = <0 0xe6c90000 0 0x0064>; 1063 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
926 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; 1064 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; 1065 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1066 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1067 dma-names = "tx", "rx";
928 #address-cells = <1>; 1068 #address-cells = <1>;
929 #size-cells = <0>; 1069 #size-cells = <0>;
930 status = "disabled"; 1070 status = "disabled";
@@ -1018,7 +1158,6 @@
1018 rcar_sound: rcar_sound@0xec500000 { 1158 rcar_sound: rcar_sound@0xec500000 {
1019 #sound-dai-cells = <1>; 1159 #sound-dai-cells = <1>;
1020 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1160 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1021 interrupt-parent = <&gic>;
1022 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1161 reg = <0 0xec500000 0 0x1000>, /* SCU */
1023 <0 0xec5a0000 0 0x100>, /* ADG */ 1162 <0 0xec5a0000 0 0x100>, /* ADG */
1024 <0 0xec540000 0 0x1000>, /* SSIU */ 1163 <0 0xec540000 0 0x1000>, /* SSIU */
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index 3a2ef0a2a137..f1b56de10205 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -135,6 +135,11 @@
135 renesas,groups = "usb1"; 135 renesas,groups = "usb1";
136 renesas,function = "usb1"; 136 renesas,function = "usb1";
137 }; 137 };
138
139 vin0_pins: vin0 {
140 renesas,groups = "vin0_data8", "vin0_clk";
141 renesas,function = "vin0";
142 };
138}; 143};
139 144
140&scif0 { 145&scif0 {
@@ -191,6 +196,19 @@
191 196
192 status = "okay"; 197 status = "okay";
193 clock-frequency = <400000>; 198 clock-frequency = <400000>;
199
200 composite-in@20 {
201 compatible = "adi,adv7180";
202 reg = <0x20>;
203 remote = <&vin0>;
204
205 port {
206 adv7180: endpoint {
207 bus-width = <8>;
208 remote-endpoint = <&vin0ep>;
209 };
210 };
211 };
194}; 212};
195 213
196&qspi { 214&qspi {
@@ -260,3 +278,20 @@
260&pciec { 278&pciec {
261 status = "okay"; 279 status = "okay";
262}; 280};
281
282/* composite video input */
283&vin0 {
284 status = "ok";
285 pinctrl-0 = <&vin0_pins>;
286 pinctrl-names = "default";
287
288 port {
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 vin0ep: endpoint {
293 remote-endpoint = <&adv7180>;
294 bus-width = <8>;
295 };
296 };
297};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index be59014474b2..07550e775e80 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -284,6 +284,11 @@
284 renesas,groups = "usb1"; 284 renesas,groups = "usb1";
285 renesas,function = "usb1"; 285 renesas,function = "usb1";
286 }; 286 };
287
288 vin1_pins: vin1 {
289 renesas,groups = "vin1_data8", "vin1_clk";
290 renesas,function = "vin1";
291 };
287}; 292};
288 293
289&ether { 294&ether {
@@ -302,6 +307,10 @@
302 }; 307 };
303}; 308};
304 309
310&cmt0 {
311 status = "ok";
312};
313
305&sata0 { 314&sata0 {
306 status = "okay"; 315 status = "okay";
307}; 316};
@@ -407,6 +416,19 @@
407 status = "okay"; 416 status = "okay";
408 clock-frequency = <400000>; 417 clock-frequency = <400000>;
409 418
419 composite-in@20 {
420 compatible = "adi,adv7180";
421 reg = <0x20>;
422 remote = <&vin1>;
423
424 port {
425 adv7180: endpoint {
426 bus-width = <8>;
427 remote-endpoint = <&vin1ep>;
428 };
429 };
430 };
431
410 eeprom@50 { 432 eeprom@50 {
411 compatible = "renesas,24c02"; 433 compatible = "renesas,24c02";
412 reg = <0x50>; 434 reg = <0x50>;
@@ -419,7 +441,7 @@
419 clock-frequency = <100000>; 441 clock-frequency = <100000>;
420 442
421 vdd_dvfs: regulator@68 { 443 vdd_dvfs: regulator@68 {
422 compatible = "diasemi,da9210"; 444 compatible = "dlg,da9210";
423 reg = <0x68>; 445 reg = <0x68>;
424 446
425 regulator-min-microvolt = <1000000>; 447 regulator-min-microvolt = <1000000>;
@@ -452,3 +474,20 @@
452&cpu0 { 474&cpu0 {
453 cpu0-supply = <&vdd_dvfs>; 475 cpu0-supply = <&vdd_dvfs>;
454}; 476};
477
478/* composite video input */
479&vin1 {
480 status = "ok";
481 pinctrl-0 = <&vin1_pins>;
482 pinctrl-names = "default";
483
484 port {
485 #address-cells = <1>;
486 #size-cells = <0>;
487
488 vin1ep: endpoint {
489 remote-endpoint = <&adv7180>;
490 bus-width = <8>;
491 };
492 };
493};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 0d82a4b3c650..e06c11fa8698 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -34,6 +34,9 @@
34 spi1 = &msiof0; 34 spi1 = &msiof0;
35 spi2 = &msiof1; 35 spi2 = &msiof1;
36 spi3 = &msiof2; 36 spi3 = &msiof2;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
37 }; 40 };
38 41
39 cpus { 42 cpus {
@@ -189,6 +192,38 @@
189 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 192 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
190 }; 193 };
191 194
195 cmt0: timer@ffca0000 {
196 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
197 reg = <0 0xffca0000 0 0x1004>;
198 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
199 <0 143 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
201 clock-names = "fck";
202
203 renesas,channels-mask = <0x60>;
204
205 status = "disabled";
206 };
207
208 cmt1: timer@e6130000 {
209 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
210 reg = <0 0xe6130000 0 0x1004>;
211 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
212 <0 121 IRQ_TYPE_LEVEL_HIGH>,
213 <0 122 IRQ_TYPE_LEVEL_HIGH>,
214 <0 123 IRQ_TYPE_LEVEL_HIGH>,
215 <0 124 IRQ_TYPE_LEVEL_HIGH>,
216 <0 125 IRQ_TYPE_LEVEL_HIGH>,
217 <0 126 IRQ_TYPE_LEVEL_HIGH>,
218 <0 127 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
220 clock-names = "fck";
221
222 renesas,channels-mask = <0xff>;
223
224 status = "disabled";
225 };
226
192 irqc0: interrupt-controller@e61c0000 { 227 irqc0: interrupt-controller@e61c0000 {
193 compatible = "renesas,irqc-r8a7791", "renesas,irqc"; 228 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
194 #interrupt-cells = <2>; 229 #interrupt-cells = <2>;
@@ -206,6 +241,66 @@
206 <0 17 IRQ_TYPE_LEVEL_HIGH>; 241 <0 17 IRQ_TYPE_LEVEL_HIGH>;
207 }; 242 };
208 243
244 dmac0: dma-controller@e6700000 {
245 compatible = "renesas,rcar-dmac";
246 reg = <0 0xe6700000 0 0x20000>;
247 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
248 0 200 IRQ_TYPE_LEVEL_HIGH
249 0 201 IRQ_TYPE_LEVEL_HIGH
250 0 202 IRQ_TYPE_LEVEL_HIGH
251 0 203 IRQ_TYPE_LEVEL_HIGH
252 0 204 IRQ_TYPE_LEVEL_HIGH
253 0 205 IRQ_TYPE_LEVEL_HIGH
254 0 206 IRQ_TYPE_LEVEL_HIGH
255 0 207 IRQ_TYPE_LEVEL_HIGH
256 0 208 IRQ_TYPE_LEVEL_HIGH
257 0 209 IRQ_TYPE_LEVEL_HIGH
258 0 210 IRQ_TYPE_LEVEL_HIGH
259 0 211 IRQ_TYPE_LEVEL_HIGH
260 0 212 IRQ_TYPE_LEVEL_HIGH
261 0 213 IRQ_TYPE_LEVEL_HIGH
262 0 214 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "error",
264 "ch0", "ch1", "ch2", "ch3",
265 "ch4", "ch5", "ch6", "ch7",
266 "ch8", "ch9", "ch10", "ch11",
267 "ch12", "ch13", "ch14";
268 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
269 clock-names = "fck";
270 #dma-cells = <1>;
271 dma-channels = <15>;
272 };
273
274 dmac1: dma-controller@e6720000 {
275 compatible = "renesas,rcar-dmac";
276 reg = <0 0xe6720000 0 0x20000>;
277 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
278 0 216 IRQ_TYPE_LEVEL_HIGH
279 0 217 IRQ_TYPE_LEVEL_HIGH
280 0 218 IRQ_TYPE_LEVEL_HIGH
281 0 219 IRQ_TYPE_LEVEL_HIGH
282 0 308 IRQ_TYPE_LEVEL_HIGH
283 0 309 IRQ_TYPE_LEVEL_HIGH
284 0 310 IRQ_TYPE_LEVEL_HIGH
285 0 311 IRQ_TYPE_LEVEL_HIGH
286 0 312 IRQ_TYPE_LEVEL_HIGH
287 0 313 IRQ_TYPE_LEVEL_HIGH
288 0 314 IRQ_TYPE_LEVEL_HIGH
289 0 315 IRQ_TYPE_LEVEL_HIGH
290 0 316 IRQ_TYPE_LEVEL_HIGH
291 0 317 IRQ_TYPE_LEVEL_HIGH
292 0 318 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error",
294 "ch0", "ch1", "ch2", "ch3",
295 "ch4", "ch5", "ch6", "ch7",
296 "ch8", "ch9", "ch10", "ch11",
297 "ch12", "ch13", "ch14";
298 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
299 clock-names = "fck";
300 #dma-cells = <1>;
301 dma-channels = <15>;
302 };
303
209 /* The memory map in the User's Manual maps the cores to bus numbers */ 304 /* The memory map in the User's Manual maps the cores to bus numbers */
210 i2c0: i2c@e6508000 { 305 i2c0: i2c@e6508000 {
211 #address-cells = <1>; 306 #address-cells = <1>;
@@ -518,6 +613,30 @@
518 status = "disabled"; 613 status = "disabled";
519 }; 614 };
520 615
616 vin0: video@e6ef0000 {
617 compatible = "renesas,vin-r8a7791";
618 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
619 reg = <0 0xe6ef0000 0 0x1000>;
620 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
621 status = "disabled";
622 };
623
624 vin1: video@e6ef1000 {
625 compatible = "renesas,vin-r8a7791";
626 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
627 reg = <0 0xe6ef1000 0 0x1000>;
628 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
629 status = "disabled";
630 };
631
632 vin2: video@e6ef2000 {
633 compatible = "renesas,vin-r8a7791";
634 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
635 reg = <0 0xe6ef2000 0 0x1000>;
636 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
637 status = "disabled";
638 };
639
521 clocks { 640 clocks {
522 #address-cells = <2>; 641 #address-cells = <2>;
523 #size-cells = <2>; 642 #size-cells = <2>;
@@ -770,16 +889,16 @@
770 mstp1_clks: mstp1_clks@e6150134 { 889 mstp1_clks: mstp1_clks@e6150134 {
771 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 890 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
772 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 891 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
773 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 892 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
774 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 893 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
775 #clock-cells = <1>; 894 #clock-cells = <1>;
776 renesas,clock-indices = < 895 renesas,clock-indices = <
777 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 896 R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
778 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 897 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
779 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S 898 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
780 >; 899 >;
781 clock-output-names = 900 clock-output-names =
782 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 901 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
783 "vsp1-du0", "vsp1-sy"; 902 "vsp1-du0", "vsp1-sy";
784 }; 903 };
785 mstp2_clks: mstp2_clks@e6150138 { 904 mstp2_clks: mstp2_clks@e6150138 {
@@ -925,6 +1044,8 @@
925 reg = <0 0xe6b10000 0 0x2c>; 1044 reg = <0 0xe6b10000 0 0x2c>;
926 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 1045 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; 1046 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1047 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1048 dma-names = "tx", "rx";
928 num-cs = <1>; 1049 num-cs = <1>;
929 #address-cells = <1>; 1050 #address-cells = <1>;
930 #size-cells = <0>; 1051 #size-cells = <0>;
@@ -933,9 +1054,11 @@
933 1054
934 msiof0: spi@e6e20000 { 1055 msiof0: spi@e6e20000 {
935 compatible = "renesas,msiof-r8a7791"; 1056 compatible = "renesas,msiof-r8a7791";
936 reg = <0 0xe6e20000 0 0x0064>; 1057 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
937 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 1059 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1060 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1061 dma-names = "tx", "rx";
939 #address-cells = <1>; 1062 #address-cells = <1>;
940 #size-cells = <0>; 1063 #size-cells = <0>;
941 status = "disabled"; 1064 status = "disabled";
@@ -943,9 +1066,11 @@
943 1066
944 msiof1: spi@e6e10000 { 1067 msiof1: spi@e6e10000 {
945 compatible = "renesas,msiof-r8a7791"; 1068 compatible = "renesas,msiof-r8a7791";
946 reg = <0 0xe6e10000 0 0x0064>; 1069 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
947 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; 1070 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; 1071 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1072 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1073 dma-names = "tx", "rx";
949 #address-cells = <1>; 1074 #address-cells = <1>;
950 #size-cells = <0>; 1075 #size-cells = <0>;
951 status = "disabled"; 1076 status = "disabled";
@@ -953,9 +1078,11 @@
953 1078
954 msiof2: spi@e6e00000 { 1079 msiof2: spi@e6e00000 {
955 compatible = "renesas,msiof-r8a7791"; 1080 compatible = "renesas,msiof-r8a7791";
956 reg = <0 0xe6e00000 0 0x0064>; 1081 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
957 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 1082 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; 1083 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1084 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1085 dma-names = "tx", "rx";
959 #address-cells = <1>; 1086 #address-cells = <1>;
960 #size-cells = <0>; 1087 #size-cells = <0>;
961 status = "disabled"; 1088 status = "disabled";
@@ -1029,7 +1156,6 @@
1029 rcar_sound: rcar_sound@0xec500000 { 1156 rcar_sound: rcar_sound@0xec500000 {
1030 #sound-dai-cells = <1>; 1157 #sound-dai-cells = <1>;
1031 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1158 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1032 interrupt-parent = <&gic>;
1033 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1159 reg = <0 0xec500000 0 0x1000>, /* SCU */
1034 <0 0xec5a0000 0 0x100>, /* ADG */ 1160 <0 0xec5a0000 0 0x100>, /* ADG */
1035 <0 0xec540000 0 0x1000>, /* SSIU */ 1161 <0 0xec540000 0 0x1000>, /* SSIU */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
new file mode 100644
index 000000000000..79d06ef017a0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -0,0 +1,47 @@
1/*
2 * Device Tree Source for the Alt board
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7794.dtsi"
13
14/ {
15 model = "Alt";
16 compatible = "renesas,alt", "renesas,r8a7794";
17
18 aliases {
19 serial0 = &scif2;
20 };
21
22 chosen {
23 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0 0x40000000 0 0x40000000>;
29 };
30
31 lbsc {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 };
35};
36
37&extal_clk {
38 clock-frequency = <20000000>;
39};
40
41&cmt0 {
42 status = "ok";
43};
44
45&scif2 {
46 status = "ok";
47};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
new file mode 100644
index 000000000000..d4e8bce1e0b7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -0,0 +1,531 @@
1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a7";
29 reg = <0>;
30 clock-frequency = <1000000000>;
31 };
32
33 cpu1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a7";
36 reg = <1>;
37 clock-frequency = <1000000000>;
38 };
39 };
40
41 gic: interrupt-controller@f1001000 {
42 compatible = "arm,cortex-a7-gic";
43 #interrupt-cells = <3>;
44 #address-cells = <0>;
45 interrupt-controller;
46 reg = <0 0xf1001000 0 0x1000>,
47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>;
50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
51 };
52
53 cmt0: timer@ffca0000 {
54 compatible = "renesas,cmt-48-gen2";
55 reg = <0 0xffca0000 0 0x1004>;
56 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
57 <0 143 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
59 clock-names = "fck";
60
61 renesas,channels-mask = <0x60>;
62
63 status = "disabled";
64 };
65
66 cmt1: timer@e6130000 {
67 compatible = "renesas,cmt-48-gen2";
68 reg = <0 0xe6130000 0 0x1004>;
69 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
70 <0 121 IRQ_TYPE_LEVEL_HIGH>,
71 <0 122 IRQ_TYPE_LEVEL_HIGH>,
72 <0 123 IRQ_TYPE_LEVEL_HIGH>,
73 <0 124 IRQ_TYPE_LEVEL_HIGH>,
74 <0 125 IRQ_TYPE_LEVEL_HIGH>,
75 <0 126 IRQ_TYPE_LEVEL_HIGH>,
76 <0 127 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
78 clock-names = "fck";
79
80 renesas,channels-mask = <0xff>;
81
82 status = "disabled";
83 };
84
85 irqc0: interrupt-controller@e61c0000 {
86 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
87 #interrupt-cells = <2>;
88 interrupt-controller;
89 reg = <0 0xe61c0000 0 0x200>;
90 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
91 <0 1 IRQ_TYPE_LEVEL_HIGH>,
92 <0 2 IRQ_TYPE_LEVEL_HIGH>,
93 <0 3 IRQ_TYPE_LEVEL_HIGH>,
94 <0 12 IRQ_TYPE_LEVEL_HIGH>,
95 <0 13 IRQ_TYPE_LEVEL_HIGH>,
96 <0 14 IRQ_TYPE_LEVEL_HIGH>,
97 <0 15 IRQ_TYPE_LEVEL_HIGH>,
98 <0 16 IRQ_TYPE_LEVEL_HIGH>,
99 <0 17 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 scifa0: serial@e6c40000 {
103 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
104 reg = <0 0xe6c40000 0 64>;
105 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
107 clock-names = "sci_ick";
108 status = "disabled";
109 };
110
111 scifa1: serial@e6c50000 {
112 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
113 reg = <0 0xe6c50000 0 64>;
114 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
116 clock-names = "sci_ick";
117 status = "disabled";
118 };
119
120 scifa2: serial@e6c60000 {
121 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
122 reg = <0 0xe6c60000 0 64>;
123 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
125 clock-names = "sci_ick";
126 status = "disabled";
127 };
128
129 scifa3: serial@e6c70000 {
130 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
131 reg = <0 0xe6c70000 0 64>;
132 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
134 clock-names = "sci_ick";
135 status = "disabled";
136 };
137
138 scifa4: serial@e6c78000 {
139 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
140 reg = <0 0xe6c78000 0 64>;
141 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
143 clock-names = "sci_ick";
144 status = "disabled";
145 };
146
147 scifa5: serial@e6c80000 {
148 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
149 reg = <0 0xe6c80000 0 64>;
150 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
152 clock-names = "sci_ick";
153 status = "disabled";
154 };
155
156 scifb0: serial@e6c20000 {
157 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
158 reg = <0 0xe6c20000 0 64>;
159 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
161 clock-names = "sci_ick";
162 status = "disabled";
163 };
164
165 scifb1: serial@e6c30000 {
166 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
167 reg = <0 0xe6c30000 0 64>;
168 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
170 clock-names = "sci_ick";
171 status = "disabled";
172 };
173
174 scifb2: serial@e6ce0000 {
175 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
176 reg = <0 0xe6ce0000 0 64>;
177 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
179 clock-names = "sci_ick";
180 status = "disabled";
181 };
182
183 scif0: serial@e6e60000 {
184 compatible = "renesas,scif-r8a7794", "renesas,scif";
185 reg = <0 0xe6e60000 0 64>;
186 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
188 clock-names = "sci_ick";
189 status = "disabled";
190 };
191
192 scif1: serial@e6e68000 {
193 compatible = "renesas,scif-r8a7794", "renesas,scif";
194 reg = <0 0xe6e68000 0 64>;
195 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
197 clock-names = "sci_ick";
198 status = "disabled";
199 };
200
201 scif2: serial@e6e58000 {
202 compatible = "renesas,scif-r8a7794", "renesas,scif";
203 reg = <0 0xe6e58000 0 64>;
204 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
206 clock-names = "sci_ick";
207 status = "disabled";
208 };
209
210 scif3: serial@e6ea8000 {
211 compatible = "renesas,scif-r8a7794", "renesas,scif";
212 reg = <0 0xe6ea8000 0 64>;
213 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
215 clock-names = "sci_ick";
216 status = "disabled";
217 };
218
219 scif4: serial@e6ee0000 {
220 compatible = "renesas,scif-r8a7794", "renesas,scif";
221 reg = <0 0xe6ee0000 0 64>;
222 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
224 clock-names = "sci_ick";
225 status = "disabled";
226 };
227
228 scif5: serial@e6ee8000 {
229 compatible = "renesas,scif-r8a7794", "renesas,scif";
230 reg = <0 0xe6ee8000 0 64>;
231 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
233 clock-names = "sci_ick";
234 status = "disabled";
235 };
236
237 hscif0: serial@e62c0000 {
238 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
239 reg = <0 0xe62c0000 0 96>;
240 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
242 clock-names = "sci_ick";
243 status = "disabled";
244 };
245
246 hscif1: serial@e62c8000 {
247 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
248 reg = <0 0xe62c8000 0 96>;
249 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
251 clock-names = "sci_ick";
252 status = "disabled";
253 };
254
255 hscif2: serial@e62d0000 {
256 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
257 reg = <0 0xe62d0000 0 96>;
258 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
260 clock-names = "sci_ick";
261 status = "disabled";
262 };
263
264 clocks {
265 #address-cells = <2>;
266 #size-cells = <2>;
267 ranges;
268
269 /* External root clock */
270 extal_clk: extal_clk {
271 compatible = "fixed-clock";
272 #clock-cells = <0>;
273 /* This value must be overriden by the board. */
274 clock-frequency = <0>;
275 clock-output-names = "extal";
276 };
277
278 /* Special CPG clocks */
279 cpg_clocks: cpg_clocks@e6150000 {
280 compatible = "renesas,r8a7794-cpg-clocks",
281 "renesas,rcar-gen2-cpg-clocks";
282 reg = <0 0xe6150000 0 0x1000>;
283 clocks = <&extal_clk>;
284 #clock-cells = <1>;
285 clock-output-names = "main", "pll0", "pll1", "pll3",
286 "lb", "qspi", "sdh", "sd0", "z";
287 };
288
289 /* Fixed factor clocks */
290 pll1_div2_clk: pll1_div2_clk {
291 compatible = "fixed-factor-clock";
292 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
293 #clock-cells = <0>;
294 clock-div = <2>;
295 clock-mult = <1>;
296 clock-output-names = "pll1_div2";
297 };
298 zg_clk: zg_clk {
299 compatible = "fixed-factor-clock";
300 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
301 #clock-cells = <0>;
302 clock-div = <6>;
303 clock-mult = <1>;
304 clock-output-names = "zg";
305 };
306 zx_clk: zx_clk {
307 compatible = "fixed-factor-clock";
308 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
309 #clock-cells = <0>;
310 clock-div = <3>;
311 clock-mult = <1>;
312 clock-output-names = "zx";
313 };
314 zs_clk: zs_clk {
315 compatible = "fixed-factor-clock";
316 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
317 #clock-cells = <0>;
318 clock-div = <6>;
319 clock-mult = <1>;
320 clock-output-names = "zs";
321 };
322 hp_clk: hp_clk {
323 compatible = "fixed-factor-clock";
324 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
325 #clock-cells = <0>;
326 clock-div = <12>;
327 clock-mult = <1>;
328 clock-output-names = "hp";
329 };
330 i_clk: i_clk {
331 compatible = "fixed-factor-clock";
332 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
333 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "i";
337 };
338 b_clk: b_clk {
339 compatible = "fixed-factor-clock";
340 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
341 #clock-cells = <0>;
342 clock-div = <12>;
343 clock-mult = <1>;
344 clock-output-names = "b";
345 };
346 p_clk: p_clk {
347 compatible = "fixed-factor-clock";
348 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
349 #clock-cells = <0>;
350 clock-div = <24>;
351 clock-mult = <1>;
352 clock-output-names = "p";
353 };
354 cl_clk: cl_clk {
355 compatible = "fixed-factor-clock";
356 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
357 #clock-cells = <0>;
358 clock-div = <48>;
359 clock-mult = <1>;
360 clock-output-names = "cl";
361 };
362 m2_clk: m2_clk {
363 compatible = "fixed-factor-clock";
364 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
365 #clock-cells = <0>;
366 clock-div = <8>;
367 clock-mult = <1>;
368 clock-output-names = "m2";
369 };
370 imp_clk: imp_clk {
371 compatible = "fixed-factor-clock";
372 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
373 #clock-cells = <0>;
374 clock-div = <4>;
375 clock-mult = <1>;
376 clock-output-names = "imp";
377 };
378 rclk_clk: rclk_clk {
379 compatible = "fixed-factor-clock";
380 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
381 #clock-cells = <0>;
382 clock-div = <(48 * 1024)>;
383 clock-mult = <1>;
384 clock-output-names = "rclk";
385 };
386 oscclk_clk: oscclk_clk {
387 compatible = "fixed-factor-clock";
388 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
389 #clock-cells = <0>;
390 clock-div = <(12 * 1024)>;
391 clock-mult = <1>;
392 clock-output-names = "oscclk";
393 };
394 zb3_clk: zb3_clk {
395 compatible = "fixed-factor-clock";
396 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
397 #clock-cells = <0>;
398 clock-div = <4>;
399 clock-mult = <1>;
400 clock-output-names = "zb3";
401 };
402 zb3d2_clk: zb3d2_clk {
403 compatible = "fixed-factor-clock";
404 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
405 #clock-cells = <0>;
406 clock-div = <8>;
407 clock-mult = <1>;
408 clock-output-names = "zb3d2";
409 };
410 ddr_clk: ddr_clk {
411 compatible = "fixed-factor-clock";
412 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
413 #clock-cells = <0>;
414 clock-div = <8>;
415 clock-mult = <1>;
416 clock-output-names = "ddr";
417 };
418 mp_clk: mp_clk {
419 compatible = "fixed-factor-clock";
420 clocks = <&pll1_div2_clk>;
421 #clock-cells = <0>;
422 clock-div = <15>;
423 clock-mult = <1>;
424 clock-output-names = "mp";
425 };
426 cp_clk: cp_clk {
427 compatible = "fixed-factor-clock";
428 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
429 #clock-cells = <0>;
430 clock-div = <48>;
431 clock-mult = <1>;
432 clock-output-names = "cp";
433 };
434
435 acp_clk: acp_clk {
436 compatible = "fixed-factor-clock";
437 clocks = <&extal_clk>;
438 #clock-cells = <0>;
439 clock-div = <2>;
440 clock-mult = <1>;
441 clock-output-names = "acp";
442 };
443
444 /* Gate clocks */
445 mstp0_clks: mstp0_clks@e6150130 {
446 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
447 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
448 clocks = <&mp_clk>;
449 #clock-cells = <1>;
450 renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
451 clock-output-names = "msiof0";
452 };
453 mstp1_clks: mstp1_clks@e6150134 {
454 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
455 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
456 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
457 <&cp_clk>,
458 <&zs_clk>, <&zs_clk>, <&zs_clk>;
459 #clock-cells = <1>;
460 renesas,clock-indices = <
461 R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
462 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
463 >;
464 clock-output-names =
465 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
466 };
467 mstp2_clks: mstp2_clks@e6150138 {
468 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
469 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
470 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
471 <&mp_clk>, <&mp_clk>, <&mp_clk>;
472 #clock-cells = <1>;
473 renesas,clock-indices = <
474 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
475 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
476 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
477 >;
478 clock-output-names =
479 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
480 "scifb1", "msiof1", "scifb2";
481 };
482 mstp3_clks: mstp3_clks@e615013c {
483 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
484 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
485 clocks = <&rclk_clk>;
486 #clock-cells = <1>;
487 renesas,clock-indices = <
488 R8A7794_CLK_CMT1
489 >;
490 clock-output-names =
491 "cmt1";
492 };
493 mstp7_clks: mstp7_clks@e615014c {
494 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
495 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
496 clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
497 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
498 #clock-cells = <1>;
499 renesas,clock-indices = <
500 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
501 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
502 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
503 R8A7794_CLK_SCIF0
504 >;
505 clock-output-names =
506 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
507 "scif3", "scif2", "scif1", "scif0";
508 };
509 mstp8_clks: mstp8_clks@e6150990 {
510 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
511 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
512 clocks = <&p_clk>;
513 #clock-cells = <1>;
514 renesas,clock-indices = <
515 R8A7794_CLK_ETHER
516 >;
517 clock-output-names =
518 "ether";
519 };
520 mstp11_clks: mstp11_clks@e615099c {
521 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
522 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
523 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
524 #clock-cells = <1>;
525 renesas,clock-indices = <
526 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
527 >;
528 clock-output-names = "scifa3", "scifa4", "scifa5";
529 };
530 };
531};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index c9d912da6141..d5344510c676 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -152,12 +152,8 @@
152 pinctrl-names = "default"; 152 pinctrl-names = "default";
153 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 153 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
154 vmmc-supply = <&vcc_sd0>; 154 vmmc-supply = <&vcc_sd0>;
155 155 bus-width = <4>;
156 slot@0 { 156 disable-wp;
157 reg = <0>;
158 bus-width = <4>;
159 disable-wp;
160 };
161}; 157};
162 158
163&mmc1 { /* wifi */ 159&mmc1 { /* wifi */
@@ -168,11 +164,8 @@
168 pinctrl-names = "default"; 164 pinctrl-names = "default";
169 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; 165 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
170 166
171 slot@0 { 167 bus-width = <4>;
172 reg = <0>; 168 disable-wp;
173 bus-width = <4>;
174 disable-wp;
175 };
176}; 169};
177 170
178&uart0 { 171&uart0 {
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 879a818fba51..ad9c2db59670 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -179,6 +179,27 @@
179 bias-disable; 179 bias-disable;
180 }; 180 };
181 181
182 emmc {
183 emmc_clk: emmc-clk {
184 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
185 };
186
187 emmc_cmd: emmc-cmd {
188 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
189 };
190
191 emmc_rst: emmc-rst {
192 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
193 };
194
195 /*
196 * The data pins are shared between nandc and emmc and
197 * not accessible through pinctrl. Also they should've
198 * been already set correctly by firmware, as
199 * flash/emmc is the boot-device.
200 */
201 };
202
182 i2c0 { 203 i2c0 {
183 i2c0_xfer: i2c0-xfer { 204 i2c0_xfer: i2c0-xfer {
184 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>, 205 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
@@ -238,6 +259,42 @@
238 }; 259 };
239 }; 260 };
240 261
262 spi0 {
263 spi0_clk: spi0-clk {
264 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
265 };
266 spi0_cs0: spi0-cs0 {
267 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
268 };
269 spi0_tx: spi0-tx {
270 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
271 };
272 spi0_rx: spi0-rx {
273 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
274 };
275 spi0_cs1: spi0-cs1 {
276 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
277 };
278 };
279
280 spi1 {
281 spi1_clk: spi1-clk {
282 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
283 };
284 spi1_cs0: spi1-cs0 {
285 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
286 };
287 spi1_rx: spi1-rx {
288 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
289 };
290 spi1_tx: spi1-tx {
291 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
292 };
293 spi1_cs1: spi1-cs1 {
294 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
295 };
296 };
297
241 uart0 { 298 uart0 {
242 uart0_xfer: uart0-xfer { 299 uart0_xfer: uart0-xfer {
243 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, 300 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
@@ -406,6 +463,16 @@
406 pinctrl-0 = <&pwm3_out>; 463 pinctrl-0 = <&pwm3_out>;
407}; 464};
408 465
466&spi0 {
467 pinctrl-names = "default";
468 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
469};
470
471&spi1 {
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
474};
475
409&uart0 { 476&uart0 {
410 pinctrl-names = "default"; 477 pinctrl-names = "default";
411 pinctrl-0 = <&uart0_xfer>; 478 pinctrl-0 = <&uart0_xfer>;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 5e4e3c238b2d..15910c9ddbc7 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -65,6 +65,19 @@
65 pinctrl-0 = <&ir_recv_pin>; 65 pinctrl-0 = <&ir_recv_pin>;
66 }; 66 };
67 67
68 vcc_otg: usb-otg-regulator {
69 compatible = "regulator-fixed";
70 enable-active-high;
71 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&otg_vbus_drv>;
74 regulator-name = "otg-vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 regulator-always-on;
78 regulator-boot-on;
79 };
80
68 vcc_sd0: sdmmc-regulator { 81 vcc_sd0: sdmmc-regulator {
69 compatible = "regulator-fixed"; 82 compatible = "regulator-fixed";
70 regulator-name = "sdmmc-supply"; 83 regulator-name = "sdmmc-supply";
@@ -74,12 +87,52 @@
74 startup-delay-us = <100000>; 87 startup-delay-us = <100000>;
75 vin-supply = <&vcc_io>; 88 vin-supply = <&vcc_io>;
76 }; 89 };
90
91 vcc_host: usb-host-regulator {
92 compatible = "regulator-fixed";
93 enable-active-high;
94 gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&host_vbus_drv>;
97 regulator-name = "host-pwr";
98 regulator-min-microvolt = <5000000>;
99 regulator-max-microvolt = <5000000>;
100 regulator-always-on;
101 regulator-boot-on;
102 };
103};
104
105&emac {
106 status = "okay";
107
108 pinctrl-names = "default";
109 pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
110
111 phy = <&phy0>;
112 phy-supply = <&vcc_rmii>;
113
114 phy0: ethernet-phy@0 {
115 reg = <0>;
116 interrupt-parent = <&gpio3>;
117 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
118 };
77}; 119};
78 120
79&i2c1 { 121&i2c1 {
80 status = "okay"; 122 status = "okay";
81 clock-frequency = <400000>; 123 clock-frequency = <400000>;
82 124
125 rtc@51 {
126 compatible = "haoyu,hym8563";
127 reg = <0x51>;
128 interrupt-parent = <&gpio0>;
129 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&rtc_int>;
132 #clock-cells = <0>;
133 clock-output-names = "xin32k";
134 };
135
83 act8846: act8846@5a { 136 act8846: act8846@5a {
84 compatible = "active-semi,act8846"; 137 compatible = "active-semi,act8846";
85 reg = <0x5a>; 138 reg = <0x5a>;
@@ -149,7 +202,6 @@
149 regulator-name = "VCC_RMII"; 202 regulator-name = "VCC_RMII";
150 regulator-min-microvolt = <3300000>; 203 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>; 204 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 }; 205 };
154 206
155 vccio_wl: REG10 { 207 vccio_wl: REG10 {
@@ -183,11 +235,8 @@
183 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 235 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
184 vmmc-supply = <&vcc_sd0>; 236 vmmc-supply = <&vcc_sd0>;
185 237
186 slot@0 { 238 bus-width = <4>;
187 reg = <0>; 239 disable-wp;
188 bus-width = <4>;
189 disable-wp;
190 };
191}; 240};
192 241
193&pinctrl { 242&pinctrl {
@@ -201,11 +250,32 @@
201 }; 250 };
202 }; 251 };
203 252
253 hym8563 {
254 rtc_int: rtc-int {
255 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
256 };
257 };
258
259 lan8720a {
260 phy_int: phy-int {
261 rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>;
262 };
263 };
264
204 ir-receiver { 265 ir-receiver {
205 ir_recv_pin: ir-recv-pin { 266 ir_recv_pin: ir-recv-pin {
206 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>; 267 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
207 }; 268 };
208 }; 269 };
270
271 usb {
272 host_vbus_drv: host-vbus-drv {
273 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
274 };
275 otg_vbus_drv: otg-vbus-drv {
276 rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
277 };
278 };
209}; 279};
210 280
211&uart0 { 281&uart0 {
@@ -224,6 +294,14 @@
224 status = "okay"; 294 status = "okay";
225}; 295};
226 296
297&usb_host {
298 status = "okay";
299};
300
301&usb_otg {
302 status = "okay";
303};
304
227&wdt { 305&wdt {
228 status = "okay"; 306 status = "okay";
229}; 307};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ee801a9c6b74..ddaada788b45 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -147,6 +147,45 @@
147 bias-disable; 147 bias-disable;
148 }; 148 };
149 149
150 emmc {
151 emmc_clk: emmc-clk {
152 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
153 };
154
155 emmc_cmd: emmc-cmd {
156 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
157 };
158
159 emmc_rst: emmc-rst {
160 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
161 };
162
163 /*
164 * The data pins are shared between nandc and emmc and
165 * not accessible through pinctrl. Also they should've
166 * been already set correctly by firmware, as
167 * flash/emmc is the boot-device.
168 */
169 };
170
171 emac {
172 emac_xfer: emac-xfer {
173 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
174 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
175 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
176 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
177 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
178 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
179 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
180 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
181 };
182
183 emac_mdio: emac-mdio {
184 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
185 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
186 };
187 };
188
150 i2c0 { 189 i2c0 {
151 i2c0_xfer: i2c0-xfer { 190 i2c0_xfer: i2c0-xfer {
152 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>, 191 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
@@ -206,6 +245,42 @@
206 }; 245 };
207 }; 246 };
208 247
248 spi0 {
249 spi0_clk: spi0-clk {
250 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
251 };
252 spi0_cs0: spi0-cs0 {
253 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
254 };
255 spi0_tx: spi0-tx {
256 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
257 };
258 spi0_rx: spi0-rx {
259 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
260 };
261 spi0_cs1: spi0-cs1 {
262 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
263 };
264 };
265
266 spi1 {
267 spi1_clk: spi1-clk {
268 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
269 };
270 spi1_cs0: spi1-cs0 {
271 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
272 };
273 spi1_rx: spi1-rx {
274 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
275 };
276 spi1_tx: spi1-tx {
277 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
278 };
279 spi1_cs1: spi1-cs1 {
280 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
281 };
282 };
283
209 uart0 { 284 uart0 {
210 uart0_xfer: uart0-xfer { 285 uart0_xfer: uart0-xfer {
211 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, 286 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
@@ -323,6 +398,10 @@
323 }; 398 };
324}; 399};
325 400
401&emac {
402 compatible = "rockchip,rk3188-emac";
403};
404
326&global_timer { 405&global_timer {
327 interrupts = <GIC_PPI 11 0xf04>; 406 interrupts = <GIC_PPI 11 0xf04>;
328}; 407};
@@ -381,6 +460,18 @@
381 pinctrl-0 = <&pwm3_out>; 460 pinctrl-0 = <&pwm3_out>;
382}; 461};
383 462
463&spi0 {
464 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
465 pinctrl-names = "default";
466 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
467};
468
469&spi1 {
470 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
473};
474
384&uart0 { 475&uart0 {
385 pinctrl-names = "default"; 476 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer>; 477 pinctrl-0 = <&uart0_xfer>;
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 7d59ff4de408..a76dd44adb53 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -26,7 +26,7 @@
26 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 26 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
27 27
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&hym8563_int>; 29 pinctrl-0 = <&pmic_int>;
30 30
31 #clock-cells = <0>; 31 #clock-cells = <0>;
32 clock-output-names = "xin32k"; 32 clock-output-names = "xin32k";
@@ -124,11 +124,3 @@
124 }; 124 };
125 }; 125 };
126}; 126};
127
128&pinctrl {
129 hym8563 {
130 hym8563_int: hym8563-int {
131 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
132 };
133 };
134};
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index 9a88b6c66396..ff522f8e3df4 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -16,3 +16,135 @@
16/ { 16/ {
17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; 17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
18}; 18};
19
20&i2c0 {
21 clock-frequency = <400000>;
22 status = "okay";
23
24 rk808: pmic@1b {
25 compatible = "rockchip,rk808";
26 reg = <0x1b>;
27 interrupt-parent = <&gpio0>;
28 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pmic_int>;
31 rockchip,system-power-controller;
32 wakeup-source;
33 #clock-cells = <1>;
34 clock-output-names = "xin32k", "rk808-clkout2";
35
36 vcc8-supply = <&vcc_18>;
37 vcc9-supply = <&vcc_io>;
38 vcc10-supply = <&vcc_io>;
39 vcc12-supply = <&vcc_io>;
40 vddio-supply = <&vccio_pmu>;
41
42 regulators {
43 vdd_cpu: DCDC_REG1 {
44 regulator-always-on;
45 regulator-boot-on;
46 regulator-min-microvolt = <750000>;
47 regulator-max-microvolt = <1300000>;
48 regulator-name = "vdd_arm";
49 };
50
51 vdd_gpu: DCDC_REG2 {
52 regulator-always-on;
53 regulator-boot-on;
54 regulator-min-microvolt = <850000>;
55 regulator-max-microvolt = <1250000>;
56 regulator-name = "vdd_gpu";
57 };
58
59 vcc_ddr: DCDC_REG3 {
60 regulator-always-on;
61 regulator-boot-on;
62 regulator-name = "vcc_ddr";
63 };
64
65 vcc_io: DCDC_REG4 {
66 regulator-always-on;
67 regulator-boot-on;
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 regulator-name = "vcc_io";
71 };
72
73 vccio_pmu: LDO_REG1 {
74 regulator-always-on;
75 regulator-boot-on;
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-name = "vccio_pmu";
79 };
80
81 vcc_tp: LDO_REG2 {
82 regulator-always-on;
83 regulator-boot-on;
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-name = "vcc_tp";
87 };
88
89 vdd_10: LDO_REG3 {
90 regulator-always-on;
91 regulator-boot-on;
92 regulator-min-microvolt = <1000000>;
93 regulator-max-microvolt = <1000000>;
94 regulator-name = "vdd_10";
95 };
96
97 vcc18_lcd: LDO_REG4 {
98 regulator-always-on;
99 regulator-boot-on;
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <1800000>;
102 regulator-name = "vcc18_lcd";
103 };
104
105 vccio_sd: LDO_REG5 {
106 regulator-always-on;
107 regulator-boot-on;
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <3300000>;
110 regulator-name = "vccio_sd";
111 };
112
113 vdd10_lcd: LDO_REG6 {
114 regulator-always-on;
115 regulator-boot-on;
116 regulator-min-microvolt = <1000000>;
117 regulator-max-microvolt = <1000000>;
118 regulator-name = "vdd10_lcd";
119 };
120
121 vcc_18: LDO_REG7 {
122 regulator-always-on;
123 regulator-boot-on;
124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <1800000>;
126 regulator-name = "vcc_18";
127 };
128
129 vcca_codec: LDO_REG8 {
130 regulator-always-on;
131 regulator-boot-on;
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 regulator-name = "vcca_codec";
135 };
136
137 vcc_wl: SWITCH_REG1 {
138 regulator-always-on;
139 regulator-boot-on;
140 regulator-name = "vcc_wl";
141 };
142
143 vcc_lcd: SWITCH_REG2 {
144 regulator-always-on;
145 regulator-boot-on;
146 regulator-name = "vcc_lcd";
147 };
148 };
149 };
150};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 4f572093c8b4..cb83cea52fa1 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -10,6 +10,7 @@
10 * GNU General Public License for more details. 10 * GNU General Public License for more details.
11 */ 11 */
12 12
13#include <dt-bindings/pwm/pwm.h>
13#include "rk3288.dtsi" 14#include "rk3288.dtsi"
14 15
15/ { 16/ {
@@ -17,6 +18,48 @@
17 reg = <0x0 0x80000000>; 18 reg = <0x0 0x80000000>;
18 }; 19 };
19 20
21 backlight {
22 compatible = "pwm-backlight";
23 brightness-levels = <
24 0 1 2 3 4 5 6 7
25 8 9 10 11 12 13 14 15
26 16 17 18 19 20 21 22 23
27 24 25 26 27 28 29 30 31
28 32 33 34 35 36 37 38 39
29 40 41 42 43 44 45 46 47
30 48 49 50 51 52 53 54 55
31 56 57 58 59 60 61 62 63
32 64 65 66 67 68 69 70 71
33 72 73 74 75 76 77 78 79
34 80 81 82 83 84 85 86 87
35 88 89 90 91 92 93 94 95
36 96 97 98 99 100 101 102 103
37 104 105 106 107 108 109 110 111
38 112 113 114 115 116 117 118 119
39 120 121 122 123 124 125 126 127
40 128 129 130 131 132 133 134 135
41 136 137 138 139 140 141 142 143
42 144 145 146 147 148 149 150 151
43 152 153 154 155 156 157 158 159
44 160 161 162 163 164 165 166 167
45 168 169 170 171 172 173 174 175
46 176 177 178 179 180 181 182 183
47 184 185 186 187 188 189 190 191
48 192 193 194 195 196 197 198 199
49 200 201 202 203 204 205 206 207
50 208 209 210 211 212 213 214 215
51 216 217 218 219 220 221 222 223
52 224 225 226 227 228 229 230 231
53 232 233 234 235 236 237 238 239
54 240 241 242 243 244 245 246 247
55 248 249 250 251 252 253 254 255>;
56 default-brightness-level = <128>;
57 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&bl_en>;
60 pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
61 };
62
20 gpio-keys { 63 gpio-keys {
21 compatible = "gpio-keys"; 64 compatible = "gpio-keys";
22 #address-cells = <1>; 65 #address-cells = <1>;
@@ -49,6 +92,30 @@
49 }; 92 };
50}; 93};
51 94
95&emmc {
96 broken-cd;
97 bus-width = <8>;
98 cap-mmc-highspeed;
99 disable-wp;
100 non-removable;
101 num-slots = <1>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
104 status = "okay";
105};
106
107&sdmmc {
108 bus-width = <4>;
109 cap-mmc-highspeed;
110 cap-sd-highspeed;
111 card-detect-delay = <200>;
112 disable-wp; /* wp not hooked up */
113 num-slots = <1>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
116 status = "okay";
117};
118
52&i2c0 { 119&i2c0 {
53 status = "okay"; 120 status = "okay";
54}; 121};
@@ -57,6 +124,10 @@
57 status = "okay"; 124 status = "okay";
58}; 125};
59 126
127&pwm0 {
128 status = "okay";
129};
130
60&uart0 { 131&uart0 {
61 status = "okay"; 132 status = "okay";
62}; 133};
@@ -78,12 +149,24 @@
78}; 149};
79 150
80&pinctrl { 151&pinctrl {
152 backlight {
153 bl_en: bl-en {
154 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
155 };
156 };
157
81 buttons { 158 buttons {
82 pwrbtn: pwrbtn { 159 pwrbtn: pwrbtn {
83 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; 160 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
84 }; 161 };
85 }; 162 };
86 163
164 pmic {
165 pmic_int: pmic-int {
166 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
167 };
168 };
169
87 usb { 170 usb {
88 host_vbus_drv: host-vbus-drv { 171 host_vbus_drv: host-vbus-drv {
89 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; 172 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -94,3 +177,7 @@
94&usb_host0_ehci { 177&usb_host0_ehci {
95 status = "okay"; 178 status = "okay";
96}; 179};
180
181&usb_host1 {
182 status = "okay";
183};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5950b0a53224..874e66dbb93b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -29,11 +29,18 @@
29 i2c3 = &i2c3; 29 i2c3 = &i2c3;
30 i2c4 = &i2c4; 30 i2c4 = &i2c4;
31 i2c5 = &i2c5; 31 i2c5 = &i2c5;
32 mshc0 = &emmc;
33 mshc1 = &sdmmc;
34 mshc2 = &sdio0;
35 mshc3 = &sdio1;
32 serial0 = &uart0; 36 serial0 = &uart0;
33 serial1 = &uart1; 37 serial1 = &uart1;
34 serial2 = &uart2; 38 serial2 = &uart2;
35 serial3 = &uart3; 39 serial3 = &uart3;
36 serial4 = &uart4; 40 serial4 = &uart4;
41 spi0 = &spi0;
42 spi1 = &spi1;
43 spi2 = &spi2;
37 }; 44 };
38 45
39 cpus { 46 cpus {
@@ -62,6 +69,44 @@
62 }; 69 };
63 }; 70 };
64 71
72 amba {
73 compatible = "arm,amba-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
78 dmac_peri: dma-controller@ff250000 {
79 compatible = "arm,pl330", "arm,primecell";
80 reg = <0xff250000 0x4000>;
81 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
83 #dma-cells = <1>;
84 clocks = <&cru ACLK_DMAC2>;
85 clock-names = "apb_pclk";
86 };
87
88 dmac_bus_ns: dma-controller@ff600000 {
89 compatible = "arm,pl330", "arm,primecell";
90 reg = <0xff600000 0x4000>;
91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
93 #dma-cells = <1>;
94 clocks = <&cru ACLK_DMAC1>;
95 clock-names = "apb_pclk";
96 status = "disabled";
97 };
98
99 dmac_bus_s: dma-controller@ffb20000 {
100 compatible = "arm,pl330", "arm,primecell";
101 reg = <0xffb20000 0x4000>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
104 #dma-cells = <1>;
105 clocks = <&cru ACLK_DMAC1>;
106 clock-names = "apb_pclk";
107 };
108 };
109
65 xin24m: oscillator { 110 xin24m: oscillator {
66 compatible = "fixed-clock"; 111 compatible = "fixed-clock";
67 clock-frequency = <24000000>; 112 clock-frequency = <24000000>;
@@ -78,6 +123,95 @@
78 clock-frequency = <24000000>; 123 clock-frequency = <24000000>;
79 }; 124 };
80 125
126 sdmmc: dwmmc@ff0c0000 {
127 compatible = "rockchip,rk3288-dw-mshc";
128 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
129 clock-names = "biu", "ciu";
130 fifo-depth = <0x100>;
131 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
132 reg = <0xff0c0000 0x4000>;
133 status = "disabled";
134 };
135
136 sdio0: dwmmc@ff0d0000 {
137 compatible = "rockchip,rk3288-dw-mshc";
138 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
139 clock-names = "biu", "ciu";
140 fifo-depth = <0x100>;
141 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
142 reg = <0xff0d0000 0x4000>;
143 status = "disabled";
144 };
145
146 sdio1: dwmmc@ff0e0000 {
147 compatible = "rockchip,rk3288-dw-mshc";
148 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
149 clock-names = "biu", "ciu";
150 fifo-depth = <0x100>;
151 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
152 reg = <0xff0e0000 0x4000>;
153 status = "disabled";
154 };
155
156 emmc: dwmmc@ff0f0000 {
157 compatible = "rockchip,rk3288-dw-mshc";
158 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
159 clock-names = "biu", "ciu";
160 fifo-depth = <0x100>;
161 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
162 reg = <0xff0f0000 0x4000>;
163 status = "disabled";
164 };
165
166 saradc: saradc@ff100000 {
167 compatible = "rockchip,saradc";
168 reg = <0xff100000 0x100>;
169 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
170 #io-channel-cells = <1>;
171 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
172 clock-names = "saradc", "apb_pclk";
173 status = "disabled";
174 };
175
176 spi0: spi@ff110000 {
177 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
178 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
179 clock-names = "spiclk", "apb_pclk";
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
183 reg = <0xff110000 0x1000>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 status = "disabled";
187 };
188
189 spi1: spi@ff120000 {
190 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
191 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
192 clock-names = "spiclk", "apb_pclk";
193 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
196 reg = <0xff120000 0x1000>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 status = "disabled";
200 };
201
202 spi2: spi@ff130000 {
203 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
204 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
205 clock-names = "spiclk", "apb_pclk";
206 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
209 reg = <0xff130000 0x1000>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 status = "disabled";
213 };
214
81 i2c1: i2c@ff140000 { 215 i2c1: i2c@ff140000 {
82 compatible = "rockchip,rk3288-i2c"; 216 compatible = "rockchip,rk3288-i2c";
83 reg = <0xff140000 0x1000>; 217 reg = <0xff140000 0x1000>;
@@ -206,6 +340,26 @@
206 340
207 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 341 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
208 342
343 usb_host1: usb@ff540000 {
344 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
345 "snps,dwc2";
346 reg = <0xff540000 0x40000>;
347 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru HCLK_USBHOST1>;
349 clock-names = "otg";
350 status = "disabled";
351 };
352
353 usb_otg: usb@ff580000 {
354 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
355 "snps,dwc2";
356 reg = <0xff580000 0x40000>;
357 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&cru HCLK_OTG0>;
359 clock-names = "otg";
360 status = "disabled";
361 };
362
209 usb_hsic: usb@ff5c0000 { 363 usb_hsic: usb@ff5c0000 {
210 compatible = "generic-ehci"; 364 compatible = "generic-ehci";
211 reg = <0xff5c0000 0x100>; 365 reg = <0xff5c0000 0x100>;
@@ -241,6 +395,50 @@
241 status = "disabled"; 395 status = "disabled";
242 }; 396 };
243 397
398 pwm0: pwm@ff680000 {
399 compatible = "rockchip,rk3288-pwm";
400 reg = <0xff680000 0x10>;
401 #pwm-cells = <3>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm0_pin>;
404 clocks = <&cru PCLK_PWM>;
405 clock-names = "pwm";
406 status = "disabled";
407 };
408
409 pwm1: pwm@ff680010 {
410 compatible = "rockchip,rk3288-pwm";
411 reg = <0xff680010 0x10>;
412 #pwm-cells = <3>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm1_pin>;
415 clocks = <&cru PCLK_PWM>;
416 clock-names = "pwm";
417 status = "disabled";
418 };
419
420 pwm2: pwm@ff680020 {
421 compatible = "rockchip,rk3288-pwm";
422 reg = <0xff680020 0x10>;
423 #pwm-cells = <3>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pwm2_pin>;
426 clocks = <&cru PCLK_PWM>;
427 clock-names = "pwm";
428 status = "disabled";
429 };
430
431 pwm3: pwm@ff680030 {
432 compatible = "rockchip,rk3288-pwm";
433 reg = <0xff680030 0x10>;
434 #pwm-cells = <2>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm3_pin>;
437 clocks = <&cru PCLK_PWM>;
438 clock-names = "pwm";
439 status = "disabled";
440 };
441
244 pmu: power-management@ff730000 { 442 pmu: power-management@ff730000 {
245 compatible = "rockchip,rk3288-pmu", "syscon"; 443 compatible = "rockchip,rk3288-pmu", "syscon";
246 reg = <0xff730000 0x100>; 444 reg = <0xff730000 0x100>;
@@ -271,6 +469,21 @@
271 status = "disabled"; 469 status = "disabled";
272 }; 470 };
273 471
472 i2s: i2s@ff890000 {
473 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
474 reg = <0xff890000 0x10000>;
475 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
479 dma-names = "tx", "rx";
480 clock-names = "i2s_hclk", "i2s_clk";
481 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
482 pinctrl-names = "default";
483 pinctrl-0 = <&i2s0_bus>;
484 status = "disabled";
485 };
486
274 gic: interrupt-controller@ffc01000 { 487 gic: interrupt-controller@ffc01000 {
275 compatible = "arm,gic-400"; 488 compatible = "arm,gic-400";
276 interrupt-controller; 489 interrupt-controller;
@@ -463,6 +676,17 @@
463 }; 676 };
464 }; 677 };
465 678
679 i2s0 {
680 i2s0_bus: i2s0-bus {
681 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
682 <6 1 RK_FUNC_1 &pcfg_pull_none>,
683 <6 2 RK_FUNC_1 &pcfg_pull_none>,
684 <6 3 RK_FUNC_1 &pcfg_pull_none>,
685 <6 4 RK_FUNC_1 &pcfg_pull_none>,
686 <6 8 RK_FUNC_1 &pcfg_pull_none>;
687 };
688 };
689
466 sdmmc { 690 sdmmc {
467 sdmmc_clk: sdmmc-clk { 691 sdmmc_clk: sdmmc-clk {
468 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 692 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
@@ -488,6 +712,88 @@
488 }; 712 };
489 }; 713 };
490 714
715 sdio0 {
716 sdio0_bus1: sdio0-bus1 {
717 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
718 };
719
720 sdio0_bus4: sdio0-bus4 {
721 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
722 <4 21 RK_FUNC_1 &pcfg_pull_up>,
723 <4 22 RK_FUNC_1 &pcfg_pull_up>,
724 <4 23 RK_FUNC_1 &pcfg_pull_up>;
725 };
726
727 sdio0_cmd: sdio0-cmd {
728 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
729 };
730
731 sdio0_clk: sdio0-clk {
732 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
733 };
734
735 sdio0_cd: sdio0-cd {
736 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
737 };
738
739 sdio0_wp: sdio0-wp {
740 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
741 };
742
743 sdio0_pwr: sdio0-pwr {
744 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
745 };
746
747 sdio0_bkpwr: sdio0-bkpwr {
748 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
749 };
750
751 sdio0_int: sdio0-int {
752 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
753 };
754 };
755
756 sdio1 {
757 sdio1_bus1: sdio1-bus1 {
758 rockchip,pins = <3 24 4 &pcfg_pull_up>;
759 };
760
761 sdio1_bus4: sdio1-bus4 {
762 rockchip,pins = <3 24 4 &pcfg_pull_up>,
763 <3 25 4 &pcfg_pull_up>,
764 <3 26 4 &pcfg_pull_up>,
765 <3 27 4 &pcfg_pull_up>;
766 };
767
768 sdio1_cd: sdio1-cd {
769 rockchip,pins = <3 28 4 &pcfg_pull_up>;
770 };
771
772 sdio1_wp: sdio1-wp {
773 rockchip,pins = <3 29 4 &pcfg_pull_up>;
774 };
775
776 sdio1_bkpwr: sdio1-bkpwr {
777 rockchip,pins = <3 30 4 &pcfg_pull_up>;
778 };
779
780 sdio1_int: sdio1-int {
781 rockchip,pins = <3 31 4 &pcfg_pull_up>;
782 };
783
784 sdio1_cmd: sdio1-cmd {
785 rockchip,pins = <4 6 4 &pcfg_pull_up>;
786 };
787
788 sdio1_clk: sdio1-clk {
789 rockchip,pins = <4 7 4 &pcfg_pull_none>;
790 };
791
792 sdio1_pwr: sdio1-pwr {
793 rockchip,pins = <4 9 4 &pcfg_pull_up>;
794 };
795 };
796
491 emmc { 797 emmc {
492 emmc_clk: emmc-clk { 798 emmc_clk: emmc-clk {
493 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 799 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
@@ -524,6 +830,56 @@
524 }; 830 };
525 }; 831 };
526 832
833 spi0 {
834 spi0_clk: spi0-clk {
835 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
836 };
837 spi0_cs0: spi0-cs0 {
838 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
839 };
840 spi0_tx: spi0-tx {
841 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
842 };
843 spi0_rx: spi0-rx {
844 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
845 };
846 spi0_cs1: spi0-cs1 {
847 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
848 };
849 };
850 spi1 {
851 spi1_clk: spi1-clk {
852 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
853 };
854 spi1_cs0: spi1-cs0 {
855 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
856 };
857 spi1_rx: spi1-rx {
858 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
859 };
860 spi1_tx: spi1-tx {
861 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
862 };
863 };
864
865 spi2 {
866 spi2_cs1: spi2-cs1 {
867 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
868 };
869 spi2_clk: spi2-clk {
870 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
871 };
872 spi2_cs0: spi2-cs0 {
873 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
874 };
875 spi2_rx: spi2-rx {
876 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
877 };
878 spi2_tx: spi2-tx {
879 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
880 };
881 };
882
527 uart0 { 883 uart0 {
528 uart0_xfer: uart0-xfer { 884 uart0_xfer: uart0-xfer {
529 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 885 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
@@ -591,5 +947,29 @@
591 rockchip,pins = <5 15 3 &pcfg_pull_none>; 947 rockchip,pins = <5 15 3 &pcfg_pull_none>;
592 }; 948 };
593 }; 949 };
950
951 pwm0 {
952 pwm0_pin: pwm0-pin {
953 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
954 };
955 };
956
957 pwm1 {
958 pwm1_pin: pwm1-pin {
959 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
960 };
961 };
962
963 pwm2 {
964 pwm2_pin: pwm2-pin {
965 rockchip,pins = <7 22 3 &pcfg_pull_none>;
966 };
967 };
968
969 pwm3 {
970 pwm3_pin: pwm3-pin {
971 rockchip,pins = <7 23 3 &pcfg_pull_none>;
972 };
973 };
594 }; 974 };
595}; 975};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 8caf85d83901..499468d42ada 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -26,6 +26,49 @@
26 i2c2 = &i2c2; 26 i2c2 = &i2c2;
27 i2c3 = &i2c3; 27 i2c3 = &i2c3;
28 i2c4 = &i2c4; 28 i2c4 = &i2c4;
29 mshc0 = &emmc;
30 mshc1 = &mmc0;
31 mshc2 = &mmc1;
32 spi0 = &spi0;
33 spi1 = &spi1;
34 };
35
36 amba {
37 compatible = "arm,amba-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges;
41
42 dmac1_s: dma-controller@20018000 {
43 compatible = "arm,pl330", "arm,primecell";
44 reg = <0x20018000 0x4000>;
45 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
47 #dma-cells = <1>;
48 clocks = <&cru ACLK_DMA1>;
49 clock-names = "apb_pclk";
50 };
51
52 dmac1_ns: dma-controller@2001c000 {
53 compatible = "arm,pl330", "arm,primecell";
54 reg = <0x2001c000 0x4000>;
55 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
57 #dma-cells = <1>;
58 clocks = <&cru ACLK_DMA1>;
59 clock-names = "apb_pclk";
60 status = "disabled";
61 };
62
63 dmac2: dma-controller@20078000 {
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x20078000 0x4000>;
66 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
68 #dma-cells = <1>;
69 clocks = <&cru ACLK_DMA2>;
70 clock-names = "apb_pclk";
71 };
29 }; 72 };
30 73
31 xin24m: oscillator { 74 xin24m: oscillator {
@@ -91,12 +134,45 @@
91 status = "disabled"; 134 status = "disabled";
92 }; 135 };
93 136
137 usb_otg: usb@10180000 {
138 compatible = "rockchip,rk3066-usb", "snps,dwc2";
139 reg = <0x10180000 0x40000>;
140 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cru HCLK_OTG0>;
142 clock-names = "otg";
143 status = "disabled";
144 };
145
146 usb_host: usb@101c0000 {
147 compatible = "snps,dwc2";
148 reg = <0x101c0000 0x40000>;
149 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&cru HCLK_OTG1>;
151 clock-names = "otg";
152 status = "disabled";
153 };
154
155 emac: ethernet@10204000 {
156 compatible = "snps,arc-emac";
157 reg = <0x10204000 0x3c>;
158 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161
162 rockchip,grf = <&grf>;
163
164 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
165 clock-names = "hclk", "macref";
166 max-speed = <100>;
167 phy-mode = "rmii";
168
169 status = "disabled";
170 };
171
94 mmc0: dwmmc@10214000 { 172 mmc0: dwmmc@10214000 {
95 compatible = "rockchip,rk2928-dw-mshc"; 173 compatible = "rockchip,rk2928-dw-mshc";
96 reg = <0x10214000 0x1000>; 174 reg = <0x10214000 0x1000>;
97 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 175 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 176
101 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 177 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
102 clock-names = "biu", "ciu"; 178 clock-names = "biu", "ciu";
@@ -108,8 +184,6 @@
108 compatible = "rockchip,rk2928-dw-mshc"; 184 compatible = "rockchip,rk2928-dw-mshc";
109 reg = <0x10218000 0x1000>; 185 reg = <0x10218000 0x1000>;
110 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 186 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 187
114 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 188 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
115 clock-names = "biu", "ciu"; 189 clock-names = "biu", "ciu";
@@ -117,6 +191,17 @@
117 status = "disabled"; 191 status = "disabled";
118 }; 192 };
119 193
194 emmc: dwmmc@1021c000 {
195 compatible = "rockchip,rk2928-dw-mshc";
196 reg = <0x1021c000 0x1000>;
197 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
198
199 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
200 clock-names = "biu", "ciu";
201
202 status = "disabled";
203 };
204
120 pmu: pmu@20004000 { 205 pmu: pmu@20004000 {
121 compatible = "rockchip,rk3066-pmu", "syscon"; 206 compatible = "rockchip,rk3066-pmu", "syscon";
122 reg = <0x20004000 0x100>; 207 reg = <0x20004000 0x100>;
@@ -135,7 +220,6 @@
135 #size-cells = <0>; 220 #size-cells = <0>;
136 221
137 rockchip,grf = <&grf>; 222 rockchip,grf = <&grf>;
138 rockchip,bus-index = <0>;
139 223
140 clock-names = "i2c"; 224 clock-names = "i2c";
141 clocks = <&cru PCLK_I2C0>; 225 clocks = <&cru PCLK_I2C0>;
@@ -264,4 +348,36 @@
264 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 348 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
265 status = "disabled"; 349 status = "disabled";
266 }; 350 };
351
352 saradc: saradc@2006c000 {
353 compatible = "rockchip,saradc";
354 reg = <0x2006c000 0x100>;
355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
356 #io-channel-cells = <1>;
357 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
358 clock-names = "saradc", "apb_pclk";
359 status = "disabled";
360 };
361
362 spi0: spi@20070000 {
363 compatible = "rockchip,rk3066-spi";
364 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
365 clock-names = "spiclk", "apb_pclk";
366 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
367 reg = <0x20070000 0x1000>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 status = "disabled";
371 };
372
373 spi1: spi@20074000 {
374 compatible = "rockchip,rk3066-spi";
375 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
376 clock-names = "spiclk", "apb_pclk";
377 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
378 reg = <0x20074000 0x1000>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 status = "disabled";
382 };
267}; 383};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 45013b867c8d..5f4144d1e3a1 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -177,6 +177,9 @@
177 compatible = "atmel,at91sam9260-usart"; 177 compatible = "atmel,at91sam9260-usart";
178 reg = <0xf001c000 0x100>; 178 reg = <0xf001c000 0x100>;
179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
180 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
181 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
182 dma-names = "tx", "rx";
180 pinctrl-names = "default"; 183 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usart0>; 184 pinctrl-0 = <&pinctrl_usart0>;
182 clocks = <&usart0_clk>; 185 clocks = <&usart0_clk>;
@@ -188,6 +191,9 @@
188 compatible = "atmel,at91sam9260-usart"; 191 compatible = "atmel,at91sam9260-usart";
189 reg = <0xf0020000 0x100>; 192 reg = <0xf0020000 0x100>;
190 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 193 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
194 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
195 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
196 dma-names = "tx", "rx";
191 pinctrl-names = "default"; 197 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_usart1>; 198 pinctrl-0 = <&pinctrl_usart1>;
193 clocks = <&usart1_clk>; 199 clocks = <&usart1_clk>;
@@ -333,6 +339,9 @@
333 compatible = "atmel,at91sam9260-usart"; 339 compatible = "atmel,at91sam9260-usart";
334 reg = <0xf8020000 0x100>; 340 reg = <0xf8020000 0x100>;
335 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 341 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
342 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
343 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
344 dma-names = "tx", "rx";
336 pinctrl-names = "default"; 345 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_usart2>; 346 pinctrl-0 = <&pinctrl_usart2>;
338 clocks = <&usart2_clk>; 347 clocks = <&usart2_clk>;
@@ -344,6 +353,9 @@
344 compatible = "atmel,at91sam9260-usart"; 353 compatible = "atmel,at91sam9260-usart";
345 reg = <0xf8024000 0x100>; 354 reg = <0xf8024000 0x100>;
346 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 355 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
356 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
357 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
358 dma-names = "tx", "rx";
347 pinctrl-names = "default"; 359 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_usart3>; 360 pinctrl-0 = <&pinctrl_usart3>;
349 clocks = <&usart3_clk>; 361 clocks = <&usart3_clk>;
@@ -402,14 +414,19 @@
402 }; 414 };
403 415
404 ramc0: ramc@ffffea00 { 416 ramc0: ramc@ffffea00 {
405 compatible = "atmel,at91sam9g45-ddramc"; 417 compatible = "atmel,sama5d3-ddramc";
406 reg = <0xffffea00 0x200>; 418 reg = <0xffffea00 0x200>;
419 clocks = <&ddrck>, <&mpddr_clk>;
420 clock-names = "ddrck", "mpddr";
407 }; 421 };
408 422
409 dbgu: serial@ffffee00 { 423 dbgu: serial@ffffee00 {
410 compatible = "atmel,at91sam9260-usart"; 424 compatible = "atmel,at91sam9260-usart";
411 reg = <0xffffee00 0x200>; 425 reg = <0xffffee00 0x200>;
412 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 426 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
427 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
428 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
429 dma-names = "tx", "rx";
413 pinctrl-names = "default"; 430 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_dbgu>; 431 pinctrl-0 = <&pinctrl_dbgu>;
415 clocks = <&dbgu_clk>; 432 clocks = <&dbgu_clk>;
@@ -428,7 +445,7 @@
428 pinctrl@fffff200 { 445 pinctrl@fffff200 {
429 #address-cells = <1>; 446 #address-cells = <1>;
430 #size-cells = <1>; 447 #size-cells = <1>;
431 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 448 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
432 ranges = <0xfffff200 0xfffff200 0xa00>; 449 ranges = <0xfffff200 0xfffff200 0xa00>;
433 atmel,mux-mask = < 450 atmel,mux-mask = <
434 /* A B C */ 451 /* A B C */
@@ -1003,6 +1020,11 @@
1003 reg = <2>; 1020 reg = <2>;
1004 }; 1021 };
1005 1022
1023 hsmc_clk: hsmc_clk {
1024 #clock-cells = <0>;
1025 reg = <5>;
1026 };
1027
1006 pioA_clk: pioA_clk { 1028 pioA_clk: pioA_clk {
1007 #clock-cells = <0>; 1029 #clock-cells = <0>;
1008 reg = <6>; 1030 reg = <6>;
@@ -1170,6 +1192,11 @@
1170 #clock-cells = <0>; 1192 #clock-cells = <0>;
1171 reg = <48>; 1193 reg = <48>;
1172 }; 1194 };
1195
1196 mpddr_clk: mpddr_clk {
1197 #clock-cells = <0>;
1198 reg = <49>;
1199 };
1173 }; 1200 };
1174 }; 1201 };
1175 1202
@@ -1178,6 +1205,11 @@
1178 reg = <0xfffffe00 0x10>; 1205 reg = <0xfffffe00 0x10>;
1179 }; 1206 };
1180 1207
1208 shutdown-controller@fffffe10 {
1209 compatible = "atmel,at91sam9x5-shdwc";
1210 reg = <0xfffffe10 0x10>;
1211 };
1212
1181 pit: timer@fffffe30 { 1213 pit: timer@fffffe30 {
1182 compatible = "atmel,at91sam9260-pit"; 1214 compatible = "atmel,at91sam9260-pit";
1183 reg = <0xfffffe30 0xf>; 1215 reg = <0xfffffe30 0xf>;
@@ -1393,6 +1425,7 @@
1393 0xffffc000 0x00000070 /* NFC HSMC regs */ 1425 0xffffc000 0x00000070 /* NFC HSMC regs */
1394 0x00200000 0x00100000 /* NFC SRAM banks */ 1426 0x00200000 0x00100000 /* NFC SRAM banks */
1395 >; 1427 >;
1428 clocks = <&hsmc_clk>;
1396 }; 1429 };
1397 }; 1430 };
1398 }; 1431 };
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index a0775851cce5..eaf41451ad0c 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -40,7 +40,7 @@
40 atmel,clk-output-range = <0 66000000>; 40 atmel,clk-output-range = <0 66000000>;
41 }; 41 };
42 42
43 can1_clk: can0_clk { 43 can1_clk: can1_clk {
44 #clock-cells = <0>; 44 #clock-cells = <0>;
45 reg = <41>; 45 reg = <41>;
46 atmel,clk-output-range = <0 66000000>; 46 atmel,clk-output-range = <0 66000000>;
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index f7d8583eef82..962dc28dc37b 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -36,6 +36,36 @@
36 36
37 macb0: ethernet@f0028000 { 37 macb0: ethernet@f0028000 {
38 phy-mode = "rgmii"; 38 phy-mode = "rgmii";
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 ethernet-phy@1 {
43 reg = <0x1>;
44 interrupt-parent = <&pioB>;
45 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
46 txen-skew-ps = <800>;
47 txc-skew-ps = <3000>;
48 rxdv-skew-ps = <400>;
49 rxc-skew-ps = <3000>;
50 rxd0-skew-ps = <400>;
51 rxd1-skew-ps = <400>;
52 rxd2-skew-ps = <400>;
53 rxd3-skew-ps = <400>;
54 };
55
56 ethernet-phy@7 {
57 reg = <0x7>;
58 interrupt-parent = <&pioB>;
59 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
60 txen-skew-ps = <800>;
61 txc-skew-ps = <3000>;
62 rxdv-skew-ps = <400>;
63 rxc-skew-ps = <3000>;
64 rxd0-skew-ps = <400>;
65 rxd1-skew-ps = <400>;
66 rxd2-skew-ps = <400>;
67 rxd3-skew-ps = <400>;
68 };
39 }; 69 };
40 70
41 pmc: pmc@fffffc00 { 71 pmc: pmc@fffffc00 {
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index b8c6f20e780c..49c10d33df30 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -25,6 +25,8 @@
25 }; 25 };
26 26
27 spi0: spi@f0004000 { 27 spi0: spi@f0004000 {
28 dmas = <0>, <0>; /* Do not use DMA for spi0 */
29
28 m25p80@0 { 30 m25p80@0 {
29 compatible = "atmel,at25df321a"; 31 compatible = "atmel,at25df321a";
30 spi-max-frequency = <50000000>; 32 spi-max-frequency = <50000000>;
@@ -51,6 +53,7 @@
51 }; 53 };
52 54
53 usart1: serial@f0020000 { 55 usart1: serial@f0020000 {
56 dmas = <0>, <0>; /* Do not use DMA for usart1 */
54 pinctrl-names = "default"; 57 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; 58 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
56 status = "okay"; 59 status = "okay";
@@ -132,6 +135,7 @@
132 }; 135 };
133 136
134 dbgu: serial@ffffee00 { 137 dbgu: serial@ffffee00 {
138 dmas = <0>, <0>; /* Do not use DMA for dbgu */
135 status = "okay"; 139 status = "okay";
136 }; 140 };
137 141
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
new file mode 100644
index 000000000000..e0157b0f075c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -0,0 +1,1240 @@
1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This library is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/pinctrl/at91.h>
49#include <dt-bindings/interrupt-controller/irq.h>
50#include <dt-bindings/gpio/gpio.h>
51
52/ {
53 model = "Atmel SAMA5D4 family SoC";
54 compatible = "atmel,sama5d4";
55 interrupt-parent = <&aic>;
56
57 aliases {
58 serial0 = &usart3;
59 serial1 = &usart4;
60 serial2 = &usart2;
61 gpio0 = &pioA;
62 gpio1 = &pioB;
63 gpio2 = &pioC;
64 gpio4 = &pioE;
65 tcb0 = &tcb0;
66 tcb1 = &tcb1;
67 i2c2 = &i2c2;
68 };
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu@0 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a5";
76 reg = <0>;
77 next-level-cache = <&L2>;
78 };
79 };
80
81 memory {
82 reg = <0x20000000 0x20000000>;
83 };
84
85 clocks {
86 slow_xtal: slow_xtal {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <0>;
90 };
91
92 main_xtal: main_xtal {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <0>;
96 };
97
98 adc_op_clk: adc_op_clk{
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <1000000>;
102 };
103 };
104
105 ahb {
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 usb0: gadget@00400000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "atmel,at91sam9rl-udc";
115 reg = <0x00400000 0x100000
116 0xfc02c000 0x4000>;
117 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
118 clocks = <&udphs_clk>, <&utmi>;
119 clock-names = "pclk", "hclk";
120 status = "disabled";
121
122 ep0 {
123 reg = <0>;
124 atmel,fifo-size = <64>;
125 atmel,nb-banks = <1>;
126 };
127
128 ep1 {
129 reg = <1>;
130 atmel,fifo-size = <1024>;
131 atmel,nb-banks = <3>;
132 atmel,can-dma;
133 atmel,can-isoc;
134 };
135
136 ep2 {
137 reg = <2>;
138 atmel,fifo-size = <1024>;
139 atmel,nb-banks = <3>;
140 atmel,can-dma;
141 atmel,can-isoc;
142 };
143
144 ep3 {
145 reg = <3>;
146 atmel,fifo-size = <1024>;
147 atmel,nb-banks = <2>;
148 atmel,can-dma;
149 atmel,can-isoc;
150 };
151
152 ep4 {
153 reg = <4>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <2>;
156 atmel,can-dma;
157 atmel,can-isoc;
158 };
159
160 ep5 {
161 reg = <5>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <2>;
164 atmel,can-dma;
165 atmel,can-isoc;
166 };
167
168 ep6 {
169 reg = <6>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
172 atmel,can-dma;
173 atmel,can-isoc;
174 };
175
176 ep7 {
177 reg = <7>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
180 atmel,can-dma;
181 atmel,can-isoc;
182 };
183
184 ep8 {
185 reg = <8>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
188 atmel,can-isoc;
189 };
190
191 ep9 {
192 reg = <9>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
195 atmel,can-isoc;
196 };
197
198 ep10 {
199 reg = <10>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
202 atmel,can-isoc;
203 };
204
205 ep11 {
206 reg = <11>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
209 atmel,can-isoc;
210 };
211
212 ep12 {
213 reg = <12>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
216 atmel,can-isoc;
217 };
218
219 ep13 {
220 reg = <13>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
223 atmel,can-isoc;
224 };
225
226 ep14 {
227 reg = <14>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
230 atmel,can-isoc;
231 };
232
233 ep15 {
234 reg = <15>;
235 atmel,fifo-size = <1024>;
236 atmel,nb-banks = <2>;
237 atmel,can-isoc;
238 };
239 };
240
241 usb1: ohci@00500000 {
242 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
243 reg = <0x00500000 0x100000>;
244 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
245 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
246 <&uhpck>;
247 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
248 status = "disabled";
249 };
250
251 usb2: ehci@00600000 {
252 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
253 reg = <0x00600000 0x100000>;
254 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
255 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
256 clock-names = "usb_clk", "ehci_clk", "uhpck";
257 status = "disabled";
258 };
259
260 L2: cache-controller@00a00000 {
261 compatible = "arm,pl310-cache";
262 reg = <0x00a00000 0x1000>;
263 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
264 cache-unified;
265 cache-level = <2>;
266 };
267
268 nand0: nand@80000000 {
269 compatible = "atmel,at91rm9200-nand";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 ranges;
273 reg = < 0x80000000 0x08000000 /* EBI CS3 */
274 0xfc05c070 0x00000490 /* SMC PMECC regs */
275 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
276 >;
277 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
278 atmel,nand-addr-offset = <21>;
279 atmel,nand-cmd-offset = <22>;
280 atmel,nand-has-dma;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_nand>;
283 status = "disabled";
284
285 nfc@90000000 {
286 compatible = "atmel,sama5d3-nfc";
287 #address-cells = <1>;
288 #size-cells = <1>;
289 reg = <
290 0x90000000 0x10000000 /* NFC Command Registers */
291 0xfc05c000 0x00000070 /* NFC HSMC regs */
292 0x00100000 0x00100000 /* NFC SRAM banks */
293 >;
294 clocks = <&hsmc_clk>;
295 atmel,write-by-sram;
296 };
297 };
298
299 apb {
300 compatible = "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges;
304
305 ramc0: ramc@f0010000 {
306 compatible = "atmel,sama5d3-ddramc";
307 reg = <0xf0010000 0x200>;
308 clocks = <&ddrck>, <&mpddr_clk>;
309 clock-names = "ddrck", "mpddr";
310 };
311
312 pmc: pmc@f0018000 {
313 compatible = "atmel,sama5d3-pmc";
314 reg = <0xf0018000 0x120>;
315 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
316 interrupt-controller;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 #interrupt-cells = <1>;
320
321 main_rc_osc: main_rc_osc {
322 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
323 #clock-cells = <0>;
324 interrupt-parent = <&pmc>;
325 interrupts = <AT91_PMC_MOSCRCS>;
326 clock-frequency = <12000000>;
327 clock-accuracy = <100000000>;
328 };
329
330 main_osc: main_osc {
331 compatible = "atmel,at91rm9200-clk-main-osc";
332 #clock-cells = <0>;
333 interrupt-parent = <&pmc>;
334 interrupts = <AT91_PMC_MOSCS>;
335 clocks = <&main_xtal>;
336 };
337
338 main: mainck {
339 compatible = "atmel,at91sam9x5-clk-main";
340 #clock-cells = <0>;
341 interrupt-parent = <&pmc>;
342 interrupts = <AT91_PMC_MOSCSELS>;
343 clocks = <&main_rc_osc &main_osc>;
344 };
345
346 plla: pllack {
347 compatible = "atmel,sama5d3-clk-pll";
348 #clock-cells = <0>;
349 interrupt-parent = <&pmc>;
350 interrupts = <AT91_PMC_LOCKA>;
351 clocks = <&main>;
352 reg = <0>;
353 atmel,clk-input-range = <12000000 12000000>;
354 #atmel,pll-clk-output-range-cells = <4>;
355 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
356 };
357
358 plladiv: plladivck {
359 compatible = "atmel,at91sam9x5-clk-plldiv";
360 #clock-cells = <0>;
361 clocks = <&plla>;
362 };
363
364 utmi: utmick {
365 compatible = "atmel,at91sam9x5-clk-utmi";
366 #clock-cells = <0>;
367 interrupt-parent = <&pmc>;
368 interrupts = <AT91_PMC_LOCKU>;
369 clocks = <&main>;
370 };
371
372 mck: masterck {
373 compatible = "atmel,at91sam9x5-clk-master";
374 #clock-cells = <0>;
375 interrupt-parent = <&pmc>;
376 interrupts = <AT91_PMC_MCKRDY>;
377 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
378 atmel,clk-output-range = <125000000 177000000>;
379 atmel,clk-divisors = <1 2 4 3>;
380 };
381
382 h32ck: h32mxck {
383 #clock-cells = <0>;
384 compatible = "atmel,sama5d4-clk-h32mx";
385 clocks = <&mck>;
386 };
387
388 usb: usbck {
389 compatible = "atmel,at91sam9x5-clk-usb";
390 #clock-cells = <0>;
391 clocks = <&plladiv>, <&utmi>;
392 };
393
394 prog: progck {
395 compatible = "atmel,at91sam9x5-clk-programmable";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 interrupt-parent = <&pmc>;
399 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
400
401 prog0: prog0 {
402 #clock-cells = <0>;
403 reg = <0>;
404 interrupts = <AT91_PMC_PCKRDY(0)>;
405 };
406
407 prog1: prog1 {
408 #clock-cells = <0>;
409 reg = <1>;
410 interrupts = <AT91_PMC_PCKRDY(1)>;
411 };
412
413 prog2: prog2 {
414 #clock-cells = <0>;
415 reg = <2>;
416 interrupts = <AT91_PMC_PCKRDY(2)>;
417 };
418 };
419
420 smd: smdclk {
421 compatible = "atmel,at91sam9x5-clk-smd";
422 #clock-cells = <0>;
423 clocks = <&plladiv>, <&utmi>;
424 };
425
426 systemck {
427 compatible = "atmel,at91rm9200-clk-system";
428 #address-cells = <1>;
429 #size-cells = <0>;
430
431 ddrck: ddrck {
432 #clock-cells = <0>;
433 reg = <2>;
434 clocks = <&mck>;
435 };
436
437 lcdck: lcdck {
438 #clock-cells = <0>;
439 reg = <4>;
440 clocks = <&smd>;
441 };
442
443 smdck: smdck {
444 #clock-cells = <0>;
445 reg = <4>;
446 clocks = <&smd>;
447 };
448
449 uhpck: uhpck {
450 #clock-cells = <0>;
451 reg = <6>;
452 clocks = <&usb>;
453 };
454
455 udpck: udpck {
456 #clock-cells = <0>;
457 reg = <7>;
458 clocks = <&usb>;
459 };
460
461 pck0: pck0 {
462 #clock-cells = <0>;
463 reg = <8>;
464 clocks = <&prog0>;
465 };
466
467 pck1: pck1 {
468 #clock-cells = <0>;
469 reg = <9>;
470 clocks = <&prog1>;
471 };
472
473 pck2: pck2 {
474 #clock-cells = <0>;
475 reg = <10>;
476 clocks = <&prog2>;
477 };
478 };
479
480 periph32ck {
481 compatible = "atmel,at91sam9x5-clk-peripheral";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clocks = <&h32ck>;
485
486 pioD_clk: pioD_clk {
487 #clock-cells = <0>;
488 reg = <5>;
489 };
490
491 usart0_clk: usart0_clk {
492 #clock-cells = <0>;
493 reg = <6>;
494 };
495
496 usart1_clk: usart1_clk {
497 #clock-cells = <0>;
498 reg = <7>;
499 };
500
501 icm_clk: icm_clk {
502 #clock-cells = <0>;
503 reg = <9>;
504 };
505
506 aes_clk: aes_clk {
507 #clock-cells = <0>;
508 reg = <12>;
509 };
510
511 tdes_clk: tdes_clk {
512 #clock-cells = <0>;
513 reg = <14>;
514 };
515
516 sha_clk: sha_clk {
517 #clock-cells = <0>;
518 reg = <15>;
519 };
520
521 matrix1_clk: matrix1_clk {
522 #clock-cells = <0>;
523 reg = <17>;
524 };
525
526 hsmc_clk: hsmc_clk {
527 #clock-cells = <0>;
528 reg = <22>;
529 };
530
531 pioA_clk: pioA_clk {
532 #clock-cells = <0>;
533 reg = <23>;
534 };
535
536 pioB_clk: pioB_clk {
537 #clock-cells = <0>;
538 reg = <24>;
539 };
540
541 pioC_clk: pioC_clk {
542 #clock-cells = <0>;
543 reg = <25>;
544 };
545
546 pioE_clk: pioE_clk {
547 #clock-cells = <0>;
548 reg = <26>;
549 };
550
551 uart0_clk: uart0_clk {
552 #clock-cells = <0>;
553 reg = <27>;
554 };
555
556 uart1_clk: uart1_clk {
557 #clock-cells = <0>;
558 reg = <28>;
559 };
560
561 usart2_clk: usart2_clk {
562 #clock-cells = <0>;
563 reg = <29>;
564 };
565
566 usart3_clk: usart3_clk {
567 #clock-cells = <0>;
568 reg = <30>;
569 };
570
571 usart4_clk: usart4_clk {
572 #clock-cells = <0>;
573 reg = <31>;
574 };
575
576 twi0_clk: twi0_clk {
577 reg = <32>;
578 #clock-cells = <0>;
579 };
580
581 twi1_clk: twi1_clk {
582 #clock-cells = <0>;
583 reg = <33>;
584 };
585
586 twi2_clk: twi2_clk {
587 #clock-cells = <0>;
588 reg = <34>;
589 };
590
591 mci0_clk: mci0_clk {
592 #clock-cells = <0>;
593 reg = <35>;
594 };
595
596 mci1_clk: mci1_clk {
597 #clock-cells = <0>;
598 reg = <36>;
599 };
600
601 spi0_clk: spi0_clk {
602 #clock-cells = <0>;
603 reg = <37>;
604 };
605
606 spi1_clk: spi1_clk {
607 #clock-cells = <0>;
608 reg = <38>;
609 };
610
611 spi2_clk: spi2_clk {
612 #clock-cells = <0>;
613 reg = <39>;
614 };
615
616 tcb0_clk: tcb0_clk {
617 #clock-cells = <0>;
618 reg = <40>;
619 };
620
621 tcb1_clk: tcb1_clk {
622 #clock-cells = <0>;
623 reg = <41>;
624 };
625
626 tcb2_clk: tcb2_clk {
627 #clock-cells = <0>;
628 reg = <42>;
629 };
630
631 pwm_clk: pwm_clk {
632 #clock-cells = <0>;
633 reg = <43>;
634 };
635
636 adc_clk: adc_clk {
637 #clock-cells = <0>;
638 reg = <44>;
639 };
640
641 dbgu_clk: dbgu_clk {
642 #clock-cells = <0>;
643 reg = <45>;
644 };
645
646 uhphs_clk: uhphs_clk {
647 #clock-cells = <0>;
648 reg = <46>;
649 };
650
651 udphs_clk: udphs_clk {
652 #clock-cells = <0>;
653 reg = <47>;
654 };
655
656 ssc0_clk: ssc0_clk {
657 #clock-cells = <0>;
658 reg = <48>;
659 };
660
661 ssc1_clk: ssc1_clk {
662 #clock-cells = <0>;
663 reg = <49>;
664 };
665
666 trng_clk: trng_clk {
667 #clock-cells = <0>;
668 reg = <53>;
669 };
670
671 macb0_clk: macb0_clk {
672 #clock-cells = <0>;
673 reg = <54>;
674 };
675
676 macb1_clk: macb1_clk {
677 #clock-cells = <0>;
678 reg = <55>;
679 };
680
681 fuse_clk: fuse_clk {
682 #clock-cells = <0>;
683 reg = <57>;
684 };
685
686 securam_clk: securam_clk {
687 #clock-cells = <0>;
688 reg = <59>;
689 };
690
691 smd_clk: smd_clk {
692 #clock-cells = <0>;
693 reg = <61>;
694 };
695
696 twi3_clk: twi3_clk {
697 #clock-cells = <0>;
698 reg = <62>;
699 };
700
701 catb_clk: catb_clk {
702 #clock-cells = <0>;
703 reg = <63>;
704 };
705 };
706
707 periph64ck {
708 compatible = "atmel,at91sam9x5-clk-peripheral";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 clocks = <&mck>;
712
713 dma0_clk: dma0_clk {
714 #clock-cells = <0>;
715 reg = <8>;
716 };
717
718 cpkcc_clk: cpkcc_clk {
719 #clock-cells = <0>;
720 reg = <10>;
721 };
722
723 aesb_clk: aesb_clk {
724 #clock-cells = <0>;
725 reg = <13>;
726 };
727
728 mpddr_clk: mpddr_clk {
729 #clock-cells = <0>;
730 reg = <16>;
731 };
732
733 matrix0_clk: matrix0_clk {
734 #clock-cells = <0>;
735 reg = <18>;
736 };
737
738 vdec_clk: vdec_clk {
739 #clock-cells = <0>;
740 reg = <19>;
741 };
742
743 dma1_clk: dma1_clk {
744 #clock-cells = <0>;
745 reg = <50>;
746 };
747
748 lcd_clk: lcd_clk {
749 #clock-cells = <0>;
750 reg = <51>;
751 };
752
753 isi_clk: isi_clk {
754 #clock-cells = <0>;
755 reg = <52>;
756 };
757 };
758 };
759
760 mmc0: mmc@f8000000 {
761 compatible = "atmel,hsmci";
762 reg = <0xf8000000 0x600>;
763 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
766 status = "disabled";
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&mci0_clk>;
770 clock-names = "mci_clk";
771 };
772
773 spi0: spi@f8010000 {
774 #address-cells = <1>;
775 #size-cells = <0>;
776 compatible = "atmel,at91rm9200-spi";
777 reg = <0xf8010000 0x100>;
778 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&pinctrl_spi0>;
781 clocks = <&spi0_clk>;
782 clock-names = "spi_clk";
783 status = "disabled";
784 };
785
786 i2c0: i2c@f8014000 {
787 compatible = "atmel,at91sam9x5-i2c";
788 reg = <0xf8014000 0x4000>;
789 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&pinctrl_i2c0>;
792 #address-cells = <1>;
793 #size-cells = <0>;
794 clocks = <&twi0_clk>;
795 status = "disabled";
796 };
797
798 tcb0: timer@f801c000 {
799 compatible = "atmel,at91sam9x5-tcb";
800 reg = <0xf801c000 0x100>;
801 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
802 clocks = <&tcb0_clk>;
803 clock-names = "t0_clk";
804 };
805
806 macb0: ethernet@f8020000 {
807 compatible = "atmel,sama5d4-gem";
808 reg = <0xf8020000 0x100>;
809 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_macb0_rmii>;
812 clocks = <&macb0_clk>, <&macb0_clk>;
813 clock-names = "hclk", "pclk";
814 status = "disabled";
815 };
816
817 i2c2: i2c@f8024000 {
818 compatible = "atmel,at91sam9x5-i2c";
819 reg = <0xf8024000 0x4000>;
820 interrupts = <34 4 6>;
821 pinctrl-names = "default";
822 pinctrl-0 = <&pinctrl_i2c2>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&twi2_clk>;
826 status = "disabled";
827 };
828
829 mmc1: mmc@fc000000 {
830 compatible = "atmel,hsmci";
831 reg = <0xfc000000 0x600>;
832 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
835 status = "disabled";
836 #address-cells = <1>;
837 #size-cells = <0>;
838 clocks = <&mci1_clk>;
839 clock-names = "mci_clk";
840 };
841
842 usart2: serial@fc008000 {
843 compatible = "atmel,at91sam9260-usart";
844 reg = <0xfc008000 0x100>;
845 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
848 clocks = <&usart2_clk>;
849 clock-names = "usart";
850 status = "disabled";
851 };
852
853 usart3: serial@fc00c000 {
854 compatible = "atmel,at91sam9260-usart";
855 reg = <0xfc00c000 0x100>;
856 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&pinctrl_usart3>;
859 clocks = <&usart3_clk>;
860 clock-names = "usart";
861 status = "disabled";
862 };
863
864 usart4: serial@fc010000 {
865 compatible = "atmel,at91sam9260-usart";
866 reg = <0xfc010000 0x100>;
867 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&pinctrl_usart4>;
870 clocks = <&usart4_clk>;
871 clock-names = "usart";
872 status = "disabled";
873 };
874
875 tcb1: timer@fc020000 {
876 compatible = "atmel,at91sam9x5-tcb";
877 reg = <0xfc020000 0x100>;
878 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&tcb1_clk>;
880 clock-names = "t0_clk";
881 };
882
883 adc0: adc@fc034000 {
884 compatible = "atmel,at91sam9x5-adc";
885 reg = <0xfc034000 0x100>;
886 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
887 pinctrl-names = "default";
888 pinctrl-0 = <
889 /* external trigger is conflict with USBA_VBUS */
890 &pinctrl_adc0_ad0
891 &pinctrl_adc0_ad1
892 &pinctrl_adc0_ad2
893 &pinctrl_adc0_ad3
894 &pinctrl_adc0_ad4
895 >;
896 clocks = <&adc_clk>,
897 <&adc_op_clk>;
898 clock-names = "adc_clk", "adc_op_clk";
899 atmel,adc-channels-used = <0x01f>;
900 atmel,adc-startup-time = <40>;
901 atmel,adc-use-external;
902 atmel,adc-vref = <3000>;
903 atmel,adc-res = <8 10>;
904 atmel,adc-sample-hold-time = <11>;
905 atmel,adc-res-names = "lowres", "highres";
906 atmel,adc-ts-pressure-threshold = <10000>;
907 status = "disabled";
908
909 trigger@0 {
910 trigger-name = "external-rising";
911 trigger-value = <0x1>;
912 trigger-external;
913 };
914 trigger@1 {
915 trigger-name = "external-falling";
916 trigger-value = <0x2>;
917 trigger-external;
918 };
919 trigger@2 {
920 trigger-name = "external-any";
921 trigger-value = <0x3>;
922 trigger-external;
923 };
924 trigger@3 {
925 trigger-name = "continuous";
926 trigger-value = <0x6>;
927 };
928 };
929
930 rstc@fc068600 {
931 compatible = "atmel,at91sam9g45-rstc";
932 reg = <0xfc068600 0x10>;
933 };
934
935 shdwc@fc068610 {
936 compatible = "atmel,at91sam9x5-shdwc";
937 reg = <0xfc068610 0x10>;
938 };
939
940 pit: timer@fc068630 {
941 compatible = "atmel,at91sam9260-pit";
942 reg = <0xfc068630 0xf>;
943 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
944 clocks = <&h32ck>;
945 };
946
947 watchdog@fc068640 {
948 compatible = "atmel,at91sam9260-wdt";
949 reg = <0xfc068640 0x10>;
950 status = "disabled";
951 };
952
953 sckc@fc068650 {
954 compatible = "atmel,at91sam9x5-sckc";
955 reg = <0xfc068650 0x4>;
956
957 slow_rc_osc: slow_rc_osc {
958 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
959 #clock-cells = <0>;
960 clock-frequency = <32768>;
961 clock-accuracy = <250000000>;
962 atmel,startup-time-usec = <75>;
963 };
964
965 slow_osc: slow_osc {
966 compatible = "atmel,at91sam9x5-clk-slow-osc";
967 #clock-cells = <0>;
968 clocks = <&slow_xtal>;
969 atmel,startup-time-usec = <1200000>;
970 };
971
972 clk32k: slowck {
973 compatible = "atmel,at91sam9x5-clk-slow";
974 #clock-cells = <0>;
975 clocks = <&slow_rc_osc &slow_osc>;
976 };
977 };
978
979 rtc@fc0686b0 {
980 compatible = "atmel,at91rm9200-rtc";
981 reg = <0xfc0686b0 0x30>;
982 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
983 };
984
985 dbgu: serial@fc069000 {
986 compatible = "atmel,at91sam9260-usart";
987 reg = <0xfc069000 0x200>;
988 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&pinctrl_dbgu>;
991 clocks = <&dbgu_clk>;
992 clock-names = "usart";
993 status = "disabled";
994 };
995
996
997 pinctrl@fc06a000 {
998 #address-cells = <1>;
999 #size-cells = <1>;
1000 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1001 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1002 /* WARNING: revisit as pin spec has changed */
1003 atmel,mux-mask = <
1004 /* A B C */
1005 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1006 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1007 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1008 0x00000000 0x00000000 0x00000000 /* pioD */
1009 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1010 >;
1011
1012 pioA: gpio@fc06a000 {
1013 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1014 reg = <0xfc06a000 0x100>;
1015 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1016 #gpio-cells = <2>;
1017 gpio-controller;
1018 interrupt-controller;
1019 #interrupt-cells = <2>;
1020 clocks = <&pioA_clk>;
1021 };
1022
1023 pioB: gpio@fc06b000 {
1024 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1025 reg = <0xfc06b000 0x100>;
1026 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1027 #gpio-cells = <2>;
1028 gpio-controller;
1029 interrupt-controller;
1030 #interrupt-cells = <2>;
1031 clocks = <&pioB_clk>;
1032 };
1033
1034 pioC: gpio@fc06c000 {
1035 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1036 reg = <0xfc06c000 0x100>;
1037 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1038 #gpio-cells = <2>;
1039 gpio-controller;
1040 interrupt-controller;
1041 #interrupt-cells = <2>;
1042 clocks = <&pioC_clk>;
1043 };
1044
1045 pioE: gpio@fc06d000 {
1046 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1047 reg = <0xfc06d000 0x100>;
1048 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1049 #gpio-cells = <2>;
1050 gpio-controller;
1051 interrupt-controller;
1052 #interrupt-cells = <2>;
1053 clocks = <&pioE_clk>;
1054 };
1055
1056 /* pinctrl pin settings */
1057 adc0 {
1058 pinctrl_adc0_adtrg: adc0_adtrg {
1059 atmel,pins =
1060 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1061 };
1062 pinctrl_adc0_ad0: adc0_ad0 {
1063 atmel,pins =
1064 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1065 };
1066 pinctrl_adc0_ad1: adc0_ad1 {
1067 atmel,pins =
1068 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1069 };
1070 pinctrl_adc0_ad2: adc0_ad2 {
1071 atmel,pins =
1072 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1073 };
1074 pinctrl_adc0_ad3: adc0_ad3 {
1075 atmel,pins =
1076 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1077 };
1078 pinctrl_adc0_ad4: adc0_ad4 {
1079 atmel,pins =
1080 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1081 };
1082 };
1083
1084 dbgu {
1085 pinctrl_dbgu: dbgu-0 {
1086 atmel,pins =
1087 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1088 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1089 };
1090 };
1091
1092 i2c0 {
1093 pinctrl_i2c0: i2c0-0 {
1094 atmel,pins =
1095 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1096 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1097 };
1098 };
1099
1100 i2c2 {
1101 pinctrl_i2c2: i2c2-0 {
1102 atmel,pins =
1103 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1104 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1105 };
1106 };
1107
1108 macb0 {
1109 pinctrl_macb0_rmii: macb0_rmii-0 {
1110 atmel,pins =
1111 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1112 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1113 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1114 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1115 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1116 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1117 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1118 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1119 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1120 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1121 >;
1122 };
1123 };
1124
1125 mmc0 {
1126 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1127 atmel,pins =
1128 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1129 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1130 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1131 >;
1132 };
1133 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1134 atmel,pins =
1135 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1136 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1137 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1138 >;
1139 };
1140 };
1141
1142 mmc1 {
1143 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1144 atmel,pins =
1145 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1146 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1147 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1148 >;
1149 };
1150 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1151 atmel,pins =
1152 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1153 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1154 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1155 >;
1156 };
1157 };
1158
1159 nand0 {
1160 pinctrl_nand: nand-0 {
1161 atmel,pins =
1162 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1163 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1164
1165 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1166 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1167
1168 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1169 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1170 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1171 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1172 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1173 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1174 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1175 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1176 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1177 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1178 };
1179 };
1180
1181 spi0 {
1182 pinctrl_spi0: spi0-0 {
1183 atmel,pins =
1184 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1185 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1186 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1187 >;
1188 };
1189 };
1190
1191 usart2 {
1192 pinctrl_usart2: usart2-0 {
1193 atmel,pins =
1194 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1195 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1196 >;
1197 };
1198 pinctrl_usart2_rts: usart2_rts-0 {
1199 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1200 };
1201 pinctrl_usart2_cts: usart2_cts-0 {
1202 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1203 };
1204 };
1205
1206 usart3 {
1207 pinctrl_usart3: usart3-0 {
1208 atmel,pins =
1209 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1210 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1211 >;
1212 };
1213 };
1214
1215 usart4 {
1216 pinctrl_usart4: usart4-0 {
1217 atmel,pins =
1218 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1219 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1220 >;
1221 };
1222 pinctrl_usart4_rts: usart4_rts-0 {
1223 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1224 };
1225 pinctrl_usart4_cts: usart4_cts-0 {
1226 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1227 };
1228 };
1229 };
1230
1231 aic: interrupt-controller@fc06e000 {
1232 #interrupt-cells = <3>;
1233 compatible = "atmel,sama5d4-aic";
1234 interrupt-controller;
1235 reg = <0xfc06e000 0x200>;
1236 atmel,external-irqs = <56>;
1237 };
1238 };
1239 };
1240};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 249f65be2a50..f863a10cb1b2 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -21,6 +21,7 @@
21 compatible = "arm,cortex-a8"; 21 compatible = "arm,cortex-a8";
22 device_type = "cpu"; 22 device_type = "cpu";
23 reg = <0x0>; 23 reg = <0x0>;
24 clock-frequency = <800000000>;
24 }; 25 };
25 }; 26 };
26 27
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 18662aec2ec4..30ef97e99dc5 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -66,7 +66,7 @@
66 }; 66 };
67 67
68 vmmc_sdhi0: regulator@2 { 68 vmmc_sdhi0: regulator@2 {
69 compatible = "regulator-fixed"; 69 compatible = "regulator-fixed";
70 regulator-name = "SDHI0 Vcc"; 70 regulator-name = "SDHI0 Vcc";
71 regulator-min-microvolt = <3300000>; 71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>;
@@ -75,7 +75,7 @@
75 }; 75 };
76 76
77 vmmc_sdhi2: regulator@3 { 77 vmmc_sdhi2: regulator@3 {
78 compatible = "regulator-fixed"; 78 compatible = "regulator-fixed";
79 regulator-name = "SDHI2 Vcc"; 79 regulator-name = "SDHI2 Vcc";
80 regulator-min-microvolt = <3300000>; 80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>;
@@ -173,6 +173,10 @@
173 }; 173 };
174}; 174};
175 175
176&cmt1 {
177 status = "ok";
178};
179
176&i2c0 { 180&i2c0 {
177 status = "okay"; 181 status = "okay";
178 as3711@40 { 182 as3711@40 {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 910b79079d5a..030a5920312f 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -14,6 +14,7 @@
14 14
15/ { 15/ {
16 compatible = "renesas,sh73a0"; 16 compatible = "renesas,sh73a0";
17 interrupt-parent = <&gic>;
17 18
18 cpus { 19 cpus {
19 #address-cells = <1>; 20 #address-cells = <1>;
@@ -23,11 +24,13 @@
23 device_type = "cpu"; 24 device_type = "cpu";
24 compatible = "arm,cortex-a9"; 25 compatible = "arm,cortex-a9";
25 reg = <0>; 26 reg = <0>;
27 clock-frequency = <1196000000>;
26 }; 28 };
27 cpu@1 { 29 cpu@1 {
28 device_type = "cpu"; 30 device_type = "cpu";
29 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
30 reg = <1>; 32 reg = <1>;
33 clock-frequency = <1196000000>;
31 }; 34 };
32 }; 35 };
33 36
@@ -45,6 +48,16 @@
45 <0 56 IRQ_TYPE_LEVEL_HIGH>; 48 <0 56 IRQ_TYPE_LEVEL_HIGH>;
46 }; 49 };
47 50
51 cmt1: timer@e6138000 {
52 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
53 reg = <0xe6138000 0x200>;
54 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
55
56 renesas,channels-mask = <0x3f>;
57
58 status = "disabled";
59 };
60
48 irqpin0: irqpin@e6900000 { 61 irqpin0: irqpin@e6900000 {
49 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; 62 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
50 #interrupt-cells = <2>; 63 #interrupt-cells = <2>;
@@ -54,7 +67,6 @@
54 <0xe6900020 1>, 67 <0xe6900020 1>,
55 <0xe6900040 1>, 68 <0xe6900040 1>,
56 <0xe6900060 1>; 69 <0xe6900060 1>;
57 interrupt-parent = <&gic>;
58 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH 70 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
59 0 2 IRQ_TYPE_LEVEL_HIGH 71 0 2 IRQ_TYPE_LEVEL_HIGH
60 0 3 IRQ_TYPE_LEVEL_HIGH 72 0 3 IRQ_TYPE_LEVEL_HIGH
@@ -74,7 +86,6 @@
74 <0xe6900024 1>, 86 <0xe6900024 1>,
75 <0xe6900044 1>, 87 <0xe6900044 1>,
76 <0xe6900064 1>; 88 <0xe6900064 1>;
77 interrupt-parent = <&gic>;
78 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH 89 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
79 0 10 IRQ_TYPE_LEVEL_HIGH 90 0 10 IRQ_TYPE_LEVEL_HIGH
80 0 11 IRQ_TYPE_LEVEL_HIGH 91 0 11 IRQ_TYPE_LEVEL_HIGH
@@ -95,7 +106,6 @@
95 <0xe6900028 1>, 106 <0xe6900028 1>,
96 <0xe6900048 1>, 107 <0xe6900048 1>,
97 <0xe6900068 1>; 108 <0xe6900068 1>;
98 interrupt-parent = <&gic>;
99 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH 109 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
100 0 18 IRQ_TYPE_LEVEL_HIGH 110 0 18 IRQ_TYPE_LEVEL_HIGH
101 0 19 IRQ_TYPE_LEVEL_HIGH 111 0 19 IRQ_TYPE_LEVEL_HIGH
@@ -115,7 +125,6 @@
115 <0xe690002c 1>, 125 <0xe690002c 1>,
116 <0xe690004c 1>, 126 <0xe690004c 1>,
117 <0xe690006c 1>; 127 <0xe690006c 1>;
118 interrupt-parent = <&gic>;
119 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH 128 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
120 0 26 IRQ_TYPE_LEVEL_HIGH 129 0 26 IRQ_TYPE_LEVEL_HIGH
121 0 27 IRQ_TYPE_LEVEL_HIGH 130 0 27 IRQ_TYPE_LEVEL_HIGH
@@ -131,7 +140,6 @@
131 #size-cells = <0>; 140 #size-cells = <0>;
132 compatible = "renesas,rmobile-iic"; 141 compatible = "renesas,rmobile-iic";
133 reg = <0xe6820000 0x425>; 142 reg = <0xe6820000 0x425>;
134 interrupt-parent = <&gic>;
135 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH 143 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
136 0 168 IRQ_TYPE_LEVEL_HIGH 144 0 168 IRQ_TYPE_LEVEL_HIGH
137 0 169 IRQ_TYPE_LEVEL_HIGH 145 0 169 IRQ_TYPE_LEVEL_HIGH
@@ -144,7 +152,6 @@
144 #size-cells = <0>; 152 #size-cells = <0>;
145 compatible = "renesas,rmobile-iic"; 153 compatible = "renesas,rmobile-iic";
146 reg = <0xe6822000 0x425>; 154 reg = <0xe6822000 0x425>;
147 interrupt-parent = <&gic>;
148 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH 155 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
149 0 52 IRQ_TYPE_LEVEL_HIGH 156 0 52 IRQ_TYPE_LEVEL_HIGH
150 0 53 IRQ_TYPE_LEVEL_HIGH 157 0 53 IRQ_TYPE_LEVEL_HIGH
@@ -157,7 +164,6 @@
157 #size-cells = <0>; 164 #size-cells = <0>;
158 compatible = "renesas,rmobile-iic"; 165 compatible = "renesas,rmobile-iic";
159 reg = <0xe6824000 0x425>; 166 reg = <0xe6824000 0x425>;
160 interrupt-parent = <&gic>;
161 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH 167 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
162 0 172 IRQ_TYPE_LEVEL_HIGH 168 0 172 IRQ_TYPE_LEVEL_HIGH
163 0 173 IRQ_TYPE_LEVEL_HIGH 169 0 173 IRQ_TYPE_LEVEL_HIGH
@@ -170,7 +176,6 @@
170 #size-cells = <0>; 176 #size-cells = <0>;
171 compatible = "renesas,rmobile-iic"; 177 compatible = "renesas,rmobile-iic";
172 reg = <0xe6826000 0x425>; 178 reg = <0xe6826000 0x425>;
173 interrupt-parent = <&gic>;
174 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH 179 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
175 0 184 IRQ_TYPE_LEVEL_HIGH 180 0 184 IRQ_TYPE_LEVEL_HIGH
176 0 185 IRQ_TYPE_LEVEL_HIGH 181 0 185 IRQ_TYPE_LEVEL_HIGH
@@ -183,7 +188,6 @@
183 #size-cells = <0>; 188 #size-cells = <0>;
184 compatible = "renesas,rmobile-iic"; 189 compatible = "renesas,rmobile-iic";
185 reg = <0xe6828000 0x425>; 190 reg = <0xe6828000 0x425>;
186 interrupt-parent = <&gic>;
187 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH 191 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
188 0 188 IRQ_TYPE_LEVEL_HIGH 192 0 188 IRQ_TYPE_LEVEL_HIGH
189 0 189 IRQ_TYPE_LEVEL_HIGH 193 0 189 IRQ_TYPE_LEVEL_HIGH
@@ -194,7 +198,6 @@
194 mmcif: mmc@e6bd0000 { 198 mmcif: mmc@e6bd0000 {
195 compatible = "renesas,sh-mmcif"; 199 compatible = "renesas,sh-mmcif";
196 reg = <0xe6bd0000 0x100>; 200 reg = <0xe6bd0000 0x100>;
197 interrupt-parent = <&gic>;
198 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 201 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
199 0 141 IRQ_TYPE_LEVEL_HIGH>; 202 0 141 IRQ_TYPE_LEVEL_HIGH>;
200 reg-io-width = <4>; 203 reg-io-width = <4>;
@@ -204,7 +207,6 @@
204 sdhi0: sd@ee100000 { 207 sdhi0: sd@ee100000 {
205 compatible = "renesas,sdhi-sh73a0"; 208 compatible = "renesas,sdhi-sh73a0";
206 reg = <0xee100000 0x100>; 209 reg = <0xee100000 0x100>;
207 interrupt-parent = <&gic>;
208 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH 210 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
209 0 84 IRQ_TYPE_LEVEL_HIGH 211 0 84 IRQ_TYPE_LEVEL_HIGH
210 0 85 IRQ_TYPE_LEVEL_HIGH>; 212 0 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -216,7 +218,6 @@
216 sdhi1: sd@ee120000 { 218 sdhi1: sd@ee120000 {
217 compatible = "renesas,sdhi-sh73a0"; 219 compatible = "renesas,sdhi-sh73a0";
218 reg = <0xee120000 0x100>; 220 reg = <0xee120000 0x100>;
219 interrupt-parent = <&gic>;
220 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 221 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
221 0 89 IRQ_TYPE_LEVEL_HIGH>; 222 0 89 IRQ_TYPE_LEVEL_HIGH>;
222 toshiba,mmc-wrprotect-disable; 223 toshiba,mmc-wrprotect-disable;
@@ -227,7 +228,6 @@
227 sdhi2: sd@ee140000 { 228 sdhi2: sd@ee140000 {
228 compatible = "renesas,sdhi-sh73a0"; 229 compatible = "renesas,sdhi-sh73a0";
229 reg = <0xee140000 0x100>; 230 reg = <0xee140000 0x100>;
230 interrupt-parent = <&gic>;
231 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 231 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
232 0 105 IRQ_TYPE_LEVEL_HIGH>; 232 0 105 IRQ_TYPE_LEVEL_HIGH>;
233 toshiba,mmc-wrprotect-disable; 233 toshiba,mmc-wrprotect-disable;
@@ -238,7 +238,6 @@
238 scifa0: serial@e6c40000 { 238 scifa0: serial@e6c40000 {
239 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 239 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
240 reg = <0xe6c40000 0x100>; 240 reg = <0xe6c40000 0x100>;
241 interrupt-parent = <&gic>;
242 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
243 status = "disabled"; 242 status = "disabled";
244 }; 243 };
@@ -246,7 +245,6 @@
246 scifa1: serial@e6c50000 { 245 scifa1: serial@e6c50000 {
247 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 246 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
248 reg = <0xe6c50000 0x100>; 247 reg = <0xe6c50000 0x100>;
249 interrupt-parent = <&gic>;
250 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 248 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled"; 249 status = "disabled";
252 }; 250 };
@@ -254,7 +252,6 @@
254 scifa2: serial@e6c60000 { 252 scifa2: serial@e6c60000 {
255 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 253 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
256 reg = <0xe6c60000 0x100>; 254 reg = <0xe6c60000 0x100>;
257 interrupt-parent = <&gic>;
258 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 255 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
259 status = "disabled"; 256 status = "disabled";
260 }; 257 };
@@ -262,7 +259,6 @@
262 scifa3: serial@e6c70000 { 259 scifa3: serial@e6c70000 {
263 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 260 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
264 reg = <0xe6c70000 0x100>; 261 reg = <0xe6c70000 0x100>;
265 interrupt-parent = <&gic>;
266 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
267 status = "disabled"; 263 status = "disabled";
268 }; 264 };
@@ -270,7 +266,6 @@
270 scifa4: serial@e6c80000 { 266 scifa4: serial@e6c80000 {
271 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 267 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
272 reg = <0xe6c80000 0x100>; 268 reg = <0xe6c80000 0x100>;
273 interrupt-parent = <&gic>;
274 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 269 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
275 status = "disabled"; 270 status = "disabled";
276 }; 271 };
@@ -278,7 +273,6 @@
278 scifa5: serial@e6cb0000 { 273 scifa5: serial@e6cb0000 {
279 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 274 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
280 reg = <0xe6cb0000 0x100>; 275 reg = <0xe6cb0000 0x100>;
281 interrupt-parent = <&gic>;
282 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 276 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
283 status = "disabled"; 277 status = "disabled";
284 }; 278 };
@@ -286,7 +280,6 @@
286 scifa6: serial@e6cc0000 { 280 scifa6: serial@e6cc0000 {
287 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 281 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
288 reg = <0xe6cc0000 0x100>; 282 reg = <0xe6cc0000 0x100>;
289 interrupt-parent = <&gic>;
290 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 283 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
291 status = "disabled"; 284 status = "disabled";
292 }; 285 };
@@ -294,7 +287,6 @@
294 scifa7: serial@e6cd0000 { 287 scifa7: serial@e6cd0000 {
295 compatible = "renesas,scifa-sh73a0", "renesas,scifa"; 288 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
296 reg = <0xe6cd0000 0x100>; 289 reg = <0xe6cd0000 0x100>;
297 interrupt-parent = <&gic>;
298 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 290 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
299 status = "disabled"; 291 status = "disabled";
300 }; 292 };
@@ -302,7 +294,6 @@
302 scifb8: serial@e6c30000 { 294 scifb8: serial@e6c30000 {
303 compatible = "renesas,scifb-sh73a0", "renesas,scifb"; 295 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
304 reg = <0xe6c30000 0x100>; 296 reg = <0xe6c30000 0x100>;
305 interrupt-parent = <&gic>;
306 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 297 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
307 status = "disabled"; 298 status = "disabled";
308 }; 299 };
@@ -328,7 +319,6 @@
328 #sound-dai-cells = <1>; 319 #sound-dai-cells = <1>;
329 compatible = "renesas,sh_fsi2"; 320 compatible = "renesas,sh_fsi2";
330 reg = <0xec230000 0x400>; 321 reg = <0xec230000 0x400>;
331 interrupt-parent = <&gic>;
332 interrupts = <0 146 0x4>; 322 interrupts = <0 146 0x4>;
333 status = "disabled"; 323 status = "disabled";
334 }; 324 };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4d77ad690ed5..45fce2cf6fed 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -607,6 +607,17 @@
607 }; 607 };
608 }; 608 };
609 609
610 sdr: sdr@ffc25000 {
611 compatible = "syscon";
612 reg = <0xffc25000 0x1000>;
613 };
614
615 sdramedac {
616 compatible = "altr,sdram-edac";
617 altr,sdr-syscon = <&sdr>;
618 interrupts = <0 39 4>;
619 };
620
610 L2: l2-cache@fffef000 { 621 L2: l2-cache@fffef000 {
611 compatible = "arm,pl310-cache"; 622 compatible = "arm,pl310-cache";
612 reg = <0xfffef000 0x1000>; 623 reg = <0xfffef000 0x1000>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 12d1c2ccaf5b..03e8268ae219 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -15,6 +15,8 @@
15 */ 15 */
16 16
17/dts-v1/; 17/dts-v1/;
18/* First 4KB has trampoline code for secondary cores. */
19/memreserve/ 0x00000000 0x0001000;
18#include "socfpga.dtsi" 20#include "socfpga.dtsi"
19 21
20/ { 22/ {
@@ -29,13 +31,10 @@
29 31
30 dwmmc0@ff704000 { 32 dwmmc0@ff704000 {
31 num-slots = <1>; 33 num-slots = <1>;
32 supports-highspeed;
33 broken-cd; 34 broken-cd;
34 35 bus-width = <4>;
35 slot@0 { 36 cap-mmc-highspeed;
36 reg = <0>; 37 cap-sd-highspeed;
37 bus-width = <4>;
38 };
39 }; 38 };
40 39
41 sysmgr@ffd08000 { 40 sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index d532d171e391..27d551c384d0 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,13 +37,6 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 aliases {
42 /* this allow the ethaddr uboot environmnet variable contents
43 * to be added to the gmac1 device tree blob.
44 */
45 ethernet0 = &gmac1;
46 };
47}; 40};
48 41
49&gmac1 { 42&gmac1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index bf511828729f..28c05e7a31c9 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -16,6 +16,8 @@
16 */ 16 */
17 17
18/dts-v1/; 18/dts-v1/;
19/* First 4KB has trampoline code for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
19#include "socfpga.dtsi" 21#include "socfpga.dtsi"
20 22
21/ { 23/ {
@@ -28,15 +30,12 @@
28 }; 30 };
29 }; 31 };
30 32
31 dwmmc0@ff704000 { 33 mmc0: dwmmc0@ff704000 {
32 num-slots = <1>; 34 num-slots = <1>;
33 supports-highspeed;
34 broken-cd; 35 broken-cd;
35 36 bus-width = <4>;
36 slot@0 { 37 cap-mmc-highspeed;
37 reg = <0>; 38 cap-sd-highspeed;
38 bus-width = <4>;
39 };
40 }; 39 };
41 40
42 ethernet@ff702000 { 41 ethernet@ff702000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 45de1514af0a..d7296a5f750c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -68,6 +68,10 @@
68 }; 68 };
69}; 69};
70 70
71&mmc0 {
72 cd-gpios = <&gpio1 18 0>;
73};
74
71&usb1 { 75&usb1 {
72 status = "okay"; 76 status = "okay";
73}; 77};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 09792b411110..f9345e02ca49 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -43,13 +43,10 @@
43 43
44 dwmmc0@ff704000 { 44 dwmmc0@ff704000 {
45 num-slots = <1>; 45 num-slots = <1>;
46 supports-highspeed;
47 broken-cd; 46 broken-cd;
48 47 bus-width = <4>;
49 slot@0 { 48 cap-mmc-highspeed;
50 reg = <0>; 49 cap-sd-highspeed;
51 bus-width = <4>;
52 };
53 }; 50 };
54 51
55 ethernet@ff700000 { 52 ethernet@ff700000 {
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index fa5f2bb5f106..9d342920695a 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -85,7 +85,8 @@
85 85
86 pcie0: pcie@b1000000 { 86 pcie0: pcie@b1000000 {
87 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 87 compatible = "st,spear1340-pcie", "snps,dw-pcie";
88 reg = <0xb1000000 0x4000>; 88 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
89 reg-names = "dbi", "config";
89 interrupts = <0 68 0x4>; 90 interrupts = <0 68 0x4>;
90 interrupt-map-mask = <0 0 0 0>; 91 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0x0 0 &gic 0 68 0x4>; 92 interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -95,15 +96,15 @@
95 #address-cells = <3>; 96 #address-cells = <3>;
96 #size-cells = <2>; 97 #size-cells = <2>;
97 device_type = "pci"; 98 device_type = "pci";
98 ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ 99 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
99 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
100 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 100 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
101 status = "disabled"; 101 status = "disabled";
102 }; 102 };
103 103
104 pcie1: pcie@b1800000 { 104 pcie1: pcie@b1800000 {
105 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 105 compatible = "st,spear1340-pcie", "snps,dw-pcie";
106 reg = <0xb1800000 0x4000>; 106 reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
107 reg-names = "dbi", "config";
107 interrupts = <0 69 0x4>; 108 interrupts = <0 69 0x4>;
108 interrupt-map-mask = <0 0 0 0>; 109 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0x0 0 &gic 0 69 0x4>; 110 interrupt-map = <0x0 0 &gic 0 69 0x4>;
@@ -113,15 +114,15 @@
113 #address-cells = <3>; 114 #address-cells = <3>;
114 #size-cells = <2>; 115 #size-cells = <2>;
115 device_type = "pci"; 116 device_type = "pci";
116 ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ 117 ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
117 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
118 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ 118 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
119 status = "disabled"; 119 status = "disabled";
120 }; 120 };
121 121
122 pcie2: pcie@b4000000 { 122 pcie2: pcie@b4000000 {
123 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 123 compatible = "st,spear1340-pcie", "snps,dw-pcie";
124 reg = <0xb4000000 0x4000>; 124 reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
125 reg-names = "dbi", "config";
125 interrupts = <0 70 0x4>; 126 interrupts = <0 70 0x4>;
126 interrupt-map-mask = <0 0 0 0>; 127 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0x0 0 &gic 0 70 0x4>; 128 interrupt-map = <0x0 0 &gic 0 70 0x4>;
@@ -131,8 +132,7 @@
131 #address-cells = <3>; 132 #address-cells = <3>;
132 #size-cells = <2>; 133 #size-cells = <2>;
133 device_type = "pci"; 134 device_type = "pci";
134 ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ 135 ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
135 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
136 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 136 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
137 status = "disabled"; 137 status = "disabled";
138 }; 138 };
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index e71df0f2cb52..13e1aa33daa2 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -50,7 +50,8 @@
50 50
51 pcie0: pcie@b1000000 { 51 pcie0: pcie@b1000000 {
52 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 52 compatible = "st,spear1340-pcie", "snps,dw-pcie";
53 reg = <0xb1000000 0x4000>; 53 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
54 reg-names = "dbi", "config";
54 interrupts = <0 68 0x4>; 55 interrupts = <0 68 0x4>;
55 interrupt-map-mask = <0 0 0 0>; 56 interrupt-map-mask = <0 0 0 0>;
56 interrupt-map = <0x0 0 &gic 0 68 0x4>; 57 interrupt-map = <0x0 0 &gic 0 68 0x4>;
@@ -60,8 +61,7 @@
60 #address-cells = <3>; 61 #address-cells = <3>;
61 #size-cells = <2>; 62 #size-cells = <2>;
62 device_type = "pci"; 63 device_type = "pci";
63 ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ 64 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
64 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
65 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 65 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
66 status = "disabled"; 66 status = "disabled";
67 }; 67 };
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 459cb6377764..380f914b226d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -339,12 +339,22 @@
339 #size-cells = <1>; 339 #size-cells = <1>;
340 ranges; 340 ranges;
341 341
342 dma: dma-controller@01c02000 {
343 compatible = "allwinner,sun4i-a10-dma";
344 reg = <0x01c02000 0x1000>;
345 interrupts = <27>;
346 clocks = <&ahb_gates 6>;
347 #dma-cells = <2>;
348 };
349
342 spi0: spi@01c05000 { 350 spi0: spi@01c05000 {
343 compatible = "allwinner,sun4i-a10-spi"; 351 compatible = "allwinner,sun4i-a10-spi";
344 reg = <0x01c05000 0x1000>; 352 reg = <0x01c05000 0x1000>;
345 interrupts = <10>; 353 interrupts = <10>;
346 clocks = <&ahb_gates 20>, <&spi0_clk>; 354 clocks = <&ahb_gates 20>, <&spi0_clk>;
347 clock-names = "ahb", "mod"; 355 clock-names = "ahb", "mod";
356 dmas = <&dma 1 27>, <&dma 1 26>;
357 dma-names = "rx", "tx";
348 status = "disabled"; 358 status = "disabled";
349 #address-cells = <1>; 359 #address-cells = <1>;
350 #size-cells = <0>; 360 #size-cells = <0>;
@@ -356,6 +366,8 @@
356 interrupts = <11>; 366 interrupts = <11>;
357 clocks = <&ahb_gates 21>, <&spi1_clk>; 367 clocks = <&ahb_gates 21>, <&spi1_clk>;
358 clock-names = "ahb", "mod"; 368 clock-names = "ahb", "mod";
369 dmas = <&dma 1 9>, <&dma 1 8>;
370 dma-names = "rx", "tx";
359 status = "disabled"; 371 status = "disabled";
360 #address-cells = <1>; 372 #address-cells = <1>;
361 #size-cells = <0>; 373 #size-cells = <0>;
@@ -451,6 +463,8 @@
451 interrupts = <12>; 463 interrupts = <12>;
452 clocks = <&ahb_gates 22>, <&spi2_clk>; 464 clocks = <&ahb_gates 22>, <&spi2_clk>;
453 clock-names = "ahb", "mod"; 465 clock-names = "ahb", "mod";
466 dmas = <&dma 1 29>, <&dma 1 28>;
467 dma-names = "rx", "tx";
454 status = "disabled"; 468 status = "disabled";
455 #address-cells = <1>; 469 #address-cells = <1>;
456 #size-cells = <0>; 470 #size-cells = <0>;
@@ -490,6 +504,8 @@
490 interrupts = <50>; 504 interrupts = <50>;
491 clocks = <&ahb_gates 23>, <&spi3_clk>; 505 clocks = <&ahb_gates 23>, <&spi3_clk>;
492 clock-names = "ahb", "mod"; 506 clock-names = "ahb", "mod";
507 dmas = <&dma 1 31>, <&dma 1 30>;
508 dma-names = "rx", "tx";
493 status = "disabled"; 509 status = "disabled";
494 #address-cells = <1>; 510 #address-cells = <1>;
495 #size-cells = <0>; 511 #size-cells = <0>;
@@ -749,7 +765,6 @@
749 reg = <0x01c2ac00 0x400>; 765 reg = <0x01c2ac00 0x400>;
750 interrupts = <7>; 766 interrupts = <7>;
751 clocks = <&apb1_gates 0>; 767 clocks = <&apb1_gates 0>;
752 clock-frequency = <100000>;
753 status = "disabled"; 768 status = "disabled";
754 #address-cells = <1>; 769 #address-cells = <1>;
755 #size-cells = <0>; 770 #size-cells = <0>;
@@ -760,7 +775,6 @@
760 reg = <0x01c2b000 0x400>; 775 reg = <0x01c2b000 0x400>;
761 interrupts = <8>; 776 interrupts = <8>;
762 clocks = <&apb1_gates 1>; 777 clocks = <&apb1_gates 1>;
763 clock-frequency = <100000>;
764 status = "disabled"; 778 status = "disabled";
765 #address-cells = <1>; 779 #address-cells = <1>;
766 #size-cells = <0>; 780 #size-cells = <0>;
@@ -771,7 +785,6 @@
771 reg = <0x01c2b400 0x400>; 785 reg = <0x01c2b400 0x400>;
772 interrupts = <9>; 786 interrupts = <9>;
773 clocks = <&apb1_gates 2>; 787 clocks = <&apb1_gates 2>;
774 clock-frequency = <100000>;
775 status = "disabled"; 788 status = "disabled";
776 #address-cells = <1>; 789 #address-cells = <1>;
777 #size-cells = <0>; 790 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 24b0ad3a7c07..d73a2287b37a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -300,12 +300,22 @@
300 #size-cells = <1>; 300 #size-cells = <1>;
301 ranges; 301 ranges;
302 302
303 dma: dma-controller@01c02000 {
304 compatible = "allwinner,sun4i-a10-dma";
305 reg = <0x01c02000 0x1000>;
306 interrupts = <27>;
307 clocks = <&ahb_gates 6>;
308 #dma-cells = <2>;
309 };
310
303 spi0: spi@01c05000 { 311 spi0: spi@01c05000 {
304 compatible = "allwinner,sun4i-a10-spi"; 312 compatible = "allwinner,sun4i-a10-spi";
305 reg = <0x01c05000 0x1000>; 313 reg = <0x01c05000 0x1000>;
306 interrupts = <10>; 314 interrupts = <10>;
307 clocks = <&ahb_gates 20>, <&spi0_clk>; 315 clocks = <&ahb_gates 20>, <&spi0_clk>;
308 clock-names = "ahb", "mod"; 316 clock-names = "ahb", "mod";
317 dmas = <&dma 1 27>, <&dma 1 26>;
318 dma-names = "rx", "tx";
309 status = "disabled"; 319 status = "disabled";
310 #address-cells = <1>; 320 #address-cells = <1>;
311 #size-cells = <0>; 321 #size-cells = <0>;
@@ -317,6 +327,8 @@
317 interrupts = <11>; 327 interrupts = <11>;
318 clocks = <&ahb_gates 21>, <&spi1_clk>; 328 clocks = <&ahb_gates 21>, <&spi1_clk>;
319 clock-names = "ahb", "mod"; 329 clock-names = "ahb", "mod";
330 dmas = <&dma 1 9>, <&dma 1 8>;
331 dma-names = "rx", "tx";
320 status = "disabled"; 332 status = "disabled";
321 #address-cells = <1>; 333 #address-cells = <1>;
322 #size-cells = <0>; 334 #size-cells = <0>;
@@ -403,6 +415,8 @@
403 interrupts = <12>; 415 interrupts = <12>;
404 clocks = <&ahb_gates 22>, <&spi2_clk>; 416 clocks = <&ahb_gates 22>, <&spi2_clk>;
405 clock-names = "ahb", "mod"; 417 clock-names = "ahb", "mod";
418 dmas = <&dma 1 29>, <&dma 1 28>;
419 dma-names = "rx", "tx";
406 status = "disabled"; 420 status = "disabled";
407 #address-cells = <1>; 421 #address-cells = <1>;
408 #size-cells = <0>; 422 #size-cells = <0>;
@@ -564,7 +578,6 @@
564 reg = <0x01c2ac00 0x400>; 578 reg = <0x01c2ac00 0x400>;
565 interrupts = <7>; 579 interrupts = <7>;
566 clocks = <&apb1_gates 0>; 580 clocks = <&apb1_gates 0>;
567 clock-frequency = <100000>;
568 status = "disabled"; 581 status = "disabled";
569 }; 582 };
570 583
@@ -575,7 +588,6 @@
575 reg = <0x01c2b000 0x400>; 588 reg = <0x01c2b000 0x400>;
576 interrupts = <8>; 589 interrupts = <8>;
577 clocks = <&apb1_gates 1>; 590 clocks = <&apb1_gates 1>;
578 clock-frequency = <100000>;
579 status = "disabled"; 591 status = "disabled";
580 }; 592 };
581 593
@@ -586,7 +598,6 @@
586 reg = <0x01c2b400 0x400>; 598 reg = <0x01c2b400 0x400>;
587 interrupts = <9>; 599 interrupts = <9>;
588 clocks = <&apb1_gates 2>; 600 clocks = <&apb1_gates 2>;
589 clock-frequency = <100000>;
590 status = "disabled"; 601 status = "disabled";
591 }; 602 };
592 603
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
new file mode 100644
index 000000000000..8b3cd0907b32
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -0,0 +1,130 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai <wens@csie.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49/include/ "sun5i-a13.dtsi"
50/include/ "sunxi-common-regulators.dtsi"
51
52/ {
53 model = "HSG H702";
54 compatible = "hsg,h702", "allwinner,sun5i-a13";
55
56 soc@01c00000 {
57 mmc0: mmc@01c0f000 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
60 vmmc-supply = <&reg_vcc3v3>;
61 bus-width = <4>;
62 cd-gpios = <&pio 6 0 0>; /* PG0 */
63 cd-inverted;
64 status = "okay";
65 };
66
67 usbphy: phy@01c13400 {
68 /*
69 * There doesn't seem to be a GPIO for controlling
70 * usb1 vbus, despite the fex file saying otherwise.
71 */
72 usb1_vbus-supply = <&reg_vcc5v0>;
73 status = "okay";
74 };
75
76 ehci0: usb@01c14000 {
77 status = "okay";
78 };
79
80 ohci0: usb@01c14400 {
81 status = "okay";
82 };
83
84 pinctrl@01c20800 {
85 mmc0_cd_pin_h702: mmc0_cd_pin@0 {
86 allwinner,pins = "PG0";
87 allwinner,function = "gpio_in";
88 allwinner,drive = <0>;
89 allwinner,pull = <1>;
90 };
91 };
92
93 uart1: serial@01c28400 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&uart1_pins_b>;
96 status = "okay";
97 };
98
99 i2c0: i2c@01c2ac00 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&i2c0_pins_a>;
102 status = "okay";
103
104 axp209: pmic@34 {
105 compatible = "x-powers,axp209";
106 reg = <0x34>;
107 interrupts = <0>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
110 };
111 };
112
113 i2c1: i2c@01c2b000 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c1_pins_a>;
116 status = "okay";
117
118 pcf8563: rtc@51 {
119 compatible = "nxp,pcf8563";
120 reg = <0x51>;
121 };
122 };
123
124 i2c2: i2c@01c2b400 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&i2c2_pins_a>;
127 status = "okay";
128 };
129 };
130};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index bf86e65dd167..c4b5d7825b9f 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -298,12 +298,22 @@
298 #size-cells = <1>; 298 #size-cells = <1>;
299 ranges; 299 ranges;
300 300
301 dma: dma-controller@01c02000 {
302 compatible = "allwinner,sun4i-a10-dma";
303 reg = <0x01c02000 0x1000>;
304 interrupts = <27>;
305 clocks = <&ahb_gates 6>;
306 #dma-cells = <2>;
307 };
308
301 spi0: spi@01c05000 { 309 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi"; 310 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>; 311 reg = <0x01c05000 0x1000>;
304 interrupts = <10>; 312 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>; 313 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod"; 314 clock-names = "ahb", "mod";
315 dmas = <&dma 1 27>, <&dma 1 26>;
316 dma-names = "rx", "tx";
307 status = "disabled"; 317 status = "disabled";
308 #address-cells = <1>; 318 #address-cells = <1>;
309 #size-cells = <0>; 319 #size-cells = <0>;
@@ -315,6 +325,8 @@
315 interrupts = <11>; 325 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>; 326 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod"; 327 clock-names = "ahb", "mod";
328 dmas = <&dma 1 9>, <&dma 1 8>;
329 dma-names = "rx", "tx";
318 status = "disabled"; 330 status = "disabled";
319 #address-cells = <1>; 331 #address-cells = <1>;
320 #size-cells = <0>; 332 #size-cells = <0>;
@@ -376,6 +388,8 @@
376 interrupts = <12>; 388 interrupts = <12>;
377 clocks = <&ahb_gates 22>, <&spi2_clk>; 389 clocks = <&ahb_gates 22>, <&spi2_clk>;
378 clock-names = "ahb", "mod"; 390 clock-names = "ahb", "mod";
391 dmas = <&dma 1 29>, <&dma 1 28>;
392 dma-names = "rx", "tx";
379 status = "disabled"; 393 status = "disabled";
380 #address-cells = <1>; 394 #address-cells = <1>;
381 #size-cells = <0>; 395 #size-cells = <0>;
@@ -490,7 +504,6 @@
490 reg = <0x01c2ac00 0x400>; 504 reg = <0x01c2ac00 0x400>;
491 interrupts = <7>; 505 interrupts = <7>;
492 clocks = <&apb1_gates 0>; 506 clocks = <&apb1_gates 0>;
493 clock-frequency = <100000>;
494 status = "disabled"; 507 status = "disabled";
495 #address-cells = <1>; 508 #address-cells = <1>;
496 #size-cells = <0>; 509 #size-cells = <0>;
@@ -501,7 +514,6 @@
501 reg = <0x01c2b000 0x400>; 514 reg = <0x01c2b000 0x400>;
502 interrupts = <8>; 515 interrupts = <8>;
503 clocks = <&apb1_gates 1>; 516 clocks = <&apb1_gates 1>;
504 clock-frequency = <100000>;
505 status = "disabled"; 517 status = "disabled";
506 #address-cells = <1>; 518 #address-cells = <1>;
507 #size-cells = <0>; 519 #size-cells = <0>;
@@ -512,7 +524,6 @@
512 reg = <0x01c2b400 0x400>; 524 reg = <0x01c2b400 0x400>;
513 interrupts = <9>; 525 interrupts = <9>;
514 clocks = <&apb1_gates 2>; 526 clocks = <&apb1_gates 2>;
515 clock-frequency = <100000>;
516 status = "disabled"; 527 status = "disabled";
517 #address-cells = <1>; 528 #address-cells = <1>;
518 #size-cells = <0>; 529 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index e06fbfc55bb7..543f895d18d3 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This library is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/include/ "skeleton.dtsi" 50/include/ "skeleton.dtsi"
@@ -657,7 +693,6 @@
657 reg = <0x01c2ac00 0x400>; 693 reg = <0x01c2ac00 0x400>;
658 interrupts = <0 6 4>; 694 interrupts = <0 6 4>;
659 clocks = <&apb2_gates 0>; 695 clocks = <&apb2_gates 0>;
660 clock-frequency = <100000>;
661 resets = <&apb2_rst 0>; 696 resets = <&apb2_rst 0>;
662 status = "disabled"; 697 status = "disabled";
663 #address-cells = <1>; 698 #address-cells = <1>;
@@ -669,7 +704,6 @@
669 reg = <0x01c2b000 0x400>; 704 reg = <0x01c2b000 0x400>;
670 interrupts = <0 7 4>; 705 interrupts = <0 7 4>;
671 clocks = <&apb2_gates 1>; 706 clocks = <&apb2_gates 1>;
672 clock-frequency = <100000>;
673 resets = <&apb2_rst 1>; 707 resets = <&apb2_rst 1>;
674 status = "disabled"; 708 status = "disabled";
675 #address-cells = <1>; 709 #address-cells = <1>;
@@ -681,7 +715,6 @@
681 reg = <0x01c2b400 0x400>; 715 reg = <0x01c2b400 0x400>;
682 interrupts = <0 8 4>; 716 interrupts = <0 8 4>;
683 clocks = <&apb2_gates 2>; 717 clocks = <&apb2_gates 2>;
684 clock-frequency = <100000>;
685 resets = <&apb2_rst 2>; 718 resets = <&apb2_rst 2>;
686 status = "disabled"; 719 status = "disabled";
687 #address-cells = <1>; 720 #address-cells = <1>;
@@ -693,7 +726,6 @@
693 reg = <0x01c2b800 0x400>; 726 reg = <0x01c2b800 0x400>;
694 interrupts = <0 9 4>; 727 interrupts = <0 9 4>;
695 clocks = <&apb2_gates 3>; 728 clocks = <&apb2_gates 3>;
696 clock-frequency = <100000>;
697 resets = <&apb2_rst 3>; 729 resets = <&apb2_rst 3>;
698 status = "disabled"; 730 status = "disabled";
699 #address-cells = <1>; 731 #address-cells = <1>;
@@ -787,6 +819,12 @@
787 interrupts = <1 9 0xf04>; 819 interrupts = <1 9 0xf04>;
788 }; 820 };
789 821
822 rtc: rtc@01f00000 {
823 compatible = "allwinner,sun6i-a31-rtc";
824 reg = <0x01f00000 0x54>;
825 interrupts = <0 40 4>, <0 41 4>;
826 };
827
790 nmi_intc: interrupt-controller@01f00c0c { 828 nmi_intc: interrupt-controller@01f00c0c {
791 compatible = "allwinner,sun6i-a31-sc-nmi"; 829 compatible = "allwinner,sun6i-a31-sc-nmi";
792 interrupt-controller; 830 interrupt-controller;
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
new file mode 100644
index 000000000000..0e4bfa3b2b85
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -0,0 +1,236 @@
1/*
2 * Copyright 2013 Wills Wang
3 *
4 * Wills Wang <wills.wang.open@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
17
18/ {
19 model = "Merrii A20 Hummingbird";
20 compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20";
21
22 soc@01c00000 {
23 mmc0: mmc@01c0f000 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
26 vmmc-supply = <&reg_vcc3v0>;
27 bus-width = <4>;
28 cd-gpios = <&pio 7 1 0>; /* PH1 */
29 cd-inverted;
30 status = "okay";
31 };
32
33 mmc3: mmc@01c12000 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&mmc3_pins_a>;
36 vmmc-supply = <&reg_mmc3_vdd>;
37 bus-width = <4>;
38 non-removable;
39 status = "okay";
40 };
41
42 usbphy: phy@01c13400 {
43 usb1_vbus-supply = <&reg_usb1_vbus>;
44 usb2_vbus-supply = <&reg_usb2_vbus>;
45 status = "okay";
46 };
47
48 ehci0: usb@01c14000 {
49 status = "okay";
50 };
51
52 ohci0: usb@01c14400 {
53 status = "okay";
54 };
55
56 ahci: sata@01c18000 {
57 target-supply = <&reg_ahci_5v>;
58 status = "okay";
59 };
60
61 ehci1: usb@01c1c000 {
62 status = "okay";
63 };
64
65 ohci1: usb@01c1c400 {
66 status = "okay";
67 };
68
69 pio: pinctrl@01c20800 {
70 ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
71 allwinner,pins = "PH15";
72 allwinner,function = "gpio_out";
73 allwinner,drive = <0>;
74 allwinner,pull = <0>;
75 };
76
77 usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
78 allwinner,pins = "PH2";
79 allwinner,function = "gpio_out";
80 allwinner,drive = <0>;
81 allwinner,pull = <0>;
82 };
83
84 mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
85 allwinner,pins = "PH9";
86 allwinner,function = "gpio_out";
87 allwinner,drive = <0>;
88 allwinner,pull = <0>;
89 };
90
91 gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
92 allwinner,pins = "PH16";
93 allwinner,function = "gpio_out";
94 allwinner,drive = <0>;
95 allwinner,pull = <0>;
96 };
97 };
98
99 pwm: pwm@01c20e00 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pwm0_pins_a>;
102 status = "okay";
103 };
104
105 ir0: ir@01c21800 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&ir0_pins_a>;
108 status = "okay";
109 };
110
111 uart0: serial@01c28000 {
112 pinctrl-names = "default";
113 pinctrl-0 = <&uart0_pins_a>;
114 status = "okay";
115 };
116
117 uart2: serial@01c28800 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&uart2_pins_a>;
120 status = "okay";
121 };
122
123 uart3: serial@01c28c00 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart3_pins_a>;
126 status = "okay";
127 };
128
129 uart4: serial@01c29000 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&uart4_pins_a>;
132 status = "okay";
133 };
134
135 uart5: serial@01c29400 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&uart5_pins_a>;
138 status = "okay";
139 };
140
141 i2c0: i2c@01c2ac00 {
142 pinctrl-names = "default";
143 pinctrl-0 = <&i2c0_pins_a>;
144 status = "okay";
145
146 axp209: pmic@34 {
147 compatible = "x-powers,axp209";
148 reg = <0x34>;
149 interrupt-parent = <&nmi_intc>;
150 interrupts = <0 8>;
151 interrupt-controller;
152 #interrupt-cells = <1>;
153 };
154 };
155
156 i2c1: i2c@01c2b000 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&i2c1_pins_a>;
159 status = "okay";
160 };
161
162 i2c2: i2c@01c2b400 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c2_pins_a>;
165 status = "okay";
166 };
167
168 i2c3: i2c@01c2b800 {
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2c3_pins_a>;
171 status = "okay";
172 };
173
174 spi2: spi@01c17000 {
175 pinctrl-names = "default";
176 pinctrl-0 = <&spi2_pins_b>;
177 status = "okay";
178 };
179
180 gmac: ethernet@01c50000 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&gmac_pins_rgmii_a>;
183 phy = <&phy1>;
184 phy-mode = "rgmii";
185 phy-supply = <&reg_gmac_vdd>;
186 /* phy reset config */
187 snps,reset-gpio = <&pio 0 17 0>; /* PA17 */
188 snps,reset-active-low;
189 /* wait 1s after reset, otherwise fail to read phy id */
190 snps,reset-delays-us = <0 10000 1000000>;
191 status = "okay";
192
193 phy1: ethernet-phy@1 {
194 reg = <1>;
195 };
196 };
197 };
198
199 reg_ahci_5v: ahci-5v {
200 pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>;
201 gpio = <&pio 7 15 0>; /* PH15 */
202 status = "okay";
203 };
204
205 reg_usb1_vbus: usb1-vbus {
206 pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>;
207 gpio = <&pio 7 2 0>; /* PH2 */
208 status = "okay";
209 };
210
211 reg_usb2_vbus: usb2-vbus {
212 status = "okay";
213 };
214
215 reg_mmc3_vdd: mmc3_vdd {
216 compatible = "regulator-fixed";
217 pinctrl-names = "default";
218 pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>;
219 regulator-name = "mmc3_vdd";
220 regulator-min-microvolt = <3000000>;
221 regulator-max-microvolt = <3000000>;
222 enable-active-high;
223 gpio = <&pio 7 9 0>; /* PH9 */
224 };
225
226 reg_gmac_vdd: gmac_vdd {
227 compatible = "regulator-fixed";
228 pinctrl-names = "default";
229 pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>;
230 regulator-name = "gmac_vdd";
231 regulator-min-microvolt = <3000000>;
232 regulator-max-microvolt = <3000000>;
233 enable-active-high;
234 gpio = <&pio 7 16 0>; /* PH16 */
235 };
236};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
new file mode 100644
index 000000000000..1eb8175959a6
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -0,0 +1,137 @@
1/*
2 * This is based on sun4i-a10-olinuxino-lime.dts
3 *
4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
5 * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15/dts-v1/;
16/include/ "sun7i-a20.dtsi"
17/include/ "sunxi-common-regulators.dtsi"
18
19/ {
20 model = "Olimex A20-OLinuXino-LIME";
21 compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20";
22
23 soc@01c00000 {
24 mmc0: mmc@01c0f000 {
25 pinctrl-names = "default";
26 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
27 vmmc-supply = <&reg_vcc3v3>;
28 bus-width = <4>;
29 cd-gpios = <&pio 7 1 0>; /* PH1 */
30 cd-inverted;
31 status = "okay";
32 };
33
34 usbphy: phy@01c13400 {
35 usb1_vbus-supply = <&reg_usb1_vbus>;
36 usb2_vbus-supply = <&reg_usb2_vbus>;
37 status = "okay";
38 };
39
40 ehci0: usb@01c14000 {
41 status = "okay";
42 };
43
44 ohci0: usb@01c14400 {
45 status = "okay";
46 };
47
48 ahci: sata@01c18000 {
49 target-supply = <&reg_ahci_5v>;
50 status = "okay";
51 };
52
53 ehci1: usb@01c1c000 {
54 status = "okay";
55 };
56
57 ohci1: usb@01c1c400 {
58 status = "okay";
59 };
60
61 pinctrl@01c20800 {
62 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
63 allwinner,pins = "PC3";
64 allwinner,function = "gpio_out";
65 allwinner,drive = <0>;
66 allwinner,pull = <0>;
67 };
68
69 led_pins_olinuxinolime: led_pins@0 {
70 allwinner,pins = "PH2";
71 allwinner,function = "gpio_out";
72 allwinner,drive = <1>;
73 allwinner,pull = <0>;
74 };
75 };
76
77 uart0: serial@01c28000 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&uart0_pins_a>;
80 status = "okay";
81 };
82
83 i2c0: i2c@01c2ac00 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&i2c0_pins_a>;
86 status = "okay";
87
88 axp209: pmic@34 {
89 compatible = "x-powers,axp209";
90 reg = <0x34>;
91 interrupt-parent = <&nmi_intc>;
92 interrupts = <0 8>;
93
94 interrupt-controller;
95 #interrupt-cells = <1>;
96 };
97 };
98
99 gmac: ethernet@01c50000 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&gmac_pins_mii_a>;
102 phy = <&phy1>;
103 phy-mode = "mii";
104 status = "okay";
105
106 phy1: ethernet-phy@1 {
107 reg = <1>;
108 };
109 };
110 };
111
112 leds {
113 compatible = "gpio-leds";
114 pinctrl-names = "default";
115 pinctrl-0 = <&led_pins_olinuxinolime>;
116
117 green {
118 label = "a20-olinuxino-lime:green:usr";
119 gpios = <&pio 7 2 0>;
120 default-state = "on";
121 };
122 };
123
124 reg_ahci_5v: ahci-5v {
125 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
126 gpio = <&pio 2 3 0>;
127 status = "okay";
128 };
129
130 reg_usb1_vbus: usb1-vbus {
131 status = "okay";
132 };
133
134 reg_usb2_vbus: usb2-vbus {
135 status = "okay";
136 };
137};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4011628c7381..a96b99465069 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This library is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/include/ "skeleton.dtsi" 50/include/ "skeleton.dtsi"
@@ -423,12 +459,22 @@
423 interrupts = <0 0 4>; 459 interrupts = <0 0 4>;
424 }; 460 };
425 461
462 dma: dma-controller@01c02000 {
463 compatible = "allwinner,sun4i-a10-dma";
464 reg = <0x01c02000 0x1000>;
465 interrupts = <0 27 4>;
466 clocks = <&ahb_gates 6>;
467 #dma-cells = <2>;
468 };
469
426 spi0: spi@01c05000 { 470 spi0: spi@01c05000 {
427 compatible = "allwinner,sun4i-a10-spi"; 471 compatible = "allwinner,sun4i-a10-spi";
428 reg = <0x01c05000 0x1000>; 472 reg = <0x01c05000 0x1000>;
429 interrupts = <0 10 4>; 473 interrupts = <0 10 4>;
430 clocks = <&ahb_gates 20>, <&spi0_clk>; 474 clocks = <&ahb_gates 20>, <&spi0_clk>;
431 clock-names = "ahb", "mod"; 475 clock-names = "ahb", "mod";
476 dmas = <&dma 1 27>, <&dma 1 26>;
477 dma-names = "rx", "tx";
432 status = "disabled"; 478 status = "disabled";
433 #address-cells = <1>; 479 #address-cells = <1>;
434 #size-cells = <0>; 480 #size-cells = <0>;
@@ -440,6 +486,8 @@
440 interrupts = <0 11 4>; 486 interrupts = <0 11 4>;
441 clocks = <&ahb_gates 21>, <&spi1_clk>; 487 clocks = <&ahb_gates 21>, <&spi1_clk>;
442 clock-names = "ahb", "mod"; 488 clock-names = "ahb", "mod";
489 dmas = <&dma 1 9>, <&dma 1 8>;
490 dma-names = "rx", "tx";
443 status = "disabled"; 491 status = "disabled";
444 #address-cells = <1>; 492 #address-cells = <1>;
445 #size-cells = <0>; 493 #size-cells = <0>;
@@ -535,6 +583,8 @@
535 interrupts = <0 12 4>; 583 interrupts = <0 12 4>;
536 clocks = <&ahb_gates 22>, <&spi2_clk>; 584 clocks = <&ahb_gates 22>, <&spi2_clk>;
537 clock-names = "ahb", "mod"; 585 clock-names = "ahb", "mod";
586 dmas = <&dma 1 29>, <&dma 1 28>;
587 dma-names = "rx", "tx";
538 status = "disabled"; 588 status = "disabled";
539 #address-cells = <1>; 589 #address-cells = <1>;
540 #size-cells = <0>; 590 #size-cells = <0>;
@@ -574,6 +624,8 @@
574 interrupts = <0 50 4>; 624 interrupts = <0 50 4>;
575 clocks = <&ahb_gates 23>, <&spi3_clk>; 625 clocks = <&ahb_gates 23>, <&spi3_clk>;
576 clock-names = "ahb", "mod"; 626 clock-names = "ahb", "mod";
627 dmas = <&dma 1 31>, <&dma 1 30>;
628 dma-names = "rx", "tx";
577 status = "disabled"; 629 status = "disabled";
578 #address-cells = <1>; 630 #address-cells = <1>;
579 #size-cells = <0>; 631 #size-cells = <0>;
@@ -618,6 +670,27 @@
618 allwinner,pull = <0>; 670 allwinner,pull = <0>;
619 }; 671 };
620 672
673 uart3_pins_a: uart3@0 {
674 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
675 allwinner,function = "uart3";
676 allwinner,drive = <0>;
677 allwinner,pull = <0>;
678 };
679
680 uart4_pins_a: uart4@0 {
681 allwinner,pins = "PG10", "PG11";
682 allwinner,function = "uart4";
683 allwinner,drive = <0>;
684 allwinner,pull = <0>;
685 };
686
687 uart5_pins_a: uart5@0 {
688 allwinner,pins = "PI10", "PI11";
689 allwinner,function = "uart5";
690 allwinner,drive = <0>;
691 allwinner,pull = <0>;
692 };
693
621 uart6_pins_a: uart6@0 { 694 uart6_pins_a: uart6@0 {
622 allwinner,pins = "PI12", "PI13"; 695 allwinner,pins = "PI12", "PI13";
623 allwinner,function = "uart6"; 696 allwinner,function = "uart6";
@@ -653,6 +726,13 @@
653 allwinner,pull = <0>; 726 allwinner,pull = <0>;
654 }; 727 };
655 728
729 i2c3_pins_a: i2c3@0 {
730 allwinner,pins = "PI0", "PI1";
731 allwinner,function = "i2c3";
732 allwinner,drive = <0>;
733 allwinner,pull = <0>;
734 };
735
656 emac_pins_a: emac0@0 { 736 emac_pins_a: emac0@0 {
657 allwinner,pins = "PA0", "PA1", "PA2", 737 allwinner,pins = "PA0", "PA1", "PA2",
658 "PA3", "PA4", "PA5", "PA6", 738 "PA3", "PA4", "PA5", "PA6",
@@ -718,6 +798,13 @@
718 allwinner,pull = <0>; 798 allwinner,pull = <0>;
719 }; 799 };
720 800
801 spi2_pins_b: spi2@1 {
802 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
803 allwinner,function = "spi2";
804 allwinner,drive = <0>;
805 allwinner,pull = <0>;
806 };
807
721 mmc0_pins_a: mmc0@0 { 808 mmc0_pins_a: mmc0@0 {
722 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 809 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
723 allwinner,function = "mmc0"; 810 allwinner,function = "mmc0";
@@ -899,7 +986,6 @@
899 reg = <0x01c2ac00 0x400>; 986 reg = <0x01c2ac00 0x400>;
900 interrupts = <0 7 4>; 987 interrupts = <0 7 4>;
901 clocks = <&apb1_gates 0>; 988 clocks = <&apb1_gates 0>;
902 clock-frequency = <100000>;
903 status = "disabled"; 989 status = "disabled";
904 #address-cells = <1>; 990 #address-cells = <1>;
905 #size-cells = <0>; 991 #size-cells = <0>;
@@ -910,7 +996,6 @@
910 reg = <0x01c2b000 0x400>; 996 reg = <0x01c2b000 0x400>;
911 interrupts = <0 8 4>; 997 interrupts = <0 8 4>;
912 clocks = <&apb1_gates 1>; 998 clocks = <&apb1_gates 1>;
913 clock-frequency = <100000>;
914 status = "disabled"; 999 status = "disabled";
915 #address-cells = <1>; 1000 #address-cells = <1>;
916 #size-cells = <0>; 1001 #size-cells = <0>;
@@ -921,7 +1006,6 @@
921 reg = <0x01c2b400 0x400>; 1006 reg = <0x01c2b400 0x400>;
922 interrupts = <0 9 4>; 1007 interrupts = <0 9 4>;
923 clocks = <&apb1_gates 2>; 1008 clocks = <&apb1_gates 2>;
924 clock-frequency = <100000>;
925 status = "disabled"; 1009 status = "disabled";
926 #address-cells = <1>; 1010 #address-cells = <1>;
927 #size-cells = <0>; 1011 #size-cells = <0>;
@@ -932,7 +1016,6 @@
932 reg = <0x01c2b800 0x400>; 1016 reg = <0x01c2b800 0x400>;
933 interrupts = <0 88 4>; 1017 interrupts = <0 88 4>;
934 clocks = <&apb1_gates 3>; 1018 clocks = <&apb1_gates 3>;
935 clock-frequency = <100000>;
936 status = "disabled"; 1019 status = "disabled";
937 #address-cells = <1>; 1020 #address-cells = <1>;
938 #size-cells = <0>; 1021 #size-cells = <0>;
@@ -943,7 +1026,6 @@
943 reg = <0x01c2c000 0x400>; 1026 reg = <0x01c2c000 0x400>;
944 interrupts = <0 89 4>; 1027 interrupts = <0 89 4>;
945 clocks = <&apb1_gates 15>; 1028 clocks = <&apb1_gates 15>;
946 clock-frequency = <100000>;
947 status = "disabled"; 1029 status = "disabled";
948 #address-cells = <1>; 1030 #address-cells = <1>;
949 #size-cells = <0>; 1031 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index 34002e3eba9d..e9b8cca8dcc1 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -13,6 +13,7 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun8i-a23.dtsi" 15/include/ "sun8i-a23.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Ippo Q8H Dual Core Tablet (v5)"; 19 model = "Ippo Q8H Dual Core Tablet (v5)";
@@ -23,7 +24,47 @@
23 }; 24 };
24 25
25 soc@01c00000 { 26 soc@01c00000 {
27 mmc0: mmc@01c0f000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
30 vmmc-supply = <&reg_vcc3v0>;
31 bus-width = <4>;
32 cd-gpios = <&pio 1 4 0>; /* PB4 */
33 cd-inverted;
34 status = "okay";
35 };
36
37 pinctrl@01c20800 {
38 mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
39 allwinner,pins = "PB4";
40 allwinner,function = "gpio_in";
41 allwinner,drive = <0>;
42 allwinner,pull = <1>;
43 };
44 };
45
46 i2c0: i2c@01c2ac00 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&i2c0_pins_a>;
49 status = "okay";
50 };
51
52 i2c1: i2c@01c2b000 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&i2c1_pins_a>;
55 status = "okay";
56 };
57
58 i2c2: i2c@01c2b400 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c2_pins_a>;
61 /* pull-ups and devices require PMIC regulator */
62 status = "failed";
63 };
64
26 r_uart: serial@01f02800 { 65 r_uart: serial@01f02800 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&r_uart_pins_a>;
27 status = "okay"; 68 status = "okay";
28 }; 69 };
29 }; 70 };
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 54ac0787216a..6146ef15efbe 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Chen-Yu Tsai <wens@csie.org> 4 * Chen-Yu Tsai <wens@csie.org>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This library is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/include/ "skeleton.dtsi" 50/include/ "skeleton.dtsi"
@@ -179,6 +215,30 @@
179 "apb2_uart1", "apb2_uart2", 215 "apb2_uart1", "apb2_uart2",
180 "apb2_uart3", "apb2_uart4"; 216 "apb2_uart3", "apb2_uart4";
181 }; 217 };
218
219 mmc0_clk: clk@01c20088 {
220 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c20088 0x4>;
223 clocks = <&osc24M>, <&pll6>;
224 clock-output-names = "mmc0";
225 };
226
227 mmc1_clk: clk@01c2008c {
228 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c2008c 0x4>;
231 clocks = <&osc24M>, <&pll6>;
232 clock-output-names = "mmc1";
233 };
234
235 mmc2_clk: clk@01c20090 {
236 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-a10-mod0-clk";
238 reg = <0x01c20090 0x4>;
239 clocks = <&osc24M>, <&pll6>;
240 clock-output-names = "mmc2";
241 };
182 }; 242 };
183 243
184 soc@01c00000 { 244 soc@01c00000 {
@@ -187,6 +247,104 @@
187 #size-cells = <1>; 247 #size-cells = <1>;
188 ranges; 248 ranges;
189 249
250 dma: dma-controller@01c02000 {
251 compatible = "allwinner,sun8i-a23-dma";
252 reg = <0x01c02000 0x1000>;
253 interrupts = <0 50 4>;
254 clocks = <&ahb1_gates 6>;
255 resets = <&ahb1_rst 6>;
256 #dma-cells = <1>;
257 };
258
259 mmc0: mmc@01c0f000 {
260 compatible = "allwinner,sun5i-a13-mmc";
261 reg = <0x01c0f000 0x1000>;
262 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
263 clock-names = "ahb", "mmc";
264 resets = <&ahb1_rst 8>;
265 reset-names = "ahb";
266 interrupts = <0 60 4>;
267 status = "disabled";
268 };
269
270 mmc1: mmc@01c10000 {
271 compatible = "allwinner,sun5i-a13-mmc";
272 reg = <0x01c10000 0x1000>;
273 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
274 clock-names = "ahb", "mmc";
275 resets = <&ahb1_rst 9>;
276 reset-names = "ahb";
277 interrupts = <0 61 4>;
278 status = "disabled";
279 };
280
281 mmc2: mmc@01c11000 {
282 compatible = "allwinner,sun5i-a13-mmc";
283 reg = <0x01c11000 0x1000>;
284 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
285 clock-names = "ahb", "mmc";
286 resets = <&ahb1_rst 10>;
287 reset-names = "ahb";
288 interrupts = <0 62 4>;
289 status = "disabled";
290 };
291
292 pio: pinctrl@01c20800 {
293 compatible = "allwinner,sun8i-a23-pinctrl";
294 reg = <0x01c20800 0x400>;
295 interrupts = <0 11 4>,
296 <0 15 4>,
297 <0 17 4>;
298 clocks = <&apb1_gates 5>;
299 gpio-controller;
300 interrupt-controller;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 #gpio-cells = <3>;
304
305 uart0_pins_a: uart0@0 {
306 allwinner,pins = "PF2", "PF4";
307 allwinner,function = "uart0";
308 allwinner,drive = <0>;
309 allwinner,pull = <0>;
310 };
311
312 mmc0_pins_a: mmc0@0 {
313 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
314 allwinner,function = "mmc0";
315 allwinner,drive = <2>;
316 allwinner,pull = <0>;
317 };
318
319 mmc1_pins_a: mmc1@0 {
320 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
321 allwinner,function = "mmc1";
322 allwinner,drive = <2>;
323 allwinner,pull = <0>;
324 };
325
326 i2c0_pins_a: i2c0@0 {
327 allwinner,pins = "PH2", "PH3";
328 allwinner,function = "i2c0";
329 allwinner,drive = <0>;
330 allwinner,pull = <0>;
331 };
332
333 i2c1_pins_a: i2c1@0 {
334 allwinner,pins = "PH4", "PH5";
335 allwinner,function = "i2c1";
336 allwinner,drive = <0>;
337 allwinner,pull = <0>;
338 };
339
340 i2c2_pins_a: i2c2@0 {
341 allwinner,pins = "PE12", "PE13";
342 allwinner,function = "i2c2";
343 allwinner,drive = <0>;
344 allwinner,pull = <0>;
345 };
346 };
347
190 ahb1_rst: reset@01c202c0 { 348 ahb1_rst: reset@01c202c0 {
191 #reset-cells = <1>; 349 #reset-cells = <1>;
192 compatible = "allwinner,sun6i-a31-clock-reset"; 350 compatible = "allwinner,sun6i-a31-clock-reset";
@@ -227,6 +385,8 @@
227 reg-io-width = <4>; 385 reg-io-width = <4>;
228 clocks = <&apb2_gates 16>; 386 clocks = <&apb2_gates 16>;
229 resets = <&apb2_rst 16>; 387 resets = <&apb2_rst 16>;
388 dmas = <&dma 6>, <&dma 6>;
389 dma-names = "rx", "tx";
230 status = "disabled"; 390 status = "disabled";
231 }; 391 };
232 392
@@ -238,6 +398,8 @@
238 reg-io-width = <4>; 398 reg-io-width = <4>;
239 clocks = <&apb2_gates 17>; 399 clocks = <&apb2_gates 17>;
240 resets = <&apb2_rst 17>; 400 resets = <&apb2_rst 17>;
401 dmas = <&dma 7>, <&dma 7>;
402 dma-names = "rx", "tx";
241 status = "disabled"; 403 status = "disabled";
242 }; 404 };
243 405
@@ -249,6 +411,8 @@
249 reg-io-width = <4>; 411 reg-io-width = <4>;
250 clocks = <&apb2_gates 18>; 412 clocks = <&apb2_gates 18>;
251 resets = <&apb2_rst 18>; 413 resets = <&apb2_rst 18>;
414 dmas = <&dma 8>, <&dma 8>;
415 dma-names = "rx", "tx";
252 status = "disabled"; 416 status = "disabled";
253 }; 417 };
254 418
@@ -260,6 +424,8 @@
260 reg-io-width = <4>; 424 reg-io-width = <4>;
261 clocks = <&apb2_gates 19>; 425 clocks = <&apb2_gates 19>;
262 resets = <&apb2_rst 19>; 426 resets = <&apb2_rst 19>;
427 dmas = <&dma 9>, <&dma 9>;
428 dma-names = "rx", "tx";
263 status = "disabled"; 429 status = "disabled";
264 }; 430 };
265 431
@@ -271,9 +437,44 @@
271 reg-io-width = <4>; 437 reg-io-width = <4>;
272 clocks = <&apb2_gates 20>; 438 clocks = <&apb2_gates 20>;
273 resets = <&apb2_rst 20>; 439 resets = <&apb2_rst 20>;
440 dmas = <&dma 10>, <&dma 10>;
441 dma-names = "rx", "tx";
274 status = "disabled"; 442 status = "disabled";
275 }; 443 };
276 444
445 i2c0: i2c@01c2ac00 {
446 compatible = "allwinner,sun6i-a31-i2c";
447 reg = <0x01c2ac00 0x400>;
448 interrupts = <0 6 4>;
449 clocks = <&apb2_gates 0>;
450 resets = <&apb2_rst 0>;
451 status = "disabled";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 };
455
456 i2c1: i2c@01c2b000 {
457 compatible = "allwinner,sun6i-a31-i2c";
458 reg = <0x01c2b000 0x400>;
459 interrupts = <0 7 4>;
460 clocks = <&apb2_gates 1>;
461 resets = <&apb2_rst 1>;
462 status = "disabled";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
466
467 i2c2: i2c@01c2b400 {
468 compatible = "allwinner,sun6i-a31-i2c";
469 reg = <0x01c2b400 0x400>;
470 interrupts = <0 8 4>;
471 clocks = <&apb2_gates 2>;
472 resets = <&apb2_rst 2>;
473 status = "disabled";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 };
477
277 gic: interrupt-controller@01c81000 { 478 gic: interrupt-controller@01c81000 {
278 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 479 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
279 reg = <0x01c81000 0x1000>, 480 reg = <0x01c81000 0x1000>,
@@ -285,6 +486,12 @@
285 interrupts = <1 9 0xf04>; 486 interrupts = <1 9 0xf04>;
286 }; 487 };
287 488
489 rtc: rtc@01f00000 {
490 compatible = "allwinner,sun6i-a31-rtc";
491 reg = <0x01f00000 0x54>;
492 interrupts = <0 40 4>, <0 41 4>;
493 };
494
288 prcm@01f01400 { 495 prcm@01f01400 {
289 compatible = "allwinner,sun8i-a23-prcm"; 496 compatible = "allwinner,sun8i-a23-prcm";
290 reg = <0x01f01400 0x200>; 497 reg = <0x01f01400 0x200>;
@@ -339,5 +546,25 @@
339 resets = <&apb0_rst 4>; 546 resets = <&apb0_rst 4>;
340 status = "disabled"; 547 status = "disabled";
341 }; 548 };
549
550 r_pio: pinctrl@01f02c00 {
551 compatible = "allwinner,sun8i-a23-r-pinctrl";
552 reg = <0x01f02c00 0x400>;
553 interrupts = <0 45 4>;
554 clocks = <&apb0_gates 0>;
555 resets = <&apb0_rst 0>;
556 gpio-controller;
557 interrupt-controller;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 #gpio-cells = <3>;
561
562 r_uart_pins_a: r_uart@0 {
563 allwinner,pins = "PL2", "PL3";
564 allwinner,function = "s_uart";
565 allwinner,drive = <0>;
566 allwinner,pull = <0>;
567 };
568 };
342 }; 569 };
343}; 570};
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index 3d021efd1a38..c9c5b10e03eb 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -86,4 +86,11 @@
86 regulator-min-microvolt = <3300000>; 86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>;
88 }; 88 };
89
90 reg_vcc5v0: vcc5v0 {
91 compatible = "regulator-fixed";
92 regulator-name = "vcc5v0";
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
95 };
89}; 96};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 80b8eddb4105..2ca9c1807f72 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -157,6 +157,11 @@
157 #reset-cells = <1>; 157 #reset-cells = <1>;
158 }; 158 };
159 159
160 flow-controller@60007000 {
161 compatible = "nvidia,tegra114-flowctrl";
162 reg = <0x60007000 0x1000>;
163 };
164
160 apbdma: dma@6000a000 { 165 apbdma: dma@6000a000 {
161 compatible = "nvidia,tegra114-apbdma"; 166 compatible = "nvidia,tegra114-apbdma";
162 reg = <0x6000a000 0x1400>; 167 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 624b0fba2d0a..029c9a021541 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -16,6 +16,26 @@
16 reg = <0x0 0x80000000 0x0 0x80000000>; 16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 }; 17 };
18 18
19 pcie-controller@0,01003000 {
20 status = "okay";
21
22 avddio-pex-supply = <&vdd_1v05_run>;
23 dvddio-pex-supply = <&vdd_1v05_run>;
24 avdd-pex-pll-supply = <&vdd_1v05_run>;
25 hvdd-pex-supply = <&vdd_3v3_lp0>;
26 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
27 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
28 avdd-pll-erefe-supply = <&avdd_1v05_run>;
29
30 pci@1,0 {
31 status = "okay";
32 };
33
34 pci@2,0 {
35 status = "okay";
36 };
37 };
38
19 host1x@0,50000000 { 39 host1x@0,50000000 {
20 hdmi@0,54280000 { 40 hdmi@0,54280000 {
21 status = "okay"; 41 status = "okay";
@@ -31,10 +51,10 @@
31 }; 51 };
32 52
33 pinmux: pinmux@0,70000868 { 53 pinmux: pinmux@0,70000868 {
34 pinctrl-names = "default"; 54 pinctrl-names = "boot";
35 pinctrl-0 = <&state_default>; 55 pinctrl-0 = <&state_boot>;
36 56
37 state_default: pinmux { 57 state_boot: pinmux {
38 clk_32k_out_pa0 { 58 clk_32k_out_pa0 {
39 nvidia,pins = "clk_32k_out_pa0"; 59 nvidia,pins = "clk_32k_out_pa0";
40 nvidia,function = "soc"; 60 nvidia,function = "soc";
@@ -1231,6 +1251,41 @@
1231 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1232 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1252 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1233 }; 1253 };
1254 pex_l0_rst_n_pdd1 {
1255 nvidia,pins = "pex_l0_rst_n_pdd1";
1256 nvidia,function = "pe0";
1257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1259 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1260 };
1261 pex_l0_clkreq_n_pdd2 {
1262 nvidia,pins = "pex_l0_clkreq_n_pdd2";
1263 nvidia,function = "pe0";
1264 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1266 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1267 };
1268 pex_wake_n_pdd3 {
1269 nvidia,pins = "pex_wake_n_pdd3";
1270 nvidia,function = "pe";
1271 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1274 };
1275 pex_l1_rst_n_pdd5 {
1276 nvidia,pins = "pex_l1_rst_n_pdd5";
1277 nvidia,function = "pe1";
1278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1280 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1281 };
1282 pex_l1_clkreq_n_pdd6 {
1283 nvidia,pins = "pex_l1_clkreq_n_pdd6";
1284 nvidia,function = "pe1";
1285 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1287 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1288 };
1234 clk3_out_pee0 { 1289 clk3_out_pee0 {
1235 nvidia,pins = "clk3_out_pee0"; 1290 nvidia,pins = "clk3_out_pee0";
1236 nvidia,function = "extperiph3"; 1291 nvidia,function = "extperiph3";
@@ -1515,7 +1570,7 @@
1515 regulator-always-on; 1570 regulator-always-on;
1516 }; 1571 };
1517 1572
1518 ldo0 { 1573 avdd_1v05_run: ldo0 {
1519 regulator-name = "+1.05V_RUN_AVDD"; 1574 regulator-name = "+1.05V_RUN_AVDD";
1520 regulator-min-microvolt = <1050000>; 1575 regulator-min-microvolt = <1050000>;
1521 regulator-max-microvolt = <1050000>; 1576 regulator-max-microvolt = <1050000>;
@@ -1619,6 +1674,18 @@
1619 nvidia,sys-clock-req-active-high; 1674 nvidia,sys-clock-req-active-high;
1620 }; 1675 };
1621 1676
1677 /* Serial ATA */
1678 sata@0,70020000 {
1679 status = "okay";
1680
1681 hvdd-supply = <&vdd_3v3_lp0>;
1682 vddio-supply = <&vdd_1v05_run>;
1683 avdd-supply = <&vdd_1v05_run>;
1684
1685 target-5v-supply = <&vdd_5v0_sata>;
1686 target-12v-supply = <&vdd_12v0_sata>;
1687 };
1688
1622 padctl@0,7009f000 { 1689 padctl@0,7009f000 {
1623 pinctrl-0 = <&padctl_default>; 1690 pinctrl-0 = <&padctl_default>;
1624 pinctrl-names = "default"; 1691 pinctrl-names = "default";
@@ -1828,6 +1895,29 @@
1828 enable-active-high; 1895 enable-active-high;
1829 vin-supply = <&vdd_5v0_sys>; 1896 vin-supply = <&vdd_5v0_sys>;
1830 }; 1897 };
1898
1899 /* Molex power connector */
1900 vdd_5v0_sata: regulator@13 {
1901 compatible = "regulator-fixed";
1902 reg = <13>;
1903 regulator-name = "+5V_SATA";
1904 regulator-min-microvolt = <5000000>;
1905 regulator-max-microvolt = <5000000>;
1906 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1907 enable-active-high;
1908 vin-supply = <&vdd_5v0_sys>;
1909 };
1910
1911 vdd_12v0_sata: regulator@14 {
1912 compatible = "regulator-fixed";
1913 reg = <14>;
1914 regulator-name = "+12V_SATA";
1915 regulator-min-microvolt = <12000000>;
1916 regulator-max-microvolt = <12000000>;
1917 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1918 enable-active-high;
1919 vin-supply = <&vdd_mux>;
1920 };
1831 }; 1921 };
1832 1922
1833 sound { 1923 sound {
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
new file mode 100644
index 000000000000..7d0784ce4c74
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -0,0 +1,1136 @@
1/dts-v1/;
2
3#include <dt-bindings/input/input.h>
4#include "tegra124.dtsi"
5
6/ {
7 model = "Acer Chromebook 13 CB5-311";
8 compatible = "google,nyan-big", "nvidia,tegra124";
9
10 aliases {
11 rtc0 = "/i2c@0,7000d000/pmic@40";
12 rtc1 = "/rtc@0,7000e000";
13 };
14
15 memory {
16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 };
18
19 host1x@0,50000000 {
20 hdmi@0,54280000 {
21 status = "okay";
22
23 vdd-supply = <&vdd_3v3_hdmi>;
24 pll-supply = <&vdd_hdmi_pll>;
25 hdmi-supply = <&vdd_5v0_hdmi>;
26
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio =
29 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
30 };
31
32 sor@0,54540000 {
33 status = "okay";
34
35 nvidia,dpaux = <&dpaux>;
36 nvidia,panel = <&panel>;
37 };
38
39 dpaux@0,545c0000 {
40 vdd-supply = <&vdd_3v3_panel>;
41 status = "okay";
42 };
43 };
44
45 pinmux@0,70000868 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinmux_default>;
48
49 pinmux_default: common {
50 dap_mclk1_pw4 {
51 nvidia,pins = "dap_mclk1_pw4";
52 nvidia,function = "extperiph1";
53 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 };
57 dap2_din_pa4 {
58 nvidia,pins = "dap2_din_pa4";
59 nvidia,function = "i2s1";
60 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
61 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
62 nvidia,tristate = <TEGRA_PIN_DISABLE>;
63 };
64 dap2_dout_pa5 {
65 nvidia,pins = "dap2_dout_pa5",
66 "dap2_fs_pa2",
67 "dap2_sclk_pa3";
68 nvidia,function = "i2s1";
69 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
70 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 };
73 dvfs_pwm_px0 {
74 nvidia,pins = "dvfs_pwm_px0",
75 "dvfs_clk_px2";
76 nvidia,function = "cldvfs";
77 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 };
81 ulpi_clk_py0 {
82 nvidia,pins = "ulpi_clk_py0",
83 "ulpi_nxt_py2",
84 "ulpi_stp_py3";
85 nvidia,function = "spi1";
86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 };
90 ulpi_dir_py1 {
91 nvidia,pins = "ulpi_dir_py1";
92 nvidia,function = "spi1";
93 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
96 };
97 cam_i2c_scl_pbb1 {
98 nvidia,pins = "cam_i2c_scl_pbb1",
99 "cam_i2c_sda_pbb2";
100 nvidia,function = "i2c3";
101 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,lock = <TEGRA_PIN_DISABLE>;
105 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
106 };
107 gen2_i2c_scl_pt5 {
108 nvidia,pins = "gen2_i2c_scl_pt5",
109 "gen2_i2c_sda_pt6";
110 nvidia,function = "i2c2";
111 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 nvidia,lock = <TEGRA_PIN_DISABLE>;
115 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
116 };
117 pg4 {
118 nvidia,pins = "pg4",
119 "pg5",
120 "pg6",
121 "pi3";
122 nvidia,function = "spi4";
123 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
124 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125 nvidia,tristate = <TEGRA_PIN_DISABLE>;
126 };
127 pg7 {
128 nvidia,pins = "pg7";
129 nvidia,function = "spi4";
130 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 };
134 ph1 {
135 nvidia,pins = "ph1";
136 nvidia,function = "pwm1";
137 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
138 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
139 nvidia,tristate = <TEGRA_PIN_DISABLE>;
140 };
141 pk0 {
142 nvidia,pins = "pk0",
143 "kb_row15_ps7",
144 "clk_32k_out_pa0";
145 nvidia,function = "soc";
146 nvidia,pull = <TEGRA_PIN_PULL_UP>;
147 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 };
150 sdmmc1_clk_pz0 {
151 nvidia,pins = "sdmmc1_clk_pz0";
152 nvidia,function = "sdmmc1";
153 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 };
157 sdmmc1_cmd_pz1 {
158 nvidia,pins = "sdmmc1_cmd_pz1",
159 "sdmmc1_dat0_py7",
160 "sdmmc1_dat1_py6",
161 "sdmmc1_dat2_py5",
162 "sdmmc1_dat3_py4";
163 nvidia,function = "sdmmc1";
164 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
165 nvidia,pull = <TEGRA_PIN_PULL_UP>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 };
168 sdmmc3_clk_pa6 {
169 nvidia,pins = "sdmmc3_clk_pa6";
170 nvidia,function = "sdmmc3";
171 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 };
175 sdmmc3_cmd_pa7 {
176 nvidia,pins = "sdmmc3_cmd_pa7",
177 "sdmmc3_dat0_pb7",
178 "sdmmc3_dat1_pb6",
179 "sdmmc3_dat2_pb5",
180 "sdmmc3_dat3_pb4",
181 "kb_col4_pq4",
182 "sdmmc3_clk_lb_out_pee4",
183 "sdmmc3_clk_lb_in_pee5",
184 "sdmmc3_cd_n_pv2";
185 nvidia,function = "sdmmc3";
186 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
187 nvidia,pull = <TEGRA_PIN_PULL_UP>;
188 nvidia,tristate = <TEGRA_PIN_DISABLE>;
189 };
190 sdmmc4_clk_pcc4 {
191 nvidia,pins = "sdmmc4_clk_pcc4";
192 nvidia,function = "sdmmc4";
193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
195 nvidia,tristate = <TEGRA_PIN_DISABLE>;
196 };
197 sdmmc4_cmd_pt7 {
198 nvidia,pins = "sdmmc4_cmd_pt7",
199 "sdmmc4_dat0_paa0",
200 "sdmmc4_dat1_paa1",
201 "sdmmc4_dat2_paa2",
202 "sdmmc4_dat3_paa3",
203 "sdmmc4_dat4_paa4",
204 "sdmmc4_dat5_paa5",
205 "sdmmc4_dat6_paa6",
206 "sdmmc4_dat7_paa7";
207 nvidia,function = "sdmmc4";
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212 pwr_i2c_scl_pz6 {
213 nvidia,pins = "pwr_i2c_scl_pz6",
214 "pwr_i2c_sda_pz7";
215 nvidia,function = "i2cpwr";
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,lock = <TEGRA_PIN_DISABLE>;
220 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
221 };
222 jtag_rtck {
223 nvidia,pins = "jtag_rtck";
224 nvidia,function = "rtck";
225 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 };
229 clk_32k_in {
230 nvidia,pins = "clk_32k_in";
231 nvidia,function = "clk";
232 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 };
236 core_pwr_req {
237 nvidia,pins = "core_pwr_req";
238 nvidia,function = "pwron";
239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 };
243 cpu_pwr_req {
244 nvidia,pins = "cpu_pwr_req";
245 nvidia,function = "cpu";
246 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 };
250 pwr_int_n {
251 nvidia,pins = "pwr_int_n";
252 nvidia,function = "pmi";
253 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
254 nvidia,pull = <TEGRA_PIN_PULL_UP>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 };
257 reset_out_n {
258 nvidia,pins = "reset_out_n";
259 nvidia,function = "reset_out_n";
260 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 };
264 clk3_out_pee0 {
265 nvidia,pins = "clk3_out_pee0";
266 nvidia,function = "extperiph3";
267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 };
271 gen1_i2c_sda_pc5 {
272 nvidia,pins = "gen1_i2c_sda_pc5",
273 "gen1_i2c_scl_pc4";
274 nvidia,function = "i2c1";
275 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
278 nvidia,lock = <TEGRA_PIN_DISABLE>;
279 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
280 };
281 hdmi_cec_pee3 {
282 nvidia,pins = "hdmi_cec_pee3";
283 nvidia,function = "cec";
284 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,lock = <TEGRA_PIN_DISABLE>;
288 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
289 };
290 hdmi_int_pn7 {
291 nvidia,pins = "hdmi_int_pn7";
292 nvidia,function = "rsvd1";
293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
294 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
295 nvidia,tristate = <TEGRA_PIN_DISABLE>;
296 };
297 ddc_scl_pv4 {
298 nvidia,pins = "ddc_scl_pv4",
299 "ddc_sda_pv5";
300 nvidia,function = "i2c4";
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,lock = <TEGRA_PIN_DISABLE>;
305 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
306 };
307 kb_row10_ps2 {
308 nvidia,pins = "kb_row10_ps2";
309 nvidia,function = "uarta";
310 nvidia,pull = <TEGRA_PIN_PULL_UP>;
311 nvidia,tristate = <TEGRA_PIN_DISABLE>;
312 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
313 };
314 kb_row9_ps1 {
315 nvidia,pins = "kb_row9_ps1";
316 nvidia,function = "uarta";
317 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
319 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
320 };
321 usb_vbus_en0_pn4 {
322 nvidia,pins = "usb_vbus_en0_pn4",
323 "usb_vbus_en1_pn5";
324 nvidia,function = "usb";
325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327 nvidia,tristate = <TEGRA_PIN_DISABLE>;
328 nvidia,lock = <TEGRA_PIN_DISABLE>;
329 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
330 };
331 drive_sdio1 {
332 nvidia,pins = "drive_sdio1";
333 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
334 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
335 nvidia,pull-down-strength = <36>;
336 nvidia,pull-up-strength = <20>;
337 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
338 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
339 };
340 drive_sdio3 {
341 nvidia,pins = "drive_sdio3";
342 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
343 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
344 nvidia,pull-down-strength = <22>;
345 nvidia,pull-up-strength = <36>;
346 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
347 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
348 };
349 drive_gma {
350 nvidia,pins = "drive_gma";
351 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
352 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
353 nvidia,pull-down-strength = <2>;
354 nvidia,pull-up-strength = <1>;
355 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
356 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
357 nvidia,drive-type = <1>;
358 };
359 codec_irq_l {
360 nvidia,pins = "ph4";
361 nvidia,function = "gmi";
362 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
363 nvidia,tristate = <TEGRA_PIN_DISABLE>;
364 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365 };
366 lcd_bl_en {
367 nvidia,pins = "ph2";
368 nvidia,function = "gmi";
369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
370 nvidia,tristate = <TEGRA_PIN_DISABLE>;
371 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
372 };
373 touch_irq_l {
374 nvidia,pins = "gpio_w3_aud_pw3";
375 nvidia,function = "spi6";
376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristate = <TEGRA_PIN_DISABLE>;
378 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
379 };
380 tpm_davint_l {
381 nvidia,pins = "ph6";
382 nvidia,function = "gmi";
383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
386 };
387 ts_irq_l {
388 nvidia,pins = "pk2";
389 nvidia,function = "gmi";
390 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
392 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
393 };
394 ts_reset_l {
395 nvidia,pins = "pk4";
396 nvidia,function = "gmi";
397 nvidia,pull = <TEGRA_PIN_PULL_UP>;
398 nvidia,tristate = <TEGRA_PIN_DISABLE>;
399 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
400 };
401 ts_shdn_l {
402 nvidia,pins = "pk1";
403 nvidia,function = "gmi";
404 nvidia,pull = <TEGRA_PIN_PULL_UP>;
405 nvidia,tristate = <TEGRA_PIN_DISABLE>;
406 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
407 };
408 ph7 {
409 nvidia,pins = "ph7";
410 nvidia,function = "gmi";
411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
414 };
415 kb_col0_ap {
416 nvidia,pins = "kb_col0_pq0";
417 nvidia,function = "rsvd4";
418 nvidia,pull = <TEGRA_PIN_PULL_UP>;
419 nvidia,tristate = <TEGRA_PIN_DISABLE>;
420 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
421 };
422 lid_open {
423 nvidia,pins = "kb_row4_pr4";
424 nvidia,function = "rsvd3";
425 nvidia,pull = <TEGRA_PIN_PULL_UP>;
426 nvidia,tristate = <TEGRA_PIN_DISABLE>;
427 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
428 };
429 en_vdd_sd {
430 nvidia,pins = "kb_row0_pr0";
431 nvidia,function = "rsvd4";
432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
435 };
436 ac_ok {
437 nvidia,pins = "pj0";
438 nvidia,function = "gmi";
439 nvidia,pull = <TEGRA_PIN_PULL_UP>;
440 nvidia,tristate = <TEGRA_PIN_DISABLE>;
441 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
442 };
443 sensor_irq_l {
444 nvidia,pins = "pi6";
445 nvidia,function = "gmi";
446 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
447 nvidia,tristate = <TEGRA_PIN_DISABLE>;
448 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
449 };
450 wifi_en {
451 nvidia,pins = "gpio_x7_aud_px7";
452 nvidia,function = "rsvd4";
453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
456 };
457 en_vdd_bl {
458 nvidia,pins = "dap3_dout_pp2";
459 nvidia,function = "i2s2";
460 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
461 nvidia,tristate = <TEGRA_PIN_DISABLE>;
462 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
463 };
464 en_vdd_hdmi {
465 nvidia,pins = "spdif_in_pk6";
466 nvidia,function = "spdif";
467 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
468 nvidia,tristate = <TEGRA_PIN_DISABLE>;
469 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
470 };
471 soc_warm_reset_l {
472 nvidia,pins = "pi5";
473 nvidia,function = "gmi";
474 nvidia,pull = <TEGRA_PIN_PULL_UP>;
475 nvidia,tristate = <TEGRA_PIN_DISABLE>;
476 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
477 };
478 hp_det_l {
479 nvidia,pins = "pi7";
480 nvidia,function = "rsvd1";
481 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
483 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
484 };
485 mic_det_l {
486 nvidia,pins = "kb_row7_pr7";
487 nvidia,function = "rsvd2";
488 nvidia,pull = <TEGRA_PIN_PULL_UP>;
489 nvidia,tristate = <TEGRA_PIN_DISABLE>;
490 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
491 };
492 };
493 };
494
495 serial@0,70006000 {
496 /* Debug connector on the bottom of the board near SD card. */
497 status = "okay";
498 };
499
500 pwm@0,7000a000 {
501 status = "okay";
502 };
503
504 i2c@0,7000c000 {
505 status = "okay";
506 clock-frequency = <100000>;
507
508 acodec: audio-codec@10 {
509 compatible = "maxim,max98090";
510 reg = <0x10>;
511 interrupt-parent = <&gpio>;
512 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
513 };
514
515 temperature-sensor@4c {
516 compatible = "ti,tmp451";
517 reg = <0x4c>;
518 interrupt-parent = <&gpio>;
519 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
520
521 #thermal-sensor-cells = <1>;
522 };
523 };
524
525 i2c@0,7000c400 {
526 status = "okay";
527 clock-frequency = <100000>;
528 };
529
530 i2c@0,7000c500 {
531 status = "okay";
532 clock-frequency = <400000>;
533
534 tpm@20 {
535 compatible = "infineon,slb9645tt";
536 reg = <0x20>;
537 };
538 };
539
540 hdmi_ddc: i2c@0,7000c700 {
541 status = "okay";
542 clock-frequency = <100000>;
543 };
544
545 i2c@0,7000d000 {
546 status = "okay";
547 clock-frequency = <400000>;
548
549 pmic: pmic@40 {
550 compatible = "ams,as3722";
551 reg = <0x40>;
552 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
553
554 ams,system-power-controller;
555
556 #interrupt-cells = <2>;
557 interrupt-controller;
558
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 pinctrl-names = "default";
563 pinctrl-0 = <&as3722_default>;
564
565 as3722_default: pinmux {
566 gpio0 {
567 pins = "gpio0";
568 function = "gpio";
569 bias-pull-down;
570 };
571
572 gpio1 {
573 pins = "gpio1";
574 function = "gpio";
575 bias-pull-up;
576 };
577
578 gpio2_4_7 {
579 pins = "gpio2", "gpio4", "gpio7";
580 function = "gpio";
581 bias-pull-up;
582 };
583
584 gpio3_6 {
585 pins = "gpio3", "gpio6";
586 bias-high-impedance;
587 };
588
589 gpio5 {
590 pins = "gpio5";
591 function = "clk32k-out";
592 bias-pull-down;
593 };
594 };
595
596 regulators {
597 vsup-sd2-supply = <&vdd_5v0_sys>;
598 vsup-sd3-supply = <&vdd_5v0_sys>;
599 vsup-sd4-supply = <&vdd_5v0_sys>;
600 vsup-sd5-supply = <&vdd_5v0_sys>;
601 vin-ldo0-supply = <&vdd_1v35_lp0>;
602 vin-ldo1-6-supply = <&vdd_3v3_run>;
603 vin-ldo2-5-7-supply = <&vddio_1v8>;
604 vin-ldo3-4-supply = <&vdd_3v3_sys>;
605 vin-ldo9-10-supply = <&vdd_5v0_sys>;
606 vin-ldo11-supply = <&vdd_3v3_run>;
607
608 sd0 {
609 regulator-name = "+VDD_CPU_AP";
610 regulator-min-microvolt = <700000>;
611 regulator-max-microvolt = <1350000>;
612 regulator-min-microamp = <3500000>;
613 regulator-max-microamp = <3500000>;
614 regulator-always-on;
615 regulator-boot-on;
616 ams,ext-control = <2>;
617 };
618
619 sd1 {
620 regulator-name = "+VDD_CORE";
621 regulator-min-microvolt = <700000>;
622 regulator-max-microvolt = <1350000>;
623 regulator-min-microamp = <2500000>;
624 regulator-max-microamp = <4000000>;
625 regulator-always-on;
626 regulator-boot-on;
627 ams,ext-control = <1>;
628 };
629
630 vdd_1v35_lp0: sd2 {
631 regulator-name = "+1.35V_LP0(sd2)";
632 regulator-min-microvolt = <1350000>;
633 regulator-max-microvolt = <1350000>;
634 regulator-always-on;
635 regulator-boot-on;
636 };
637
638 sd3 {
639 regulator-name = "+1.35V_LP0(sd3)";
640 regulator-min-microvolt = <1350000>;
641 regulator-max-microvolt = <1350000>;
642 regulator-always-on;
643 regulator-boot-on;
644 };
645
646 vdd_1v05_run: sd4 {
647 regulator-name = "+1.05V_RUN";
648 regulator-min-microvolt = <1050000>;
649 regulator-max-microvolt = <1050000>;
650 };
651
652 vddio_1v8: sd5 {
653 regulator-name = "+1.8V_VDDIO";
654 regulator-min-microvolt = <1800000>;
655 regulator-max-microvolt = <1800000>;
656 regulator-boot-on;
657 regulator-always-on;
658 };
659
660 sd6 {
661 regulator-name = "+VDD_GPU_AP";
662 regulator-min-microvolt = <650000>;
663 regulator-max-microvolt = <1200000>;
664 regulator-min-microamp = <3500000>;
665 regulator-max-microamp = <3500000>;
666 regulator-boot-on;
667 regulator-always-on;
668 };
669
670 ldo0 {
671 regulator-name = "+1.05V_RUN_AVDD";
672 regulator-min-microvolt = <1050000>;
673 regulator-max-microvolt = <1050000>;
674 regulator-boot-on;
675 regulator-always-on;
676 ams,ext-control = <1>;
677 };
678
679 ldo1 {
680 regulator-name = "+1.8V_RUN_CAM";
681 regulator-min-microvolt = <1800000>;
682 regulator-max-microvolt = <1800000>;
683 };
684
685 ldo2 {
686 regulator-name = "+1.2V_GEN_AVDD";
687 regulator-min-microvolt = <1200000>;
688 regulator-max-microvolt = <1200000>;
689 regulator-boot-on;
690 regulator-always-on;
691 };
692
693 ldo3 {
694 regulator-name = "+1.00V_LP0_VDD_RTC";
695 regulator-min-microvolt = <1000000>;
696 regulator-max-microvolt = <1000000>;
697 regulator-boot-on;
698 regulator-always-on;
699 ams,enable-tracking;
700 };
701
702 vdd_run_cam: ldo4 {
703 regulator-name = "+3.3V_RUN_CAM";
704 regulator-min-microvolt = <2800000>;
705 regulator-max-microvolt = <2800000>;
706 };
707
708 ldo5 {
709 regulator-name = "+1.2V_RUN_CAM_FRONT";
710 regulator-min-microvolt = <1200000>;
711 regulator-max-microvolt = <1200000>;
712 };
713
714 vddio_sdmmc3: ldo6 {
715 regulator-name = "+VDDIO_SDMMC3";
716 regulator-min-microvolt = <1800000>;
717 regulator-max-microvolt = <3300000>;
718 };
719
720 ldo7 {
721 regulator-name = "+1.05V_RUN_CAM_REAR";
722 regulator-min-microvolt = <1050000>;
723 regulator-max-microvolt = <1050000>;
724 };
725
726 ldo9 {
727 regulator-name = "+2.8V_RUN_TOUCH";
728 regulator-min-microvolt = <2800000>;
729 regulator-max-microvolt = <2800000>;
730 };
731
732 ldo10 {
733 regulator-name = "+2.8V_RUN_CAM_AF";
734 regulator-min-microvolt = <2800000>;
735 regulator-max-microvolt = <2800000>;
736 };
737
738 ldo11 {
739 regulator-name = "+1.8V_RUN_VPP_FUSE";
740 regulator-min-microvolt = <1800000>;
741 regulator-max-microvolt = <1800000>;
742 };
743 };
744 };
745 };
746
747 spi@0,7000d400 {
748 status = "okay";
749
750 cros_ec: cros-ec@0 {
751 compatible = "google,cros-ec-spi";
752 spi-max-frequency = <3000000>;
753 interrupt-parent = <&gpio>;
754 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
755 reg = <0>;
756
757 google,cros-ec-spi-msg-delay = <2000>;
758
759 i2c-tunnel {
760 compatible = "google,cros-ec-i2c-tunnel";
761 #address-cells = <1>;
762 #size-cells = <0>;
763
764 google,remote-bus = <0>;
765
766 charger: bq24735@9 {
767 compatible = "ti,bq24735";
768 reg = <0x9>;
769 interrupt-parent = <&gpio>;
770 interrupts = <TEGRA_GPIO(J, 0)
771 GPIO_ACTIVE_HIGH>;
772 ti,ac-detect-gpios = <&gpio
773 TEGRA_GPIO(J, 0)
774 GPIO_ACTIVE_HIGH>;
775 };
776
777 battery: sbs-battery@b {
778 compatible = "sbs,sbs-battery";
779 reg = <0xb>;
780 sbs,i2c-retry-count = <2>;
781 sbs,poll-retry-count = <10>;
782 power-supplies = <&charger>;
783 };
784 };
785 };
786 };
787
788 spi@0,7000da00 {
789 status = "okay";
790 spi-max-frequency = <25000000>;
791
792 flash@0 {
793 compatible = "winbond,w25q32dw";
794 reg = <0>;
795 };
796 };
797
798 pmc@0,7000e400 {
799 nvidia,invert-interrupt;
800 nvidia,suspend-mode = <0>;
801 nvidia,cpu-pwr-good-time = <500>;
802 nvidia,cpu-pwr-off-time = <300>;
803 nvidia,core-pwr-good-time = <641 3845>;
804 nvidia,core-pwr-off-time = <61036>;
805 nvidia,core-power-req-active-high;
806 nvidia,sys-clock-req-active-high;
807 };
808
809 hda@0,70030000 {
810 status = "okay";
811 };
812
813 sdhci@0,700b0000 { /* WiFi/BT on this bus */
814 status = "okay";
815 power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
816 bus-width = <4>;
817 no-1-8-v;
818 non-removable;
819 };
820
821 sdhci@0,700b0400 { /* SD Card on this bus */
822 status = "okay";
823 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
824 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
825 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
826 bus-width = <4>;
827 no-1-8-v;
828 vqmmc-supply = <&vddio_sdmmc3>;
829 };
830
831 sdhci@0,700b0600 { /* eMMC on this bus */
832 status = "okay";
833 bus-width = <8>;
834 no-1-8-v;
835 non-removable;
836 };
837
838 ahub@0,70300000 {
839 i2s@0,70301100 {
840 status = "okay";
841 };
842 };
843
844 usb@0,7d000000 { /* Rear external USB port. */
845 status = "okay";
846 };
847
848 usb-phy@0,7d000000 {
849 status = "okay";
850 vbus-supply = <&vdd_usb1_vbus>;
851 };
852
853 usb@0,7d004000 { /* Internal webcam. */
854 status = "okay";
855 };
856
857 usb-phy@0,7d004000 {
858 status = "okay";
859 vbus-supply = <&vdd_run_cam>;
860 };
861
862 usb@0,7d008000 { /* Left external USB port. */
863 status = "okay";
864 };
865
866 usb-phy@0,7d008000 {
867 status = "okay";
868 vbus-supply = <&vdd_usb3_vbus>;
869 };
870
871 backlight: backlight {
872 compatible = "pwm-backlight";
873
874 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
875 power-supply = <&vdd_led>;
876 pwms = <&pwm 1 1000000>;
877
878 default-brightness-level = <224>;
879 brightness-levels =
880 < 0 1 2 3 4 5 6 7
881 8 9 10 11 12 13 14 15
882 16 17 18 19 20 21 22 23
883 24 25 26 27 28 29 30 31
884 32 33 34 35 36 37 38 39
885 40 41 42 43 44 45 46 47
886 48 49 50 51 52 53 54 55
887 56 57 58 59 60 61 62 63
888 64 65 66 67 68 69 70 71
889 72 73 74 75 76 77 78 79
890 80 81 82 83 84 85 86 87
891 88 89 90 91 92 93 94 95
892 96 97 98 99 100 101 102 103
893 104 105 106 107 108 109 110 111
894 112 113 114 115 116 117 118 119
895 120 121 122 123 124 125 126 127
896 128 129 130 131 132 133 134 135
897 136 137 138 139 140 141 142 143
898 144 145 146 147 148 149 150 151
899 152 153 154 155 156 157 158 159
900 160 161 162 163 164 165 166 167
901 168 169 170 171 172 173 174 175
902 176 177 178 179 180 181 182 183
903 184 185 186 187 188 189 190 191
904 192 193 194 195 196 197 198 199
905 200 201 202 203 204 205 206 207
906 208 209 210 211 212 213 214 215
907 216 217 218 219 220 221 222 223
908 224 225 226 227 228 229 230 231
909 232 233 234 235 236 237 238 239
910 240 241 242 243 244 245 246 247
911 248 249 250 251 252 253 254 255
912 256>;
913 };
914
915 clocks {
916 compatible = "simple-bus";
917 #address-cells = <1>;
918 #size-cells = <0>;
919
920 clk32k_in: clock@0 {
921 compatible = "fixed-clock";
922 reg = <0>;
923 #clock-cells = <0>;
924 clock-frequency = <32768>;
925 };
926 };
927
928 gpio-keys {
929 compatible = "gpio-keys";
930
931 lid {
932 label = "Lid";
933 gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
934 linux,input-type = <5>;
935 linux,code = <KEY_RESERVED>;
936 debounce-interval = <1>;
937 gpio-key,wakeup;
938 };
939
940 power {
941 label = "Power";
942 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
943 linux,code = <KEY_POWER>;
944 debounce-interval = <30>;
945 gpio-key,wakeup;
946 };
947 };
948
949 panel: panel {
950 compatible = "auo,b133xtn01";
951
952 backlight = <&backlight>;
953 ddc-i2c-bus = <&dpaux>;
954 };
955
956 regulators {
957 compatible = "simple-bus";
958 #address-cells = <1>;
959 #size-cells = <0>;
960
961 vdd_mux: regulator@0 {
962 compatible = "regulator-fixed";
963 reg = <0>;
964 regulator-name = "+VDD_MUX";
965 regulator-min-microvolt = <12000000>;
966 regulator-max-microvolt = <12000000>;
967 regulator-always-on;
968 regulator-boot-on;
969 };
970
971 vdd_5v0_sys: regulator@1 {
972 compatible = "regulator-fixed";
973 reg = <1>;
974 regulator-name = "+5V_SYS";
975 regulator-min-microvolt = <5000000>;
976 regulator-max-microvolt = <5000000>;
977 regulator-always-on;
978 regulator-boot-on;
979 vin-supply = <&vdd_mux>;
980 };
981
982 vdd_3v3_sys: regulator@2 {
983 compatible = "regulator-fixed";
984 reg = <2>;
985 regulator-name = "+3.3V_SYS";
986 regulator-min-microvolt = <3300000>;
987 regulator-max-microvolt = <3300000>;
988 regulator-always-on;
989 regulator-boot-on;
990 vin-supply = <&vdd_mux>;
991 };
992
993 vdd_3v3_run: regulator@3 {
994 compatible = "regulator-fixed";
995 reg = <3>;
996 regulator-name = "+3.3V_RUN";
997 regulator-min-microvolt = <3300000>;
998 regulator-max-microvolt = <3300000>;
999 regulator-always-on;
1000 regulator-boot-on;
1001 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1002 enable-active-high;
1003 vin-supply = <&vdd_3v3_sys>;
1004 };
1005
1006 vdd_3v3_hdmi: regulator@4 {
1007 compatible = "regulator-fixed";
1008 reg = <4>;
1009 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1010 regulator-min-microvolt = <3300000>;
1011 regulator-max-microvolt = <3300000>;
1012 vin-supply = <&vdd_3v3_run>;
1013 };
1014
1015 vdd_led: regulator@5 {
1016 compatible = "regulator-fixed";
1017 reg = <5>;
1018 regulator-name = "+VDD_LED";
1019 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1020 enable-active-high;
1021 vin-supply = <&vdd_mux>;
1022 };
1023
1024 vdd_5v0_ts: regulator@6 {
1025 compatible = "regulator-fixed";
1026 reg = <6>;
1027 regulator-name = "+5V_VDD_TS_SW";
1028 regulator-min-microvolt = <5000000>;
1029 regulator-max-microvolt = <5000000>;
1030 regulator-boot-on;
1031 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1032 enable-active-high;
1033 vin-supply = <&vdd_5v0_sys>;
1034 };
1035
1036 vdd_usb1_vbus: regulator@7 {
1037 compatible = "regulator-fixed";
1038 reg = <7>;
1039 regulator-name = "+5V_USB_HS";
1040 regulator-min-microvolt = <5000000>;
1041 regulator-max-microvolt = <5000000>;
1042 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1043 enable-active-high;
1044 gpio-open-drain;
1045 vin-supply = <&vdd_5v0_sys>;
1046 };
1047
1048 vdd_usb3_vbus: regulator@8 {
1049 compatible = "regulator-fixed";
1050 reg = <8>;
1051 regulator-name = "+5V_USB_SS";
1052 regulator-min-microvolt = <5000000>;
1053 regulator-max-microvolt = <5000000>;
1054 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1055 enable-active-high;
1056 gpio-open-drain;
1057 vin-supply = <&vdd_5v0_sys>;
1058 };
1059
1060 vdd_3v3_panel: regulator@9 {
1061 compatible = "regulator-fixed";
1062 reg = <9>;
1063 regulator-name = "+3.3V_PANEL";
1064 regulator-min-microvolt = <3300000>;
1065 regulator-max-microvolt = <3300000>;
1066 gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
1067 enable-active-high;
1068 vin-supply = <&vdd_3v3_run>;
1069 };
1070
1071 vdd_3v3_lp0: regulator@10 {
1072 compatible = "regulator-fixed";
1073 reg = <10>;
1074 regulator-name = "+3.3V_LP0";
1075 regulator-min-microvolt = <3300000>;
1076 regulator-max-microvolt = <3300000>;
1077 /*
1078 * TODO: find a way to wire this up with the USB EHCI
1079 * controllers so that it can be enabled on demand.
1080 */
1081 regulator-always-on;
1082 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1083 enable-active-high;
1084 vin-supply = <&vdd_3v3_sys>;
1085 };
1086
1087 vdd_hdmi_pll: regulator@11 {
1088 compatible = "regulator-fixed";
1089 reg = <11>;
1090 regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
1091 regulator-min-microvolt = <1050000>;
1092 regulator-max-microvolt = <1050000>;
1093 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1094 vin-supply = <&vdd_1v05_run>;
1095 };
1096
1097 vdd_5v0_hdmi: regulator@12 {
1098 compatible = "regulator-fixed";
1099 reg = <12>;
1100 regulator-name = "+5V_HDMI_CON";
1101 regulator-min-microvolt = <5000000>;
1102 regulator-max-microvolt = <5000000>;
1103 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1104 enable-active-high;
1105 vin-supply = <&vdd_5v0_sys>;
1106 };
1107 };
1108
1109 sound {
1110 compatible = "nvidia,tegra-audio-max98090-nyan-big",
1111 "nvidia,tegra-audio-max98090";
1112 nvidia,model = "Acer Chromebook 13";
1113
1114 nvidia,audio-routing =
1115 "Headphones", "HPR",
1116 "Headphones", "HPL",
1117 "Speakers", "SPKR",
1118 "Speakers", "SPKL",
1119 "Mic Jack", "MICBIAS",
1120 "DMICL", "Int Mic",
1121 "DMICR", "Int Mic",
1122 "IN34", "Mic Jack";
1123
1124 nvidia,i2s-controller = <&tegra_i2s1>;
1125 nvidia,audio-codec = <&acodec>;
1126
1127 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1128 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1129 <&tegra_car TEGRA124_CLK_EXTERN1>;
1130 clock-names = "pll_a", "pll_a_out0", "mclk";
1131
1132 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
1133 };
1134};
1135
1136#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 70ad91d1a20b..13008858e967 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -36,17 +36,17 @@
36 nvidia,panel = <&panel>; 36 nvidia,panel = <&panel>;
37 }; 37 };
38 38
39 dpaux: dpaux@0,545c0000 { 39 dpaux@0,545c0000 {
40 vdd-supply = <&vdd_3v3_panel>; 40 vdd-supply = <&vdd_3v3_panel>;
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 }; 43 };
44 44
45 pinmux: pinmux@0,70000868 { 45 pinmux: pinmux@0,70000868 {
46 pinctrl-names = "default"; 46 pinctrl-names = "boot";
47 pinctrl-0 = <&pinmux_default>; 47 pinctrl-0 = <&pinmux_boot>;
48 48
49 pinmux_default: common { 49 pinmux_boot: common {
50 dap_mclk1_pw4 { 50 dap_mclk1_pw4 {
51 nvidia,pins = "dap_mclk1_pw4"; 51 nvidia,pins = "dap_mclk1_pw4";
52 nvidia,function = "extperiph1"; 52 nvidia,function = "extperiph1";
@@ -587,7 +587,7 @@
587 status = "okay"; 587 status = "okay";
588 }; 588 };
589 589
590 pwm: pwm@0,7000a000 { 590 pwm@0,7000a000 {
591 status = "okay"; 591 status = "okay";
592 }; 592 };
593 593
@@ -606,6 +606,14 @@
606 i2c@0,7000c400 { 606 i2c@0,7000c400 {
607 status = "okay"; 607 status = "okay";
608 clock-frequency = <100000>; 608 clock-frequency = <100000>;
609
610 trackpad@4b {
611 compatible = "atmel,maxtouch";
612 reg = <0x4b>;
613 interrupt-parent = <&gpio>;
614 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
615 linux,gpio-keymap = <0 0 0 BTN_LEFT>;
616 };
609 }; 617 };
610 618
611 i2c@0,7000c500 { 619 i2c@0,7000c500 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 03916efd6fa9..478c555ebd96 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -12,6 +12,72 @@
12 #address-cells = <2>; 12 #address-cells = <2>;
13 #size-cells = <2>; 13 #size-cells = <2>;
14 14
15 pcie-controller@0,01003000 {
16 compatible = "nvidia,tegra124-pcie";
17 device_type = "pci";
18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21 reg-names = "pads", "afi", "cs";
22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
24 interrupt-names = "intr", "msi";
25
26 #interrupt-cells = <1>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
39
40 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
41 <&tegra_car TEGRA124_CLK_AFI>,
42 <&tegra_car TEGRA124_CLK_PLL_E>,
43 <&tegra_car TEGRA124_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
46 <&tegra_car 72>,
47 <&tegra_car 74>;
48 reset-names = "pex", "afi", "pcie_x";
49 status = "disabled";
50
51 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
52 phy-names = "pcie";
53
54 pci@1,0 {
55 device_type = "pci";
56 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
57 reg = <0x000800 0 0 0 0>;
58 status = "disabled";
59
60 #address-cells = <3>;
61 #size-cells = <2>;
62 ranges;
63
64 nvidia,num-lanes = <2>;
65 };
66
67 pci@2,0 {
68 device_type = "pci";
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
71 status = "disabled";
72
73 #address-cells = <3>;
74 #size-cells = <2>;
75 ranges;
76
77 nvidia,num-lanes = <1>;
78 };
79 };
80
15 host1x@0,50000000 { 81 host1x@0,50000000 {
16 compatible = "nvidia,tegra124-host1x", "simple-bus"; 82 compatible = "nvidia,tegra124-host1x", "simple-bus";
17 reg = <0x0 0x50000000 0x0 0x00034000>; 83 reg = <0x0 0x50000000 0x0 0x00034000>;
@@ -78,7 +144,7 @@
78 status = "disabled"; 144 status = "disabled";
79 }; 145 };
80 146
81 dpaux@0,545c0000 { 147 dpaux: dpaux@0,545c0000 {
82 compatible = "nvidia,tegra124-dpaux"; 148 compatible = "nvidia,tegra124-dpaux";
83 reg = <0x0 0x545c0000 0x0 0x00040000>; 149 reg = <0x0 0x545c0000 0x0 0x00040000>;
84 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 150 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@@ -137,6 +203,11 @@
137 #reset-cells = <1>; 203 #reset-cells = <1>;
138 }; 204 };
139 205
206 flow-controller@0,60007000 {
207 compatible = "nvidia,tegra124-flowctrl";
208 reg = <0x0 0x60007000 0x0 0x1000>;
209 };
210
140 gpio: gpio@0,6000d000 { 211 gpio: gpio@0,6000d000 {
141 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 212 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
142 reg = <0x0 0x6000d000 0x0 0x1000>; 213 reg = <0x0 0x6000d000 0x0 0x1000>;
@@ -267,7 +338,7 @@
267 status = "disabled"; 338 status = "disabled";
268 }; 339 };
269 340
270 pwm@0,7000a000 { 341 pwm: pwm@0,7000a000 {
271 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 342 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
272 reg = <0x0 0x7000a000 0x0 0x100>; 343 reg = <0x0 0x7000a000 0x0 0x100>;
273 #pwm-cells = <2>; 344 #pwm-cells = <2>;
@@ -480,6 +551,31 @@
480 reset-names = "fuse"; 551 reset-names = "fuse";
481 }; 552 };
482 553
554 sata@0,70020000 {
555 compatible = "nvidia,tegra124-ahci";
556
557 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
558 <0x0 0x70020000 0x0 0x7000>; /* SATA */
559
560 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
561
562 clocks = <&tegra_car TEGRA124_CLK_SATA>,
563 <&tegra_car TEGRA124_CLK_SATA_OOB>,
564 <&tegra_car TEGRA124_CLK_CML1>,
565 <&tegra_car TEGRA124_CLK_PLL_E>;
566 clock-names = "sata", "sata-oob", "cml1", "pll_e";
567
568 resets = <&tegra_car 124>,
569 <&tegra_car 123>,
570 <&tegra_car 129>;
571 reset-names = "sata", "sata-oob", "sata-cold";
572
573 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
574 phy-names = "sata-phy";
575
576 status = "disabled";
577 };
578
483 hda@0,70030000 { 579 hda@0,70030000 {
484 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 580 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
485 reg = <0x0 0x70030000 0x0 0x10000>; 581 reg = <0x0 0x70030000 0x0 0x10000>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 1908f6937e53..3b374c49d04d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -190,6 +190,11 @@
190 #reset-cells = <1>; 190 #reset-cells = <1>;
191 }; 191 };
192 192
193 flow-controller@60007000 {
194 compatible = "nvidia,tegra20-flowctrl";
195 reg = <0x60007000 0x1000>;
196 };
197
193 apbdma: dma@6000a000 { 198 apbdma: dma@6000a000 {
194 compatible = "nvidia,tegra20-apbdma"; 199 compatible = "nvidia,tegra20-apbdma";
195 reg = <0x6000a000 0x1200>; 200 reg = <0x6000a000 0x1200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 6b35c29278d7..aa6ccea13d30 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -272,6 +272,11 @@
272 #reset-cells = <1>; 272 #reset-cells = <1>;
273 }; 273 };
274 274
275 flow-controller@60007000 {
276 compatible = "nvidia,tegra30-flowctrl";
277 reg = <0x60007000 0x1000>;
278 };
279
275 apbdma: dma@6000a000 { 280 apbdma: dma@6000a000 {
276 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 281 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
277 reg = <0x6000a000 0x1400>; 282 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 756c986995a3..2efb2058ba49 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -41,7 +41,7 @@
41 bank-width = <4>; 41 bank-width = <4>;
42 }; 42 };
43 43
44 vram@2,00000000 { 44 v2m_video_ram: vram@2,00000000 {
45 compatible = "arm,vexpress-vram"; 45 compatible = "arm,vexpress-vram";
46 reg = <2 0x00000000 0x00800000>; 46 reg = <2 0x00000000 0x00800000>;
47 }; 47 };
@@ -246,9 +246,41 @@
246 clcd@1f0000 { 246 clcd@1f0000 {
247 compatible = "arm,pl111", "arm,primecell"; 247 compatible = "arm,pl111", "arm,primecell";
248 reg = <0x1f0000 0x1000>; 248 reg = <0x1f0000 0x1000>;
249 interrupt-names = "combined";
249 interrupts = <14>; 250 interrupts = <14>;
250 clocks = <&v2m_oscclk1>, <&smbclk>; 251 clocks = <&v2m_oscclk1>, <&smbclk>;
251 clock-names = "clcdclk", "apb_pclk"; 252 clock-names = "clcdclk", "apb_pclk";
253 memory-region = <&v2m_video_ram>;
254 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
255
256 port {
257 v2m_clcd_pads: endpoint {
258 remote-endpoint = <&v2m_clcd_panel>;
259 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
260 };
261 };
262
263 panel {
264 compatible = "panel-dpi";
265
266 port {
267 v2m_clcd_panel: endpoint {
268 remote-endpoint = <&v2m_clcd_pads>;
269 };
270 };
271
272 panel-timing {
273 clock-frequency = <25175000>;
274 hactive = <640>;
275 hback-porch = <40>;
276 hfront-porch = <24>;
277 hsync-len = <96>;
278 vactive = <480>;
279 vback-porch = <32>;
280 vfront-porch = <11>;
281 vsync-len = <2>;
282 };
283 };
252 }; 284 };
253 }; 285 };
254 286
@@ -350,7 +382,7 @@
350 /* CLCD clock */ 382 /* CLCD clock */
351 compatible = "arm,vexpress-osc"; 383 compatible = "arm,vexpress-osc";
352 arm,vexpress-sysreg,func = <1 1>; 384 arm,vexpress-sysreg,func = <1 1>;
353 freq-range = <23750000 63500000>; 385 freq-range = <23750000 65000000>;
354 #clock-cells = <0>; 386 #clock-cells = <0>;
355 clock-output-names = "v2m:oscclk1"; 387 clock-output-names = "v2m:oscclk1";
356 }; 388 };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index ba856d604fb7..cb3090f919a7 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -40,7 +40,7 @@
40 bank-width = <4>; 40 bank-width = <4>;
41 }; 41 };
42 42
43 vram@3,00000000 { 43 v2m_video_ram: vram@3,00000000 {
44 compatible = "arm,vexpress-vram"; 44 compatible = "arm,vexpress-vram";
45 reg = <3 0x00000000 0x00800000>; 45 reg = <3 0x00000000 0x00800000>;
46 }; 46 };
@@ -245,9 +245,41 @@
245 clcd@1f000 { 245 clcd@1f000 {
246 compatible = "arm,pl111", "arm,primecell"; 246 compatible = "arm,pl111", "arm,primecell";
247 reg = <0x1f000 0x1000>; 247 reg = <0x1f000 0x1000>;
248 interrupt-names = "combined";
248 interrupts = <14>; 249 interrupts = <14>;
249 clocks = <&v2m_oscclk1>, <&smbclk>; 250 clocks = <&v2m_oscclk1>, <&smbclk>;
250 clock-names = "clcdclk", "apb_pclk"; 251 clock-names = "clcdclk", "apb_pclk";
252 memory-region = <&v2m_video_ram>;
253 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
254
255 port {
256 v2m_clcd_pads: endpoint {
257 remote-endpoint = <&v2m_clcd_panel>;
258 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
259 };
260 };
261
262 panel {
263 compatible = "panel-dpi";
264
265 port {
266 v2m_clcd_panel: endpoint {
267 remote-endpoint = <&v2m_clcd_pads>;
268 };
269 };
270
271 panel-timing {
272 clock-frequency = <25175000>;
273 hactive = <640>;
274 hback-porch = <40>;
275 hfront-porch = <24>;
276 hsync-len = <96>;
277 vactive = <480>;
278 vback-porch = <32>;
279 vfront-porch = <11>;
280 vsync-len = <2>;
281 };
282 };
251 }; 283 };
252 }; 284 };
253 285
@@ -349,7 +381,7 @@
349 /* CLCD clock */ 381 /* CLCD clock */
350 compatible = "arm,vexpress-osc"; 382 compatible = "arm,vexpress-osc";
351 arm,vexpress-sysreg,func = <1 1>; 383 arm,vexpress-sysreg,func = <1 1>;
352 freq-range = <23750000 63500000>; 384 freq-range = <23750000 65000000>;
353 #clock-cells = <0>; 385 #clock-cells = <0>;
354 clock-output-names = "v2m:oscclk1"; 386 clock-output-names = "v2m:oscclk1";
355 }; 387 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index a25c262326dc..322fd1519b09 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -38,6 +38,7 @@
38 compatible = "arm,cortex-a15"; 38 compatible = "arm,cortex-a15";
39 reg = <0>; 39 reg = <0>;
40 cci-control-port = <&cci_control1>; 40 cci-control-port = <&cci_control1>;
41 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
41 }; 42 };
42 43
43 cpu1: cpu@1 { 44 cpu1: cpu@1 {
@@ -45,6 +46,7 @@
45 compatible = "arm,cortex-a15"; 46 compatible = "arm,cortex-a15";
46 reg = <1>; 47 reg = <1>;
47 cci-control-port = <&cci_control1>; 48 cci-control-port = <&cci_control1>;
49 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
48 }; 50 };
49 51
50 cpu2: cpu@2 { 52 cpu2: cpu@2 {
@@ -52,6 +54,7 @@
52 compatible = "arm,cortex-a7"; 54 compatible = "arm,cortex-a7";
53 reg = <0x100>; 55 reg = <0x100>;
54 cci-control-port = <&cci_control2>; 56 cci-control-port = <&cci_control2>;
57 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
55 }; 58 };
56 59
57 cpu3: cpu@3 { 60 cpu3: cpu@3 {
@@ -59,6 +62,7 @@
59 compatible = "arm,cortex-a7"; 62 compatible = "arm,cortex-a7";
60 reg = <0x101>; 63 reg = <0x101>;
61 cci-control-port = <&cci_control2>; 64 cci-control-port = <&cci_control2>;
65 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
62 }; 66 };
63 67
64 cpu4: cpu@4 { 68 cpu4: cpu@4 {
@@ -66,6 +70,25 @@
66 compatible = "arm,cortex-a7"; 70 compatible = "arm,cortex-a7";
67 reg = <0x102>; 71 reg = <0x102>;
68 cci-control-port = <&cci_control2>; 72 cci-control-port = <&cci_control2>;
73 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
74 };
75
76 idle-states {
77 CLUSTER_SLEEP_BIG: cluster-sleep-big {
78 compatible = "arm,idle-state";
79 local-timer-stop;
80 entry-latency-us = <1000>;
81 exit-latency-us = <700>;
82 min-residency-us = <2000>;
83 };
84
85 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
86 compatible = "arm,idle-state";
87 local-timer-stop;
88 entry-latency-us = <1000>;
89 exit-latency-us = <500>;
90 min-residency-us = <2500>;
91 };
69 }; 92 };
70 }; 93 };
71 94
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 62d9b225dcce..23662b5a5e9d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -70,9 +70,40 @@
70 clcd@10020000 { 70 clcd@10020000 {
71 compatible = "arm,pl111", "arm,primecell"; 71 compatible = "arm,pl111", "arm,primecell";
72 reg = <0x10020000 0x1000>; 72 reg = <0x10020000 0x1000>;
73 interrupt-names = "combined";
73 interrupts = <0 44 4>; 74 interrupts = <0 44 4>;
74 clocks = <&oscclk1>, <&oscclk2>; 75 clocks = <&oscclk1>, <&oscclk2>;
75 clock-names = "clcdclk", "apb_pclk"; 76 clock-names = "clcdclk", "apb_pclk";
77 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
78
79 port {
80 clcd_pads: endpoint {
81 remote-endpoint = <&clcd_panel>;
82 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
83 };
84 };
85
86 panel {
87 compatible = "panel-dpi";
88
89 port {
90 clcd_panel: endpoint {
91 remote-endpoint = <&clcd_pads>;
92 };
93 };
94
95 panel-timing {
96 clock-frequency = <63500127>;
97 hactive = <1024>;
98 hback-porch = <152>;
99 hfront-porch = <48>;
100 hsync-len = <104>;
101 vactive = <768>;
102 vback-porch = <23>;
103 vfront-porch = <3>;
104 vsync-len = <4>;
105 };
106 };
76 }; 107 };
77 108
78 memory-controller@100e0000 { 109 memory-controller@100e0000 {
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7fb306679341
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/dts-v1/;
11#include "vf610-colibri.dtsi"
12
13/ {
14 model = "Toradex Colibri VF61 on Colibri Evaluation Board";
15 compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
16
17 chosen {
18 bootargs = "console=ttyLP0,115200";
19 };
20};
21
22&esdhc1 {
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_esdhc1>;
25 bus-width = <4>;
26 status = "okay";
27};
28
29&fec1 {
30 phy-mode = "rmii";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_fec1>;
33 status = "okay";
34};
35
36&uart0 {
37 status = "okay";
38};
39
40&uart1 {
41 status = "okay";
42};
43
44&uart2 {
45 status = "okay";
46};
diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dtsi
index aecc7dbc65e8..0cd83434b073 100644
--- a/arch/arm/boot/dts/vf610-colibri.dts
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -7,16 +7,11 @@
7 * (at your option) any later version. 7 * (at your option) any later version.
8 */ 8 */
9 9
10/dts-v1/;
11#include "vf610.dtsi" 10#include "vf610.dtsi"
12 11
13/ { 12/ {
14 model = "Toradex Colibri VF61 COM"; 13 model = "Toradex Colibri VF61 COM";
15 compatible = "toradex,vf610-colibri", "fsl,vf610"; 14 compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
16
17 chosen {
18 bootargs = "console=ttyLP0,115200";
19 };
20 15
21 memory { 16 memory {
22 reg = <0x80000000 0x10000000>; 17 reg = <0x80000000 0x10000000>;
@@ -36,14 +31,12 @@
36 pinctrl-names = "default"; 31 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc1>; 32 pinctrl-0 = <&pinctrl_esdhc1>;
38 bus-width = <4>; 33 bus-width = <4>;
39 status = "okay";
40}; 34};
41 35
42&fec1 { 36&fec1 {
43 phy-mode = "rmii"; 37 phy-mode = "rmii";
44 pinctrl-names = "default"; 38 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_fec1>; 39 pinctrl-0 = <&pinctrl_fec1>;
46 status = "okay";
47}; 40};
48 41
49&L2 { 42&L2 {
@@ -54,25 +47,32 @@
54&uart0 { 47&uart0 {
55 pinctrl-names = "default"; 48 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_uart0>; 49 pinctrl-0 = <&pinctrl_uart0>;
57 status = "okay";
58}; 50};
59 51
60&uart1 { 52&uart1 {
61 pinctrl-names = "default"; 53 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_uart1>; 54 pinctrl-0 = <&pinctrl_uart1>;
63 status = "okay";
64}; 55};
65 56
66&uart2 { 57&uart2 {
67 pinctrl-names = "default"; 58 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_uart2>; 59 pinctrl-0 = <&pinctrl_uart2>;
60};
61
62&usbdev0 {
63 disable-over-current;
64 status = "okay";
65};
66
67&usbh1 {
68 disable-over-current;
69 status = "okay"; 69 status = "okay";
70}; 70};
71 71
72&iomuxc { 72&iomuxc {
73 vf610-colibri { 73 vf610-colibri {
74 pinctrl_esdhc1: esdhc1grp { 74 pinctrl_esdhc1: esdhc1grp {
75 fsl,fsl,pins = < 75 fsl,pins = <
76 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 76 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
77 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 77 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
78 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 78 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index b8a5e8c68f06..189b6975fe7d 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -76,7 +76,6 @@
76 76
77 simple-audio-card,cpu { 77 simple-audio-card,cpu {
78 sound-dai = <&sai2>; 78 sound-dai = <&sai2>;
79 master-clkdir-out;
80 frame-master; 79 frame-master;
81 bitclock-master; 80 bitclock-master;
82 }; 81 };
@@ -221,8 +220,6 @@
221 VF610_PAD_PTB1__FTM0_CH1 0x1582 220 VF610_PAD_PTB1__FTM0_CH1 0x1582
222 VF610_PAD_PTB2__FTM0_CH2 0x1582 221 VF610_PAD_PTB2__FTM0_CH2 0x1582
223 VF610_PAD_PTB3__FTM0_CH3 0x1582 222 VF610_PAD_PTB3__FTM0_CH3 0x1582
224 VF610_PAD_PTB6__FTM0_CH6 0x1582
225 VF610_PAD_PTB7__FTM0_CH7 0x1582
226 >; 223 >;
227 }; 224 };
228 225
@@ -244,6 +241,13 @@
244 VF610_PAD_PTB5__UART1_RX 0x21a1 241 VF610_PAD_PTB5__UART1_RX 0x21a1
245 >; 242 >;
246 }; 243 };
244
245 pinctrl_uart2: uart2grp {
246 fsl,pins = <
247 VF610_PAD_PTB6__UART2_TX 0x21a2
248 VF610_PAD_PTB7__UART2_RX 0x21a1
249 >;
250 };
247 }; 251 };
248}; 252};
249 253
@@ -265,3 +269,19 @@
265 pinctrl-0 = <&pinctrl_uart1>; 269 pinctrl-0 = <&pinctrl_uart1>;
266 status = "okay"; 270 status = "okay";
267}; 271};
272
273&uart2 {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_uart2>;
276 status = "okay";
277};
278
279&usbdev0 {
280 disable-over-current;
281 status = "okay";
282};
283
284&usbh1 {
285 disable-over-current;
286 status = "okay";
287};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 583dd363c9dc..4d2ec32de96f 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -27,6 +27,8 @@
27 gpio2 = &gpio3; 27 gpio2 = &gpio3;
28 gpio3 = &gpio4; 28 gpio3 = &gpio4;
29 gpio4 = &gpio5; 29 gpio4 = &gpio5;
30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
30 }; 32 };
31 33
32 cpus { 34 cpus {
@@ -297,9 +299,25 @@
297 gpio-ranges = <&iomuxc 0 128 7>; 299 gpio-ranges = <&iomuxc 0 128 7>;
298 }; 300 };
299 301
300 anatop@40050000 { 302 anatop: anatop@40050000 {
301 compatible = "fsl,vf610-anatop"; 303 compatible = "fsl,vf610-anatop", "syscon";
302 reg = <0x40050000 0x1000>; 304 reg = <0x40050000 0x400>;
305 };
306
307 usbphy0: usbphy@40050800 {
308 compatible = "fsl,vf610-usbphy";
309 reg = <0x40050800 0x400>;
310 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks VF610_CLK_USBPHY0>;
312 fsl,anatop = <&anatop>;
313 };
314
315 usbphy1: usbphy@40050c00 {
316 compatible = "fsl,vf610-usbphy";
317 reg = <0x40050c00 0x400>;
318 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks VF610_CLK_USBPHY1>;
320 fsl,anatop = <&anatop>;
303 }; 321 };
304 322
305 i2c0: i2c@40066000 { 323 i2c0: i2c@40066000 {
@@ -321,6 +339,24 @@
321 reg = <0x4006b000 0x1000>; 339 reg = <0x4006b000 0x1000>;
322 #clock-cells = <1>; 340 #clock-cells = <1>;
323 }; 341 };
342
343 usbdev0: usb@40034000 {
344 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
345 reg = <0x40034000 0x800>;
346 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks VF610_CLK_USBC0>;
348 fsl,usbphy = <&usbphy0>;
349 fsl,usbmisc = <&usbmisc0 0>;
350 dr_mode = "peripheral";
351 status = "disabled";
352 };
353
354 usbmisc0: usb@40034800 {
355 #index-cells = <1>;
356 compatible = "fsl,vf610-usbmisc";
357 reg = <0x40034800 0x200>;
358 clocks = <&clks VF610_CLK_USBC0>;
359 };
324 }; 360 };
325 361
326 aips1: aips-bus@40080000 { 362 aips1: aips-bus@40080000 {
@@ -383,6 +419,24 @@
383 status = "disabled"; 419 status = "disabled";
384 }; 420 };
385 421
422 usbh1: usb@400b4000 {
423 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
424 reg = <0x400b4000 0x800>;
425 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks VF610_CLK_USBC1>;
427 fsl,usbphy = <&usbphy1>;
428 fsl,usbmisc = <&usbmisc1 0>;
429 dr_mode = "host";
430 status = "disabled";
431 };
432
433 usbmisc1: usb@400b4800 {
434 #index-cells = <1>;
435 compatible = "fsl,vf610-usbmisc";
436 reg = <0x400b4800 0x200>;
437 clocks = <&clks VF610_CLK_USBC1>;
438 };
439
386 ftm: ftm@400b8000 { 440 ftm: ftm@400b8000 {
387 compatible = "fsl,ftm-timer"; 441 compatible = "fsl,ftm-timer";
388 reg = <0x400b8000 0x1000 0x400b9000 0x1000>; 442 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6cc83d4c6c76..24036c440440 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -146,6 +146,11 @@
146 cache-level = <2>; 146 cache-level = <2>;
147 }; 147 };
148 148
149 memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>;
152 } ;
153
149 uart0: serial@e0000000 { 154 uart0: serial@e0000000 {
150 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 155 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
151 status = "disabled"; 156 status = "disabled";
@@ -195,6 +200,8 @@
195 interrupts = <0 22 4>; 200 interrupts = <0 22 4>;
196 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
197 clock-names = "pclk", "hclk", "tx_clk"; 202 clock-names = "pclk", "hclk", "tx_clk";
203 #address-cells = <1>;
204 #size-cells = <0>;
198 }; 205 };
199 206
200 gem1: ethernet@e000c000 { 207 gem1: ethernet@e000c000 {
@@ -204,6 +211,8 @@
204 interrupts = <0 45 4>; 211 interrupts = <0 45 4>;
205 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
206 clock-names = "pclk", "hclk", "tx_clk"; 213 clock-names = "pclk", "hclk", "tx_clk";
214 #address-cells = <1>;
215 #size-cells = <0>;
207 }; 216 };
208 217
209 sdhci0: sdhci@e0100000 { 218 sdhci0: sdhci@e0100000 {
@@ -214,7 +223,7 @@
214 interrupt-parent = <&intc>; 223 interrupt-parent = <&intc>;
215 interrupts = <0 24 4>; 224 interrupts = <0 24 4>;
216 reg = <0xe0100000 0x1000>; 225 reg = <0xe0100000 0x1000>;
217 } ; 226 };
218 227
219 sdhci1: sdhci@e0101000 { 228 sdhci1: sdhci@e0101000 {
220 compatible = "arasan,sdhci-8.9a"; 229 compatible = "arasan,sdhci-8.9a";
@@ -224,7 +233,7 @@
224 interrupt-parent = <&intc>; 233 interrupt-parent = <&intc>;
225 interrupts = <0 47 4>; 234 interrupts = <0 47 4>;
226 reg = <0xe0101000 0x1000>; 235 reg = <0xe0101000 0x1000>;
227 } ; 236 };
228 237
229 slcr: slcr@f8000000 { 238 slcr: slcr@f8000000 {
230 #address-cells = <1>; 239 #address-cells = <1>;
@@ -256,6 +265,8 @@
256 compatible = "arm,pl330", "arm,primecell"; 265 compatible = "arm,pl330", "arm,primecell";
257 reg = <0xf8003000 0x1000>; 266 reg = <0xf8003000 0x1000>;
258 interrupt-parent = <&intc>; 267 interrupt-parent = <&intc>;
268 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
269 "dma4", "dma5", "dma6", "dma7";
259 interrupts = <0 13 4>, 270 interrupts = <0 13 4>,
260 <0 14 4>, <0 15 4>, 271 <0 14 4>, <0 15 4>,
261 <0 16 4>, <0 17 4>, 272 <0 16 4>, <0 17 4>,
@@ -271,7 +282,7 @@
271 devcfg: devcfg@f8007000 { 282 devcfg: devcfg@f8007000 {
272 compatible = "xlnx,zynq-devcfg-1.0"; 283 compatible = "xlnx,zynq-devcfg-1.0";
273 reg = <0xf8007000 0x100>; 284 reg = <0xf8007000 0x100>;
274 } ; 285 };
275 286
276 global_timer: timer@f8f00200 { 287 global_timer: timer@f8f00200 {
277 compatible = "arm,cortex-a9-global-timer"; 288 compatible = "arm,cortex-a9-global-timer";
@@ -303,6 +314,6 @@
303 compatible = "arm,cortex-a9-twd-timer"; 314 compatible = "arm,cortex-a9-twd-timer";
304 reg = <0xf8f00600 0x20>; 315 reg = <0xf8f00600 0x20>;
305 clocks = <&clkc 4>; 316 clocks = <&clkc 4>;
306 } ; 317 };
307 }; 318 };
308}; 319};
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 41afd9da6876..e1f51ca127fe 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -25,7 +25,7 @@
25 25
26 memory { 26 memory {
27 device_type = "memory"; 27 device_type = "memory";
28 reg = <0 0x40000000>; 28 reg = <0x0 0x40000000>;
29 }; 29 };
30 30
31 chosen { 31 chosen {
@@ -38,8 +38,6 @@
38 status = "okay"; 38 status = "okay";
39 phy-mode = "rgmii-id"; 39 phy-mode = "rgmii-id";
40 phy-handle = <&ethernet_phy>; 40 phy-handle = <&ethernet_phy>;
41 #address-cells = <1>;
42 #size-cells = <0>;
43 41
44 ethernet_phy: ethernet-phy@0 { 42 ethernet_phy: ethernet-phy@0 {
45 /* Marvell 88E1318 */ 43 /* Marvell 88E1318 */
@@ -53,6 +51,29 @@
53 51
54&i2c0 { 52&i2c0 {
55 status = "okay"; 53 status = "okay";
54
55 isl9305: isl9305@68 {
56 compatible = "isl,isl9305";
57 reg = <0x68>;
58
59 regulators {
60 dcd1 {
61 regulator-name = "VDD_DSP";
62 regulator-always-on;
63 };
64 dcd2 {
65 regulator-name = "1P35V";
66 regulator-always-on;
67 };
68 ldo1 {
69 regulator-name = "VDD_ADJ";
70 };
71 ldo2 {
72 regulator-name = "VDD_GPIO";
73 regulator-always-on;
74 };
75 };
76 };
56}; 77};
57 78
58&sdhci1 { 79&sdhci1 {
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 835c3089c61c..94e2cda6f9b6 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2011 Xilinx 2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp. 3 * Copyright (C) 2012 National Instruments Corp.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
@@ -27,6 +27,15 @@
27 bootargs = "console=ttyPS0,115200 earlyprintk"; 27 bootargs = "console=ttyPS0,115200 earlyprintk";
28 }; 28 };
29 29
30 leds {
31 compatible = "gpio-leds";
32
33 ds23 {
34 label = "ds23";
35 gpios = <&gpio0 10 0>;
36 linux,default-trigger = "heartbeat";
37 };
38 };
30}; 39};
31 40
32&can0 { 41&can0 {
@@ -35,7 +44,12 @@
35 44
36&gem0 { 45&gem0 {
37 status = "okay"; 46 status = "okay";
38 phy-mode = "rgmii"; 47 phy-mode = "rgmii-id";
48 phy-handle = <&ethernet_phy>;
49
50 ethernet_phy: ethernet-phy@7 {
51 reg = <7>;
52 };
39}; 53};
40 54
41&i2c0 { 55&i2c0 {
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 4cc9913078cd..a8bbdfbc7093 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -1,7 +1,6 @@
1/* 1/*
2 * Copyright (C) 2011 Xilinx 2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp. 3 * Copyright (C) 2012 National Instruments Corp.
4 * Copyright (C) 2013 Xilinx
5 * 4 *
6 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -21,7 +20,7 @@
21 20
22 memory { 21 memory {
23 device_type = "memory"; 22 device_type = "memory";
24 reg = <0 0x40000000>; 23 reg = <0x0 0x40000000>;
25 }; 24 };
26 25
27 chosen { 26 chosen {
@@ -32,7 +31,12 @@
32 31
33&gem0 { 32&gem0 {
34 status = "okay"; 33 status = "okay";
35 phy-mode = "rgmii"; 34 phy-mode = "rgmii-id";
35 phy-handle = <&ethernet_phy>;
36
37 ethernet_phy: ethernet-phy@7 {
38 reg = <7>;
39 };
36}; 40};
37 41
38&i2c0 { 42&i2c0 {
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 82d7ef1a9a9c..697779a353ed 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -1,7 +1,6 @@
1/* 1/*
2 * Copyright (C) 2011 Xilinx 2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp. 3 * Copyright (C) 2012 National Instruments Corp.
4 * Copyright (C) 2013 Xilinx
5 * 4 *
6 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -17,11 +16,11 @@
17 16
18/ { 17/ {
19 model = "Zynq Zed Development Board"; 18 model = "Zynq Zed Development Board";
20 compatible = "xlnx,zynq-7000"; 19 compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
21 20
22 memory { 21 memory {
23 device_type = "memory"; 22 device_type = "memory";
24 reg = <0 0x20000000>; 23 reg = <0x0 0x20000000>;
25 }; 24 };
26 25
27 chosen { 26 chosen {
@@ -32,7 +31,12 @@
32 31
33&gem0 { 32&gem0 {
34 status = "okay"; 33 status = "okay";
35 phy-mode = "rgmii"; 34 phy-mode = "rgmii-id";
35 phy-handle = <&ethernet_phy>;
36
37 ethernet_phy: ethernet-phy@0 {
38 reg = <0>;
39 };
36}; 40};
37 41
38&sdhci0 { 42&sdhci0 {
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index a20fa80776d3..45f4c21e393c 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -243,18 +243,12 @@ err_ioremap:
243static int scoop_remove(struct platform_device *pdev) 243static int scoop_remove(struct platform_device *pdev)
244{ 244{
245 struct scoop_dev *sdev = platform_get_drvdata(pdev); 245 struct scoop_dev *sdev = platform_get_drvdata(pdev);
246 int ret;
247 246
248 if (!sdev) 247 if (!sdev)
249 return -EINVAL; 248 return -EINVAL;
250 249
251 if (sdev->gpio.base != -1) { 250 if (sdev->gpio.base != -1)
252 ret = gpiochip_remove(&sdev->gpio); 251 gpiochip_remove(&sdev->gpio);
253 if (ret) {
254 dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret);
255 return ret;
256 }
257 }
258 252
259 platform_set_drvdata(pdev, NULL); 253 platform_set_drvdata(pdev, NULL);
260 iounmap(sdev->base); 254 iounmap(sdev->base);
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index bb396c0e5fda..b54b28fc5a70 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -12,7 +12,6 @@ CONFIG_KALLSYMS_ALL=y
12CONFIG_EMBEDDED=y 12CONFIG_EMBEDDED=y
13CONFIG_PERF_EVENTS=y 13CONFIG_PERF_EVENTS=y
14CONFIG_SLAB=y 14CONFIG_SLAB=y
15# CONFIG_BLOCK is not set
16CONFIG_ARCH_SHMOBILE_LEGACY=y 15CONFIG_ARCH_SHMOBILE_LEGACY=y
17CONFIG_ARCH_R8A73A4=y 16CONFIG_ARCH_R8A73A4=y
18CONFIG_MACH_APE6EVM=y 17CONFIG_MACH_APE6EVM=y
@@ -64,6 +63,8 @@ CONFIG_SERIAL_NONSTANDARD=y
64CONFIG_SERIAL_SH_SCI=y 63CONFIG_SERIAL_SH_SCI=y
65CONFIG_SERIAL_SH_SCI_NR_UARTS=12 64CONFIG_SERIAL_SH_SCI_NR_UARTS=12
66CONFIG_SERIAL_SH_SCI_CONSOLE=y 65CONFIG_SERIAL_SH_SCI_CONSOLE=y
66CONFIG_I2C=y
67CONFIG_I2C_SH_MOBILE=y
67CONFIG_GPIO_SH_PFC=y 68CONFIG_GPIO_SH_PFC=y
68CONFIG_GPIOLIB=y 69CONFIG_GPIOLIB=y
69# CONFIG_HWMON is not set 70# CONFIG_HWMON is not set
@@ -72,11 +73,17 @@ CONFIG_RCAR_THERMAL=y
72CONFIG_REGULATOR=y 73CONFIG_REGULATOR=y
73CONFIG_REGULATOR_FIXED_VOLTAGE=y 74CONFIG_REGULATOR_FIXED_VOLTAGE=y
74CONFIG_REGULATOR_GPIO=y 75CONFIG_REGULATOR_GPIO=y
76CONFIG_REGULATOR_MAX8973=y
75# CONFIG_HID is not set 77# CONFIG_HID is not set
76# CONFIG_USB_SUPPORT is not set 78# CONFIG_USB_SUPPORT is not set
79CONFIG_MMC=y
80CONFIG_MMC_SDHI=y
81CONFIG_MMC_SH_MMCIF=y
77CONFIG_NEW_LEDS=y 82CONFIG_NEW_LEDS=y
78CONFIG_LEDS_CLASS=y 83CONFIG_LEDS_CLASS=y
79CONFIG_LEDS_GPIO=y 84CONFIG_LEDS_GPIO=y
85CONFIG_DMADEVICES=y
86CONFIG_SH_DMAE=y
80# CONFIG_IOMMU_SUPPORT is not set 87# CONFIG_IOMMU_SUPPORT is not set
81# CONFIG_DNOTIFY is not set 88# CONFIG_DNOTIFY is not set
82CONFIG_TMPFS=y 89CONFIG_TMPFS=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 300ded9acbe9..3b515c179487 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -18,15 +18,14 @@ CONFIG_SOC_AT91RM9200=y
18CONFIG_SOC_AT91SAM9260=y 18CONFIG_SOC_AT91SAM9260=y
19CONFIG_SOC_AT91SAM9261=y 19CONFIG_SOC_AT91SAM9261=y
20CONFIG_SOC_AT91SAM9263=y 20CONFIG_SOC_AT91SAM9263=y
21CONFIG_SOC_AT91SAM9RL=y
21CONFIG_SOC_AT91SAM9G45=y 22CONFIG_SOC_AT91SAM9G45=y
22CONFIG_SOC_AT91SAM9X5=y 23CONFIG_SOC_AT91SAM9X5=y
23CONFIG_SOC_AT91SAM9N12=y 24CONFIG_SOC_AT91SAM9N12=y
24CONFIG_SOC_AT91SAM9RL=y
25CONFIG_MACH_AT91RM9200_DT=y 25CONFIG_MACH_AT91RM9200_DT=y
26CONFIG_MACH_AT91SAM9_DT=y 26CONFIG_MACH_AT91SAM9_DT=y
27CONFIG_AT91_TIMER_HZ=128 27CONFIG_AT91_TIMER_HZ=128
28CONFIG_AEABI=y 28CONFIG_AEABI=y
29# CONFIG_OABI_COMPAT is not set
30CONFIG_UACCESS_WITH_MEMCPY=y 29CONFIG_UACCESS_WITH_MEMCPY=y
31CONFIG_ZBOOT_ROM_TEXT=0x0 30CONFIG_ZBOOT_ROM_TEXT=0x0
32CONFIG_ZBOOT_ROM_BSS=0x0 31CONFIG_ZBOOT_ROM_BSS=0x0
@@ -63,23 +62,20 @@ CONFIG_DEVTMPFS_MOUNT=y
63# CONFIG_PREVENT_FIRMWARE_BUILD is not set 62# CONFIG_PREVENT_FIRMWARE_BUILD is not set
64CONFIG_MTD=y 63CONFIG_MTD=y
65CONFIG_MTD_CMDLINE_PARTS=y 64CONFIG_MTD_CMDLINE_PARTS=y
66CONFIG_MTD_CHAR=y
67CONFIG_MTD_BLOCK=y 65CONFIG_MTD_BLOCK=y
68CONFIG_MTD_DATAFLASH=y 66CONFIG_MTD_DATAFLASH=y
69CONFIG_MTD_NAND=y 67CONFIG_MTD_NAND=y
70CONFIG_MTD_NAND_ATMEL=y 68CONFIG_MTD_NAND_ATMEL=y
71CONFIG_MTD_UBI=y 69CONFIG_MTD_UBI=y
72CONFIG_MTD_UBI_GLUEBI=y 70CONFIG_MTD_UBI_GLUEBI=y
73CONFIG_PROC_DEVICETREE=y
74CONFIG_BLK_DEV_LOOP=y 71CONFIG_BLK_DEV_LOOP=y
75CONFIG_BLK_DEV_RAM=y 72CONFIG_BLK_DEV_RAM=y
76CONFIG_BLK_DEV_RAM_COUNT=4 73CONFIG_BLK_DEV_RAM_COUNT=4
77CONFIG_BLK_DEV_RAM_SIZE=8192 74CONFIG_BLK_DEV_RAM_SIZE=8192
78CONFIG_ATMEL_PWM=y
79CONFIG_ATMEL_TCLIB=y 75CONFIG_ATMEL_TCLIB=y
76CONFIG_ATMEL_SSC=y
80CONFIG_SCSI=y 77CONFIG_SCSI=y
81CONFIG_BLK_DEV_SD=y 78CONFIG_BLK_DEV_SD=y
82CONFIG_SCSI_MULTI_LUN=y
83# CONFIG_SCSI_LOWLEVEL is not set 79# CONFIG_SCSI_LOWLEVEL is not set
84CONFIG_NETDEVICES=y 80CONFIG_NETDEVICES=y
85CONFIG_MACB=y 81CONFIG_MACB=y
@@ -105,9 +101,8 @@ CONFIG_RT2800USB=m
105CONFIG_RT2800USB_RT53XX=y 101CONFIG_RT2800USB_RT53XX=y
106CONFIG_RT2800USB_RT55XX=y 102CONFIG_RT2800USB_RT55XX=y
107CONFIG_RT2800USB_UNKNOWN=y 103CONFIG_RT2800USB_UNKNOWN=y
108CONFIG_RTLWIFI=m
109# CONFIG_RTLWIFI_DEBUG is not set
110CONFIG_RTL8192CU=m 104CONFIG_RTL8192CU=m
105# CONFIG_RTLWIFI_DEBUG is not set
111CONFIG_MWIFIEX=m 106CONFIG_MWIFIEX=m
112CONFIG_MWIFIEX_SDIO=m 107CONFIG_MWIFIEX_SDIO=m
113CONFIG_MWIFIEX_USB=m 108CONFIG_MWIFIEX_USB=m
@@ -128,9 +123,12 @@ CONFIG_SERIAL_ATMEL=y
128CONFIG_SERIAL_ATMEL_CONSOLE=y 123CONFIG_SERIAL_ATMEL_CONSOLE=y
129CONFIG_HW_RANDOM=y 124CONFIG_HW_RANDOM=y
130CONFIG_I2C=y 125CONFIG_I2C=y
126CONFIG_I2C_AT91=y
131CONFIG_I2C_GPIO=y 127CONFIG_I2C_GPIO=y
132CONFIG_SPI=y 128CONFIG_SPI=y
133CONFIG_SPI_ATMEL=y 129CONFIG_SPI_ATMEL=y
130CONFIG_POWER_SUPPLY=y
131CONFIG_POWER_RESET=y
134# CONFIG_HWMON is not set 132# CONFIG_HWMON is not set
135CONFIG_WATCHDOG=y 133CONFIG_WATCHDOG=y
136CONFIG_AT91SAM9X_WATCHDOG=y 134CONFIG_AT91SAM9X_WATCHDOG=y
@@ -144,11 +142,14 @@ CONFIG_BACKLIGHT_ATMEL_LCDC=y
144# CONFIG_BACKLIGHT_GENERIC is not set 142# CONFIG_BACKLIGHT_GENERIC is not set
145CONFIG_FRAMEBUFFER_CONSOLE=y 143CONFIG_FRAMEBUFFER_CONSOLE=y
146CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y 144CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
147CONFIG_FONTS=y
148CONFIG_FONT_8x8=y
149CONFIG_FONT_ACORN_8x8=y
150CONFIG_FONT_MINI_4x6=y
151CONFIG_LOGO=y 145CONFIG_LOGO=y
146CONFIG_SOUND=y
147CONFIG_SND=y
148CONFIG_SND_SOC=y
149CONFIG_SND_ATMEL_SOC=y
150CONFIG_SND_AT91_SOC_SAM9G20_WM8731=y
151CONFIG_SND_ATMEL_SOC_WM8904=y
152CONFIG_SND_AT91_SOC_SAM9X5_WM8731=y
152CONFIG_USB=y 153CONFIG_USB=y
153CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 154CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
154CONFIG_USB_EHCI_HCD=y 155CONFIG_USB_EHCI_HCD=y
@@ -169,6 +170,7 @@ CONFIG_MMC_SPI=y
169CONFIG_NEW_LEDS=y 170CONFIG_NEW_LEDS=y
170CONFIG_LEDS_CLASS=y 171CONFIG_LEDS_CLASS=y
171CONFIG_LEDS_GPIO=y 172CONFIG_LEDS_GPIO=y
173CONFIG_LEDS_PWM=y
172CONFIG_LEDS_TRIGGERS=y 174CONFIG_LEDS_TRIGGERS=y
173CONFIG_LEDS_TRIGGER_TIMER=y 175CONFIG_LEDS_TRIGGER_TIMER=y
174CONFIG_LEDS_TRIGGER_HEARTBEAT=y 176CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -178,7 +180,12 @@ CONFIG_RTC_DRV_RV3029C2=y
178CONFIG_RTC_DRV_AT91RM9200=y 180CONFIG_RTC_DRV_AT91RM9200=y
179CONFIG_RTC_DRV_AT91SAM9=y 181CONFIG_RTC_DRV_AT91SAM9=y
180CONFIG_DMADEVICES=y 182CONFIG_DMADEVICES=y
183CONFIG_AT_HDMAC=y
181# CONFIG_IOMMU_SUPPORT is not set 184# CONFIG_IOMMU_SUPPORT is not set
185CONFIG_IIO=y
186CONFIG_AT91_ADC=y
187CONFIG_PWM=y
188CONFIG_PWM_ATMEL=y
182CONFIG_EXT4_FS=y 189CONFIG_EXT4_FS=y
183CONFIG_FANOTIFY=y 190CONFIG_FANOTIFY=y
184CONFIG_VFAT_FS=y 191CONFIG_VFAT_FS=y
@@ -209,3 +216,7 @@ CONFIG_CRC_CCITT=y
209CONFIG_CRC_ITU_T=y 216CONFIG_CRC_ITU_T=y
210CONFIG_CRC7=m 217CONFIG_CRC7=m
211CONFIG_AVERAGE=y 218CONFIG_AVERAGE=y
219CONFIG_FONTS=y
220CONFIG_FONT_8x8=y
221CONFIG_FONT_ACORN_8x8=y
222CONFIG_FONT_MINI_4x6=y
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index c4c160fc8791..3ada05d639ad 100644
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -54,7 +54,6 @@ CONFIG_DEVTMPFS=y
54CONFIG_DEVTMPFS_MOUNT=y 54CONFIG_DEVTMPFS_MOUNT=y
55CONFIG_MTD=y 55CONFIG_MTD=y
56CONFIG_MTD_CMDLINE_PARTS=y 56CONFIG_MTD_CMDLINE_PARTS=y
57CONFIG_MTD_OF_PARTS=y
58CONFIG_MTD_BLOCK=y 57CONFIG_MTD_BLOCK=y
59CONFIG_MTD_DATAFLASH=y 58CONFIG_MTD_DATAFLASH=y
60CONFIG_MTD_NAND=y 59CONFIG_MTD_NAND=y
@@ -66,13 +65,10 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
66CONFIG_EEPROM_AT25=y 65CONFIG_EEPROM_AT25=y
67CONFIG_SCSI=y 66CONFIG_SCSI=y
68CONFIG_BLK_DEV_SD=y 67CONFIG_BLK_DEV_SD=y
69CONFIG_SCSI_MULTI_LUN=y
70# CONFIG_SCSI_LOWLEVEL is not set 68# CONFIG_SCSI_LOWLEVEL is not set
71CONFIG_NETDEVICES=y 69CONFIG_NETDEVICES=y
72CONFIG_MII=y
73CONFIG_MACB=y 70CONFIG_MACB=y
74# CONFIG_NET_VENDOR_BROADCOM is not set 71# CONFIG_NET_VENDOR_BROADCOM is not set
75# CONFIG_NET_VENDOR_CHELSIO is not set
76# CONFIG_NET_VENDOR_FARADAY is not set 72# CONFIG_NET_VENDOR_FARADAY is not set
77# CONFIG_NET_VENDOR_INTEL is not set 73# CONFIG_NET_VENDOR_INTEL is not set
78# CONFIG_NET_VENDOR_MARVELL is not set 74# CONFIG_NET_VENDOR_MARVELL is not set
@@ -86,7 +82,6 @@ CONFIG_SMSC_PHY=y
86# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 82# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
87CONFIG_KEYBOARD_GPIO=y 83CONFIG_KEYBOARD_GPIO=y
88# CONFIG_INPUT_MOUSE is not set 84# CONFIG_INPUT_MOUSE is not set
89# CONFIG_SERIO is not set
90CONFIG_SERIAL_ATMEL=y 85CONFIG_SERIAL_ATMEL=y
91CONFIG_SERIAL_ATMEL_CONSOLE=y 86CONFIG_SERIAL_ATMEL_CONSOLE=y
92CONFIG_HW_RANDOM=y 87CONFIG_HW_RANDOM=y
@@ -97,6 +92,8 @@ CONFIG_SPI=y
97CONFIG_SPI_ATMEL=y 92CONFIG_SPI_ATMEL=y
98CONFIG_SPI_SPIDEV=y 93CONFIG_SPI_SPIDEV=y
99CONFIG_GPIO_SYSFS=y 94CONFIG_GPIO_SYSFS=y
95CONFIG_POWER_SUPPLY=y
96CONFIG_POWER_RESET=y
100# CONFIG_HWMON is not set 97# CONFIG_HWMON is not set
101CONFIG_WATCHDOG=y 98CONFIG_WATCHDOG=y
102CONFIG_WATCHDOG_NOWAYOUT=y 99CONFIG_WATCHDOG_NOWAYOUT=y
@@ -127,6 +124,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
127CONFIG_RTC_CLASS=y 124CONFIG_RTC_CLASS=y
128CONFIG_RTC_DRV_RV3029C2=y 125CONFIG_RTC_DRV_RV3029C2=y
129CONFIG_RTC_DRV_AT91SAM9=y 126CONFIG_RTC_DRV_AT91SAM9=y
127CONFIG_IIO=y
128CONFIG_AT91_ADC=y
130CONFIG_EXT4_FS=y 129CONFIG_EXT4_FS=y
131CONFIG_VFAT_FS=y 130CONFIG_VFAT_FS=y
132CONFIG_TMPFS=y 131CONFIG_TMPFS=y
@@ -139,10 +138,8 @@ CONFIG_NLS_CODEPAGE_850=y
139CONFIG_NLS_ISO8859_1=y 138CONFIG_NLS_ISO8859_1=y
140CONFIG_NLS_ISO8859_15=y 139CONFIG_NLS_ISO8859_15=y
141CONFIG_NLS_UTF8=y 140CONFIG_NLS_UTF8=y
142# CONFIG_ENABLE_WARN_DEPRECATED is not set
143CONFIG_DEBUG_KERNEL=y
144CONFIG_DEBUG_INFO=y 141CONFIG_DEBUG_INFO=y
142# CONFIG_ENABLE_WARN_DEPRECATED is not set
145# CONFIG_FTRACE is not set 143# CONFIG_FTRACE is not set
146CONFIG_DEBUG_LL=y 144CONFIG_DEBUG_LL=y
147CONFIG_AT91_DEBUG_LL_DBGU0=y
148CONFIG_EARLY_PRINTK=y 145CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9261_9g10_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
index f80e993b04ce..0c505d801e25 100644
--- a/arch/arm/configs/at91sam9261_9g10_defconfig
+++ b/arch/arm/configs/at91sam9261_9g10_defconfig
@@ -1,4 +1,3 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_LOCALVERSION_AUTO is not set 1# CONFIG_LOCALVERSION_AUTO is not set
3CONFIG_KERNEL_LZMA=y 2CONFIG_KERNEL_LZMA=y
4# CONFIG_SWAP is not set 3# CONFIG_SWAP is not set
@@ -20,7 +19,6 @@ CONFIG_MACH_AT91SAM9261EK=y
20CONFIG_MACH_AT91SAM9G10EK=y 19CONFIG_MACH_AT91SAM9G10EK=y
21# CONFIG_ARM_THUMB is not set 20# CONFIG_ARM_THUMB is not set
22CONFIG_AEABI=y 21CONFIG_AEABI=y
23# CONFIG_OABI_COMPAT is not set
24CONFIG_ZBOOT_ROM_TEXT=0x0 22CONFIG_ZBOOT_ROM_TEXT=0x0
25CONFIG_ZBOOT_ROM_BSS=0x0 23CONFIG_ZBOOT_ROM_BSS=0x0
26CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" 24CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
@@ -55,7 +53,6 @@ CONFIG_ATMEL_TCLIB=y
55CONFIG_ATMEL_SSC=y 53CONFIG_ATMEL_SSC=y
56CONFIG_SCSI=y 54CONFIG_SCSI=y
57CONFIG_BLK_DEV_SD=y 55CONFIG_BLK_DEV_SD=y
58CONFIG_SCSI_MULTI_LUN=y
59CONFIG_NETDEVICES=y 56CONFIG_NETDEVICES=y
60CONFIG_DM9000=y 57CONFIG_DM9000=y
61CONFIG_USB_ZD1201=m 58CONFIG_USB_ZD1201=m
@@ -87,6 +84,8 @@ CONFIG_I2C_CHARDEV=y
87CONFIG_I2C_GPIO=y 84CONFIG_I2C_GPIO=y
88CONFIG_SPI=y 85CONFIG_SPI=y
89CONFIG_SPI_ATMEL=y 86CONFIG_SPI_ATMEL=y
87CONFIG_POWER_SUPPLY=y
88CONFIG_POWER_RESET=y
90# CONFIG_HWMON is not set 89# CONFIG_HWMON is not set
91CONFIG_WATCHDOG=y 90CONFIG_WATCHDOG=y
92CONFIG_WATCHDOG_NOWAYOUT=y 91CONFIG_WATCHDOG_NOWAYOUT=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index e40026364e57..8b671c977b81 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -18,7 +18,6 @@ CONFIG_MACH_AT91SAM9263EK=y
18CONFIG_MTD_AT91_DATAFLASH_CARD=y 18CONFIG_MTD_AT91_DATAFLASH_CARD=y
19# CONFIG_ARM_THUMB is not set 19# CONFIG_ARM_THUMB is not set
20CONFIG_AEABI=y 20CONFIG_AEABI=y
21# CONFIG_OABI_COMPAT is not set
22CONFIG_ZBOOT_ROM_TEXT=0x0 21CONFIG_ZBOOT_ROM_TEXT=0x0
23CONFIG_ZBOOT_ROM_BSS=0x0 22CONFIG_ZBOOT_ROM_BSS=0x0
24CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" 23CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
@@ -51,7 +50,6 @@ CONFIG_DEVTMPFS=y
51CONFIG_DEVTMPFS_MOUNT=y 50CONFIG_DEVTMPFS_MOUNT=y
52CONFIG_MTD=y 51CONFIG_MTD=y
53CONFIG_MTD_CMDLINE_PARTS=y 52CONFIG_MTD_CMDLINE_PARTS=y
54CONFIG_MTD_CHAR=y
55CONFIG_MTD_BLOCK=y 53CONFIG_MTD_BLOCK=y
56CONFIG_NFTL=y 54CONFIG_NFTL=y
57CONFIG_NFTL_RW=y 55CONFIG_NFTL_RW=y
@@ -64,13 +62,10 @@ CONFIG_MTD_UBI_GLUEBI=y
64CONFIG_BLK_DEV_LOOP=y 62CONFIG_BLK_DEV_LOOP=y
65CONFIG_BLK_DEV_RAM=y 63CONFIG_BLK_DEV_RAM=y
66CONFIG_BLK_DEV_RAM_SIZE=8192 64CONFIG_BLK_DEV_RAM_SIZE=8192
67CONFIG_ATMEL_PWM=y
68CONFIG_ATMEL_TCLIB=y 65CONFIG_ATMEL_TCLIB=y
69CONFIG_SCSI=y 66CONFIG_SCSI=y
70CONFIG_BLK_DEV_SD=y 67CONFIG_BLK_DEV_SD=y
71CONFIG_SCSI_MULTI_LUN=y
72CONFIG_NETDEVICES=y 68CONFIG_NETDEVICES=y
73CONFIG_MII=y
74CONFIG_MACB=y 69CONFIG_MACB=y
75CONFIG_SMSC_PHY=y 70CONFIG_SMSC_PHY=y
76# CONFIG_WLAN is not set 71# CONFIG_WLAN is not set
@@ -92,6 +87,8 @@ CONFIG_I2C_GPIO=y
92CONFIG_SPI=y 87CONFIG_SPI=y
93CONFIG_SPI_ATMEL=y 88CONFIG_SPI_ATMEL=y
94CONFIG_GPIO_SYSFS=y 89CONFIG_GPIO_SYSFS=y
90CONFIG_POWER_SUPPLY=y
91CONFIG_POWER_RESET=y
95# CONFIG_HWMON is not set 92# CONFIG_HWMON is not set
96CONFIG_WATCHDOG=y 93CONFIG_WATCHDOG=y
97CONFIG_WATCHDOG_NOWAYOUT=y 94CONFIG_WATCHDOG_NOWAYOUT=y
@@ -103,7 +100,6 @@ CONFIG_LCD_CLASS_DEVICE=y
103CONFIG_BACKLIGHT_CLASS_DEVICE=y 100CONFIG_BACKLIGHT_CLASS_DEVICE=y
104CONFIG_FRAMEBUFFER_CONSOLE=y 101CONFIG_FRAMEBUFFER_CONSOLE=y
105CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y 102CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
106CONFIG_FONTS=y
107CONFIG_LOGO=y 103CONFIG_LOGO=y
108CONFIG_SOUND=y 104CONFIG_SOUND=y
109CONFIG_SND=y 105CONFIG_SND=y
@@ -129,12 +125,14 @@ CONFIG_SDIO_UART=m
129CONFIG_MMC_ATMELMCI=m 125CONFIG_MMC_ATMELMCI=m
130CONFIG_NEW_LEDS=y 126CONFIG_NEW_LEDS=y
131CONFIG_LEDS_CLASS=y 127CONFIG_LEDS_CLASS=y
132CONFIG_LEDS_ATMEL_PWM=y
133CONFIG_LEDS_GPIO=y 128CONFIG_LEDS_GPIO=y
129CONFIG_LEDS_PWM=y
134CONFIG_LEDS_TRIGGERS=y 130CONFIG_LEDS_TRIGGERS=y
135CONFIG_LEDS_TRIGGER_HEARTBEAT=y 131CONFIG_LEDS_TRIGGER_HEARTBEAT=y
136CONFIG_RTC_CLASS=y 132CONFIG_RTC_CLASS=y
137CONFIG_RTC_DRV_AT91SAM9=y 133CONFIG_RTC_DRV_AT91SAM9=y
134CONFIG_PWM=y
135CONFIG_PWM_ATMEL=y
138CONFIG_EXT4_FS=y 136CONFIG_EXT4_FS=y
139CONFIG_VFAT_FS=y 137CONFIG_VFAT_FS=y
140CONFIG_TMPFS=y 138CONFIG_TMPFS=y
@@ -150,3 +148,4 @@ CONFIG_NLS_ISO8859_1=y
150CONFIG_NLS_UTF8=y 148CONFIG_NLS_UTF8=y
151CONFIG_DEBUG_USER=y 149CONFIG_DEBUG_USER=y
152CONFIG_XZ_DEC=y 150CONFIG_XZ_DEC=y
151CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index c6661a60025d..f66d1a1b64bf 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -20,7 +20,6 @@ CONFIG_MACH_AT91SAM9M10G45EK=y
20CONFIG_MACH_AT91SAM9_DT=y 20CONFIG_MACH_AT91SAM9_DT=y
21CONFIG_AT91_SLOW_CLOCK=y 21CONFIG_AT91_SLOW_CLOCK=y
22CONFIG_AEABI=y 22CONFIG_AEABI=y
23# CONFIG_OABI_COMPAT is not set
24CONFIG_UACCESS_WITH_MEMCPY=y 23CONFIG_UACCESS_WITH_MEMCPY=y
25CONFIG_ZBOOT_ROM_TEXT=0x0 24CONFIG_ZBOOT_ROM_TEXT=0x0
26CONFIG_ZBOOT_ROM_BSS=0x0 25CONFIG_ZBOOT_ROM_BSS=0x0
@@ -51,7 +50,6 @@ CONFIG_DEVTMPFS_MOUNT=y
51# CONFIG_PREVENT_FIRMWARE_BUILD is not set 50# CONFIG_PREVENT_FIRMWARE_BUILD is not set
52CONFIG_MTD=y 51CONFIG_MTD=y
53CONFIG_MTD_CMDLINE_PARTS=y 52CONFIG_MTD_CMDLINE_PARTS=y
54CONFIG_MTD_CHAR=y
55CONFIG_MTD_BLOCK=y 53CONFIG_MTD_BLOCK=y
56CONFIG_MTD_DATAFLASH=y 54CONFIG_MTD_DATAFLASH=y
57CONFIG_MTD_NAND=y 55CONFIG_MTD_NAND=y
@@ -62,15 +60,12 @@ CONFIG_BLK_DEV_LOOP=y
62CONFIG_BLK_DEV_RAM=y 60CONFIG_BLK_DEV_RAM=y
63CONFIG_BLK_DEV_RAM_COUNT=4 61CONFIG_BLK_DEV_RAM_COUNT=4
64CONFIG_BLK_DEV_RAM_SIZE=8192 62CONFIG_BLK_DEV_RAM_SIZE=8192
65CONFIG_ATMEL_PWM=y
66CONFIG_ATMEL_TCLIB=y 63CONFIG_ATMEL_TCLIB=y
67CONFIG_ATMEL_SSC=y 64CONFIG_ATMEL_SSC=y
68CONFIG_SCSI=y 65CONFIG_SCSI=y
69CONFIG_BLK_DEV_SD=y 66CONFIG_BLK_DEV_SD=y
70CONFIG_SCSI_MULTI_LUN=y
71# CONFIG_SCSI_LOWLEVEL is not set 67# CONFIG_SCSI_LOWLEVEL is not set
72CONFIG_NETDEVICES=y 68CONFIG_NETDEVICES=y
73CONFIG_MII=y
74CONFIG_MACB=y 69CONFIG_MACB=y
75CONFIG_DAVICOM_PHY=y 70CONFIG_DAVICOM_PHY=y
76# CONFIG_INPUT_MOUSEDEV is not set 71# CONFIG_INPUT_MOUSEDEV is not set
@@ -93,18 +88,22 @@ CONFIG_I2C_CHARDEV=y
93CONFIG_I2C_GPIO=y 88CONFIG_I2C_GPIO=y
94CONFIG_SPI=y 89CONFIG_SPI=y
95CONFIG_SPI_ATMEL=y 90CONFIG_SPI_ATMEL=y
91CONFIG_POWER_SUPPLY=y
92CONFIG_POWER_RESET=y
96# CONFIG_HWMON is not set 93# CONFIG_HWMON is not set
94CONFIG_WATCHDOG=y
95CONFIG_WATCHDOG_NOWAYOUT=y
96CONFIG_AT91SAM9X_WATCHDOG=y
97CONFIG_FB=y 97CONFIG_FB=y
98CONFIG_FB_ATMEL=y 98CONFIG_FB_ATMEL=y
99CONFIG_BACKLIGHT_LCD_SUPPORT=y 99CONFIG_BACKLIGHT_LCD_SUPPORT=y
100CONFIG_LCD_CLASS_DEVICE=y 100CONFIG_LCD_CLASS_DEVICE=y
101CONFIG_BACKLIGHT_CLASS_DEVICE=y 101CONFIG_BACKLIGHT_CLASS_DEVICE=y
102CONFIG_BACKLIGHT_ATMEL_LCDC=y 102CONFIG_BACKLIGHT_ATMEL_LCDC=y
103CONFIG_BACKLIGHT_ATMEL_PWM=y
104# CONFIG_BACKLIGHT_GENERIC is not set 103# CONFIG_BACKLIGHT_GENERIC is not set
104CONFIG_BACKLIGHT_PWM=y
105CONFIG_FRAMEBUFFER_CONSOLE=y 105CONFIG_FRAMEBUFFER_CONSOLE=y
106CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y 106CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
107CONFIG_FONTS=y
108CONFIG_LOGO=y 107CONFIG_LOGO=y
109CONFIG_SOUND=y 108CONFIG_SOUND=y
110CONFIG_SND=y 109CONFIG_SND=y
@@ -135,6 +134,7 @@ CONFIG_MMC_ATMELMCI=y
135CONFIG_NEW_LEDS=y 134CONFIG_NEW_LEDS=y
136CONFIG_LEDS_CLASS=y 135CONFIG_LEDS_CLASS=y
137CONFIG_LEDS_GPIO=y 136CONFIG_LEDS_GPIO=y
137CONFIG_LEDS_PWM=y
138CONFIG_LEDS_TRIGGERS=y 138CONFIG_LEDS_TRIGGERS=y
139CONFIG_LEDS_TRIGGER_TIMER=y 139CONFIG_LEDS_TRIGGER_TIMER=y
140CONFIG_LEDS_TRIGGER_HEARTBEAT=y 140CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -147,6 +147,8 @@ CONFIG_DMATEST=m
147# CONFIG_IOMMU_SUPPORT is not set 147# CONFIG_IOMMU_SUPPORT is not set
148CONFIG_IIO=y 148CONFIG_IIO=y
149CONFIG_AT91_ADC=y 149CONFIG_AT91_ADC=y
150CONFIG_PWM=y
151CONFIG_PWM_ATMEL=y
150CONFIG_EXT4_FS=y 152CONFIG_EXT4_FS=y
151CONFIG_FANOTIFY=y 153CONFIG_FANOTIFY=y
152CONFIG_VFAT_FS=y 154CONFIG_VFAT_FS=y
@@ -159,8 +161,8 @@ CONFIG_NLS_CODEPAGE_437=y
159CONFIG_NLS_CODEPAGE_850=y 161CONFIG_NLS_CODEPAGE_850=y
160CONFIG_NLS_ISO8859_1=y 162CONFIG_NLS_ISO8859_1=y
161CONFIG_STRIP_ASM_SYMS=y 163CONFIG_STRIP_ASM_SYMS=y
162# CONFIG_SCHED_DEBUG is not set
163CONFIG_DEBUG_MEMORY_INIT=y 164CONFIG_DEBUG_MEMORY_INIT=y
165# CONFIG_SCHED_DEBUG is not set
164# CONFIG_FTRACE is not set 166# CONFIG_FTRACE is not set
165CONFIG_DEBUG_USER=y 167CONFIG_DEBUG_USER=y
166CONFIG_DEBUG_LL=y 168CONFIG_DEBUG_LL=y
@@ -170,3 +172,4 @@ CONFIG_CRYPTO_ECB=y
170CONFIG_CRYPTO_USER_API_HASH=m 172CONFIG_CRYPTO_USER_API_HASH=m
171CONFIG_CRYPTO_USER_API_SKCIPHER=m 173CONFIG_CRYPTO_USER_API_SKCIPHER=m
172# CONFIG_CRYPTO_HW is not set 174# CONFIG_CRYPTO_HW is not set
175CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index 5d7797d43d23..4c26d344ae88 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -2,8 +2,8 @@
2# CONFIG_SWAP is not set 2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14 4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_EMBEDDED=y
6CONFIG_BLK_DEV_INITRD=y 5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EMBEDDED=y
7CONFIG_SLAB=y 7CONFIG_SLAB=y
8CONFIG_MODULES=y 8CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y 9CONFIG_MODULE_UNLOAD=y
@@ -37,7 +37,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4
37CONFIG_BLK_DEV_RAM_SIZE=24576 37CONFIG_BLK_DEV_RAM_SIZE=24576
38CONFIG_SCSI=y 38CONFIG_SCSI=y
39CONFIG_BLK_DEV_SD=y 39CONFIG_BLK_DEV_SD=y
40CONFIG_SCSI_MULTI_LUN=y
41# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 40# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
42CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 41CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
43CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 42CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
@@ -54,20 +53,31 @@ CONFIG_I2C_CHARDEV=y
54CONFIG_I2C_GPIO=y 53CONFIG_I2C_GPIO=y
55CONFIG_SPI=y 54CONFIG_SPI=y
56CONFIG_SPI_ATMEL=y 55CONFIG_SPI_ATMEL=y
56CONFIG_POWER_SUPPLY=y
57CONFIG_POWER_RESET=y
57# CONFIG_HWMON is not set 58# CONFIG_HWMON is not set
58CONFIG_WATCHDOG=y 59CONFIG_WATCHDOG=y
59CONFIG_WATCHDOG_NOWAYOUT=y 60CONFIG_WATCHDOG_NOWAYOUT=y
60CONFIG_AT91SAM9X_WATCHDOG=y 61CONFIG_AT91SAM9X_WATCHDOG=y
61CONFIG_FB=y 62CONFIG_FB=y
62CONFIG_FB_ATMEL=y 63CONFIG_FB_ATMEL=y
64CONFIG_USB_GADGET=y
65CONFIG_USB_ATMEL_USBA=y
63CONFIG_MMC=y 66CONFIG_MMC=y
64CONFIG_MMC_ATMELMCI=m 67CONFIG_MMC_ATMELMCI=m
68CONFIG_NEW_LEDS=y
69CONFIG_LEDS_CLASS=y
70CONFIG_LEDS_GPIO=y
71CONFIG_LEDS_PWM=y
72CONFIG_LEDS_TRIGGERS=y
73CONFIG_LEDS_TRIGGER_HEARTBEAT=y
65CONFIG_RTC_CLASS=y 74CONFIG_RTC_CLASS=y
66CONFIG_RTC_DRV_AT91SAM9=y 75CONFIG_RTC_DRV_AT91SAM9=y
67CONFIG_IIO=y 76CONFIG_IIO=y
68CONFIG_AT91_ADC=y 77CONFIG_AT91_ADC=y
69CONFIG_EXT2_FS=y 78CONFIG_PWM=y
70CONFIG_MSDOS_FS=y 79CONFIG_PWM_ATMEL=y
80CONFIG_EXT4_FS=y
71CONFIG_VFAT_FS=y 81CONFIG_VFAT_FS=y
72CONFIG_TMPFS=y 82CONFIG_TMPFS=y
73CONFIG_UBIFS_FS=y 83CONFIG_UBIFS_FS=y
@@ -77,7 +87,6 @@ CONFIG_NLS_CODEPAGE_850=y
77CONFIG_NLS_ISO8859_1=y 87CONFIG_NLS_ISO8859_1=y
78CONFIG_NLS_ISO8859_15=y 88CONFIG_NLS_ISO8859_15=y
79CONFIG_NLS_UTF8=y 89CONFIG_NLS_UTF8=y
80CONFIG_DEBUG_KERNEL=y
81CONFIG_DEBUG_INFO=y 90CONFIG_DEBUG_INFO=y
82CONFIG_DEBUG_USER=y 91CONFIG_DEBUG_USER=y
83CONFIG_DEBUG_LL=y 92CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 0302d293fba0..31cb07388885 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -98,6 +98,7 @@ CONFIG_LEDS_TRIGGER_TRANSIENT=y
98CONFIG_LEDS_TRIGGER_CAMERA=y 98CONFIG_LEDS_TRIGGER_CAMERA=y
99CONFIG_STAGING=y 99CONFIG_STAGING=y
100CONFIG_USB_DWC2=y 100CONFIG_USB_DWC2=y
101CONFIG_USB_DWC2_HOST=y
101# CONFIG_IOMMU_SUPPORT is not set 102# CONFIG_IOMMU_SUPPORT is not set
102CONFIG_EXT2_FS=y 103CONFIG_EXT2_FS=y
103CONFIG_EXT2_FS_XATTR=y 104CONFIG_EXT2_FS_XATTR=y
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index fbebcbce1e8c..bc614f44b33d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -83,7 +83,6 @@ CONFIG_I2C_CHARDEV=y
83CONFIG_MFD_BCM590XX=y 83CONFIG_MFD_BCM590XX=y
84CONFIG_REGULATOR=y 84CONFIG_REGULATOR=y
85CONFIG_REGULATOR_FIXED_VOLTAGE=y 85CONFIG_REGULATOR_FIXED_VOLTAGE=y
86CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
87CONFIG_REGULATOR_USERSPACE_CONSUMER=y 86CONFIG_REGULATOR_USERSPACE_CONSUMER=y
88CONFIG_REGULATOR_BCM590XX=y 87CONFIG_REGULATOR_BCM590XX=y
89 88
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index e816140d81c5..1dde5daa84f9 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -29,7 +29,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0
29CONFIG_ARM_APPENDED_DTB=y 29CONFIG_ARM_APPENDED_DTB=y
30CONFIG_VFP=y 30CONFIG_VFP=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32# CONFIG_SUSPEND is not set
33CONFIG_PM_RUNTIME=y 32CONFIG_PM_RUNTIME=y
34CONFIG_NET=y 33CONFIG_NET=y
35CONFIG_PACKET=y 34CONFIG_PACKET=y
@@ -55,6 +54,7 @@ CONFIG_MTD_BLOCK=y
55CONFIG_MTD_CFI=y 54CONFIG_MTD_CFI=y
56CONFIG_MTD_CFI_AMDSTD=y 55CONFIG_MTD_CFI_AMDSTD=y
57CONFIG_MTD_M25P80=y 56CONFIG_MTD_M25P80=y
57CONFIG_MTD_SPI_NOR=y
58CONFIG_SCSI=y 58CONFIG_SCSI=y
59CONFIG_BLK_DEV_SD=y 59CONFIG_BLK_DEV_SD=y
60CONFIG_NETDEVICES=y 60CONFIG_NETDEVICES=y
@@ -82,6 +82,7 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
82# CONFIG_HWMON is not set 82# CONFIG_HWMON is not set
83CONFIG_I2C=y 83CONFIG_I2C=y
84CONFIG_I2C_RCAR=y 84CONFIG_I2C_RCAR=y
85CONFIG_GPIO_RCAR=y
85CONFIG_REGULATOR=y 86CONFIG_REGULATOR=y
86CONFIG_MEDIA_SUPPORT=y 87CONFIG_MEDIA_SUPPORT=y
87CONFIG_MEDIA_CAMERA_SUPPORT=y 88CONFIG_MEDIA_CAMERA_SUPPORT=y
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 0facf9da047c..fc105c9178cc 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -68,8 +68,8 @@ CONFIG_GPIO_GENERIC_PLATFORM=y
68# CONFIG_HWMON is not set 68# CONFIG_HWMON is not set
69CONFIG_FB=y 69CONFIG_FB=y
70CONFIG_FB_CLPS711X=y 70CONFIG_FB_CLPS711X=y
71CONFIG_BACKLIGHT_LCD_SUPPORT=y
72CONFIG_LCD_PLATFORM=y 71CONFIG_LCD_PLATFORM=y
72CONFIG_BACKLIGHT_PWM=y
73# CONFIG_USB_SUPPORT is not set 73# CONFIG_USB_SUPPORT is not set
74CONFIG_NEW_LEDS=y 74CONFIG_NEW_LEDS=y
75CONFIG_LEDS_CLASS=y 75CONFIG_LEDS_CLASS=y
@@ -77,6 +77,8 @@ CONFIG_LEDS_GPIO=y
77CONFIG_LEDS_TRIGGERS=y 77CONFIG_LEDS_TRIGGERS=y
78CONFIG_LEDS_TRIGGER_HEARTBEAT=y 78CONFIG_LEDS_TRIGGER_HEARTBEAT=y
79# CONFIG_IOMMU_SUPPORT is not set 79# CONFIG_IOMMU_SUPPORT is not set
80CONFIG_PWM=y
81CONFIG_PWM_CLPS711X=y
80CONFIG_EXT2_FS=y 82CONFIG_EXT2_FS=y
81CONFIG_CRAMFS=y 83CONFIG_CRAMFS=y
82CONFIG_MINIX_FS=y 84CONFIG_MINIX_FS=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 1b650c85bdd0..72233b9c9d07 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -107,5 +107,6 @@ CONFIG_DEBUG_SPINLOCK=y
107CONFIG_DEBUG_MUTEXES=y 107CONFIG_DEBUG_MUTEXES=y
108CONFIG_DEBUG_USER=y 108CONFIG_DEBUG_USER=y
109CONFIG_DEBUG_LL=y 109CONFIG_DEBUG_LL=y
110CONFIG_DEBUG_LL_UART_PL01X=y
110# CONFIG_CRYPTO_ANSI_CPRNG is not set 111# CONFIG_CRYPTO_ANSI_CPRNG is not set
111CONFIG_LIBCRC32C=y 112CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index d95763d5f0d8..eb440aae4283 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -230,7 +230,6 @@ CONFIG_POWER_SUPPLY=y
230CONFIG_EZX_PCAP=y 230CONFIG_EZX_PCAP=y
231CONFIG_REGULATOR=y 231CONFIG_REGULATOR=y
232CONFIG_REGULATOR_DEBUG=y 232CONFIG_REGULATOR_DEBUG=y
233CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
234CONFIG_REGULATOR_USERSPACE_CONSUMER=y 233CONFIG_REGULATOR_USERSPACE_CONSUMER=y
235CONFIG_REGULATOR_PCAP=y 234CONFIG_REGULATOR_PCAP=y
236CONFIG_MEDIA_SUPPORT=y 235CONFIG_MEDIA_SUPPORT=y
diff --git a/arch/arm/configs/hi3xxx_defconfig b/arch/arm/configs/hisi_defconfig
index 9630687e7d07..1772505caeba 100644
--- a/arch/arm/configs/hi3xxx_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -6,10 +6,15 @@ CONFIG_RD_LZMA=y
6CONFIG_ARCH_HISI=y 6CONFIG_ARCH_HISI=y
7CONFIG_ARCH_HI3xxx=y 7CONFIG_ARCH_HI3xxx=y
8CONFIG_ARCH_HIX5HD2=y 8CONFIG_ARCH_HIX5HD2=y
9CONFIG_ARCH_HIP04=y
9CONFIG_SMP=y 10CONFIG_SMP=y
11CONFIG_NR_CPUS=16
10CONFIG_PREEMPT=y 12CONFIG_PREEMPT=y
11CONFIG_AEABI=y 13CONFIG_AEABI=y
14CONFIG_HIGHMEM=y
12CONFIG_ARM_APPENDED_DTB=y 15CONFIG_ARM_APPENDED_DTB=y
16CONFIG_ARM_ATAG_DTB_COMPAT=y
17CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
13CONFIG_NET=y 18CONFIG_NET=y
14CONFIG_UNIX=y 19CONFIG_UNIX=y
15CONFIG_INET=y 20CONFIG_INET=y
@@ -21,6 +26,12 @@ CONFIG_BLK_DEV_SD=y
21CONFIG_ATA=y 26CONFIG_ATA=y
22CONFIG_SATA_AHCI_PLATFORM=y 27CONFIG_SATA_AHCI_PLATFORM=y
23CONFIG_NETDEVICES=y 28CONFIG_NETDEVICES=y
29CONFIG_SERIAL_8250=y
30CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
31CONFIG_SERIAL_8250_CONSOLE=y
32CONFIG_SERIAL_8250_NR_UARTS=2
33CONFIG_SERIAL_8250_RUNTIME_UARTS=2
34CONFIG_SERIAL_8250_DW=y
24CONFIG_SERIAL_AMBA_PL011=y 35CONFIG_SERIAL_AMBA_PL011=y
25CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 36CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
26CONFIG_SERIAL_OF_PLATFORM=y 37CONFIG_SERIAL_OF_PLATFORM=y
@@ -56,3 +67,5 @@ CONFIG_PRINTK_TIME=y
56CONFIG_DEBUG_FS=y 67CONFIG_DEBUG_FS=y
57CONFIG_DEBUG_KERNEL=y 68CONFIG_DEBUG_KERNEL=y
58CONFIG_LOCKUP_DETECTOR=y 69CONFIG_LOCKUP_DETECTOR=y
70CONFIG_VFP=y
71CONFIG_VFPv3=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index fd996bb13022..182e54692664 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -208,7 +208,6 @@ CONFIG_POWER_SUPPLY=y
208CONFIG_PMIC_DA903X=y 208CONFIG_PMIC_DA903X=y
209CONFIG_REGULATOR=y 209CONFIG_REGULATOR=y
210CONFIG_REGULATOR_DEBUG=y 210CONFIG_REGULATOR_DEBUG=y
211CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
212CONFIG_REGULATOR_USERSPACE_CONSUMER=y 211CONFIG_REGULATOR_USERSPACE_CONSUMER=y
213CONFIG_REGULATOR_DA903X=y 212CONFIG_REGULATOR_DA903X=y
214CONFIG_MEDIA_SUPPORT=y 213CONFIG_MEDIA_SUPPORT=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 63bde0efc041..e688741c89aa 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -21,8 +21,6 @@ CONFIG_ARCH_MULTI_V4T=y
21CONFIG_ARCH_MULTI_V5=y 21CONFIG_ARCH_MULTI_V5=y
22# CONFIG_ARCH_MULTI_V7 is not set 22# CONFIG_ARCH_MULTI_V7 is not set
23CONFIG_ARCH_MXC=y 23CONFIG_ARCH_MXC=y
24CONFIG_MXC_IRQ_PRIOR=y
25CONFIG_ARCH_MX1ADS=y
26CONFIG_MACH_SCB9328=y 24CONFIG_MACH_SCB9328=y
27CONFIG_MACH_APF9328=y 25CONFIG_MACH_APF9328=y
28CONFIG_MACH_MX21ADS=y 26CONFIG_MACH_MX21ADS=y
@@ -30,10 +28,6 @@ CONFIG_MACH_MX25_3DS=y
30CONFIG_MACH_EUKREA_CPUIMX25SD=y 28CONFIG_MACH_EUKREA_CPUIMX25SD=y
31CONFIG_MACH_IMX25_DT=y 29CONFIG_MACH_IMX25_DT=y
32CONFIG_MACH_MX27ADS=y 30CONFIG_MACH_MX27ADS=y
33CONFIG_MACH_PCM038=y
34CONFIG_MACH_CPUIMX27=y
35CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
36CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
37CONFIG_MACH_MX27_3DS=y 31CONFIG_MACH_MX27_3DS=y
38CONFIG_MACH_IMX27_VISSTRIM_M10=y 32CONFIG_MACH_IMX27_VISSTRIM_M10=y
39CONFIG_MACH_PCA100=y 33CONFIG_MACH_PCA100=y
@@ -43,8 +37,6 @@ CONFIG_PREEMPT=y
43CONFIG_AEABI=y 37CONFIG_AEABI=y
44CONFIG_ZBOOT_ROM_TEXT=0x0 38CONFIG_ZBOOT_ROM_TEXT=0x0
45CONFIG_ZBOOT_ROM_BSS=0x0 39CONFIG_ZBOOT_ROM_BSS=0x0
46CONFIG_FPE_NWFPE=y
47CONFIG_FPE_NWFPE_XP=y
48CONFIG_PM_DEBUG=y 40CONFIG_PM_DEBUG=y
49CONFIG_NET=y 41CONFIG_NET=y
50CONFIG_PACKET=y 42CONFIG_PACKET=y
@@ -63,6 +55,7 @@ CONFIG_NETFILTER=y
63CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 55CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
64CONFIG_DEVTMPFS=y 56CONFIG_DEVTMPFS=y
65CONFIG_DEVTMPFS_MOUNT=y 57CONFIG_DEVTMPFS_MOUNT=y
58CONFIG_IMX_WEIM=y
66CONFIG_MTD=y 59CONFIG_MTD=y
67CONFIG_MTD_CMDLINE_PARTS=y 60CONFIG_MTD_CMDLINE_PARTS=y
68CONFIG_MTD_BLOCK=y 61CONFIG_MTD_BLOCK=y
@@ -78,8 +71,8 @@ CONFIG_MTD_NAND_MXC=y
78CONFIG_MTD_UBI=y 71CONFIG_MTD_UBI=y
79CONFIG_EEPROM_AT24=y 72CONFIG_EEPROM_AT24=y
80CONFIG_EEPROM_AT25=y 73CONFIG_EEPROM_AT25=y
81CONFIG_ATA=y
82CONFIG_BLK_DEV_SD=y 74CONFIG_BLK_DEV_SD=y
75CONFIG_ATA=y
83CONFIG_PATA_IMX=y 76CONFIG_PATA_IMX=y
84CONFIG_NETDEVICES=y 77CONFIG_NETDEVICES=y
85CONFIG_CS89x0=y 78CONFIG_CS89x0=y
@@ -102,10 +95,8 @@ CONFIG_SERIAL_8250=m
102CONFIG_SERIAL_IMX=y 95CONFIG_SERIAL_IMX=y
103CONFIG_SERIAL_IMX_CONSOLE=y 96CONFIG_SERIAL_IMX_CONSOLE=y
104# CONFIG_HW_RANDOM is not set 97# CONFIG_HW_RANDOM is not set
105CONFIG_I2C=y
106CONFIG_I2C_CHARDEV=y 98CONFIG_I2C_CHARDEV=y
107CONFIG_I2C_IMX=y 99CONFIG_I2C_IMX=y
108CONFIG_SPI=y
109CONFIG_SPI_IMX=y 100CONFIG_SPI_IMX=y
110CONFIG_SPI_SPIDEV=y 101CONFIG_SPI_SPIDEV=y
111CONFIG_GPIO_SYSFS=y 102CONFIG_GPIO_SYSFS=y
@@ -132,10 +123,7 @@ CONFIG_VIDEO_CODA=y
132CONFIG_SOC_CAMERA_OV2640=y 123CONFIG_SOC_CAMERA_OV2640=y
133CONFIG_FB=y 124CONFIG_FB=y
134CONFIG_FB_IMX=y 125CONFIG_FB_IMX=y
135CONFIG_BACKLIGHT_LCD_SUPPORT=y
136CONFIG_LCD_CLASS_DEVICE=y
137CONFIG_LCD_L4F00242T03=y 126CONFIG_LCD_L4F00242T03=y
138CONFIG_BACKLIGHT_CLASS_DEVICE=y
139CONFIG_FRAMEBUFFER_CONSOLE=y 127CONFIG_FRAMEBUFFER_CONSOLE=y
140CONFIG_LOGO=y 128CONFIG_LOGO=y
141CONFIG_SOUND=y 129CONFIG_SOUND=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 16cfec4385c8..8fca6e276b69 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,8 +32,8 @@ CONFIG_MACH_IMX35_DT=y
32CONFIG_MACH_PCM043=y 32CONFIG_MACH_PCM043=y
33CONFIG_MACH_MX35_3DS=y 33CONFIG_MACH_MX35_3DS=y
34CONFIG_MACH_VPR200=y 34CONFIG_MACH_VPR200=y
35CONFIG_SOC_IMX51=y
36CONFIG_SOC_IMX50=y 35CONFIG_SOC_IMX50=y
36CONFIG_SOC_IMX51=y
37CONFIG_SOC_IMX53=y 37CONFIG_SOC_IMX53=y
38CONFIG_SOC_IMX6Q=y 38CONFIG_SOC_IMX6Q=y
39CONFIG_SOC_IMX6SL=y 39CONFIG_SOC_IMX6SL=y
@@ -105,7 +105,6 @@ CONFIG_EEPROM_AT24=y
105CONFIG_EEPROM_AT25=y 105CONFIG_EEPROM_AT25=y
106# CONFIG_SCSI_PROC_FS is not set 106# CONFIG_SCSI_PROC_FS is not set
107CONFIG_BLK_DEV_SD=y 107CONFIG_BLK_DEV_SD=y
108CONFIG_SCSI_MULTI_LUN=y
109CONFIG_SCSI_CONSTANTS=y 108CONFIG_SCSI_CONSTANTS=y
110CONFIG_SCSI_LOGGING=y 109CONFIG_SCSI_LOGGING=y
111CONFIG_SCSI_SCAN_ASYNC=y 110CONFIG_SCSI_SCAN_ASYNC=y
@@ -153,14 +152,12 @@ CONFIG_SERIAL_IMX_CONSOLE=y
153CONFIG_SERIAL_FSL_LPUART=y 152CONFIG_SERIAL_FSL_LPUART=y
154CONFIG_SERIAL_FSL_LPUART_CONSOLE=y 153CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
155CONFIG_HW_RANDOM=y 154CONFIG_HW_RANDOM=y
156CONFIG_HW_RANDOM_MXC_RNGA=y
157# CONFIG_I2C_COMPAT is not set 155# CONFIG_I2C_COMPAT is not set
158CONFIG_I2C_CHARDEV=y 156CONFIG_I2C_CHARDEV=y
159# CONFIG_I2C_HELPER_AUTO is not set 157# CONFIG_I2C_HELPER_AUTO is not set
160CONFIG_I2C_ALGOPCF=m 158CONFIG_I2C_ALGOPCF=m
161CONFIG_I2C_ALGOPCA=m 159CONFIG_I2C_ALGOPCA=m
162CONFIG_I2C_IMX=y 160CONFIG_I2C_IMX=y
163CONFIG_SPI=y
164CONFIG_SPI_IMX=y 161CONFIG_SPI_IMX=y
165CONFIG_GPIO_SYSFS=y 162CONFIG_GPIO_SYSFS=y
166CONFIG_GPIO_MC9S08DZ60=y 163CONFIG_GPIO_MC9S08DZ60=y
@@ -198,7 +195,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
198CONFIG_LCD_CLASS_DEVICE=y 195CONFIG_LCD_CLASS_DEVICE=y
199CONFIG_LCD_L4F00242T03=y 196CONFIG_LCD_L4F00242T03=y
200CONFIG_LCD_PLATFORM=y 197CONFIG_LCD_PLATFORM=y
201CONFIG_BACKLIGHT_CLASS_DEVICE=y
202CONFIG_BACKLIGHT_PWM=y 198CONFIG_BACKLIGHT_PWM=y
203CONFIG_BACKLIGHT_GPIO=y 199CONFIG_BACKLIGHT_GPIO=y
204CONFIG_FRAMEBUFFER_CONSOLE=y 200CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -206,6 +202,7 @@ CONFIG_LOGO=y
206CONFIG_SOUND=y 202CONFIG_SOUND=y
207CONFIG_SND=y 203CONFIG_SND=y
208CONFIG_SND_SOC=y 204CONFIG_SND_SOC=y
205CONFIG_SND_SOC_FSL_SAI=y
209CONFIG_SND_IMX_SOC=y 206CONFIG_SND_IMX_SOC=y
210CONFIG_SND_SOC_PHYCORE_AC97=y 207CONFIG_SND_SOC_PHYCORE_AC97=y
211CONFIG_SND_SOC_EUKREA_TLV320=y 208CONFIG_SND_SOC_EUKREA_TLV320=y
@@ -213,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y
213CONFIG_SND_SOC_IMX_SGTL5000=y 210CONFIG_SND_SOC_IMX_SGTL5000=y
214CONFIG_SND_SOC_IMX_SPDIF=y 211CONFIG_SND_SOC_IMX_SPDIF=y
215CONFIG_SND_SOC_IMX_MC13783=y 212CONFIG_SND_SOC_IMX_MC13783=y
213CONFIG_SND_SIMPLE_CARD=y
216CONFIG_USB=y 214CONFIG_USB=y
217CONFIG_USB_EHCI_HCD=y 215CONFIG_USB_EHCI_HCD=y
218CONFIG_USB_EHCI_MXC=y 216CONFIG_USB_EHCI_MXC=y
@@ -240,6 +238,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
240CONFIG_LEDS_TRIGGER_GPIO=y 238CONFIG_LEDS_TRIGGER_GPIO=y
241CONFIG_RTC_CLASS=y 239CONFIG_RTC_CLASS=y
242CONFIG_RTC_INTF_DEV_UIE_EMUL=y 240CONFIG_RTC_INTF_DEV_UIE_EMUL=y
241CONFIG_RTC_DRV_ISL1208=y
243CONFIG_RTC_DRV_PCF8563=y 242CONFIG_RTC_DRV_PCF8563=y
244CONFIG_RTC_DRV_MC13XXX=y 243CONFIG_RTC_DRV_MC13XXX=y
245CONFIG_RTC_DRV_MXC=y 244CONFIG_RTC_DRV_MXC=y
@@ -254,7 +253,6 @@ CONFIG_DRM_IMX_FB_HELPER=y
254CONFIG_DRM_IMX_PARALLEL_DISPLAY=y 253CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
255CONFIG_DRM_IMX_TVE=y 254CONFIG_DRM_IMX_TVE=y
256CONFIG_DRM_IMX_LDB=y 255CONFIG_DRM_IMX_LDB=y
257CONFIG_DRM_IMX_IPUV3_CORE=y
258CONFIG_DRM_IMX_IPUV3=y 256CONFIG_DRM_IMX_IPUV3=y
259CONFIG_DRM_IMX_HDMI=y 257CONFIG_DRM_IMX_HDMI=y
260# CONFIG_IOMMU_SUPPORT is not set 258# CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index 86faab565a96..b33d19b7f134 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -15,6 +15,9 @@ CONFIG_MACH_KOELSCH=y
15CONFIG_CPU_BPREDICT_DISABLE=y 15CONFIG_CPU_BPREDICT_DISABLE=y
16CONFIG_PL310_ERRATA_588369=y 16CONFIG_PL310_ERRATA_588369=y
17CONFIG_ARM_ERRATA_754322=y 17CONFIG_ARM_ERRATA_754322=y
18CONFIG_PCI=y
19CONFIG_PCI_RCAR_GEN2=y
20CONFIG_PCI_RCAR_GEN2_PCIE=y
18CONFIG_SMP=y 21CONFIG_SMP=y
19CONFIG_SCHED_MC=y 22CONFIG_SCHED_MC=y
20CONFIG_NR_CPUS=8 23CONFIG_NR_CPUS=8
@@ -42,6 +45,8 @@ CONFIG_ATA=y
42CONFIG_SATA_RCAR=y 45CONFIG_SATA_RCAR=y
43CONFIG_MTD=y 46CONFIG_MTD=y
44CONFIG_MTD_M25P80=y 47CONFIG_MTD_M25P80=y
48CONFIG_MTD_SPI_NOR=y
49CONFIG_EEPROM_AT24=y
45CONFIG_NETDEVICES=y 50CONFIG_NETDEVICES=y
46# CONFIG_NET_VENDOR_ARC is not set 51# CONFIG_NET_VENDOR_ARC is not set
47# CONFIG_NET_CADENCE is not set 52# CONFIG_NET_CADENCE is not set
@@ -66,9 +71,12 @@ CONFIG_SERIAL_SH_SCI=y
66CONFIG_SERIAL_SH_SCI_NR_UARTS=20 71CONFIG_SERIAL_SH_SCI_NR_UARTS=20
67CONFIG_SERIAL_SH_SCI_CONSOLE=y 72CONFIG_SERIAL_SH_SCI_CONSOLE=y
68CONFIG_I2C=y 73CONFIG_I2C=y
74CONFIG_I2C_MUX=y
75CONFIG_I2C_SH_MOBILE=y
69CONFIG_I2C_RCAR=y 76CONFIG_I2C_RCAR=y
70CONFIG_SPI=y 77CONFIG_SPI=y
71CONFIG_SPI_RSPI=y 78CONFIG_SPI_RSPI=y
79CONFIG_SPI_SH_MSIOF=y
72CONFIG_GPIOLIB=y 80CONFIG_GPIOLIB=y
73CONFIG_GPIO_RCAR=y 81CONFIG_GPIO_RCAR=y
74# CONFIG_HWMON is not set 82# CONFIG_HWMON is not set
@@ -76,7 +84,16 @@ CONFIG_THERMAL=y
76CONFIG_RCAR_THERMAL=y 84CONFIG_RCAR_THERMAL=y
77CONFIG_REGULATOR=y 85CONFIG_REGULATOR=y
78CONFIG_REGULATOR_FIXED_VOLTAGE=y 86CONFIG_REGULATOR_FIXED_VOLTAGE=y
87CONFIG_REGULATOR_DA9210=y
79CONFIG_REGULATOR_GPIO=y 88CONFIG_REGULATOR_GPIO=y
89CONFIG_MEDIA_SUPPORT=y
90CONFIG_MEDIA_CAMERA_SUPPORT=y
91CONFIG_V4L_PLATFORM_DRIVERS=y
92CONFIG_SOC_CAMERA=y
93CONFIG_SOC_CAMERA_PLATFORM=y
94CONFIG_VIDEO_RCAR_VIN=y
95# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
96CONFIG_VIDEO_ADV7180=y
80# CONFIG_HID is not set 97# CONFIG_HID is not set
81# CONFIG_USB_SUPPORT is not set 98# CONFIG_USB_SUPPORT is not set
82CONFIG_MMC=y 99CONFIG_MMC=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index bd097d455f87..8cb115d74fdf 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -119,6 +119,7 @@ CONFIG_MMC_SDHI=y
119CONFIG_MMC_SH_MMCIF=y 119CONFIG_MMC_SH_MMCIF=y
120CONFIG_NEW_LEDS=y 120CONFIG_NEW_LEDS=y
121CONFIG_LEDS_CLASS=y 121CONFIG_LEDS_CLASS=y
122CONFIG_LEDS_GPIO=y
122CONFIG_RTC_CLASS=y 123CONFIG_RTC_CLASS=y
123CONFIG_RTC_DRV_RS5C372=y 124CONFIG_RTC_DRV_RS5C372=y
124CONFIG_DMADEVICES=y 125CONFIG_DMADEVICES=y
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 58702440472a..929c571ea29b 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -22,6 +22,9 @@ CONFIG_ARM_ERRATA_458693=y
22CONFIG_ARM_ERRATA_460075=y 22CONFIG_ARM_ERRATA_460075=y
23CONFIG_ARM_ERRATA_743622=y 23CONFIG_ARM_ERRATA_743622=y
24CONFIG_ARM_ERRATA_754322=y 24CONFIG_ARM_ERRATA_754322=y
25CONFIG_PCI=y
26CONFIG_PCI_RCAR_GEN2=y
27CONFIG_PCI_RCAR_GEN2_PCIE=y
25CONFIG_HAVE_ARM_ARCH_TIMER=y 28CONFIG_HAVE_ARM_ARCH_TIMER=y
26CONFIG_AEABI=y 29CONFIG_AEABI=y
27# CONFIG_OABI_COMPAT is not set 30# CONFIG_OABI_COMPAT is not set
@@ -53,6 +56,7 @@ CONFIG_DEVTMPFS=y
53CONFIG_DEVTMPFS_MOUNT=y 56CONFIG_DEVTMPFS_MOUNT=y
54CONFIG_MTD=y 57CONFIG_MTD=y
55CONFIG_MTD_M25P80=y 58CONFIG_MTD_M25P80=y
59CONFIG_MTD_SPI_NOR=y
56CONFIG_BLK_DEV_SD=y 60CONFIG_BLK_DEV_SD=y
57CONFIG_ATA=y 61CONFIG_ATA=y
58CONFIG_SATA_RCAR=y 62CONFIG_SATA_RCAR=y
@@ -85,11 +89,12 @@ CONFIG_SERIAL_SH_SCI=y
85CONFIG_SERIAL_SH_SCI_NR_UARTS=10 89CONFIG_SERIAL_SH_SCI_NR_UARTS=10
86CONFIG_SERIAL_SH_SCI_CONSOLE=y 90CONFIG_SERIAL_SH_SCI_CONSOLE=y
87# CONFIG_HW_RANDOM is not set 91# CONFIG_HW_RANDOM is not set
88CONFIG_I2C=y
89CONFIG_I2C_GPIO=y 92CONFIG_I2C_GPIO=y
93CONFIG_I2C_SH_MOBILE=y
90CONFIG_I2C_RCAR=y 94CONFIG_I2C_RCAR=y
91CONFIG_SPI=y 95CONFIG_SPI=y
92CONFIG_SPI_RSPI=y 96CONFIG_SPI_RSPI=y
97CONFIG_SPI_SH_MSIOF=y
93CONFIG_GPIO_SH_PFC=y 98CONFIG_GPIO_SH_PFC=y
94CONFIG_GPIOLIB=y 99CONFIG_GPIOLIB=y
95CONFIG_GPIO_RCAR=y 100CONFIG_GPIO_RCAR=y
@@ -98,6 +103,7 @@ CONFIG_THERMAL=y
98CONFIG_RCAR_THERMAL=y 103CONFIG_RCAR_THERMAL=y
99CONFIG_REGULATOR=y 104CONFIG_REGULATOR=y
100CONFIG_REGULATOR_FIXED_VOLTAGE=y 105CONFIG_REGULATOR_FIXED_VOLTAGE=y
106CONFIG_REGULATOR_DA9210=y
101CONFIG_REGULATOR_GPIO=y 107CONFIG_REGULATOR_GPIO=y
102CONFIG_MEDIA_SUPPORT=y 108CONFIG_MEDIA_SUPPORT=y
103CONFIG_MEDIA_CAMERA_SUPPORT=y 109CONFIG_MEDIA_CAMERA_SUPPORT=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 398a367ffce8..9f56ca3985ae 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -59,6 +59,7 @@ CONFIG_MTD_M25P80=y
59CONFIG_MTD_NAND=y 59CONFIG_MTD_NAND=y
60CONFIG_MTD_NAND_SLC_LPC32XX=y 60CONFIG_MTD_NAND_SLC_LPC32XX=y
61CONFIG_MTD_NAND_MLC_LPC32XX=y 61CONFIG_MTD_NAND_MLC_LPC32XX=y
62CONFIG_MTD_UBI=y
62CONFIG_BLK_DEV_LOOP=y 63CONFIG_BLK_DEV_LOOP=y
63CONFIG_BLK_DEV_CRYPTOLOOP=y 64CONFIG_BLK_DEV_CRYPTOLOOP=y
64CONFIG_BLK_DEV_RAM=y 65CONFIG_BLK_DEV_RAM=y
@@ -189,6 +190,7 @@ CONFIG_VFAT_FS=y
189CONFIG_TMPFS=y 190CONFIG_TMPFS=y
190CONFIG_JFFS2_FS=y 191CONFIG_JFFS2_FS=y
191CONFIG_JFFS2_FS_WBUF_VERIFY=y 192CONFIG_JFFS2_FS_WBUF_VERIFY=y
193CONFIG_UBIFS_FS=y
192CONFIG_CRAMFS=y 194CONFIG_CRAMFS=y
193CONFIG_NFS_FS=y 195CONFIG_NFS_FS=y
194CONFIG_ROOT_NFS=y 196CONFIG_ROOT_NFS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 92994f7f6fd8..ff91630d34e1 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -84,6 +84,7 @@ CONFIG_GPIO_RCAR=y
84CONFIG_THERMAL=y 84CONFIG_THERMAL=y
85CONFIG_RCAR_THERMAL=y 85CONFIG_RCAR_THERMAL=y
86CONFIG_SSB=y 86CONFIG_SSB=y
87CONFIG_REGULATOR=y
87CONFIG_MEDIA_SUPPORT=y 88CONFIG_MEDIA_SUPPORT=y
88CONFIG_MEDIA_CAMERA_SUPPORT=y 89CONFIG_MEDIA_CAMERA_SUPPORT=y
89CONFIG_V4L_PLATFORM_DRIVERS=y 90CONFIG_V4L_PLATFORM_DRIVERS=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fb95fb758d9..491b7d5523bf 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -28,7 +28,9 @@ CONFIG_ARCH_HIGHBANK=y
28CONFIG_ARCH_HISI=y 28CONFIG_ARCH_HISI=y
29CONFIG_ARCH_HI3xxx=y 29CONFIG_ARCH_HI3xxx=y
30CONFIG_ARCH_HIX5HD2=y 30CONFIG_ARCH_HIX5HD2=y
31CONFIG_ARCH_HIP04=y
31CONFIG_ARCH_KEYSTONE=y 32CONFIG_ARCH_KEYSTONE=y
33CONFIG_ARCH_MESON=y
32CONFIG_ARCH_MXC=y 34CONFIG_ARCH_MXC=y
33CONFIG_SOC_IMX51=y 35CONFIG_SOC_IMX51=y
34CONFIG_SOC_IMX53=y 36CONFIG_SOC_IMX53=y
@@ -42,6 +44,7 @@ CONFIG_SOC_AM33XX=y
42CONFIG_SOC_AM43XX=y 44CONFIG_SOC_AM43XX=y
43CONFIG_SOC_DRA7XX=y 45CONFIG_SOC_DRA7XX=y
44CONFIG_ARCH_QCOM=y 46CONFIG_ARCH_QCOM=y
47CONFIG_ARCH_MEDIATEK=y
45CONFIG_ARCH_MSM8X60=y 48CONFIG_ARCH_MSM8X60=y
46CONFIG_ARCH_MSM8960=y 49CONFIG_ARCH_MSM8960=y
47CONFIG_ARCH_MSM8974=y 50CONFIG_ARCH_MSM8974=y
@@ -74,6 +77,7 @@ CONFIG_PCI=y
74CONFIG_PCI_MSI=y 77CONFIG_PCI_MSI=y
75CONFIG_PCI_MVEBU=y 78CONFIG_PCI_MVEBU=y
76CONFIG_PCI_TEGRA=y 79CONFIG_PCI_TEGRA=y
80CONFIG_PCIEPORTBUS=y
77CONFIG_SMP=y 81CONFIG_SMP=y
78CONFIG_NR_CPUS=8 82CONFIG_NR_CPUS=8
79CONFIG_HIGHPTE=y 83CONFIG_HIGHPTE=y
@@ -86,6 +90,7 @@ CONFIG_CPU_FREQ_STAT_DETAILS=y
86CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 90CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
87CONFIG_CPU_IDLE=y 91CONFIG_CPU_IDLE=y
88CONFIG_NEON=y 92CONFIG_NEON=y
93CONFIG_ARM_ZYNQ_CPUIDLE=y
89CONFIG_NET=y 94CONFIG_NET=y
90CONFIG_PACKET=y 95CONFIG_PACKET=y
91CONFIG_UNIX=y 96CONFIG_UNIX=y
@@ -106,6 +111,7 @@ CONFIG_CAN=y
106CONFIG_CAN_RAW=y 111CONFIG_CAN_RAW=y
107CONFIG_CAN_BCM=y 112CONFIG_CAN_BCM=y
108CONFIG_CAN_DEV=y 113CONFIG_CAN_DEV=y
114CONFIG_CAN_XILINXCAN=y
109CONFIG_CAN_MCP251X=y 115CONFIG_CAN_MCP251X=y
110CONFIG_CFG80211=m 116CONFIG_CFG80211=m
111CONFIG_MAC80211=m 117CONFIG_MAC80211=m
@@ -119,7 +125,10 @@ CONFIG_CMA_SIZE_MBYTES=64
119CONFIG_OMAP_OCP2SCP=y 125CONFIG_OMAP_OCP2SCP=y
120CONFIG_MTD=y 126CONFIG_MTD=y
121CONFIG_MTD_M25P80=y 127CONFIG_MTD_M25P80=y
128CONFIG_MTD_SPI_NOR=y
122CONFIG_BLK_DEV_LOOP=y 129CONFIG_BLK_DEV_LOOP=y
130CONFIG_AD525X_DPOT=y
131CONFIG_AD525X_DPOT_I2C=y
123CONFIG_ICS932S401=y 132CONFIG_ICS932S401=y
124CONFIG_APDS9802ALS=y 133CONFIG_APDS9802ALS=y
125CONFIG_ISL29003=y 134CONFIG_ISL29003=y
@@ -129,9 +138,11 @@ CONFIG_BLK_DEV_SD=y
129CONFIG_BLK_DEV_SR=y 138CONFIG_BLK_DEV_SR=y
130CONFIG_SCSI_MULTI_LUN=y 139CONFIG_SCSI_MULTI_LUN=y
131CONFIG_ATA=y 140CONFIG_ATA=y
141CONFIG_SATA_AHCI=y
132CONFIG_SATA_AHCI_PLATFORM=y 142CONFIG_SATA_AHCI_PLATFORM=y
133CONFIG_AHCI_ST=y 143CONFIG_AHCI_ST=y
134CONFIG_AHCI_SUNXI=y 144CONFIG_AHCI_SUNXI=y
145CONFIG_AHCI_TEGRA=y
135CONFIG_SATA_HIGHBANK=y 146CONFIG_SATA_HIGHBANK=y
136CONFIG_SATA_MV=y 147CONFIG_SATA_MV=y
137CONFIG_NETDEVICES=y 148CONFIG_NETDEVICES=y
@@ -146,6 +157,7 @@ CONFIG_R8169=y
146CONFIG_SMSC911X=y 157CONFIG_SMSC911X=y
147CONFIG_STMMAC_ETH=y 158CONFIG_STMMAC_ETH=y
148CONFIG_TI_CPSW=y 159CONFIG_TI_CPSW=y
160CONFIG_XILINX_EMACLITE=y
149CONFIG_AT803X_PHY=y 161CONFIG_AT803X_PHY=y
150CONFIG_MARVELL_PHY=y 162CONFIG_MARVELL_PHY=y
151CONFIG_ICPLUS_PHY=y 163CONFIG_ICPLUS_PHY=y
@@ -156,6 +168,7 @@ CONFIG_USB_NET_SMSC95XX=y
156CONFIG_BRCMFMAC=m 168CONFIG_BRCMFMAC=m
157CONFIG_RT2X00=m 169CONFIG_RT2X00=m
158CONFIG_RT2800USB=m 170CONFIG_RT2800USB=m
171CONFIG_INPUT_JOYDEV=y
159CONFIG_INPUT_EVDEV=y 172CONFIG_INPUT_EVDEV=y
160CONFIG_KEYBOARD_GPIO=y 173CONFIG_KEYBOARD_GPIO=y
161CONFIG_KEYBOARD_TEGRA=y 174CONFIG_KEYBOARD_TEGRA=y
@@ -164,6 +177,7 @@ CONFIG_KEYBOARD_ST_KEYSCAN=y
164CONFIG_KEYBOARD_CROS_EC=y 177CONFIG_KEYBOARD_CROS_EC=y
165CONFIG_MOUSE_PS2_ELANTECH=y 178CONFIG_MOUSE_PS2_ELANTECH=y
166CONFIG_INPUT_TOUCHSCREEN=y 179CONFIG_INPUT_TOUCHSCREEN=y
180CONFIG_TOUCHSCREEN_ATMEL_MXT=y
167CONFIG_TOUCHSCREEN_STMPE=y 181CONFIG_TOUCHSCREEN_STMPE=y
168CONFIG_INPUT_MISC=y 182CONFIG_INPUT_MISC=y
169CONFIG_INPUT_MPU3050=y 183CONFIG_INPUT_MPU3050=y
@@ -173,6 +187,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
173CONFIG_SERIAL_8250_DW=y 187CONFIG_SERIAL_8250_DW=y
174CONFIG_SERIAL_AMBA_PL011=y 188CONFIG_SERIAL_AMBA_PL011=y
175CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 189CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
190CONFIG_SERIAL_MESON=y
191CONFIG_SERIAL_MESON_CONSOLE=y
176CONFIG_SERIAL_SAMSUNG=y 192CONFIG_SERIAL_SAMSUNG=y
177CONFIG_SERIAL_SAMSUNG_CONSOLE=y 193CONFIG_SERIAL_SAMSUNG_CONSOLE=y
178CONFIG_SERIAL_SIRFSOC=y 194CONFIG_SERIAL_SIRFSOC=y
@@ -205,6 +221,8 @@ CONFIG_I2C_SIRF=y
205CONFIG_I2C_TEGRA=y 221CONFIG_I2C_TEGRA=y
206CONFIG_I2C_ST=y 222CONFIG_I2C_ST=y
207CONFIG_SPI=y 223CONFIG_SPI=y
224CONFIG_I2C_XILINX=y
225CONFIG_SPI_CADENCE=y
208CONFIG_SPI_OMAP24XX=y 226CONFIG_SPI_OMAP24XX=y
209CONFIG_SPI_ORION=y 227CONFIG_SPI_ORION=y
210CONFIG_SPI_PL022=y 228CONFIG_SPI_PL022=y
@@ -214,11 +232,14 @@ CONFIG_SPI_SUN6I=y
214CONFIG_SPI_TEGRA114=y 232CONFIG_SPI_TEGRA114=y
215CONFIG_SPI_TEGRA20_SFLASH=y 233CONFIG_SPI_TEGRA20_SFLASH=y
216CONFIG_SPI_TEGRA20_SLINK=y 234CONFIG_SPI_TEGRA20_SLINK=y
235CONFIG_SPI_XILINX=y
217CONFIG_PINCTRL_AS3722=y 236CONFIG_PINCTRL_AS3722=y
218CONFIG_PINCTRL_PALMAS=y 237CONFIG_PINCTRL_PALMAS=y
219CONFIG_GPIO_SYSFS=y 238CONFIG_GPIO_SYSFS=y
220CONFIG_GPIO_GENERIC_PLATFORM=y 239CONFIG_GPIO_GENERIC_PLATFORM=y
221CONFIG_GPIO_DWAPB=y 240CONFIG_GPIO_DWAPB=y
241CONFIG_GPIO_XILINX=y
242CONFIG_GPIO_ZYNQ=y
222CONFIG_GPIO_PCA953X=y 243CONFIG_GPIO_PCA953X=y
223CONFIG_GPIO_PCA953X_IRQ=y 244CONFIG_GPIO_PCA953X_IRQ=y
224CONFIG_GPIO_TWL4030=y 245CONFIG_GPIO_TWL4030=y
@@ -237,6 +258,7 @@ CONFIG_ARMADA_THERMAL=y
237CONFIG_ST_THERMAL_SYSCFG=y 258CONFIG_ST_THERMAL_SYSCFG=y
238CONFIG_ST_THERMAL_MEMMAP=y 259CONFIG_ST_THERMAL_MEMMAP=y
239CONFIG_WATCHDOG=y 260CONFIG_WATCHDOG=y
261CONFIG_XILINX_WATCHDOG=y
240CONFIG_ORION_WATCHDOG=y 262CONFIG_ORION_WATCHDOG=y
241CONFIG_SUNXI_WATCHDOG=y 263CONFIG_SUNXI_WATCHDOG=y
242CONFIG_MFD_AS3722=y 264CONFIG_MFD_AS3722=y
@@ -250,7 +272,6 @@ CONFIG_MFD_PALMAS=y
250CONFIG_MFD_TPS65090=y 272CONFIG_MFD_TPS65090=y
251CONFIG_MFD_TPS6586X=y 273CONFIG_MFD_TPS6586X=y
252CONFIG_MFD_TPS65910=y 274CONFIG_MFD_TPS65910=y
253CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
254CONFIG_REGULATOR_AB8500=y 275CONFIG_REGULATOR_AB8500=y
255CONFIG_REGULATOR_AS3722=y 276CONFIG_REGULATOR_AS3722=y
256CONFIG_REGULATOR_BCM590XX=y 277CONFIG_REGULATOR_BCM590XX=y
@@ -281,6 +302,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
281CONFIG_BACKLIGHT_CLASS_DEVICE=y 302CONFIG_BACKLIGHT_CLASS_DEVICE=y
282CONFIG_BACKLIGHT_PWM=y 303CONFIG_BACKLIGHT_PWM=y
283CONFIG_FRAMEBUFFER_CONSOLE=y 304CONFIG_FRAMEBUFFER_CONSOLE=y
305CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
284CONFIG_SOUND=y 306CONFIG_SOUND=y
285CONFIG_SND=y 307CONFIG_SND=y
286CONFIG_SND_SOC=y 308CONFIG_SND_SOC=y
@@ -333,7 +355,18 @@ CONFIG_MMC_DW=y
333CONFIG_MMC_DW_EXYNOS=y 355CONFIG_MMC_DW_EXYNOS=y
334CONFIG_NEW_LEDS=y 356CONFIG_NEW_LEDS=y
335CONFIG_LEDS_CLASS=y 357CONFIG_LEDS_CLASS=y
358CONFIG_LEDS_GPIO=y
336CONFIG_LEDS_PWM=y 359CONFIG_LEDS_PWM=y
360CONFIG_LEDS_TRIGGERS=y
361CONFIG_LEDS_TRIGGER_TIMER=y
362CONFIG_LEDS_TRIGGER_ONESHOT=y
363CONFIG_LEDS_TRIGGER_HEARTBEAT=y
364CONFIG_LEDS_TRIGGER_BACKLIGHT=y
365CONFIG_LEDS_TRIGGER_CPU=y
366CONFIG_LEDS_TRIGGER_GPIO=y
367CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
368CONFIG_LEDS_TRIGGER_TRANSIENT=y
369CONFIG_LEDS_TRIGGER_CAMERA=y
337CONFIG_EDAC=y 370CONFIG_EDAC=y
338CONFIG_EDAC_MM_EDAC=y 371CONFIG_EDAC_MM_EDAC=y
339CONFIG_EDAC_HIGHBANK_MC=y 372CONFIG_EDAC_HIGHBANK_MC=y
@@ -349,6 +382,7 @@ CONFIG_RTC_DRV_TPS65910=y
349CONFIG_RTC_DRV_EM3027=y 382CONFIG_RTC_DRV_EM3027=y
350CONFIG_RTC_DRV_PL031=y 383CONFIG_RTC_DRV_PL031=y
351CONFIG_RTC_DRV_VT8500=y 384CONFIG_RTC_DRV_VT8500=y
385CONFIG_RTC_DRV_SUN6I=y
352CONFIG_RTC_DRV_SUNXI=y 386CONFIG_RTC_DRV_SUNXI=y
353CONFIG_RTC_DRV_MV=y 387CONFIG_RTC_DRV_MV=y
354CONFIG_RTC_DRV_TEGRA=y 388CONFIG_RTC_DRV_TEGRA=y
@@ -364,6 +398,7 @@ CONFIG_IMX_SDMA=y
364CONFIG_IMX_DMA=y 398CONFIG_IMX_DMA=y
365CONFIG_MXS_DMA=y 399CONFIG_MXS_DMA=y
366CONFIG_DMA_OMAP=y 400CONFIG_DMA_OMAP=y
401CONFIG_XILINX_VDMA=y
367CONFIG_STAGING=y 402CONFIG_STAGING=y
368CONFIG_SENSORS_ISL29018=y 403CONFIG_SENSORS_ISL29018=y
369CONFIG_SENSORS_ISL29028=y 404CONFIG_SENSORS_ISL29028=y
@@ -371,6 +406,7 @@ CONFIG_MFD_NVEC=y
371CONFIG_KEYBOARD_NVEC=y 406CONFIG_KEYBOARD_NVEC=y
372CONFIG_SERIO_NVEC_PS2=y 407CONFIG_SERIO_NVEC_PS2=y
373CONFIG_NVEC_POWER=y 408CONFIG_NVEC_POWER=y
409CONFIG_NVEC_PAZ00=y
374CONFIG_QCOM_GSBI=y 410CONFIG_QCOM_GSBI=y
375CONFIG_COMMON_CLK_QCOM=y 411CONFIG_COMMON_CLK_QCOM=y
376CONFIG_MSM_GCC_8660=y 412CONFIG_MSM_GCC_8660=y
@@ -380,6 +416,7 @@ CONFIG_TEGRA_IOMMU_GART=y
380CONFIG_TEGRA_IOMMU_SMMU=y 416CONFIG_TEGRA_IOMMU_SMMU=y
381CONFIG_MEMORY=y 417CONFIG_MEMORY=y
382CONFIG_IIO=y 418CONFIG_IIO=y
419CONFIG_XILINX_XADC=y
383CONFIG_AK8975=y 420CONFIG_AK8975=y
384CONFIG_PWM=y 421CONFIG_PWM=y
385CONFIG_PWM_TEGRA=y 422CONFIG_PWM_TEGRA=y
@@ -403,3 +440,4 @@ CONFIG_DEBUG_FS=y
403CONFIG_MAGIC_SYSRQ=y 440CONFIG_MAGIC_SYSRQ=y
404CONFIG_LOCKUP_DETECTOR=y 441CONFIG_LOCKUP_DETECTOR=y
405CONFIG_CRYPTO_DEV_TEGRA_AES=y 442CONFIG_CRYPTO_DEV_TEGRA_AES=y
443CONFIG_GENERIC_CPUFREQ_CPU0=y
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index fdfda1fa9521..ed0a0d1be0f3 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -1,4 +1,3 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 1CONFIG_SYSVIPC=y
3CONFIG_FHANDLE=y 2CONFIG_FHANDLE=y
4CONFIG_IRQ_DOMAIN_DEBUG=y 3CONFIG_IRQ_DOMAIN_DEBUG=y
@@ -15,9 +14,6 @@ CONFIG_MACH_ARMADA_375=y
15CONFIG_MACH_ARMADA_38X=y 14CONFIG_MACH_ARMADA_38X=y
16CONFIG_MACH_ARMADA_XP=y 15CONFIG_MACH_ARMADA_XP=y
17CONFIG_MACH_DOVE=y 16CONFIG_MACH_DOVE=y
18CONFIG_NEON=y
19# CONFIG_CACHE_L2X0 is not set
20# CONFIG_SWP_EMULATE is not set
21CONFIG_PCI=y 17CONFIG_PCI=y
22CONFIG_PCI_MSI=y 18CONFIG_PCI_MSI=y
23CONFIG_PCI_MVEBU=y 19CONFIG_PCI_MVEBU=y
@@ -29,12 +25,14 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
29CONFIG_ZBOOT_ROM_BSS=0x0 25CONFIG_ZBOOT_ROM_BSS=0x0
30CONFIG_ARM_APPENDED_DTB=y 26CONFIG_ARM_APPENDED_DTB=y
31CONFIG_ARM_ATAG_DTB_COMPAT=y 27CONFIG_ARM_ATAG_DTB_COMPAT=y
28CONFIG_CPU_FREQ=y
32CONFIG_CPU_IDLE=y 29CONFIG_CPU_IDLE=y
33CONFIG_ARM_MVEBU_V7_CPUIDLE=y 30CONFIG_ARM_MVEBU_V7_CPUIDLE=y
34CONFIG_CPU_FREQ=y
35CONFIG_CPUFREQ_GENERIC=y
36CONFIG_VFP=y 31CONFIG_VFP=y
32CONFIG_NEON=y
37CONFIG_NET=y 33CONFIG_NET=y
34CONFIG_PACKET=y
35CONFIG_UNIX=y
38CONFIG_INET=y 36CONFIG_INET=y
39CONFIG_IP_PNP=y 37CONFIG_IP_PNP=y
40CONFIG_IP_PNP_DHCP=y 38CONFIG_IP_PNP_DHCP=y
@@ -44,11 +42,24 @@ CONFIG_BT_MRVL=y
44CONFIG_BT_MRVL_SDIO=y 42CONFIG_BT_MRVL_SDIO=y
45CONFIG_CFG80211=y 43CONFIG_CFG80211=y
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_DEVTMPFS=y
46CONFIG_DEVTMPFS_MOUNT=y
47CONFIG_MTD=y
48CONFIG_MTD_CFI=y
49CONFIG_MTD_CFI_INTELEXT=y
50CONFIG_MTD_CFI_AMDSTD=y
51CONFIG_MTD_CFI_STAA=y
52CONFIG_MTD_PHYSMAP_OF=y
53CONFIG_MTD_M25P80=y
54CONFIG_MTD_NAND=y
55CONFIG_MTD_NAND_PXA3xx=y
56CONFIG_MTD_SPI_NOR=y
47CONFIG_BLK_DEV_SD=y 57CONFIG_BLK_DEV_SD=y
48CONFIG_ATA=y 58CONFIG_ATA=y
49CONFIG_AHCI_MVEBU=y 59CONFIG_AHCI_MVEBU=y
50CONFIG_SATA_MV=y 60CONFIG_SATA_MV=y
51CONFIG_NETDEVICES=y 61CONFIG_NETDEVICES=y
62CONFIG_MV643XX_ETH=y
52CONFIG_MVNETA=y 63CONFIG_MVNETA=y
53CONFIG_MVPP2=y 64CONFIG_MVPP2=y
54CONFIG_MARVELL_PHY=y 65CONFIG_MARVELL_PHY=y
@@ -58,47 +69,36 @@ CONFIG_INPUT_EVDEV=y
58CONFIG_KEYBOARD_GPIO=y 69CONFIG_KEYBOARD_GPIO=y
59CONFIG_SERIAL_8250=y 70CONFIG_SERIAL_8250=y
60CONFIG_SERIAL_8250_CONSOLE=y 71CONFIG_SERIAL_8250_CONSOLE=y
72CONFIG_SERIAL_8250_DW=y
61CONFIG_SERIAL_OF_PLATFORM=y 73CONFIG_SERIAL_OF_PLATFORM=y
62CONFIG_I2C=y 74CONFIG_I2C=y
75CONFIG_I2C_MV64XXX=y
63CONFIG_SPI=y 76CONFIG_SPI=y
64CONFIG_SPI_ORION=y 77CONFIG_SPI_ORION=y
65CONFIG_I2C_MV64XXX=y
66CONFIG_MTD=y
67CONFIG_MTD_CHAR=y
68CONFIG_MTD_M25P80=y
69CONFIG_MTD_SPI_NOR=y
70CONFIG_MTD_CFI=y
71CONFIG_MTD_CFI_INTELEXT=y
72CONFIG_MTD_CFI_AMDSTD=y
73CONFIG_MTD_CFI_STAA=y
74CONFIG_MTD_PHYSMAP_OF=y
75CONFIG_MTD_NAND=y
76CONFIG_MTD_NAND_PXA3xx=y
77CONFIG_SERIAL_8250_DW=y
78CONFIG_GPIOLIB=y
79CONFIG_GPIO_SYSFS=y 78CONFIG_GPIO_SYSFS=y
79CONFIG_SENSORS_GPIO_FAN=y
80CONFIG_THERMAL=y 80CONFIG_THERMAL=y
81CONFIG_ARMADA_THERMAL=y 81CONFIG_ARMADA_THERMAL=y
82CONFIG_WATCHDOG=y
83CONFIG_ORION_WATCHDOG=y
82CONFIG_SOUND=y 84CONFIG_SOUND=y
83CONFIG_SND=y 85CONFIG_SND=y
84CONFIG_SND_SOC=y 86CONFIG_SND_SOC=y
85CONFIG_SND_KIRKWOOD_SOC=y 87CONFIG_SND_KIRKWOOD_SOC=y
86CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=y 88CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=y
87CONFIG_WATCHDOG=y
88CONFIG_ORION_WATCHDOG=y
89CONFIG_USB_SUPPORT=y
90CONFIG_USB=y 89CONFIG_USB=y
90CONFIG_USB_XHCI_HCD=y
91CONFIG_USB_XHCI_MVEBU=y
91CONFIG_USB_EHCI_HCD=y 92CONFIG_USB_EHCI_HCD=y
92CONFIG_USB_EHCI_ROOT_HUB_TT=y 93CONFIG_USB_EHCI_ROOT_HUB_TT=y
93CONFIG_USB_STORAGE=y 94CONFIG_USB_STORAGE=y
94CONFIG_USB_XHCI_HCD=y
95CONFIG_USB_XHCI_MVEBU=y
96CONFIG_MMC=y 95CONFIG_MMC=y
97CONFIG_MMC_SDHCI_PXAV3=y 96CONFIG_MMC_SDHCI=y
97CONFIG_MMC_SDHCI_PLTFM=y
98CONFIG_MMC_SDHCI_DOVE=y
98CONFIG_MMC_MVSDIO=y 99CONFIG_MMC_MVSDIO=y
99CONFIG_NEW_LEDS=y
100CONFIG_LEDS_GPIO=y 100CONFIG_LEDS_GPIO=y
101CONFIG_LEDS_CLASS=m 101CONFIG_LEDS_CLASS=y
102CONFIG_LEDS_TRIGGERS=y 102CONFIG_LEDS_TRIGGERS=y
103CONFIG_LEDS_TRIGGER_TIMER=y 103CONFIG_LEDS_TRIGGER_TIMER=y
104CONFIG_LEDS_TRIGGER_HEARTBEAT=y 104CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -107,12 +107,9 @@ CONFIG_RTC_DRV_S35390A=y
107CONFIG_RTC_DRV_MV=y 107CONFIG_RTC_DRV_MV=y
108CONFIG_DMADEVICES=y 108CONFIG_DMADEVICES=y
109CONFIG_MV_XOR=y 109CONFIG_MV_XOR=y
110CONFIG_MEMORY=y
111CONFIG_MVEBU_DEVBUS=y
112# CONFIG_IOMMU_SUPPORT is not set 110# CONFIG_IOMMU_SUPPORT is not set
113CONFIG_EXT2_FS=y 111CONFIG_MEMORY=y
114CONFIG_EXT3_FS=y 112CONFIG_EXT4_FS=y
115# CONFIG_EXT3_FS_XATTR is not set
116CONFIG_ISO9660_FS=y 113CONFIG_ISO9660_FS=y
117CONFIG_JOLIET=y 114CONFIG_JOLIET=y
118CONFIG_UDF_FS=m 115CONFIG_UDF_FS=m
@@ -126,10 +123,11 @@ CONFIG_NLS_CODEPAGE_850=y
126CONFIG_NLS_ISO8859_1=y 123CONFIG_NLS_ISO8859_1=y
127CONFIG_NLS_ISO8859_2=y 124CONFIG_NLS_ISO8859_2=y
128CONFIG_NLS_UTF8=y 125CONFIG_NLS_UTF8=y
129CONFIG_MAGIC_SYSRQ=y 126CONFIG_PRINTK_TIME=y
127CONFIG_DEBUG_INFO=y
130CONFIG_DEBUG_FS=y 128CONFIG_DEBUG_FS=y
129CONFIG_MAGIC_SYSRQ=y
131# CONFIG_SCHED_DEBUG is not set 130# CONFIG_SCHED_DEBUG is not set
132CONFIG_TIMER_STATS=y 131CONFIG_TIMER_STATS=y
133# CONFIG_DEBUG_BUGVERBOSE is not set 132# CONFIG_DEBUG_BUGVERBOSE is not set
134CONFIG_DEBUG_INFO=y
135CONFIG_DEBUG_USER=y 133CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f650f00e8cee..69c7bed3c634 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -1,11 +1,28 @@
1CONFIG_SYSVIPC=y 1CONFIG_SYSVIPC=y
2CONFIG_POSIX_MQUEUE=y 2CONFIG_POSIX_MQUEUE=y
3CONFIG_FHANDLE=y
4CONFIG_AUDIT=y
3CONFIG_NO_HZ=y 5CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y 6CONFIG_HIGH_RES_TIMERS=y
5CONFIG_BSD_PROCESS_ACCT=y 7CONFIG_BSD_PROCESS_ACCT=y
6CONFIG_IKCONFIG=y 8CONFIG_IKCONFIG=y
7CONFIG_IKCONFIG_PROC=y 9CONFIG_IKCONFIG_PROC=y
8CONFIG_LOG_BUF_SHIFT=16 10CONFIG_LOG_BUF_SHIFT=16
11CONFIG_CGROUPS=y
12CONFIG_CGROUP_FREEZER=y
13CONFIG_CGROUP_DEVICE=y
14CONFIG_CPUSETS=y
15CONFIG_CGROUP_CPUACCT=y
16CONFIG_RESOURCE_COUNTERS=y
17CONFIG_MEMCG=y
18CONFIG_MEMCG_SWAP=y
19CONFIG_MEMCG_KMEM=y
20CONFIG_CGROUP_PERF=y
21CONFIG_CGROUP_SCHED=y
22CONFIG_CFS_BANDWIDTH=y
23CONFIG_RT_GROUP_SCHED=y
24CONFIG_BLK_CGROUP=y
25CONFIG_NAMESPACES=y
9CONFIG_BLK_DEV_INITRD=y 26CONFIG_BLK_DEV_INITRD=y
10CONFIG_EXPERT=y 27CONFIG_EXPERT=y
11CONFIG_SLAB=y 28CONFIG_SLAB=y
@@ -32,19 +49,26 @@ CONFIG_SOC_OMAP5=y
32CONFIG_SOC_AM33XX=y 49CONFIG_SOC_AM33XX=y
33CONFIG_SOC_AM43XX=y 50CONFIG_SOC_AM43XX=y
34CONFIG_SOC_DRA7XX=y 51CONFIG_SOC_DRA7XX=y
35CONFIG_CACHE_L2X0=y
36CONFIG_ARM_THUMBEE=y 52CONFIG_ARM_THUMBEE=y
37CONFIG_ARM_ERRATA_411920=y 53CONFIG_ARM_ERRATA_411920=y
38CONFIG_SMP=y 54CONFIG_SMP=y
39CONFIG_NR_CPUS=2 55CONFIG_NR_CPUS=2
40CONFIG_CMA=y 56CONFIG_CMA=y
57CONFIG_SECCOMP=y
41CONFIG_ZBOOT_ROM_TEXT=0x0 58CONFIG_ZBOOT_ROM_TEXT=0x0
42CONFIG_ZBOOT_ROM_BSS=0x0 59CONFIG_ZBOOT_ROM_BSS=0x0
43CONFIG_ARM_APPENDED_DTB=y 60CONFIG_ARM_APPENDED_DTB=y
44CONFIG_ARM_ATAG_DTB_COMPAT=y 61CONFIG_ARM_ATAG_DTB_COMPAT=y
45CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" 62CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
46CONFIG_KEXEC=y 63CONFIG_KEXEC=y
47CONFIG_FPE_NWFPE=y 64CONFIG_CPU_FREQ=y
65CONFIG_CPU_FREQ_STAT_DETAILS=y
66CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
67CONFIG_CPU_FREQ_GOV_POWERSAVE=y
68CONFIG_CPU_FREQ_GOV_USERSPACE=y
69CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
70CONFIG_GENERIC_CPUFREQ_CPU0=y
71# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
48CONFIG_CPU_IDLE=y 72CONFIG_CPU_IDLE=y
49CONFIG_BINFMT_MISC=y 73CONFIG_BINFMT_MISC=y
50CONFIG_PM_DEBUG=y 74CONFIG_PM_DEBUG=y
@@ -61,7 +85,7 @@ CONFIG_IP_PNP_DHCP=y
61CONFIG_IP_PNP_BOOTP=y 85CONFIG_IP_PNP_BOOTP=y
62CONFIG_IP_PNP_RARP=y 86CONFIG_IP_PNP_RARP=y
63# CONFIG_INET_LRO is not set 87# CONFIG_INET_LRO is not set
64# CONFIG_IPV6 is not set 88CONFIG_IPV6=y
65CONFIG_NETFILTER=y 89CONFIG_NETFILTER=y
66CONFIG_CAN=m 90CONFIG_CAN=m
67CONFIG_CAN_C_CAN=m 91CONFIG_CAN_C_CAN=m
@@ -75,9 +99,6 @@ CONFIG_BT_HCIBCM203X=m
75CONFIG_BT_HCIBPA10X=m 99CONFIG_BT_HCIBPA10X=m
76CONFIG_CFG80211=m 100CONFIG_CFG80211=m
77CONFIG_MAC80211=m 101CONFIG_MAC80211=m
78CONFIG_MAC80211_RC_PID=y
79CONFIG_MAC80211_RC_DEFAULT_PID=y
80CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
81CONFIG_DEVTMPFS=y 102CONFIG_DEVTMPFS=y
82CONFIG_DEVTMPFS_MOUNT=y 103CONFIG_DEVTMPFS_MOUNT=y
83CONFIG_DMA_CMA=y 104CONFIG_DMA_CMA=y
@@ -101,9 +122,9 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
101CONFIG_SENSORS_TSL2550=m 122CONFIG_SENSORS_TSL2550=m
102CONFIG_BMP085_I2C=m 123CONFIG_BMP085_I2C=m
103CONFIG_SENSORS_LIS3_I2C=m 124CONFIG_SENSORS_LIS3_I2C=m
125CONFIG_SRAM=y
104CONFIG_SCSI=y 126CONFIG_SCSI=y
105CONFIG_BLK_DEV_SD=y 127CONFIG_BLK_DEV_SD=y
106CONFIG_SCSI_MULTI_LUN=y
107CONFIG_SCSI_SCAN_ASYNC=y 128CONFIG_SCSI_SCAN_ASYNC=y
108CONFIG_MD=y 129CONFIG_MD=y
109CONFIG_NETDEVICES=y 130CONFIG_NETDEVICES=y
@@ -138,7 +159,9 @@ CONFIG_KEYBOARD_GPIO=y
138CONFIG_KEYBOARD_MATRIX=m 159CONFIG_KEYBOARD_MATRIX=m
139CONFIG_KEYBOARD_TWL4030=y 160CONFIG_KEYBOARD_TWL4030=y
140CONFIG_INPUT_TOUCHSCREEN=y 161CONFIG_INPUT_TOUCHSCREEN=y
141CONFIG_TOUCHSCREEN_ADS7846=y 162CONFIG_TOUCHSCREEN_ADS7846=m
163CONFIG_TOUCHSCREEN_TSC2005=m
164CONFIG_TOUCHSCREEN_TSC2007=m
142CONFIG_INPUT_MISC=y 165CONFIG_INPUT_MISC=y
143CONFIG_INPUT_TWL4030_PWRBUTTON=y 166CONFIG_INPUT_TWL4030_PWRBUTTON=y
144# CONFIG_LEGACY_PTYS is not set 167# CONFIG_LEGACY_PTYS is not set
@@ -162,7 +185,13 @@ CONFIG_DEBUG_GPIO=y
162CONFIG_GPIO_SYSFS=y 185CONFIG_GPIO_SYSFS=y
163CONFIG_GPIO_TWL4030=y 186CONFIG_GPIO_TWL4030=y
164CONFIG_W1=y 187CONFIG_W1=y
165CONFIG_POWER_SUPPLY=y 188CONFIG_BATTERY_BQ27x00=m
189CONFIG_CHARGER_ISP1704=m
190CONFIG_CHARGER_TWL4030=m
191CONFIG_CHARGER_BQ2415X=m
192CONFIG_CHARGER_BQ24190=m
193CONFIG_CHARGER_BQ24735=m
194CONFIG_POWER_RESET=y
166CONFIG_POWER_AVS=y 195CONFIG_POWER_AVS=y
167CONFIG_SENSORS_LM75=m 196CONFIG_SENSORS_LM75=m
168CONFIG_THERMAL=y 197CONFIG_THERMAL=y
@@ -183,8 +212,8 @@ CONFIG_MFD_TPS65217=y
183CONFIG_MFD_TPS65218=y 212CONFIG_MFD_TPS65218=y
184CONFIG_MFD_TPS65910=y 213CONFIG_MFD_TPS65910=y
185CONFIG_TWL6040_CORE=y 214CONFIG_TWL6040_CORE=y
186CONFIG_REGULATOR_FIXED_VOLTAGE=y
187CONFIG_REGULATOR_PALMAS=y 215CONFIG_REGULATOR_PALMAS=y
216CONFIG_REGULATOR_PBIAS=y
188CONFIG_REGULATOR_TI_ABB=y 217CONFIG_REGULATOR_TI_ABB=y
189CONFIG_REGULATOR_TPS65023=y 218CONFIG_REGULATOR_TPS65023=y
190CONFIG_REGULATOR_TPS6507X=y 219CONFIG_REGULATOR_TPS6507X=y
@@ -192,12 +221,12 @@ CONFIG_REGULATOR_TPS65217=y
192CONFIG_REGULATOR_TPS65218=y 221CONFIG_REGULATOR_TPS65218=y
193CONFIG_REGULATOR_TPS65910=y 222CONFIG_REGULATOR_TPS65910=y
194CONFIG_REGULATOR_TWL4030=y 223CONFIG_REGULATOR_TWL4030=y
195CONFIG_REGULATOR_PBIAS=y
196CONFIG_FB=y 224CONFIG_FB=y
197CONFIG_FIRMWARE_EDID=y 225CONFIG_FIRMWARE_EDID=y
198CONFIG_FB_MODE_HELPERS=y 226CONFIG_FB_MODE_HELPERS=y
199CONFIG_FB_TILEBLITTING=y 227CONFIG_FB_TILEBLITTING=y
200CONFIG_OMAP2_DSS=m 228CONFIG_OMAP2_DSS=m
229CONFIG_OMAP5_DSS_HDMI=y
201CONFIG_OMAP2_DSS_SDI=y 230CONFIG_OMAP2_DSS_SDI=y
202CONFIG_OMAP2_DSS_DSI=y 231CONFIG_OMAP2_DSS_DSI=y
203CONFIG_FB_OMAP2=m 232CONFIG_FB_OMAP2=m
@@ -205,11 +234,25 @@ CONFIG_DISPLAY_ENCODER_TFP410=m
205CONFIG_DISPLAY_ENCODER_TPD12S015=m 234CONFIG_DISPLAY_ENCODER_TPD12S015=m
206CONFIG_DISPLAY_CONNECTOR_DVI=m 235CONFIG_DISPLAY_CONNECTOR_DVI=m
207CONFIG_DISPLAY_CONNECTOR_HDMI=m 236CONFIG_DISPLAY_CONNECTOR_HDMI=m
237CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=m
208CONFIG_DISPLAY_PANEL_DPI=m 238CONFIG_DISPLAY_PANEL_DPI=m
239CONFIG_DISPLAY_PANEL_DSI_CM=m
240CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m
241CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=m
242CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=m
243CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=m
244CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=m
245CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=m
209CONFIG_BACKLIGHT_LCD_SUPPORT=y 246CONFIG_BACKLIGHT_LCD_SUPPORT=y
210CONFIG_LCD_CLASS_DEVICE=y 247CONFIG_LCD_CLASS_DEVICE=y
211CONFIG_LCD_PLATFORM=y 248CONFIG_LCD_PLATFORM=y
249CONFIG_BACKLIGHT_CLASS_DEVICE=y
250CONFIG_BACKLIGHT_GENERIC=m
251CONFIG_BACKLIGHT_PWM=m
252CONFIG_BACKLIGHT_PANDORA=m
253CONFIG_BACKLIGHT_GPIO=m
212CONFIG_FRAMEBUFFER_CONSOLE=y 254CONFIG_FRAMEBUFFER_CONSOLE=y
255CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
213CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y 256CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
214CONFIG_LOGO=y 257CONFIG_LOGO=y
215CONFIG_SOUND=m 258CONFIG_SOUND=m
@@ -221,8 +264,6 @@ CONFIG_SND_DEBUG=y
221CONFIG_SND_USB_AUDIO=m 264CONFIG_SND_USB_AUDIO=m
222CONFIG_SND_SOC=m 265CONFIG_SND_SOC=m
223CONFIG_SND_OMAP_SOC=m 266CONFIG_SND_OMAP_SOC=m
224CONFIG_SND_AM33XX_SOC_EVM=m
225CONFIG_SND_DAVINCI_SOC=m
226CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m 267CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
227CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m 268CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
228CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m 269CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
@@ -233,9 +274,6 @@ CONFIG_USB_WDM=y
233CONFIG_USB_STORAGE=y 274CONFIG_USB_STORAGE=y
234CONFIG_USB_DWC3=m 275CONFIG_USB_DWC3=m
235CONFIG_USB_TEST=y 276CONFIG_USB_TEST=y
236CONFIG_NOP_USB_XCEIV=y
237CONFIG_OMAP_USB2=y
238CONFIG_TI_PIPE3=y
239CONFIG_AM335X_PHY_USB=y 277CONFIG_AM335X_PHY_USB=y
240CONFIG_USB_GADGET=y 278CONFIG_USB_GADGET=y
241CONFIG_USB_GADGET_DEBUG=y 279CONFIG_USB_GADGET_DEBUG=y
@@ -243,7 +281,6 @@ CONFIG_USB_GADGET_DEBUG_FILES=y
243CONFIG_USB_GADGET_DEBUG_FS=y 281CONFIG_USB_GADGET_DEBUG_FS=y
244CONFIG_USB_ZERO=m 282CONFIG_USB_ZERO=m
245CONFIG_MMC=y 283CONFIG_MMC=y
246CONFIG_MMC_UNSAFE_RESUME=y
247CONFIG_SDIO_UART=y 284CONFIG_SDIO_UART=y
248CONFIG_MMC_OMAP=y 285CONFIG_MMC_OMAP=y
249CONFIG_MMC_OMAP_HS=y 286CONFIG_MMC_OMAP_HS=y
@@ -267,15 +304,23 @@ CONFIG_TI_EDMA=y
267CONFIG_DMA_OMAP=y 304CONFIG_DMA_OMAP=y
268CONFIG_EXTCON=y 305CONFIG_EXTCON=y
269CONFIG_EXTCON_PALMAS=y 306CONFIG_EXTCON_PALMAS=y
307CONFIG_PWM=y
308CONFIG_PWM_TWL=y
309CONFIG_PWM_TWL_LED=y
310CONFIG_OMAP_USB2=y
311CONFIG_TI_PIPE3=y
270CONFIG_EXT2_FS=y 312CONFIG_EXT2_FS=y
271CONFIG_EXT3_FS=y 313CONFIG_EXT3_FS=y
272# CONFIG_EXT3_FS_XATTR is not set 314# CONFIG_EXT3_FS_XATTR is not set
273CONFIG_EXT4_FS=y 315CONFIG_EXT4_FS=y
316CONFIG_FANOTIFY=y
274CONFIG_QUOTA=y 317CONFIG_QUOTA=y
275CONFIG_QFMT_V2=y 318CONFIG_QFMT_V2=y
319CONFIG_AUTOFS4_FS=y
276CONFIG_MSDOS_FS=y 320CONFIG_MSDOS_FS=y
277CONFIG_VFAT_FS=y 321CONFIG_VFAT_FS=y
278CONFIG_TMPFS=y 322CONFIG_TMPFS=y
323CONFIG_TMPFS_POSIX_ACL=y
279CONFIG_JFFS2_FS=y 324CONFIG_JFFS2_FS=y
280CONFIG_JFFS2_SUMMARY=y 325CONFIG_JFFS2_SUMMARY=y
281CONFIG_JFFS2_FS_XATTR=y 326CONFIG_JFFS2_FS_XATTR=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index 60e313834b3f..5f337d7ceb5b 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -77,7 +77,6 @@ CONFIG_BATTERY_DA9030=y
77CONFIG_PMIC_DA903X=y 77CONFIG_PMIC_DA903X=y
78CONFIG_REGULATOR=y 78CONFIG_REGULATOR=y
79CONFIG_REGULATOR_DEBUG=y 79CONFIG_REGULATOR_DEBUG=y
80CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
81CONFIG_REGULATOR_DA903X=y 80CONFIG_REGULATOR_DA903X=y
82CONFIG_FB=y 81CONFIG_FB=y
83CONFIG_FB_PXA=y 82CONFIG_FB_PXA=y
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 42ebd72799e6..8c7da3319d82 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -29,6 +29,7 @@ CONFIG_HIGHPTE=y
29CONFIG_CLEANCACHE=y 29CONFIG_CLEANCACHE=y
30CONFIG_ARM_APPENDED_DTB=y 30CONFIG_ARM_APPENDED_DTB=y
31CONFIG_ARM_ATAG_DTB_COMPAT=y 31CONFIG_ARM_ATAG_DTB_COMPAT=y
32CONFIG_CPU_IDLE=y
32CONFIG_VFP=y 33CONFIG_VFP=y
33CONFIG_NEON=y 34CONFIG_NEON=y
34# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 35# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -53,14 +54,13 @@ CONFIG_DEVTMPFS_MOUNT=y
53CONFIG_MTD=y 54CONFIG_MTD=y
54CONFIG_MTD_BLOCK=y 55CONFIG_MTD_BLOCK=y
55CONFIG_MTD_M25P80=y 56CONFIG_MTD_M25P80=y
57CONFIG_MTD_SPI_NOR=y
56CONFIG_BLK_DEV_LOOP=y 58CONFIG_BLK_DEV_LOOP=y
57CONFIG_BLK_DEV_RAM=y 59CONFIG_BLK_DEV_RAM=y
58CONFIG_SCSI=y 60CONFIG_SCSI=y
59CONFIG_SCSI_TGT=y
60CONFIG_BLK_DEV_SD=y 61CONFIG_BLK_DEV_SD=y
61CONFIG_CHR_DEV_SG=y 62CONFIG_CHR_DEV_SG=y
62CONFIG_CHR_DEV_SCH=y 63CONFIG_CHR_DEV_SCH=y
63CONFIG_SCSI_MULTI_LUN=y
64CONFIG_SCSI_CONSTANTS=y 64CONFIG_SCSI_CONSTANTS=y
65CONFIG_SCSI_LOGGING=y 65CONFIG_SCSI_LOGGING=y
66CONFIG_SCSI_SCAN_ASYNC=y 66CONFIG_SCSI_SCAN_ASYNC=y
@@ -86,7 +86,6 @@ CONFIG_SERIO_LIBPS2=y
86CONFIG_SERIAL_MSM=y 86CONFIG_SERIAL_MSM=y
87CONFIG_SERIAL_MSM_CONSOLE=y 87CONFIG_SERIAL_MSM_CONSOLE=y
88CONFIG_HW_RANDOM=y 88CONFIG_HW_RANDOM=y
89CONFIG_HW_RANDOM_MSM=y
90CONFIG_I2C=y 89CONFIG_I2C=y
91CONFIG_I2C_CHARDEV=y 90CONFIG_I2C_CHARDEV=y
92CONFIG_I2C_QUP=y 91CONFIG_I2C_QUP=y
@@ -94,7 +93,9 @@ CONFIG_SPI=y
94CONFIG_SPI_QUP=y 93CONFIG_SPI_QUP=y
95CONFIG_SPMI=y 94CONFIG_SPMI=y
96CONFIG_PINCTRL_APQ8064=y 95CONFIG_PINCTRL_APQ8064=y
96CONFIG_PINCTRL_APQ8084=y
97CONFIG_PINCTRL_IPQ8064=y 97CONFIG_PINCTRL_IPQ8064=y
98CONFIG_PINCTRL_MSM8960=y
98CONFIG_PINCTRL_MSM8X74=y 99CONFIG_PINCTRL_MSM8X74=y
99CONFIG_DEBUG_GPIO=y 100CONFIG_DEBUG_GPIO=y
100CONFIG_GPIO_SYSFS=y 101CONFIG_GPIO_SYSFS=y
@@ -103,6 +104,7 @@ CONFIG_POWER_RESET=y
103CONFIG_POWER_RESET_MSM=y 104CONFIG_POWER_RESET_MSM=y
104CONFIG_THERMAL=y 105CONFIG_THERMAL=y
105CONFIG_REGULATOR=y 106CONFIG_REGULATOR=y
107CONFIG_REGULATOR_FIXED_VOLTAGE=y
106CONFIG_MEDIA_SUPPORT=y 108CONFIG_MEDIA_SUPPORT=y
107CONFIG_FB=y 109CONFIG_FB=y
108CONFIG_SOUND=y 110CONFIG_SOUND=y
@@ -124,6 +126,7 @@ CONFIG_USB_GADGET_DEBUG_FILES=y
124CONFIG_USB_GADGET_VBUS_DRAW=500 126CONFIG_USB_GADGET_VBUS_DRAW=500
125CONFIG_MMC=y 127CONFIG_MMC=y
126CONFIG_MMC_BLOCK_MINORS=16 128CONFIG_MMC_BLOCK_MINORS=16
129CONFIG_MMC_ARMMMCI=y
127CONFIG_MMC_SDHCI=y 130CONFIG_MMC_SDHCI=y
128CONFIG_MMC_SDHCI_PLTFM=y 131CONFIG_MMC_SDHCI_PLTFM=y
129CONFIG_MMC_SDHCI_MSM=y 132CONFIG_MMC_SDHCI_MSM=y
@@ -133,11 +136,14 @@ CONFIG_QCOM_BAM_DMA=y
133CONFIG_STAGING=y 136CONFIG_STAGING=y
134CONFIG_QCOM_GSBI=y 137CONFIG_QCOM_GSBI=y
135CONFIG_COMMON_CLK_QCOM=y 138CONFIG_COMMON_CLK_QCOM=y
139CONFIG_APQ_MMCC_8084=y
140CONFIG_IPQ_GCC_806X=y
136CONFIG_MSM_GCC_8660=y 141CONFIG_MSM_GCC_8660=y
137CONFIG_MSM_MMCC_8960=y 142CONFIG_MSM_MMCC_8960=y
138CONFIG_MSM_MMCC_8974=y 143CONFIG_MSM_MMCC_8974=y
139CONFIG_MSM_IOMMU=y 144CONFIG_MSM_IOMMU=y
140CONFIG_GENERIC_PHY=y 145CONFIG_PHY_QCOM_APQ8064_SATA=y
146CONFIG_PHY_QCOM_IPQ806X_SATA=y
141CONFIG_EXT2_FS=y 147CONFIG_EXT2_FS=y
142CONFIG_EXT2_FS_XATTR=y 148CONFIG_EXT2_FS_XATTR=y
143CONFIG_EXT3_FS=y 149CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 4414990521d3..c9089c927daf 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -19,9 +19,9 @@ CONFIG_MODULE_FORCE_UNLOAD=y
19CONFIG_ARCH_AT91=y 19CONFIG_ARCH_AT91=y
20CONFIG_SOC_SAM_V7=y 20CONFIG_SOC_SAM_V7=y
21CONFIG_SOC_SAMA5D3=y 21CONFIG_SOC_SAMA5D3=y
22CONFIG_SOC_SAMA5D4=y
22CONFIG_MACH_SAMA5_DT=y 23CONFIG_MACH_SAMA5_DT=y
23CONFIG_AEABI=y 24CONFIG_AEABI=y
24# CONFIG_OABI_COMPAT is not set
25CONFIG_UACCESS_WITH_MEMCPY=y 25CONFIG_UACCESS_WITH_MEMCPY=y
26CONFIG_ZBOOT_ROM_TEXT=0x0 26CONFIG_ZBOOT_ROM_TEXT=0x0
27CONFIG_ZBOOT_ROM_BSS=0x0 27CONFIG_ZBOOT_ROM_BSS=0x0
@@ -65,15 +65,14 @@ CONFIG_DEVTMPFS_MOUNT=y
65# CONFIG_PREVENT_FIRMWARE_BUILD is not set 65# CONFIG_PREVENT_FIRMWARE_BUILD is not set
66CONFIG_MTD=y 66CONFIG_MTD=y
67CONFIG_MTD_CMDLINE_PARTS=y 67CONFIG_MTD_CMDLINE_PARTS=y
68CONFIG_MTD_CHAR=y
69CONFIG_MTD_BLOCK=y 68CONFIG_MTD_BLOCK=y
70CONFIG_MTD_CFI=y 69CONFIG_MTD_CFI=y
71CONFIG_MTD_M25P80=y 70CONFIG_MTD_M25P80=y
72CONFIG_MTD_NAND=y 71CONFIG_MTD_NAND=y
73CONFIG_MTD_NAND_ATMEL=y 72CONFIG_MTD_NAND_ATMEL=y
73CONFIG_MTD_SPI_NOR=y
74CONFIG_MTD_UBI=y 74CONFIG_MTD_UBI=y
75CONFIG_MTD_UBI_GLUEBI=y 75CONFIG_MTD_UBI_GLUEBI=y
76CONFIG_PROC_DEVICETREE=y
77CONFIG_BLK_DEV_LOOP=y 76CONFIG_BLK_DEV_LOOP=y
78CONFIG_BLK_DEV_RAM=y 77CONFIG_BLK_DEV_RAM=y
79CONFIG_BLK_DEV_RAM_COUNT=4 78CONFIG_BLK_DEV_RAM_COUNT=4
@@ -83,10 +82,8 @@ CONFIG_ATMEL_SSC=y
83CONFIG_EEPROM_AT24=y 82CONFIG_EEPROM_AT24=y
84CONFIG_SCSI=y 83CONFIG_SCSI=y
85CONFIG_BLK_DEV_SD=y 84CONFIG_BLK_DEV_SD=y
86CONFIG_SCSI_MULTI_LUN=y
87# CONFIG_SCSI_LOWLEVEL is not set 85# CONFIG_SCSI_LOWLEVEL is not set
88CONFIG_NETDEVICES=y 86CONFIG_NETDEVICES=y
89CONFIG_MII=y
90CONFIG_MACB=y 87CONFIG_MACB=y
91# CONFIG_NET_VENDOR_BROADCOM is not set 88# CONFIG_NET_VENDOR_BROADCOM is not set
92# CONFIG_NET_VENDOR_CIRRUS is not set 89# CONFIG_NET_VENDOR_CIRRUS is not set
@@ -135,6 +132,8 @@ CONFIG_SPI=y
135CONFIG_SPI_ATMEL=y 132CONFIG_SPI_ATMEL=y
136CONFIG_SPI_GPIO=y 133CONFIG_SPI_GPIO=y
137CONFIG_GPIO_SYSFS=y 134CONFIG_GPIO_SYSFS=y
135CONFIG_POWER_SUPPLY=y
136CONFIG_POWER_RESET=y
138# CONFIG_HWMON is not set 137# CONFIG_HWMON is not set
139CONFIG_SSB=m 138CONFIG_SSB=m
140CONFIG_REGULATOR=y 139CONFIG_REGULATOR=y
@@ -145,6 +144,11 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
145CONFIG_BACKLIGHT_CLASS_DEVICE=y 144CONFIG_BACKLIGHT_CLASS_DEVICE=y
146# CONFIG_BACKLIGHT_GENERIC is not set 145# CONFIG_BACKLIGHT_GENERIC is not set
147CONFIG_FRAMEBUFFER_CONSOLE=y 146CONFIG_FRAMEBUFFER_CONSOLE=y
147CONFIG_SOUND=y
148CONFIG_SND=y
149CONFIG_SND_SOC=y
150CONFIG_SND_ATMEL_SOC=y
151CONFIG_SND_ATMEL_SOC_WM8904=y
148# CONFIG_HID_GENERIC is not set 152# CONFIG_HID_GENERIC is not set
149CONFIG_USB=y 153CONFIG_USB=y
150CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 154CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -165,6 +169,7 @@ CONFIG_MMC_ATMELMCI=y
165CONFIG_NEW_LEDS=y 169CONFIG_NEW_LEDS=y
166CONFIG_LEDS_CLASS=y 170CONFIG_LEDS_CLASS=y
167CONFIG_LEDS_GPIO=y 171CONFIG_LEDS_GPIO=y
172CONFIG_LEDS_PWM=y
168CONFIG_LEDS_TRIGGER_TIMER=y 173CONFIG_LEDS_TRIGGER_TIMER=y
169CONFIG_LEDS_TRIGGER_HEARTBEAT=y 174CONFIG_LEDS_TRIGGER_HEARTBEAT=y
170CONFIG_LEDS_TRIGGER_GPIO=y 175CONFIG_LEDS_TRIGGER_GPIO=y
@@ -174,6 +179,8 @@ CONFIG_DMADEVICES=y
174# CONFIG_IOMMU_SUPPORT is not set 179# CONFIG_IOMMU_SUPPORT is not set
175CONFIG_IIO=y 180CONFIG_IIO=y
176CONFIG_AT91_ADC=y 181CONFIG_AT91_ADC=y
182CONFIG_PWM=y
183CONFIG_PWM_ATMEL=y
177CONFIG_EXT4_FS=y 184CONFIG_EXT4_FS=y
178CONFIG_FANOTIFY=y 185CONFIG_FANOTIFY=y
179CONFIG_VFAT_FS=y 186CONFIG_VFAT_FS=y
@@ -188,8 +195,8 @@ CONFIG_NLS_ISO8859_1=y
188CONFIG_NLS_UTF8=y 195CONFIG_NLS_UTF8=y
189CONFIG_STRIP_ASM_SYMS=y 196CONFIG_STRIP_ASM_SYMS=y
190CONFIG_DEBUG_FS=y 197CONFIG_DEBUG_FS=y
191# CONFIG_SCHED_DEBUG is not set
192CONFIG_DEBUG_MEMORY_INIT=y 198CONFIG_DEBUG_MEMORY_INIT=y
199# CONFIG_SCHED_DEBUG is not set
193# CONFIG_FTRACE is not set 200# CONFIG_FTRACE is not set
194CONFIG_DEBUG_USER=y 201CONFIG_DEBUG_USER=y
195CONFIG_DEBUG_LL=y 202CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 3b136144cc83..d7346ad51043 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -3,6 +3,7 @@ CONFIG_NO_HZ=y
3CONFIG_IKCONFIG=y 3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y 4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16 5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_BLK_DEV_INITRD=y
6CONFIG_CC_OPTIMIZE_FOR_SIZE=y 7CONFIG_CC_OPTIMIZE_FOR_SIZE=y
7CONFIG_SYSCTL_SYSCALL=y 8CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y 9CONFIG_EMBEDDED=y
@@ -11,9 +12,11 @@ CONFIG_SLAB=y
11CONFIG_ARCH_SHMOBILE_MULTI=y 12CONFIG_ARCH_SHMOBILE_MULTI=y
12CONFIG_ARCH_EMEV2=y 13CONFIG_ARCH_EMEV2=y
13CONFIG_ARCH_R7S72100=y 14CONFIG_ARCH_R7S72100=y
15CONFIG_ARCH_R8A7740=y
14CONFIG_ARCH_R8A7779=y 16CONFIG_ARCH_R8A7779=y
15CONFIG_ARCH_R8A7790=y 17CONFIG_ARCH_R8A7790=y
16CONFIG_ARCH_R8A7791=y 18CONFIG_ARCH_R8A7791=y
19CONFIG_ARCH_R8A7794=y
17CONFIG_MACH_KOELSCH=y 20CONFIG_MACH_KOELSCH=y
18CONFIG_MACH_LAGER=y 21CONFIG_MACH_LAGER=y
19CONFIG_MACH_MARZEN=y 22CONFIG_MACH_MARZEN=y
@@ -49,6 +52,7 @@ CONFIG_DEVTMPFS=y
49CONFIG_DEVTMPFS_MOUNT=y 52CONFIG_DEVTMPFS_MOUNT=y
50CONFIG_MTD=y 53CONFIG_MTD=y
51CONFIG_MTD_M25P80=y 54CONFIG_MTD_M25P80=y
55CONFIG_MTD_SPI_NOR=y
52CONFIG_EEPROM_AT24=y 56CONFIG_EEPROM_AT24=y
53CONFIG_BLK_DEV_SD=y 57CONFIG_BLK_DEV_SD=y
54CONFIG_ATA=y 58CONFIG_ATA=y
@@ -73,6 +77,8 @@ CONFIG_SMSC_PHY=y
73# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 77# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
74CONFIG_KEYBOARD_GPIO=y 78CONFIG_KEYBOARD_GPIO=y
75# CONFIG_INPUT_MOUSE is not set 79# CONFIG_INPUT_MOUSE is not set
80CONFIG_INPUT_TOUCHSCREEN=y
81CONFIG_TOUCHSCREEN_ST1232=y
76# CONFIG_LEGACY_PTYS is not set 82# CONFIG_LEGACY_PTYS is not set
77CONFIG_SERIAL_8250=y 83CONFIG_SERIAL_8250=y
78CONFIG_SERIAL_8250_CONSOLE=y 84CONFIG_SERIAL_8250_CONSOLE=y
@@ -82,6 +88,7 @@ CONFIG_SERIAL_SH_SCI=y
82CONFIG_SERIAL_SH_SCI_NR_UARTS=20 88CONFIG_SERIAL_SH_SCI_NR_UARTS=20
83CONFIG_SERIAL_SH_SCI_CONSOLE=y 89CONFIG_SERIAL_SH_SCI_CONSOLE=y
84CONFIG_I2C_GPIO=y 90CONFIG_I2C_GPIO=y
91CONFIG_I2C_RIIC=y
85CONFIG_I2C_SH_MOBILE=y 92CONFIG_I2C_SH_MOBILE=y
86CONFIG_I2C_RCAR=y 93CONFIG_I2C_RCAR=y
87CONFIG_SPI=y 94CONFIG_SPI=y
@@ -110,10 +117,16 @@ CONFIG_VIDEO_RENESAS_VSP1=y
110CONFIG_VIDEO_ADV7180=y 117CONFIG_VIDEO_ADV7180=y
111CONFIG_DRM=y 118CONFIG_DRM=y
112CONFIG_DRM_RCAR_DU=y 119CONFIG_DRM_RCAR_DU=y
120CONFIG_BACKLIGHT_LCD_SUPPORT=y
121# CONFIG_LCD_CLASS_DEVICE is not set
122# CONFIG_BACKLIGHT_GENERIC is not set
123CONFIG_BACKLIGHT_PWM=y
113CONFIG_SOUND=y 124CONFIG_SOUND=y
114CONFIG_SND=y 125CONFIG_SND=y
115CONFIG_SND_SOC=y 126CONFIG_SND_SOC=y
127CONFIG_SND_SOC_SH4_FSI=y
116CONFIG_SND_SOC_RCAR=y 128CONFIG_SND_SOC_RCAR=y
129CONFIG_SND_SOC_WM8978=y
117CONFIG_USB=y 130CONFIG_USB=y
118CONFIG_USB_EHCI_HCD=y 131CONFIG_USB_EHCI_HCD=y
119CONFIG_USB_OHCI_HCD=y 132CONFIG_USB_OHCI_HCD=y
@@ -130,9 +143,12 @@ CONFIG_NEW_LEDS=y
130CONFIG_LEDS_CLASS=y 143CONFIG_LEDS_CLASS=y
131CONFIG_LEDS_GPIO=y 144CONFIG_LEDS_GPIO=y
132CONFIG_RTC_CLASS=y 145CONFIG_RTC_CLASS=y
146CONFIG_RTC_DRV_S35390A=y
133CONFIG_DMADEVICES=y 147CONFIG_DMADEVICES=y
134CONFIG_SH_DMAE=y 148CONFIG_SH_DMAE=y
135# CONFIG_IOMMU_SUPPORT is not set 149# CONFIG_IOMMU_SUPPORT is not set
150CONFIG_PWM=y
151CONFIG_PWM_RENESAS_TPU=y
136# CONFIG_DNOTIFY is not set 152# CONFIG_DNOTIFY is not set
137CONFIG_MSDOS_FS=y 153CONFIG_MSDOS_FS=y
138CONFIG_VFAT_FS=y 154CONFIG_VFAT_FS=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 7209bfd62074..c1a4ca4f6e6d 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -75,7 +75,6 @@ CONFIG_POWER_RESET_SUN6I=y
75CONFIG_WATCHDOG=y 75CONFIG_WATCHDOG=y
76CONFIG_SUNXI_WATCHDOG=y 76CONFIG_SUNXI_WATCHDOG=y
77CONFIG_MFD_AXP20X=y 77CONFIG_MFD_AXP20X=y
78CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
79CONFIG_REGULATOR_GPIO=y 78CONFIG_REGULATOR_GPIO=y
80CONFIG_USB=y 79CONFIG_USB=y
81CONFIG_USB_EHCI_HCD=y 80CONFIG_USB_EHCI_HCD=y
@@ -93,6 +92,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
93CONFIG_RTC_CLASS=y 92CONFIG_RTC_CLASS=y
94# CONFIG_RTC_INTF_SYSFS is not set 93# CONFIG_RTC_INTF_SYSFS is not set
95# CONFIG_RTC_INTF_PROC is not set 94# CONFIG_RTC_INTF_PROC is not set
95CONFIG_RTC_DRV_SUN6I=y
96CONFIG_RTC_DRV_SUNXI=y 96CONFIG_RTC_DRV_SUNXI=y
97# CONFIG_IOMMU_SUPPORT is not set 97# CONFIG_IOMMU_SUPPORT is not set
98CONFIG_PHY_SUN4I_USB=y 98CONFIG_PHY_SUN4I_USB=y
@@ -103,5 +103,7 @@ CONFIG_NFS_FS=y
103CONFIG_NFS_V3_ACL=y 103CONFIG_NFS_V3_ACL=y
104CONFIG_NFS_V4=y 104CONFIG_NFS_V4=y
105CONFIG_ROOT_NFS=y 105CONFIG_ROOT_NFS=y
106CONFIG_NLS_CODEPAGE_437=y
107CONFIG_NLS_ISO8859_1=y
106CONFIG_PRINTK_TIME=y 108CONFIG_PRINTK_TIME=y
107CONFIG_DEBUG_FS=y 109CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 285c433a9aad..888fc1521322 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -102,6 +102,9 @@ CONFIG_BLK_DEV_SD=y
102CONFIG_BLK_DEV_SR=y 102CONFIG_BLK_DEV_SR=y
103CONFIG_SCSI_MULTI_LUN=y 103CONFIG_SCSI_MULTI_LUN=y
104# CONFIG_SCSI_LOWLEVEL is not set 104# CONFIG_SCSI_LOWLEVEL is not set
105CONFIG_ATA=y
106CONFIG_SATA_AHCI=y
107CONFIG_AHCI_TEGRA=y
105CONFIG_NETDEVICES=y 108CONFIG_NETDEVICES=y
106CONFIG_DUMMY=y 109CONFIG_DUMMY=y
107CONFIG_IGB=y 110CONFIG_IGB=y
@@ -120,6 +123,7 @@ CONFIG_KEYBOARD_TEGRA=y
120CONFIG_KEYBOARD_CROS_EC=y 123CONFIG_KEYBOARD_CROS_EC=y
121CONFIG_MOUSE_PS2_ELANTECH=y 124CONFIG_MOUSE_PS2_ELANTECH=y
122CONFIG_INPUT_TOUCHSCREEN=y 125CONFIG_INPUT_TOUCHSCREEN=y
126CONFIG_TOUCHSCREEN_ATMEL_MXT=y
123CONFIG_TOUCHSCREEN_STMPE=y 127CONFIG_TOUCHSCREEN_STMPE=y
124CONFIG_INPUT_MISC=y 128CONFIG_INPUT_MISC=y
125CONFIG_INPUT_MPU3050=y 129CONFIG_INPUT_MPU3050=y
@@ -165,7 +169,6 @@ CONFIG_MFD_TPS6586X=y
165CONFIG_MFD_TPS65910=y 169CONFIG_MFD_TPS65910=y
166CONFIG_REGULATOR=y 170CONFIG_REGULATOR=y
167CONFIG_REGULATOR_FIXED_VOLTAGE=y 171CONFIG_REGULATOR_FIXED_VOLTAGE=y
168CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
169CONFIG_REGULATOR_AS3722=y 172CONFIG_REGULATOR_AS3722=y
170CONFIG_REGULATOR_GPIO=y 173CONFIG_REGULATOR_GPIO=y
171CONFIG_REGULATOR_MAX8907=y 174CONFIG_REGULATOR_MAX8907=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index d52b4ffe2012..ea49d37564da 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -82,5 +82,6 @@ CONFIG_MAGIC_SYSRQ=y
82CONFIG_DEBUG_KERNEL=y 82CONFIG_DEBUG_KERNEL=y
83CONFIG_DEBUG_USER=y 83CONFIG_DEBUG_USER=y
84CONFIG_DEBUG_LL=y 84CONFIG_DEBUG_LL=y
85CONFIG_DEBUG_LL_UART_PL01X=y
85CONFIG_FONTS=y 86CONFIG_FONTS=y
86CONFIG_FONT_ACORN_8x8=y 87CONFIG_FONT_ACORN_8x8=y
diff --git a/arch/arm/crypto/sha1-armv7-neon.S b/arch/arm/crypto/sha1-armv7-neon.S
index 50013c0e2864..dcd01f3f0bb0 100644
--- a/arch/arm/crypto/sha1-armv7-neon.S
+++ b/arch/arm/crypto/sha1-armv7-neon.S
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12 12#include <asm/assembler.h>
13 13
14.syntax unified 14.syntax unified
15.code 32 15.code 32
@@ -61,13 +61,13 @@
61#define RT3 r12 61#define RT3 r12
62 62
63#define W0 q0 63#define W0 q0
64#define W1 q1 64#define W1 q7
65#define W2 q2 65#define W2 q2
66#define W3 q3 66#define W3 q3
67#define W4 q4 67#define W4 q4
68#define W5 q5 68#define W5 q6
69#define W6 q6 69#define W6 q5
70#define W7 q7 70#define W7 q1
71 71
72#define tmp0 q8 72#define tmp0 q8
73#define tmp1 q9 73#define tmp1 q9
@@ -79,6 +79,11 @@
79#define qK3 q14 79#define qK3 q14
80#define qK4 q15 80#define qK4 q15
81 81
82#ifdef CONFIG_CPU_BIG_ENDIAN
83#define ARM_LE(code...)
84#else
85#define ARM_LE(code...) code
86#endif
82 87
83/* Round function macros. */ 88/* Round function macros. */
84 89
@@ -150,45 +155,45 @@
150#define W_PRECALC_00_15() \ 155#define W_PRECALC_00_15() \
151 add RWK, sp, #(WK_offs(0)); \ 156 add RWK, sp, #(WK_offs(0)); \
152 \ 157 \
153 vld1.32 {tmp0, tmp1}, [RDATA]!; \ 158 vld1.32 {W0, W7}, [RDATA]!; \
154 vrev32.8 W0, tmp0; /* big => little */ \ 159 ARM_LE(vrev32.8 W0, W0; ) /* big => little */ \
155 vld1.32 {tmp2, tmp3}, [RDATA]!; \ 160 vld1.32 {W6, W5}, [RDATA]!; \
156 vadd.u32 tmp0, W0, curK; \ 161 vadd.u32 tmp0, W0, curK; \
157 vrev32.8 W7, tmp1; /* big => little */ \ 162 ARM_LE(vrev32.8 W7, W7; ) /* big => little */ \
158 vrev32.8 W6, tmp2; /* big => little */ \ 163 ARM_LE(vrev32.8 W6, W6; ) /* big => little */ \
159 vadd.u32 tmp1, W7, curK; \ 164 vadd.u32 tmp1, W7, curK; \
160 vrev32.8 W5, tmp3; /* big => little */ \ 165 ARM_LE(vrev32.8 W5, W5; ) /* big => little */ \
161 vadd.u32 tmp2, W6, curK; \ 166 vadd.u32 tmp2, W6, curK; \
162 vst1.32 {tmp0, tmp1}, [RWK]!; \ 167 vst1.32 {tmp0, tmp1}, [RWK]!; \
163 vadd.u32 tmp3, W5, curK; \ 168 vadd.u32 tmp3, W5, curK; \
164 vst1.32 {tmp2, tmp3}, [RWK]; \ 169 vst1.32 {tmp2, tmp3}, [RWK]; \
165 170
166#define WPRECALC_00_15_0(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 171#define WPRECALC_00_15_0(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
167 vld1.32 {tmp0, tmp1}, [RDATA]!; \ 172 vld1.32 {W0, W7}, [RDATA]!; \
168 173
169#define WPRECALC_00_15_1(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 174#define WPRECALC_00_15_1(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
170 add RWK, sp, #(WK_offs(0)); \ 175 add RWK, sp, #(WK_offs(0)); \
171 176
172#define WPRECALC_00_15_2(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 177#define WPRECALC_00_15_2(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
173 vrev32.8 W0, tmp0; /* big => little */ \ 178 ARM_LE(vrev32.8 W0, W0; ) /* big => little */ \
174 179
175#define WPRECALC_00_15_3(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 180#define WPRECALC_00_15_3(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
176 vld1.32 {tmp2, tmp3}, [RDATA]!; \ 181 vld1.32 {W6, W5}, [RDATA]!; \
177 182
178#define WPRECALC_00_15_4(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 183#define WPRECALC_00_15_4(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
179 vadd.u32 tmp0, W0, curK; \ 184 vadd.u32 tmp0, W0, curK; \
180 185
181#define WPRECALC_00_15_5(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 186#define WPRECALC_00_15_5(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
182 vrev32.8 W7, tmp1; /* big => little */ \ 187 ARM_LE(vrev32.8 W7, W7; ) /* big => little */ \
183 188
184#define WPRECALC_00_15_6(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 189#define WPRECALC_00_15_6(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
185 vrev32.8 W6, tmp2; /* big => little */ \ 190 ARM_LE(vrev32.8 W6, W6; ) /* big => little */ \
186 191
187#define WPRECALC_00_15_7(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 192#define WPRECALC_00_15_7(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
188 vadd.u32 tmp1, W7, curK; \ 193 vadd.u32 tmp1, W7, curK; \
189 194
190#define WPRECALC_00_15_8(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 195#define WPRECALC_00_15_8(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
191 vrev32.8 W5, tmp3; /* big => little */ \ 196 ARM_LE(vrev32.8 W5, W5; ) /* big => little */ \
192 197
193#define WPRECALC_00_15_9(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \ 198#define WPRECALC_00_15_9(i,W,W_m04,W_m08,W_m12,W_m16,W_m20,W_m24,W_m28) \
194 vadd.u32 tmp2, W6, curK; \ 199 vadd.u32 tmp2, W6, curK; \
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 0704e0cf5571..92793ba69c40 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -99,31 +99,6 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl)
99 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); 99 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
100} 100}
101 101
102static inline void arch_counter_set_user_access(void)
103{
104 u32 cntkctl = arch_timer_get_cntkctl();
105
106 /* Disable user access to both physical/virtual counters/timers */
107 /* Also disable virtual event stream */
108 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
109 | ARCH_TIMER_USR_VT_ACCESS_EN
110 | ARCH_TIMER_VIRT_EVT_EN
111 | ARCH_TIMER_USR_VCT_ACCESS_EN
112 | ARCH_TIMER_USR_PCT_ACCESS_EN);
113 arch_timer_set_cntkctl(cntkctl);
114}
115
116static inline void arch_timer_evtstrm_enable(int divider)
117{
118 u32 cntkctl = arch_timer_get_cntkctl();
119 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
120 /* Set the divider and enable virtual event stream */
121 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
122 | ARCH_TIMER_VIRT_EVT_EN;
123 arch_timer_set_cntkctl(cntkctl);
124 elf_hwcap |= HWCAP_EVTSTRM;
125}
126
127#endif 102#endif
128 103
129#endif 104#endif
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 3040359094d9..e22c11970b7b 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -27,7 +27,7 @@
27 * strex/ldrex monitor on some implementations. The reason we can use it for 27 * strex/ldrex monitor on some implementations. The reason we can use it for
28 * atomic_set() is the clrex or dummy strex done on every exception return. 28 * atomic_set() is the clrex or dummy strex done on every exception return.
29 */ 29 */
30#define atomic_read(v) (*(volatile int *)&(v)->counter) 30#define atomic_read(v) ACCESS_ONCE((v)->counter)
31#define atomic_set(v,i) (((v)->counter) = (i)) 31#define atomic_set(v,i) (((v)->counter) = (i))
32 32
33#if __LINUX_ARM_ARCH__ >= 6 33#if __LINUX_ARM_ARCH__ >= 6
@@ -37,84 +37,47 @@
37 * store exclusive to ensure that these are atomic. We may loop 37 * store exclusive to ensure that these are atomic. We may loop
38 * to ensure that the update happens. 38 * to ensure that the update happens.
39 */ 39 */
40static inline void atomic_add(int i, atomic_t *v)
41{
42 unsigned long tmp;
43 int result;
44
45 prefetchw(&v->counter);
46 __asm__ __volatile__("@ atomic_add\n"
47"1: ldrex %0, [%3]\n"
48" add %0, %0, %4\n"
49" strex %1, %0, [%3]\n"
50" teq %1, #0\n"
51" bne 1b"
52 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
53 : "r" (&v->counter), "Ir" (i)
54 : "cc");
55}
56 40
57static inline int atomic_add_return(int i, atomic_t *v) 41#define ATOMIC_OP(op, c_op, asm_op) \
58{ 42static inline void atomic_##op(int i, atomic_t *v) \
59 unsigned long tmp; 43{ \
60 int result; 44 unsigned long tmp; \
61 45 int result; \
62 smp_mb(); 46 \
63 prefetchw(&v->counter); 47 prefetchw(&v->counter); \
64 48 __asm__ __volatile__("@ atomic_" #op "\n" \
65 __asm__ __volatile__("@ atomic_add_return\n" 49"1: ldrex %0, [%3]\n" \
66"1: ldrex %0, [%3]\n" 50" " #asm_op " %0, %0, %4\n" \
67" add %0, %0, %4\n" 51" strex %1, %0, [%3]\n" \
68" strex %1, %0, [%3]\n" 52" teq %1, #0\n" \
69" teq %1, #0\n" 53" bne 1b" \
70" bne 1b" 54 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
71 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) 55 : "r" (&v->counter), "Ir" (i) \
72 : "r" (&v->counter), "Ir" (i) 56 : "cc"); \
73 : "cc"); 57} \
74 58
75 smp_mb(); 59#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
76 60static inline int atomic_##op##_return(int i, atomic_t *v) \
77 return result; 61{ \
78} 62 unsigned long tmp; \
79 63 int result; \
80static inline void atomic_sub(int i, atomic_t *v) 64 \
81{ 65 smp_mb(); \
82 unsigned long tmp; 66 prefetchw(&v->counter); \
83 int result; 67 \
84 68 __asm__ __volatile__("@ atomic_" #op "_return\n" \
85 prefetchw(&v->counter); 69"1: ldrex %0, [%3]\n" \
86 __asm__ __volatile__("@ atomic_sub\n" 70" " #asm_op " %0, %0, %4\n" \
87"1: ldrex %0, [%3]\n" 71" strex %1, %0, [%3]\n" \
88" sub %0, %0, %4\n" 72" teq %1, #0\n" \
89" strex %1, %0, [%3]\n" 73" bne 1b" \
90" teq %1, #0\n" 74 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
91" bne 1b" 75 : "r" (&v->counter), "Ir" (i) \
92 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) 76 : "cc"); \
93 : "r" (&v->counter), "Ir" (i) 77 \
94 : "cc"); 78 smp_mb(); \
95} 79 \
96 80 return result; \
97static inline int atomic_sub_return(int i, atomic_t *v)
98{
99 unsigned long tmp;
100 int result;
101
102 smp_mb();
103 prefetchw(&v->counter);
104
105 __asm__ __volatile__("@ atomic_sub_return\n"
106"1: ldrex %0, [%3]\n"
107" sub %0, %0, %4\n"
108" strex %1, %0, [%3]\n"
109" teq %1, #0\n"
110" bne 1b"
111 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
112 : "r" (&v->counter), "Ir" (i)
113 : "cc");
114
115 smp_mb();
116
117 return result;
118} 81}
119 82
120static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) 83static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
@@ -174,33 +137,29 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
174#error SMP not supported on pre-ARMv6 CPUs 137#error SMP not supported on pre-ARMv6 CPUs
175#endif 138#endif
176 139
177static inline int atomic_add_return(int i, atomic_t *v) 140#define ATOMIC_OP(op, c_op, asm_op) \
178{ 141static inline void atomic_##op(int i, atomic_t *v) \
179 unsigned long flags; 142{ \
180 int val; 143 unsigned long flags; \
181 144 \
182 raw_local_irq_save(flags); 145 raw_local_irq_save(flags); \
183 val = v->counter; 146 v->counter c_op i; \
184 v->counter = val += i; 147 raw_local_irq_restore(flags); \
185 raw_local_irq_restore(flags); 148} \
186 149
187 return val; 150#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
188} 151static inline int atomic_##op##_return(int i, atomic_t *v) \
189#define atomic_add(i, v) (void) atomic_add_return(i, v) 152{ \
190 153 unsigned long flags; \
191static inline int atomic_sub_return(int i, atomic_t *v) 154 int val; \
192{ 155 \
193 unsigned long flags; 156 raw_local_irq_save(flags); \
194 int val; 157 v->counter c_op i; \
195 158 val = v->counter; \
196 raw_local_irq_save(flags); 159 raw_local_irq_restore(flags); \
197 val = v->counter; 160 \
198 v->counter = val -= i; 161 return val; \
199 raw_local_irq_restore(flags);
200
201 return val;
202} 162}
203#define atomic_sub(i, v) (void) atomic_sub_return(i, v)
204 163
205static inline int atomic_cmpxchg(atomic_t *v, int old, int new) 164static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
206{ 165{
@@ -228,6 +187,17 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
228 187
229#endif /* __LINUX_ARM_ARCH__ */ 188#endif /* __LINUX_ARM_ARCH__ */
230 189
190#define ATOMIC_OPS(op, c_op, asm_op) \
191 ATOMIC_OP(op, c_op, asm_op) \
192 ATOMIC_OP_RETURN(op, c_op, asm_op)
193
194ATOMIC_OPS(add, +=, add)
195ATOMIC_OPS(sub, -=, sub)
196
197#undef ATOMIC_OPS
198#undef ATOMIC_OP_RETURN
199#undef ATOMIC_OP
200
231#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 201#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
232 202
233#define atomic_inc(v) atomic_add(1, v) 203#define atomic_inc(v) atomic_add(1, v)
@@ -300,89 +270,60 @@ static inline void atomic64_set(atomic64_t *v, long long i)
300} 270}
301#endif 271#endif
302 272
303static inline void atomic64_add(long long i, atomic64_t *v) 273#define ATOMIC64_OP(op, op1, op2) \
304{ 274static inline void atomic64_##op(long long i, atomic64_t *v) \
305 long long result; 275{ \
306 unsigned long tmp; 276 long long result; \
307 277 unsigned long tmp; \
308 prefetchw(&v->counter); 278 \
309 __asm__ __volatile__("@ atomic64_add\n" 279 prefetchw(&v->counter); \
310"1: ldrexd %0, %H0, [%3]\n" 280 __asm__ __volatile__("@ atomic64_" #op "\n" \
311" adds %Q0, %Q0, %Q4\n" 281"1: ldrexd %0, %H0, [%3]\n" \
312" adc %R0, %R0, %R4\n" 282" " #op1 " %Q0, %Q0, %Q4\n" \
313" strexd %1, %0, %H0, [%3]\n" 283" " #op2 " %R0, %R0, %R4\n" \
314" teq %1, #0\n" 284" strexd %1, %0, %H0, [%3]\n" \
315" bne 1b" 285" teq %1, #0\n" \
316 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) 286" bne 1b" \
317 : "r" (&v->counter), "r" (i) 287 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
318 : "cc"); 288 : "r" (&v->counter), "r" (i) \
319} 289 : "cc"); \
320 290} \
321static inline long long atomic64_add_return(long long i, atomic64_t *v) 291
322{ 292#define ATOMIC64_OP_RETURN(op, op1, op2) \
323 long long result; 293static inline long long atomic64_##op##_return(long long i, atomic64_t *v) \
324 unsigned long tmp; 294{ \
325 295 long long result; \
326 smp_mb(); 296 unsigned long tmp; \
327 prefetchw(&v->counter); 297 \
328 298 smp_mb(); \
329 __asm__ __volatile__("@ atomic64_add_return\n" 299 prefetchw(&v->counter); \
330"1: ldrexd %0, %H0, [%3]\n" 300 \
331" adds %Q0, %Q0, %Q4\n" 301 __asm__ __volatile__("@ atomic64_" #op "_return\n" \
332" adc %R0, %R0, %R4\n" 302"1: ldrexd %0, %H0, [%3]\n" \
333" strexd %1, %0, %H0, [%3]\n" 303" " #op1 " %Q0, %Q0, %Q4\n" \
334" teq %1, #0\n" 304" " #op2 " %R0, %R0, %R4\n" \
335" bne 1b" 305" strexd %1, %0, %H0, [%3]\n" \
336 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) 306" teq %1, #0\n" \
337 : "r" (&v->counter), "r" (i) 307" bne 1b" \
338 : "cc"); 308 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
339 309 : "r" (&v->counter), "r" (i) \
340 smp_mb(); 310 : "cc"); \
341 311 \
342 return result; 312 smp_mb(); \
343} 313 \
344 314 return result; \
345static inline void atomic64_sub(long long i, atomic64_t *v)
346{
347 long long result;
348 unsigned long tmp;
349
350 prefetchw(&v->counter);
351 __asm__ __volatile__("@ atomic64_sub\n"
352"1: ldrexd %0, %H0, [%3]\n"
353" subs %Q0, %Q0, %Q4\n"
354" sbc %R0, %R0, %R4\n"
355" strexd %1, %0, %H0, [%3]\n"
356" teq %1, #0\n"
357" bne 1b"
358 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
359 : "r" (&v->counter), "r" (i)
360 : "cc");
361} 315}
362 316
363static inline long long atomic64_sub_return(long long i, atomic64_t *v) 317#define ATOMIC64_OPS(op, op1, op2) \
364{ 318 ATOMIC64_OP(op, op1, op2) \
365 long long result; 319 ATOMIC64_OP_RETURN(op, op1, op2)
366 unsigned long tmp;
367
368 smp_mb();
369 prefetchw(&v->counter);
370
371 __asm__ __volatile__("@ atomic64_sub_return\n"
372"1: ldrexd %0, %H0, [%3]\n"
373" subs %Q0, %Q0, %Q4\n"
374" sbc %R0, %R0, %R4\n"
375" strexd %1, %0, %H0, [%3]\n"
376" teq %1, #0\n"
377" bne 1b"
378 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
379 : "r" (&v->counter), "r" (i)
380 : "cc");
381 320
382 smp_mb(); 321ATOMIC64_OPS(add, adds, adc)
322ATOMIC64_OPS(sub, subs, sbc)
383 323
384 return result; 324#undef ATOMIC64_OPS
385} 325#undef ATOMIC64_OP_RETURN
326#undef ATOMIC64_OP
386 327
387static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old, 328static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
388 long long new) 329 long long new)
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 79ecb4f34ffb..10e78d00a0bb 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -466,6 +466,7 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
466 */ 466 */
467#define v7_exit_coherency_flush(level) \ 467#define v7_exit_coherency_flush(level) \
468 asm volatile( \ 468 asm volatile( \
469 ".arch armv7-a \n\t" \
469 "stmfd sp!, {fp, ip} \n\t" \ 470 "stmfd sp!, {fp, ip} \n\t" \
470 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ 471 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
471 "bic r0, r0, #"__stringify(CR_C)" \n\t" \ 472 "bic r0, r0, #"__stringify(CR_C)" \n\t" \
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index c45b61a4b4a5..85738b200023 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -265,22 +265,6 @@ extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
265 void *cpu_addr, dma_addr_t dma_addr, size_t size, 265 void *cpu_addr, dma_addr_t dma_addr, size_t size,
266 struct dma_attrs *attrs); 266 struct dma_attrs *attrs);
267 267
268static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
269 dma_addr_t *dma_handle, gfp_t flag)
270{
271 DEFINE_DMA_ATTRS(attrs);
272 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
273 return dma_alloc_attrs(dev, size, dma_handle, flag, &attrs);
274}
275
276static inline void dma_free_writecombine(struct device *dev, size_t size,
277 void *cpu_addr, dma_addr_t dma_handle)
278{
279 DEFINE_DMA_ATTRS(attrs);
280 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
281 return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
282}
283
284/* 268/*
285 * This can be called during early boot to increase the size of the atomic 269 * This can be called during early boot to increase the size of the atomic
286 * coherent DMA pool above the default value of 256KiB. It must be called 270 * coherent DMA pool above the default value of 256KiB. It must be called
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index 39eb16b0066f..bfe2a2f5a644 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -45,7 +45,7 @@ void *return_address(unsigned int);
45 45
46#else 46#else
47 47
48extern inline void *return_address(unsigned int level) 48static inline void *return_address(unsigned int level)
49{ 49{
50 return NULL; 50 return NULL;
51} 51}
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 3d23418cbddd..180567408ee8 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -178,6 +178,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
178 178
179/* PCI fixed i/o mapping */ 179/* PCI fixed i/o mapping */
180#define PCI_IO_VIRT_BASE 0xfee00000 180#define PCI_IO_VIRT_BASE 0xfee00000
181#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
181 182
182#if defined(CONFIG_PCI) 183#if defined(CONFIG_PCI)
183void pci_ioremap_set_mem_type(int mem_type); 184void pci_ioremap_set_mem_type(int mem_type);
diff --git a/arch/arm/include/asm/irq_work.h b/arch/arm/include/asm/irq_work.h
new file mode 100644
index 000000000000..712d03e5973a
--- /dev/null
+++ b/arch/arm/include/asm/irq_work.h
@@ -0,0 +1,11 @@
1#ifndef __ASM_ARM_IRQ_WORK_H
2#define __ASM_ARM_IRQ_WORK_H
3
4#include <asm/smp_plat.h>
5
6static inline bool arch_irq_work_has_interrupt(void)
7{
8 return is_smp();
9}
10
11#endif /* _ASM_ARM_IRQ_WORK_H */
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 69b746955fca..b9db269c6e61 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -149,6 +149,11 @@ static inline bool kvm_vcpu_trap_is_iabt(struct kvm_vcpu *vcpu)
149 149
150static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu) 150static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)
151{ 151{
152 return kvm_vcpu_get_hsr(vcpu) & HSR_FSC;
153}
154
155static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)
156{
152 return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE; 157 return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;
153} 158}
154 159
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 6dfb404f6c46..53036e21756b 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -19,6 +19,8 @@
19#ifndef __ARM_KVM_HOST_H__ 19#ifndef __ARM_KVM_HOST_H__
20#define __ARM_KVM_HOST_H__ 20#define __ARM_KVM_HOST_H__
21 21
22#include <linux/types.h>
23#include <linux/kvm_types.h>
22#include <asm/kvm.h> 24#include <asm/kvm.h>
23#include <asm/kvm_asm.h> 25#include <asm/kvm_asm.h>
24#include <asm/kvm_mmio.h> 26#include <asm/kvm_mmio.h>
@@ -40,9 +42,8 @@
40 42
41#include <kvm/arm_vgic.h> 43#include <kvm/arm_vgic.h>
42 44
43struct kvm_vcpu;
44u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); 45u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
45int kvm_target_cpu(void); 46int __attribute_const__ kvm_target_cpu(void);
46int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 47int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
47void kvm_reset_coprocs(struct kvm_vcpu *vcpu); 48void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
48 49
@@ -149,20 +150,17 @@ struct kvm_vcpu_stat {
149 u32 halt_wakeup; 150 u32 halt_wakeup;
150}; 151};
151 152
152struct kvm_vcpu_init;
153int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, 153int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
154 const struct kvm_vcpu_init *init); 154 const struct kvm_vcpu_init *init);
155int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 155int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
156unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 156unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
157int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 157int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
158struct kvm_one_reg;
159int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 158int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
160int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 159int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
161u64 kvm_call_hyp(void *hypfn, ...); 160u64 kvm_call_hyp(void *hypfn, ...);
162void force_vm_exit(const cpumask_t *mask); 161void force_vm_exit(const cpumask_t *mask);
163 162
164#define KVM_ARCH_WANT_MMU_NOTIFIER 163#define KVM_ARCH_WANT_MMU_NOTIFIER
165struct kvm;
166int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 164int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
167int kvm_unmap_hva_range(struct kvm *kvm, 165int kvm_unmap_hva_range(struct kvm *kvm,
168 unsigned long start, unsigned long end); 166 unsigned long start, unsigned long end);
@@ -172,7 +170,8 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
172int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 170int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
173 171
174/* We do not have shadow page tables, hence the empty hooks */ 172/* We do not have shadow page tables, hence the empty hooks */
175static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva) 173static inline int kvm_age_hva(struct kvm *kvm, unsigned long start,
174 unsigned long end)
176{ 175{
177 return 0; 176 return 0;
178} 177}
@@ -182,12 +181,16 @@ static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
182 return 0; 181 return 0;
183} 182}
184 183
184static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
185 unsigned long address)
186{
187}
188
185struct kvm_vcpu *kvm_arm_get_running_vcpu(void); 189struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
186struct kvm_vcpu __percpu **kvm_get_running_vcpus(void); 190struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
187 191
188int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 192int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
189unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu); 193unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
190struct kvm_one_reg;
191int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); 194int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
192int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); 195int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
193 196
@@ -233,4 +236,10 @@ static inline void vgic_arch_setup(const struct vgic_params *vgic)
233int kvm_perf_init(void); 236int kvm_perf_init(void);
234int kvm_perf_teardown(void); 237int kvm_perf_teardown(void);
235 238
239static inline void kvm_arch_hardware_disable(void) {}
240static inline void kvm_arch_hardware_unsetup(void) {}
241static inline void kvm_arch_sync_events(struct kvm *kvm) {}
242static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
243static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
244
236#endif /* __ARM_KVM_HOST_H__ */ 245#endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 5cc0b0f5f72f..3f688b458143 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -78,17 +78,6 @@ static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
78 flush_pmd_entry(pte); 78 flush_pmd_entry(pte);
79} 79}
80 80
81static inline bool kvm_is_write_fault(unsigned long hsr)
82{
83 unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
84 if (hsr_ec == HSR_EC_IABT)
85 return false;
86 else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
87 return false;
88 else
89 return true;
90}
91
92static inline void kvm_clean_pgd(pgd_t *pgd) 81static inline void kvm_clean_pgd(pgd_t *pgd)
93{ 82{
94 clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t)); 83 clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h
index 57ff7f2a3084..d428e386c88e 100644
--- a/arch/arm/include/asm/mcpm.h
+++ b/arch/arm/include/asm/mcpm.h
@@ -20,7 +20,12 @@
20 * to consider dynamic allocation. 20 * to consider dynamic allocation.
21 */ 21 */
22#define MAX_CPUS_PER_CLUSTER 4 22#define MAX_CPUS_PER_CLUSTER 4
23
24#ifdef CONFIG_MCPM_QUAD_CLUSTER
25#define MAX_NR_CLUSTERS 4
26#else
23#define MAX_NR_CLUSTERS 2 27#define MAX_NR_CLUSTERS 2
28#endif
24 29
25#ifndef __ASSEMBLY__ 30#ifndef __ASSEMBLY__
26 31
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 219ac88a9542..f0279411847d 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -182,6 +182,8 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
182#define pmd_addr_end(addr,end) (end) 182#define pmd_addr_end(addr,end) (end)
183 183
184#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) 184#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
185#define pte_special(pte) (0)
186static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
185 187
186/* 188/*
187 * We don't have huge page support for short descriptors, for the moment 189 * We don't have huge page support for short descriptors, for the moment
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 06e0bc0f8b00..a31ecdad4b59 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -213,10 +213,19 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
213#define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val))) 213#define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val)))
214 214
215#define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF)) 215#define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF))
216#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
217static inline pte_t pte_mkspecial(pte_t pte)
218{
219 pte_val(pte) |= L_PTE_SPECIAL;
220 return pte;
221}
222#define __HAVE_ARCH_PTE_SPECIAL
216 223
217#define __HAVE_ARCH_PMD_WRITE 224#define __HAVE_ARCH_PMD_WRITE
218#define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY)) 225#define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY))
219#define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY)) 226#define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY))
227#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
228#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
220 229
221#define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd)) 230#define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd))
222#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 231#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
@@ -224,6 +233,12 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
224#ifdef CONFIG_TRANSPARENT_HUGEPAGE 233#ifdef CONFIG_TRANSPARENT_HUGEPAGE
225#define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd)) 234#define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd))
226#define pmd_trans_splitting(pmd) (pmd_isset((pmd), L_PMD_SECT_SPLITTING)) 235#define pmd_trans_splitting(pmd) (pmd_isset((pmd), L_PMD_SECT_SPLITTING))
236
237#ifdef CONFIG_HAVE_RCU_TABLE_FREE
238#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
239void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
240 pmd_t *pmdp);
241#endif
227#endif 242#endif
228 243
229#define PMD_BIT_FUNC(fn,op) \ 244#define PMD_BIT_FUNC(fn,op) \
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 01baef07cd0c..90aa4583b308 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -226,7 +226,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
226#define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY)) 226#define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY))
227#define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG)) 227#define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG))
228#define pte_exec(pte) (pte_isclear((pte), L_PTE_XN)) 228#define pte_exec(pte) (pte_isclear((pte), L_PTE_XN))
229#define pte_special(pte) (0)
230 229
231#define pte_valid_user(pte) \ 230#define pte_valid_user(pte) \
232 (pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte)) 231 (pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
@@ -245,7 +244,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
245 unsigned long ext = 0; 244 unsigned long ext = 0;
246 245
247 if (addr < TASK_SIZE && pte_valid_user(pteval)) { 246 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
248 __sync_icache_dcache(pteval); 247 if (!pte_special(pteval))
248 __sync_icache_dcache(pteval);
249 ext |= PTE_EXT_NG; 249 ext |= PTE_EXT_NG;
250 } 250 }
251 251
@@ -264,8 +264,6 @@ PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG);
264PTE_BIT_FUNC(mkexec, &= ~L_PTE_XN); 264PTE_BIT_FUNC(mkexec, &= ~L_PTE_XN);
265PTE_BIT_FUNC(mknexec, |= L_PTE_XN); 265PTE_BIT_FUNC(mknexec, |= L_PTE_XN);
266 266
267static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
268
269static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 267static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
270{ 268{
271 const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER | 269 const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 2ec765c39ab4..18f5a554134f 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -49,12 +49,6 @@ extern void smp_init_cpus(void);
49extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int)); 49extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
50 50
51/* 51/*
52 * Boot a secondary CPU, and assign it the specified idle task.
53 * This also gives us the initial stack to use for this CPU.
54 */
55extern int boot_secondary(unsigned int cpu, struct task_struct *);
56
57/*
58 * Called from platform specific assembly code, this is the 52 * Called from platform specific assembly code, this is the
59 * secondary CPU entry point. 53 * secondary CPU entry point.
60 */ 54 */
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index 4651f6999b7d..e86c985b8c7a 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -63,8 +63,8 @@ static inline void syscall_get_arguments(struct task_struct *task,
63 if (i + n > SYSCALL_MAX_ARGS) { 63 if (i + n > SYSCALL_MAX_ARGS) {
64 unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i; 64 unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
65 unsigned int n_bad = n + i - SYSCALL_MAX_ARGS; 65 unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
66 pr_warning("%s called with max args %d, handling only %d\n", 66 pr_warn("%s called with max args %d, handling only %d\n",
67 __func__, i + n, SYSCALL_MAX_ARGS); 67 __func__, i + n, SYSCALL_MAX_ARGS);
68 memset(args_bad, 0, n_bad * sizeof(args[0])); 68 memset(args_bad, 0, n_bad * sizeof(args[0]));
69 n = SYSCALL_MAX_ARGS - i; 69 n = SYSCALL_MAX_ARGS - i;
70 } 70 }
@@ -88,8 +88,8 @@ static inline void syscall_set_arguments(struct task_struct *task,
88 return; 88 return;
89 89
90 if (i + n > SYSCALL_MAX_ARGS) { 90 if (i + n > SYSCALL_MAX_ARGS) {
91 pr_warning("%s called with max args %d, handling only %d\n", 91 pr_warn("%s called with max args %d, handling only %d\n",
92 __func__, i + n, SYSCALL_MAX_ARGS); 92 __func__, i + n, SYSCALL_MAX_ARGS);
93 n = SYSCALL_MAX_ARGS - i; 93 n = SYSCALL_MAX_ARGS - i;
94 } 94 }
95 95
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index f1a0dace3efe..3cadb726ec88 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -35,12 +35,39 @@
35 35
36#define MMU_GATHER_BUNDLE 8 36#define MMU_GATHER_BUNDLE 8
37 37
38#ifdef CONFIG_HAVE_RCU_TABLE_FREE
39static inline void __tlb_remove_table(void *_table)
40{
41 free_page_and_swap_cache((struct page *)_table);
42}
43
44struct mmu_table_batch {
45 struct rcu_head rcu;
46 unsigned int nr;
47 void *tables[0];
48};
49
50#define MAX_TABLE_BATCH \
51 ((PAGE_SIZE - sizeof(struct mmu_table_batch)) / sizeof(void *))
52
53extern void tlb_table_flush(struct mmu_gather *tlb);
54extern void tlb_remove_table(struct mmu_gather *tlb, void *table);
55
56#define tlb_remove_entry(tlb, entry) tlb_remove_table(tlb, entry)
57#else
58#define tlb_remove_entry(tlb, entry) tlb_remove_page(tlb, entry)
59#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
60
38/* 61/*
39 * TLB handling. This allows us to remove pages from the page 62 * TLB handling. This allows us to remove pages from the page
40 * tables, and efficiently handle the TLB issues. 63 * tables, and efficiently handle the TLB issues.
41 */ 64 */
42struct mmu_gather { 65struct mmu_gather {
43 struct mm_struct *mm; 66 struct mm_struct *mm;
67#ifdef CONFIG_HAVE_RCU_TABLE_FREE
68 struct mmu_table_batch *batch;
69 unsigned int need_flush;
70#endif
44 unsigned int fullmm; 71 unsigned int fullmm;
45 struct vm_area_struct *vma; 72 struct vm_area_struct *vma;
46 unsigned long start, end; 73 unsigned long start, end;
@@ -101,6 +128,9 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb)
101static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb) 128static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb)
102{ 129{
103 tlb_flush(tlb); 130 tlb_flush(tlb);
131#ifdef CONFIG_HAVE_RCU_TABLE_FREE
132 tlb_table_flush(tlb);
133#endif
104} 134}
105 135
106static inline void tlb_flush_mmu_free(struct mmu_gather *tlb) 136static inline void tlb_flush_mmu_free(struct mmu_gather *tlb)
@@ -129,6 +159,10 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start
129 tlb->pages = tlb->local; 159 tlb->pages = tlb->local;
130 tlb->nr = 0; 160 tlb->nr = 0;
131 __tlb_alloc_page(tlb); 161 __tlb_alloc_page(tlb);
162
163#ifdef CONFIG_HAVE_RCU_TABLE_FREE
164 tlb->batch = NULL;
165#endif
132} 166}
133 167
134static inline void 168static inline void
@@ -205,7 +239,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
205 tlb_add_flush(tlb, addr + SZ_1M); 239 tlb_add_flush(tlb, addr + SZ_1M);
206#endif 240#endif
207 241
208 tlb_remove_page(tlb, pte); 242 tlb_remove_entry(tlb, pte);
209} 243}
210 244
211static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, 245static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
@@ -213,7 +247,7 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
213{ 247{
214#ifdef CONFIG_ARM_LPAE 248#ifdef CONFIG_ARM_LPAE
215 tlb_add_flush(tlb, addr); 249 tlb_add_flush(tlb, addr);
216 tlb_remove_page(tlb, virt_to_page(pmdp)); 250 tlb_remove_entry(tlb, virt_to_page(pmdp));
217#endif 251#endif
218} 252}
219 253
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 36172adda9d0..5f833f7adba1 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -81,6 +81,7 @@ static inline void set_tls(unsigned long val)
81 asm("mcr p15, 0, %0, c13, c0, 3" 81 asm("mcr p15, 0, %0, c13, c0, 3"
82 : : "r" (val)); 82 : : "r" (val));
83 } else { 83 } else {
84#ifdef CONFIG_KUSER_HELPERS
84 /* 85 /*
85 * User space must never try to access this 86 * User space must never try to access this
86 * directly. Expect your app to break 87 * directly. Expect your app to break
@@ -89,6 +90,7 @@ static inline void set_tls(unsigned long val)
89 * entry-armv.S for details) 90 * entry-armv.S for details)
90 */ 91 */
91 *((unsigned int *)0xffff0ff0) = val; 92 *((unsigned int *)0xffff0ff0) = val;
93#endif
92 } 94 }
93 95
94 } 96 }
diff --git a/arch/arm/include/debug/bcm63xx.S b/arch/arm/include/debug/bcm63xx.S
new file mode 100644
index 000000000000..e7164d570f44
--- /dev/null
+++ b/arch/arm/include/debug/bcm63xx.S
@@ -0,0 +1,33 @@
1/*
2 * Broadcom BCM63xx low-level UART debug
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/serial_bcm63xx.h>
12
13 .macro addruart, rp, rv, tmp
14 ldr \rp, =CONFIG_DEBUG_UART_PHYS
15 ldr \rv, =CONFIG_DEBUG_UART_VIRT
16 .endm
17
18 .macro senduart, rd, rx
19 /* word access do not work */
20 strb \rd, [\rx, #UART_FIFO_REG]
21 .endm
22
23 .macro waituart, rd, rx
241001: ldr \rd, [\rx, #UART_IR_REG]
25 tst \rd, #(1 << UART_IR_TXEMPTY)
26 beq 1001b
27 .endm
28
29 .macro busyuart, rd, rx
301002: ldr \rd, [\rx, #UART_IR_REG]
31 tst \rd, #(1 << UART_IR_TXTRESH)
32 beq 1002b
33 .endm
diff --git a/arch/arm/include/debug/meson.S b/arch/arm/include/debug/meson.S
new file mode 100644
index 000000000000..1bae99bf6f11
--- /dev/null
+++ b/arch/arm/include/debug/meson.S
@@ -0,0 +1,35 @@
1/*
2 * Copyright (C) 2014 Carlo Caione
3 * Carlo Caione <carlo@caione.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define MESON_AO_UART_WFIFO 0x0
11#define MESON_AO_UART_STATUS 0xc
12
13#define MESON_AO_UART_TX_FIFO_EMPTY (1 << 22)
14#define MESON_AO_UART_TX_FIFO_FULL (1 << 21)
15
16 .macro addruart, rp, rv, tmp
17 ldr \rp, =(CONFIG_DEBUG_UART_PHYS) @ physical
18 ldr \rv, =(CONFIG_DEBUG_UART_VIRT) @ virtual
19 .endm
20
21 .macro senduart,rd,rx
22 str \rd, [\rx, #MESON_AO_UART_WFIFO]
23 .endm
24
25 .macro busyuart,rd,rx
261002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
27 tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY
28 beq 1002b
29 .endm
30
31 .macro waituart,rd,rx
321001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
33 tst \rd, #MESON_AO_UART_TX_FIFO_FULL
34 bne 1001b
35 .endm
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index e6ebdd3471e5..09ee408c1a67 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -25,6 +25,7 @@
25 25
26#define __KVM_HAVE_GUEST_DEBUG 26#define __KVM_HAVE_GUEST_DEBUG
27#define __KVM_HAVE_IRQ_LINE 27#define __KVM_HAVE_IRQ_LINE
28#define __KVM_HAVE_READONLY_MEM
28 29
29#define KVM_REG_SIZE(id) \ 30#define KVM_REG_SIZE(id) \
30 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 31 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
@@ -173,6 +174,7 @@ struct kvm_arch_memory_slot {
173#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 174#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
174#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 175#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
175#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 176#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
177#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
176 178
177/* KVM_IRQ_LINE irq field index values */ 179/* KVM_IRQ_LINE irq field index values */
178#define KVM_ARM_IRQ_TYPE_SHIFT 24 180#define KVM_ARM_IRQ_TYPE_SHIFT 24
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
index 7807ef58a2ab..528f8af2addb 100644
--- a/arch/arm/kernel/atags_parse.c
+++ b/arch/arm/kernel/atags_parse.c
@@ -130,7 +130,7 @@ static int __init parse_tag_cmdline(const struct tag *tag)
130 strlcat(default_command_line, tag->u.cmdline.cmdline, 130 strlcat(default_command_line, tag->u.cmdline.cmdline,
131 COMMAND_LINE_SIZE); 131 COMMAND_LINE_SIZE);
132#elif defined(CONFIG_CMDLINE_FORCE) 132#elif defined(CONFIG_CMDLINE_FORCE)
133 pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); 133 pr_warn("Ignoring tag cmdline (using the default kernel command line)\n");
134#else 134#else
135 strlcpy(default_command_line, tag->u.cmdline.cmdline, 135 strlcpy(default_command_line, tag->u.cmdline.cmdline,
136 COMMAND_LINE_SIZE); 136 COMMAND_LINE_SIZE);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 36276cdccfbc..2f5555d307b3 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -146,7 +146,7 @@ ENDPROC(__und_invalid)
146#define SPFIX(code...) 146#define SPFIX(code...)
147#endif 147#endif
148 148
149 .macro svc_entry, stack_hole=0 149 .macro svc_entry, stack_hole=0, trace=1
150 UNWIND(.fnstart ) 150 UNWIND(.fnstart )
151 UNWIND(.save {r0 - pc} ) 151 UNWIND(.save {r0 - pc} )
152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
@@ -182,9 +182,11 @@ ENDPROC(__und_invalid)
182 @ 182 @
183 stmia r7, {r2 - r6} 183 stmia r7, {r2 - r6}
184 184
185 .if \trace
185#ifdef CONFIG_TRACE_IRQFLAGS 186#ifdef CONFIG_TRACE_IRQFLAGS
186 bl trace_hardirqs_off 187 bl trace_hardirqs_off
187#endif 188#endif
189 .endif
188 .endm 190 .endm
189 191
190 .align 5 192 .align 5
@@ -295,6 +297,15 @@ __pabt_svc:
295ENDPROC(__pabt_svc) 297ENDPROC(__pabt_svc)
296 298
297 .align 5 299 .align 5
300__fiq_svc:
301 svc_entry trace=0
302 mov r0, sp @ struct pt_regs *regs
303 bl handle_fiq_as_nmi
304 svc_exit_via_fiq
305 UNWIND(.fnend )
306ENDPROC(__fiq_svc)
307
308 .align 5
298.LCcralign: 309.LCcralign:
299 .word cr_alignment 310 .word cr_alignment
300#ifdef MULTI_DABORT 311#ifdef MULTI_DABORT
@@ -305,6 +316,46 @@ ENDPROC(__pabt_svc)
305 .word fp_enter 316 .word fp_enter
306 317
307/* 318/*
319 * Abort mode handlers
320 */
321
322@
323@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
324@ and reuses the same macros. However in abort mode we must also
325@ save/restore lr_abt and spsr_abt to make nested aborts safe.
326@
327 .align 5
328__fiq_abt:
329 svc_entry trace=0
330
331 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
332 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
333 THUMB( msr cpsr_c, r0 )
334 mov r1, lr @ Save lr_abt
335 mrs r2, spsr @ Save spsr_abt, abort is now safe
336 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
337 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
338 THUMB( msr cpsr_c, r0 )
339 stmfd sp!, {r1 - r2}
340
341 add r0, sp, #8 @ struct pt_regs *regs
342 bl handle_fiq_as_nmi
343
344 ldmfd sp!, {r1 - r2}
345 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
346 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
347 THUMB( msr cpsr_c, r0 )
348 mov lr, r1 @ Restore lr_abt, abort is unsafe
349 msr spsr_cxsf, r2 @ Restore spsr_abt
350 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
351 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
352 THUMB( msr cpsr_c, r0 )
353
354 svc_exit_via_fiq
355 UNWIND(.fnend )
356ENDPROC(__fiq_abt)
357
358/*
308 * User mode handlers 359 * User mode handlers
309 * 360 *
310 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 361 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
@@ -314,13 +365,16 @@ ENDPROC(__pabt_svc)
314#error "sizeof(struct pt_regs) must be a multiple of 8" 365#error "sizeof(struct pt_regs) must be a multiple of 8"
315#endif 366#endif
316 367
317 .macro usr_entry 368 .macro usr_entry, trace=1
318 UNWIND(.fnstart ) 369 UNWIND(.fnstart )
319 UNWIND(.cantunwind ) @ don't unwind the user space 370 UNWIND(.cantunwind ) @ don't unwind the user space
320 sub sp, sp, #S_FRAME_SIZE 371 sub sp, sp, #S_FRAME_SIZE
321 ARM( stmib sp, {r1 - r12} ) 372 ARM( stmib sp, {r1 - r12} )
322 THUMB( stmia sp, {r0 - r12} ) 373 THUMB( stmia sp, {r0 - r12} )
323 374
375 ATRAP( mrc p15, 0, r7, c1, c0, 0)
376 ATRAP( ldr r8, .LCcralign)
377
324 ldmia r0, {r3 - r5} 378 ldmia r0, {r3 - r5}
325 add r0, sp, #S_PC @ here for interlock avoidance 379 add r0, sp, #S_PC @ here for interlock avoidance
326 mov r6, #-1 @ "" "" "" "" 380 mov r6, #-1 @ "" "" "" ""
@@ -328,6 +382,8 @@ ENDPROC(__pabt_svc)
328 str r3, [sp] @ save the "real" r0 copied 382 str r3, [sp] @ save the "real" r0 copied
329 @ from the exception stack 383 @ from the exception stack
330 384
385 ATRAP( ldr r8, [r8, #0])
386
331 @ 387 @
332 @ We are now ready to fill in the remaining blanks on the stack: 388 @ We are now ready to fill in the remaining blanks on the stack:
333 @ 389 @
@@ -341,20 +397,21 @@ ENDPROC(__pabt_svc)
341 ARM( stmdb r0, {sp, lr}^ ) 397 ARM( stmdb r0, {sp, lr}^ )
342 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 398 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
343 399
344 @
345 @ Enable the alignment trap while in kernel mode 400 @ Enable the alignment trap while in kernel mode
346 @ 401 ATRAP( teq r8, r7)
347 alignment_trap r0, .LCcralign 402 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
348 403
349 @ 404 @
350 @ Clear FP to mark the first stack frame 405 @ Clear FP to mark the first stack frame
351 @ 406 @
352 zero_fp 407 zero_fp
353 408
409 .if \trace
354#ifdef CONFIG_IRQSOFF_TRACER 410#ifdef CONFIG_IRQSOFF_TRACER
355 bl trace_hardirqs_off 411 bl trace_hardirqs_off
356#endif 412#endif
357 ct_user_exit save = 0 413 ct_user_exit save = 0
414 .endif
358 .endm 415 .endm
359 416
360 .macro kuser_cmpxchg_check 417 .macro kuser_cmpxchg_check
@@ -683,6 +740,17 @@ ENTRY(ret_from_exception)
683ENDPROC(__pabt_usr) 740ENDPROC(__pabt_usr)
684ENDPROC(ret_from_exception) 741ENDPROC(ret_from_exception)
685 742
743 .align 5
744__fiq_usr:
745 usr_entry trace=0
746 kuser_cmpxchg_check
747 mov r0, sp @ struct pt_regs *regs
748 bl handle_fiq_as_nmi
749 get_thread_info tsk
750 restore_user_regs fast = 0, offset = 0
751 UNWIND(.fnend )
752ENDPROC(__fiq_usr)
753
686/* 754/*
687 * Register switch for ARMv3 and ARMv4 processors 755 * Register switch for ARMv3 and ARMv4 processors
688 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 756 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
@@ -1118,17 +1186,29 @@ vector_addrexcptn:
1118 b vector_addrexcptn 1186 b vector_addrexcptn
1119 1187
1120/*============================================================================= 1188/*=============================================================================
1121 * Undefined FIQs 1189 * FIQ "NMI" handler
1122 *----------------------------------------------------------------------------- 1190 *-----------------------------------------------------------------------------
1123 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1191 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1124 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1192 * systems.
1125 * Basically to switch modes, we *HAVE* to clobber one register... brain
1126 * damage alert! I don't think that we can execute any code in here in any
1127 * other mode than FIQ... Ok you can switch to another mode, but you can't
1128 * get out of that mode without clobbering one register.
1129 */ 1193 */
1130vector_fiq: 1194 vector_stub fiq, FIQ_MODE, 4
1131 subs pc, lr, #4 1195
1196 .long __fiq_usr @ 0 (USR_26 / USR_32)
1197 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1198 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1199 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1200 .long __fiq_svc @ 4
1201 .long __fiq_svc @ 5
1202 .long __fiq_svc @ 6
1203 .long __fiq_abt @ 7
1204 .long __fiq_svc @ 8
1205 .long __fiq_svc @ 9
1206 .long __fiq_svc @ a
1207 .long __fiq_svc @ b
1208 .long __fiq_svc @ c
1209 .long __fiq_svc @ d
1210 .long __fiq_svc @ e
1211 .long __fiq_svc @ f
1132 1212
1133 .globl vector_fiq_offset 1213 .globl vector_fiq_offset
1134 .equ vector_fiq_offset, vector_fiq 1214 .equ vector_fiq_offset, vector_fiq
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index e52fe5a2d843..6bb09d4abdea 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -366,7 +366,7 @@ ENTRY(vector_swi)
366 str r0, [sp, #S_OLD_R0] @ Save OLD_R0 366 str r0, [sp, #S_OLD_R0] @ Save OLD_R0
367#endif 367#endif
368 zero_fp 368 zero_fp
369 alignment_trap ip, __cr_alignment 369 alignment_trap r10, ip, __cr_alignment
370 enable_irq 370 enable_irq
371 ct_user_exit 371 ct_user_exit
372 get_thread_info tsk 372 get_thread_info tsk
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 2fdf8679b46e..4176df721bf0 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -37,11 +37,19 @@
37#endif 37#endif
38 .endm 38 .endm
39 39
40 .macro alignment_trap, rtemp, label
41#ifdef CONFIG_ALIGNMENT_TRAP 40#ifdef CONFIG_ALIGNMENT_TRAP
42 ldr \rtemp, \label 41#define ATRAP(x...) x
43 ldr \rtemp, [\rtemp] 42#else
44 mcr p15, 0, \rtemp, c1, c0 43#define ATRAP(x...)
44#endif
45
46 .macro alignment_trap, rtmp1, rtmp2, label
47#ifdef CONFIG_ALIGNMENT_TRAP
48 mrc p15, 0, \rtmp2, c1, c0, 0
49 ldr \rtmp1, \label
50 ldr \rtmp1, [\rtmp1]
51 teq \rtmp1, \rtmp2
52 mcrne p15, 0, \rtmp1, c1, c0, 0
45#endif 53#endif
46 .endm 54 .endm
47 55
@@ -216,6 +224,34 @@
216 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 224 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
217 .endm 225 .endm
218 226
227 @
228 @ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
229 @
230 @ This macro acts in a similar manner to svc_exit but switches to FIQ
231 @ mode to restore the final part of the register state.
232 @
233 @ We cannot use the normal svc_exit procedure because that would
234 @ clobber spsr_svc (FIQ could be delivered during the first few
235 @ instructions of vector_swi meaning its contents have not been
236 @ saved anywhere).
237 @
238 @ Note that, unlike svc_exit, this macro also does not allow a caller
239 @ supplied rpsr. This is because the FIQ exceptions are not re-entrant
240 @ and the handlers cannot call into the scheduler (meaning the value
241 @ on the stack remains correct).
242 @
243 .macro svc_exit_via_fiq
244 mov r0, sp
245 ldmib r0, {r1 - r14} @ abort is deadly from here onward (it will
246 @ clobber state restored below)
247 msr cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
248 add r8, r0, #S_PC
249 ldr r9, [r0, #S_PSR]
250 msr spsr_cxsf, r9
251 ldr r0, [r0, #S_R0]
252 ldmia r8, {pc}^
253 .endm
254
219 .macro restore_user_regs, fast = 0, offset = 0 255 .macro restore_user_regs, fast = 0, offset = 0
220 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr 256 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
221 ldr lr, [sp, #\offset + S_PC]! @ get pc 257 ldr lr, [sp, #\offset + S_PC]! @ get pc
@@ -267,6 +303,25 @@
267 rfeia sp! 303 rfeia sp!
268 .endm 304 .endm
269 305
306 @
307 @ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
308 @
309 @ For full details see non-Thumb implementation above.
310 @
311 .macro svc_exit_via_fiq
312 add r0, sp, #S_R2
313 ldr lr, [sp, #S_LR]
314 ldr sp, [sp, #S_SP] @ abort is deadly from here onward (it will
315 @ clobber state restored below)
316 ldmia r0, {r2 - r12}
317 mov r1, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
318 msr cpsr_c, r1
319 sub r0, #S_R2
320 add r8, r0, #S_PC
321 ldmia r0, {r0 - r1}
322 rfeia r8
323 .endm
324
270#ifdef CONFIG_CPU_V7M 325#ifdef CONFIG_CPU_V7M
271 /* 326 /*
272 * Note we don't need to do clrex here as clearing the local monitor is 327 * Note we don't need to do clrex here as clearing the local monitor is
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 918875d96d5d..b37752a96652 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -52,7 +52,8 @@
52 (unsigned)&vector_fiq_offset; \ 52 (unsigned)&vector_fiq_offset; \
53 }) 53 })
54 54
55static unsigned long no_fiq_insn; 55static unsigned long dfl_fiq_insn;
56static struct pt_regs dfl_fiq_regs;
56 57
57/* Default reacquire function 58/* Default reacquire function
58 * - we always relinquish FIQ control 59 * - we always relinquish FIQ control
@@ -60,8 +61,15 @@ static unsigned long no_fiq_insn;
60 */ 61 */
61static int fiq_def_op(void *ref, int relinquish) 62static int fiq_def_op(void *ref, int relinquish)
62{ 63{
63 if (!relinquish) 64 if (!relinquish) {
64 set_fiq_handler(&no_fiq_insn, sizeof(no_fiq_insn)); 65 /* Restore default handler and registers */
66 local_fiq_disable();
67 set_fiq_regs(&dfl_fiq_regs);
68 set_fiq_handler(&dfl_fiq_insn, sizeof(dfl_fiq_insn));
69 local_fiq_enable();
70
71 /* FIXME: notify irq controller to standard enable FIQs */
72 }
65 73
66 return 0; 74 return 0;
67} 75}
@@ -150,6 +158,7 @@ EXPORT_SYMBOL(disable_fiq);
150void __init init_FIQ(int start) 158void __init init_FIQ(int start)
151{ 159{
152 unsigned offset = FIQ_OFFSET; 160 unsigned offset = FIQ_OFFSET;
153 no_fiq_insn = *(unsigned long *)(0xffff0000 + offset); 161 dfl_fiq_insn = *(unsigned long *)(0xffff0000 + offset);
162 get_fiq_regs(&dfl_fiq_regs);
154 fiq_start = start; 163 fiq_start = start;
155} 164}
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
index bb8b79648643..c4cc50e58c13 100644
--- a/arch/arm/kernel/hibernate.c
+++ b/arch/arm/kernel/hibernate.c
@@ -21,8 +21,7 @@
21#include <asm/idmap.h> 21#include <asm/idmap.h>
22#include <asm/suspend.h> 22#include <asm/suspend.h>
23#include <asm/memory.h> 23#include <asm/memory.h>
24 24#include <asm/sections.h>
25extern const void __nosave_begin, __nosave_end;
26 25
27int pfn_is_nosave(unsigned long pfn) 26int pfn_is_nosave(unsigned long pfn)
28{ 27{
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 4d963fb66e3f..b5b452f90f76 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -113,8 +113,8 @@ static u32 read_wb_reg(int n)
113 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); 113 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
114 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); 114 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
115 default: 115 default:
116 pr_warning("attempt to read from unknown breakpoint " 116 pr_warn("attempt to read from unknown breakpoint register %d\n",
117 "register %d\n", n); 117 n);
118 } 118 }
119 119
120 return val; 120 return val;
@@ -128,8 +128,8 @@ static void write_wb_reg(int n, u32 val)
128 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); 128 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
129 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); 129 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
130 default: 130 default:
131 pr_warning("attempt to write to unknown breakpoint " 131 pr_warn("attempt to write to unknown breakpoint register %d\n",
132 "register %d\n", n); 132 n);
133 } 133 }
134 isb(); 134 isb();
135} 135}
@@ -292,7 +292,7 @@ int hw_breakpoint_slots(int type)
292 case TYPE_DATA: 292 case TYPE_DATA:
293 return get_num_wrps(); 293 return get_num_wrps();
294 default: 294 default:
295 pr_warning("unknown slot type: %d\n", type); 295 pr_warn("unknown slot type: %d\n", type);
296 return 0; 296 return 0;
297 } 297 }
298} 298}
@@ -365,7 +365,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
365 } 365 }
366 366
367 if (i == max_slots) { 367 if (i == max_slots) {
368 pr_warning("Can't find any breakpoint slot\n"); 368 pr_warn("Can't find any breakpoint slot\n");
369 return -EBUSY; 369 return -EBUSY;
370 } 370 }
371 371
@@ -417,7 +417,7 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
417 } 417 }
418 418
419 if (i == max_slots) { 419 if (i == max_slots) {
420 pr_warning("Can't find any breakpoint slot\n"); 420 pr_warn("Can't find any breakpoint slot\n");
421 return; 421 return;
422 } 422 }
423 423
@@ -894,8 +894,8 @@ static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
894{ 894{
895 int cpu = smp_processor_id(); 895 int cpu = smp_processor_id();
896 896
897 pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n", 897 pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
898 instr, cpu); 898 instr, cpu);
899 899
900 /* Set the error flag for this CPU and skip the faulting instruction. */ 900 /* Set the error flag for this CPU and skip the faulting instruction. */
901 cpumask_set_cpu(cpu, &debug_err_mask); 901 cpumask_set_cpu(cpu, &debug_err_mask);
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 5c4d38e32a51..7c81ec428b9b 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -65,24 +65,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
65 */ 65 */
66void handle_IRQ(unsigned int irq, struct pt_regs *regs) 66void handle_IRQ(unsigned int irq, struct pt_regs *regs)
67{ 67{
68 struct pt_regs *old_regs = set_irq_regs(regs); 68 __handle_domain_irq(NULL, irq, false, regs);
69
70 irq_enter();
71
72 /*
73 * Some hardware gives randomly wrong interrupts. Rather
74 * than crashing, do something sensible.
75 */
76 if (unlikely(irq >= nr_irqs)) {
77 if (printk_ratelimit())
78 printk(KERN_WARNING "Bad IRQ%u\n", irq);
79 ack_bad_irq(irq);
80 } else {
81 generic_handle_irq(irq);
82 }
83
84 irq_exit();
85 set_irq_regs(old_regs);
86} 69}
87 70
88/* 71/*
@@ -205,8 +188,8 @@ void migrate_irqs(void)
205 raw_spin_unlock(&desc->lock); 188 raw_spin_unlock(&desc->lock);
206 189
207 if (affinity_broken && printk_ratelimit()) 190 if (affinity_broken && printk_ratelimit())
208 pr_warning("IRQ%u no longer affine to CPU%u\n", i, 191 pr_warn("IRQ%u no longer affine to CPU%u\n",
209 smp_processor_id()); 192 i, smp_processor_id());
210 } 193 }
211 194
212 local_irq_restore(flags); 195 local_irq_restore(flags);
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
index 08d731294bcd..b206d7790c77 100644
--- a/arch/arm/kernel/kprobes-test.c
+++ b/arch/arm/kernel/kprobes-test.c
@@ -110,10 +110,13 @@
110 * 110 *
111 * @ TESTCASE_START 111 * @ TESTCASE_START
112 * bl __kprobes_test_case_start 112 * bl __kprobes_test_case_start
113 * @ start of inline data... 113 * .pushsection .rodata
114 * "10:
114 * .ascii "mov r0, r7" @ text title for test case 115 * .ascii "mov r0, r7" @ text title for test case
115 * .byte 0 116 * .byte 0
116 * .align 2, 0 117 * .popsection
118 * @ start of inline data...
119 * .word 10b @ pointer to title in .rodata section
117 * 120 *
118 * @ TEST_ARG_REG 121 * @ TEST_ARG_REG
119 * .byte ARG_TYPE_REG 122 * .byte ARG_TYPE_REG
@@ -971,7 +974,7 @@ void __naked __kprobes_test_case_start(void)
971 __asm__ __volatile__ ( 974 __asm__ __volatile__ (
972 "stmdb sp!, {r4-r11} \n\t" 975 "stmdb sp!, {r4-r11} \n\t"
973 "sub sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t" 976 "sub sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
974 "bic r0, lr, #1 @ r0 = inline title string \n\t" 977 "bic r0, lr, #1 @ r0 = inline data \n\t"
975 "mov r1, sp \n\t" 978 "mov r1, sp \n\t"
976 "bl kprobes_test_case_start \n\t" 979 "bl kprobes_test_case_start \n\t"
977 "bx r0 \n\t" 980 "bx r0 \n\t"
@@ -1349,15 +1352,14 @@ static unsigned long next_instruction(unsigned long pc)
1349 return pc + 4; 1352 return pc + 4;
1350} 1353}
1351 1354
1352static uintptr_t __used kprobes_test_case_start(const char *title, void *stack) 1355static uintptr_t __used kprobes_test_case_start(const char **title, void *stack)
1353{ 1356{
1354 struct test_arg *args; 1357 struct test_arg *args;
1355 struct test_arg_end *end_arg; 1358 struct test_arg_end *end_arg;
1356 unsigned long test_code; 1359 unsigned long test_code;
1357 1360
1358 args = (struct test_arg *)PTR_ALIGN(title + strlen(title) + 1, 4); 1361 current_title = *title++;
1359 1362 args = (struct test_arg *)title;
1360 current_title = title;
1361 current_args = args; 1363 current_args = args;
1362 current_stack = stack; 1364 current_stack = stack;
1363 1365
diff --git a/arch/arm/kernel/kprobes-test.h b/arch/arm/kernel/kprobes-test.h
index eecc90a0fd91..4430990e90e7 100644
--- a/arch/arm/kernel/kprobes-test.h
+++ b/arch/arm/kernel/kprobes-test.h
@@ -111,11 +111,14 @@ struct test_arg_end {
111#define TESTCASE_START(title) \ 111#define TESTCASE_START(title) \
112 __asm__ __volatile__ ( \ 112 __asm__ __volatile__ ( \
113 "bl __kprobes_test_case_start \n\t" \ 113 "bl __kprobes_test_case_start \n\t" \
114 ".pushsection .rodata \n\t" \
115 "10: \n\t" \
114 /* don't use .asciz here as 'title' may be */ \ 116 /* don't use .asciz here as 'title' may be */ \
115 /* multiple strings to be concatenated. */ \ 117 /* multiple strings to be concatenated. */ \
116 ".ascii "#title" \n\t" \ 118 ".ascii "#title" \n\t" \
117 ".byte 0 \n\t" \ 119 ".byte 0 \n\t" \
118 ".align 2, 0 \n\t" 120 ".popsection \n\t" \
121 ".word 10b \n\t"
119 122
120#define TEST_ARG_REG(reg, val) \ 123#define TEST_ARG_REG(reg, val) \
121 ".byte "__stringify(ARG_TYPE_REG)" \n\t" \ 124 ".byte "__stringify(ARG_TYPE_REG)" \n\t" \
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 4bf4cce759fe..eb2c4d55666b 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -146,8 +146,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
146 * continue. Otherwise, continue without this interrupt. 146 * continue. Otherwise, continue without this interrupt.
147 */ 147 */
148 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { 148 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
149 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", 149 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
150 irq, i); 150 irq, i);
151 continue; 151 continue;
152 } 152 }
153 153
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index a35f6ebbd2c2..fe972a2f3df3 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -114,18 +114,13 @@ void soft_restart(unsigned long addr)
114 BUG(); 114 BUG();
115} 115}
116 116
117static void null_restart(enum reboot_mode reboot_mode, const char *cmd)
118{
119}
120
121/* 117/*
122 * Function pointers to optional machine specific functions 118 * Function pointers to optional machine specific functions
123 */ 119 */
124void (*pm_power_off)(void); 120void (*pm_power_off)(void);
125EXPORT_SYMBOL(pm_power_off); 121EXPORT_SYMBOL(pm_power_off);
126 122
127void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd) = null_restart; 123void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
128EXPORT_SYMBOL_GPL(arm_pm_restart);
129 124
130/* 125/*
131 * This is our default idle handler. 126 * This is our default idle handler.
@@ -230,7 +225,10 @@ void machine_restart(char *cmd)
230 local_irq_disable(); 225 local_irq_disable();
231 smp_send_stop(); 226 smp_send_stop();
232 227
233 arm_pm_restart(reboot_mode, cmd); 228 if (arm_pm_restart)
229 arm_pm_restart(reboot_mode, cmd);
230 else
231 do_kernel_restart(cmd);
234 232
235 /* Give a grace period for failure to restart of 1s */ 233 /* Give a grace period for failure to restart of 1s */
236 mdelay(1000); 234 mdelay(1000);
@@ -306,7 +304,6 @@ void __show_regs(struct pt_regs *regs)
306 304
307void show_regs(struct pt_regs * regs) 305void show_regs(struct pt_regs * regs)
308{ 306{
309 printk("\n");
310 __show_regs(regs); 307 __show_regs(regs);
311 dump_stack(); 308 dump_stack();
312} 309}
@@ -474,19 +471,57 @@ int in_gate_area_no_mm(unsigned long addr)
474 471
475const char *arch_vma_name(struct vm_area_struct *vma) 472const char *arch_vma_name(struct vm_area_struct *vma)
476{ 473{
477 return is_gate_vma(vma) ? "[vectors]" : 474 return is_gate_vma(vma) ? "[vectors]" : NULL;
478 (vma->vm_mm && vma->vm_start == vma->vm_mm->context.sigpage) ? 475}
479 "[sigpage]" : NULL; 476
477/* If possible, provide a placement hint at a random offset from the
478 * stack for the signal page.
479 */
480static unsigned long sigpage_addr(const struct mm_struct *mm,
481 unsigned int npages)
482{
483 unsigned long offset;
484 unsigned long first;
485 unsigned long last;
486 unsigned long addr;
487 unsigned int slots;
488
489 first = PAGE_ALIGN(mm->start_stack);
490
491 last = TASK_SIZE - (npages << PAGE_SHIFT);
492
493 /* No room after stack? */
494 if (first > last)
495 return 0;
496
497 /* Just enough room? */
498 if (first == last)
499 return first;
500
501 slots = ((last - first) >> PAGE_SHIFT) + 1;
502
503 offset = get_random_int() % slots;
504
505 addr = first + (offset << PAGE_SHIFT);
506
507 return addr;
480} 508}
481 509
482static struct page *signal_page; 510static struct page *signal_page;
483extern struct page *get_signal_page(void); 511extern struct page *get_signal_page(void);
484 512
513static const struct vm_special_mapping sigpage_mapping = {
514 .name = "[sigpage]",
515 .pages = &signal_page,
516};
517
485int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) 518int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
486{ 519{
487 struct mm_struct *mm = current->mm; 520 struct mm_struct *mm = current->mm;
521 struct vm_area_struct *vma;
488 unsigned long addr; 522 unsigned long addr;
489 int ret; 523 unsigned long hint;
524 int ret = 0;
490 525
491 if (!signal_page) 526 if (!signal_page)
492 signal_page = get_signal_page(); 527 signal_page = get_signal_page();
@@ -494,18 +529,23 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
494 return -ENOMEM; 529 return -ENOMEM;
495 530
496 down_write(&mm->mmap_sem); 531 down_write(&mm->mmap_sem);
497 addr = get_unmapped_area(NULL, 0, PAGE_SIZE, 0, 0); 532 hint = sigpage_addr(mm, 1);
533 addr = get_unmapped_area(NULL, hint, PAGE_SIZE, 0, 0);
498 if (IS_ERR_VALUE(addr)) { 534 if (IS_ERR_VALUE(addr)) {
499 ret = addr; 535 ret = addr;
500 goto up_fail; 536 goto up_fail;
501 } 537 }
502 538
503 ret = install_special_mapping(mm, addr, PAGE_SIZE, 539 vma = _install_special_mapping(mm, addr, PAGE_SIZE,
504 VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC, 540 VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
505 &signal_page); 541 &sigpage_mapping);
542
543 if (IS_ERR(vma)) {
544 ret = PTR_ERR(vma);
545 goto up_fail;
546 }
506 547
507 if (ret == 0) 548 mm->context.sigpage = addr;
508 mm->context.sigpage = addr;
509 549
510 up_fail: 550 up_fail:
511 up_write(&mm->mmap_sem); 551 up_write(&mm->mmap_sem);
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c
index fafedd86885d..98ea4b7eb406 100644
--- a/arch/arm/kernel/return_address.c
+++ b/arch/arm/kernel/return_address.c
@@ -59,15 +59,6 @@ void *return_address(unsigned int level)
59 59
60#else /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) */ 60#else /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) */
61 61
62#if defined(CONFIG_ARM_UNWIND)
63#warning "TODO: return_address should use unwind tables"
64#endif
65
66void *return_address(unsigned int level)
67{
68 return NULL;
69}
70
71#endif /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) / else */ 62#endif /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) / else */
72 63
73EXPORT_SYMBOL_GPL(return_address); 64EXPORT_SYMBOL_GPL(return_address);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 84db893dedc2..c03106378b49 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -133,6 +133,7 @@ struct stack {
133 u32 irq[3]; 133 u32 irq[3];
134 u32 abt[3]; 134 u32 abt[3];
135 u32 und[3]; 135 u32 und[3];
136 u32 fiq[3];
136} ____cacheline_aligned; 137} ____cacheline_aligned;
137 138
138#ifndef CONFIG_CPU_V7M 139#ifndef CONFIG_CPU_V7M
@@ -470,7 +471,10 @@ void notrace cpu_init(void)
470 "msr cpsr_c, %5\n\t" 471 "msr cpsr_c, %5\n\t"
471 "add r14, %0, %6\n\t" 472 "add r14, %0, %6\n\t"
472 "mov sp, r14\n\t" 473 "mov sp, r14\n\t"
473 "msr cpsr_c, %7" 474 "msr cpsr_c, %7\n\t"
475 "add r14, %0, %8\n\t"
476 "mov sp, r14\n\t"
477 "msr cpsr_c, %9"
474 : 478 :
475 : "r" (stk), 479 : "r" (stk),
476 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), 480 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
@@ -479,6 +483,8 @@ void notrace cpu_init(void)
479 "I" (offsetof(struct stack, abt[0])), 483 "I" (offsetof(struct stack, abt[0])),
480 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), 484 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
481 "I" (offsetof(struct stack, und[0])), 485 "I" (offsetof(struct stack, und[0])),
486 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
487 "I" (offsetof(struct stack, fiq[0])),
482 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) 488 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
483 : "r14"); 489 : "r14");
484#endif 490#endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 9388a3d479e1..13396d3d600e 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -95,6 +95,9 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
95{ 95{
96 int ret; 96 int ret;
97 97
98 if (!smp_ops.smp_boot_secondary)
99 return -ENOSYS;
100
98 /* 101 /*
99 * We need to tell the secondary core where to find 102 * We need to tell the secondary core where to find
100 * its stack and the page tables. 103 * its stack and the page tables.
@@ -113,7 +116,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
113 /* 116 /*
114 * Now bring the CPU into our world. 117 * Now bring the CPU into our world.
115 */ 118 */
116 ret = boot_secondary(cpu, idle); 119 ret = smp_ops.smp_boot_secondary(cpu, idle);
117 if (ret == 0) { 120 if (ret == 0) {
118 /* 121 /*
119 * CPU was successfully started, wait for it 122 * CPU was successfully started, wait for it
@@ -142,13 +145,6 @@ void __init smp_init_cpus(void)
142 smp_ops.smp_init_cpus(); 145 smp_ops.smp_init_cpus();
143} 146}
144 147
145int boot_secondary(unsigned int cpu, struct task_struct *idle)
146{
147 if (smp_ops.smp_boot_secondary)
148 return smp_ops.smp_boot_secondary(cpu, idle);
149 return -ENOSYS;
150}
151
152int platform_can_cpu_hotplug(void) 148int platform_can_cpu_hotplug(void)
153{ 149{
154#ifdef CONFIG_HOTPLUG_CPU 150#ifdef CONFIG_HOTPLUG_CPU
@@ -503,7 +499,7 @@ void arch_send_call_function_single_ipi(int cpu)
503#ifdef CONFIG_IRQ_WORK 499#ifdef CONFIG_IRQ_WORK
504void arch_irq_work_raise(void) 500void arch_irq_work_raise(void)
505{ 501{
506 if (is_smp()) 502 if (arch_irq_work_has_interrupt())
507 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); 503 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
508} 504}
509#endif 505#endif
@@ -650,7 +646,7 @@ void smp_send_stop(void)
650 udelay(1); 646 udelay(1);
651 647
652 if (num_online_cpus() > 1) 648 if (num_online_cpus() > 1)
653 pr_warning("SMP: failed to stop secondary CPUs\n"); 649 pr_warn("SMP: failed to stop secondary CPUs\n");
654} 650}
655 651
656/* 652/*
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index a964c9f40f87..0c8b10801d36 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -25,6 +25,7 @@
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/sched.h> 27#include <linux/sched.h>
28#include <linux/irq.h>
28 29
29#include <linux/atomic.h> 30#include <linux/atomic.h>
30#include <asm/cacheflush.h> 31#include <asm/cacheflush.h>
@@ -460,10 +461,29 @@ die_sig:
460 arm_notify_die("Oops - undefined instruction", regs, &info, 0, 6); 461 arm_notify_die("Oops - undefined instruction", regs, &info, 0, 6);
461} 462}
462 463
463asmlinkage void do_unexp_fiq (struct pt_regs *regs) 464/*
465 * Handle FIQ similarly to NMI on x86 systems.
466 *
467 * The runtime environment for NMIs is extremely restrictive
468 * (NMIs can pre-empt critical sections meaning almost all locking is
469 * forbidden) meaning this default FIQ handling must only be used in
470 * circumstances where non-maskability improves robustness, such as
471 * watchdog or debug logic.
472 *
473 * This handler is not appropriate for general purpose use in drivers
474 * platform code and can be overrideen using set_fiq_handler.
475 */
476asmlinkage void __exception_irq_entry handle_fiq_as_nmi(struct pt_regs *regs)
464{ 477{
465 printk("Hmm. Unexpected FIQ received, but trying to continue\n"); 478 struct pt_regs *old_regs = set_irq_regs(regs);
466 printk("You may have a hardware problem...\n"); 479
480 nmi_enter();
481
482 /* nop. FIQ handlers for special arch/arm features can be added here. */
483
484 nmi_exit();
485
486 set_irq_regs(old_regs);
467} 487}
468 488
469/* 489/*
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index a61a1dfbb0db..cbb85c5fabf9 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -157,7 +157,7 @@ static const struct unwind_idx *search_index(unsigned long addr,
157 if (likely(start->addr_offset <= addr_prel31)) 157 if (likely(start->addr_offset <= addr_prel31))
158 return start; 158 return start;
159 else { 159 else {
160 pr_warning("unwind: Unknown symbol address %08lx\n", addr); 160 pr_warn("unwind: Unknown symbol address %08lx\n", addr);
161 return NULL; 161 return NULL;
162 } 162 }
163} 163}
@@ -225,7 +225,7 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl)
225 unsigned long ret; 225 unsigned long ret;
226 226
227 if (ctrl->entries <= 0) { 227 if (ctrl->entries <= 0) {
228 pr_warning("unwind: Corrupt unwind table\n"); 228 pr_warn("unwind: Corrupt unwind table\n");
229 return 0; 229 return 0;
230 } 230 }
231 231
@@ -333,8 +333,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
333 insn = (insn << 8) | unwind_get_byte(ctrl); 333 insn = (insn << 8) | unwind_get_byte(ctrl);
334 mask = insn & 0x0fff; 334 mask = insn & 0x0fff;
335 if (mask == 0) { 335 if (mask == 0) {
336 pr_warning("unwind: 'Refuse to unwind' instruction %04lx\n", 336 pr_warn("unwind: 'Refuse to unwind' instruction %04lx\n",
337 insn); 337 insn);
338 return -URC_FAILURE; 338 return -URC_FAILURE;
339 } 339 }
340 340
@@ -357,8 +357,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
357 unsigned long mask = unwind_get_byte(ctrl); 357 unsigned long mask = unwind_get_byte(ctrl);
358 358
359 if (mask == 0 || mask & 0xf0) { 359 if (mask == 0 || mask & 0xf0) {
360 pr_warning("unwind: Spare encoding %04lx\n", 360 pr_warn("unwind: Spare encoding %04lx\n",
361 (insn << 8) | mask); 361 (insn << 8) | mask);
362 return -URC_FAILURE; 362 return -URC_FAILURE;
363 } 363 }
364 364
@@ -370,7 +370,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
370 370
371 ctrl->vrs[SP] += 0x204 + (uleb128 << 2); 371 ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
372 } else { 372 } else {
373 pr_warning("unwind: Unhandled instruction %02lx\n", insn); 373 pr_warn("unwind: Unhandled instruction %02lx\n", insn);
374 return -URC_FAILURE; 374 return -URC_FAILURE;
375 } 375 }
376 376
@@ -403,7 +403,7 @@ int unwind_frame(struct stackframe *frame)
403 403
404 idx = unwind_find_idx(frame->pc); 404 idx = unwind_find_idx(frame->pc);
405 if (!idx) { 405 if (!idx) {
406 pr_warning("unwind: Index not found %08lx\n", frame->pc); 406 pr_warn("unwind: Index not found %08lx\n", frame->pc);
407 return -URC_FAILURE; 407 return -URC_FAILURE;
408 } 408 }
409 409
@@ -422,8 +422,8 @@ int unwind_frame(struct stackframe *frame)
422 /* only personality routine 0 supported in the index */ 422 /* only personality routine 0 supported in the index */
423 ctrl.insn = &idx->insn; 423 ctrl.insn = &idx->insn;
424 else { 424 else {
425 pr_warning("unwind: Unsupported personality routine %08lx in the index at %p\n", 425 pr_warn("unwind: Unsupported personality routine %08lx in the index at %p\n",
426 idx->insn, idx); 426 idx->insn, idx);
427 return -URC_FAILURE; 427 return -URC_FAILURE;
428 } 428 }
429 429
@@ -435,8 +435,8 @@ int unwind_frame(struct stackframe *frame)
435 ctrl.byte = 1; 435 ctrl.byte = 1;
436 ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16); 436 ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16);
437 } else { 437 } else {
438 pr_warning("unwind: Unsupported personality routine %08lx at %p\n", 438 pr_warn("unwind: Unsupported personality routine %08lx at %p\n",
439 *ctrl.insn, ctrl.insn); 439 *ctrl.insn, ctrl.insn);
440 return -URC_FAILURE; 440 return -URC_FAILURE;
441 } 441 }
442 442
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 6f57cb94367f..8e95aa47457a 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -219,8 +219,8 @@ SECTIONS
219 __data_loc = ALIGN(4); /* location in binary */ 219 __data_loc = ALIGN(4); /* location in binary */
220 . = PAGE_OFFSET + TEXT_OFFSET; 220 . = PAGE_OFFSET + TEXT_OFFSET;
221#else 221#else
222 __init_end = .;
223 . = ALIGN(THREAD_SIZE); 222 . = ALIGN(THREAD_SIZE);
223 __init_end = .;
224 __data_loc = .; 224 __data_loc = .;
225#endif 225#endif
226 226
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index a99e0cdf8ba2..779605122f32 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -82,12 +82,12 @@ struct kvm_vcpu *kvm_arm_get_running_vcpu(void)
82/** 82/**
83 * kvm_arm_get_running_vcpus - get the per-CPU array of currently running vcpus. 83 * kvm_arm_get_running_vcpus - get the per-CPU array of currently running vcpus.
84 */ 84 */
85struct kvm_vcpu __percpu **kvm_get_running_vcpus(void) 85struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void)
86{ 86{
87 return &kvm_arm_running_vcpu; 87 return &kvm_arm_running_vcpu;
88} 88}
89 89
90int kvm_arch_hardware_enable(void *garbage) 90int kvm_arch_hardware_enable(void)
91{ 91{
92 return 0; 92 return 0;
93} 93}
@@ -97,27 +97,16 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
97 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 97 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
98} 98}
99 99
100void kvm_arch_hardware_disable(void *garbage)
101{
102}
103
104int kvm_arch_hardware_setup(void) 100int kvm_arch_hardware_setup(void)
105{ 101{
106 return 0; 102 return 0;
107} 103}
108 104
109void kvm_arch_hardware_unsetup(void)
110{
111}
112
113void kvm_arch_check_processor_compat(void *rtn) 105void kvm_arch_check_processor_compat(void *rtn)
114{ 106{
115 *(int *)rtn = 0; 107 *(int *)rtn = 0;
116} 108}
117 109
118void kvm_arch_sync_events(struct kvm *kvm)
119{
120}
121 110
122/** 111/**
123 * kvm_arch_init_vm - initializes a VM data structure 112 * kvm_arch_init_vm - initializes a VM data structure
@@ -172,6 +161,8 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
172 kvm->vcpus[i] = NULL; 161 kvm->vcpus[i] = NULL;
173 } 162 }
174 } 163 }
164
165 kvm_vgic_destroy(kvm);
175} 166}
176 167
177int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 168int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
@@ -188,6 +179,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
188 case KVM_CAP_ONE_REG: 179 case KVM_CAP_ONE_REG:
189 case KVM_CAP_ARM_PSCI: 180 case KVM_CAP_ARM_PSCI:
190 case KVM_CAP_ARM_PSCI_0_2: 181 case KVM_CAP_ARM_PSCI_0_2:
182 case KVM_CAP_READONLY_MEM:
191 r = 1; 183 r = 1;
192 break; 184 break;
193 case KVM_CAP_COALESCED_MMIO: 185 case KVM_CAP_COALESCED_MMIO:
@@ -253,6 +245,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
253{ 245{
254 kvm_mmu_free_memory_caches(vcpu); 246 kvm_mmu_free_memory_caches(vcpu);
255 kvm_timer_vcpu_terminate(vcpu); 247 kvm_timer_vcpu_terminate(vcpu);
248 kvm_vgic_vcpu_destroy(vcpu);
256 kmem_cache_free(kvm_vcpu_cache, vcpu); 249 kmem_cache_free(kvm_vcpu_cache, vcpu);
257} 250}
258 251
@@ -268,26 +261,15 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
268 261
269int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 262int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
270{ 263{
271 int ret;
272
273 /* Force users to call KVM_ARM_VCPU_INIT */ 264 /* Force users to call KVM_ARM_VCPU_INIT */
274 vcpu->arch.target = -1; 265 vcpu->arch.target = -1;
275 266
276 /* Set up VGIC */
277 ret = kvm_vgic_vcpu_init(vcpu);
278 if (ret)
279 return ret;
280
281 /* Set up the timer */ 267 /* Set up the timer */
282 kvm_timer_vcpu_init(vcpu); 268 kvm_timer_vcpu_init(vcpu);
283 269
284 return 0; 270 return 0;
285} 271}
286 272
287void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
288{
289}
290
291void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 273void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
292{ 274{
293 vcpu->cpu = cpu; 275 vcpu->cpu = cpu;
@@ -428,9 +410,9 @@ static void update_vttbr(struct kvm *kvm)
428 410
429 /* update vttbr to be used with the new vmid */ 411 /* update vttbr to be used with the new vmid */
430 pgd_phys = virt_to_phys(kvm->arch.pgd); 412 pgd_phys = virt_to_phys(kvm->arch.pgd);
413 BUG_ON(pgd_phys & ~VTTBR_BADDR_MASK);
431 vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK; 414 vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK;
432 kvm->arch.vttbr = pgd_phys & VTTBR_BADDR_MASK; 415 kvm->arch.vttbr = pgd_phys | vmid;
433 kvm->arch.vttbr |= vmid;
434 416
435 spin_unlock(&kvm_vmid_lock); 417 spin_unlock(&kvm_vmid_lock);
436} 418}
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 37a0fe1bb9bb..7928dbdf2102 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -791,7 +791,7 @@ static bool is_valid_cache(u32 val)
791 u32 level, ctype; 791 u32 level, ctype;
792 792
793 if (val >= CSSELR_MAX) 793 if (val >= CSSELR_MAX)
794 return -ENOENT; 794 return false;
795 795
796 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 796 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
797 level = (val >> 1); 797 level = (val >> 1);
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
index 813e49258690..cc0b78769bd8 100644
--- a/arch/arm/kvm/guest.c
+++ b/arch/arm/kvm/guest.c
@@ -163,7 +163,7 @@ static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
163 163
164 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id)); 164 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
165 if (ret != 0) 165 if (ret != 0)
166 return ret; 166 return -EFAULT;
167 167
168 return kvm_arm_timer_set_reg(vcpu, reg->id, val); 168 return kvm_arm_timer_set_reg(vcpu, reg->id, val);
169} 169}
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 16e7994bf347..eea03069161b 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -746,22 +746,29 @@ static bool transparent_hugepage_adjust(pfn_t *pfnp, phys_addr_t *ipap)
746 return false; 746 return false;
747} 747}
748 748
749static bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
750{
751 if (kvm_vcpu_trap_is_iabt(vcpu))
752 return false;
753
754 return kvm_vcpu_dabt_iswrite(vcpu);
755}
756
749static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, 757static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
750 struct kvm_memory_slot *memslot, 758 struct kvm_memory_slot *memslot, unsigned long hva,
751 unsigned long fault_status) 759 unsigned long fault_status)
752{ 760{
753 int ret; 761 int ret;
754 bool write_fault, writable, hugetlb = false, force_pte = false; 762 bool write_fault, writable, hugetlb = false, force_pte = false;
755 unsigned long mmu_seq; 763 unsigned long mmu_seq;
756 gfn_t gfn = fault_ipa >> PAGE_SHIFT; 764 gfn_t gfn = fault_ipa >> PAGE_SHIFT;
757 unsigned long hva = gfn_to_hva(vcpu->kvm, gfn);
758 struct kvm *kvm = vcpu->kvm; 765 struct kvm *kvm = vcpu->kvm;
759 struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache; 766 struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
760 struct vm_area_struct *vma; 767 struct vm_area_struct *vma;
761 pfn_t pfn; 768 pfn_t pfn;
762 pgprot_t mem_type = PAGE_S2; 769 pgprot_t mem_type = PAGE_S2;
763 770
764 write_fault = kvm_is_write_fault(kvm_vcpu_get_hsr(vcpu)); 771 write_fault = kvm_is_write_fault(vcpu);
765 if (fault_status == FSC_PERM && !write_fault) { 772 if (fault_status == FSC_PERM && !write_fault) {
766 kvm_err("Unexpected L2 read permission error\n"); 773 kvm_err("Unexpected L2 read permission error\n");
767 return -EFAULT; 774 return -EFAULT;
@@ -863,7 +870,8 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
863 unsigned long fault_status; 870 unsigned long fault_status;
864 phys_addr_t fault_ipa; 871 phys_addr_t fault_ipa;
865 struct kvm_memory_slot *memslot; 872 struct kvm_memory_slot *memslot;
866 bool is_iabt; 873 unsigned long hva;
874 bool is_iabt, write_fault, writable;
867 gfn_t gfn; 875 gfn_t gfn;
868 int ret, idx; 876 int ret, idx;
869 877
@@ -874,17 +882,22 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
874 kvm_vcpu_get_hfar(vcpu), fault_ipa); 882 kvm_vcpu_get_hfar(vcpu), fault_ipa);
875 883
876 /* Check the stage-2 fault is trans. fault or write fault */ 884 /* Check the stage-2 fault is trans. fault or write fault */
877 fault_status = kvm_vcpu_trap_get_fault(vcpu); 885 fault_status = kvm_vcpu_trap_get_fault_type(vcpu);
878 if (fault_status != FSC_FAULT && fault_status != FSC_PERM) { 886 if (fault_status != FSC_FAULT && fault_status != FSC_PERM) {
879 kvm_err("Unsupported fault status: EC=%#x DFCS=%#lx\n", 887 kvm_err("Unsupported FSC: EC=%#x xFSC=%#lx ESR_EL2=%#lx\n",
880 kvm_vcpu_trap_get_class(vcpu), fault_status); 888 kvm_vcpu_trap_get_class(vcpu),
889 (unsigned long)kvm_vcpu_trap_get_fault(vcpu),
890 (unsigned long)kvm_vcpu_get_hsr(vcpu));
881 return -EFAULT; 891 return -EFAULT;
882 } 892 }
883 893
884 idx = srcu_read_lock(&vcpu->kvm->srcu); 894 idx = srcu_read_lock(&vcpu->kvm->srcu);
885 895
886 gfn = fault_ipa >> PAGE_SHIFT; 896 gfn = fault_ipa >> PAGE_SHIFT;
887 if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) { 897 memslot = gfn_to_memslot(vcpu->kvm, gfn);
898 hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable);
899 write_fault = kvm_is_write_fault(vcpu);
900 if (kvm_is_error_hva(hva) || (write_fault && !writable)) {
888 if (is_iabt) { 901 if (is_iabt) {
889 /* Prefetch Abort on I/O address */ 902 /* Prefetch Abort on I/O address */
890 kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu)); 903 kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
@@ -892,13 +905,6 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
892 goto out_unlock; 905 goto out_unlock;
893 } 906 }
894 907
895 if (fault_status != FSC_FAULT) {
896 kvm_err("Unsupported fault status on io memory: %#lx\n",
897 fault_status);
898 ret = -EFAULT;
899 goto out_unlock;
900 }
901
902 /* 908 /*
903 * The IPA is reported as [MAX:12], so we need to 909 * The IPA is reported as [MAX:12], so we need to
904 * complement it with the bottom 12 bits from the 910 * complement it with the bottom 12 bits from the
@@ -910,9 +916,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
910 goto out_unlock; 916 goto out_unlock;
911 } 917 }
912 918
913 memslot = gfn_to_memslot(vcpu->kvm, gfn); 919 ret = user_mem_abort(vcpu, fault_ipa, memslot, hva, fault_status);
914
915 ret = user_mem_abort(vcpu, fault_ipa, memslot, fault_status);
916 if (ret == 0) 920 if (ret == 0)
917 ret = 1; 921 ret = 1;
918out_unlock: 922out_unlock:
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6cc6f7aebdae..0e6d548b70d9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,6 +12,9 @@ config HAVE_AT91_DBGU0
12config HAVE_AT91_DBGU1 12config HAVE_AT91_DBGU1
13 bool 13 bool
14 14
15config HAVE_AT91_DBGU2
16 bool
17
15config AT91_USE_OLD_CLK 18config AT91_USE_OLD_CLK
16 bool 19 bool
17 20
@@ -28,36 +31,33 @@ config OLD_CLK_AT91
28 bool 31 bool
29 default AT91_PMC_UNIT && AT91_USE_OLD_CLK 32 default AT91_PMC_UNIT && AT91_USE_OLD_CLK
30 33
31config AT91_SAM9_ALT_RESET 34config OLD_IRQ_AT91
32 bool 35 bool
33 default !ARCH_AT91X40 36 select MULTI_IRQ_HANDLER
34 37 select SPARSE_IRQ
35config AT91_SAM9G45_RESET
36 bool
37 default !ARCH_AT91X40
38 38
39config AT91_SAM9_TIME 39config HAVE_AT91_SMD
40 bool 40 bool
41 41
42config HAVE_AT91_SMD 42config HAVE_AT91_H32MX
43 bool 43 bool
44 44
45config SOC_AT91SAM9 45config SOC_AT91SAM9
46 bool 46 bool
47 select AT91_SAM9_TIME 47 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
48 select CPU_ARM926T 48 select CPU_ARM926T
49 select GENERIC_CLOCKEVENTS 49 select GENERIC_CLOCKEVENTS
50 select MULTI_IRQ_HANDLER 50 select MEMORY if USE_OF
51 select SPARSE_IRQ 51 select ATMEL_SDRAMC if USE_OF
52 52
53config SOC_SAMA5 53config SOC_SAMA5
54 bool 54 bool
55 select AT91_SAM9_TIME 55 select ATMEL_AIC5_IRQ
56 select CPU_V7 56 select CPU_V7
57 select GENERIC_CLOCKEVENTS 57 select GENERIC_CLOCKEVENTS
58 select MULTI_IRQ_HANDLER
59 select SPARSE_IRQ
60 select USE_OF 58 select USE_OF
59 select MEMORY
60 select ATMEL_SDRAMC
61 61
62menu "Atmel AT91 System-on-Chip" 62menu "Atmel AT91 System-on-Chip"
63 63
@@ -70,8 +70,7 @@ config ARCH_AT91X40
70 depends on !MMU 70 depends on !MMU
71 select CPU_ARM7TDMI 71 select CPU_ARM7TDMI
72 select ARCH_USES_GETTIMEOFFSET 72 select ARCH_USES_GETTIMEOFFSET
73 select MULTI_IRQ_HANDLER 73 select OLD_IRQ_AT91
74 select SPARSE_IRQ
75 74
76 help 75 help
77 Select this if you are using one of Atmel's AT91X40 SoC. 76 Select this if you are using one of Atmel's AT91X40 SoC.
@@ -103,16 +102,30 @@ config SOC_SAMA5D3
103 help 102 help
104 Select this if you are using one of Atmel's SAMA5D3 family SoC. 103 Select this if you are using one of Atmel's SAMA5D3 family SoC.
105 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. 104 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
105
106config SOC_SAMA5D4
107 bool "SAMA5D4 family"
108 select SOC_SAMA5
109 select HAVE_AT91_DBGU2
110 select CLKSRC_MMIO
111 select CACHE_L2X0
112 select CACHE_PL310
113 select HAVE_FB_ATMEL
114 select HAVE_AT91_UTMI
115 select HAVE_AT91_SMD
116 select HAVE_AT91_USB_CLK
117 select HAVE_AT91_H32MX
118 help
119 Select this if you are using one of Atmel's SAMA5D4 family SoC.
106endif 120endif
107 121
108if SOC_SAM_V4_V5 122if SOC_SAM_V4_V5
109config SOC_AT91RM9200 123config SOC_AT91RM9200
110 bool "AT91RM9200" 124 bool "AT91RM9200"
125 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
111 select CPU_ARM920T 126 select CPU_ARM920T
112 select GENERIC_CLOCKEVENTS 127 select GENERIC_CLOCKEVENTS
113 select HAVE_AT91_DBGU0 128 select HAVE_AT91_DBGU0
114 select MULTI_IRQ_HANDLER
115 select SPARSE_IRQ
116 select HAVE_AT91_USB_CLK 129 select HAVE_AT91_USB_CLK
117 130
118config SOC_AT91SAM9260 131config SOC_AT91SAM9260
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 44ace320d2e1..d8e88219edb4 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,31 +14,37 @@ config ARCH_AT91RM9200
14 bool "AT91RM9200" 14 bool "AT91RM9200"
15 select SOC_AT91RM9200 15 select SOC_AT91RM9200
16 select AT91_USE_OLD_CLK 16 select AT91_USE_OLD_CLK
17 select OLD_IRQ_AT91
17 18
18config ARCH_AT91SAM9260 19config ARCH_AT91SAM9260
19 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" 20 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
20 select SOC_AT91SAM9260 21 select SOC_AT91SAM9260
21 select AT91_USE_OLD_CLK 22 select AT91_USE_OLD_CLK
23 select OLD_IRQ_AT91
22 24
23config ARCH_AT91SAM9261 25config ARCH_AT91SAM9261
24 bool "AT91SAM9261 or AT91SAM9G10" 26 bool "AT91SAM9261 or AT91SAM9G10"
25 select SOC_AT91SAM9261 27 select SOC_AT91SAM9261
26 select AT91_USE_OLD_CLK 28 select AT91_USE_OLD_CLK
29 select OLD_IRQ_AT91
27 30
28config ARCH_AT91SAM9263 31config ARCH_AT91SAM9263
29 bool "AT91SAM9263" 32 bool "AT91SAM9263"
30 select SOC_AT91SAM9263 33 select SOC_AT91SAM9263
31 select AT91_USE_OLD_CLK 34 select AT91_USE_OLD_CLK
35 select OLD_IRQ_AT91
32 36
33config ARCH_AT91SAM9RL 37config ARCH_AT91SAM9RL
34 bool "AT91SAM9RL" 38 bool "AT91SAM9RL"
35 select SOC_AT91SAM9RL 39 select SOC_AT91SAM9RL
36 select AT91_USE_OLD_CLK 40 select AT91_USE_OLD_CLK
41 select OLD_IRQ_AT91
37 42
38config ARCH_AT91SAM9G45 43config ARCH_AT91SAM9G45
39 bool "AT91SAM9G45" 44 bool "AT91SAM9G45"
40 select SOC_AT91SAM9G45 45 select SOC_AT91SAM9G45
41 select AT91_USE_OLD_CLK 46 select AT91_USE_OLD_CLK
47 select OLD_IRQ_AT91
42 48
43endchoice 49endchoice
44 50
@@ -132,12 +138,6 @@ config MACH_ECO920
132 bool "eco920" 138 bool "eco920"
133 help 139 help
134 Select this if you are using the eco920 board 140 Select this if you are using the eco920 board
135
136config MACH_RSI_EWS
137 bool "RSI Embedded Webserver"
138 depends on ARCH_AT91RM9200
139 help
140 Select this if you are using RSIs EWS board.
141endif 141endif
142 142
143# ---------------------------------------------------------- 143# ----------------------------------------------------------
@@ -212,12 +212,6 @@ config MACH_CPU9G20
212 Select this if you are using a Eukrea Electromatique's 212 Select this if you are using a Eukrea Electromatique's
213 CPU9G20 Board <http://www.eukrea.com/> 213 CPU9G20 Board <http://www.eukrea.com/>
214 214
215config MACH_ACMENETUSFOXG20
216 bool "Acme Systems srl FOX Board G20"
217 help
218 Select this if you are using Acme Systems
219 FOX Board G20 <http://www.acmesystems.it>
220
221config MACH_PORTUXG20 215config MACH_PORTUXG20
222 bool "taskit PortuxG20" 216 bool "taskit PortuxG20"
223 help 217 help
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 78e9cec282f4..ac99d87ffefe 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,15 +2,13 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o gpio.o setup.o sysirq_mask.o 5obj-y := gpio.o setup.o sysirq_mask.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
10obj-$(CONFIG_OLD_CLK_AT91) += clock.o 11obj-$(CONFIG_OLD_CLK_AT91) += clock.o
11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
13obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
14obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 12obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
15 13
16# CPU-specific support 14# CPU-specific support
@@ -23,6 +21,7 @@ obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
23obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o 21obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
24obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o 22obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
25obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o 23obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
24obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
26 25
27obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o 26obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
28obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o 27obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
@@ -46,7 +45,6 @@ obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
46obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o 45obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
47obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o 46obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
48obj-$(CONFIG_MACH_ECO920) += board-eco920.o 47obj-$(CONFIG_MACH_ECO920) += board-eco920.o
49obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o
50 48
51# AT91SAM9260 board-specific support 49# AT91SAM9260 board-specific support
52obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o 50obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
@@ -69,7 +67,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
69# AT91SAM9G20 board-specific support 67# AT91SAM9G20 board-specific support
70obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o 68obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
71obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o 69obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
72obj-$(CONFIG_MACH_ACMENETUSFOXG20) += board-foxg20.o
73obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o 70obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
74obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 71obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
75obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o 72obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
diff --git a/arch/arm/mach-at91/at91_rstc.h b/arch/arm/mach-at91/at91_rstc.h
deleted file mode 100644
index a600e6992920..000000000000
--- a/arch/arm/mach-at91/at91_rstc.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_rstc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Reset Controller (RSTC) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_RSTC_H
17#define AT91_RSTC_H
18
19#ifndef __ASSEMBLY__
20extern void __iomem *at91_rstc_base;
21
22#define at91_rstc_read(field) \
23 __raw_readl(at91_rstc_base + field)
24
25#define at91_rstc_write(field, value) \
26 __raw_writel(value, at91_rstc_base + field)
27#else
28.extern at91_rstc_base
29#endif
30
31#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
32#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
33#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
34#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
35#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
36
37#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
38#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
39#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
40#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
41#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
42#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
43#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
44#define AT91_RSTC_RSTTYP_USER (4 << 8)
45#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
46#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
47
48#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
49#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
50#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
51#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
52
53#endif
diff --git a/arch/arm/mach-at91/at91_shdwc.h b/arch/arm/mach-at91/at91_shdwc.h
deleted file mode 100644
index 9e29f31ec9a6..000000000000
--- a/arch/arm/mach-at91/at91_shdwc.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_shdwc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Shutdown Controller (SHDWC) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_SHDWC_H
17#define AT91_SHDWC_H
18
19#ifndef __ASSEMBLY__
20extern void __iomem *at91_shdwc_base;
21
22#define at91_shdwc_read(field) \
23 __raw_readl(at91_shdwc_base + field)
24
25#define at91_shdwc_write(field, value) \
26 __raw_writel(value, at91_shdwc_base + field)
27#endif
28
29#define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
30#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
31#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
32
33#define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
34#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
35#define AT91_SHDW_WKMODE0_NONE 0
36#define AT91_SHDW_WKMODE0_HIGH 1
37#define AT91_SHDW_WKMODE0_LOW 2
38#define AT91_SHDW_WKMODE0_ANYLEVEL 3
39#define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */
40#define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
41#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
42#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
43#define AT91_SHDW_RTCWKEN (1 << 17) /* Real Time Clock Wake-up Enable */
44
45#define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
46#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
47#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
48#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
49
50#endif
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 3477ba94c4c5..aab1f969a7c3 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/platform_device.h>
14#include <linux/clk/at91_pmc.h> 15#include <linux/clk/at91_pmc.h>
15 16
16#include <asm/proc-fns.h> 17#include <asm/proc-fns.h>
@@ -24,7 +25,6 @@
24#include <mach/hardware.h> 25#include <mach/hardware.h>
25 26
26#include "at91_aic.h" 27#include "at91_aic.h"
27#include "at91_rstc.h"
28#include "soc.h" 28#include "soc.h"
29#include "generic.h" 29#include "generic.h"
30#include "sam9_smc.h" 30#include "sam9_smc.h"
@@ -342,8 +342,6 @@ static void __init at91sam9260_map_io(void)
342 342
343static void __init at91sam9260_ioremap_registers(void) 343static void __init at91sam9260_ioremap_registers(void)
344{ 344{
345 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
346 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
347 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512); 345 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
348 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 346 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
349 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 347 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
@@ -354,7 +352,6 @@ static void __init at91sam9260_ioremap_registers(void)
354static void __init at91sam9260_initialize(void) 352static void __init at91sam9260_initialize(void)
355{ 353{
356 arm_pm_idle = at91sam9_idle; 354 arm_pm_idle = at91sam9_idle;
357 arm_pm_restart = at91sam9_alt_restart;
358 355
359 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT); 356 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
360 357
@@ -362,6 +359,45 @@ static void __init at91sam9260_initialize(void)
362 at91_gpio_init(at91sam9260_gpio, 3); 359 at91_gpio_init(at91sam9260_gpio, 3);
363} 360}
364 361
362static struct resource rstc_resources[] = {
363 [0] = {
364 .start = AT91SAM9260_BASE_RSTC,
365 .end = AT91SAM9260_BASE_RSTC + SZ_16 - 1,
366 .flags = IORESOURCE_MEM,
367 },
368 [1] = {
369 .start = AT91SAM9260_BASE_SDRAMC,
370 .end = AT91SAM9260_BASE_SDRAMC + SZ_512 - 1,
371 .flags = IORESOURCE_MEM,
372 },
373};
374
375static struct platform_device rstc_device = {
376 .name = "at91-sam9260-reset",
377 .resource = rstc_resources,
378 .num_resources = ARRAY_SIZE(rstc_resources),
379};
380
381static struct resource shdwc_resources[] = {
382 [0] = {
383 .start = AT91SAM9260_BASE_SHDWC,
384 .end = AT91SAM9260_BASE_SHDWC + SZ_16 - 1,
385 .flags = IORESOURCE_MEM,
386 },
387};
388
389static struct platform_device shdwc_device = {
390 .name = "at91-poweroff",
391 .resource = shdwc_resources,
392 .num_resources = ARRAY_SIZE(shdwc_resources),
393};
394
395static void __init at91sam9260_register_devices(void)
396{
397 platform_device_register(&rstc_device);
398 platform_device_register(&shdwc_device);
399}
400
365/* -------------------------------------------------------------------- 401/* --------------------------------------------------------------------
366 * Interrupt initialization 402 * Interrupt initialization
367 * -------------------------------------------------------------------- */ 403 * -------------------------------------------------------------------- */
@@ -404,6 +440,11 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
404 0, /* Advanced Interrupt Controller */ 440 0, /* Advanced Interrupt Controller */
405}; 441};
406 442
443static void __init at91sam9260_init_time(void)
444{
445 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
446}
447
407AT91_SOC_START(at91sam9260) 448AT91_SOC_START(at91sam9260)
408 .map_io = at91sam9260_map_io, 449 .map_io = at91sam9260_map_io,
409 .default_irq_priority = at91sam9260_default_irq_priority, 450 .default_irq_priority = at91sam9260_default_irq_priority,
@@ -411,5 +452,7 @@ AT91_SOC_START(at91sam9260)
411 | (1 << AT91SAM9260_ID_IRQ2), 452 | (1 << AT91SAM9260_ID_IRQ2),
412 .ioremap_registers = at91sam9260_ioremap_registers, 453 .ioremap_registers = at91sam9260_ioremap_registers,
413 .register_clocks = at91sam9260_register_clocks, 454 .register_clocks = at91sam9260_register_clocks,
455 .register_devices = at91sam9260_register_devices,
414 .init = at91sam9260_initialize, 456 .init = at91sam9260_initialize,
457 .init_time = at91sam9260_init_time,
415AT91_SOC_END 458AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index fb164a5d04a9..a8bd35963332 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/platform_device.h>
14#include <linux/clk/at91_pmc.h> 15#include <linux/clk/at91_pmc.h>
15 16
16#include <asm/proc-fns.h> 17#include <asm/proc-fns.h>
@@ -23,7 +24,6 @@
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24 25
25#include "at91_aic.h" 26#include "at91_aic.h"
26#include "at91_rstc.h"
27#include "soc.h" 27#include "soc.h"
28#include "generic.h" 28#include "generic.h"
29#include "sam9_smc.h" 29#include "sam9_smc.h"
@@ -301,8 +301,6 @@ static void __init at91sam9261_map_io(void)
301 301
302static void __init at91sam9261_ioremap_registers(void) 302static void __init at91sam9261_ioremap_registers(void)
303{ 303{
304 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
305 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
306 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512); 304 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
307 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 305 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
308 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 306 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
@@ -313,7 +311,6 @@ static void __init at91sam9261_ioremap_registers(void)
313static void __init at91sam9261_initialize(void) 311static void __init at91sam9261_initialize(void)
314{ 312{
315 arm_pm_idle = at91sam9_idle; 313 arm_pm_idle = at91sam9_idle;
316 arm_pm_restart = at91sam9_alt_restart;
317 314
318 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT); 315 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
319 316
@@ -321,6 +318,45 @@ static void __init at91sam9261_initialize(void)
321 at91_gpio_init(at91sam9261_gpio, 3); 318 at91_gpio_init(at91sam9261_gpio, 3);
322} 319}
323 320
321static struct resource rstc_resources[] = {
322 [0] = {
323 .start = AT91SAM9261_BASE_RSTC,
324 .end = AT91SAM9261_BASE_RSTC + SZ_16 - 1,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .start = AT91SAM9261_BASE_SDRAMC,
329 .end = AT91SAM9261_BASE_SDRAMC + SZ_512 - 1,
330 .flags = IORESOURCE_MEM,
331 },
332};
333
334static struct platform_device rstc_device = {
335 .name = "at91-sam9260-reset",
336 .resource = rstc_resources,
337 .num_resources = ARRAY_SIZE(rstc_resources),
338};
339
340static struct resource shdwc_resources[] = {
341 [0] = {
342 .start = AT91SAM9261_BASE_SHDWC,
343 .end = AT91SAM9261_BASE_SHDWC + SZ_16 - 1,
344 .flags = IORESOURCE_MEM,
345 },
346};
347
348static struct platform_device shdwc_device = {
349 .name = "at91-poweroff",
350 .resource = shdwc_resources,
351 .num_resources = ARRAY_SIZE(shdwc_resources),
352};
353
354static void __init at91sam9261_register_devices(void)
355{
356 platform_device_register(&rstc_device);
357 platform_device_register(&shdwc_device);
358}
359
324/* -------------------------------------------------------------------- 360/* --------------------------------------------------------------------
325 * Interrupt initialization 361 * Interrupt initialization
326 * -------------------------------------------------------------------- */ 362 * -------------------------------------------------------------------- */
@@ -363,6 +399,11 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
363 0, /* Advanced Interrupt Controller */ 399 0, /* Advanced Interrupt Controller */
364}; 400};
365 401
402static void __init at91sam9261_init_time(void)
403{
404 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
405}
406
366AT91_SOC_START(at91sam9261) 407AT91_SOC_START(at91sam9261)
367 .map_io = at91sam9261_map_io, 408 .map_io = at91sam9261_map_io,
368 .default_irq_priority = at91sam9261_default_irq_priority, 409 .default_irq_priority = at91sam9261_default_irq_priority,
@@ -370,5 +411,7 @@ AT91_SOC_START(at91sam9261)
370 | (1 << AT91SAM9261_ID_IRQ2), 411 | (1 << AT91SAM9261_ID_IRQ2),
371 .ioremap_registers = at91sam9261_ioremap_registers, 412 .ioremap_registers = at91sam9261_ioremap_registers,
372 .register_clocks = at91sam9261_register_clocks, 413 .register_clocks = at91sam9261_register_clocks,
414 .register_devices = at91sam9261_register_devices,
373 .init = at91sam9261_initialize, 415 .init = at91sam9261_initialize,
416 .init_time = at91sam9261_init_time,
374AT91_SOC_END 417AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 810fa5f15a51..fbff228cc63e 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/platform_device.h>
14#include <linux/clk/at91_pmc.h> 15#include <linux/clk/at91_pmc.h>
15 16
16#include <asm/proc-fns.h> 17#include <asm/proc-fns.h>
@@ -22,7 +23,6 @@
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23 24
24#include "at91_aic.h" 25#include "at91_aic.h"
25#include "at91_rstc.h"
26#include "soc.h" 26#include "soc.h"
27#include "generic.h" 27#include "generic.h"
28#include "sam9_smc.h" 28#include "sam9_smc.h"
@@ -321,8 +321,6 @@ static void __init at91sam9263_map_io(void)
321 321
322static void __init at91sam9263_ioremap_registers(void) 322static void __init at91sam9263_ioremap_registers(void)
323{ 323{
324 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
325 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
326 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512); 324 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
327 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512); 325 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
328 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 326 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
@@ -335,7 +333,6 @@ static void __init at91sam9263_ioremap_registers(void)
335static void __init at91sam9263_initialize(void) 333static void __init at91sam9263_initialize(void)
336{ 334{
337 arm_pm_idle = at91sam9_idle; 335 arm_pm_idle = at91sam9_idle;
338 arm_pm_restart = at91sam9_alt_restart;
339 336
340 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0); 337 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
341 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1); 338 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
@@ -344,6 +341,45 @@ static void __init at91sam9263_initialize(void)
344 at91_gpio_init(at91sam9263_gpio, 5); 341 at91_gpio_init(at91sam9263_gpio, 5);
345} 342}
346 343
344static struct resource rstc_resources[] = {
345 [0] = {
346 .start = AT91SAM9263_BASE_RSTC,
347 .end = AT91SAM9263_BASE_RSTC + SZ_16 - 1,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AT91SAM9263_BASE_SDRAMC0,
352 .end = AT91SAM9263_BASE_SDRAMC0 + SZ_512 - 1,
353 .flags = IORESOURCE_MEM,
354 },
355};
356
357static struct platform_device rstc_device = {
358 .name = "at91-sam9260-reset",
359 .resource = rstc_resources,
360 .num_resources = ARRAY_SIZE(rstc_resources),
361};
362
363static struct resource shdwc_resources[] = {
364 [0] = {
365 .start = AT91SAM9263_BASE_SHDWC,
366 .end = AT91SAM9263_BASE_SHDWC + SZ_16 - 1,
367 .flags = IORESOURCE_MEM,
368 },
369};
370
371static struct platform_device shdwc_device = {
372 .name = "at91-poweroff",
373 .resource = shdwc_resources,
374 .num_resources = ARRAY_SIZE(shdwc_resources),
375};
376
377static void __init at91sam9263_register_devices(void)
378{
379 platform_device_register(&rstc_device);
380 platform_device_register(&shdwc_device);
381}
382
347/* -------------------------------------------------------------------- 383/* --------------------------------------------------------------------
348 * Interrupt initialization 384 * Interrupt initialization
349 * -------------------------------------------------------------------- */ 385 * -------------------------------------------------------------------- */
@@ -386,11 +422,18 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
386 0, /* Advanced Interrupt Controller (IRQ1) */ 422 0, /* Advanced Interrupt Controller (IRQ1) */
387}; 423};
388 424
425static void __init at91sam9263_init_time(void)
426{
427 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
428}
429
389AT91_SOC_START(at91sam9263) 430AT91_SOC_START(at91sam9263)
390 .map_io = at91sam9263_map_io, 431 .map_io = at91sam9263_map_io,
391 .default_irq_priority = at91sam9263_default_irq_priority, 432 .default_irq_priority = at91sam9263_default_irq_priority,
392 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1), 433 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
393 .ioremap_registers = at91sam9263_ioremap_registers, 434 .ioremap_registers = at91sam9263_ioremap_registers,
394 .register_clocks = at91sam9263_register_clocks, 435 .register_clocks = at91sam9263_register_clocks,
436 .register_devices = at91sam9263_register_devices,
395 .init = at91sam9263_initialize, 437 .init = at91sam9263_initialize,
438 .init_time = at91sam9263_init_time,
396AT91_SOC_END 439AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
deleted file mode 100644
index 0a9e2fc8f796..000000000000
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
3 *
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6 * Converted to ClockSource/ClockEvents by David Brownell.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/clockchips.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20
21#include <asm/mach/time.h>
22#include <mach/hardware.h>
23
24#define AT91_PIT_MR 0x00 /* Mode Register */
25#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
26#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
27#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
28
29#define AT91_PIT_SR 0x04 /* Status Register */
30#define AT91_PIT_PITS (1 << 0) /* Timer Status */
31
32#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
33#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
34#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
35#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
36
37#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
38#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
39
40static u32 pit_cycle; /* write-once */
41static u32 pit_cnt; /* access only w/system irq blocked */
42static void __iomem *pit_base_addr __read_mostly;
43static struct clk *mck;
44
45static inline unsigned int pit_read(unsigned int reg_offset)
46{
47 return __raw_readl(pit_base_addr + reg_offset);
48}
49
50static inline void pit_write(unsigned int reg_offset, unsigned long value)
51{
52 __raw_writel(value, pit_base_addr + reg_offset);
53}
54
55/*
56 * Clocksource: just a monotonic counter of MCK/16 cycles.
57 * We don't care whether or not PIT irqs are enabled.
58 */
59static cycle_t read_pit_clk(struct clocksource *cs)
60{
61 unsigned long flags;
62 u32 elapsed;
63 u32 t;
64
65 raw_local_irq_save(flags);
66 elapsed = pit_cnt;
67 t = pit_read(AT91_PIT_PIIR);
68 raw_local_irq_restore(flags);
69
70 elapsed += PIT_PICNT(t) * pit_cycle;
71 elapsed += PIT_CPIV(t);
72 return elapsed;
73}
74
75static struct clocksource pit_clk = {
76 .name = "pit",
77 .rating = 175,
78 .read = read_pit_clk,
79 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
80};
81
82
83/*
84 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
85 */
86static void
87pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
88{
89 switch (mode) {
90 case CLOCK_EVT_MODE_PERIODIC:
91 /* update clocksource counter */
92 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
93 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
94 | AT91_PIT_PITIEN);
95 break;
96 case CLOCK_EVT_MODE_ONESHOT:
97 BUG();
98 /* FALLTHROUGH */
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 case CLOCK_EVT_MODE_UNUSED:
101 /* disable irq, leaving the clocksource active */
102 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
103 break;
104 case CLOCK_EVT_MODE_RESUME:
105 break;
106 }
107}
108
109static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
110{
111 /* Disable timer */
112 pit_write(AT91_PIT_MR, 0);
113}
114
115static void at91sam926x_pit_reset(void)
116{
117 /* Disable timer and irqs */
118 pit_write(AT91_PIT_MR, 0);
119
120 /* Clear any pending interrupts, wait for PIT to stop counting */
121 while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
122 cpu_relax();
123
124 /* Start PIT but don't enable IRQ */
125 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
126}
127
128static void at91sam926x_pit_resume(struct clock_event_device *cedev)
129{
130 at91sam926x_pit_reset();
131}
132
133static struct clock_event_device pit_clkevt = {
134 .name = "pit",
135 .features = CLOCK_EVT_FEAT_PERIODIC,
136 .shift = 32,
137 .rating = 100,
138 .set_mode = pit_clkevt_mode,
139 .suspend = at91sam926x_pit_suspend,
140 .resume = at91sam926x_pit_resume,
141};
142
143
144/*
145 * IRQ handler for the timer.
146 */
147static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
148{
149 /*
150 * irqs should be disabled here, but as the irq is shared they are only
151 * guaranteed to be off if the timer irq is registered first.
152 */
153 WARN_ON_ONCE(!irqs_disabled());
154
155 /* The PIT interrupt may be disabled, and is shared */
156 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
157 && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
158 unsigned nr_ticks;
159
160 /* Get number of ticks performed before irq, and ack it */
161 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
162 do {
163 pit_cnt += pit_cycle;
164 pit_clkevt.event_handler(&pit_clkevt);
165 nr_ticks--;
166 } while (nr_ticks);
167
168 return IRQ_HANDLED;
169 }
170
171 return IRQ_NONE;
172}
173
174static struct irqaction at91sam926x_pit_irq = {
175 .name = "at91_tick",
176 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
177 .handler = at91sam926x_pit_interrupt,
178 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
179};
180
181#ifdef CONFIG_OF
182static struct of_device_id pit_timer_ids[] = {
183 { .compatible = "atmel,at91sam9260-pit" },
184 { /* sentinel */ }
185};
186
187static int __init of_at91sam926x_pit_init(void)
188{
189 struct device_node *np;
190 int ret;
191
192 np = of_find_matching_node(NULL, pit_timer_ids);
193 if (!np)
194 goto err;
195
196 pit_base_addr = of_iomap(np, 0);
197 if (!pit_base_addr)
198 goto node_err;
199
200 mck = of_clk_get(np, 0);
201
202 /* Get the interrupts property */
203 ret = irq_of_parse_and_map(np, 0);
204 if (!ret) {
205 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
206 if (!IS_ERR(mck))
207 clk_put(mck);
208 goto ioremap_err;
209 }
210 at91sam926x_pit_irq.irq = ret;
211
212 of_node_put(np);
213
214 return 0;
215
216ioremap_err:
217 iounmap(pit_base_addr);
218node_err:
219 of_node_put(np);
220err:
221 return -EINVAL;
222}
223#else
224static int __init of_at91sam926x_pit_init(void)
225{
226 return -EINVAL;
227}
228#endif
229
230/*
231 * Set up both clocksource and clockevent support.
232 */
233void __init at91sam926x_pit_init(void)
234{
235 unsigned long pit_rate;
236 unsigned bits;
237 int ret;
238
239 mck = ERR_PTR(-ENOENT);
240
241 /* For device tree enabled device: initialize here */
242 of_at91sam926x_pit_init();
243
244 /*
245 * Use our actual MCK to figure out how many MCK/16 ticks per
246 * 1/HZ period (instead of a compile-time constant LATCH).
247 */
248 if (IS_ERR(mck))
249 mck = clk_get(NULL, "mck");
250
251 if (IS_ERR(mck))
252 panic("AT91: PIT: Unable to get mck clk\n");
253 pit_rate = clk_get_rate(mck) / 16;
254 pit_cycle = (pit_rate + HZ/2) / HZ;
255 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
256
257 /* Initialize and enable the timer */
258 at91sam926x_pit_reset();
259
260 /*
261 * Register clocksource. The high order bits of PIV are unused,
262 * so this isn't a 32-bit counter unless we get clockevent irqs.
263 */
264 bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
265 pit_clk.mask = CLOCKSOURCE_MASK(bits);
266 clocksource_register_hz(&pit_clk, pit_rate);
267
268 /* Set up irq handler */
269 ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
270 if (ret)
271 pr_crit("AT91: PIT: Unable to setup IRQ\n");
272
273 /* Set up and register clockevents */
274 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
275 pit_clkevt.cpumask = cpumask_of(0);
276 clockevents_register_device(&pit_clkevt);
277}
278
279void __init at91sam926x_ioremap_pit(u32 addr)
280{
281#if defined(CONFIG_OF)
282 struct device_node *np =
283 of_find_matching_node(NULL, pit_timer_ids);
284
285 if (np) {
286 of_node_put(np);
287 return;
288 }
289#endif
290 pit_base_addr = ioremap(addr, 16);
291
292 if (!pit_base_addr)
293 panic("Impossible to ioremap PIT\n");
294}
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
deleted file mode 100644
index f039538d3bdb..000000000000
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * reset AT91SAM9G20 as per errata
3 *
4 * (C) BitBox Ltd 2010
5 *
6 * unless the SDRAM is cleanly shutdown before we hit the
7 * reset register it can be left driving the data bus and
8 * killing the chance of a subsequent boot from NAND
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/linkage.h>
17#include <mach/hardware.h>
18#include <mach/at91_ramc.h>
19#include "at91_rstc.h"
20
21 .arm
22
23 .globl at91sam9_alt_restart
24
25at91sam9_alt_restart: ldr r0, =at91_ramc_base @ preload constants
26 ldr r0, [r0]
27 ldr r4, =at91_rstc_base
28 ldr r1, [r4]
29
30 mov r2, #1
31 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
32 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
33
34 .balign 32 @ align to cache line
35
36 str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
37 str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
38 str r4, [r1, #AT91_RSTC_CR] @ reset processor
39
40 b .
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9d45496e4932..405427ec05f8 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -13,6 +13,7 @@
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/clk/at91_pmc.h> 15#include <linux/clk/at91_pmc.h>
16#include <linux/platform_device.h>
16 17
17#include <asm/irq.h> 18#include <asm/irq.h>
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
@@ -371,8 +372,6 @@ static void __init at91sam9g45_map_io(void)
371 372
372static void __init at91sam9g45_ioremap_registers(void) 373static void __init at91sam9g45_ioremap_registers(void)
373{ 374{
374 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
375 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
376 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512); 375 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
377 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512); 376 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
378 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 377 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
@@ -384,7 +383,6 @@ static void __init at91sam9g45_ioremap_registers(void)
384static void __init at91sam9g45_initialize(void) 383static void __init at91sam9g45_initialize(void)
385{ 384{
386 arm_pm_idle = at91sam9_idle; 385 arm_pm_idle = at91sam9_idle;
387 arm_pm_restart = at91sam9g45_restart;
388 386
389 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC); 387 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
390 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT); 388 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
@@ -393,6 +391,50 @@ static void __init at91sam9g45_initialize(void)
393 at91_gpio_init(at91sam9g45_gpio, 5); 391 at91_gpio_init(at91sam9g45_gpio, 5);
394} 392}
395 393
394static struct resource rstc_resources[] = {
395 [0] = {
396 .start = AT91SAM9G45_BASE_RSTC,
397 .end = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = AT91SAM9G45_BASE_DDRSDRC1,
402 .end = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
403 .flags = IORESOURCE_MEM,
404 },
405 [2] = {
406 .start = AT91SAM9G45_BASE_DDRSDRC0,
407 .end = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
408 .flags = IORESOURCE_MEM,
409 },
410};
411
412static struct platform_device rstc_device = {
413 .name = "at91-sam9g45-reset",
414 .resource = rstc_resources,
415 .num_resources = ARRAY_SIZE(rstc_resources),
416};
417
418static struct resource shdwc_resources[] = {
419 [0] = {
420 .start = AT91SAM9G45_BASE_SHDWC,
421 .end = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
422 .flags = IORESOURCE_MEM,
423 },
424};
425
426static struct platform_device shdwc_device = {
427 .name = "at91-poweroff",
428 .resource = shdwc_resources,
429 .num_resources = ARRAY_SIZE(shdwc_resources),
430};
431
432static void __init at91sam9g45_register_devices(void)
433{
434 platform_device_register(&rstc_device);
435 platform_device_register(&shdwc_device);
436}
437
396/* -------------------------------------------------------------------- 438/* --------------------------------------------------------------------
397 * Interrupt initialization 439 * Interrupt initialization
398 * -------------------------------------------------------------------- */ 440 * -------------------------------------------------------------------- */
@@ -435,11 +477,18 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
435 0, /* Advanced Interrupt Controller (IRQ0) */ 477 0, /* Advanced Interrupt Controller (IRQ0) */
436}; 478};
437 479
480static void __init at91sam9g45_init_time(void)
481{
482 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
483}
484
438AT91_SOC_START(at91sam9g45) 485AT91_SOC_START(at91sam9g45)
439 .map_io = at91sam9g45_map_io, 486 .map_io = at91sam9g45_map_io,
440 .default_irq_priority = at91sam9g45_default_irq_priority, 487 .default_irq_priority = at91sam9g45_default_irq_priority,
441 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0), 488 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
442 .ioremap_registers = at91sam9g45_ioremap_registers, 489 .ioremap_registers = at91sam9g45_ioremap_registers,
443 .register_clocks = at91sam9g45_register_clocks, 490 .register_clocks = at91sam9g45_register_clocks,
491 .register_devices = at91sam9g45_register_devices,
444 .init = at91sam9g45_initialize, 492 .init = at91sam9g45_initialize,
493 .init_time = at91sam9g45_init_time,
445AT91_SOC_END 494AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
deleted file mode 100644
index c40c1e2ef80f..000000000000
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * reset AT91SAM9G45 as per errata
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
5 *
6 * unless the SDRAM is cleanly shutdown before we hit the
7 * reset register it can be left driving the data bus and
8 * killing the chance of a subsequent boot from NAND
9 *
10 * GPLv2 Only
11 */
12
13#include <linux/linkage.h>
14#include <mach/hardware.h>
15#include <mach/at91_ramc.h>
16#include "at91_rstc.h"
17 .arm
18
19/*
20 * at91_ramc_base is an array void*
21 * init at NULL if only one DDR controler is present in or DT
22 */
23 .globl at91sam9g45_restart
24
25at91sam9g45_restart:
26 ldr r5, =at91_ramc_base @ preload constants
27 ldr r0, [r5]
28 ldr r5, [r5, #4] @ ddr1
29 cmp r5, #0
30 ldr r4, =at91_rstc_base
31 ldr r1, [r4]
32
33 mov r2, #1
34 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
35 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
36
37 .balign 32 @ align to cache line
38
39 strne r2, [r5, #AT91_DDRSDRC_RTR] @ disable DDR1 access
40 strne r3, [r5, #AT91_DDRSDRC_LPR] @ power down DDR1
41 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
42 str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
43 str r4, [r1, #AT91_RSTC_CR] @ reset processor
44
45 b .
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 878d5015daab..f553e4ea034b 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/platform_device.h>
13#include <linux/clk/at91_pmc.h> 14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/proc-fns.h> 16#include <asm/proc-fns.h>
@@ -23,7 +24,6 @@
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24 25
25#include "at91_aic.h" 26#include "at91_aic.h"
26#include "at91_rstc.h"
27#include "soc.h" 27#include "soc.h"
28#include "generic.h" 28#include "generic.h"
29#include "sam9_smc.h" 29#include "sam9_smc.h"
@@ -311,8 +311,6 @@ static void __init at91sam9rl_map_io(void)
311 311
312static void __init at91sam9rl_ioremap_registers(void) 312static void __init at91sam9rl_ioremap_registers(void)
313{ 313{
314 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
315 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
316 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512); 314 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
317 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 315 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
318 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 316 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
@@ -323,7 +321,6 @@ static void __init at91sam9rl_ioremap_registers(void)
323static void __init at91sam9rl_initialize(void) 321static void __init at91sam9rl_initialize(void)
324{ 322{
325 arm_pm_idle = at91sam9_idle; 323 arm_pm_idle = at91sam9_idle;
326 arm_pm_restart = at91sam9_alt_restart;
327 324
328 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); 325 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
329 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); 326 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
@@ -332,6 +329,45 @@ static void __init at91sam9rl_initialize(void)
332 at91_gpio_init(at91sam9rl_gpio, 4); 329 at91_gpio_init(at91sam9rl_gpio, 4);
333} 330}
334 331
332static struct resource rstc_resources[] = {
333 [0] = {
334 .start = AT91SAM9RL_BASE_RSTC,
335 .end = AT91SAM9RL_BASE_RSTC + SZ_16 - 1,
336 .flags = IORESOURCE_MEM,
337 },
338 [1] = {
339 .start = AT91SAM9RL_BASE_SDRAMC,
340 .end = AT91SAM9RL_BASE_SDRAMC + SZ_512 - 1,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct platform_device rstc_device = {
346 .name = "at91-sam9260-reset",
347 .resource = rstc_resources,
348 .num_resources = ARRAY_SIZE(rstc_resources),
349};
350
351static struct resource shdwc_resources[] = {
352 [0] = {
353 .start = AT91SAM9RL_BASE_SHDWC,
354 .end = AT91SAM9RL_BASE_SHDWC + SZ_16 - 1,
355 .flags = IORESOURCE_MEM,
356 },
357};
358
359static struct platform_device shdwc_device = {
360 .name = "at91-poweroff",
361 .resource = shdwc_resources,
362 .num_resources = ARRAY_SIZE(shdwc_resources),
363};
364
365static void __init at91sam9rl_register_devices(void)
366{
367 platform_device_register(&rstc_device);
368 platform_device_register(&shdwc_device);
369}
370
335/* -------------------------------------------------------------------- 371/* --------------------------------------------------------------------
336 * Interrupt initialization 372 * Interrupt initialization
337 * -------------------------------------------------------------------- */ 373 * -------------------------------------------------------------------- */
@@ -374,6 +410,11 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
374 0, /* Advanced Interrupt Controller */ 410 0, /* Advanced Interrupt Controller */
375}; 411};
376 412
413static void __init at91sam9rl_init_time(void)
414{
415 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
416}
417
377AT91_SOC_START(at91sam9rl) 418AT91_SOC_START(at91sam9rl)
378 .map_io = at91sam9rl_map_io, 419 .map_io = at91sam9rl_map_io,
379 .default_irq_priority = at91sam9rl_default_irq_priority, 420 .default_irq_priority = at91sam9rl_default_irq_priority,
@@ -382,5 +423,7 @@ AT91_SOC_START(at91sam9rl)
382#if defined(CONFIG_OLD_CLK_AT91) 423#if defined(CONFIG_OLD_CLK_AT91)
383 .register_clocks = at91sam9rl_register_clocks, 424 .register_clocks = at91sam9rl_register_clocks,
384#endif 425#endif
426 .register_devices = at91sam9rl_register_devices,
385 .init = at91sam9rl_initialize, 427 .init = at91sam9rl_initialize,
428 .init_time = at91sam9rl_init_time,
386AT91_SOC_END 429AT91_SOC_END
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 597c649170aa..e76e35ce81e7 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -167,6 +167,8 @@ static struct at91_cf_data afeb9260_cf_data = {
167 167
168static void __init afeb9260_board_init(void) 168static void __init afeb9260_board_init(void)
169{ 169{
170 at91_register_devices();
171
170 /* Serial */ 172 /* Serial */
171 /* DBGU on ttyS0. (Rx & Tx only) */ 173 /* DBGU on ttyS0. (Rx & Tx only) */
172 at91_register_uart(0, 0, 0); 174 at91_register_uart(0, 0, 0);
@@ -211,7 +213,7 @@ static void __init afeb9260_board_init(void)
211 213
212MACHINE_START(AFEB9260, "Custom afeb9260 board") 214MACHINE_START(AFEB9260, "Custom afeb9260 board")
213 /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ 215 /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
214 .init_time = at91sam926x_pit_init, 216 .init_time = at91_init_time,
215 .map_io = at91_map_io, 217 .map_io = at91_map_io,
216 .handle_irq = at91_aic_handle_irq, 218 .handle_irq = at91_aic_handle_irq,
217 .init_early = afeb9260_init_early, 219 .init_early = afeb9260_init_early,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index a30502c8d379..ae827dd2d0d2 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -170,6 +170,8 @@ static void __init cam60_add_device_nand(void)
170 170
171static void __init cam60_board_init(void) 171static void __init cam60_board_init(void)
172{ 172{
173 at91_register_devices();
174
173 /* Serial */ 175 /* Serial */
174 /* DBGU on ttyS0. (Rx & Tx only) */ 176 /* DBGU on ttyS0. (Rx & Tx only) */
175 at91_register_uart(0, 0, 0); 177 at91_register_uart(0, 0, 0);
@@ -188,7 +190,7 @@ static void __init cam60_board_init(void)
188 190
189MACHINE_START(CAM60, "KwikByte CAM60") 191MACHINE_START(CAM60, "KwikByte CAM60")
190 /* Maintainer: KwikByte */ 192 /* Maintainer: KwikByte */
191 .init_time = at91sam926x_pit_init, 193 .init_time = at91_init_time,
192 .map_io = at91_map_io, 194 .map_io = at91_map_io,
193 .handle_irq = at91_aic_handle_irq, 195 .handle_irq = at91_aic_handle_irq,
194 .init_early = cam60_init_early, 196 .init_early = cam60_init_early,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 2037f78c84e7..731c8318f4f5 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -322,6 +322,8 @@ static struct mci_platform_data __initdata cpu9krea_mci0_data = {
322 322
323static void __init cpu9krea_board_init(void) 323static void __init cpu9krea_board_init(void)
324{ 324{
325 at91_register_devices();
326
325 /* NOR */ 327 /* NOR */
326 cpu9krea_add_device_nor(); 328 cpu9krea_add_device_nor();
327 /* Serial */ 329 /* Serial */
@@ -375,7 +377,7 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
375MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") 377MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
376#endif 378#endif
377 /* Maintainer: Eric Benard - EUKREA Electromatique */ 379 /* Maintainer: Eric Benard - EUKREA Electromatique */
378 .init_time = at91sam926x_pit_init, 380 .init_time = at91_init_time,
379 .map_io = at91_map_io, 381 .map_io = at91_map_io,
380 .handle_irq = at91_aic_handle_irq, 382 .handle_irq = at91_aic_handle_irq,
381 .init_early = cpu9krea_init_early, 383 .init_early = cpu9krea_init_early,
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index f4b6e91843e4..226563f850b8 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -25,17 +25,6 @@
25#include "at91_aic.h" 25#include "at91_aic.h"
26#include "generic.h" 26#include "generic.h"
27 27
28
29static const struct of_device_id irq_of_match[] __initconst = {
30 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
31 { /*sentinel*/ }
32};
33
34static void __init at91rm9200_dt_init_irq(void)
35{
36 of_irq_init(irq_of_match);
37}
38
39static void __init at91rm9200_dt_timer_init(void) 28static void __init at91rm9200_dt_timer_init(void)
40{ 29{
41#if defined(CONFIG_COMMON_CLK) 30#if defined(CONFIG_COMMON_CLK)
@@ -52,8 +41,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
52DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)") 41DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
53 .init_time = at91rm9200_dt_timer_init, 42 .init_time = at91rm9200_dt_timer_init,
54 .map_io = at91_map_io, 43 .map_io = at91_map_io,
55 .handle_irq = at91_aic_handle_irq,
56 .init_early = at91rm9200_dt_initialize, 44 .init_early = at91rm9200_dt_initialize,
57 .init_irq = at91rm9200_dt_init_irq,
58 .dt_compat = at91rm9200_dt_board_compat, 45 .dt_compat = at91rm9200_dt_board_compat,
59MACHINE_END 46MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 575b0be66ca8..d3048ccdc41f 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -25,26 +25,6 @@
25#include "board.h" 25#include "board.h"
26#include "generic.h" 26#include "generic.h"
27 27
28
29static void __init sam9_dt_timer_init(void)
30{
31#if defined(CONFIG_COMMON_CLK)
32 of_clk_init(NULL);
33#endif
34 at91sam926x_pit_init();
35}
36
37static const struct of_device_id irq_of_match[] __initconst = {
38
39 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
40 { /*sentinel*/ }
41};
42
43static void __init at91_dt_init_irq(void)
44{
45 of_irq_init(irq_of_match);
46}
47
48static const char *at91_dt_board_compat[] __initdata = { 28static const char *at91_dt_board_compat[] __initdata = {
49 "atmel,at91sam9", 29 "atmel,at91sam9",
50 NULL 30 NULL
@@ -52,10 +32,7 @@ static const char *at91_dt_board_compat[] __initdata = {
52 32
53DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") 33DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
54 /* Maintainer: Atmel */ 34 /* Maintainer: Atmel */
55 .init_time = sam9_dt_timer_init,
56 .map_io = at91_map_io, 35 .map_io = at91_map_io,
57 .handle_irq = at91_aic_handle_irq,
58 .init_early = at91_dt_initialize, 36 .init_early = at91_dt_initialize,
59 .init_irq = at91_dt_init_irq,
60 .dt_compat = at91_dt_board_compat, 37 .dt_compat = at91_dt_board_compat,
61MACHINE_END 38MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 075ec0576ada..129e2917506b 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -27,64 +27,34 @@
27#include "at91_aic.h" 27#include "at91_aic.h"
28#include "generic.h" 28#include "generic.h"
29 29
30static void __init sama5_dt_timer_init(void)
31{
32#if defined(CONFIG_COMMON_CLK)
33 of_clk_init(NULL);
34#endif
35 at91sam926x_pit_init();
36}
37
38static const struct of_device_id irq_of_match[] __initconst = {
39
40 { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
41 { /*sentinel*/ }
42};
43
44static void __init at91_dt_init_irq(void)
45{
46 of_irq_init(irq_of_match);
47}
48
49static int ksz9021rn_phy_fixup(struct phy_device *phy)
50{
51 int value;
52
53 /* Set delay values */
54 value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
55 phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
56 value = 0xF2F4;
57 phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
58 value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
59 phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
60 value = 0x2222;
61 phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
62
63 return 0;
64}
65
66static void __init sama5_dt_device_init(void) 30static void __init sama5_dt_device_init(void)
67{ 31{
68 if (of_machine_is_compatible("atmel,sama5d3xcm") &&
69 IS_ENABLED(CONFIG_PHYLIB))
70 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
71 ksz9021rn_phy_fixup);
72
73 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 32 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
74} 33}
75 34
76static const char *sama5_dt_board_compat[] __initdata = { 35static const char *sama5_dt_board_compat[] __initconst = {
77 "atmel,sama5", 36 "atmel,sama5",
78 NULL 37 NULL
79}; 38};
80 39
81DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") 40DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
82 /* Maintainer: Atmel */ 41 /* Maintainer: Atmel */
83 .init_time = sama5_dt_timer_init,
84 .map_io = at91_map_io, 42 .map_io = at91_map_io,
85 .handle_irq = at91_aic5_handle_irq,
86 .init_early = at91_dt_initialize, 43 .init_early = at91_dt_initialize,
87 .init_irq = at91_dt_init_irq,
88 .init_machine = sama5_dt_device_init, 44 .init_machine = sama5_dt_device_init,
89 .dt_compat = sama5_dt_board_compat, 45 .dt_compat = sama5_dt_board_compat,
90MACHINE_END 46MACHINE_END
47
48static const char *sama5_alt_dt_board_compat[] __initconst = {
49 "atmel,sama5d4",
50 NULL
51};
52
53DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5 (Device Tree)")
54 /* Maintainer: Atmel */
55 .map_io = at91_alt_map_io,
56 .init_early = at91_dt_initialize,
57 .init_machine = sama5_dt_device_init,
58 .dt_compat = sama5_alt_dt_board_compat,
59 .l2c_aux_mask = ~0UL,
60MACHINE_END
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 68f1ab6bd08f..a6aa4a2432f2 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -138,6 +138,8 @@ static struct gpio_led flexibity_leds[] = {
138 138
139static void __init flexibity_board_init(void) 139static void __init flexibity_board_init(void)
140{ 140{
141 at91_register_devices();
142
141 /* Serial */ 143 /* Serial */
142 /* DBGU on ttyS0. (Rx & Tx only) */ 144 /* DBGU on ttyS0. (Rx & Tx only) */
143 at91_register_uart(0, 0, 0); 145 at91_register_uart(0, 0, 0);
@@ -160,7 +162,7 @@ static void __init flexibity_board_init(void)
160 162
161MACHINE_START(FLEXIBITY, "Flexibity Connect") 163MACHINE_START(FLEXIBITY, "Flexibity Connect")
162 /* Maintainer: Maxim Osipov */ 164 /* Maintainer: Maxim Osipov */
163 .init_time = at91sam926x_pit_init, 165 .init_time = at91_init_time,
164 .map_io = at91_map_io, 166 .map_io = at91_map_io,
165 .handle_irq = at91_aic_handle_irq, 167 .handle_irq = at91_aic_handle_irq,
166 .init_early = flexibity_init_early, 168 .init_early = flexibity_init_early,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
deleted file mode 100644
index 8b22c60bb238..000000000000
--- a/arch/arm/mach-at91/board-foxg20.c
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2008 Atmel
4 * Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com
5 * Copyright (C) 2010 Sergio Tanzilli - tanzilli@acmesystems.it
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/at73c213.h>
29#include <linux/gpio.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/clk.h>
33#include <linux/w1-gpio.h>
34
35#include <mach/hardware.h>
36#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/irq.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43
44#include <mach/at91sam9_smc.h>
45
46#include "at91_aic.h"
47#include "board.h"
48#include "sam9_smc.h"
49#include "generic.h"
50#include "gpio.h"
51
52/*
53 * The FOX Board G20 hardware comes as the "Netus G20" board with
54 * just the cpu, ram, dataflash and two header connectors.
55 * This is plugged into the FOX Board which provides the ethernet,
56 * usb, rtc, leds, switch, ...
57 *
58 * For more info visit: http://www.acmesystems.it/foxg20
59 */
60
61
62static void __init foxg20_init_early(void)
63{
64 /* Initialize processor: 18.432 MHz crystal */
65 at91_initialize(18432000);
66}
67
68/*
69 * USB Host port
70 */
71static struct at91_usbh_data __initdata foxg20_usbh_data = {
72 .ports = 2,
73 .vbus_pin = {-EINVAL, -EINVAL},
74 .overcurrent_pin= {-EINVAL, -EINVAL},
75};
76
77/*
78 * USB Device port
79 */
80static struct at91_udc_data __initdata foxg20_udc_data = {
81 .vbus_pin = AT91_PIN_PC6,
82 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
83};
84
85
86/*
87 * SPI devices.
88 */
89static struct spi_board_info foxg20_spi_devices[] = {
90#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
91 {
92 .modalias = "mtd_dataflash",
93 .chip_select = 1,
94 .max_speed_hz = 15 * 1000 * 1000,
95 .bus_num = 0,
96 },
97#endif
98};
99
100
101/*
102 * MACB Ethernet device
103 */
104static struct macb_platform_data __initdata foxg20_macb_data = {
105 .phy_irq_pin = AT91_PIN_PA7,
106 .is_rmii = 1,
107};
108
109/*
110 * MCI (SD/MMC)
111 * det_pin, wp_pin and vcc_pin are not connected
112 */
113static struct mci_platform_data __initdata foxg20_mci0_data = {
114 .slot[1] = {
115 .bus_width = 4,
116 .detect_pin = -EINVAL,
117 .wp_pin = -EINVAL,
118 },
119};
120
121
122/*
123 * LEDs
124 */
125static struct gpio_led foxg20_leds[] = {
126 { /* user led, red */
127 .name = "user_led",
128 .gpio = AT91_PIN_PC7,
129 .active_low = 0,
130 .default_trigger = "heartbeat",
131 },
132};
133
134
135/*
136 * GPIO Buttons
137 */
138#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
139static struct gpio_keys_button foxg20_buttons[] = {
140 {
141 .gpio = AT91_PIN_PC4,
142 .code = BTN_1,
143 .desc = "Button 1",
144 .active_low = 1,
145 .wakeup = 1,
146 },
147};
148
149static struct gpio_keys_platform_data foxg20_button_data = {
150 .buttons = foxg20_buttons,
151 .nbuttons = ARRAY_SIZE(foxg20_buttons),
152};
153
154static struct platform_device foxg20_button_device = {
155 .name = "gpio-keys",
156 .id = -1,
157 .num_resources = 0,
158 .dev = {
159 .platform_data = &foxg20_button_data,
160 }
161};
162
163static void __init foxg20_add_device_buttons(void)
164{
165 at91_set_gpio_input(AT91_PIN_PC4, 1); /* btn1 */
166 at91_set_deglitch(AT91_PIN_PC4, 1);
167
168 platform_device_register(&foxg20_button_device);
169}
170#else
171static void __init foxg20_add_device_buttons(void) {}
172#endif
173
174
175#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
176static struct w1_gpio_platform_data w1_gpio_pdata = {
177 /* If you choose to use a pin other than PB16 it needs to be 3.3V */
178 .pin = AT91_PIN_PB16,
179 .is_open_drain = 1,
180 .ext_pullup_enable_pin = -EINVAL,
181};
182
183static struct platform_device w1_device = {
184 .name = "w1-gpio",
185 .id = -1,
186 .dev.platform_data = &w1_gpio_pdata,
187};
188
189static void __init at91_add_device_w1(void)
190{
191 at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
192 at91_set_multi_drive(w1_gpio_pdata.pin, 1);
193 platform_device_register(&w1_device);
194}
195
196#endif
197
198
199static struct i2c_board_info __initdata foxg20_i2c_devices[] = {
200 {
201 I2C_BOARD_INFO("24c512", 0x50),
202 },
203};
204
205
206static void __init foxg20_board_init(void)
207{
208 /* Serial */
209 /* DBGU on ttyS0. (Rx & Tx only) */
210 at91_register_uart(0, 0, 0);
211
212 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
213 at91_register_uart(AT91SAM9260_ID_US0, 1,
214 ATMEL_UART_CTS
215 | ATMEL_UART_RTS
216 | ATMEL_UART_DTR
217 | ATMEL_UART_DSR
218 | ATMEL_UART_DCD
219 | ATMEL_UART_RI);
220
221 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
222 at91_register_uart(AT91SAM9260_ID_US1, 2,
223 ATMEL_UART_CTS
224 | ATMEL_UART_RTS);
225
226 /* USART2 on ttyS3. (Rx & Tx only) */
227 at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
228
229 /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
230 at91_register_uart(AT91SAM9260_ID_US3, 4,
231 ATMEL_UART_CTS
232 | ATMEL_UART_RTS);
233
234 /* USART4 on ttyS5. (Rx & Tx only) */
235 at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
236
237 /* USART5 on ttyS6. (Rx & Tx only) */
238 at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
239
240 /* Set the internal pull-up resistor on DRXD */
241 at91_set_A_periph(AT91_PIN_PB14, 1);
242 at91_add_device_serial();
243 /* USB Host */
244 at91_add_device_usbh(&foxg20_usbh_data);
245 /* USB Device */
246 at91_add_device_udc(&foxg20_udc_data);
247 /* SPI */
248 at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices));
249 /* Ethernet */
250 at91_add_device_eth(&foxg20_macb_data);
251 /* MMC */
252 at91_add_device_mci(0, &foxg20_mci0_data);
253 /* I2C */
254 at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices));
255 /* LEDs */
256 at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds));
257 /* Push Buttons */
258 foxg20_add_device_buttons();
259#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
260 at91_add_device_w1();
261#endif
262}
263
264MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
265 /* Maintainer: Sergio Tanzilli */
266 .init_time = at91sam926x_pit_init,
267 .map_io = at91_map_io,
268 .handle_irq = at91_aic_handle_irq,
269 .init_early = foxg20_init_early,
270 .init_irq = at91_init_irq_default,
271 .init_machine = foxg20_board_init,
272MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index b729dd1271bf..bf5cc55c7db6 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -576,7 +576,7 @@ static void __init gsia18s_board_init(void)
576} 576}
577 577
578MACHINE_START(GSIA18S, "GS_IA18_S") 578MACHINE_START(GSIA18S, "GS_IA18_S")
579 .init_time = at91sam926x_pit_init, 579 .init_time = at91_init_time,
580 .map_io = at91_map_io, 580 .map_io = at91_map_io,
581 .handle_irq = at91_aic_handle_irq, 581 .handle_irq = at91_aic_handle_irq,
582 .init_early = gsia18s_init_early, 582 .init_early = gsia18s_init_early,
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index b48d95ec5152..9c26b94ce448 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -219,7 +219,7 @@ static void __init pcontrol_g20_board_init(void)
219 219
220MACHINE_START(PCONTROL_G20, "PControl G20") 220MACHINE_START(PCONTROL_G20, "PControl G20")
221 /* Maintainer: pgsellmann@portner-elektronik.at */ 221 /* Maintainer: pgsellmann@portner-elektronik.at */
222 .init_time = at91sam926x_pit_init, 222 .init_time = at91_init_time,
223 .map_io = at91_map_io, 223 .map_io = at91_map_io,
224 .handle_irq = at91_aic_handle_irq, 224 .handle_irq = at91_aic_handle_irq,
225 .init_early = pcontrol_g20_init_early, 225 .init_early = pcontrol_g20_init_early,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
deleted file mode 100644
index f28e8b74df4b..000000000000
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ /dev/null
@@ -1,232 +0,0 @@
1/*
2 * board-rsi-ews.c
3 *
4 * Copyright (C)
5 * 2005 SAN People,
6 * 2008-2011 R-S-I Elektrotechnik GmbH & Co. KG
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/mtd/physmap.h>
18
19#include <asm/setup.h>
20#include <asm/mach-types.h>
21#include <asm/irq.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <mach/hardware.h>
28
29#include <linux/gpio.h>
30
31#include "at91_aic.h"
32#include "board.h"
33#include "generic.h"
34#include "gpio.h"
35
36static void __init rsi_ews_init_early(void)
37{
38 /* Initialize processor: 18.432 MHz crystal */
39 at91_initialize(18432000);
40}
41
42/*
43 * Ethernet
44 */
45static struct macb_platform_data rsi_ews_eth_data __initdata = {
46 .phy_irq_pin = AT91_PIN_PC4,
47 .is_rmii = 1,
48};
49
50/*
51 * USB Host
52 */
53static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
54 .ports = 1,
55 .vbus_pin = {-EINVAL, -EINVAL},
56 .overcurrent_pin= {-EINVAL, -EINVAL},
57};
58
59/*
60 * SD/MC
61 */
62static struct mci_platform_data __initdata rsi_ews_mci0_data = {
63 .slot[0] = {
64 .bus_width = 4,
65 .detect_pin = AT91_PIN_PB27,
66 .wp_pin = AT91_PIN_PB29,
67 },
68};
69
70/*
71 * I2C
72 */
73static struct i2c_board_info rsi_ews_i2c_devices[] __initdata = {
74 {
75 I2C_BOARD_INFO("ds1337", 0x68),
76 },
77 {
78 I2C_BOARD_INFO("24c01", 0x50),
79 }
80};
81
82/*
83 * LEDs
84 */
85static struct gpio_led rsi_ews_leds[] = {
86 {
87 .name = "led0",
88 .gpio = AT91_PIN_PB6,
89 .active_low = 0,
90 },
91 {
92 .name = "led1",
93 .gpio = AT91_PIN_PB7,
94 .active_low = 0,
95 },
96 {
97 .name = "led2",
98 .gpio = AT91_PIN_PB8,
99 .active_low = 0,
100 },
101 {
102 .name = "led3",
103 .gpio = AT91_PIN_PB9,
104 .active_low = 0,
105 },
106};
107
108/*
109 * DataFlash
110 */
111static struct spi_board_info rsi_ews_spi_devices[] = {
112 { /* DataFlash chip 1*/
113 .modalias = "mtd_dataflash",
114 .chip_select = 0,
115 .max_speed_hz = 5 * 1000 * 1000,
116 },
117 { /* DataFlash chip 2*/
118 .modalias = "mtd_dataflash",
119 .chip_select = 1,
120 .max_speed_hz = 5 * 1000 * 1000,
121 },
122};
123
124/*
125 * NOR flash
126 */
127static struct mtd_partition rsiews_nor_partitions[] = {
128 {
129 .name = "boot",
130 .offset = 0,
131 .size = 3 * SZ_128K,
132 .mask_flags = MTD_WRITEABLE
133 },
134 {
135 .name = "kernel",
136 .offset = MTDPART_OFS_NXTBLK,
137 .size = SZ_2M - (3 * SZ_128K)
138 },
139 {
140 .name = "root",
141 .offset = MTDPART_OFS_NXTBLK,
142 .size = SZ_8M
143 },
144 {
145 .name = "kernelupd",
146 .offset = MTDPART_OFS_NXTBLK,
147 .size = 3 * SZ_512K,
148 .mask_flags = MTD_WRITEABLE
149 },
150 {
151 .name = "rootupd",
152 .offset = MTDPART_OFS_NXTBLK,
153 .size = 9 * SZ_512K,
154 .mask_flags = MTD_WRITEABLE
155 },
156};
157
158static struct physmap_flash_data rsiews_nor_data = {
159 .width = 2,
160 .parts = rsiews_nor_partitions,
161 .nr_parts = ARRAY_SIZE(rsiews_nor_partitions),
162};
163
164#define NOR_BASE AT91_CHIPSELECT_0
165#define NOR_SIZE SZ_16M
166
167static struct resource nor_flash_resources[] = {
168 {
169 .start = NOR_BASE,
170 .end = NOR_BASE + NOR_SIZE - 1,
171 .flags = IORESOURCE_MEM,
172 }
173};
174
175static struct platform_device rsiews_nor_flash = {
176 .name = "physmap-flash",
177 .id = 0,
178 .dev = {
179 .platform_data = &rsiews_nor_data,
180 },
181 .resource = nor_flash_resources,
182 .num_resources = ARRAY_SIZE(nor_flash_resources),
183};
184
185/*
186 * Init Func
187 */
188static void __init rsi_ews_board_init(void)
189{
190 /* Serial */
191 /* DBGU on ttyS0. (Rx & Tx only) */
192 /* This one is for debugging */
193 at91_register_uart(0, 0, 0);
194
195 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
196 /* Dialin/-out modem interface */
197 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
198 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
199 | ATMEL_UART_RI);
200
201 /* USART3 on ttyS4. (Rx, Tx, RTS) */
202 /* RS485 communication */
203 at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
204 at91_add_device_serial();
205 at91_set_gpio_output(AT91_PIN_PA21, 0);
206 /* Ethernet */
207 at91_add_device_eth(&rsi_ews_eth_data);
208 /* USB Host */
209 at91_add_device_usbh(&rsi_ews_usbh_data);
210 /* I2C */
211 at91_add_device_i2c(rsi_ews_i2c_devices,
212 ARRAY_SIZE(rsi_ews_i2c_devices));
213 /* SPI */
214 at91_add_device_spi(rsi_ews_spi_devices,
215 ARRAY_SIZE(rsi_ews_spi_devices));
216 /* MMC */
217 at91_add_device_mci(0, &rsi_ews_mci0_data);
218 /* NOR Flash */
219 platform_device_register(&rsiews_nor_flash);
220 /* LEDs */
221 at91_gpio_leds(rsi_ews_leds, ARRAY_SIZE(rsi_ews_leds));
222}
223
224MACHINE_START(RSI_EWS, "RSI EWS")
225 /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
226 .init_time = at91rm9200_timer_init,
227 .map_io = at91_map_io,
228 .handle_irq = at91_aic_handle_irq,
229 .init_early = rsi_ews_init_early,
230 .init_irq = at91_init_irq_default,
231 .init_machine = rsi_ews_board_init,
232MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index d24dda67e2d3..c2166e3a236c 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -187,6 +187,8 @@ static struct gpio_led ek_leds[] = {
187 187
188static void __init ek_board_init(void) 188static void __init ek_board_init(void)
189{ 189{
190 at91_register_devices();
191
190 /* Serial */ 192 /* Serial */
191 /* DBGU on ttyS0. (Rx & Tx only) */ 193 /* DBGU on ttyS0. (Rx & Tx only) */
192 at91_register_uart(0, 0, 0); 194 at91_register_uart(0, 0, 0);
@@ -219,7 +221,7 @@ static void __init ek_board_init(void)
219 221
220MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") 222MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
221 /* Maintainer: Olimex */ 223 /* Maintainer: Olimex */
222 .init_time = at91sam926x_pit_init, 224 .init_time = at91_init_time,
223 .map_io = at91_map_io, 225 .map_io = at91_map_io,
224 .handle_irq = at91_aic_handle_irq, 226 .handle_irq = at91_aic_handle_irq,
225 .init_early = ek_init_early, 227 .init_early = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 65dea12d685e..bf8a946b4cd0 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -45,7 +45,6 @@
45#include <mach/system_rev.h> 45#include <mach/system_rev.h>
46 46
47#include "at91_aic.h" 47#include "at91_aic.h"
48#include "at91_shdwc.h"
49#include "board.h" 48#include "board.h"
50#include "sam9_smc.h" 49#include "sam9_smc.h"
51#include "generic.h" 50#include "generic.h"
@@ -307,6 +306,8 @@ static void __init ek_add_device_buttons(void) {}
307 306
308static void __init ek_board_init(void) 307static void __init ek_board_init(void)
309{ 308{
309 at91_register_devices();
310
310 /* Serial */ 311 /* Serial */
311 /* DBGU on ttyS0. (Rx & Tx only) */ 312 /* DBGU on ttyS0. (Rx & Tx only) */
312 at91_register_uart(0, 0, 0); 313 at91_register_uart(0, 0, 0);
@@ -344,7 +345,7 @@ static void __init ek_board_init(void)
344 345
345MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") 346MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
346 /* Maintainer: Atmel */ 347 /* Maintainer: Atmel */
347 .init_time = at91sam926x_pit_init, 348 .init_time = at91_init_time,
348 .map_io = at91_map_io, 349 .map_io = at91_map_io,
349 .handle_irq = at91_aic_handle_irq, 350 .handle_irq = at91_aic_handle_irq,
350 .init_early = ek_init_early, 351 .init_early = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 4637432de08f..e85ada820bfb 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -49,7 +49,6 @@
49#include <mach/system_rev.h> 49#include <mach/system_rev.h>
50 50
51#include "at91_aic.h" 51#include "at91_aic.h"
52#include "at91_shdwc.h"
53#include "board.h" 52#include "board.h"
54#include "sam9_smc.h" 53#include "sam9_smc.h"
55#include "generic.h" 54#include "generic.h"
@@ -561,6 +560,8 @@ static struct gpio_led ek_leds[] = {
561 560
562static void __init ek_board_init(void) 561static void __init ek_board_init(void)
563{ 562{
563 at91_register_devices();
564
564 /* Serial */ 565 /* Serial */
565 /* DBGU on ttyS0. (Rx & Tx only) */ 566 /* DBGU on ttyS0. (Rx & Tx only) */
566 at91_register_uart(0, 0, 0); 567 at91_register_uart(0, 0, 0);
@@ -603,7 +604,7 @@ static void __init ek_board_init(void)
603 604
604MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") 605MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
605 /* Maintainer: Atmel */ 606 /* Maintainer: Atmel */
606 .init_time = at91sam926x_pit_init, 607 .init_time = at91_init_time,
607 .map_io = at91_map_io, 608 .map_io = at91_map_io,
608 .handle_irq = at91_aic_handle_irq, 609 .handle_irq = at91_aic_handle_irq,
609 .init_early = ek_init_early, 610 .init_early = ek_init_early,
@@ -613,7 +614,7 @@ MACHINE_END
613 614
614MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") 615MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
615 /* Maintainer: Atmel */ 616 /* Maintainer: Atmel */
616 .init_time = at91sam926x_pit_init, 617 .init_time = at91_init_time,
617 .map_io = at91_map_io, 618 .map_io = at91_map_io,
618 .handle_irq = at91_aic_handle_irq, 619 .handle_irq = at91_aic_handle_irq,
619 .init_early = ek_init_early, 620 .init_early = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index fc446097f410..d76680f2a209 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -50,7 +50,6 @@
50#include <mach/system_rev.h> 50#include <mach/system_rev.h>
51 51
52#include "at91_aic.h" 52#include "at91_aic.h"
53#include "at91_shdwc.h"
54#include "board.h" 53#include "board.h"
55#include "sam9_smc.h" 54#include "sam9_smc.h"
56#include "generic.h" 55#include "generic.h"
@@ -439,6 +438,8 @@ static struct platform_device *devices[] __initdata = {
439 438
440static void __init ek_board_init(void) 439static void __init ek_board_init(void)
441{ 440{
441 at91_register_devices();
442
442 /* Serial */ 443 /* Serial */
443 /* DBGU on ttyS0. (Rx & Tx only) */ 444 /* DBGU on ttyS0. (Rx & Tx only) */
444 at91_register_uart(0, 0, 0); 445 at91_register_uart(0, 0, 0);
@@ -483,7 +484,7 @@ static void __init ek_board_init(void)
483 484
484MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") 485MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
485 /* Maintainer: Atmel */ 486 /* Maintainer: Atmel */
486 .init_time = at91sam926x_pit_init, 487 .init_time = at91_init_time,
487 .map_io = at91_map_io, 488 .map_io = at91_map_io,
488 .handle_irq = at91_aic_handle_irq, 489 .handle_irq = at91_aic_handle_irq,
489 .init_early = ek_init_early, 490 .init_early = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index e1be6e25b380..49f075213451 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -410,7 +410,7 @@ static void __init ek_board_init(void)
410 410
411MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") 411MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
412 /* Maintainer: Atmel */ 412 /* Maintainer: Atmel */
413 .init_time = at91sam926x_pit_init, 413 .init_time = at91_init_time,
414 .map_io = at91_map_io, 414 .map_io = at91_map_io,
415 .handle_irq = at91_aic_handle_irq, 415 .handle_irq = at91_aic_handle_irq,
416 .init_early = ek_init_early, 416 .init_early = ek_init_early,
@@ -420,7 +420,7 @@ MACHINE_END
420 420
421MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") 421MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
422 /* Maintainer: Atmel */ 422 /* Maintainer: Atmel */
423 .init_time = at91sam926x_pit_init, 423 .init_time = at91_init_time,
424 .map_io = at91_map_io, 424 .map_io = at91_map_io,
425 .handle_irq = at91_aic_handle_irq, 425 .handle_irq = at91_aic_handle_irq,
426 .init_early = ek_init_early, 426 .init_early = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index b227732b0c83..a517c7f7af92 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -48,7 +48,6 @@
48#include <mach/system_rev.h> 48#include <mach/system_rev.h>
49 49
50#include "at91_aic.h" 50#include "at91_aic.h"
51#include "at91_shdwc.h"
52#include "board.h" 51#include "board.h"
53#include "sam9_smc.h" 52#include "sam9_smc.h"
54#include "generic.h" 53#include "generic.h"
@@ -471,6 +470,8 @@ static struct platform_device *devices[] __initdata = {
471 470
472static void __init ek_board_init(void) 471static void __init ek_board_init(void)
473{ 472{
473 at91_register_devices();
474
474 /* Serial */ 475 /* Serial */
475 /* DGBU on ttyS0. (Rx & Tx only) */ 476 /* DGBU on ttyS0. (Rx & Tx only) */
476 at91_register_uart(0, 0, 0); 477 at91_register_uart(0, 0, 0);
@@ -517,7 +518,7 @@ static void __init ek_board_init(void)
517 518
518MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") 519MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
519 /* Maintainer: Atmel */ 520 /* Maintainer: Atmel */
520 .init_time = at91sam926x_pit_init, 521 .init_time = at91_init_time,
521 .map_io = at91_map_io, 522 .map_io = at91_map_io,
522 .handle_irq = at91_aic_handle_irq, 523 .handle_irq = at91_aic_handle_irq,
523 .init_early = ek_init_early, 524 .init_early = ek_init_early,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index b64648b4a1fc..8bca329b0293 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -35,7 +35,6 @@
35 35
36 36
37#include "at91_aic.h" 37#include "at91_aic.h"
38#include "at91_shdwc.h"
39#include "board.h" 38#include "board.h"
40#include "sam9_smc.h" 39#include "sam9_smc.h"
41#include "generic.h" 40#include "generic.h"
@@ -292,6 +291,8 @@ static void __init ek_add_device_buttons(void) {}
292 291
293static void __init ek_board_init(void) 292static void __init ek_board_init(void)
294{ 293{
294 at91_register_devices();
295
295 /* Serial */ 296 /* Serial */
296 /* DBGU on ttyS0. (Rx & Tx only) */ 297 /* DBGU on ttyS0. (Rx & Tx only) */
297 at91_register_uart(0, 0, 0); 298 at91_register_uart(0, 0, 0);
@@ -323,7 +324,7 @@ static void __init ek_board_init(void)
323 324
324MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") 325MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
325 /* Maintainer: Atmel */ 326 /* Maintainer: Atmel */
326 .init_time = at91sam926x_pit_init, 327 .init_time = at91_init_time,
327 .map_io = at91_map_io, 328 .map_io = at91_map_io,
328 .handle_irq = at91_aic_handle_irq, 329 .handle_irq = at91_aic_handle_irq,
329 .init_early = ek_init_early, 330 .init_early = ek_init_early,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 1b870e6def0c..b4aff840a1a0 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -154,6 +154,8 @@ static void __init snapper9260_add_device_nand(void)
154 154
155static void __init snapper9260_board_init(void) 155static void __init snapper9260_board_init(void)
156{ 156{
157 at91_register_devices();
158
157 at91_add_device_i2c(snapper9260_i2c_devices, 159 at91_add_device_i2c(snapper9260_i2c_devices,
158 ARRAY_SIZE(snapper9260_i2c_devices)); 160 ARRAY_SIZE(snapper9260_i2c_devices));
159 161
@@ -178,7 +180,7 @@ static void __init snapper9260_board_init(void)
178} 180}
179 181
180MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") 182MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
181 .init_time = at91sam926x_pit_init, 183 .init_time = at91_init_time,
182 .map_io = at91_map_io, 184 .map_io = at91_map_io,
183 .handle_irq = at91_aic_handle_irq, 185 .handle_irq = at91_aic_handle_irq,
184 .init_early = snapper9260_init_early, 186 .init_early = snapper9260_init_early,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 3b575036ff96..e825641a1dee 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -275,7 +275,7 @@ static void __init stamp9g20evb_board_init(void)
275 275
276MACHINE_START(PORTUXG20, "taskit PortuxG20") 276MACHINE_START(PORTUXG20, "taskit PortuxG20")
277 /* Maintainer: taskit GmbH */ 277 /* Maintainer: taskit GmbH */
278 .init_time = at91sam926x_pit_init, 278 .init_time = at91_init_time,
279 .map_io = at91_map_io, 279 .map_io = at91_map_io,
280 .handle_irq = at91_aic_handle_irq, 280 .handle_irq = at91_aic_handle_irq,
281 .init_early = stamp9g20_init_early, 281 .init_early = stamp9g20_init_early,
@@ -285,7 +285,7 @@ MACHINE_END
285 285
286MACHINE_START(STAMP9G20, "taskit Stamp9G20") 286MACHINE_START(STAMP9G20, "taskit Stamp9G20")
287 /* Maintainer: taskit GmbH */ 287 /* Maintainer: taskit GmbH */
288 .init_time = at91sam926x_pit_init, 288 .init_time = at91_init_time,
289 .map_io = at91_map_io, 289 .map_io = at91_map_io,
290 .handle_irq = at91_aic_handle_irq, 290 .handle_irq = at91_aic_handle_irq,
291 .init_early = stamp9g20_init_early, 291 .init_early = stamp9g20_init_early,
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 034529d801b2..d66f102c352a 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -962,6 +962,7 @@ static int __init at91_clock_reset(void)
962 } 962 }
963 963
964 at91_pmc_write(AT91_PMC_SCDR, scdr); 964 at91_pmc_write(AT91_PMC_SCDR, scdr);
965 at91_pmc_write(AT91_PMC_PCDR, pcdr);
965 if (cpu_is_sama5d3()) 966 if (cpu_is_sama5d3())
966 at91_pmc_write(AT91_PMC_PCDR1, pcdr1); 967 at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
967 968
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 631fa3b8c16d..81959cf4a137 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -8,12 +8,16 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef _AT91_GENERIC_H
12#define _AT91_GENERIC_H
13
11#include <linux/clkdev.h> 14#include <linux/clkdev.h>
12#include <linux/of.h> 15#include <linux/of.h>
13#include <linux/reboot.h> 16#include <linux/reboot.h>
14 17
15 /* Map io */ 18 /* Map io */
16extern void __init at91_map_io(void); 19extern void __init at91_map_io(void);
20extern void __init at91_alt_map_io(void);
17extern void __init at91_init_sram(int bank, unsigned long base, 21extern void __init at91_init_sram(int bank, unsigned long base,
18 unsigned int length); 22 unsigned int length);
19 23
@@ -37,12 +41,15 @@ extern int __init at91_aic5_of_init(struct device_node *node,
37extern void __init at91_sysirq_mask_rtc(u32 rtc_base); 41extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
38extern void __init at91_sysirq_mask_rtt(u32 rtt_base); 42extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
39 43
44 /* Devices */
45extern void __init at91_register_devices(void);
40 46
41 /* Timer */ 47 /* Timer */
48extern void __init at91_init_time(void);
42extern void at91rm9200_ioremap_st(u32 addr); 49extern void at91rm9200_ioremap_st(u32 addr);
43extern void at91rm9200_timer_init(void); 50extern void at91rm9200_timer_init(void);
44extern void at91sam926x_ioremap_pit(u32 addr); 51extern void at91sam926x_ioremap_pit(u32 addr);
45extern void at91sam926x_pit_init(void); 52extern void at91sam926x_pit_init(int irq);
46extern void at91x40_timer_init(void); 53extern void at91x40_timer_init(void);
47 54
48 /* Clocks */ 55 /* Clocks */
@@ -62,14 +69,6 @@ extern void at91_irq_resume(void);
62/* idle */ 69/* idle */
63extern void at91sam9_idle(void); 70extern void at91sam9_idle(void);
64 71
65/* reset */
66extern void at91_ioremap_rstc(u32 base_addr);
67extern void at91sam9_alt_restart(enum reboot_mode, const char *);
68extern void at91sam9g45_restart(enum reboot_mode, const char *);
69
70/* shutdown */
71extern void at91_ioremap_shdwc(u32 base_addr);
72
73/* Matrix */ 72/* Matrix */
74extern void at91_ioremap_matrix(u32 base_addr); 73extern void at91_ioremap_matrix(u32 base_addr);
75 74
@@ -90,3 +89,5 @@ extern int __init at91_gpio_of_irq_setup(struct device_node *node,
90 struct device_node *parent); 89 struct device_node *parent);
91 90
92extern u32 at91_get_extern_irq(void); 91extern u32 at91_get_extern_irq(void);
92
93#endif /* _AT91_GENERIC_H */
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index 732b11c37f1a..7b7366253ceb 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -71,4 +71,10 @@
71#define ABCDSR_PERIPH_C 0x2 71#define ABCDSR_PERIPH_C 0x2
72#define ABCDSR_PERIPH_D 0x3 72#define ABCDSR_PERIPH_D 0x3
73 73
74#define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
75#define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
76
77#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
78#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
79
74#endif 80#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 86c71debab5b..b27e9ca65653 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -36,7 +36,7 @@
36#define ARCH_ID_AT91M40807 0x14080745 36#define ARCH_ID_AT91M40807 0x14080745
37#define ARCH_ID_AT91R40008 0x44000840 37#define ARCH_ID_AT91R40008 0x44000840
38 38
39#define ARCH_ID_SAMA5D3 0x8A5C07C0 39#define ARCH_ID_SAMA5 0x8A5C07C0
40 40
41#define ARCH_EXID_AT91SAM9M11 0x00000001 41#define ARCH_EXID_AT91SAM9M11 0x00000001
42#define ARCH_EXID_AT91SAM9M10 0x00000002 42#define ARCH_EXID_AT91SAM9M10 0x00000002
@@ -49,12 +49,19 @@
49#define ARCH_EXID_AT91SAM9G25 0x00000003 49#define ARCH_EXID_AT91SAM9G25 0x00000003
50#define ARCH_EXID_AT91SAM9X25 0x00000004 50#define ARCH_EXID_AT91SAM9X25 0x00000004
51 51
52#define ARCH_EXID_SAMA5D3 0x00004300
52#define ARCH_EXID_SAMA5D31 0x00444300 53#define ARCH_EXID_SAMA5D31 0x00444300
53#define ARCH_EXID_SAMA5D33 0x00414300 54#define ARCH_EXID_SAMA5D33 0x00414300
54#define ARCH_EXID_SAMA5D34 0x00414301 55#define ARCH_EXID_SAMA5D34 0x00414301
55#define ARCH_EXID_SAMA5D35 0x00584300 56#define ARCH_EXID_SAMA5D35 0x00584300
56#define ARCH_EXID_SAMA5D36 0x00004301 57#define ARCH_EXID_SAMA5D36 0x00004301
57 58
59#define ARCH_EXID_SAMA5D4 0x00000007
60#define ARCH_EXID_SAMA5D41 0x00000001
61#define ARCH_EXID_SAMA5D42 0x00000002
62#define ARCH_EXID_SAMA5D43 0x00000003
63#define ARCH_EXID_SAMA5D44 0x00000004
64
58#define ARCH_FAMILY_AT91X92 0x09200000 65#define ARCH_FAMILY_AT91X92 0x09200000
59#define ARCH_FAMILY_AT91SAM9 0x01900000 66#define ARCH_FAMILY_AT91SAM9 0x01900000
60#define ARCH_FAMILY_AT91SAM9XE 0x02900000 67#define ARCH_FAMILY_AT91SAM9XE 0x02900000
@@ -86,6 +93,9 @@ enum at91_soc_type {
86 /* SAMA5D3 */ 93 /* SAMA5D3 */
87 AT91_SOC_SAMA5D3, 94 AT91_SOC_SAMA5D3,
88 95
96 /* SAMA5D4 */
97 AT91_SOC_SAMA5D4,
98
89 /* Unknown type */ 99 /* Unknown type */
90 AT91_SOC_UNKNOWN, 100 AT91_SOC_UNKNOWN,
91}; 101};
@@ -108,6 +118,10 @@ enum at91_soc_subtype {
108 AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, 118 AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
109 AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, 119 AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
110 120
121 /* SAMA5D4 */
122 AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
123 AT91_SOC_SAMA5D44,
124
111 /* No subtype for this SoC */ 125 /* No subtype for this SoC */
112 AT91_SOC_SUBTYPE_NONE, 126 AT91_SOC_SUBTYPE_NONE,
113 127
@@ -211,6 +225,12 @@ static inline int at91_soc_is_detected(void)
211#define cpu_is_sama5d3() (0) 225#define cpu_is_sama5d3() (0)
212#endif 226#endif
213 227
228#ifdef CONFIG_SOC_SAMA5D4
229#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
230#else
231#define cpu_is_sama5d4() (0)
232#endif
233
214/* 234/*
215 * Since this is ARM, we will never run on any AVR32 CPU. But these 235 * Since this is ARM, we will never run on any AVR32 CPU. But these
216 * definitions may reduce clutter in common drivers. 236 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index c6bb9e2d9baa..2103a90f2261 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -16,8 +16,11 @@
16 16
17#if defined(CONFIG_AT91_DEBUG_LL_DBGU0) 17#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
18#define AT91_DBGU AT91_BASE_DBGU0 18#define AT91_DBGU AT91_BASE_DBGU0
19#else 19#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
20#define AT91_DBGU AT91_BASE_DBGU1 20#define AT91_DBGU AT91_BASE_DBGU1
21#else
22/* On sama5d4, use USART3 as low level serial console */
23#define AT91_DBGU SAMA5D4_BASE_USART3
21#endif 24#endif
22 25
23 .macro addruart, rp, rv, tmp 26 .macro addruart, rp, rv, tmp
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 56338245653a..c13797352688 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,8 +19,10 @@
19/* DBGU base */ 19/* DBGU base */
20/* rm9200, 9260/9g20, 9261/9g10, 9rl */ 20/* rm9200, 9260/9g20, 9261/9g10, 9rl */
21#define AT91_BASE_DBGU0 0xfffff200 21#define AT91_BASE_DBGU0 0xfffff200
22/* 9263, 9g45 */ 22/* 9263, 9g45, sama5d3 */
23#define AT91_BASE_DBGU1 0xffffee00 23#define AT91_BASE_DBGU1 0xffffee00
24/* sama5d4 */
25#define AT91_BASE_DBGU2 0xfc069000
24 26
25#if defined(CONFIG_ARCH_AT91X40) 27#if defined(CONFIG_ARCH_AT91X40)
26#include <mach/at91x40.h> 28#include <mach/at91x40.h>
@@ -34,6 +36,7 @@
34#include <mach/at91sam9x5.h> 36#include <mach/at91sam9x5.h>
35#include <mach/at91sam9n12.h> 37#include <mach/at91sam9n12.h>
36#include <mach/sama5d3.h> 38#include <mach/sama5d3.h>
39#include <mach/sama5d4.h>
37 40
38/* 41/*
39 * On all at91 except rm9200 and x40 have the System Controller starts 42 * On all at91 except rm9200 and x40 have the System Controller starts
@@ -47,9 +50,15 @@
47 * and map the same memory space 50 * and map the same memory space
48 */ 51 */
49#define AT91_BASE_SYS 0xffffc000 52#define AT91_BASE_SYS 0xffffc000
53
50#endif 54#endif
51 55
52/* 56/*
57 * On sama5d4 there is no system controller, we map some needed peripherals
58 */
59#define AT91_ALT_BASE_SYS 0xfc069000
60
61/*
53 * On all at91 have the Advanced Interrupt Controller starts at address 62 * On all at91 have the Advanced Interrupt Controller starts at address
54 * 0xfffff000 and the Power Management Controller starts at 0xfffffc00 63 * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
55 */ 64 */
@@ -69,23 +78,35 @@
69 */ 78 */
70#define AT91_IO_PHYS_BASE 0xFFF78000 79#define AT91_IO_PHYS_BASE 0xFFF78000
71#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) 80#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
81
82/*
83 * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
84 * to 0xFB069000 .. 0xFB06F000. (24Kb)
85 */
86#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
87#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000)
72#else 88#else
73/* 89/*
74 * Identity mapping for the non MMU case. 90 * Identity mapping for the non MMU case.
75 */ 91 */
76#define AT91_IO_PHYS_BASE AT91_BASE_SYS 92#define AT91_IO_PHYS_BASE AT91_BASE_SYS
77#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE) 93#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE)
94
95#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
96#define AT91_ALT_IO_VIRT_BASE IOMEM(AT91_ALT_BASE_SYS)
78#endif 97#endif
79 98
80#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) 99#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
81 100
82 /* Convert a physical IO address to virtual IO address */ 101 /* Convert a physical IO address to virtual IO address */
83#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) 102#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
103#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
84 104
85/* 105/*
86 * Virtual to Physical Address mapping for IO devices. 106 * Virtual to Physical Address mapping for IO devices.
87 */ 107 */
88#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) 108#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
109#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
89 110
90 /* Internal SRAM is mapped below the IO devices */ 111 /* Internal SRAM is mapped below the IO devices */
91#define AT91_SRAM_MAX SZ_1M 112#define AT91_SRAM_MAX SZ_1M
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
new file mode 100644
index 000000000000..f256a45d9854
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -0,0 +1,33 @@
1/*
2 * Chip-specific header file for the SAMA5D4 family
3 *
4 * Copyright (C) 2013 Atmel Corporation,
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Common definitions.
8 * Based on SAMA5D4 datasheet.
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13#ifndef SAMA5D4_H
14#define SAMA5D4_H
15
16/*
17 * User Peripheral physical base addresses.
18 */
19#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */
20#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */
21#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */
22#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
23
24/* Some other peripherals */
25#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD
26
27/*
28 * Internal Memory.
29 */
30#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */
31#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */
32
33#endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 4bb644f8e87c..acb2d890ad7e 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
94 0, 94 0,
95}; 95};
96 96
97static const u32 uarts_sama5[] = { 97static const u32 uarts_sama5d3[] = {
98 AT91_BASE_DBGU1, 98 AT91_BASE_DBGU1,
99 SAMA5D3_BASE_USART0, 99 SAMA5D3_BASE_USART0,
100 SAMA5D3_BASE_USART1, 100 SAMA5D3_BASE_USART1,
@@ -103,6 +103,12 @@ static const u32 uarts_sama5[] = {
103 0, 103 0,
104}; 104};
105 105
106static const u32 uarts_sama5d4[] = {
107 AT91_BASE_DBGU2,
108 SAMA5D4_BASE_USART3,
109 0,
110};
111
106static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) 112static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
107{ 113{
108 u32 cidr, socid; 114 u32 cidr, socid;
@@ -134,8 +140,14 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
134 case ARCH_ID_AT91SAM9X5: 140 case ARCH_ID_AT91SAM9X5:
135 return uarts_sam9x5; 141 return uarts_sam9x5;
136 142
137 case ARCH_ID_SAMA5D3: 143 case ARCH_ID_SAMA5:
138 return uarts_sama5; 144 cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
145 if (cidr & ARCH_EXID_SAMA5D3)
146 return uarts_sama5d3;
147 else if (cidr & ARCH_EXID_SAMA5D4)
148 return uarts_sama5d4;
149
150 break;
139 } 151 }
140 152
141 /* at91sam9g10 */ 153 /* at91sam9g10 */
@@ -156,9 +168,10 @@ static inline void arch_decomp_setup(void)
156 const u32* usarts; 168 const u32* usarts;
157 169
158 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); 170 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
159
160 if (!usarts) 171 if (!usarts)
161 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); 172 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
173 if (!usarts)
174 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
162 if (!usarts) { 175 if (!usarts) {
163 at91_uart = NULL; 176 at91_uart = NULL;
164 return; 177 return;
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 3d192c5aee66..cdb3ec9efd2b 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -48,11 +48,6 @@ void __iomem *at91_aic_base;
48static struct irq_domain *at91_aic_domain; 48static struct irq_domain *at91_aic_domain;
49static struct device_node *at91_aic_np; 49static struct device_node *at91_aic_np;
50static unsigned int n_irqs = NR_AIC_IRQS; 50static unsigned int n_irqs = NR_AIC_IRQS;
51static unsigned long at91_aic_caps = 0;
52
53/* AIC5 introduces a Source Select Register */
54#define AT91_AIC_CAP_AIC5 (1 << 0)
55#define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5)
56 51
57#ifdef CONFIG_PM 52#ifdef CONFIG_PM
58 53
@@ -92,50 +87,14 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
92 87
93void at91_irq_suspend(void) 88void at91_irq_suspend(void)
94{ 89{
95 int bit = -1; 90 at91_aic_write(AT91_AIC_IDCR, *backups);
96 91 at91_aic_write(AT91_AIC_IECR, *wakeups);
97 if (has_aic5()) {
98 /* disable enabled irqs */
99 while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
100 at91_aic_write(AT91_AIC5_SSR,
101 bit & AT91_AIC5_INTSEL_MSK);
102 at91_aic_write(AT91_AIC5_IDCR, 1);
103 }
104 /* enable wakeup irqs */
105 bit = -1;
106 while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
107 at91_aic_write(AT91_AIC5_SSR,
108 bit & AT91_AIC5_INTSEL_MSK);
109 at91_aic_write(AT91_AIC5_IECR, 1);
110 }
111 } else {
112 at91_aic_write(AT91_AIC_IDCR, *backups);
113 at91_aic_write(AT91_AIC_IECR, *wakeups);
114 }
115} 92}
116 93
117void at91_irq_resume(void) 94void at91_irq_resume(void)
118{ 95{
119 int bit = -1; 96 at91_aic_write(AT91_AIC_IDCR, *wakeups);
120 97 at91_aic_write(AT91_AIC_IECR, *backups);
121 if (has_aic5()) {
122 /* disable wakeup irqs */
123 while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
124 at91_aic_write(AT91_AIC5_SSR,
125 bit & AT91_AIC5_INTSEL_MSK);
126 at91_aic_write(AT91_AIC5_IDCR, 1);
127 }
128 /* enable irqs disabled for suspend */
129 bit = -1;
130 while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
131 at91_aic_write(AT91_AIC5_SSR,
132 bit & AT91_AIC5_INTSEL_MSK);
133 at91_aic_write(AT91_AIC5_IECR, 1);
134 }
135 } else {
136 at91_aic_write(AT91_AIC_IDCR, *wakeups);
137 at91_aic_write(AT91_AIC_IECR, *backups);
138 }
139} 98}
140 99
141#else 100#else
@@ -169,21 +128,6 @@ at91_aic_handle_irq(struct pt_regs *regs)
169 handle_IRQ(irqnr, regs); 128 handle_IRQ(irqnr, regs);
170} 129}
171 130
172asmlinkage void __exception_irq_entry
173at91_aic5_handle_irq(struct pt_regs *regs)
174{
175 u32 irqnr;
176 u32 irqstat;
177
178 irqnr = at91_aic_read(AT91_AIC5_IVR);
179 irqstat = at91_aic_read(AT91_AIC5_ISR);
180
181 if (!irqstat)
182 at91_aic_write(AT91_AIC5_EOICR, 0);
183 else
184 handle_IRQ(irqnr, regs);
185}
186
187static void at91_aic_mask_irq(struct irq_data *d) 131static void at91_aic_mask_irq(struct irq_data *d)
188{ 132{
189 /* Disable interrupt on AIC */ 133 /* Disable interrupt on AIC */
@@ -192,15 +136,6 @@ static void at91_aic_mask_irq(struct irq_data *d)
192 clear_backup(d->hwirq); 136 clear_backup(d->hwirq);
193} 137}
194 138
195static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
196{
197 /* Disable interrupt on AIC5 */
198 at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
199 at91_aic_write(AT91_AIC5_IDCR, 1);
200 /* Update ISR cache */
201 clear_backup(d->hwirq);
202}
203
204static void at91_aic_unmask_irq(struct irq_data *d) 139static void at91_aic_unmask_irq(struct irq_data *d)
205{ 140{
206 /* Enable interrupt on AIC */ 141 /* Enable interrupt on AIC */
@@ -209,15 +144,6 @@ static void at91_aic_unmask_irq(struct irq_data *d)
209 set_backup(d->hwirq); 144 set_backup(d->hwirq);
210} 145}
211 146
212static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
213{
214 /* Enable interrupt on AIC5 */
215 at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
216 at91_aic_write(AT91_AIC5_IECR, 1);
217 /* Update ISR cache */
218 set_backup(d->hwirq);
219}
220
221static void at91_aic_eoi(struct irq_data *d) 147static void at91_aic_eoi(struct irq_data *d)
222{ 148{
223 /* 149 /*
@@ -227,11 +153,6 @@ static void at91_aic_eoi(struct irq_data *d)
227 at91_aic_write(AT91_AIC_EOICR, 0); 153 at91_aic_write(AT91_AIC_EOICR, 0);
228} 154}
229 155
230static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
231{
232 at91_aic_write(AT91_AIC5_EOICR, 0);
233}
234
235static unsigned long *at91_extern_irq; 156static unsigned long *at91_extern_irq;
236 157
237u32 at91_get_extern_irq(void) 158u32 at91_get_extern_irq(void)
@@ -282,16 +203,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
282 if (srctype < 0) 203 if (srctype < 0)
283 return srctype; 204 return srctype;
284 205
285 if (has_aic5()) { 206 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
286 at91_aic_write(AT91_AIC5_SSR, 207 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
287 d->hwirq & AT91_AIC5_INTSEL_MSK);
288 smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
289 at91_aic_write(AT91_AIC5_SMR, smr | srctype);
290 } else {
291 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
292 & ~AT91_AIC_SRCTYPE;
293 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
294 }
295 208
296 return 0; 209 return 0;
297} 210}
@@ -331,177 +244,6 @@ static void __init at91_aic_hw_init(unsigned int spu_vector)
331 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); 244 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
332} 245}
333 246
334static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
335{
336 int i;
337
338 /*
339 * Perform 8 End Of Interrupt Command to make sure AIC
340 * will not Lock out nIRQ
341 */
342 for (i = 0; i < 8; i++)
343 at91_aic_write(AT91_AIC5_EOICR, 0);
344
345 /*
346 * Spurious Interrupt ID in Spurious Vector Register.
347 * When there is no current interrupt, the IRQ Vector Register
348 * reads the value stored in AIC_SPU
349 */
350 at91_aic_write(AT91_AIC5_SPU, spu_vector);
351
352 /* No debugging in AIC: Debug (Protect) Control Register */
353 at91_aic_write(AT91_AIC5_DCR, 0);
354
355 /* Disable and clear all interrupts initially */
356 for (i = 0; i < n_irqs; i++) {
357 at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
358 at91_aic_write(AT91_AIC5_IDCR, 1);
359 at91_aic_write(AT91_AIC5_ICCR, 1);
360 }
361}
362
363#if defined(CONFIG_OF)
364static unsigned int *at91_aic_irq_priorities;
365
366static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
367 irq_hw_number_t hw)
368{
369 /* Put virq number in Source Vector Register */
370 at91_aic_write(AT91_AIC_SVR(hw), virq);
371
372 /* Active Low interrupt, with priority */
373 at91_aic_write(AT91_AIC_SMR(hw),
374 AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
375
376 irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
377 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
378
379 return 0;
380}
381
382static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
383 irq_hw_number_t hw)
384{
385 at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
386
387 /* Put virq number in Source Vector Register */
388 at91_aic_write(AT91_AIC5_SVR, virq);
389
390 /* Active Low interrupt, with priority */
391 at91_aic_write(AT91_AIC5_SMR,
392 AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
393
394 irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
395 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
396
397 return 0;
398}
399
400static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
401 const u32 *intspec, unsigned int intsize,
402 irq_hw_number_t *out_hwirq, unsigned int *out_type)
403{
404 if (WARN_ON(intsize < 3))
405 return -EINVAL;
406 if (WARN_ON(intspec[0] >= n_irqs))
407 return -EINVAL;
408 if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
409 || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
410 return -EINVAL;
411
412 *out_hwirq = intspec[0];
413 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
414 at91_aic_irq_priorities[*out_hwirq] = intspec[2];
415
416 return 0;
417}
418
419static struct irq_domain_ops at91_aic_irq_ops = {
420 .map = at91_aic_irq_map,
421 .xlate = at91_aic_irq_domain_xlate,
422};
423
424int __init at91_aic_of_common_init(struct device_node *node,
425 struct device_node *parent)
426{
427 struct property *prop;
428 const __be32 *p;
429 u32 val;
430
431 at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
432 * sizeof(*at91_extern_irq), GFP_KERNEL);
433 if (!at91_extern_irq)
434 return -ENOMEM;
435
436 if (at91_aic_pm_init()) {
437 kfree(at91_extern_irq);
438 return -ENOMEM;
439 }
440
441 at91_aic_irq_priorities = kzalloc(n_irqs
442 * sizeof(*at91_aic_irq_priorities),
443 GFP_KERNEL);
444 if (!at91_aic_irq_priorities)
445 return -ENOMEM;
446
447 at91_aic_base = of_iomap(node, 0);
448 at91_aic_np = node;
449
450 at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
451 &at91_aic_irq_ops, NULL);
452 if (!at91_aic_domain)
453 panic("Unable to add AIC irq domain (DT)\n");
454
455 of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
456 if (val >= n_irqs)
457 pr_warn("AIC: external irq %d >= %d skip it\n",
458 val, n_irqs);
459 else
460 set_bit(val, at91_extern_irq);
461 }
462
463 irq_set_default_host(at91_aic_domain);
464
465 return 0;
466}
467
468int __init at91_aic_of_init(struct device_node *node,
469 struct device_node *parent)
470{
471 int err;
472
473 err = at91_aic_of_common_init(node, parent);
474 if (err)
475 return err;
476
477 at91_aic_hw_init(n_irqs);
478
479 return 0;
480}
481
482int __init at91_aic5_of_init(struct device_node *node,
483 struct device_node *parent)
484{
485 int err;
486
487 at91_aic_caps |= AT91_AIC_CAP_AIC5;
488 n_irqs = NR_AIC5_IRQS;
489 at91_aic_chip.irq_ack = at91_aic5_mask_irq;
490 at91_aic_chip.irq_mask = at91_aic5_mask_irq;
491 at91_aic_chip.irq_unmask = at91_aic5_unmask_irq;
492 at91_aic_chip.irq_eoi = at91_aic5_eoi;
493 at91_aic_irq_ops.map = at91_aic5_irq_map;
494
495 err = at91_aic_of_common_init(node, parent);
496 if (err)
497 return err;
498
499 at91_aic5_hw_init(n_irqs);
500
501 return 0;
502}
503#endif
504
505/* 247/*
506 * Initialize the AIC interrupt controller. 248 * Initialize the AIC interrupt controller.
507 */ 249 */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e95554532987..4073ab7f38f3 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -34,79 +34,8 @@
34#include "pm.h" 34#include "pm.h"
35#include "gpio.h" 35#include "gpio.h"
36 36
37/*
38 * Show the reason for the previous system reset.
39 */
40
41#include "at91_rstc.h"
42#include "at91_shdwc.h"
43
44static void (*at91_pm_standby)(void); 37static void (*at91_pm_standby)(void);
45 38
46static void __init show_reset_status(void)
47{
48 static char reset[] __initdata = "reset";
49
50 static char general[] __initdata = "general";
51 static char wakeup[] __initdata = "wakeup";
52 static char watchdog[] __initdata = "watchdog";
53 static char software[] __initdata = "software";
54 static char user[] __initdata = "user";
55 static char unknown[] __initdata = "unknown";
56
57 static char signal[] __initdata = "signal";
58 static char rtc[] __initdata = "rtc";
59 static char rtt[] __initdata = "rtt";
60 static char restore[] __initdata = "power-restored";
61
62 char *reason, *r2 = reset;
63 u32 reset_type, wake_type;
64
65 if (!at91_shdwc_base || !at91_rstc_base)
66 return;
67
68 reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
69 wake_type = at91_shdwc_read(AT91_SHDW_SR);
70
71 switch (reset_type) {
72 case AT91_RSTC_RSTTYP_GENERAL:
73 reason = general;
74 break;
75 case AT91_RSTC_RSTTYP_WAKEUP:
76 /* board-specific code enabled the wakeup sources */
77 reason = wakeup;
78
79 /* "wakeup signal" */
80 if (wake_type & AT91_SHDW_WAKEUP0)
81 r2 = signal;
82 else {
83 r2 = reason;
84 if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */
85 reason = rtt;
86 else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */
87 reason = rtc;
88 else if (wake_type == 0) /* power-restored wakeup */
89 reason = restore;
90 else /* unknown wakeup */
91 reason = unknown;
92 }
93 break;
94 case AT91_RSTC_RSTTYP_WATCHDOG:
95 reason = watchdog;
96 break;
97 case AT91_RSTC_RSTTYP_SOFTWARE:
98 reason = software;
99 break;
100 case AT91_RSTC_RSTTYP_USER:
101 reason = user;
102 break;
103 default:
104 reason = unknown;
105 break;
106 }
107 pr_info("AT91: Starting after %s %s\n", reason, r2);
108}
109
110static int at91_pm_valid_state(suspend_state_t state) 39static int at91_pm_valid_state(suspend_state_t state)
111{ 40{
112 switch (state) { 41 switch (state) {
@@ -206,16 +135,19 @@ static int at91_pm_enter(suspend_state_t state)
206 at91_pinctrl_gpio_suspend(); 135 at91_pinctrl_gpio_suspend();
207 else 136 else
208 at91_gpio_suspend(); 137 at91_gpio_suspend();
209 at91_irq_suspend();
210 138
211 pr_debug("AT91: PM - wake mask %08x, pm state %d\n", 139 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
212 /* remember all the always-wake irqs */ 140 at91_irq_suspend();
213 (at91_pmc_read(AT91_PMC_PCSR) 141
214 | (1 << AT91_ID_FIQ) 142 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
215 | (1 << AT91_ID_SYS) 143 /* remember all the always-wake irqs */
216 | (at91_get_extern_irq())) 144 (at91_pmc_read(AT91_PMC_PCSR)
217 & at91_aic_read(AT91_AIC_IMR), 145 | (1 << AT91_ID_FIQ)
218 state); 146 | (1 << AT91_ID_SYS)
147 | (at91_get_extern_irq()))
148 & at91_aic_read(AT91_AIC_IMR),
149 state);
150 }
219 151
220 switch (state) { 152 switch (state) {
221 /* 153 /*
@@ -280,12 +212,17 @@ static int at91_pm_enter(suspend_state_t state)
280 goto error; 212 goto error;
281 } 213 }
282 214
283 pr_debug("AT91: PM - wakeup %08x\n", 215 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
284 at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR)); 216 pr_debug("AT91: PM - wakeup %08x\n",
217 at91_aic_read(AT91_AIC_IPR) &
218 at91_aic_read(AT91_AIC_IMR));
285 219
286error: 220error:
287 target_state = PM_SUSPEND_ON; 221 target_state = PM_SUSPEND_ON;
288 at91_irq_resume(); 222
223 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
224 at91_irq_resume();
225
289 if (of_have_populated_dt()) 226 if (of_have_populated_dt())
290 at91_pinctrl_gpio_resume(); 227 at91_pinctrl_gpio_resume();
291 else 228 else
@@ -338,7 +275,6 @@ static int __init at91_pm_init(void)
338 275
339 suspend_set_ops(&at91_pm_ops); 276 suspend_set_ops(&at91_pm_ops);
340 277
341 show_reset_status();
342 return 0; 278 return 0;
343} 279}
344arch_initcall(at91_pm_init); 280arch_initcall(at91_pm_init);
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
new file mode 100644
index 000000000000..7638509639f4
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -0,0 +1,64 @@
1/*
2 * Chip-specific setup code for the SAMA5D4 family
3 *
4 * Copyright (C) 2013 Atmel Corporation,
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/dma-mapping.h>
12#include <linux/clk/at91_pmc.h>
13
14#include <asm/irq.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <mach/sama5d4.h>
18#include <mach/cpu.h>
19#include <mach/hardware.h>
20
21#include "soc.h"
22#include "generic.h"
23#include "sam9_smc.h"
24
25/* --------------------------------------------------------------------
26 * Processor initialization
27 * -------------------------------------------------------------------- */
28static struct map_desc at91_io_desc[] __initdata = {
29 {
30 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
31 .pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
32 .length = SZ_512,
33 .type = MT_DEVICE,
34 },
35 {
36 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
37 .pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
38 .length = SZ_512,
39 .type = MT_DEVICE,
40 },
41 { /* On sama5d4, we use USART3 as serial console */
42 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
43 .pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
44 .length = SZ_256,
45 .type = MT_DEVICE,
46 },
47 { /* A bunch of peripheral with fine grained IO space */
48 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
49 .pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
50 .length = SZ_2K,
51 .type = MT_DEVICE,
52 },
53};
54
55
56static void __init sama5d4_map_io(void)
57{
58 iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
59 at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
60}
61
62AT91_SOC_START(sama5d4)
63 .map_io = sama5d4_map_io,
64AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f7a07a58ebb6..961079250b83 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -5,6 +5,8 @@
5 * Under GPLv2 5 * Under GPLv2
6 */ 6 */
7 7
8#define pr_fmt(fmt) "AT91: " fmt
9
8#include <linux/module.h> 10#include <linux/module.h>
9#include <linux/io.h> 11#include <linux/io.h>
10#include <linux/mm.h> 12#include <linux/mm.h>
@@ -20,7 +22,6 @@
20#include <mach/cpu.h> 22#include <mach/cpu.h>
21#include <mach/at91_dbgu.h> 23#include <mach/at91_dbgu.h>
22 24
23#include "at91_shdwc.h"
24#include "soc.h" 25#include "soc.h"
25#include "generic.h" 26#include "generic.h"
26#include "pm.h" 27#include "pm.h"
@@ -37,7 +38,7 @@ void __init at91rm9200_set_type(int type)
37 else 38 else
38 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; 39 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
39 40
40 pr_info("AT91: filled in soc subtype: %s\n", 41 pr_info("filled in soc subtype: %s\n",
41 at91_get_soc_subtype(&at91_soc_initdata)); 42 at91_get_soc_subtype(&at91_soc_initdata));
42} 43}
43 44
@@ -49,7 +50,8 @@ void __init at91_init_irq_default(void)
49void __init at91_init_interrupts(unsigned int *priority) 50void __init at91_init_interrupts(unsigned int *priority)
50{ 51{
51 /* Initialize the AIC interrupt controller */ 52 /* Initialize the AIC interrupt controller */
52 at91_aic_init(priority, at91_boot_soc.extern_irq); 53 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
54 at91_aic_init(priority, at91_boot_soc.extern_irq);
53 55
54 /* Enable GPIO interrupts */ 56 /* Enable GPIO interrupts */
55 at91_gpio_irq_setup(); 57 at91_gpio_irq_setup();
@@ -66,7 +68,7 @@ void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
66 } 68 }
67 at91_ramc_base[id] = ioremap(addr, size); 69 at91_ramc_base[id] = ioremap(addr, size);
68 if (!at91_ramc_base[id]) 70 if (!at91_ramc_base[id])
69 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr); 71 panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
70} 72}
71 73
72static struct map_desc sram_desc[2] __initdata; 74static struct map_desc sram_desc[2] __initdata;
@@ -83,7 +85,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
83 desc->length = length; 85 desc->length = length;
84 desc->type = MT_MEMORY_RWX_NONCACHED; 86 desc->type = MT_MEMORY_RWX_NONCACHED;
85 87
86 pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n", 88 pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
87 base, length, desc->virtual); 89 base, length, desc->virtual);
88 90
89 iotable_init(desc, 1); 91 iotable_init(desc, 1);
@@ -96,6 +98,13 @@ static struct map_desc at91_io_desc __initdata __maybe_unused = {
96 .type = MT_DEVICE, 98 .type = MT_DEVICE,
97}; 99};
98 100
101static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
102 .virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
103 .pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
104 .length = 24 * SZ_1K,
105 .type = MT_DEVICE,
106};
107
99static void __init soc_detect(u32 dbgu_base) 108static void __init soc_detect(u32 dbgu_base)
100{ 109{
101 u32 cidr, socid; 110 u32 cidr, socid;
@@ -158,9 +167,12 @@ static void __init soc_detect(u32 dbgu_base)
158 at91_boot_soc = at91sam9n12_soc; 167 at91_boot_soc = at91sam9n12_soc;
159 break; 168 break;
160 169
161 case ARCH_ID_SAMA5D3: 170 case ARCH_ID_SAMA5:
162 at91_soc_initdata.type = AT91_SOC_SAMA5D3; 171 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
163 at91_boot_soc = sama5d3_soc; 172 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
173 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
174 at91_boot_soc = sama5d3_soc;
175 }
164 break; 176 break;
165 } 177 }
166 178
@@ -183,7 +195,8 @@ static void __init soc_detect(u32 dbgu_base)
183 at91_soc_initdata.cidr = cidr; 195 at91_soc_initdata.cidr = cidr;
184 196
185 /* sub version of soc */ 197 /* sub version of soc */
186 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID); 198 if (!at91_soc_initdata.exid)
199 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
187 200
188 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) { 201 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
189 switch (at91_soc_initdata.exid) { 202 switch (at91_soc_initdata.exid) {
@@ -240,6 +253,54 @@ static void __init soc_detect(u32 dbgu_base)
240 } 253 }
241} 254}
242 255
256static void __init alt_soc_detect(u32 dbgu_base)
257{
258 u32 cidr, socid;
259
260 /* SoC ID */
261 cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
262 socid = cidr & ~AT91_CIDR_VERSION;
263
264 switch (socid) {
265 case ARCH_ID_SAMA5:
266 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
267 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
268 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
269 at91_boot_soc = sama5d3_soc;
270 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
271 at91_soc_initdata.type = AT91_SOC_SAMA5D4;
272 at91_boot_soc = sama5d4_soc;
273 }
274 break;
275 }
276
277 if (!at91_soc_is_detected())
278 return;
279
280 at91_soc_initdata.cidr = cidr;
281
282 /* sub version of soc */
283 if (!at91_soc_initdata.exid)
284 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
285
286 if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
287 switch (at91_soc_initdata.exid) {
288 case ARCH_EXID_SAMA5D41:
289 at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
290 break;
291 case ARCH_EXID_SAMA5D42:
292 at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
293 break;
294 case ARCH_EXID_SAMA5D43:
295 at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
296 break;
297 case ARCH_EXID_SAMA5D44:
298 at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
299 break;
300 }
301 }
302}
303
243static const char *soc_name[] = { 304static const char *soc_name[] = {
244 [AT91_SOC_RM9200] = "at91rm9200", 305 [AT91_SOC_RM9200] = "at91rm9200",
245 [AT91_SOC_SAM9260] = "at91sam9260", 306 [AT91_SOC_SAM9260] = "at91sam9260",
@@ -252,6 +313,7 @@ static const char *soc_name[] = {
252 [AT91_SOC_SAM9X5] = "at91sam9x5", 313 [AT91_SOC_SAM9X5] = "at91sam9x5",
253 [AT91_SOC_SAM9N12] = "at91sam9n12", 314 [AT91_SOC_SAM9N12] = "at91sam9n12",
254 [AT91_SOC_SAMA5D3] = "sama5d3", 315 [AT91_SOC_SAMA5D3] = "sama5d3",
316 [AT91_SOC_SAMA5D4] = "sama5d4",
255 [AT91_SOC_UNKNOWN] = "Unknown", 317 [AT91_SOC_UNKNOWN] = "Unknown",
256}; 318};
257 319
@@ -279,6 +341,10 @@ static const char *soc_subtype_name[] = {
279 [AT91_SOC_SAMA5D34] = "sama5d34", 341 [AT91_SOC_SAMA5D34] = "sama5d34",
280 [AT91_SOC_SAMA5D35] = "sama5d35", 342 [AT91_SOC_SAMA5D35] = "sama5d35",
281 [AT91_SOC_SAMA5D36] = "sama5d36", 343 [AT91_SOC_SAMA5D36] = "sama5d36",
344 [AT91_SOC_SAMA5D41] = "sama5d41",
345 [AT91_SOC_SAMA5D42] = "sama5d42",
346 [AT91_SOC_SAMA5D43] = "sama5d43",
347 [AT91_SOC_SAMA5D44] = "sama5d44",
282 [AT91_SOC_SUBTYPE_NONE] = "None", 348 [AT91_SOC_SUBTYPE_NONE] = "None",
283 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", 349 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
284}; 350};
@@ -302,43 +368,44 @@ void __init at91_map_io(void)
302 soc_detect(AT91_BASE_DBGU1); 368 soc_detect(AT91_BASE_DBGU1);
303 369
304 if (!at91_soc_is_detected()) 370 if (!at91_soc_is_detected())
305 panic("AT91: Impossible to detect the SOC type"); 371 panic(pr_fmt("Impossible to detect the SOC type"));
306 372
307 pr_info("AT91: Detected soc type: %s\n", 373 pr_info("Detected soc type: %s\n",
308 at91_get_soc_type(&at91_soc_initdata)); 374 at91_get_soc_type(&at91_soc_initdata));
309 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE) 375 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
310 pr_info("AT91: Detected soc subtype: %s\n", 376 pr_info("Detected soc subtype: %s\n",
311 at91_get_soc_subtype(&at91_soc_initdata)); 377 at91_get_soc_subtype(&at91_soc_initdata));
312 378
313 if (!at91_soc_is_enabled()) 379 if (!at91_soc_is_enabled())
314 panic("AT91: Soc not enabled"); 380 panic(pr_fmt("Soc not enabled"));
315 381
316 if (at91_boot_soc.map_io) 382 if (at91_boot_soc.map_io)
317 at91_boot_soc.map_io(); 383 at91_boot_soc.map_io();
318} 384}
319 385
320void __iomem *at91_shdwc_base = NULL; 386void __init at91_alt_map_io(void)
321
322static void at91sam9_poweroff(void)
323{ 387{
324 at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); 388 /* Map peripherals */
325} 389 iotable_init(&at91_alt_io_desc, 1);
326 390
327void __init at91_ioremap_shdwc(u32 base_addr) 391 at91_soc_initdata.type = AT91_SOC_UNKNOWN;
328{ 392 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
329 at91_shdwc_base = ioremap(base_addr, 16);
330 if (!at91_shdwc_base)
331 panic("Impossible to ioremap at91_shdwc_base\n");
332 pm_power_off = at91sam9_poweroff;
333}
334 393
335void __iomem *at91_rstc_base; 394 alt_soc_detect(AT91_BASE_DBGU2);
395 if (!at91_soc_is_detected())
396 panic("AT91: Impossible to detect the SOC type");
336 397
337void __init at91_ioremap_rstc(u32 base_addr) 398 pr_info("AT91: Detected soc type: %s\n",
338{ 399 at91_get_soc_type(&at91_soc_initdata));
339 at91_rstc_base = ioremap(base_addr, 16); 400 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
340 if (!at91_rstc_base) 401 pr_info("AT91: Detected soc subtype: %s\n",
341 panic("Impossible to ioremap at91_rstc_base\n"); 402 at91_get_soc_subtype(&at91_soc_initdata));
403
404 if (!at91_soc_is_enabled())
405 panic("AT91: Soc not enabled");
406
407 if (at91_boot_soc.map_io)
408 at91_boot_soc.map_io();
342} 409}
343 410
344void __iomem *at91_matrix_base; 411void __iomem *at91_matrix_base;
@@ -348,42 +415,15 @@ void __init at91_ioremap_matrix(u32 base_addr)
348{ 415{
349 at91_matrix_base = ioremap(base_addr, 512); 416 at91_matrix_base = ioremap(base_addr, 512);
350 if (!at91_matrix_base) 417 if (!at91_matrix_base)
351 panic("Impossible to ioremap at91_matrix_base\n"); 418 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
352} 419}
353 420
354#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40) 421#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
355static struct of_device_id rstc_ids[] = {
356 { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
357 { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
358 { /*sentinel*/ }
359};
360
361static void at91_dt_rstc(void)
362{
363 struct device_node *np;
364 const struct of_device_id *of_id;
365
366 np = of_find_matching_node(NULL, rstc_ids);
367 if (!np)
368 panic("unable to find compatible rstc node in dtb\n");
369
370 at91_rstc_base = of_iomap(np, 0);
371 if (!at91_rstc_base)
372 panic("unable to map rstc cpu registers\n");
373
374 of_id = of_match_node(rstc_ids, np);
375 if (!of_id)
376 panic("AT91: rtsc no restart function available\n");
377
378 arm_pm_restart = of_id->data;
379
380 of_node_put(np);
381}
382
383static struct of_device_id ramc_ids[] = { 422static struct of_device_id ramc_ids[] = {
384 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, 423 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
385 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, 424 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
386 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, 425 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
426 { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
387 { /*sentinel*/ } 427 { /*sentinel*/ }
388}; 428};
389 429
@@ -391,100 +431,29 @@ static void at91_dt_ramc(void)
391{ 431{
392 struct device_node *np; 432 struct device_node *np;
393 const struct of_device_id *of_id; 433 const struct of_device_id *of_id;
434 int idx = 0;
435 const void *standby = NULL;
394 436
395 np = of_find_matching_node(NULL, ramc_ids); 437 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
396 if (!np) 438 at91_ramc_base[idx] = of_iomap(np, 0);
397 panic("unable to find compatible ram controller node in dtb\n"); 439 if (!at91_ramc_base[idx])
398 440 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
399 at91_ramc_base[0] = of_iomap(np, 0);
400 if (!at91_ramc_base[0])
401 panic("unable to map ramc[0] cpu registers\n");
402 /* the controller may have 2 banks */
403 at91_ramc_base[1] = of_iomap(np, 1);
404 441
405 of_id = of_match_node(ramc_ids, np); 442 if (!standby)
406 if (!of_id) 443 standby = of_id->data;
407 pr_warn("AT91: ramc no standby function available\n");
408 else
409 at91_pm_set_standby(of_id->data);
410 444
411 of_node_put(np); 445 idx++;
412}
413
414static struct of_device_id shdwc_ids[] = {
415 { .compatible = "atmel,at91sam9260-shdwc", },
416 { .compatible = "atmel,at91sam9rl-shdwc", },
417 { .compatible = "atmel,at91sam9x5-shdwc", },
418 { /*sentinel*/ }
419};
420
421static const char *shdwc_wakeup_modes[] = {
422 [AT91_SHDW_WKMODE0_NONE] = "none",
423 [AT91_SHDW_WKMODE0_HIGH] = "high",
424 [AT91_SHDW_WKMODE0_LOW] = "low",
425 [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
426};
427
428const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
429{
430 const char *pm;
431 int err, i;
432
433 err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
434 if (err < 0)
435 return AT91_SHDW_WKMODE0_ANYLEVEL;
436
437 for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
438 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
439 return i;
440
441 return -ENODEV;
442}
443
444static void at91_dt_shdwc(void)
445{
446 struct device_node *np;
447 int wakeup_mode;
448 u32 reg;
449 u32 mode = 0;
450
451 np = of_find_matching_node(NULL, shdwc_ids);
452 if (!np) {
453 pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
454 return;
455 } 446 }
456 447
457 at91_shdwc_base = of_iomap(np, 0); 448 if (!idx)
458 if (!at91_shdwc_base) 449 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
459 panic("AT91: unable to map shdwc cpu registers\n");
460
461 wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
462 if (wakeup_mode < 0) {
463 pr_warn("AT91: shdwc unknown wakeup mode\n");
464 goto end;
465 }
466 450
467 if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) { 451 if (!standby) {
468 if (reg > AT91_SHDW_CPTWK0_MAX) { 452 pr_warn("ramc no standby function available\n");
469 pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n", 453 return;
470 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
471 reg = AT91_SHDW_CPTWK0_MAX;
472 }
473 mode |= AT91_SHDW_CPTWK0_(reg);
474 } 454 }
475 455
476 if (of_property_read_bool(np, "atmel,wakeup-rtc-timer")) 456 at91_pm_set_standby(standby);
477 mode |= AT91_SHDW_RTCWKEN;
478
479 if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
480 mode |= AT91_SHDW_RTTWKEN;
481
482 at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
483
484end:
485 pm_power_off = at91sam9_poweroff;
486
487 of_node_put(np);
488} 457}
489 458
490void __init at91rm9200_dt_initialize(void) 459void __init at91rm9200_dt_initialize(void)
@@ -503,9 +472,7 @@ void __init at91rm9200_dt_initialize(void)
503 472
504void __init at91_dt_initialize(void) 473void __init at91_dt_initialize(void)
505{ 474{
506 at91_dt_rstc();
507 at91_dt_ramc(); 475 at91_dt_ramc();
508 at91_dt_shdwc();
509 476
510 /* Init clock subsystem */ 477 /* Init clock subsystem */
511 at91_dt_clock_init(); 478 at91_dt_clock_init();
@@ -533,3 +500,13 @@ void __init at91_initialize(unsigned long main_clock)
533 500
534 pinctrl_provide_dummies(); 501 pinctrl_provide_dummies();
535} 502}
503
504void __init at91_register_devices(void)
505{
506 at91_boot_soc.register_devices();
507}
508
509void __init at91_init_time(void)
510{
511 at91_boot_soc.init_time();
512}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index a1e1482c6da8..9a8fd97a8bef 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -11,7 +11,9 @@ struct at91_init_soc {
11 void (*map_io)(void); 11 void (*map_io)(void);
12 void (*ioremap_registers)(void); 12 void (*ioremap_registers)(void);
13 void (*register_clocks)(void); 13 void (*register_clocks)(void);
14 void (*register_devices)(void);
14 void (*init)(void); 15 void (*init)(void);
16 void (*init_time)(void);
15}; 17};
16 18
17extern struct at91_init_soc at91_boot_soc; 19extern struct at91_init_soc at91_boot_soc;
@@ -24,6 +26,7 @@ extern struct at91_init_soc at91sam9rl_soc;
24extern struct at91_init_soc at91sam9x5_soc; 26extern struct at91_init_soc at91sam9x5_soc;
25extern struct at91_init_soc at91sam9n12_soc; 27extern struct at91_init_soc at91sam9n12_soc;
26extern struct at91_init_soc sama5d3_soc; 28extern struct at91_init_soc sama5d3_soc;
29extern struct at91_init_soc sama5d4_soc;
27 30
28#define AT91_SOC_START(_name) \ 31#define AT91_SOC_START(_name) \
29struct at91_init_soc __initdata _name##_soc \ 32struct at91_init_soc __initdata _name##_soc \
@@ -74,3 +77,7 @@ static inline int at91_soc_is_enabled(void)
74#if !defined(CONFIG_SOC_SAMA5D3) 77#if !defined(CONFIG_SOC_SAMA5D3)
75#define sama5d3_soc at91_boot_soc 78#define sama5d3_soc at91_boot_soc
76#endif 79#endif
80
81#if !defined(CONFIG_SOC_SAMA5D4)
82#define sama5d4_soc at91_boot_soc
83#endif
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index fc938005ad39..2abad742516d 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -99,6 +99,23 @@ config ARCH_BCM_5301X
99 different SoC or with the older BCM47XX and BCM53XX based 99 different SoC or with the older BCM47XX and BCM53XX based
100 network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx 100 network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
101 101
102config ARCH_BCM_63XX
103 bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
104 depends on MMU
105 select ARM_ERRATA_754322
106 select ARM_ERRATA_764369 if SMP
107 select ARM_GIC
108 select ARM_GLOBAL_TIMER
109 select CACHE_L2X0
110 select HAVE_ARM_ARCH_TIMER
111 select HAVE_ARM_TWD if SMP
112 select HAVE_ARM_SCU if SMP
113 select HAVE_SMP
114 help
115 This enables support for systems based on Broadcom DSL SoCs.
116 It currently supports the 'BCM63XX' ARM-based family, which includes
117 the BCM63138 variant.
118
102config ARCH_BRCMSTB 119config ARCH_BRCMSTB
103 bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7 120 bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
104 depends on MMU 121 depends on MMU
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index b19a39652545..300ae4b79ae6 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -34,6 +34,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
34# BCM5301X 34# BCM5301X
35obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o 35obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
36 36
37# BCM63XXx
38obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
39
37ifeq ($(CONFIG_ARCH_BRCMSTB),y) 40ifeq ($(CONFIG_ARCH_BRCMSTB),y)
38obj-y += brcmstb.o 41obj-y += brcmstb.o
39endif 42endif
diff --git a/arch/arm/mach-bcm/bcm63xx.c b/arch/arm/mach-bcm/bcm63xx.c
new file mode 100644
index 000000000000..c4c66ae51308
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm63xx.c
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/of_platform.h>
15
16#include <asm/mach/arch.h>
17
18static const char * const bcm63xx_dt_compat[] = {
19 "brcm,bcm63138",
20 NULL
21};
22
23DT_MACHINE_START(BCM63XXX_DT, "BCM63xx DSL SoC")
24 .dt_compat = bcm63xx_dt_compat,
25 .l2c_aux_val = 0,
26 .l2c_aux_mask = ~0,
27MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index fdf54d40909a..f33979784f38 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -14,8 +14,9 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/i2c-gpio.h> 15#include <linux/i2c-gpio.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/backlight.h>
18#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/pwm_backlight.h>
19#include <linux/memblock.h> 20#include <linux/memblock.h>
20 21
21#include <linux/mtd/physmap.h> 22#include <linux/mtd/physmap.h>
@@ -108,23 +109,23 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
108 .set_power = edb7211_lcd_power_set, 109 .set_power = edb7211_lcd_power_set,
109}; 110};
110 111
111static void edb7211_lcd_backlight_set_intensity(int intensity) 112static struct pwm_lookup edb7211_pwm_lookup[] = {
112{ 113 PWM_LOOKUP("clps711x-pwm", 0, "pwm-backlight.0", NULL,
113 gpio_set_value(EDB7211_LCDBL, !!intensity); 114 0, PWM_POLARITY_NORMAL),
114 clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON); 115};
115}
116 116
117static struct generic_bl_info edb7211_lcd_backlight_pdata = { 117static struct platform_pwm_backlight_data pwm_bl_pdata = {
118 .name = "lcd-backlight.0", 118 .dft_brightness = 0x01,
119 .default_intensity = 0x01, 119 .max_brightness = 0x0f,
120 .max_intensity = 0x0f, 120 .enable_gpio = EDB7211_LCDBL,
121 .set_bl_intensity = edb7211_lcd_backlight_set_intensity,
122}; 121};
123 122
123static struct resource clps711x_pwm_res =
124 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + PMPCON, SZ_4);
125
124static struct gpio edb7211_gpios[] __initconst = { 126static struct gpio edb7211_gpios[] __initconst = {
125 { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" }, 127 { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" },
126 { EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" }, 128 { EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" },
127 { EDB7211_LCDBL, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT" },
128}; 129};
129 130
130/* Reserve screen memory region at the start of main system memory. */ 131/* Reserve screen memory region at the start of main system memory. */
@@ -153,12 +154,18 @@ static void __init edb7211_init_late(void)
153 gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios)); 154 gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
154 155
155 platform_device_register(&edb7211_flash_pdev); 156 platform_device_register(&edb7211_flash_pdev);
157
156 platform_device_register_data(NULL, "platform-lcd", 0, 158 platform_device_register_data(NULL, "platform-lcd", 0,
157 &edb7211_lcd_power_pdata, 159 &edb7211_lcd_power_pdata,
158 sizeof(edb7211_lcd_power_pdata)); 160 sizeof(edb7211_lcd_power_pdata));
159 platform_device_register_data(NULL, "generic-bl", 0, 161
160 &edb7211_lcd_backlight_pdata, 162 platform_device_register_simple("clps711x-pwm", PLATFORM_DEVID_NONE,
161 sizeof(edb7211_lcd_backlight_pdata)); 163 &clps711x_pwm_res, 1);
164 pwm_add_table(edb7211_pwm_lookup, ARRAY_SIZE(edb7211_pwm_lookup));
165
166 platform_device_register_data(&platform_bus, "pwm-backlight", 0,
167 &pwm_bl_pdata, sizeof(pwm_bl_pdata));
168
162 platform_device_register_simple("video-clps711x", 0, NULL, 0); 169 platform_device_register_simple("video-clps711x", 0, NULL, 0);
163 platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource, 170 platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
164 ARRAY_SIZE(edb7211_cs8900_resource)); 171 ARRAY_SIZE(edb7211_cs8900_resource));
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 2a6323b15782..671acc5a3282 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -19,29 +19,17 @@
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */ 21 */
22#include <linux/io.h> 22
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/sizes.h> 24#include <linux/sizes.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/clk.h>
28#include <linux/clkdev.h>
29#include <linux/clockchips.h>
30#include <linux/clocksource.h>
31#include <linux/clk-provider.h>
32#include <linux/sched_clock.h>
33 25
34#include <asm/mach/map.h> 26#include <asm/mach/map.h>
35#include <asm/mach/time.h>
36#include <asm/system_misc.h> 27#include <asm/system_misc.h>
37 28
38#include <mach/hardware.h> 29#include <mach/hardware.h>
39 30
40#include "common.h" 31#include "common.h"
41 32
42static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
43 *clk_tint, *clk_spi;
44
45/* 33/*
46 * This maps the generic CLPS711x registers 34 * This maps the generic CLPS711x registers
47 */ 35 */
@@ -64,129 +52,11 @@ void __init clps711x_init_irq(void)
64 clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K); 52 clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
65} 53}
66 54
67static u64 notrace clps711x_sched_clock_read(void)
68{
69 return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
70}
71
72static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
73 struct clock_event_device *evt)
74{
75 disable_irq(IRQ_TC2OI);
76
77 switch (mode) {
78 case CLOCK_EVT_MODE_PERIODIC:
79 enable_irq(IRQ_TC2OI);
80 break;
81 case CLOCK_EVT_MODE_ONESHOT:
82 /* Not supported */
83 case CLOCK_EVT_MODE_SHUTDOWN:
84 case CLOCK_EVT_MODE_UNUSED:
85 case CLOCK_EVT_MODE_RESUME:
86 /* Left event sources disabled, no more interrupts appear */
87 break;
88 }
89}
90
91static struct clock_event_device clockevent_clps711x = {
92 .name = "clps711x-clockevent",
93 .rating = 300,
94 .features = CLOCK_EVT_FEAT_PERIODIC,
95 .set_mode = clps711x_clockevent_set_mode,
96};
97
98static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
99{
100 clockevent_clps711x.event_handler(&clockevent_clps711x);
101
102 return IRQ_HANDLED;
103}
104
105static struct irqaction clps711x_timer_irq = {
106 .name = "clps711x-timer",
107 .flags = IRQF_TIMER | IRQF_IRQPOLL,
108 .handler = clps711x_timer_interrupt,
109};
110
111static void add_fixed_clk(struct clk *clk, const char *name, int rate)
112{
113 clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
114 clk_register_clkdev(clk, name, NULL);
115}
116
117void __init clps711x_timer_init(void) 55void __init clps711x_timer_init(void)
118{ 56{
119 int osc, ext, pll, cpu, bus, timl, timh, uart, spi; 57 clps711x_clk_init(CLPS711X_VIRT_BASE);
120 u32 tmp; 58 clps711x_clksrc_init(CLPS711X_VIRT_BASE + TC1D,
121 59 CLPS711X_VIRT_BASE + TC2D, IRQ_TC2OI);
122 osc = 3686400;
123 ext = 13000000;
124
125 tmp = clps_readl(PLLR) >> 24;
126 if (tmp)
127 pll = (osc * tmp) / 2;
128 else
129 pll = 73728000; /* Default value */
130
131 tmp = clps_readl(SYSFLG2);
132 if (tmp & SYSFLG2_CKMODE) {
133 cpu = ext;
134 bus = cpu;
135 spi = 135400;
136 pll = 0;
137 } else {
138 cpu = pll;
139 if (cpu >= 36864000)
140 bus = cpu / 2;
141 else
142 bus = 36864000 / 2;
143 spi = cpu / 576;
144 }
145
146 uart = bus / 10;
147
148 if (tmp & SYSFLG2_CKMODE) {
149 tmp = clps_readl(SYSCON2);
150 if (tmp & SYSCON2_OSTB)
151 timh = ext / 26;
152 else
153 timh = 541440;
154 } else
155 timh = DIV_ROUND_CLOSEST(cpu, 144);
156
157 timl = DIV_ROUND_CLOSEST(timh, 256);
158
159 /* All clocks are fixed */
160 add_fixed_clk(clk_pll, "pll", pll);
161 add_fixed_clk(clk_bus, "bus", bus);
162 add_fixed_clk(clk_uart, "uart", uart);
163 add_fixed_clk(clk_timerl, "timer_lf", timl);
164 add_fixed_clk(clk_timerh, "timer_hf", timh);
165 add_fixed_clk(clk_tint, "tint", 64);
166 add_fixed_clk(clk_spi, "spi", spi);
167
168 pr_info("CPU frequency set at %i Hz.\n", cpu);
169
170 /* Start Timer1 in free running mode (Low frequency) */
171 tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
172 clps_writel(tmp, SYSCON1);
173
174 sched_clock_register(clps711x_sched_clock_read, 16, timl);
175
176 clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
177 "clps711x_clocksource", timl, 300, 16,
178 clocksource_mmio_readw_down);
179
180 /* Set Timer2 prescaler */
181 clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
182
183 /* Start Timer2 in prescale mode (High frequency)*/
184 tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
185 clps_writel(tmp, SYSCON1);
186
187 clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
188
189 setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
190} 60}
191 61
192void clps711x_restart(enum reboot_mode mode, const char *cmd) 62void clps711x_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f88189963898..370200b26333 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -16,3 +16,8 @@ extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
16 16
17/* drivers/irqchip/irq-clps711x.c */ 17/* drivers/irqchip/irq-clps711x.c */
18void clps711x_intc_init(phys_addr_t, resource_size_t); 18void clps711x_intc_init(phys_addr_t, resource_size_t);
19/* drivers/clk/clk-clps711x.c */
20void clps711x_clk_init(void __iomem *base);
21/* drivers/clocksource/clps711x-timer.c */
22void clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
23 unsigned int irq);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index 0c689d3a6710..77a9617c216d 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * CLPS711X common devices definitions 2 * CLPS711X common devices definitions
3 * 3 *
4 * Author: Alexander Shiyan <shc_work@mail.ru>, 2013 4 * Author: Alexander Shiyan <shc_work@mail.ru>, 2013-2014
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -9,8 +9,15 @@
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11 11
12#include <linux/io.h>
13#include <linux/of_fdt.h>
12#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/random.h>
13#include <linux/sizes.h> 16#include <linux/sizes.h>
17#include <linux/slab.h>
18#include <linux/sys_soc.h>
19
20#include <asm/system_info.h>
14 21
15#include <mach/hardware.h> 22#include <mach/hardware.h>
16 23
@@ -90,10 +97,53 @@ static void __init clps711x_add_uart(void)
90 ARRAY_SIZE(clps711x_uart2_res)); 97 ARRAY_SIZE(clps711x_uart2_res));
91}; 98};
92 99
100static void __init clps711x_soc_init(void)
101{
102 struct soc_device_attribute *soc_dev_attr;
103 struct soc_device *soc_dev;
104 void __iomem *base;
105 u32 id[5];
106
107 base = ioremap(CLPS711X_PHYS_BASE, SZ_32K);
108 if (!base)
109 return;
110
111 id[0] = readl(base + UNIQID);
112 id[1] = readl(base + RANDID0);
113 id[2] = readl(base + RANDID1);
114 id[3] = readl(base + RANDID2);
115 id[4] = readl(base + RANDID3);
116 system_rev = SYSFLG1_VERID(readl(base + SYSFLG1));
117
118 add_device_randomness(id, sizeof(id));
119
120 system_serial_low = id[0];
121
122 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
123 if (!soc_dev_attr)
124 goto out_unmap;
125
126 soc_dev_attr->machine = of_flat_dt_get_machine_name();
127 soc_dev_attr->family = "Cirrus Logic CLPS711X";
128 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", system_rev);
129 soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%08x", id[0]);
130
131 soc_dev = soc_device_register(soc_dev_attr);
132 if (IS_ERR(soc_dev)) {
133 kfree(soc_dev_attr->revision);
134 kfree(soc_dev_attr->soc_id);
135 kfree(soc_dev_attr);
136 }
137
138out_unmap:
139 iounmap(base);
140}
141
93void __init clps711x_devices_init(void) 142void __init clps711x_devices_init(void)
94{ 143{
95 clps711x_add_cpuidle(); 144 clps711x_add_cpuidle();
96 clps711x_add_gpio(); 145 clps711x_add_gpio();
97 clps711x_add_syscon(); 146 clps711x_add_syscon();
98 clps711x_add_uart(); 147 clps711x_add_uart();
148 clps711x_soc_init();
99} 149}
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index d863d8729edc..6428bcc77e87 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -250,5 +250,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
250 .init_irq = cns3xxx_init_irq, 250 .init_irq = cns3xxx_init_irq,
251 .init_time = cns3xxx_timer_init, 251 .init_time = cns3xxx_timer_init,
252 .init_machine = cns3420_init, 252 .init_machine = cns3420_init,
253 .init_late = cns3xxx_pcie_init_late,
253 .restart = cns3xxx_restart, 254 .restart = cns3xxx_restart,
254MACHINE_END 255MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index f85449a6accd..4e9837ded96d 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -404,5 +404,6 @@ DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
404 .init_irq = cns3xxx_init_irq, 404 .init_irq = cns3xxx_init_irq,
405 .init_time = cns3xxx_timer_init, 405 .init_time = cns3xxx_timer_init,
406 .init_machine = cns3xxx_init, 406 .init_machine = cns3xxx_init,
407 .init_late = cns3xxx_pcie_init_late,
407 .restart = cns3xxx_restart, 408 .restart = cns3xxx_restart,
408MACHINE_END 409MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index 5218b6198dc2..dc5df7f1e39f 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -21,6 +21,12 @@ void __init cns3xxx_l2x0_init(void);
21static inline void cns3xxx_l2x0_init(void) {} 21static inline void cns3xxx_l2x0_init(void) {}
22#endif /* CONFIG_CACHE_L2X0 */ 22#endif /* CONFIG_CACHE_L2X0 */
23 23
24#ifdef CONFIG_PCI
25extern void __init cns3xxx_pcie_init_late(void);
26#else
27static inline void __init cns3xxx_pcie_init_late(void) {}
28#endif
29
24void __init cns3xxx_map_io(void); 30void __init cns3xxx_map_io(void);
25void __init cns3xxx_init_irq(void); 31void __init cns3xxx_init_irq(void);
26void cns3xxx_power_off(void); 32void cns3xxx_power_off(void);
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 413134c54452..45d6bd09e6ef 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -60,11 +60,10 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
60 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); 60 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
61 int busno = bus->number; 61 int busno = bus->number;
62 int slot = PCI_SLOT(devfn); 62 int slot = PCI_SLOT(devfn);
63 int offset;
64 void __iomem *base; 63 void __iomem *base;
65 64
66 /* If there is no link, just show the CNS PCI bridge. */ 65 /* If there is no link, just show the CNS PCI bridge. */
67 if (!cnspci->linked && (busno > 0 || slot > 0)) 66 if (!cnspci->linked && busno > 0)
68 return NULL; 67 return NULL;
69 68
70 /* 69 /*
@@ -72,22 +71,21 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
72 * we still want to access it. For this to work, we must place 71 * we still want to access it. For this to work, we must place
73 * the first device on the same bus as the CNS PCI bridge. 72 * the first device on the same bus as the CNS PCI bridge.
74 */ 73 */
75 if (busno == 0) { /* directly connected PCIe bus */ 74 if (busno == 0) { /* internal PCIe bus, host bridge device */
76 switch (slot) { 75 if (devfn == 0) /* device# and function# are ignored by hw */
77 case 0: /* host bridge device, function 0 only */
78 base = cnspci->host_regs; 76 base = cnspci->host_regs;
79 break; 77 else
80 case 1: /* directly connected device */ 78 return NULL; /* no such device */
79
80 } else if (busno == 1) { /* directly connected PCIe device */
81 if (slot == 0) /* device# is ignored by hw */
81 base = cnspci->cfg0_regs; 82 base = cnspci->cfg0_regs;
82 break; 83 else
83 default:
84 return NULL; /* no such device */ 84 return NULL; /* no such device */
85 }
86 } else /* remote PCI bus */ 85 } else /* remote PCI bus */
87 base = cnspci->cfg1_regs; 86 base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
88 87
89 offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc); 88 return base + (where & 0xffc) + (devfn << 12);
90 return base + offset;
91} 89}
92 90
93static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 91static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
@@ -167,7 +165,7 @@ static struct pci_ops cns3xxx_pcie_ops = {
167static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 165static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
168{ 166{
169 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); 167 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
170 int irq = cnspci->irqs[slot]; 168 int irq = cnspci->irqs[!!dev->bus->number];
171 169
172 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", 170 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
173 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), 171 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
@@ -297,15 +295,19 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
297 return; 295 return;
298 296
299 /* Set Device Max_Read_Request_Size to 128 byte */ 297 /* Set Device Max_Read_Request_Size to 128 byte */
300 devfn = PCI_DEVFN(1, 0); 298 bus.number = 1; /* directly connected PCIe device */
299 devfn = PCI_DEVFN(0, 0);
301 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); 300 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
302 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); 301 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
303 dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */ 302 if (dc & PCI_EXP_DEVCTL_READRQ) {
304 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); 303 dc &= ~PCI_EXP_DEVCTL_READRQ;
305 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); 304 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
306 if (!(dc & (0x3 << 12))) 305 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
307 pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n"); 306 if (dc & PCI_EXP_DEVCTL_READRQ)
308 307 pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n");
308 else
309 pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n");
310 }
309 /* Disable PCIe0 Interrupt Mask INTA to INTD */ 311 /* Disable PCIe0 Interrupt Mask INTA to INTD */
310 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port)); 312 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
311} 313}
@@ -318,7 +320,7 @@ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
318 return 0; 320 return 0;
319} 321}
320 322
321static int __init cns3xxx_pcie_init(void) 323void __init cns3xxx_pcie_init_late(void)
322{ 324{
323 int i; 325 int i;
324 326
@@ -337,7 +339,4 @@ static int __init cns3xxx_pcie_init(void)
337 } 339 }
338 340
339 pci_assign_unassigned_resources(); 341 pci_assign_unassigned_resources();
340
341 return 0;
342} 342}
343device_initcall(cns3xxx_pcie_init);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 234c5bb091f5..fa11415e906a 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -35,6 +35,7 @@
35#include <linux/platform_data/uio_pruss.h> 35#include <linux/platform_data/uio_pruss.h>
36#include <linux/regulator/machine.h> 36#include <linux/regulator/machine.h>
37#include <linux/regulator/tps6507x.h> 37#include <linux/regulator/tps6507x.h>
38#include <linux/regulator/fixed.h>
38#include <linux/spi/spi.h> 39#include <linux/spi/spi.h>
39#include <linux/spi/flash.h> 40#include <linux/spi/flash.h>
40#include <linux/wl12xx.h> 41#include <linux/wl12xx.h>
@@ -842,6 +843,16 @@ static int da850_lcd_hw_init(void)
842 return 0; 843 return 0;
843} 844}
844 845
846/* Fixed regulator support */
847static struct regulator_consumer_supply fixed_supplies[] = {
848 /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */
849 REGULATOR_SUPPLY("AVDD", "1-0018"),
850 REGULATOR_SUPPLY("DRVDD", "1-0018"),
851
852 /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
853 REGULATOR_SUPPLY("DVDD", "1-0018"),
854};
855
845/* TPS65070 voltage regulator support */ 856/* TPS65070 voltage regulator support */
846 857
847/* 3.3V */ 858/* 3.3V */
@@ -865,6 +876,7 @@ static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
865 { 876 {
866 .supply = "dvdd3318_c", 877 .supply = "dvdd3318_c",
867 }, 878 },
879 REGULATOR_SUPPLY("IOVDD", "1-0018"),
868}; 880};
869 881
870/* 1.2V */ 882/* 1.2V */
@@ -936,6 +948,7 @@ static struct regulator_init_data tps65070_regulator_data[] = {
936 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | 948 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
937 REGULATOR_CHANGE_STATUS), 949 REGULATOR_CHANGE_STATUS),
938 .boot_on = 1, 950 .boot_on = 1,
951 .always_on = 1,
939 }, 952 },
940 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers), 953 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
941 .consumer_supplies = tps65070_dcdc2_consumers, 954 .consumer_supplies = tps65070_dcdc2_consumers,
@@ -1446,6 +1459,8 @@ static __init void da850_evm_init(void)
1446 if (ret) 1459 if (ret)
1447 pr_warn("%s: GPIO init failed: %d\n", __func__, ret); 1460 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
1448 1461
1462 regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies));
1463
1449 ret = pmic_tps65070_init(); 1464 ret = pmic_tps65070_init();
1450 if (ret) 1465 if (ret)
1451 pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret); 1466 pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index ed1928740b5f..f703d82f08a8 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -46,6 +46,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
46 OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL), 46 OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL),
47 OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1", 47 OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1",
48 NULL), 48 NULL),
49 OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
49 {} 50 {}
50}; 51};
51 52
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6a24e111d6e1..b89e5f35db84 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -193,7 +193,6 @@ static void __init exynos_init_late(void)
193 /* to be supported later */ 193 /* to be supported later */
194 return; 194 return;
195 195
196 pm_genpd_poweroff_unused();
197 exynos_pm_init(); 196 exynos_pm_init();
198} 197}
199 198
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
deleted file mode 100644
index e19df1f18c0d..000000000000
--- a/arch/arm/mach-exynos/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Memory definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H __FILE__
14
15#define PLAT_PHYS_OFFSET UL(0x40000000)
16
17#ifndef CONFIG_ARM_LPAE
18/* Maximum of 256MiB in one bank */
19#define MAX_PHYSMEM_BITS 32
20#define SECTION_SIZE_BITS 28
21#else
22#define MAX_PHYSMEM_BITS 36
23#define SECTION_SIZE_BITS 31
24#endif
25
26#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a9f1cf759949..41ae28d69e6f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -224,7 +224,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
224 ret = PTR_ERR(boot_reg); 224 ret = PTR_ERR(boot_reg);
225 goto fail; 225 goto fail;
226 } 226 }
227 __raw_writel(boot_addr, cpu_boot_reg(core_id)); 227 __raw_writel(boot_addr, boot_reg);
228 } 228 }
229 229
230 call_firmware_op(cpu_boot, core_id); 230 call_firmware_op(cpu_boot, core_id);
@@ -313,7 +313,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
313 313
314 if (IS_ERR(boot_reg)) 314 if (IS_ERR(boot_reg))
315 break; 315 break;
316 __raw_writel(boot_addr, cpu_boot_reg(core_id)); 316 __raw_writel(boot_addr, boot_reg);
317 } 317 }
318 } 318 }
319} 319}
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index fd76e1b5a471..20f267121b3e 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -105,78 +105,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
105 return exynos_pd_power(domain, false); 105 return exynos_pd_power(domain, false);
106} 106}
107 107
108static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
109 struct device *dev)
110{
111 int ret;
112
113 dev_dbg(dev, "adding to power domain %s\n", pd->pd.name);
114
115 while (1) {
116 ret = pm_genpd_add_device(&pd->pd, dev);
117 if (ret != -EAGAIN)
118 break;
119 cond_resched();
120 }
121
122 pm_genpd_dev_need_restore(dev, true);
123}
124
125static void exynos_remove_device_from_domain(struct device *dev)
126{
127 struct generic_pm_domain *genpd = dev_to_genpd(dev);
128 int ret;
129
130 dev_dbg(dev, "removing from power domain %s\n", genpd->name);
131
132 while (1) {
133 ret = pm_genpd_remove_device(genpd, dev);
134 if (ret != -EAGAIN)
135 break;
136 cond_resched();
137 }
138}
139
140static void exynos_read_domain_from_dt(struct device *dev)
141{
142 struct platform_device *pd_pdev;
143 struct exynos_pm_domain *pd;
144 struct device_node *node;
145
146 node = of_parse_phandle(dev->of_node, "samsung,power-domain", 0);
147 if (!node)
148 return;
149 pd_pdev = of_find_device_by_node(node);
150 if (!pd_pdev)
151 return;
152 pd = platform_get_drvdata(pd_pdev);
153 exynos_add_device_to_domain(pd, dev);
154}
155
156static int exynos_pm_notifier_call(struct notifier_block *nb,
157 unsigned long event, void *data)
158{
159 struct device *dev = data;
160
161 switch (event) {
162 case BUS_NOTIFY_BIND_DRIVER:
163 if (dev->of_node)
164 exynos_read_domain_from_dt(dev);
165
166 break;
167
168 case BUS_NOTIFY_UNBOUND_DRIVER:
169 exynos_remove_device_from_domain(dev);
170
171 break;
172 }
173 return NOTIFY_DONE;
174}
175
176static struct notifier_block platform_nb = {
177 .notifier_call = exynos_pm_notifier_call,
178};
179
180static __init int exynos4_pm_init_power_domain(void) 108static __init int exynos4_pm_init_power_domain(void)
181{ 109{
182 struct platform_device *pdev; 110 struct platform_device *pdev;
@@ -202,7 +130,6 @@ static __init int exynos4_pm_init_power_domain(void)
202 pd->base = of_iomap(np, 0); 130 pd->base = of_iomap(np, 0);
203 pd->pd.power_off = exynos_pd_power_off; 131 pd->pd.power_off = exynos_pd_power_off;
204 pd->pd.power_on = exynos_pd_power_on; 132 pd->pd.power_on = exynos_pd_power_on;
205 pd->pd.of_node = np;
206 133
207 pd->oscclk = clk_get(dev, "oscclk"); 134 pd->oscclk = clk_get(dev, "oscclk");
208 if (IS_ERR(pd->oscclk)) 135 if (IS_ERR(pd->oscclk))
@@ -228,15 +155,12 @@ static __init int exynos4_pm_init_power_domain(void)
228 clk_put(pd->oscclk); 155 clk_put(pd->oscclk);
229 156
230no_clk: 157no_clk:
231 platform_set_drvdata(pdev, pd);
232
233 on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN; 158 on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
234 159
235 pm_genpd_init(&pd->pd, NULL, !on); 160 pm_genpd_init(&pd->pd, NULL, !on);
161 of_genpd_add_provider_simple(np, &pd->pd);
236 } 162 }
237 163
238 bus_register_notifier(&platform_bus_type, &platform_nb);
239
240 return 0; 164 return 0;
241} 165}
242arch_initcall(exynos4_pm_init_power_domain); 166arch_initcall(exynos4_pm_init_power_domain);
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 984882943f77..cd19433f76d3 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,6 +1,6 @@
1config ARCH_HISI 1config ARCH_HISI
2 bool "Hisilicon SoC Support" 2 bool "Hisilicon SoC Support"
3 depends on ARCH_MULTIPLATFORM 3 depends on ARCH_MULTI_V7
4 select ARM_AMBA 4 select ARM_AMBA
5 select ARM_GIC 5 select ARM_GIC
6 select ARM_TIMER_SP804 6 select ARM_TIMER_SP804
@@ -22,6 +22,15 @@ config ARCH_HI3xxx
22 help 22 help
23 Support for Hisilicon Hi36xx SoC family 23 Support for Hisilicon Hi36xx SoC family
24 24
25config ARCH_HIP04
26 bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7
27 select ARM_ERRATA_798181 if SMP
28 select HAVE_ARM_ARCH_TIMER
29 select MCPM if SMP
30 select MCPM_QUAD_CLUSTER if SMP
31 help
32 Support for Hisilicon HiP04 SoC family
33
25config ARCH_HIX5HD2 34config ARCH_HIX5HD2
26 bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7 35 bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
27 select CACHE_L2X0 36 select CACHE_L2X0
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index ee2506b9cde3..6b7b3033de0b 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -2,5 +2,8 @@
2# Makefile for Hisilicon processors family 2# Makefile for Hisilicon processors family
3# 3#
4 4
5CFLAGS_platmcpm.o := -march=armv7-a
6
5obj-y += hisilicon.o 7obj-y += hisilicon.o
8obj-$(CONFIG_MCPM) += platmcpm.o
6obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o 9obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 7cda6dda3cd0..7744c351bbfd 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -63,3 +63,12 @@ static const char *hix5hd2_compat[] __initconst = {
63DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)") 63DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
64 .dt_compat = hix5hd2_compat, 64 .dt_compat = hix5hd2_compat,
65MACHINE_END 65MACHINE_END
66
67static const char *hip04_compat[] __initconst = {
68 "hisilicon,hip04-d01",
69 NULL,
70};
71
72DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
73 .dt_compat = hip04_compat,
74MACHINE_END
diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
new file mode 100644
index 000000000000..280f3f14f77c
--- /dev/null
+++ b/arch/arm/mach-hisi/platmcpm.c
@@ -0,0 +1,386 @@
1/*
2 * Copyright (c) 2013-2014 Linaro Ltd.
3 * Copyright (c) 2013-2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/memblock.h>
12#include <linux/of_address.h>
13
14#include <asm/cputype.h>
15#include <asm/cp15.h>
16#include <asm/mcpm.h>
17
18#include "core.h"
19
20/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
21 * 1 -- unreset; 0 -- reset
22 */
23#define CORE_RESET_BIT(x) (1 << x)
24#define NEON_RESET_BIT(x) (1 << (x + 4))
25#define CORE_DEBUG_RESET_BIT(x) (1 << (x + 9))
26#define CLUSTER_L2_RESET_BIT (1 << 8)
27#define CLUSTER_DEBUG_RESET_BIT (1 << 13)
28
29/*
30 * bits definition in SC_CPU_RESET_STATUS[x]
31 * 1 -- reset status; 0 -- unreset status
32 */
33#define CORE_RESET_STATUS(x) (1 << x)
34#define NEON_RESET_STATUS(x) (1 << (x + 4))
35#define CORE_DEBUG_RESET_STATUS(x) (1 << (x + 9))
36#define CLUSTER_L2_RESET_STATUS (1 << 8)
37#define CLUSTER_DEBUG_RESET_STATUS (1 << 13)
38#define CORE_WFI_STATUS(x) (1 << (x + 16))
39#define CORE_WFE_STATUS(x) (1 << (x + 20))
40#define CORE_DEBUG_ACK(x) (1 << (x + 24))
41
42#define SC_CPU_RESET_REQ(x) (0x520 + (x << 3)) /* reset */
43#define SC_CPU_RESET_DREQ(x) (0x524 + (x << 3)) /* unreset */
44#define SC_CPU_RESET_STATUS(x) (0x1520 + (x << 3))
45
46#define FAB_SF_MODE 0x0c
47#define FAB_SF_INVLD 0x10
48
49/* bits definition in FB_SF_INVLD */
50#define FB_SF_INVLD_START (1 << 8)
51
52#define HIP04_MAX_CLUSTERS 4
53#define HIP04_MAX_CPUS_PER_CLUSTER 4
54
55#define POLL_MSEC 10
56#define TIMEOUT_MSEC 1000
57
58static void __iomem *sysctrl, *fabric;
59static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
60static DEFINE_SPINLOCK(boot_lock);
61static u32 fabric_phys_addr;
62/*
63 * [0]: bootwrapper physical address
64 * [1]: bootwrapper size
65 * [2]: relocation address
66 * [3]: relocation size
67 */
68static u32 hip04_boot_method[4];
69
70static bool hip04_cluster_is_down(unsigned int cluster)
71{
72 int i;
73
74 for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
75 if (hip04_cpu_table[cluster][i])
76 return false;
77 return true;
78}
79
80static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
81{
82 unsigned long data;
83
84 if (!fabric)
85 BUG();
86 data = readl_relaxed(fabric + FAB_SF_MODE);
87 if (on)
88 data |= 1 << cluster;
89 else
90 data &= ~(1 << cluster);
91 writel_relaxed(data, fabric + FAB_SF_MODE);
92 do {
93 cpu_relax();
94 } while (data != readl_relaxed(fabric + FAB_SF_MODE));
95}
96
97static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
98{
99 unsigned long data;
100 void __iomem *sys_dreq, *sys_status;
101
102 if (!sysctrl)
103 return -ENODEV;
104 if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
105 return -EINVAL;
106
107 spin_lock_irq(&boot_lock);
108
109 if (hip04_cpu_table[cluster][cpu])
110 goto out;
111
112 sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster);
113 sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster);
114 if (hip04_cluster_is_down(cluster)) {
115 data = CLUSTER_DEBUG_RESET_BIT;
116 writel_relaxed(data, sys_dreq);
117 do {
118 cpu_relax();
119 data = readl_relaxed(sys_status);
120 } while (data & CLUSTER_DEBUG_RESET_STATUS);
121 }
122
123 data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
124 CORE_DEBUG_RESET_BIT(cpu);
125 writel_relaxed(data, sys_dreq);
126 do {
127 cpu_relax();
128 } while (data == readl_relaxed(sys_status));
129 /*
130 * We may fail to power up core again without this delay.
131 * It's not mentioned in document. It's found by test.
132 */
133 udelay(20);
134out:
135 hip04_cpu_table[cluster][cpu]++;
136 spin_unlock_irq(&boot_lock);
137
138 return 0;
139}
140
141static void hip04_mcpm_power_down(void)
142{
143 unsigned int mpidr, cpu, cluster;
144 bool skip_wfi = false, last_man = false;
145
146 mpidr = read_cpuid_mpidr();
147 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
148 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
149
150 __mcpm_cpu_going_down(cpu, cluster);
151
152 spin_lock(&boot_lock);
153 BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
154 hip04_cpu_table[cluster][cpu]--;
155 if (hip04_cpu_table[cluster][cpu] == 1) {
156 /* A power_up request went ahead of us. */
157 skip_wfi = true;
158 } else if (hip04_cpu_table[cluster][cpu] > 1) {
159 pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
160 BUG();
161 }
162
163 last_man = hip04_cluster_is_down(cluster);
164 if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
165 spin_unlock(&boot_lock);
166 /* Since it's Cortex A15, disable L2 prefetching. */
167 asm volatile(
168 "mcr p15, 1, %0, c15, c0, 3 \n\t"
169 "isb \n\t"
170 "dsb "
171 : : "r" (0x400) );
172 v7_exit_coherency_flush(all);
173 hip04_set_snoop_filter(cluster, 0);
174 __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
175 } else {
176 spin_unlock(&boot_lock);
177 v7_exit_coherency_flush(louis);
178 }
179
180 __mcpm_cpu_down(cpu, cluster);
181
182 if (!skip_wfi)
183 wfi();
184}
185
186static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
187{
188 unsigned int data, tries, count;
189 int ret = -ETIMEDOUT;
190
191 BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
192 cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
193
194 count = TIMEOUT_MSEC / POLL_MSEC;
195 spin_lock_irq(&boot_lock);
196 for (tries = 0; tries < count; tries++) {
197 if (hip04_cpu_table[cluster][cpu]) {
198 ret = -EBUSY;
199 goto err;
200 }
201 cpu_relax();
202 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
203 if (data & CORE_WFI_STATUS(cpu))
204 break;
205 spin_unlock_irq(&boot_lock);
206 /* Wait for clean L2 when the whole cluster is down. */
207 msleep(POLL_MSEC);
208 spin_lock_irq(&boot_lock);
209 }
210 if (tries >= count)
211 goto err;
212 data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
213 CORE_DEBUG_RESET_BIT(cpu);
214 writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
215 for (tries = 0; tries < count; tries++) {
216 cpu_relax();
217 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
218 if (data & CORE_RESET_STATUS(cpu))
219 break;
220 }
221 if (tries >= count)
222 goto err;
223 spin_unlock_irq(&boot_lock);
224 return 0;
225err:
226 spin_unlock_irq(&boot_lock);
227 return ret;
228}
229
230static void hip04_mcpm_powered_up(void)
231{
232 unsigned int mpidr, cpu, cluster;
233
234 mpidr = read_cpuid_mpidr();
235 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
236 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
237
238 spin_lock(&boot_lock);
239 if (!hip04_cpu_table[cluster][cpu])
240 hip04_cpu_table[cluster][cpu] = 1;
241 spin_unlock(&boot_lock);
242}
243
244static void __naked hip04_mcpm_power_up_setup(unsigned int affinity_level)
245{
246 asm volatile (" \n"
247" cmp r0, #0 \n"
248" bxeq lr \n"
249 /* calculate fabric phys address */
250" adr r2, 2f \n"
251" ldmia r2, {r1, r3} \n"
252" sub r0, r2, r1 \n"
253" ldr r2, [r0, r3] \n"
254 /* get cluster id from MPIDR */
255" mrc p15, 0, r0, c0, c0, 5 \n"
256" ubfx r1, r0, #8, #8 \n"
257 /* 1 << cluster id */
258" mov r0, #1 \n"
259" mov r3, r0, lsl r1 \n"
260" ldr r0, [r2, #"__stringify(FAB_SF_MODE)"] \n"
261" tst r0, r3 \n"
262" bxne lr \n"
263" orr r1, r0, r3 \n"
264" str r1, [r2, #"__stringify(FAB_SF_MODE)"] \n"
265"1: ldr r0, [r2, #"__stringify(FAB_SF_MODE)"] \n"
266" tst r0, r3 \n"
267" beq 1b \n"
268" bx lr \n"
269
270" .align 2 \n"
271"2: .word . \n"
272" .word fabric_phys_addr \n"
273 );
274}
275
276static const struct mcpm_platform_ops hip04_mcpm_ops = {
277 .power_up = hip04_mcpm_power_up,
278 .power_down = hip04_mcpm_power_down,
279 .wait_for_powerdown = hip04_mcpm_wait_for_powerdown,
280 .powered_up = hip04_mcpm_powered_up,
281};
282
283static bool __init hip04_cpu_table_init(void)
284{
285 unsigned int mpidr, cpu, cluster;
286
287 mpidr = read_cpuid_mpidr();
288 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
289 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
290
291 if (cluster >= HIP04_MAX_CLUSTERS ||
292 cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
293 pr_err("%s: boot CPU is out of bound!\n", __func__);
294 return false;
295 }
296 hip04_set_snoop_filter(cluster, 1);
297 hip04_cpu_table[cluster][cpu] = 1;
298 return true;
299}
300
301static int __init hip04_mcpm_init(void)
302{
303 struct device_node *np, *np_sctl, *np_fab;
304 struct resource fab_res;
305 void __iomem *relocation;
306 int ret = -ENODEV;
307
308 np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper");
309 if (!np)
310 goto err;
311 ret = of_property_read_u32_array(np, "boot-method",
312 &hip04_boot_method[0], 4);
313 if (ret)
314 goto err;
315 np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
316 if (!np_sctl)
317 goto err;
318 np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
319 if (!np_fab)
320 goto err;
321
322 ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]);
323 if (ret)
324 goto err;
325
326 relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]);
327 if (!relocation) {
328 pr_err("failed to map relocation space\n");
329 ret = -ENOMEM;
330 goto err_reloc;
331 }
332 sysctrl = of_iomap(np_sctl, 0);
333 if (!sysctrl) {
334 pr_err("failed to get sysctrl base\n");
335 ret = -ENOMEM;
336 goto err_sysctrl;
337 }
338 ret = of_address_to_resource(np_fab, 0, &fab_res);
339 if (ret) {
340 pr_err("failed to get fabric base phys\n");
341 goto err_fabric;
342 }
343 fabric_phys_addr = fab_res.start;
344 sync_cache_w(&fabric_phys_addr);
345 fabric = of_iomap(np_fab, 0);
346 if (!fabric) {
347 pr_err("failed to get fabric base\n");
348 ret = -ENOMEM;
349 goto err_fabric;
350 }
351
352 if (!hip04_cpu_table_init()) {
353 ret = -EINVAL;
354 goto err_table;
355 }
356 ret = mcpm_platform_register(&hip04_mcpm_ops);
357 if (ret) {
358 goto err_table;
359 }
360
361 /*
362 * Fill the instruction address that is used after secondary core
363 * out of reset.
364 */
365 writel_relaxed(hip04_boot_method[0], relocation);
366 writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
367 writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8);
368 writel_relaxed(0, relocation + 12);
369 iounmap(relocation);
370
371 mcpm_sync_init(hip04_mcpm_power_up_setup);
372 mcpm_smp_set_ops();
373 pr_info("HiP04 MCPM initialized\n");
374 return ret;
375err_table:
376 iounmap(fabric);
377err_fabric:
378 iounmap(sysctrl);
379err_sysctrl:
380 iounmap(relocation);
381err_reloc:
382 memblock_free(hip04_boot_method[0], hip04_boot_method[1]);
383err:
384 return ret;
385}
386early_initcall(hip04_mcpm_init);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index be9a51afe05a..11b2957f792b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -69,6 +69,7 @@ config SOC_IMX1
69 select CPU_ARM920T 69 select CPU_ARM920T
70 select IMX_HAVE_IOMUX_V1 70 select IMX_HAVE_IOMUX_V1
71 select MXC_AVIC 71 select MXC_AVIC
72 select PINCTRL_IMX1
72 73
73config SOC_IMX21 74config SOC_IMX21
74 bool 75 bool
@@ -108,17 +109,6 @@ config SOC_IMX35
108if ARCH_MULTI_V4T 109if ARCH_MULTI_V4T
109 110
110comment "MX1 platforms:" 111comment "MX1 platforms:"
111config MACH_MXLADS
112 bool
113
114config ARCH_MX1ADS
115 bool "MX1ADS platform"
116 select IMX_HAVE_PLATFORM_IMX_I2C
117 select IMX_HAVE_PLATFORM_IMX_UART
118 select MACH_MXLADS
119 select SOC_IMX1
120 help
121 Say Y here if you are using Motorola MX1ADS/MXLADS boards
122 112
123config MACH_SCB9328 113config MACH_SCB9328
124 bool "Synertronixx scb9328" 114 bool "Synertronixx scb9328"
@@ -135,6 +125,13 @@ config MACH_APF9328
135 help 125 help
136 Say Yes here if you are using the Armadeus APF9328 development board 126 Say Yes here if you are using the Armadeus APF9328 development board
137 127
128config MACH_IMX1_DT
129 bool "Support i.MX1 platforms from device tree"
130 select SOC_IMX1
131 help
132 Include support for Freescale i.MX1 based platforms
133 using the device tree for discovery.
134
138endif 135endif
139 136
140if ARCH_MULTI_V5 137if ARCH_MULTI_V5
@@ -223,86 +220,6 @@ config MACH_MX27ADS
223 Include support for MX27ADS platform. This includes specific 220 Include support for MX27ADS platform. This includes specific
224 configurations for the board and its peripherals. 221 configurations for the board and its peripherals.
225 222
226config MACH_PCM038
227 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
228 select IMX_HAVE_PLATFORM_IMX2_WDT
229 select IMX_HAVE_PLATFORM_IMX_I2C
230 select IMX_HAVE_PLATFORM_IMX_UART
231 select IMX_HAVE_PLATFORM_MXC_EHCI
232 select IMX_HAVE_PLATFORM_MXC_NAND
233 select IMX_HAVE_PLATFORM_MXC_W1
234 select IMX_HAVE_PLATFORM_SPI_IMX
235 select USB_ULPI_VIEWPORT if USB_ULPI
236 select SOC_IMX27
237 help
238 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
239 includes specific configurations for the module and its peripherals.
240
241choice
242 prompt "Baseboard"
243 depends on MACH_PCM038
244 default MACH_PCM970_BASEBOARD
245
246config MACH_PCM970_BASEBOARD
247 bool "PHYTEC PCM970 development board"
248 select IMX_HAVE_PLATFORM_IMX_FB
249 select IMX_HAVE_PLATFORM_MXC_MMC
250 help
251 This adds board specific devices that can be found on Phytec's
252 PCM970 evaluation board.
253
254endchoice
255
256config MACH_CPUIMX27
257 bool "Eukrea CPUIMX27 module"
258 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
259 select IMX_HAVE_PLATFORM_IMX2_WDT
260 select IMX_HAVE_PLATFORM_IMX_I2C
261 select IMX_HAVE_PLATFORM_IMX_UART
262 select IMX_HAVE_PLATFORM_MXC_EHCI
263 select IMX_HAVE_PLATFORM_MXC_NAND
264 select IMX_HAVE_PLATFORM_MXC_W1
265 select USB_ULPI_VIEWPORT if USB_ULPI
266 select SOC_IMX27
267 help
268 Include support for Eukrea CPUIMX27 platform. This includes
269 specific configurations for the module and its peripherals.
270
271config MACH_EUKREA_CPUIMX27_USESDHC2
272 bool "CPUIMX27 integrates SDHC2 module"
273 depends on MACH_CPUIMX27
274 select IMX_HAVE_PLATFORM_MXC_MMC
275 help
276 This adds support for the internal SDHC2 used on CPUIMX27
277 for wifi or eMMC.
278
279config MACH_EUKREA_CPUIMX27_USEUART4
280 bool "CPUIMX27 integrates UART4 module"
281 depends on MACH_CPUIMX27
282 help
283 This adds support for the internal UART4 used on CPUIMX27
284 for bluetooth.
285
286choice
287 prompt "Baseboard"
288 depends on MACH_CPUIMX27
289 default MACH_EUKREA_MBIMX27_BASEBOARD
290
291config MACH_EUKREA_MBIMX27_BASEBOARD
292 bool "Eukrea MBIMX27 development board"
293 select IMX_HAVE_PLATFORM_IMX_FB
294 select IMX_HAVE_PLATFORM_IMX_KEYPAD
295 select IMX_HAVE_PLATFORM_IMX_SSI
296 select IMX_HAVE_PLATFORM_IMX_UART
297 select IMX_HAVE_PLATFORM_MXC_MMC
298 select IMX_HAVE_PLATFORM_SPI_IMX
299 select LEDS_GPIO_REGISTER
300 help
301 This adds board specific devices that can be found on Eukrea's
302 MBIMX27 evaluation board.
303
304endchoice
305
306config MACH_MX27_3DS 223config MACH_MX27_3DS
307 bool "MX27PDK platform" 224 bool "MX27PDK platform"
308 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 225 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
@@ -359,18 +276,6 @@ config MACH_PCA100
359 Include support for phyCARD-s (aka pca100) platform. This 276 Include support for phyCARD-s (aka pca100) platform. This
360 includes specific configurations for the module and its peripherals. 277 includes specific configurations for the module and its peripherals.
361 278
362config MACH_MXT_TD60
363 bool "Maxtrack i-MXT TD60"
364 select IMX_HAVE_PLATFORM_IMX_FB
365 select IMX_HAVE_PLATFORM_IMX_I2C
366 select IMX_HAVE_PLATFORM_IMX_UART
367 select IMX_HAVE_PLATFORM_MXC_MMC
368 select IMX_HAVE_PLATFORM_MXC_NAND
369 select SOC_IMX27
370 help
371 Include support for i-MXT (aka td60) platform. This
372 includes specific configurations for the module and its peripherals.
373
374config MACH_IMX27_DT 279config MACH_IMX27_DT
375 bool "Support i.MX27 platforms from device tree" 280 bool "Support i.MX27 platforms from device tree"
376 select SOC_IMX27 281 select SOC_IMX27
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 23c02932bf84..6e4fcd8339cd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
16 16
17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ 17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18 clk-pfd.o clk-busy.o clk.o \ 18 clk-pfd.o clk-busy.o clk.o \
19 clk-fixup-div.o clk-fixup-mux.o 19 clk-fixup-div.o clk-fixup-mux.o \
20 clk-gate-exclusive.o
20 21
21obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 22obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
22obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 23obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
@@ -41,9 +42,9 @@ obj-y += ssi-fiq-ksym.o
41endif 42endif
42 43
43# i.MX1 based machines 44# i.MX1 based machines
44obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
45obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o 45obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
46obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o 46obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
47obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
47 48
48# i.MX21 based machines 49# i.MX21 based machines
49obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 50obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
@@ -56,14 +57,9 @@ obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
56 57
57# i.MX27 based machines 58# i.MX27 based machines
58obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 59obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
59obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
60obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
61obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o 60obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
62obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o 61obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
63obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
64obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
65obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 62obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
66obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
67obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o 63obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
68 64
69# i.MX31 based machines 65# i.MX31 based machines
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 4a40bbb46183..8259a625a920 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -104,6 +104,19 @@ void __init imx_init_revision_from_anatop(void)
104 case 2: 104 case 2:
105 revision = IMX_CHIP_REVISION_1_2; 105 revision = IMX_CHIP_REVISION_1_2;
106 break; 106 break;
107 case 3:
108 revision = IMX_CHIP_REVISION_1_3;
109 break;
110 case 4:
111 revision = IMX_CHIP_REVISION_1_4;
112 break;
113 case 5:
114 /*
115 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
116 * as 'D' in Part Number last character.
117 */
118 revision = IMX_CHIP_REVISION_1_5;
119 break;
107 default: 120 default:
108 revision = IMX_CHIP_REVISION_UNKNOWN; 121 revision = IMX_CHIP_REVISION_UNKNOWN;
109 } 122 }
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 24b103c67f82..1a8932335b21 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -144,7 +144,7 @@ static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
144 if (nivector == 0xffff) 144 if (nivector == 0xffff)
145 break; 145 break;
146 146
147 handle_IRQ(irq_find_mapping(domain, nivector), regs); 147 handle_domain_irq(domain, nivector, regs);
148 } while (1); 148 } while (1);
149} 149}
150 150
diff --git a/arch/arm/mach-imx/board-pcm038.h b/arch/arm/mach-imx/board-pcm038.h
deleted file mode 100644
index 6f371e35753d..000000000000
--- a/arch/arm/mach-imx/board-pcm038.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
20#define __ASM_ARCH_MXC_BOARD_PCM038_H__
21
22#ifndef __ASSEMBLY__
23/*
24 * This CPU module needs a baseboard to work. After basic initializing
25 * its own devices, it calls the baseboard's init function.
26 * TODO: Add your own baseboard init function and call it from
27 * inside pcm038_init().
28 *
29 * This example here is for the development board. Refer pcm970-baseboard.c
30 */
31
32extern void pcm970_baseboard_init(void);
33
34#endif
35
36#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/arch/arm/mach-imx/clk-gate-exclusive.c b/arch/arm/mach-imx/clk-gate-exclusive.c
new file mode 100644
index 000000000000..c12f5f2e04dc
--- /dev/null
+++ b/arch/arm/mach-imx/clk-gate-exclusive.c
@@ -0,0 +1,94 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/slab.h>
13#include "clk.h"
14
15/**
16 * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
17 * exclusive with other gate clocks
18 *
19 * @gate: the parent class
20 * @exclusive_mask: mask of gate bits which are mutually exclusive to this
21 * gate clock
22 *
23 * The imx exclusive gate clock is a subclass of basic clk_gate
24 * with an addtional mask to indicate which other gate bits in the same
25 * register is mutually exclusive to this gate clock.
26 */
27struct clk_gate_exclusive {
28 struct clk_gate gate;
29 u32 exclusive_mask;
30};
31
32static int clk_gate_exclusive_enable(struct clk_hw *hw)
33{
34 struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
35 struct clk_gate_exclusive *exgate = container_of(gate,
36 struct clk_gate_exclusive, gate);
37 u32 val = readl(gate->reg);
38
39 if (val & exgate->exclusive_mask)
40 return -EBUSY;
41
42 return clk_gate_ops.enable(hw);
43}
44
45static void clk_gate_exclusive_disable(struct clk_hw *hw)
46{
47 clk_gate_ops.disable(hw);
48}
49
50static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
51{
52 return clk_gate_ops.is_enabled(hw);
53}
54
55static const struct clk_ops clk_gate_exclusive_ops = {
56 .enable = clk_gate_exclusive_enable,
57 .disable = clk_gate_exclusive_disable,
58 .is_enabled = clk_gate_exclusive_is_enabled,
59};
60
61struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
62 void __iomem *reg, u8 shift, u32 exclusive_mask)
63{
64 struct clk_gate_exclusive *exgate;
65 struct clk_gate *gate;
66 struct clk *clk;
67 struct clk_init_data init;
68
69 if (exclusive_mask == 0)
70 return ERR_PTR(-EINVAL);
71
72 exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
73 if (!exgate)
74 return ERR_PTR(-ENOMEM);
75 gate = &exgate->gate;
76
77 init.name = name;
78 init.ops = &clk_gate_exclusive_ops;
79 init.flags = CLK_SET_RATE_PARENT;
80 init.parent_names = parent ? &parent : NULL;
81 init.num_parents = parent ? 1 : 0;
82
83 gate->reg = reg;
84 gate->bit_idx = shift;
85 gate->lock = &imx_ccm_lock;
86 gate->hw.init = &init;
87 exgate->exclusive_mask = exclusive_mask;
88
89 clk = clk_register(NULL, &gate->hw);
90 if (IS_ERR(clk))
91 kfree(exgate);
92
93 return clk;
94}
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 29d412975aff..1412daf4a714 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -64,7 +64,7 @@ static const char *cko2_sels[] = {
64 "ipu2", "vdo_axi", "osc", "gpu2d_core", 64 "ipu2", "vdo_axi", "osc", "gpu2d_core",
65 "gpu3d_core", "usdhc2", "ssi1", "ssi2", 65 "gpu3d_core", "usdhc2", "ssi1", "ssi2",
66 "ssi3", "gpu3d_shader", "vpu_axi", "can_root", 66 "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
67 "ldb_di0", "ldb_di1", "esai", "eim_slow", 67 "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
68 "uart_serial", "spdif", "asrc", "hsi_tx", 68 "uart_serial", "spdif", "asrc", "hsi_tx",
69}; 69};
70static const char *cko_sels[] = { "cko1", "cko2", }; 70static const char *cko_sels[] = { "cko1", "cko2", };
@@ -73,6 +73,14 @@ static const char *lvds_sels[] = {
73 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", 73 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
74 "pcie_ref_125m", "sata_ref_100m", 74 "pcie_ref_125m", "sata_ref_100m",
75}; 75};
76static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
77static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
78static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
79static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
80static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
81static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
82static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
83static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
76 84
77static struct clk *clk[IMX6QDL_CLK_END]; 85static struct clk *clk[IMX6QDL_CLK_END];
78static struct clk_onecell_data clk_data; 86static struct clk_onecell_data clk_data;
@@ -107,6 +115,10 @@ static struct clk_div_table video_div_table[] = {
107}; 115};
108 116
109static unsigned int share_count_esai; 117static unsigned int share_count_esai;
118static unsigned int share_count_asrc;
119static unsigned int share_count_ssi1;
120static unsigned int share_count_ssi2;
121static unsigned int share_count_ssi3;
110 122
111static void __init imx6q_clocks_init(struct device_node *ccm_node) 123static void __init imx6q_clocks_init(struct device_node *ccm_node)
112{ 124{
@@ -119,6 +131,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
119 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); 131 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
120 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); 132 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
121 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); 133 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
134 /* Clock source from external clock via CLK1/2 PADs */
135 clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
136 clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
122 137
123 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 138 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
124 base = of_iomap(np, 0); 139 base = of_iomap(np, 0);
@@ -132,14 +147,47 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
132 video_div_table[2].div = 1; 147 video_div_table[2].div = 1;
133 }; 148 };
134 149
135 /* type name parent_name base div_mask */ 150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
136 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 151 clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
137 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 152 clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
138 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 153 clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
139 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 154 clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
140 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 155 clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
141 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 156 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
142 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); 157
158 /* type name parent_name base div_mask */
159 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
160 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
161 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
162 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
163 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
164 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
165 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
166
167 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
168 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
169 clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
170 clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
171 clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
172 clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
173 clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
174
175 /* Do not bypass PLLs initially */
176 clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
177 clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
178 clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
179 clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
180 clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
181 clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
182 clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
183
184 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
185 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
186 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
187 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
188 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
189 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
190 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
143 191
144 /* 192 /*
145 * Bit 20 is the reserved and read-only bit, we do this only for: 193 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,8 +224,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
176 * the "output_enable" bit as a gate, even though it's really just 224 * the "output_enable" bit as a gate, even though it's really just
177 * enabling clock output. 225 * enabling clock output.
178 */ 226 */
179 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); 227 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
180 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); 228 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
229
230 clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
231 clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
181 232
182 /* name parent_name reg idx */ 233 /* name parent_name reg idx */
183 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 234 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
@@ -194,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
194 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 245 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
195 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 246 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
196 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); 247 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
248 clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
197 if (cpu_is_imx6dl()) { 249 if (cpu_is_imx6dl()) {
198 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); 250 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
199 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); 251 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
@@ -317,7 +369,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
317 369
318 /* name parent_name reg shift */ 370 /* name parent_name reg shift */
319 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); 371 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
320 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); 372 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
373 clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
374 clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
321 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); 375 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
322 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); 376 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
323 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); 377 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
@@ -331,8 +385,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
331 else 385 else
332 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 386 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
333 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 387 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
334 clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); 388 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
335 clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); 389 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ipg", base + 0x6c, 16, &share_count_esai);
390 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
336 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 391 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
337 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 392 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
338 if (cpu_is_imx6dl()) 393 if (cpu_is_imx6dl())
@@ -388,9 +443,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
388 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 443 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
389 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 444 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
390 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); 445 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
391 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); 446 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
392 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); 447 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
393 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); 448 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
449 clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
450 clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
451 clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
394 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 452 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
395 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 453 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
396 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 454 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
@@ -404,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
404 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
405 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); 463 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
406 464
465 /*
466 * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it
467 * to clock gpt_ipg_per to ease the gpt driver code.
468 */
469 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
470 clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];
471
407 imx_check_clocks(clk, ARRAY_SIZE(clk)); 472 imx_check_clocks(clk, ARRAY_SIZE(clk));
408 473
409 clk_data.clks = clk; 474 clk_data.clks = clk;
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index fef46faf692f..e982ebe10814 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -43,11 +43,13 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy",
43static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 43static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
44static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; 44static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
45static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; 45static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
46static const char *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; 46static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
47static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
47static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; 48static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
48static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; 49static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
49static const char *perclk_sels[] = { "ipg", "osc", }; 50static const char *perclk_sels[] = { "ipg", "osc", };
50static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; 51static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
52static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
51static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; 53static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
52static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; 54static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
53static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; 55static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
@@ -55,6 +57,20 @@ static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_d
55static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; 57static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
56static const char *ecspi_sels[] = { "pll3_60m", "osc", }; 58static const char *ecspi_sels[] = { "pll3_60m", "osc", };
57static const char *uart_sels[] = { "pll3_80m", "osc", }; 59static const char *uart_sels[] = { "pll3_80m", "osc", };
60static const char *lvds_sels[] = {
61 "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
62 "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
63 "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
64 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
65};
66static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
67static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
68static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
69static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
70static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
71static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
72static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
73static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
58 74
59static struct clk_div_table clk_enet_ref_table[] = { 75static struct clk_div_table clk_enet_ref_table[] = {
60 { .val = 0, .div = 20, }, 76 { .val = 0, .div = 20, },
@@ -79,6 +95,10 @@ static struct clk_div_table video_div_table[] = {
79 { } 95 { }
80}; 96};
81 97
98static unsigned int share_count_ssi1;
99static unsigned int share_count_ssi2;
100static unsigned int share_count_ssi3;
101
82static struct clk *clks[IMX6SL_CLK_END]; 102static struct clk *clks[IMX6SL_CLK_END];
83static struct clk_onecell_data clk_data; 103static struct clk_onecell_data clk_data;
84static void __iomem *ccm_base; 104static void __iomem *ccm_base;
@@ -175,20 +195,59 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
175 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 195 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
176 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); 196 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
177 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); 197 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
198 /* Clock source from external clock via CLK1 PAD */
199 clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
178 200
179 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); 201 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
180 base = of_iomap(np, 0); 202 base = of_iomap(np, 0);
181 WARN_ON(!base); 203 WARN_ON(!base);
182 anatop_base = base; 204 anatop_base = base;
183 205
184 /* type name parent base div_mask */ 206 clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
185 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 207 clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
186 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 208 clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
187 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 209 clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
188 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 210 clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
189 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 211 clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
190 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 212 clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
191 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); 213
214 /* type name parent_name base div_mask */
215 clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
216 clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
217 clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
218 clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
219 clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
220 clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
221 clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
222
223 clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
224 clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
225 clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
226 clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
227 clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
228 clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
229 clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
230
231 /* Do not bypass PLLs initially */
232 clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
233 clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
234 clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
235 clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
236 clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
237 clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
238 clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
239
240 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
241 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
242 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
243 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
244 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
245 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
246 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
247
248 clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
249 clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
250 clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
192 251
193 /* 252 /*
194 * usbphy1 and usbphy2 are implemented as dummy gates using reserve 253 * usbphy1 and usbphy2 are implemented as dummy gates using reserve
@@ -241,8 +300,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
241 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); 300 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
242 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); 301 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
243 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 302 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
244 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); 303 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
245 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); 304 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
246 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 305 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
247 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 306 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
248 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 307 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
@@ -251,8 +310,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
251 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 310 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
252 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 311 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
253 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); 312 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
254 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); 313 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
255 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); 314 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
256 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); 315 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
257 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); 316 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
258 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); 317 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
@@ -337,9 +396,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
337 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); 396 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
338 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 397 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
339 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); 398 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
340 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); 399 clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
341 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); 400 clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
342 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); 401 clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
402 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
403 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
404 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
343 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); 405 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
344 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); 406 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
345 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 407 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
@@ -375,6 +437,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
375 /* Audio-related clocks configuration */ 437 /* Audio-related clocks configuration */
376 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); 438 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
377 439
440 /* set PLL5 video as lcdif pix parent clock */
441 clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
442 clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
443
444 clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
445 clks[IMX6SL_CLK_PLL2_PFD2]);
446
378 /* Set initial power mode */ 447 /* Set initial power mode */
379 imx6q_set_lpm(WAIT_CLOCKED); 448 imx6q_set_lpm(WAIT_CLOCKED);
380} 449}
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index ecde72bdfe88..17354a11356f 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -81,6 +81,14 @@ static const char *lvds_sels[] = {
81 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", 81 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
82 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", 82 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
83}; 83};
84static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
85static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
86static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
87static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
88static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
89static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
90static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
91static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
84 92
85static struct clk *clks[IMX6SX_CLK_CLK_END]; 93static struct clk *clks[IMX6SX_CLK_CLK_END];
86static struct clk_onecell_data clk_data; 94static struct clk_onecell_data clk_data;
@@ -143,18 +151,54 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
143 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); 151 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
144 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); 152 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
145 153
154 /* Clock source from external clock via CLK1 PAD */
155 clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
156
146 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); 157 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
147 base = of_iomap(np, 0); 158 base = of_iomap(np, 0);
148 WARN_ON(!base); 159 WARN_ON(!base);
149 160
150 /* type name parent_name base div_mask */ 161 clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
151 clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 162 clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
152 clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 163 clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
153 clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 164 clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
154 clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 165 clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
155 clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 166 clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
156 clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 167 clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
157 clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); 168
169 /* type name parent_name base div_mask */
170 clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
171 clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
172 clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
173 clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
174 clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
175 clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
176 clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
177
178 clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
179 clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
180 clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
181 clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
182 clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
183 clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
184 clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
185
186 /* Do not bypass PLLs initially */
187 clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
188 clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
189 clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
190 clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
191 clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
192 clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
193 clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
194
195 clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
196 clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
197 clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
198 clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
199 clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
200 clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
201 clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
158 202
159 /* 203 /*
160 * Bit 20 is the reserved and read-only bit, we do this only for: 204 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,7 +220,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
176 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5); 220 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
177 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 221 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
178 222
179 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10); 223 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
224 clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
180 225
181 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 226 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
182 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 227 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 61364050fccd..57de74da0acf 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -23,8 +23,6 @@
23#define PLL_DENOM_OFFSET 0x20 23#define PLL_DENOM_OFFSET 0x20
24 24
25#define BM_PLL_POWER (0x1 << 12) 25#define BM_PLL_POWER (0x1 << 12)
26#define BM_PLL_ENABLE (0x1 << 13)
27#define BM_PLL_BYPASS (0x1 << 16)
28#define BM_PLL_LOCK (0x1 << 31) 26#define BM_PLL_LOCK (0x1 << 31)
29 27
30/** 28/**
@@ -84,10 +82,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
84 if (ret) 82 if (ret)
85 return ret; 83 return ret;
86 84
87 val = readl_relaxed(pll->base);
88 val &= ~BM_PLL_BYPASS;
89 writel_relaxed(val, pll->base);
90
91 return 0; 85 return 0;
92} 86}
93 87
@@ -97,7 +91,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
97 u32 val; 91 u32 val;
98 92
99 val = readl_relaxed(pll->base); 93 val = readl_relaxed(pll->base);
100 val |= BM_PLL_BYPASS;
101 if (pll->powerup_set) 94 if (pll->powerup_set)
102 val &= ~BM_PLL_POWER; 95 val &= ~BM_PLL_POWER;
103 else 96 else
@@ -105,28 +98,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
105 writel_relaxed(val, pll->base); 98 writel_relaxed(val, pll->base);
106} 99}
107 100
108static int clk_pllv3_enable(struct clk_hw *hw)
109{
110 struct clk_pllv3 *pll = to_clk_pllv3(hw);
111 u32 val;
112
113 val = readl_relaxed(pll->base);
114 val |= BM_PLL_ENABLE;
115 writel_relaxed(val, pll->base);
116
117 return 0;
118}
119
120static void clk_pllv3_disable(struct clk_hw *hw)
121{
122 struct clk_pllv3 *pll = to_clk_pllv3(hw);
123 u32 val;
124
125 val = readl_relaxed(pll->base);
126 val &= ~BM_PLL_ENABLE;
127 writel_relaxed(val, pll->base);
128}
129
130static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 101static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
131 unsigned long parent_rate) 102 unsigned long parent_rate)
132{ 103{
@@ -169,8 +140,6 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
169static const struct clk_ops clk_pllv3_ops = { 140static const struct clk_ops clk_pllv3_ops = {
170 .prepare = clk_pllv3_prepare, 141 .prepare = clk_pllv3_prepare,
171 .unprepare = clk_pllv3_unprepare, 142 .unprepare = clk_pllv3_unprepare,
172 .enable = clk_pllv3_enable,
173 .disable = clk_pllv3_disable,
174 .recalc_rate = clk_pllv3_recalc_rate, 143 .recalc_rate = clk_pllv3_recalc_rate,
175 .round_rate = clk_pllv3_round_rate, 144 .round_rate = clk_pllv3_round_rate,
176 .set_rate = clk_pllv3_set_rate, 145 .set_rate = clk_pllv3_set_rate,
@@ -225,8 +194,6 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
225static const struct clk_ops clk_pllv3_sys_ops = { 194static const struct clk_ops clk_pllv3_sys_ops = {
226 .prepare = clk_pllv3_prepare, 195 .prepare = clk_pllv3_prepare,
227 .unprepare = clk_pllv3_unprepare, 196 .unprepare = clk_pllv3_unprepare,
228 .enable = clk_pllv3_enable,
229 .disable = clk_pllv3_disable,
230 .recalc_rate = clk_pllv3_sys_recalc_rate, 197 .recalc_rate = clk_pllv3_sys_recalc_rate,
231 .round_rate = clk_pllv3_sys_round_rate, 198 .round_rate = clk_pllv3_sys_round_rate,
232 .set_rate = clk_pllv3_sys_set_rate, 199 .set_rate = clk_pllv3_sys_set_rate,
@@ -299,8 +266,6 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
299static const struct clk_ops clk_pllv3_av_ops = { 266static const struct clk_ops clk_pllv3_av_ops = {
300 .prepare = clk_pllv3_prepare, 267 .prepare = clk_pllv3_prepare,
301 .unprepare = clk_pllv3_unprepare, 268 .unprepare = clk_pllv3_unprepare,
302 .enable = clk_pllv3_enable,
303 .disable = clk_pllv3_disable,
304 .recalc_rate = clk_pllv3_av_recalc_rate, 269 .recalc_rate = clk_pllv3_av_recalc_rate,
305 .round_rate = clk_pllv3_av_round_rate, 270 .round_rate = clk_pllv3_av_round_rate,
306 .set_rate = clk_pllv3_av_set_rate, 271 .set_rate = clk_pllv3_av_set_rate,
@@ -315,8 +280,6 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
315static const struct clk_ops clk_pllv3_enet_ops = { 280static const struct clk_ops clk_pllv3_enet_ops = {
316 .prepare = clk_pllv3_prepare, 281 .prepare = clk_pllv3_prepare,
317 .unprepare = clk_pllv3_unprepare, 282 .unprepare = clk_pllv3_unprepare,
318 .enable = clk_pllv3_enable,
319 .disable = clk_pllv3_disable,
320 .recalc_rate = clk_pllv3_enet_recalc_rate, 283 .recalc_rate = clk_pllv3_enet_recalc_rate,
321}; 284};
322 285
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index f60d6d569ce3..a17818475050 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -58,6 +58,8 @@
58#define PFD_PLL1_BASE (anatop_base + 0x2b0) 58#define PFD_PLL1_BASE (anatop_base + 0x2b0)
59#define PFD_PLL2_BASE (anatop_base + 0x100) 59#define PFD_PLL2_BASE (anatop_base + 0x100)
60#define PFD_PLL3_BASE (anatop_base + 0xf0) 60#define PFD_PLL3_BASE (anatop_base + 0xf0)
61#define PLL3_CTRL (anatop_base + 0x10)
62#define PLL7_CTRL (anatop_base + 0x20)
61 63
62static void __iomem *anatop_base; 64static void __iomem *anatop_base;
63static void __iomem *ccm_base; 65static void __iomem *ccm_base;
@@ -98,9 +100,15 @@ static struct clk_div_table pll4_main_div_table[] = {
98static struct clk *clk[VF610_CLK_END]; 100static struct clk *clk[VF610_CLK_END];
99static struct clk_onecell_data clk_data; 101static struct clk_onecell_data clk_data;
100 102
103static unsigned int const clks_init_on[] __initconst = {
104 VF610_CLK_SYS_BUS,
105 VF610_CLK_DDR_SEL,
106};
107
101static void __init vf610_clocks_init(struct device_node *ccm_node) 108static void __init vf610_clocks_init(struct device_node *ccm_node)
102{ 109{
103 struct device_node *np; 110 struct device_node *np;
111 int i;
104 112
105 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 113 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
106 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); 114 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
@@ -148,6 +156,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
148 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); 156 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
149 /* pll6: default 960Mhz */ 157 /* pll6: default 960Mhz */
150 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); 158 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
159 /* pll7: USB1 PLL at 480MHz */
160 clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
161
151 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); 162 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
152 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); 163 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
153 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); 164 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
@@ -160,8 +171,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
160 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); 171 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
161 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); 172 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
162 173
163 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); 174 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
164 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); 175 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
176
177 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
178 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
165 179
166 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); 180 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
167 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); 181 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
@@ -322,6 +336,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
322 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); 336 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
323 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); 337 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
324 338
339 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
340 clk_prepare_enable(clk[clks_init_on[i]]);
341
325 /* Add the clocks to provider list */ 342 /* Add the clocks to provider list */
326 clk_data.clks = clk; 343 clk_data.clks = clk;
327 clk_data.clk_num = ARRAY_SIZE(clk); 344 clk_data.clk_num = ARRAY_SIZE(clk);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d5ba76fee115..4cdf8b6a74e8 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -36,6 +36,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
36struct clk * imx_obtain_fixed_clock( 36struct clk * imx_obtain_fixed_clock(
37 const char *name, unsigned long rate); 37 const char *name, unsigned long rate);
38 38
39struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
40 void __iomem *reg, u8 shift, u32 exclusive_mask);
41
39static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 42static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
40 void __iomem *reg, u8 shift) 43 void __iomem *reg, u8 shift)
41{ 44{
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 22ba8973bcb9..1dabf435c592 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -98,11 +98,9 @@ void imx_set_cpu_arg(int cpu, u32 arg);
98void v7_secondary_startup(void); 98void v7_secondary_startup(void);
99void imx_scu_map_io(void); 99void imx_scu_map_io(void);
100void imx_smp_prepare(void); 100void imx_smp_prepare(void);
101void imx_scu_standby_enable(void);
102#else 101#else
103static inline void imx_scu_map_io(void) {} 102static inline void imx_scu_map_io(void) {}
104static inline void imx_smp_prepare(void) {} 103static inline void imx_smp_prepare(void) {}
105static inline void imx_scu_standby_enable(void) {}
106#endif 104#endif
107void imx_src_init(void); 105void imx_src_init(void);
108void imx_gpc_init(void); 106void imx_gpc_init(void);
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 10844d3bb926..aa935787b743 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -66,10 +66,6 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
66 66
67int __init imx6q_cpuidle_init(void) 67int __init imx6q_cpuidle_init(void)
68{ 68{
69 /* Need to enable SCU standby for entering WAIT modes */
70 if (!cpu_is_imx6sx())
71 imx_scu_standby_enable();
72
73 /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ 69 /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
74 imx6q_set_int_mem_clk_lpm(true); 70 imx6q_set_int_mem_clk_lpm(true);
75 71
diff --git a/arch/arm/mach-imx/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h
index a21d3313f994..bb2c90d65914 100644
--- a/arch/arm/mach-imx/eukrea-baseboards.h
+++ b/arch/arm/mach-imx/eukrea-baseboards.h
@@ -27,23 +27,15 @@
27 * This CPU module needs a baseboard to work. After basic initializing 27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() 30 * inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init()
31 * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
32 * or eukrea_cpuimx51sd_init().
33 * 31 *
34 * This example here is for the development board. Refer 32 * This example here is for the development board. Refer
35 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 33 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
36 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
37 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 34 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
38 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
39 * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
40 */ 35 */
41 36
42extern void eukrea_mbimxsd25_baseboard_init(void); 37extern void eukrea_mbimxsd25_baseboard_init(void);
43extern void eukrea_mbimx27_baseboard_init(void);
44extern void eukrea_mbimxsd35_baseboard_init(void); 38extern void eukrea_mbimxsd35_baseboard_init(void);
45extern void eukrea_mbimx51_baseboard_init(void);
46extern void eukrea_mbimxsd51_baseboard_init(void);
47 39
48#endif 40#endif
49 41
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
deleted file mode 100644
index b2f08bfbbdd3..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ /dev/null
@@ -1,351 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/gpio.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h>
27#include <linux/backlight.h>
28#include <video/platform_lcd.h>
29
30#include <asm/mach/arch.h>
31
32#include "common.h"
33#include "devices-imx27.h"
34#include "hardware.h"
35#include "iomux-mx27.h"
36
37static const int eukrea_mbimx27_pins[] __initconst = {
38 /* UART2 */
39 PE3_PF_UART2_CTS,
40 PE4_PF_UART2_RTS,
41 PE6_PF_UART2_TXD,
42 PE7_PF_UART2_RXD,
43 /* UART3 */
44 PE8_PF_UART3_TXD,
45 PE9_PF_UART3_RXD,
46 PE10_PF_UART3_CTS,
47 PE11_PF_UART3_RTS,
48 /* UART4 */
49#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
50 PB26_AF_UART4_RTS,
51 PB28_AF_UART4_TXD,
52 PB29_AF_UART4_CTS,
53 PB31_AF_UART4_RXD,
54#endif
55 /* SDHC1*/
56 PE18_PF_SD1_D0,
57 PE19_PF_SD1_D1,
58 PE20_PF_SD1_D2,
59 PE21_PF_SD1_D3,
60 PE22_PF_SD1_CMD,
61 PE23_PF_SD1_CLK,
62 /* display */
63 PA5_PF_LSCLK,
64 PA6_PF_LD0,
65 PA7_PF_LD1,
66 PA8_PF_LD2,
67 PA9_PF_LD3,
68 PA10_PF_LD4,
69 PA11_PF_LD5,
70 PA12_PF_LD6,
71 PA13_PF_LD7,
72 PA14_PF_LD8,
73 PA15_PF_LD9,
74 PA16_PF_LD10,
75 PA17_PF_LD11,
76 PA18_PF_LD12,
77 PA19_PF_LD13,
78 PA20_PF_LD14,
79 PA21_PF_LD15,
80 PA22_PF_LD16,
81 PA23_PF_LD17,
82 PA28_PF_HSYNC,
83 PA29_PF_VSYNC,
84 PA30_PF_CONTRAST,
85 PA31_PF_OE_ACD,
86 /* SPI1 */
87 PD29_PF_CSPI1_SCLK,
88 PD30_PF_CSPI1_MISO,
89 PD31_PF_CSPI1_MOSI,
90 /* SSI4 */
91#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
92 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
93 PC16_PF_SSI4_FS,
94 PC17_PF_SSI4_RXD | GPIO_PUEN,
95 PC18_PF_SSI4_TXD | GPIO_PUEN,
96 PC19_PF_SSI4_CLK,
97#endif
98};
99
100static const uint32_t eukrea_mbimx27_keymap[] = {
101 KEY(0, 0, KEY_UP),
102 KEY(0, 1, KEY_DOWN),
103 KEY(1, 0, KEY_RIGHT),
104 KEY(1, 1, KEY_LEFT),
105};
106
107static const struct matrix_keymap_data
108eukrea_mbimx27_keymap_data __initconst = {
109 .keymap = eukrea_mbimx27_keymap,
110 .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
111};
112
113static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = {
114 {
115 .name = "led1",
116 .default_trigger = "heartbeat",
117 .active_low = 1,
118 .gpio = GPIO_PORTF | 16,
119 },
120 {
121 .name = "led2",
122 .default_trigger = "none",
123 .active_low = 1,
124 .gpio = GPIO_PORTF | 19,
125 },
126};
127
128static const struct gpio_led_platform_data
129 eukrea_mbimx27_gpio_led_info __initconst = {
130 .leds = eukrea_mbimx27_gpio_leds,
131 .num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds),
132};
133
134static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
135 {
136 .mode = {
137 .name = "CMO-QVGA",
138 .refresh = 60,
139 .xres = 320,
140 .yres = 240,
141 .pixclock = 156000,
142 .hsync_len = 30,
143 .left_margin = 38,
144 .right_margin = 20,
145 .vsync_len = 3,
146 .upper_margin = 15,
147 .lower_margin = 4,
148 },
149 .pcr = 0xFAD08B80,
150 .bpp = 16,
151 }, {
152 .mode = {
153 .name = "DVI-VGA",
154 .refresh = 60,
155 .xres = 640,
156 .yres = 480,
157 .pixclock = 32000,
158 .hsync_len = 1,
159 .left_margin = 35,
160 .right_margin = 0,
161 .vsync_len = 1,
162 .upper_margin = 7,
163 .lower_margin = 0,
164 },
165 .pcr = 0xFA208B80,
166 .bpp = 16,
167 }, {
168 .mode = {
169 .name = "DVI-SVGA",
170 .refresh = 60,
171 .xres = 800,
172 .yres = 600,
173 .pixclock = 25000,
174 .hsync_len = 1,
175 .left_margin = 35,
176 .right_margin = 0,
177 .vsync_len = 1,
178 .upper_margin = 7,
179 .lower_margin = 0,
180 },
181 .pcr = 0xFA208B80,
182 .bpp = 16,
183 },
184};
185
186static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
187 .mode = eukrea_mbimx27_modes,
188 .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
189
190 .pwmr = 0x00A903FF,
191 .lscr1 = 0x00120300,
192 .dmacr = 0x00040060,
193};
194
195static void eukrea_mbimx27_bl_set_intensity(int intensity)
196{
197 if (intensity)
198 gpio_direction_output(GPIO_PORTE | 5, 1);
199 else
200 gpio_direction_output(GPIO_PORTE | 5, 0);
201}
202
203static struct generic_bl_info eukrea_mbimx27_bl_info = {
204 .name = "eukrea_mbimx27-bl",
205 .max_intensity = 0xff,
206 .default_intensity = 0xff,
207 .set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
208};
209
210static struct platform_device eukrea_mbimx27_bl_dev = {
211 .name = "generic-bl",
212 .id = 1,
213 .dev = {
214 .platform_data = &eukrea_mbimx27_bl_info,
215 },
216};
217
218static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
219 unsigned int power)
220{
221 if (power)
222 gpio_direction_output(GPIO_PORTA | 25, 1);
223 else
224 gpio_direction_output(GPIO_PORTA | 25, 0);
225}
226
227static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
228 .set_power = eukrea_mbimx27_lcd_power_set,
229};
230
231static struct platform_device eukrea_mbimx27_lcd_powerdev = {
232 .name = "platform-lcd",
233 .dev.platform_data = &eukrea_mbimx27_lcd_power_data,
234};
235
236static const struct imxuart_platform_data uart_pdata __initconst = {
237 .flags = IMXUART_HAVE_RTSCTS,
238};
239
240#define ADS7846_PENDOWN (GPIO_PORTD | 25)
241
242static void __maybe_unused ads7846_dev_init(void)
243{
244 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
245 printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
246 return;
247 }
248 gpio_direction_input(ADS7846_PENDOWN);
249}
250
251static int ads7846_get_pendown_state(void)
252{
253 return !gpio_get_value(ADS7846_PENDOWN);
254}
255
256static struct ads7846_platform_data ads7846_config __initdata = {
257 .get_pendown_state = ads7846_get_pendown_state,
258 .keep_vref_on = 1,
259};
260
261static struct spi_board_info __maybe_unused
262 eukrea_mbimx27_spi_board_info[] __initdata = {
263 [0] = {
264 .modalias = "ads7846",
265 .bus_num = 0,
266 .chip_select = 0,
267 .max_speed_hz = 1500000,
268 /* irq number is run-time assigned */
269 .platform_data = &ads7846_config,
270 .mode = SPI_MODE_2,
271 },
272};
273
274static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
275
276static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
277 .chipselect = eukrea_mbimx27_spi_cs,
278 .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
279};
280
281static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
282 {
283 I2C_BOARD_INFO("tlv320aic23", 0x1a),
284 },
285};
286
287static const struct imxmmc_platform_data sdhc_pdata __initconst = {
288 .dat3_card_detect = 1,
289};
290
291static const
292struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
293 .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
294};
295
296/*
297 * system init for baseboard usage. Will be called by cpuimx27 init.
298 *
299 * Add platform devices present on this baseboard and init
300 * them from CPU side as far as required to use them later on
301 */
302void __init eukrea_mbimx27_baseboard_init(void)
303{
304 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
305 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
306
307 imx27_add_imx_uart1(&uart_pdata);
308 imx27_add_imx_uart2(&uart_pdata);
309#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
310 imx27_add_imx_uart3(&uart_pdata);
311#endif
312
313 imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
314 imx27_add_mxc_mmc(0, &sdhc_pdata);
315
316 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
317 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
318
319 imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
320
321#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
322 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
323 /* ADS7846 Touchscreen controller init */
324 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
325 ads7846_dev_init();
326#endif
327
328 /* SPI_CS0 init */
329 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
330 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
331 eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
332 spi_register_board_info(eukrea_mbimx27_spi_board_info,
333 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
334
335 /* Leds configuration */
336 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
337 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
338 /* Backlight */
339 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
340 gpio_request(GPIO_PORTE | 5, "backlight");
341 platform_device_register(&eukrea_mbimx27_bl_dev);
342 /* LCD Reset */
343 mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
344 gpio_request(GPIO_PORTA | 25, "lcd_enable");
345 platform_device_register(&eukrea_mbimx27_lcd_powerdev);
346
347 imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
348
349 gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
350 imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
351}
diff --git a/arch/arm/mach-imx/imx1-dt.c b/arch/arm/mach-imx/imx1-dt.c
new file mode 100644
index 000000000000..6f915b0961c4
--- /dev/null
+++ b/arch/arm/mach-imx/imx1-dt.c
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/of_platform.h>
11#include <asm/mach/arch.h>
12
13#include "common.h"
14
15static const char * const imx1_dt_board_compat[] __initconst = {
16 "fsl,imx1",
17 NULL
18};
19
20DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
21 .map_io = mx1_map_io,
22 .init_early = imx1_init_early,
23 .init_irq = mx1_init_irq,
24 .dt_compat = imx1_dt_board_compat,
25 .restart = mxc_restart,
26MACHINE_END
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 080e66c6a1d0..dc8f1a6f45f2 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -20,7 +20,7 @@
20 20
21static void __init imx27_dt_init(void) 21static void __init imx27_dt_init(void)
22{ 22{
23 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; 23 struct platform_device_info devinfo = { .name = "cpufreq-dt", };
24 24
25 mxc_arch_reset_init_dt(); 25 mxc_arch_reset_init_dt();
26 26
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 7c66805d2cc0..1657fe64cd0f 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -64,7 +64,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
64 64
65 return ret; 65 return ret;
66} 66}
67EXPORT_SYMBOL(mxc_iomux_mode);
68 67
69/* 68/*
70 * This function configures the pad value for a IOMUX pin. 69 * This function configures the pad value for a IOMUX pin.
@@ -90,7 +89,6 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
90 89
91 spin_unlock(&gpio_mux_lock); 90 spin_unlock(&gpio_mux_lock);
92} 91}
93EXPORT_SYMBOL(mxc_iomux_set_pad);
94 92
95/* 93/*
96 * allocs a single pin: 94 * allocs a single pin:
@@ -116,7 +114,6 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
116 114
117 return 0; 115 return 0;
118} 116}
119EXPORT_SYMBOL(mxc_iomux_alloc_pin);
120 117
121int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, 118int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
122 const char *label) 119 const char *label)
@@ -137,7 +134,6 @@ setup_error:
137 mxc_iomux_release_multiple_pins(pin_list, i); 134 mxc_iomux_release_multiple_pins(pin_list, i);
138 return ret; 135 return ret;
139} 136}
140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
141 137
142void mxc_iomux_release_pin(unsigned int pin) 138void mxc_iomux_release_pin(unsigned int pin)
143{ 139{
@@ -146,7 +142,6 @@ void mxc_iomux_release_pin(unsigned int pin)
146 if (pad < (PIN_MAX + 1)) 142 if (pad < (PIN_MAX + 1))
147 clear_bit(pad, mxc_pin_alloc_map); 143 clear_bit(pad, mxc_pin_alloc_map);
148} 144}
149EXPORT_SYMBOL(mxc_iomux_release_pin);
150 145
151void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) 146void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
152{ 147{
@@ -158,7 +153,6 @@ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
158 p++; 153 p++;
159 } 154 }
160} 155}
161EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
162 156
163/* 157/*
164 * This function enables/disables the general purpose function for a particular 158 * This function enables/disables the general purpose function for a particular
@@ -178,4 +172,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
178 __raw_writel(l, IOMUXGPR); 172 __raw_writel(l, IOMUXGPR);
179 spin_unlock(&gpio_mux_lock); 173 spin_unlock(&gpio_mux_lock);
180} 174}
181EXPORT_SYMBOL(mxc_iomux_set_gpr);
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index 2b156d1d9e21..ecd543664644 100644
--- a/arch/arm/mach-imx/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -153,7 +153,6 @@ int mxc_gpio_mode(int gpio_mode)
153 153
154 return 0; 154 return 0;
155} 155}
156EXPORT_SYMBOL(mxc_gpio_mode);
157 156
158static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) 157static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
159{ 158{
@@ -178,7 +177,6 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
178 ret = imx_iomuxv1_setup_multiple(pin_list, count); 177 ret = imx_iomuxv1_setup_multiple(pin_list, count);
179 return ret; 178 return ret;
180} 179}
181EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
182 180
183int __init imx_iomuxv1_init(void __iomem *base, int numports) 181int __init imx_iomuxv1_init(void __iomem *base, int numports)
184{ 182{
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 9dae74bf47fc..d61f9606fc56 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -55,7 +55,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
55 55
56 return 0; 56 return 0;
57} 57}
58EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
59 58
60int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) 59int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
61{ 60{
@@ -71,7 +70,6 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
71 } 70 }
72 return 0; 71 return 0;
73} 72}
74EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
75 73
76void mxc_iomux_v3_init(void __iomem *iomux_v3_base) 74void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
77{ 75{
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index a7e9bd26a552..f2060523ba48 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -537,7 +537,7 @@ static void __init armadillo5x0_init(void)
537 gpio_free(ARMADILLO5X0_RTC_GPIO); 537 gpio_free(ARMADILLO5X0_RTC_GPIO);
538 } 538 }
539 if (armadillo5x0_i2c_rtc.irq == 0) 539 if (armadillo5x0_i2c_rtc.irq == 0)
540 pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); 540 pr_warn("armadillo5x0_init: failed to get RTC IRQ\n");
541 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); 541 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
542 542
543 /* USB */ 543 /* USB */
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
deleted file mode 100644
index e6d4b9929571..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm038.c which is :
5 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
6 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/mtd/plat-ram.h>
26#include <linux/mtd/physmap.h>
27#include <linux/platform_device.h>
28#include <linux/serial_8250.h>
29#include <linux/usb/otg.h>
30#include <linux/usb/ulpi.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35#include <asm/mach/map.h>
36
37#include "common.h"
38#include "devices-imx27.h"
39#include "ehci.h"
40#include "eukrea-baseboards.h"
41#include "hardware.h"
42#include "iomux-mx27.h"
43#include "ulpi.h"
44
45static const int eukrea_cpuimx27_pins[] __initconst = {
46 /* UART1 */
47 PE12_PF_UART1_TXD,
48 PE13_PF_UART1_RXD,
49 PE14_PF_UART1_CTS,
50 PE15_PF_UART1_RTS,
51 /* UART4 */
52#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
53 PB26_AF_UART4_RTS,
54 PB28_AF_UART4_TXD,
55 PB29_AF_UART4_CTS,
56 PB31_AF_UART4_RXD,
57#endif
58 /* FEC */
59 PD0_AIN_FEC_TXD0,
60 PD1_AIN_FEC_TXD1,
61 PD2_AIN_FEC_TXD2,
62 PD3_AIN_FEC_TXD3,
63 PD4_AOUT_FEC_RX_ER,
64 PD5_AOUT_FEC_RXD1,
65 PD6_AOUT_FEC_RXD2,
66 PD7_AOUT_FEC_RXD3,
67 PD8_AF_FEC_MDIO,
68 PD9_AIN_FEC_MDC,
69 PD10_AOUT_FEC_CRS,
70 PD11_AOUT_FEC_TX_CLK,
71 PD12_AOUT_FEC_RXD0,
72 PD13_AOUT_FEC_RX_DV,
73 PD14_AOUT_FEC_RX_CLK,
74 PD15_AOUT_FEC_COL,
75 PD16_AIN_FEC_TX_ER,
76 PF23_AIN_FEC_TX_EN,
77 /* I2C1 */
78 PD17_PF_I2C_DATA,
79 PD18_PF_I2C_CLK,
80 /* SDHC2 */
81#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
82 PB4_PF_SD2_D0,
83 PB5_PF_SD2_D1,
84 PB6_PF_SD2_D2,
85 PB7_PF_SD2_D3,
86 PB8_PF_SD2_CMD,
87 PB9_PF_SD2_CLK,
88#endif
89#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
90 /* Quad UART's IRQ */
91 GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
92 GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
93 GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
94 GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
95#endif
96 /* OTG */
97 PC7_PF_USBOTG_DATA5,
98 PC8_PF_USBOTG_DATA6,
99 PC9_PF_USBOTG_DATA0,
100 PC10_PF_USBOTG_DATA2,
101 PC11_PF_USBOTG_DATA1,
102 PC12_PF_USBOTG_DATA4,
103 PC13_PF_USBOTG_DATA3,
104 PE0_PF_USBOTG_NXT,
105 PE1_PF_USBOTG_STP,
106 PE2_PF_USBOTG_DIR,
107 PE24_PF_USBOTG_CLK,
108 PE25_PF_USBOTG_DATA7,
109 /* USBH2 */
110 PA0_PF_USBH2_CLK,
111 PA1_PF_USBH2_DIR,
112 PA2_PF_USBH2_DATA7,
113 PA3_PF_USBH2_NXT,
114 PA4_PF_USBH2_STP,
115 PD19_AF_USBH2_DATA4,
116 PD20_AF_USBH2_DATA3,
117 PD21_AF_USBH2_DATA6,
118 PD22_AF_USBH2_DATA0,
119 PD23_AF_USBH2_DATA2,
120 PD24_AF_USBH2_DATA1,
121 PD26_AF_USBH2_DATA5,
122};
123
124static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
125 .width = 2,
126};
127
128static struct resource eukrea_cpuimx27_flash_resource = {
129 .start = 0xc0000000,
130 .end = 0xc3ffffff,
131 .flags = IORESOURCE_MEM,
132};
133
134static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
135 .name = "physmap-flash",
136 .id = 0,
137 .dev = {
138 .platform_data = &eukrea_cpuimx27_flash_data,
139 },
140 .num_resources = 1,
141 .resource = &eukrea_cpuimx27_flash_resource,
142};
143
144static const struct imxuart_platform_data uart_pdata __initconst = {
145 .flags = IMXUART_HAVE_RTSCTS,
146};
147
148static const struct mxc_nand_platform_data
149cpuimx27_nand_board_info __initconst = {
150 .width = 1,
151 .hw_ecc = 1,
152};
153
154static struct platform_device *platform_devices[] __initdata = {
155 &eukrea_cpuimx27_nor_mtd_device,
156};
157
158static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
159 .bitrate = 100000,
160};
161
162static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
163 {
164 I2C_BOARD_INFO("pcf8563", 0x51),
165 },
166};
167
168#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
169static struct plat_serial8250_port serial_platform_data[] = {
170 {
171 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
172 /* irq number is run-time assigned */
173 .uartclk = 14745600,
174 .regshift = 1,
175 .iotype = UPIO_MEM,
176 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
177 }, {
178 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
179 /* irq number is run-time assigned */
180 .uartclk = 14745600,
181 .regshift = 1,
182 .iotype = UPIO_MEM,
183 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
184 }, {
185 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
186 /* irq number is run-time assigned */
187 .uartclk = 14745600,
188 .regshift = 1,
189 .iotype = UPIO_MEM,
190 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
191 }, {
192 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
193 /* irq number is run-time assigned */
194 .uartclk = 14745600,
195 .regshift = 1,
196 .iotype = UPIO_MEM,
197 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
198 }, {
199 }
200};
201
202static struct platform_device serial_device = {
203 .name = "serial8250",
204 .id = 0,
205 .dev = {
206 .platform_data = serial_platform_data,
207 },
208};
209#endif
210
211static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
212{
213 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
214}
215
216static struct mxc_usbh_platform_data otg_pdata __initdata = {
217 .init = eukrea_cpuimx27_otg_init,
218 .portsc = MXC_EHCI_MODE_ULPI,
219};
220
221static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
222{
223 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
224}
225
226static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
227 .init = eukrea_cpuimx27_usbh2_init,
228 .portsc = MXC_EHCI_MODE_ULPI,
229};
230
231static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
232 .operating_mode = FSL_USB2_DR_DEVICE,
233 .phy_mode = FSL_USB2_PHY_ULPI,
234};
235
236static bool otg_mode_host __initdata;
237
238static int __init eukrea_cpuimx27_otg_mode(char *options)
239{
240 if (!strcmp(options, "host"))
241 otg_mode_host = true;
242 else if (!strcmp(options, "device"))
243 otg_mode_host = false;
244 else
245 pr_info("otg_mode neither \"host\" nor \"device\". "
246 "Defaulting to device\n");
247 return 1;
248}
249__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
250
251static void __init eukrea_cpuimx27_init(void)
252{
253 imx27_soc_init();
254
255 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
256 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
257
258 imx27_add_imx_uart0(&uart_pdata);
259
260 imx27_add_mxc_nand(&cpuimx27_nand_board_info);
261
262 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
263 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
264
265 imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
266
267 imx27_add_fec(NULL);
268 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
269 imx27_add_imx2_wdt();
270 imx27_add_mxc_w1();
271
272#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
273 /* SDHC2 can be used for Wifi */
274 imx27_add_mxc_mmc(1, NULL);
275#endif
276#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
277 /* in which case UART4 is also used for Bluetooth */
278 imx27_add_imx_uart3(&uart_pdata);
279#endif
280
281#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
282 serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
283 serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
284 serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
285 serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
286 platform_device_register(&serial_device);
287#endif
288
289 if (otg_mode_host) {
290 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
291 ULPI_OTG_DRVVBUS_EXT);
292 if (otg_pdata.otg)
293 imx27_add_mxc_ehci_otg(&otg_pdata);
294 } else {
295 imx27_add_fsl_usb2_udc(&otg_device_pdata);
296 }
297
298 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
299 ULPI_OTG_DRVVBUS_EXT);
300 if (usbh2_pdata.otg)
301 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
302
303#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
304 eukrea_mbimx27_baseboard_init();
305#endif
306}
307
308static void __init eukrea_cpuimx27_timer_init(void)
309{
310 mx27_clocks_init(26000000);
311}
312
313MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
314 .atag_offset = 0x100,
315 .map_io = mx27_map_io,
316 .init_early = imx27_init_early,
317 .init_irq = mx27_init_irq,
318 .init_time = eukrea_cpuimx27_timer_init,
319 .init_machine = eukrea_cpuimx27_init,
320 .restart = mxc_restart,
321MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c
index c77deb3f0893..2c5fcaf8675b 100644
--- a/arch/arm/mach-imx/mach-imx51.c
+++ b/arch/arm/mach-imx/mach-imx51.c
@@ -51,7 +51,7 @@ static void __init imx51_ipu_mipi_setup(void)
51 51
52static void __init imx51_dt_init(void) 52static void __init imx51_dt_init(void)
53{ 53{
54 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; 54 struct platform_device_info devinfo = { .name = "cpufreq-dt", };
55 55
56 mxc_arch_reset_init_dt(); 56 mxc_arch_reset_init_dt();
57 imx51_ipu_mipi_setup(); 57 imx51_ipu_mipi_setup();
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 673a734165ba..3de3b7369aef 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -42,6 +42,9 @@ static void __init imx6sx_init_irq(void)
42static void __init imx6sx_init_late(void) 42static void __init imx6sx_init_late(void)
43{ 43{
44 imx6q_cpuidle_init(); 44 imx6q_cpuidle_init();
45
46 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
47 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
45} 48}
46 49
47static const char * const imx6sx_dt_compat[] __initconst = { 50static const char * const imx6sx_dt_compat[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
deleted file mode 100644
index 77fda3de4290..000000000000
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * arch/arm/mach-imx/mach-mx1ads.c
3 *
4 * Initially based on:
5 * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
6 * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
7 *
8 * 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/i2c.h>
16#include <linux/i2c/pcf857x.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/time.h>
25
26#include "common.h"
27#include "devices-imx1.h"
28#include "hardware.h"
29#include "iomux-mx1.h"
30
31static const int mx1ads_pins[] __initconst = {
32 /* UART1 */
33 PC9_PF_UART1_CTS,
34 PC10_PF_UART1_RTS,
35 PC11_PF_UART1_TXD,
36 PC12_PF_UART1_RXD,
37 /* UART2 */
38 PB28_PF_UART2_CTS,
39 PB29_PF_UART2_RTS,
40 PB30_PF_UART2_TXD,
41 PB31_PF_UART2_RXD,
42 /* I2C */
43 PA15_PF_I2C_SDA,
44 PA16_PF_I2C_SCL,
45 /* SPI */
46 PC13_PF_SPI1_SPI_RDY,
47 PC14_PF_SPI1_SCLK,
48 PC15_PF_SPI1_SS,
49 PC16_PF_SPI1_MISO,
50 PC17_PF_SPI1_MOSI,
51};
52
53/*
54 * UARTs platform data
55 */
56
57static const struct imxuart_platform_data uart0_pdata __initconst = {
58 .flags = IMXUART_HAVE_RTSCTS,
59};
60
61static const struct imxuart_platform_data uart1_pdata __initconst = {
62 .flags = IMXUART_HAVE_RTSCTS,
63};
64
65/*
66 * Physmap flash
67 */
68
69static const struct physmap_flash_data mx1ads_flash_data __initconst = {
70 .width = 4, /* bankwidth in bytes */
71};
72
73static const struct resource flash_resource __initconst = {
74 .start = MX1_CS0_PHYS,
75 .end = MX1_CS0_PHYS + SZ_32M - 1,
76 .flags = IORESOURCE_MEM,
77};
78
79/*
80 * I2C
81 */
82static struct pcf857x_platform_data pcf857x_data[] = {
83 {
84 .gpio_base = 4 * 32,
85 }, {
86 .gpio_base = 4 * 32 + 16,
87 }
88};
89
90static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
91 .bitrate = 100000,
92};
93
94static struct i2c_board_info mx1ads_i2c_devices[] = {
95 {
96 I2C_BOARD_INFO("pcf8575", 0x22),
97 .platform_data = &pcf857x_data[0],
98 }, {
99 I2C_BOARD_INFO("pcf8575", 0x24),
100 .platform_data = &pcf857x_data[1],
101 },
102};
103
104/*
105 * Board init
106 */
107static void __init mx1ads_init(void)
108{
109 imx1_soc_init();
110
111 mxc_gpio_setup_multiple_pins(mx1ads_pins,
112 ARRAY_SIZE(mx1ads_pins), "mx1ads");
113
114 /* UART */
115 imx1_add_imx_uart0(&uart0_pdata);
116 imx1_add_imx_uart1(&uart1_pdata);
117
118 /* Physmap flash */
119 platform_device_register_resndata(NULL, "physmap-flash", 0,
120 &flash_resource, 1,
121 &mx1ads_flash_data, sizeof(mx1ads_flash_data));
122
123 /* I2C */
124 i2c_register_board_info(0, mx1ads_i2c_devices,
125 ARRAY_SIZE(mx1ads_i2c_devices));
126
127 imx1_add_imx_i2c(&mx1ads_i2c_data);
128}
129
130static void __init mx1ads_timer_init(void)
131{
132 mx1_clocks_init(32000);
133}
134
135MACHINE_START(MX1ADS, "Freescale MX1ADS")
136 /* Maintainer: Sascha Hauer, Pengutronix */
137 .atag_offset = 0x100,
138 .map_io = mx1_map_io,
139 .init_early = imx1_init_early,
140 .init_irq = mx1_init_irq,
141 .init_time = mx1ads_timer_init,
142 .init_machine = mx1ads_init,
143 .restart = mxc_restart,
144MACHINE_END
145
146MACHINE_START(MXLADS, "Freescale MXLADS")
147 .atag_offset = 0x100,
148 .map_io = mx1_map_io,
149 .init_early = imx1_init_early,
150 .init_irq = mx1_init_irq,
151 .init_time = mx1ads_timer_init,
152 .init_machine = mx1ads_init,
153 .restart = mxc_restart,
154MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 453f41a2c5a9..65a0dc06a97c 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -307,7 +307,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
307 ret = gpio_request_array(mx31_3ds_sdhc1_gpios, 307 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
308 ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); 308 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
309 if (ret) { 309 if (ret) {
310 pr_warning("Unable to request the SD/MMC GPIOs.\n"); 310 pr_warn("Unable to request the SD/MMC GPIOs.\n");
311 return ret; 311 return ret;
312 } 312 }
313 313
@@ -316,7 +316,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
316 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 316 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
317 "sdhc1-detect", data); 317 "sdhc1-detect", data);
318 if (ret) { 318 if (ret) {
319 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); 319 pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
320 goto gpio_free; 320 goto gpio_free;
321 } 321 }
322 322
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 57eac6f45fab..4822a1738de4 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -270,7 +270,7 @@ static void __init mx31lite_init(void)
270 /* SMSC9117 IRQ pin */ 270 /* SMSC9117 IRQ pin */
271 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); 271 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
272 if (ret) 272 if (ret)
273 pr_warning("could not get LAN irq gpio\n"); 273 pr_warn("could not get LAN irq gpio\n");
274 else { 274 else {
275 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); 275 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
276 smsc911x_resources[1].start = 276 smsc911x_resources[1].start =
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
deleted file mode 100644
index 0b5d1ca31b9f..000000000000
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ /dev/null
@@ -1,273 +0,0 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_device.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/map.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/physmap.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
28#include <linux/gpio.h>
29#include <linux/platform_data/pca953x.h>
30
31#include "common.h"
32#include "devices-imx27.h"
33#include "hardware.h"
34#include "iomux-mx27.h"
35
36static const int mxt_td60_pins[] __initconst = {
37 /* UART0 */
38 PE12_PF_UART1_TXD,
39 PE13_PF_UART1_RXD,
40 PE14_PF_UART1_CTS,
41 PE15_PF_UART1_RTS,
42 /* UART1 */
43 PE3_PF_UART2_CTS,
44 PE4_PF_UART2_RTS,
45 PE6_PF_UART2_TXD,
46 PE7_PF_UART2_RXD,
47 /* UART2 */
48 PE8_PF_UART3_TXD,
49 PE9_PF_UART3_RXD,
50 PE10_PF_UART3_CTS,
51 PE11_PF_UART3_RTS,
52 /* FEC */
53 PD0_AIN_FEC_TXD0,
54 PD1_AIN_FEC_TXD1,
55 PD2_AIN_FEC_TXD2,
56 PD3_AIN_FEC_TXD3,
57 PD4_AOUT_FEC_RX_ER,
58 PD5_AOUT_FEC_RXD1,
59 PD6_AOUT_FEC_RXD2,
60 PD7_AOUT_FEC_RXD3,
61 PD8_AF_FEC_MDIO,
62 PD9_AIN_FEC_MDC,
63 PD10_AOUT_FEC_CRS,
64 PD11_AOUT_FEC_TX_CLK,
65 PD12_AOUT_FEC_RXD0,
66 PD13_AOUT_FEC_RX_DV,
67 PD14_AOUT_FEC_RX_CLK,
68 PD15_AOUT_FEC_COL,
69 PD16_AIN_FEC_TX_ER,
70 PF23_AIN_FEC_TX_EN,
71 /* I2C1 */
72 PD17_PF_I2C_DATA,
73 PD18_PF_I2C_CLK,
74 /* I2C2 */
75 PC5_PF_I2C2_SDA,
76 PC6_PF_I2C2_SCL,
77 /* FB */
78 PA5_PF_LSCLK,
79 PA6_PF_LD0,
80 PA7_PF_LD1,
81 PA8_PF_LD2,
82 PA9_PF_LD3,
83 PA10_PF_LD4,
84 PA11_PF_LD5,
85 PA12_PF_LD6,
86 PA13_PF_LD7,
87 PA14_PF_LD8,
88 PA15_PF_LD9,
89 PA16_PF_LD10,
90 PA17_PF_LD11,
91 PA18_PF_LD12,
92 PA19_PF_LD13,
93 PA20_PF_LD14,
94 PA21_PF_LD15,
95 PA22_PF_LD16,
96 PA23_PF_LD17,
97 PA25_PF_CLS,
98 PA27_PF_SPL_SPR,
99 PA28_PF_HSYNC,
100 PA29_PF_VSYNC,
101 PA30_PF_CONTRAST,
102 PA31_PF_OE_ACD,
103 /* OWIRE */
104 PE16_AF_OWIRE,
105 /* SDHC1*/
106 PE18_PF_SD1_D0,
107 PE19_PF_SD1_D1,
108 PE20_PF_SD1_D2,
109 PE21_PF_SD1_D3,
110 PE22_PF_SD1_CMD,
111 PE23_PF_SD1_CLK,
112 PF8_AF_ATA_IORDY,
113 /* SDHC2*/
114 PB4_PF_SD2_D0,
115 PB5_PF_SD2_D1,
116 PB6_PF_SD2_D2,
117 PB7_PF_SD2_D3,
118 PB8_PF_SD2_CMD,
119 PB9_PF_SD2_CLK,
120};
121
122static const struct mxc_nand_platform_data
123mxt_td60_nand_board_info __initconst = {
124 .width = 1,
125 .hw_ecc = 1,
126};
127
128static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
129 .bitrate = 100000,
130};
131
132/* PCA9557 */
133static int mxt_td60_pca9557_setup(struct i2c_client *client,
134 unsigned gpio_base, unsigned ngpio,
135 void *context)
136{
137 static int mxt_td60_gpio_value[] = {
138 -1, -1, -1, -1, -1, -1, -1, 1
139 };
140 int n;
141
142 for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
143 gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
144 if (mxt_td60_gpio_value[n] < 0)
145 gpio_direction_input(gpio_base + n);
146 else
147 gpio_direction_output(gpio_base + n,
148 mxt_td60_gpio_value[n]);
149 gpio_export(gpio_base + n, 0);
150 }
151
152 return 0;
153}
154
155static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
156 .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */
157 .invert = 0, /* Do not invert */
158 .setup = mxt_td60_pca9557_setup,
159};
160
161static struct i2c_board_info mxt_td60_i2c_devices[] = {
162 {
163 I2C_BOARD_INFO("pca9557", 0x18),
164 .platform_data = &mxt_td60_pca9557_pdata,
165 },
166};
167
168static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
169 .bitrate = 100000,
170};
171
172static struct i2c_board_info mxt_td60_i2c2_devices[] = {
173};
174
175static struct imx_fb_videomode mxt_td60_modes[] = {
176 {
177 .mode = {
178 .name = "Chimei LW700AT9003",
179 .refresh = 60,
180 .xres = 800,
181 .yres = 480,
182 .pixclock = 30303,
183 .hsync_len = 64,
184 .left_margin = 0x67,
185 .right_margin = 0x68,
186 .vsync_len = 16,
187 .upper_margin = 0x0f,
188 .lower_margin = 0x0f,
189 },
190 .bpp = 16,
191 .pcr = 0xFA208B83,
192 },
193};
194
195static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
196 .mode = mxt_td60_modes,
197 .num_modes = ARRAY_SIZE(mxt_td60_modes),
198
199 /*
200 * - HSYNC active high
201 * - VSYNC active high
202 * - clk notenabled while idle
203 * - clock inverted
204 * - data not inverted
205 * - data enable low active
206 * - enable sharp mode
207 */
208 .pwmr = 0x00A903FF,
209 .lscr1 = 0x00120300,
210 .dmacr = 0x00020010,
211};
212
213static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
214 void *data)
215{
216 return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
217 IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
218}
219
220static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
221{
222 free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
223}
224
225static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
226 .init = mxt_td60_sdhc1_init,
227 .exit = mxt_td60_sdhc1_exit,
228};
229
230static const struct imxuart_platform_data uart_pdata __initconst = {
231 .flags = IMXUART_HAVE_RTSCTS,
232};
233
234static void __init mxt_td60_board_init(void)
235{
236 imx27_soc_init();
237
238 mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
239 "MXT_TD60");
240
241 imx27_add_imx_uart0(&uart_pdata);
242 imx27_add_imx_uart1(&uart_pdata);
243 imx27_add_imx_uart2(&uart_pdata);
244 imx27_add_mxc_nand(&mxt_td60_nand_board_info);
245
246 i2c_register_board_info(0, mxt_td60_i2c_devices,
247 ARRAY_SIZE(mxt_td60_i2c_devices));
248
249 i2c_register_board_info(1, mxt_td60_i2c2_devices,
250 ARRAY_SIZE(mxt_td60_i2c2_devices));
251
252 imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
253 imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
254 imx27_add_imx_fb(&mxt_td60_fb_data);
255 imx27_add_mxc_mmc(0, &sdhc1_pdata);
256 imx27_add_fec(NULL);
257}
258
259static void __init mxt_td60_timer_init(void)
260{
261 mx27_clocks_init(26000000);
262}
263
264MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
265 /* maintainer: Maxtrack Industrial */
266 .atag_offset = 0x100,
267 .map_io = mx27_map_io,
268 .init_early = imx27_init_early,
269 .init_irq = mx27_init_irq,
270 .init_time = mxt_td60_timer_init,
271 .init_machine = mxt_td60_board_init,
272 .restart = mxc_restart,
273MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 8eb1570f7851..6d879417db49 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -58,7 +58,7 @@ static int __init pcm037_variant_setup(char *str)
58 if (!strcmp("eet", str)) 58 if (!strcmp("eet", str))
59 pcm037_instance = PCM037_EET; 59 pcm037_instance = PCM037_EET;
60 else if (strcmp("pcm970", str)) 60 else if (strcmp("pcm970", str))
61 pr_warning("Unknown pcm037 baseboard variant %s\n", str); 61 pr_warn("Unknown pcm037 baseboard variant %s\n", str);
62 62
63 return 1; 63 return 1;
64} 64}
@@ -624,7 +624,7 @@ static void __init pcm037_init(void)
624 /* LAN9217 IRQ pin */ 624 /* LAN9217 IRQ pin */
625 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); 625 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
626 if (ret) 626 if (ret)
627 pr_warning("could not get LAN irq gpio\n"); 627 pr_warn("could not get LAN irq gpio\n");
628 else { 628 else {
629 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); 629 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
630 smsc911x_resources[1].start = 630 smsc911x_resources[1].start =
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
deleted file mode 100644
index ee862ad6b6fc..000000000000
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ /dev/null
@@ -1,358 +0,0 @@
1/*
2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/i2c.h>
21#include <linux/platform_data/at24.h>
22#include <linux/io.h>
23#include <linux/mtd/plat-ram.h>
24#include <linux/mtd/physmap.h>
25#include <linux/platform_device.h>
26#include <linux/regulator/machine.h>
27#include <linux/mfd/mc13783.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
30#include <linux/gpio.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35
36#include "board-pcm038.h"
37#include "common.h"
38#include "devices-imx27.h"
39#include "ehci.h"
40#include "hardware.h"
41#include "iomux-mx27.h"
42#include "ulpi.h"
43
44static const int pcm038_pins[] __initconst = {
45 /* UART1 */
46 PE12_PF_UART1_TXD,
47 PE13_PF_UART1_RXD,
48 PE14_PF_UART1_CTS,
49 PE15_PF_UART1_RTS,
50 /* UART2 */
51 PE3_PF_UART2_CTS,
52 PE4_PF_UART2_RTS,
53 PE6_PF_UART2_TXD,
54 PE7_PF_UART2_RXD,
55 /* UART3 */
56 PE8_PF_UART3_TXD,
57 PE9_PF_UART3_RXD,
58 PE10_PF_UART3_CTS,
59 PE11_PF_UART3_RTS,
60 /* FEC */
61 PD0_AIN_FEC_TXD0,
62 PD1_AIN_FEC_TXD1,
63 PD2_AIN_FEC_TXD2,
64 PD3_AIN_FEC_TXD3,
65 PD4_AOUT_FEC_RX_ER,
66 PD5_AOUT_FEC_RXD1,
67 PD6_AOUT_FEC_RXD2,
68 PD7_AOUT_FEC_RXD3,
69 PD8_AF_FEC_MDIO,
70 PD9_AIN_FEC_MDC,
71 PD10_AOUT_FEC_CRS,
72 PD11_AOUT_FEC_TX_CLK,
73 PD12_AOUT_FEC_RXD0,
74 PD13_AOUT_FEC_RX_DV,
75 PD14_AOUT_FEC_RX_CLK,
76 PD15_AOUT_FEC_COL,
77 PD16_AIN_FEC_TX_ER,
78 PF23_AIN_FEC_TX_EN,
79 /* I2C2 */
80 PC5_PF_I2C2_SDA,
81 PC6_PF_I2C2_SCL,
82 /* SPI1 */
83 PD25_PF_CSPI1_RDY,
84 PD29_PF_CSPI1_SCLK,
85 PD30_PF_CSPI1_MISO,
86 PD31_PF_CSPI1_MOSI,
87 /* SSI1 */
88 PC20_PF_SSI1_FS,
89 PC21_PF_SSI1_RXD,
90 PC22_PF_SSI1_TXD,
91 PC23_PF_SSI1_CLK,
92 /* SSI4 */
93 PC16_PF_SSI4_FS,
94 PC17_PF_SSI4_RXD,
95 PC18_PF_SSI4_TXD,
96 PC19_PF_SSI4_CLK,
97 /* USB host */
98 PA0_PF_USBH2_CLK,
99 PA1_PF_USBH2_DIR,
100 PA2_PF_USBH2_DATA7,
101 PA3_PF_USBH2_NXT,
102 PA4_PF_USBH2_STP,
103 PD19_AF_USBH2_DATA4,
104 PD20_AF_USBH2_DATA3,
105 PD21_AF_USBH2_DATA6,
106 PD22_AF_USBH2_DATA0,
107 PD23_AF_USBH2_DATA2,
108 PD24_AF_USBH2_DATA1,
109 PD26_AF_USBH2_DATA5,
110};
111
112/*
113 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
114 * 16 bit width
115 */
116
117static struct platdata_mtd_ram pcm038_sram_data = {
118 .bankwidth = 2,
119};
120
121static struct resource pcm038_sram_resource = {
122 .start = MX27_CS1_BASE_ADDR,
123 .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
124 .flags = IORESOURCE_MEM,
125};
126
127static struct platform_device pcm038_sram_mtd_device = {
128 .name = "mtd-ram",
129 .id = 0,
130 .dev = {
131 .platform_data = &pcm038_sram_data,
132 },
133 .num_resources = 1,
134 .resource = &pcm038_sram_resource,
135};
136
137/*
138 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
139 * 16 bit width
140 */
141static struct physmap_flash_data pcm038_flash_data = {
142 .width = 2,
143};
144
145static struct resource pcm038_flash_resource = {
146 .start = 0xc0000000,
147 .end = 0xc1ffffff,
148 .flags = IORESOURCE_MEM,
149};
150
151static struct platform_device pcm038_nor_mtd_device = {
152 .name = "physmap-flash",
153 .id = 0,
154 .dev = {
155 .platform_data = &pcm038_flash_data,
156 },
157 .num_resources = 1,
158 .resource = &pcm038_flash_resource,
159};
160
161static const struct imxuart_platform_data uart_pdata __initconst = {
162 .flags = IMXUART_HAVE_RTSCTS,
163};
164
165static const struct mxc_nand_platform_data
166pcm038_nand_board_info __initconst = {
167 .width = 1,
168 .hw_ecc = 1,
169};
170
171static struct platform_device *platform_devices[] __initdata = {
172 &pcm038_nor_mtd_device,
173 &pcm038_sram_mtd_device,
174};
175
176/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
177 * setup other stuffs to access the sram. */
178static void __init pcm038_init_sram(void)
179{
180 __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1)));
181 __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1)));
182 __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1)));
183}
184
185static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
186 .bitrate = 100000,
187};
188
189static struct at24_platform_data board_eeprom = {
190 .byte_len = 4096,
191 .page_size = 32,
192 .flags = AT24_FLAG_ADDR16,
193};
194
195static struct i2c_board_info pcm038_i2c_devices[] = {
196 {
197 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
198 .platform_data = &board_eeprom,
199 }, {
200 I2C_BOARD_INFO("pcf8563", 0x51),
201 }, {
202 I2C_BOARD_INFO("lm75", 0x4a),
203 }
204};
205
206static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
207
208static const struct spi_imx_master pcm038_spi0_data __initconst = {
209 .chipselect = pcm038_spi_cs,
210 .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
211};
212
213static struct regulator_consumer_supply sdhc1_consumers[] = {
214 {
215 .dev_name = "imx21-mmc.1",
216 .supply = "sdhc_vcc",
217 },
218};
219
220static struct regulator_init_data sdhc1_data = {
221 .constraints = {
222 .min_uV = 3000000,
223 .max_uV = 3400000,
224 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
225 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
226 .valid_modes_mask = REGULATOR_MODE_NORMAL |
227 REGULATOR_MODE_FAST,
228 .always_on = 0,
229 .boot_on = 0,
230 },
231 .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers),
232 .consumer_supplies = sdhc1_consumers,
233};
234
235static struct regulator_consumer_supply cam_consumers[] = {
236 {
237 .dev_name = NULL,
238 .supply = "imx_cam_vcc",
239 },
240};
241
242static struct regulator_init_data cam_data = {
243 .constraints = {
244 .min_uV = 3000000,
245 .max_uV = 3400000,
246 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
247 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
248 .valid_modes_mask = REGULATOR_MODE_NORMAL |
249 REGULATOR_MODE_FAST,
250 .always_on = 0,
251 .boot_on = 0,
252 },
253 .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
254 .consumer_supplies = cam_consumers,
255};
256
257static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
258 {
259 .id = MC13783_REG_VCAM,
260 .init_data = &cam_data,
261 }, {
262 .id = MC13783_REG_VMMC1,
263 .init_data = &sdhc1_data,
264 },
265};
266
267static struct mc13xxx_platform_data pcm038_pmic = {
268 .regulators = {
269 .regulators = pcm038_regulators,
270 .num_regulators = ARRAY_SIZE(pcm038_regulators),
271 },
272 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
273};
274
275static struct spi_board_info pcm038_spi_board_info[] __initdata = {
276 {
277 .modalias = "mc13783",
278 /* irq number is run-time assigned */
279 .max_speed_hz = 300000,
280 .bus_num = 0,
281 .chip_select = 0,
282 .platform_data = &pcm038_pmic,
283 .mode = SPI_CS_HIGH,
284 }
285};
286
287static int pcm038_usbh2_init(struct platform_device *pdev)
288{
289 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
290 MXC_EHCI_INTERFACE_DIFF_UNI);
291}
292
293static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
294 .init = pcm038_usbh2_init,
295 .portsc = MXC_EHCI_MODE_ULPI,
296};
297
298static void __init pcm038_init(void)
299{
300 imx27_soc_init();
301
302 mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
303 "PCM038");
304
305 pcm038_init_sram();
306
307 imx27_add_imx_uart0(&uart_pdata);
308 imx27_add_imx_uart1(&uart_pdata);
309 imx27_add_imx_uart2(&uart_pdata);
310
311 mxc_gpio_mode(PE16_AF_OWIRE);
312 imx27_add_mxc_nand(&pcm038_nand_board_info);
313
314 /* only the i2c master 1 is used on this CPU card */
315 i2c_register_board_info(1, pcm038_i2c_devices,
316 ARRAY_SIZE(pcm038_i2c_devices));
317
318 imx27_add_imx_i2c(1, &pcm038_i2c1_data);
319
320 /* PE18 for user-LED D40 */
321 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
322
323 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
324
325 /* MC13783 IRQ */
326 mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
327
328 imx27_add_spi_imx0(&pcm038_spi0_data);
329 pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
330 spi_register_board_info(pcm038_spi_board_info,
331 ARRAY_SIZE(pcm038_spi_board_info));
332
333 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
334
335 imx27_add_fec(NULL);
336 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
337 imx27_add_imx2_wdt();
338 imx27_add_mxc_w1();
339
340#ifdef CONFIG_MACH_PCM970_BASEBOARD
341 pcm970_baseboard_init();
342#endif
343}
344
345static void __init pcm038_timer_init(void)
346{
347 mx27_clocks_init(26000000);
348}
349
350MACHINE_START(PCM038, "phyCORE-i.MX27")
351 .atag_offset = 0x100,
352 .map_io = mx27_map_io,
353 .init_early = imx27_init_early,
354 .init_irq = mx27_init_irq,
355 .init_time = pcm038_timer_init,
356 .init_machine = pcm038_init,
357 .restart = mxc_restart,
358MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index a39b69ef4301..17a41ca65acf 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -43,6 +43,8 @@
43#define IMX_CHIP_REVISION_1_1 0x11 43#define IMX_CHIP_REVISION_1_1 0x11
44#define IMX_CHIP_REVISION_1_2 0x12 44#define IMX_CHIP_REVISION_1_2 0x12
45#define IMX_CHIP_REVISION_1_3 0x13 45#define IMX_CHIP_REVISION_1_3 0x13
46#define IMX_CHIP_REVISION_1_4 0x14
47#define IMX_CHIP_REVISION_1_5 0x15
46#define IMX_CHIP_REVISION_2_0 0x20 48#define IMX_CHIP_REVISION_2_0 0x20
47#define IMX_CHIP_REVISION_2_1 0x21 49#define IMX_CHIP_REVISION_2_1 0x21
48#define IMX_CHIP_REVISION_2_2 0x22 50#define IMX_CHIP_REVISION_2_2 0x22
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
deleted file mode 100644
index 51c608234089..000000000000
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/gpio.h>
20#include <linux/irq.h>
21#include <linux/platform_device.h>
22#include <linux/can/platform/sja1000.h>
23
24#include <asm/mach/arch.h>
25
26#include "common.h"
27#include "devices-imx27.h"
28#include "hardware.h"
29#include "iomux-mx27.h"
30
31static const int pcm970_pins[] __initconst = {
32 /* SDHC */
33 PB4_PF_SD2_D0,
34 PB5_PF_SD2_D1,
35 PB6_PF_SD2_D2,
36 PB7_PF_SD2_D3,
37 PB8_PF_SD2_CMD,
38 PB9_PF_SD2_CLK,
39 /* display */
40 PA5_PF_LSCLK,
41 PA6_PF_LD0,
42 PA7_PF_LD1,
43 PA8_PF_LD2,
44 PA9_PF_LD3,
45 PA10_PF_LD4,
46 PA11_PF_LD5,
47 PA12_PF_LD6,
48 PA13_PF_LD7,
49 PA14_PF_LD8,
50 PA15_PF_LD9,
51 PA16_PF_LD10,
52 PA17_PF_LD11,
53 PA18_PF_LD12,
54 PA19_PF_LD13,
55 PA20_PF_LD14,
56 PA21_PF_LD15,
57 PA22_PF_LD16,
58 PA23_PF_LD17,
59 PA24_PF_REV,
60 PA25_PF_CLS,
61 PA26_PF_PS,
62 PA27_PF_SPL_SPR,
63 PA28_PF_HSYNC,
64 PA29_PF_VSYNC,
65 PA30_PF_CONTRAST,
66 PA31_PF_OE_ACD,
67 /*
68 * it seems the data line misses a pullup, so we must enable
69 * the internal pullup as a local workaround
70 */
71 PD17_PF_I2C_DATA | GPIO_PUEN,
72 PD18_PF_I2C_CLK,
73 /* Camera */
74 PB10_PF_CSI_D0,
75 PB11_PF_CSI_D1,
76 PB12_PF_CSI_D2,
77 PB13_PF_CSI_D3,
78 PB14_PF_CSI_D4,
79 PB15_PF_CSI_MCLK,
80 PB16_PF_CSI_PIXCLK,
81 PB17_PF_CSI_D5,
82 PB18_PF_CSI_D6,
83 PB19_PF_CSI_D7,
84 PB20_PF_CSI_VSYNC,
85 PB21_PF_CSI_HSYNC,
86};
87
88static int pcm970_sdhc2_get_ro(struct device *dev)
89{
90 return gpio_get_value(GPIO_PORTC + 28);
91}
92
93static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
94{
95 int ret;
96
97 ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
98 IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
99 if (ret)
100 return ret;
101
102 ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
103 if (ret) {
104 free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
105 return ret;
106 }
107
108 gpio_direction_input(GPIO_PORTC + 28);
109
110 return 0;
111}
112
113static void pcm970_sdhc2_exit(struct device *dev, void *data)
114{
115 free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
116 gpio_free(GPIO_PORTC + 28);
117}
118
119static const struct imxmmc_platform_data sdhc_pdata __initconst = {
120 .get_ro = pcm970_sdhc2_get_ro,
121 .init = pcm970_sdhc2_init,
122 .exit = pcm970_sdhc2_exit,
123};
124
125static struct imx_fb_videomode pcm970_modes[] = {
126 {
127 .mode = {
128 .name = "Sharp-LQ035Q7",
129 .refresh = 60,
130 .xres = 240,
131 .yres = 320,
132 .pixclock = 188679, /* in ps (5.3MHz) */
133 .hsync_len = 7,
134 .left_margin = 5,
135 .right_margin = 16,
136 .vsync_len = 1,
137 .upper_margin = 7,
138 .lower_margin = 9,
139 },
140 /*
141 * - HSYNC active high
142 * - VSYNC active high
143 * - clk notenabled while idle
144 * - clock not inverted
145 * - data not inverted
146 * - data enable low active
147 * - enable sharp mode
148 */
149 .pcr = 0xF00080C0,
150 .bpp = 16,
151 }, {
152 .mode = {
153 .name = "TX090",
154 .refresh = 60,
155 .xres = 240,
156 .yres = 320,
157 .pixclock = 38255,
158 .left_margin = 144,
159 .right_margin = 0,
160 .upper_margin = 7,
161 .lower_margin = 40,
162 .hsync_len = 96,
163 .vsync_len = 1,
164 },
165 /*
166 * - HSYNC active low (1 << 22)
167 * - VSYNC active low (1 << 23)
168 * - clk notenabled while idle
169 * - clock not inverted
170 * - data not inverted
171 * - data enable low active
172 * - enable sharp mode
173 */
174 .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
175 .bpp = 32,
176 },
177};
178
179static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
180 .mode = pcm970_modes,
181 .num_modes = ARRAY_SIZE(pcm970_modes),
182
183 .pwmr = 0x00A903FF,
184 .lscr1 = 0x00120300,
185 .dmacr = 0x00020010,
186};
187
188static struct resource pcm970_sja1000_resources[] = {
189 {
190 .start = MX27_CS4_BASE_ADDR,
191 .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
192 .flags = IORESOURCE_MEM,
193 }, {
194 /* irq number is run-time assigned */
195 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
196 },
197};
198
199static struct sja1000_platform_data pcm970_sja1000_platform_data = {
200 .osc_freq = 16000000,
201 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
202 .cdr = CDR_CBP,
203};
204
205static struct platform_device pcm970_sja1000 = {
206 .name = "sja1000_platform",
207 .dev = {
208 .platform_data = &pcm970_sja1000_platform_data,
209 },
210 .resource = pcm970_sja1000_resources,
211 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
212};
213
214/*
215 * system init for baseboard usage. Will be called by pcm038 init.
216 *
217 * Add platform devices present on this baseboard and init
218 * them from CPU side as far as required to use them later on
219 */
220void __init pcm970_baseboard_init(void)
221{
222 mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
223 "PCM970");
224
225 imx27_add_imx_fb(&pcm038_fb_data);
226 mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
227 imx27_add_mxc_mmc(1, &sdhc_pdata);
228 pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
229 pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
230 platform_device_register(&pcm970_sja1000);
231}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 5b57c17c06bd..771bd25c1025 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -20,8 +20,6 @@
20#include "common.h" 20#include "common.h"
21#include "hardware.h" 21#include "hardware.h"
22 22
23#define SCU_STANDBY_ENABLE (1 << 5)
24
25u32 g_diag_reg; 23u32 g_diag_reg;
26static void __iomem *scu_base; 24static void __iomem *scu_base;
27 25
@@ -45,14 +43,6 @@ void __init imx_scu_map_io(void)
45 scu_base = IMX_IO_ADDRESS(base); 43 scu_base = IMX_IO_ADDRESS(base);
46} 44}
47 45
48void imx_scu_standby_enable(void)
49{
50 u32 val = readl_relaxed(scu_base);
51
52 val |= SCU_STANDBY_ENABLE;
53 writel_relaxed(val, scu_base);
54}
55
56static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) 46static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
57{ 47{
58 imx_set_cpu_jump(cpu, v7_secondary_startup); 48 imx_set_cpu_jump(cpu, v7_secondary_startup);
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bf92e5a351c0..15d18e198303 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -60,17 +60,22 @@
60#define MX2_TSTAT_CAPT (1 << 1) 60#define MX2_TSTAT_CAPT (1 << 1)
61#define MX2_TSTAT_COMP (1 << 0) 61#define MX2_TSTAT_COMP (1 << 0)
62 62
63/* MX31, MX35, MX25, MX5 */ 63/* MX31, MX35, MX25, MX5, MX6 */
64#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 64#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
65#define V2_TCTL_CLK_IPG (1 << 6) 65#define V2_TCTL_CLK_IPG (1 << 6)
66#define V2_TCTL_CLK_PER (2 << 6) 66#define V2_TCTL_CLK_PER (2 << 6)
67#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
67#define V2_TCTL_FRR (1 << 9) 68#define V2_TCTL_FRR (1 << 9)
69#define V2_TCTL_24MEN (1 << 10)
70#define V2_TPRER_PRE24M 12
68#define V2_IR 0x0c 71#define V2_IR 0x0c
69#define V2_TSTAT 0x08 72#define V2_TSTAT 0x08
70#define V2_TSTAT_OF1 (1 << 0) 73#define V2_TSTAT_OF1 (1 << 0)
71#define V2_TCN 0x24 74#define V2_TCN 0x24
72#define V2_TCMP 0x10 75#define V2_TCMP 0x10
73 76
77#define V2_TIMER_RATE_OSC_DIV8 3000000
78
74#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) 79#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
75#define timer_is_v2() (!timer_is_v1()) 80#define timer_is_v2() (!timer_is_v1())
76 81
@@ -312,10 +317,22 @@ static void __init _mxc_timer_init(int irq,
312 __raw_writel(0, timer_base + MXC_TCTL); 317 __raw_writel(0, timer_base + MXC_TCTL);
313 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 318 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
314 319
315 if (timer_is_v2()) 320 if (timer_is_v2()) {
316 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; 321 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
317 else 322 if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) {
323 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
324 if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
325 /* 24 / 8 = 3 MHz */
326 __raw_writel(7 << V2_TPRER_PRE24M,
327 timer_base + MXC_TPRER);
328 tctl_val |= V2_TCTL_24MEN;
329 }
330 } else {
331 tctl_val |= V2_TCTL_CLK_PER;
332 }
333 } else {
318 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 334 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
335 }
319 336
320 __raw_writel(tctl_val, timer_base + MXC_TCTL); 337 __raw_writel(tctl_val, timer_base + MXC_TCTL);
321 338
@@ -349,9 +366,13 @@ static void __init mxc_timer_init_dt(struct device_node *np)
349 WARN_ON(!timer_base); 366 WARN_ON(!timer_base);
350 irq = irq_of_parse_and_map(np, 0); 367 irq = irq_of_parse_and_map(np, 0);
351 368
352 clk_per = of_clk_get_by_name(np, "per");
353 clk_ipg = of_clk_get_by_name(np, "ipg"); 369 clk_ipg = of_clk_get_by_name(np, "ipg");
354 370
371 /* Try osc_per first, and fall back to per otherwise */
372 clk_per = of_clk_get_by_name(np, "osc_per");
373 if (IS_ERR(clk_per))
374 clk_per = of_clk_get_by_name(np, "per");
375
355 _mxc_timer_init(irq, clk_per, clk_ipg); 376 _mxc_timer_init(irq, clk_per, clk_ipg);
356} 377}
357CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); 378CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 1d4f384ca773..4de65eeda1eb 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -141,8 +141,7 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
141 while (stat) { 141 while (stat) {
142 handled = 1; 142 handled = 1;
143 irqofs = fls(stat) - 1; 143 irqofs = fls(stat) - 1;
144 handle_IRQ(irq_find_mapping(domain, 144 handle_domain_irq(domain, irqofs + i * 32, regs);
145 irqofs + i * 32), regs);
146 stat &= ~(1 << irqofs); 145 stat &= ~(1 << irqofs);
147 } 146 }
148 } 147 }
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 3ce880729cff..38b0da300dd5 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -20,10 +20,13 @@
20#include <linux/mm.h> 20#include <linux/mm.h>
21#include <linux/amba/bus.h> 21#include <linux/amba/bus.h>
22#include <linux/amba/clcd.h> 22#include <linux/amba/clcd.h>
23#include <linux/amba/mmci.h>
24#include <linux/amba/pl061.h>
23#include <linux/io.h> 25#include <linux/io.h>
24#include <linux/platform_data/clk-integrator.h> 26#include <linux/platform_data/clk-integrator.h>
25#include <linux/slab.h> 27#include <linux/slab.h>
26#include <linux/irqchip/arm-vic.h> 28#include <linux/irqchip/arm-vic.h>
29#include <linux/gpio/machine.h>
27 30
28#include <asm/sizes.h> 31#include <asm/sizes.h>
29#include "lm.h" 32#include "lm.h"
@@ -52,6 +55,13 @@ void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
52EXPORT_SYMBOL(impd1_tweak_control); 55EXPORT_SYMBOL(impd1_tweak_control);
53 56
54/* 57/*
58 * MMC support
59 */
60static struct mmci_platform_data mmc_data = {
61 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
62};
63
64/*
55 * CLCD support 65 * CLCD support
56 */ 66 */
57#define PANEL PROSPECTOR 67#define PANEL PROSPECTOR
@@ -291,6 +301,7 @@ static struct impd1_device impd1_devs[] = {
291 .offset = 0x00700000, 301 .offset = 0x00700000,
292 .irq = { 7, 8 }, 302 .irq = { 7, 8 },
293 .id = 0x00041181, 303 .id = 0x00041181,
304 .platform_data = &mmc_data,
294 }, { 305 }, {
295 .offset = 0x00800000, 306 .offset = 0x00800000,
296 .irq = { 9 }, 307 .irq = { 9 },
@@ -372,6 +383,43 @@ static int __init_refok impd1_probe(struct lm_device *dev)
372 383
373 pc_base = dev->resource.start + idev->offset; 384 pc_base = dev->resource.start + idev->offset;
374 snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12); 385 snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
386
387 /* Add GPIO descriptor lookup table for the PL061 block */
388 if (idev->offset == 0x00400000) {
389 struct gpiod_lookup_table *lookup;
390 char *chipname;
391 char *mmciname;
392
393 lookup = devm_kzalloc(&dev->dev,
394 sizeof(*lookup) + 3 * sizeof(struct gpiod_lookup),
395 GFP_KERNEL);
396 chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL);
397 mmciname = kasprintf(GFP_KERNEL, "lm%x:00700", dev->id);
398 lookup->dev_id = mmciname;
399 /*
400 * Offsets on GPIO block 1:
401 * 3 = MMC WP (write protect)
402 * 4 = MMC CD (card detect)
403 *
404 * Offsets on GPIO block 2:
405 * 0 = Up key
406 * 1 = Down key
407 * 2 = Left key
408 * 3 = Right key
409 * 4 = Key lower left
410 * 5 = Key lower right
411 */
412 /* We need the two MMCI GPIO entries */
413 lookup->table[0].chip_label = chipname;
414 lookup->table[0].chip_hwnum = 3;
415 lookup->table[0].con_id = "wp";
416 lookup->table[1].chip_label = chipname;
417 lookup->table[1].chip_hwnum = 4;
418 lookup->table[1].con_id = "cd";
419 lookup->table[1].flags = GPIO_ACTIVE_LOW;
420 gpiod_add_lookup_table(lookup);
421 }
422
375 d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K, 423 d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K,
376 irq1, irq2, 424 irq1, irq2,
377 idev->platform_data, idev->id, 425 idev->platform_data, idev->id,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 05e1f73a1e8d..c186a17c2cff 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -660,6 +660,7 @@ static void __init pci_v3_preinit(void)
660{ 660{
661 unsigned long flags; 661 unsigned long flags;
662 unsigned int temp; 662 unsigned int temp;
663 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
663 664
664 pcibios_min_mem = 0x00100000; 665 pcibios_min_mem = 0x00100000;
665 666
@@ -701,7 +702,7 @@ static void __init pci_v3_preinit(void)
701 /* 702 /*
702 * Setup window 2 - PCI IO 703 * Setup window 2 - PCI IO
703 */ 704 */
704 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) | 705 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
705 V3_LB_BASE_ENABLE); 706 V3_LB_BASE_ENABLE);
706 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); 707 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
707 708
@@ -742,6 +743,7 @@ static void __init pci_v3_preinit(void)
742static void __init pci_v3_postinit(void) 743static void __init pci_v3_postinit(void)
743{ 744{
744 unsigned int pci_cmd; 745 unsigned int pci_cmd;
746 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
745 747
746 pci_cmd = PCI_COMMAND_MEMORY | 748 pci_cmd = PCI_COMMAND_MEMORY |
747 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; 749 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
@@ -758,7 +760,7 @@ static void __init pci_v3_postinit(void)
758 "interrupt: %d\n", ret); 760 "interrupt: %d\n", ret);
759#endif 761#endif
760 762
761 register_isa_ports(non_mem.start, io_mem.start, 0); 763 register_isa_ports(non_mem.start, io_address, 0);
762} 764}
763 765
764/* 766/*
@@ -867,33 +869,32 @@ static int __init pci_v3_probe(struct platform_device *pdev)
867 869
868 for_each_of_pci_range(&parser, &range) { 870 for_each_of_pci_range(&parser, &range) {
869 if (!range.flags) { 871 if (!range.flags) {
870 of_pci_range_to_resource(&range, np, &conf_mem); 872 ret = of_pci_range_to_resource(&range, np, &conf_mem);
871 conf_mem.name = "PCIv3 config"; 873 conf_mem.name = "PCIv3 config";
872 } 874 }
873 if (range.flags & IORESOURCE_IO) { 875 if (range.flags & IORESOURCE_IO) {
874 of_pci_range_to_resource(&range, np, &io_mem); 876 ret = of_pci_range_to_resource(&range, np, &io_mem);
875 io_mem.name = "PCIv3 I/O"; 877 io_mem.name = "PCIv3 I/O";
876 } 878 }
877 if ((range.flags & IORESOURCE_MEM) && 879 if ((range.flags & IORESOURCE_MEM) &&
878 !(range.flags & IORESOURCE_PREFETCH)) { 880 !(range.flags & IORESOURCE_PREFETCH)) {
879 non_mem_pci = range.pci_addr; 881 non_mem_pci = range.pci_addr;
880 non_mem_pci_sz = range.size; 882 non_mem_pci_sz = range.size;
881 of_pci_range_to_resource(&range, np, &non_mem); 883 ret = of_pci_range_to_resource(&range, np, &non_mem);
882 non_mem.name = "PCIv3 non-prefetched mem"; 884 non_mem.name = "PCIv3 non-prefetched mem";
883 } 885 }
884 if ((range.flags & IORESOURCE_MEM) && 886 if ((range.flags & IORESOURCE_MEM) &&
885 (range.flags & IORESOURCE_PREFETCH)) { 887 (range.flags & IORESOURCE_PREFETCH)) {
886 pre_mem_pci = range.pci_addr; 888 pre_mem_pci = range.pci_addr;
887 pre_mem_pci_sz = range.size; 889 pre_mem_pci_sz = range.size;
888 of_pci_range_to_resource(&range, np, &pre_mem); 890 ret = of_pci_range_to_resource(&range, np, &pre_mem);
889 pre_mem.name = "PCIv3 prefetched mem"; 891 pre_mem.name = "PCIv3 prefetched mem";
890 } 892 }
891 }
892 893
893 if (!conf_mem.start || !io_mem.start || 894 if (ret < 0) {
894 !non_mem.start || !pre_mem.start) { 895 dev_err(&pdev->dev, "missing ranges in device node\n");
895 dev_err(&pdev->dev, "missing ranges in device node\n"); 896 return ret;
896 return -EINVAL; 897 }
897 } 898 }
898 899
899 pci_v3.map_irq = of_irq_parse_and_map_pci; 900 pci_v3.map_irq = of_irq_parse_and_map_pci;
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index de03620d7fa7..716e83eb1db8 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -57,20 +57,6 @@ int clk_is_sysclk_mainosc(void)
57} 57}
58 58
59/* 59/*
60 * System reset via the watchdog timer
61 */
62static void lpc32xx_watchdog_reset(void)
63{
64 /* Make sure WDT clocks are enabled */
65 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
66 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
67
68 /* Instant assert of RESETOUT_N with pulse length 1mS */
69 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
70 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
71}
72
73/*
74 * Detects and returns IRAM size for the device variation 60 * Detects and returns IRAM size for the device variation
75 */ 61 */
76#define LPC32XX_IRAM_BANK_SIZE SZ_128K 62#define LPC32XX_IRAM_BANK_SIZE SZ_128K
@@ -210,16 +196,13 @@ void __init lpc32xx_map_io(void)
210 196
211void lpc23xx_restart(enum reboot_mode mode, const char *cmd) 197void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
212{ 198{
213 switch (mode) { 199 /* Make sure WDT clocks are enabled */
214 case REBOOT_SOFT: 200 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
215 case REBOOT_HARD: 201 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
216 lpc32xx_watchdog_reset();
217 break;
218 202
219 default: 203 /* Instant assert of RESETOUT_N with pulse length 1mS */
220 /* Do nothing */ 204 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
221 break; 205 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
222 }
223 206
224 /* Wait for watchdog to reset system */ 207 /* Wait for watchdog to reset system */
225 while (1) 208 while (1)
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
new file mode 100644
index 000000000000..2c1154e1794a
--- /dev/null
+++ b/arch/arm/mach-meson/Kconfig
@@ -0,0 +1,13 @@
1menuconfig ARCH_MESON
2 bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
3 select GENERIC_IRQ_CHIP
4 select ARM_GIC
5
6if ARCH_MESON
7
8config MACH_MESON6
9 bool "Amlogic Meson6 (8726MX) SoCs support"
10 default ARCH_MESON
11 select MESON6_TIMER
12
13endif
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
new file mode 100644
index 000000000000..9d7380eeeedd
--- /dev/null
+++ b/arch/arm/mach-meson/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_ARCH_MESON) += meson.o
diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
new file mode 100644
index 000000000000..5ee064f5a89f
--- /dev/null
+++ b/arch/arm/mach-meson/meson.c
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#include <linux/of_platform.h>
17#include <asm/mach/arch.h>
18
19static const char * const m6_common_board_compat[] = {
20 "amlogic,meson6",
21 NULL,
22};
23
24DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
25 .dt_compat = m6_common_board_compat,
26MACHINE_END
27
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
deleted file mode 100644
index 873c3ca3cd7e..000000000000
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/* linux/arch/arm/mach-msm/board-mahimahi.c
2 *
3 * Copyright (C) 2009 Google, Inc.
4 * Copyright (C) 2009 HTC Corporation.
5 * Author: Dima Zavin <dima@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/delay.h>
19#include <linux/gpio.h>
20#include <linux/init.h>
21#include <linux/input.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/platform_device.h>
25#include <linux/memblock.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/setup.h>
31
32#include <mach/hardware.h>
33
34#include "board-mahimahi.h"
35#include "devices.h"
36#include "proc_comm.h"
37#include "common.h"
38
39static uint debug_uart;
40
41module_param_named(debug_uart, debug_uart, uint, 0);
42
43static struct platform_device *devices[] __initdata = {
44#if !defined(CONFIG_MSM_SERIAL_DEBUGGER)
45 &msm_device_uart1,
46#endif
47 &msm_device_uart_dm1,
48 &msm_device_nand,
49};
50
51static void __init mahimahi_init(void)
52{
53 platform_add_devices(devices, ARRAY_SIZE(devices));
54}
55
56static void __init mahimahi_fixup(struct tag *tags, char **cmdline)
57{
58 memblock_add(PHYS_OFFSET, 219*SZ_1M);
59 memblock_add(MSM_HIGHMEM_BASE, MSM_HIGHMEM_SIZE);
60}
61
62static void __init mahimahi_map_io(void)
63{
64 msm_map_common_io();
65 msm_clock_init();
66}
67
68static void __init mahimahi_init_late(void)
69{
70 smd_debugfs_init();
71}
72
73void msm_timer_init(void);
74
75MACHINE_START(MAHIMAHI, "mahimahi")
76 .atag_offset = 0x100,
77 .fixup = mahimahi_fixup,
78 .map_io = mahimahi_map_io,
79 .init_irq = msm_init_irq,
80 .init_machine = mahimahi_init,
81 .init_late = mahimahi_init_late,
82 .init_time = msm_timer_init,
83MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 245884319d2e..8f5ecdc4f3ce 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -124,7 +124,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
124static struct platform_device *devices[] __initdata = { 124static struct platform_device *devices[] __initdata = {
125 &msm_clock_7x30, 125 &msm_clock_7x30,
126 &msm_device_gpio_7x30, 126 &msm_device_gpio_7x30,
127#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) 127#if defined(CONFIG_SERIAL_MSM)
128 &msm_device_uart2, 128 &msm_device_uart2,
129#endif 129#endif
130 &msm_device_smd, 130 &msm_device_smd,
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 2c25050209ce..722ad63b7edc 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -94,7 +94,7 @@ static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
94 } 94 }
95 95
96static struct msm_gpio_chip msm_gpio_banks[] = { 96static struct msm_gpio_chip msm_gpio_banks[] = {
97#if defined(CONFIG_MSM_DEBUG_UART1) 97#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9a00000)
98 /* H2W pins <-> UART1 */ 98 /* H2W pins <-> UART1 */
99 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40), 99 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),
100#else 100#else
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index f72b07de2152..ba3edd3a46cb 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -88,7 +88,7 @@ static void __init trout_map_io(void)
88 msm_map_common_io(); 88 msm_map_common_io();
89 iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc)); 89 iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
90 90
91#ifdef CONFIG_MSM_DEBUG_UART3 91#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9c00000)
92 /* route UART3 to the "H2W" extended usb connector */ 92 /* route UART3 to the "H2W" extended usb connector */
93 writeb(0x80, TROUT_CPLD_BASE + 0x00); 93 writeb(0x80, TROUT_CPLD_BASE + 0x00);
94#endif 94#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 34e09474636d..b042dca1f633 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -57,8 +57,7 @@ static struct map_desc msm_io_desc[] __initdata = {
57 .length = MSM_SHARED_RAM_SIZE, 57 .length = MSM_SHARED_RAM_SIZE,
58 .type = MT_DEVICE, 58 .type = MT_DEVICE,
59 }, 59 },
60#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 60#if defined(CONFIG_DEBUG_MSM_UART)
61 defined(CONFIG_DEBUG_MSM_UART3)
62 { 61 {
63 /* Must be last: virtual and pfn filled in by debug_ll_addr() */ 62 /* Must be last: virtual and pfn filled in by debug_ll_addr() */
64 .length = SZ_4K, 63 .length = SZ_4K,
@@ -76,8 +75,7 @@ void __init msm_map_common_io(void)
76 * pages are peripheral interface or not. 75 * pages are peripheral interface or not.
77 */ 76 */
78 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); 77 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
79#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 78#if defined(CONFIG_DEBUG_MSM_UART)
80 defined(CONFIG_DEBUG_MSM_UART3)
81#ifdef CONFIG_MMU 79#ifdef CONFIG_MMU
82 debug_ll_addr(&msm_io_desc[size - 1].pfn, 80 debug_ll_addr(&msm_io_desc[size - 1].pfn,
83 &msm_io_desc[size - 1].virtual); 81 &msm_io_desc[size - 1].virtual);
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 8a70a51533fd..bbd8664d1bac 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -644,7 +644,7 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
644 } 644 }
645 } 645 }
646 646
647 platform_device_register_simple("cpufreq-generic", -1, NULL, 0); 647 platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
648 return 0; 648 return 0;
649} 649}
650 650
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 08d4167cc7c5..f4d06aea8460 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -22,7 +22,6 @@ config ARCH_OMAP4
22 bool "TI OMAP4" 22 bool "TI OMAP4"
23 depends on ARCH_MULTI_V7 23 depends on ARCH_MULTI_V7
24 select ARCH_OMAP2PLUS 24 select ARCH_OMAP2PLUS
25 select ARCH_HAS_OPP
26 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 25 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
27 select ARM_CPU_SUSPEND if PM 26 select ARM_CPU_SUSPEND if PM
28 select ARM_ERRATA_720789 27 select ARM_ERRATA_720789
@@ -41,7 +40,6 @@ config SOC_OMAP5
41 bool "TI OMAP5" 40 bool "TI OMAP5"
42 depends on ARCH_MULTI_V7 41 depends on ARCH_MULTI_V7
43 select ARCH_OMAP2PLUS 42 select ARCH_OMAP2PLUS
44 select ARCH_HAS_OPP
45 select ARM_CPU_SUSPEND if PM 43 select ARM_CPU_SUSPEND if PM
46 select ARM_GIC 44 select ARM_GIC
47 select HAVE_ARM_SCU if SMP 45 select HAVE_ARM_SCU if SMP
@@ -53,14 +51,12 @@ config SOC_AM33XX
53 bool "TI AM33XX" 51 bool "TI AM33XX"
54 depends on ARCH_MULTI_V7 52 depends on ARCH_MULTI_V7
55 select ARCH_OMAP2PLUS 53 select ARCH_OMAP2PLUS
56 select ARCH_HAS_OPP
57 select ARM_CPU_SUSPEND if PM 54 select ARM_CPU_SUSPEND if PM
58 55
59config SOC_AM43XX 56config SOC_AM43XX
60 bool "TI AM43x" 57 bool "TI AM43x"
61 depends on ARCH_MULTI_V7 58 depends on ARCH_MULTI_V7
62 select ARCH_OMAP2PLUS 59 select ARCH_OMAP2PLUS
63 select ARCH_HAS_OPP
64 select ARM_GIC 60 select ARM_GIC
65 select MACH_OMAP_GENERIC 61 select MACH_OMAP_GENERIC
66 select MIGHT_HAVE_CACHE_L2X0 62 select MIGHT_HAVE_CACHE_L2X0
@@ -69,7 +65,6 @@ config SOC_DRA7XX
69 bool "TI DRA7XX" 65 bool "TI DRA7XX"
70 depends on ARCH_MULTI_V7 66 depends on ARCH_MULTI_V7
71 select ARCH_OMAP2PLUS 67 select ARCH_OMAP2PLUS
72 select ARCH_HAS_OPP
73 select ARM_CPU_SUSPEND if PM 68 select ARM_CPU_SUSPEND if PM
74 select ARM_GIC 69 select ARM_GIC
75 select HAVE_ARM_ARCH_TIMER 70 select HAVE_ARM_ARCH_TIMER
@@ -88,6 +83,7 @@ config ARCH_OMAP2PLUS
88 select PINCTRL 83 select PINCTRL
89 select SOC_BUS 84 select SOC_BUS
90 select TI_PRIV_EDMA 85 select TI_PRIV_EDMA
86 select OMAP_IRQCHIP
91 help 87 help
92 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 88 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
93 89
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 69bbcba8842f..d9e94122073e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -10,7 +10,6 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ 10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
11 omap_device.o sram.o drm.o 11 omap_device.o sram.o drm.o
12 12
13omap-2-3-common = irq.o
14hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ 13hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
15 omap_hwmod_common_data.o 14 omap_hwmod_common_data.o
16clock-common = clock.o clock_common_data.o \ 15clock-common = clock.o clock_common_data.o \
@@ -20,7 +19,7 @@ secure-common = omap-smc.o omap-secure.o
20obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) 19obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
21obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 20obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
22obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) 21obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 22obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common)
24obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) 23obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) 24obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
26obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) 25obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
@@ -87,9 +86,10 @@ ifeq ($(CONFIG_PM),y)
87obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o 86obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
88obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o 87obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
89obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 88obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
90obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 89omap-4-5-pm-common = pm44xx.o omap-mpuss-lowpower.o
91obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o 90obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
92obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o 91obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
92obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common)
93obj-$(CONFIG_PM_DEBUG) += pm-debug.o 93obj-$(CONFIG_PM_DEBUG) += pm-debug.o
94 94
95obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o 95obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
@@ -102,7 +102,10 @@ endif
102 102
103ifeq ($(CONFIG_CPU_IDLE),y) 103ifeq ($(CONFIG_CPU_IDLE),y)
104obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o 104obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
105obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o 105omap-4-5-idle-common = cpuidle44xx.o
106obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-idle-common)
107obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-idle-common)
108obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-idle-common)
106endif 109endif
107 110
108# PRCM 111# PRCM
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index d95d0ef1354a..d21a3048d06b 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -625,7 +625,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
625 .map_io = omap3_map_io, 625 .map_io = omap3_map_io,
626 .init_early = omap3430_init_early, 626 .init_early = omap3430_init_early,
627 .init_irq = omap3_init_irq, 627 .init_irq = omap3_init_irq,
628 .handle_irq = omap3_intc_handle_irq,
629 .init_machine = omap_3430sdp_init, 628 .init_machine = omap_3430sdp_init,
630 .init_late = omap3430_init_late, 629 .init_late = omap3430_init_late,
631 .init_time = omap3_sync32k_timer_init, 630 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 0d499a1878f6..212c3160de18 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -142,7 +142,6 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
142 .map_io = omap3_map_io, 142 .map_io = omap3_map_io,
143 .init_early = am35xx_init_early, 143 .init_early = am35xx_init_early,
144 .init_irq = omap3_init_irq, 144 .init_irq = omap3_init_irq,
145 .handle_irq = omap3_intc_handle_irq,
146 .init_machine = am3517_crane_init, 145 .init_machine = am3517_crane_init,
147 .init_late = am35xx_init_late, 146 .init_late = am35xx_init_late,
148 .init_time = omap3_sync32k_timer_init, 147 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4f9383cecf76..1c091b3fa312 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -366,7 +366,6 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
366 .map_io = omap3_map_io, 366 .map_io = omap3_map_io,
367 .init_early = am35xx_init_early, 367 .init_early = am35xx_init_early,
368 .init_irq = omap3_init_irq, 368 .init_irq = omap3_init_irq,
369 .handle_irq = omap3_intc_handle_irq,
370 .init_machine = am3517_evm_init, 369 .init_machine = am3517_evm_init,
371 .init_late = am35xx_init_late, 370 .init_late = am35xx_init_late,
372 .init_time = omap3_sync32k_timer_init, 371 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 018353d88b96..c6df8eec4553 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -766,7 +766,6 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
766 .map_io = omap3_map_io, 766 .map_io = omap3_map_io,
767 .init_early = omap35xx_init_early, 767 .init_early = omap35xx_init_early,
768 .init_irq = omap3_init_irq, 768 .init_irq = omap3_init_irq,
769 .handle_irq = omap3_intc_handle_irq,
770 .init_machine = cm_t35_init, 769 .init_machine = cm_t35_init,
771 .init_late = omap35xx_init_late, 770 .init_late = omap35xx_init_late,
772 .init_time = omap3_sync32k_timer_init, 771 .init_time = omap3_sync32k_timer_init,
@@ -779,7 +778,6 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
779 .map_io = omap3_map_io, 778 .map_io = omap3_map_io,
780 .init_early = omap3630_init_early, 779 .init_early = omap3630_init_early,
781 .init_irq = omap3_init_irq, 780 .init_irq = omap3_init_irq,
782 .handle_irq = omap3_intc_handle_irq,
783 .init_machine = cm_t3730_init, 781 .init_machine = cm_t3730_init,
784 .init_late = omap3630_init_late, 782 .init_late = omap3630_init_late,
785 .init_time = omap3_sync32k_timer_init, 783 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 4eb5e6f2f7f5..8a2c1677964c 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -329,7 +329,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
329 .map_io = omap3_map_io, 329 .map_io = omap3_map_io,
330 .init_early = am35xx_init_early, 330 .init_early = am35xx_init_early,
331 .init_irq = omap3_init_irq, 331 .init_irq = omap3_init_irq,
332 .handle_irq = omap3_intc_handle_irq,
333 .init_machine = cm_t3517_init, 332 .init_machine = cm_t3517_init,
334 .init_late = am35xx_init_late, 333 .init_late = am35xx_init_late,
335 .init_time = omap3_gptimer_timer_init, 334 .init_time = omap3_gptimer_timer_init,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index cdc4fb9960a9..d8e4f346936a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -647,7 +647,6 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
647 .map_io = omap3_map_io, 647 .map_io = omap3_map_io,
648 .init_early = omap35xx_init_early, 648 .init_early = omap35xx_init_early,
649 .init_irq = omap3_init_irq, 649 .init_irq = omap3_init_irq,
650 .handle_irq = omap3_intc_handle_irq,
651 .init_machine = devkit8000_init, 650 .init_machine = devkit8000_init,
652 .init_late = omap35xx_init_late, 651 .init_late = omap35xx_init_late,
653 .init_time = omap3_secure_sync32k_timer_init, 652 .init_time = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 9480997ba616..608079a1aba6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -27,7 +27,7 @@
27#define gic_of_init NULL 27#define gic_of_init NULL
28#endif 28#endif
29 29
30static struct of_device_id omap_dt_match_table[] __initdata = { 30static const struct of_device_id omap_dt_match_table[] __initconst = {
31 { .compatible = "simple-bus", }, 31 { .compatible = "simple-bus", },
32 { .compatible = "ti,omap-infra", }, 32 { .compatible = "ti,omap-infra", },
33 { } 33 { }
@@ -43,7 +43,7 @@ static void __init omap_generic_init(void)
43} 43}
44 44
45#ifdef CONFIG_SOC_OMAP2420 45#ifdef CONFIG_SOC_OMAP2420
46static const char *omap242x_boards_compat[] __initconst = { 46static const char *const omap242x_boards_compat[] __initconst = {
47 "ti,omap2420", 47 "ti,omap2420",
48 NULL, 48 NULL,
49}; 49};
@@ -52,8 +52,6 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
52 .reserve = omap_reserve, 52 .reserve = omap_reserve,
53 .map_io = omap242x_map_io, 53 .map_io = omap242x_map_io,
54 .init_early = omap2420_init_early, 54 .init_early = omap2420_init_early,
55 .init_irq = omap_intc_of_init,
56 .handle_irq = omap2_intc_handle_irq,
57 .init_machine = omap_generic_init, 55 .init_machine = omap_generic_init,
58 .init_time = omap2_sync32k_timer_init, 56 .init_time = omap2_sync32k_timer_init,
59 .dt_compat = omap242x_boards_compat, 57 .dt_compat = omap242x_boards_compat,
@@ -62,7 +60,7 @@ MACHINE_END
62#endif 60#endif
63 61
64#ifdef CONFIG_SOC_OMAP2430 62#ifdef CONFIG_SOC_OMAP2430
65static const char *omap243x_boards_compat[] __initconst = { 63static const char *const omap243x_boards_compat[] __initconst = {
66 "ti,omap2430", 64 "ti,omap2430",
67 NULL, 65 NULL,
68}; 66};
@@ -71,8 +69,6 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
71 .reserve = omap_reserve, 69 .reserve = omap_reserve,
72 .map_io = omap243x_map_io, 70 .map_io = omap243x_map_io,
73 .init_early = omap2430_init_early, 71 .init_early = omap2430_init_early,
74 .init_irq = omap_intc_of_init,
75 .handle_irq = omap2_intc_handle_irq,
76 .init_machine = omap_generic_init, 72 .init_machine = omap_generic_init,
77 .init_time = omap2_sync32k_timer_init, 73 .init_time = omap2_sync32k_timer_init,
78 .dt_compat = omap243x_boards_compat, 74 .dt_compat = omap243x_boards_compat,
@@ -81,7 +77,7 @@ MACHINE_END
81#endif 77#endif
82 78
83#ifdef CONFIG_ARCH_OMAP3 79#ifdef CONFIG_ARCH_OMAP3
84static const char *omap3_boards_compat[] __initconst = { 80static const char *const omap3_boards_compat[] __initconst = {
85 "ti,omap3430", 81 "ti,omap3430",
86 "ti,omap3", 82 "ti,omap3",
87 NULL, 83 NULL,
@@ -91,8 +87,6 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
91 .reserve = omap_reserve, 87 .reserve = omap_reserve,
92 .map_io = omap3_map_io, 88 .map_io = omap3_map_io,
93 .init_early = omap3430_init_early, 89 .init_early = omap3430_init_early,
94 .init_irq = omap_intc_of_init,
95 .handle_irq = omap3_intc_handle_irq,
96 .init_machine = omap_generic_init, 90 .init_machine = omap_generic_init,
97 .init_late = omap3_init_late, 91 .init_late = omap3_init_late,
98 .init_time = omap3_sync32k_timer_init, 92 .init_time = omap3_sync32k_timer_init,
@@ -100,7 +94,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
100 .restart = omap3xxx_restart, 94 .restart = omap3xxx_restart,
101MACHINE_END 95MACHINE_END
102 96
103static const char *omap36xx_boards_compat[] __initconst = { 97static const char *const omap36xx_boards_compat[] __initconst = {
104 "ti,omap36xx", 98 "ti,omap36xx",
105 NULL, 99 NULL,
106}; 100};
@@ -109,8 +103,6 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
109 .reserve = omap_reserve, 103 .reserve = omap_reserve,
110 .map_io = omap3_map_io, 104 .map_io = omap3_map_io,
111 .init_early = omap3630_init_early, 105 .init_early = omap3630_init_early,
112 .init_irq = omap_intc_of_init,
113 .handle_irq = omap3_intc_handle_irq,
114 .init_machine = omap_generic_init, 106 .init_machine = omap_generic_init,
115 .init_late = omap3_init_late, 107 .init_late = omap3_init_late,
116 .init_time = omap3_sync32k_timer_init, 108 .init_time = omap3_sync32k_timer_init,
@@ -118,7 +110,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
118 .restart = omap3xxx_restart, 110 .restart = omap3xxx_restart,
119MACHINE_END 111MACHINE_END
120 112
121static const char *omap3_gp_boards_compat[] __initconst = { 113static const char *const omap3_gp_boards_compat[] __initconst = {
122 "ti,omap3-beagle", 114 "ti,omap3-beagle",
123 "timll,omap3-devkit8000", 115 "timll,omap3-devkit8000",
124 NULL, 116 NULL,
@@ -128,8 +120,6 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
128 .reserve = omap_reserve, 120 .reserve = omap_reserve,
129 .map_io = omap3_map_io, 121 .map_io = omap3_map_io,
130 .init_early = omap3430_init_early, 122 .init_early = omap3430_init_early,
131 .init_irq = omap_intc_of_init,
132 .handle_irq = omap3_intc_handle_irq,
133 .init_machine = omap_generic_init, 123 .init_machine = omap_generic_init,
134 .init_late = omap3_init_late, 124 .init_late = omap3_init_late,
135 .init_time = omap3_secure_sync32k_timer_init, 125 .init_time = omap3_secure_sync32k_timer_init,
@@ -137,7 +127,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
137 .restart = omap3xxx_restart, 127 .restart = omap3xxx_restart,
138MACHINE_END 128MACHINE_END
139 129
140static const char *am3517_boards_compat[] __initconst = { 130static const char *const am3517_boards_compat[] __initconst = {
141 "ti,am3517", 131 "ti,am3517",
142 NULL, 132 NULL,
143}; 133};
@@ -146,8 +136,6 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
146 .reserve = omap_reserve, 136 .reserve = omap_reserve,
147 .map_io = omap3_map_io, 137 .map_io = omap3_map_io,
148 .init_early = am35xx_init_early, 138 .init_early = am35xx_init_early,
149 .init_irq = omap_intc_of_init,
150 .handle_irq = omap3_intc_handle_irq,
151 .init_machine = omap_generic_init, 139 .init_machine = omap_generic_init,
152 .init_late = omap3_init_late, 140 .init_late = omap3_init_late,
153 .init_time = omap3_gptimer_timer_init, 141 .init_time = omap3_gptimer_timer_init,
@@ -157,7 +145,7 @@ MACHINE_END
157#endif 145#endif
158 146
159#ifdef CONFIG_SOC_AM33XX 147#ifdef CONFIG_SOC_AM33XX
160static const char *am33xx_boards_compat[] __initconst = { 148static const char *const am33xx_boards_compat[] __initconst = {
161 "ti,am33xx", 149 "ti,am33xx",
162 NULL, 150 NULL,
163}; 151};
@@ -166,8 +154,6 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
166 .reserve = omap_reserve, 154 .reserve = omap_reserve,
167 .map_io = am33xx_map_io, 155 .map_io = am33xx_map_io,
168 .init_early = am33xx_init_early, 156 .init_early = am33xx_init_early,
169 .init_irq = omap_intc_of_init,
170 .handle_irq = omap3_intc_handle_irq,
171 .init_machine = omap_generic_init, 157 .init_machine = omap_generic_init,
172 .init_late = am33xx_init_late, 158 .init_late = am33xx_init_late,
173 .init_time = omap3_gptimer_timer_init, 159 .init_time = omap3_gptimer_timer_init,
@@ -177,7 +163,7 @@ MACHINE_END
177#endif 163#endif
178 164
179#ifdef CONFIG_ARCH_OMAP4 165#ifdef CONFIG_ARCH_OMAP4
180static const char *omap4_boards_compat[] __initconst = { 166static const char *const omap4_boards_compat[] __initconst = {
181 "ti,omap4460", 167 "ti,omap4460",
182 "ti,omap4430", 168 "ti,omap4430",
183 "ti,omap4", 169 "ti,omap4",
@@ -199,7 +185,7 @@ MACHINE_END
199#endif 185#endif
200 186
201#ifdef CONFIG_SOC_OMAP5 187#ifdef CONFIG_SOC_OMAP5
202static const char *omap5_boards_compat[] __initconst = { 188static const char *const omap5_boards_compat[] __initconst = {
203 "ti,omap5432", 189 "ti,omap5432",
204 "ti,omap5430", 190 "ti,omap5430",
205 "ti,omap5", 191 "ti,omap5",
@@ -221,7 +207,7 @@ MACHINE_END
221#endif 207#endif
222 208
223#ifdef CONFIG_SOC_AM43XX 209#ifdef CONFIG_SOC_AM43XX
224static const char *am43_boards_compat[] __initconst = { 210static const char *const am43_boards_compat[] __initconst = {
225 "ti,am4372", 211 "ti,am4372",
226 "ti,am43", 212 "ti,am43",
227 NULL, 213 NULL,
@@ -240,7 +226,9 @@ MACHINE_END
240#endif 226#endif
241 227
242#ifdef CONFIG_SOC_DRA7XX 228#ifdef CONFIG_SOC_DRA7XX
243static const char *dra74x_boards_compat[] __initconst = { 229static const char *const dra74x_boards_compat[] __initconst = {
230 "ti,am5728",
231 "ti,am5726",
244 "ti,dra742", 232 "ti,dra742",
245 "ti,dra7", 233 "ti,dra7",
246 NULL, 234 NULL,
@@ -259,7 +247,9 @@ DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
259 .restart = omap44xx_restart, 247 .restart = omap44xx_restart,
260MACHINE_END 248MACHINE_END
261 249
262static const char *dra72x_boards_compat[] __initconst = { 250static const char *const dra72x_boards_compat[] __initconst = {
251 "ti,am5718",
252 "ti,am5716",
263 "ti,dra722", 253 "ti,dra722",
264 NULL, 254 NULL,
265}; 255};
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 44a59c3abfb0..c2975af4cd5d 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -422,7 +422,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
422 .map_io = omap3_map_io, 422 .map_io = omap3_map_io,
423 .init_early = omap3430_init_early, 423 .init_early = omap3430_init_early,
424 .init_irq = omap3_init_irq, 424 .init_irq = omap3_init_irq,
425 .handle_irq = omap3_intc_handle_irq,
426 .init_machine = omap_ldp_init, 425 .init_machine = omap_ldp_init,
427 .init_late = omap3430_init_late, 426 .init_late = omap3430_init_late,
428 .init_time = omap3_sync32k_timer_init, 427 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index aead77a4bc6d..97767a27ca9d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -33,6 +33,7 @@
33#include "mmc.h" 33#include "mmc.h"
34#include "soc.h" 34#include "soc.h"
35#include "gpmc-onenand.h" 35#include "gpmc-onenand.h"
36#include "common-board-devices.h"
36 37
37#define TUSB6010_ASYNC_CS 1 38#define TUSB6010_ASYNC_CS 1
38#define TUSB6010_SYNC_CS 4 39#define TUSB6010_SYNC_CS 4
@@ -568,29 +569,14 @@ static int n8x0_menelaus_late_init(struct device *dev)
568} 569}
569#endif 570#endif
570 571
571static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { 572struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
572 .late_init = n8x0_menelaus_late_init, 573 .late_init = n8x0_menelaus_late_init,
573}; 574};
574 575
575static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { 576struct aic3x_pdata n810_aic33_data __initdata = {
576 {
577 I2C_BOARD_INFO("menelaus", 0x72),
578 .irq = 7 + OMAP_INTC_START,
579 .platform_data = &n8x0_menelaus_platform_data,
580 },
581};
582
583static struct aic3x_pdata n810_aic33_data __initdata = {
584 .gpio_reset = 118, 577 .gpio_reset = 118,
585}; 578};
586 579
587static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
588 {
589 I2C_BOARD_INFO("tlv320aic3x", 0x18),
590 .platform_data = &n810_aic33_data,
591 },
592};
593
594static int __init n8x0_late_initcall(void) 580static int __init n8x0_late_initcall(void)
595{ 581{
596 if (!board_caps) 582 if (!board_caps)
@@ -612,11 +598,5 @@ void * __init n8x0_legacy_init(void)
612 board_check_revision(); 598 board_check_revision();
613 spi_register_board_info(n800_spi_board_info, 599 spi_register_board_info(n800_spi_board_info,
614 ARRAY_SIZE(n800_spi_board_info)); 600 ARRAY_SIZE(n800_spi_board_info));
615 i2c_register_board_info(0, n8x0_i2c_board_info_1,
616 ARRAY_SIZE(n8x0_i2c_board_info_1));
617 if (board_is_n810())
618 i2c_register_board_info(1, n810_i2c_board_info_2,
619 ARRAY_SIZE(n810_i2c_board_info_2));
620
621 return &mmc1_data; 601 return &mmc1_data;
622} 602}
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index e2e52031f056..81de1c68b360 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -588,7 +588,6 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
588 .map_io = omap3_map_io, 588 .map_io = omap3_map_io,
589 .init_early = omap3_init_early, 589 .init_early = omap3_init_early,
590 .init_irq = omap3_init_irq, 590 .init_irq = omap3_init_irq,
591 .handle_irq = omap3_intc_handle_irq,
592 .init_machine = omap3_beagle_init, 591 .init_machine = omap3_beagle_init,
593 .init_late = omap3_init_late, 592 .init_late = omap3_init_late,
594 .init_time = omap3_secure_sync32k_timer_init, 593 .init_time = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index bab51e64c4b5..6049f60a8813 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -230,7 +230,6 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
230 .map_io = omap3_map_io, 230 .map_io = omap3_map_io,
231 .init_early = omap35xx_init_early, 231 .init_early = omap35xx_init_early,
232 .init_irq = omap3_init_irq, 232 .init_irq = omap3_init_irq,
233 .handle_irq = omap3_intc_handle_irq,
234 .init_machine = omap3logic_init, 233 .init_machine = omap3logic_init,
235 .init_late = omap35xx_init_late, 234 .init_late = omap35xx_init_late,
236 .init_time = omap3_sync32k_timer_init, 235 .init_time = omap3_sync32k_timer_init,
@@ -243,7 +242,6 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
243 .map_io = omap3_map_io, 242 .map_io = omap3_map_io,
244 .init_early = omap35xx_init_early, 243 .init_early = omap35xx_init_early,
245 .init_irq = omap3_init_irq, 244 .init_irq = omap3_init_irq,
246 .handle_irq = omap3_intc_handle_irq,
247 .init_machine = omap3logic_init, 245 .init_machine = omap3logic_init,
248 .init_late = omap35xx_init_late, 246 .init_late = omap35xx_init_late,
249 .init_time = omap3_sync32k_timer_init, 247 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index cf18340eb3bb..f32201656cf3 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -624,7 +624,6 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
624 .map_io = omap3_map_io, 624 .map_io = omap3_map_io,
625 .init_early = omap35xx_init_early, 625 .init_early = omap35xx_init_early,
626 .init_irq = omap3_init_irq, 626 .init_irq = omap3_init_irq,
627 .handle_irq = omap3_intc_handle_irq,
628 .init_machine = omap3pandora_init, 627 .init_machine = omap3pandora_init,
629 .init_late = omap35xx_init_late, 628 .init_late = omap35xx_init_late,
630 .init_time = omap3_sync32k_timer_init, 629 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index a2e035e0792a..6311f4b1ee44 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -426,7 +426,6 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
426 .map_io = omap3_map_io, 426 .map_io = omap3_map_io,
427 .init_early = omap35xx_init_early, 427 .init_early = omap35xx_init_early,
428 .init_irq = omap3_init_irq, 428 .init_irq = omap3_init_irq,
429 .handle_irq = omap3_intc_handle_irq,
430 .init_machine = omap3_stalker_init, 429 .init_machine = omap3_stalker_init,
431 .init_late = omap35xx_init_late, 430 .init_late = omap35xx_init_late,
432 .init_time = omap3_secure_sync32k_timer_init, 431 .init_time = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 70b904c010c6..a01993e5500f 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -388,7 +388,6 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
388 .map_io = omap3_map_io, 388 .map_io = omap3_map_io,
389 .init_early = omap3430_init_early, 389 .init_early = omap3430_init_early,
390 .init_irq = omap3_init_irq, 390 .init_irq = omap3_init_irq,
391 .handle_irq = omap3_intc_handle_irq,
392 .init_machine = omap3_touchbook_init, 391 .init_machine = omap3_touchbook_init,
393 .init_late = omap3430_init_late, 392 .init_late = omap3430_init_late,
394 .init_time = omap3_secure_sync32k_timer_init, 393 .init_time = omap3_secure_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index f6d384111911..2dae6ccd39bb 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -564,7 +564,6 @@ MACHINE_START(OVERO, "Gumstix Overo")
564 .map_io = omap3_map_io, 564 .map_io = omap3_map_io,
565 .init_early = omap35xx_init_early, 565 .init_early = omap35xx_init_early,
566 .init_irq = omap3_init_irq, 566 .init_irq = omap3_init_irq,
567 .handle_irq = omap3_intc_handle_irq,
568 .init_machine = overo_init, 567 .init_machine = overo_init,
569 .init_late = omap35xx_init_late, 568 .init_late = omap35xx_init_late,
570 .init_time = omap3_sync32k_timer_init, 569 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index db168c9627a1..2d1e5a6beb85 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -134,7 +134,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
134 .map_io = omap3_map_io, 134 .map_io = omap3_map_io,
135 .init_early = omap3430_init_early, 135 .init_early = omap3430_init_early,
136 .init_irq = omap3_init_irq, 136 .init_irq = omap3_init_irq,
137 .handle_irq = omap3_intc_handle_irq,
138 .init_machine = rx51_init, 137 .init_machine = rx51_init,
139 .init_late = omap3430_init_late, 138 .init_late = omap3430_init_late,
140 .init_time = omap3_sync32k_timer_init, 139 .init_time = omap3_sync32k_timer_init,
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index f338177e6900..07c88ae083fb 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -1,6 +1,8 @@
1#ifndef __OMAP_COMMON_BOARD_DEVICES__ 1#ifndef __OMAP_COMMON_BOARD_DEVICES__
2#define __OMAP_COMMON_BOARD_DEVICES__ 2#define __OMAP_COMMON_BOARD_DEVICES__
3 3
4#include <sound/tlv320aic3x.h>
5#include <linux/mfd/menelaus.h>
4#include "twl-common.h" 6#include "twl-common.h"
5 7
6#define NAND_BLOCK_SIZE SZ_128K 8#define NAND_BLOCK_SIZE SZ_128K
@@ -12,4 +14,7 @@ void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
12 struct ads7846_platform_data *board_pdata); 14 struct ads7846_platform_data *board_pdata);
13void *n8x0_legacy_init(void); 15void *n8x0_legacy_init(void);
14 16
17extern struct menelaus_platform_data n8x0_menelaus_platform_data;
18extern struct aic3x_pdata n810_aic33_data;
19
15#endif /* __OMAP_COMMON_BOARD_DEVICES__ */ 20#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index dc571f1d3b8a..377eea849e7b 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -32,6 +32,7 @@
32#include <linux/i2c/twl.h> 32#include <linux/i2c/twl.h>
33#include <linux/i2c-omap.h> 33#include <linux/i2c-omap.h>
34#include <linux/reboot.h> 34#include <linux/reboot.h>
35#include <linux/irqchip/irq-omap-intc.h>
35 36
36#include <asm/proc-fns.h> 37#include <asm/proc-fns.h>
37 38
@@ -60,7 +61,7 @@ static inline int omap3_pm_init(void)
60} 61}
61#endif 62#endif
62 63
63#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) 64#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
64int omap4_pm_init(void); 65int omap4_pm_init(void);
65int omap4_pm_init_early(void); 66int omap4_pm_init_early(void);
66#else 67#else
@@ -210,18 +211,6 @@ extern struct device *omap2_get_iva_device(void);
210extern struct device *omap2_get_l3_device(void); 211extern struct device *omap2_get_l3_device(void);
211extern struct device *omap4_get_dsp_device(void); 212extern struct device *omap4_get_dsp_device(void);
212 213
213void omap2_init_irq(void);
214void omap3_init_irq(void);
215void ti81xx_init_irq(void);
216extern int omap_irq_pending(void);
217void omap_intc_save_context(void);
218void omap_intc_restore_context(void);
219void omap3_intc_suspend(void);
220void omap3_intc_prepare_idle(void);
221void omap3_intc_resume_idle(void);
222void omap2_intc_handle_irq(struct pt_regs *regs);
223void omap3_intc_handle_irq(struct pt_regs *regs);
224void omap_intc_of_init(void);
225void omap_gic_of_init(void); 214void omap_gic_of_init(void);
226 215
227#ifdef CONFIG_CACHE_L2X0 216#ifdef CONFIG_CACHE_L2X0
@@ -229,16 +218,6 @@ extern void __iomem *omap4_get_l2cache_base(void);
229#endif 218#endif
230 219
231struct device_node; 220struct device_node;
232#ifdef CONFIG_OF
233int __init intc_of_init(struct device_node *node,
234 struct device_node *parent);
235#else
236int __init intc_of_init(struct device_node *node,
237 struct device_node *parent)
238{
239 return 0;
240}
241#endif
242 221
243#ifdef CONFIG_SMP 222#ifdef CONFIG_SMP
244extern void __iomem *omap4_get_scu_base(void); 223extern void __iomem *omap4_get_scu_base(void);
@@ -307,7 +286,7 @@ static inline void omap4_cpu_resume(void)
307 286
308#endif 287#endif
309 288
310void pdata_quirks_init(struct of_device_id *); 289void pdata_quirks_init(const struct of_device_id *);
311void omap_auxdata_legacy_init(struct device *dev); 290void omap_auxdata_legacy_init(struct device *dev);
312void omap_pcs_legacy_init(int irq, void (*rearm)(void)); 291void omap_pcs_legacy_init(int irq, void (*rearm)(void));
313 292
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index bf852d7ae951..7a050f9c37ff 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -544,7 +544,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
544 MAX_MODULE_SOFTRESET_WAIT, c); 544 MAX_MODULE_SOFTRESET_WAIT, c);
545 545
546 if (c == MAX_MODULE_SOFTRESET_WAIT) 546 if (c == MAX_MODULE_SOFTRESET_WAIT)
547 pr_warning("dss_core: waiting for reset to finish failed\n"); 547 pr_warn("dss_core: waiting for reset to finish failed\n");
548 else 548 else
549 pr_debug("dss_core: softreset done\n"); 549 pr_debug("dss_core: softreset done\n");
550 550
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2f97228f188a..a4d52c42a438 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1243,7 +1243,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1243} 1243}
1244 1244
1245#ifdef CONFIG_OF 1245#ifdef CONFIG_OF
1246static struct of_device_id gpmc_dt_ids[] = { 1246static const struct of_device_id gpmc_dt_ids[] = {
1247 { .compatible = "ti,omap2420-gpmc" }, 1247 { .compatible = "ti,omap2420-gpmc" },
1248 { .compatible = "ti,omap2430-gpmc" }, 1248 { .compatible = "ti,omap2430-gpmc" },
1249 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ 1249 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index f78b4a161959..f3897d82e53e 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -67,8 +67,8 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
67 MAX_MODULE_SOFTRESET_WAIT, c); 67 MAX_MODULE_SOFTRESET_WAIT, c);
68 68
69 if (c == MAX_MODULE_SOFTRESET_WAIT) 69 if (c == MAX_MODULE_SOFTRESET_WAIT)
70 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 70 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
71 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 71 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
72 else 72 else
73 pr_debug("%s: %s: softreset in %d usec\n", __func__, 73 pr_debug("%s: %s: softreset in %d usec\n", __func__,
74 oh->name, c); 74 oh->name, c);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b456b4471f35..b9d8e47ffe8e 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -99,7 +99,7 @@ int omap_i2c_reset(struct omap_hwmod *oh)
99 MAX_MODULE_SOFTRESET_WAIT, c); 99 MAX_MODULE_SOFTRESET_WAIT, c);
100 100
101 if (c == MAX_MODULE_SOFTRESET_WAIT) 101 if (c == MAX_MODULE_SOFTRESET_WAIT)
102 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 102 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
103 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 103 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
104 else 104 else
105 pr_debug("%s: %s: softreset in %d usec\n", __func__, 105 pr_debug("%s: %s: softreset in %d usec\n", __func__,
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5d0667c119f6..b8ad045bcb8d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -231,15 +231,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
231 .length = L4_PER_44XX_SIZE, 231 .length = L4_PER_44XX_SIZE,
232 .type = MT_DEVICE, 232 .type = MT_DEVICE,
233 }, 233 },
234#ifdef CONFIG_OMAP4_ERRATA_I688
235 {
236 .virtual = OMAP4_SRAM_VA,
237 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
238 .length = PAGE_SIZE,
239 .type = MT_MEMORY_RW_SO,
240 },
241#endif
242
243}; 234};
244#endif 235#endif
245 236
@@ -269,14 +260,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
269 .length = L4_PER_54XX_SIZE, 260 .length = L4_PER_54XX_SIZE,
270 .type = MT_DEVICE, 261 .type = MT_DEVICE,
271 }, 262 },
272#ifdef CONFIG_OMAP4_ERRATA_I688
273 {
274 .virtual = OMAP4_SRAM_VA,
275 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
276 .length = PAGE_SIZE,
277 .type = MT_MEMORY_RW_SO,
278 },
279#endif
280}; 263};
281#endif 264#endif
282 265
@@ -667,6 +650,7 @@ void __init omap5_init_early(void)
667 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), 650 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
668 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 651 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
669 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 652 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
653 omap4_pm_init_early();
670 omap_prm_base_init(); 654 omap_prm_base_init();
671 omap_cm_base_init(); 655 omap_cm_base_init();
672 omap44xx_prm_init(); 656 omap44xx_prm_init();
@@ -682,6 +666,8 @@ void __init omap5_init_early(void)
682void __init omap5_init_late(void) 666void __init omap5_init_late(void)
683{ 667{
684 omap_common_late_init(); 668 omap_common_late_init();
669 omap4_pm_init();
670 omap2_clk_enable_autoidle_all();
685} 671}
686#endif 672#endif
687 673
@@ -695,6 +681,7 @@ void __init dra7xx_init_early(void)
695 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), 681 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
696 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 682 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
697 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 683 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
684 omap4_pm_init_early();
698 omap_prm_base_init(); 685 omap_prm_base_init();
699 omap_cm_base_init(); 686 omap_cm_base_init();
700 omap44xx_prm_init(); 687 omap44xx_prm_init();
@@ -709,6 +696,8 @@ void __init dra7xx_init_early(void)
709void __init dra7xx_init_late(void) 696void __init dra7xx_init_late(void)
710{ 697{
711 omap_common_late_init(); 698 omap_common_late_init();
699 omap4_pm_init();
700 omap2_clk_enable_autoidle_all();
712} 701}
713#endif 702#endif
714 703
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
deleted file mode 100644
index 35b8590c322e..000000000000
--- a/arch/arm/mach-omap2/irq.c
+++ /dev/null
@@ -1,380 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/irq.c
3 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18
19#include <asm/exception.h>
20#include <asm/mach/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "common.h"
29
30/* selected INTC register offsets */
31
32#define INTC_REVISION 0x0000
33#define INTC_SYSCONFIG 0x0010
34#define INTC_SYSSTATUS 0x0014
35#define INTC_SIR 0x0040
36#define INTC_CONTROL 0x0048
37#define INTC_PROTECTION 0x004C
38#define INTC_IDLE 0x0050
39#define INTC_THRESHOLD 0x0068
40#define INTC_MIR0 0x0084
41#define INTC_MIR_CLEAR0 0x0088
42#define INTC_MIR_SET0 0x008c
43#define INTC_PENDING_IRQ0 0x0098
44/* Number of IRQ state bits in each MIR register */
45#define IRQ_BITS_PER_REG 32
46
47#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
48#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
49#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
50#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
51#define INTCPS_NR_MIR_REGS 3
52#define INTCPS_NR_IRQS 96
53
54/*
55 * OMAP2 has a number of different interrupt controllers, each interrupt
56 * controller is identified as its own "bank". Register definitions are
57 * fairly consistent for each bank, but not all registers are implemented
58 * for each bank.. when in doubt, consult the TRM.
59 */
60static struct omap_irq_bank {
61 void __iomem *base_reg;
62 unsigned int nr_irqs;
63} __attribute__ ((aligned(4))) irq_banks[] = {
64 {
65 /* MPU INTC */
66 .nr_irqs = 96,
67 },
68};
69
70static struct irq_domain *domain;
71
72/* Structure to save interrupt controller context */
73struct omap3_intc_regs {
74 u32 sysconfig;
75 u32 protection;
76 u32 idle;
77 u32 threshold;
78 u32 ilr[INTCPS_NR_IRQS];
79 u32 mir[INTCPS_NR_MIR_REGS];
80};
81
82/* INTC bank register get/set */
83
84static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
85{
86 writel_relaxed(val, bank->base_reg + reg);
87}
88
89static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
90{
91 return readl_relaxed(bank->base_reg + reg);
92}
93
94/* XXX: FIQ and additional INTC support (only MPU at the moment) */
95static void omap_ack_irq(struct irq_data *d)
96{
97 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
98}
99
100static void omap_mask_ack_irq(struct irq_data *d)
101{
102 irq_gc_mask_disable_reg(d);
103 omap_ack_irq(d);
104}
105
106static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
107{
108 unsigned long tmp;
109
110 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
111 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
112 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
113
114 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
115 tmp |= 1 << 1; /* soft reset */
116 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
117
118 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
119 /* Wait for reset to complete */;
120
121 /* Enable autoidle */
122 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
123}
124
125int omap_irq_pending(void)
126{
127 int i;
128
129 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
130 struct omap_irq_bank *bank = irq_banks + i;
131 int irq;
132
133 for (irq = 0; irq < bank->nr_irqs; irq += 32)
134 if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
135 ((irq >> 5) << 5)))
136 return 1;
137 }
138 return 0;
139}
140
141static __init void
142omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
143{
144 struct irq_chip_generic *gc;
145 struct irq_chip_type *ct;
146
147 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
148 handle_level_irq);
149 ct = gc->chip_types;
150 ct->chip.irq_ack = omap_mask_ack_irq;
151 ct->chip.irq_mask = irq_gc_mask_disable_reg;
152 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
153 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
154
155 ct->regs.enable = INTC_MIR_CLEAR0;
156 ct->regs.disable = INTC_MIR_SET0;
157 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
158 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
159}
160
161static void __init omap_init_irq(u32 base, int nr_irqs,
162 struct device_node *node)
163{
164 void __iomem *omap_irq_base;
165 unsigned long nr_of_irqs = 0;
166 unsigned int nr_banks = 0;
167 int i, j, irq_base;
168
169 omap_irq_base = ioremap(base, SZ_4K);
170 if (WARN_ON(!omap_irq_base))
171 return;
172
173 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
174 if (irq_base < 0) {
175 pr_warn("Couldn't allocate IRQ numbers\n");
176 irq_base = 0;
177 }
178
179 domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
180 &irq_domain_simple_ops, NULL);
181
182 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
183 struct omap_irq_bank *bank = irq_banks + i;
184
185 bank->nr_irqs = nr_irqs;
186
187 /* Static mapping, never released */
188 bank->base_reg = ioremap(base, SZ_4K);
189 if (!bank->base_reg) {
190 pr_err("Could not ioremap irq bank%i\n", i);
191 continue;
192 }
193
194 omap_irq_bank_init_one(bank);
195
196 for (j = 0; j < bank->nr_irqs; j += 32)
197 omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
198
199 nr_of_irqs += bank->nr_irqs;
200 nr_banks++;
201 }
202
203 pr_info("Total of %ld interrupts on %d active controller%s\n",
204 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
205}
206
207void __init omap2_init_irq(void)
208{
209 omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
210}
211
212void __init omap3_init_irq(void)
213{
214 omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
215}
216
217void __init ti81xx_init_irq(void)
218{
219 omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
220}
221
222static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
223{
224 u32 irqnr;
225 int handled_irq = 0;
226
227 do {
228 irqnr = readl_relaxed(base_addr + 0x98);
229 if (irqnr)
230 goto out;
231
232 irqnr = readl_relaxed(base_addr + 0xb8);
233 if (irqnr)
234 goto out;
235
236 irqnr = readl_relaxed(base_addr + 0xd8);
237#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
238 if (irqnr)
239 goto out;
240 irqnr = readl_relaxed(base_addr + 0xf8);
241#endif
242
243out:
244 if (!irqnr)
245 break;
246
247 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
248 irqnr &= ACTIVEIRQ_MASK;
249
250 if (irqnr) {
251 irqnr = irq_find_mapping(domain, irqnr);
252 handle_IRQ(irqnr, regs);
253 handled_irq = 1;
254 }
255 } while (irqnr);
256
257 /* If an irq is masked or deasserted while active, we will
258 * keep ending up here with no irq handled. So remove it from
259 * the INTC with an ack.*/
260 if (!handled_irq)
261 omap_ack_irq(NULL);
262}
263
264asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
265{
266 void __iomem *base_addr = OMAP2_IRQ_BASE;
267 omap_intc_handle_irq(base_addr, regs);
268}
269
270int __init intc_of_init(struct device_node *node,
271 struct device_node *parent)
272{
273 struct resource res;
274 u32 nr_irq = 96;
275
276 if (WARN_ON(!node))
277 return -ENODEV;
278
279 if (of_address_to_resource(node, 0, &res)) {
280 WARN(1, "unable to get intc registers\n");
281 return -EINVAL;
282 }
283
284 if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
285 pr_warn("unable to get intc-size, default to %d\n", nr_irq);
286
287 omap_init_irq(res.start, nr_irq, of_node_get(node));
288
289 return 0;
290}
291
292static struct of_device_id irq_match[] __initdata = {
293 { .compatible = "ti,omap2-intc", .data = intc_of_init, },
294 { }
295};
296
297void __init omap_intc_of_init(void)
298{
299 of_irq_init(irq_match);
300}
301
302#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
303static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
304
305void omap_intc_save_context(void)
306{
307 int ind = 0, i = 0;
308 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
309 struct omap_irq_bank *bank = irq_banks + ind;
310 intc_context[ind].sysconfig =
311 intc_bank_read_reg(bank, INTC_SYSCONFIG);
312 intc_context[ind].protection =
313 intc_bank_read_reg(bank, INTC_PROTECTION);
314 intc_context[ind].idle =
315 intc_bank_read_reg(bank, INTC_IDLE);
316 intc_context[ind].threshold =
317 intc_bank_read_reg(bank, INTC_THRESHOLD);
318 for (i = 0; i < INTCPS_NR_IRQS; i++)
319 intc_context[ind].ilr[i] =
320 intc_bank_read_reg(bank, (0x100 + 0x4*i));
321 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
322 intc_context[ind].mir[i] =
323 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
324 (0x20 * i));
325 }
326}
327
328void omap_intc_restore_context(void)
329{
330 int ind = 0, i = 0;
331
332 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
333 struct omap_irq_bank *bank = irq_banks + ind;
334 intc_bank_write_reg(intc_context[ind].sysconfig,
335 bank, INTC_SYSCONFIG);
336 intc_bank_write_reg(intc_context[ind].sysconfig,
337 bank, INTC_SYSCONFIG);
338 intc_bank_write_reg(intc_context[ind].protection,
339 bank, INTC_PROTECTION);
340 intc_bank_write_reg(intc_context[ind].idle,
341 bank, INTC_IDLE);
342 intc_bank_write_reg(intc_context[ind].threshold,
343 bank, INTC_THRESHOLD);
344 for (i = 0; i < INTCPS_NR_IRQS; i++)
345 intc_bank_write_reg(intc_context[ind].ilr[i],
346 bank, (0x100 + 0x4*i));
347 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
348 intc_bank_write_reg(intc_context[ind].mir[i],
349 &irq_banks[0], INTC_MIR0 + (0x20 * i));
350 }
351 /* MIRs are saved and restore with other PRCM registers */
352}
353
354void omap3_intc_suspend(void)
355{
356 /* A pending interrupt would prevent OMAP from entering suspend */
357 omap_ack_irq(NULL);
358}
359
360void omap3_intc_prepare_idle(void)
361{
362 /*
363 * Disable autoidle as it can stall interrupt controller,
364 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
365 */
366 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
367}
368
369void omap3_intc_resume_idle(void)
370{
371 /* Re-enable autoidle */
372 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
373}
374
375asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
376{
377 void __iomem *base_addr = OMAP3_IRQ_BASE;
378 omap_intc_handle_irq(base_addr, regs);
379}
380#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 828e0db3d943..8bdf182422bd 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -76,8 +76,8 @@ int omap_msdi_reset(struct omap_hwmod *oh)
76 MAX_MODULE_SOFTRESET_WAIT, c); 76 MAX_MODULE_SOFTRESET_WAIT, c);
77 77
78 if (c == MAX_MODULE_SOFTRESET_WAIT) 78 if (c == MAX_MODULE_SOFTRESET_WAIT)
79 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 79 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
80 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 80 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
81 else 81 else
82 pr_debug("%s: %s: softreset in %d usec\n", __func__, 82 pr_debug("%s: %s: softreset in %d usec\n", __func__,
83 oh->name, c); 83 oh->name, c);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ac8a249779f2..78064b0d4db5 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -814,7 +814,7 @@ int __init omap_mux_late_init(void)
814 "hwmod_io", omap_mux_late_init); 814 "hwmod_io", omap_mux_late_init);
815 815
816 if (ret) 816 if (ret)
817 pr_warning("mux: Failed to setup hwmod io irq %d\n", ret); 817 pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
818 818
819 return 0; 819 return 0;
820} 820}
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 4001325f90fb..6944ae3674e8 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -56,6 +56,7 @@
56#include "omap4-sar-layout.h" 56#include "omap4-sar-layout.h"
57#include "pm.h" 57#include "pm.h"
58#include "prcm_mpu44xx.h" 58#include "prcm_mpu44xx.h"
59#include "prcm_mpu54xx.h"
59#include "prminst44xx.h" 60#include "prminst44xx.h"
60#include "prcm44xx.h" 61#include "prcm44xx.h"
61#include "prm44xx.h" 62#include "prm44xx.h"
@@ -68,7 +69,6 @@ struct omap4_cpu_pm_info {
68 void __iomem *scu_sar_addr; 69 void __iomem *scu_sar_addr;
69 void __iomem *wkup_sar_addr; 70 void __iomem *wkup_sar_addr;
70 void __iomem *l2x0_sar_addr; 71 void __iomem *l2x0_sar_addr;
71 void (*secondary_startup)(void);
72}; 72};
73 73
74/** 74/**
@@ -76,6 +76,7 @@ struct omap4_cpu_pm_info {
76 * @finish_suspend: CPU suspend finisher function pointer 76 * @finish_suspend: CPU suspend finisher function pointer
77 * @resume: CPU resume function pointer 77 * @resume: CPU resume function pointer
78 * @scu_prepare: CPU Snoop Control program function pointer 78 * @scu_prepare: CPU Snoop Control program function pointer
79 * @hotplug_restart: CPU restart function pointer
79 * 80 *
80 * Structure holds functions pointer for CPU low power operations like 81 * Structure holds functions pointer for CPU low power operations like
81 * suspend, resume and scu programming. 82 * suspend, resume and scu programming.
@@ -84,11 +85,13 @@ struct cpu_pm_ops {
84 int (*finish_suspend)(unsigned long cpu_state); 85 int (*finish_suspend)(unsigned long cpu_state);
85 void (*resume)(void); 86 void (*resume)(void);
86 void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state); 87 void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
88 void (*hotplug_restart)(void);
87}; 89};
88 90
89static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); 91static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
90static struct powerdomain *mpuss_pd; 92static struct powerdomain *mpuss_pd;
91static void __iomem *sar_base; 93static void __iomem *sar_base;
94static u32 cpu_context_offset;
92 95
93static int default_finish_suspend(unsigned long cpu_state) 96static int default_finish_suspend(unsigned long cpu_state)
94{ 97{
@@ -106,6 +109,7 @@ struct cpu_pm_ops omap_pm_ops = {
106 .finish_suspend = default_finish_suspend, 109 .finish_suspend = default_finish_suspend,
107 .resume = dummy_cpu_resume, 110 .resume = dummy_cpu_resume,
108 .scu_prepare = dummy_scu_prepare, 111 .scu_prepare = dummy_scu_prepare,
112 .hotplug_restart = dummy_cpu_resume,
109}; 113};
110 114
111/* 115/*
@@ -116,7 +120,8 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
116{ 120{
117 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 121 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
118 122
119 writel_relaxed(addr, pm_info->wkup_sar_addr); 123 if (pm_info->wkup_sar_addr)
124 writel_relaxed(addr, pm_info->wkup_sar_addr);
120} 125}
121 126
122/* 127/*
@@ -141,7 +146,8 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
141 break; 146 break;
142 } 147 }
143 148
144 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); 149 if (pm_info->scu_sar_addr)
150 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
145} 151}
146 152
147/* Helper functions for MPUSS OSWR */ 153/* Helper functions for MPUSS OSWR */
@@ -161,14 +167,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
161 167
162 if (cpu_id) { 168 if (cpu_id) {
163 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, 169 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
164 OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); 170 cpu_context_offset);
165 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, 171 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
166 OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); 172 cpu_context_offset);
167 } else { 173 } else {
168 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, 174 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
169 OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); 175 cpu_context_offset);
170 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, 176 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
171 OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); 177 cpu_context_offset);
172 } 178 }
173} 179}
174 180
@@ -179,7 +185,8 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
179{ 185{
180 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 186 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
181 187
182 writel_relaxed(save_state, pm_info->l2x0_sar_addr); 188 if (pm_info->l2x0_sar_addr)
189 writel_relaxed(save_state, pm_info->l2x0_sar_addr);
183} 190}
184 191
185/* 192/*
@@ -189,10 +196,14 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
189#ifdef CONFIG_CACHE_L2X0 196#ifdef CONFIG_CACHE_L2X0
190static void __init save_l2x0_context(void) 197static void __init save_l2x0_context(void)
191{ 198{
192 writel_relaxed(l2x0_saved_regs.aux_ctrl, 199 void __iomem *l2x0_base = omap4_get_l2cache_base();
193 sar_base + L2X0_AUXCTRL_OFFSET); 200
194 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 201 if (l2x0_base && sar_base) {
195 sar_base + L2X0_PREFETCH_CTRL_OFFSET); 202 writel_relaxed(l2x0_saved_regs.aux_ctrl,
203 sar_base + L2X0_AUXCTRL_OFFSET);
204 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
205 sar_base + L2X0_PREFETCH_CTRL_OFFSET);
206 }
196} 207}
197#else 208#else
198static void __init save_l2x0_context(void) 209static void __init save_l2x0_context(void)
@@ -231,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
231 save_state = 1; 242 save_state = 1;
232 break; 243 break;
233 case PWRDM_POWER_RET: 244 case PWRDM_POWER_RET:
245 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
246 save_state = 0;
247 break;
248 }
234 default: 249 default:
235 /* 250 /*
236 * CPUx CSWR is invalid hardware state. Also CPUx OSWR 251 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
@@ -298,12 +313,16 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
298 if (omap_rev() == OMAP4430_REV_ES1_0) 313 if (omap_rev() == OMAP4430_REV_ES1_0)
299 return -ENXIO; 314 return -ENXIO;
300 315
316 /* Use the achievable power state for the domain */
317 power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
318 false, power_state);
319
301 if (power_state == PWRDM_POWER_OFF) 320 if (power_state == PWRDM_POWER_OFF)
302 cpu_state = 1; 321 cpu_state = 1;
303 322
304 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 323 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
305 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 324 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
306 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); 325 set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
307 omap_pm_ops.scu_prepare(cpu, power_state); 326 omap_pm_ops.scu_prepare(cpu, power_state);
308 327
309 /* 328 /*
@@ -319,6 +338,21 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
319 338
320 339
321/* 340/*
341 * Enable Mercury Fast HG retention mode by default.
342 */
343static void enable_mercury_retention_mode(void)
344{
345 u32 reg;
346
347 reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
348 OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
349 /* Enable HG_EN, HG_RAMPUP = fast mode */
350 reg |= BIT(24) | BIT(25);
351 omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
352 OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
353}
354
355/*
322 * Initialise OMAP4 MPUSS 356 * Initialise OMAP4 MPUSS
323 */ 357 */
324int __init omap4_mpuss_init(void) 358int __init omap4_mpuss_init(void)
@@ -330,13 +364,17 @@ int __init omap4_mpuss_init(void)
330 return -ENODEV; 364 return -ENODEV;
331 } 365 }
332 366
333 sar_base = omap4_get_sar_ram_base(); 367 if (cpu_is_omap44xx())
368 sar_base = omap4_get_sar_ram_base();
334 369
335 /* Initilaise per CPU PM information */ 370 /* Initilaise per CPU PM information */
336 pm_info = &per_cpu(omap4_pm_info, 0x0); 371 pm_info = &per_cpu(omap4_pm_info, 0x0);
337 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; 372 if (sar_base) {
338 pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; 373 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
339 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; 374 pm_info->wkup_sar_addr = sar_base +
375 CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
376 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
377 }
340 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); 378 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
341 if (!pm_info->pwrdm) { 379 if (!pm_info->pwrdm) {
342 pr_err("Lookup failed for CPU0 pwrdm\n"); 380 pr_err("Lookup failed for CPU0 pwrdm\n");
@@ -351,13 +389,12 @@ int __init omap4_mpuss_init(void)
351 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 389 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
352 390
353 pm_info = &per_cpu(omap4_pm_info, 0x1); 391 pm_info = &per_cpu(omap4_pm_info, 0x1);
354 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; 392 if (sar_base) {
355 pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 393 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
356 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; 394 pm_info->wkup_sar_addr = sar_base +
357 if (cpu_is_omap446x()) 395 CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
358 pm_info->secondary_startup = omap4460_secondary_startup; 396 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
359 else 397 }
360 pm_info->secondary_startup = omap4_secondary_startup;
361 398
362 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); 399 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
363 if (!pm_info->pwrdm) { 400 if (!pm_info->pwrdm) {
@@ -380,20 +417,27 @@ int __init omap4_mpuss_init(void)
380 pwrdm_clear_all_prev_pwrst(mpuss_pd); 417 pwrdm_clear_all_prev_pwrst(mpuss_pd);
381 mpuss_clear_prev_logic_pwrst(); 418 mpuss_clear_prev_logic_pwrst();
382 419
383 /* Save device type on scratchpad for low level code to use */ 420 if (sar_base) {
384 if (omap_type() != OMAP2_DEVICE_TYPE_GP) 421 /* Save device type on scratchpad for low level code to use */
385 writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET); 422 writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
386 else 423 sar_base + OMAP_TYPE_OFFSET);
387 writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET); 424 save_l2x0_context();
388 425 }
389 save_l2x0_context();
390 426
391 if (cpu_is_omap44xx()) { 427 if (cpu_is_omap44xx()) {
392 omap_pm_ops.finish_suspend = omap4_finish_suspend; 428 omap_pm_ops.finish_suspend = omap4_finish_suspend;
393 omap_pm_ops.resume = omap4_cpu_resume; 429 omap_pm_ops.resume = omap4_cpu_resume;
394 omap_pm_ops.scu_prepare = scu_pwrst_prepare; 430 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
431 omap_pm_ops.hotplug_restart = omap4_secondary_startup;
432 cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
433 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
434 cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
435 enable_mercury_retention_mode();
395 } 436 }
396 437
438 if (cpu_is_omap446x())
439 omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
440
397 return 0; 441 return 0;
398} 442}
399 443
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 3e97c6c8ecf1..dec2b05d184b 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -45,6 +45,7 @@
45#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 45#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
46 46
47#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 47#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
48#define OMAP5_MON_AMBA_IF_INDEX 0x108
48 49
49/* Secure PPA(Primary Protected Application) APIs */ 50/* Secure PPA(Primary Protected Application) APIs */
50#define OMAP4_PPA_L2_POR_INDEX 0x23 51#define OMAP4_PPA_L2_POR_INDEX 0x23
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 37843a7d3639..f961c46453b9 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -32,6 +32,7 @@
32#include "soc.h" 32#include "soc.h"
33#include "omap4-sar-layout.h" 33#include "omap4-sar-layout.h"
34#include "common.h" 34#include "common.h"
35#include "pm.h"
35 36
36#define AM43XX_NR_REG_BANKS 7 37#define AM43XX_NR_REG_BANKS 7
37#define AM43XX_IRQS 224 38#define AM43XX_IRQS 224
@@ -381,7 +382,7 @@ static struct notifier_block irq_notifier_block = {
381static void __init irq_pm_init(void) 382static void __init irq_pm_init(void)
382{ 383{
383 /* FIXME: Remove this when MPU OSWR support is added */ 384 /* FIXME: Remove this when MPU OSWR support is added */
384 if (!soc_is_omap54xx()) 385 if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
385 cpu_pm_register_notifier(&irq_notifier_block); 386 cpu_pm_register_notifier(&irq_notifier_block);
386} 387}
387#else 388#else
@@ -406,6 +407,7 @@ int __init omap_wakeupgen_init(void)
406{ 407{
407 int i; 408 int i;
408 unsigned int boot_cpu = smp_processor_id(); 409 unsigned int boot_cpu = smp_processor_id();
410 u32 val;
409 411
410 /* Not supported on OMAP4 ES1.0 silicon */ 412 /* Not supported on OMAP4 ES1.0 silicon */
411 if (omap_rev() == OMAP4430_REV_ES1_0) { 413 if (omap_rev() == OMAP4430_REV_ES1_0) {
@@ -451,6 +453,22 @@ int __init omap_wakeupgen_init(void)
451 for (i = 0; i < max_irqs; i++) 453 for (i = 0; i < max_irqs; i++)
452 irq_target_cpu[i] = boot_cpu; 454 irq_target_cpu[i] = boot_cpu;
453 455
456 /*
457 * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
458 * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
459 * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
460 * independently.
461 * This needs to be set one time thanks to always ON domain.
462 *
463 * We do not support ES1 behavior anymore. OMAP5 is assumed to be
464 * ES2.0, and the same is applicable for DRA7.
465 */
466 if (soc_is_omap54xx() || soc_is_dra7xx()) {
467 val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
468 val |= BIT(5);
469 omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
470 }
471
454 irq_hotplug_init(); 472 irq_hotplug_init();
455 irq_pm_init(); 473 irq_pm_init();
456 474
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h
index b0fd16f5c391..b3c8eccfae79 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
@@ -27,6 +27,7 @@
27#define OMAP_WKG_ENB_E_1 0x420 27#define OMAP_WKG_ENB_E_1 0x420
28#define OMAP_AUX_CORE_BOOT_0 0x800 28#define OMAP_AUX_CORE_BOOT_0 0x800
29#define OMAP_AUX_CORE_BOOT_1 0x804 29#define OMAP_AUX_CORE_BOOT_1 0x804
30#define OMAP_AMBA_IF_MODE 0x80c
30#define OMAP_PTMSYNCREQ_MASK 0xc00 31#define OMAP_PTMSYNCREQ_MASK 0xc00
31#define OMAP_PTMSYNCREQ_EN 0xc04 32#define OMAP_PTMSYNCREQ_EN 0xc04
32#define OMAP_TIMESTAMPCYCLELO 0xc08 33#define OMAP_TIMESTAMPCYCLELO 0xc08
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index a0fe747634c1..16b20cedc38d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -25,6 +25,7 @@
25#include <linux/irqchip/irq-crossbar.h> 25#include <linux/irqchip/irq-crossbar.h>
26#include <linux/of_address.h> 26#include <linux/of_address.h>
27#include <linux/reboot.h> 27#include <linux/reboot.h>
28#include <linux/genalloc.h>
28 29
29#include <asm/hardware/cache-l2x0.h> 30#include <asm/hardware/cache-l2x0.h>
30#include <asm/mach/map.h> 31#include <asm/mach/map.h>
@@ -71,6 +72,26 @@ void omap_bus_sync(void)
71} 72}
72EXPORT_SYMBOL(omap_bus_sync); 73EXPORT_SYMBOL(omap_bus_sync);
73 74
75static int __init omap4_sram_init(void)
76{
77 struct device_node *np;
78 struct gen_pool *sram_pool;
79
80 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
81 if (!np)
82 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
83 __func__);
84 sram_pool = of_get_named_gen_pool(np, "sram", 0);
85 if (!sram_pool)
86 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
87 __func__);
88 else
89 sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
90
91 return 0;
92}
93omap_arch_initcall(omap4_sram_init);
94
74/* Steal one page physical memory for barrier implementation */ 95/* Steal one page physical memory for barrier implementation */
75int __init omap_barrier_reserve_memblock(void) 96int __init omap_barrier_reserve_memblock(void)
76{ 97{
@@ -91,7 +112,6 @@ void __init omap_barriers_init(void)
91 dram_io_desc[0].type = MT_MEMORY_RW_SO; 112 dram_io_desc[0].type = MT_MEMORY_RW_SO;
92 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); 113 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
93 dram_sync = (void __iomem *) dram_io_desc[0].virtual; 114 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
94 sram_sync = (void __iomem *) OMAP4_SRAM_VA;
95 115
96 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", 116 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
97 (long long) paddr, dram_io_desc[0].virtual); 117 (long long) paddr, dram_io_desc[0].virtual);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9e91a4e7519a..716247ed9e0c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -769,8 +769,8 @@ static int _init_main_clk(struct omap_hwmod *oh)
769 769
770 oh->_clk = clk_get(NULL, oh->main_clk); 770 oh->_clk = clk_get(NULL, oh->main_clk);
771 if (IS_ERR(oh->_clk)) { 771 if (IS_ERR(oh->_clk)) {
772 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", 772 pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
773 oh->name, oh->main_clk); 773 oh->name, oh->main_clk);
774 return -EINVAL; 774 return -EINVAL;
775 } 775 }
776 /* 776 /*
@@ -814,8 +814,8 @@ static int _init_interface_clks(struct omap_hwmod *oh)
814 814
815 c = clk_get(NULL, os->clk); 815 c = clk_get(NULL, os->clk);
816 if (IS_ERR(c)) { 816 if (IS_ERR(c)) {
817 pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", 817 pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
818 oh->name, os->clk); 818 oh->name, os->clk);
819 ret = -EINVAL; 819 ret = -EINVAL;
820 continue; 820 continue;
821 } 821 }
@@ -851,8 +851,8 @@ static int _init_opt_clks(struct omap_hwmod *oh)
851 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { 851 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
852 c = clk_get(NULL, oc->clk); 852 c = clk_get(NULL, oc->clk);
853 if (IS_ERR(c)) { 853 if (IS_ERR(c)) {
854 pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", 854 pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
855 oh->name, oc->clk); 855 oh->name, oc->clk);
856 ret = -EINVAL; 856 ret = -EINVAL;
857 continue; 857 continue;
858 } 858 }
@@ -1576,7 +1576,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
1576 1576
1577 oh->clkdm = clkdm_lookup(oh->clkdm_name); 1577 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1578 if (!oh->clkdm) { 1578 if (!oh->clkdm) {
1579 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", 1579 pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n",
1580 oh->name, oh->clkdm_name); 1580 oh->name, oh->clkdm_name);
1581 return 0; 1581 return 0;
1582 } 1582 }
@@ -1616,7 +1616,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1616 if (!ret) 1616 if (!ret)
1617 oh->_state = _HWMOD_STATE_CLKS_INITED; 1617 oh->_state = _HWMOD_STATE_CLKS_INITED;
1618 else 1618 else
1619 pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); 1619 pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
1620 1620
1621 return ret; 1621 return ret;
1622} 1622}
@@ -1739,7 +1739,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1739 _disable_clocks(oh); 1739 _disable_clocks(oh);
1740 1740
1741 if (ret == -EBUSY) 1741 if (ret == -EBUSY)
1742 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); 1742 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
1743 1743
1744 if (!ret) { 1744 if (!ret) {
1745 /* 1745 /*
@@ -1953,8 +1953,8 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1953 1953
1954 c = _wait_softreset_complete(oh); 1954 c = _wait_softreset_complete(oh);
1955 if (c == MAX_MODULE_SOFTRESET_WAIT) { 1955 if (c == MAX_MODULE_SOFTRESET_WAIT) {
1956 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", 1956 pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1957 oh->name, MAX_MODULE_SOFTRESET_WAIT); 1957 oh->name, MAX_MODULE_SOFTRESET_WAIT);
1958 ret = -ETIMEDOUT; 1958 ret = -ETIMEDOUT;
1959 goto dis_opt_clks; 1959 goto dis_opt_clks;
1960 } else { 1960 } else {
@@ -2185,7 +2185,7 @@ static int _enable(struct omap_hwmod *oh)
2185 oh->mux->pads_dynamic))) { 2185 oh->mux->pads_dynamic))) {
2186 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); 2186 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2187 _reconfigure_io_chain(); 2187 _reconfigure_io_chain();
2188 } else if (oh->flags & HWMOD_FORCE_MSTANDBY) { 2188 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2189 _reconfigure_io_chain(); 2189 _reconfigure_io_chain();
2190 } 2190 }
2191 2191
@@ -2293,7 +2293,7 @@ static int _idle(struct omap_hwmod *oh)
2293 if (oh->mux && oh->mux->pads_dynamic) { 2293 if (oh->mux && oh->mux->pads_dynamic) {
2294 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); 2294 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
2295 _reconfigure_io_chain(); 2295 _reconfigure_io_chain();
2296 } else if (oh->flags & HWMOD_FORCE_MSTANDBY) { 2296 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2297 _reconfigure_io_chain(); 2297 _reconfigure_io_chain();
2298 } 2298 }
2299 2299
@@ -2618,8 +2618,8 @@ static int __init _setup_reset(struct omap_hwmod *oh)
2618 if (oh->rst_lines_cnt == 0) { 2618 if (oh->rst_lines_cnt == 0) {
2619 r = _enable(oh); 2619 r = _enable(oh);
2620 if (r) { 2620 if (r) {
2621 pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", 2621 pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
2622 oh->name, oh->_state); 2622 oh->name, oh->_state);
2623 return -EINVAL; 2623 return -EINVAL;
2624 } 2624 }
2625 } 2625 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0f97d635ff90..512f809a3f4d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -514,6 +514,9 @@ struct omap_hwmod_omap4_prcm {
514 * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module 514 * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
515 * out of idle, but rely on smart-idle to the put it back in idle, 515 * out of idle, but rely on smart-idle to the put it back in idle,
516 * so the wakeups are still functional (Only known case for now is UART) 516 * so the wakeups are still functional (Only known case for now is UART)
517 * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up
518 * events by calling _reconfigure_io_chain() when a device is enabled
519 * or idled.
517 */ 520 */
518#define HWMOD_SWSUP_SIDLE (1 << 0) 521#define HWMOD_SWSUP_SIDLE (1 << 0)
519#define HWMOD_SWSUP_MSTANDBY (1 << 1) 522#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -528,6 +531,7 @@ struct omap_hwmod_omap4_prcm {
528#define HWMOD_BLOCK_WFI (1 << 10) 531#define HWMOD_BLOCK_WFI (1 << 10)
529#define HWMOD_FORCE_MSTANDBY (1 << 11) 532#define HWMOD_FORCE_MSTANDBY (1 << 11)
530#define HWMOD_SWSUP_SIDLE_ACT (1 << 12) 533#define HWMOD_SWSUP_SIDLE_ACT (1 << 12)
534#define HWMOD_RECONFIG_IO_CHAIN (1 << 13)
531 535
532/* 536/*
533 * omap_hwmod._int_flags definitions 537 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e9516b454e76..2a78b093c0ce 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -490,7 +490,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
490 .mpu_irqs = omap2_uart1_mpu_irqs, 490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs, 491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck", 492 .main_clk = "uart1_fck",
493 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 493 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
494 .prcm = { 494 .prcm = {
495 .omap2 = { 495 .omap2 = {
496 .module_offs = CORE_MOD, 496 .module_offs = CORE_MOD,
@@ -509,7 +509,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
509 .mpu_irqs = omap2_uart2_mpu_irqs, 509 .mpu_irqs = omap2_uart2_mpu_irqs,
510 .sdma_reqs = omap2_uart2_sdma_reqs, 510 .sdma_reqs = omap2_uart2_sdma_reqs,
511 .main_clk = "uart2_fck", 511 .main_clk = "uart2_fck",
512 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 512 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
513 .prcm = { 513 .prcm = {
514 .omap2 = { 514 .omap2 = {
515 .module_offs = CORE_MOD, 515 .module_offs = CORE_MOD,
@@ -529,7 +529,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
529 .sdma_reqs = omap2_uart3_sdma_reqs, 529 .sdma_reqs = omap2_uart3_sdma_reqs,
530 .main_clk = "uart3_fck", 530 .main_clk = "uart3_fck",
531 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 531 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
532 HWMOD_SWSUP_SIDLE_ACT, 532 HWMOD_SWSUP_SIDLE,
533 .prcm = { 533 .prcm = {
534 .omap2 = { 534 .omap2 = {
535 .module_offs = OMAP3430_PER_MOD, 535 .module_offs = OMAP3430_PER_MOD,
@@ -559,7 +559,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
559 .mpu_irqs = uart4_mpu_irqs, 559 .mpu_irqs = uart4_mpu_irqs,
560 .sdma_reqs = uart4_sdma_reqs, 560 .sdma_reqs = uart4_sdma_reqs,
561 .main_clk = "uart4_fck", 561 .main_clk = "uart4_fck",
562 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 562 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
563 .prcm = { 563 .prcm = {
564 .omap2 = { 564 .omap2 = {
565 .module_offs = OMAP3430_PER_MOD, 565 .module_offs = OMAP3430_PER_MOD,
@@ -1730,8 +1730,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1730 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY 1730 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1731 * signal when MIDLEMODE is set to force-idle. 1731 * signal when MIDLEMODE is set to force-idle.
1732 */ 1732 */
1733 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 1733 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1734 | HWMOD_FORCE_MSTANDBY, 1734 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1735}; 1735};
1736 1736
1737/* usb_otg_hs */ 1737/* usb_otg_hs */
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 90c88d498485..c95346c94829 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -244,14 +244,22 @@ static void __init nokia_n900_legacy_init(void)
244 /* set IBE to 1 */ 244 /* set IBE to 1 */
245 rx51_secure_update_aux_cr(BIT(6), 0); 245 rx51_secure_update_aux_cr(BIT(6), 0);
246 } else { 246 } else {
247 pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n"); 247 pr_warn("RX-51: Not enabling ARM errata 430973 workaround\n");
248 pr_warning("Thumb binaries may crash randomly without this workaround\n"); 248 pr_warn("Thumb binaries may crash randomly without this workaround\n");
249 } 249 }
250 250
251 pr_info("RX-51: Registring OMAP3 HWRNG device\n"); 251 pr_info("RX-51: Registring OMAP3 HWRNG device\n");
252 platform_device_register(&omap3_rom_rng_device); 252 platform_device_register(&omap3_rom_rng_device);
253 253
254 } 254 }
255
256 /* Only on some development boards */
257 gpio_request_one(164, GPIOF_OUT_INIT_LOW, "smc91x reset");
258}
259
260static void __init omap3_tao3530_legacy_init(void)
261{
262 hsmmc2_internal_input_clk();
255} 263}
256#endif /* CONFIG_ARCH_OMAP3 */ 264#endif /* CONFIG_ARCH_OMAP3 */
257 265
@@ -336,6 +344,8 @@ static struct pdata_init auxdata_quirks[] __initdata = {
336struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { 344struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
337#ifdef CONFIG_MACH_NOKIA_N8X0 345#ifdef CONFIG_MACH_NOKIA_N8X0
338 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), 346 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
347 OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
348 OF_DEV_AUXDATA("tlv320aic3x", 0x18, "2-0018", &n810_aic33_data),
339#endif 349#endif
340#ifdef CONFIG_ARCH_OMAP3 350#ifdef CONFIG_ARCH_OMAP3
341 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), 351 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
@@ -352,6 +362,16 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
352 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), 362 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
353 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), 363 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata),
354#endif 364#endif
365#ifdef CONFIG_SOC_OMAP5
366 OF_DEV_AUXDATA("ti,omap5-padconf", 0x4a002840, "4a002840.pinmux", &pcs_pdata),
367 OF_DEV_AUXDATA("ti,omap5-padconf", 0x4ae0c840, "4ae0c840.pinmux", &pcs_pdata),
368#endif
369#ifdef CONFIG_SOC_DRA7XX
370 OF_DEV_AUXDATA("ti,dra7-padconf", 0x4a003400, "4a003400.pinmux", &pcs_pdata),
371#endif
372#ifdef CONFIG_SOC_AM43XX
373 OF_DEV_AUXDATA("ti,am437-padconf", 0x44e10800, "44e10800.pinmux", &pcs_pdata),
374#endif
355#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) 375#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
356 OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", 376 OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
357 &omap4_iommu_pdata), 377 &omap4_iommu_pdata),
@@ -377,6 +397,7 @@ static struct pdata_init pdata_quirks[] __initdata = {
377 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, 397 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
378 { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, 398 { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
379 { "ti,am3517-evm", am3517_evm_legacy_init, }, 399 { "ti,am3517-evm", am3517_evm_legacy_init, },
400 { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, },
380#endif 401#endif
381#ifdef CONFIG_ARCH_OMAP4 402#ifdef CONFIG_ARCH_OMAP4
382 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, 403 { "ti,omap4-sdp", omap4_sdp_legacy_init, },
@@ -405,7 +426,7 @@ static void pdata_quirks_check(struct pdata_init *quirks)
405 } 426 }
406} 427}
407 428
408void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) 429void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table)
409{ 430{
410 omap_sdrc_init(NULL, NULL); 431 omap_sdrc_init(NULL, NULL);
411 pdata_quirks_check(auxdata_quirks); 432 pdata_quirks_check(auxdata_quirks);
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 828aee9ea6a8..58920bc8807b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -282,7 +282,7 @@ static inline void omap_init_cpufreq(void)
282 if (!of_have_populated_dt()) 282 if (!of_have_populated_dt())
283 devinfo.name = "omap-cpufreq"; 283 devinfo.name = "omap-cpufreq";
284 else 284 else
285 devinfo.name = "cpufreq-cpu0"; 285 devinfo.name = "cpufreq-dt";
286 platform_device_register_full(&devinfo); 286 platform_device_register_full(&devinfo);
287} 287}
288 288
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index e150102d6c06..425bfcd67db6 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -101,6 +101,7 @@ static inline void enable_omap3630_toggle_l2_on_restore(void) { }
101#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ 101#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
102 102
103#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0) 103#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
104#define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1)
104 105
105#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) 106#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
106extern u16 pm44xx_errata; 107extern u16 pm44xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3f80929a5f7e..175564c88a30 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -465,7 +465,7 @@ int __init omap3_pm_init(void)
465 int ret; 465 int ret;
466 466
467 if (!omap3_has_io_chain_ctrl()) 467 if (!omap3_has_io_chain_ctrl())
468 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); 468 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
469 469
470 pm_errata_configure(); 470 pm_errata_configure();
471 471
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 0dda6cf8b855..503097c72b82 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -29,6 +29,7 @@ u16 pm44xx_errata;
29struct power_state { 29struct power_state {
30 struct powerdomain *pwrdm; 30 struct powerdomain *pwrdm;
31 u32 next_state; 31 u32 next_state;
32 u32 next_logic_state;
32#ifdef CONFIG_SUSPEND 33#ifdef CONFIG_SUSPEND
33 u32 saved_state; 34 u32 saved_state;
34 u32 saved_logic_state; 35 u32 saved_logic_state;
@@ -36,6 +37,8 @@ struct power_state {
36 struct list_head node; 37 struct list_head node;
37}; 38};
38 39
40static u32 cpu_suspend_state = PWRDM_POWER_OFF;
41
39static LIST_HEAD(pwrst_list); 42static LIST_HEAD(pwrst_list);
40 43
41#ifdef CONFIG_SUSPEND 44#ifdef CONFIG_SUSPEND
@@ -54,7 +57,7 @@ static int omap4_pm_suspend(void)
54 /* Set targeted power domain states by suspend */ 57 /* Set targeted power domain states by suspend */
55 list_for_each_entry(pwrst, &pwrst_list, node) { 58 list_for_each_entry(pwrst, &pwrst_list, node) {
56 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 59 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
57 pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); 60 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
58 } 61 }
59 62
60 /* 63 /*
@@ -66,7 +69,7 @@ static int omap4_pm_suspend(void)
66 * domain CSWR is not supported by hardware. 69 * domain CSWR is not supported by hardware.
67 * More details can be found in OMAP4430 TRM section 4.3.4.2. 70 * More details can be found in OMAP4430 TRM section 4.3.4.2.
68 */ 71 */
69 omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); 72 omap4_enter_lowpower(cpu_id, cpu_suspend_state);
70 73
71 /* Restore next powerdomain state */ 74 /* Restore next powerdomain state */
72 list_for_each_entry(pwrst, &pwrst_list, node) { 75 list_for_each_entry(pwrst, &pwrst_list, node) {
@@ -112,15 +115,22 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
112 * through hotplug path and CPU0 explicitly programmed 115 * through hotplug path and CPU0 explicitly programmed
113 * further down in the code path 116 * further down in the code path
114 */ 117 */
115 if (!strncmp(pwrdm->name, "cpu", 3)) 118 if (!strncmp(pwrdm->name, "cpu", 3)) {
119 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
120 cpu_suspend_state = PWRDM_POWER_RET;
116 return 0; 121 return 0;
122 }
117 123
118 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 124 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
119 if (!pwrst) 125 if (!pwrst)
120 return -ENOMEM; 126 return -ENOMEM;
121 127
122 pwrst->pwrdm = pwrdm; 128 pwrst->pwrdm = pwrdm;
123 pwrst->next_state = PWRDM_POWER_RET; 129 pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
130 PWRDM_POWER_RET);
131 pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
132 PWRDM_POWER_OFF);
133
124 list_add(&pwrst->node, &pwrst_list); 134 list_add(&pwrst->node, &pwrst_list);
125 135
126 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 136 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
@@ -203,6 +213,32 @@ static inline int omap4_init_static_deps(void)
203} 213}
204 214
205/** 215/**
216 * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
217 * DRA7
218 *
219 * The dynamic dependency between MPUSS -> EMIF is broken and has
220 * not worked as expected. The hardware recommendation is to
221 * enable static dependencies for these to avoid system
222 * lock ups or random crashes.
223 */
224static inline int omap5_dra7_init_static_deps(void)
225{
226 struct clockdomain *mpuss_clkdm, *emif_clkdm;
227 int ret;
228
229 mpuss_clkdm = clkdm_lookup("mpu_clkdm");
230 emif_clkdm = clkdm_lookup("emif_clkdm");
231 if (!mpuss_clkdm || !emif_clkdm)
232 return -EINVAL;
233
234 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
235 if (ret)
236 pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");
237
238 return ret;
239}
240
241/**
206 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices 242 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
207 * 243 *
208 * Initializes basic stuff for power management functionality. 244 * Initializes basic stuff for power management functionality.
@@ -212,6 +248,9 @@ int __init omap4_pm_init_early(void)
212 if (cpu_is_omap446x()) 248 if (cpu_is_omap446x())
213 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; 249 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
214 250
251 if (soc_is_omap54xx() || soc_is_dra7xx())
252 pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;
253
215 return 0; 254 return 0;
216} 255}
217 256
@@ -239,10 +278,14 @@ int __init omap4_pm_init(void)
239 goto err2; 278 goto err2;
240 } 279 }
241 280
242 if (cpu_is_omap44xx()) { 281 if (cpu_is_omap44xx())
243 ret = omap4_init_static_deps(); 282 ret = omap4_init_static_deps();
244 if (ret) 283 else if (soc_is_omap54xx() || soc_is_dra7xx())
245 goto err2; 284 ret = omap5_dra7_init_static_deps();
285
286 if (ret) {
287 pr_err("Failed to initialise static dependencies.\n");
288 goto err2;
246 } 289 }
247 290
248 ret = omap4_mpuss_init(); 291 ret = omap4_mpuss_init();
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index faebd5f076af..7fb033eca0a5 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -546,7 +546,8 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
546 return -EINVAL; 546 return -EINVAL;
547 547
548 for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++) 548 for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
549 ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); 549 if (pwrdm->pwrdm_clkdms[i])
550 ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
550 551
551 return ret; 552 return ret;
552} 553}
@@ -1080,6 +1081,82 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
1080} 1081}
1081 1082
1082/** 1083/**
1084 * pwrdm_get_valid_lp_state() - Find best match deep power state
1085 * @pwrdm: power domain for which we want to find best match
1086 * @is_logic_state: Are we looking for logic state match here? Should
1087 * be one of PWRDM_xxx macro values
1088 * @req_state: requested power state
1089 *
1090 * Returns: closest match for requested power state. default fallback
1091 * is RET for logic state and ON for power state.
1092 *
1093 * This does a search from the power domain data looking for the
1094 * closest valid power domain state that the hardware can achieve.
1095 * PRCM definitions for PWRSTCTRL allows us to program whatever
1096 * configuration we'd like, and PRCM will actually attempt such
1097 * a transition, however if the powerdomain does not actually support it,
1098 * we endup with a hung system. The valid power domain states are already
1099 * available in our powerdomain data files. So this function tries to do
1100 * the following:
1101 * a) find if we have an exact match to the request - no issues.
1102 * b) else find if a deeper power state is possible.
1103 * c) failing which, it tries to find closest higher power state for the
1104 * request.
1105 */
1106u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
1107 bool is_logic_state, u8 req_state)
1108{
1109 u8 pwrdm_states = is_logic_state ? pwrdm->pwrsts_logic_ret :
1110 pwrdm->pwrsts;
1111 /* For logic, ret is highest and others, ON is highest */
1112 u8 default_pwrst = is_logic_state ? PWRDM_POWER_RET : PWRDM_POWER_ON;
1113 u8 new_pwrst;
1114 bool found;
1115
1116 /* If it is already supported, nothing to search */
1117 if (pwrdm_states & BIT(req_state))
1118 return req_state;
1119
1120 if (!req_state)
1121 goto up_search;
1122
1123 /*
1124 * So, we dont have a exact match
1125 * Can we get a deeper power state match?
1126 */
1127 new_pwrst = req_state - 1;
1128 found = true;
1129 while (!(pwrdm_states & BIT(new_pwrst))) {
1130 /* No match even at OFF? Not available */
1131 if (new_pwrst == PWRDM_POWER_OFF) {
1132 found = false;
1133 break;
1134 }
1135 new_pwrst--;
1136 }
1137
1138 if (found)
1139 goto done;
1140
1141up_search:
1142 /* OK, no deeper ones, can we get a higher match? */
1143 new_pwrst = req_state + 1;
1144 while (!(pwrdm_states & BIT(new_pwrst))) {
1145 if (new_pwrst > PWRDM_POWER_ON) {
1146 WARN(1, "powerdomain: %s: Fix max powerstate to ON\n",
1147 pwrdm->name);
1148 return PWRDM_POWER_ON;
1149 }
1150
1151 if (new_pwrst == default_pwrst)
1152 break;
1153 new_pwrst++;
1154 }
1155done:
1156 return new_pwrst;
1157}
1158
1159/**
1083 * omap_set_pwrdm_state - change a powerdomain's current power state 1160 * omap_set_pwrdm_state - change a powerdomain's current power state
1084 * @pwrdm: struct powerdomain * to change the power state of 1161 * @pwrdm: struct powerdomain * to change the power state of
1085 * @pwrst: power state to change to 1162 * @pwrst: power state to change to
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index f4727117f6cc..11bd4dd7d8d6 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -39,6 +39,7 @@
39#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET) 39#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
40#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 40#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
41#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) 41#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
42#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
42 43
43 44
44/* 45/*
@@ -219,6 +220,9 @@ struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
219 220
220int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); 221int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
221 222
223u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
224 bool is_logic_state, u8 req_state);
225
222int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); 226int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
223int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); 227int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
224int pwrdm_read_pwrst(struct powerdomain *pwrdm); 228int pwrdm_read_pwrst(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
index ce1d752af991..60d7ed8ef8ca 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -35,7 +35,7 @@ static struct powerdomain core_54xx_pwrdm = {
35 .prcm_offs = OMAP54XX_PRM_CORE_INST, 35 .prcm_offs = OMAP54XX_PRM_CORE_INST,
36 .prcm_partition = OMAP54XX_PRM_PARTITION, 36 .prcm_partition = OMAP54XX_PRM_PARTITION,
37 .pwrsts = PWRSTS_RET_ON, 37 .pwrsts = PWRSTS_RET_ON,
38 .pwrsts_logic_ret = PWRSTS_OFF_RET, 38 .pwrsts_logic_ret = PWRSTS_RET,
39 .banks = 5, 39 .banks = 5,
40 .pwrsts_mem_ret = { 40 .pwrsts_mem_ret = {
41 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 41 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
@@ -107,8 +107,8 @@ static struct powerdomain cpu0_54xx_pwrdm = {
107 .voltdm = { .name = "mpu" }, 107 .voltdm = { .name = "mpu" },
108 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, 108 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
109 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, 109 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
110 .pwrsts = PWRSTS_OFF_RET_ON, 110 .pwrsts = PWRSTS_RET_ON,
111 .pwrsts_logic_ret = PWRSTS_OFF_RET, 111 .pwrsts_logic_ret = PWRSTS_RET,
112 .banks = 1, 112 .banks = 1,
113 .pwrsts_mem_ret = { 113 .pwrsts_mem_ret = {
114 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 114 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
@@ -124,8 +124,8 @@ static struct powerdomain cpu1_54xx_pwrdm = {
124 .voltdm = { .name = "mpu" }, 124 .voltdm = { .name = "mpu" },
125 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, 125 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
126 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, 126 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
127 .pwrsts = PWRSTS_OFF_RET_ON, 127 .pwrsts = PWRSTS_RET_ON,
128 .pwrsts_logic_ret = PWRSTS_OFF_RET, 128 .pwrsts_logic_ret = PWRSTS_RET,
129 .banks = 1, 129 .banks = 1,
130 .pwrsts_mem_ret = { 130 .pwrsts_mem_ret = {
131 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 131 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
@@ -158,7 +158,7 @@ static struct powerdomain mpu_54xx_pwrdm = {
158 .prcm_offs = OMAP54XX_PRM_MPU_INST, 158 .prcm_offs = OMAP54XX_PRM_MPU_INST,
159 .prcm_partition = OMAP54XX_PRM_PARTITION, 159 .prcm_partition = OMAP54XX_PRM_PARTITION,
160 .pwrsts = PWRSTS_RET_ON, 160 .pwrsts = PWRSTS_RET_ON,
161 .pwrsts_logic_ret = PWRSTS_OFF_RET, 161 .pwrsts_logic_ret = PWRSTS_RET,
162 .banks = 2, 162 .banks = 2,
163 .pwrsts_mem_ret = { 163 .pwrsts_mem_ret = {
164 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 164 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 48151d1cfde0..287a2037aa16 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -160,8 +160,8 @@ static struct powerdomain core_7xx_pwrdm = {
160 .name = "core_pwrdm", 160 .name = "core_pwrdm",
161 .prcm_offs = DRA7XX_PRM_CORE_INST, 161 .prcm_offs = DRA7XX_PRM_CORE_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION, 162 .prcm_partition = DRA7XX_PRM_PARTITION,
163 .pwrsts = PWRSTS_RET_ON, 163 .pwrsts = PWRSTS_INA_ON,
164 .pwrsts_logic_ret = PWRSTS_OFF_RET, 164 .pwrsts_logic_ret = PWRSTS_RET,
165 .banks = 5, 165 .banks = 5,
166 .pwrsts_mem_ret = { 166 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
@@ -193,8 +193,8 @@ static struct powerdomain cpu0_7xx_pwrdm = {
193 .name = "cpu0_pwrdm", 193 .name = "cpu0_pwrdm",
194 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, 194 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
195 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 195 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
196 .pwrsts = PWRSTS_OFF_RET_ON, 196 .pwrsts = PWRSTS_RET_ON,
197 .pwrsts_logic_ret = PWRSTS_OFF_RET, 197 .pwrsts_logic_ret = PWRSTS_RET,
198 .banks = 1, 198 .banks = 1,
199 .pwrsts_mem_ret = { 199 .pwrsts_mem_ret = {
200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
@@ -209,8 +209,8 @@ static struct powerdomain cpu1_7xx_pwrdm = {
209 .name = "cpu1_pwrdm", 209 .name = "cpu1_pwrdm",
210 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, 210 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
211 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 211 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
212 .pwrsts = PWRSTS_OFF_RET_ON, 212 .pwrsts = PWRSTS_RET_ON,
213 .pwrsts_logic_ret = PWRSTS_OFF_RET, 213 .pwrsts_logic_ret = PWRSTS_RET,
214 .banks = 1, 214 .banks = 1,
215 .pwrsts_mem_ret = { 215 .pwrsts_mem_ret = {
216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
@@ -243,7 +243,7 @@ static struct powerdomain mpu_7xx_pwrdm = {
243 .prcm_offs = DRA7XX_PRM_MPU_INST, 243 .prcm_offs = DRA7XX_PRM_MPU_INST,
244 .prcm_partition = DRA7XX_PRM_PARTITION, 244 .prcm_partition = DRA7XX_PRM_PARTITION,
245 .pwrsts = PWRSTS_RET_ON, 245 .pwrsts = PWRSTS_RET_ON,
246 .pwrsts_logic_ret = PWRSTS_OFF_RET, 246 .pwrsts_logic_ret = PWRSTS_RET,
247 .banks = 2, 247 .banks = 2,
248 .pwrsts_mem_ret = { 248 .pwrsts_mem_ret = {
249 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 249 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 372de3edf4a5..ff08da385a2d 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -17,6 +17,7 @@
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <linux/of_irq.h>
20 21
21#include "soc.h" 22#include "soc.h"
22#include "common.h" 23#include "common.h"
@@ -673,6 +674,11 @@ int __init omap3xxx_prm_init(void)
673 return prm_register(&omap3xxx_prm_ll_data); 674 return prm_register(&omap3xxx_prm_ll_data);
674} 675}
675 676
677static struct of_device_id omap3_prm_dt_match_table[] = {
678 { .compatible = "ti,omap3-prm" },
679 { }
680};
681
676static int omap3xxx_prm_late_init(void) 682static int omap3xxx_prm_late_init(void)
677{ 683{
678 int ret; 684 int ret;
@@ -687,6 +693,18 @@ static int omap3xxx_prm_late_init(void)
687 omap3_prcm_irq_setup.reconfigure_io_chain = 693 omap3_prcm_irq_setup.reconfigure_io_chain =
688 omap3430_pre_es3_1_reconfigure_io_chain; 694 omap3430_pre_es3_1_reconfigure_io_chain;
689 695
696 if (of_have_populated_dt()) {
697 struct device_node *np;
698 int irq_num;
699
700 np = of_find_matching_node(NULL, omap3_prm_dt_match_table);
701 if (np) {
702 irq_num = of_irq_get(np, 0);
703 if (irq_num >= 0)
704 omap3_prcm_irq_setup.irq = irq_num;
705 }
706 }
707
690 omap3xxx_prm_enable_io_wakeup(); 708 omap3xxx_prm_enable_io_wakeup();
691 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); 709 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
692 if (!ret) 710 if (!ret)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a7f6ea27180a..0958d070d3db 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,6 +17,7 @@
17#include <linux/errno.h> 17#include <linux/errno.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/of_irq.h>
20 21
21 22
22#include "soc.h" 23#include "soc.h"
@@ -32,7 +33,6 @@
32/* Static data */ 33/* Static data */
33 34
34static const struct omap_prcm_irq omap4_prcm_irqs[] = { 35static const struct omap_prcm_irq omap4_prcm_irqs[] = {
35 OMAP_PRCM_IRQ("wkup", 0, 0),
36 OMAP_PRCM_IRQ("io", 9, 1), 36 OMAP_PRCM_IRQ("io", 9, 1),
37}; 37};
38 38
@@ -154,21 +154,36 @@ void omap4_prm_vp_clear_txdone(u8 vp_id)
154 154
155u32 omap4_prm_vcvp_read(u8 offset) 155u32 omap4_prm_vcvp_read(u8 offset)
156{ 156{
157 s32 inst = omap4_prmst_get_prm_dev_inst();
158
159 if (inst == PRM_INSTANCE_UNKNOWN)
160 return 0;
161
157 return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 162 return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
158 OMAP4430_PRM_DEVICE_INST, offset); 163 inst, offset);
159} 164}
160 165
161void omap4_prm_vcvp_write(u32 val, u8 offset) 166void omap4_prm_vcvp_write(u32 val, u8 offset)
162{ 167{
168 s32 inst = omap4_prmst_get_prm_dev_inst();
169
170 if (inst == PRM_INSTANCE_UNKNOWN)
171 return;
172
163 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, 173 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
164 OMAP4430_PRM_DEVICE_INST, offset); 174 inst, offset);
165} 175}
166 176
167u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) 177u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
168{ 178{
179 s32 inst = omap4_prmst_get_prm_dev_inst();
180
181 if (inst == PRM_INSTANCE_UNKNOWN)
182 return 0;
183
169 return omap4_prminst_rmw_inst_reg_bits(mask, bits, 184 return omap4_prminst_rmw_inst_reg_bits(mask, bits,
170 OMAP4430_PRM_PARTITION, 185 OMAP4430_PRM_PARTITION,
171 OMAP4430_PRM_DEVICE_INST, 186 inst,
172 offset); 187 offset);
173} 188}
174 189
@@ -275,14 +290,18 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
275void omap44xx_prm_reconfigure_io_chain(void) 290void omap44xx_prm_reconfigure_io_chain(void)
276{ 291{
277 int i = 0; 292 int i = 0;
293 s32 inst = omap4_prmst_get_prm_dev_inst();
294
295 if (inst == PRM_INSTANCE_UNKNOWN)
296 return;
278 297
279 /* Trigger WUCLKIN enable */ 298 /* Trigger WUCLKIN enable */
280 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 299 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
281 OMAP4430_WUCLK_CTRL_MASK, 300 OMAP4430_WUCLK_CTRL_MASK,
282 OMAP4430_PRM_DEVICE_INST, 301 inst,
283 OMAP4_PRM_IO_PMCTRL_OFFSET); 302 OMAP4_PRM_IO_PMCTRL_OFFSET);
284 omap_test_timeout( 303 omap_test_timeout(
285 (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 304 (((omap4_prm_read_inst_reg(inst,
286 OMAP4_PRM_IO_PMCTRL_OFFSET) & 305 OMAP4_PRM_IO_PMCTRL_OFFSET) &
287 OMAP4430_WUCLK_STATUS_MASK) >> 306 OMAP4430_WUCLK_STATUS_MASK) >>
288 OMAP4430_WUCLK_STATUS_SHIFT) == 1), 307 OMAP4430_WUCLK_STATUS_SHIFT) == 1),
@@ -292,10 +311,10 @@ void omap44xx_prm_reconfigure_io_chain(void)
292 311
293 /* Trigger WUCLKIN disable */ 312 /* Trigger WUCLKIN disable */
294 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, 313 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
295 OMAP4430_PRM_DEVICE_INST, 314 inst,
296 OMAP4_PRM_IO_PMCTRL_OFFSET); 315 OMAP4_PRM_IO_PMCTRL_OFFSET);
297 omap_test_timeout( 316 omap_test_timeout(
298 (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 317 (((omap4_prm_read_inst_reg(inst,
299 OMAP4_PRM_IO_PMCTRL_OFFSET) & 318 OMAP4_PRM_IO_PMCTRL_OFFSET) &
300 OMAP4430_WUCLK_STATUS_MASK) >> 319 OMAP4430_WUCLK_STATUS_MASK) >>
301 OMAP4430_WUCLK_STATUS_SHIFT) == 0), 320 OMAP4430_WUCLK_STATUS_SHIFT) == 0),
@@ -316,9 +335,14 @@ void omap44xx_prm_reconfigure_io_chain(void)
316 */ 335 */
317static void __init omap44xx_prm_enable_io_wakeup(void) 336static void __init omap44xx_prm_enable_io_wakeup(void)
318{ 337{
338 s32 inst = omap4_prmst_get_prm_dev_inst();
339
340 if (inst == PRM_INSTANCE_UNKNOWN)
341 return;
342
319 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, 343 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
320 OMAP4430_GLOBAL_WUEN_MASK, 344 OMAP4430_GLOBAL_WUEN_MASK,
321 OMAP4430_PRM_DEVICE_INST, 345 inst,
322 OMAP4_PRM_IO_PMCTRL_OFFSET); 346 OMAP4_PRM_IO_PMCTRL_OFFSET);
323} 347}
324 348
@@ -333,8 +357,13 @@ static u32 omap44xx_prm_read_reset_sources(void)
333 struct prm_reset_src_map *p; 357 struct prm_reset_src_map *p;
334 u32 r = 0; 358 u32 r = 0;
335 u32 v; 359 u32 v;
360 s32 inst = omap4_prmst_get_prm_dev_inst();
336 361
337 v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 362 if (inst == PRM_INSTANCE_UNKNOWN)
363 return 0;
364
365
366 v = omap4_prm_read_inst_reg(inst,
338 OMAP4_RM_RSTST); 367 OMAP4_RM_RSTST);
339 368
340 p = omap44xx_prm_reset_src_map; 369 p = omap44xx_prm_reset_src_map;
@@ -664,17 +693,56 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
664 693
665int __init omap44xx_prm_init(void) 694int __init omap44xx_prm_init(void)
666{ 695{
667 if (cpu_is_omap44xx()) 696 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
668 prm_features |= PRM_HAS_IO_WAKEUP; 697 prm_features |= PRM_HAS_IO_WAKEUP;
669 698
670 return prm_register(&omap44xx_prm_ll_data); 699 return prm_register(&omap44xx_prm_ll_data);
671} 700}
672 701
702static struct of_device_id omap_prm_dt_match_table[] = {
703 { .compatible = "ti,omap4-prm" },
704 { .compatible = "ti,omap5-prm" },
705 { .compatible = "ti,dra7-prm" },
706 { }
707};
708
673static int omap44xx_prm_late_init(void) 709static int omap44xx_prm_late_init(void)
674{ 710{
711 struct device_node *np;
712 int irq_num;
713
675 if (!(prm_features & PRM_HAS_IO_WAKEUP)) 714 if (!(prm_features & PRM_HAS_IO_WAKEUP))
676 return 0; 715 return 0;
677 716
717 /* OMAP4+ is DT only now */
718 if (!of_have_populated_dt())
719 return 0;
720
721 np = of_find_matching_node(NULL, omap_prm_dt_match_table);
722
723 if (!np) {
724 /* Default loaded up with OMAP4 values */
725 if (!cpu_is_omap44xx())
726 return 0;
727 } else {
728 irq_num = of_irq_get(np, 0);
729 /*
730 * Already have OMAP4 IRQ num. For all other platforms, we need
731 * IRQ numbers from DT
732 */
733 if (irq_num < 0 && !cpu_is_omap44xx()) {
734 if (irq_num == -EPROBE_DEFER)
735 return irq_num;
736
737 /* Have nothing to do */
738 return 0;
739 }
740
741 /* Once OMAP4 DT is filled as well */
742 if (irq_num >= 0)
743 omap4_prcm_irq_setup.irq = irq_num;
744 }
745
678 omap44xx_prm_enable_io_wakeup(); 746 omap44xx_prm_enable_io_wakeup();
679 747
680 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); 748 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 76ca320f007c..74054b813600 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -467,7 +467,7 @@ int prm_unregister(struct prm_ll_data *pld)
467 return 0; 467 return 0;
468} 468}
469 469
470static struct of_device_id omap_prcm_dt_match_table[] = { 470static const struct of_device_id omap_prcm_dt_match_table[] = {
471 { .compatible = "ti,am3-prcm" }, 471 { .compatible = "ti,am3-prcm" },
472 { .compatible = "ti,am3-scrm" }, 472 { .compatible = "ti,am3-scrm" },
473 { .compatible = "ti,am4-prcm" }, 473 { .compatible = "ti,am4-prcm" },
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 69f0dd08629c..225e0258d76d 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -31,6 +31,8 @@
31 31
32static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 32static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
33 33
34static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
35
34/** 36/**
35 * omap_prm_base_init - Populates the prm partitions 37 * omap_prm_base_init - Populates the prm partitions
36 * 38 *
@@ -43,6 +45,24 @@ void omap_prm_base_init(void)
43 _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 45 _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
44} 46}
45 47
48s32 omap4_prmst_get_prm_dev_inst(void)
49{
50 if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
51 return prm_dev_inst;
52
53 /* This cannot be done way early at boot.. as things are not setup */
54 if (cpu_is_omap44xx())
55 prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
56 else if (soc_is_omap54xx())
57 prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
58 else if (soc_is_dra7xx())
59 prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
60 else if (soc_is_am43xx())
61 prm_dev_inst = AM43XX_PRM_DEVICE_INST;
62
63 return prm_dev_inst;
64}
65
46/* Read a register in a PRM instance */ 66/* Read a register in a PRM instance */
47u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) 67u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
48{ 68{
@@ -169,28 +189,18 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
169void omap4_prminst_global_warm_sw_reset(void) 189void omap4_prminst_global_warm_sw_reset(void)
170{ 190{
171 u32 v; 191 u32 v;
172 s16 dev_inst; 192 s32 inst = omap4_prmst_get_prm_dev_inst();
173 193
174 if (cpu_is_omap44xx()) 194 if (inst == PRM_INSTANCE_UNKNOWN)
175 dev_inst = OMAP4430_PRM_DEVICE_INST;
176 else if (soc_is_omap54xx())
177 dev_inst = OMAP54XX_PRM_DEVICE_INST;
178 else if (soc_is_dra7xx())
179 dev_inst = DRA7XX_PRM_DEVICE_INST;
180 else if (soc_is_am43xx())
181 dev_inst = AM43XX_PRM_DEVICE_INST;
182 else
183 return; 195 return;
184 196
185 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst, 197 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
186 OMAP4_PRM_RSTCTRL_OFFSET); 198 OMAP4_PRM_RSTCTRL_OFFSET);
187 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 199 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
188 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 200 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
189 dev_inst, 201 inst, OMAP4_PRM_RSTCTRL_OFFSET);
190 OMAP4_PRM_RSTCTRL_OFFSET);
191 202
192 /* OCP barrier */ 203 /* OCP barrier */
193 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 204 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
194 dev_inst, 205 inst, OMAP4_PRM_RSTCTRL_OFFSET);
195 OMAP4_PRM_RSTCTRL_OFFSET);
196} 206}
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index a2ede2d65481..583aa3774571 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -12,6 +12,9 @@
12#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H 12#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
13#define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H 13#define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
14 14
15#define PRM_INSTANCE_UNKNOWN -1
16extern s32 omap4_prmst_get_prm_dev_inst(void);
17
15/* 18/*
16 * In an ideal world, we would not export these low-level functions, 19 * In an ideal world, we would not export these low-level functions,
17 * but this will probably take some time to fix properly 20 * but this will probably take some time to fix properly
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 7a42e1960c3b..d3a588cf3a6e 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -20,8 +20,8 @@ static int sr_class3_enable(struct omap_sr *sr)
20 unsigned long volt = voltdm_get_voltage(sr->voltdm); 20 unsigned long volt = voltdm_get_voltage(sr->voltdm);
21 21
22 if (!volt) { 22 if (!volt) {
23 pr_warning("%s: Curr voltage unknown. Cannot enable %s\n", 23 pr_warn("%s: Curr voltage unknown. Cannot enable %s\n",
24 __func__, sr->name); 24 __func__, sr->name);
25 return -ENODATA; 25 return -ENODATA;
26 } 26 }
27 27
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 1b91ef0c182a..d7cff2632d1e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -154,7 +154,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
154 154
155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data)); 155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
156 if (IS_ERR(pdev)) 156 if (IS_ERR(pdev))
157 pr_warning("%s: Could not build omap_device for %s: %s.\n\n", 157 pr_warn("%s: Could not build omap_device for %s: %s\n",
158 __func__, name, oh->name); 158 __func__, name, oh->name);
159exit: 159exit:
160 i++; 160 i++;
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index ddf1818af228..cd488b80ba36 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -32,12 +32,6 @@
32 32
33#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) 33#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
34#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) 34#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
35#ifdef CONFIG_OMAP4_ERRATA_I688
36#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
37#else
38#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
39#endif
40#define OMAP5_SRAM_PA 0x40300000
41 35
42#define SRAM_BOOTLOADER_SZ 0x00 36#define SRAM_BOOTLOADER_SZ 0x00
43 37
@@ -105,32 +99,14 @@ static void __init omap_detect_sram(void)
105 } else { 99 } else {
106 omap_sram_size = 0x8000; /* 32K */ 100 omap_sram_size = 0x8000; /* 32K */
107 } 101 }
108 } else if (cpu_is_omap44xx()) {
109 omap_sram_start = OMAP4_SRAM_PUB_PA;
110 omap_sram_size = 0xa000; /* 40K */
111 } else if (soc_is_omap54xx()) {
112 omap_sram_start = OMAP5_SRAM_PA;
113 omap_sram_size = SZ_128K; /* 128KB */
114 } else { 102 } else {
115 omap_sram_start = OMAP2_SRAM_PUB_PA; 103 omap_sram_start = OMAP2_SRAM_PUB_PA;
116 omap_sram_size = 0x800; /* 2K */ 104 omap_sram_size = 0x800; /* 2K */
117 } 105 }
118 } else { 106 } else {
119 if (soc_is_am33xx()) { 107 if (cpu_is_omap34xx()) {
120 omap_sram_start = AM33XX_SRAM_PA;
121 omap_sram_size = 0x10000; /* 64K */
122 } else if (soc_is_am43xx()) {
123 omap_sram_start = AM33XX_SRAM_PA;
124 omap_sram_size = SZ_256K;
125 } else if (cpu_is_omap34xx()) {
126 omap_sram_start = OMAP3_SRAM_PA; 108 omap_sram_start = OMAP3_SRAM_PA;
127 omap_sram_size = 0x10000; /* 64K */ 109 omap_sram_size = 0x10000; /* 64K */
128 } else if (cpu_is_omap44xx()) {
129 omap_sram_start = OMAP4_SRAM_PA;
130 omap_sram_size = 0xe000; /* 56K */
131 } else if (soc_is_omap54xx()) {
132 omap_sram_start = OMAP5_SRAM_PA;
133 omap_sram_size = SZ_128K; /* 128KB */
134 } else { 110 } else {
135 omap_sram_start = OMAP2_SRAM_PA; 111 omap_sram_start = OMAP2_SRAM_PA;
136 if (cpu_is_omap242x()) 112 if (cpu_is_omap242x())
@@ -148,12 +124,6 @@ static void __init omap2_map_sram(void)
148{ 124{
149 int cached = 1; 125 int cached = 1;
150 126
151#ifdef CONFIG_OMAP4_ERRATA_I688
152 if (cpu_is_omap44xx()) {
153 omap_sram_start += PAGE_SIZE;
154 omap_sram_size -= SZ_16K;
155 }
156#endif
157 if (cpu_is_omap34xx()) { 127 if (cpu_is_omap34xx()) {
158 /* 128 /*
159 * SRAM must be marked as non-cached on OMAP3 since the 129 * SRAM must be marked as non-cached on OMAP3 since the
@@ -285,11 +255,6 @@ static inline int omap34xx_sram_init(void)
285} 255}
286#endif /* CONFIG_ARCH_OMAP3 */ 256#endif /* CONFIG_ARCH_OMAP3 */
287 257
288static inline int am33xx_sram_init(void)
289{
290 return 0;
291}
292
293int __init omap_sram_init(void) 258int __init omap_sram_init(void)
294{ 259{
295 omap_detect_sram(); 260 omap_detect_sram();
@@ -299,8 +264,6 @@ int __init omap_sram_init(void)
299 omap242x_sram_init(); 264 omap242x_sram_init();
300 else if (cpu_is_omap2430()) 265 else if (cpu_is_omap2430())
301 omap243x_sram_init(); 266 omap243x_sram_init();
302 else if (soc_is_am33xx())
303 am33xx_sram_init();
304 else if (cpu_is_omap34xx()) 267 else if (cpu_is_omap34xx())
305 omap34xx_sram_init(); 268 omap34xx_sram_init();
306 269
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
index ca7277c2a9ee..948d3edefc38 100644
--- a/arch/arm/mach-omap2/sram.h
+++ b/arch/arm/mach-omap2/sram.h
@@ -74,10 +74,3 @@ static inline void omap_push_sram_idle(void) {}
74 */ 74 */
75#define OMAP2_SRAM_PA 0x40200000 75#define OMAP2_SRAM_PA 0x40200000
76#define OMAP3_SRAM_PA 0x40200000 76#define OMAP3_SRAM_PA 0x40200000
77#ifdef CONFIG_OMAP4_ERRATA_I688
78#define OMAP4_SRAM_PA 0x40304000
79#define OMAP4_SRAM_VA 0xfe404000
80#else
81#define OMAP4_SRAM_PA 0x40300000
82#endif
83#define AM33XX_SRAM_PA 0x40300000
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 43d03fbf4c0b..4f61148ec168 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -141,7 +141,7 @@ static struct property device_disabled = {
141 .value = "disabled", 141 .value = "disabled",
142}; 142};
143 143
144static struct of_device_id omap_timer_match[] __initdata = { 144static const struct of_device_id omap_timer_match[] __initconst = {
145 { .compatible = "ti,omap2420-timer", }, 145 { .compatible = "ti,omap2420-timer", },
146 { .compatible = "ti,omap3430-timer", }, 146 { .compatible = "ti,omap3430-timer", },
147 { .compatible = "ti,omap4430-timer", }, 147 { .compatible = "ti,omap4430-timer", },
@@ -162,7 +162,7 @@ static struct of_device_id omap_timer_match[] __initdata = {
162 * the timer node in device-tree as disabled, to prevent the kernel from 162 * the timer node in device-tree as disabled, to prevent the kernel from
163 * registering this timer as a platform device and so no one else can use it. 163 * registering this timer as a platform device and so no one else can use it.
164 */ 164 */
165static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, 165static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
166 const char *property) 166 const char *property)
167{ 167{
168 struct device_node *np; 168 struct device_node *np;
@@ -388,7 +388,7 @@ static u64 notrace dmtimer_read_sched_clock(void)
388 return 0; 388 return 0;
389} 389}
390 390
391static struct of_device_id omap_counter_match[] __initdata = { 391static const struct of_device_id omap_counter_match[] __initconst = {
392 { .compatible = "ti,omap-counter32k", }, 392 { .compatible = "ti,omap-counter32k", },
393 { } 393 { }
394}; 394};
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index a4628a9e760c..be9ef834fa81 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -198,7 +198,7 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
198 loop_cnt++; 198 loop_cnt++;
199 199
200 if (retries_cnt > 10) { 200 if (retries_cnt > 10) {
201 pr_warning("%s: Retry count exceeded\n", __func__); 201 pr_warn("%s: Retry count exceeded\n", __func__);
202 return -ETIMEDOUT; 202 return -ETIMEDOUT;
203 } 203 }
204 204
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3ac8fe1d8213..3783b8625f0f 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -55,7 +55,7 @@ static LIST_HEAD(voltdm_list);
55unsigned long voltdm_get_voltage(struct voltagedomain *voltdm) 55unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
56{ 56{
57 if (!voltdm || IS_ERR(voltdm)) { 57 if (!voltdm || IS_ERR(voltdm)) {
58 pr_warning("%s: VDD specified does not exist!\n", __func__); 58 pr_warn("%s: VDD specified does not exist!\n", __func__);
59 return 0; 59 return 0;
60 } 60 }
61 61
@@ -77,7 +77,7 @@ int voltdm_scale(struct voltagedomain *voltdm,
77 unsigned long volt = 0; 77 unsigned long volt = 0;
78 78
79 if (!voltdm || IS_ERR(voltdm)) { 79 if (!voltdm || IS_ERR(voltdm)) {
80 pr_warning("%s: VDD specified does not exist!\n", __func__); 80 pr_warn("%s: VDD specified does not exist!\n", __func__);
81 return -EINVAL; 81 return -EINVAL;
82 } 82 }
83 83
@@ -96,8 +96,8 @@ int voltdm_scale(struct voltagedomain *voltdm,
96 } 96 }
97 97
98 if (!volt) { 98 if (!volt) {
99 pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n", 99 pr_warn("%s: not scaling. OPP voltage for %lu, not found.\n",
100 __func__, target_volt); 100 __func__, target_volt);
101 return -EINVAL; 101 return -EINVAL;
102 } 102 }
103 103
@@ -122,7 +122,7 @@ void voltdm_reset(struct voltagedomain *voltdm)
122 unsigned long target_volt; 122 unsigned long target_volt;
123 123
124 if (!voltdm || IS_ERR(voltdm)) { 124 if (!voltdm || IS_ERR(voltdm)) {
125 pr_warning("%s: VDD specified does not exist!\n", __func__); 125 pr_warn("%s: VDD specified does not exist!\n", __func__);
126 return; 126 return;
127 } 127 }
128 128
@@ -152,7 +152,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
152 struct omap_volt_data **volt_data) 152 struct omap_volt_data **volt_data)
153{ 153{
154 if (!voltdm || IS_ERR(voltdm)) { 154 if (!voltdm || IS_ERR(voltdm)) {
155 pr_warning("%s: VDD specified does not exist!\n", __func__); 155 pr_warn("%s: VDD specified does not exist!\n", __func__);
156 return; 156 return;
157 } 157 }
158 158
@@ -180,12 +180,12 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
180 int i; 180 int i;
181 181
182 if (!voltdm || IS_ERR(voltdm)) { 182 if (!voltdm || IS_ERR(voltdm)) {
183 pr_warning("%s: VDD specified does not exist!\n", __func__); 183 pr_warn("%s: VDD specified does not exist!\n", __func__);
184 return ERR_PTR(-EINVAL); 184 return ERR_PTR(-EINVAL);
185 } 185 }
186 186
187 if (!voltdm->volt_data) { 187 if (!voltdm->volt_data) {
188 pr_warning("%s: voltage table does not exist for vdd_%s\n", 188 pr_warn("%s: voltage table does not exist for vdd_%s\n",
189 __func__, voltdm->name); 189 __func__, voltdm->name);
190 return ERR_PTR(-ENODATA); 190 return ERR_PTR(-ENODATA);
191 } 191 }
@@ -214,7 +214,7 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
214 struct omap_voltdm_pmic *pmic) 214 struct omap_voltdm_pmic *pmic)
215{ 215{
216 if (!voltdm || IS_ERR(voltdm)) { 216 if (!voltdm || IS_ERR(voltdm)) {
217 pr_warning("%s: VDD specified does not exist!\n", __func__); 217 pr_warn("%s: VDD specified does not exist!\n", __func__);
218 return -EINVAL; 218 return -EINVAL;
219 } 219 }
220 220
@@ -237,7 +237,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
237 int voltscale_method) 237 int voltscale_method)
238{ 238{
239 if (!voltdm || IS_ERR(voltdm)) { 239 if (!voltdm || IS_ERR(voltdm)) {
240 pr_warning("%s: VDD specified does not exist!\n", __func__); 240 pr_warn("%s: VDD specified does not exist!\n", __func__);
241 return; 241 return;
242 } 242 }
243 243
@@ -279,7 +279,7 @@ int __init omap_voltage_late_init(void)
279 279
280 sys_ck = clk_get(NULL, voltdm->sys_clk.name); 280 sys_ck = clk_get(NULL, voltdm->sys_clk.name);
281 if (IS_ERR(sys_ck)) { 281 if (IS_ERR(sys_ck)) {
282 pr_warning("%s: Could not get sys clk.\n", __func__); 282 pr_warn("%s: Could not get sys clk.\n", __func__);
283 return -EINVAL; 283 return -EINVAL;
284 } 284 }
285 voltdm->sys_clk.rate = clk_get_rate(sys_ck); 285 voltdm->sys_clk.rate = clk_get_rate(sys_ck);
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 97d6607d447a..ff0a68cf7439 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -93,8 +93,8 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh)
93 udelay(oh->class->sysc->srst_udelay); 93 udelay(oh->class->sysc->srst_udelay);
94 94
95 if (c == MAX_MODULE_SOFTRESET_WAIT) 95 if (c == MAX_MODULE_SOFTRESET_WAIT)
96 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 96 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
97 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 97 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
98 else 98 else
99 pr_debug("%s: %s: softreset in %d usec\n", __func__, 99 pr_debug("%s: %s: softreset in %d usec\n", __func__,
100 oh->name, c); 100 oh->name, c);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 56edeab17b68..09d2a26985da 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -550,7 +550,7 @@ static int __init dns323_identify_rev(void)
550 break; 550 break;
551 } 551 }
552 if (i >= 1000) { 552 if (i >= 1000) {
553 pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n"); 553 pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n");
554 return DNS323_REV_B1; 554 return DNS323_REV_B1;
555 } 555 }
556 writel((3 << 21) /* phy ID reg */ | 556 writel((3 << 21) /* phy ID reg */ |
@@ -562,7 +562,7 @@ static int __init dns323_identify_rev(void)
562 break; 562 break;
563 } 563 }
564 if (i >= 1000) { 564 if (i >= 1000) {
565 pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n"); 565 pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n");
566 return DNS323_REV_B1; 566 return DNS323_REV_B1;
567 } 567 }
568 pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff); 568 pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
@@ -577,8 +577,8 @@ static int __init dns323_identify_rev(void)
577 case 0x0e10: /* MV88E1118 */ 577 case 0x0e10: /* MV88E1118 */
578 return DNS323_REV_C1; 578 return DNS323_REV_C1;
579 default: 579 default:
580 pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n", 580 pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
581 reg & 0xffff); 581 reg & 0xffff);
582 } 582 }
583 return DNS323_REV_B1; 583 return DNS323_REV_B1;
584} 584}
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 6208d125c1b9..12086745c9fd 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -349,7 +349,7 @@ static void __init tsp2_init(void)
349 gpio_free(TSP2_RTC_GPIO); 349 gpio_free(TSP2_RTC_GPIO);
350 } 350 }
351 if (tsp2_i2c_rtc.irq == 0) 351 if (tsp2_i2c_rtc.irq == 0)
352 pr_warning("tsp2_init: failed to get RTC IRQ\n"); 352 pr_warn("tsp2_init: failed to get RTC IRQ\n");
353 i2c_register_board_info(0, &tsp2_i2c_rtc, 1); 353 i2c_register_board_info(0, &tsp2_i2c_rtc, 1);
354 354
355 /* register Terastation Pro II specific power-off method */ 355 /* register Terastation Pro II specific power-off method */
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9136797addb2..c725b7cb9875 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -314,7 +314,7 @@ static void __init qnap_ts209_init(void)
314 gpio_free(TS209_RTC_GPIO); 314 gpio_free(TS209_RTC_GPIO);
315 } 315 }
316 if (qnap_ts209_i2c_rtc.irq == 0) 316 if (qnap_ts209_i2c_rtc.irq == 0)
317 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); 317 pr_warn("qnap_ts209_init: failed to get RTC IRQ\n");
318 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); 318 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
319 319
320 /* register tsx09 specific power-off method */ 320 /* register tsx09 specific power-off method */
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 5c079d312015..cf2ab531cabc 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -302,7 +302,7 @@ static void __init qnap_ts409_init(void)
302 gpio_free(TS409_RTC_GPIO); 302 gpio_free(TS409_RTC_GPIO);
303 } 303 }
304 if (qnap_ts409_i2c_rtc.irq == 0) 304 if (qnap_ts409_i2c_rtc.irq == 0)
305 pr_warning("qnap_ts409_init: failed to get RTC IRQ\n"); 305 pr_warn("qnap_ts409_init: failed to get RTC IRQ\n");
306 i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1); 306 i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
307 platform_device_register(&ts409_leds); 307 platform_device_register(&ts409_leds);
308 308
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index db16dae441e2..1b704d35cf5b 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -403,8 +403,8 @@ static void ts78xx_fpga_supports(void)
403 /* enable devices if magic matches */ 403 /* enable devices if magic matches */
404 switch ((ts78xx_fpga.id >> 8) & 0xffffff) { 404 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
405 case TS7800_FPGA_MAGIC: 405 case TS7800_FPGA_MAGIC:
406 pr_warning("unrecognised FPGA revision 0x%.2x\n", 406 pr_warn("unrecognised FPGA revision 0x%.2x\n",
407 ts78xx_fpga.id & 0xff); 407 ts78xx_fpga.id & 0xff);
408 ts78xx_fpga.supports.ts_rtc.present = 1; 408 ts78xx_fpga.supports.ts_rtc.present = 1;
409 ts78xx_fpga.supports.ts_nand.present = 1; 409 ts78xx_fpga.supports.ts_nand.present = 1;
410 ts78xx_fpga.supports.ts_rng.present = 1; 410 ts78xx_fpga.supports.ts_rng.present = 1;
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 666094315ab1..ac7b3eabbd85 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -1071,9 +1071,47 @@ static struct resource pxa3xx_resource_ssp4[] = {
1071 }, 1071 },
1072}; 1072};
1073 1073
1074/*
1075 * PXA3xx SSP is basically equivalent to PXA27x.
1076 * However, we need to register the device by the correct name in order to
1077 * make the driver set the correct internal type, hence we provide specific
1078 * platform_devices for each of them.
1079 */
1080struct platform_device pxa3xx_device_ssp1 = {
1081 .name = "pxa3xx-ssp",
1082 .id = 0,
1083 .dev = {
1084 .dma_mask = &pxa27x_ssp1_dma_mask,
1085 .coherent_dma_mask = DMA_BIT_MASK(32),
1086 },
1087 .resource = pxa27x_resource_ssp1,
1088 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
1089};
1090
1091struct platform_device pxa3xx_device_ssp2 = {
1092 .name = "pxa3xx-ssp",
1093 .id = 1,
1094 .dev = {
1095 .dma_mask = &pxa27x_ssp2_dma_mask,
1096 .coherent_dma_mask = DMA_BIT_MASK(32),
1097 },
1098 .resource = pxa27x_resource_ssp2,
1099 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
1100};
1101
1102struct platform_device pxa3xx_device_ssp3 = {
1103 .name = "pxa3xx-ssp",
1104 .id = 2,
1105 .dev = {
1106 .dma_mask = &pxa27x_ssp3_dma_mask,
1107 .coherent_dma_mask = DMA_BIT_MASK(32),
1108 },
1109 .resource = pxa27x_resource_ssp3,
1110 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
1111};
1112
1074struct platform_device pxa3xx_device_ssp4 = { 1113struct platform_device pxa3xx_device_ssp4 = {
1075 /* PXA3xx SSP is basically equivalent to PXA27x */ 1114 .name = "pxa3xx-ssp",
1076 .name = "pxa27x-ssp",
1077 .id = 3, 1115 .id = 3,
1078 .dev = { 1116 .dev = {
1079 .dma_mask = &pxa3xx_ssp4_dma_mask, 1117 .dma_mask = &pxa3xx_ssp4_dma_mask,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 0f3fd0d65b12..4a13c32fb705 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -27,6 +27,9 @@ extern struct platform_device pxa25x_device_assp;
27extern struct platform_device pxa27x_device_ssp1; 27extern struct platform_device pxa27x_device_ssp1;
28extern struct platform_device pxa27x_device_ssp2; 28extern struct platform_device pxa27x_device_ssp2;
29extern struct platform_device pxa27x_device_ssp3; 29extern struct platform_device pxa27x_device_ssp3;
30extern struct platform_device pxa3xx_device_ssp1;
31extern struct platform_device pxa3xx_device_ssp2;
32extern struct platform_device pxa3xx_device_ssp3;
30extern struct platform_device pxa3xx_device_ssp4; 33extern struct platform_device pxa3xx_device_ssp4;
31 34
32extern struct platform_device pxa25x_device_pwm0; 35extern struct platform_device pxa25x_device_pwm0;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 593ccd35ca97..edcbd9c0bcb2 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -84,10 +84,10 @@ static struct clk_lookup pxa3xx_clkregs[] = {
84 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 84 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
85 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), 85 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
86 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 86 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
87 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 87 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa3xx-ssp.0", NULL),
88 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 88 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa3xx-ssp.1", NULL),
89 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), 89 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa3xx-ssp.2", NULL),
90 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), 90 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa3xx-ssp.3", NULL),
91 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), 91 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
92 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), 92 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
93 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 93 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
@@ -452,9 +452,9 @@ static struct platform_device *devices[] __initdata = {
452 &pxa_device_asoc_platform, 452 &pxa_device_asoc_platform,
453 &sa1100_device_rtc, 453 &sa1100_device_rtc,
454 &pxa_device_rtc, 454 &pxa_device_rtc,
455 &pxa27x_device_ssp1, 455 &pxa3xx_device_ssp1,
456 &pxa27x_device_ssp2, 456 &pxa3xx_device_ssp2,
457 &pxa27x_device_ssp3, 457 &pxa3xx_device_ssp3,
458 &pxa3xx_device_ssp4, 458 &pxa3xx_device_ssp4,
459 &pxa27x_device_pwm0, 459 &pxa27x_device_pwm0,
460 &pxa27x_device_pwm1, 460 &pxa27x_device_pwm1,
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index c437a9941726..6d8bbf7d39d8 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,8 @@ static const char * const qcom_dt_match[] __initconst = {
18 "qcom,apq8064", 18 "qcom,apq8064",
19 "qcom,apq8074-dragonboard", 19 "qcom,apq8074-dragonboard",
20 "qcom,apq8084", 20 "qcom,apq8084",
21 "qcom,ipq8062",
22 "qcom,ipq8064",
21 "qcom,msm8660-surf", 23 "qcom,msm8660-surf",
22 "qcom,msm8960-cdp", 24 "qcom,msm8960-cdp",
23 NULL 25 NULL
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d1686696ca41..ac5803cac98d 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -4,6 +4,7 @@ config ARCH_ROCKCHIP
4 select PINCTRL_ROCKCHIP 4 select PINCTRL_ROCKCHIP
5 select ARCH_HAS_RESET_CONTROLLER 5 select ARCH_HAS_RESET_CONTROLLER
6 select ARCH_REQUIRE_GPIOLIB 6 select ARCH_REQUIRE_GPIOLIB
7 select ARM_AMBA
7 select ARM_GIC 8 select ARM_GIC
8 select CACHE_L2X0 9 select CACHE_L2X0
9 select HAVE_ARM_ARCH_TIMER 10 select HAVE_ARM_ARCH_TIMER
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index ad5316ae524e..9eb22297cbe1 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -32,7 +32,6 @@ config CPU_S3C2410
32 select S3C2410_DMA if S3C24XX_DMA 32 select S3C2410_DMA if S3C24XX_DMA
33 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ 33 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
34 select S3C2410_PM if PM 34 select S3C2410_PM if PM
35 select SAMSUNG_WDT_RESET
36 help 35 help
37 Support for S3C2410 and S3C2410A family from the S3C24XX line 36 Support for S3C2410 and S3C2410A family from the S3C24XX line
38 of Samsung Mobile CPUs. 37 of Samsung Mobile CPUs.
@@ -76,7 +75,6 @@ config CPU_S3C2442
76config CPU_S3C244X 75config CPU_S3C244X
77 def_bool y 76 def_bool y
78 depends on CPU_S3C2440 || CPU_S3C2442 77 depends on CPU_S3C2440 || CPU_S3C2442
79 select SAMSUNG_WDT_RESET
80 78
81config CPU_S3C2443 79config CPU_S3C2443
82 bool "SAMSUNG S3C2443" 80 bool "SAMSUNG S3C2443"
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 44fa95df9262..bf50328107bd 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -51,7 +51,6 @@
51#include <plat/devs.h> 51#include <plat/devs.h>
52#include <plat/cpu-freq.h> 52#include <plat/cpu-freq.h>
53#include <plat/pwm-core.h> 53#include <plat/pwm-core.h>
54#include <plat/watchdog-reset.h>
55 54
56#include "common.h" 55#include "common.h"
57 56
@@ -513,7 +512,6 @@ struct platform_device s3c2443_device_dma = {
513void __init s3c2410_init_clocks(int xtal) 512void __init s3c2410_init_clocks(int xtal)
514{ 513{
515 s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); 514 s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
516 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
517} 515}
518#endif 516#endif
519 517
@@ -535,7 +533,6 @@ void __init s3c2416_init_clocks(int xtal)
535void __init s3c2440_init_clocks(int xtal) 533void __init s3c2440_init_clocks(int xtal)
536{ 534{
537 s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); 535 s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
538 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
539} 536}
540#endif 537#endif
541 538
@@ -543,7 +540,6 @@ void __init s3c2440_init_clocks(int xtal)
543void __init s3c2442_init_clocks(int xtal) 540void __init s3c2442_init_clocks(int xtal)
544{ 541{
545 s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR); 542 s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
546 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
547} 543}
548#endif 544#endif
549 545
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ac3ff12a0601..c7ac7e61a22e 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -22,7 +22,6 @@ extern int s3c2410a_init(void);
22extern void s3c2410_map_io(void); 22extern void s3c2410_map_io(void);
23extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); 23extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
24extern void s3c2410_init_clocks(int xtal); 24extern void s3c2410_init_clocks(int xtal);
25extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
26extern void s3c2410_init_irq(void); 25extern void s3c2410_init_irq(void);
27#else 26#else
28#define s3c2410_init_clocks NULL 27#define s3c2410_init_clocks NULL
@@ -38,7 +37,6 @@ extern void s3c2412_map_io(void);
38extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); 37extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
39extern void s3c2412_init_clocks(int xtal); 38extern void s3c2412_init_clocks(int xtal);
40extern int s3c2412_baseclk_add(void); 39extern int s3c2412_baseclk_add(void);
41extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
42extern void s3c2412_init_irq(void); 40extern void s3c2412_init_irq(void);
43#else 41#else
44#define s3c2412_init_clocks NULL 42#define s3c2412_init_clocks NULL
@@ -53,7 +51,6 @@ extern void s3c2416_map_io(void);
53extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); 51extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
54extern void s3c2416_init_clocks(int xtal); 52extern void s3c2416_init_clocks(int xtal);
55extern int s3c2416_baseclk_add(void); 53extern int s3c2416_baseclk_add(void);
56extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
57extern void s3c2416_init_irq(void); 54extern void s3c2416_init_irq(void);
58 55
59extern struct syscore_ops s3c2416_irq_syscore_ops; 56extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -67,7 +64,6 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
67#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) 64#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
68extern void s3c244x_map_io(void); 65extern void s3c244x_map_io(void);
69extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); 66extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
70extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
71#else 67#else
72#define s3c244x_init_uarts NULL 68#define s3c244x_init_uarts NULL
73#endif 69#endif
@@ -98,7 +94,6 @@ extern void s3c2443_map_io(void);
98extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); 94extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
99extern void s3c2443_init_clocks(int xtal); 95extern void s3c2443_init_clocks(int xtal);
100extern int s3c2443_baseclk_add(void); 96extern int s3c2443_baseclk_add(void);
101extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
102extern void s3c2443_init_irq(void); 97extern void s3c2443_init_irq(void);
103#else 98#else
104#define s3c2443_init_clocks NULL 99#define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
index c3feff3c0488..ffe37bdb9f59 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
@@ -42,8 +42,6 @@
42#define S3C2443_URSTCON S3C2443_CLKREG(0x88) 42#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
43#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) 43#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
44 44
45#define S3C2443_SWRST_RESET (0x533c2443)
46
47#define S3C2443_PLLCON_OFF (1<<24) 45#define S3C2443_PLLCON_OFF (1<<24)
48 46
49#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) 47#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 5157e250dd13..3e63777a109f 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -247,5 +247,4 @@ MACHINE_START(AML_M5900, "AML_M5900")
247 .init_irq = s3c2410_init_irq, 247 .init_irq = s3c2410_init_irq,
248 .init_machine = amlm5900_init, 248 .init_machine = amlm5900_init,
249 .init_time = amlm5900_init_time, 249 .init_time = amlm5900_init_time,
250 .restart = s3c2410_restart,
251MACHINE_END 250MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index e053581cab0b..d03df0df01fa 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -430,5 +430,4 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
430 .init_machine = anubis_init, 430 .init_machine = anubis_init,
431 .init_irq = s3c2440_init_irq, 431 .init_irq = s3c2440_init_irq,
432 .init_time = anubis_init_time, 432 .init_time = anubis_init_time,
433 .restart = s3c244x_restart,
434MACHINE_END 433MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 9db768f448a5..9ae170fef2a7 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -218,5 +218,4 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
218 .init_machine = at2440evb_init, 218 .init_machine = at2440evb_init,
219 .init_irq = s3c2440_init_irq, 219 .init_irq = s3c2440_init_irq,
220 .init_time = at2440evb_init_time, 220 .init_time = at2440evb_init_time,
221 .restart = s3c244x_restart,
222MACHINE_END 221MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index f9112b801a33..ed07cf392d4b 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -591,5 +591,4 @@ MACHINE_START(BAST, "Simtec-BAST")
591 .init_irq = s3c2410_init_irq, 591 .init_irq = s3c2410_init_irq,
592 .init_machine = bast_init, 592 .init_machine = bast_init,
593 .init_time = bast_init_time, 593 .init_time = bast_init_time,
594 .restart = s3c2410_restart,
595MACHINE_END 594MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index fc3a08d0cb3f..6d1e0b9c5b27 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -597,5 +597,4 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
597 .init_irq = s3c2442_init_irq, 597 .init_irq = s3c2442_init_irq,
598 .init_machine = gta02_machine_init, 598 .init_machine = gta02_machine_init,
599 .init_time = gta02_init_time, 599 .init_time = gta02_init_time,
600 .restart = s3c244x_restart,
601MACHINE_END 600MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index c9a99bbad545..d35ddc1d9991 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -747,5 +747,4 @@ MACHINE_START(H1940, "IPAQ-H1940")
747 .init_irq = s3c2410_init_irq, 747 .init_irq = s3c2410_init_irq,
748 .init_machine = h1940_init, 748 .init_machine = h1940_init,
749 .init_time = h1940_init_time, 749 .init_time = h1940_init_time,
750 .restart = s3c2410_restart,
751MACHINE_END 750MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 7804d3c6991b..7d99fe8f6157 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -670,5 +670,4 @@ MACHINE_START(JIVE, "JIVE")
670 .map_io = jive_map_io, 670 .map_io = jive_map_io,
671 .init_machine = jive_machine_init, 671 .init_machine = jive_machine_init,
672 .init_time = jive_init_time, 672 .init_time = jive_init_time,
673 .restart = s3c2412_restart,
674MACHINE_END 673MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 5cc40ec1d254..a8521684a7f5 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -695,5 +695,4 @@ MACHINE_START(MINI2440, "MINI2440")
695 .init_machine = mini2440_init, 695 .init_machine = mini2440_init,
696 .init_irq = s3c2440_init_irq, 696 .init_irq = s3c2440_init_irq,
697 .init_time = mini2440_init_time, 697 .init_time = mini2440_init_time,
698 .restart = s3c244x_restart,
699MACHINE_END 698MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 3ac2a54348d6..171c1f11fd22 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -599,7 +599,6 @@ MACHINE_START(N30, "Acer-N30")
599 .init_machine = n30_init, 599 .init_machine = n30_init,
600 .init_irq = s3c2410_init_irq, 600 .init_irq = s3c2410_init_irq,
601 .map_io = n30_map_io, 601 .map_io = n30_map_io,
602 .restart = s3c2410_restart,
603MACHINE_END 602MACHINE_END
604 603
605MACHINE_START(N35, "Acer-N35") 604MACHINE_START(N35, "Acer-N35")
@@ -610,5 +609,4 @@ MACHINE_START(N35, "Acer-N35")
610 .init_machine = n30_init, 609 .init_machine = n30_init,
611 .init_irq = s3c2410_init_irq, 610 .init_irq = s3c2410_init_irq,
612 .map_io = n30_map_io, 611 .map_io = n30_map_io,
613 .restart = s3c2410_restart,
614MACHINE_END 612MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index c82c281ce351..2a61d13dcd6c 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -159,5 +159,4 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
159 .init_machine = nexcoder_init, 159 .init_machine = nexcoder_init,
160 .init_irq = s3c2440_init_irq, 160 .init_irq = s3c2440_init_irq,
161 .init_time = nexcoder_init_time, 161 .init_time = nexcoder_init_time,
162 .restart = s3c244x_restart,
163MACHINE_END 162MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 189147b80eca..2f6fdc326835 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -412,5 +412,4 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
412 .init_irq = s3c2440_init_irq, 412 .init_irq = s3c2440_init_irq,
413 .init_machine = osiris_init, 413 .init_machine = osiris_init,
414 .init_time = osiris_init_time, 414 .init_time = osiris_init_time,
415 .restart = s3c244x_restart,
416MACHINE_END 415MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 45833001186d..345a484b93cc 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -122,5 +122,4 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
122 .init_machine = otom11_init, 122 .init_machine = otom11_init,
123 .init_irq = s3c2410_init_irq, 123 .init_irq = s3c2410_init_irq,
124 .init_time = otom11_init_time, 124 .init_time = otom11_init_time,
125 .restart = s3c2410_restart,
126MACHINE_END 125MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 228c9094519d..984516e8307a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -352,5 +352,4 @@ MACHINE_START(QT2410, "QT2410")
352 .init_irq = s3c2410_init_irq, 352 .init_irq = s3c2410_init_irq,
353 .init_machine = qt2410_machine_init, 353 .init_machine = qt2410_machine_init,
354 .init_time = qt2410_init_time, 354 .init_time = qt2410_init_time,
355 .restart = s3c2410_restart,
356MACHINE_END 355MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index e2c6541909c1..c3f2682d0c62 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -812,5 +812,4 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
812 .init_irq = s3c2442_init_irq, 812 .init_irq = s3c2442_init_irq,
813 .init_machine = rx1950_init_machine, 813 .init_machine = rx1950_init_machine,
814 .init_time = rx1950_init_time, 814 .init_time = rx1950_init_time,
815 .restart = s3c244x_restart,
816MACHINE_END 815MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 6e749ec3a2ea..cf55196f89ca 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -215,5 +215,4 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
215 .init_irq = s3c2440_init_irq, 215 .init_irq = s3c2440_init_irq,
216 .init_machine = rx3715_init_machine, 216 .init_machine = rx3715_init_machine,
217 .init_time = rx3715_init_time, 217 .init_time = rx3715_init_time,
218 .restart = s3c244x_restart,
219MACHINE_END 218MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
index e4dcb9aa2ca2..f886478b88c5 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -51,5 +51,4 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
51 .map_io = s3c2416_dt_map_io, 51 .map_io = s3c2416_dt_map_io,
52 .init_irq = irqchip_init, 52 .init_irq = irqchip_init,
53 .init_machine = s3c2416_dt_machine_init, 53 .init_machine = s3c2416_dt_machine_init,
54 .restart = s3c2416_restart,
55MACHINE_END 54MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index 419fadd6e446..27dd6605e395 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -124,5 +124,4 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
124 .init_irq = s3c2410_init_irq, 124 .init_irq = s3c2410_init_irq,
125 .init_machine = smdk2410_init, 125 .init_machine = smdk2410_init,
126 .init_time = smdk2410_init_time, 126 .init_time = smdk2410_init_time,
127 .restart = s3c2410_restart,
128MACHINE_END 127MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 10726bf84920..586e4a3b8d5d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -138,7 +138,6 @@ MACHINE_START(S3C2413, "S3C2413")
138 .map_io = smdk2413_map_io, 138 .map_io = smdk2413_map_io,
139 .init_machine = smdk2413_machine_init, 139 .init_machine = smdk2413_machine_init,
140 .init_time = samsung_timer_init, 140 .init_time = samsung_timer_init,
141 .restart = s3c2412_restart,
142MACHINE_END 141MACHINE_END
143 142
144MACHINE_START(SMDK2412, "SMDK2412") 143MACHINE_START(SMDK2412, "SMDK2412")
@@ -150,7 +149,6 @@ MACHINE_START(SMDK2412, "SMDK2412")
150 .map_io = smdk2413_map_io, 149 .map_io = smdk2413_map_io,
151 .init_machine = smdk2413_machine_init, 150 .init_machine = smdk2413_machine_init,
152 .init_time = samsung_timer_init, 151 .init_time = samsung_timer_init,
153 .restart = s3c2412_restart,
154MACHINE_END 152MACHINE_END
155 153
156MACHINE_START(SMDK2413, "SMDK2413") 154MACHINE_START(SMDK2413, "SMDK2413")
@@ -162,5 +160,4 @@ MACHINE_START(SMDK2413, "SMDK2413")
162 .map_io = smdk2413_map_io, 160 .map_io = smdk2413_map_io,
163 .init_machine = smdk2413_machine_init, 161 .init_machine = smdk2413_machine_init,
164 .init_time = smdk2413_init_time, 162 .init_time = smdk2413_init_time,
165 .restart = s3c2412_restart,
166MACHINE_END 163MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 24189e8e8560..86394f72d29e 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -262,5 +262,4 @@ MACHINE_START(SMDK2416, "SMDK2416")
262 .map_io = smdk2416_map_io, 262 .map_io = smdk2416_map_io,
263 .init_machine = smdk2416_machine_init, 263 .init_machine = smdk2416_machine_init,
264 .init_time = smdk2416_init_time, 264 .init_time = smdk2416_init_time,
265 .restart = s3c2416_restart,
266MACHINE_END 265MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 5fb89c0ae17a..9bb96bfbb420 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -185,5 +185,4 @@ MACHINE_START(S3C2440, "SMDK2440")
185 .map_io = smdk2440_map_io, 185 .map_io = smdk2440_map_io,
186 .init_machine = smdk2440_machine_init, 186 .init_machine = smdk2440_machine_init,
187 .init_time = smdk2440_init_time, 187 .init_time = smdk2440_init_time,
188 .restart = s3c244x_restart,
189MACHINE_END 188MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 0ed77614dcfe..87fe5c5b8073 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -150,5 +150,4 @@ MACHINE_START(SMDK2443, "SMDK2443")
150 .map_io = smdk2443_map_io, 150 .map_io = smdk2443_map_io,
151 .init_machine = smdk2443_machine_init, 151 .init_machine = smdk2443_machine_init,
152 .init_time = smdk2443_init_time, 152 .init_time = smdk2443_init_time,
153 .restart = s3c2443_restart,
154MACHINE_END 153MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index c616ca2d409e..2deb62f92fb2 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -157,5 +157,4 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
157 .init_irq = s3c2410_init_irq, 157 .init_irq = s3c2410_init_irq,
158 .init_machine = tct_hammer_init, 158 .init_machine = tct_hammer_init,
159 .init_time = tct_hammer_init_time, 159 .init_time = tct_hammer_init_time,
160 .restart = s3c2410_restart,
161MACHINE_END 160MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index f88c584c3001..89f32bd3f01b 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -340,5 +340,4 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
340 .init_machine = vr1000_init, 340 .init_machine = vr1000_init,
341 .init_irq = s3c2410_init_irq, 341 .init_irq = s3c2410_init_irq,
342 .init_time = vr1000_init_time, 342 .init_time = vr1000_init_time,
343 .restart = s3c2410_restart,
344MACHINE_END 343MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 9d4f64750698..b4460d5f7011 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -165,5 +165,4 @@ MACHINE_START(VSTMS, "VSTMS")
165 .init_machine = vstms_init, 165 .init_machine = vstms_init,
166 .map_io = vstms_map_io, 166 .map_io = vstms_map_io,
167 .init_time = vstms_init_time, 167 .init_time = vstms_init_time,
168 .restart = s3c2412_restart,
169MACHINE_END 168MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 5ffe828cd659..2a6985a4a0ff 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -42,7 +42,6 @@
42#include <plat/cpu.h> 42#include <plat/cpu.h>
43#include <plat/devs.h> 43#include <plat/devs.h>
44#include <plat/pm.h> 44#include <plat/pm.h>
45#include <plat/watchdog-reset.h>
46 45
47#include <plat/gpio-core.h> 46#include <plat/gpio-core.h>
48#include <plat/gpio-cfg.h> 47#include <plat/gpio-cfg.h>
@@ -135,15 +134,3 @@ int __init s3c2410a_init(void)
135 s3c2410_dev.bus = &s3c2410a_subsys; 134 s3c2410_dev.bus = &s3c2410a_subsys;
136 return s3c2410_init(); 135 return s3c2410_init();
137} 136}
138
139void s3c2410_restart(enum reboot_mode mode, const char *cmd)
140{
141 if (mode == REBOOT_SOFT) {
142 soft_restart(0);
143 }
144
145 samsung_wdt_reset();
146
147 /* we'll take a jump through zero as a poor second */
148 soft_restart(0);
149}
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 569f3f5a6c71..ecf2c77ab88b 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -48,9 +48,6 @@
48#include "regs-dsc.h" 48#include "regs-dsc.h"
49#include "s3c2412-power.h" 49#include "s3c2412-power.h"
50 50
51#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
52#define S3C2412_SWRST_RESET (0x533C2412)
53
54#ifndef CONFIG_CPU_S3C2412_ONLY 51#ifndef CONFIG_CPU_S3C2412_ONLY
55void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; 52void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
56 53
@@ -128,26 +125,6 @@ static void s3c2412_idle(void)
128 cpu_do_idle(); 125 cpu_do_idle();
129} 126}
130 127
131void s3c2412_restart(enum reboot_mode mode, const char *cmd)
132{
133 if (mode == REBOOT_SOFT)
134 soft_restart(0);
135
136 /* errata "Watch-dog/Software Reset Problem" specifies that
137 * this reset must be done with the SYSCLK sourced from
138 * EXTCLK instead of FOUT to avoid a glitch in the reset
139 * mechanism.
140 *
141 * See the watchdog section of the S3C2412 manual for more
142 * information on this fix.
143 */
144
145 __raw_writel(0x00, S3C2412_CLKSRC);
146 __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
147
148 mdelay(1);
149}
150
151/* s3c2412_map_io 128/* s3c2412_map_io
152 * 129 *
153 * register the standard cpu IO areas, and any passed in from the 130 * register the standard cpu IO areas, and any passed in from the
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 9fe260ae11e1..bfd4da86deb8 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -81,14 +81,6 @@ static struct device s3c2416_dev = {
81 .bus = &s3c2416_subsys, 81 .bus = &s3c2416_subsys,
82}; 82};
83 83
84void s3c2416_restart(enum reboot_mode mode, const char *cmd)
85{
86 if (mode == REBOOT_SOFT)
87 soft_restart(0);
88
89 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
90}
91
92int __init s3c2416_init(void) 84int __init s3c2416_init(void)
93{ 85{
94 printk(KERN_INFO "S3C2416: Initializing architecture\n"); 86 printk(KERN_INFO "S3C2416: Initializing architecture\n");
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index c7a804d0348e..87b6b89d8ee7 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -61,14 +61,6 @@ static struct device s3c2443_dev = {
61 .bus = &s3c2443_subsys, 61 .bus = &s3c2443_subsys,
62}; 62};
63 63
64void s3c2443_restart(enum reboot_mode mode, const char *cmd)
65{
66 if (mode == REBOOT_SOFT)
67 soft_restart(0);
68
69 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
70}
71
72int __init s3c2443_init(void) 64int __init s3c2443_init(void)
73{ 65{
74 printk("S3C2443: Initialising architecture\n"); 66 printk("S3C2443: Initialising architecture\n");
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index d1c3e65785a1..177f97802745 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -42,7 +42,6 @@
42#include <plat/cpu.h> 42#include <plat/cpu.h>
43#include <plat/pm.h> 43#include <plat/pm.h>
44#include <plat/nand-core.h> 44#include <plat/nand-core.h>
45#include <plat/watchdog-reset.h>
46 45
47#include "common.h" 46#include "common.h"
48#include "regs-dsc.h" 47#include "regs-dsc.h"
@@ -137,14 +136,3 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
137 .suspend = s3c244x_suspend, 136 .suspend = s3c244x_suspend,
138 .resume = s3c244x_resume, 137 .resume = s3c244x_resume,
139}; 138};
140
141void s3c244x_restart(enum reboot_mode mode, const char *cmd)
142{
143 if (mode == REBOOT_SOFT)
144 soft_restart(0);
145
146 samsung_wdt_reset();
147
148 /* we'll take a jump through zero as a poor second */
149 soft_restart(0);
150}
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 5c45aae675b6..16547f2641a3 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -440,8 +440,3 @@ void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
440 /* if all else fails, or mode was for soft, jump to 0 */ 440 /* if all else fails, or mode was for soft, jump to 0 */
441 soft_restart(0); 441 soft_restart(0);
442} 442}
443
444void __init s3c64xx_init_late(void)
445{
446 s3c64xx_pm_late_initcall();
447}
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 7043e7a3a67e..9eb864412911 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -23,7 +23,6 @@ void s3c64xx_init_irq(u32 vic0, u32 vic1);
23void s3c64xx_init_io(struct map_desc *mach_desc, int size); 23void s3c64xx_init_io(struct map_desc *mach_desc, int size);
24 24
25void s3c64xx_restart(enum reboot_mode mode, const char *cmd); 25void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
26void s3c64xx_init_late(void);
27 26
28void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, 27void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
29 unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base); 28 unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
@@ -52,12 +51,6 @@ extern void s3c6410_map_io(void);
52#define s3c6410_init NULL 51#define s3c6410_init NULL
53#endif 52#endif
54 53
55#ifdef CONFIG_PM
56int __init s3c64xx_pm_late_initcall(void);
57#else
58static inline int s3c64xx_pm_late_initcall(void) { return 0; }
59#endif
60
61#ifdef CONFIG_S3C64XX_PL080 54#ifdef CONFIG_S3C64XX_PL080
62extern struct pl08x_platform_data s3c64xx_dma0_plat_data; 55extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
63extern struct pl08x_platform_data s3c64xx_dma1_plat_data; 56extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 60576dfbea8d..6224c67f5061 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -233,7 +233,6 @@ MACHINE_START(ANW6410, "A&W6410")
233 .init_irq = s3c6410_init_irq, 233 .init_irq = s3c6410_init_irq,
234 .map_io = anw6410_map_io, 234 .map_io = anw6410_map_io,
235 .init_machine = anw6410_machine_init, 235 .init_machine = anw6410_machine_init,
236 .init_late = s3c64xx_init_late,
237 .init_time = samsung_timer_init, 236 .init_time = samsung_timer_init,
238 .restart = s3c64xx_restart, 237 .restart = s3c64xx_restart,
239MACHINE_END 238MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index fe116334afda..10b913baab28 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -857,7 +857,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
857 .init_irq = s3c6410_init_irq, 857 .init_irq = s3c6410_init_irq,
858 .map_io = crag6410_map_io, 858 .map_io = crag6410_map_io,
859 .init_machine = crag6410_machine_init, 859 .init_machine = crag6410_machine_init,
860 .init_late = s3c64xx_init_late,
861 .init_time = samsung_timer_init, 860 .init_time = samsung_timer_init,
862 .restart = s3c64xx_restart, 861 .restart = s3c64xx_restart,
863MACHINE_END 862MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 19e8feb908fd..e4b087c58ee6 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -277,7 +277,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
277 .init_irq = s3c6410_init_irq, 277 .init_irq = s3c6410_init_irq,
278 .map_io = hmt_map_io, 278 .map_io = hmt_map_io,
279 .init_machine = hmt_machine_init, 279 .init_machine = hmt_machine_init,
280 .init_late = s3c64xx_init_late,
281 .init_time = samsung_timer_init, 280 .init_time = samsung_timer_init,
282 .restart = s3c64xx_restart, 281 .restart = s3c64xx_restart,
283MACHINE_END 282MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 9cbc07602ef3..ab61af50bfb9 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -366,7 +366,6 @@ MACHINE_START(MINI6410, "MINI6410")
366 .init_irq = s3c6410_init_irq, 366 .init_irq = s3c6410_init_irq,
367 .map_io = mini6410_map_io, 367 .map_io = mini6410_map_io,
368 .init_machine = mini6410_machine_init, 368 .init_machine = mini6410_machine_init,
369 .init_late = s3c64xx_init_late,
370 .init_time = samsung_timer_init, 369 .init_time = samsung_timer_init,
371 .restart = s3c64xx_restart, 370 .restart = s3c64xx_restart,
372MACHINE_END 371MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 4bae7dc49eea..80cb1446f69f 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -103,7 +103,6 @@ MACHINE_START(NCP, "NCP")
103 .init_irq = s3c6410_init_irq, 103 .init_irq = s3c6410_init_irq,
104 .map_io = ncp_map_io, 104 .map_io = ncp_map_io,
105 .init_machine = ncp_machine_init, 105 .init_machine = ncp_machine_init,
106 .init_late = s3c64xx_init_late,
107 .init_time = samsung_timer_init, 106 .init_time = samsung_timer_init,
108 .restart = s3c64xx_restart, 107 .restart = s3c64xx_restart,
109MACHINE_END 108MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index fbad2af1ef16..85fa9598b980 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -335,7 +335,6 @@ MACHINE_START(REAL6410, "REAL6410")
335 .init_irq = s3c6410_init_irq, 335 .init_irq = s3c6410_init_irq,
336 .map_io = real6410_map_io, 336 .map_io = real6410_map_io,
337 .init_machine = real6410_machine_init, 337 .init_machine = real6410_machine_init,
338 .init_late = s3c64xx_init_late,
339 .init_time = samsung_timer_init, 338 .init_time = samsung_timer_init,
340 .restart = s3c64xx_restart, 339 .restart = s3c64xx_restart,
341MACHINE_END 340MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index dec4c08e834f..33224ab36fac 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -156,7 +156,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
156 .init_irq = s3c6410_init_irq, 156 .init_irq = s3c6410_init_irq,
157 .map_io = smartq_map_io, 157 .map_io = smartq_map_io,
158 .init_machine = smartq5_machine_init, 158 .init_machine = smartq5_machine_init,
159 .init_late = s3c64xx_init_late,
160 .init_time = samsung_timer_init, 159 .init_time = samsung_timer_init,
161 .restart = s3c64xx_restart, 160 .restart = s3c64xx_restart,
162MACHINE_END 161MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 27b322069c7d..fc7fece22fb0 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -172,7 +172,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
172 .init_irq = s3c6410_init_irq, 172 .init_irq = s3c6410_init_irq,
173 .map_io = smartq_map_io, 173 .map_io = smartq_map_io,
174 .init_machine = smartq7_machine_init, 174 .init_machine = smartq7_machine_init,
175 .init_late = s3c64xx_init_late,
176 .init_time = samsung_timer_init, 175 .init_time = samsung_timer_init,
177 .restart = s3c64xx_restart, 176 .restart = s3c64xx_restart,
178MACHINE_END 177MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 910749768340..6f425126a735 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -92,7 +92,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
92 .init_irq = s3c6400_init_irq, 92 .init_irq = s3c6400_init_irq,
93 .map_io = smdk6400_map_io, 93 .map_io = smdk6400_map_io,
94 .init_machine = smdk6400_machine_init, 94 .init_machine = smdk6400_machine_init,
95 .init_late = s3c64xx_init_late,
96 .init_time = samsung_timer_init, 95 .init_time = samsung_timer_init,
97 .restart = s3c64xx_restart, 96 .restart = s3c64xx_restart,
98MACHINE_END 97MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 1dc86d76b530..661eb662d051 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -705,7 +705,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
705 .init_irq = s3c6410_init_irq, 705 .init_irq = s3c6410_init_irq,
706 .map_io = smdk6410_map_io, 706 .map_io = smdk6410_map_io,
707 .init_machine = smdk6410_machine_init, 707 .init_machine = smdk6410_machine_init,
708 .init_late = s3c64xx_init_late,
709 .init_time = samsung_timer_init, 708 .init_time = samsung_timer_init,
710 .restart = s3c64xx_restart, 709 .restart = s3c64xx_restart,
711MACHINE_END 710MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 6b37694fa335..aaf7bea4032f 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -347,10 +347,3 @@ static __init int s3c64xx_pm_initcall(void)
347 return 0; 347 return 0;
348} 348}
349arch_initcall(s3c64xx_pm_initcall); 349arch_initcall(s3c64xx_pm_initcall);
350
351int __init s3c64xx_pm_late_initcall(void)
352{
353 pm_genpd_poweroff_unused();
354
355 return 0;
356}
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 123163dd2ab0..21b4b13c5ab7 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -24,9 +24,8 @@
24 24
25#include <plat/pm-common.h> 25#include <plat/pm-common.h>
26 26
27#include <mach/regs-clock.h>
28
29#include "common.h" 27#include "common.h"
28#include "regs-clock.h"
30 29
31static struct sleep_save s5pv210_core_save[] = { 30static struct sleep_save s5pv210_core_save[] = {
32 /* Clock ETC */ 31 /* Clock ETC */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h
index b14ffcd7f6cc..4640f0f03c12 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/regs-clock.h
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/regs-clock.h 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c
index 53feff33d129..43eb1eaea0c9 100644
--- a/arch/arm/mach-s5pv210/s5pv210.c
+++ b/arch/arm/mach-s5pv210/s5pv210.c
@@ -18,9 +18,9 @@
18#include <asm/system_misc.h> 18#include <asm/system_misc.h>
19 19
20#include <plat/map-base.h> 20#include <plat/map-base.h>
21#include <mach/regs-clock.h>
22 21
23#include "common.h" 22#include "common.h"
23#include "regs-clock.h"
24 24
25static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname, 25static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
26 int depth, void *data) 26 int depth, void *data)
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 04f9784ff0ed..c6f6ed1cbed0 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -58,6 +58,7 @@ config SA1100_H3100
58 bool "Compaq iPAQ H3100" 58 bool "Compaq iPAQ H3100"
59 select ARM_SA1110_CPUFREQ 59 select ARM_SA1110_CPUFREQ
60 select HTC_EGPIO 60 select HTC_EGPIO
61 select MFD_IPAQ_MICRO
61 help 62 help
62 Say Y here if you intend to run this kernel on the Compaq iPAQ 63 Say Y here if you intend to run this kernel on the Compaq iPAQ
63 H3100 handheld computer. Information about this machine and the 64 H3100 handheld computer. Information about this machine and the
@@ -69,6 +70,7 @@ config SA1100_H3600
69 bool "Compaq iPAQ H3600/H3700" 70 bool "Compaq iPAQ H3600/H3700"
70 select ARM_SA1110_CPUFREQ 71 select ARM_SA1110_CPUFREQ
71 select HTC_EGPIO 72 select HTC_EGPIO
73 select MFD_IPAQ_MICRO
72 help 74 help
73 Say Y here if you intend to run this kernel on the Compaq iPAQ 75 Say Y here if you intend to run this kernel on the Compaq iPAQ
74 H3600 handheld computer. Information about this machine and the 76 H3600 handheld computer. Information about this machine and the
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index c79bf467fb7f..b1d4faa12f9a 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -25,6 +25,7 @@
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26 26
27#include <mach/h3xxx.h> 27#include <mach/h3xxx.h>
28#include <mach/irqs.h>
28 29
29#include "generic.h" 30#include "generic.h"
30 31
@@ -244,9 +245,23 @@ static struct platform_device h3xxx_keys = {
244 }, 245 },
245}; 246};
246 247
248static struct resource h3xxx_micro_resources[] = {
249 DEFINE_RES_MEM(0x80010000, SZ_4K),
250 DEFINE_RES_MEM(0x80020000, SZ_4K),
251 DEFINE_RES_IRQ(IRQ_Ser1UART),
252};
253
254struct platform_device h3xxx_micro_asic = {
255 .name = "ipaq-h3xxx-micro",
256 .id = -1,
257 .resource = h3xxx_micro_resources,
258 .num_resources = ARRAY_SIZE(h3xxx_micro_resources),
259};
260
247static struct platform_device *h3xxx_devices[] = { 261static struct platform_device *h3xxx_devices[] = {
248 &h3xxx_egpio, 262 &h3xxx_egpio,
249 &h3xxx_keys, 263 &h3xxx_keys,
264 &h3xxx_micro_asic,
250}; 265};
251 266
252void __init h3xxx_mach_init(void) 267void __init h3xxx_mach_init(void)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1e6c51c7c2d5..21f457b56c01 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,30 @@
1config ARCH_SHMOBILE 1config ARCH_SHMOBILE
2 bool 2 bool
3 3
4config PM_RCAR
5 bool
6
7config PM_RMOBILE
8 bool
9
10config ARCH_RCAR_GEN1
11 bool
12 select PM_RCAR if PM || SMP
13 select RENESAS_INTC_IRQPIN
14 select SYS_SUPPORTS_SH_TMU
15
16config ARCH_RCAR_GEN2
17 bool
18 select PM_RCAR if PM || SMP
19 select RENESAS_IRQC
20 select SYS_SUPPORTS_SH_CMT
21
22config ARCH_RMOBILE
23 bool
24 select PM_RMOBILE if PM && !ARCH_SHMOBILE_MULTI
25 select SYS_SUPPORTS_SH_CMT
26 select SYS_SUPPORTS_SH_TMU
27
4menuconfig ARCH_SHMOBILE_MULTI 28menuconfig ARCH_SHMOBILE_MULTI
5 bool "Renesas ARM SoCs" if ARCH_MULTI_V7 29 bool "Renesas ARM SoCs" if ARCH_MULTI_V7
6 depends on MMU 30 depends on MMU
@@ -26,26 +50,28 @@ config ARCH_R7S72100
26 bool "RZ/A1H (R7S72100)" 50 bool "RZ/A1H (R7S72100)"
27 select SYS_SUPPORTS_SH_MTU2 51 select SYS_SUPPORTS_SH_MTU2
28 52
53config ARCH_R8A7740
54 bool "R-Mobile A1 (R8A77400)"
55 select ARCH_RMOBILE
56 select RENESAS_INTC_IRQPIN
57
29config ARCH_R8A7779 58config ARCH_R8A7779
30 bool "R-Car H1 (R8A77790)" 59 bool "R-Car H1 (R8A77790)"
31 select RENESAS_INTC_IRQPIN 60 select ARCH_RCAR_GEN1
32 select SYS_SUPPORTS_SH_TMU
33 61
34config ARCH_R8A7790 62config ARCH_R8A7790
35 bool "R-Car H2 (R8A77900)" 63 bool "R-Car H2 (R8A77900)"
36 select RENESAS_IRQC 64 select ARCH_RCAR_GEN2
37 select SYS_SUPPORTS_SH_CMT
38 65
39config ARCH_R8A7791 66config ARCH_R8A7791
40 bool "R-Car M2 (R8A77910)" 67 bool "R-Car M2-W (R8A77910)"
41 select RENESAS_IRQC 68 select ARCH_RCAR_GEN2
42 select SYS_SUPPORTS_SH_CMT
43 69
44comment "Renesas ARM SoCs Board Type" 70config ARCH_R8A7794
71 bool "R-Car E2 (R8A77940)"
72 select ARCH_RCAR_GEN2
45 73
46config MACH_GENMAI 74comment "Renesas ARM SoCs Board Type"
47 bool "Genmai board"
48 depends on ARCH_R7S72100
49 75
50config MACH_KOELSCH 76config MACH_KOELSCH
51 bool "Koelsch board" 77 bool "Koelsch board"
@@ -71,94 +97,62 @@ comment "Renesas ARM SoCs System Type"
71 97
72config ARCH_SH7372 98config ARCH_SH7372
73 bool "SH-Mobile AP4 (SH7372)" 99 bool "SH-Mobile AP4 (SH7372)"
100 select ARCH_RMOBILE
74 select ARCH_WANT_OPTIONAL_GPIOLIB 101 select ARCH_WANT_OPTIONAL_GPIOLIB
75 select ARM_CPU_SUSPEND if PM || CPU_IDLE 102 select ARM_CPU_SUSPEND if PM || CPU_IDLE
76 select CPU_V7
77 select SH_CLK_CPG
78 select SH_INTC 103 select SH_INTC
79 select SYS_SUPPORTS_SH_CMT
80 select SYS_SUPPORTS_SH_TMU
81 104
82config ARCH_SH73A0 105config ARCH_SH73A0
83 bool "SH-Mobile AG5 (R8A73A00)" 106 bool "SH-Mobile AG5 (R8A73A00)"
107 select ARCH_RMOBILE
84 select ARCH_WANT_OPTIONAL_GPIOLIB 108 select ARCH_WANT_OPTIONAL_GPIOLIB
85 select ARM_GIC 109 select ARM_GIC
86 select CPU_V7
87 select I2C 110 select I2C
88 select SH_CLK_CPG
89 select SH_INTC 111 select SH_INTC
90 select RENESAS_INTC_IRQPIN 112 select RENESAS_INTC_IRQPIN
91 select SYS_SUPPORTS_SH_CMT
92 select SYS_SUPPORTS_SH_TMU
93 113
94config ARCH_R8A73A4 114config ARCH_R8A73A4
95 bool "R-Mobile APE6 (R8A73A40)" 115 bool "R-Mobile APE6 (R8A73A40)"
116 select ARCH_RMOBILE
96 select ARCH_WANT_OPTIONAL_GPIOLIB 117 select ARCH_WANT_OPTIONAL_GPIOLIB
97 select ARM_GIC 118 select ARM_GIC
98 select CPU_V7
99 select SH_CLK_CPG
100 select RENESAS_IRQC 119 select RENESAS_IRQC
101 select SYS_SUPPORTS_SH_CMT
102 select SYS_SUPPORTS_SH_TMU
103 120
104config ARCH_R8A7740 121config ARCH_R8A7740
105 bool "R-Mobile A1 (R8A77400)" 122 bool "R-Mobile A1 (R8A77400)"
123 select ARCH_RMOBILE
106 select ARCH_WANT_OPTIONAL_GPIOLIB 124 select ARCH_WANT_OPTIONAL_GPIOLIB
107 select ARM_GIC 125 select ARM_GIC
108 select CPU_V7
109 select SH_CLK_CPG
110 select RENESAS_INTC_IRQPIN 126 select RENESAS_INTC_IRQPIN
111 select SYS_SUPPORTS_SH_CMT
112 select SYS_SUPPORTS_SH_TMU
113 127
114config ARCH_R8A7778 128config ARCH_R8A7778
115 bool "R-Car M1A (R8A77781)" 129 bool "R-Car M1A (R8A77781)"
130 select ARCH_RCAR_GEN1
116 select ARCH_WANT_OPTIONAL_GPIOLIB 131 select ARCH_WANT_OPTIONAL_GPIOLIB
117 select CPU_V7
118 select SH_CLK_CPG
119 select ARM_GIC 132 select ARM_GIC
120 select SYS_SUPPORTS_SH_TMU
121 select RENESAS_INTC_IRQPIN
122 133
123config ARCH_R8A7779 134config ARCH_R8A7779
124 bool "R-Car H1 (R8A77790)" 135 bool "R-Car H1 (R8A77790)"
136 select ARCH_RCAR_GEN1
125 select ARCH_WANT_OPTIONAL_GPIOLIB 137 select ARCH_WANT_OPTIONAL_GPIOLIB
126 select ARM_GIC 138 select ARM_GIC
127 select CPU_V7
128 select SH_CLK_CPG
129 select RENESAS_INTC_IRQPIN
130 select SYS_SUPPORTS_SH_TMU
131 139
132config ARCH_R8A7790 140config ARCH_R8A7790
133 bool "R-Car H2 (R8A77900)" 141 bool "R-Car H2 (R8A77900)"
142 select ARCH_RCAR_GEN2
134 select ARCH_WANT_OPTIONAL_GPIOLIB 143 select ARCH_WANT_OPTIONAL_GPIOLIB
135 select ARM_GIC 144 select ARM_GIC
136 select CPU_V7
137 select MIGHT_HAVE_PCI 145 select MIGHT_HAVE_PCI
138 select SH_CLK_CPG
139 select RENESAS_IRQC
140 select SYS_SUPPORTS_SH_CMT
141 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 146 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
142 147
143config ARCH_R8A7791 148config ARCH_R8A7791
144 bool "R-Car M2 (R8A77910)" 149 bool "R-Car M2-W (R8A77910)"
150 select ARCH_RCAR_GEN2
145 select ARCH_WANT_OPTIONAL_GPIOLIB 151 select ARCH_WANT_OPTIONAL_GPIOLIB
146 select ARM_GIC 152 select ARM_GIC
147 select CPU_V7
148 select MIGHT_HAVE_PCI 153 select MIGHT_HAVE_PCI
149 select SH_CLK_CPG
150 select RENESAS_IRQC
151 select SYS_SUPPORTS_SH_CMT
152 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 154 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
153 155
154config ARCH_R7S72100
155 bool "RZ/A1H (R7S72100)"
156 select ARCH_WANT_OPTIONAL_GPIOLIB
157 select ARM_GIC
158 select CPU_V7
159 select SH_CLK_CPG
160 select SYS_SUPPORTS_SH_MTU2
161
162comment "Renesas ARM SoCs Board Type" 156comment "Renesas ARM SoCs Board Type"
163 157
164config MACH_APE6EVM 158config MACH_APE6EVM
@@ -197,21 +191,6 @@ config MACH_ARMADILLO800EVA
197 select SND_SOC_WM8978 if SND_SIMPLE_CARD 191 select SND_SOC_WM8978 if SND_SIMPLE_CARD
198 select USE_OF 192 select USE_OF
199 193
200config MACH_ARMADILLO800EVA_REFERENCE
201 bool "Armadillo-800 EVA board - Reference Device Tree Implementation"
202 depends on ARCH_R8A7740
203 select ARCH_REQUIRE_GPIOLIB
204 select REGULATOR_FIXED_VOLTAGE if REGULATOR
205 select SMSC_PHY if SH_ETH
206 select SND_SOC_WM8978 if SND_SIMPLE_CARD
207 select USE_OF
208 ---help---
209 Use reference implementation of Armadillo800 EVA board support
210 which makes greater use of device tree at the expense
211 of not supporting a number of devices.
212
213 This is intended to aid developers
214
215config MACH_BOCKW 194config MACH_BOCKW
216 bool "BOCK-W platform" 195 bool "BOCK-W platform"
217 depends on ARCH_R8A7778 196 depends on ARCH_R8A7778
@@ -234,11 +213,6 @@ config MACH_BOCKW_REFERENCE
234 213
235 This is intended to aid developers 214 This is intended to aid developers
236 215
237config MACH_GENMAI
238 bool "Genmai board"
239 depends on ARCH_R7S72100
240 select USE_OF
241
242config MACH_MARZEN 216config MACH_MARZEN
243 bool "MARZEN board" 217 bool "MARZEN board"
244 depends on ARCH_R8A7779 218 depends on ARCH_R8A7779
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe3878a1a69a..e20f2786ec72 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -2,21 +2,19 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/mach-shmobile/include
6
7# Common objects 5# Common objects
8obj-y := timer.o console.o 6obj-y := timer.o console.o
9 7
10# CPU objects 8# CPU objects
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o 9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o pm-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o 10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o
13obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o 11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
14obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o 12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o
15obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o 13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
16obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o 14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o
17obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o 15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o pm-r8a7790.o
18obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o setup-rcar-gen2.o 16obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o pm-r8a7791.o
19obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o setup-rcar-gen2.o 17obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o
20obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o 18obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
21obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o 19obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
22 20
@@ -31,13 +29,13 @@ obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
31obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o 29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
32obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o 30obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
33obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o 31obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
34obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o
35endif 32endif
36 33
37# CPU reset vector handling objects 34# CPU reset vector handling objects
38cpu-y := platsmp.o headsmp.o 35cpu-y := platsmp.o headsmp.o
39cpu-$(CONFIG_ARCH_R8A7790) += platsmp-apmu.o 36
40cpu-$(CONFIG_ARCH_R8A7791) += platsmp-apmu.o 37# Shared SoC family objects
38obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
41 39
42# SMP objects 40# SMP objects
43smp-y := $(cpu-y) 41smp-y := $(cpu-y)
@@ -51,19 +49,14 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
51obj-$(CONFIG_SUSPEND) += suspend.o 49obj-$(CONFIG_SUSPEND) += suspend.o
52obj-$(CONFIG_CPU_IDLE) += cpuidle.o 50obj-$(CONFIG_CPU_IDLE) += cpuidle.o
53obj-$(CONFIG_CPU_FREQ) += cpufreq.o 51obj-$(CONFIG_CPU_FREQ) += cpufreq.o
54obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o pm-rmobile.o 52obj-$(CONFIG_PM_RCAR) += pm-rcar.o
55obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o 53obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
56obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o pm-rmobile.o
57obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o pm-rcar.o
58obj-$(CONFIG_ARCH_R8A7790) += pm-r8a7790.o pm-rcar.o $(cpu-y)
59obj-$(CONFIG_ARCH_R8A7791) += pm-r8a7791.o pm-rcar.o $(cpu-y)
60 54
61# IRQ objects 55# special sh7372 handling for IRQ objects and low level sleep code
62obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 56obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
63 57
64# Board objects 58# Board objects
65ifdef CONFIG_ARCH_SHMOBILE_MULTI 59ifdef CONFIG_ARCH_SHMOBILE_MULTI
66obj-$(CONFIG_MACH_GENMAI) += board-genmai-reference.o
67obj-$(CONFIG_MACH_KOELSCH) += board-koelsch-reference.o 60obj-$(CONFIG_MACH_KOELSCH) += board-koelsch-reference.o
68obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o 61obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o
69obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o 62obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
@@ -73,11 +66,9 @@ obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o
73obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 66obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
74obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 67obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
75obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o 68obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
76obj-$(CONFIG_MACH_GENMAI) += board-genmai.o
77obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 69obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
78obj-$(CONFIG_MACH_LAGER) += board-lager.o 70obj-$(CONFIG_MACH_LAGER) += board-lager.o
79obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
80obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o
81obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o 72obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o
82obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 73obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
83obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 74obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index ebf97d4bcfd8..de9a23852fc8 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -3,10 +3,8 @@ loadaddr-y :=
3loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 3loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
4loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000 4loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
6loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
7loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 6loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
9loadaddr-$(CONFIG_MACH_GENMAI) += 0x08008000
10loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 8loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
11loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 9loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
12loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 10loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
index 2f7723e5fe91..a6503d8c77de 100644
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -50,7 +50,6 @@ static void __init ape6evm_add_standard_devices(void)
50 50
51 r8a73a4_add_dt_devices(); 51 r8a73a4_add_dt_devices();
52 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 52 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
53 platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
54} 53}
55 54
56static const char *ape6evm_boards_compat_dt[] __initdata = { 55static const char *ape6evm_boards_compat_dt[] __initdata = {
@@ -59,7 +58,8 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
59}; 58};
60 59
61DT_MACHINE_START(APE6EVM_DT, "ape6evm") 60DT_MACHINE_START(APE6EVM_DT, "ape6evm")
62 .init_early = r8a73a4_init_early, 61 .init_early = shmobile_init_delay,
63 .init_machine = ape6evm_add_standard_devices, 62 .init_machine = ape6evm_add_standard_devices,
63 .init_late = shmobile_init_late,
64 .dt_compat = ape6evm_boards_compat_dt, 64 .dt_compat = ape6evm_boards_compat_dt,
65MACHINE_END 65MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 1585b8830b13..b222f68d55b7 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -283,7 +283,8 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
283}; 283};
284 284
285DT_MACHINE_START(APE6EVM_DT, "ape6evm") 285DT_MACHINE_START(APE6EVM_DT, "ape6evm")
286 .init_early = r8a73a4_init_early, 286 .init_early = shmobile_init_delay,
287 .init_machine = ape6evm_add_standard_devices, 287 .init_machine = ape6evm_add_standard_devices,
288 .init_late = shmobile_init_late,
288 .dt_compat = ape6evm_boards_compat_dt, 289 .dt_compat = ape6evm_boards_compat_dt,
289MACHINE_END 290MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
deleted file mode 100644
index 84bc6cb6d5aa..000000000000
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ /dev/null
@@ -1,198 +0,0 @@
1/*
2 * armadillo 800 eva board support
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/kernel.h>
25#include <linux/gpio.h>
26#include <linux/io.h>
27
28#include <asm/mach/arch.h>
29#include <asm/hardware/cache-l2x0.h>
30
31#include "common.h"
32#include "r8a7740.h"
33
34/*
35 * CON1 Camera Module
36 * CON2 Extension Bus
37 * CON3 HDMI Output
38 * CON4 Composite Video Output
39 * CON5 H-UDI JTAG
40 * CON6 ARM JTAG
41 * CON7 SD1
42 * CON8 SD2
43 * CON9 RTC BackUp
44 * CON10 Monaural Mic Input
45 * CON11 Stereo Headphone Output
46 * CON12 Audio Line Output(L)
47 * CON13 Audio Line Output(R)
48 * CON14 AWL13 Module
49 * CON15 Extension
50 * CON16 LCD1
51 * CON17 LCD2
52 * CON19 Power Input
53 * CON20 USB1
54 * CON21 USB2
55 * CON22 Serial
56 * CON23 LAN
57 * CON24 USB3
58 * LED1 Camera LED (Yellow)
59 * LED2 Power LED (Green)
60 * LED3-LED6 User LED (Yellow)
61 * LED7 LAN link LED (Green)
62 * LED8 LAN activity LED (Yellow)
63 */
64
65/*
66 * DipSwitch
67 *
68 * SW1
69 *
70 * -12345678-+---------------+----------------------------
71 * 1 | boot | hermit
72 * 0 | boot | OS auto boot
73 * -12345678-+---------------+----------------------------
74 * 00 | boot device | eMMC
75 * 10 | boot device | SDHI0 (CON7)
76 * 01 | boot device | -
77 * 11 | boot device | Extension Buss (CS0)
78 * -12345678-+---------------+----------------------------
79 * 0 | Extension Bus | D8-D15 disable, eMMC enable
80 * 1 | Extension Bus | D8-D15 enable, eMMC disable
81 * -12345678-+---------------+----------------------------
82 * 0 | SDHI1 | COM8 disable, COM14 enable
83 * 1 | SDHI1 | COM8 enable, COM14 disable
84 * -12345678-+---------------+----------------------------
85 * 0 | USB0 | COM20 enable, COM24 disable
86 * 1 | USB0 | COM20 disable, COM24 enable
87 * -12345678-+---------------+----------------------------
88 * 00 | JTAG | SH-X2
89 * 10 | JTAG | ARM
90 * 01 | JTAG | -
91 * 11 | JTAG | Boundary Scan
92 *-----------+---------------+----------------------------
93 */
94
95/*
96 * FSI-WM8978
97 *
98 * this command is required when playback.
99 *
100 * # amixer set "Headphone" 50
101 *
102 * this command is required when capture.
103 *
104 * # amixer set "Input PGA" 15
105 * # amixer set "Left Input Mixer MicP" on
106 * # amixer set "Left Input Mixer MicN" on
107 * # amixer set "Right Input Mixer MicN" on
108 * # amixer set "Right Input Mixer MicP" on
109 */
110
111/*
112 * USB function
113 *
114 * When you use USB Function,
115 * set SW1.6 ON, and connect cable to CN24.
116 *
117 * USBF needs workaround on R8A7740 chip.
118 * These are a little bit complex.
119 * see
120 * usbhsf_power_ctrl()
121 */
122
123static void __init eva_clock_init(void)
124{
125 struct clk *system = clk_get(NULL, "system_clk");
126 struct clk *xtal1 = clk_get(NULL, "extal1");
127 struct clk *usb24s = clk_get(NULL, "usb24s");
128 struct clk *fsibck = clk_get(NULL, "fsibck");
129
130 if (IS_ERR(system) ||
131 IS_ERR(xtal1) ||
132 IS_ERR(usb24s) ||
133 IS_ERR(fsibck)) {
134 pr_err("armadillo800eva board clock init failed\n");
135 goto clock_error;
136 }
137
138 /* armadillo 800 eva extal1 is 24MHz */
139 clk_set_rate(xtal1, 24000000);
140
141 /* usb24s use extal1 (= system) clock (= 24MHz) */
142 clk_set_parent(usb24s, system);
143
144 /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
145 clk_set_rate(fsibck, 12288000);
146
147clock_error:
148 if (!IS_ERR(system))
149 clk_put(system);
150 if (!IS_ERR(xtal1))
151 clk_put(xtal1);
152 if (!IS_ERR(usb24s))
153 clk_put(usb24s);
154 if (!IS_ERR(fsibck))
155 clk_put(fsibck);
156}
157
158/*
159 * board init
160 */
161static void __init eva_init(void)
162{
163 r8a7740_clock_init(MD_CK0 | MD_CK2);
164 eva_clock_init();
165
166 r8a7740_meram_workaround();
167
168#ifdef CONFIG_CACHE_L2X0
169 /* Shared attribute override enable, 32K*8way */
170 l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
171#endif
172
173 r8a7740_add_standard_devices_dt();
174
175 r8a7740_pm_init();
176}
177
178#define RESCNT2 IOMEM(0xe6188020)
179static void eva_restart(enum reboot_mode mode, const char *cmd)
180{
181 /* Do soft power on reset */
182 writel(1 << 31, RESCNT2);
183}
184
185static const char *eva_boards_compat_dt[] __initdata = {
186 "renesas,armadillo800eva-reference",
187 NULL,
188};
189
190DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
191 .map_io = r8a7740_map_io,
192 .init_early = shmobile_init_delay,
193 .init_irq = r8a7740_init_irq_of,
194 .init_machine = eva_init,
195 .init_late = shmobile_init_late,
196 .dt_compat = eva_boards_compat_dt,
197 .restart = eva_restart,
198MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 6dbaad611a92..e70983534403 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1231,6 +1231,10 @@ clock_error:
1231#define GPIO_PORT8CR IOMEM(0xe6050008) 1231#define GPIO_PORT8CR IOMEM(0xe6050008)
1232static void __init eva_init(void) 1232static void __init eva_init(void)
1233{ 1233{
1234 static struct pm_domain_device domain_devices[] __initdata = {
1235 { "A4LC", &lcdc0_device },
1236 { "A4LC", &hdmi_lcdc_device },
1237 };
1234 struct platform_device *usb = NULL; 1238 struct platform_device *usb = NULL;
1235 1239
1236 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 1240 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -1316,8 +1320,8 @@ static void __init eva_init(void)
1316 platform_add_devices(eva_devices, 1320 platform_add_devices(eva_devices,
1317 ARRAY_SIZE(eva_devices)); 1321 ARRAY_SIZE(eva_devices));
1318 1322
1319 rmobile_add_device_to_domain("A4LC", &lcdc0_device); 1323 rmobile_add_devices_to_domains(domain_devices,
1320 rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device); 1324 ARRAY_SIZE(domain_devices));
1321 if (usb) 1325 if (usb)
1322 rmobile_add_device_to_domain("A3SP", usb); 1326 rmobile_add_device_to_domain("A3SP", usb);
1323 1327
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index ba840cd333b9..79c47847f200 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -80,8 +80,9 @@ static const char *bockw_boards_compat_dt[] __initdata = {
80}; 80};
81 81
82DT_MACHINE_START(BOCKW_DT, "bockw") 82DT_MACHINE_START(BOCKW_DT, "bockw")
83 .init_early = r8a7778_init_delay, 83 .init_early = shmobile_init_delay,
84 .init_irq = r8a7778_init_irq_dt, 84 .init_irq = r8a7778_init_irq_dt,
85 .init_machine = bockw_init, 85 .init_machine = bockw_init,
86 .init_late = shmobile_init_late,
86 .dt_compat = bockw_boards_compat_dt, 87 .dt_compat = bockw_boards_compat_dt,
87MACHINE_END 88MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 8a83eb39d3f1..1cf2c75dacfb 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -733,7 +733,7 @@ static const char *bockw_boards_compat_dt[] __initdata = {
733}; 733};
734 734
735DT_MACHINE_START(BOCKW_DT, "bockw") 735DT_MACHINE_START(BOCKW_DT, "bockw")
736 .init_early = r8a7778_init_delay, 736 .init_early = shmobile_init_delay,
737 .init_irq = r8a7778_init_irq_dt, 737 .init_irq = r8a7778_init_irq_dt,
738 .init_machine = bockw_init, 738 .init_machine = bockw_init,
739 .dt_compat = bockw_boards_compat_dt, 739 .dt_compat = bockw_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c
deleted file mode 100644
index e5448f7b868a..000000000000
--- a/arch/arm/mach-shmobile/board-genmai-reference.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Genmai board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/of_platform.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26
27#include "clock.h"
28#include "common.h"
29#include "r7s72100.h"
30
31/*
32 * This is a really crude hack to provide clkdev support to platform
33 * devices until they get moved to DT.
34 */
35static const struct clk_name clk_names[] = {
36 { "mtu2", "fck", "sh-mtu2" },
37};
38
39static void __init genmai_add_standard_devices(void)
40{
41 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), true);
42 r7s72100_add_dt_devices();
43 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
44}
45
46static const char * const genmai_boards_compat_dt[] __initconst = {
47 "renesas,genmai",
48 NULL,
49};
50
51DT_MACHINE_START(GENMAI_DT, "genmai")
52 .init_early = shmobile_init_delay,
53 .init_machine = genmai_add_standard_devices,
54 .dt_compat = genmai_boards_compat_dt,
55MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c
deleted file mode 100644
index 7bf2d8057535..000000000000
--- a/arch/arm/mach-shmobile/board-genmai.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/*
2 * Genmai board support
3 *
4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2014 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/platform_device.h>
24#include <linux/serial_sci.h>
25#include <linux/sh_eth.h>
26#include <linux/spi/rspi.h>
27#include <linux/spi/spi.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#include "common.h"
33#include "irqs.h"
34#include "r7s72100.h"
35
36/* Ether */
37static const struct sh_eth_plat_data ether_pdata __initconst = {
38 .phy = 0x00, /* PD60610 */
39 .edmac_endian = EDMAC_LITTLE_ENDIAN,
40 .phy_interface = PHY_INTERFACE_MODE_MII,
41 .no_ether_link = 1
42};
43
44static const struct resource ether_resources[] __initconst = {
45 DEFINE_RES_MEM(0xe8203000, 0x800),
46 DEFINE_RES_MEM(0xe8204800, 0x200),
47 DEFINE_RES_IRQ(gic_iid(359)),
48};
49
50static const struct platform_device_info ether_info __initconst = {
51 .name = "r7s72100-ether",
52 .id = -1,
53 .res = ether_resources,
54 .num_res = ARRAY_SIZE(ether_resources),
55 .data = &ether_pdata,
56 .size_data = sizeof(ether_pdata),
57 .dma_mask = DMA_BIT_MASK(32),
58};
59
60/* RSPI */
61#define RSPI_RESOURCE(idx, baseaddr, irq) \
62static const struct resource rspi##idx##_resources[] __initconst = { \
63 DEFINE_RES_MEM(baseaddr, 0x24), \
64 DEFINE_RES_IRQ_NAMED(irq, "error"), \
65 DEFINE_RES_IRQ_NAMED(irq + 1, "rx"), \
66 DEFINE_RES_IRQ_NAMED(irq + 2, "tx"), \
67}
68
69RSPI_RESOURCE(0, 0xe800c800, gic_iid(270));
70RSPI_RESOURCE(1, 0xe800d000, gic_iid(273));
71RSPI_RESOURCE(2, 0xe800d800, gic_iid(276));
72RSPI_RESOURCE(3, 0xe800e000, gic_iid(279));
73RSPI_RESOURCE(4, 0xe800e800, gic_iid(282));
74
75static const struct rspi_plat_data rspi_pdata __initconst = {
76 .num_chipselect = 1,
77};
78
79#define r7s72100_register_rspi(idx) \
80 platform_device_register_resndata(NULL, "rspi-rz", idx, \
81 rspi##idx##_resources, \
82 ARRAY_SIZE(rspi##idx##_resources), \
83 &rspi_pdata, sizeof(rspi_pdata))
84
85static const struct spi_board_info spi_info[] __initconst = {
86 {
87 .modalias = "wm8978",
88 .max_speed_hz = 5000000,
89 .bus_num = 4,
90 .chip_select = 0,
91 },
92};
93
94/* SCIF */
95#define R7S72100_SCIF(index, baseaddr, irq) \
96static const struct plat_sci_port scif##index##_platform_data = { \
97 .type = PORT_SCIF, \
98 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
99 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
100 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
101 SCSCR_REIE, \
102}; \
103 \
104static struct resource scif##index##_resources[] = { \
105 DEFINE_RES_MEM(baseaddr, 0x100), \
106 DEFINE_RES_IRQ(irq + 1), \
107 DEFINE_RES_IRQ(irq + 2), \
108 DEFINE_RES_IRQ(irq + 3), \
109 DEFINE_RES_IRQ(irq), \
110} \
111
112R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
113R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
114R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
115R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
116R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
117R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
118R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
119R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
120
121#define r7s72100_register_scif(index) \
122 platform_device_register_resndata(NULL, "sh-sci", index, \
123 scif##index##_resources, \
124 ARRAY_SIZE(scif##index##_resources), \
125 &scif##index##_platform_data, \
126 sizeof(scif##index##_platform_data))
127
128static void __init genmai_add_standard_devices(void)
129{
130 r7s72100_clock_init();
131 r7s72100_add_dt_devices();
132
133 platform_device_register_full(&ether_info);
134
135 r7s72100_register_rspi(0);
136 r7s72100_register_rspi(1);
137 r7s72100_register_rspi(2);
138 r7s72100_register_rspi(3);
139 r7s72100_register_rspi(4);
140 spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
141
142 r7s72100_register_scif(0);
143 r7s72100_register_scif(1);
144 r7s72100_register_scif(2);
145 r7s72100_register_scif(3);
146 r7s72100_register_scif(4);
147 r7s72100_register_scif(5);
148 r7s72100_register_scif(6);
149 r7s72100_register_scif(7);
150}
151
152static const char * const genmai_boards_compat_dt[] __initconst = {
153 "renesas,genmai",
154 NULL,
155};
156
157DT_MACHINE_START(GENMAI_DT, "genmai")
158 .init_early = shmobile_init_delay,
159 .init_machine = genmai_add_standard_devices,
160 .dt_compat = genmai_boards_compat_dt,
161MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index 3ff88c138896..9db5e6774fb7 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -88,7 +88,6 @@ static void __init koelsch_add_du_device(void)
88 * devices until they get moved to DT. 88 * devices until they get moved to DT.
89 */ 89 */
90static const struct clk_name clk_names[] __initconst = { 90static const struct clk_name clk_names[] __initconst = {
91 { "cmt0", "fck", "sh-cmt-48-gen2.0" },
92 { "du0", "du.0", "rcar-du-r8a7791" }, 91 { "du0", "du.0", "rcar-du-r8a7791" },
93 { "du1", "du.1", "rcar-du-r8a7791" }, 92 { "du1", "du.1", "rcar-du-r8a7791" },
94 { "lvds0", "lvds.0", "rcar-du-r8a7791" }, 93 { "lvds0", "lvds.0", "rcar-du-r8a7791" },
@@ -97,7 +96,6 @@ static const struct clk_name clk_names[] __initconst = {
97static void __init koelsch_add_standard_devices(void) 96static void __init koelsch_add_standard_devices(void)
98{ 97{
99 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); 98 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
100 r8a7791_add_dt_devices();
101 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 99 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
102 100
103 koelsch_add_du_device(); 101 koelsch_add_du_device();
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index b7d5bc7659cd..126a8b4ec491 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -331,7 +331,6 @@ SDHI_REGULATOR(2, RCAR_GP_PIN(7, 19), RCAR_GP_PIN(2, 26));
331static struct sh_mobile_sdhi_info sdhi0_info __initdata = { 331static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
332 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 332 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
333 MMC_CAP_POWER_OFF_CARD, 333 MMC_CAP_POWER_OFF_CARD,
334 .tmio_caps2 = MMC_CAP2_NO_MULTI_READ,
335 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 334 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
336}; 335};
337 336
@@ -344,7 +343,6 @@ static struct resource sdhi0_resources[] __initdata = {
344static struct sh_mobile_sdhi_info sdhi1_info __initdata = { 343static struct sh_mobile_sdhi_info sdhi1_info __initdata = {
345 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 344 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
346 MMC_CAP_POWER_OFF_CARD, 345 MMC_CAP_POWER_OFF_CARD,
347 .tmio_caps2 = MMC_CAP2_NO_MULTI_READ,
348 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 346 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
349}; 347};
350 348
@@ -357,7 +355,6 @@ static struct resource sdhi1_resources[] __initdata = {
357static struct sh_mobile_sdhi_info sdhi2_info __initdata = { 355static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
358 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 356 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
359 MMC_CAP_POWER_OFF_CARD, 357 MMC_CAP_POWER_OFF_CARD,
360 .tmio_caps2 = MMC_CAP2_NO_MULTI_READ,
361 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | 358 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
362 TMIO_MMC_WRPROTECT_DISABLE, 359 TMIO_MMC_WRPROTECT_DISABLE,
363}; 360};
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 5d2621f202d1..d9cdf9a97e23 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -51,8 +51,8 @@ static const char *kzm9g_boards_compat_dt[] __initdata = {
51DT_MACHINE_START(KZM9G_DT, "kzm9g-reference") 51DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
52 .smp = smp_ops(sh73a0_smp_ops), 52 .smp = smp_ops(sh73a0_smp_ops),
53 .map_io = sh73a0_map_io, 53 .map_io = sh73a0_map_io,
54 .init_early = sh73a0_init_delay, 54 .init_early = shmobile_init_delay,
55 .nr_irqs = NR_IRQS_LEGACY,
56 .init_machine = kzm_init, 55 .init_machine = kzm_init,
56 .init_late = shmobile_init_late,
57 .dt_compat = kzm9g_boards_compat_dt, 57 .dt_compat = kzm9g_boards_compat_dt,
58MACHINE_END 58MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index f8bc7f8f86ad..77e36fa0b142 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -50,6 +50,7 @@
50#include <video/sh_mobile_lcdc.h> 50#include <video/sh_mobile_lcdc.h>
51 51
52#include "common.h" 52#include "common.h"
53#include "intc.h"
53#include "irqs.h" 54#include "irqs.h"
54#include "sh73a0.h" 55#include "sh73a0.h"
55 56
@@ -910,7 +911,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
910 .smp = smp_ops(sh73a0_smp_ops), 911 .smp = smp_ops(sh73a0_smp_ops),
911 .map_io = sh73a0_map_io, 912 .map_io = sh73a0_map_io,
912 .init_early = sh73a0_add_early_devices, 913 .init_early = sh73a0_add_early_devices,
913 .nr_irqs = NR_IRQS_LEGACY,
914 .init_irq = sh73a0_init_irq, 914 .init_irq = sh73a0_init_irq,
915 .init_machine = kzm_init, 915 .init_machine = kzm_init,
916 .init_late = shmobile_init_late, 916 .init_late = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 41c808e56005..2a05c02bec39 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -92,7 +92,6 @@ static void __init lager_add_du_device(void)
92 * devices until they get moved to DT. 92 * devices until they get moved to DT.
93 */ 93 */
94static const struct clk_name clk_names[] __initconst = { 94static const struct clk_name clk_names[] __initconst = {
95 { "cmt0", "fck", "sh-cmt-48-gen2.0" },
96 { "du0", "du.0", "rcar-du-r8a7790" }, 95 { "du0", "du.0", "rcar-du-r8a7790" },
97 { "du1", "du.1", "rcar-du-r8a7790" }, 96 { "du1", "du.1", "rcar-du-r8a7790" },
98 { "du2", "du.2", "rcar-du-r8a7790" }, 97 { "du2", "du.2", "rcar-du-r8a7790" },
@@ -103,7 +102,6 @@ static const struct clk_name clk_names[] __initconst = {
103static void __init lager_add_standard_devices(void) 102static void __init lager_add_standard_devices(void)
104{ 103{
105 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); 104 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
106 r8a7790_add_dt_devices();
107 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 105 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
108 106
109 lager_add_du_device(); 107 lager_add_du_device();
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index e1d8215da0b0..f5a98e2942b3 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -630,7 +630,6 @@ static void __init lager_add_rsnd_device(void)
630static struct sh_mobile_sdhi_info sdhi0_info __initdata = { 630static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
631 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 631 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
632 MMC_CAP_POWER_OFF_CARD, 632 MMC_CAP_POWER_OFF_CARD,
633 .tmio_caps2 = MMC_CAP2_NO_MULTI_READ,
634 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | 633 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
635 TMIO_MMC_WRPROTECT_DISABLE, 634 TMIO_MMC_WRPROTECT_DISABLE,
636}; 635};
@@ -644,7 +643,6 @@ static struct resource sdhi0_resources[] __initdata = {
644static struct sh_mobile_sdhi_info sdhi2_info __initdata = { 643static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
645 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 644 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
646 MMC_CAP_POWER_OFF_CARD, 645 MMC_CAP_POWER_OFF_CARD,
647 .tmio_caps2 = MMC_CAP2_NO_MULTI_READ,
648 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | 646 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
649 TMIO_MMC_WRPROTECT_DISABLE, 647 TMIO_MMC_WRPROTECT_DISABLE,
650}; 648};
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 79f448e93abb..ca5d34b92aa7 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -63,6 +63,7 @@
63#include <asm/mach-types.h> 63#include <asm/mach-types.h>
64 64
65#include "common.h" 65#include "common.h"
66#include "intc.h"
66#include "irqs.h" 67#include "irqs.h"
67#include "pm-rmobile.h" 68#include "pm-rmobile.h"
68#include "sh-gpio.h" 69#include "sh-gpio.h"
@@ -1420,7 +1421,7 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
1420#define USCCR1 IOMEM(0xE6058144) 1421#define USCCR1 IOMEM(0xE6058144)
1421static void __init mackerel_init(void) 1422static void __init mackerel_init(void)
1422{ 1423{
1423 struct pm_domain_device domain_devices[] = { 1424 static struct pm_domain_device domain_devices[] __initdata = {
1424 { "A4LC", &lcdc_device, }, 1425 { "A4LC", &lcdc_device, },
1425 { "A4LC", &hdmi_lcdc_device, }, 1426 { "A4LC", &hdmi_lcdc_device, },
1426 { "A4LC", &meram_device, }, 1427 { "A4LC", &meram_device, },
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 21b3e1ca2261..38d9cdd26587 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -37,18 +37,8 @@ static void __init marzen_init_timer(void)
37 clocksource_of_init(); 37 clocksource_of_init();
38} 38}
39 39
40/*
41 * This is a really crude hack to provide clkdev support to platform
42 * devices until they get moved to DT.
43 */
44static const struct clk_name clk_names[] __initconst = {
45 { "tmu0", "fck", "sh-tmu.0" },
46};
47
48static void __init marzen_init(void) 40static void __init marzen_init(void)
49{ 41{
50 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
51 r8a7779_add_standard_devices_dt();
52 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 42 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
53 r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */ 43 r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
54} 44}
@@ -64,8 +54,8 @@ DT_MACHINE_START(MARZEN, "marzen")
64 .map_io = r8a7779_map_io, 54 .map_io = r8a7779_map_io,
65 .init_early = shmobile_init_delay, 55 .init_early = shmobile_init_delay,
66 .init_time = marzen_init_timer, 56 .init_time = marzen_init_timer,
67 .nr_irqs = NR_IRQS_LEGACY,
68 .init_irq = r8a7779_init_irq_dt, 57 .init_irq = r8a7779_init_irq_dt,
69 .init_machine = marzen_init, 58 .init_machine = marzen_init,
59 .init_late = shmobile_init_late,
70 .dt_compat = marzen_boards_compat_dt, 60 .dt_compat = marzen_boards_compat_dt,
71MACHINE_END 61MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
deleted file mode 100644
index 3eb2ec401e0c..000000000000
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * r7a72100 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2012 Phil Edworthy
6 * Copyright (C) 2011 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/io.h>
20#include <linux/sh_clk.h>
21#include <linux/clkdev.h>
22
23#include "common.h"
24#include "r7s72100.h"
25
26/* Frequency Control Registers */
27#define FRQCR 0xfcfe0010
28#define FRQCR2 0xfcfe0014
29/* Standby Control Registers */
30#define STBCR3 0xfcfe0420
31#define STBCR4 0xfcfe0424
32#define STBCR7 0xfcfe0430
33#define STBCR9 0xfcfe0438
34#define STBCR10 0xfcfe043c
35
36#define PLL_RATE 30
37
38static struct clk_mapping cpg_mapping = {
39 .phys = 0xfcfe0000,
40 .len = 0x1000,
41};
42
43/* Fixed 32 KHz root clock for RTC */
44static struct clk r_clk = {
45 .rate = 32768,
46};
47
48/*
49 * Default rate for the root input clock, reset this with clk_set_rate()
50 * from the platform code.
51 */
52static struct clk extal_clk = {
53 .rate = 13330000,
54 .mapping = &cpg_mapping,
55};
56
57static unsigned long pll_recalc(struct clk *clk)
58{
59 return clk->parent->rate * PLL_RATE;
60}
61
62static struct sh_clk_ops pll_clk_ops = {
63 .recalc = pll_recalc,
64};
65
66static struct clk pll_clk = {
67 .ops = &pll_clk_ops,
68 .parent = &extal_clk,
69 .flags = CLK_ENABLE_ON_INIT,
70};
71
72static unsigned long bus_recalc(struct clk *clk)
73{
74 return clk->parent->rate / 3;
75}
76
77static struct sh_clk_ops bus_clk_ops = {
78 .recalc = bus_recalc,
79};
80
81static struct clk bus_clk = {
82 .ops = &bus_clk_ops,
83 .parent = &pll_clk,
84 .flags = CLK_ENABLE_ON_INIT,
85};
86
87static unsigned long peripheral0_recalc(struct clk *clk)
88{
89 return clk->parent->rate / 12;
90}
91
92static struct sh_clk_ops peripheral0_clk_ops = {
93 .recalc = peripheral0_recalc,
94};
95
96static struct clk peripheral0_clk = {
97 .ops = &peripheral0_clk_ops,
98 .parent = &pll_clk,
99 .flags = CLK_ENABLE_ON_INIT,
100};
101
102static unsigned long peripheral1_recalc(struct clk *clk)
103{
104 return clk->parent->rate / 6;
105}
106
107static struct sh_clk_ops peripheral1_clk_ops = {
108 .recalc = peripheral1_recalc,
109};
110
111static struct clk peripheral1_clk = {
112 .ops = &peripheral1_clk_ops,
113 .parent = &pll_clk,
114 .flags = CLK_ENABLE_ON_INIT,
115};
116
117struct clk *main_clks[] = {
118 &r_clk,
119 &extal_clk,
120 &pll_clk,
121 &bus_clk,
122 &peripheral0_clk,
123 &peripheral1_clk,
124};
125
126static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
127static int multipliers[] = { 1, 2, 1, 1 };
128
129static struct clk_div_mult_table div4_div_mult_table = {
130 .divisors = div2,
131 .nr_divisors = ARRAY_SIZE(div2),
132 .multipliers = multipliers,
133 .nr_multipliers = ARRAY_SIZE(multipliers),
134};
135
136static struct clk_div4_table div4_table = {
137 .div_mult_table = &div4_div_mult_table,
138};
139
140enum { DIV4_I,
141 DIV4_NR };
142
143#define DIV4(_reg, _bit, _mask, _flags) \
144 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
145
146/* The mask field specifies the div2 entries that are valid */
147struct clk div4_clks[DIV4_NR] = {
148 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
149 | CLK_ENABLE_ON_INIT),
150};
151
152enum {
153 MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
154 MSTP97, MSTP96, MSTP95, MSTP94,
155 MSTP74,
156 MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
157 MSTP33, MSTP_NR
158};
159
160static struct clk mstp_clks[MSTP_NR] = {
161 [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
162 [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
163 [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
164 [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
165 [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
166 [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
167 [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
168 [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
169 [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
170 [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
171 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
172 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
173 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
174 [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
175 [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
176 [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
177 [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
178 [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
179 [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
180};
181
182static struct clk_lookup lookups[] = {
183 /* main clocks */
184 CLKDEV_CON_ID("rclk", &r_clk),
185 CLKDEV_CON_ID("extal", &extal_clk),
186 CLKDEV_CON_ID("pll_clk", &pll_clk),
187 CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
188
189 /* DIV4 clocks */
190 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
191
192 /* MSTP clocks */
193 CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
194 CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
195 CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
196 CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
197 CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
198 CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
199
200 /* ICK */
201 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
202 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
203 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
204 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
205 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
206 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
207 CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
208 CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
209 CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
210};
211
212void __init r7s72100_clock_init(void)
213{
214 int k, ret = 0;
215
216 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
217 ret = clk_register(main_clks[k]);
218
219 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
220
221 if (!ret)
222 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
223
224 if (!ret)
225 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
226
227 if (!ret)
228 shmobile_clk_init();
229 else
230 panic("failed to setup rza1 clocks\n");
231}
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 98056081f0da..72087c79ad7b 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,8 +2,6 @@
2#define __ARCH_MACH_COMMON_H 2#define __ARCH_MACH_COMMON_H
3 3
4extern void shmobile_earlytimer_init(void); 4extern void shmobile_earlytimer_init(void);
5extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
6 unsigned int mult, unsigned int div);
7extern void shmobile_init_delay(void); 5extern void shmobile_init_delay(void);
8struct twd_local_timer; 6struct twd_local_timer;
9extern void shmobile_setup_console(void); 7extern void shmobile_setup_console(void);
diff --git a/arch/arm/mach-shmobile/cpufreq.c b/arch/arm/mach-shmobile/cpufreq.c
index 8a24b2be46ae..57fbff024dcd 100644
--- a/arch/arm/mach-shmobile/cpufreq.c
+++ b/arch/arm/mach-shmobile/cpufreq.c
@@ -12,6 +12,6 @@
12 12
13int __init shmobile_cpufreq_init(void) 13int __init shmobile_cpufreq_init(void)
14{ 14{
15 platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0); 15 platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
16 return 0; 16 return 0;
17} 17}
diff --git a/arch/arm/mach-shmobile/dma-register.h b/arch/arm/mach-shmobile/dma-register.h
index 97c40bd9b94f..52a2f66e600f 100644
--- a/arch/arm/mach-shmobile/dma-register.h
+++ b/arch/arm/mach-shmobile/dma-register.h
@@ -52,8 +52,8 @@ static const unsigned int dma_ts_shift[] = {
52 ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\ 52 ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
53 (((i) & TS_HI_BIT) << TS_HI_SHIFT)) 53 (((i) & TS_HI_BIT) << TS_HI_SHIFT))
54 54
55#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz))) 55#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
56#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz))) 56#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
57 57
58 58
59/* 59/*
diff --git a/arch/arm/mach-shmobile/intc.h b/arch/arm/mach-shmobile/intc.h
index a5603c76cfe0..40b2ad4ca5b4 100644
--- a/arch/arm/mach-shmobile/intc.h
+++ b/arch/arm/mach-shmobile/intc.h
@@ -287,4 +287,9 @@ static struct intc_desc p ## _desc __initdata = { \
287 p ## _sense_registers, NULL), \ 287 p ## _sense_registers, NULL), \
288} 288}
289 289
290/* INTCS */
291#define INTCS_VECT_BASE 0x3400
292#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
293#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
294
290#endif /* __ASM_MACH_INTC_H */ 295#endif /* __ASM_MACH_INTC_H */
diff --git a/arch/arm/mach-shmobile/irqs.h b/arch/arm/mach-shmobile/irqs.h
index 4ff2d2aa94f0..3070f6d887eb 100644
--- a/arch/arm/mach-shmobile/irqs.h
+++ b/arch/arm/mach-shmobile/irqs.h
@@ -1,18 +1,12 @@
1#ifndef __SHMOBILE_IRQS_H 1#ifndef __SHMOBILE_IRQS_H
2#define __SHMOBILE_IRQS_H 2#define __SHMOBILE_IRQS_H
3 3
4#include <linux/sh_intc.h> 4#include "include/mach/irqs.h"
5#include <mach/irqs.h>
6 5
7/* GIC */ 6/* GIC */
8#define gic_spi(nr) ((nr) + 32) 7#define gic_spi(nr) ((nr) + 32)
9#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ 8#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */
10 9
11/* INTCS */
12#define INTCS_VECT_BASE 0x3400
13#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
14#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
15
16/* GPIO IRQ */ 10/* GPIO IRQ */
17#define _GPIO_IRQ_BASE 2500 11#define _GPIO_IRQ_BASE 2500
18#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x)) 12#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x))
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index a0d44d537fa0..e3f146448237 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -13,12 +13,12 @@
13#include "common.h" 13#include "common.h"
14#include "pm-rmobile.h" 14#include "pm-rmobile.h"
15 15
16#ifdef CONFIG_PM 16#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
17static int r8a7740_pd_a4s_suspend(void) 17static int r8a7740_pd_a4s_suspend(void)
18{ 18{
19 /* 19 /*
20 * The A4S domain contains the CPU core and therefore it should 20 * The A4S domain contains the CPU core and therefore it should
21 * only be turned off if the CPU is in use. 21 * only be turned off if the CPU is not in use.
22 */ 22 */
23 return -EBUSY; 23 return -EBUSY;
24} 24}
@@ -34,23 +34,21 @@ static int r8a7740_pd_a3sp_suspend(void)
34 34
35static struct rmobile_pm_domain r8a7740_pm_domains[] = { 35static struct rmobile_pm_domain r8a7740_pm_domains[] = {
36 { 36 {
37 .genpd.name = "A4LC",
38 .bit_shift = 1,
39 }, {
37 .genpd.name = "A4S", 40 .genpd.name = "A4S",
38 .bit_shift = 10, 41 .bit_shift = 10,
39 .gov = &pm_domain_always_on_gov, 42 .gov = &pm_domain_always_on_gov,
40 .no_debug = true, 43 .no_debug = true,
41 .suspend = r8a7740_pd_a4s_suspend, 44 .suspend = r8a7740_pd_a4s_suspend,
42 }, 45 }, {
43 {
44 .genpd.name = "A3SP", 46 .genpd.name = "A3SP",
45 .bit_shift = 11, 47 .bit_shift = 11,
46 .gov = &pm_domain_always_on_gov, 48 .gov = &pm_domain_always_on_gov,
47 .no_debug = true, 49 .no_debug = true,
48 .suspend = r8a7740_pd_a3sp_suspend, 50 .suspend = r8a7740_pd_a3sp_suspend,
49 }, 51 },
50 {
51 .genpd.name = "A4LC",
52 .bit_shift = 1,
53 },
54}; 52};
55 53
56void __init r8a7740_init_pm_domains(void) 54void __init r8a7740_init_pm_domains(void)
@@ -58,8 +56,7 @@ void __init r8a7740_init_pm_domains(void)
58 rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains)); 56 rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
59 pm_genpd_add_subdomain_names("A4S", "A3SP"); 57 pm_genpd_add_subdomain_names("A4S", "A3SP");
60} 58}
61 59#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
62#endif /* CONFIG_PM */
63 60
64#ifdef CONFIG_SUSPEND 61#ifdef CONFIG_SUSPEND
65static int r8a7740_enter_suspend(suspend_state_t suspend_state) 62static int r8a7740_enter_suspend(suspend_state_t suspend_state)
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index 69f70b7f7fb2..82fe3d7f9662 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -87,7 +87,6 @@ static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
87 genpd->dev_ops.stop = pm_clk_suspend; 87 genpd->dev_ops.stop = pm_clk_suspend;
88 genpd->dev_ops.start = pm_clk_resume; 88 genpd->dev_ops.start = pm_clk_resume;
89 genpd->dev_ops.active_wakeup = pd_active_wakeup; 89 genpd->dev_ops.active_wakeup = pd_active_wakeup;
90 genpd->dev_irq_safe = true;
91 genpd->power_off = pd_power_down; 90 genpd->power_off = pd_power_down;
92 genpd->power_on = pd_power_up; 91 genpd->power_on = pd_power_up;
93 92
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c
index 34b8a5674f85..00022ee56f80 100644
--- a/arch/arm/mach-shmobile/pm-rcar.c
+++ b/arch/arm/mach-shmobile/pm-rcar.c
@@ -31,8 +31,6 @@
31#define SYSCISR_RETRIES 1000 31#define SYSCISR_RETRIES 1000
32#define SYSCISR_DELAY_US 1 32#define SYSCISR_DELAY_US 1
33 33
34#if defined(CONFIG_PM) || defined(CONFIG_SMP)
35
36static void __iomem *rcar_sysc_base; 34static void __iomem *rcar_sysc_base;
37static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ 35static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
38 36
@@ -137,5 +135,3 @@ void __iomem *rcar_sysc_init(phys_addr_t base)
137 135
138 return rcar_sysc_base; 136 return rcar_sysc_base;
139} 137}
140
141#endif /* CONFIG_PM || CONFIG_SMP */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index ebdd16e94a84..717e6413d29c 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -27,7 +27,6 @@
27#define PSTR_RETRIES 100 27#define PSTR_RETRIES 100
28#define PSTR_DELAY_US 10 28#define PSTR_DELAY_US 10
29 29
30#ifdef CONFIG_PM
31static int rmobile_pd_power_down(struct generic_pm_domain *genpd) 30static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
32{ 31{
33 struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd); 32 struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);
@@ -111,7 +110,6 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
111 genpd->dev_ops.stop = pm_clk_suspend; 110 genpd->dev_ops.stop = pm_clk_suspend;
112 genpd->dev_ops.start = pm_clk_resume; 111 genpd->dev_ops.start = pm_clk_resume;
113 genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup; 112 genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup;
114 genpd->dev_irq_safe = true;
115 genpd->power_off = rmobile_pd_power_down; 113 genpd->power_off = rmobile_pd_power_down;
116 genpd->power_on = rmobile_pd_power_up; 114 genpd->power_on = rmobile_pd_power_up;
117 __rmobile_pd_power_up(rmobile_pd, false); 115 __rmobile_pd_power_up(rmobile_pd, false);
@@ -151,4 +149,3 @@ void rmobile_add_devices_to_domains(struct pm_domain_device data[],
151 rmobile_add_device_to_domain_td(data[j].domain_name, 149 rmobile_add_device_to_domain_td(data[j].domain_name,
152 data[j].pdev, &latencies); 150 data[j].pdev, &latencies);
153} 151}
154#endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h
index 690553a06887..8f66b343162b 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.h
+++ b/arch/arm/mach-shmobile/pm-rmobile.h
@@ -36,7 +36,7 @@ struct pm_domain_device {
36 struct platform_device *pdev; 36 struct platform_device *pdev;
37}; 37};
38 38
39#ifdef CONFIG_PM 39#ifdef CONFIG_PM_RMOBILE
40extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num); 40extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num);
41extern void rmobile_add_device_to_domain_td(const char *domain_name, 41extern void rmobile_add_device_to_domain_td(const char *domain_name,
42 struct platform_device *pdev, 42 struct platform_device *pdev,
@@ -58,6 +58,6 @@ extern void rmobile_add_devices_to_domains(struct pm_domain_device data[],
58 58
59static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[], 59static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[],
60 int size) {} 60 int size) {}
61#endif /* CONFIG_PM */ 61#endif /* CONFIG_PM_RMOBILE */
62 62
63#endif /* PM_RMOBILE_H */ 63#endif /* PM_RMOBILE_H */
diff --git a/arch/arm/mach-shmobile/r7s72100.h b/arch/arm/mach-shmobile/r7s72100.h
deleted file mode 100644
index efb723c88dd0..000000000000
--- a/arch/arm/mach-shmobile/r7s72100.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_R7S72100_H__
2#define __ASM_R7S72100_H__
3
4void r7s72100_add_dt_devices(void);
5void r7s72100_clock_init(void);
6
7#endif /* __ASM_R7S72100_H__ */
diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
index ce8bdd1d8a8a..5fafd6fcedf7 100644
--- a/arch/arm/mach-shmobile/r8a73a4.h
+++ b/arch/arm/mach-shmobile/r8a73a4.h
@@ -14,6 +14,5 @@ void r8a73a4_add_standard_devices(void);
14void r8a73a4_add_dt_devices(void); 14void r8a73a4_add_dt_devices(void);
15void r8a73a4_clock_init(void); 15void r8a73a4_clock_init(void);
16void r8a73a4_pinmux_init(void); 16void r8a73a4_pinmux_init(void);
17void r8a73a4_init_early(void);
18 17
19#endif /* __ASM_R8A73A4_H__ */ 18#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h
index 1d1a5fd78b6b..f369b4b0863d 100644
--- a/arch/arm/mach-shmobile/r8a7740.h
+++ b/arch/arm/mach-shmobile/r8a7740.h
@@ -49,15 +49,14 @@ extern void r8a7740_init_irq_of(void);
49extern void r8a7740_map_io(void); 49extern void r8a7740_map_io(void);
50extern void r8a7740_add_early_devices(void); 50extern void r8a7740_add_early_devices(void);
51extern void r8a7740_add_standard_devices(void); 51extern void r8a7740_add_standard_devices(void);
52extern void r8a7740_add_standard_devices_dt(void);
53extern void r8a7740_clock_init(u8 md_ck); 52extern void r8a7740_clock_init(u8 md_ck);
54extern void r8a7740_pinmux_init(void); 53extern void r8a7740_pinmux_init(void);
55extern void r8a7740_pm_init(void); 54extern void r8a7740_pm_init(void);
56 55
57#ifdef CONFIG_PM 56#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
58extern void __init r8a7740_init_pm_domains(void); 57extern void __init r8a7740_init_pm_domains(void);
59#else 58#else
60static inline void r8a7740_init_pm_domains(void) {} 59static inline void r8a7740_init_pm_domains(void) {}
61#endif /* CONFIG_PM */ 60#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
62 61
63#endif /* __ASM_R8A7740_H__ */ 62#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h
index 5415c719dc19..19f97046dd70 100644
--- a/arch/arm/mach-shmobile/r8a7779.h
+++ b/arch/arm/mach-shmobile/r8a7779.h
@@ -17,7 +17,6 @@ extern void r8a7779_map_io(void);
17extern void r8a7779_earlytimer_init(void); 17extern void r8a7779_earlytimer_init(void);
18extern void r8a7779_add_early_devices(void); 18extern void r8a7779_add_early_devices(void);
19extern void r8a7779_add_standard_devices(void); 19extern void r8a7779_add_standard_devices(void);
20extern void r8a7779_add_standard_devices_dt(void);
21extern void r8a7779_init_late(void); 20extern void r8a7779_init_late(void);
22extern u32 r8a7779_read_mode_pins(void); 21extern u32 r8a7779_read_mode_pins(void);
23extern void r8a7779_clock_init(void); 22extern void r8a7779_clock_init(void);
diff --git a/arch/arm/mach-shmobile/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index 459827f1369b..388f0514d931 100644
--- a/arch/arm/mach-shmobile/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -27,7 +27,6 @@ enum {
27}; 27};
28 28
29void r8a7790_add_standard_devices(void); 29void r8a7790_add_standard_devices(void);
30void r8a7790_add_dt_devices(void);
31void r8a7790_clock_init(void); 30void r8a7790_clock_init(void);
32void r8a7790_pinmux_init(void); 31void r8a7790_pinmux_init(void);
33void r8a7790_pm_init(void); 32void r8a7790_pm_init(void);
diff --git a/arch/arm/mach-shmobile/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h
index 86eae7bceb6f..c1bf7abefa5a 100644
--- a/arch/arm/mach-shmobile/r8a7791.h
+++ b/arch/arm/mach-shmobile/r8a7791.h
@@ -2,7 +2,6 @@
2#define __ASM_R8A7791_H__ 2#define __ASM_R8A7791_H__
3 3
4void r8a7791_add_standard_devices(void); 4void r8a7791_add_standard_devices(void);
5void r8a7791_add_dt_devices(void);
6void r8a7791_clock_init(void); 5void r8a7791_clock_init(void);
7void r8a7791_pinmux_init(void); 6void r8a7791_pinmux_init(void);
8void r8a7791_pm_init(void); 7void r8a7791_pm_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index f3b3b14ba972..4122104359f9 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -18,34 +18,12 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/irq.h>
22#include <linux/kernel.h> 21#include <linux/kernel.h>
23#include <linux/of_platform.h>
24#include <linux/sh_timer.h>
25 22
26#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
27 24
28#include "common.h" 25#include "common.h"
29#include "irqs.h"
30#include "r7s72100.h"
31 26
32static struct resource mtu2_resources[] __initdata = {
33 DEFINE_RES_MEM(0xfcff0000, 0x400),
34 DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"),
35};
36
37#define r7s72100_register_mtu2() \
38 platform_device_register_resndata(NULL, "sh-mtu2", \
39 -1, mtu2_resources, \
40 ARRAY_SIZE(mtu2_resources), \
41 NULL, 0)
42
43void __init r7s72100_add_dt_devices(void)
44{
45 r7s72100_register_mtu2();
46}
47
48#ifdef CONFIG_USE_OF
49static const char *r7s72100_boards_compat_dt[] __initdata = { 27static const char *r7s72100_boards_compat_dt[] __initdata = {
50 "renesas,r7s72100", 28 "renesas,r7s72100",
51 NULL, 29 NULL,
@@ -53,6 +31,6 @@ static const char *r7s72100_boards_compat_dt[] __initdata = {
53 31
54DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") 32DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
55 .init_early = shmobile_init_delay, 33 .init_early = shmobile_init_delay,
34 .init_late = shmobile_init_late,
56 .dt_compat = r7s72100_boards_compat_dt, 35 .dt_compat = r7s72100_boards_compat_dt,
57MACHINE_END 36MACHINE_END
58#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 6683072a9d98..53f40b70680d 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -295,13 +295,6 @@ void __init r8a73a4_add_standard_devices(void)
295 r8a73a4_register_dmac(); 295 r8a73a4_register_dmac();
296} 296}
297 297
298void __init r8a73a4_init_early(void)
299{
300#ifndef CONFIG_ARM_ARCH_TIMER
301 shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
302#endif
303}
304
305#ifdef CONFIG_USE_OF 298#ifdef CONFIG_USE_OF
306 299
307static const char *r8a73a4_boards_compat_dt[] __initdata = { 300static const char *r8a73a4_boards_compat_dt[] __initdata = {
@@ -310,7 +303,8 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
310}; 303};
311 304
312DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") 305DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
313 .init_early = r8a73a4_init_early, 306 .init_early = shmobile_init_delay,
307 .init_late = shmobile_init_late,
314 .dt_compat = r8a73a4_boards_compat_dt, 308 .dt_compat = r8a73a4_boards_compat_dt,
315MACHINE_END 309MACHINE_END
316#endif /* CONFIG_USE_OF */ 310#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 3d5eacaba3e6..8894e1b7ab0e 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -36,6 +36,7 @@
36#include <asm/mach/map.h> 36#include <asm/mach/map.h>
37#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
38#include <asm/mach/time.h> 38#include <asm/mach/time.h>
39#include <asm/hardware/cache-l2x0.h>
39 40
40#include "common.h" 41#include "common.h"
41#include "dma-register.h" 42#include "dma-register.h"
@@ -311,10 +312,6 @@ static struct platform_device ipmmu_device = {
311 .num_resources = ARRAY_SIZE(ipmmu_resources), 312 .num_resources = ARRAY_SIZE(ipmmu_resources),
312}; 313};
313 314
314static struct platform_device *r8a7740_devices_dt[] __initdata = {
315 &cmt1_device,
316};
317
318static struct platform_device *r8a7740_early_devices[] __initdata = { 315static struct platform_device *r8a7740_early_devices[] __initdata = {
319 &scif0_device, 316 &scif0_device,
320 &scif1_device, 317 &scif1_device,
@@ -331,6 +328,7 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
331 &irqpin3_device, 328 &irqpin3_device,
332 &tmu0_device, 329 &tmu0_device,
333 &ipmmu_device, 330 &ipmmu_device,
331 &cmt1_device,
334}; 332};
335 333
336/* DMA */ 334/* DMA */
@@ -747,6 +745,19 @@ static void r8a7740_i2c_workaround(struct platform_device *pdev)
747 745
748void __init r8a7740_add_standard_devices(void) 746void __init r8a7740_add_standard_devices(void)
749{ 747{
748 static struct pm_domain_device domain_devices[] __initdata = {
749 { "A3SP", &scif0_device },
750 { "A3SP", &scif1_device },
751 { "A3SP", &scif2_device },
752 { "A3SP", &scif3_device },
753 { "A3SP", &scif4_device },
754 { "A3SP", &scif5_device },
755 { "A3SP", &scif6_device },
756 { "A3SP", &scif7_device },
757 { "A3SP", &scif8_device },
758 { "A3SP", &i2c1_device },
759 };
760
750 /* I2C work-around */ 761 /* I2C work-around */
751 r8a7740_i2c_workaround(&i2c0_device); 762 r8a7740_i2c_workaround(&i2c0_device);
752 r8a7740_i2c_workaround(&i2c1_device); 763 r8a7740_i2c_workaround(&i2c1_device);
@@ -756,31 +767,18 @@ void __init r8a7740_add_standard_devices(void)
756 /* add devices */ 767 /* add devices */
757 platform_add_devices(r8a7740_early_devices, 768 platform_add_devices(r8a7740_early_devices,
758 ARRAY_SIZE(r8a7740_early_devices)); 769 ARRAY_SIZE(r8a7740_early_devices));
759 platform_add_devices(r8a7740_devices_dt,
760 ARRAY_SIZE(r8a7740_devices_dt));
761 platform_add_devices(r8a7740_late_devices, 770 platform_add_devices(r8a7740_late_devices,
762 ARRAY_SIZE(r8a7740_late_devices)); 771 ARRAY_SIZE(r8a7740_late_devices));
763 772
764 /* add devices to PM domain */ 773 /* add devices to PM domain */
765 774 rmobile_add_devices_to_domains(domain_devices,
766 rmobile_add_device_to_domain("A3SP", &scif0_device); 775 ARRAY_SIZE(domain_devices));
767 rmobile_add_device_to_domain("A3SP", &scif1_device);
768 rmobile_add_device_to_domain("A3SP", &scif2_device);
769 rmobile_add_device_to_domain("A3SP", &scif3_device);
770 rmobile_add_device_to_domain("A3SP", &scif4_device);
771 rmobile_add_device_to_domain("A3SP", &scif5_device);
772 rmobile_add_device_to_domain("A3SP", &scif6_device);
773 rmobile_add_device_to_domain("A3SP", &scif7_device);
774 rmobile_add_device_to_domain("A3SP", &scif8_device);
775 rmobile_add_device_to_domain("A3SP", &i2c1_device);
776} 776}
777 777
778void __init r8a7740_add_early_devices(void) 778void __init r8a7740_add_early_devices(void)
779{ 779{
780 early_platform_add_devices(r8a7740_early_devices, 780 early_platform_add_devices(r8a7740_early_devices,
781 ARRAY_SIZE(r8a7740_early_devices)); 781 ARRAY_SIZE(r8a7740_early_devices));
782 early_platform_add_devices(r8a7740_devices_dt,
783 ARRAY_SIZE(r8a7740_devices_dt));
784 782
785 /* setup early console here as well */ 783 /* setup early console here as well */
786 shmobile_setup_console(); 784 shmobile_setup_console();
@@ -788,13 +786,6 @@ void __init r8a7740_add_early_devices(void)
788 786
789#ifdef CONFIG_USE_OF 787#ifdef CONFIG_USE_OF
790 788
791void __init r8a7740_add_standard_devices_dt(void)
792{
793 platform_add_devices(r8a7740_devices_dt,
794 ARRAY_SIZE(r8a7740_devices_dt));
795 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
796}
797
798void __init r8a7740_init_irq_of(void) 789void __init r8a7740_init_irq_of(void)
799{ 790{
800 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); 791 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
@@ -827,8 +818,20 @@ void __init r8a7740_init_irq_of(void)
827 818
828static void __init r8a7740_generic_init(void) 819static void __init r8a7740_generic_init(void)
829{ 820{
830 r8a7740_clock_init(0); 821 r8a7740_meram_workaround();
831 r8a7740_add_standard_devices_dt(); 822
823#ifdef CONFIG_CACHE_L2X0
824 /* Shared attribute override enable, 32K*8way */
825 l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
826#endif
827 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
828}
829
830#define RESCNT2 IOMEM(0xe6188020)
831static void r8a7740_restart(enum reboot_mode mode, const char *cmd)
832{
833 /* Do soft power on reset */
834 writel(1 << 31, RESCNT2);
832} 835}
833 836
834static const char *r8a7740_boards_compat_dt[] __initdata = { 837static const char *r8a7740_boards_compat_dt[] __initdata = {
@@ -843,6 +846,7 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
843 .init_machine = r8a7740_generic_init, 846 .init_machine = r8a7740_generic_init,
844 .init_late = shmobile_init_late, 847 .init_late = shmobile_init_late,
845 .dt_compat = r8a7740_boards_compat_dt, 848 .dt_compat = r8a7740_boards_compat_dt,
849 .restart = r8a7740_restart,
846MACHINE_END 850MACHINE_END
847 851
848#endif /* CONFIG_USE_OF */ 852#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index f00a488dcf43..85fe016d6a87 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -520,6 +520,7 @@ void __init r8a7778_add_standard_devices(void)
520 520
521void __init r8a7778_init_late(void) 521void __init r8a7778_init_late(void)
522{ 522{
523 shmobile_init_late();
523 platform_device_register_full(&ehci_info); 524 platform_device_register_full(&ehci_info);
524 platform_device_register_full(&ohci_info); 525 platform_device_register_full(&ohci_info);
525} 526}
@@ -573,7 +574,7 @@ void __init r8a7778_init_irq_extpin(int irlm)
573 574
574void __init r8a7778_init_delay(void) 575void __init r8a7778_init_delay(void)
575{ 576{
576 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 577 shmobile_init_delay();
577} 578}
578 579
579#ifdef CONFIG_USE_OF 580#ifdef CONFIG_USE_OF
@@ -609,8 +610,8 @@ static const char *r8a7778_compat_dt[] __initdata = {
609DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 610DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
610 .init_early = r8a7778_init_delay, 611 .init_early = r8a7778_init_delay,
611 .init_irq = r8a7778_init_irq_dt, 612 .init_irq = r8a7778_init_irq_dt,
613 .init_late = shmobile_init_late,
612 .dt_compat = r8a7778_compat_dt, 614 .dt_compat = r8a7778_compat_dt,
613 .init_late = r8a7778_init_late,
614MACHINE_END 615MACHINE_END
615 616
616#endif /* CONFIG_USE_OF */ 617#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 236c1befb9e3..136078ab9407 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -641,7 +641,7 @@ static void __init r8a7779_register_hpb_dmae(void)
641 sizeof(dma_platform_data)); 641 sizeof(dma_platform_data));
642} 642}
643 643
644static struct platform_device *r8a7779_devices_dt[] __initdata = { 644static struct platform_device *r8a7779_early_devices[] __initdata = {
645 &tmu0_device, 645 &tmu0_device,
646}; 646};
647 647
@@ -669,8 +669,8 @@ void __init r8a7779_add_standard_devices(void)
669 669
670 r8a7779_init_pm_domains(); 670 r8a7779_init_pm_domains();
671 671
672 platform_add_devices(r8a7779_devices_dt, 672 platform_add_devices(r8a7779_early_devices,
673 ARRAY_SIZE(r8a7779_devices_dt)); 673 ARRAY_SIZE(r8a7779_early_devices));
674 platform_add_devices(r8a7779_standard_devices, 674 platform_add_devices(r8a7779_standard_devices,
675 ARRAY_SIZE(r8a7779_standard_devices)); 675 ARRAY_SIZE(r8a7779_standard_devices));
676 r8a7779_register_hpb_dmae(); 676 r8a7779_register_hpb_dmae();
@@ -678,8 +678,8 @@ void __init r8a7779_add_standard_devices(void)
678 678
679void __init r8a7779_add_early_devices(void) 679void __init r8a7779_add_early_devices(void)
680{ 680{
681 early_platform_add_devices(r8a7779_devices_dt, 681 early_platform_add_devices(r8a7779_early_devices,
682 ARRAY_SIZE(r8a7779_devices_dt)); 682 ARRAY_SIZE(r8a7779_early_devices));
683 683
684 /* Early serial console setup is not included here due to 684 /* Early serial console setup is not included here due to
685 * memory map collisions. The SCIF serial ports in r8a7779 685 * memory map collisions. The SCIF serial ports in r8a7779
@@ -739,12 +739,6 @@ void __init r8a7779_init_irq_dt(void)
739 __raw_writel(0x003fee3f, INT2SMSKCR4); 739 __raw_writel(0x003fee3f, INT2SMSKCR4);
740} 740}
741 741
742void __init r8a7779_add_standard_devices_dt(void)
743{
744 platform_add_devices(r8a7779_devices_dt,
745 ARRAY_SIZE(r8a7779_devices_dt));
746}
747
748#define MODEMR 0xffcc0020 742#define MODEMR 0xffcc0020
749 743
750u32 __init r8a7779_read_mode_pins(void) 744u32 __init r8a7779_read_mode_pins(void)
@@ -771,10 +765,8 @@ static const char *r8a7779_compat_dt[] __initdata = {
771DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") 765DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
772 .map_io = r8a7779_map_io, 766 .map_io = r8a7779_map_io,
773 .init_early = shmobile_init_delay, 767 .init_early = shmobile_init_delay,
774 .nr_irqs = NR_IRQS_LEGACY,
775 .init_irq = r8a7779_init_irq_dt, 768 .init_irq = r8a7779_init_irq_dt,
776 .init_machine = r8a7779_add_standard_devices_dt, 769 .init_late = shmobile_init_late,
777 .init_late = r8a7779_init_late,
778 .dt_compat = r8a7779_compat_dt, 770 .dt_compat = r8a7779_compat_dt,
779MACHINE_END 771MACHINE_END
780#endif /* CONFIG_USE_OF */ 772#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 0c12b01bb9e3..877fdeb985d0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -282,11 +282,6 @@ static struct resource cmt0_resources[] = {
282 &cmt##idx##_platform_data, \ 282 &cmt##idx##_platform_data, \
283 sizeof(struct sh_timer_config)) 283 sizeof(struct sh_timer_config))
284 284
285void __init r8a7790_add_dt_devices(void)
286{
287 r8a7790_register_cmt(0);
288}
289
290void __init r8a7790_add_standard_devices(void) 285void __init r8a7790_add_standard_devices(void)
291{ 286{
292 r8a7790_register_scif(0); 287 r8a7790_register_scif(0);
@@ -299,7 +294,7 @@ void __init r8a7790_add_standard_devices(void)
299 r8a7790_register_scif(7); 294 r8a7790_register_scif(7);
300 r8a7790_register_scif(8); 295 r8a7790_register_scif(8);
301 r8a7790_register_scif(9); 296 r8a7790_register_scif(9);
302 r8a7790_add_dt_devices(); 297 r8a7790_register_cmt(0);
303 r8a7790_register_irqc(0); 298 r8a7790_register_irqc(0);
304 r8a7790_register_thermal(); 299 r8a7790_register_thermal();
305 r8a7790_register_i2c(0); 300 r8a7790_register_i2c(0);
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index d47d8b16a43f..35d78639244f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -182,11 +182,6 @@ static const struct resource thermal_resources[] __initconst = {
182 thermal_resources, \ 182 thermal_resources, \
183 ARRAY_SIZE(thermal_resources)) 183 ARRAY_SIZE(thermal_resources))
184 184
185void __init r8a7791_add_dt_devices(void)
186{
187 r8a7791_register_cmt(0);
188}
189
190void __init r8a7791_add_standard_devices(void) 185void __init r8a7791_add_standard_devices(void)
191{ 186{
192 r8a7791_register_scif(0); 187 r8a7791_register_scif(0);
@@ -204,7 +199,7 @@ void __init r8a7791_add_standard_devices(void)
204 r8a7791_register_scif(12); 199 r8a7791_register_scif(12);
205 r8a7791_register_scif(13); 200 r8a7791_register_scif(13);
206 r8a7791_register_scif(14); 201 r8a7791_register_scif(14);
207 r8a7791_add_dt_devices(); 202 r8a7791_register_cmt(0);
208 r8a7791_register_irqc(0); 203 r8a7791_register_irqc(0);
209 r8a7791_register_thermal(); 204 r8a7791_register_thermal();
210} 205}
diff --git a/arch/arm/mach-shmobile/setup-r8a7794.c b/arch/arm/mach-shmobile/setup-r8a7794.c
new file mode 100644
index 000000000000..d2b093033132
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7794.c
@@ -0,0 +1,33 @@
1/*
2 * r8a7794 processor support
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/of_platform.h>
18#include "common.h"
19#include "rcar-gen2.h"
20#include <asm/mach/arch.h>
21
22static const char * const r8a7794_boards_compat_dt[] __initconst = {
23 "renesas,r8a7794",
24 NULL,
25};
26
27DT_MACHINE_START(R8A7794_DT, "Generic R8A7794 (Flattened Device Tree)")
28 .init_early = shmobile_init_delay,
29 .init_late = shmobile_init_late,
30 .init_time = rcar_gen2_timer_init,
31 .reserve = rcar_gen2_reserve,
32 .dt_compat = r8a7794_boards_compat_dt,
33MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 9cdfcdfd38fc..d646c8d12423 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -41,6 +41,7 @@
41 41
42#include "common.h" 42#include "common.h"
43#include "dma-register.h" 43#include "dma-register.h"
44#include "intc.h"
44#include "irqs.h" 45#include "irqs.h"
45#include "pm-rmobile.h" 46#include "pm-rmobile.h"
46#include "sh7372.h" 47#include "sh7372.h"
@@ -927,7 +928,7 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
927 928
928void __init sh7372_add_standard_devices(void) 929void __init sh7372_add_standard_devices(void)
929{ 930{
930 struct pm_domain_device domain_devices[] = { 931 static struct pm_domain_device domain_devices[] __initdata = {
931 { "A3RV", &vpu_device, }, 932 { "A3RV", &vpu_device, },
932 { "A4MP", &spu0_device, }, 933 { "A4MP", &spu0_device, },
933 { "A4MP", &spu1_device, }, 934 { "A4MP", &spu1_device, },
@@ -984,7 +985,7 @@ void __init sh7372_add_early_devices(void)
984 985
985void __init sh7372_add_early_devices_dt(void) 986void __init sh7372_add_early_devices_dt(void)
986{ 987{
987 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */ 988 shmobile_init_delay();
988 989
989 sh7372_add_early_devices(); 990 sh7372_add_early_devices();
990} 991}
@@ -1008,7 +1009,6 @@ static const char *sh7372_boards_compat_dt[] __initdata = {
1008DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)") 1009DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1009 .map_io = sh7372_map_io, 1010 .map_io = sh7372_map_io,
1010 .init_early = sh7372_add_early_devices_dt, 1011 .init_early = sh7372_add_early_devices_dt,
1011 .nr_irqs = NR_IRQS_LEGACY,
1012 .init_irq = sh7372_init_irq, 1012 .init_irq = sh7372_init_irq,
1013 .handle_irq = shmobile_handle_irq_intc, 1013 .handle_irq = shmobile_handle_irq_intc,
1014 .init_machine = sh7372_add_standard_devices_dt, 1014 .init_machine = sh7372_add_standard_devices_dt,
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 2c802ae9b241..b7bd8e509668 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -40,6 +40,7 @@
40 40
41#include "common.h" 41#include "common.h"
42#include "dma-register.h" 42#include "dma-register.h"
43#include "intc.h"
43#include "irqs.h" 44#include "irqs.h"
44#include "sh73a0.h" 45#include "sh73a0.h"
45 46
@@ -696,10 +697,6 @@ static struct platform_device irqpin3_device = {
696 }, 697 },
697}; 698};
698 699
699static struct platform_device *sh73a0_devices_dt[] __initdata = {
700 &cmt1_device,
701};
702
703static struct platform_device *sh73a0_early_devices[] __initdata = { 700static struct platform_device *sh73a0_early_devices[] __initdata = {
704 &scif0_device, 701 &scif0_device,
705 &scif1_device, 702 &scif1_device,
@@ -712,6 +709,7 @@ static struct platform_device *sh73a0_early_devices[] __initdata = {
712 &scif8_device, 709 &scif8_device,
713 &tmu0_device, 710 &tmu0_device,
714 &ipmmu_device, 711 &ipmmu_device,
712 &cmt1_device,
715}; 713};
716 714
717static struct platform_device *sh73a0_late_devices[] __initdata = { 715static struct platform_device *sh73a0_late_devices[] __initdata = {
@@ -736,8 +734,6 @@ void __init sh73a0_add_standard_devices(void)
736 /* Clear software reset bit on SY-DMAC module */ 734 /* Clear software reset bit on SY-DMAC module */
737 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); 735 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
738 736
739 platform_add_devices(sh73a0_devices_dt,
740 ARRAY_SIZE(sh73a0_devices_dt));
741 platform_add_devices(sh73a0_early_devices, 737 platform_add_devices(sh73a0_early_devices,
742 ARRAY_SIZE(sh73a0_early_devices)); 738 ARRAY_SIZE(sh73a0_early_devices));
743 platform_add_devices(sh73a0_late_devices, 739 platform_add_devices(sh73a0_late_devices,
@@ -746,7 +742,7 @@ void __init sh73a0_add_standard_devices(void)
746 742
747void __init sh73a0_init_delay(void) 743void __init sh73a0_init_delay(void)
748{ 744{
749 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ 745 shmobile_init_delay();
750} 746}
751 747
752/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 748/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
@@ -762,8 +758,6 @@ void __init sh73a0_earlytimer_init(void)
762 758
763void __init sh73a0_add_early_devices(void) 759void __init sh73a0_add_early_devices(void)
764{ 760{
765 early_platform_add_devices(sh73a0_devices_dt,
766 ARRAY_SIZE(sh73a0_devices_dt));
767 early_platform_add_devices(sh73a0_early_devices, 761 early_platform_add_devices(sh73a0_early_devices,
768 ARRAY_SIZE(sh73a0_early_devices)); 762 ARRAY_SIZE(sh73a0_early_devices));
769 763
@@ -775,17 +769,10 @@ void __init sh73a0_add_early_devices(void)
775 769
776void __init sh73a0_add_standard_devices_dt(void) 770void __init sh73a0_add_standard_devices_dt(void)
777{ 771{
778 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
779
780 /* clocks are setup late during boot in the case of DT */ 772 /* clocks are setup late during boot in the case of DT */
781 sh73a0_clock_init(); 773 sh73a0_clock_init();
782 774
783 platform_add_devices(sh73a0_devices_dt,
784 ARRAY_SIZE(sh73a0_devices_dt));
785 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 775 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
786
787 /* Instantiate cpufreq-cpu0 */
788 platform_device_register_full(&devinfo);
789} 776}
790 777
791static const char *sh73a0_boards_compat_dt[] __initdata = { 778static const char *sh73a0_boards_compat_dt[] __initdata = {
@@ -797,8 +784,8 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
797 .smp = smp_ops(sh73a0_smp_ops), 784 .smp = smp_ops(sh73a0_smp_ops),
798 .map_io = sh73a0_map_io, 785 .map_io = sh73a0_map_io,
799 .init_early = sh73a0_init_delay, 786 .init_early = sh73a0_init_delay,
800 .nr_irqs = NR_IRQS_LEGACY,
801 .init_machine = sh73a0_add_standard_devices_dt, 787 .init_machine = sh73a0_add_standard_devices_dt,
788 .init_late = shmobile_init_late,
802 .dt_compat = sh73a0_boards_compat_dt, 789 .dt_compat = sh73a0_boards_compat_dt,
803MACHINE_END 790MACHINE_END
804#endif /* CONFIG_USE_OF */ 791#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 942efdc82a62..87c6be1e79bd 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -23,8 +23,8 @@
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/of_address.h> 24#include <linux/of_address.h>
25 25
26void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz, 26static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
27 unsigned int mult, unsigned int div) 27 unsigned int mult, unsigned int div)
28{ 28{
29 /* calculate a worst-case loops-per-jiffy value 29 /* calculate a worst-case loops-per-jiffy value
30 * based on maximum cpu core hz setting and the 30 * based on maximum cpu core hz setting and the
@@ -40,27 +40,10 @@ void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
40 preset_lpj = max_cpu_core_hz / value; 40 preset_lpj = max_cpu_core_hz / value;
41} 41}
42 42
43void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
44 unsigned int mult, unsigned int div)
45{
46 /* calculate a worst-case loops-per-jiffy value
47 * based on maximum cpu core mhz setting and the
48 * __delay() implementation in arch/arm/lib/delay.S
49 *
50 * this will result in a longer delay than expected
51 * when the cpu core runs on lower frequencies.
52 */
53
54 unsigned int value = (1000000 * mult) / (HZ * div);
55
56 if (!preset_lpj)
57 preset_lpj = max_cpu_core_mhz * value;
58}
59
60void __init shmobile_init_delay(void) 43void __init shmobile_init_delay(void)
61{ 44{
62 struct device_node *np, *cpus; 45 struct device_node *np, *cpus;
63 bool is_a8_a9 = false; 46 bool is_a7_a8_a9 = false;
64 bool is_a15 = false; 47 bool is_a15 = false;
65 u32 max_freq = 0; 48 u32 max_freq = 0;
66 49
@@ -74,9 +57,10 @@ void __init shmobile_init_delay(void)
74 if (!of_property_read_u32(np, "clock-frequency", &freq)) 57 if (!of_property_read_u32(np, "clock-frequency", &freq))
75 max_freq = max(max_freq, freq); 58 max_freq = max(max_freq, freq);
76 59
77 if (of_device_is_compatible(np, "arm,cortex-a8") || 60 if (of_device_is_compatible(np, "arm,cortex-a7") ||
61 of_device_is_compatible(np, "arm,cortex-a8") ||
78 of_device_is_compatible(np, "arm,cortex-a9")) 62 of_device_is_compatible(np, "arm,cortex-a9"))
79 is_a8_a9 = true; 63 is_a7_a8_a9 = true;
80 else if (of_device_is_compatible(np, "arm,cortex-a15")) 64 else if (of_device_is_compatible(np, "arm,cortex-a15"))
81 is_a15 = true; 65 is_a15 = true;
82 } 66 }
@@ -86,7 +70,7 @@ void __init shmobile_init_delay(void)
86 if (!max_freq) 70 if (!max_freq)
87 return; 71 return;
88 72
89 if (is_a8_a9) 73 if (is_a7_a8_a9)
90 shmobile_setup_delay_hz(max_freq, 1, 3); 74 shmobile_setup_delay_hz(max_freq, 1, 3);
91 else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) 75 else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
92 shmobile_setup_delay_hz(max_freq, 2, 4); 76 shmobile_setup_delay_hz(max_freq, 2, 4);
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 6fd4dc88160b..b6f4bda273b3 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -4,7 +4,6 @@
4 4
5menuconfig PLAT_SPEAR 5menuconfig PLAT_SPEAR
6 bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5 6 bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
7 default PLAT_SPEAR_SINGLE
8 select ARCH_REQUIRE_GPIOLIB 7 select ARCH_REQUIRE_GPIOLIB
9 select ARM_AMBA 8 select ARM_AMBA
10 select CLKSRC_MMIO 9 select CLKSRC_MMIO
@@ -13,7 +12,7 @@ if PLAT_SPEAR
13 12
14config ARCH_SPEAR13XX 13config ARCH_SPEAR13XX
15 bool "ST SPEAr13xx" 14 bool "ST SPEAr13xx"
16 depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE 15 depends on ARCH_MULTI_V7
17 select ARM_GIC 16 select ARM_GIC
18 select GPIO_SPEAR_SPICS 17 select GPIO_SPEAR_SPICS
19 select HAVE_ARM_SCU if SMP 18 select HAVE_ARM_SCU if SMP
@@ -44,7 +43,7 @@ endif #ARCH_SPEAR13XX
44 43
45config ARCH_SPEAR3XX 44config ARCH_SPEAR3XX
46 bool "ST SPEAr3xx" 45 bool "ST SPEAr3xx"
47 depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE 46 depends on ARCH_MULTI_V5
48 depends on !ARCH_SPEAR13XX 47 depends on !ARCH_SPEAR13XX
49 select ARM_VIC 48 select ARM_VIC
50 select PINCTRL 49 select PINCTRL
@@ -75,7 +74,7 @@ endif
75 74
76config ARCH_SPEAR6XX 75config ARCH_SPEAR6XX
77 bool "ST SPEAr6XX" 76 bool "ST SPEAr6XX"
78 depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE 77 depends on ARCH_MULTI_V5
79 depends on !ARCH_SPEAR13XX 78 depends on !ARCH_SPEAR13XX
80 select ARM_VIC 79 select ARM_VIC
81 help 80 help
@@ -88,7 +87,7 @@ config MACH_SPEAR600
88 Supports ST SPEAr600 boards configured via the device-tree 87 Supports ST SPEAr600 boards configured via the device-tree
89 88
90config ARCH_SPEAR_AUTO 89config ARCH_SPEAR_AUTO
91 def_bool PLAT_SPEAR_SINGLE 90 bool
92 depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX 91 depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
93 select ARCH_SPEAR3XX 92 select ARCH_SPEAR3XX
94 93
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 42d4753683ce..d7598aeed803 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -12,81 +12,9 @@
12 12
13#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
14#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/init.h> 15#include <linux/init.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/io.h>
22#include <linux/reboot.h>
23 16
24#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/system_misc.h>
27
28#define SUN4I_WATCHDOG_CTRL_REG 0x00
29#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
30#define SUN4I_WATCHDOG_MODE_REG 0x04
31#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
32#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
33
34#define SUN6I_WATCHDOG1_IRQ_REG 0x00
35#define SUN6I_WATCHDOG1_CTRL_REG 0x10
36#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
37#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
38#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
39#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
40#define SUN6I_WATCHDOG1_MODE_REG 0x18
41#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
42
43static void __iomem *wdt_base;
44
45static void sun4i_restart(enum reboot_mode mode, const char *cmd)
46{
47 if (!wdt_base)
48 return;
49
50 /* Enable timer and set reset bit in the watchdog */
51 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
52 wdt_base + SUN4I_WATCHDOG_MODE_REG);
53
54 /*
55 * Restart the watchdog. The default (and lowest) interval
56 * value for the watchdog is 0.5s.
57 */
58 writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
59
60 while (1) {
61 mdelay(5);
62 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
63 wdt_base + SUN4I_WATCHDOG_MODE_REG);
64 }
65}
66
67static struct of_device_id sunxi_restart_ids[] = {
68 { .compatible = "allwinner,sun4i-a10-wdt" },
69 { /*sentinel*/ }
70};
71
72static void sunxi_setup_restart(void)
73{
74 struct device_node *np;
75
76 np = of_find_matching_node(NULL, sunxi_restart_ids);
77 if (WARN(!np, "unable to setup watchdog restart"))
78 return;
79
80 wdt_base = of_iomap(np, 0);
81 WARN(!wdt_base, "failed to map watchdog base address");
82}
83
84static void __init sunxi_dt_init(void)
85{
86 sunxi_setup_restart();
87
88 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
89}
90 18
91static const char * const sunxi_board_dt_compat[] = { 19static const char * const sunxi_board_dt_compat[] = {
92 "allwinner,sun4i-a10", 20 "allwinner,sun4i-a10",
@@ -96,9 +24,7 @@ static const char * const sunxi_board_dt_compat[] = {
96}; 24};
97 25
98DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") 26DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
99 .init_machine = sunxi_dt_init,
100 .dt_compat = sunxi_board_dt_compat, 27 .dt_compat = sunxi_board_dt_compat,
101 .restart = sun4i_restart,
102MACHINE_END 28MACHINE_END
103 29
104static const char * const sun6i_board_dt_compat[] = { 30static const char * const sun6i_board_dt_compat[] = {
@@ -126,9 +52,7 @@ static const char * const sun7i_board_dt_compat[] = {
126}; 52};
127 53
128DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") 54DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
129 .init_machine = sunxi_dt_init,
130 .dt_compat = sun7i_board_dt_compat, 55 .dt_compat = sun7i_board_dt_compat,
131 .restart = sun4i_restart,
132MACHINE_END 56MACHINE_END
133 57
134static const char * const sun8i_board_dt_compat[] = { 58static const char * const sun8i_board_dt_compat[] = {
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index ec55d1de1b55..475e783992fd 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -22,11 +22,12 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
25 27
26#include <soc/tegra/fuse.h> 28#include <soc/tegra/fuse.h>
27 29
28#include "flowctrl.h" 30#include "flowctrl.h"
29#include "iomap.h"
30 31
31static u8 flowctrl_offset_halt_cpu[] = { 32static u8 flowctrl_offset_halt_cpu[] = {
32 FLOW_CTRL_HALT_CPU0_EVENTS, 33 FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -42,23 +43,22 @@ static u8 flowctrl_offset_cpu_csr[] = {
42 FLOW_CTRL_CPU1_CSR + 16, 43 FLOW_CTRL_CPU1_CSR + 16,
43}; 44};
44 45
46static void __iomem *tegra_flowctrl_base;
47
45static void flowctrl_update(u8 offset, u32 value) 48static void flowctrl_update(u8 offset, u32 value)
46{ 49{
47 void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset; 50 writel(value, tegra_flowctrl_base + offset);
48
49 writel(value, addr);
50 51
51 /* ensure the update has reached the flow controller */ 52 /* ensure the update has reached the flow controller */
52 wmb(); 53 wmb();
53 readl_relaxed(addr); 54 readl_relaxed(tegra_flowctrl_base + offset);
54} 55}
55 56
56u32 flowctrl_read_cpu_csr(unsigned int cpuid) 57u32 flowctrl_read_cpu_csr(unsigned int cpuid)
57{ 58{
58 u8 offset = flowctrl_offset_cpu_csr[cpuid]; 59 u8 offset = flowctrl_offset_cpu_csr[cpuid];
59 void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
60 60
61 return readl(addr); 61 return readl(tegra_flowctrl_base + offset);
62} 62}
63 63
64void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) 64void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
@@ -139,3 +139,33 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
139 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ 139 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
140 flowctrl_write_cpu_csr(cpuid, reg); 140 flowctrl_write_cpu_csr(cpuid, reg);
141} 141}
142
143static const struct of_device_id matches[] __initconst = {
144 { .compatible = "nvidia,tegra124-flowctrl" },
145 { .compatible = "nvidia,tegra114-flowctrl" },
146 { .compatible = "nvidia,tegra30-flowctrl" },
147 { .compatible = "nvidia,tegra20-flowctrl" },
148 { }
149};
150
151void __init tegra_flowctrl_init(void)
152{
153 /* hardcoded fallback if device tree node is missing */
154 unsigned long base = 0x60007000;
155 unsigned long size = SZ_4K;
156 struct device_node *np;
157
158 np = of_find_matching_node(NULL, matches);
159 if (np) {
160 struct resource res;
161
162 if (of_address_to_resource(np, 0, &res) == 0) {
163 size = resource_size(&res);
164 base = res.start;
165 }
166
167 of_node_put(np);
168 }
169
170 tegra_flowctrl_base = ioremap_nocache(base, size);
171}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index c89aac60a143..73a9c5016c1a 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
59 59
60void flowctrl_cpu_suspend_enter(unsigned int cpuid); 60void flowctrl_cpu_suspend_enter(unsigned int cpuid);
61void flowctrl_cpu_suspend_exit(unsigned int cpuid); 61void flowctrl_cpu_suspend_exit(unsigned int cpuid);
62
63void tegra_flowctrl_init(void);
62#endif 64#endif
63 65
64#endif 66#endif
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 5ef5173dec83..ef016af1c9e7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -48,6 +48,7 @@
48#include "board.h" 48#include "board.h"
49#include "common.h" 49#include "common.h"
50#include "cpuidle.h" 50#include "cpuidle.h"
51#include "flowctrl.h"
51#include "iomap.h" 52#include "iomap.h"
52#include "irq.h" 53#include "irq.h"
53#include "pm.h" 54#include "pm.h"
@@ -74,6 +75,7 @@ static void __init tegra_init_early(void)
74{ 75{
75 of_register_trusted_foundations(); 76 of_register_trusted_foundations();
76 tegra_cpu_reset_handler_init(); 77 tegra_cpu_reset_handler_init();
78 tegra_flowctrl_init();
77} 79}
78 80
79static void __init tegra_dt_init_irq(void) 81static void __init tegra_dt_init_irq(void)
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 2da7be31e7e2..3bc0dc9a4d69 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -69,7 +69,7 @@ static void vt8500_power_off(void)
69{ 69{
70 local_irq_disable(); 70 local_irq_disable();
71 writew(5, pmc_base + VT8500_HCR_REG); 71 writew(5, pmc_base + VT8500_HCR_REG);
72 asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); 72 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (0));
73} 73}
74 74
75static void __init vt8500_init(void) 75static void __init vt8500_init(void)
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 1b25d92ebf22..c85fb3f7d5cd 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -3,8 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o slcr.o 6obj-y := common.o slcr.o pm.o
7CFLAGS_REMOVE_hotplug.o =-march=armv6k 7CFLAGS_REMOVE_hotplug.o =-march=armv6k
8CFLAGS_hotplug.o =-Wa,-march=armv7-a -mcpu=cortex-a9 8CFLAGS_hotplug.o =-Wa,-march=armv7-a -mcpu=cortex-a9
9obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
10obj-$(CONFIG_SMP) += headsmp.o platsmp.o 9obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 31a6fa40ba37..26f92c28d22b 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -98,13 +98,19 @@ static int __init zynq_get_revision(void)
98 return revision; 98 return revision;
99} 99}
100 100
101static void __init zynq_init_late(void)
102{
103 zynq_core_pm_init();
104 zynq_pm_late_init();
105}
106
101/** 107/**
102 * zynq_init_machine - System specific initialization, intended to be 108 * zynq_init_machine - System specific initialization, intended to be
103 * called from board specific initialization. 109 * called from board specific initialization.
104 */ 110 */
105static void __init zynq_init_machine(void) 111static void __init zynq_init_machine(void)
106{ 112{
107 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; 113 struct platform_device_info devinfo = { .name = "cpufreq-dt", };
108 struct soc_device_attribute *soc_dev_attr; 114 struct soc_device_attribute *soc_dev_attr;
109 struct soc_device *soc_dev; 115 struct soc_device *soc_dev;
110 struct device *parent = NULL; 116 struct device *parent = NULL;
@@ -198,12 +204,13 @@ static const char * const zynq_dt_match[] = {
198 204
199DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") 205DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
200 /* 64KB way size, 8-way associativity, parity disabled */ 206 /* 64KB way size, 8-way associativity, parity disabled */
201 .l2c_aux_val = 0x02000000, 207 .l2c_aux_val = 0x00000000,
202 .l2c_aux_mask = 0xf0ffffff, 208 .l2c_aux_mask = 0xffffffff,
203 .smp = smp_ops(zynq_smp_ops), 209 .smp = smp_ops(zynq_smp_ops),
204 .map_io = zynq_map_io, 210 .map_io = zynq_map_io,
205 .init_irq = zynq_irq_init, 211 .init_irq = zynq_irq_init,
206 .init_machine = zynq_init_machine, 212 .init_machine = zynq_init_machine,
213 .init_late = zynq_init_late,
207 .init_time = zynq_timer_init, 214 .init_time = zynq_timer_init,
208 .dt_compat = zynq_dt_match, 215 .dt_compat = zynq_dt_match,
209 .reserve = zynq_memory_init, 216 .reserve = zynq_memory_init,
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index f652f0a884a6..2bc71273c73c 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -24,6 +24,8 @@ extern int zynq_early_slcr_init(void);
24extern void zynq_slcr_system_reset(void); 24extern void zynq_slcr_system_reset(void);
25extern void zynq_slcr_cpu_stop(int cpu); 25extern void zynq_slcr_cpu_stop(int cpu);
26extern void zynq_slcr_cpu_start(int cpu); 26extern void zynq_slcr_cpu_start(int cpu);
27extern bool zynq_slcr_cpu_state_read(int cpu);
28extern void zynq_slcr_cpu_state_write(int cpu, bool die);
27extern u32 zynq_slcr_get_device_id(void); 29extern u32 zynq_slcr_get_device_id(void);
28 30
29#ifdef CONFIG_SMP 31#ifdef CONFIG_SMP
@@ -37,7 +39,17 @@ extern struct smp_operations zynq_smp_ops __initdata;
37 39
38extern void __iomem *zynq_scu_base; 40extern void __iomem *zynq_scu_base;
39 41
40/* Hotplug */ 42void zynq_pm_late_init(void);
41extern void zynq_platform_cpu_die(unsigned int cpu); 43
44static inline void zynq_core_pm_init(void)
45{
46 /* A9 clock gating */
47 asm volatile ("mrc p15, 0, r12, c15, c0, 0\n"
48 "orr r12, r12, #1\n"
49 "mcr p15, 0, r12, c15, c0, 0\n"
50 : /* no outputs */
51 : /* no inputs */
52 : "r12");
53}
42 54
43#endif 55#endif
diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
index 5052c70326e4..b685c89f11e4 100644
--- a/arch/arm/mach-zynq/hotplug.c
+++ b/arch/arm/mach-zynq/hotplug.c
@@ -10,50 +10,5 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#include <linux/kernel.h> 13#include <asm/proc-fns.h>
14#include <linux/errno.h>
15#include <linux/smp.h>
16 14
17#include <asm/cacheflush.h>
18#include <asm/cp15.h>
19#include "common.h"
20
21static inline void zynq_cpu_enter_lowpower(void)
22{
23 unsigned int v;
24
25 flush_cache_all();
26 asm volatile(
27 " mcr p15, 0, %1, c7, c5, 0\n"
28 " dsb\n"
29 /*
30 * Turn off coherency
31 */
32 " mrc p15, 0, %0, c1, c0, 1\n"
33 " bic %0, %0, #0x40\n"
34 " mcr p15, 0, %0, c1, c0, 1\n"
35 " mrc p15, 0, %0, c1, c0, 0\n"
36 " bic %0, %0, %2\n"
37 " mcr p15, 0, %0, c1, c0, 0\n"
38 : "=&r" (v)
39 : "r" (0), "Ir" (CR_C)
40 : "cc");
41}
42
43/*
44 * platform-specific code to shutdown a CPU
45 *
46 * Called with IRQs disabled
47 */
48void zynq_platform_cpu_die(unsigned int cpu)
49{
50 zynq_cpu_enter_lowpower();
51
52 /*
53 * there is no power-control hardware on this platform, so all
54 * we can do is put the core into WFI; this is safe as the calling
55 * code will have already disabled interrupts
56 */
57 for (;;)
58 cpu_do_idle();
59}
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index abc82ef085c1..52d768ff7857 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -112,20 +112,59 @@ static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
112 scu_enable(zynq_scu_base); 112 scu_enable(zynq_scu_base);
113} 113}
114 114
115/**
116 * zynq_secondary_init - Initialize secondary CPU cores
117 * @cpu: CPU that is initialized
118 *
119 * This function is in the hotplug path. Don't move it into the
120 * init section!!
121 */
122static void zynq_secondary_init(unsigned int cpu)
123{
124 zynq_core_pm_init();
125}
126
115#ifdef CONFIG_HOTPLUG_CPU 127#ifdef CONFIG_HOTPLUG_CPU
116static int zynq_cpu_kill(unsigned cpu) 128static int zynq_cpu_kill(unsigned cpu)
117{ 129{
130 unsigned long timeout = jiffies + msecs_to_jiffies(50);
131
132 while (zynq_slcr_cpu_state_read(cpu))
133 if (time_after(jiffies, timeout))
134 return 0;
135
118 zynq_slcr_cpu_stop(cpu); 136 zynq_slcr_cpu_stop(cpu);
119 return 1; 137 return 1;
120} 138}
139
140/**
141 * zynq_cpu_die - Let a CPU core die
142 * @cpu: Dying CPU
143 *
144 * Platform-specific code to shutdown a CPU.
145 * Called with IRQs disabled on the dying CPU.
146 */
147static void zynq_cpu_die(unsigned int cpu)
148{
149 zynq_slcr_cpu_state_write(cpu, true);
150
151 /*
152 * there is no power-control hardware on this platform, so all
153 * we can do is put the core into WFI; this is safe as the calling
154 * code will have already disabled interrupts
155 */
156 for (;;)
157 cpu_do_idle();
158}
121#endif 159#endif
122 160
123struct smp_operations zynq_smp_ops __initdata = { 161struct smp_operations zynq_smp_ops __initdata = {
124 .smp_init_cpus = zynq_smp_init_cpus, 162 .smp_init_cpus = zynq_smp_init_cpus,
125 .smp_prepare_cpus = zynq_smp_prepare_cpus, 163 .smp_prepare_cpus = zynq_smp_prepare_cpus,
126 .smp_boot_secondary = zynq_boot_secondary, 164 .smp_boot_secondary = zynq_boot_secondary,
165 .smp_secondary_init = zynq_secondary_init,
127#ifdef CONFIG_HOTPLUG_CPU 166#ifdef CONFIG_HOTPLUG_CPU
128 .cpu_die = zynq_platform_cpu_die, 167 .cpu_die = zynq_cpu_die,
129 .cpu_kill = zynq_cpu_kill, 168 .cpu_kill = zynq_cpu_kill,
130#endif 169#endif
131}; 170};
diff --git a/arch/arm/mach-zynq/pm.c b/arch/arm/mach-zynq/pm.c
new file mode 100644
index 000000000000..911fcf865be8
--- /dev/null
+++ b/arch/arm/mach-zynq/pm.c
@@ -0,0 +1,83 @@
1/*
2 * Zynq power management
3 *
4 * Copyright (C) 2012 - 2014 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/io.h>
23#include <linux/of_address.h>
24#include <linux/of_device.h>
25#include "common.h"
26
27/* register offsets */
28#define DDRC_CTRL_REG1_OFFS 0x60
29#define DDRC_DRAM_PARAM_REG3_OFFS 0x20
30
31/* bitfields */
32#define DDRC_CLOCKSTOP_MASK BIT(23)
33#define DDRC_SELFREFRESH_MASK BIT(12)
34
35static void __iomem *ddrc_base;
36
37/**
38 * zynq_pm_ioremap() - Create IO mappings
39 * @comp: DT compatible string
40 * Return: Pointer to the mapped memory or NULL.
41 *
42 * Remap the memory region for a compatible DT node.
43 */
44static void __iomem *zynq_pm_ioremap(const char *comp)
45{
46 struct device_node *np;
47 void __iomem *base = NULL;
48
49 np = of_find_compatible_node(NULL, NULL, comp);
50 if (np) {
51 base = of_iomap(np, 0);
52 of_node_put(np);
53 } else {
54 pr_warn("%s: no compatible node found for '%s'\n", __func__,
55 comp);
56 }
57
58 return base;
59}
60
61/**
62 * zynq_pm_late_init() - Power management init
63 *
64 * Initialization of power management related featurs and infrastructure.
65 */
66void __init zynq_pm_late_init(void)
67{
68 u32 reg;
69
70 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05");
71 if (!ddrc_base) {
72 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__);
73 } else {
74 /*
75 * Enable DDRC clock stop feature. The HW takes care of
76 * entering/exiting the correct mode depending
77 * on activity state.
78 */
79 reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
80 reg |= DDRC_CLOCKSTOP_MASK;
81 writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
82 }
83}
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index c43a2d16e223..d4cb50cf97c0 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -138,6 +138,8 @@ void zynq_slcr_cpu_start(int cpu)
138 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); 138 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
139 reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); 139 reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
140 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); 140 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
141
142 zynq_slcr_cpu_state_write(cpu, false);
141} 143}
142 144
143/** 145/**
@@ -154,8 +156,47 @@ void zynq_slcr_cpu_stop(int cpu)
154} 156}
155 157
156/** 158/**
157 * zynq_slcr_init - Regular slcr driver init 159 * zynq_slcr_cpu_state - Read/write cpu state
160 * @cpu: cpu number
158 * 161 *
162 * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
163 * 0 means cpu is running, 1 cpu is going to die.
164 *
165 * Return: true if cpu is running, false if cpu is going to die
166 */
167bool zynq_slcr_cpu_state_read(int cpu)
168{
169 u32 state;
170
171 state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
172 state &= 1 << (31 - cpu);
173
174 return !state;
175}
176
177/**
178 * zynq_slcr_cpu_state - Read/write cpu state
179 * @cpu: cpu number
180 * @die: cpu state - true if cpu is going to die
181 *
182 * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
183 * 0 means cpu is running, 1 cpu is going to die.
184 */
185void zynq_slcr_cpu_state_write(int cpu, bool die)
186{
187 u32 state, mask;
188
189 state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
190 mask = 1 << (31 - cpu);
191 if (die)
192 state |= mask;
193 else
194 state &= ~mask;
195 writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
196}
197
198/**
199 * zynq_slcr_init - Regular slcr driver init
159 * Return: 0 on success, negative errno otherwise. 200 * Return: 0 on success, negative errno otherwise.
160 * 201 *
161 * Called early during boot from platform code to remap SLCR area. 202 * Called early during boot from platform code to remap SLCR area.
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 0c1ab49e5f7b..83792f4324ea 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -41,6 +41,7 @@
41 * This code is not portable to processors with late data abort handling. 41 * This code is not portable to processors with late data abort handling.
42 */ 42 */
43#define CODING_BITS(i) (i & 0x0e000000) 43#define CODING_BITS(i) (i & 0x0e000000)
44#define COND_BITS(i) (i & 0xf0000000)
44 45
45#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */ 46#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
46#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */ 47#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
@@ -821,6 +822,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
821 break; 822 break;
822 823
823 case 0x04000000: /* ldr or str immediate */ 824 case 0x04000000: /* ldr or str immediate */
825 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
826 goto bad;
824 offset.un = OFFSET_BITS(instr); 827 offset.un = OFFSET_BITS(instr);
825 handler = do_alignment_ldrstr; 828 handler = do_alignment_ldrstr;
826 break; 829 break;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5f2c988a06ac..55f9d6e0cc88 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/log2.h>
24#include <linux/io.h> 25#include <linux/io.h>
25#include <linux/of.h> 26#include <linux/of.h>
26#include <linux/of_address.h> 27#include <linux/of_address.h>
@@ -945,6 +946,98 @@ static int l2_wt_override;
945 * pass it though the device tree */ 946 * pass it though the device tree */
946static u32 cache_id_part_number_from_dt; 947static u32 cache_id_part_number_from_dt;
947 948
949/**
950 * l2x0_cache_size_of_parse() - read cache size parameters from DT
951 * @np: the device tree node for the l2 cache
952 * @aux_val: pointer to machine-supplied auxilary register value, to
953 * be augmented by the call (bits to be set to 1)
954 * @aux_mask: pointer to machine-supplied auxilary register mask, to
955 * be augmented by the call (bits to be set to 0)
956 * @associativity: variable to return the calculated associativity in
957 * @max_way_size: the maximum size in bytes for the cache ways
958 */
959static void __init l2x0_cache_size_of_parse(const struct device_node *np,
960 u32 *aux_val, u32 *aux_mask,
961 u32 *associativity,
962 u32 max_way_size)
963{
964 u32 mask = 0, val = 0;
965 u32 cache_size = 0, sets = 0;
966 u32 way_size_bits = 1;
967 u32 way_size = 0;
968 u32 block_size = 0;
969 u32 line_size = 0;
970
971 of_property_read_u32(np, "cache-size", &cache_size);
972 of_property_read_u32(np, "cache-sets", &sets);
973 of_property_read_u32(np, "cache-block-size", &block_size);
974 of_property_read_u32(np, "cache-line-size", &line_size);
975
976 if (!cache_size || !sets)
977 return;
978
979 /* All these l2 caches have the same line = block size actually */
980 if (!line_size) {
981 if (block_size) {
982 /* If linesize if not given, it is equal to blocksize */
983 line_size = block_size;
984 } else {
985 /* Fall back to known size */
986 pr_warn("L2C OF: no cache block/line size given: "
987 "falling back to default size %d bytes\n",
988 CACHE_LINE_SIZE);
989 line_size = CACHE_LINE_SIZE;
990 }
991 }
992
993 if (line_size != CACHE_LINE_SIZE)
994 pr_warn("L2C OF: DT supplied line size %d bytes does "
995 "not match hardware line size of %d bytes\n",
996 line_size,
997 CACHE_LINE_SIZE);
998
999 /*
1000 * Since:
1001 * set size = cache size / sets
1002 * ways = cache size / (sets * line size)
1003 * way size = cache size / (cache size / (sets * line size))
1004 * way size = sets * line size
1005 * associativity = ways = cache size / way size
1006 */
1007 way_size = sets * line_size;
1008 *associativity = cache_size / way_size;
1009
1010 if (way_size > max_way_size) {
1011 pr_err("L2C OF: set size %dKB is too large\n", way_size);
1012 return;
1013 }
1014
1015 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
1016 cache_size, cache_size >> 10);
1017 pr_info("L2C OF: override line size: %d bytes\n", line_size);
1018 pr_info("L2C OF: override way size: %d bytes (%dKB)\n",
1019 way_size, way_size >> 10);
1020 pr_info("L2C OF: override associativity: %d\n", *associativity);
1021
1022 /*
1023 * Calculates the bits 17:19 to set for way size:
1024 * 512KB -> 6, 256KB -> 5, ... 16KB -> 1
1025 */
1026 way_size_bits = ilog2(way_size >> 10) - 3;
1027 if (way_size_bits < 1 || way_size_bits > 6) {
1028 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
1029 way_size);
1030 return;
1031 }
1032
1033 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
1034 val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT);
1035
1036 *aux_val &= ~mask;
1037 *aux_val |= val;
1038 *aux_mask &= ~mask;
1039}
1040
948static void __init l2x0_of_parse(const struct device_node *np, 1041static void __init l2x0_of_parse(const struct device_node *np,
949 u32 *aux_val, u32 *aux_mask) 1042 u32 *aux_val, u32 *aux_mask)
950{ 1043{
@@ -952,6 +1045,7 @@ static void __init l2x0_of_parse(const struct device_node *np,
952 u32 tag = 0; 1045 u32 tag = 0;
953 u32 dirty = 0; 1046 u32 dirty = 0;
954 u32 val = 0, mask = 0; 1047 u32 val = 0, mask = 0;
1048 u32 assoc;
955 1049
956 of_property_read_u32(np, "arm,tag-latency", &tag); 1050 of_property_read_u32(np, "arm,tag-latency", &tag);
957 if (tag) { 1051 if (tag) {
@@ -974,6 +1068,15 @@ static void __init l2x0_of_parse(const struct device_node *np,
974 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 1068 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
975 } 1069 }
976 1070
1071 l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
1072 if (assoc > 8) {
1073 pr_err("l2x0 of: cache setting yield too high associativity\n");
1074 pr_err("l2x0 of: %d calculated, max 8\n", assoc);
1075 } else {
1076 mask |= L2X0_AUX_CTRL_ASSOC_MASK;
1077 val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT);
1078 }
1079
977 *aux_val &= ~mask; 1080 *aux_val &= ~mask;
978 *aux_val |= val; 1081 *aux_val |= val;
979 *aux_mask &= ~mask; 1082 *aux_mask &= ~mask;
@@ -1021,6 +1124,7 @@ static void __init l2c310_of_parse(const struct device_node *np,
1021 u32 data[3] = { 0, 0, 0 }; 1124 u32 data[3] = { 0, 0, 0 };
1022 u32 tag[3] = { 0, 0, 0 }; 1125 u32 tag[3] = { 0, 0, 0 };
1023 u32 filter[2] = { 0, 0 }; 1126 u32 filter[2] = { 0, 0 };
1127 u32 assoc;
1024 1128
1025 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 1129 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
1026 if (tag[0] && tag[1] && tag[2]) 1130 if (tag[0] && tag[1] && tag[2])
@@ -1047,6 +1151,23 @@ static void __init l2c310_of_parse(const struct device_node *np,
1047 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN, 1151 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
1048 l2x0_base + L310_ADDR_FILTER_START); 1152 l2x0_base + L310_ADDR_FILTER_START);
1049 } 1153 }
1154
1155 l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
1156 switch (assoc) {
1157 case 16:
1158 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1159 *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16;
1160 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1161 break;
1162 case 8:
1163 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1164 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1165 break;
1166 default:
1167 pr_err("PL310 OF: cache setting yield illegal associativity\n");
1168 pr_err("PL310 OF: %d calculated, only 8 and 16 legal\n", assoc);
1169 break;
1170 }
1050} 1171}
1051 1172
1052static const struct l2c_init_data of_l2c310_data __initconst = { 1173static const struct l2c_init_data of_l2c310_data __initconst = {
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 7a996aaa061e..c245d903927f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -12,6 +12,7 @@
12#include <linux/bootmem.h> 12#include <linux/bootmem.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/genalloc.h>
15#include <linux/gfp.h> 16#include <linux/gfp.h>
16#include <linux/errno.h> 17#include <linux/errno.h>
17#include <linux/list.h> 18#include <linux/list.h>
@@ -298,57 +299,29 @@ static void *
298__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, 299__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
299 const void *caller) 300 const void *caller)
300{ 301{
301 struct vm_struct *area;
302 unsigned long addr;
303
304 /* 302 /*
305 * DMA allocation can be mapped to user space, so lets 303 * DMA allocation can be mapped to user space, so lets
306 * set VM_USERMAP flags too. 304 * set VM_USERMAP flags too.
307 */ 305 */
308 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, 306 return dma_common_contiguous_remap(page, size,
309 caller); 307 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
310 if (!area) 308 prot, caller);
311 return NULL;
312 addr = (unsigned long)area->addr;
313 area->phys_addr = __pfn_to_phys(page_to_pfn(page));
314
315 if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
316 vunmap((void *)addr);
317 return NULL;
318 }
319 return (void *)addr;
320} 309}
321 310
322static void __dma_free_remap(void *cpu_addr, size_t size) 311static void __dma_free_remap(void *cpu_addr, size_t size)
323{ 312{
324 unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; 313 dma_common_free_remap(cpu_addr, size,
325 struct vm_struct *area = find_vm_area(cpu_addr); 314 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
326 if (!area || (area->flags & flags) != flags) {
327 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
328 return;
329 }
330 unmap_kernel_range((unsigned long)cpu_addr, size);
331 vunmap(cpu_addr);
332} 315}
333 316
334#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K 317#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
318static struct gen_pool *atomic_pool;
335 319
336struct dma_pool { 320static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
337 size_t size;
338 spinlock_t lock;
339 unsigned long *bitmap;
340 unsigned long nr_pages;
341 void *vaddr;
342 struct page **pages;
343};
344
345static struct dma_pool atomic_pool = {
346 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
347};
348 321
349static int __init early_coherent_pool(char *p) 322static int __init early_coherent_pool(char *p)
350{ 323{
351 atomic_pool.size = memparse(p, &p); 324 atomic_pool_size = memparse(p, &p);
352 return 0; 325 return 0;
353} 326}
354early_param("coherent_pool", early_coherent_pool); 327early_param("coherent_pool", early_coherent_pool);
@@ -358,14 +331,14 @@ void __init init_dma_coherent_pool_size(unsigned long size)
358 /* 331 /*
359 * Catch any attempt to set the pool size too late. 332 * Catch any attempt to set the pool size too late.
360 */ 333 */
361 BUG_ON(atomic_pool.vaddr); 334 BUG_ON(atomic_pool);
362 335
363 /* 336 /*
364 * Set architecture specific coherent pool size only if 337 * Set architecture specific coherent pool size only if
365 * it has not been changed by kernel command line parameter. 338 * it has not been changed by kernel command line parameter.
366 */ 339 */
367 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) 340 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
368 atomic_pool.size = size; 341 atomic_pool_size = size;
369} 342}
370 343
371/* 344/*
@@ -373,52 +346,44 @@ void __init init_dma_coherent_pool_size(unsigned long size)
373 */ 346 */
374static int __init atomic_pool_init(void) 347static int __init atomic_pool_init(void)
375{ 348{
376 struct dma_pool *pool = &atomic_pool;
377 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); 349 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
378 gfp_t gfp = GFP_KERNEL | GFP_DMA; 350 gfp_t gfp = GFP_KERNEL | GFP_DMA;
379 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
380 unsigned long *bitmap;
381 struct page *page; 351 struct page *page;
382 struct page **pages;
383 void *ptr; 352 void *ptr;
384 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
385 353
386 bitmap = kzalloc(bitmap_size, GFP_KERNEL); 354 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
387 if (!bitmap) 355 if (!atomic_pool)
388 goto no_bitmap; 356 goto out;
389
390 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
391 if (!pages)
392 goto no_pages;
393 357
394 if (dev_get_cma_area(NULL)) 358 if (dev_get_cma_area(NULL))
395 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page, 359 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
396 atomic_pool_init); 360 &page, atomic_pool_init);
397 else 361 else
398 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page, 362 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
399 atomic_pool_init); 363 &page, atomic_pool_init);
400 if (ptr) { 364 if (ptr) {
401 int i; 365 int ret;
402 366
403 for (i = 0; i < nr_pages; i++) 367 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
404 pages[i] = page + i; 368 page_to_phys(page),
405 369 atomic_pool_size, -1);
406 spin_lock_init(&pool->lock); 370 if (ret)
407 pool->vaddr = ptr; 371 goto destroy_genpool;
408 pool->pages = pages; 372
409 pool->bitmap = bitmap; 373 gen_pool_set_algo(atomic_pool,
410 pool->nr_pages = nr_pages; 374 gen_pool_first_fit_order_align,
411 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", 375 (void *)PAGE_SHIFT);
412 (unsigned)pool->size / 1024); 376 pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n",
377 atomic_pool_size / 1024);
413 return 0; 378 return 0;
414 } 379 }
415 380
416 kfree(pages); 381destroy_genpool:
417no_pages: 382 gen_pool_destroy(atomic_pool);
418 kfree(bitmap); 383 atomic_pool = NULL;
419no_bitmap: 384out:
420 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", 385 pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n",
421 (unsigned)pool->size / 1024); 386 atomic_pool_size / 1024);
422 return -ENOMEM; 387 return -ENOMEM;
423} 388}
424/* 389/*
@@ -522,76 +487,36 @@ static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
522 487
523static void *__alloc_from_pool(size_t size, struct page **ret_page) 488static void *__alloc_from_pool(size_t size, struct page **ret_page)
524{ 489{
525 struct dma_pool *pool = &atomic_pool; 490 unsigned long val;
526 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
527 unsigned int pageno;
528 unsigned long flags;
529 void *ptr = NULL; 491 void *ptr = NULL;
530 unsigned long align_mask;
531 492
532 if (!pool->vaddr) { 493 if (!atomic_pool) {
533 WARN(1, "coherent pool not initialised!\n"); 494 WARN(1, "coherent pool not initialised!\n");
534 return NULL; 495 return NULL;
535 } 496 }
536 497
537 /* 498 val = gen_pool_alloc(atomic_pool, size);
538 * Align the region allocation - allocations from pool are rather 499 if (val) {
539 * small, so align them to their order in pages, minimum is a page 500 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
540 * size. This helps reduce fragmentation of the DMA space. 501
541 */ 502 *ret_page = phys_to_page(phys);
542 align_mask = (1 << get_order(size)) - 1; 503 ptr = (void *)val;
543
544 spin_lock_irqsave(&pool->lock, flags);
545 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
546 0, count, align_mask);
547 if (pageno < pool->nr_pages) {
548 bitmap_set(pool->bitmap, pageno, count);
549 ptr = pool->vaddr + PAGE_SIZE * pageno;
550 *ret_page = pool->pages[pageno];
551 } else {
552 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
553 "Please increase it with coherent_pool= kernel parameter!\n",
554 (unsigned)pool->size / 1024);
555 } 504 }
556 spin_unlock_irqrestore(&pool->lock, flags);
557 505
558 return ptr; 506 return ptr;
559} 507}
560 508
561static bool __in_atomic_pool(void *start, size_t size) 509static bool __in_atomic_pool(void *start, size_t size)
562{ 510{
563 struct dma_pool *pool = &atomic_pool; 511 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
564 void *end = start + size;
565 void *pool_start = pool->vaddr;
566 void *pool_end = pool->vaddr + pool->size;
567
568 if (start < pool_start || start >= pool_end)
569 return false;
570
571 if (end <= pool_end)
572 return true;
573
574 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
575 start, end - 1, pool_start, pool_end - 1);
576
577 return false;
578} 512}
579 513
580static int __free_from_pool(void *start, size_t size) 514static int __free_from_pool(void *start, size_t size)
581{ 515{
582 struct dma_pool *pool = &atomic_pool;
583 unsigned long pageno, count;
584 unsigned long flags;
585
586 if (!__in_atomic_pool(start, size)) 516 if (!__in_atomic_pool(start, size))
587 return 0; 517 return 0;
588 518
589 pageno = (start - pool->vaddr) >> PAGE_SHIFT; 519 gen_pool_free(atomic_pool, (unsigned long)start, size);
590 count = size >> PAGE_SHIFT;
591
592 spin_lock_irqsave(&pool->lock, flags);
593 bitmap_clear(pool->bitmap, pageno, count);
594 spin_unlock_irqrestore(&pool->lock, flags);
595 520
596 return 1; 521 return 1;
597} 522}
@@ -1271,29 +1196,8 @@ static void *
1271__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, 1196__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1272 const void *caller) 1197 const void *caller)
1273{ 1198{
1274 unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 1199 return dma_common_pages_remap(pages, size,
1275 struct vm_struct *area; 1200 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1276 unsigned long p;
1277
1278 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
1279 caller);
1280 if (!area)
1281 return NULL;
1282
1283 area->pages = pages;
1284 area->nr_pages = nr_pages;
1285 p = (unsigned long)area->addr;
1286
1287 for (i = 0; i < nr_pages; i++) {
1288 phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
1289 if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
1290 goto err;
1291 p += PAGE_SIZE;
1292 }
1293 return area->addr;
1294err:
1295 unmap_kernel_range((unsigned long)area->addr, size);
1296 vunmap(area->addr);
1297 return NULL; 1201 return NULL;
1298} 1202}
1299 1203
@@ -1355,11 +1259,13 @@ static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t si
1355 1259
1356static struct page **__atomic_get_pages(void *addr) 1260static struct page **__atomic_get_pages(void *addr)
1357{ 1261{
1358 struct dma_pool *pool = &atomic_pool; 1262 struct page *page;
1359 struct page **pages = pool->pages; 1263 phys_addr_t phys;
1360 int offs = (addr - pool->vaddr) >> PAGE_SHIFT; 1264
1265 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1266 page = phys_to_page(phys);
1361 1267
1362 return pages + offs; 1268 return (struct page **)page;
1363} 1269}
1364 1270
1365static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) 1271static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
@@ -1501,8 +1407,8 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1501 } 1407 }
1502 1408
1503 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { 1409 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1504 unmap_kernel_range((unsigned long)cpu_addr, size); 1410 dma_common_free_remap(cpu_addr, size,
1505 vunmap(cpu_addr); 1411 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1506 } 1412 }
1507 1413
1508 __iommu_remove_mapping(dev, handle, size); 1414 __iommu_remove_mapping(dev, handle, size);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 43d54f5b26b9..265b836b3bd1 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -400,3 +400,18 @@ void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned l
400 */ 400 */
401 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); 401 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
402} 402}
403
404#ifdef CONFIG_TRANSPARENT_HUGEPAGE
405#ifdef CONFIG_HAVE_RCU_TABLE_FREE
406void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
407 pmd_t *pmdp)
408{
409 pmd_t pmd = pmd_mksplitting(*pmdp);
410 VM_BUG_ON(address & ~PMD_MASK);
411 set_pmd_at(vma->vm_mm, address, pmdp, pmd);
412
413 /* dummy IPI to serialise against fast_gup */
414 kick_all_cpus_sync();
415}
416#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
417#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index c447ec70e868..e7a81cebbb2e 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -27,7 +27,7 @@ static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end,
27 if (pud_none_or_clear_bad(pud) || (pud_val(*pud) & L_PGD_SWAPPER)) { 27 if (pud_none_or_clear_bad(pud) || (pud_val(*pud) & L_PGD_SWAPPER)) {
28 pmd = pmd_alloc_one(&init_mm, addr); 28 pmd = pmd_alloc_one(&init_mm, addr);
29 if (!pmd) { 29 if (!pmd) {
30 pr_warning("Failed to allocate identity pmd.\n"); 30 pr_warn("Failed to allocate identity pmd.\n");
31 return; 31 return;
32 } 32 }
33 /* 33 /*
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 659c75d808dc..92bba32d9230 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -322,7 +322,7 @@ void __init arm_memblock_init(const struct machine_desc *mdesc)
322 * reserve memory for DMA contigouos allocations, 322 * reserve memory for DMA contigouos allocations,
323 * must come from DMA area inside low memory 323 * must come from DMA area inside low memory
324 */ 324 */
325 dma_contiguous_reserve(min(arm_dma_limit, arm_lowmem_limit)); 325 dma_contiguous_reserve(arm_dma_limit);
326 326
327 arm_memblock_steal_permitted = false; 327 arm_memblock_steal_permitted = false;
328 memblock_dump_all(); 328 memblock_dump_all();
@@ -636,6 +636,11 @@ static int keep_initrd;
636void free_initrd_mem(unsigned long start, unsigned long end) 636void free_initrd_mem(unsigned long start, unsigned long end)
637{ 637{
638 if (!keep_initrd) { 638 if (!keep_initrd) {
639 if (start == initrd_start)
640 start = round_down(start, PAGE_SIZE);
641 if (end == initrd_end)
642 end = round_up(end, PAGE_SIZE);
643
639 poison_init_mem((void *)start, PAGE_ALIGN(end) - start); 644 poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
640 free_reserved_area((void *)start, (void *)end, -1, "initrd"); 645 free_reserved_area((void *)start, (void *)end, -1, "initrd");
641 } 646 }
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 8348ed6b2efe..9f98cec7fe1e 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -223,13 +223,13 @@ early_param("ecc", early_ecc);
223 223
224static int __init early_cachepolicy(char *p) 224static int __init early_cachepolicy(char *p)
225{ 225{
226 pr_warning("cachepolicy kernel parameter not supported without cp15\n"); 226 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
227} 227}
228early_param("cachepolicy", early_cachepolicy); 228early_param("cachepolicy", early_cachepolicy);
229 229
230static int __init noalign_setup(char *__unused) 230static int __init noalign_setup(char *__unused)
231{ 231{
232 pr_warning("noalign kernel parameter not supported without cp15\n"); 232 pr_warn("noalign kernel parameter not supported without cp15\n");
233} 233}
234__setup("noalign", noalign_setup); 234__setup("noalign", noalign_setup);
235 235
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index b64e67c7f176..d3daed0ae0ad 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -157,9 +157,9 @@ ENDPROC(cpu_v7_set_pte_ext)
157 * TFR EV X F IHD LR S 157 * TFR EV X F IHD LR S
158 * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM 158 * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
159 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 159 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
160 * 11 0 110 1 0011 1100 .111 1101 < we want 160 * 11 0 110 0 0011 1100 .111 1101 < we want
161 */ 161 */
162 .align 2 162 .align 2
163 .type v7_crval, #object 163 .type v7_crval, #object
164v7_crval: 164v7_crval:
165 crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c 165 crval clear=0x0122c302, mmuset=0x30c03c7d, ucset=0x00c01c7c
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b5d67db20897..b3a947863ac7 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -570,7 +570,7 @@ __v7_ca15mp_proc_info:
570__v7_b15mp_proc_info: 570__v7_b15mp_proc_info:
571 .long 0x420f00f0 571 .long 0x420f00f0
572 .long 0xff0ffff0 572 .long 0xff0ffff0
573 __v7_proc __v7_b15mp_setup, hwcaps = HWCAP_IDIV 573 __v7_proc __v7_b15mp_setup
574 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info 574 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
575 575
576 /* 576 /*
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index a37b989a2f91..e1268f905026 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -12,11 +12,11 @@
12#include <linux/compiler.h> 12#include <linux/compiler.h>
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/filter.h> 14#include <linux/filter.h>
15#include <linux/moduleloader.h>
16#include <linux/netdevice.h> 15#include <linux/netdevice.h>
17#include <linux/string.h> 16#include <linux/string.h>
18#include <linux/slab.h> 17#include <linux/slab.h>
19#include <linux/if_vlan.h> 18#include <linux/if_vlan.h>
19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/hwcap.h> 21#include <asm/hwcap.h>
22#include <asm/opcodes.h> 22#include <asm/opcodes.h>
@@ -174,6 +174,14 @@ static inline bool is_load_to_a(u16 inst)
174 } 174 }
175} 175}
176 176
177static void jit_fill_hole(void *area, unsigned int size)
178{
179 u32 *ptr;
180 /* We are guaranteed to have aligned memory. */
181 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
182 *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
183}
184
177static void build_prologue(struct jit_ctx *ctx) 185static void build_prologue(struct jit_ctx *ctx)
178{ 186{
179 u16 reg_set = saved_regs(ctx); 187 u16 reg_set = saved_regs(ctx);
@@ -859,9 +867,11 @@ b_epilogue:
859 867
860void bpf_jit_compile(struct bpf_prog *fp) 868void bpf_jit_compile(struct bpf_prog *fp)
861{ 869{
870 struct bpf_binary_header *header;
862 struct jit_ctx ctx; 871 struct jit_ctx ctx;
863 unsigned tmp_idx; 872 unsigned tmp_idx;
864 unsigned alloc_size; 873 unsigned alloc_size;
874 u8 *target_ptr;
865 875
866 if (!bpf_jit_enable) 876 if (!bpf_jit_enable)
867 return; 877 return;
@@ -897,13 +907,15 @@ void bpf_jit_compile(struct bpf_prog *fp)
897 /* there's nothing after the epilogue on ARMv7 */ 907 /* there's nothing after the epilogue on ARMv7 */
898 build_epilogue(&ctx); 908 build_epilogue(&ctx);
899#endif 909#endif
900
901 alloc_size = 4 * ctx.idx; 910 alloc_size = 4 * ctx.idx;
902 ctx.target = module_alloc(alloc_size); 911 header = bpf_jit_binary_alloc(alloc_size, &target_ptr,
903 if (unlikely(ctx.target == NULL)) 912 4, jit_fill_hole);
913 if (header == NULL)
904 goto out; 914 goto out;
905 915
916 ctx.target = (u32 *) target_ptr;
906 ctx.idx = 0; 917 ctx.idx = 0;
918
907 build_prologue(&ctx); 919 build_prologue(&ctx);
908 build_body(&ctx); 920 build_body(&ctx);
909 build_epilogue(&ctx); 921 build_epilogue(&ctx);
@@ -919,8 +931,9 @@ void bpf_jit_compile(struct bpf_prog *fp)
919 /* there are 2 passes here */ 931 /* there are 2 passes here */
920 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target); 932 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
921 933
934 set_memory_ro((unsigned long)header, header->pages);
922 fp->bpf_func = (void *)ctx.target; 935 fp->bpf_func = (void *)ctx.target;
923 fp->jited = 1; 936 fp->jited = true;
924out: 937out:
925 kfree(ctx.offsets); 938 kfree(ctx.offsets);
926 return; 939 return;
@@ -928,7 +941,15 @@ out:
928 941
929void bpf_jit_free(struct bpf_prog *fp) 942void bpf_jit_free(struct bpf_prog *fp)
930{ 943{
931 if (fp->jited) 944 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
932 module_free(NULL, fp->bpf_func); 945 struct bpf_binary_header *header = (void *)addr;
933 kfree(fp); 946
947 if (!fp->jited)
948 goto free_filter;
949
950 set_memory_rw(addr, header->pages);
951 bpf_jit_binary_free(header);
952
953free_filter:
954 bpf_prog_unlock_free(fp);
934} 955}
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index afb84621ff6f..b2d7d92859d3 100644
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -114,6 +114,20 @@
114 114
115#define ARM_INST_UMULL 0x00800090 115#define ARM_INST_UMULL 0x00800090
116 116
117/*
118 * Use a suitable undefined instruction to use for ARM/Thumb2 faulting.
119 * We need to be careful not to conflict with those used by other modules
120 * (BUG, kprobes, etc) and the register_undef_hook() system.
121 *
122 * The ARM architecture reference manual guarantees that the following
123 * instruction space will produce an undefined instruction exception on
124 * all CPUs:
125 *
126 * ARM: xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx ARMv7-AR, section A5.4
127 * Thumb: 1101 1110 xxxx xxxx ARMv7-M, section A5.2.6
128 */
129#define ARM_INST_UDF 0xe7fddef1
130
117/* register */ 131/* register */
118#define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) 132#define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
119/* immediate */ 133/* immediate */
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c2baa8ede543..24770e5a5081 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -64,7 +64,9 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
64 64
65static struct omap_system_dma_plat_info *p; 65static struct omap_system_dma_plat_info *p;
66static struct omap_dma_dev_attr *d; 66static struct omap_dma_dev_attr *d;
67 67static void omap_clear_dma(int lch);
68static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
69 unsigned char write_prio);
68static int enable_1510_mode; 70static int enable_1510_mode;
69static u32 errata; 71static u32 errata;
70 72
@@ -284,66 +286,6 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
284} 286}
285EXPORT_SYMBOL(omap_set_dma_transfer_params); 287EXPORT_SYMBOL(omap_set_dma_transfer_params);
286 288
287void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
288{
289 BUG_ON(omap_dma_in_1510_mode());
290
291 if (dma_omap1()) {
292 u16 w;
293
294 w = p->dma_read(CCR2, lch);
295 w &= ~0x03;
296
297 switch (mode) {
298 case OMAP_DMA_CONSTANT_FILL:
299 w |= 0x01;
300 break;
301 case OMAP_DMA_TRANSPARENT_COPY:
302 w |= 0x02;
303 break;
304 case OMAP_DMA_COLOR_DIS:
305 break;
306 default:
307 BUG();
308 }
309 p->dma_write(w, CCR2, lch);
310
311 w = p->dma_read(LCH_CTRL, lch);
312 w &= ~0x0f;
313 /* Default is channel type 2D */
314 if (mode) {
315 p->dma_write(color, COLOR, lch);
316 w |= 1; /* Channel type G */
317 }
318 p->dma_write(w, LCH_CTRL, lch);
319 }
320
321 if (dma_omap2plus()) {
322 u32 val;
323
324 val = p->dma_read(CCR, lch);
325 val &= ~((1 << 17) | (1 << 16));
326
327 switch (mode) {
328 case OMAP_DMA_CONSTANT_FILL:
329 val |= 1 << 16;
330 break;
331 case OMAP_DMA_TRANSPARENT_COPY:
332 val |= 1 << 17;
333 break;
334 case OMAP_DMA_COLOR_DIS:
335 break;
336 default:
337 BUG();
338 }
339 p->dma_write(val, CCR, lch);
340
341 color &= 0xffffff;
342 p->dma_write(color, COLOR, lch);
343 }
344}
345EXPORT_SYMBOL(omap_set_dma_color_mode);
346
347void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 289void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
348{ 290{
349 if (dma_omap2plus()) { 291 if (dma_omap2plus()) {
@@ -417,16 +359,6 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
417} 359}
418EXPORT_SYMBOL(omap_set_dma_params); 360EXPORT_SYMBOL(omap_set_dma_params);
419 361
420void omap_set_dma_src_index(int lch, int eidx, int fidx)
421{
422 if (dma_omap2plus())
423 return;
424
425 p->dma_write(eidx, CSEI, lch);
426 p->dma_write(fidx, CSFI, lch);
427}
428EXPORT_SYMBOL(omap_set_dma_src_index);
429
430void omap_set_dma_src_data_pack(int lch, int enable) 362void omap_set_dma_src_data_pack(int lch, int enable)
431{ 363{
432 u32 l; 364 u32 l;
@@ -510,16 +442,6 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
510} 442}
511EXPORT_SYMBOL(omap_set_dma_dest_params); 443EXPORT_SYMBOL(omap_set_dma_dest_params);
512 444
513void omap_set_dma_dest_index(int lch, int eidx, int fidx)
514{
515 if (dma_omap2plus())
516 return;
517
518 p->dma_write(eidx, CDEI, lch);
519 p->dma_write(fidx, CDFI, lch);
520}
521EXPORT_SYMBOL(omap_set_dma_dest_index);
522
523void omap_set_dma_dest_data_pack(int lch, int enable) 445void omap_set_dma_dest_data_pack(int lch, int enable)
524{ 446{
525 u32 l; 447 u32 l;
@@ -843,7 +765,7 @@ EXPORT_SYMBOL(omap_dma_set_global_params);
843 * Both of the above can be set with one of the following values : 765 * Both of the above can be set with one of the following values :
844 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW 766 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
845 */ 767 */
846int 768static int
847omap_dma_set_prio_lch(int lch, unsigned char read_prio, 769omap_dma_set_prio_lch(int lch, unsigned char read_prio,
848 unsigned char write_prio) 770 unsigned char write_prio)
849{ 771{
@@ -864,13 +786,13 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
864 786
865 return 0; 787 return 0;
866} 788}
867EXPORT_SYMBOL(omap_dma_set_prio_lch); 789
868 790
869/* 791/*
870 * Clears any DMA state so the DMA engine is ready to restart with new buffers 792 * Clears any DMA state so the DMA engine is ready to restart with new buffers
871 * through omap_start_dma(). Any buffers in flight are discarded. 793 * through omap_start_dma(). Any buffers in flight are discarded.
872 */ 794 */
873void omap_clear_dma(int lch) 795static void omap_clear_dma(int lch)
874{ 796{
875 unsigned long flags; 797 unsigned long flags;
876 798
@@ -878,7 +800,6 @@ void omap_clear_dma(int lch)
878 p->clear_dma(lch); 800 p->clear_dma(lch);
879 local_irq_restore(flags); 801 local_irq_restore(flags);
880} 802}
881EXPORT_SYMBOL(omap_clear_dma);
882 803
883void omap_start_dma(int lch) 804void omap_start_dma(int lch)
884{ 805{
@@ -1167,652 +1088,6 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
1167} 1088}
1168EXPORT_SYMBOL(omap_dma_link_lch); 1089EXPORT_SYMBOL(omap_dma_link_lch);
1169 1090
1170/*
1171 * Once the DMA queue is stopped, we can destroy it.
1172 */
1173void omap_dma_unlink_lch(int lch_head, int lch_queue)
1174{
1175 if (omap_dma_in_1510_mode()) {
1176 if (lch_head == lch_queue) {
1177 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1178 CCR, lch_head);
1179 return;
1180 }
1181 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1182 BUG();
1183 return;
1184 }
1185
1186 if (dma_chan[lch_head].next_lch != lch_queue ||
1187 dma_chan[lch_head].next_lch == -1) {
1188 pr_err("omap_dma: trying to unlink non linked channels\n");
1189 dump_stack();
1190 }
1191
1192 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1193 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1194 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1195 dump_stack();
1196 }
1197
1198 dma_chan[lch_head].next_lch = -1;
1199}
1200EXPORT_SYMBOL(omap_dma_unlink_lch);
1201
1202#ifndef CONFIG_ARCH_OMAP1
1203/* Create chain of DMA channesls */
1204static void create_dma_lch_chain(int lch_head, int lch_queue)
1205{
1206 u32 l;
1207
1208 /* Check if this is the first link in chain */
1209 if (dma_chan[lch_head].next_linked_ch == -1) {
1210 dma_chan[lch_head].next_linked_ch = lch_queue;
1211 dma_chan[lch_head].prev_linked_ch = lch_queue;
1212 dma_chan[lch_queue].next_linked_ch = lch_head;
1213 dma_chan[lch_queue].prev_linked_ch = lch_head;
1214 }
1215
1216 /* a link exists, link the new channel in circular chain */
1217 else {
1218 dma_chan[lch_queue].next_linked_ch =
1219 dma_chan[lch_head].next_linked_ch;
1220 dma_chan[lch_queue].prev_linked_ch = lch_head;
1221 dma_chan[lch_head].next_linked_ch = lch_queue;
1222 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1223 lch_queue;
1224 }
1225
1226 l = p->dma_read(CLNK_CTRL, lch_head);
1227 l &= ~(0x1f);
1228 l |= lch_queue;
1229 p->dma_write(l, CLNK_CTRL, lch_head);
1230
1231 l = p->dma_read(CLNK_CTRL, lch_queue);
1232 l &= ~(0x1f);
1233 l |= (dma_chan[lch_queue].next_linked_ch);
1234 p->dma_write(l, CLNK_CTRL, lch_queue);
1235}
1236
1237/**
1238 * @brief omap_request_dma_chain : Request a chain of DMA channels
1239 *
1240 * @param dev_id - Device id using the dma channel
1241 * @param dev_name - Device name
1242 * @param callback - Call back function
1243 * @chain_id -
1244 * @no_of_chans - Number of channels requested
1245 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1246 * OMAP_DMA_DYNAMIC_CHAIN
1247 * @params - Channel parameters
1248 *
1249 * @return - Success : 0
1250 * Failure: -EINVAL/-ENOMEM
1251 */
1252int omap_request_dma_chain(int dev_id, const char *dev_name,
1253 void (*callback) (int lch, u16 ch_status,
1254 void *data),
1255 int *chain_id, int no_of_chans, int chain_mode,
1256 struct omap_dma_channel_params params)
1257{
1258 int *channels;
1259 int i, err;
1260
1261 /* Is the chain mode valid ? */
1262 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1263 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1264 printk(KERN_ERR "Invalid chain mode requested\n");
1265 return -EINVAL;
1266 }
1267
1268 if (unlikely((no_of_chans < 1
1269 || no_of_chans > dma_lch_count))) {
1270 printk(KERN_ERR "Invalid Number of channels requested\n");
1271 return -EINVAL;
1272 }
1273
1274 /*
1275 * Allocate a queue to maintain the status of the channels
1276 * in the chain
1277 */
1278 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1279 if (channels == NULL) {
1280 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1281 return -ENOMEM;
1282 }
1283
1284 /* request and reserve DMA channels for the chain */
1285 for (i = 0; i < no_of_chans; i++) {
1286 err = omap_request_dma(dev_id, dev_name,
1287 callback, NULL, &channels[i]);
1288 if (err < 0) {
1289 int j;
1290 for (j = 0; j < i; j++)
1291 omap_free_dma(channels[j]);
1292 kfree(channels);
1293 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1294 return err;
1295 }
1296 dma_chan[channels[i]].prev_linked_ch = -1;
1297 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1298
1299 /*
1300 * Allowing client drivers to set common parameters now,
1301 * so that later only relevant (src_start, dest_start
1302 * and element count) can be set
1303 */
1304 omap_set_dma_params(channels[i], &params);
1305 }
1306
1307 *chain_id = channels[0];
1308 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1309 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1310 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1311 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1312
1313 for (i = 0; i < no_of_chans; i++)
1314 dma_chan[channels[i]].chain_id = *chain_id;
1315
1316 /* Reset the Queue pointers */
1317 OMAP_DMA_CHAIN_QINIT(*chain_id);
1318
1319 /* Set up the chain */
1320 if (no_of_chans == 1)
1321 create_dma_lch_chain(channels[0], channels[0]);
1322 else {
1323 for (i = 0; i < (no_of_chans - 1); i++)
1324 create_dma_lch_chain(channels[i], channels[i + 1]);
1325 }
1326
1327 return 0;
1328}
1329EXPORT_SYMBOL(omap_request_dma_chain);
1330
1331/**
1332 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1333 * params after setting it. Dont do this while dma is running!!
1334 *
1335 * @param chain_id - Chained logical channel id.
1336 * @param params
1337 *
1338 * @return - Success : 0
1339 * Failure : -EINVAL
1340 */
1341int omap_modify_dma_chain_params(int chain_id,
1342 struct omap_dma_channel_params params)
1343{
1344 int *channels;
1345 u32 i;
1346
1347 /* Check for input params */
1348 if (unlikely((chain_id < 0
1349 || chain_id >= dma_lch_count))) {
1350 printk(KERN_ERR "Invalid chain id\n");
1351 return -EINVAL;
1352 }
1353
1354 /* Check if the chain exists */
1355 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1356 printk(KERN_ERR "Chain doesn't exists\n");
1357 return -EINVAL;
1358 }
1359 channels = dma_linked_lch[chain_id].linked_dmach_q;
1360
1361 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1362 /*
1363 * Allowing client drivers to set common parameters now,
1364 * so that later only relevant (src_start, dest_start
1365 * and element count) can be set
1366 */
1367 omap_set_dma_params(channels[i], &params);
1368 }
1369
1370 return 0;
1371}
1372EXPORT_SYMBOL(omap_modify_dma_chain_params);
1373
1374/**
1375 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1376 *
1377 * @param chain_id
1378 *
1379 * @return - Success : 0
1380 * Failure : -EINVAL
1381 */
1382int omap_free_dma_chain(int chain_id)
1383{
1384 int *channels;
1385 u32 i;
1386
1387 /* Check for input params */
1388 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1389 printk(KERN_ERR "Invalid chain id\n");
1390 return -EINVAL;
1391 }
1392
1393 /* Check if the chain exists */
1394 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1395 printk(KERN_ERR "Chain doesn't exists\n");
1396 return -EINVAL;
1397 }
1398
1399 channels = dma_linked_lch[chain_id].linked_dmach_q;
1400 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1401 dma_chan[channels[i]].next_linked_ch = -1;
1402 dma_chan[channels[i]].prev_linked_ch = -1;
1403 dma_chan[channels[i]].chain_id = -1;
1404 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1405 omap_free_dma(channels[i]);
1406 }
1407
1408 kfree(channels);
1409
1410 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1411 dma_linked_lch[chain_id].chain_mode = -1;
1412 dma_linked_lch[chain_id].chain_state = -1;
1413
1414 return (0);
1415}
1416EXPORT_SYMBOL(omap_free_dma_chain);
1417
1418/**
1419 * @brief omap_dma_chain_status - Check if the chain is in
1420 * active / inactive state.
1421 * @param chain_id
1422 *
1423 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1424 * Failure : -EINVAL
1425 */
1426int omap_dma_chain_status(int chain_id)
1427{
1428 /* Check for input params */
1429 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1430 printk(KERN_ERR "Invalid chain id\n");
1431 return -EINVAL;
1432 }
1433
1434 /* Check if the chain exists */
1435 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1436 printk(KERN_ERR "Chain doesn't exists\n");
1437 return -EINVAL;
1438 }
1439 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1440 dma_linked_lch[chain_id].q_count);
1441
1442 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1443 return OMAP_DMA_CHAIN_INACTIVE;
1444
1445 return OMAP_DMA_CHAIN_ACTIVE;
1446}
1447EXPORT_SYMBOL(omap_dma_chain_status);
1448
1449/**
1450 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1451 * set the params and start the transfer.
1452 *
1453 * @param chain_id
1454 * @param src_start - buffer start address
1455 * @param dest_start - Dest address
1456 * @param elem_count
1457 * @param frame_count
1458 * @param callbk_data - channel callback parameter data.
1459 *
1460 * @return - Success : 0
1461 * Failure: -EINVAL/-EBUSY
1462 */
1463int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1464 int elem_count, int frame_count, void *callbk_data)
1465{
1466 int *channels;
1467 u32 l, lch;
1468 int start_dma = 0;
1469
1470 /*
1471 * if buffer size is less than 1 then there is
1472 * no use of starting the chain
1473 */
1474 if (elem_count < 1) {
1475 printk(KERN_ERR "Invalid buffer size\n");
1476 return -EINVAL;
1477 }
1478
1479 /* Check for input params */
1480 if (unlikely((chain_id < 0
1481 || chain_id >= dma_lch_count))) {
1482 printk(KERN_ERR "Invalid chain id\n");
1483 return -EINVAL;
1484 }
1485
1486 /* Check if the chain exists */
1487 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1488 printk(KERN_ERR "Chain doesn't exist\n");
1489 return -EINVAL;
1490 }
1491
1492 /* Check if all the channels in chain are in use */
1493 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1494 return -EBUSY;
1495
1496 /* Frame count may be negative in case of indexed transfers */
1497 channels = dma_linked_lch[chain_id].linked_dmach_q;
1498
1499 /* Get a free channel */
1500 lch = channels[dma_linked_lch[chain_id].q_tail];
1501
1502 /* Store the callback data */
1503 dma_chan[lch].data = callbk_data;
1504
1505 /* Increment the q_tail */
1506 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1507
1508 /* Set the params to the free channel */
1509 if (src_start != 0)
1510 p->dma_write(src_start, CSSA, lch);
1511 if (dest_start != 0)
1512 p->dma_write(dest_start, CDSA, lch);
1513
1514 /* Write the buffer size */
1515 p->dma_write(elem_count, CEN, lch);
1516 p->dma_write(frame_count, CFN, lch);
1517
1518 /*
1519 * If the chain is dynamically linked,
1520 * then we may have to start the chain if its not active
1521 */
1522 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1523
1524 /*
1525 * In Dynamic chain, if the chain is not started,
1526 * queue the channel
1527 */
1528 if (dma_linked_lch[chain_id].chain_state ==
1529 DMA_CHAIN_NOTSTARTED) {
1530 /* Enable the link in previous channel */
1531 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1532 DMA_CH_QUEUED)
1533 enable_lnk(dma_chan[lch].prev_linked_ch);
1534 dma_chan[lch].state = DMA_CH_QUEUED;
1535 }
1536
1537 /*
1538 * Chain is already started, make sure its active,
1539 * if not then start the chain
1540 */
1541 else {
1542 start_dma = 1;
1543
1544 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1545 DMA_CH_STARTED) {
1546 enable_lnk(dma_chan[lch].prev_linked_ch);
1547 dma_chan[lch].state = DMA_CH_QUEUED;
1548 start_dma = 0;
1549 if (0 == ((1 << 7) & p->dma_read(
1550 CCR, dma_chan[lch].prev_linked_ch))) {
1551 disable_lnk(dma_chan[lch].
1552 prev_linked_ch);
1553 pr_debug("\n prev ch is stopped\n");
1554 start_dma = 1;
1555 }
1556 }
1557
1558 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1559 == DMA_CH_QUEUED) {
1560 enable_lnk(dma_chan[lch].prev_linked_ch);
1561 dma_chan[lch].state = DMA_CH_QUEUED;
1562 start_dma = 0;
1563 }
1564 omap_enable_channel_irq(lch);
1565
1566 l = p->dma_read(CCR, lch);
1567
1568 if ((0 == (l & (1 << 24))))
1569 l &= ~(1 << 25);
1570 else
1571 l |= (1 << 25);
1572 if (start_dma == 1) {
1573 if (0 == (l & (1 << 7))) {
1574 l |= (1 << 7);
1575 dma_chan[lch].state = DMA_CH_STARTED;
1576 pr_debug("starting %d\n", lch);
1577 p->dma_write(l, CCR, lch);
1578 } else
1579 start_dma = 0;
1580 } else {
1581 if (0 == (l & (1 << 7)))
1582 p->dma_write(l, CCR, lch);
1583 }
1584 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1585 }
1586 }
1587
1588 return 0;
1589}
1590EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1591
1592/**
1593 * @brief omap_start_dma_chain_transfers - Start the chain
1594 *
1595 * @param chain_id
1596 *
1597 * @return - Success : 0
1598 * Failure : -EINVAL/-EBUSY
1599 */
1600int omap_start_dma_chain_transfers(int chain_id)
1601{
1602 int *channels;
1603 u32 l, i;
1604
1605 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1606 printk(KERN_ERR "Invalid chain id\n");
1607 return -EINVAL;
1608 }
1609
1610 channels = dma_linked_lch[chain_id].linked_dmach_q;
1611
1612 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1613 printk(KERN_ERR "Chain is already started\n");
1614 return -EBUSY;
1615 }
1616
1617 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1618 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1619 i++) {
1620 enable_lnk(channels[i]);
1621 omap_enable_channel_irq(channels[i]);
1622 }
1623 } else {
1624 omap_enable_channel_irq(channels[0]);
1625 }
1626
1627 l = p->dma_read(CCR, channels[0]);
1628 l |= (1 << 7);
1629 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1630 dma_chan[channels[0]].state = DMA_CH_STARTED;
1631
1632 if ((0 == (l & (1 << 24))))
1633 l &= ~(1 << 25);
1634 else
1635 l |= (1 << 25);
1636 p->dma_write(l, CCR, channels[0]);
1637
1638 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1639
1640 return 0;
1641}
1642EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1643
1644/**
1645 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1646 *
1647 * @param chain_id
1648 *
1649 * @return - Success : 0
1650 * Failure : EINVAL
1651 */
1652int omap_stop_dma_chain_transfers(int chain_id)
1653{
1654 int *channels;
1655 u32 l, i;
1656 u32 sys_cf = 0;
1657
1658 /* Check for input params */
1659 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1660 printk(KERN_ERR "Invalid chain id\n");
1661 return -EINVAL;
1662 }
1663
1664 /* Check if the chain exists */
1665 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1666 printk(KERN_ERR "Chain doesn't exists\n");
1667 return -EINVAL;
1668 }
1669 channels = dma_linked_lch[chain_id].linked_dmach_q;
1670
1671 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1672 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1673 l = sys_cf;
1674 /* Middle mode reg set no Standby */
1675 l &= ~((1 << 12)|(1 << 13));
1676 p->dma_write(l, OCP_SYSCONFIG, 0);
1677 }
1678
1679 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1680
1681 /* Stop the Channel transmission */
1682 l = p->dma_read(CCR, channels[i]);
1683 l &= ~(1 << 7);
1684 p->dma_write(l, CCR, channels[i]);
1685
1686 /* Disable the link in all the channels */
1687 disable_lnk(channels[i]);
1688 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1689
1690 }
1691 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1692
1693 /* Reset the Queue pointers */
1694 OMAP_DMA_CHAIN_QINIT(chain_id);
1695
1696 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1697 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1698
1699 return 0;
1700}
1701EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1702
1703/* Get the index of the ongoing DMA in chain */
1704/**
1705 * @brief omap_get_dma_chain_index - Get the element and frame index
1706 * of the ongoing DMA in chain
1707 *
1708 * @param chain_id
1709 * @param ei - Element index
1710 * @param fi - Frame index
1711 *
1712 * @return - Success : 0
1713 * Failure : -EINVAL
1714 */
1715int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1716{
1717 int lch;
1718 int *channels;
1719
1720 /* Check for input params */
1721 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1722 printk(KERN_ERR "Invalid chain id\n");
1723 return -EINVAL;
1724 }
1725
1726 /* Check if the chain exists */
1727 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1728 printk(KERN_ERR "Chain doesn't exists\n");
1729 return -EINVAL;
1730 }
1731 if ((!ei) || (!fi))
1732 return -EINVAL;
1733
1734 channels = dma_linked_lch[chain_id].linked_dmach_q;
1735
1736 /* Get the current channel */
1737 lch = channels[dma_linked_lch[chain_id].q_head];
1738
1739 *ei = p->dma_read(CCEN, lch);
1740 *fi = p->dma_read(CCFN, lch);
1741
1742 return 0;
1743}
1744EXPORT_SYMBOL(omap_get_dma_chain_index);
1745
1746/**
1747 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1748 * ongoing DMA in chain
1749 *
1750 * @param chain_id
1751 *
1752 * @return - Success : Destination position
1753 * Failure : -EINVAL
1754 */
1755int omap_get_dma_chain_dst_pos(int chain_id)
1756{
1757 int lch;
1758 int *channels;
1759
1760 /* Check for input params */
1761 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1762 printk(KERN_ERR "Invalid chain id\n");
1763 return -EINVAL;
1764 }
1765
1766 /* Check if the chain exists */
1767 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1768 printk(KERN_ERR "Chain doesn't exists\n");
1769 return -EINVAL;
1770 }
1771
1772 channels = dma_linked_lch[chain_id].linked_dmach_q;
1773
1774 /* Get the current channel */
1775 lch = channels[dma_linked_lch[chain_id].q_head];
1776
1777 return p->dma_read(CDAC, lch);
1778}
1779EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1780
1781/**
1782 * @brief omap_get_dma_chain_src_pos - Get the source position
1783 * of the ongoing DMA in chain
1784 * @param chain_id
1785 *
1786 * @return - Success : Destination position
1787 * Failure : -EINVAL
1788 */
1789int omap_get_dma_chain_src_pos(int chain_id)
1790{
1791 int lch;
1792 int *channels;
1793
1794 /* Check for input params */
1795 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1796 printk(KERN_ERR "Invalid chain id\n");
1797 return -EINVAL;
1798 }
1799
1800 /* Check if the chain exists */
1801 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1802 printk(KERN_ERR "Chain doesn't exists\n");
1803 return -EINVAL;
1804 }
1805
1806 channels = dma_linked_lch[chain_id].linked_dmach_q;
1807
1808 /* Get the current channel */
1809 lch = channels[dma_linked_lch[chain_id].q_head];
1810
1811 return p->dma_read(CSAC, lch);
1812}
1813EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1814#endif /* ifndef CONFIG_ARCH_OMAP1 */
1815
1816/*----------------------------------------------------------------------------*/ 1091/*----------------------------------------------------------------------------*/
1817 1092
1818#ifdef CONFIG_ARCH_OMAP1 1093#ifdef CONFIG_ARCH_OMAP1
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 3ec6e8e8d368..f5b00f41c4f6 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -499,7 +499,7 @@ void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
499 499
500 d->netdev = &orion_ge00.dev; 500 d->netdev = &orion_ge00.dev;
501 for (i = 0; i < d->nr_chips; i++) 501 for (i = 0; i < d->nr_chips; i++)
502 d->chip[i].mii_bus = &orion_ge00_shared.dev; 502 d->chip[i].host_dev = &orion_ge00_shared.dev;
503 orion_switch_device.dev.platform_data = d; 503 orion_switch_device.dev.platform_data = d;
504 504
505 platform_device_register(&orion_switch_device); 505 platform_device_register(&orion_switch_device);
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
index 3ea02903d75a..1f5ee17a10e8 100644
--- a/arch/arm/plat-pxa/ssp.c
+++ b/arch/arm/plat-pxa/ssp.c
@@ -258,6 +258,7 @@ static const struct platform_device_id ssp_id_table[] = {
258 { "pxa25x-ssp", PXA25x_SSP }, 258 { "pxa25x-ssp", PXA25x_SSP },
259 { "pxa25x-nssp", PXA25x_NSSP }, 259 { "pxa25x-nssp", PXA25x_NSSP },
260 { "pxa27x-ssp", PXA27x_SSP }, 260 { "pxa27x-ssp", PXA27x_SSP },
261 { "pxa3xx-ssp", PXA3xx_SSP },
261 { "pxa168-ssp", PXA168_SSP }, 262 { "pxa168-ssp", PXA168_SSP },
262 { "pxa910-ssp", PXA910_SSP }, 263 { "pxa910-ssp", PXA910_SSP },
263 { }, 264 { },
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 04:08:40 -0400