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-rw-r--r--arch/arm/Kconfig37
-rw-r--r--arch/arm/Kconfig.debug4
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/common/gic.c2
-rw-r--r--arch/arm/common/locomo.c84
-rw-r--r--arch/arm/common/sa1111.c30
-rw-r--r--arch/arm/common/sharpsl_pm.c22
-rw-r--r--arch/arm/common/vic.c8
-rw-r--r--arch/arm/configs/at91rm9200dk_defconfig1
-rw-r--r--arch/arm/configs/at91rm9200ek_defconfig1
-rw-r--r--arch/arm/configs/badge4_defconfig1
-rw-r--r--arch/arm/configs/cerfcube_defconfig1
-rw-r--r--arch/arm/configs/collie_defconfig1
-rw-r--r--arch/arm/configs/corgi_defconfig1
-rw-r--r--arch/arm/configs/csb337_defconfig1
-rw-r--r--arch/arm/configs/csb637_defconfig1
-rw-r--r--arch/arm/configs/ep93xx_defconfig2
-rw-r--r--arch/arm/configs/h7202_defconfig1
-rw-r--r--arch/arm/configs/hackkit_defconfig1
-rw-r--r--arch/arm/configs/integrator_defconfig1
-rw-r--r--arch/arm/configs/iop13xx_defconfig1134
-rw-r--r--arch/arm/configs/iop32x_defconfig1
-rw-r--r--arch/arm/configs/iop33x_defconfig1
-rw-r--r--arch/arm/configs/ixp2000_defconfig1
-rw-r--r--arch/arm/configs/ixp23xx_defconfig1
-rw-r--r--arch/arm/configs/ixp4xx_defconfig1
-rw-r--r--arch/arm/configs/jornada720_defconfig1
-rw-r--r--arch/arm/configs/kb9202_defconfig1
-rw-r--r--arch/arm/configs/lpd270_defconfig1
-rw-r--r--arch/arm/configs/lpd7a400_defconfig1
-rw-r--r--arch/arm/configs/lpd7a404_defconfig1
-rw-r--r--arch/arm/configs/lubbock_defconfig1
-rw-r--r--arch/arm/configs/mainstone_defconfig1
-rw-r--r--arch/arm/configs/mx1ads_defconfig1
-rw-r--r--arch/arm/configs/neponset_defconfig1
-rw-r--r--arch/arm/configs/netwinder_defconfig1
-rw-r--r--arch/arm/configs/netx_defconfig1
-rw-r--r--arch/arm/configs/onearm_defconfig1
-rw-r--r--arch/arm/configs/pleb_defconfig1
-rw-r--r--arch/arm/configs/pnx4008_defconfig1
-rw-r--r--arch/arm/configs/pxa255-idp_defconfig1
-rw-r--r--arch/arm/configs/realview-smp_defconfig1
-rw-r--r--arch/arm/configs/realview_defconfig1
-rw-r--r--arch/arm/configs/rpc_defconfig1
-rw-r--r--arch/arm/configs/s3c2410_defconfig1
-rw-r--r--arch/arm/configs/shark_defconfig1
-rw-r--r--arch/arm/configs/simpad_defconfig1
-rw-r--r--arch/arm/configs/spitz_defconfig1
-rw-r--r--arch/arm/configs/versatile_defconfig1
-rw-r--r--arch/arm/kernel/Makefile4
-rw-r--r--arch/arm/kernel/apm.c187
-rw-r--r--arch/arm/kernel/asm-offsets.c1
-rw-r--r--arch/arm/kernel/calls.S13
-rw-r--r--arch/arm/kernel/ecard.c10
-rw-r--r--arch/arm/kernel/entry-armv.S9
-rw-r--r--arch/arm/kernel/head-nommu.S1
-rw-r--r--arch/arm/kernel/head.S20
-rw-r--r--arch/arm/kernel/irq.c8
-rw-r--r--arch/arm/kernel/iwmmxt-notifier.c63
-rw-r--r--arch/arm/kernel/process.c61
-rw-r--r--arch/arm/kernel/setup.c17
-rw-r--r--arch/arm/kernel/signal.c2
-rw-r--r--arch/arm/kernel/traps.c7
-rw-r--r--arch/arm/kernel/xscale-cp0.c179
-rw-r--r--arch/arm/mach-aaec2000/core.c4
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c8
-rw-r--r--arch/arm/mach-at91rm9200/irq.c2
-rw-r--r--arch/arm/mach-clps711x/irq.c8
-rw-r--r--arch/arm/mach-clps7500/core.c28
-rw-r--r--arch/arm/mach-ebsa110/core.c4
-rw-r--r--arch/arm/mach-ep93xx/Kconfig12
-rw-r--r--arch/arm/mach-ep93xx/Makefile2
-rw-r--r--arch/arm/mach-ep93xx/adssphere.c91
-rw-r--r--arch/arm/mach-ep93xx/core.c6
-rw-r--r--arch/arm/mach-ep93xx/edb9302a.c91
-rw-r--r--arch/arm/mach-footbridge/common.c4
-rw-r--r--arch/arm/mach-footbridge/isa-irq.c10
-rw-r--r--arch/arm/mach-h720x/common.c22
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c6
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/cpufreq.c287
-rw-r--r--arch/arm/mach-imx/generic.c9
-rw-r--r--arch/arm/mach-imx/irq.c14
-rw-r--r--arch/arm/mach-imx/time.c86
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c8
-rw-r--r--arch/arm/mach-integrator/platsmp.c1
-rw-r--r--arch/arm/mach-iop13xx/Kconfig20
-rw-r--r--arch/arm/mach-iop13xx/Makefile12
-rw-r--r--arch/arm/mach-iop13xx/Makefile.boot3
-rw-r--r--arch/arm/mach-iop13xx/io.c93
-rw-r--r--arch/arm/mach-iop13xx/iq81340mc.c98
-rw-r--r--arch/arm/mach-iop13xx/iq81340sc.c100
-rw-r--r--arch/arm/mach-iop13xx/irq.c286
-rw-r--r--arch/arm/mach-iop13xx/pci.c1113
-rw-r--r--arch/arm/mach-iop13xx/setup.c406
-rw-r--r--arch/arm/mach-iop13xx/time.c102
-rw-r--r--arch/arm/mach-iop32x/irq.c2
-rw-r--r--arch/arm/mach-iop33x/irq.c2
-rw-r--r--arch/arm/mach-ixp2000/core.c20
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c8
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c8
-rw-r--r--arch/arm/mach-ixp2000/pci.c2
-rw-r--r--arch/arm/mach-ixp23xx/core.c16
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c16
-rw-r--r--arch/arm/mach-ixp23xx/pci.c2
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig2
-rw-r--r--arch/arm/mach-ixp4xx/common.c51
-rw-r--r--arch/arm/mach-l7200/core.c4
-rw-r--r--arch/arm/mach-lh7a40x/Kconfig2
-rw-r--r--arch/arm/mach-lh7a40x/arch-kev7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/arch-lpd7a40x.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-kev7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a404.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lpd7a40x.c4
-rw-r--r--arch/arm/mach-netx/generic.c6
-rw-r--r--arch/arm/mach-netx/time.c42
-rw-r--r--arch/arm/mach-omap1/board-h3.c3
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c6
-rw-r--r--arch/arm/mach-omap1/devices.c2
-rw-r--r--arch/arm/mach-omap1/fpga.c6
-rw-r--r--arch/arm/mach-omap1/irq.c2
-rw-r--r--arch/arm/mach-omap1/leds-osk.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c3
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-pnx4008/Makefile2
-rw-r--r--arch/arm/mach-pnx4008/i2c.c167
-rw-r--r--arch/arm/mach-pnx4008/irq.c10
-rw-r--r--arch/arm/mach-pxa/Kconfig8
-rw-r--r--arch/arm/mach-pxa/akita-ioexp.c6
-rw-r--r--arch/arm/mach-pxa/generic.c60
-rw-r--r--arch/arm/mach-pxa/irq.c10
-rw-r--r--arch/arm/mach-pxa/lpd270.c4
-rw-r--r--arch/arm/mach-pxa/lubbock.c4
-rw-r--r--arch/arm/mach-pxa/mainstone.c4
-rw-r--r--arch/arm/mach-pxa/pm.c3
-rw-r--r--arch/arm/mach-pxa/time.c52
-rw-r--r--arch/arm/mach-pxa/trizeps4.c5
-rw-r--r--arch/arm/mach-realview/core.c13
-rw-r--r--arch/arm/mach-realview/core.h1
-rw-r--r--arch/arm/mach-realview/realview_eb.c1
-rw-r--r--arch/arm/mach-rpc/irq.c14
-rw-r--r--arch/arm/mach-s3c2410/Kconfig10
-rw-r--r--arch/arm/mach-s3c2410/Makefile1
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c8
-rw-r--r--arch/arm/mach-s3c2410/dma.c4
-rw-r--r--arch/arm/mach-s3c2410/irq.c63
-rw-r--r--arch/arm/mach-s3c2410/irq.h2
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c8
-rw-r--r--arch/arm/mach-s3c2410/mach-osiris.c9
-rw-r--r--arch/arm/mach-s3c2410/mach-rx3715.c3
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c50
-rw-r--r--arch/arm/mach-s3c2410/pm-h1940.S33
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-pm.c30
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-irq.c4
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c10
-rw-r--r--arch/arm/mach-s3c2410/s3c244x-irq.c12
-rw-r--r--arch/arm/mach-sa1100/generic.c15
-rw-r--r--arch/arm/mach-sa1100/h3600.c6
-rw-r--r--arch/arm/mach-sa1100/irq.c8
-rw-r--r--arch/arm/mach-sa1100/jornada720.c229
-rw-r--r--arch/arm/mach-sa1100/neponset.c8
-rw-r--r--arch/arm/mach-sa1100/time.c7
-rw-r--r--arch/arm/mach-shark/irq.c2
-rw-r--r--arch/arm/mach-versatile/core.c32
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c18
-rw-r--r--arch/arm/mm/Kconfig6
-rw-r--r--arch/arm/mm/consistent.c2
-rw-r--r--arch/arm/mm/copypage-v4mc.c2
-rw-r--r--arch/arm/mm/copypage-v6.c6
-rw-r--r--arch/arm/mm/copypage-xscale.c2
-rw-r--r--arch/arm/mm/fault-armv.c2
-rw-r--r--arch/arm/mm/fault.c2
-rw-r--r--arch/arm/mm/flush.c2
-rw-r--r--arch/arm/mm/ioremap.c100
-rw-r--r--arch/arm/mm/mm.h5
-rw-r--r--arch/arm/mm/mmu.c17
-rw-r--r--arch/arm/mm/nommu.c4
-rw-r--r--arch/arm/mm/pgd.c2
-rw-r--r--arch/arm/mm/proc-arm1020.S6
-rw-r--r--arch/arm/mm/proc-arm1020e.S6
-rw-r--r--arch/arm/mm/proc-arm1022.S8
-rw-r--r--arch/arm/mm/proc-arm1026.S8
-rw-r--r--arch/arm/mm/proc-arm6_7.S12
-rw-r--r--arch/arm/mm/proc-arm720.S8
-rw-r--r--arch/arm/mm/proc-arm740.S2
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S2
-rw-r--r--arch/arm/mm/proc-arm920.S8
-rw-r--r--arch/arm/mm/proc-arm922.S8
-rw-r--r--arch/arm/mm/proc-arm925.S8
-rw-r--r--arch/arm/mm/proc-arm926.S10
-rw-r--r--arch/arm/mm/proc-arm940.S2
-rw-r--r--arch/arm/mm/proc-arm946.S2
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S2
-rw-r--r--arch/arm/mm/proc-sa110.S8
-rw-r--r--arch/arm/mm/proc-sa1100.S8
-rw-r--r--arch/arm/mm/proc-syms.c2
-rw-r--r--arch/arm/mm/proc-v6.S41
-rw-r--r--arch/arm/mm/proc-xsc3.S19
-rw-r--r--arch/arm/mm/proc-xscale.S17
-rw-r--r--arch/arm/plat-omap/gpio.c8
-rw-r--r--arch/arm/tools/mach-types58
-rw-r--r--arch/arm/vfp/vfpmodule.c26
204 files changed, 5579 insertions, 910 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 43bd17bfc381..6783c2e5512d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -74,6 +74,14 @@ config RWSEM_GENERIC_SPINLOCK
74config RWSEM_XCHGADD_ALGORITHM 74config RWSEM_XCHGADD_ALGORITHM
75 bool 75 bool
76 76
77config ARCH_HAS_ILOG2_U32
78 bool
79 default n
80
81config ARCH_HAS_ILOG2_U64
82 bool
83 default n
84
77config GENERIC_HWEIGHT 85config GENERIC_HWEIGHT
78 bool 86 bool
79 default y 87 default y
@@ -223,6 +231,12 @@ config ARCH_IOP33X
223 help 231 help
224 Support for Intel's IOP33X (XScale) family of processors. 232 Support for Intel's IOP33X (XScale) family of processors.
225 233
234config ARCH_IOP13XX
235 bool "IOP13xx-based"
236 select PCI
237 help
238 Support for Intel's IOP13XX (XScale) family of processors.
239
226config ARCH_IXP4XX 240config ARCH_IXP4XX
227 bool "IXP4xx-based" 241 bool "IXP4xx-based"
228 depends on MMU 242 depends on MMU
@@ -331,6 +345,8 @@ source "arch/arm/mach-iop32x/Kconfig"
331 345
332source "arch/arm/mach-iop33x/Kconfig" 346source "arch/arm/mach-iop33x/Kconfig"
333 347
348source "arch/arm/mach-iop13xx/Kconfig"
349
334source "arch/arm/mach-ixp4xx/Kconfig" 350source "arch/arm/mach-ixp4xx/Kconfig"
335 351
336source "arch/arm/mach-ixp2000/Kconfig" 352source "arch/arm/mach-ixp2000/Kconfig"
@@ -374,6 +390,14 @@ config PLAT_IOP
374 390
375source arch/arm/mm/Kconfig 391source arch/arm/mm/Kconfig
376 392
393config IWMMXT
394 bool "Enable iWMMXt support"
395 depends CPU_XSCALE || CPU_XSC3
396 default y if PXA27x
397 help
398 Enable support for iWMMXt context switching at run time if
399 running on a CPU that supports it.
400
377# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER 401# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
378config XSCALE_PMU 402config XSCALE_PMU
379 bool 403 bool
@@ -716,7 +740,7 @@ config XIP_PHYS_ADDR
716 740
717endmenu 741endmenu
718 742
719if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP) 743if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX )
720 744
721menu "CPU Frequency scaling" 745menu "CPU Frequency scaling"
722 746
@@ -743,6 +767,15 @@ config CPU_FREQ_INTEGRATOR
743 767
744 If in doubt, say Y. 768 If in doubt, say Y.
745 769
770config CPU_FREQ_IMX
771 tristate "CPUfreq driver for i.MX CPUs"
772 depends on ARCH_IMX && CPU_FREQ
773 default n
774 help
775 This enables the CPUfreq driver for i.MX CPUs.
776
777 If in doubt, say N.
778
746endmenu 779endmenu
747 780
748endif 781endif
@@ -921,6 +954,8 @@ source "drivers/video/Kconfig"
921 954
922source "sound/Kconfig" 955source "sound/Kconfig"
923 956
957source "drivers/hid/Kconfig"
958
924source "drivers/usb/Kconfig" 959source "drivers/usb/Kconfig"
925 960
926source "drivers/mmc/Kconfig" 961source "drivers/mmc/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d22f38b957db..40c5eb1f55c7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -32,10 +32,6 @@ config DEBUG_USER
32 8 - SIGSEGV faults 32 8 - SIGSEGV faults
33 16 - SIGBUS faults 33 16 - SIGBUS faults
34 34
35config DEBUG_WAITQ
36 bool "Wait queue debugging"
37 depends on DEBUG_KERNEL
38
39config DEBUG_ERRORS 35config DEBUG_ERRORS
40 bool "Verbose kernel error messages" 36 bool "Verbose kernel error messages"
41 depends on DEBUG_KERNEL 37 depends on DEBUG_KERNEL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f4f8bf36071..000f1100b553 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,6 +15,8 @@ CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
15OBJCOPYFLAGS :=-O binary -R .note -R .comment -S 15OBJCOPYFLAGS :=-O binary -R .note -R .comment -S
16GZFLAGS :=-9 16GZFLAGS :=-9
17#CFLAGS +=-pipe 17#CFLAGS +=-pipe
18# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
19CFLAGS +=$(call cc-option,-marm,)
18 20
19# Do not use arch/arm/defconfig - it's always outdated. 21# Do not use arch/arm/defconfig - it's always outdated.
20# Select a platform tht is kept up-to-date 22# Select a platform tht is kept up-to-date
@@ -108,6 +110,7 @@ endif
108 machine-$(CONFIG_ARCH_CLPS711X) := clps711x 110 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
109 machine-$(CONFIG_ARCH_IOP32X) := iop32x 111 machine-$(CONFIG_ARCH_IOP32X) := iop32x
110 machine-$(CONFIG_ARCH_IOP33X) := iop33x 112 machine-$(CONFIG_ARCH_IOP33X) := iop33x
113 machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
111 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 114 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
112 machine-$(CONFIG_ARCH_IXP2000) := ixp2000 115 machine-$(CONFIG_ARCH_IXP2000) := ixp2000
113 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx 116 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f3e020f2227f..09b9d1b6844c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -160,7 +160,7 @@ void __init gic_dist_init(void __iomem *base)
160 */ 160 */
161 for (i = 29; i < max_irq; i++) { 161 for (i = 29; i < max_irq; i++) {
162 set_irq_chip(i, &gic_chip); 162 set_irq_chip(i, &gic_chip);
163 set_irq_handler(i, do_level_IRQ); 163 set_irq_handler(i, handle_level_irq);
164 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 164 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
165 } 165 }
166 166
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 80a72c75214f..cfe6f4650bc9 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -163,11 +163,11 @@ static struct locomo_dev_info locomo_devices[] = {
163#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT) 163#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT)
164#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR) 164#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR)
165 165
166static void locomo_handler(unsigned int irq, struct irqdesc *desc) 166static void locomo_handler(unsigned int irq, struct irq_desc *desc)
167{ 167{
168 int req, i; 168 int req, i;
169 struct irqdesc *d; 169 struct irq_desc *d;
170 void __iomem *mapbase = get_irq_chipdata(irq); 170 void __iomem *mapbase = get_irq_chip_data(irq);
171 171
172 /* Acknowledge the parent IRQ */ 172 /* Acknowledge the parent IRQ */
173 desc->chip->ack(irq); 173 desc->chip->ack(irq);
@@ -194,7 +194,7 @@ static void locomo_ack_irq(unsigned int irq)
194 194
195static void locomo_mask_irq(unsigned int irq) 195static void locomo_mask_irq(unsigned int irq)
196{ 196{
197 void __iomem *mapbase = get_irq_chipdata(irq); 197 void __iomem *mapbase = get_irq_chip_data(irq);
198 unsigned int r; 198 unsigned int r;
199 r = locomo_readl(mapbase + LOCOMO_ICR); 199 r = locomo_readl(mapbase + LOCOMO_ICR);
200 r &= ~(0x0010 << (irq - LOCOMO_IRQ_START)); 200 r &= ~(0x0010 << (irq - LOCOMO_IRQ_START));
@@ -203,7 +203,7 @@ static void locomo_mask_irq(unsigned int irq)
203 203
204static void locomo_unmask_irq(unsigned int irq) 204static void locomo_unmask_irq(unsigned int irq)
205{ 205{
206 void __iomem *mapbase = get_irq_chipdata(irq); 206 void __iomem *mapbase = get_irq_chip_data(irq);
207 unsigned int r; 207 unsigned int r;
208 r = locomo_readl(mapbase + LOCOMO_ICR); 208 r = locomo_readl(mapbase + LOCOMO_ICR);
209 r |= (0x0010 << (irq - LOCOMO_IRQ_START)); 209 r |= (0x0010 << (irq - LOCOMO_IRQ_START));
@@ -217,10 +217,10 @@ static struct irq_chip locomo_chip = {
217 .unmask = locomo_unmask_irq, 217 .unmask = locomo_unmask_irq,
218}; 218};
219 219
220static void locomo_key_handler(unsigned int irq, struct irqdesc *desc) 220static void locomo_key_handler(unsigned int irq, struct irq_desc *desc)
221{ 221{
222 struct irqdesc *d; 222 struct irq_desc *d;
223 void __iomem *mapbase = get_irq_chipdata(irq); 223 void __iomem *mapbase = get_irq_chip_data(irq);
224 224
225 if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { 225 if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
226 d = irq_desc + LOCOMO_IRQ_KEY_START; 226 d = irq_desc + LOCOMO_IRQ_KEY_START;
@@ -230,7 +230,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
230 230
231static void locomo_key_ack_irq(unsigned int irq) 231static void locomo_key_ack_irq(unsigned int irq)
232{ 232{
233 void __iomem *mapbase = get_irq_chipdata(irq); 233 void __iomem *mapbase = get_irq_chip_data(irq);
234 unsigned int r; 234 unsigned int r;
235 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 235 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
236 r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START)); 236 r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START));
@@ -239,7 +239,7 @@ static void locomo_key_ack_irq(unsigned int irq)
239 239
240static void locomo_key_mask_irq(unsigned int irq) 240static void locomo_key_mask_irq(unsigned int irq)
241{ 241{
242 void __iomem *mapbase = get_irq_chipdata(irq); 242 void __iomem *mapbase = get_irq_chip_data(irq);
243 unsigned int r; 243 unsigned int r;
244 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 244 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
245 r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START)); 245 r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -248,7 +248,7 @@ static void locomo_key_mask_irq(unsigned int irq)
248 248
249static void locomo_key_unmask_irq(unsigned int irq) 249static void locomo_key_unmask_irq(unsigned int irq)
250{ 250{
251 void __iomem *mapbase = get_irq_chipdata(irq); 251 void __iomem *mapbase = get_irq_chip_data(irq);
252 unsigned int r; 252 unsigned int r;
253 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 253 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
254 r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START)); 254 r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -262,11 +262,11 @@ static struct irq_chip locomo_key_chip = {
262 .unmask = locomo_key_unmask_irq, 262 .unmask = locomo_key_unmask_irq,
263}; 263};
264 264
265static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc) 265static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
266{ 266{
267 int req, i; 267 int req, i;
268 struct irqdesc *d; 268 struct irq_desc *d;
269 void __iomem *mapbase = get_irq_chipdata(irq); 269 void __iomem *mapbase = get_irq_chip_data(irq);
270 270
271 req = locomo_readl(mapbase + LOCOMO_GIR) & 271 req = locomo_readl(mapbase + LOCOMO_GIR) &
272 locomo_readl(mapbase + LOCOMO_GPD) & 272 locomo_readl(mapbase + LOCOMO_GPD) &
@@ -285,7 +285,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
285 285
286static void locomo_gpio_ack_irq(unsigned int irq) 286static void locomo_gpio_ack_irq(unsigned int irq)
287{ 287{
288 void __iomem *mapbase = get_irq_chipdata(irq); 288 void __iomem *mapbase = get_irq_chip_data(irq);
289 unsigned int r; 289 unsigned int r;
290 r = locomo_readl(mapbase + LOCOMO_GWE); 290 r = locomo_readl(mapbase + LOCOMO_GWE);
291 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 291 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -302,7 +302,7 @@ static void locomo_gpio_ack_irq(unsigned int irq)
302 302
303static void locomo_gpio_mask_irq(unsigned int irq) 303static void locomo_gpio_mask_irq(unsigned int irq)
304{ 304{
305 void __iomem *mapbase = get_irq_chipdata(irq); 305 void __iomem *mapbase = get_irq_chip_data(irq);
306 unsigned int r; 306 unsigned int r;
307 r = locomo_readl(mapbase + LOCOMO_GIE); 307 r = locomo_readl(mapbase + LOCOMO_GIE);
308 r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 308 r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -311,7 +311,7 @@ static void locomo_gpio_mask_irq(unsigned int irq)
311 311
312static void locomo_gpio_unmask_irq(unsigned int irq) 312static void locomo_gpio_unmask_irq(unsigned int irq)
313{ 313{
314 void __iomem *mapbase = get_irq_chipdata(irq); 314 void __iomem *mapbase = get_irq_chip_data(irq);
315 unsigned int r; 315 unsigned int r;
316 r = locomo_readl(mapbase + LOCOMO_GIE); 316 r = locomo_readl(mapbase + LOCOMO_GIE);
317 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 317 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -325,10 +325,10 @@ static struct irq_chip locomo_gpio_chip = {
325 .unmask = locomo_gpio_unmask_irq, 325 .unmask = locomo_gpio_unmask_irq,
326}; 326};
327 327
328static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc) 328static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
329{ 329{
330 struct irqdesc *d; 330 struct irq_desc *d;
331 void __iomem *mapbase = get_irq_chipdata(irq); 331 void __iomem *mapbase = get_irq_chip_data(irq);
332 332
333 if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) { 333 if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
334 d = irq_desc + LOCOMO_IRQ_LT_START; 334 d = irq_desc + LOCOMO_IRQ_LT_START;
@@ -338,7 +338,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
338 338
339static void locomo_lt_ack_irq(unsigned int irq) 339static void locomo_lt_ack_irq(unsigned int irq)
340{ 340{
341 void __iomem *mapbase = get_irq_chipdata(irq); 341 void __iomem *mapbase = get_irq_chip_data(irq);
342 unsigned int r; 342 unsigned int r;
343 r = locomo_readl(mapbase + LOCOMO_LTINT); 343 r = locomo_readl(mapbase + LOCOMO_LTINT);
344 r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START)); 344 r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START));
@@ -347,7 +347,7 @@ static void locomo_lt_ack_irq(unsigned int irq)
347 347
348static void locomo_lt_mask_irq(unsigned int irq) 348static void locomo_lt_mask_irq(unsigned int irq)
349{ 349{
350 void __iomem *mapbase = get_irq_chipdata(irq); 350 void __iomem *mapbase = get_irq_chip_data(irq);
351 unsigned int r; 351 unsigned int r;
352 r = locomo_readl(mapbase + LOCOMO_LTINT); 352 r = locomo_readl(mapbase + LOCOMO_LTINT);
353 r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START)); 353 r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -356,7 +356,7 @@ static void locomo_lt_mask_irq(unsigned int irq)
356 356
357static void locomo_lt_unmask_irq(unsigned int irq) 357static void locomo_lt_unmask_irq(unsigned int irq)
358{ 358{
359 void __iomem *mapbase = get_irq_chipdata(irq); 359 void __iomem *mapbase = get_irq_chip_data(irq);
360 unsigned int r; 360 unsigned int r;
361 r = locomo_readl(mapbase + LOCOMO_LTINT); 361 r = locomo_readl(mapbase + LOCOMO_LTINT);
362 r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START)); 362 r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -370,11 +370,11 @@ static struct irq_chip locomo_lt_chip = {
370 .unmask = locomo_lt_unmask_irq, 370 .unmask = locomo_lt_unmask_irq,
371}; 371};
372 372
373static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc) 373static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc)
374{ 374{
375 int req, i; 375 int req, i;
376 struct irqdesc *d; 376 struct irq_desc *d;
377 void __iomem *mapbase = get_irq_chipdata(irq); 377 void __iomem *mapbase = get_irq_chip_data(irq);
378 378
379 req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F; 379 req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
380 if (req) { 380 if (req) {
@@ -391,7 +391,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
391 391
392static void locomo_spi_ack_irq(unsigned int irq) 392static void locomo_spi_ack_irq(unsigned int irq)
393{ 393{
394 void __iomem *mapbase = get_irq_chipdata(irq); 394 void __iomem *mapbase = get_irq_chip_data(irq);
395 unsigned int r; 395 unsigned int r;
396 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE); 396 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
397 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 397 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -408,7 +408,7 @@ static void locomo_spi_ack_irq(unsigned int irq)
408 408
409static void locomo_spi_mask_irq(unsigned int irq) 409static void locomo_spi_mask_irq(unsigned int irq)
410{ 410{
411 void __iomem *mapbase = get_irq_chipdata(irq); 411 void __iomem *mapbase = get_irq_chip_data(irq);
412 unsigned int r; 412 unsigned int r;
413 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); 413 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
414 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 414 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -417,7 +417,7 @@ static void locomo_spi_mask_irq(unsigned int irq)
417 417
418static void locomo_spi_unmask_irq(unsigned int irq) 418static void locomo_spi_unmask_irq(unsigned int irq)
419{ 419{
420 void __iomem *mapbase = get_irq_chipdata(irq); 420 void __iomem *mapbase = get_irq_chip_data(irq);
421 unsigned int r; 421 unsigned int r;
422 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); 422 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
423 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 423 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -440,55 +440,55 @@ static void locomo_setup_irq(struct locomo *lchip)
440 * Install handler for IRQ_LOCOMO_HW. 440 * Install handler for IRQ_LOCOMO_HW.
441 */ 441 */
442 set_irq_type(lchip->irq, IRQT_FALLING); 442 set_irq_type(lchip->irq, IRQT_FALLING);
443 set_irq_chipdata(lchip->irq, irqbase); 443 set_irq_chip_data(lchip->irq, irqbase);
444 set_irq_chained_handler(lchip->irq, locomo_handler); 444 set_irq_chained_handler(lchip->irq, locomo_handler);
445 445
446 /* Install handlers for IRQ_LOCOMO_*_BASE */ 446 /* Install handlers for IRQ_LOCOMO_*_BASE */
447 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip); 447 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip);
448 set_irq_chipdata(IRQ_LOCOMO_KEY_BASE, irqbase); 448 set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase);
449 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler); 449 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler);
450 set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE); 450 set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE);
451 451
452 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip); 452 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip);
453 set_irq_chipdata(IRQ_LOCOMO_GPIO_BASE, irqbase); 453 set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase);
454 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler); 454 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler);
455 set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE); 455 set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE);
456 456
457 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip); 457 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip);
458 set_irq_chipdata(IRQ_LOCOMO_LT_BASE, irqbase); 458 set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase);
459 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler); 459 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler);
460 set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE); 460 set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE);
461 461
462 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip); 462 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip);
463 set_irq_chipdata(IRQ_LOCOMO_SPI_BASE, irqbase); 463 set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase);
464 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler); 464 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler);
465 set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE); 465 set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE);
466 466
467 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */ 467 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */
468 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip); 468 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip);
469 set_irq_chipdata(LOCOMO_IRQ_KEY_START, irqbase); 469 set_irq_chip_data(LOCOMO_IRQ_KEY_START, irqbase);
470 set_irq_handler(LOCOMO_IRQ_KEY_START, do_edge_IRQ); 470 set_irq_handler(LOCOMO_IRQ_KEY_START, handle_edge_irq);
471 set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE); 471 set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE);
472 472
473 /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */ 473 /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */
474 for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) { 474 for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) {
475 set_irq_chip(irq, &locomo_gpio_chip); 475 set_irq_chip(irq, &locomo_gpio_chip);
476 set_irq_chipdata(irq, irqbase); 476 set_irq_chip_data(irq, irqbase);
477 set_irq_handler(irq, do_edge_IRQ); 477 set_irq_handler(irq, handle_edge_irq);
478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
479 } 479 }
480 480
481 /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */ 481 /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */
482 set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip); 482 set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip);
483 set_irq_chipdata(LOCOMO_IRQ_LT_START, irqbase); 483 set_irq_chip_data(LOCOMO_IRQ_LT_START, irqbase);
484 set_irq_handler(LOCOMO_IRQ_LT_START, do_edge_IRQ); 484 set_irq_handler(LOCOMO_IRQ_LT_START, handle_edge_irq);
485 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE); 485 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE);
486 486
487 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */ 487 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */
488 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) { 488 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) {
489 set_irq_chip(irq, &locomo_spi_chip); 489 set_irq_chip(irq, &locomo_spi_chip);
490 set_irq_chipdata(irq, irqbase); 490 set_irq_chip_data(irq, irqbase);
491 set_irq_handler(irq, do_edge_IRQ); 491 set_irq_handler(irq, handle_edge_irq);
492 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 492 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
493 } 493 }
494} 494}
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index d5f72010a6f3..fe3f05901a23 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -147,7 +147,7 @@ void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *ho
147 * will call us again if there are more interrupts to process. 147 * will call us again if there are more interrupts to process.
148 */ 148 */
149static void 149static void
150sa1111_irq_handler(unsigned int irq, struct irqdesc *desc) 150sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
151{ 151{
152 unsigned int stat0, stat1, i; 152 unsigned int stat0, stat1, i;
153 void __iomem *base = get_irq_data(irq); 153 void __iomem *base = get_irq_data(irq);
@@ -187,7 +187,7 @@ static void sa1111_ack_irq(unsigned int irq)
187 187
188static void sa1111_mask_lowirq(unsigned int irq) 188static void sa1111_mask_lowirq(unsigned int irq)
189{ 189{
190 void __iomem *mapbase = get_irq_chipdata(irq); 190 void __iomem *mapbase = get_irq_chip_data(irq);
191 unsigned long ie0; 191 unsigned long ie0;
192 192
193 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 193 ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -197,7 +197,7 @@ static void sa1111_mask_lowirq(unsigned int irq)
197 197
198static void sa1111_unmask_lowirq(unsigned int irq) 198static void sa1111_unmask_lowirq(unsigned int irq)
199{ 199{
200 void __iomem *mapbase = get_irq_chipdata(irq); 200 void __iomem *mapbase = get_irq_chip_data(irq);
201 unsigned long ie0; 201 unsigned long ie0;
202 202
203 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 203 ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -215,7 +215,7 @@ static void sa1111_unmask_lowirq(unsigned int irq)
215static int sa1111_retrigger_lowirq(unsigned int irq) 215static int sa1111_retrigger_lowirq(unsigned int irq)
216{ 216{
217 unsigned int mask = SA1111_IRQMASK_LO(irq); 217 unsigned int mask = SA1111_IRQMASK_LO(irq);
218 void __iomem *mapbase = get_irq_chipdata(irq); 218 void __iomem *mapbase = get_irq_chip_data(irq);
219 unsigned long ip0; 219 unsigned long ip0;
220 int i; 220 int i;
221 221
@@ -236,7 +236,7 @@ static int sa1111_retrigger_lowirq(unsigned int irq)
236static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) 236static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
237{ 237{
238 unsigned int mask = SA1111_IRQMASK_LO(irq); 238 unsigned int mask = SA1111_IRQMASK_LO(irq);
239 void __iomem *mapbase = get_irq_chipdata(irq); 239 void __iomem *mapbase = get_irq_chip_data(irq);
240 unsigned long ip0; 240 unsigned long ip0;
241 241
242 if (flags == IRQT_PROBE) 242 if (flags == IRQT_PROBE)
@@ -259,7 +259,7 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
259static int sa1111_wake_lowirq(unsigned int irq, unsigned int on) 259static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
260{ 260{
261 unsigned int mask = SA1111_IRQMASK_LO(irq); 261 unsigned int mask = SA1111_IRQMASK_LO(irq);
262 void __iomem *mapbase = get_irq_chipdata(irq); 262 void __iomem *mapbase = get_irq_chip_data(irq);
263 unsigned long we0; 263 unsigned long we0;
264 264
265 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); 265 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0);
@@ -284,7 +284,7 @@ static struct irq_chip sa1111_low_chip = {
284 284
285static void sa1111_mask_highirq(unsigned int irq) 285static void sa1111_mask_highirq(unsigned int irq)
286{ 286{
287 void __iomem *mapbase = get_irq_chipdata(irq); 287 void __iomem *mapbase = get_irq_chip_data(irq);
288 unsigned long ie1; 288 unsigned long ie1;
289 289
290 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 290 ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -294,7 +294,7 @@ static void sa1111_mask_highirq(unsigned int irq)
294 294
295static void sa1111_unmask_highirq(unsigned int irq) 295static void sa1111_unmask_highirq(unsigned int irq)
296{ 296{
297 void __iomem *mapbase = get_irq_chipdata(irq); 297 void __iomem *mapbase = get_irq_chip_data(irq);
298 unsigned long ie1; 298 unsigned long ie1;
299 299
300 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 300 ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -312,7 +312,7 @@ static void sa1111_unmask_highirq(unsigned int irq)
312static int sa1111_retrigger_highirq(unsigned int irq) 312static int sa1111_retrigger_highirq(unsigned int irq)
313{ 313{
314 unsigned int mask = SA1111_IRQMASK_HI(irq); 314 unsigned int mask = SA1111_IRQMASK_HI(irq);
315 void __iomem *mapbase = get_irq_chipdata(irq); 315 void __iomem *mapbase = get_irq_chip_data(irq);
316 unsigned long ip1; 316 unsigned long ip1;
317 int i; 317 int i;
318 318
@@ -333,7 +333,7 @@ static int sa1111_retrigger_highirq(unsigned int irq)
333static int sa1111_type_highirq(unsigned int irq, unsigned int flags) 333static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
334{ 334{
335 unsigned int mask = SA1111_IRQMASK_HI(irq); 335 unsigned int mask = SA1111_IRQMASK_HI(irq);
336 void __iomem *mapbase = get_irq_chipdata(irq); 336 void __iomem *mapbase = get_irq_chip_data(irq);
337 unsigned long ip1; 337 unsigned long ip1;
338 338
339 if (flags == IRQT_PROBE) 339 if (flags == IRQT_PROBE)
@@ -356,7 +356,7 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
356static int sa1111_wake_highirq(unsigned int irq, unsigned int on) 356static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
357{ 357{
358 unsigned int mask = SA1111_IRQMASK_HI(irq); 358 unsigned int mask = SA1111_IRQMASK_HI(irq);
359 void __iomem *mapbase = get_irq_chipdata(irq); 359 void __iomem *mapbase = get_irq_chip_data(irq);
360 unsigned long we1; 360 unsigned long we1;
361 361
362 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); 362 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1);
@@ -410,15 +410,15 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
410 410
411 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { 411 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
412 set_irq_chip(irq, &sa1111_low_chip); 412 set_irq_chip(irq, &sa1111_low_chip);
413 set_irq_chipdata(irq, irqbase); 413 set_irq_chip_data(irq, irqbase);
414 set_irq_handler(irq, do_edge_IRQ); 414 set_irq_handler(irq, handle_edge_irq);
415 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 415 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
416 } 416 }
417 417
418 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { 418 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
419 set_irq_chip(irq, &sa1111_high_chip); 419 set_irq_chip(irq, &sa1111_high_chip);
420 set_irq_chipdata(irq, irqbase); 420 set_irq_chip_data(irq, irqbase);
421 set_irq_handler(irq, do_edge_IRQ); 421 set_irq_handler(irq, handle_edge_irq);
422 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 422 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
423 } 423 }
424 424
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index 605dedf96790..b3599743093b 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -60,16 +60,16 @@ static int sharpsl_ac_check(void);
60static int sharpsl_fatal_check(void); 60static int sharpsl_fatal_check(void);
61static int sharpsl_average_value(int ad); 61static int sharpsl_average_value(int ad);
62static void sharpsl_average_clear(void); 62static void sharpsl_average_clear(void);
63static void sharpsl_charge_toggle(void *private_); 63static void sharpsl_charge_toggle(struct work_struct *private_);
64static void sharpsl_battery_thread(void *private_); 64static void sharpsl_battery_thread(struct work_struct *private_);
65 65
66 66
67/* 67/*
68 * Variables 68 * Variables
69 */ 69 */
70struct sharpsl_pm_status sharpsl_pm; 70struct sharpsl_pm_status sharpsl_pm;
71DECLARE_WORK(toggle_charger, sharpsl_charge_toggle, NULL); 71DECLARE_DELAYED_WORK(toggle_charger, sharpsl_charge_toggle);
72DECLARE_WORK(sharpsl_bat, sharpsl_battery_thread, NULL); 72DECLARE_DELAYED_WORK(sharpsl_bat, sharpsl_battery_thread);
73DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger); 73DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger);
74 74
75 75
@@ -116,7 +116,7 @@ void sharpsl_battery_kick(void)
116EXPORT_SYMBOL(sharpsl_battery_kick); 116EXPORT_SYMBOL(sharpsl_battery_kick);
117 117
118 118
119static void sharpsl_battery_thread(void *private_) 119static void sharpsl_battery_thread(struct work_struct *private_)
120{ 120{
121 int voltage, percent, apm_status, i = 0; 121 int voltage, percent, apm_status, i = 0;
122 122
@@ -128,7 +128,7 @@ static void sharpsl_battery_thread(void *private_)
128 /* Corgi cannot confirm when battery fully charged so periodically kick! */ 128 /* Corgi cannot confirm when battery fully charged so periodically kick! */
129 if (!sharpsl_pm.machinfo->batfull_irq && (sharpsl_pm.charge_mode == CHRG_ON) 129 if (!sharpsl_pm.machinfo->batfull_irq && (sharpsl_pm.charge_mode == CHRG_ON)
130 && time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_ON_TIME_INTERVAL)) 130 && time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_ON_TIME_INTERVAL))
131 schedule_work(&toggle_charger); 131 schedule_delayed_work(&toggle_charger, 0);
132 132
133 while(1) { 133 while(1) {
134 voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); 134 voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
@@ -212,7 +212,7 @@ static void sharpsl_charge_off(void)
212 sharpsl_pm_led(SHARPSL_LED_OFF); 212 sharpsl_pm_led(SHARPSL_LED_OFF);
213 sharpsl_pm.charge_mode = CHRG_OFF; 213 sharpsl_pm.charge_mode = CHRG_OFF;
214 214
215 schedule_work(&sharpsl_bat); 215 schedule_delayed_work(&sharpsl_bat, 0);
216} 216}
217 217
218static void sharpsl_charge_error(void) 218static void sharpsl_charge_error(void)
@@ -222,7 +222,7 @@ static void sharpsl_charge_error(void)
222 sharpsl_pm.charge_mode = CHRG_ERROR; 222 sharpsl_pm.charge_mode = CHRG_ERROR;
223} 223}
224 224
225static void sharpsl_charge_toggle(void *private_) 225static void sharpsl_charge_toggle(struct work_struct *private_)
226{ 226{
227 dev_dbg(sharpsl_pm.dev, "Toogling Charger at time: %lx\n", jiffies); 227 dev_dbg(sharpsl_pm.dev, "Toogling Charger at time: %lx\n", jiffies);
228 228
@@ -254,7 +254,7 @@ static void sharpsl_ac_timer(unsigned long data)
254 else if (sharpsl_pm.charge_mode == CHRG_ON) 254 else if (sharpsl_pm.charge_mode == CHRG_ON)
255 sharpsl_charge_off(); 255 sharpsl_charge_off();
256 256
257 schedule_work(&sharpsl_bat); 257 schedule_delayed_work(&sharpsl_bat, 0);
258} 258}
259 259
260 260
@@ -279,10 +279,10 @@ static void sharpsl_chrg_full_timer(unsigned long data)
279 sharpsl_charge_off(); 279 sharpsl_charge_off();
280 } else if (sharpsl_pm.full_count < 2) { 280 } else if (sharpsl_pm.full_count < 2) {
281 dev_dbg(sharpsl_pm.dev, "Charge Full: Count too low\n"); 281 dev_dbg(sharpsl_pm.dev, "Charge Full: Count too low\n");
282 schedule_work(&toggle_charger); 282 schedule_delayed_work(&toggle_charger, 0);
283 } else if (time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_FINISH_TIME)) { 283 } else if (time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_FINISH_TIME)) {
284 dev_dbg(sharpsl_pm.dev, "Charge Full: Interrupt generated too slowly - retry.\n"); 284 dev_dbg(sharpsl_pm.dev, "Charge Full: Interrupt generated too slowly - retry.\n");
285 schedule_work(&toggle_charger); 285 schedule_delayed_work(&toggle_charger, 0);
286 } else { 286 } else {
287 sharpsl_charge_off(); 287 sharpsl_charge_off();
288 sharpsl_pm.charge_mode = CHRG_DONE; 288 sharpsl_pm.charge_mode = CHRG_DONE;
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 43d278134521..c026fa2214a3 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -27,14 +27,14 @@
27 27
28static void vic_mask_irq(unsigned int irq) 28static void vic_mask_irq(unsigned int irq)
29{ 29{
30 void __iomem *base = get_irq_chipdata(irq); 30 void __iomem *base = get_irq_chip_data(irq);
31 irq &= 31; 31 irq &= 31;
32 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); 32 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
33} 33}
34 34
35static void vic_unmask_irq(unsigned int irq) 35static void vic_unmask_irq(unsigned int irq)
36{ 36{
37 void __iomem *base = get_irq_chipdata(irq); 37 void __iomem *base = get_irq_chip_data(irq);
38 irq &= 31; 38 irq &= 31;
39 writel(1 << irq, base + VIC_INT_ENABLE); 39 writel(1 << irq, base + VIC_INT_ENABLE);
40} 40}
@@ -88,10 +88,10 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
88 unsigned int irq = irq_start + i; 88 unsigned int irq = irq_start + i;
89 89
90 set_irq_chip(irq, &vic_chip); 90 set_irq_chip(irq, &vic_chip);
91 set_irq_chipdata(irq, base); 91 set_irq_chip_data(irq, base);
92 92
93 if (vic_sources & (1 << i)) { 93 if (vic_sources & (1 << i)) {
94 set_irq_handler(irq, do_level_IRQ); 94 set_irq_handler(irq, handle_level_irq);
95 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 95 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
96 } 96 }
97 } 97 }
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 1d79360f3eba..e10d003566d6 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -981,7 +981,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
981CONFIG_FRAME_POINTER=y 981CONFIG_FRAME_POINTER=y
982# CONFIG_RCU_TORTURE_TEST is not set 982# CONFIG_RCU_TORTURE_TEST is not set
983CONFIG_DEBUG_USER=y 983CONFIG_DEBUG_USER=y
984# CONFIG_DEBUG_WAITQ is not set
985# CONFIG_DEBUG_ERRORS is not set 984# CONFIG_DEBUG_ERRORS is not set
986CONFIG_DEBUG_LL=y 985CONFIG_DEBUG_LL=y
987# CONFIG_DEBUG_ICEDCC is not set 986# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 16120bca3cb7..834dddb51314 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -970,7 +970,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
970CONFIG_FRAME_POINTER=y 970CONFIG_FRAME_POINTER=y
971# CONFIG_RCU_TORTURE_TEST is not set 971# CONFIG_RCU_TORTURE_TEST is not set
972CONFIG_DEBUG_USER=y 972CONFIG_DEBUG_USER=y
973# CONFIG_DEBUG_WAITQ is not set
974# CONFIG_DEBUG_ERRORS is not set 973# CONFIG_DEBUG_ERRORS is not set
975CONFIG_DEBUG_LL=y 974CONFIG_DEBUG_LL=y
976# CONFIG_DEBUG_ICEDCC is not set 975# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index cfe6bd8e81cd..821865f75605 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -1216,7 +1216,6 @@ CONFIG_DEBUG_INFO=y
1216# CONFIG_DEBUG_FS is not set 1216# CONFIG_DEBUG_FS is not set
1217CONFIG_FRAME_POINTER=y 1217CONFIG_FRAME_POINTER=y
1218CONFIG_DEBUG_USER=y 1218CONFIG_DEBUG_USER=y
1219# CONFIG_DEBUG_WAITQ is not set
1220CONFIG_DEBUG_ERRORS=y 1219CONFIG_DEBUG_ERRORS=y
1221CONFIG_DEBUG_LL=y 1220CONFIG_DEBUG_LL=y
1222# CONFIG_DEBUG_ICEDCC is not set 1221# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig
index 09b7acd7f647..ee130b528bd4 100644
--- a/arch/arm/configs/cerfcube_defconfig
+++ b/arch/arm/configs/cerfcube_defconfig
@@ -851,7 +851,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
851# CONFIG_DEBUG_FS is not set 851# CONFIG_DEBUG_FS is not set
852CONFIG_FRAME_POINTER=y 852CONFIG_FRAME_POINTER=y
853CONFIG_DEBUG_USER=y 853CONFIG_DEBUG_USER=y
854# CONFIG_DEBUG_WAITQ is not set
855CONFIG_DEBUG_ERRORS=y 854CONFIG_DEBUG_ERRORS=y
856CONFIG_DEBUG_LL=y 855CONFIG_DEBUG_LL=y
857# CONFIG_DEBUG_ICEDCC is not set 856# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index a3758913c0bb..970c8c772eb7 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -934,7 +934,6 @@ CONFIG_FRAME_POINTER=y
934CONFIG_FORCED_INLINING=y 934CONFIG_FORCED_INLINING=y
935# CONFIG_RCU_TORTURE_TEST is not set 935# CONFIG_RCU_TORTURE_TEST is not set
936# CONFIG_DEBUG_USER is not set 936# CONFIG_DEBUG_USER is not set
937# CONFIG_DEBUG_WAITQ is not set
938CONFIG_DEBUG_ERRORS=y 937CONFIG_DEBUG_ERRORS=y
939# CONFIG_DEBUG_LL is not set 938# CONFIG_DEBUG_LL is not set
940 939
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index c41c04fa5020..e8980a9bb893 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -1513,7 +1513,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1513CONFIG_FRAME_POINTER=y 1513CONFIG_FRAME_POINTER=y
1514# CONFIG_RCU_TORTURE_TEST is not set 1514# CONFIG_RCU_TORTURE_TEST is not set
1515# CONFIG_DEBUG_USER is not set 1515# CONFIG_DEBUG_USER is not set
1516# CONFIG_DEBUG_WAITQ is not set
1517CONFIG_DEBUG_ERRORS=y 1516CONFIG_DEBUG_ERRORS=y
1518CONFIG_DEBUG_LL=y 1517CONFIG_DEBUG_LL=y
1519# CONFIG_DEBUG_ICEDCC is not set 1518# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig
index 20e68250d835..2cadd51506bb 100644
--- a/arch/arm/configs/csb337_defconfig
+++ b/arch/arm/configs/csb337_defconfig
@@ -1113,7 +1113,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1113CONFIG_FRAME_POINTER=y 1113CONFIG_FRAME_POINTER=y
1114# CONFIG_RCU_TORTURE_TEST is not set 1114# CONFIG_RCU_TORTURE_TEST is not set
1115CONFIG_DEBUG_USER=y 1115CONFIG_DEBUG_USER=y
1116# CONFIG_DEBUG_WAITQ is not set
1117# CONFIG_DEBUG_ERRORS is not set 1116# CONFIG_DEBUG_ERRORS is not set
1118CONFIG_DEBUG_LL=y 1117CONFIG_DEBUG_LL=y
1119# CONFIG_DEBUG_ICEDCC is not set 1118# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
index abf33520b709..94908c1df4cf 100644
--- a/arch/arm/configs/csb637_defconfig
+++ b/arch/arm/configs/csb637_defconfig
@@ -1062,7 +1062,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1062CONFIG_FRAME_POINTER=y 1062CONFIG_FRAME_POINTER=y
1063# CONFIG_RCU_TORTURE_TEST is not set 1063# CONFIG_RCU_TORTURE_TEST is not set
1064CONFIG_DEBUG_USER=y 1064CONFIG_DEBUG_USER=y
1065# CONFIG_DEBUG_WAITQ is not set
1066# CONFIG_DEBUG_ERRORS is not set 1065# CONFIG_DEBUG_ERRORS is not set
1067CONFIG_DEBUG_LL=y 1066CONFIG_DEBUG_LL=y
1068# CONFIG_DEBUG_ICEDCC is not set 1067# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 3b4802a849e4..f8a66b72ad5d 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -125,6 +125,7 @@ CONFIG_CRUNCH=y
125# 125#
126# EP93xx Platforms 126# EP93xx Platforms
127# 127#
128CONFIG_MACH_ADSSPHERE=y
128CONFIG_MACH_EDB9302=y 129CONFIG_MACH_EDB9302=y
129CONFIG_MACH_EDB9312=y 130CONFIG_MACH_EDB9312=y
130CONFIG_MACH_EDB9315=y 131CONFIG_MACH_EDB9315=y
@@ -1134,7 +1135,6 @@ CONFIG_FRAME_POINTER=y
1134CONFIG_FORCED_INLINING=y 1135CONFIG_FORCED_INLINING=y
1135# CONFIG_RCU_TORTURE_TEST is not set 1136# CONFIG_RCU_TORTURE_TEST is not set
1136CONFIG_DEBUG_USER=y 1137CONFIG_DEBUG_USER=y
1137CONFIG_DEBUG_WAITQ=y
1138CONFIG_DEBUG_ERRORS=y 1138CONFIG_DEBUG_ERRORS=y
1139CONFIG_DEBUG_LL=y 1139CONFIG_DEBUG_LL=y
1140# CONFIG_DEBUG_ICEDCC is not set 1140# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
index 9d62ed16bf57..0e739af52713 100644
--- a/arch/arm/configs/h7202_defconfig
+++ b/arch/arm/configs/h7202_defconfig
@@ -702,7 +702,6 @@ CONFIG_DEBUG_INFO=y
702# CONFIG_DEBUG_FS is not set 702# CONFIG_DEBUG_FS is not set
703CONFIG_FRAME_POINTER=y 703CONFIG_FRAME_POINTER=y
704CONFIG_DEBUG_USER=y 704CONFIG_DEBUG_USER=y
705# CONFIG_DEBUG_WAITQ is not set
706# CONFIG_DEBUG_ERRORS is not set 705# CONFIG_DEBUG_ERRORS is not set
707# CONFIG_DEBUG_LL is not set 706# CONFIG_DEBUG_LL is not set
708 707
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index a45b57582b86..1c8fb89a6730 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -740,7 +740,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
740# CONFIG_DEBUG_FS is not set 740# CONFIG_DEBUG_FS is not set
741CONFIG_FRAME_POINTER=y 741CONFIG_FRAME_POINTER=y
742CONFIG_DEBUG_USER=y 742CONFIG_DEBUG_USER=y
743CONFIG_DEBUG_WAITQ=y
744CONFIG_DEBUG_ERRORS=y 743CONFIG_DEBUG_ERRORS=y
745CONFIG_DEBUG_LL=y 744CONFIG_DEBUG_LL=y
746# CONFIG_DEBUG_ICEDCC is not set 745# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 692ab57ba1ca..3ce96e60b409 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -835,7 +835,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
835# CONFIG_DEBUG_FS is not set 835# CONFIG_DEBUG_FS is not set
836CONFIG_FRAME_POINTER=y 836CONFIG_FRAME_POINTER=y
837# CONFIG_DEBUG_USER is not set 837# CONFIG_DEBUG_USER is not set
838# CONFIG_DEBUG_WAITQ is not set
839CONFIG_DEBUG_ERRORS=y 838CONFIG_DEBUG_ERRORS=y
840# CONFIG_DEBUG_LL is not set 839# CONFIG_DEBUG_LL is not set
841 840
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
new file mode 100644
index 000000000000..f6e46193fd26
--- /dev/null
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -0,0 +1,1134 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.19
4# Fri Dec 1 10:51:01 2006
5#
6CONFIG_ARM=y
7# CONFIG_GENERIC_TIME is not set
8CONFIG_MMU=y
9CONFIG_GENERIC_HARDIRQS=y
10CONFIG_TRACE_IRQFLAGS_SUPPORT=y
11CONFIG_HARDIRQS_SW_RESEND=y
12CONFIG_GENERIC_IRQ_PROBE=y
13CONFIG_RWSEM_GENERIC_SPINLOCK=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_CALIBRATE_DELAY=y
16CONFIG_VECTORS_BASE=0xffff0000
17CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
18
19#
20# Code maturity level options
21#
22CONFIG_EXPERIMENTAL=y
23CONFIG_BROKEN_ON_SMP=y
24CONFIG_INIT_ENV_ARG_LIMIT=32
25
26#
27# General setup
28#
29CONFIG_LOCALVERSION=""
30# CONFIG_LOCALVERSION_AUTO is not set
31CONFIG_SWAP=y
32CONFIG_SYSVIPC=y
33# CONFIG_IPC_NS is not set
34CONFIG_POSIX_MQUEUE=y
35CONFIG_BSD_PROCESS_ACCT=y
36# CONFIG_BSD_PROCESS_ACCT_V3 is not set
37# CONFIG_TASKSTATS is not set
38# CONFIG_UTS_NS is not set
39# CONFIG_AUDIT is not set
40CONFIG_IKCONFIG=y
41CONFIG_IKCONFIG_PROC=y
42# CONFIG_RELAY is not set
43CONFIG_INITRAMFS_SOURCE=""
44# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
45CONFIG_SYSCTL=y
46# CONFIG_EMBEDDED is not set
47CONFIG_UID16=y
48CONFIG_SYSCTL_SYSCALL=y
49CONFIG_KALLSYMS=y
50# CONFIG_KALLSYMS_EXTRA_PASS is not set
51CONFIG_HOTPLUG=y
52CONFIG_PRINTK=y
53CONFIG_BUG=y
54CONFIG_ELF_CORE=y
55CONFIG_BASE_FULL=y
56CONFIG_FUTEX=y
57CONFIG_EPOLL=y
58CONFIG_SHMEM=y
59CONFIG_SLAB=y
60CONFIG_VM_EVENT_COUNTERS=y
61CONFIG_RT_MUTEXES=y
62# CONFIG_TINY_SHMEM is not set
63CONFIG_BASE_SMALL=0
64# CONFIG_SLOB is not set
65
66#
67# Loadable module support
68#
69CONFIG_MODULES=y
70CONFIG_MODULE_UNLOAD=y
71# CONFIG_MODULE_FORCE_UNLOAD is not set
72CONFIG_MODVERSIONS=y
73# CONFIG_MODULE_SRCVERSION_ALL is not set
74CONFIG_KMOD=y
75
76#
77# Block layer
78#
79CONFIG_BLOCK=y
80# CONFIG_BLK_DEV_IO_TRACE is not set
81
82#
83# IO Schedulers
84#
85CONFIG_IOSCHED_NOOP=y
86# CONFIG_IOSCHED_AS is not set
87CONFIG_IOSCHED_DEADLINE=y
88# CONFIG_IOSCHED_CFQ is not set
89# CONFIG_DEFAULT_AS is not set
90CONFIG_DEFAULT_DEADLINE=y
91# CONFIG_DEFAULT_CFQ is not set
92# CONFIG_DEFAULT_NOOP is not set
93CONFIG_DEFAULT_IOSCHED="deadline"
94
95#
96# System Type
97#
98# CONFIG_ARCH_AAEC2000 is not set
99# CONFIG_ARCH_INTEGRATOR is not set
100# CONFIG_ARCH_REALVIEW is not set
101# CONFIG_ARCH_VERSATILE is not set
102# CONFIG_ARCH_AT91 is not set
103# CONFIG_ARCH_CLPS7500 is not set
104# CONFIG_ARCH_CLPS711X is not set
105# CONFIG_ARCH_CO285 is not set
106# CONFIG_ARCH_EBSA110 is not set
107# CONFIG_ARCH_EP93XX is not set
108# CONFIG_ARCH_FOOTBRIDGE is not set
109# CONFIG_ARCH_NETX is not set
110# CONFIG_ARCH_H720X is not set
111# CONFIG_ARCH_IMX is not set
112# CONFIG_ARCH_IOP32X is not set
113# CONFIG_ARCH_IOP33X is not set
114CONFIG_ARCH_IOP13XX=y
115# CONFIG_ARCH_IXP4XX is not set
116# CONFIG_ARCH_IXP2000 is not set
117# CONFIG_ARCH_IXP23XX is not set
118# CONFIG_ARCH_L7200 is not set
119# CONFIG_ARCH_PNX4008 is not set
120# CONFIG_ARCH_PXA is not set
121# CONFIG_ARCH_RPC is not set
122# CONFIG_ARCH_SA1100 is not set
123# CONFIG_ARCH_S3C2410 is not set
124# CONFIG_ARCH_SHARK is not set
125# CONFIG_ARCH_LH7A40X is not set
126# CONFIG_ARCH_OMAP is not set
127
128#
129# IOP13XX Implementation Options
130#
131
132#
133# IOP13XX Platform Support
134#
135CONFIG_MACH_IQ81340SC=y
136CONFIG_MACH_IQ81340MC=y
137
138#
139# Processor Type
140#
141CONFIG_CPU_32=y
142CONFIG_CPU_XSC3=y
143CONFIG_CPU_32v5=y
144CONFIG_CPU_ABRT_EV5T=y
145CONFIG_CPU_CACHE_VIVT=y
146CONFIG_CPU_TLB_V4WBI=y
147CONFIG_CPU_CP15=y
148CONFIG_CPU_CP15_MMU=y
149CONFIG_IO_36=y
150
151#
152# Processor Features
153#
154CONFIG_ARM_THUMB=y
155# CONFIG_CPU_DCACHE_DISABLE is not set
156# CONFIG_CPU_BPREDICT_DISABLE is not set
157
158#
159# Bus support
160#
161CONFIG_PCI=y
162
163#
164# PCCARD (PCMCIA/CardBus) support
165#
166# CONFIG_PCCARD is not set
167
168#
169# Kernel Features
170#
171# CONFIG_PREEMPT is not set
172# CONFIG_NO_IDLE_HZ is not set
173CONFIG_HZ=100
174# CONFIG_AEABI is not set
175# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
176CONFIG_SELECT_MEMORY_MODEL=y
177CONFIG_FLATMEM_MANUAL=y
178# CONFIG_DISCONTIGMEM_MANUAL is not set
179# CONFIG_SPARSEMEM_MANUAL is not set
180CONFIG_FLATMEM=y
181CONFIG_FLAT_NODE_MEM_MAP=y
182# CONFIG_SPARSEMEM_STATIC is not set
183CONFIG_SPLIT_PTLOCK_CPUS=4096
184# CONFIG_RESOURCES_64BIT is not set
185CONFIG_ALIGNMENT_TRAP=y
186
187#
188# Boot options
189#
190CONFIG_ZBOOT_ROM_TEXT=0x0
191CONFIG_ZBOOT_ROM_BSS=0x0
192CONFIG_CMDLINE="ip=bootp root=nfs console=ttyS0,115200 nfsroot=,tcp,v3,wsize=8192,rsize=8192"
193# CONFIG_XIP_KERNEL is not set
194
195#
196# Floating point emulation
197#
198
199#
200# At least one emulation must be selected
201#
202CONFIG_FPE_NWFPE=y
203# CONFIG_FPE_NWFPE_XP is not set
204# CONFIG_FPE_FASTFPE is not set
205
206#
207# Userspace binary formats
208#
209CONFIG_BINFMT_ELF=y
210CONFIG_BINFMT_AOUT=y
211# CONFIG_BINFMT_MISC is not set
212# CONFIG_ARTHUR is not set
213
214#
215# Power management options
216#
217# CONFIG_PM is not set
218# CONFIG_APM is not set
219
220#
221# Networking
222#
223CONFIG_NET=y
224
225#
226# Networking options
227#
228# CONFIG_NETDEBUG is not set
229CONFIG_PACKET=y
230CONFIG_PACKET_MMAP=y
231CONFIG_UNIX=y
232CONFIG_XFRM=y
233# CONFIG_XFRM_USER is not set
234# CONFIG_XFRM_SUB_POLICY is not set
235CONFIG_NET_KEY=y
236CONFIG_INET=y
237CONFIG_IP_MULTICAST=y
238# CONFIG_IP_ADVANCED_ROUTER is not set
239CONFIG_IP_FIB_HASH=y
240CONFIG_IP_PNP=y
241# CONFIG_IP_PNP_DHCP is not set
242CONFIG_IP_PNP_BOOTP=y
243# CONFIG_IP_PNP_RARP is not set
244# CONFIG_NET_IPIP is not set
245# CONFIG_NET_IPGRE is not set
246# CONFIG_IP_MROUTE is not set
247# CONFIG_ARPD is not set
248# CONFIG_SYN_COOKIES is not set
249# CONFIG_INET_AH is not set
250# CONFIG_INET_ESP is not set
251# CONFIG_INET_IPCOMP is not set
252# CONFIG_INET_XFRM_TUNNEL is not set
253# CONFIG_INET_TUNNEL is not set
254CONFIG_INET_XFRM_MODE_TRANSPORT=y
255CONFIG_INET_XFRM_MODE_TUNNEL=y
256CONFIG_INET_XFRM_MODE_BEET=y
257CONFIG_INET_DIAG=y
258CONFIG_INET_TCP_DIAG=y
259# CONFIG_TCP_CONG_ADVANCED is not set
260CONFIG_TCP_CONG_CUBIC=y
261CONFIG_DEFAULT_TCP_CONG="cubic"
262# CONFIG_IPV6 is not set
263# CONFIG_INET6_XFRM_TUNNEL is not set
264# CONFIG_INET6_TUNNEL is not set
265# CONFIG_NETWORK_SECMARK is not set
266# CONFIG_NETFILTER is not set
267
268#
269# DCCP Configuration (EXPERIMENTAL)
270#
271# CONFIG_IP_DCCP is not set
272
273#
274# SCTP Configuration (EXPERIMENTAL)
275#
276# CONFIG_IP_SCTP is not set
277
278#
279# TIPC Configuration (EXPERIMENTAL)
280#
281# CONFIG_TIPC is not set
282# CONFIG_ATM is not set
283# CONFIG_BRIDGE is not set
284# CONFIG_VLAN_8021Q is not set
285# CONFIG_DECNET is not set
286# CONFIG_LLC2 is not set
287# CONFIG_IPX is not set
288# CONFIG_ATALK is not set
289# CONFIG_X25 is not set
290# CONFIG_LAPB is not set
291# CONFIG_ECONET is not set
292# CONFIG_WAN_ROUTER is not set
293
294#
295# QoS and/or fair queueing
296#
297# CONFIG_NET_SCHED is not set
298
299#
300# Network testing
301#
302# CONFIG_NET_PKTGEN is not set
303# CONFIG_HAMRADIO is not set
304# CONFIG_IRDA is not set
305# CONFIG_BT is not set
306# CONFIG_IEEE80211 is not set
307
308#
309# Device Drivers
310#
311
312#
313# Generic Driver Options
314#
315CONFIG_STANDALONE=y
316CONFIG_PREVENT_FIRMWARE_BUILD=y
317# CONFIG_FW_LOADER is not set
318# CONFIG_SYS_HYPERVISOR is not set
319
320#
321# Connector - unified userspace <-> kernelspace linker
322#
323# CONFIG_CONNECTOR is not set
324
325#
326# Memory Technology Devices (MTD)
327#
328CONFIG_MTD=y
329# CONFIG_MTD_DEBUG is not set
330# CONFIG_MTD_CONCAT is not set
331CONFIG_MTD_PARTITIONS=y
332CONFIG_MTD_REDBOOT_PARTS=y
333CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
334CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
335CONFIG_MTD_REDBOOT_PARTS_READONLY=y
336# CONFIG_MTD_CMDLINE_PARTS is not set
337# CONFIG_MTD_AFS_PARTS is not set
338
339#
340# User Modules And Translation Layers
341#
342# CONFIG_MTD_CHAR is not set
343CONFIG_MTD_BLOCK=y
344# CONFIG_FTL is not set
345# CONFIG_NFTL is not set
346# CONFIG_INFTL is not set
347# CONFIG_RFD_FTL is not set
348# CONFIG_SSFDC is not set
349
350#
351# RAM/ROM/Flash chip drivers
352#
353CONFIG_MTD_CFI=y
354# CONFIG_MTD_JEDECPROBE is not set
355CONFIG_MTD_GEN_PROBE=y
356CONFIG_MTD_CFI_ADV_OPTIONS=y
357CONFIG_MTD_CFI_NOSWAP=y
358# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
359# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
360# CONFIG_MTD_CFI_GEOMETRY is not set
361CONFIG_MTD_MAP_BANK_WIDTH_1=y
362CONFIG_MTD_MAP_BANK_WIDTH_2=y
363CONFIG_MTD_MAP_BANK_WIDTH_4=y
364# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
365# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
366# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
367CONFIG_MTD_CFI_I1=y
368CONFIG_MTD_CFI_I2=y
369# CONFIG_MTD_CFI_I4 is not set
370# CONFIG_MTD_CFI_I8 is not set
371# CONFIG_MTD_OTP is not set
372CONFIG_MTD_CFI_INTELEXT=y
373# CONFIG_MTD_CFI_AMDSTD is not set
374# CONFIG_MTD_CFI_STAA is not set
375CONFIG_MTD_CFI_UTIL=y
376# CONFIG_MTD_RAM is not set
377# CONFIG_MTD_ROM is not set
378# CONFIG_MTD_ABSENT is not set
379# CONFIG_MTD_OBSOLETE_CHIPS is not set
380
381#
382# Mapping drivers for chip access
383#
384# CONFIG_MTD_COMPLEX_MAPPINGS is not set
385CONFIG_MTD_PHYSMAP=y
386CONFIG_MTD_PHYSMAP_START=0xfa000000
387CONFIG_MTD_PHYSMAP_LEN=0x0
388CONFIG_MTD_PHYSMAP_BANKWIDTH=2
389# CONFIG_MTD_ARM_INTEGRATOR is not set
390# CONFIG_MTD_PLATRAM is not set
391
392#
393# Self-contained MTD device drivers
394#
395# CONFIG_MTD_PMC551 is not set
396# CONFIG_MTD_SLRAM is not set
397# CONFIG_MTD_PHRAM is not set
398# CONFIG_MTD_MTDRAM is not set
399# CONFIG_MTD_BLOCK2MTD is not set
400
401#
402# Disk-On-Chip Device Drivers
403#
404# CONFIG_MTD_DOC2000 is not set
405# CONFIG_MTD_DOC2001 is not set
406# CONFIG_MTD_DOC2001PLUS is not set
407
408#
409# NAND Flash Device Drivers
410#
411# CONFIG_MTD_NAND is not set
412
413#
414# OneNAND Flash Device Drivers
415#
416# CONFIG_MTD_ONENAND is not set
417
418#
419# Parallel port support
420#
421# CONFIG_PARPORT is not set
422
423#
424# Plug and Play support
425#
426
427#
428# Block devices
429#
430# CONFIG_BLK_CPQ_DA is not set
431# CONFIG_BLK_CPQ_CISS_DA is not set
432# CONFIG_BLK_DEV_DAC960 is not set
433# CONFIG_BLK_DEV_UMEM is not set
434# CONFIG_BLK_DEV_COW_COMMON is not set
435# CONFIG_BLK_DEV_LOOP is not set
436# CONFIG_BLK_DEV_NBD is not set
437# CONFIG_BLK_DEV_SX8 is not set
438CONFIG_BLK_DEV_RAM=y
439CONFIG_BLK_DEV_RAM_COUNT=2
440CONFIG_BLK_DEV_RAM_SIZE=8192
441CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
442CONFIG_BLK_DEV_INITRD=y
443# CONFIG_CDROM_PKTCDVD is not set
444# CONFIG_ATA_OVER_ETH is not set
445
446#
447# SCSI device support
448#
449# CONFIG_RAID_ATTRS is not set
450CONFIG_SCSI=y
451# CONFIG_SCSI_NETLINK is not set
452CONFIG_SCSI_PROC_FS=y
453
454#
455# SCSI support type (disk, tape, CD-ROM)
456#
457CONFIG_BLK_DEV_SD=y
458# CONFIG_CHR_DEV_ST is not set
459# CONFIG_CHR_DEV_OSST is not set
460# CONFIG_BLK_DEV_SR is not set
461CONFIG_CHR_DEV_SG=y
462# CONFIG_CHR_DEV_SCH is not set
463
464#
465# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
466#
467# CONFIG_SCSI_MULTI_LUN is not set
468CONFIG_SCSI_CONSTANTS=y
469# CONFIG_SCSI_LOGGING is not set
470
471#
472# SCSI Transports
473#
474# CONFIG_SCSI_SPI_ATTRS is not set
475# CONFIG_SCSI_FC_ATTRS is not set
476CONFIG_SCSI_ISCSI_ATTRS=y
477CONFIG_SCSI_SAS_ATTRS=y
478# CONFIG_SCSI_SAS_LIBSAS is not set
479
480#
481# SCSI low-level drivers
482#
483# CONFIG_ISCSI_TCP is not set
484# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
485# CONFIG_SCSI_3W_9XXX is not set
486# CONFIG_SCSI_ACARD is not set
487# CONFIG_SCSI_AACRAID is not set
488# CONFIG_SCSI_AIC7XXX is not set
489# CONFIG_SCSI_AIC7XXX_OLD is not set
490# CONFIG_SCSI_AIC79XX is not set
491# CONFIG_SCSI_AIC94XX is not set
492# CONFIG_SCSI_DPT_I2O is not set
493# CONFIG_SCSI_ARCMSR is not set
494# CONFIG_MEGARAID_NEWGEN is not set
495# CONFIG_MEGARAID_LEGACY is not set
496# CONFIG_MEGARAID_SAS is not set
497# CONFIG_SCSI_HPTIOP is not set
498# CONFIG_SCSI_DMX3191D is not set
499# CONFIG_SCSI_FUTURE_DOMAIN is not set
500# CONFIG_SCSI_IPS is not set
501# CONFIG_SCSI_INITIO is not set
502# CONFIG_SCSI_INIA100 is not set
503# CONFIG_SCSI_STEX is not set
504# CONFIG_SCSI_SYM53C8XX_2 is not set
505# CONFIG_SCSI_QLOGIC_1280 is not set
506# CONFIG_SCSI_QLA_FC is not set
507# CONFIG_SCSI_QLA_ISCSI is not set
508# CONFIG_SCSI_LPFC is not set
509# CONFIG_SCSI_DC395x is not set
510# CONFIG_SCSI_DC390T is not set
511# CONFIG_SCSI_NSP32 is not set
512# CONFIG_SCSI_DEBUG is not set
513
514#
515# Serial ATA (prod) and Parallel ATA (experimental) drivers
516#
517# CONFIG_ATA is not set
518
519#
520# Multi-device support (RAID and LVM)
521#
522CONFIG_MD=y
523CONFIG_BLK_DEV_MD=y
524# CONFIG_MD_LINEAR is not set
525CONFIG_MD_RAID0=y
526CONFIG_MD_RAID1=y
527CONFIG_MD_RAID10=y
528CONFIG_MD_RAID456=y
529# CONFIG_MD_RAID5_RESHAPE is not set
530# CONFIG_MD_MULTIPATH is not set
531# CONFIG_MD_FAULTY is not set
532CONFIG_BLK_DEV_DM=y
533# CONFIG_DM_DEBUG is not set
534# CONFIG_DM_CRYPT is not set
535# CONFIG_DM_SNAPSHOT is not set
536# CONFIG_DM_MIRROR is not set
537# CONFIG_DM_ZERO is not set
538# CONFIG_DM_MULTIPATH is not set
539
540#
541# Fusion MPT device support
542#
543# CONFIG_FUSION is not set
544# CONFIG_FUSION_SPI is not set
545# CONFIG_FUSION_FC is not set
546# CONFIG_FUSION_SAS is not set
547
548#
549# IEEE 1394 (FireWire) support
550#
551# CONFIG_IEEE1394 is not set
552
553#
554# I2O device support
555#
556# CONFIG_I2O is not set
557
558#
559# Network device support
560#
561CONFIG_NETDEVICES=y
562# CONFIG_DUMMY is not set
563# CONFIG_BONDING is not set
564# CONFIG_EQUALIZER is not set
565# CONFIG_TUN is not set
566
567#
568# ARCnet devices
569#
570# CONFIG_ARCNET is not set
571
572#
573# PHY device support
574#
575
576#
577# Ethernet (10 or 100Mbit)
578#
579# CONFIG_NET_ETHERNET is not set
580
581#
582# Ethernet (1000 Mbit)
583#
584# CONFIG_ACENIC is not set
585# CONFIG_DL2K is not set
586CONFIG_E1000=y
587CONFIG_E1000_NAPI=y
588# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
589# CONFIG_NS83820 is not set
590# CONFIG_HAMACHI is not set
591# CONFIG_YELLOWFIN is not set
592# CONFIG_R8169 is not set
593# CONFIG_SIS190 is not set
594# CONFIG_SKGE is not set
595# CONFIG_SKY2 is not set
596# CONFIG_SK98LIN is not set
597# CONFIG_TIGON3 is not set
598# CONFIG_BNX2 is not set
599# CONFIG_QLA3XXX is not set
600
601#
602# Ethernet (10000 Mbit)
603#
604# CONFIG_CHELSIO_T1 is not set
605# CONFIG_IXGB is not set
606# CONFIG_S2IO is not set
607# CONFIG_MYRI10GE is not set
608
609#
610# Token Ring devices
611#
612# CONFIG_TR is not set
613
614#
615# Wireless LAN (non-hamradio)
616#
617# CONFIG_NET_RADIO is not set
618
619#
620# Wan interfaces
621#
622# CONFIG_WAN is not set
623# CONFIG_FDDI is not set
624# CONFIG_HIPPI is not set
625# CONFIG_PPP is not set
626# CONFIG_SLIP is not set
627# CONFIG_NET_FC is not set
628# CONFIG_SHAPER is not set
629# CONFIG_NETCONSOLE is not set
630# CONFIG_NETPOLL is not set
631# CONFIG_NET_POLL_CONTROLLER is not set
632
633#
634# ISDN subsystem
635#
636# CONFIG_ISDN is not set
637
638#
639# Input device support
640#
641CONFIG_INPUT=y
642# CONFIG_INPUT_FF_MEMLESS is not set
643
644#
645# Userland interfaces
646#
647CONFIG_INPUT_MOUSEDEV=y
648# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
649CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
650CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
651# CONFIG_INPUT_JOYDEV is not set
652# CONFIG_INPUT_TSDEV is not set
653# CONFIG_INPUT_EVDEV is not set
654# CONFIG_INPUT_EVBUG is not set
655
656#
657# Input Device Drivers
658#
659# CONFIG_INPUT_KEYBOARD is not set
660# CONFIG_INPUT_MOUSE is not set
661# CONFIG_INPUT_JOYSTICK is not set
662# CONFIG_INPUT_TOUCHSCREEN is not set
663# CONFIG_INPUT_MISC is not set
664
665#
666# Hardware I/O ports
667#
668# CONFIG_SERIO is not set
669# CONFIG_GAMEPORT is not set
670
671#
672# Character devices
673#
674CONFIG_VT=y
675CONFIG_VT_CONSOLE=y
676CONFIG_HW_CONSOLE=y
677# CONFIG_VT_HW_CONSOLE_BINDING is not set
678# CONFIG_SERIAL_NONSTANDARD is not set
679
680#
681# Serial drivers
682#
683CONFIG_SERIAL_8250=y
684CONFIG_SERIAL_8250_CONSOLE=y
685CONFIG_SERIAL_8250_PCI=y
686CONFIG_SERIAL_8250_NR_UARTS=2
687CONFIG_SERIAL_8250_RUNTIME_UARTS=2
688# CONFIG_SERIAL_8250_EXTENDED is not set
689
690#
691# Non-8250 serial port support
692#
693CONFIG_SERIAL_CORE=y
694CONFIG_SERIAL_CORE_CONSOLE=y
695# CONFIG_SERIAL_JSM is not set
696CONFIG_UNIX98_PTYS=y
697CONFIG_LEGACY_PTYS=y
698CONFIG_LEGACY_PTY_COUNT=256
699
700#
701# IPMI
702#
703# CONFIG_IPMI_HANDLER is not set
704
705#
706# Watchdog Cards
707#
708# CONFIG_WATCHDOG is not set
709CONFIG_HW_RANDOM=y
710# CONFIG_NVRAM is not set
711# CONFIG_DTLK is not set
712# CONFIG_R3964 is not set
713# CONFIG_APPLICOM is not set
714
715#
716# Ftape, the floppy tape device driver
717#
718# CONFIG_DRM is not set
719# CONFIG_RAW_DRIVER is not set
720
721#
722# TPM devices
723#
724# CONFIG_TCG_TPM is not set
725
726#
727# I2C support
728#
729CONFIG_I2C=y
730# CONFIG_I2C_CHARDEV is not set
731
732#
733# I2C Algorithms
734#
735CONFIG_I2C_ALGOBIT=m
736CONFIG_I2C_ALGOPCF=m
737CONFIG_I2C_ALGOPCA=m
738
739#
740# I2C Hardware Bus support
741#
742# CONFIG_I2C_ALI1535 is not set
743# CONFIG_I2C_ALI1563 is not set
744# CONFIG_I2C_ALI15X3 is not set
745# CONFIG_I2C_AMD756 is not set
746# CONFIG_I2C_AMD8111 is not set
747# CONFIG_I2C_I801 is not set
748# CONFIG_I2C_I810 is not set
749# CONFIG_I2C_PIIX4 is not set
750CONFIG_I2C_IOP3XX=y
751# CONFIG_I2C_NFORCE2 is not set
752# CONFIG_I2C_OCORES is not set
753# CONFIG_I2C_PARPORT_LIGHT is not set
754# CONFIG_I2C_PROSAVAGE is not set
755# CONFIG_I2C_SAVAGE4 is not set
756# CONFIG_I2C_SIS5595 is not set
757# CONFIG_I2C_SIS630 is not set
758# CONFIG_I2C_SIS96X is not set
759# CONFIG_I2C_STUB is not set
760# CONFIG_I2C_VIA is not set
761# CONFIG_I2C_VIAPRO is not set
762# CONFIG_I2C_VOODOO3 is not set
763# CONFIG_I2C_PCA_ISA is not set
764
765#
766# Miscellaneous I2C Chip support
767#
768# CONFIG_SENSORS_DS1337 is not set
769# CONFIG_SENSORS_DS1374 is not set
770# CONFIG_SENSORS_EEPROM is not set
771# CONFIG_SENSORS_PCF8574 is not set
772# CONFIG_SENSORS_PCA9539 is not set
773# CONFIG_SENSORS_PCF8591 is not set
774# CONFIG_SENSORS_MAX6875 is not set
775# CONFIG_I2C_DEBUG_CORE is not set
776# CONFIG_I2C_DEBUG_ALGO is not set
777# CONFIG_I2C_DEBUG_BUS is not set
778# CONFIG_I2C_DEBUG_CHIP is not set
779
780#
781# SPI support
782#
783# CONFIG_SPI is not set
784# CONFIG_SPI_MASTER is not set
785
786#
787# Dallas's 1-wire bus
788#
789# CONFIG_W1 is not set
790
791#
792# Hardware Monitoring support
793#
794CONFIG_HWMON=y
795# CONFIG_HWMON_VID is not set
796# CONFIG_SENSORS_ABITUGURU is not set
797# CONFIG_SENSORS_ADM1021 is not set
798# CONFIG_SENSORS_ADM1025 is not set
799# CONFIG_SENSORS_ADM1026 is not set
800# CONFIG_SENSORS_ADM1031 is not set
801# CONFIG_SENSORS_ADM9240 is not set
802# CONFIG_SENSORS_ASB100 is not set
803# CONFIG_SENSORS_ATXP1 is not set
804# CONFIG_SENSORS_DS1621 is not set
805# CONFIG_SENSORS_F71805F is not set
806# CONFIG_SENSORS_FSCHER is not set
807# CONFIG_SENSORS_FSCPOS is not set
808# CONFIG_SENSORS_GL518SM is not set
809# CONFIG_SENSORS_GL520SM is not set
810# CONFIG_SENSORS_IT87 is not set
811# CONFIG_SENSORS_LM63 is not set
812# CONFIG_SENSORS_LM75 is not set
813# CONFIG_SENSORS_LM77 is not set
814# CONFIG_SENSORS_LM78 is not set
815# CONFIG_SENSORS_LM80 is not set
816# CONFIG_SENSORS_LM83 is not set
817# CONFIG_SENSORS_LM85 is not set
818# CONFIG_SENSORS_LM87 is not set
819# CONFIG_SENSORS_LM90 is not set
820# CONFIG_SENSORS_LM92 is not set
821# CONFIG_SENSORS_MAX1619 is not set
822# CONFIG_SENSORS_PC87360 is not set
823# CONFIG_SENSORS_SIS5595 is not set
824# CONFIG_SENSORS_SMSC47M1 is not set
825# CONFIG_SENSORS_SMSC47M192 is not set
826# CONFIG_SENSORS_SMSC47B397 is not set
827# CONFIG_SENSORS_VIA686A is not set
828# CONFIG_SENSORS_VT1211 is not set
829# CONFIG_SENSORS_VT8231 is not set
830# CONFIG_SENSORS_W83781D is not set
831# CONFIG_SENSORS_W83791D is not set
832# CONFIG_SENSORS_W83792D is not set
833# CONFIG_SENSORS_W83L785TS is not set
834# CONFIG_SENSORS_W83627HF is not set
835# CONFIG_SENSORS_W83627EHF is not set
836# CONFIG_HWMON_DEBUG_CHIP is not set
837
838#
839# Misc devices
840#
841# CONFIG_SGI_IOC4 is not set
842# CONFIG_TIFM_CORE is not set
843
844#
845# LED devices
846#
847# CONFIG_NEW_LEDS is not set
848
849#
850# LED drivers
851#
852
853#
854# LED Triggers
855#
856
857#
858# Multimedia devices
859#
860# CONFIG_VIDEO_DEV is not set
861
862#
863# Digital Video Broadcasting Devices
864#
865# CONFIG_DVB is not set
866
867#
868# Graphics support
869#
870CONFIG_FIRMWARE_EDID=y
871# CONFIG_FB is not set
872
873#
874# Console display driver support
875#
876# CONFIG_VGA_CONSOLE is not set
877CONFIG_DUMMY_CONSOLE=y
878# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
879
880#
881# Sound
882#
883# CONFIG_SOUND is not set
884
885#
886# USB support
887#
888CONFIG_USB_ARCH_HAS_HCD=y
889CONFIG_USB_ARCH_HAS_OHCI=y
890CONFIG_USB_ARCH_HAS_EHCI=y
891# CONFIG_USB is not set
892
893#
894# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
895#
896
897#
898# USB Gadget Support
899#
900# CONFIG_USB_GADGET is not set
901
902#
903# MMC/SD Card support
904#
905# CONFIG_MMC is not set
906
907#
908# Real Time Clock
909#
910CONFIG_RTC_LIB=y
911# CONFIG_RTC_CLASS is not set
912
913#
914# File systems
915#
916CONFIG_EXT2_FS=y
917# CONFIG_EXT2_FS_XATTR is not set
918# CONFIG_EXT2_FS_XIP is not set
919CONFIG_EXT3_FS=y
920CONFIG_EXT3_FS_XATTR=y
921# CONFIG_EXT3_FS_POSIX_ACL is not set
922# CONFIG_EXT3_FS_SECURITY is not set
923# CONFIG_EXT4DEV_FS is not set
924CONFIG_JBD=y
925# CONFIG_JBD_DEBUG is not set
926CONFIG_FS_MBCACHE=y
927# CONFIG_REISERFS_FS is not set
928# CONFIG_JFS_FS is not set
929# CONFIG_FS_POSIX_ACL is not set
930# CONFIG_XFS_FS is not set
931# CONFIG_GFS2_FS is not set
932# CONFIG_OCFS2_FS is not set
933# CONFIG_MINIX_FS is not set
934# CONFIG_ROMFS_FS is not set
935CONFIG_INOTIFY=y
936CONFIG_INOTIFY_USER=y
937# CONFIG_QUOTA is not set
938CONFIG_DNOTIFY=y
939# CONFIG_AUTOFS_FS is not set
940# CONFIG_AUTOFS4_FS is not set
941# CONFIG_FUSE_FS is not set
942
943#
944# CD-ROM/DVD Filesystems
945#
946# CONFIG_ISO9660_FS is not set
947# CONFIG_UDF_FS is not set
948
949#
950# DOS/FAT/NT Filesystems
951#
952# CONFIG_MSDOS_FS is not set
953# CONFIG_VFAT_FS is not set
954# CONFIG_NTFS_FS is not set
955
956#
957# Pseudo filesystems
958#
959CONFIG_PROC_FS=y
960CONFIG_PROC_SYSCTL=y
961CONFIG_SYSFS=y
962CONFIG_TMPFS=y
963# CONFIG_TMPFS_POSIX_ACL is not set
964# CONFIG_HUGETLB_PAGE is not set
965CONFIG_RAMFS=y
966# CONFIG_CONFIGFS_FS is not set
967
968#
969# Miscellaneous filesystems
970#
971# CONFIG_ADFS_FS is not set
972# CONFIG_AFFS_FS is not set
973# CONFIG_HFS_FS is not set
974# CONFIG_HFSPLUS_FS is not set
975# CONFIG_BEFS_FS is not set
976# CONFIG_BFS_FS is not set
977# CONFIG_EFS_FS is not set
978# CONFIG_JFFS_FS is not set
979CONFIG_JFFS2_FS=y
980CONFIG_JFFS2_FS_DEBUG=0
981CONFIG_JFFS2_FS_WRITEBUFFER=y
982# CONFIG_JFFS2_SUMMARY is not set
983# CONFIG_JFFS2_FS_XATTR is not set
984# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
985CONFIG_JFFS2_ZLIB=y
986CONFIG_JFFS2_RTIME=y
987# CONFIG_JFFS2_RUBIN is not set
988# CONFIG_CRAMFS is not set
989# CONFIG_VXFS_FS is not set
990# CONFIG_HPFS_FS is not set
991# CONFIG_QNX4FS_FS is not set
992# CONFIG_SYSV_FS is not set
993# CONFIG_UFS_FS is not set
994
995#
996# Network File Systems
997#
998CONFIG_NFS_FS=y
999CONFIG_NFS_V3=y
1000# CONFIG_NFS_V3_ACL is not set
1001# CONFIG_NFS_V4 is not set
1002# CONFIG_NFS_DIRECTIO is not set
1003CONFIG_NFSD=y
1004CONFIG_NFSD_V3=y
1005# CONFIG_NFSD_V3_ACL is not set
1006# CONFIG_NFSD_V4 is not set
1007CONFIG_NFSD_TCP=y
1008CONFIG_ROOT_NFS=y
1009CONFIG_LOCKD=y
1010CONFIG_LOCKD_V4=y
1011CONFIG_EXPORTFS=y
1012CONFIG_NFS_COMMON=y
1013CONFIG_SUNRPC=y
1014# CONFIG_RPCSEC_GSS_KRB5 is not set
1015# CONFIG_RPCSEC_GSS_SPKM3 is not set
1016CONFIG_SMB_FS=m
1017# CONFIG_SMB_NLS_DEFAULT is not set
1018CONFIG_CIFS=m
1019# CONFIG_CIFS_STATS is not set
1020# CONFIG_CIFS_WEAK_PW_HASH is not set
1021# CONFIG_CIFS_XATTR is not set
1022# CONFIG_CIFS_DEBUG2 is not set
1023# CONFIG_CIFS_EXPERIMENTAL is not set
1024# CONFIG_NCP_FS is not set
1025# CONFIG_CODA_FS is not set
1026# CONFIG_AFS_FS is not set
1027# CONFIG_9P_FS is not set
1028
1029#
1030# Partition Types
1031#
1032CONFIG_PARTITION_ADVANCED=y
1033# CONFIG_ACORN_PARTITION is not set
1034# CONFIG_OSF_PARTITION is not set
1035# CONFIG_AMIGA_PARTITION is not set
1036# CONFIG_ATARI_PARTITION is not set
1037# CONFIG_MAC_PARTITION is not set
1038CONFIG_MSDOS_PARTITION=y
1039# CONFIG_BSD_DISKLABEL is not set
1040# CONFIG_MINIX_SUBPARTITION is not set
1041# CONFIG_SOLARIS_X86_PARTITION is not set
1042# CONFIG_UNIXWARE_DISKLABEL is not set
1043# CONFIG_LDM_PARTITION is not set
1044# CONFIG_SGI_PARTITION is not set
1045# CONFIG_ULTRIX_PARTITION is not set
1046# CONFIG_SUN_PARTITION is not set
1047# CONFIG_KARMA_PARTITION is not set
1048# CONFIG_EFI_PARTITION is not set
1049
1050#
1051# Native Language Support
1052#
1053CONFIG_NLS=y
1054CONFIG_NLS_DEFAULT="iso8859-1"
1055# CONFIG_NLS_CODEPAGE_437 is not set
1056# CONFIG_NLS_CODEPAGE_737 is not set
1057# CONFIG_NLS_CODEPAGE_775 is not set
1058# CONFIG_NLS_CODEPAGE_850 is not set
1059# CONFIG_NLS_CODEPAGE_852 is not set
1060# CONFIG_NLS_CODEPAGE_855 is not set
1061# CONFIG_NLS_CODEPAGE_857 is not set
1062# CONFIG_NLS_CODEPAGE_860 is not set
1063# CONFIG_NLS_CODEPAGE_861 is not set
1064# CONFIG_NLS_CODEPAGE_862 is not set
1065# CONFIG_NLS_CODEPAGE_863 is not set
1066# CONFIG_NLS_CODEPAGE_864 is not set
1067# CONFIG_NLS_CODEPAGE_865 is not set
1068# CONFIG_NLS_CODEPAGE_866 is not set
1069# CONFIG_NLS_CODEPAGE_869 is not set
1070# CONFIG_NLS_CODEPAGE_936 is not set
1071# CONFIG_NLS_CODEPAGE_950 is not set
1072# CONFIG_NLS_CODEPAGE_932 is not set
1073# CONFIG_NLS_CODEPAGE_949 is not set
1074# CONFIG_NLS_CODEPAGE_874 is not set
1075# CONFIG_NLS_ISO8859_8 is not set
1076# CONFIG_NLS_CODEPAGE_1250 is not set
1077# CONFIG_NLS_CODEPAGE_1251 is not set
1078# CONFIG_NLS_ASCII is not set
1079# CONFIG_NLS_ISO8859_1 is not set
1080# CONFIG_NLS_ISO8859_2 is not set
1081# CONFIG_NLS_ISO8859_3 is not set
1082# CONFIG_NLS_ISO8859_4 is not set
1083# CONFIG_NLS_ISO8859_5 is not set
1084# CONFIG_NLS_ISO8859_6 is not set
1085# CONFIG_NLS_ISO8859_7 is not set
1086# CONFIG_NLS_ISO8859_9 is not set
1087# CONFIG_NLS_ISO8859_13 is not set
1088# CONFIG_NLS_ISO8859_14 is not set
1089# CONFIG_NLS_ISO8859_15 is not set
1090# CONFIG_NLS_KOI8_R is not set
1091# CONFIG_NLS_KOI8_U is not set
1092# CONFIG_NLS_UTF8 is not set
1093
1094#
1095# Profiling support
1096#
1097# CONFIG_PROFILING is not set
1098
1099#
1100# Kernel hacking
1101#
1102# CONFIG_PRINTK_TIME is not set
1103CONFIG_ENABLE_MUST_CHECK=y
1104# CONFIG_MAGIC_SYSRQ is not set
1105# CONFIG_UNUSED_SYMBOLS is not set
1106# CONFIG_DEBUG_KERNEL is not set
1107CONFIG_LOG_BUF_SHIFT=14
1108CONFIG_DEBUG_BUGVERBOSE=y
1109# CONFIG_DEBUG_FS is not set
1110CONFIG_FRAME_POINTER=y
1111# CONFIG_HEADERS_CHECK is not set
1112CONFIG_DEBUG_USER=y
1113
1114#
1115# Security options
1116#
1117# CONFIG_KEYS is not set
1118# CONFIG_SECURITY is not set
1119
1120#
1121# Cryptographic options
1122#
1123# CONFIG_CRYPTO is not set
1124
1125#
1126# Library routines
1127#
1128CONFIG_CRC_CCITT=y
1129# CONFIG_CRC16 is not set
1130CONFIG_CRC32=y
1131CONFIG_LIBCRC32C=y
1132CONFIG_ZLIB_INFLATE=y
1133CONFIG_ZLIB_DEFLATE=y
1134CONFIG_PLIST=y
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 0d67f66e78c2..b275c53728ec 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -1204,7 +1204,6 @@ CONFIG_FRAME_POINTER=y
1204# CONFIG_FORCED_INLINING is not set 1204# CONFIG_FORCED_INLINING is not set
1205# CONFIG_RCU_TORTURE_TEST is not set 1205# CONFIG_RCU_TORTURE_TEST is not set
1206CONFIG_DEBUG_USER=y 1206CONFIG_DEBUG_USER=y
1207# CONFIG_DEBUG_WAITQ is not set
1208# CONFIG_DEBUG_ERRORS is not set 1207# CONFIG_DEBUG_ERRORS is not set
1209CONFIG_DEBUG_LL=y 1208CONFIG_DEBUG_LL=y
1210# CONFIG_DEBUG_ICEDCC is not set 1209# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index 2a8fc153969d..848e3ace9069 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -1051,7 +1051,6 @@ CONFIG_FRAME_POINTER=y
1051# CONFIG_FORCED_INLINING is not set 1051# CONFIG_FORCED_INLINING is not set
1052# CONFIG_RCU_TORTURE_TEST is not set 1052# CONFIG_RCU_TORTURE_TEST is not set
1053CONFIG_DEBUG_USER=y 1053CONFIG_DEBUG_USER=y
1054# CONFIG_DEBUG_WAITQ is not set
1055# CONFIG_DEBUG_ERRORS is not set 1054# CONFIG_DEBUG_ERRORS is not set
1056CONFIG_DEBUG_LL=y 1055CONFIG_DEBUG_LL=y
1057# CONFIG_DEBUG_ICEDCC is not set 1056# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
index 27b3e31a8ad8..bbd2dcf91e52 100644
--- a/arch/arm/configs/ixp2000_defconfig
+++ b/arch/arm/configs/ixp2000_defconfig
@@ -1026,7 +1026,6 @@ CONFIG_FRAME_POINTER=y
1026CONFIG_FORCED_INLINING=y 1026CONFIG_FORCED_INLINING=y
1027# CONFIG_RCU_TORTURE_TEST is not set 1027# CONFIG_RCU_TORTURE_TEST is not set
1028CONFIG_DEBUG_USER=y 1028CONFIG_DEBUG_USER=y
1029# CONFIG_DEBUG_WAITQ is not set
1030CONFIG_DEBUG_ERRORS=y 1029CONFIG_DEBUG_ERRORS=y
1031CONFIG_DEBUG_LL=y 1030CONFIG_DEBUG_LL=y
1032# CONFIG_DEBUG_ICEDCC is not set 1031# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
index 7b18997083ce..06deefaec1d2 100644
--- a/arch/arm/configs/ixp23xx_defconfig
+++ b/arch/arm/configs/ixp23xx_defconfig
@@ -1305,7 +1305,6 @@ CONFIG_FRAME_POINTER=y
1305CONFIG_FORCED_INLINING=y 1305CONFIG_FORCED_INLINING=y
1306# CONFIG_RCU_TORTURE_TEST is not set 1306# CONFIG_RCU_TORTURE_TEST is not set
1307CONFIG_DEBUG_USER=y 1307CONFIG_DEBUG_USER=y
1308# CONFIG_DEBUG_WAITQ is not set
1309CONFIG_DEBUG_ERRORS=y 1308CONFIG_DEBUG_ERRORS=y
1310CONFIG_DEBUG_LL=y 1309CONFIG_DEBUG_LL=y
1311# CONFIG_DEBUG_ICEDCC is not set 1310# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index fac7c3b240c0..fabf74c51a88 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -1243,7 +1243,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1243CONFIG_FRAME_POINTER=y 1243CONFIG_FRAME_POINTER=y
1244# CONFIG_RCU_TORTURE_TEST is not set 1244# CONFIG_RCU_TORTURE_TEST is not set
1245# CONFIG_DEBUG_USER is not set 1245# CONFIG_DEBUG_USER is not set
1246# CONFIG_DEBUG_WAITQ is not set
1247CONFIG_DEBUG_ERRORS=y 1246CONFIG_DEBUG_ERRORS=y
1248CONFIG_DEBUG_LL=y 1247CONFIG_DEBUG_LL=y
1249# CONFIG_DEBUG_ICEDCC is not set 1248# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index 80a6fd97eb32..0c556289a3f4 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -889,7 +889,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
889# CONFIG_DEBUG_FS is not set 889# CONFIG_DEBUG_FS is not set
890CONFIG_FRAME_POINTER=y 890CONFIG_FRAME_POINTER=y
891# CONFIG_DEBUG_USER is not set 891# CONFIG_DEBUG_USER is not set
892# CONFIG_DEBUG_WAITQ is not set
893CONFIG_DEBUG_ERRORS=y 892CONFIG_DEBUG_ERRORS=y
894CONFIG_DEBUG_LL=y 893CONFIG_DEBUG_LL=y
895# CONFIG_DEBUG_ICEDCC is not set 894# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index 9ab0e0a66fd5..c16537d9d67a 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -753,7 +753,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
753# CONFIG_DEBUG_FS is not set 753# CONFIG_DEBUG_FS is not set
754CONFIG_FRAME_POINTER=y 754CONFIG_FRAME_POINTER=y
755CONFIG_DEBUG_USER=y 755CONFIG_DEBUG_USER=y
756# CONFIG_DEBUG_WAITQ is not set
757CONFIG_DEBUG_ERRORS=y 756CONFIG_DEBUG_ERRORS=y
758CONFIG_DEBUG_LL=y 757CONFIG_DEBUG_LL=y
759# CONFIG_DEBUG_ICEDCC is not set 758# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
index 4b29e099640d..e146189ab54f 100644
--- a/arch/arm/configs/lpd270_defconfig
+++ b/arch/arm/configs/lpd270_defconfig
@@ -949,7 +949,6 @@ CONFIG_FRAME_POINTER=y
949CONFIG_FORCED_INLINING=y 949CONFIG_FORCED_INLINING=y
950# CONFIG_RCU_TORTURE_TEST is not set 950# CONFIG_RCU_TORTURE_TEST is not set
951CONFIG_DEBUG_USER=y 951CONFIG_DEBUG_USER=y
952# CONFIG_DEBUG_WAITQ is not set
953CONFIG_DEBUG_ERRORS=y 952CONFIG_DEBUG_ERRORS=y
954CONFIG_DEBUG_LL=y 953CONFIG_DEBUG_LL=y
955# CONFIG_DEBUG_ICEDCC is not set 954# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig
index bf9cf9c6d2df..f8ac29d5c654 100644
--- a/arch/arm/configs/lpd7a400_defconfig
+++ b/arch/arm/configs/lpd7a400_defconfig
@@ -850,7 +850,6 @@ CONFIG_DEBUG_INFO=y
850# CONFIG_DEBUG_FS is not set 850# CONFIG_DEBUG_FS is not set
851CONFIG_FRAME_POINTER=y 851CONFIG_FRAME_POINTER=y
852CONFIG_DEBUG_USER=y 852CONFIG_DEBUG_USER=y
853# CONFIG_DEBUG_WAITQ is not set
854CONFIG_DEBUG_ERRORS=y 853CONFIG_DEBUG_ERRORS=y
855# CONFIG_DEBUG_LL is not set 854# CONFIG_DEBUG_LL is not set
856 855
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 3a57be32e849..46a0f7fe1fa5 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -1100,7 +1100,6 @@ CONFIG_FRAME_POINTER=y
1100CONFIG_FORCED_INLINING=y 1100CONFIG_FORCED_INLINING=y
1101# CONFIG_RCU_TORTURE_TEST is not set 1101# CONFIG_RCU_TORTURE_TEST is not set
1102CONFIG_DEBUG_USER=y 1102CONFIG_DEBUG_USER=y
1103# CONFIG_DEBUG_WAITQ is not set
1104CONFIG_DEBUG_ERRORS=y 1103CONFIG_DEBUG_ERRORS=y
1105# CONFIG_DEBUG_LL is not set 1104# CONFIG_DEBUG_LL is not set
1106 1105
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
index 81daadcbe0ba..e544bfbbde5d 100644
--- a/arch/arm/configs/lubbock_defconfig
+++ b/arch/arm/configs/lubbock_defconfig
@@ -772,7 +772,6 @@ CONFIG_DEBUG_INFO=y
772# CONFIG_DEBUG_FS is not set 772# CONFIG_DEBUG_FS is not set
773CONFIG_FRAME_POINTER=y 773CONFIG_FRAME_POINTER=y
774CONFIG_DEBUG_USER=y 774CONFIG_DEBUG_USER=y
775# CONFIG_DEBUG_WAITQ is not set
776CONFIG_DEBUG_ERRORS=y 775CONFIG_DEBUG_ERRORS=y
777CONFIG_DEBUG_LL=y 776CONFIG_DEBUG_LL=y
778# CONFIG_DEBUG_ICEDCC is not set 777# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
index b112bd75bda2..cc8c95b99292 100644
--- a/arch/arm/configs/mainstone_defconfig
+++ b/arch/arm/configs/mainstone_defconfig
@@ -766,7 +766,6 @@ CONFIG_DEBUG_INFO=y
766# CONFIG_DEBUG_FS is not set 766# CONFIG_DEBUG_FS is not set
767CONFIG_FRAME_POINTER=y 767CONFIG_FRAME_POINTER=y
768CONFIG_DEBUG_USER=y 768CONFIG_DEBUG_USER=y
769# CONFIG_DEBUG_WAITQ is not set
770CONFIG_DEBUG_ERRORS=y 769CONFIG_DEBUG_ERRORS=y
771CONFIG_DEBUG_LL=y 770CONFIG_DEBUG_LL=y
772# CONFIG_DEBUG_ICEDCC is not set 771# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/mx1ads_defconfig b/arch/arm/configs/mx1ads_defconfig
index d16f6cd6e039..577d7e1b5d42 100644
--- a/arch/arm/configs/mx1ads_defconfig
+++ b/arch/arm/configs/mx1ads_defconfig
@@ -691,7 +691,6 @@ CONFIG_DEBUG_INFO=y
691# CONFIG_DEBUG_FS is not set 691# CONFIG_DEBUG_FS is not set
692CONFIG_FRAME_POINTER=y 692CONFIG_FRAME_POINTER=y
693CONFIG_DEBUG_USER=y 693CONFIG_DEBUG_USER=y
694# CONFIG_DEBUG_WAITQ is not set
695CONFIG_DEBUG_ERRORS=y 694CONFIG_DEBUG_ERRORS=y
696# CONFIG_DEBUG_LL is not set 695# CONFIG_DEBUG_LL is not set
697 696
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index df8168e57b7c..e86794a10fc0 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -1115,7 +1115,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1115# CONFIG_DEBUG_FS is not set 1115# CONFIG_DEBUG_FS is not set
1116CONFIG_FRAME_POINTER=y 1116CONFIG_FRAME_POINTER=y
1117CONFIG_DEBUG_USER=y 1117CONFIG_DEBUG_USER=y
1118# CONFIG_DEBUG_WAITQ is not set
1119CONFIG_DEBUG_ERRORS=y 1118CONFIG_DEBUG_ERRORS=y
1120CONFIG_DEBUG_LL=y 1119CONFIG_DEBUG_LL=y
1121# CONFIG_DEBUG_ICEDCC is not set 1120# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
index 2cae1ead9f9b..c1a63a35c58d 100644
--- a/arch/arm/configs/netwinder_defconfig
+++ b/arch/arm/configs/netwinder_defconfig
@@ -994,7 +994,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
994# CONFIG_DEBUG_FS is not set 994# CONFIG_DEBUG_FS is not set
995CONFIG_FRAME_POINTER=y 995CONFIG_FRAME_POINTER=y
996CONFIG_DEBUG_USER=y 996CONFIG_DEBUG_USER=y
997# CONFIG_DEBUG_WAITQ is not set
998# CONFIG_DEBUG_ERRORS is not set 997# CONFIG_DEBUG_ERRORS is not set
999# CONFIG_DEBUG_LL is not set 998# CONFIG_DEBUG_LL is not set
1000 999
diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig
index 61115a773382..57f32f39d0ff 100644
--- a/arch/arm/configs/netx_defconfig
+++ b/arch/arm/configs/netx_defconfig
@@ -872,7 +872,6 @@ CONFIG_FRAME_POINTER=y
872CONFIG_FORCED_INLINING=y 872CONFIG_FORCED_INLINING=y
873# CONFIG_RCU_TORTURE_TEST is not set 873# CONFIG_RCU_TORTURE_TEST is not set
874# CONFIG_DEBUG_USER is not set 874# CONFIG_DEBUG_USER is not set
875# CONFIG_DEBUG_WAITQ is not set
876CONFIG_DEBUG_ERRORS=y 875CONFIG_DEBUG_ERRORS=y
877# CONFIG_DEBUG_LL is not set 876# CONFIG_DEBUG_LL is not set
878 877
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
index 9b9f2155af35..0498ebd7d5de 100644
--- a/arch/arm/configs/onearm_defconfig
+++ b/arch/arm/configs/onearm_defconfig
@@ -1045,7 +1045,6 @@ CONFIG_FRAME_POINTER=y
1045CONFIG_FORCED_INLINING=y 1045CONFIG_FORCED_INLINING=y
1046# CONFIG_RCU_TORTURE_TEST is not set 1046# CONFIG_RCU_TORTURE_TEST is not set
1047CONFIG_DEBUG_USER=y 1047CONFIG_DEBUG_USER=y
1048# CONFIG_DEBUG_WAITQ is not set
1049# CONFIG_DEBUG_ERRORS is not set 1048# CONFIG_DEBUG_ERRORS is not set
1050CONFIG_DEBUG_LL=y 1049CONFIG_DEBUG_LL=y
1051# CONFIG_DEBUG_ICEDCC is not set 1050# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
index 24e8bdd4cb91..a6b47ea8e465 100644
--- a/arch/arm/configs/pleb_defconfig
+++ b/arch/arm/configs/pleb_defconfig
@@ -721,7 +721,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
721# CONFIG_DEBUG_FS is not set 721# CONFIG_DEBUG_FS is not set
722CONFIG_FRAME_POINTER=y 722CONFIG_FRAME_POINTER=y
723# CONFIG_DEBUG_USER is not set 723# CONFIG_DEBUG_USER is not set
724# CONFIG_DEBUG_WAITQ is not set
725# CONFIG_DEBUG_ERRORS is not set 724# CONFIG_DEBUG_ERRORS is not set
726# CONFIG_DEBUG_LL is not set 725# CONFIG_DEBUG_LL is not set
727 726
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
index a4989f44baaa..b5e11aa2e290 100644
--- a/arch/arm/configs/pnx4008_defconfig
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -1604,7 +1604,6 @@ CONFIG_FRAME_POINTER=y
1604CONFIG_FORCED_INLINING=y 1604CONFIG_FORCED_INLINING=y
1605# CONFIG_RCU_TORTURE_TEST is not set 1605# CONFIG_RCU_TORTURE_TEST is not set
1606# CONFIG_DEBUG_USER is not set 1606# CONFIG_DEBUG_USER is not set
1607# CONFIG_DEBUG_WAITQ is not set
1608# CONFIG_DEBUG_ERRORS is not set 1607# CONFIG_DEBUG_ERRORS is not set
1609# CONFIG_DEBUG_LL is not set 1608# CONFIG_DEBUG_LL is not set
1610 1609
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
index b71d31a4bb56..46e5089df0ae 100644
--- a/arch/arm/configs/pxa255-idp_defconfig
+++ b/arch/arm/configs/pxa255-idp_defconfig
@@ -768,7 +768,6 @@ CONFIG_DEBUG_INFO=y
768# CONFIG_DEBUG_FS is not set 768# CONFIG_DEBUG_FS is not set
769CONFIG_FRAME_POINTER=y 769CONFIG_FRAME_POINTER=y
770CONFIG_DEBUG_USER=y 770CONFIG_DEBUG_USER=y
771# CONFIG_DEBUG_WAITQ is not set
772CONFIG_DEBUG_ERRORS=y 771CONFIG_DEBUG_ERRORS=y
773CONFIG_DEBUG_LL=y 772CONFIG_DEBUG_LL=y
774# CONFIG_DEBUG_ICEDCC is not set 773# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index ffd905ff19f1..fc39ba1a89f3 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -967,7 +967,6 @@ CONFIG_FORCED_INLINING=y
967# CONFIG_HEADERS_CHECK is not set 967# CONFIG_HEADERS_CHECK is not set
968# CONFIG_RCU_TORTURE_TEST is not set 968# CONFIG_RCU_TORTURE_TEST is not set
969CONFIG_DEBUG_USER=y 969CONFIG_DEBUG_USER=y
970# CONFIG_DEBUG_WAITQ is not set
971CONFIG_DEBUG_ERRORS=y 970CONFIG_DEBUG_ERRORS=y
972CONFIG_DEBUG_LL=y 971CONFIG_DEBUG_LL=y
973# CONFIG_DEBUG_ICEDCC is not set 972# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 3f1ec4e304f7..accbf529ce5b 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -759,7 +759,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
759# CONFIG_DEBUG_FS is not set 759# CONFIG_DEBUG_FS is not set
760CONFIG_FRAME_POINTER=y 760CONFIG_FRAME_POINTER=y
761CONFIG_DEBUG_USER=y 761CONFIG_DEBUG_USER=y
762# CONFIG_DEBUG_WAITQ is not set
763CONFIG_DEBUG_ERRORS=y 762CONFIG_DEBUG_ERRORS=y
764# CONFIG_DEBUG_LL is not set 763# CONFIG_DEBUG_LL is not set
765 764
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index b498afdc03b6..bc091264d354 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -910,7 +910,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
910# CONFIG_DEBUG_FS is not set 910# CONFIG_DEBUG_FS is not set
911CONFIG_FRAME_POINTER=y 911CONFIG_FRAME_POINTER=y
912CONFIG_DEBUG_USER=y 912CONFIG_DEBUG_USER=y
913# CONFIG_DEBUG_WAITQ is not set
914CONFIG_DEBUG_ERRORS=y 913CONFIG_DEBUG_ERRORS=y
915CONFIG_DEBUG_LL=y 914CONFIG_DEBUG_LL=y
916# CONFIG_DEBUG_ICEDCC is not set 915# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index c0152393e494..3b31a33d0080 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1319,7 +1319,6 @@ CONFIG_FORCED_INLINING=y
1319# CONFIG_HEADERS_CHECK is not set 1319# CONFIG_HEADERS_CHECK is not set
1320# CONFIG_RCU_TORTURE_TEST is not set 1320# CONFIG_RCU_TORTURE_TEST is not set
1321CONFIG_DEBUG_USER=y 1321CONFIG_DEBUG_USER=y
1322# CONFIG_DEBUG_WAITQ is not set
1323# CONFIG_DEBUG_ERRORS is not set 1322# CONFIG_DEBUG_ERRORS is not set
1324CONFIG_DEBUG_LL=y 1323CONFIG_DEBUG_LL=y
1325# CONFIG_DEBUG_ICEDCC is not set 1324# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index c48d17062262..9b6561d119af 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -965,7 +965,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
965# CONFIG_DEBUG_FS is not set 965# CONFIG_DEBUG_FS is not set
966CONFIG_FRAME_POINTER=y 966CONFIG_FRAME_POINTER=y
967CONFIG_DEBUG_USER=y 967CONFIG_DEBUG_USER=y
968# CONFIG_DEBUG_WAITQ is not set
969# CONFIG_DEBUG_ERRORS is not set 968# CONFIG_DEBUG_ERRORS is not set
970# CONFIG_DEBUG_LL is not set 969# CONFIG_DEBUG_LL is not set
971 970
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig
index 140056a3507f..03f783e696b3 100644
--- a/arch/arm/configs/simpad_defconfig
+++ b/arch/arm/configs/simpad_defconfig
@@ -934,7 +934,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
934# CONFIG_DEBUG_FS is not set 934# CONFIG_DEBUG_FS is not set
935CONFIG_FRAME_POINTER=y 935CONFIG_FRAME_POINTER=y
936CONFIG_DEBUG_USER=y 936CONFIG_DEBUG_USER=y
937# CONFIG_DEBUG_WAITQ is not set
938CONFIG_DEBUG_ERRORS=y 937CONFIG_DEBUG_ERRORS=y
939CONFIG_DEBUG_LL=y 938CONFIG_DEBUG_LL=y
940# CONFIG_DEBUG_ICEDCC is not set 939# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index bd03238968c1..aa7a01179500 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -1406,7 +1406,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
1406CONFIG_FRAME_POINTER=y 1406CONFIG_FRAME_POINTER=y
1407# CONFIG_RCU_TORTURE_TEST is not set 1407# CONFIG_RCU_TORTURE_TEST is not set
1408# CONFIG_DEBUG_USER is not set 1408# CONFIG_DEBUG_USER is not set
1409# CONFIG_DEBUG_WAITQ is not set
1410CONFIG_DEBUG_ERRORS=y 1409CONFIG_DEBUG_ERRORS=y
1411CONFIG_DEBUG_LL=y 1410CONFIG_DEBUG_LL=y
1412# CONFIG_DEBUG_ICEDCC is not set 1411# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index f7bf6ef27d19..48dca69addae 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -972,7 +972,6 @@ CONFIG_FRAME_POINTER=y
972CONFIG_FORCED_INLINING=y 972CONFIG_FORCED_INLINING=y
973# CONFIG_RCU_TORTURE_TEST is not set 973# CONFIG_RCU_TORTURE_TEST is not set
974CONFIG_DEBUG_USER=y 974CONFIG_DEBUG_USER=y
975# CONFIG_DEBUG_WAITQ is not set
976CONFIG_DEBUG_ERRORS=y 975CONFIG_DEBUG_ERRORS=y
977CONFIG_DEBUG_LL=y 976CONFIG_DEBUG_LL=y
978# CONFIG_DEBUG_ICEDCC is not set 977# CONFIG_DEBUG_ICEDCC is not set
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 1320a0efca73..ab06a86e85d5 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -24,7 +24,9 @@ obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
24obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o 24obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
25AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 25AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
26 26
27obj-$(CONFIG_IWMMXT) += iwmmxt.o iwmmxt-notifier.o 27obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
28obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
29obj-$(CONFIG_IWMMXT) += iwmmxt.o
28AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt 30AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
29 31
30ifneq ($(CONFIG_ARCH_EBSA110),y) 32ifneq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/kernel/apm.c b/arch/arm/kernel/apm.c
index ecf4f9472d94..a11fb9a40c04 100644
--- a/arch/arm/kernel/apm.c
+++ b/arch/arm/kernel/apm.c
@@ -12,7 +12,6 @@
12 */ 12 */
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/poll.h> 14#include <linux/poll.h>
15#include <linux/timer.h>
16#include <linux/slab.h> 15#include <linux/slab.h>
17#include <linux/proc_fs.h> 16#include <linux/proc_fs.h>
18#include <linux/miscdevice.h> 17#include <linux/miscdevice.h>
@@ -26,6 +25,7 @@
26#include <linux/init.h> 25#include <linux/init.h>
27#include <linux/completion.h> 26#include <linux/completion.h>
28#include <linux/kthread.h> 27#include <linux/kthread.h>
28#include <linux/delay.h>
29 29
30#include <asm/apm.h> /* apm_power_info */ 30#include <asm/apm.h> /* apm_power_info */
31#include <asm/system.h> 31#include <asm/system.h>
@@ -71,7 +71,8 @@ struct apm_user {
71#define SUSPEND_PENDING 1 /* suspend pending read */ 71#define SUSPEND_PENDING 1 /* suspend pending read */
72#define SUSPEND_READ 2 /* suspend read, pending ack */ 72#define SUSPEND_READ 2 /* suspend read, pending ack */
73#define SUSPEND_ACKED 3 /* suspend acked */ 73#define SUSPEND_ACKED 3 /* suspend acked */
74#define SUSPEND_DONE 4 /* suspend completed */ 74#define SUSPEND_WAIT 4 /* waiting for suspend */
75#define SUSPEND_DONE 5 /* suspend completed */
75 76
76 struct apm_queue queue; 77 struct apm_queue queue;
77}; 78};
@@ -101,6 +102,7 @@ static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait);
101static DEFINE_SPINLOCK(kapmd_queue_lock); 102static DEFINE_SPINLOCK(kapmd_queue_lock);
102static struct apm_queue kapmd_queue; 103static struct apm_queue kapmd_queue;
103 104
105static DEFINE_MUTEX(state_lock);
104 106
105static const char driver_version[] = "1.13"; /* no spaces */ 107static const char driver_version[] = "1.13"; /* no spaces */
106 108
@@ -148,38 +150,60 @@ static void queue_add_event(struct apm_queue *q, apm_event_t event)
148 q->events[q->event_head] = event; 150 q->events[q->event_head] = event;
149} 151}
150 152
151static void queue_event_one_user(struct apm_user *as, apm_event_t event) 153static void queue_event(apm_event_t event)
152{ 154{
153 if (as->suser && as->writer) { 155 struct apm_user *as;
154 switch (event) {
155 case APM_SYS_SUSPEND:
156 case APM_USER_SUSPEND:
157 /*
158 * If this user already has a suspend pending,
159 * don't queue another one.
160 */
161 if (as->suspend_state != SUSPEND_NONE)
162 return;
163 156
164 as->suspend_state = SUSPEND_PENDING; 157 down_read(&user_list_lock);
165 suspends_pending++; 158 list_for_each_entry(as, &apm_user_list, list) {
166 break; 159 if (as->reader)
167 } 160 queue_add_event(&as->queue, event);
168 } 161 }
169 queue_add_event(&as->queue, event); 162 up_read(&user_list_lock);
163 wake_up_interruptible(&apm_waitqueue);
170} 164}
171 165
172static void queue_event(apm_event_t event, struct apm_user *sender) 166/*
167 * queue_suspend_event - queue an APM suspend event.
168 *
169 * Check that we're in a state where we can suspend. If not,
170 * return -EBUSY. Otherwise, queue an event to all "writer"
171 * users. If there are no "writer" users, return '1' to
172 * indicate that we can immediately suspend.
173 */
174static int queue_suspend_event(apm_event_t event, struct apm_user *sender)
173{ 175{
174 struct apm_user *as; 176 struct apm_user *as;
177 int ret = 1;
175 178
179 mutex_lock(&state_lock);
176 down_read(&user_list_lock); 180 down_read(&user_list_lock);
181
182 /*
183 * If a thread is still processing, we can't suspend, so reject
184 * the request.
185 */
177 list_for_each_entry(as, &apm_user_list, list) { 186 list_for_each_entry(as, &apm_user_list, list) {
178 if (as != sender && as->reader) 187 if (as != sender && as->reader && as->writer && as->suser &&
179 queue_event_one_user(as, event); 188 as->suspend_state != SUSPEND_NONE) {
189 ret = -EBUSY;
190 goto out;
191 }
180 } 192 }
193
194 list_for_each_entry(as, &apm_user_list, list) {
195 if (as != sender && as->reader && as->writer && as->suser) {
196 as->suspend_state = SUSPEND_PENDING;
197 suspends_pending++;
198 queue_add_event(&as->queue, event);
199 ret = 0;
200 }
201 }
202 out:
181 up_read(&user_list_lock); 203 up_read(&user_list_lock);
204 mutex_unlock(&state_lock);
182 wake_up_interruptible(&apm_waitqueue); 205 wake_up_interruptible(&apm_waitqueue);
206 return ret;
183} 207}
184 208
185static void apm_suspend(void) 209static void apm_suspend(void)
@@ -191,17 +215,22 @@ static void apm_suspend(void)
191 * Anyone on the APM queues will think we're still suspended. 215 * Anyone on the APM queues will think we're still suspended.
192 * Send a message so everyone knows we're now awake again. 216 * Send a message so everyone knows we're now awake again.
193 */ 217 */
194 queue_event(APM_NORMAL_RESUME, NULL); 218 queue_event(APM_NORMAL_RESUME);
195 219
196 /* 220 /*
197 * Finally, wake up anyone who is sleeping on the suspend. 221 * Finally, wake up anyone who is sleeping on the suspend.
198 */ 222 */
223 mutex_lock(&state_lock);
199 down_read(&user_list_lock); 224 down_read(&user_list_lock);
200 list_for_each_entry(as, &apm_user_list, list) { 225 list_for_each_entry(as, &apm_user_list, list) {
201 as->suspend_result = err; 226 if (as->suspend_state == SUSPEND_WAIT ||
202 as->suspend_state = SUSPEND_DONE; 227 as->suspend_state == SUSPEND_ACKED) {
228 as->suspend_result = err;
229 as->suspend_state = SUSPEND_DONE;
230 }
203 } 231 }
204 up_read(&user_list_lock); 232 up_read(&user_list_lock);
233 mutex_unlock(&state_lock);
205 234
206 wake_up(&apm_suspend_waitqueue); 235 wake_up(&apm_suspend_waitqueue);
207} 236}
@@ -227,8 +256,11 @@ static ssize_t apm_read(struct file *fp, char __user *buf, size_t count, loff_t
227 if (copy_to_user(buf, &event, sizeof(event))) 256 if (copy_to_user(buf, &event, sizeof(event)))
228 break; 257 break;
229 258
230 if (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND) 259 mutex_lock(&state_lock);
260 if (as->suspend_state == SUSPEND_PENDING &&
261 (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND))
231 as->suspend_state = SUSPEND_READ; 262 as->suspend_state = SUSPEND_READ;
263 mutex_unlock(&state_lock);
232 264
233 buf += sizeof(event); 265 buf += sizeof(event);
234 i -= sizeof(event); 266 i -= sizeof(event);
@@ -270,9 +302,13 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
270 302
271 switch (cmd) { 303 switch (cmd) {
272 case APM_IOC_SUSPEND: 304 case APM_IOC_SUSPEND:
305 mutex_lock(&state_lock);
306
273 as->suspend_result = -EINTR; 307 as->suspend_result = -EINTR;
274 308
275 if (as->suspend_state == SUSPEND_READ) { 309 if (as->suspend_state == SUSPEND_READ) {
310 int pending;
311
276 /* 312 /*
277 * If we read a suspend command from /dev/apm_bios, 313 * If we read a suspend command from /dev/apm_bios,
278 * then the corresponding APM_IOC_SUSPEND ioctl is 314 * then the corresponding APM_IOC_SUSPEND ioctl is
@@ -280,47 +316,73 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
280 */ 316 */
281 as->suspend_state = SUSPEND_ACKED; 317 as->suspend_state = SUSPEND_ACKED;
282 suspends_pending--; 318 suspends_pending--;
319 pending = suspends_pending == 0;
320 mutex_unlock(&state_lock);
321
322 /*
323 * If there are no further acknowledges required,
324 * suspend the system.
325 */
326 if (pending)
327 apm_suspend();
328
329 /*
330 * Wait for the suspend/resume to complete. If there
331 * are pending acknowledges, we wait here for them.
332 *
333 * Note: we need to ensure that the PM subsystem does
334 * not kick us out of the wait when it suspends the
335 * threads.
336 */
337 flags = current->flags;
338 current->flags |= PF_NOFREEZE;
339
340 wait_event(apm_suspend_waitqueue,
341 as->suspend_state == SUSPEND_DONE);
283 } else { 342 } else {
343 as->suspend_state = SUSPEND_WAIT;
344 mutex_unlock(&state_lock);
345
284 /* 346 /*
285 * Otherwise it is a request to suspend the system. 347 * Otherwise it is a request to suspend the system.
286 * Queue an event for all readers, and expect an 348 * Queue an event for all readers, and expect an
287 * acknowledge from all writers who haven't already 349 * acknowledge from all writers who haven't already
288 * acknowledged. 350 * acknowledged.
289 */ 351 */
290 queue_event(APM_USER_SUSPEND, as); 352 err = queue_suspend_event(APM_USER_SUSPEND, as);
291 } 353 if (err < 0) {
292 354 /*
293 /* 355 * Avoid taking the lock here - this
294 * If there are no further acknowledges required, suspend 356 * should be fine.
295 * the system. 357 */
296 */ 358 as->suspend_state = SUSPEND_NONE;
297 if (suspends_pending == 0) 359 break;
298 apm_suspend(); 360 }
361
362 if (err > 0)
363 apm_suspend();
299 364
300 /* 365 /*
301 * Wait for the suspend/resume to complete. If there are 366 * Wait for the suspend/resume to complete. If there
302 * pending acknowledges, we wait here for them. 367 * are pending acknowledges, we wait here for them.
303 * 368 *
304 * Note that we need to ensure that the PM subsystem does 369 * Note: we need to ensure that the PM subsystem does
305 * not kick us out of the wait when it suspends the threads. 370 * not kick us out of the wait when it suspends the
306 */ 371 * threads.
307 flags = current->flags; 372 */
308 current->flags |= PF_NOFREEZE; 373 flags = current->flags;
374 current->flags |= PF_NOFREEZE;
309 375
310 /*
311 * Note: do not allow a thread which is acking the suspend
312 * to escape until the resume is complete.
313 */
314 if (as->suspend_state == SUSPEND_ACKED)
315 wait_event(apm_suspend_waitqueue,
316 as->suspend_state == SUSPEND_DONE);
317 else
318 wait_event_interruptible(apm_suspend_waitqueue, 376 wait_event_interruptible(apm_suspend_waitqueue,
319 as->suspend_state == SUSPEND_DONE); 377 as->suspend_state == SUSPEND_DONE);
378 }
320 379
321 current->flags = flags; 380 current->flags = flags;
381
382 mutex_lock(&state_lock);
322 err = as->suspend_result; 383 err = as->suspend_result;
323 as->suspend_state = SUSPEND_NONE; 384 as->suspend_state = SUSPEND_NONE;
385 mutex_unlock(&state_lock);
324 break; 386 break;
325 } 387 }
326 388
@@ -330,6 +392,8 @@ apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
330static int apm_release(struct inode * inode, struct file * filp) 392static int apm_release(struct inode * inode, struct file * filp)
331{ 393{
332 struct apm_user *as = filp->private_data; 394 struct apm_user *as = filp->private_data;
395 int pending = 0;
396
333 filp->private_data = NULL; 397 filp->private_data = NULL;
334 398
335 down_write(&user_list_lock); 399 down_write(&user_list_lock);
@@ -342,11 +406,14 @@ static int apm_release(struct inode * inode, struct file * filp)
342 * need to balance suspends_pending, which means the 406 * need to balance suspends_pending, which means the
343 * possibility of sleeping. 407 * possibility of sleeping.
344 */ 408 */
409 mutex_lock(&state_lock);
345 if (as->suspend_state != SUSPEND_NONE) { 410 if (as->suspend_state != SUSPEND_NONE) {
346 suspends_pending -= 1; 411 suspends_pending -= 1;
347 if (suspends_pending == 0) 412 pending = suspends_pending == 0;
348 apm_suspend();
349 } 413 }
414 mutex_unlock(&state_lock);
415 if (pending)
416 apm_suspend();
350 417
351 kfree(as); 418 kfree(as);
352 return 0; 419 return 0;
@@ -470,6 +537,7 @@ static int kapmd(void *arg)
470{ 537{
471 do { 538 do {
472 apm_event_t event; 539 apm_event_t event;
540 int ret;
473 541
474 wait_event_interruptible(kapmd_wait, 542 wait_event_interruptible(kapmd_wait,
475 !queue_empty(&kapmd_queue) || kthread_should_stop()); 543 !queue_empty(&kapmd_queue) || kthread_should_stop());
@@ -489,13 +557,20 @@ static int kapmd(void *arg)
489 557
490 case APM_LOW_BATTERY: 558 case APM_LOW_BATTERY:
491 case APM_POWER_STATUS_CHANGE: 559 case APM_POWER_STATUS_CHANGE:
492 queue_event(event, NULL); 560 queue_event(event);
493 break; 561 break;
494 562
495 case APM_USER_SUSPEND: 563 case APM_USER_SUSPEND:
496 case APM_SYS_SUSPEND: 564 case APM_SYS_SUSPEND:
497 queue_event(event, NULL); 565 ret = queue_suspend_event(event, NULL);
498 if (suspends_pending == 0) 566 if (ret < 0) {
567 /*
568 * We were busy. Try again in 50ms.
569 */
570 queue_add_event(&kapmd_queue, event);
571 msleep(50);
572 }
573 if (ret > 0)
499 apm_suspend(); 574 apm_suspend();
500 break; 575 break;
501 576
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index cc2d58d028e1..3c078e346753 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -15,6 +15,7 @@
15#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
16#include <asm/thread_info.h> 16#include <asm/thread_info.h>
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <asm/procinfo.h>
18 19
19/* 20/*
20 * Make sure that the compiler and target are compatible. 21 * Make sure that the compiler and target are compatible.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 3173924a9b60..e8f74363328c 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -331,6 +331,19 @@
331 CALL(sys_mbind) 331 CALL(sys_mbind)
332/* 320 */ CALL(sys_get_mempolicy) 332/* 320 */ CALL(sys_get_mempolicy)
333 CALL(sys_set_mempolicy) 333 CALL(sys_set_mempolicy)
334 CALL(sys_openat)
335 CALL(sys_mkdirat)
336 CALL(sys_mknodat)
337/* 325 */ CALL(sys_fchownat)
338 CALL(sys_futimesat)
339 CALL(sys_fstatat64)
340 CALL(sys_unlinkat)
341 CALL(sys_renameat)
342/* 330 */ CALL(sys_linkat)
343 CALL(sys_symlinkat)
344 CALL(sys_readlinkat)
345 CALL(sys_fchmodat)
346 CALL(sys_faccessat)
334#ifndef syscalls_counted 347#ifndef syscalls_counted
335.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 348.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
336#define syscalls_counted 349#define syscalls_counted
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index b27513a0f11e..a786f769035d 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -529,7 +529,7 @@ static void ecard_dump_irq_state(void)
529 } 529 }
530} 530}
531 531
532static void ecard_check_lockup(struct irqdesc *desc) 532static void ecard_check_lockup(struct irq_desc *desc)
533{ 533{
534 static unsigned long last; 534 static unsigned long last;
535 static int lockup; 535 static int lockup;
@@ -567,7 +567,7 @@ static void ecard_check_lockup(struct irqdesc *desc)
567} 567}
568 568
569static void 569static void
570ecard_irq_handler(unsigned int irq, struct irqdesc *desc) 570ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
571{ 571{
572 ecard_t *ec; 572 ecard_t *ec;
573 int called = 0; 573 int called = 0;
@@ -585,7 +585,7 @@ ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
585 pending = ecard_default_ops.irqpending(ec); 585 pending = ecard_default_ops.irqpending(ec);
586 586
587 if (pending) { 587 if (pending) {
588 struct irqdesc *d = irq_desc + ec->irq; 588 struct irq_desc *d = irq_desc + ec->irq;
589 desc_handle_irq(ec->irq, d); 589 desc_handle_irq(ec->irq, d);
590 called ++; 590 called ++;
591 } 591 }
@@ -609,7 +609,7 @@ static unsigned char first_set[] =
609}; 609};
610 610
611static void 611static void
612ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc) 612ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
613{ 613{
614 const unsigned int statusmask = 15; 614 const unsigned int statusmask = 15;
615 unsigned int status; 615 unsigned int status;
@@ -1022,7 +1022,7 @@ ecard_probe(int slot, card_type_t type)
1022 if (slot < 8) { 1022 if (slot < 8) {
1023 ec->irq = 32 + slot; 1023 ec->irq = 32 + slot;
1024 set_irq_chip(ec->irq, &ecard_chip); 1024 set_irq_chip(ec->irq, &ecard_chip);
1025 set_irq_handler(ec->irq, do_level_IRQ); 1025 set_irq_handler(ec->irq, handle_level_irq);
1026 set_irq_flags(ec->irq, IRQF_VALID); 1026 set_irq_flags(ec->irq, IRQF_VALID);
1027 } 1027 }
1028 1028
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bd623b73445f..2db42b18f53f 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -589,10 +589,6 @@ ENTRY(__switch_to)
589 strex r5, r4, [ip] @ Clear exclusive monitor 589 strex r5, r4, [ip] @ Clear exclusive monitor
590#endif 590#endif
591#endif 591#endif
592#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
593 mra r4, r5, acc0
594 stmia ip, {r4, r5}
595#endif
596#if defined(CONFIG_HAS_TLS_REG) 592#if defined(CONFIG_HAS_TLS_REG)
597 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 593 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
598#elif !defined(CONFIG_TLS_REG_EMUL) 594#elif !defined(CONFIG_TLS_REG_EMUL)
@@ -602,11 +598,6 @@ ENTRY(__switch_to)
602#ifdef CONFIG_MMU 598#ifdef CONFIG_MMU
603 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 599 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
604#endif 600#endif
605#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
606 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra
607 ldmib r4, {r4, r5}
608 mar acc0, r4, r5
609#endif
610 mov r5, r0 601 mov r5, r0
611 add r4, r2, #TI_CPU_SAVE 602 add r4, r2, #TI_CPU_SAVE
612 ldr r0, =thread_notify_head 603 ldr r0, =thread_notify_head
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index f359a189dcf2..0119c0d5f978 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -16,7 +16,6 @@
16 16
17#include <asm/assembler.h> 17#include <asm/assembler.h>
18#include <asm/mach-types.h> 18#include <asm/mach-types.h>
19#include <asm/procinfo.h>
20#include <asm/ptrace.h> 19#include <asm/ptrace.h>
21#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
22#include <asm/thread_info.h> 21#include <asm/thread_info.h>
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index ebc3e74a7947..d994561816a1 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -16,37 +16,37 @@
16 16
17#include <asm/assembler.h> 17#include <asm/assembler.h>
18#include <asm/domain.h> 18#include <asm/domain.h>
19#include <asm/procinfo.h>
20#include <asm/ptrace.h> 19#include <asm/ptrace.h>
21#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
22#include <asm/memory.h> 21#include <asm/memory.h>
23#include <asm/thread_info.h> 22#include <asm/thread_info.h>
24#include <asm/system.h> 23#include <asm/system.h>
25 24
26#define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET) 25#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
26#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
27 27
28/* 28/*
29 * swapper_pg_dir is the virtual address of the initial page table. 29 * swapper_pg_dir is the virtual address of the initial page table.
30 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must 30 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
31 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect 31 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
32 * the least significant 16 bits to be 0x8000, but we could probably 32 * the least significant 16 bits to be 0x8000, but we could probably
33 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000. 33 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
34 */ 34 */
35#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000 35#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
36#error KERNEL_RAM_ADDR must start at 0xXXXX8000 36#error KERNEL_RAM_VADDR must start at 0xXXXX8000
37#endif 37#endif
38 38
39 .globl swapper_pg_dir 39 .globl swapper_pg_dir
40 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000 40 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
41 41
42 .macro pgtbl, rd 42 .macro pgtbl, rd
43 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000)) 43 ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
44 .endm 44 .endm
45 45
46#ifdef CONFIG_XIP_KERNEL 46#ifdef CONFIG_XIP_KERNEL
47#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 47#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
48#else 48#else
49#define TEXTADDR KERNEL_RAM_ADDR 49#define TEXTADDR KERNEL_RAM_VADDR
50#endif 50#endif
51 51
52/* 52/*
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c4ff1cbe334..ec01f08f5642 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -112,7 +112,7 @@ static struct irq_desc bad_irq_desc = {
112asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) 112asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
113{ 113{
114 struct pt_regs *old_regs = set_irq_regs(regs); 114 struct pt_regs *old_regs = set_irq_regs(regs);
115 struct irqdesc *desc = irq_desc + irq; 115 struct irq_desc *desc = irq_desc + irq;
116 116
117 /* 117 /*
118 * Some hardware gives randomly wrong interrupts. Rather 118 * Some hardware gives randomly wrong interrupts. Rather
@@ -134,7 +134,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
134 134
135void set_irq_flags(unsigned int irq, unsigned int iflags) 135void set_irq_flags(unsigned int irq, unsigned int iflags)
136{ 136{
137 struct irqdesc *desc; 137 struct irq_desc *desc;
138 unsigned long flags; 138 unsigned long flags;
139 139
140 if (irq >= NR_IRQS) { 140 if (irq >= NR_IRQS) {
@@ -171,7 +171,7 @@ void __init init_IRQ(void)
171 171
172#ifdef CONFIG_HOTPLUG_CPU 172#ifdef CONFIG_HOTPLUG_CPU
173 173
174static void route_irq(struct irqdesc *desc, unsigned int irq, unsigned int cpu) 174static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
175{ 175{
176 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); 176 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu);
177 177
@@ -190,7 +190,7 @@ void migrate_irqs(void)
190 unsigned int i, cpu = smp_processor_id(); 190 unsigned int i, cpu = smp_processor_id();
191 191
192 for (i = 0; i < NR_IRQS; i++) { 192 for (i = 0; i < NR_IRQS; i++) {
193 struct irqdesc *desc = irq_desc + i; 193 struct irq_desc *desc = irq_desc + i;
194 194
195 if (desc->cpu == cpu) { 195 if (desc->cpu == cpu) {
196 unsigned int newcpu = any_online_cpu(desc->affinity); 196 unsigned int newcpu = any_online_cpu(desc->affinity);
diff --git a/arch/arm/kernel/iwmmxt-notifier.c b/arch/arm/kernel/iwmmxt-notifier.c
deleted file mode 100644
index 0d1a1db40062..000000000000
--- a/arch/arm/kernel/iwmmxt-notifier.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * linux/arch/arm/kernel/iwmmxt-notifier.c
3 *
4 * XScale iWMMXt (Concan) context switching and handling
5 *
6 * Initial code:
7 * Copyright (c) 2003, Intel Corporation
8 *
9 * Full lazy switching support, optimizations and more, by Nicolas Pitre
10 * Copyright (c) 2003-2004, MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/init.h>
23#include <asm/thread_notify.h>
24#include <asm/io.h>
25
26static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
27{
28 struct thread_info *thread = t;
29
30 switch (cmd) {
31 case THREAD_NOTIFY_FLUSH:
32 /*
33 * flush_thread() zeroes thread->fpstate, so no need
34 * to do anything here.
35 *
36 * FALLTHROUGH: Ensure we don't try to overwrite our newly
37 * initialised state information on the first fault.
38 */
39
40 case THREAD_NOTIFY_RELEASE:
41 iwmmxt_task_release(thread);
42 break;
43
44 case THREAD_NOTIFY_SWITCH:
45 iwmmxt_task_switch(thread);
46 break;
47 }
48
49 return NOTIFY_DONE;
50}
51
52static struct notifier_block iwmmxt_notifier_block = {
53 .notifier_call = iwmmxt_do,
54};
55
56static int __init iwmmxt_init(void)
57{
58 thread_register_notifier(&iwmmxt_notifier_block);
59
60 return 0;
61}
62
63late_initcall(iwmmxt_init);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index bf35c178a877..a9e8f7e55fd6 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -281,67 +281,6 @@ void show_fpregs(struct user_fp *regs)
281} 281}
282 282
283/* 283/*
284 * Task structure and kernel stack allocation.
285 */
286struct thread_info_list {
287 unsigned long *head;
288 unsigned int nr;
289};
290
291static DEFINE_PER_CPU(struct thread_info_list, thread_info_list) = { NULL, 0 };
292
293#define EXTRA_TASK_STRUCT 4
294
295struct thread_info *alloc_thread_info(struct task_struct *task)
296{
297 struct thread_info *thread = NULL;
298
299 if (EXTRA_TASK_STRUCT) {
300 struct thread_info_list *th = &get_cpu_var(thread_info_list);
301 unsigned long *p = th->head;
302
303 if (p) {
304 th->head = (unsigned long *)p[0];
305 th->nr -= 1;
306 }
307 put_cpu_var(thread_info_list);
308
309 thread = (struct thread_info *)p;
310 }
311
312 if (!thread)
313 thread = (struct thread_info *)
314 __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
315
316#ifdef CONFIG_DEBUG_STACK_USAGE
317 /*
318 * The stack must be cleared if you want SYSRQ-T to
319 * give sensible stack usage information
320 */
321 if (thread)
322 memzero(thread, THREAD_SIZE);
323#endif
324 return thread;
325}
326
327void free_thread_info(struct thread_info *thread)
328{
329 if (EXTRA_TASK_STRUCT) {
330 struct thread_info_list *th = &get_cpu_var(thread_info_list);
331 if (th->nr < EXTRA_TASK_STRUCT) {
332 unsigned long *p = (unsigned long *)thread;
333 p[0] = (unsigned long)th->head;
334 th->head = p;
335 th->nr += 1;
336 put_cpu_var(thread_info_list);
337 return;
338 }
339 put_cpu_var(thread_info_list);
340 }
341 free_pages((unsigned long)thread, THREAD_SIZE_ORDER);
342}
343
344/*
345 * Free current thread data structures etc.. 284 * Free current thread data structures etc..
346 */ 285 */
347void exit_thread(void) 286void exit_thread(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 29efc9f82057..cf2bd4242803 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -354,12 +354,6 @@ static void __init setup_processor(void)
354#ifndef CONFIG_ARM_THUMB 354#ifndef CONFIG_ARM_THUMB
355 elf_hwcap &= ~HWCAP_THUMB; 355 elf_hwcap &= ~HWCAP_THUMB;
356#endif 356#endif
357#ifndef CONFIG_VFP
358 elf_hwcap &= ~HWCAP_VFP;
359#endif
360#ifndef CONFIG_IWMMXT
361 elf_hwcap &= ~HWCAP_IWMMXT;
362#endif
363 357
364 cpu_proc_init(); 358 cpu_proc_init();
365} 359}
@@ -441,16 +435,19 @@ __early_param("initrd=", early_initrd);
441 435
442static void __init arm_add_memory(unsigned long start, unsigned long size) 436static void __init arm_add_memory(unsigned long start, unsigned long size)
443{ 437{
438 struct membank *bank;
439
444 /* 440 /*
445 * Ensure that start/size are aligned to a page boundary. 441 * Ensure that start/size are aligned to a page boundary.
446 * Size is appropriately rounded down, start is rounded up. 442 * Size is appropriately rounded down, start is rounded up.
447 */ 443 */
448 size -= start & ~PAGE_MASK; 444 size -= start & ~PAGE_MASK;
449 445
450 meminfo.bank[meminfo.nr_banks].start = PAGE_ALIGN(start); 446 bank = &meminfo.bank[meminfo.nr_banks++];
451 meminfo.bank[meminfo.nr_banks].size = size & PAGE_MASK; 447
452 meminfo.bank[meminfo.nr_banks].node = PHYS_TO_NID(start); 448 bank->start = PAGE_ALIGN(start);
453 meminfo.nr_banks += 1; 449 bank->size = size & PAGE_MASK;
450 bank->node = PHYS_TO_NID(start);
454} 451}
455 452
456/* 453/*
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 48cf7fffddf2..3843d3bab2dd 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -11,7 +11,9 @@
11#include <linux/signal.h> 11#include <linux/signal.h>
12#include <linux/ptrace.h> 12#include <linux/ptrace.h>
13#include <linux/personality.h> 13#include <linux/personality.h>
14#include <linux/freezer.h>
14 15
16#include <asm/elf.h>
15#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
16#include <asm/ucontext.h> 18#include <asm/ucontext.h>
17#include <asm/uaccess.h> 19#include <asm/uaccess.h>
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index bede380c07a9..042a12982e98 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -631,12 +631,9 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs)
631 notify_die("unknown data abort code", regs, &info, instr, 0); 631 notify_die("unknown data abort code", regs, &info, instr, 0);
632} 632}
633 633
634void __attribute__((noreturn)) __bug(const char *file, int line, void *data) 634void __attribute__((noreturn)) __bug(const char *file, int line)
635{ 635{
636 printk(KERN_CRIT"kernel BUG at %s:%d!", file, line); 636 printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line);
637 if (data)
638 printk(" - extra data = %p", data);
639 printk("\n");
640 *(int *)0 = 0; 637 *(int *)0 = 0;
641 638
642 /* Avoid "noreturn function does return" */ 639 /* Avoid "noreturn function does return" */
diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c
new file mode 100644
index 000000000000..180000bfdc8f
--- /dev/null
+++ b/arch/arm/kernel/xscale-cp0.c
@@ -0,0 +1,179 @@
1/*
2 * linux/arch/arm/kernel/xscale-cp0.c
3 *
4 * XScale DSP and iWMMXt coprocessor context switching and handling
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/init.h>
17#include <asm/thread_notify.h>
18#include <asm/io.h>
19
20static inline void dsp_save_state(u32 *state)
21{
22 __asm__ __volatile__ (
23 "mrrc p0, 0, %0, %1, c0\n"
24 : "=r" (state[0]), "=r" (state[1]));
25}
26
27static inline void dsp_load_state(u32 *state)
28{
29 __asm__ __volatile__ (
30 "mcrr p0, 0, %0, %1, c0\n"
31 : : "r" (state[0]), "r" (state[1]));
32}
33
34static int dsp_do(struct notifier_block *self, unsigned long cmd, void *t)
35{
36 struct thread_info *thread = t;
37
38 switch (cmd) {
39 case THREAD_NOTIFY_FLUSH:
40 thread->cpu_context.extra[0] = 0;
41 thread->cpu_context.extra[1] = 0;
42 break;
43
44 case THREAD_NOTIFY_SWITCH:
45 dsp_save_state(current_thread_info()->cpu_context.extra);
46 dsp_load_state(thread->cpu_context.extra);
47 break;
48 }
49
50 return NOTIFY_DONE;
51}
52
53static struct notifier_block dsp_notifier_block = {
54 .notifier_call = dsp_do,
55};
56
57
58#ifdef CONFIG_IWMMXT
59static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
60{
61 struct thread_info *thread = t;
62
63 switch (cmd) {
64 case THREAD_NOTIFY_FLUSH:
65 /*
66 * flush_thread() zeroes thread->fpstate, so no need
67 * to do anything here.
68 *
69 * FALLTHROUGH: Ensure we don't try to overwrite our newly
70 * initialised state information on the first fault.
71 */
72
73 case THREAD_NOTIFY_RELEASE:
74 iwmmxt_task_release(thread);
75 break;
76
77 case THREAD_NOTIFY_SWITCH:
78 iwmmxt_task_switch(thread);
79 break;
80 }
81
82 return NOTIFY_DONE;
83}
84
85static struct notifier_block iwmmxt_notifier_block = {
86 .notifier_call = iwmmxt_do,
87};
88#endif
89
90
91static u32 __init xscale_cp_access_read(void)
92{
93 u32 value;
94
95 __asm__ __volatile__ (
96 "mrc p15, 0, %0, c15, c1, 0\n\t"
97 : "=r" (value));
98
99 return value;
100}
101
102static void __init xscale_cp_access_write(u32 value)
103{
104 u32 temp;
105
106 __asm__ __volatile__ (
107 "mcr p15, 0, %1, c15, c1, 0\n\t"
108 "mrc p15, 0, %0, c15, c1, 0\n\t"
109 "mov %0, %0\n\t"
110 "sub pc, pc, #4\n\t"
111 : "=r" (temp) : "r" (value));
112}
113
114/*
115 * Detect whether we have a MAC coprocessor (40 bit register) or an
116 * iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000
117 * into a coprocessor register and reading it back, and checking
118 * whether the upper word survived intact.
119 */
120static int __init cpu_has_iwmmxt(void)
121{
122 u32 lo;
123 u32 hi;
124
125 /*
126 * This sequence is interpreted by the DSP coprocessor as:
127 * mar acc0, %2, %3
128 * mra %0, %1, acc0
129 *
130 * And by the iWMMXt coprocessor as:
131 * tmcrr wR0, %2, %3
132 * tmrrc %0, %1, wR0
133 */
134 __asm__ __volatile__ (
135 "mcrr p0, 0, %2, %3, c0\n"
136 "mrrc p0, 0, %0, %1, c0\n"
137 : "=r" (lo), "=r" (hi)
138 : "r" (0), "r" (0x100));
139
140 return !!hi;
141}
142
143
144/*
145 * If we detect that the CPU has iWMMXt (and CONFIG_IWMMXT=y), we
146 * disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
147 * switch code handle iWMMXt context switching. If on the other
148 * hand the CPU has a DSP coprocessor, we keep access to CP0 enabled
149 * all the time, and save/restore acc0 on context switch in non-lazy
150 * fashion.
151 */
152static int __init xscale_cp0_init(void)
153{
154 u32 cp_access;
155
156 cp_access = xscale_cp_access_read() & ~3;
157 xscale_cp_access_write(cp_access | 1);
158
159 if (cpu_has_iwmmxt()) {
160#ifndef CONFIG_IWMMXT
161 printk(KERN_WARNING "CAUTION: XScale iWMMXt coprocessor "
162 "detected, but kernel support is missing.\n");
163#else
164 printk(KERN_INFO "XScale iWMMXt coprocessor detected.\n");
165 elf_hwcap |= HWCAP_IWMMXT;
166 thread_register_notifier(&iwmmxt_notifier_block);
167#endif
168 } else {
169 printk(KERN_INFO "XScale DSP coprocessor detected.\n");
170 thread_register_notifier(&dsp_notifier_block);
171 cp_access |= 1;
172 }
173
174 xscale_cp_access_write(cp_access);
175
176 return 0;
177}
178
179late_initcall(xscale_cp0_init);
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
index fe3d297d682d..a950160fcfb6 100644
--- a/arch/arm/mach-aaec2000/core.c
+++ b/arch/arm/mach-aaec2000/core.c
@@ -82,7 +82,7 @@ static void aaec2000_int_unmask(unsigned int irq)
82 IRQ_INTENS |= (1 << irq); 82 IRQ_INTENS |= (1 << irq);
83} 83}
84 84
85static struct irqchip aaec2000_irq_chip = { 85static struct irq_chip aaec2000_irq_chip = {
86 .ack = aaec2000_int_ack, 86 .ack = aaec2000_int_ack,
87 .mask = aaec2000_int_mask, 87 .mask = aaec2000_int_mask,
88 .unmask = aaec2000_int_unmask, 88 .unmask = aaec2000_int_unmask,
@@ -93,7 +93,7 @@ void __init aaec2000_init_irq(void)
93 unsigned int i; 93 unsigned int i;
94 94
95 for (i = 0; i < NR_IRQS; i++) { 95 for (i = 0; i < NR_IRQS; i++) {
96 set_irq_handler(i, do_level_IRQ); 96 set_irq_handler(i, handle_level_irq);
97 set_irq_chip(i, &aaec2000_irq_chip); 97 set_irq_chip(i, &aaec2000_irq_chip);
98 set_irq_flags(i, IRQF_VALID); 98 set_irq_flags(i, IRQF_VALID);
99 } 99 }
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index e76422761db3..3f188508c391 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -334,10 +334,10 @@ static struct irq_chip gpio_irqchip = {
334 .set_wake = gpio_irq_set_wake, 334 .set_wake = gpio_irq_set_wake,
335}; 335};
336 336
337static void gpio_irq_handler(unsigned irq, struct irqdesc *desc) 337static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
338{ 338{
339 unsigned pin; 339 unsigned pin;
340 struct irqdesc *gpio; 340 struct irq_desc *gpio;
341 void __iomem *pio; 341 void __iomem *pio;
342 u32 isr; 342 u32 isr;
343 343
@@ -398,7 +398,7 @@ void __init at91_gpio_irq_setup(void)
398 __raw_writel(~0, controller + PIO_IDR); 398 __raw_writel(~0, controller + PIO_IDR);
399 399
400 set_irq_data(id, (void *) pin); 400 set_irq_data(id, (void *) pin);
401 set_irq_chipdata(id, controller); 401 set_irq_chip_data(id, controller);
402 402
403 for (i = 0; i < 32; i++, pin++) { 403 for (i = 0; i < 32; i++, pin++) {
404 /* 404 /*
@@ -406,7 +406,7 @@ void __init at91_gpio_irq_setup(void)
406 * shorter, and the AIC handles interupts sanely. 406 * shorter, and the AIC handles interupts sanely.
407 */ 407 */
408 set_irq_chip(pin, &gpio_irqchip); 408 set_irq_chip(pin, &gpio_irqchip);
409 set_irq_handler(pin, do_simple_IRQ); 409 set_irq_handler(pin, handle_simple_irq);
410 set_irq_flags(pin, IRQF_VALID); 410 set_irq_flags(pin, IRQF_VALID);
411 } 411 }
412 412
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index 2cea07a34a85..2148daafd29c 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -145,7 +145,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
145 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); 145 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
146 146
147 set_irq_chip(i, &at91_aic_chip); 147 set_irq_chip(i, &at91_aic_chip);
148 set_irq_handler(i, do_level_IRQ); 148 set_irq_handler(i, handle_level_irq);
149 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 149 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
150 150
151 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ 151 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 7ee926e5bad2..ca102960f528 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -63,7 +63,7 @@ static void int1_unmask(unsigned int irq)
63 clps_writel(intmr1, INTMR1); 63 clps_writel(intmr1, INTMR1);
64} 64}
65 65
66static struct irqchip int1_chip = { 66static struct irq_chip int1_chip = {
67 .ack = int1_ack, 67 .ack = int1_ack,
68 .mask = int1_mask, 68 .mask = int1_mask,
69 .unmask = int1_unmask, 69 .unmask = int1_unmask,
@@ -100,7 +100,7 @@ static void int2_unmask(unsigned int irq)
100 clps_writel(intmr2, INTMR2); 100 clps_writel(intmr2, INTMR2);
101} 101}
102 102
103static struct irqchip int2_chip = { 103static struct irq_chip int2_chip = {
104 .ack = int2_ack, 104 .ack = int2_ack,
105 .mask = int2_mask, 105 .mask = int2_mask,
106 .unmask = int2_unmask, 106 .unmask = int2_unmask,
@@ -112,12 +112,12 @@ void __init clps711x_init_irq(void)
112 112
113 for (i = 0; i < NR_IRQS; i++) { 113 for (i = 0; i < NR_IRQS; i++) {
114 if (INT1_IRQS & (1 << i)) { 114 if (INT1_IRQS & (1 << i)) {
115 set_irq_handler(i, do_level_IRQ); 115 set_irq_handler(i, handle_level_irq);
116 set_irq_chip(i, &int1_chip); 116 set_irq_chip(i, &int1_chip);
117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
118 } 118 }
119 if (INT2_IRQS & (1 << i)) { 119 if (INT2_IRQS & (1 << i)) {
120 set_irq_handler(i, do_level_IRQ); 120 set_irq_handler(i, handle_level_irq);
121 set_irq_chip(i, &int2_chip); 121 set_irq_chip(i, &int2_chip);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 } 123 }
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
index fb10cf252588..231b90004736 100644
--- a/arch/arm/mach-clps7500/core.c
+++ b/arch/arm/mach-clps7500/core.c
@@ -57,7 +57,7 @@ static void cl7500_unmask_irq_a(unsigned int irq)
57 iomd_writeb(val | mask, IOMD_IRQMASKA); 57 iomd_writeb(val | mask, IOMD_IRQMASKA);
58} 58}
59 59
60static struct irqchip clps7500_a_chip = { 60static struct irq_chip clps7500_a_chip = {
61 .ack = cl7500_ack_irq_a, 61 .ack = cl7500_ack_irq_a,
62 .mask = cl7500_mask_irq_a, 62 .mask = cl7500_mask_irq_a,
63 .unmask = cl7500_unmask_irq_a, 63 .unmask = cl7500_unmask_irq_a,
@@ -81,7 +81,7 @@ static void cl7500_unmask_irq_b(unsigned int irq)
81 iomd_writeb(val | mask, IOMD_IRQMASKB); 81 iomd_writeb(val | mask, IOMD_IRQMASKB);
82} 82}
83 83
84static struct irqchip clps7500_b_chip = { 84static struct irq_chip clps7500_b_chip = {
85 .ack = cl7500_mask_irq_b, 85 .ack = cl7500_mask_irq_b,
86 .mask = cl7500_mask_irq_b, 86 .mask = cl7500_mask_irq_b,
87 .unmask = cl7500_unmask_irq_b, 87 .unmask = cl7500_unmask_irq_b,
@@ -105,7 +105,7 @@ static void cl7500_unmask_irq_c(unsigned int irq)
105 iomd_writeb(val | mask, IOMD_IRQMASKC); 105 iomd_writeb(val | mask, IOMD_IRQMASKC);
106} 106}
107 107
108static struct irqchip clps7500_c_chip = { 108static struct irq_chip clps7500_c_chip = {
109 .ack = cl7500_mask_irq_c, 109 .ack = cl7500_mask_irq_c,
110 .mask = cl7500_mask_irq_c, 110 .mask = cl7500_mask_irq_c,
111 .unmask = cl7500_unmask_irq_c, 111 .unmask = cl7500_unmask_irq_c,
@@ -129,7 +129,7 @@ static void cl7500_unmask_irq_d(unsigned int irq)
129 iomd_writeb(val | mask, IOMD_IRQMASKD); 129 iomd_writeb(val | mask, IOMD_IRQMASKD);
130} 130}
131 131
132static struct irqchip clps7500_d_chip = { 132static struct irq_chip clps7500_d_chip = {
133 .ack = cl7500_mask_irq_d, 133 .ack = cl7500_mask_irq_d,
134 .mask = cl7500_mask_irq_d, 134 .mask = cl7500_mask_irq_d,
135 .unmask = cl7500_unmask_irq_d, 135 .unmask = cl7500_unmask_irq_d,
@@ -153,7 +153,7 @@ static void cl7500_unmask_irq_dma(unsigned int irq)
153 iomd_writeb(val | mask, IOMD_DMAMASK); 153 iomd_writeb(val | mask, IOMD_DMAMASK);
154} 154}
155 155
156static struct irqchip clps7500_dma_chip = { 156static struct irq_chip clps7500_dma_chip = {
157 .ack = cl7500_mask_irq_dma, 157 .ack = cl7500_mask_irq_dma,
158 .mask = cl7500_mask_irq_dma, 158 .mask = cl7500_mask_irq_dma,
159 .unmask = cl7500_unmask_irq_dma, 159 .unmask = cl7500_unmask_irq_dma,
@@ -177,7 +177,7 @@ static void cl7500_unmask_irq_fiq(unsigned int irq)
177 iomd_writeb(val | mask, IOMD_FIQMASK); 177 iomd_writeb(val | mask, IOMD_FIQMASK);
178} 178}
179 179
180static struct irqchip clps7500_fiq_chip = { 180static struct irq_chip clps7500_fiq_chip = {
181 .ack = cl7500_mask_irq_fiq, 181 .ack = cl7500_mask_irq_fiq,
182 .mask = cl7500_mask_irq_fiq, 182 .mask = cl7500_mask_irq_fiq,
183 .unmask = cl7500_unmask_irq_fiq, 183 .unmask = cl7500_unmask_irq_fiq,
@@ -187,7 +187,7 @@ static void cl7500_no_action(unsigned int irq)
187{ 187{
188} 188}
189 189
190static struct irqchip clps7500_no_chip = { 190static struct irq_chip clps7500_no_chip = {
191 .ack = cl7500_no_action, 191 .ack = cl7500_no_action,
192 .mask = cl7500_no_action, 192 .mask = cl7500_no_action,
193 .unmask = cl7500_no_action, 193 .unmask = cl7500_no_action,
@@ -214,43 +214,43 @@ static void __init clps7500_init_irq(void)
214 switch (irq) { 214 switch (irq) {
215 case 0 ... 7: 215 case 0 ... 7:
216 set_irq_chip(irq, &clps7500_a_chip); 216 set_irq_chip(irq, &clps7500_a_chip);
217 set_irq_handler(irq, do_level_IRQ); 217 set_irq_handler(irq, handle_level_irq);
218 set_irq_flags(irq, flags); 218 set_irq_flags(irq, flags);
219 break; 219 break;
220 220
221 case 8 ... 15: 221 case 8 ... 15:
222 set_irq_chip(irq, &clps7500_b_chip); 222 set_irq_chip(irq, &clps7500_b_chip);
223 set_irq_handler(irq, do_level_IRQ); 223 set_irq_handler(irq, handle_level_irq);
224 set_irq_flags(irq, flags); 224 set_irq_flags(irq, flags);
225 break; 225 break;
226 226
227 case 16 ... 22: 227 case 16 ... 22:
228 set_irq_chip(irq, &clps7500_dma_chip); 228 set_irq_chip(irq, &clps7500_dma_chip);
229 set_irq_handler(irq, do_level_IRQ); 229 set_irq_handler(irq, handle_level_irq);
230 set_irq_flags(irq, flags); 230 set_irq_flags(irq, flags);
231 break; 231 break;
232 232
233 case 24 ... 31: 233 case 24 ... 31:
234 set_irq_chip(irq, &clps7500_c_chip); 234 set_irq_chip(irq, &clps7500_c_chip);
235 set_irq_handler(irq, do_level_IRQ); 235 set_irq_handler(irq, handle_level_irq);
236 set_irq_flags(irq, flags); 236 set_irq_flags(irq, flags);
237 break; 237 break;
238 238
239 case 40 ... 47: 239 case 40 ... 47:
240 set_irq_chip(irq, &clps7500_d_chip); 240 set_irq_chip(irq, &clps7500_d_chip);
241 set_irq_handler(irq, do_level_IRQ); 241 set_irq_handler(irq, handle_level_irq);
242 set_irq_flags(irq, flags); 242 set_irq_flags(irq, flags);
243 break; 243 break;
244 244
245 case 48 ... 55: 245 case 48 ... 55:
246 set_irq_chip(irq, &clps7500_no_chip); 246 set_irq_chip(irq, &clps7500_no_chip);
247 set_irq_handler(irq, do_level_IRQ); 247 set_irq_handler(irq, handle_level_irq);
248 set_irq_flags(irq, flags); 248 set_irq_flags(irq, flags);
249 break; 249 break;
250 250
251 case 64 ... 72: 251 case 64 ... 72:
252 set_irq_chip(irq, &clps7500_fiq_chip); 252 set_irq_chip(irq, &clps7500_fiq_chip);
253 set_irq_handler(irq, do_level_IRQ); 253 set_irq_handler(irq, handle_level_irq);
254 set_irq_flags(irq, flags); 254 set_irq_flags(irq, flags);
255 break; 255 break;
256 } 256 }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 90103ab373a6..8459431cfd71 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -45,7 +45,7 @@ static void ebsa110_unmask_irq(unsigned int irq)
45 __raw_writeb(1 << irq, IRQ_MSET); 45 __raw_writeb(1 << irq, IRQ_MSET);
46} 46}
47 47
48static struct irqchip ebsa110_irq_chip = { 48static struct irq_chip ebsa110_irq_chip = {
49 .ack = ebsa110_mask_irq, 49 .ack = ebsa110_mask_irq,
50 .mask = ebsa110_mask_irq, 50 .mask = ebsa110_mask_irq,
51 .unmask = ebsa110_unmask_irq, 51 .unmask = ebsa110_unmask_irq,
@@ -67,7 +67,7 @@ static void __init ebsa110_init_irq(void)
67 67
68 for (irq = 0; irq < NR_IRQS; irq++) { 68 for (irq = 0; irq < NR_IRQS; irq++) {
69 set_irq_chip(irq, &ebsa110_irq_chip); 69 set_irq_chip(irq, &ebsa110_irq_chip);
70 set_irq_handler(irq, do_level_IRQ); 70 set_irq_handler(irq, handle_level_irq);
71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
72 } 72 }
73} 73}
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index e346b03cd921..af7904b3d0a8 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -9,12 +9,24 @@ config CRUNCH
9 9
10comment "EP93xx Platforms" 10comment "EP93xx Platforms"
11 11
12config MACH_ADSSPHERE
13 bool "Support ADS Sphere"
14 help
15 Say 'Y' here if you want your kernel to support the ADS
16 Sphere board.
17
12config MACH_EDB9302 18config MACH_EDB9302
13 bool "Support Cirrus Logic EDB9302" 19 bool "Support Cirrus Logic EDB9302"
14 help 20 help
15 Say 'Y' here if you want your kernel to support the Cirrus 21 Say 'Y' here if you want your kernel to support the Cirrus
16 Logic EDB9302 Evaluation Board. 22 Logic EDB9302 Evaluation Board.
17 23
24config MACH_EDB9302A
25 bool "Support Cirrus Logic EDB9302A"
26 help
27 Say 'Y' here if you want your kernel to support the Cirrus
28 Logic EDB9302A Evaluation Board.
29
18config MACH_EDB9312 30config MACH_EDB9312
19 bool "Support Cirrus Logic EDB9312" 31 bool "Support Cirrus Logic EDB9312"
20 help 32 help
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index c2eb18b530c2..b06641dd450d 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -6,7 +6,9 @@ obj-m :=
6obj-n := 6obj-n :=
7obj- := 7obj- :=
8 8
9obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o
9obj-$(CONFIG_MACH_EDB9302) += edb9302.o 10obj-$(CONFIG_MACH_EDB9302) += edb9302.o
11obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o
10obj-$(CONFIG_MACH_EDB9312) += edb9312.o 12obj-$(CONFIG_MACH_EDB9312) += edb9312.o
11obj-$(CONFIG_MACH_EDB9315) += edb9315.o 13obj-$(CONFIG_MACH_EDB9315) += edb9315.o
12obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o 14obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
new file mode 100644
index 000000000000..ac5d5818eb7b
--- /dev/null
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -0,0 +1,91 @@
1/*
2 * arch/arm/mach-ep93xx/adssphere.c
3 * ADS Sphere support.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/mtd/physmap.h>
20#include <linux/platform_device.h>
21#include <asm/io.h>
22#include <asm/hardware.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25
26static struct physmap_flash_data adssphere_flash_data = {
27 .width = 4,
28};
29
30static struct resource adssphere_flash_resource = {
31 .start = 0x60000000,
32 .end = 0x61ffffff,
33 .flags = IORESOURCE_MEM,
34};
35
36static struct platform_device adssphere_flash = {
37 .name = "physmap-flash",
38 .id = 0,
39 .dev = {
40 .platform_data = &adssphere_flash_data,
41 },
42 .num_resources = 1,
43 .resource = &adssphere_flash_resource,
44};
45
46static struct ep93xx_eth_data adssphere_eth_data = {
47 .phy_id = 1,
48};
49
50static struct resource adssphere_eth_resource[] = {
51 {
52 .start = EP93XX_ETHERNET_PHYS_BASE,
53 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
54 .flags = IORESOURCE_MEM,
55 }, {
56 .start = IRQ_EP93XX_ETHERNET,
57 .end = IRQ_EP93XX_ETHERNET,
58 .flags = IORESOURCE_IRQ,
59 }
60};
61
62static struct platform_device adssphere_eth_device = {
63 .name = "ep93xx-eth",
64 .id = -1,
65 .dev = {
66 .platform_data = &adssphere_eth_data,
67 },
68 .num_resources = 2,
69 .resource = adssphere_eth_resource,
70};
71
72static void __init adssphere_init_machine(void)
73{
74 ep93xx_init_devices();
75 platform_device_register(&adssphere_flash);
76
77 memcpy(adssphere_eth_data.dev_addr,
78 (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
79 platform_device_register(&adssphere_eth_device);
80}
81
82MACHINE_START(ADSSPHERE, "ADS Sphere board")
83 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
84 .phys_io = EP93XX_APB_PHYS_BASE,
85 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
86 .boot_params = 0x00000100,
87 .map_io = ep93xx_map_io,
88 .init_irq = ep93xx_init_irq,
89 .timer = &ep93xx_timer,
90 .init_machine = adssphere_init_machine,
91MACHINE_END
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index e3fd1ab6adcc..d649b39711d4 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -245,7 +245,7 @@ EXPORT_SYMBOL(gpio_line_set);
245 * EP93xx IRQ handling 245 * EP93xx IRQ handling
246 *************************************************************************/ 246 *************************************************************************/
247static void ep93xx_gpio_ab_irq_handler(unsigned int irq, 247static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
248 struct irqdesc *desc) 248 struct irq_desc *desc)
249{ 249{
250 unsigned char status; 250 unsigned char status;
251 int i; 251 int i;
@@ -335,7 +335,7 @@ static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
335 return 0; 335 return 0;
336} 336}
337 337
338static struct irqchip ep93xx_gpio_ab_irq_chip = { 338static struct irq_chip ep93xx_gpio_ab_irq_chip = {
339 .ack = ep93xx_gpio_ab_irq_mask_ack, 339 .ack = ep93xx_gpio_ab_irq_mask_ack,
340 .mask = ep93xx_gpio_ab_irq_mask, 340 .mask = ep93xx_gpio_ab_irq_mask,
341 .unmask = ep93xx_gpio_ab_irq_unmask, 341 .unmask = ep93xx_gpio_ab_irq_unmask,
@@ -352,7 +352,7 @@ void __init ep93xx_init_irq(void)
352 352
353 for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) { 353 for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
354 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip); 354 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
355 set_irq_handler(irq, do_level_IRQ); 355 set_irq_handler(irq, handle_level_irq);
356 set_irq_flags(irq, IRQF_VALID); 356 set_irq_flags(irq, IRQF_VALID);
357 } 357 }
358 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); 358 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c
new file mode 100644
index 000000000000..62e064bab1d2
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb9302a.c
@@ -0,0 +1,91 @@
1/*
2 * arch/arm/mach-ep93xx/edb9302a.c
3 * Cirrus Logic EDB9302A support.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/mtd/physmap.h>
20#include <linux/platform_device.h>
21#include <asm/io.h>
22#include <asm/hardware.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25
26static struct physmap_flash_data edb9302a_flash_data = {
27 .width = 2,
28};
29
30static struct resource edb9302a_flash_resource = {
31 .start = 0x60000000,
32 .end = 0x60ffffff,
33 .flags = IORESOURCE_MEM,
34};
35
36static struct platform_device edb9302a_flash = {
37 .name = "physmap-flash",
38 .id = 0,
39 .dev = {
40 .platform_data = &edb9302a_flash_data,
41 },
42 .num_resources = 1,
43 .resource = &edb9302a_flash_resource,
44};
45
46static struct ep93xx_eth_data edb9302a_eth_data = {
47 .phy_id = 1,
48};
49
50static struct resource edb9302a_eth_resource[] = {
51 {
52 .start = EP93XX_ETHERNET_PHYS_BASE,
53 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
54 .flags = IORESOURCE_MEM,
55 }, {
56 .start = IRQ_EP93XX_ETHERNET,
57 .end = IRQ_EP93XX_ETHERNET,
58 .flags = IORESOURCE_IRQ,
59 }
60};
61
62static struct platform_device edb9302a_eth_device = {
63 .name = "ep93xx-eth",
64 .id = -1,
65 .dev = {
66 .platform_data = &edb9302a_eth_data,
67 },
68 .num_resources = 2,
69 .resource = edb9302a_eth_resource,
70};
71
72static void __init edb9302a_init_machine(void)
73{
74 ep93xx_init_devices();
75 platform_device_register(&edb9302a_flash);
76
77 memcpy(edb9302a_eth_data.dev_addr,
78 (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
79 platform_device_register(&edb9302a_eth_device);
80}
81
82MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
83 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
84 .phys_io = EP93XX_APB_PHYS_BASE,
85 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
86 .boot_params = 0xc0000100,
87 .map_io = ep93xx_map_io,
88 .init_irq = ep93xx_init_irq,
89 .timer = &ep93xx_timer,
90 .init_machine = edb9302a_init_machine,
91MACHINE_END
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index af900f4755a4..ef29fc34ce65 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -78,7 +78,7 @@ static void fb_unmask_irq(unsigned int irq)
78 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)]; 78 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
79} 79}
80 80
81static struct irqchip fb_chip = { 81static struct irq_chip fb_chip = {
82 .ack = fb_mask_irq, 82 .ack = fb_mask_irq,
83 .mask = fb_mask_irq, 83 .mask = fb_mask_irq,
84 .unmask = fb_unmask_irq, 84 .unmask = fb_unmask_irq,
@@ -96,7 +96,7 @@ static void __init __fb_init_irq(void)
96 96
97 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { 97 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
98 set_irq_chip(irq, &fb_chip); 98 set_irq_chip(irq, &fb_chip);
99 set_irq_handler(irq, do_level_IRQ); 99 set_irq_handler(irq, handle_level_irq);
100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
101 } 101 }
102} 102}
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 888dedd501b9..79443ffc8916 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -49,7 +49,7 @@ static void isa_unmask_pic_lo_irq(unsigned int irq)
49 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); 49 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
50} 50}
51 51
52static struct irqchip isa_lo_chip = { 52static struct irq_chip isa_lo_chip = {
53 .ack = isa_ack_pic_lo_irq, 53 .ack = isa_ack_pic_lo_irq,
54 .mask = isa_mask_pic_lo_irq, 54 .mask = isa_mask_pic_lo_irq,
55 .unmask = isa_unmask_pic_lo_irq, 55 .unmask = isa_unmask_pic_lo_irq,
@@ -78,14 +78,14 @@ static void isa_unmask_pic_hi_irq(unsigned int irq)
78 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); 78 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
79} 79}
80 80
81static struct irqchip isa_hi_chip = { 81static struct irq_chip isa_hi_chip = {
82 .ack = isa_ack_pic_hi_irq, 82 .ack = isa_ack_pic_hi_irq,
83 .mask = isa_mask_pic_hi_irq, 83 .mask = isa_mask_pic_hi_irq,
84 .unmask = isa_unmask_pic_hi_irq, 84 .unmask = isa_unmask_pic_hi_irq,
85}; 85};
86 86
87static void 87static void
88isa_irq_handler(unsigned int irq, struct irqdesc *desc) 88isa_irq_handler(unsigned int irq, struct irq_desc *desc)
89{ 89{
90 unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE; 90 unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
91 91
@@ -150,13 +150,13 @@ void __init isa_init_irq(unsigned int host_irq)
150 if (host_irq != (unsigned int)-1) { 150 if (host_irq != (unsigned int)-1) {
151 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { 151 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
152 set_irq_chip(irq, &isa_lo_chip); 152 set_irq_chip(irq, &isa_lo_chip);
153 set_irq_handler(irq, do_level_IRQ); 153 set_irq_handler(irq, handle_level_irq);
154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
155 } 155 }
156 156
157 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { 157 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
158 set_irq_chip(irq, &isa_hi_chip); 158 set_irq_chip(irq, &isa_hi_chip);
159 set_irq_handler(irq, do_level_IRQ); 159 set_irq_handler(irq, handle_level_irq);
160 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 160 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
161 } 161 }
162 162
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 4719229a1a78..7f31816896ad 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -101,7 +101,7 @@ static void inline unmask_gpio_irq(u32 irq)
101 101
102static void 102static void
103h720x_gpio_handler(unsigned int mask, unsigned int irq, 103h720x_gpio_handler(unsigned int mask, unsigned int irq,
104 struct irqdesc *desc) 104 struct irq_desc *desc)
105{ 105{
106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq); 106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
107 desc = irq_desc + irq; 107 desc = irq_desc + irq;
@@ -117,7 +117,7 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
117} 117}
118 118
119static void 119static void
120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
121{ 121{
122 unsigned int mask, irq; 122 unsigned int mask, irq;
123 123
@@ -128,7 +128,7 @@ h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
128} 128}
129 129
130static void 130static void
131h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 131h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
132{ 132{
133 unsigned int mask, irq; 133 unsigned int mask, irq;
134 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 134 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
@@ -138,7 +138,7 @@ h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
138} 138}
139 139
140static void 140static void
141h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 141h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
142{ 142{
143 unsigned int mask, irq; 143 unsigned int mask, irq;
144 144
@@ -149,7 +149,7 @@ h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
149} 149}
150 150
151static void 151static void
152h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 152h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
153{ 153{
154 unsigned int mask, irq; 154 unsigned int mask, irq;
155 155
@@ -161,7 +161,7 @@ h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
161 161
162#ifdef CONFIG_CPU_H7202 162#ifdef CONFIG_CPU_H7202
163static void 163static void
164h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 164h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
165{ 165{
166 unsigned int mask, irq; 166 unsigned int mask, irq;
167 167
@@ -172,13 +172,13 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
172} 172}
173#endif 173#endif
174 174
175static struct irqchip h720x_global_chip = { 175static struct irq_chip h720x_global_chip = {
176 .ack = mask_global_irq, 176 .ack = mask_global_irq,
177 .mask = mask_global_irq, 177 .mask = mask_global_irq,
178 .unmask = unmask_global_irq, 178 .unmask = unmask_global_irq,
179}; 179};
180 180
181static struct irqchip h720x_gpio_chip = { 181static struct irq_chip h720x_gpio_chip = {
182 .ack = ack_gpio_irq, 182 .ack = ack_gpio_irq,
183 .mask = mask_gpio_irq, 183 .mask = mask_gpio_irq,
184 .unmask = unmask_gpio_irq, 184 .unmask = unmask_gpio_irq,
@@ -203,14 +203,14 @@ void __init h720x_init_irq (void)
203 /* Initialize global IRQ's, fast path */ 203 /* Initialize global IRQ's, fast path */
204 for (irq = 0; irq < NR_GLBL_IRQS; irq++) { 204 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
205 set_irq_chip(irq, &h720x_global_chip); 205 set_irq_chip(irq, &h720x_global_chip);
206 set_irq_handler(irq, do_level_IRQ); 206 set_irq_handler(irq, handle_level_irq);
207 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 207 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
208 } 208 }
209 209
210 /* Initialize multiplexed IRQ's, slow path */ 210 /* Initialize multiplexed IRQ's, slow path */
211 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { 211 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
212 set_irq_chip(irq, &h720x_gpio_chip); 212 set_irq_chip(irq, &h720x_gpio_chip);
213 set_irq_handler(irq, do_edge_IRQ); 213 set_irq_handler(irq, handle_edge_irq);
214 set_irq_flags(irq, IRQF_VALID ); 214 set_irq_flags(irq, IRQF_VALID );
215 } 215 }
216 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); 216 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
@@ -221,7 +221,7 @@ void __init h720x_init_irq (void)
221#ifdef CONFIG_CPU_H7202 221#ifdef CONFIG_CPU_H7202
222 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { 222 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
223 set_irq_chip(irq, &h720x_gpio_chip); 223 set_irq_chip(irq, &h720x_gpio_chip);
224 set_irq_handler(irq, do_edge_IRQ); 224 set_irq_handler(irq, handle_edge_irq);
225 set_irq_flags(irq, IRQF_VALID ); 225 set_irq_flags(irq, IRQF_VALID );
226 } 226 }
227 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); 227 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 06fecaefd8dc..703870f30adf 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -106,7 +106,7 @@ static struct platform_device *devices[] __initdata = {
106 * we have to handle all timer interrupts in one place. 106 * we have to handle all timer interrupts in one place.
107 */ 107 */
108static void 108static void
109h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 109h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
110{ 110{
111 unsigned int mask, irq; 111 unsigned int mask, irq;
112 112
@@ -162,7 +162,7 @@ static void inline unmask_timerx_irq (u32 irq)
162 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; 162 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
163} 163}
164 164
165static struct irqchip h7202_timerx_chip = { 165static struct irq_chip h7202_timerx_chip = {
166 .ack = mask_timerx_irq, 166 .ack = mask_timerx_irq,
167 .mask = mask_timerx_irq, 167 .mask = mask_timerx_irq,
168 .unmask = unmask_timerx_irq, 168 .unmask = unmask_timerx_irq,
@@ -202,7 +202,7 @@ void __init h7202_init_irq (void)
202 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { 202 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
203 mask_timerx_irq(irq); 203 mask_timerx_irq(irq);
204 set_irq_chip(irq, &h7202_timerx_chip); 204 set_irq_chip(irq, &h7202_timerx_chip);
205 set_irq_handler(irq, do_edge_IRQ); 205 set_irq_handler(irq, handle_edge_irq);
206 set_irq_flags(irq, IRQF_VALID ); 206 set_irq_flags(irq, IRQF_VALID );
207 } 207 }
208 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); 208 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0b27d79f2efd..02272aa36e90 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,6 +9,8 @@
9 9
10obj-y += irq.o time.o dma.o generic.o 10obj-y += irq.o time.o dma.o generic.o
11 11
12obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
13
12# Specific board support 14# Specific board support
13obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o 15obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
14 16
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
new file mode 100644
index 000000000000..ac5f99895660
--- /dev/null
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -0,0 +1,287 @@
1/*
2 * cpu.c: clock scaling for the iMX
3 *
4 * Copyright (C) 2000 2001, The Delft University of Technology
5 * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
6 * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com>
7 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
8 *
9 * Based on SA1100 version written by:
10 * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
11 * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29/*#define DEBUG*/
30
31#include <linux/kernel.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/cpufreq.h>
35#include <asm/system.h>
36
37#include <asm/hardware.h>
38
39#include "generic.h"
40
41#ifndef __val2mfld
42#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
43#endif
44#ifndef __mfld2val
45#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
46#endif
47
48#define CR_920T_CLOCK_MODE 0xC0000000
49#define CR_920T_FASTBUS_MODE 0x00000000
50#define CR_920T_ASYNC_MODE 0xC0000000
51
52static u32 mpctl0_at_boot;
53
54static void imx_set_async_mode(void)
55{
56 adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
57}
58
59static void imx_set_fastbus_mode(void)
60{
61 adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE);
62}
63
64static void imx_set_mpctl0(u32 mpctl0)
65{
66 unsigned long flags;
67
68 if (mpctl0 == 0) {
69 local_irq_save(flags);
70 CSCR &= ~CSCR_MPEN;
71 local_irq_restore(flags);
72 return;
73 }
74
75 local_irq_save(flags);
76 MPCTL0 = mpctl0;
77 CSCR |= CSCR_MPEN;
78 local_irq_restore(flags);
79}
80
81/**
82 * imx_compute_mpctl - compute new PLL parameters
83 * @new_mpctl: pointer to location assigned by new PLL control register value
84 * @cur_mpctl: current PLL control register parameters
85 * @freq: required frequency in Hz
86 * @relation: is one of %CPUFREQ_RELATION_L (supremum)
87 * and %CPUFREQ_RELATION_H (infimum)
88 */
89long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, unsigned long freq, int relation)
90{
91 u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
92 u32 mfi;
93 u32 mfn;
94 u32 mfd;
95 u32 pd;
96 unsigned long long ll;
97 long l;
98 long quot;
99
100 /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */
101 /* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */
102
103 if (cur_mpctl) {
104 mfd = ((cur_mpctl >> 16) & 0x3ff) + 1;
105 pd = ((cur_mpctl >> 26) & 0xf) + 1;
106 } else {
107 pd=2; mfd=313;
108 }
109
110 /* pd=2; mfd=313; mfi=8; mfn=183; */
111 /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */
112
113 quot = (f_ref + (1 << 9)) >> 10;
114 l = (freq * pd + quot) / (2 * quot);
115 mfi = l >> 10;
116 mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10;
117
118 mfd -= 1;
119 pd -= 1;
120
121 *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16)
122 | ((pd & 0xf) << 26);
123
124 ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
125 quot = (pd+1) * (1<<16);
126 ll += quot / 2;
127 do_div(ll, quot);
128 freq = ll;
129
130 pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n",
131 pd, mfd, mfi, mfn, freq);
132
133 return freq;
134}
135
136
137static int imx_verify_speed(struct cpufreq_policy *policy)
138{
139 if (policy->cpu != 0)
140 return -EINVAL;
141
142 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
143
144 return 0;
145}
146
147static unsigned int imx_get_speed(unsigned int cpu)
148{
149 unsigned int freq;
150 unsigned int cr;
151 unsigned int cscr;
152 unsigned int bclk_div;
153
154 if (cpu)
155 return 0;
156
157 cscr = CSCR;
158 bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1;
159 cr = get_cr();
160
161 if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
162 freq = imx_get_system_clk();
163 freq = (freq + bclk_div/2) / bclk_div;
164 } else {
165 freq = imx_get_mcu_clk();
166 if (cscr & CSCR_MPU_PRESC)
167 freq /= 2;
168 }
169
170 freq = (freq + 500) / 1000;
171
172 return freq;
173}
174
175static int imx_set_target(struct cpufreq_policy *policy,
176 unsigned int target_freq,
177 unsigned int relation)
178{
179 struct cpufreq_freqs freqs;
180 u32 mpctl0 = 0;
181 u32 cscr;
182 unsigned long flags;
183 long freq;
184 long sysclk;
185 unsigned int bclk_div = 1;
186
187 freq = target_freq * 1000;
188
189 pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
190 freq, mpctl0_at_boot);
191
192 sysclk = imx_get_system_clk();
193
194 if (freq > sysclk + 1000000) {
195 freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation);
196 if (freq < 0) {
197 printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
198 return -EINVAL;
199 }
200 } else {
201 if(freq + 1000 < sysclk) {
202 if (relation == CPUFREQ_RELATION_L)
203 bclk_div = (sysclk - 1000) / freq;
204 else
205 bclk_div = (sysclk + freq + 1000) / freq;
206
207 if(bclk_div > 16)
208 bclk_div = 16;
209 }
210 freq = (sysclk + bclk_div / 2) / bclk_div;
211 }
212
213 freqs.old = imx_get_speed(0);
214 freqs.new = (freq + 500) / 1000;
215 freqs.cpu = 0;
216 freqs.flags = 0;
217
218 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
219
220 local_irq_save(flags);
221
222 imx_set_fastbus_mode();
223
224 imx_set_mpctl0(mpctl0);
225
226 cscr = CSCR;
227 cscr &= ~CSCR_BCLK_DIV;
228 cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1);
229 CSCR = cscr;
230
231 if(mpctl0) {
232 CSCR |= CSCR_MPLL_RESTART;
233
234 /* Wait until MPLL is stablized */
235 while( CSCR & CSCR_MPLL_RESTART );
236
237 imx_set_async_mode();
238 }
239
240 local_irq_restore(flags);
241
242 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
243
244 pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n",
245 freq, mpctl0? "MPLL": "SPLL");
246
247 return 0;
248}
249
250static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
251{
252 printk(KERN_INFO "i.MX cpu freq change driver v1.0\n");
253
254 if (policy->cpu != 0)
255 return -EINVAL;
256
257 policy->cur = policy->min = policy->max = imx_get_speed(0);
258 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
259 policy->cpuinfo.min_freq = 8000;
260 policy->cpuinfo.max_freq = 200000;
261 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
262 return 0;
263}
264
265static struct cpufreq_driver imx_driver = {
266 .flags = CPUFREQ_STICKY,
267 .verify = imx_verify_speed,
268 .target = imx_set_target,
269 .get = imx_get_speed,
270 .init = imx_cpufreq_driver_init,
271 .name = "imx",
272};
273
274static int __init imx_cpufreq_init(void)
275{
276
277 mpctl0_at_boot = 0;
278
279 if((CSCR & CSCR_MPEN) &&
280 ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
281 mpctl0_at_boot = MPCTL0;
282
283 return cpufreq_register_driver(&imx_driver);
284}
285
286arch_initcall(imx_cpufreq_init);
287
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 12ea58a3b84f..b5aa49d00ca3 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -104,6 +104,9 @@ EXPORT_SYMBOL(imx_gpio_mode);
104 */ 104 */
105static unsigned int imx_decode_pll(unsigned int pll) 105static unsigned int imx_decode_pll(unsigned int pll)
106{ 106{
107 unsigned long long ll;
108 unsigned long quot;
109
107 u32 mfi = (pll >> 10) & 0xf; 110 u32 mfi = (pll >> 10) & 0xf;
108 u32 mfn = pll & 0x3ff; 111 u32 mfn = pll & 0x3ff;
109 u32 mfd = (pll >> 16) & 0x3ff; 112 u32 mfd = (pll >> 16) & 0x3ff;
@@ -112,7 +115,11 @@ static unsigned int imx_decode_pll(unsigned int pll)
112 115
113 mfi = mfi <= 5 ? 5 : mfi; 116 mfi = mfi <= 5 ? 5 : mfi;
114 117
115 return (2 * (f_ref>>10) * ( (mfi<<10) + (mfn<<10) / (mfd+1) )) / (pd+1); 118 ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
119 quot = (pd+1) * (1<<16);
120 ll += quot / 2;
121 do_div(ll, quot);
122 return (unsigned int) ll;
116} 123}
117 124
118unsigned int imx_get_system_clk(void) 125unsigned int imx_get_system_clk(void)
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 368b13b058ab..0791b56caecc 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -146,7 +146,7 @@ imx_gpio_unmask_irq(unsigned int irq)
146 146
147static void 147static void
148imx_gpio_handler(unsigned int mask, unsigned int irq, 148imx_gpio_handler(unsigned int mask, unsigned int irq,
149 struct irqdesc *desc) 149 struct irq_desc *desc)
150{ 150{
151 desc = irq_desc + irq; 151 desc = irq_desc + irq;
152 while (mask) { 152 while (mask) {
@@ -161,7 +161,7 @@ imx_gpio_handler(unsigned int mask, unsigned int irq,
161} 161}
162 162
163static void 163static void
164imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 164imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
165{ 165{
166 unsigned int mask, irq; 166 unsigned int mask, irq;
167 167
@@ -171,7 +171,7 @@ imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
171} 171}
172 172
173static void 173static void
174imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 174imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
175{ 175{
176 unsigned int mask, irq; 176 unsigned int mask, irq;
177 177
@@ -181,7 +181,7 @@ imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
181} 181}
182 182
183static void 183static void
184imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 184imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
185{ 185{
186 unsigned int mask, irq; 186 unsigned int mask, irq;
187 187
@@ -191,7 +191,7 @@ imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
191} 191}
192 192
193static void 193static void
194imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 194imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
195{ 195{
196 unsigned int mask, irq; 196 unsigned int mask, irq;
197 197
@@ -230,13 +230,13 @@ imx_init_irq(void)
230 230
231 for (irq = 0; irq < IMX_IRQS; irq++) { 231 for (irq = 0; irq < IMX_IRQS; irq++) {
232 set_irq_chip(irq, &imx_internal_chip); 232 set_irq_chip(irq, &imx_internal_chip);
233 set_irq_handler(irq, do_level_IRQ); 233 set_irq_handler(irq, handle_level_irq);
234 set_irq_flags(irq, IRQF_VALID); 234 set_irq_flags(irq, IRQF_VALID);
235 } 235 }
236 236
237 for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { 237 for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
238 set_irq_chip(irq, &imx_gpio_chip); 238 set_irq_chip(irq, &imx_gpio_chip);
239 set_irq_handler(irq, do_edge_IRQ); 239 set_irq_handler(irq, handle_edge_irq);
240 set_irq_flags(irq, IRQF_VALID); 240 set_irq_flags(irq, IRQF_VALID);
241 } 241 }
242 242
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 8ae4a2c5066f..40039b2a90b3 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -14,6 +14,7 @@
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/time.h> 16#include <linux/time.h>
17#include <linux/clocksource.h>
17 18
18#include <asm/hardware.h> 19#include <asm/hardware.h>
19#include <asm/io.h> 20#include <asm/io.h>
@@ -24,33 +25,7 @@
24/* Use timer 1 as system timer */ 25/* Use timer 1 as system timer */
25#define TIMER_BASE IMX_TIM1_BASE 26#define TIMER_BASE IMX_TIM1_BASE
26 27
27/* 28static unsigned long evt_diff;
28 * Returns number of us since last clock interrupt. Note that interrupts
29 * will have been disabled by do_gettimeoffset()
30 */
31static unsigned long imx_gettimeoffset(void)
32{
33 unsigned long ticks;
34
35 /*
36 * Get the current number of ticks. Note that there is a race
37 * condition between us reading the timer and checking for
38 * an interrupt. We get around this by ensuring that the
39 * counter has not reloaded between our two reads.
40 */
41 ticks = IMX_TCN(TIMER_BASE);
42
43 /*
44 * Interrupt pending? If so, we've reloaded once already.
45 */
46 if (IMX_TSTAT(TIMER_BASE) & TSTAT_COMP)
47 ticks += LATCH;
48
49 /*
50 * Convert the ticks to usecs
51 */
52 return (1000000 / CLK32) * ticks;
53}
54 29
55/* 30/*
56 * IRQ handler for the timer 31 * IRQ handler for the timer
@@ -58,14 +33,23 @@ static unsigned long imx_gettimeoffset(void)
58static irqreturn_t 33static irqreturn_t
59imx_timer_interrupt(int irq, void *dev_id) 34imx_timer_interrupt(int irq, void *dev_id)
60{ 35{
61 write_seqlock(&xtime_lock); 36 uint32_t tstat;
62 37
63 /* clear the interrupt */ 38 /* clear the interrupt */
64 if (IMX_TSTAT(TIMER_BASE)) 39 tstat = IMX_TSTAT(TIMER_BASE);
65 IMX_TSTAT(TIMER_BASE) = 0; 40 IMX_TSTAT(TIMER_BASE) = 0;
41
42 if (tstat & TSTAT_COMP) {
43 do {
44
45 write_seqlock(&xtime_lock);
46 timer_tick();
47 write_sequnlock(&xtime_lock);
48 IMX_TCMP(TIMER_BASE) += evt_diff;
66 49
67 timer_tick(); 50 } while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE)
68 write_sequnlock(&xtime_lock); 51 - IMX_TCN(TIMER_BASE)) < 0));
52 }
69 53
70 return IRQ_HANDLED; 54 return IRQ_HANDLED;
71} 55}
@@ -77,9 +61,9 @@ static struct irqaction imx_timer_irq = {
77}; 61};
78 62
79/* 63/*
80 * Set up timer interrupt, and return the current time in seconds. 64 * Set up timer hardware into expected mode and state.
81 */ 65 */
82static void __init imx_timer_init(void) 66static void __init imx_timer_hardware_init(void)
83{ 67{
84 /* 68 /*
85 * Initialise to a known state (all timers off, and timing reset) 69 * Initialise to a known state (all timers off, and timing reset)
@@ -87,7 +71,38 @@ static void __init imx_timer_init(void)
87 IMX_TCTL(TIMER_BASE) = 0; 71 IMX_TCTL(TIMER_BASE) = 0;
88 IMX_TPRER(TIMER_BASE) = 0; 72 IMX_TPRER(TIMER_BASE) = 0;
89 IMX_TCMP(TIMER_BASE) = LATCH - 1; 73 IMX_TCMP(TIMER_BASE) = LATCH - 1;
90 IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN; 74
75 IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN;
76 evt_diff = LATCH;
77}
78
79cycle_t imx_get_cycles(void)
80{
81 return IMX_TCN(TIMER_BASE);
82}
83
84static struct clocksource clocksource_imx = {
85 .name = "imx_timer1",
86 .rating = 200,
87 .read = imx_get_cycles,
88 .mask = 0xFFFFFFFF,
89 .shift = 20,
90 .is_continuous = 1,
91};
92
93static int __init imx_clocksource_init(void)
94{
95 clocksource_imx.mult =
96 clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
97 clocksource_register(&clocksource_imx);
98
99 return 0;
100}
101
102static void __init imx_timer_init(void)
103{
104 imx_timer_hardware_init();
105 imx_clocksource_init();
91 106
92 /* 107 /*
93 * Make irqs happen for the system timer 108 * Make irqs happen for the system timer
@@ -97,5 +112,4 @@ static void __init imx_timer_init(void)
97 112
98struct sys_timer imx_timer = { 113struct sys_timer imx_timer = {
99 .init = imx_timer_init, 114 .init = imx_timer_init,
100 .offset = imx_gettimeoffset,
101}; 115};
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 191c57a3b997..72280754354d 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -183,7 +183,7 @@ static void __init ap_init_irq(void)
183 for (i = 0; i < NR_IRQS; i++) { 183 for (i = 0; i < NR_IRQS; i++) {
184 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) { 184 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
185 set_irq_chip(i, &sc_chip); 185 set_irq_chip(i, &sc_chip);
186 set_irq_handler(i, do_level_IRQ); 186 set_irq_handler(i, handle_level_irq);
187 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 187 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
188 } 188 }
189 } 189 }
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 771b65bffe69..913f64b22405 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -202,7 +202,7 @@ static struct irq_chip sic_chip = {
202}; 202};
203 203
204static void 204static void
205sic_handle_irq(unsigned int irq, struct irqdesc *desc) 205sic_handle_irq(unsigned int irq, struct irq_desc *desc)
206{ 206{
207 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); 207 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
208 208
@@ -238,7 +238,7 @@ static void __init intcp_init_irq(void)
238 if (i == 29) 238 if (i == 29)
239 break; 239 break;
240 set_irq_chip(i, &pic_chip); 240 set_irq_chip(i, &pic_chip);
241 set_irq_handler(i, do_level_IRQ); 241 set_irq_handler(i, handle_level_irq);
242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
243 } 243 }
244 244
@@ -247,7 +247,7 @@ static void __init intcp_init_irq(void)
247 247
248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { 248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
249 set_irq_chip(i, &cic_chip); 249 set_irq_chip(i, &cic_chip);
250 set_irq_handler(i, do_level_IRQ); 250 set_irq_handler(i, handle_level_irq);
251 set_irq_flags(i, IRQF_VALID); 251 set_irq_flags(i, IRQF_VALID);
252 } 252 }
253 253
@@ -256,7 +256,7 @@ static void __init intcp_init_irq(void)
256 256
257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { 257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
258 set_irq_chip(i, &sic_chip); 258 set_irq_chip(i, &sic_chip);
259 set_irq_handler(i, do_level_IRQ); 259 set_irq_handler(i, handle_level_irq);
260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
261 } 261 }
262 262
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
index 1bc8534ef0c6..613b841a10f3 100644
--- a/arch/arm/mach-integrator/platsmp.c
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -18,7 +18,6 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/delay.h> 19#include <asm/delay.h>
20#include <asm/mmu_context.h> 20#include <asm/mmu_context.h>
21#include <asm/procinfo.h>
22#include <asm/ptrace.h> 21#include <asm/ptrace.h>
23#include <asm/smp.h> 22#include <asm/smp.h>
24 23
diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig
new file mode 100644
index 000000000000..40c2d689f2eb
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Kconfig
@@ -0,0 +1,20 @@
1if ARCH_IOP13XX
2
3menu "IOP13XX Implementation Options"
4
5comment "IOP13XX Platform Support"
6
7config MACH_IQ81340SC
8 bool "Enable IQ81340SC Hardware Support"
9 help
10 Say Y here if you want to support running on the Intel IQ81340SC
11 evaluation kit.
12
13config MACH_IQ81340MC
14 bool "Enable IQ81340MC Hardware Support"
15 help
16 Say Y here if you want to support running on the Intel IQ81340MC
17 evaluation kit.
18
19endmenu
20endif
diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
new file mode 100644
index 000000000000..c3d6c08f2d4c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile
@@ -0,0 +1,12 @@
1obj-y :=
2obj-m :=
3obj-n :=
4obj- :=
5
6obj-$(CONFIG_ARCH_IOP13XX) += setup.o
7obj-$(CONFIG_ARCH_IOP13XX) += irq.o
8obj-$(CONFIG_ARCH_IOP13XX) += time.o
9obj-$(CONFIG_ARCH_IOP13XX) += pci.o
10obj-$(CONFIG_ARCH_IOP13XX) += io.o
11obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
12obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot
new file mode 100644
index 000000000000..0b0e19fdfe6c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
new file mode 100644
index 000000000000..fbf9f88e46ea
--- /dev/null
+++ b/arch/arm/mach-iop13xx/io.c
@@ -0,0 +1,93 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <asm/hardware.h>
22#include <asm/io.h>
23
24void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
25 unsigned long flags)
26{
27 void __iomem * retval;
28
29 switch (cookie) {
30 case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
31 if (unlikely(!iop13xx_atux_mem_base))
32 retval = NULL;
33 else
34 retval = (void *)(iop13xx_atux_mem_base +
35 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
36 break;
37 case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
38 if (unlikely(!iop13xx_atue_mem_base))
39 retval = NULL;
40 else
41 retval = (void *)(iop13xx_atue_mem_base +
42 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
43 break;
44 case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
45 retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
46 (cookie - IOP13XX_PBI_LOWER_MEM_RA),
47 size, flags);
48 break;
49 case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
50 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
51 break;
52 case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
53 retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
54 break;
55 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
56 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
57 break;
58 default:
59 retval = __ioremap(cookie, size, flags);
60 }
61
62 return retval;
63}
64EXPORT_SYMBOL(__iop13xx_ioremap);
65
66void __iop13xx_iounmap(void __iomem *addr)
67{
68 extern void __iounmap(volatile void __iomem *addr);
69
70 if (iop13xx_atue_mem_base)
71 if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
72 addr < (void __iomem *) (iop13xx_atue_mem_base +
73 iop13xx_atue_mem_size))
74 goto skip;
75
76 if (iop13xx_atux_mem_base)
77 if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
78 addr < (void __iomem *) (iop13xx_atux_mem_base +
79 iop13xx_atux_mem_size))
80 goto skip;
81
82 switch ((u32) addr) {
83 case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
84 case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
85 case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
86 goto skip;
87 }
88 __iounmap(addr);
89
90skip:
91 return;
92}
93EXPORT_SYMBOL(__iop13xx_iounmap);
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
new file mode 100644
index 000000000000..ee595786cd22
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -0,0 +1,98 @@
1/*
2 * iq81340mc board support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/pci.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h>
27#include <asm/mach/time.h>
28
29extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
30
31static int __init
32iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
33{
34 switch (idsel) {
35 case 1:
36 switch (pin) {
37 case 1: return ATUX_INTB;
38 case 2: return ATUX_INTC;
39 case 3: return ATUX_INTD;
40 case 4: return ATUX_INTA;
41 default: return -1;
42 }
43 case 2:
44 switch (pin) {
45 case 1: return ATUX_INTC;
46 case 2: return ATUX_INTD;
47 case 3: return ATUX_INTC;
48 case 4: return ATUX_INTD;
49 default: return -1;
50 }
51 default: return -1;
52 }
53}
54
55static struct hw_pci iq81340mc_pci __initdata = {
56 .swizzle = pci_std_swizzle,
57 .nr_controllers = 0,
58 .setup = iop13xx_pci_setup,
59 .map_irq = iq81340mc_pcix_map_irq,
60 .scan = iop13xx_scan_bus,
61 .preinit = iop13xx_pci_init,
62};
63
64static int __init iq81340mc_pci_init(void)
65{
66 iop13xx_atu_select(&iq81340mc_pci);
67 pci_common_init(&iq81340mc_pci);
68 iop13xx_map_pci_memory();
69
70 return 0;
71}
72
73static void __init iq81340mc_init(void)
74{
75 iop13xx_platform_init();
76 iq81340mc_pci_init();
77}
78
79static void __init iq81340mc_timer_init(void)
80{
81 iop13xx_init_time(400000000);
82}
83
84static struct sys_timer iq81340mc_timer = {
85 .init = iq81340mc_timer_init,
86 .offset = iop13xx_gettimeoffset,
87};
88
89MACHINE_START(IQ81340MC, "Intel IQ81340MC")
90 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
91 .phys_io = PHYS_IO,
92 .io_pg_offst = IO_PG_OFFSET,
93 .map_io = iop13xx_map_io,
94 .init_irq = iop13xx_init_irq,
95 .timer = &iq81340mc_timer,
96 .boot_params = BOOT_PARAM_OFFSET,
97 .init_machine = iq81340mc_init,
98MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
new file mode 100644
index 000000000000..6677e14b61bf
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -0,0 +1,100 @@
1/*
2 * iq81340sc board support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/pci.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h>
27#include <asm/mach/time.h>
28
29extern int init_atu;
30
31static int __init
32iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
33{
34 WARN_ON(idsel < 1 || idsel > 2);
35
36 switch (idsel) {
37 case 1:
38 switch (pin) {
39 case 1: return ATUX_INTB;
40 case 2: return ATUX_INTC;
41 case 3: return ATUX_INTD;
42 case 4: return ATUX_INTA;
43 default: return -1;
44 }
45 case 2:
46 switch (pin) {
47 case 1: return ATUX_INTC;
48 case 2: return ATUX_INTC;
49 case 3: return ATUX_INTC;
50 case 4: return ATUX_INTC;
51 default: return -1;
52 }
53 default: return -1;
54 }
55}
56
57static struct hw_pci iq81340sc_pci __initdata = {
58 .swizzle = pci_std_swizzle,
59 .nr_controllers = 0,
60 .setup = iop13xx_pci_setup,
61 .scan = iop13xx_scan_bus,
62 .map_irq = iq81340sc_atux_map_irq,
63 .preinit = iop13xx_pci_init
64};
65
66static int __init iq81340sc_pci_init(void)
67{
68 iop13xx_atu_select(&iq81340sc_pci);
69 pci_common_init(&iq81340sc_pci);
70 iop13xx_map_pci_memory();
71
72 return 0;
73}
74
75static void __init iq81340sc_init(void)
76{
77 iop13xx_platform_init();
78 iq81340sc_pci_init();
79}
80
81static void __init iq81340sc_timer_init(void)
82{
83 iop13xx_init_time(400000000);
84}
85
86static struct sys_timer iq81340sc_timer = {
87 .init = iq81340sc_timer_init,
88 .offset = iop13xx_gettimeoffset,
89};
90
91MACHINE_START(IQ81340SC, "Intel IQ81340SC")
92 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
93 .phys_io = PHYS_IO,
94 .io_pg_offst = IO_PG_OFFSET,
95 .map_io = iop13xx_map_io,
96 .init_irq = iop13xx_init_irq,
97 .timer = &iq81340sc_timer,
98 .boot_params = BOOT_PARAM_OFFSET,
99 .init_machine = iq81340sc_init,
100MACHINE_END
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
new file mode 100644
index 000000000000..c4d9c8c5579c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -0,0 +1,286 @@
1/*
2 * iop13xx IRQ handling / support functions
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/sysctl.h>
23#include <asm/uaccess.h>
24#include <asm/mach/irq.h>
25#include <asm/irq.h>
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/arch/irqs.h>
29
30/* INTCTL0 CP6 R0 Page 4
31 */
32static inline u32 read_intctl_0(void)
33{
34 u32 val;
35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
36 return val;
37}
38static inline void write_intctl_0(u32 val)
39{
40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
41}
42
43/* INTCTL1 CP6 R1 Page 4
44 */
45static inline u32 read_intctl_1(void)
46{
47 u32 val;
48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
49 return val;
50}
51static inline void write_intctl_1(u32 val)
52{
53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
54}
55
56/* INTCTL2 CP6 R2 Page 4
57 */
58static inline u32 read_intctl_2(void)
59{
60 u32 val;
61 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
62 return val;
63}
64static inline void write_intctl_2(u32 val)
65{
66 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
67}
68
69/* INTCTL3 CP6 R3 Page 4
70 */
71static inline u32 read_intctl_3(void)
72{
73 u32 val;
74 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
75 return val;
76}
77static inline void write_intctl_3(u32 val)
78{
79 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
80}
81
82/* INTSTR0 CP6 R0 Page 5
83 */
84static inline u32 read_intstr_0(void)
85{
86 u32 val;
87 asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
88 return val;
89}
90static inline void write_intstr_0(u32 val)
91{
92 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
93}
94
95/* INTSTR1 CP6 R1 Page 5
96 */
97static inline u32 read_intstr_1(void)
98{
99 u32 val;
100 asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
101 return val;
102}
103static void write_intstr_1(u32 val)
104{
105 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
106}
107
108/* INTSTR2 CP6 R2 Page 5
109 */
110static inline u32 read_intstr_2(void)
111{
112 u32 val;
113 asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
114 return val;
115}
116static void write_intstr_2(u32 val)
117{
118 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
119}
120
121/* INTSTR3 CP6 R3 Page 5
122 */
123static inline u32 read_intstr_3(void)
124{
125 u32 val;
126 asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
127 return val;
128}
129static void write_intstr_3(u32 val)
130{
131 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
132}
133
134/* INTBASE CP6 R0 Page 2
135 */
136static inline u32 read_intbase(void)
137{
138 u32 val;
139 asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
140 return val;
141}
142static void write_intbase(u32 val)
143{
144 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
145}
146
147/* INTSIZE CP6 R2 Page 2
148 */
149static inline u32 read_intsize(void)
150{
151 u32 val;
152 asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
153 return val;
154}
155static void write_intsize(u32 val)
156{
157 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
158}
159
160/* 0 = Interrupt Masked and 1 = Interrupt not masked */
161static void
162iop13xx_irq_mask0 (unsigned int irq)
163{
164 u32 cp_flags = iop13xx_cp6_save();
165 write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
166 iop13xx_cp6_restore(cp_flags);
167}
168
169static void
170iop13xx_irq_mask1 (unsigned int irq)
171{
172 u32 cp_flags = iop13xx_cp6_save();
173 write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
174 iop13xx_cp6_restore(cp_flags);
175}
176
177static void
178iop13xx_irq_mask2 (unsigned int irq)
179{
180 u32 cp_flags = iop13xx_cp6_save();
181 write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
182 iop13xx_cp6_restore(cp_flags);
183}
184
185static void
186iop13xx_irq_mask3 (unsigned int irq)
187{
188 u32 cp_flags = iop13xx_cp6_save();
189 write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
190 iop13xx_cp6_restore(cp_flags);
191}
192
193static void
194iop13xx_irq_unmask0(unsigned int irq)
195{
196 u32 cp_flags = iop13xx_cp6_save();
197 write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
198 iop13xx_cp6_restore(cp_flags);
199}
200
201static void
202iop13xx_irq_unmask1(unsigned int irq)
203{
204 u32 cp_flags = iop13xx_cp6_save();
205 write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
206 iop13xx_cp6_restore(cp_flags);
207}
208
209static void
210iop13xx_irq_unmask2(unsigned int irq)
211{
212 u32 cp_flags = iop13xx_cp6_save();
213 write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
214 iop13xx_cp6_restore(cp_flags);
215}
216
217static void
218iop13xx_irq_unmask3(unsigned int irq)
219{
220 u32 cp_flags = iop13xx_cp6_save();
221 write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
222 iop13xx_cp6_restore(cp_flags);
223}
224
225static struct irqchip iop13xx_irqchip0 = {
226 .ack = iop13xx_irq_mask0,
227 .mask = iop13xx_irq_mask0,
228 .unmask = iop13xx_irq_unmask0,
229};
230
231static struct irqchip iop13xx_irqchip1 = {
232 .ack = iop13xx_irq_mask1,
233 .mask = iop13xx_irq_mask1,
234 .unmask = iop13xx_irq_unmask1,
235};
236
237static struct irqchip iop13xx_irqchip2 = {
238 .ack = iop13xx_irq_mask2,
239 .mask = iop13xx_irq_mask2,
240 .unmask = iop13xx_irq_unmask2,
241};
242
243static struct irqchip iop13xx_irqchip3 = {
244 .ack = iop13xx_irq_mask3,
245 .mask = iop13xx_irq_mask3,
246 .unmask = iop13xx_irq_unmask3,
247};
248
249void __init iop13xx_init_irq(void)
250{
251 unsigned int i;
252
253 u32 cp_flags = iop13xx_cp6_save();
254
255 /* disable all interrupts */
256 write_intctl_0(0);
257 write_intctl_1(0);
258 write_intctl_2(0);
259 write_intctl_3(0);
260
261 /* treat all as IRQ */
262 write_intstr_0(0);
263 write_intstr_1(0);
264 write_intstr_2(0);
265 write_intstr_3(0);
266
267 /* initialize the interrupt vector generator */
268 write_intbase(INTBASE);
269 write_intsize(INTSIZE_4);
270
271 for(i = 0; i < NR_IOP13XX_IRQS; i++) {
272 if (i < 32)
273 set_irq_chip(i, &iop13xx_irqchip0);
274 else if (i < 64)
275 set_irq_chip(i, &iop13xx_irqchip1);
276 else if (i < 96)
277 set_irq_chip(i, &iop13xx_irqchip2);
278 else
279 set_irq_chip(i, &iop13xx_irqchip3);
280
281 set_irq_handler(i, do_level_IRQ);
282 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
283 }
284
285 iop13xx_cp6_restore(cp_flags);
286}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
new file mode 100644
index 000000000000..89ec70ea3187
--- /dev/null
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -0,0 +1,1113 @@
1/*
2 * iop13xx PCI support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/pci.h>
21#include <linux/delay.h>
22
23#include <asm/irq.h>
24#include <asm/hardware.h>
25#include <asm/sizes.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/pci.h>
28
29#define IOP13XX_PCI_DEBUG 0
30#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
31
32u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
33u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
34static struct pci_bus *pci_bus_atux = 0;
35static struct pci_bus *pci_bus_atue = 0;
36u32 iop13xx_atue_mem_base;
37u32 iop13xx_atux_mem_base;
38size_t iop13xx_atue_mem_size;
39size_t iop13xx_atux_mem_size;
40unsigned long iop13xx_pcibios_min_io = 0;
41unsigned long iop13xx_pcibios_min_mem = 0;
42
43EXPORT_SYMBOL(iop13xx_atue_mem_base);
44EXPORT_SYMBOL(iop13xx_atux_mem_base);
45EXPORT_SYMBOL(iop13xx_atue_mem_size);
46EXPORT_SYMBOL(iop13xx_atux_mem_size);
47
48int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
49static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
50 access */
51
52/* Scan the initialized busses and ioremap the requested memory range
53 */
54void iop13xx_map_pci_memory(void)
55{
56 int atu;
57 struct pci_bus *bus;
58 struct pci_dev *dev;
59 resource_size_t end = 0;
60
61 for (atu = 0; atu < 2; atu++) {
62 bus = atu ? pci_bus_atue : pci_bus_atux;
63 if (bus) {
64 list_for_each_entry(dev, &bus->devices, bus_list) {
65 int i;
66 int max = 7;
67
68 if (dev->subordinate)
69 max = DEVICE_COUNT_RESOURCE;
70
71 for (i = 0; i < max; i++) {
72 struct resource *res = &dev->resource[i];
73 if (res->flags & IORESOURCE_MEM)
74 end = max(res->end, end);
75 }
76 }
77
78 switch(atu) {
79 case 0:
80 iop13xx_atux_mem_size =
81 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
82
83 /* 16MB align the request */
84 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
85 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
86 iop13xx_atux_mem_size += SZ_16M;
87 }
88
89 if (end) {
90 iop13xx_atux_mem_base =
91 (u32) __ioremap_pfn(
92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
93 , 0, iop13xx_atux_mem_size, 0);
94 if (!iop13xx_atux_mem_base) {
95 printk("%s: atux allocation "
96 "failed\n", __FUNCTION__);
97 BUG();
98 }
99 } else
100 iop13xx_atux_mem_size = 0;
101 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
102 __FUNCTION__, atu, iop13xx_atux_mem_size,
103 iop13xx_atux_mem_base);
104 break;
105 case 1:
106 iop13xx_atue_mem_size =
107 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
108
109 /* 16MB align the request */
110 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
111 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
112 iop13xx_atue_mem_size += SZ_16M;
113 }
114
115 if (end) {
116 iop13xx_atue_mem_base =
117 (u32) __ioremap_pfn(
118 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
119 , 0, iop13xx_atue_mem_size, 0);
120 if (!iop13xx_atue_mem_base) {
121 printk("%s: atue allocation "
122 "failed\n", __FUNCTION__);
123 BUG();
124 }
125 } else
126 iop13xx_atue_mem_size = 0;
127 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
128 __FUNCTION__, atu, iop13xx_atue_mem_size,
129 iop13xx_atue_mem_base);
130 break;
131 }
132
133 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
134 atu ? "ATUE" : "ATUX",
135 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
136 SZ_1M,
137 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
138 IOP13XX_PCIX_LOWER_MEM_RA,
139 atu ? iop13xx_atue_mem_base :
140 iop13xx_atux_mem_base);
141 end = 0;
142 }
143
144 }
145}
146
147static inline int iop13xx_atu_function(int atu)
148{
149 int func = 0;
150 /* the function number depends on the value of the
151 * IOP13XX_INTERFACE_SEL_PCIX reset strap
152 * see C-Spec section 3.17
153 */
154 switch(atu) {
155 case IOP13XX_INIT_ATU_ATUX:
156 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
157 func = 5;
158 else
159 func = 0;
160 break;
161 case IOP13XX_INIT_ATU_ATUE:
162 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
163 func = 0;
164 else
165 func = 5;
166 break;
167 default:
168 BUG();
169 }
170
171 return func;
172}
173
174/* iop13xx_atux_cfg_address - format a configuration address for atux
175 * @bus: Target bus to access
176 * @devfn: Combined device number and function number
177 * @where: Desired register's address offset
178 *
179 * Convert the parameters to a configuration address formatted
180 * according the PCI-X 2.0 specification
181 */
182static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
183{
184 struct pci_sys_data *sys = bus->sysdata;
185 u32 addr;
186
187 if (sys->busnr == bus->number)
188 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
189 else
190 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
191
192 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
193 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
194
195 return addr;
196}
197
198/* iop13xx_atue_cfg_address - format a configuration address for atue
199 * @bus: Target bus to access
200 * @devfn: Combined device number and function number
201 * @where: Desired register's address offset
202 *
203 * Convert the parameters to an address usable by the ATUE_OCCAR
204 */
205static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
206{
207 struct pci_sys_data *sys = bus->sysdata;
208 u32 addr;
209
210 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
211 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
212 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
213 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
214 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
215 (where & ~0x3);
216
217 if (sys->busnr != bus->number)
218 addr |= 1; /* type 1 access */
219
220 return addr;
221}
222
223/* This routine checks the status of the last configuration cycle. If an error
224 * was detected it returns >0, else it returns a 0. The errors being checked
225 * are parity, master abort, target abort (master and target). These types of
226 * errors occure during a config cycle where there is no device, like during
227 * the discovery stage.
228 */
229static int iop13xx_atux_pci_status(int clear)
230{
231 unsigned int status;
232 int err = 0;
233
234 /*
235 * Check the status registers.
236 */
237 status = __raw_readw(IOP13XX_ATUX_ATUSR);
238 if (status & IOP_PCI_STATUS_ERROR)
239 {
240 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
241 if(clear)
242 __raw_writew(status & IOP_PCI_STATUS_ERROR,
243 IOP13XX_ATUX_ATUSR);
244 err = 1;
245 }
246 status = __raw_readl(IOP13XX_ATUX_ATUISR);
247 if (status & IOP13XX_ATUX_ATUISR_ERROR)
248 {
249 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
250 if(clear)
251 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
252 IOP13XX_ATUX_ATUISR);
253 err = 1;
254 }
255 return err;
256}
257
258/* Simply write the address register and read the configuration
259 * data. Note that the data dependency on %0 encourages an abort
260 * to be detected before we return.
261 */
262static inline u32 iop13xx_atux_read(unsigned long addr)
263{
264 u32 val;
265
266 __asm__ __volatile__(
267 "str %1, [%2]\n\t"
268 "ldr %0, [%3]\n\t"
269 "mov %0, %0\n\t"
270 : "=r" (val)
271 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
272
273 return val;
274}
275
276/* The read routines must check the error status of the last configuration
277 * cycle. If there was an error, the routine returns all hex f's.
278 */
279static int
280iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
281 int size, u32 *value)
282{
283 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
284 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
285
286 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
287 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
288 IOP13XX_XBG_BECSR);
289 val = 0xffffffff;
290 }
291
292 *value = val;
293
294 return PCIBIOS_SUCCESSFUL;
295}
296
297static int
298iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
299 int size, u32 value)
300{
301 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
302 u32 val;
303
304 if (size != 4) {
305 val = iop13xx_atux_read(addr);
306 if (!iop13xx_atux_pci_status(1) == 0)
307 return PCIBIOS_SUCCESSFUL;
308
309 where = (where & 3) * 8;
310
311 if (size == 1)
312 val &= ~(0xff << where);
313 else
314 val &= ~(0xffff << where);
315
316 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
317 } else {
318 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
319 __raw_writel(value, IOP13XX_ATUX_OCCDR);
320 }
321
322 return PCIBIOS_SUCCESSFUL;
323}
324
325static struct pci_ops iop13xx_atux_ops = {
326 .read = iop13xx_atux_read_config,
327 .write = iop13xx_atux_write_config,
328};
329
330/* This routine checks the status of the last configuration cycle. If an error
331 * was detected it returns >0, else it returns a 0. The errors being checked
332 * are parity, master abort, target abort (master and target). These types of
333 * errors occure during a config cycle where there is no device, like during
334 * the discovery stage.
335 */
336static int iop13xx_atue_pci_status(int clear)
337{
338 unsigned int status;
339 int err = 0;
340
341 /*
342 * Check the status registers.
343 */
344
345 /* standard pci status register */
346 status = __raw_readw(IOP13XX_ATUE_ATUSR);
347 if (status & IOP_PCI_STATUS_ERROR) {
348 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
349 if(clear)
350 __raw_writew(status & IOP_PCI_STATUS_ERROR,
351 IOP13XX_ATUE_ATUSR);
352 err++;
353 }
354
355 /* check the normal status bits in the ATUISR */
356 status = __raw_readl(IOP13XX_ATUE_ATUISR);
357 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
358 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
359 if (clear)
360 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
361 IOP13XX_ATUE_ATUISR);
362 err++;
363
364 /* check the PCI-E status if the ATUISR reports an interface error */
365 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
366 /* get the unmasked errors */
367 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
368 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
369
370 if (status) {
371 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
372 __raw_readl(IOP13XX_ATUE_PIE_STS));
373 err++;
374 } else {
375 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
376 __raw_readl(IOP13XX_ATUE_PIE_STS));
377 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
378 __raw_readl(IOP13XX_ATUE_PIE_MSK));
379 BUG();
380 }
381
382 if(clear)
383 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
384 }
385 }
386
387 return err;
388}
389
390static inline int __init
391iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
392{
393 WARN_ON(idsel != 0);
394
395 switch (pin) {
396 case 1: return ATUE_INTA;
397 case 2: return ATUE_INTB;
398 case 3: return ATUE_INTC;
399 case 4: return ATUE_INTD;
400 default: return -1;
401 }
402}
403
404static inline u32 iop13xx_atue_read(unsigned long addr)
405{
406 u32 val;
407
408 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
409 val = __raw_readl(IOP13XX_ATUE_OCCDR);
410
411 rmb();
412
413 return val;
414}
415
416/* The read routines must check the error status of the last configuration
417 * cycle. If there was an error, the routine returns all hex f's.
418 */
419static int
420iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
421 int size, u32 *value)
422{
423 u32 val;
424 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
425
426 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
427 if (!PCI_SLOT(devfn) || (addr & 1)) {
428 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
429 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
430 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
431 IOP13XX_XBG_BECSR);
432 val = 0xffffffff;
433 }
434
435 PRINTK("addr=%#0lx, val=%#010x", addr, val);
436 } else
437 val = 0xffffffff;
438
439 *value = val;
440
441 return PCIBIOS_SUCCESSFUL;
442}
443
444static int
445iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
446 int size, u32 value)
447{
448 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
449 u32 val;
450
451 if (size != 4) {
452 val = iop13xx_atue_read(addr);
453 if (!iop13xx_atue_pci_status(1) == 0)
454 return PCIBIOS_SUCCESSFUL;
455
456 where = (where & 3) * 8;
457
458 if (size == 1)
459 val &= ~(0xff << where);
460 else
461 val &= ~(0xffff << where);
462
463 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
464 } else {
465 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
466 __raw_writel(value, IOP13XX_ATUE_OCCDR);
467 }
468
469 return PCIBIOS_SUCCESSFUL;
470}
471
472static struct pci_ops iop13xx_atue_ops = {
473 .read = iop13xx_atue_read_config,
474 .write = iop13xx_atue_write_config,
475};
476
477/* When a PCI device does not exist during config cycles, the XScale gets a
478 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
479 * bits to tell us that it was indeed a configuration cycle that caused this
480 * error especially in the case when the ATUE link is down. Instead we rely
481 * on data from the south XSI bridge to validate the abort
482 */
483int
484iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
485{
486 PRINTK("Data abort: address = 0x%08lx "
487 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
488 addr, fsr, regs->ARM_pc, regs->ARM_lr);
489
490 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
491 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
492 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
493
494 /* If it was an imprecise abort, then we need to correct the
495 * return address to be _after_ the instruction.
496 */
497 if (fsr & (1 << 10))
498 regs->ARM_pc += 4;
499
500 if (is_atue_occdr_error() || is_atux_occdr_error())
501 return 0;
502 else
503 return 1;
504}
505
506/* Scan an IOP13XX PCI bus. nr selects which ATU we use.
507 */
508struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
509{
510 int which_atu;
511 struct pci_bus *bus = NULL;
512
513 switch (init_atu) {
514 case IOP13XX_INIT_ATU_ATUX:
515 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
516 break;
517 case IOP13XX_INIT_ATU_ATUE:
518 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
519 break;
520 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
521 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
522 break;
523 default:
524 which_atu = 0;
525 }
526
527 if (!which_atu) {
528 BUG();
529 return NULL;
530 }
531
532 switch (which_atu) {
533 case IOP13XX_INIT_ATU_ATUX:
534 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
535 atux_trhfa_timeout)) /* ensure not wrap */
536 while(time_before(jiffies, atux_trhfa_timeout))
537 udelay(100);
538
539 bus = pci_bus_atux = pci_scan_bus(sys->busnr,
540 &iop13xx_atux_ops,
541 sys);
542 break;
543 case IOP13XX_INIT_ATU_ATUE:
544 bus = pci_bus_atue = pci_scan_bus(sys->busnr,
545 &iop13xx_atue_ops,
546 sys);
547 break;
548 }
549
550 return bus;
551}
552
553/* This function is called from iop13xx_pci_init() after assigning valid
554 * values to iop13xx_atue_pmmr_offset. This is the location for common
555 * setup of ATUE for all IOP13XX implementations.
556 */
557void __init iop13xx_atue_setup(void)
558{
559 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
560 u32 reg_val;
561
562 /* BAR 1 (1:1 mapping with Physical RAM) */
563 /* Set limit and enable */
564 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
565 IOP13XX_ATUE_IALR1);
566 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
567
568 /* Set base at the top of the reserved address space */
569 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
570 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
571
572 /* 1:1 mapping with physical ram
573 * (leave big endian byte swap disabled)
574 */
575 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
576 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
577
578 /* Outbound window 1 (PCIX/PCIE memory window) */
579 /* 32 bit Address Space */
580 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
581 /* PA[35:32] */
582 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
583 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
584 IOP13XX_ATUE_OUMBAR1);
585
586 /* Setup the I/O Bar
587 * A[35-16] in 31-12
588 */
589 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
590 IOP13XX_ATUE_OIOBAR);
591 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
592
593 /* clear startup errors */
594 iop13xx_atue_pci_status(1);
595
596 /* OIOBAR function number
597 */
598 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
599 reg_val &= ~0x7;
600 reg_val |= func;
601 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
602
603 /* OUMBAR function numbers
604 */
605 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
606 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
607 IOP13XX_ATU_OUMBAR_FUNC_NUM);
608 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
609 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
610
611 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
612 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
613 IOP13XX_ATU_OUMBAR_FUNC_NUM);
614 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
615 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
616
617 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
618 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
619 IOP13XX_ATU_OUMBAR_FUNC_NUM);
620 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
621 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
622
623 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
624 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
625 IOP13XX_ATU_OUMBAR_FUNC_NUM);
626 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
627 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
628
629 /* Enable inbound and outbound cycles
630 */
631 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
632 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
633 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
634 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
635
636 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
637 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
638 IOP13XX_ATUE_ATUCR_IVM;
639 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
640}
641
642void __init iop13xx_atue_disable(void)
643{
644 u32 reg_val;
645
646 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
647 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
648
649 /* wait for cycles to quiesce */
650 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
651 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
652 IOP13XX_ATUE_PCSR_LLRB_BUSY))
653 cpu_relax();
654
655 /* BAR 0 ( Disabled ) */
656 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
657 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
658 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
659 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
660 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
661 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
662 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
663 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
664
665 /* BAR 1 ( Disabled ) */
666 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
667 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
668 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
669 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
670 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
671 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
672 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
673 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
674
675 /* BAR 2 ( Disabled ) */
676 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
677 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
678 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
679 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
680 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
681 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
682 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
683 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
684
685 /* BAR 3 ( Disabled ) */
686 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
687 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
688 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
689
690 /* Setup the I/O Bar
691 * A[35-16] in 31-12
692 */
693 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
694 IOP13XX_ATUE_OIOBAR);
695 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
696}
697
698/* This function is called from iop13xx_pci_init() after assigning valid
699 * values to iop13xx_atux_pmmr_offset. This is the location for common
700 * setup of ATUX for all IOP13XX implementations.
701 */
702void __init iop13xx_atux_setup(void)
703{
704 u32 reg_val;
705 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
706
707 /* Take PCI-X bus out of reset if bootloader hasn't already.
708 * According to spec, we should wait for 2^25 PCI clocks to meet
709 * the PCI timing parameter Trhfa (RST# high to first access).
710 * This is rarely necessary and often ignored.
711 */
712 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
713 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
714 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
715 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
716 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
717 IOP13XX_ATUX_PCSR);
718 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
719 }
720 else
721 atux_trhfa_timeout = jiffies;
722
723 /* BAR 1 (1:1 mapping with Physical RAM) */
724 /* Set limit and enable */
725 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
726 IOP13XX_ATUX_IALR1);
727 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
728
729 /* Set base at the top of the reserved address space */
730 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
731 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
732
733 /* 1:1 mapping with physical ram
734 * (leave big endian byte swap disabled)
735 */
736 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
737 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
738
739 /* Outbound window 1 (PCIX/PCIE memory window) */
740 /* 32 bit Address Space */
741 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
742 /* PA[35:32] */
743 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
744 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
745 IOP13XX_ATUX_OUMBAR1);
746
747 /* Setup the I/O Bar
748 * A[35-16] in 31-12
749 */
750 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
751 IOP13XX_ATUX_OIOBAR);
752 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
753
754 /* clear startup errors */
755 iop13xx_atux_pci_status(1);
756
757 /* OIOBAR function number
758 */
759 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
760 reg_val &= ~0x7;
761 reg_val |= func;
762 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
763
764 /* OUMBAR function numbers
765 */
766 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
767 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
768 IOP13XX_ATU_OUMBAR_FUNC_NUM);
769 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
770 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
771
772 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
773 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
774 IOP13XX_ATU_OUMBAR_FUNC_NUM);
775 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
776 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
777
778 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
779 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
780 IOP13XX_ATU_OUMBAR_FUNC_NUM);
781 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
782 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
783
784 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
785 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
786 IOP13XX_ATU_OUMBAR_FUNC_NUM);
787 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
788 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
789
790 /* Enable inbound and outbound cycles
791 */
792 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
793 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
794 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
795 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
796
797 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
798 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
799 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
800}
801
802void __init iop13xx_atux_disable(void)
803{
804 u32 reg_val;
805
806 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
807 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
808
809 /* wait for cycles to quiesce */
810 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
811 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
812 cpu_relax();
813
814 /* BAR 0 ( Disabled ) */
815 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
816 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
817 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
818 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
819 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
820 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
821 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
822 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
823
824 /* BAR 1 ( Disabled ) */
825 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
826 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
827 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
828 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
829 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
830 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
831 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
832 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
833
834 /* BAR 2 ( Disabled ) */
835 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
836 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
837 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
838 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
839 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
840 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
841 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
842 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
843
844 /* BAR 3 ( Disabled ) */
845 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
846 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
847 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
848 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
849 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
850 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
851 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
852 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
853
854 /* Setup the I/O Bar
855 * A[35-16] in 31-12
856 */
857 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
858 IOP13XX_ATUX_OIOBAR);
859 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
860}
861
862void __init iop13xx_set_atu_mmr_bases(void)
863{
864 /* Based on ESSR0, determine the ATU X/E offsets */
865 switch(__raw_readl(IOP13XX_ESSR0) &
866 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
867 /* both asserted */
868 case 0:
869 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
870 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
871 break;
872 /* IOP13XX_CONTROLLER_ONLY = deasserted
873 * IOP13XX_INTERFACE_SEL_PCIX = asserted
874 */
875 case IOP13XX_CONTROLLER_ONLY:
876 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
877 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
878 break;
879 /* IOP13XX_CONTROLLER_ONLY = asserted
880 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
881 */
882 case IOP13XX_INTERFACE_SEL_PCIX:
883 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
884 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
885 break;
886 /* both deasserted */
887 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
888 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
889 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
890 break;
891 default:
892 BUG();
893 }
894}
895
896void __init iop13xx_atu_select(struct hw_pci *plat_pci)
897{
898 int i;
899
900 /* set system defaults
901 * note: if "iop13xx_init_atu=" is specified this autodetect
902 * sequence will be bypassed
903 */
904 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
905 /* check for single/dual interface */
906 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
907 /* ATUE must be present check the device id
908 * to see if ATUX is present.
909 */
910 init_atu |= IOP13XX_INIT_ATU_ATUE;
911 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
912 case 0x70:
913 case 0x80:
914 case 0xc0:
915 init_atu |= IOP13XX_INIT_ATU_ATUX;
916 break;
917 }
918 } else {
919 /* ATUX must be present check the device id
920 * to see if ATUE is present.
921 */
922 init_atu |= IOP13XX_INIT_ATU_ATUX;
923 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
924 case 0x70:
925 case 0x80:
926 case 0xc0:
927 init_atu |= IOP13XX_INIT_ATU_ATUE;
928 break;
929 }
930 }
931
932 /* check central resource and root complex capability */
933 if (init_atu & IOP13XX_INIT_ATU_ATUX)
934 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
935 IOP13XX_ATUX_PCSR_CENTRAL_RES))
936 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
937
938 if (init_atu & IOP13XX_INIT_ATU_ATUE)
939 if (__raw_readl(IOP13XX_ATUE_PCSR) &
940 IOP13XX_ATUE_PCSR_END_POINT)
941 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
942 }
943
944 for (i = 0; i < 2; i++) {
945 if((init_atu & (1 << i)) == (1 << i))
946 plat_pci->nr_controllers++;
947 }
948}
949
950void __init iop13xx_pci_init(void)
951{
952 /* clear pre-existing south bridge errors */
953 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
954
955 /* Setup the Min Address for PCI memory... */
956 iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
957
958 /* if Linux is given control of an ATU
959 * clear out its prior configuration,
960 * otherwise do not touch the registers
961 */
962 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
963 iop13xx_atue_disable();
964 iop13xx_atue_setup();
965 }
966
967 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
968 iop13xx_atux_disable();
969 iop13xx_atux_setup();
970 }
971
972 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
973 "imprecise external abort");
974}
975
976/* intialize the pci memory space. handle any combination of
977 * atue and atux enabled/disabled
978 */
979int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
980{
981 struct resource *res;
982 int which_atu;
983 u32 pcixsr, pcsr;
984
985 if (nr > 1)
986 return 0;
987
988 res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
989 if (!res)
990 panic("PCI: unable to alloc resources");
991
992 memset(res, 0, sizeof(struct resource) * 2);
993
994 /* 'nr' assumptions:
995 * ATUX is always 0
996 * ATUE is 1 when ATUX is also enabled
997 * ATUE is 0 when ATUX is disabled
998 */
999 switch(init_atu) {
1000 case IOP13XX_INIT_ATU_ATUX:
1001 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1002 break;
1003 case IOP13XX_INIT_ATU_ATUE:
1004 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1005 break;
1006 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1007 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1008 break;
1009 default:
1010 which_atu = 0;
1011 }
1012
1013 if (!which_atu)
1014 return 0;
1015
1016 switch(which_atu) {
1017 case IOP13XX_INIT_ATU_ATUX:
1018 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1019 pcixsr &= ~0xffff;
1020 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1021 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1022 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1023 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1024 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1025
1026 res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
1027 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1028 res[0].name = "IQ81340 ATUX PCI I/O Space";
1029 res[0].flags = IORESOURCE_IO;
1030
1031 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
1032 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
1033 res[1].name = "IQ81340 ATUX PCI Memory Space";
1034 res[1].flags = IORESOURCE_MEM;
1035 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1036 sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
1037 break;
1038 case IOP13XX_INIT_ATU_ATUE:
1039 /* Note: the function number field in the PCSR is ro */
1040 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1041 pcsr &= ~(0xfff8 << 16);
1042 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1043 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1044
1045 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1046
1047 res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
1048 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1049 res[0].name = "IQ81340 ATUE PCI I/O Space";
1050 res[0].flags = IORESOURCE_IO;
1051
1052 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
1053 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
1054 res[1].name = "IQ81340 ATUE PCI Memory Space";
1055 res[1].flags = IORESOURCE_MEM;
1056 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1057 sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
1058 sys->map_irq = iop13xx_pcie_map_irq;
1059 break;
1060 default:
1061 return 0;
1062 }
1063
1064 request_resource(&ioport_resource, &res[0]);
1065 request_resource(&iomem_resource, &res[1]);
1066
1067 sys->resource[0] = &res[0];
1068 sys->resource[1] = &res[1];
1069 sys->resource[2] = NULL;
1070
1071 return 1;
1072}
1073
1074u16 iop13xx_dev_id(void)
1075{
1076 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1077 return __raw_readw(IOP13XX_ATUE_DID);
1078 else
1079 return __raw_readw(IOP13XX_ATUX_DID);
1080}
1081
1082static int __init iop13xx_init_atu_setup(char *str)
1083{
1084 init_atu = IOP13XX_INIT_ATU_NONE;
1085 if (str) {
1086 while (*str != '\0') {
1087 switch (*str) {
1088 case 'x':
1089 case 'X':
1090 init_atu |= IOP13XX_INIT_ATU_ATUX;
1091 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1092 break;
1093 case 'e':
1094 case 'E':
1095 init_atu |= IOP13XX_INIT_ATU_ATUE;
1096 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1097 break;
1098 case ',':
1099 case '=':
1100 break;
1101 default:
1102 PRINTK("\"iop13xx_init_atu\" malformed at "
1103 "character: \'%c\'", *str);
1104 *(str + 1) = '\0';
1105 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1106 }
1107 str++;
1108 }
1109 }
1110 return 1;
1111}
1112
1113__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
new file mode 100644
index 000000000000..3756d2ccb1a7
--- /dev/null
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -0,0 +1,406 @@
1/*
2 * iop13xx platform Initialization
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/serial_8250.h>
21#ifdef CONFIG_MTD_PHYSMAP
22#include <linux/mtd/physmap.h>
23#endif
24#include <asm/mach/map.h>
25#include <asm/hardware.h>
26#include <asm/irq.h>
27
28#define IOP13XX_UART_XTAL 33334000
29#define IOP13XX_SETUP_DEBUG 0
30#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
31
32/* Standard IO mapping for all IOP13XX based systems
33 */
34static struct map_desc iop13xx_std_desc[] __initdata = {
35 { /* mem mapped registers */
36 .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
37 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
38 .length = IOP13XX_PMMR_SIZE,
39 .type = MT_DEVICE,
40 }, { /* PCIE IO space */
41 .virtual = IOP13XX_PCIE_LOWER_IO_VA,
42 .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
43 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
44 .type = MT_DEVICE,
45 }, { /* PCIX IO space */
46 .virtual = IOP13XX_PCIX_LOWER_IO_VA,
47 .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
48 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
49 .type = MT_DEVICE,
50 },
51};
52
53static struct resource iop13xx_uart0_resources[] = {
54 [0] = {
55 .start = IOP13XX_UART0_PHYS,
56 .end = IOP13XX_UART0_PHYS + 0x3f,
57 .flags = IORESOURCE_MEM,
58 },
59 [1] = {
60 .start = IRQ_IOP13XX_UART0,
61 .end = IRQ_IOP13XX_UART0,
62 .flags = IORESOURCE_IRQ
63 }
64};
65
66static struct resource iop13xx_uart1_resources[] = {
67 [0] = {
68 .start = IOP13XX_UART1_PHYS,
69 .end = IOP13XX_UART1_PHYS + 0x3f,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = IRQ_IOP13XX_UART1,
74 .end = IRQ_IOP13XX_UART1,
75 .flags = IORESOURCE_IRQ
76 }
77};
78
79static struct plat_serial8250_port iop13xx_uart0_data[] = {
80 {
81 .membase = (char*)(IOP13XX_UART0_VIRT),
82 .mapbase = (IOP13XX_UART0_PHYS),
83 .irq = IRQ_IOP13XX_UART0,
84 .uartclk = IOP13XX_UART_XTAL,
85 .regshift = 2,
86 .iotype = UPIO_MEM,
87 .flags = UPF_SKIP_TEST,
88 },
89 { },
90};
91
92static struct plat_serial8250_port iop13xx_uart1_data[] = {
93 {
94 .membase = (char*)(IOP13XX_UART1_VIRT),
95 .mapbase = (IOP13XX_UART1_PHYS),
96 .irq = IRQ_IOP13XX_UART1,
97 .uartclk = IOP13XX_UART_XTAL,
98 .regshift = 2,
99 .iotype = UPIO_MEM,
100 .flags = UPF_SKIP_TEST,
101 },
102 { },
103};
104
105/* The ids are fixed up later in iop13xx_platform_init */
106static struct platform_device iop13xx_uart0 = {
107 .name = "serial8250",
108 .id = 0,
109 .dev.platform_data = iop13xx_uart0_data,
110 .num_resources = 2,
111 .resource = iop13xx_uart0_resources,
112};
113
114static struct platform_device iop13xx_uart1 = {
115 .name = "serial8250",
116 .id = 0,
117 .dev.platform_data = iop13xx_uart1_data,
118 .num_resources = 2,
119 .resource = iop13xx_uart1_resources
120};
121
122static struct resource iop13xx_i2c_0_resources[] = {
123 [0] = {
124 .start = IOP13XX_I2C0_PHYS,
125 .end = IOP13XX_I2C0_PHYS + 0x18,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = IRQ_IOP13XX_I2C_0,
130 .end = IRQ_IOP13XX_I2C_0,
131 .flags = IORESOURCE_IRQ
132 }
133};
134
135static struct resource iop13xx_i2c_1_resources[] = {
136 [0] = {
137 .start = IOP13XX_I2C1_PHYS,
138 .end = IOP13XX_I2C1_PHYS + 0x18,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 .start = IRQ_IOP13XX_I2C_1,
143 .end = IRQ_IOP13XX_I2C_1,
144 .flags = IORESOURCE_IRQ
145 }
146};
147
148static struct resource iop13xx_i2c_2_resources[] = {
149 [0] = {
150 .start = IOP13XX_I2C2_PHYS,
151 .end = IOP13XX_I2C2_PHYS + 0x18,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = IRQ_IOP13XX_I2C_2,
156 .end = IRQ_IOP13XX_I2C_2,
157 .flags = IORESOURCE_IRQ
158 }
159};
160
161/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
162 * we just use the same device name.
163 */
164
165/* The ids are fixed up later in iop13xx_platform_init */
166static struct platform_device iop13xx_i2c_0_controller = {
167 .name = "IOP3xx-I2C",
168 .id = 0,
169 .num_resources = 2,
170 .resource = iop13xx_i2c_0_resources
171};
172
173static struct platform_device iop13xx_i2c_1_controller = {
174 .name = "IOP3xx-I2C",
175 .id = 0,
176 .num_resources = 2,
177 .resource = iop13xx_i2c_1_resources
178};
179
180static struct platform_device iop13xx_i2c_2_controller = {
181 .name = "IOP3xx-I2C",
182 .id = 0,
183 .num_resources = 2,
184 .resource = iop13xx_i2c_2_resources
185};
186
187#ifdef CONFIG_MTD_PHYSMAP
188/* PBI Flash Device
189 */
190static struct physmap_flash_data iq8134x_flash_data = {
191 .width = 2,
192};
193
194static struct resource iq8134x_flash_resource = {
195 .start = IQ81340_FLASHBASE,
196 .end = 0,
197 .flags = IORESOURCE_MEM,
198};
199
200static struct platform_device iq8134x_flash = {
201 .name = "physmap-flash",
202 .id = 0,
203 .dev = { .platform_data = &iq8134x_flash_data, },
204 .num_resources = 1,
205 .resource = &iq8134x_flash_resource,
206};
207
208static unsigned long iq8134x_probe_flash_size(void)
209{
210 uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
211 int i;
212 char query[3];
213 unsigned long size = 0;
214 int width = iq8134x_flash_data.width;
215
216 if (flash_addr) {
217 /* send CFI 'query' command */
218 writew(0x98, flash_addr);
219
220 /* check for CFI compliance */
221 for (i = 0; i < 3 * width; i += width)
222 query[i / width] = readb(flash_addr + (0x10 * width) + i);
223
224 /* read the size */
225 if (memcmp(query, "QRY", 3) == 0)
226 size = 1 << readb(flash_addr + (0x27 * width));
227
228 /* send CFI 'read array' command */
229 writew(0xff, flash_addr);
230
231 iounmap(flash_addr);
232 }
233
234 return size;
235}
236#endif
237
238void __init iop13xx_map_io(void)
239{
240 /* Initialize the Static Page Table maps */
241 iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
242}
243
244static int init_uart = 0;
245static int init_i2c = 0;
246
247void __init iop13xx_platform_init(void)
248{
249 int i;
250 u32 uart_idx, i2c_idx, plat_idx;
251 struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
252
253 /* set the bases so we can read the device id */
254 iop13xx_set_atu_mmr_bases();
255
256 memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
257
258 if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
259 switch (iop13xx_dev_id()) {
260 /* enable both uarts on iop341 and iop342 */
261 case 0x3380:
262 case 0x3384:
263 case 0x3388:
264 case 0x338c:
265 case 0x3382:
266 case 0x3386:
267 case 0x338a:
268 case 0x338e:
269 init_uart |= IOP13XX_INIT_UART_0;
270 init_uart |= IOP13XX_INIT_UART_1;
271 break;
272 /* only enable uart 1 */
273 default:
274 init_uart |= IOP13XX_INIT_UART_1;
275 }
276 }
277
278 if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
279 switch (iop13xx_dev_id()) {
280 /* enable all i2c units on iop341 and iop342 */
281 case 0x3380:
282 case 0x3384:
283 case 0x3388:
284 case 0x338c:
285 case 0x3382:
286 case 0x3386:
287 case 0x338a:
288 case 0x338e:
289 init_i2c |= IOP13XX_INIT_I2C_0;
290 init_i2c |= IOP13XX_INIT_I2C_1;
291 init_i2c |= IOP13XX_INIT_I2C_2;
292 break;
293 /* only enable i2c 1 and 2 */
294 default:
295 init_i2c |= IOP13XX_INIT_I2C_1;
296 init_i2c |= IOP13XX_INIT_I2C_2;
297 }
298 }
299
300 plat_idx = 0;
301 uart_idx = 0;
302 i2c_idx = 0;
303
304 /* uart 1 (if enabled) is ttyS0 */
305 if (init_uart & IOP13XX_INIT_UART_1) {
306 PRINTK("Adding uart1 to platform device list\n");
307 iop13xx_uart1.id = uart_idx++;
308 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
309 }
310 if (init_uart & IOP13XX_INIT_UART_0) {
311 PRINTK("Adding uart0 to platform device list\n");
312 iop13xx_uart0.id = uart_idx++;
313 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
314 }
315
316 for(i = 0; i < IQ81340_NUM_I2C; i++) {
317 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
318 printk("Adding i2c%d to platform device list\n", i);
319 switch(init_i2c & (1 << i)) {
320 case IOP13XX_INIT_I2C_0:
321 iop13xx_i2c_0_controller.id = i2c_idx++;
322 iop13xx_devices[plat_idx++] =
323 &iop13xx_i2c_0_controller;
324 break;
325 case IOP13XX_INIT_I2C_1:
326 iop13xx_i2c_1_controller.id = i2c_idx++;
327 iop13xx_devices[plat_idx++] =
328 &iop13xx_i2c_1_controller;
329 break;
330 case IOP13XX_INIT_I2C_2:
331 iop13xx_i2c_2_controller.id = i2c_idx++;
332 iop13xx_devices[plat_idx++] =
333 &iop13xx_i2c_2_controller;
334 break;
335 }
336 }
337
338#ifdef CONFIG_MTD_PHYSMAP
339 iq8134x_flash_resource.end = iq8134x_flash_resource.start +
340 iq8134x_probe_flash_size();
341 if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
342 iop13xx_devices[plat_idx++] = &iq8134x_flash;
343 else
344 printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
345#endif
346
347 platform_add_devices(iop13xx_devices, plat_idx);
348}
349
350static int __init iop13xx_init_uart_setup(char *str)
351{
352 if (str) {
353 while (*str != '\0') {
354 switch(*str) {
355 case '0':
356 init_uart |= IOP13XX_INIT_UART_0;
357 break;
358 case '1':
359 init_uart |= IOP13XX_INIT_UART_1;
360 break;
361 case ',':
362 case '=':
363 break;
364 default:
365 PRINTK("\"iop13xx_init_uart\" malformed"
366 " at character: \'%c\'", *str);
367 *(str + 1) = '\0';
368 init_uart = IOP13XX_INIT_UART_DEFAULT;
369 }
370 str++;
371 }
372 }
373 return 1;
374}
375
376static int __init iop13xx_init_i2c_setup(char *str)
377{
378 if (str) {
379 while (*str != '\0') {
380 switch(*str) {
381 case '0':
382 init_i2c |= IOP13XX_INIT_I2C_0;
383 break;
384 case '1':
385 init_i2c |= IOP13XX_INIT_I2C_1;
386 break;
387 case '2':
388 init_i2c |= IOP13XX_INIT_I2C_2;
389 break;
390 case ',':
391 case '=':
392 break;
393 default:
394 PRINTK("\"iop13xx_init_i2c\" malformed"
395 " at character: \'%c\'", *str);
396 *(str + 1) = '\0';
397 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
398 }
399 str++;
400 }
401 }
402 return 1;
403}
404
405__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
406__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c
new file mode 100644
index 000000000000..8b21365f653f
--- /dev/null
+++ b/arch/arm/mach-iop13xx/time.c
@@ -0,0 +1,102 @@
1/*
2 * arch/arm/mach-iop13xx/time.c
3 *
4 * Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2002-2003 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/time.h>
19#include <linux/init.h>
20#include <linux/timex.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/uaccess.h>
24#include <asm/mach/irq.h>
25#include <asm/mach/time.h>
26
27static unsigned long ticks_per_jiffy;
28static unsigned long ticks_per_usec;
29static unsigned long next_jiffy_time;
30
31static inline u32 read_tcr1(void)
32{
33 u32 val;
34 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
35 return val;
36}
37
38unsigned long iop13xx_gettimeoffset(void)
39{
40 unsigned long offset;
41 u32 cp_flags;
42
43 cp_flags = iop13xx_cp6_save();
44 offset = next_jiffy_time - read_tcr1();
45 iop13xx_cp6_restore(cp_flags);
46
47 return offset / ticks_per_usec;
48}
49
50static irqreturn_t
51iop13xx_timer_interrupt(int irq, void *dev_id)
52{
53 u32 cp_flags = iop13xx_cp6_save();
54
55 write_seqlock(&xtime_lock);
56
57 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
58
59 while ((signed long)(next_jiffy_time - read_tcr1())
60 >= ticks_per_jiffy) {
61 timer_tick();
62 next_jiffy_time -= ticks_per_jiffy;
63 }
64
65 write_sequnlock(&xtime_lock);
66
67 iop13xx_cp6_restore(cp_flags);
68
69 return IRQ_HANDLED;
70}
71
72static struct irqaction iop13xx_timer_irq = {
73 .name = "IOP13XX Timer Tick",
74 .handler = iop13xx_timer_interrupt,
75 .flags = IRQF_DISABLED | IRQF_TIMER,
76};
77
78void __init iop13xx_init_time(unsigned long tick_rate)
79{
80 u32 timer_ctl;
81 u32 cp_flags;
82
83 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
84 ticks_per_usec = tick_rate / 1000000;
85 next_jiffy_time = 0xffffffff;
86
87 timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
88 IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
89
90 /*
91 * We use timer 0 for our timer interrupt, and timer 1 as
92 * monotonic counter for tracking missed jiffies.
93 */
94 cp_flags = iop13xx_cp6_save();
95 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
96 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
97 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
98 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
99 iop13xx_cp6_restore(cp_flags);
100
101 setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
102}
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 69d6302f40cf..3ec1cd5c4f99 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -70,7 +70,7 @@ void __init iop32x_init_irq(void)
70 70
71 for (i = 0; i < NR_IRQS; i++) { 71 for (i = 0; i < NR_IRQS; i++) {
72 set_irq_chip(i, &ext_chip); 72 set_irq_chip(i, &ext_chip);
73 set_irq_handler(i, do_level_IRQ); 73 set_irq_handler(i, handle_level_irq);
74 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 74 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
75 } 75 }
76} 76}
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 63304b3d0d76..00b37f32d72e 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -121,7 +121,7 @@ void __init iop33x_init_irq(void)
121 121
122 for (i = 0; i < NR_IRQS; i++) { 122 for (i = 0; i < NR_IRQS; i++) {
123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); 123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
124 set_irq_handler(i, do_level_IRQ); 124 set_irq_handler(i, handle_level_irq);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 } 126 }
127} 127}
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 22c98e9dad28..27b7480f4afe 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -308,7 +308,7 @@ EXPORT_SYMBOL(gpio_line_config);
308/************************************************************************* 308/*************************************************************************
309 * IRQ handling IXP2000 309 * IRQ handling IXP2000
310 *************************************************************************/ 310 *************************************************************************/
311static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc) 311static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
312{ 312{
313 int i; 313 int i;
314 unsigned long status = *IXP2000_GPIO_INST; 314 unsigned long status = *IXP2000_GPIO_INST;
@@ -373,7 +373,7 @@ static void ixp2000_GPIO_irq_unmask(unsigned int irq)
373 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 373 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
374} 374}
375 375
376static struct irqchip ixp2000_GPIO_irq_chip = { 376static struct irq_chip ixp2000_GPIO_irq_chip = {
377 .ack = ixp2000_GPIO_irq_mask_ack, 377 .ack = ixp2000_GPIO_irq_mask_ack,
378 .mask = ixp2000_GPIO_irq_mask, 378 .mask = ixp2000_GPIO_irq_mask,
379 .unmask = ixp2000_GPIO_irq_unmask, 379 .unmask = ixp2000_GPIO_irq_unmask,
@@ -401,7 +401,7 @@ static void ixp2000_pci_irq_unmask(unsigned int irq)
401/* 401/*
402 * Error interrupts. These are used extensively by the microengine drivers 402 * Error interrupts. These are used extensively by the microengine drivers
403 */ 403 */
404static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc) 404static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
405{ 405{
406 int i; 406 int i;
407 unsigned long status = *IXP2000_IRQ_ERR_STATUS; 407 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
@@ -426,13 +426,13 @@ static void ixp2000_err_irq_unmask(unsigned int irq)
426 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))); 426 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
427} 427}
428 428
429static struct irqchip ixp2000_err_irq_chip = { 429static struct irq_chip ixp2000_err_irq_chip = {
430 .ack = ixp2000_err_irq_mask, 430 .ack = ixp2000_err_irq_mask,
431 .mask = ixp2000_err_irq_mask, 431 .mask = ixp2000_err_irq_mask,
432 .unmask = ixp2000_err_irq_unmask 432 .unmask = ixp2000_err_irq_unmask
433}; 433};
434 434
435static struct irqchip ixp2000_pci_irq_chip = { 435static struct irq_chip ixp2000_pci_irq_chip = {
436 .ack = ixp2000_pci_irq_mask, 436 .ack = ixp2000_pci_irq_mask,
437 .mask = ixp2000_pci_irq_mask, 437 .mask = ixp2000_pci_irq_mask,
438 .unmask = ixp2000_pci_irq_unmask 438 .unmask = ixp2000_pci_irq_unmask
@@ -448,7 +448,7 @@ static void ixp2000_irq_unmask(unsigned int irq)
448 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq)); 448 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
449} 449}
450 450
451static struct irqchip ixp2000_irq_chip = { 451static struct irq_chip ixp2000_irq_chip = {
452 .ack = ixp2000_irq_mask, 452 .ack = ixp2000_irq_mask,
453 .mask = ixp2000_irq_mask, 453 .mask = ixp2000_irq_mask,
454 .unmask = ixp2000_irq_unmask 454 .unmask = ixp2000_irq_unmask
@@ -484,7 +484,7 @@ void __init ixp2000_init_irq(void)
484 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { 484 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
485 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { 485 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
486 set_irq_chip(irq, &ixp2000_irq_chip); 486 set_irq_chip(irq, &ixp2000_irq_chip);
487 set_irq_handler(irq, do_level_IRQ); 487 set_irq_handler(irq, handle_level_irq);
488 set_irq_flags(irq, IRQF_VALID); 488 set_irq_flags(irq, IRQF_VALID);
489 } else set_irq_flags(irq, 0); 489 } else set_irq_flags(irq, 0);
490 } 490 }
@@ -493,7 +493,7 @@ void __init ixp2000_init_irq(void)
493 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & 493 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
494 IXP2000_VALID_ERR_IRQ_MASK) { 494 IXP2000_VALID_ERR_IRQ_MASK) {
495 set_irq_chip(irq, &ixp2000_err_irq_chip); 495 set_irq_chip(irq, &ixp2000_err_irq_chip);
496 set_irq_handler(irq, do_level_IRQ); 496 set_irq_handler(irq, handle_level_irq);
497 set_irq_flags(irq, IRQF_VALID); 497 set_irq_flags(irq, IRQF_VALID);
498 } 498 }
499 else 499 else
@@ -503,7 +503,7 @@ void __init ixp2000_init_irq(void)
503 503
504 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { 504 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
505 set_irq_chip(irq, &ixp2000_GPIO_irq_chip); 505 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
506 set_irq_handler(irq, do_level_IRQ); 506 set_irq_handler(irq, handle_level_irq);
507 set_irq_flags(irq, IRQF_VALID); 507 set_irq_flags(irq, IRQF_VALID);
508 } 508 }
509 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); 509 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
@@ -516,7 +516,7 @@ void __init ixp2000_init_irq(void)
516 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); 516 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
517 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { 517 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
518 set_irq_chip(irq, &ixp2000_pci_irq_chip); 518 set_irq_chip(irq, &ixp2000_pci_irq_chip);
519 set_irq_handler(irq, do_level_IRQ); 519 set_irq_handler(irq, handle_level_irq);
520 set_irq_flags(irq, IRQF_VALID); 520 set_irq_flags(irq, IRQF_VALID);
521 } 521 }
522} 522}
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index aa2655092d2d..52b368b34346 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -106,7 +106,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
106 ixp2000_release_slowport(&old_cfg); 106 ixp2000_release_slowport(&old_cfg);
107} 107}
108 108
109static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc) 109static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
110{ 110{
111 volatile u32 ex_interrupt = 0; 111 volatile u32 ex_interrupt = 0;
112 static struct slowport_cfg old_cfg; 112 static struct slowport_cfg old_cfg;
@@ -129,7 +129,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
129 129
130 for(i = 0; i < board_irq_count; i++) { 130 for(i = 0; i < board_irq_count; i++) {
131 if(ex_interrupt & (1 << i)) { 131 if(ex_interrupt & (1 << i)) {
132 struct irqdesc *cpld_desc; 132 struct irq_desc *cpld_desc;
133 int cpld_irq = IXP2000_BOARD_IRQ(0) + i; 133 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
134 cpld_desc = irq_desc + cpld_irq; 134 cpld_desc = irq_desc + cpld_irq;
135 desc_handle_irq(cpld_irq, cpld_desc); 135 desc_handle_irq(cpld_irq, cpld_desc);
@@ -139,7 +139,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
139 desc->chip->unmask(irq); 139 desc->chip->unmask(irq);
140} 140}
141 141
142static struct irqchip ixdp2x00_cpld_irq_chip = { 142static struct irq_chip ixdp2x00_cpld_irq_chip = {
143 .ack = ixdp2x00_irq_mask, 143 .ack = ixdp2x00_irq_mask,
144 .mask = ixdp2x00_irq_mask, 144 .mask = ixdp2x00_irq_mask,
145 .unmask = ixdp2x00_irq_unmask 145 .unmask = ixdp2x00_irq_unmask
@@ -162,7 +162,7 @@ void ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long
162 162
163 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { 163 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
164 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); 164 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
165 set_irq_handler(irq, do_level_IRQ); 165 set_irq_handler(irq, handle_level_irq);
166 set_irq_flags(irq, IRQF_VALID); 166 set_irq_flags(irq, IRQF_VALID);
167 } 167 }
168 168
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 9ccae9e63f70..3084a5fa751c 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -63,7 +63,7 @@ static void ixdp2x01_irq_unmask(unsigned int irq)
63 63
64static u32 valid_irq_mask; 64static u32 valid_irq_mask;
65 65
66static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc) 66static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
67{ 67{
68 u32 ex_interrupt; 68 u32 ex_interrupt;
69 int i; 69 int i;
@@ -79,7 +79,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
79 79
80 for (i = 0; i < IXP2000_BOARD_IRQS; i++) { 80 for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
81 if (ex_interrupt & (1 << i)) { 81 if (ex_interrupt & (1 << i)) {
82 struct irqdesc *cpld_desc; 82 struct irq_desc *cpld_desc;
83 int cpld_irq = IXP2000_BOARD_IRQ(0) + i; 83 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
84 cpld_desc = irq_desc + cpld_irq; 84 cpld_desc = irq_desc + cpld_irq;
85 desc_handle_irq(cpld_irq, cpld_desc); 85 desc_handle_irq(cpld_irq, cpld_desc);
@@ -89,7 +89,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
89 desc->chip->unmask(irq); 89 desc->chip->unmask(irq);
90} 90}
91 91
92static struct irqchip ixdp2x01_irq_chip = { 92static struct irq_chip ixdp2x01_irq_chip = {
93 .mask = ixdp2x01_irq_mask, 93 .mask = ixdp2x01_irq_mask,
94 .ack = ixdp2x01_irq_mask, 94 .ack = ixdp2x01_irq_mask,
95 .unmask = ixdp2x01_irq_unmask 95 .unmask = ixdp2x01_irq_unmask
@@ -119,7 +119,7 @@ void __init ixdp2x01_init_irq(void)
119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { 119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
120 if (irq & valid_irq_mask) { 120 if (irq & valid_irq_mask) {
121 set_irq_chip(irq, &ixdp2x01_irq_chip); 121 set_irq_chip(irq, &ixdp2x01_irq_chip);
122 set_irq_handler(irq, do_level_IRQ); 122 set_irq_handler(irq, handle_level_irq);
123 set_irq_flags(irq, IRQF_VALID); 123 set_irq_flags(irq, IRQF_VALID);
124 } else { 124 } else {
125 set_irq_flags(irq, 0); 125 set_irq_flags(irq, 0);
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index d4bf1e1c0031..5a09a90c08fb 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -32,7 +32,7 @@
32 32
33#include <asm/mach/pci.h> 33#include <asm/mach/pci.h>
34 34
35static int pci_master_aborts = 0; 35static volatile int pci_master_aborts = 0;
36 36
37static int clear_master_aborts(void); 37static int clear_master_aborts(void);
38 38
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index a704a1820048..ce6ad635a00c 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -224,14 +224,14 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq)
224 *intr_reg |= (1 << (irq % 32)); 224 *intr_reg |= (1 << (irq % 32));
225} 225}
226 226
227static struct irqchip ixp23xx_irq_level_chip = { 227static struct irq_chip ixp23xx_irq_level_chip = {
228 .ack = ixp23xx_irq_mask, 228 .ack = ixp23xx_irq_mask,
229 .mask = ixp23xx_irq_mask, 229 .mask = ixp23xx_irq_mask,
230 .unmask = ixp23xx_irq_level_unmask, 230 .unmask = ixp23xx_irq_level_unmask,
231 .set_type = ixp23xx_irq_set_type 231 .set_type = ixp23xx_irq_set_type
232}; 232};
233 233
234static struct irqchip ixp23xx_irq_edge_chip = { 234static struct irq_chip ixp23xx_irq_edge_chip = {
235 .ack = ixp23xx_irq_ack, 235 .ack = ixp23xx_irq_ack,
236 .mask = ixp23xx_irq_mask, 236 .mask = ixp23xx_irq_mask,
237 .unmask = ixp23xx_irq_edge_unmask, 237 .unmask = ixp23xx_irq_edge_unmask,
@@ -251,11 +251,11 @@ static void ixp23xx_pci_irq_unmask(unsigned int irq)
251/* 251/*
252 * TODO: Should this just be done at ASM level? 252 * TODO: Should this just be done at ASM level?
253 */ 253 */
254static void pci_handler(unsigned int irq, struct irqdesc *desc) 254static void pci_handler(unsigned int irq, struct irq_desc *desc)
255{ 255{
256 u32 pci_interrupt; 256 u32 pci_interrupt;
257 unsigned int irqno; 257 unsigned int irqno;
258 struct irqdesc *int_desc; 258 struct irq_desc *int_desc;
259 259
260 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS; 260 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
261 261
@@ -276,7 +276,7 @@ static void pci_handler(unsigned int irq, struct irqdesc *desc)
276 desc->chip->unmask(irq); 276 desc->chip->unmask(irq);
277} 277}
278 278
279static struct irqchip ixp23xx_pci_irq_chip = { 279static struct irq_chip ixp23xx_pci_irq_chip = {
280 .ack = ixp23xx_pci_irq_mask, 280 .ack = ixp23xx_pci_irq_mask,
281 .mask = ixp23xx_pci_irq_mask, 281 .mask = ixp23xx_pci_irq_mask,
282 .unmask = ixp23xx_pci_irq_unmask 282 .unmask = ixp23xx_pci_irq_unmask
@@ -287,11 +287,11 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
287 switch (type) { 287 switch (type) {
288 case IXP23XX_IRQ_LEVEL: 288 case IXP23XX_IRQ_LEVEL:
289 set_irq_chip(irq, &ixp23xx_irq_level_chip); 289 set_irq_chip(irq, &ixp23xx_irq_level_chip);
290 set_irq_handler(irq, do_level_IRQ); 290 set_irq_handler(irq, handle_level_irq);
291 break; 291 break;
292 case IXP23XX_IRQ_EDGE: 292 case IXP23XX_IRQ_EDGE:
293 set_irq_chip(irq, &ixp23xx_irq_edge_chip); 293 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
294 set_irq_handler(irq, do_edge_IRQ); 294 set_irq_handler(irq, handle_edge_irq);
295 break; 295 break;
296 } 296 }
297 set_irq_flags(irq, IRQF_VALID); 297 set_irq_flags(irq, IRQF_VALID);
@@ -322,7 +322,7 @@ void __init ixp23xx_init_irq(void)
322 322
323 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { 323 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
324 set_irq_chip(irq, &ixp23xx_pci_irq_chip); 324 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
325 set_irq_handler(irq, do_level_IRQ); 325 set_irq_handler(irq, handle_level_irq);
326 set_irq_flags(irq, IRQF_VALID); 326 set_irq_flags(irq, IRQF_VALID);
327 } 327 }
328 328
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index b6ab0e8bb5e8..7a86a2516eaa 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -60,7 +60,7 @@ static void ixdp2351_inta_unmask(unsigned int irq)
60 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq); 60 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
61} 61}
62 62
63static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc) 63static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
64{ 64{
65 u16 ex_interrupt = 65 u16 ex_interrupt =
66 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID; 66 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
@@ -70,7 +70,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
70 70
71 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) { 71 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
72 if (ex_interrupt & (1 << i)) { 72 if (ex_interrupt & (1 << i)) {
73 struct irqdesc *cpld_desc; 73 struct irq_desc *cpld_desc;
74 int cpld_irq = 74 int cpld_irq =
75 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i); 75 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
76 cpld_desc = irq_desc + cpld_irq; 76 cpld_desc = irq_desc + cpld_irq;
@@ -81,7 +81,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
81 desc->chip->unmask(irq); 81 desc->chip->unmask(irq);
82} 82}
83 83
84static struct irqchip ixdp2351_inta_chip = { 84static struct irq_chip ixdp2351_inta_chip = {
85 .ack = ixdp2351_inta_mask, 85 .ack = ixdp2351_inta_mask,
86 .mask = ixdp2351_inta_mask, 86 .mask = ixdp2351_inta_mask,
87 .unmask = ixdp2351_inta_unmask 87 .unmask = ixdp2351_inta_unmask
@@ -97,7 +97,7 @@ static void ixdp2351_intb_unmask(unsigned int irq)
97 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq); 97 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
98} 98}
99 99
100static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc) 100static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
101{ 101{
102 u16 ex_interrupt = 102 u16 ex_interrupt =
103 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID; 103 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
@@ -107,7 +107,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
107 107
108 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) { 108 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
109 if (ex_interrupt & (1 << i)) { 109 if (ex_interrupt & (1 << i)) {
110 struct irqdesc *cpld_desc; 110 struct irq_desc *cpld_desc;
111 int cpld_irq = 111 int cpld_irq =
112 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i); 112 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
113 cpld_desc = irq_desc + cpld_irq; 113 cpld_desc = irq_desc + cpld_irq;
@@ -118,7 +118,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
118 desc->chip->unmask(irq); 118 desc->chip->unmask(irq);
119} 119}
120 120
121static struct irqchip ixdp2351_intb_chip = { 121static struct irq_chip ixdp2351_intb_chip = {
122 .ack = ixdp2351_intb_mask, 122 .ack = ixdp2351_intb_mask,
123 .mask = ixdp2351_intb_mask, 123 .mask = ixdp2351_intb_mask,
124 .unmask = ixdp2351_intb_unmask 124 .unmask = ixdp2351_intb_unmask
@@ -142,7 +142,7 @@ void ixdp2351_init_irq(void)
142 irq++) { 142 irq++) {
143 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { 143 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
144 set_irq_flags(irq, IRQF_VALID); 144 set_irq_flags(irq, IRQF_VALID);
145 set_irq_handler(irq, do_level_IRQ); 145 set_irq_handler(irq, handle_level_irq);
146 set_irq_chip(irq, &ixdp2351_inta_chip); 146 set_irq_chip(irq, &ixdp2351_inta_chip);
147 } 147 }
148 } 148 }
@@ -153,7 +153,7 @@ void ixdp2351_init_irq(void)
153 irq++) { 153 irq++) {
154 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { 154 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
155 set_irq_flags(irq, IRQF_VALID); 155 set_irq_flags(irq, IRQF_VALID);
156 set_irq_handler(irq, do_level_IRQ); 156 set_irq_handler(irq, handle_level_irq);
157 set_irq_chip(irq, &ixdp2351_intb_chip); 157 set_irq_chip(irq, &ixdp2351_intb_chip);
158 } 158 }
159 } 159 }
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 3b34fa35e36b..ac7d43d23c28 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -36,7 +36,7 @@
36 36
37extern int (*external_fault) (unsigned long, struct pt_regs *); 37extern int (*external_fault) (unsigned long, struct pt_regs *);
38 38
39static int pci_master_aborts = 0; 39static volatile int pci_master_aborts = 0;
40 40
41#ifdef DEBUG 41#ifdef DEBUG
42#define DBG(x...) printk(x) 42#define DBG(x...) printk(x)
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 57f23b465392..e316bd93313f 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -133,7 +133,7 @@ config IXP4XX_INDIRECT_PCI
133 into the kernel and we can use the standard read[bwl]/write[bwl] 133 into the kernel and we can use the standard read[bwl]/write[bwl]
134 macros. This is the preferred method due to speed but it 134 macros. This is the preferred method due to speed but it
135 limits the system to just 64MB of PCI memory. This can be 135 limits the system to just 64MB of PCI memory. This can be
136 problamatic if using video cards and other memory-heavy devices. 136 problematic if using video cards and other memory-heavy devices.
137 137
138 2) If > 64MB of memory space is required, the IXP4xx can be 138 2) If > 64MB of memory space is required, the IXP4xx can be
139 configured to use indirect registers to access PCI This allows 139 configured to use indirect registers to access PCI This allows
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fbe288a8da65..2ec9a9e9a04d 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -28,6 +28,7 @@
28#include <linux/timex.h> 28#include <linux/timex.h>
29#include <linux/clocksource.h> 29#include <linux/clocksource.h>
30 30
31#include <asm/arch/udc.h>
31#include <asm/hardware.h> 32#include <asm/hardware.h>
32#include <asm/uaccess.h> 33#include <asm/uaccess.h>
33#include <asm/io.h> 34#include <asm/io.h>
@@ -39,6 +40,8 @@
39#include <asm/mach/irq.h> 40#include <asm/mach/irq.h>
40#include <asm/mach/time.h> 41#include <asm/mach/time.h>
41 42
43static int __init ixp4xx_clocksource_init(void);
44
42/************************************************************************* 45/*************************************************************************
43 * IXP4xx chipset I/O mapping 46 * IXP4xx chipset I/O mapping
44 *************************************************************************/ 47 *************************************************************************/
@@ -195,7 +198,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
195 *IXP4XX_ICMR |= (1 << irq); 198 *IXP4XX_ICMR |= (1 << irq);
196} 199}
197 200
198static struct irqchip ixp4xx_irq_chip = { 201static struct irq_chip ixp4xx_irq_chip = {
199 .name = "IXP4xx", 202 .name = "IXP4xx",
200 .ack = ixp4xx_irq_ack, 203 .ack = ixp4xx_irq_ack,
201 .mask = ixp4xx_irq_mask, 204 .mask = ixp4xx_irq_mask,
@@ -224,7 +227,7 @@ void __init ixp4xx_init_irq(void)
224 /* Default to all level triggered */ 227 /* Default to all level triggered */
225 for(i = 0; i < NR_IRQS; i++) { 228 for(i = 0; i < NR_IRQS; i++) {
226 set_irq_chip(i, &ixp4xx_irq_chip); 229 set_irq_chip(i, &ixp4xx_irq_chip);
227 set_irq_handler(i, do_level_IRQ); 230 set_irq_handler(i, handle_level_irq);
228 set_irq_flags(i, IRQF_VALID); 231 set_irq_flags(i, IRQF_VALID);
229 } 232 }
230} 233}
@@ -280,12 +283,52 @@ static void __init ixp4xx_timer_init(void)
280 283
281 /* Connect the interrupt handler and enable the interrupt */ 284 /* Connect the interrupt handler and enable the interrupt */
282 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq); 285 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
286
287 ixp4xx_clocksource_init();
283} 288}
284 289
285struct sys_timer ixp4xx_timer = { 290struct sys_timer ixp4xx_timer = {
286 .init = ixp4xx_timer_init, 291 .init = ixp4xx_timer_init,
287}; 292};
288 293
294static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
295
296void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
297{
298 memcpy(&ixp4xx_udc_info, info, sizeof *info);
299}
300
301static struct resource ixp4xx_udc_resources[] = {
302 [0] = {
303 .start = 0xc800b000,
304 .end = 0xc800bfff,
305 .flags = IORESOURCE_MEM,
306 },
307 [1] = {
308 .start = IRQ_IXP4XX_USB,
309 .end = IRQ_IXP4XX_USB,
310 .flags = IORESOURCE_IRQ,
311 },
312};
313
314/*
315 * USB device controller. The IXP4xx uses the same controller as PXA2XX,
316 * so we just use the same device.
317 */
318static struct platform_device ixp4xx_udc_device = {
319 .name = "pxa2xx-udc",
320 .id = -1,
321 .num_resources = 2,
322 .resource = ixp4xx_udc_resources,
323 .dev = {
324 .platform_data = &ixp4xx_udc_info,
325 },
326};
327
328static struct platform_device *ixp4xx_devices[] __initdata = {
329 &ixp4xx_udc_device,
330};
331
289static struct resource ixp46x_i2c_resources[] = { 332static struct resource ixp46x_i2c_resources[] = {
290 [0] = { 333 [0] = {
291 .start = 0xc8011000, 334 .start = 0xc8011000,
@@ -321,6 +364,8 @@ void __init ixp4xx_sys_init(void)
321{ 364{
322 ixp4xx_exp_bus_size = SZ_16M; 365 ixp4xx_exp_bus_size = SZ_16M;
323 366
367 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
368
324 if (cpu_is_ixp46x()) { 369 if (cpu_is_ixp46x()) {
325 int region; 370 int region;
326 371
@@ -363,5 +408,3 @@ static int __init ixp4xx_clocksource_init(void)
363 408
364 return 0; 409 return 0;
365} 410}
366
367device_initcall(ixp4xx_clocksource_init);
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
index b7af5640ea7b..561a0fe7095d 100644
--- a/arch/arm/mach-l7200/core.c
+++ b/arch/arm/mach-l7200/core.c
@@ -55,7 +55,7 @@ static void l7200_unmask_irq(unsigned int irq)
55 IRQ_ENABLE = 1 << irq; 55 IRQ_ENABLE = 1 << irq;
56} 56}
57 57
58static struct irqchip l7200_irq_chip = { 58static struct irq_chip l7200_irq_chip = {
59 .ack = l7200_mask_irq, 59 .ack = l7200_mask_irq,
60 .mask = l7200_mask_irq, 60 .mask = l7200_mask_irq,
61 .unmask = l7200_unmask_irq 61 .unmask = l7200_unmask_irq
@@ -71,7 +71,7 @@ static void __init l7200_init_irq(void)
71 for (irq = 0; irq < NR_IRQS; irq++) { 71 for (irq = 0; irq < NR_IRQS; irq++) {
72 set_irq_chip(irq, &l7200_irq_chip); 72 set_irq_chip(irq, &l7200_irq_chip);
73 set_irq_flags(irq, IRQF_VALID); 73 set_irq_flags(irq, IRQF_VALID);
74 set_irq_handler(irq, do_level_IRQ); 74 set_irq_handler(irq, handle_level_irq);
75 } 75 }
76 76
77 init_FIQ(); 77 init_FIQ();
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig
index 147b01928a9b..6f4c6a1798c1 100644
--- a/arch/arm/mach-lh7a40x/Kconfig
+++ b/arch/arm/mach-lh7a40x/Kconfig
@@ -8,7 +8,7 @@ config MACH_KEV7A400
8 help 8 help
9 Say Y here if you are using the Sharp KEV7A400 development 9 Say Y here if you are using the Sharp KEV7A400 development
10 board. This hardware is discontinued, so I'd be very 10 board. This hardware is discontinued, so I'd be very
11 suprised if you wanted this option. 11 surprised if you wanted this option.
12 12
13config MACH_LPD7A400 13config MACH_LPD7A400
14 bool "LPD7A400 Card Engine" 14 bool "LPD7A400 Card Engine"
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 15fbcc911fe7..6d26661d99f6 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -71,7 +71,7 @@ static struct irq_chip kev7a400_cpld_chip = {
71}; 71};
72 72
73 73
74static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc) 74static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
75{ 75{
76 u32 mask = CPLD_LATCHED_INTS; 76 u32 mask = CPLD_LATCHED_INTS;
77 irq = IRQ_KEV7A400_CPLD; 77 irq = IRQ_KEV7A400_CPLD;
@@ -88,7 +88,7 @@ void __init lh7a40x_init_board_irq (void)
88 for (irq = IRQ_KEV7A400_CPLD; 88 for (irq = IRQ_KEV7A400_CPLD;
89 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) { 89 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
90 set_irq_chip (irq, &kev7a400_cpld_chip); 90 set_irq_chip (irq, &kev7a400_cpld_chip);
91 set_irq_handler (irq, do_edge_IRQ); 91 set_irq_handler (irq, handle_edge_irq);
92 set_irq_flags (irq, IRQF_VALID); 92 set_irq_flags (irq, IRQF_VALID);
93 } 93 }
94 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); 94 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index 8441e0a156cb..fe64946f9e18 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -207,7 +207,7 @@ static struct irq_chip lpd7a40x_cpld_chip = {
207 .unmask = lh7a40x_unmask_cpld_irq, 207 .unmask = lh7a40x_unmask_cpld_irq,
208}; 208};
209 209
210static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc) 210static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
211{ 211{
212 unsigned int mask = CPLD_INTERRUPTS; 212 unsigned int mask = CPLD_INTERRUPTS;
213 213
@@ -279,7 +279,7 @@ void __init lh7a40x_init_board_irq (void)
279 for (irq = IRQ_BOARD_START; 279 for (irq = IRQ_BOARD_START;
280 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { 280 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
281 set_irq_chip (irq, &lpd7a40x_cpld_chip); 281 set_irq_chip (irq, &lpd7a40x_cpld_chip);
282 set_irq_handler (irq, do_level_IRQ); 282 set_irq_handler (irq, handle_level_irq);
283 set_irq_flags (irq, IRQF_VALID); 283 set_irq_flags (irq, IRQF_VALID);
284 } 284 }
285 285
diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c
index 646071334b8f..c7433b3c5812 100644
--- a/arch/arm/mach-lh7a40x/irq-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-kev7a400.c
@@ -51,7 +51,7 @@ irq_chip lh7a400_cpld_chip = {
51}; 51};
52 52
53static void 53static void
54lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc) 54lh7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
55{ 55{
56 u32 mask = CPLD_LATCHED_INTS; 56 u32 mask = CPLD_LATCHED_INTS;
57 irq = IRQ_KEV_7A400_CPLD; 57 irq = IRQ_KEV_7A400_CPLD;
@@ -71,7 +71,7 @@ lh7a400_init_board_irq (void)
71 for (irq = IRQ_KEV7A400_CPLD; 71 for (irq = IRQ_KEV7A400_CPLD;
72 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) { 72 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
73 set_irq_chip (irq, &lh7a400_cpld_chip); 73 set_irq_chip (irq, &lh7a400_cpld_chip);
74 set_irq_handler (irq, do_edge_IRQ); 74 set_irq_handler (irq, handle_edge_irq);
75 set_irq_flags (irq, IRQF_VALID); 75 set_irq_flags (irq, IRQF_VALID);
76 } 76 }
77 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); 77 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
index 091b2dc58d25..0b938e8b4d98 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c
@@ -74,11 +74,11 @@ void __init lh7a400_init_irq (void)
74 case IRQ_GPIO6INTR: 74 case IRQ_GPIO6INTR:
75 case IRQ_GPIO7INTR: 75 case IRQ_GPIO7INTR:
76 set_irq_chip (irq, &lh7a400_gpio_chip); 76 set_irq_chip (irq, &lh7a400_gpio_chip);
77 set_irq_handler (irq, do_level_IRQ); /* OK default */ 77 set_irq_handler (irq, handle_level_irq); /* OK default */
78 break; 78 break;
79 default: 79 default:
80 set_irq_chip (irq, &lh7a400_internal_chip); 80 set_irq_chip (irq, &lh7a400_internal_chip);
81 set_irq_handler (irq, do_level_IRQ); 81 set_irq_handler (irq, handle_level_irq);
82 } 82 }
83 set_irq_flags (irq, IRQF_VALID); 83 set_irq_flags (irq, IRQF_VALID);
84 } 84 }
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index 7059b983724f..5760f8c53e89 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -161,13 +161,13 @@ void __init lh7a404_init_irq (void)
161 set_irq_chip (irq, irq < 32 161 set_irq_chip (irq, irq < 32
162 ? &lh7a404_gpio_vic1_chip 162 ? &lh7a404_gpio_vic1_chip
163 : &lh7a404_gpio_vic2_chip); 163 : &lh7a404_gpio_vic2_chip);
164 set_irq_handler (irq, do_level_IRQ); /* OK default */ 164 set_irq_handler (irq, handle_level_irq); /* OK default */
165 break; 165 break;
166 default: 166 default:
167 set_irq_chip (irq, irq < 32 167 set_irq_chip (irq, irq < 32
168 ? &lh7a404_vic1_chip 168 ? &lh7a404_vic1_chip
169 : &lh7a404_vic2_chip); 169 : &lh7a404_vic2_chip);
170 set_irq_handler (irq, do_level_IRQ); 170 set_irq_handler (irq, handle_level_irq);
171 } 171 }
172 set_irq_flags (irq, IRQF_VALID); 172 set_irq_flags (irq, IRQF_VALID);
173 } 173 }
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index b20376804bbb..15b9577023c9 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -57,7 +57,7 @@ static struct irq_chip lh7a40x_cpld_chip = {
57 .unmask = lh7a40x_unmask_cpld_irq, 57 .unmask = lh7a40x_unmask_cpld_irq,
58}; 58};
59 59
60static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc) 60static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
61{ 61{
62 unsigned int mask = CPLD_INTERRUPTS; 62 unsigned int mask = CPLD_INTERRUPTS;
63 63
@@ -118,7 +118,7 @@ void __init lh7a40x_init_board_irq (void)
118 for (irq = IRQ_BOARD_START; 118 for (irq = IRQ_BOARD_START;
119 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { 119 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
120 set_irq_chip (irq, &lh7a40x_cpld_chip); 120 set_irq_chip (irq, &lh7a40x_cpld_chip);
121 set_irq_handler (irq, do_edge_IRQ); 121 set_irq_handler (irq, handle_edge_irq);
122 set_irq_flags (irq, IRQF_VALID); 122 set_irq_flags (irq, IRQF_VALID);
123 } 123 }
124 124
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index edbbbdc3b06b..b9ca8f98265d 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -69,7 +69,7 @@ static struct platform_device *devices[] __initdata = {
69#endif 69#endif
70 70
71static void 71static void
72netx_hif_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 72netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
73{ 73{
74 unsigned int irq = NETX_IRQ_HIF_CHAINED(0); 74 unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
75 unsigned int stat; 75 unsigned int stat;
@@ -160,7 +160,7 @@ netx_hif_unmask_irq(unsigned int _irq)
160 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq); 160 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
161} 161}
162 162
163static struct irqchip netx_hif_chip = { 163static struct irq_chip netx_hif_chip = {
164 .ack = netx_hif_ack_irq, 164 .ack = netx_hif_ack_irq,
165 .mask = netx_hif_mask_irq, 165 .mask = netx_hif_mask_irq,
166 .unmask = netx_hif_unmask_irq, 166 .unmask = netx_hif_unmask_irq,
@@ -175,7 +175,7 @@ void __init netx_init_irq(void)
175 175
176 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { 176 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
177 set_irq_chip(irq, &netx_hif_chip); 177 set_irq_chip(irq, &netx_hif_chip);
178 set_irq_handler(irq, do_level_IRQ); 178 set_irq_handler(irq, handle_level_irq);
179 set_irq_flags(irq, IRQF_VALID); 179 set_irq_flags(irq, IRQF_VALID);
180 } 180 }
181 181
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index 0993336c0b55..5773b55ef4a6 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -19,6 +19,8 @@
19 19
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/clocksource.h>
22 24
23#include <asm/hardware.h> 25#include <asm/hardware.h>
24#include <asm/io.h> 26#include <asm/io.h>
@@ -26,15 +28,6 @@
26#include <asm/arch/netx-regs.h> 28#include <asm/arch/netx-regs.h>
27 29
28/* 30/*
29 * Returns number of us since last clock interrupt. Note that interrupts
30 * will have been disabled by do_gettimeoffset()
31 */
32static unsigned long netx_gettimeoffset(void)
33{
34 return readl(NETX_GPIO_COUNTER_CURRENT(0)) / 100;
35}
36
37/*
38 * IRQ handler for the timer 31 * IRQ handler for the timer
39 */ 32 */
40static irqreturn_t 33static irqreturn_t
@@ -43,6 +36,7 @@ netx_timer_interrupt(int irq, void *dev_id)
43 write_seqlock(&xtime_lock); 36 write_seqlock(&xtime_lock);
44 37
45 timer_tick(); 38 timer_tick();
39
46 write_sequnlock(&xtime_lock); 40 write_sequnlock(&xtime_lock);
47 41
48 /* acknowledge interrupt */ 42 /* acknowledge interrupt */
@@ -51,13 +45,26 @@ netx_timer_interrupt(int irq, void *dev_id)
51 return IRQ_HANDLED; 45 return IRQ_HANDLED;
52} 46}
53 47
54
55static struct irqaction netx_timer_irq = { 48static struct irqaction netx_timer_irq = {
56 .name = "NetX Timer Tick", 49 .name = "NetX Timer Tick",
57 .flags = IRQF_DISABLED | IRQF_TIMER, 50 .flags = IRQF_DISABLED | IRQF_TIMER,
58 .handler = netx_timer_interrupt, 51 .handler = netx_timer_interrupt,
59}; 52};
60 53
54cycle_t netx_get_cycles(void)
55{
56 return readl(NETX_GPIO_COUNTER_CURRENT(1));
57}
58
59static struct clocksource clocksource_netx = {
60 .name = "netx_timer",
61 .rating = 200,
62 .read = netx_get_cycles,
63 .mask = CLOCKSOURCE_MASK(32),
64 .shift = 20,
65 .is_continuous = 1,
66};
67
61/* 68/*
62 * Set up timer interrupt 69 * Set up timer interrupt
63 */ 70 */
@@ -80,9 +87,20 @@ static void __init netx_timer_init(void)
80 NETX_GPIO_COUNTER_CTRL(0)); 87 NETX_GPIO_COUNTER_CTRL(0));
81 88
82 setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq); 89 setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
90
91 /* Setup timer one for clocksource */
92 writel(0, NETX_GPIO_COUNTER_CTRL(1));
93 writel(0, NETX_GPIO_COUNTER_CURRENT(1));
94 writel(0xFFFFFFFF, NETX_GPIO_COUNTER_MAX(1));
95
96 writel(NETX_GPIO_COUNTER_CTRL_RUN,
97 NETX_GPIO_COUNTER_CTRL(1));
98
99 clocksource_netx.mult =
100 clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_netx.shift);
101 clocksource_register(&clocksource_netx);
83} 102}
84 103
85struct sys_timer netx_timer = { 104struct sys_timer netx_timer = {
86 .init = netx_timer_init, 105 .init = netx_timer_init,
87 .offset = netx_gettimeoffset,
88}; 106};
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index f225a083dee1..9d2346fb68f4 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -323,7 +323,8 @@ static int h3_transceiver_mode(struct device *dev, int mode)
323 323
324 cancel_delayed_work(&irda_config->gpio_expa); 324 cancel_delayed_work(&irda_config->gpio_expa);
325 PREPARE_WORK(&irda_config->gpio_expa, set_trans_mode, &mode); 325 PREPARE_WORK(&irda_config->gpio_expa, set_trans_mode, &mode);
326 schedule_work(&irda_config->gpio_expa); 326#error this is not permitted - mode is an argument variable
327 schedule_delayed_work(&irda_config->gpio_expa, 0);
327 328
328 return 0; 329 return 0;
329} 330}
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index dbc555d209ff..cbe909bad79b 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -74,7 +74,7 @@ static struct omap_kp_platform_data nokia770_kp_data = {
74 .rows = 8, 74 .rows = 8,
75 .cols = 8, 75 .cols = 8,
76 .keymap = nokia770_keymap, 76 .keymap = nokia770_keymap,
77 .keymapsize = ARRAY_SIZE(nokia770_keymap) 77 .keymapsize = ARRAY_SIZE(nokia770_keymap),
78 .delay = 4, 78 .delay = 4,
79}; 79};
80 80
@@ -191,7 +191,7 @@ static void nokia770_audio_pwr_up(void)
191 printk("HP connected\n"); 191 printk("HP connected\n");
192} 192}
193 193
194static void codec_delayed_power_down(void *arg) 194static void codec_delayed_power_down(struct work_struct *work)
195{ 195{
196 down(&audio_pwr_sem); 196 down(&audio_pwr_sem);
197 if (audio_pwr_state == -1) 197 if (audio_pwr_state == -1)
@@ -200,7 +200,7 @@ static void codec_delayed_power_down(void *arg)
200 up(&audio_pwr_sem); 200 up(&audio_pwr_sem);
201} 201}
202 202
203static DECLARE_WORK(codec_power_down_work, codec_delayed_power_down, NULL); 203static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
204 204
205static void nokia770_audio_pwr_down(void) 205static void nokia770_audio_pwr_down(void)
206{ 206{
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index a611c3b63954..6dcd10ab4496 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -55,7 +55,7 @@ static inline void omap_init_irda(void) {}
55 55
56/*-------------------------------------------------------------------------*/ 56/*-------------------------------------------------------------------------*/
57 57
58#if defined(CONFIG_OMAP_RTC) || defined(CONFIG_OMAP_RTC) 58#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)
59 59
60#define OMAP_RTC_BASE 0xfffb4800 60#define OMAP_RTC_BASE 0xfffb4800
61 61
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 8e40208b10bb..30e188109046 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -84,9 +84,9 @@ static void fpga_mask_ack_irq(unsigned int irq)
84 fpga_ack_irq(irq); 84 fpga_ack_irq(irq);
85} 85}
86 86
87void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc) 87void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
88{ 88{
89 struct irqdesc *d; 89 struct irq_desc *d;
90 u32 stat; 90 u32 stat;
91 int fpga_irq; 91 int fpga_irq;
92 92
@@ -168,7 +168,7 @@ void omap1510_fpga_init_irq(void)
168 set_irq_chip(i, &omap_fpga_irq); 168 set_irq_chip(i, &omap_fpga_irq);
169 } 169 }
170 170
171 set_irq_handler(i, do_edge_IRQ); 171 set_irq_handler(i, handle_edge_irq);
172 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
173 } 173 }
174 174
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 3ea140bb9eba..6383a12ad970 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -229,7 +229,7 @@ void __init omap_init_irq(void)
229 omap_irq_set_cfg(j, 0, 0, irq_trigger); 229 omap_irq_set_cfg(j, 0, 0, irq_trigger);
230 230
231 set_irq_chip(j, &omap_irq_chip); 231 set_irq_chip(j, &omap_irq_chip);
232 set_irq_handler(j, do_level_IRQ); 232 set_irq_handler(j, handle_level_irq);
233 set_irq_flags(j, IRQF_VALID); 233 set_irq_flags(j, IRQF_VALID);
234 } 234 }
235 } 235 }
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index 3b29e59b0e6f..0cbf1b0071f8 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -35,7 +35,7 @@ static u8 hw_led_state;
35 35
36static u8 tps_leds_change; 36static u8 tps_leds_change;
37 37
38static void tps_work(void *unused) 38static void tps_work(struct work_struct *unused)
39{ 39{
40 for (;;) { 40 for (;;) {
41 u8 leds; 41 u8 leds;
@@ -61,7 +61,7 @@ static void tps_work(void *unused)
61 } 61 }
62} 62}
63 63
64static DECLARE_WORK(work, tps_work, NULL); 64static DECLARE_WORK(work, tps_work);
65 65
66#ifdef CONFIG_OMAP_OSK_MISTRAL 66#ifdef CONFIG_OMAP_OSK_MISTRAL
67 67
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 26a95a642ad7..3b1ad1d981a3 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -206,7 +206,8 @@ static int h4_transceiver_mode(struct device *dev, int mode)
206 206
207 cancel_delayed_work(&irda_config->gpio_expa); 207 cancel_delayed_work(&irda_config->gpio_expa);
208 PREPARE_WORK(&irda_config->gpio_expa, set_trans_mode, &mode); 208 PREPARE_WORK(&irda_config->gpio_expa, set_trans_mode, &mode);
209 schedule_work(&irda_config->gpio_expa); 209#error this is not permitted - mode is an argument variable
210 schedule_delayed_work(&irda_config->gpio_expa, 0);
210 211
211 return 0; 212 return 0;
212} 213}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 11870093d7a1..a39d30680300 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -130,7 +130,7 @@ void __init omap_init_irq(void)
130 130
131 for (i = 0; i < nr_irqs; i++) { 131 for (i = 0; i < nr_irqs; i++) {
132 set_irq_chip(i, &omap_irq_chip); 132 set_irq_chip(i, &omap_irq_chip);
133 set_irq_handler(i, do_level_IRQ); 133 set_irq_handler(i, handle_level_irq);
134 set_irq_flags(i, IRQF_VALID); 134 set_irq_flags(i, IRQF_VALID);
135 } 135 }
136} 136}
diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile
index b457ca0a431a..777564c90a12 100644
--- a/arch/arm/mach-pnx4008/Makefile
+++ b/arch/arm/mach-pnx4008/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := core.o irq.o time.o clock.o gpio.o serial.o dma.o 5obj-y := core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
new file mode 100644
index 000000000000..6f308827c4fe
--- /dev/null
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -0,0 +1,167 @@
1/*
2 * I2C initialization for PNX4008.
3 *
4 * Author: Vitaly Wool <vitalywool@gmail.com>
5 *
6 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/i2c.h>
14#include <linux/i2c-pnx.h>
15#include <linux/platform_device.h>
16#include <linux/err.h>
17#include <asm/arch/platform.h>
18#include <asm/arch/i2c.h>
19
20static int set_clock_run(struct platform_device *pdev)
21{
22 struct clk *clk;
23 char name[10];
24 int retval = 0;
25
26 snprintf(name, 10, "i2c%d_ck", pdev->id);
27 clk = clk_get(&pdev->dev, name);
28 if (!IS_ERR(clk)) {
29 clk_set_rate(clk, 1);
30 clk_put(clk);
31 } else
32 retval = -ENOENT;
33
34 return retval;
35}
36
37static int set_clock_stop(struct platform_device *pdev)
38{
39 struct clk *clk;
40 char name[10];
41 int retval = 0;
42
43 snprintf(name, 10, "i2c%d_ck", pdev->id);
44 clk = clk_get(&pdev->dev, name);
45 if (!IS_ERR(clk)) {
46 clk_set_rate(clk, 0);
47 clk_put(clk);
48 } else
49 retval = -ENOENT;
50
51 return retval;
52}
53
54static int i2c_pnx_suspend(struct platform_device *pdev, pm_message_t state)
55{
56 int retval = 0;
57#ifdef CONFIG_PM
58 retval = set_clock_run(pdev);
59#endif
60 return retval;
61}
62
63static int i2c_pnx_resume(struct platform_device *pdev)
64{
65 int retval = 0;
66#ifdef CONFIG_PM
67 retval = set_clock_run(pdev);
68#endif
69 return retval;
70}
71
72static u32 calculate_input_freq(struct platform_device *pdev)
73{
74 return HCLK_MHZ;
75}
76
77
78static struct i2c_pnx_algo_data pnx_algo_data0 = {
79 .base = PNX4008_I2C1_BASE,
80 .irq = I2C_1_INT,
81};
82
83static struct i2c_pnx_algo_data pnx_algo_data1 = {
84 .base = PNX4008_I2C2_BASE,
85 .irq = I2C_2_INT,
86};
87
88static struct i2c_pnx_algo_data pnx_algo_data2 = {
89 .base = (PNX4008_USB_CONFIG_BASE + 0x300),
90 .irq = USB_I2C_INT,
91};
92
93static struct i2c_adapter pnx_adapter0 = {
94 .name = I2C_CHIP_NAME "0",
95 .algo_data = &pnx_algo_data0,
96};
97static struct i2c_adapter pnx_adapter1 = {
98 .name = I2C_CHIP_NAME "1",
99 .algo_data = &pnx_algo_data1,
100};
101
102static struct i2c_adapter pnx_adapter2 = {
103 .name = "USB-I2C",
104 .algo_data = &pnx_algo_data2,
105};
106
107static struct i2c_pnx_data i2c0_data = {
108 .suspend = i2c_pnx_suspend,
109 .resume = i2c_pnx_resume,
110 .calculate_input_freq = calculate_input_freq,
111 .set_clock_run = set_clock_run,
112 .set_clock_stop = set_clock_stop,
113 .adapter = &pnx_adapter0,
114};
115
116static struct i2c_pnx_data i2c1_data = {
117 .suspend = i2c_pnx_suspend,
118 .resume = i2c_pnx_resume,
119 .calculate_input_freq = calculate_input_freq,
120 .set_clock_run = set_clock_run,
121 .set_clock_stop = set_clock_stop,
122 .adapter = &pnx_adapter1,
123};
124
125static struct i2c_pnx_data i2c2_data = {
126 .suspend = i2c_pnx_suspend,
127 .resume = i2c_pnx_resume,
128 .calculate_input_freq = calculate_input_freq,
129 .set_clock_run = set_clock_run,
130 .set_clock_stop = set_clock_stop,
131 .adapter = &pnx_adapter2,
132};
133
134static struct platform_device i2c0_device = {
135 .name = "pnx-i2c",
136 .id = 0,
137 .dev = {
138 .platform_data = &i2c0_data,
139 },
140};
141
142static struct platform_device i2c1_device = {
143 .name = "pnx-i2c",
144 .id = 1,
145 .dev = {
146 .platform_data = &i2c1_data,
147 },
148};
149
150static struct platform_device i2c2_device = {
151 .name = "pnx-i2c",
152 .id = 2,
153 .dev = {
154 .platform_data = &i2c2_data,
155 },
156};
157
158static struct platform_device *devices[] __initdata = {
159 &i2c0_device,
160 &i2c1_device,
161 &i2c2_device,
162};
163
164void __init pnx4008_register_i2c_devices(void)
165{
166 platform_add_devices(devices, ARRAY_SIZE(devices));
167}
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 3a4bcf3d91fa..968d0b027597 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -59,22 +59,22 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
59 case IRQT_RISING: 59 case IRQT_RISING:
60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ 61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
62 set_irq_handler(irq, do_edge_IRQ); 62 set_irq_handler(irq, handle_edge_irq);
63 break; 63 break;
64 case IRQT_FALLING: 64 case IRQT_FALLING:
65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ 66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
67 set_irq_handler(irq, do_edge_IRQ); 67 set_irq_handler(irq, handle_edge_irq);
68 break; 68 break;
69 case IRQT_LOW: 69 case IRQT_LOW:
70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ 71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
72 set_irq_handler(irq, do_level_IRQ); 72 set_irq_handler(irq, handle_level_irq);
73 break; 73 break;
74 case IRQT_HIGH: 74 case IRQT_HIGH:
75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ 76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
77 set_irq_handler(irq, do_level_IRQ); 77 set_irq_handler(irq, handle_level_irq);
78 break; 78 break;
79 79
80 /* IRQT_BOTHEDGE is not supported */ 80 /* IRQT_BOTHEDGE is not supported */
@@ -85,7 +85,7 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
85 return 0; 85 return 0;
86} 86}
87 87
88static struct irqchip pnx4008_irq_chip = { 88static struct irq_chip pnx4008_irq_chip = {
89 .ack = pnx4008_mask_ack_irq, 89 .ack = pnx4008_mask_ack_irq,
90 .mask = pnx4008_mask_irq, 90 .mask = pnx4008_mask_irq,
91 .unmask = pnx4008_unmask_irq, 91 .unmask = pnx4008_unmask_irq,
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 03d07cae26c8..9e3d0bdcba07 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -13,12 +13,10 @@ config ARCH_LUBBOCK
13config MACH_LOGICPD_PXA270 13config MACH_LOGICPD_PXA270
14 bool "LogicPD PXA270 Card Engine Development Platform" 14 bool "LogicPD PXA270 Card Engine Development Platform"
15 select PXA27x 15 select PXA27x
16 select IWMMXT
17 16
18config MACH_MAINSTONE 17config MACH_MAINSTONE
19 bool "Intel HCDDBBVA0 Development Platform" 18 bool "Intel HCDDBBVA0 Development Platform"
20 select PXA27x 19 select PXA27x
21 select IWMMXT
22 20
23config ARCH_PXA_IDP 21config ARCH_PXA_IDP
24 bool "Accelent Xscale IDP" 22 bool "Accelent Xscale IDP"
@@ -53,7 +51,6 @@ config PXA_SHARPSL_25x
53config PXA_SHARPSL_27x 51config PXA_SHARPSL_27x
54 bool "Sharp PXA270 models (SL-Cxx00)" 52 bool "Sharp PXA270 models (SL-Cxx00)"
55 select PXA27x 53 select PXA27x
56 select IWMMXT
57 54
58endchoice 55endchoice
59 56
@@ -129,11 +126,6 @@ config PXA27x
129 help 126 help
130 Select code specific to PXA27x variants 127 Select code specific to PXA27x variants
131 128
132config IWMMXT
133 bool
134 help
135 Enable support for iWMMXt
136
137config PXA_SHARP_C7xx 129config PXA_SHARP_C7xx
138 bool 130 bool
139 select PXA_SSP 131 select PXA_SSP
diff --git a/arch/arm/mach-pxa/akita-ioexp.c b/arch/arm/mach-pxa/akita-ioexp.c
index 1b398742ab56..12d2fe0ceff6 100644
--- a/arch/arm/mach-pxa/akita-ioexp.c
+++ b/arch/arm/mach-pxa/akita-ioexp.c
@@ -36,11 +36,11 @@ I2C_CLIENT_INSMOD;
36 36
37static int max7310_write(struct i2c_client *client, int address, int data); 37static int max7310_write(struct i2c_client *client, int address, int data);
38static struct i2c_client max7310_template; 38static struct i2c_client max7310_template;
39static void akita_ioexp_work(void *private_); 39static void akita_ioexp_work(struct work_struct *private_);
40 40
41static struct device *akita_ioexp_device; 41static struct device *akita_ioexp_device;
42static unsigned char ioexp_output_value = AKITA_IOEXP_IO_OUT; 42static unsigned char ioexp_output_value = AKITA_IOEXP_IO_OUT;
43DECLARE_WORK(akita_ioexp, akita_ioexp_work, NULL); 43DECLARE_WORK(akita_ioexp, akita_ioexp_work);
44 44
45 45
46/* 46/*
@@ -158,7 +158,7 @@ void akita_reset_ioexp(struct device *dev, unsigned char bit)
158EXPORT_SYMBOL(akita_set_ioexp); 158EXPORT_SYMBOL(akita_set_ioexp);
159EXPORT_SYMBOL(akita_reset_ioexp); 159EXPORT_SYMBOL(akita_reset_ioexp);
160 160
161static void akita_ioexp_work(void *private_) 161static void akita_ioexp_work(struct work_struct *private_)
162{ 162{
163 if (akita_ioexp_device) 163 if (akita_ioexp_device)
164 max7310_set_ouputs(akita_ioexp_device, ioexp_output_value); 164 max7310_set_ouputs(akita_ioexp_device, ioexp_output_value);
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 45fb2c3bcf82..6ae605857ca9 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -25,6 +25,10 @@
25#include <linux/pm.h> 25#include <linux/pm.h>
26#include <linux/string.h> 26#include <linux/string.h>
27 27
28#include <linux/sched.h>
29#include <asm/cnt32_to_63.h>
30#include <asm/div64.h>
31
28#include <asm/hardware.h> 32#include <asm/hardware.h>
29#include <asm/irq.h> 33#include <asm/irq.h>
30#include <asm/system.h> 34#include <asm/system.h>
@@ -41,6 +45,62 @@
41#include "generic.h" 45#include "generic.h"
42 46
43/* 47/*
48 * This is the PXA2xx sched_clock implementation. This has a resolution
49 * of at least 308ns and a maximum value that depends on the value of
50 * CLOCK_TICK_RATE.
51 *
52 * The return value is guaranteed to be monotonic in that range as
53 * long as there is always less than 582 seconds between successive
54 * calls to this function.
55 */
56unsigned long long sched_clock(void)
57{
58 unsigned long long v = cnt32_to_63(OSCR);
59 /* Note: top bit ov v needs cleared unless multiplier is even. */
60
61#if CLOCK_TICK_RATE == 3686400
62 /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
63 /* The <<1 is used to get rid of tick.hi top bit */
64 v *= 78125<<1;
65 do_div(v, 288<<1);
66#elif CLOCK_TICK_RATE == 3250000
67 /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
68 v *= 4000;
69 do_div(v, 13);
70#elif CLOCK_TICK_RATE == 3249600
71 /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
72 v *= 625000;
73 do_div(v, 2031);
74#else
75#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
76 /*
77 * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
78 * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
79 * years range which is nice, but with higher computation cost.
80 */
81 {
82 union {
83 unsigned long long val;
84 struct { unsigned long lo, hi; };
85 } x;
86 unsigned long long y;
87
88 x.val = v;
89 x.hi &= 0x7fffffff;
90 y = (unsigned long long)x.lo * NSEC_PER_SEC;
91 x.lo = y;
92 y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
93 x.hi = do_div(y, CLOCK_TICK_RATE);
94 do_div(x.val, CLOCK_TICK_RATE);
95 x.hi += y;
96 v = x.val;
97 }
98#endif
99
100 return v;
101}
102
103/*
44 * Handy function to set GPIO alternate functions 104 * Handy function to set GPIO alternate functions
45 */ 105 */
46 106
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index ab1a16025d51..f815678a9d63 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -143,7 +143,7 @@ static struct irq_chip pxa_low_gpio_chip = {
143 * Demux handler for GPIO>=2 edge detect interrupts 143 * Demux handler for GPIO>=2 edge detect interrupts
144 */ 144 */
145 145
146static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc) 146static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
147{ 147{
148 unsigned int mask; 148 unsigned int mask;
149 int loop; 149 int loop;
@@ -286,27 +286,27 @@ void __init pxa_init_irq(void)
286 286
287 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { 287 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
288 set_irq_chip(irq, &pxa_internal_chip_low); 288 set_irq_chip(irq, &pxa_internal_chip_low);
289 set_irq_handler(irq, do_level_IRQ); 289 set_irq_handler(irq, handle_level_irq);
290 set_irq_flags(irq, IRQF_VALID); 290 set_irq_flags(irq, IRQF_VALID);
291 } 291 }
292 292
293#if PXA_INTERNAL_IRQS > 32 293#if PXA_INTERNAL_IRQS > 32
294 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { 294 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
295 set_irq_chip(irq, &pxa_internal_chip_high); 295 set_irq_chip(irq, &pxa_internal_chip_high);
296 set_irq_handler(irq, do_level_IRQ); 296 set_irq_handler(irq, handle_level_irq);
297 set_irq_flags(irq, IRQF_VALID); 297 set_irq_flags(irq, IRQF_VALID);
298 } 298 }
299#endif 299#endif
300 300
301 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 301 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
302 set_irq_chip(irq, &pxa_low_gpio_chip); 302 set_irq_chip(irq, &pxa_low_gpio_chip);
303 set_irq_handler(irq, do_edge_IRQ); 303 set_irq_handler(irq, handle_edge_irq);
304 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 304 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
305 } 305 }
306 306
307 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { 307 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
308 set_irq_chip(irq, &pxa_muxed_gpio_chip); 308 set_irq_chip(irq, &pxa_muxed_gpio_chip);
309 set_irq_handler(irq, do_edge_IRQ); 309 set_irq_handler(irq, handle_edge_irq);
310 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 310 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
311 } 311 }
312 312
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 5749f6b72e12..8e27a64fa9f4 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -75,7 +75,7 @@ static struct irq_chip lpd270_irq_chip = {
75 .unmask = lpd270_unmask_irq, 75 .unmask = lpd270_unmask_irq,
76}; 76};
77 77
78static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc) 78static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
79{ 79{
80 unsigned long pending; 80 unsigned long pending;
81 81
@@ -105,7 +105,7 @@ static void __init lpd270_init_irq(void)
105 /* setup extra LogicPD PXA270 irqs */ 105 /* setup extra LogicPD PXA270 irqs */
106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { 106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
107 set_irq_chip(irq, &lpd270_irq_chip); 107 set_irq_chip(irq, &lpd270_irq_chip);
108 set_irq_handler(irq, do_level_IRQ); 108 set_irq_handler(irq, handle_level_irq);
109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
110 } 110 }
111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); 111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 142c33c3dff5..055de7f4f00a 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -85,7 +85,7 @@ static struct irq_chip lubbock_irq_chip = {
85 .unmask = lubbock_unmask_irq, 85 .unmask = lubbock_unmask_irq,
86}; 86};
87 87
88static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc) 88static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
89{ 89{
90 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; 90 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
91 do { 91 do {
@@ -108,7 +108,7 @@ static void __init lubbock_init_irq(void)
108 /* setup extra lubbock irqs */ 108 /* setup extra lubbock irqs */
109 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { 109 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
110 set_irq_chip(irq, &lubbock_irq_chip); 110 set_irq_chip(irq, &lubbock_irq_chip);
111 set_irq_handler(irq, do_level_IRQ); 111 set_irq_handler(irq, handle_level_irq);
112 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 112 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
113 } 113 }
114 114
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 49c34d94a9fe..56d94d88d5ca 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -71,7 +71,7 @@ static struct irq_chip mainstone_irq_chip = {
71 .unmask = mainstone_unmask_irq, 71 .unmask = mainstone_unmask_irq,
72}; 72};
73 73
74static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc) 74static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
75{ 75{
76 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; 76 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
77 do { 77 do {
@@ -94,7 +94,7 @@ static void __init mainstone_init_irq(void)
94 /* setup extra Mainstone irqs */ 94 /* setup extra Mainstone irqs */
95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { 95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
96 set_irq_chip(irq, &mainstone_irq_chip); 96 set_irq_chip(irq, &mainstone_irq_chip);
97 set_irq_handler(irq, do_level_IRQ); 97 set_irq_handler(irq, handle_level_irq);
98 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) 98 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
99 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); 99 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
100 else 100 else
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 2112c414f0e2..b4d8276d6050 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -83,7 +83,8 @@ int pxa_pm_enter(suspend_state_t state)
83 83
84#ifdef CONFIG_IWMMXT 84#ifdef CONFIG_IWMMXT
85 /* force any iWMMXt context to ram **/ 85 /* force any iWMMXt context to ram **/
86 iwmmxt_task_disable(NULL); 86 if (elf_hwcap & HWCAP_IWMMXT)
87 iwmmxt_task_disable(NULL);
87#endif 88#endif
88 89
89 /* preserve current time */ 90 /* preserve current time */
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 3ac268fa419b..3775b8f38429 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -18,6 +18,7 @@
18#include <linux/signal.h> 18#include <linux/signal.h>
19#include <linux/errno.h> 19#include <linux/errno.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/clocksource.h>
21 22
22#include <asm/system.h> 23#include <asm/system.h>
23#include <asm/hardware.h> 24#include <asm/hardware.h>
@@ -48,27 +49,6 @@ static int pxa_set_rtc(void)
48 return 0; 49 return 0;
49} 50}
50 51
51/* IRQs are disabled before entering here from do_gettimeofday() */
52static unsigned long pxa_gettimeoffset (void)
53{
54 long ticks_to_match, elapsed, usec;
55
56 /* Get ticks before next timer match */
57 ticks_to_match = OSMR0 - OSCR;
58
59 /* We need elapsed ticks since last match */
60 elapsed = LATCH - ticks_to_match;
61
62 /* don't get fooled by the workaround in pxa_timer_interrupt() */
63 if (elapsed <= 0)
64 return 0;
65
66 /* Now convert them to usec */
67 usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
68
69 return usec;
70}
71
72#ifdef CONFIG_NO_IDLE_HZ 52#ifdef CONFIG_NO_IDLE_HZ
73static unsigned long initial_match; 53static unsigned long initial_match;
74static int match_posponed; 54static int match_posponed;
@@ -121,9 +101,24 @@ static struct irqaction pxa_timer_irq = {
121 .handler = pxa_timer_interrupt, 101 .handler = pxa_timer_interrupt,
122}; 102};
123 103
104cycle_t pxa_get_cycles(void)
105{
106 return OSCR;
107}
108
109static struct clocksource clocksource_pxa = {
110 .name = "pxa_timer",
111 .rating = 200,
112 .read = pxa_get_cycles,
113 .mask = CLOCKSOURCE_MASK(32),
114 .shift = 20,
115 .is_continuous = 1,
116};
117
124static void __init pxa_timer_init(void) 118static void __init pxa_timer_init(void)
125{ 119{
126 struct timespec tv; 120 struct timespec tv;
121 unsigned long flags;
127 122
128 set_rtc = pxa_set_rtc; 123 set_rtc = pxa_set_rtc;
129 124
@@ -132,12 +127,20 @@ static void __init pxa_timer_init(void)
132 do_settimeofday(&tv); 127 do_settimeofday(&tv);
133 128
134 OIER = 0; /* disable any timer interrupts */ 129 OIER = 0; /* disable any timer interrupts */
135 OSCR = LATCH*2; /* push OSCR out of the way */
136 OSMR0 = LATCH; /* set initial match */
137 OSSR = 0xf; /* clear status on all timers */ 130 OSSR = 0xf; /* clear status on all timers */
138 setup_irq(IRQ_OST0, &pxa_timer_irq); 131 setup_irq(IRQ_OST0, &pxa_timer_irq);
132 local_irq_save(flags);
139 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ 133 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
140 OSCR = 0; /* initialize free-running timer */ 134 OSMR0 = OSCR + LATCH; /* set initial match */
135 local_irq_restore(flags);
136
137 /* on PXA OSCR runs continiously and is not written to, so we can use it
138 * as clock source directly.
139 */
140 clocksource_pxa.mult =
141 clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_pxa.shift);
142 clocksource_register(&clocksource_pxa);
143
141} 144}
142 145
143#ifdef CONFIG_NO_IDLE_HZ 146#ifdef CONFIG_NO_IDLE_HZ
@@ -210,7 +213,6 @@ struct sys_timer pxa_timer = {
210 .init = pxa_timer_init, 213 .init = pxa_timer_init,
211 .suspend = pxa_timer_suspend, 214 .suspend = pxa_timer_suspend,
212 .resume = pxa_timer_resume, 215 .resume = pxa_timer_resume,
213 .offset = pxa_gettimeoffset,
214#ifdef CONFIG_NO_IDLE_HZ 216#ifdef CONFIG_NO_IDLE_HZ
215 .dyn_tick = &pxa_dyn_tick, 217 .dyn_tick = &pxa_dyn_tick,
216#endif 218#endif
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index c1827d021ba8..119c64b7223f 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -393,10 +393,6 @@ static struct pxafb_mach_info sharp_lcd = {
393 .pxafb_backlight_power = board_backlight_power, 393 .pxafb_backlight_power = board_backlight_power,
394}; 394};
395 395
396static void __init trizeps4_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi)
397{
398}
399
400static void __init trizeps4_init(void) 396static void __init trizeps4_init(void)
401{ 397{
402 platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices)); 398 platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices));
@@ -469,7 +465,6 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
469 .phys_io = 0x40000000, 465 .phys_io = 0x40000000,
470 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, 466 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
471 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100, 467 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100,
472 .fixup = trizeps4_fixup,
473 .init_machine = trizeps4_init, 468 .init_machine = trizeps4_init,
474 .map_io = trizeps4_map_io, 469 .map_io = trizeps4_map_io,
475 .init_irq = pxa_init_irq, 470 .init_irq = pxa_init_irq,
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 68c67053f479..84d3fe76e94e 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -141,6 +141,19 @@ struct platform_device realview_smc91x_device = {
141 .resource = realview_smc91x_resources, 141 .resource = realview_smc91x_resources,
142}; 142};
143 143
144static struct resource realview_i2c_resource = {
145 .start = REALVIEW_I2C_BASE,
146 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
147 .flags = IORESOURCE_MEM,
148};
149
150struct platform_device realview_i2c_device = {
151 .name = "versatile-i2c",
152 .id = -1,
153 .num_resources = 1,
154 .resource = &realview_i2c_resource,
155};
156
144#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) 157#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
145 158
146static unsigned int realview_mmc_status(struct device *dev) 159static unsigned int realview_mmc_status(struct device *dev)
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 93e86d9f439c..2b53420f9c1b 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -108,6 +108,7 @@ static struct amba_device name##_device = { \
108 108
109extern struct platform_device realview_flash_device; 109extern struct platform_device realview_flash_device;
110extern struct platform_device realview_smc91x_device; 110extern struct platform_device realview_smc91x_device;
111extern struct platform_device realview_i2c_device;
111extern struct mmc_platform_data realview_mmc0_plat_data; 112extern struct mmc_platform_data realview_mmc0_plat_data;
112extern struct mmc_platform_data realview_mmc1_plat_data; 113extern struct mmc_platform_data realview_mmc1_plat_data;
113extern struct clk realview_clcd_clk; 114extern struct clk realview_clcd_clk;
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 84a959530fb6..9741b4d3c9cf 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -155,6 +155,7 @@ static void __init realview_eb_init(void)
155 155
156 platform_device_register(&realview_flash_device); 156 platform_device_register(&realview_flash_device);
157 platform_device_register(&realview_smc91x_device); 157 platform_device_register(&realview_smc91x_device);
158 platform_device_register(&realview_i2c_device);
158 159
159 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 160 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
160 struct amba_device *d = amba_devs[i]; 161 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 56b2716f8cf5..7a029621db43 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -34,7 +34,7 @@ static void iomd_unmask_irq_a(unsigned int irq)
34 iomd_writeb(val | mask, IOMD_IRQMASKA); 34 iomd_writeb(val | mask, IOMD_IRQMASKA);
35} 35}
36 36
37static struct irqchip iomd_a_chip = { 37static struct irq_chip iomd_a_chip = {
38 .ack = iomd_ack_irq_a, 38 .ack = iomd_ack_irq_a,
39 .mask = iomd_mask_irq_a, 39 .mask = iomd_mask_irq_a,
40 .unmask = iomd_unmask_irq_a, 40 .unmask = iomd_unmask_irq_a,
@@ -58,7 +58,7 @@ static void iomd_unmask_irq_b(unsigned int irq)
58 iomd_writeb(val | mask, IOMD_IRQMASKB); 58 iomd_writeb(val | mask, IOMD_IRQMASKB);
59} 59}
60 60
61static struct irqchip iomd_b_chip = { 61static struct irq_chip iomd_b_chip = {
62 .ack = iomd_mask_irq_b, 62 .ack = iomd_mask_irq_b,
63 .mask = iomd_mask_irq_b, 63 .mask = iomd_mask_irq_b,
64 .unmask = iomd_unmask_irq_b, 64 .unmask = iomd_unmask_irq_b,
@@ -82,7 +82,7 @@ static void iomd_unmask_irq_dma(unsigned int irq)
82 iomd_writeb(val | mask, IOMD_DMAMASK); 82 iomd_writeb(val | mask, IOMD_DMAMASK);
83} 83}
84 84
85static struct irqchip iomd_dma_chip = { 85static struct irq_chip iomd_dma_chip = {
86 .ack = iomd_mask_irq_dma, 86 .ack = iomd_mask_irq_dma,
87 .mask = iomd_mask_irq_dma, 87 .mask = iomd_mask_irq_dma,
88 .unmask = iomd_unmask_irq_dma, 88 .unmask = iomd_unmask_irq_dma,
@@ -106,7 +106,7 @@ static void iomd_unmask_irq_fiq(unsigned int irq)
106 iomd_writeb(val | mask, IOMD_FIQMASK); 106 iomd_writeb(val | mask, IOMD_FIQMASK);
107} 107}
108 108
109static struct irqchip iomd_fiq_chip = { 109static struct irq_chip iomd_fiq_chip = {
110 .ack = iomd_mask_irq_fiq, 110 .ack = iomd_mask_irq_fiq,
111 .mask = iomd_mask_irq_fiq, 111 .mask = iomd_mask_irq_fiq,
112 .unmask = iomd_unmask_irq_fiq, 112 .unmask = iomd_unmask_irq_fiq,
@@ -134,19 +134,19 @@ void __init rpc_init_irq(void)
134 switch (irq) { 134 switch (irq) {
135 case 0 ... 7: 135 case 0 ... 7:
136 set_irq_chip(irq, &iomd_a_chip); 136 set_irq_chip(irq, &iomd_a_chip);
137 set_irq_handler(irq, do_level_IRQ); 137 set_irq_handler(irq, handle_level_irq);
138 set_irq_flags(irq, flags); 138 set_irq_flags(irq, flags);
139 break; 139 break;
140 140
141 case 8 ... 15: 141 case 8 ... 15:
142 set_irq_chip(irq, &iomd_b_chip); 142 set_irq_chip(irq, &iomd_b_chip);
143 set_irq_handler(irq, do_level_IRQ); 143 set_irq_handler(irq, handle_level_irq);
144 set_irq_flags(irq, flags); 144 set_irq_flags(irq, flags);
145 break; 145 break;
146 146
147 case 16 ... 21: 147 case 16 ... 21:
148 set_irq_chip(irq, &iomd_dma_chip); 148 set_irq_chip(irq, &iomd_dma_chip);
149 set_irq_handler(irq, do_level_IRQ); 149 set_irq_handler(irq, handle_level_irq);
150 set_irq_flags(irq, flags); 150 set_irq_flags(irq, flags);
151 break; 151 break;
152 152
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 63965c78de8c..9f46bf330bc8 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -41,9 +41,16 @@ config BAST_PC104_IRQ
41 Say Y here to enable the PC104 IRQ routing on the 41 Say Y here to enable the PC104 IRQ routing on the
42 Simtec BAST (EB2410ITX) 42 Simtec BAST (EB2410ITX)
43 43
44config PM_H1940
45 bool
46 depends on PM
47 help
48 Internal node for H1940 and related PM
49
44config ARCH_H1940 50config ARCH_H1940
45 bool "IPAQ H1940" 51 bool "IPAQ H1940"
46 select CPU_S3C2410 52 select CPU_S3C2410
53 select PM_H1940
47 help 54 help
48 Say Y here if you are using the HP IPAQ H1940 55 Say Y here if you are using the HP IPAQ H1940
49 56
@@ -91,7 +98,7 @@ config SMDK2440_CPU2442
91config MACH_S3C2413 98config MACH_S3C2413
92 bool 99 bool
93 help 100 help
94 Internal node for S3C2413 verison of SMDK2413, so that 101 Internal node for S3C2413 version of SMDK2413, so that
95 machine_is_s3c2413() will work when MACH_SMDK2413 is 102 machine_is_s3c2413() will work when MACH_SMDK2413 is
96 selected 103 selected
97 104
@@ -115,6 +122,7 @@ config MACH_VR1000
115config MACH_RX3715 122config MACH_RX3715
116 bool "HP iPAQ rx3715" 123 bool "HP iPAQ rx3715"
117 select CPU_S3C2440 124 select CPU_S3C2440
125 select PM_H1940
118 help 126 help
119 Say Y here if you are using the HP iPAQ rx3715. 127 Say Y here if you are using the HP iPAQ rx3715.
120 128
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index d66013365b6b..27663e28cc88 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += s3c2410-dma.o
31 31
32obj-$(CONFIG_PM) += pm.o sleep.o 32obj-$(CONFIG_PM) += pm.o sleep.o
33obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 33obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
34obj-$(CONFIG_PM_H1940) += pm-h1940.o
34 35
35# S3C2412 support 36# S3C2412 support
36obj-$(CONFIG_CPU_S3C2412) += s3c2412.o 37obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 23d5beea5568..379efe70778c 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -88,7 +88,7 @@ bast_pc104_mask(unsigned int irqno)
88static void 88static void
89bast_pc104_maskack(unsigned int irqno) 89bast_pc104_maskack(unsigned int irqno)
90{ 90{
91 struct irqdesc *desc = irq_desc + IRQ_ISA; 91 struct irq_desc *desc = irq_desc + IRQ_ISA;
92 92
93 bast_pc104_mask(irqno); 93 bast_pc104_mask(irqno);
94 desc->chip->ack(IRQ_ISA); 94 desc->chip->ack(IRQ_ISA);
@@ -104,7 +104,7 @@ bast_pc104_unmask(unsigned int irqno)
104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK); 104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
105} 105}
106 106
107static struct irqchip bast_pc104_chip = { 107static struct irq_chip bast_pc104_chip = {
108 .mask = bast_pc104_mask, 108 .mask = bast_pc104_mask,
109 .unmask = bast_pc104_unmask, 109 .unmask = bast_pc104_unmask,
110 .ack = bast_pc104_maskack 110 .ack = bast_pc104_maskack
@@ -112,7 +112,7 @@ static struct irqchip bast_pc104_chip = {
112 112
113static void 113static void
114bast_irq_pc104_demux(unsigned int irq, 114bast_irq_pc104_demux(unsigned int irq,
115 struct irqdesc *desc) 115 struct irq_desc *desc)
116{ 116{
117 unsigned int stat; 117 unsigned int stat;
118 unsigned int irqno; 118 unsigned int irqno;
@@ -157,7 +157,7 @@ static __init int bast_irq_init(void)
157 unsigned int irqno = bast_pc104_irqs[i]; 157 unsigned int irqno = bast_pc104_irqs[i];
158 158
159 set_irq_chip(irqno, &bast_pc104_chip); 159 set_irq_chip(irqno, &bast_pc104_chip);
160 set_irq_handler(irqno, do_level_IRQ); 160 set_irq_handler(irqno, handle_level_irq);
161 set_irq_flags(irqno, IRQF_VALID); 161 set_irq_flags(irqno, IRQF_VALID);
162 } 162 }
163 } 163 }
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 3d211dc2f2f9..01abb0ace234 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -40,7 +40,7 @@
40 40
41/* io map for dma */ 41/* io map for dma */
42static void __iomem *dma_base; 42static void __iomem *dma_base;
43static kmem_cache_t *dma_kmem; 43static struct kmem_cache *dma_kmem;
44 44
45struct s3c24xx_dma_selection dma_sel; 45struct s3c24xx_dma_selection dma_sel;
46 46
@@ -1271,7 +1271,7 @@ struct sysdev_class dma_sysclass = {
1271 1271
1272/* kmem cache implementation */ 1272/* kmem cache implementation */
1273 1273
1274static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f) 1274static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f)
1275{ 1275{
1276 memset(p, 0, sizeof(struct s3c2410_dma_buf)); 1276 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1277} 1277}
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 683b3491ba3c..3c0ed7871c55 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
180 __raw_writel(mask, S3C2410_INTMSK); 180 __raw_writel(mask, S3C2410_INTMSK);
181} 181}
182 182
183struct irqchip s3c_irq_level_chip = { 183struct irq_chip s3c_irq_level_chip = {
184 .name = "s3c-level", 184 .name = "s3c-level",
185 .ack = s3c_irq_maskack, 185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask, 186 .mask = s3c_irq_mask,
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = {
188 .set_wake = s3c_irq_wake 188 .set_wake = s3c_irq_wake
189}; 189};
190 190
191static struct irqchip s3c_irq_chip = { 191static struct irq_chip s3c_irq_chip = {
192 .name = "s3c", 192 .name = "s3c",
193 .ack = s3c_irq_ack, 193 .ack = s3c_irq_ack,
194 .mask = s3c_irq_mask, 194 .mask = s3c_irq_mask,
@@ -206,18 +206,6 @@ s3c_irqext_mask(unsigned int irqno)
206 mask = __raw_readl(S3C24XX_EINTMASK); 206 mask = __raw_readl(S3C24XX_EINTMASK);
207 mask |= ( 1UL << irqno); 207 mask |= ( 1UL << irqno);
208 __raw_writel(mask, S3C24XX_EINTMASK); 208 __raw_writel(mask, S3C24XX_EINTMASK);
209
210 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
211 /* check to see if all need masking */
212
213 if ((mask & (0xf << 4)) == (0xf << 4)) {
214 /* all masked, mask the parent */
215 s3c_irq_mask(IRQ_EINT4t7);
216 }
217 } else {
218 /* todo: the same check as above for the rest of the irq regs...*/
219
220 }
221} 209}
222 210
223static void 211static void
@@ -229,7 +217,6 @@ s3c_irqext_ack(unsigned int irqno)
229 217
230 bit = 1UL << (irqno - EXTINT_OFF); 218 bit = 1UL << (irqno - EXTINT_OFF);
231 219
232
233 mask = __raw_readl(S3C24XX_EINTMASK); 220 mask = __raw_readl(S3C24XX_EINTMASK);
234 221
235 __raw_writel(bit, S3C24XX_EINTPEND); 222 __raw_writel(bit, S3C24XX_EINTPEND);
@@ -258,8 +245,6 @@ s3c_irqext_unmask(unsigned int irqno)
258 mask = __raw_readl(S3C24XX_EINTMASK); 245 mask = __raw_readl(S3C24XX_EINTMASK);
259 mask &= ~( 1UL << irqno); 246 mask &= ~( 1UL << irqno);
260 __raw_writel(mask, S3C24XX_EINTMASK); 247 __raw_writel(mask, S3C24XX_EINTMASK);
261
262 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
263} 248}
264 249
265int 250int
@@ -344,7 +329,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
344 return 0; 329 return 0;
345} 330}
346 331
347static struct irqchip s3c_irqext_chip = { 332static struct irq_chip s3c_irqext_chip = {
348 .name = "s3c-ext", 333 .name = "s3c-ext",
349 .mask = s3c_irqext_mask, 334 .mask = s3c_irqext_mask,
350 .unmask = s3c_irqext_unmask, 335 .unmask = s3c_irqext_unmask,
@@ -353,7 +338,7 @@ static struct irqchip s3c_irqext_chip = {
353 .set_wake = s3c_irqext_wake 338 .set_wake = s3c_irqext_wake
354}; 339};
355 340
356static struct irqchip s3c_irq_eint0t4 = { 341static struct irq_chip s3c_irq_eint0t4 = {
357 .name = "s3c-ext0", 342 .name = "s3c-ext0",
358 .ack = s3c_irq_ack, 343 .ack = s3c_irq_ack,
359 .mask = s3c_irq_mask, 344 .mask = s3c_irq_mask,
@@ -390,7 +375,7 @@ s3c_irq_uart0_ack(unsigned int irqno)
390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); 375 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
391} 376}
392 377
393static struct irqchip s3c_irq_uart0 = { 378static struct irq_chip s3c_irq_uart0 = {
394 .name = "s3c-uart0", 379 .name = "s3c-uart0",
395 .mask = s3c_irq_uart0_mask, 380 .mask = s3c_irq_uart0_mask,
396 .unmask = s3c_irq_uart0_unmask, 381 .unmask = s3c_irq_uart0_unmask,
@@ -417,7 +402,7 @@ s3c_irq_uart1_ack(unsigned int irqno)
417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); 402 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
418} 403}
419 404
420static struct irqchip s3c_irq_uart1 = { 405static struct irq_chip s3c_irq_uart1 = {
421 .name = "s3c-uart1", 406 .name = "s3c-uart1",
422 .mask = s3c_irq_uart1_mask, 407 .mask = s3c_irq_uart1_mask,
423 .unmask = s3c_irq_uart1_unmask, 408 .unmask = s3c_irq_uart1_unmask,
@@ -444,7 +429,7 @@ s3c_irq_uart2_ack(unsigned int irqno)
444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); 429 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
445} 430}
446 431
447static struct irqchip s3c_irq_uart2 = { 432static struct irq_chip s3c_irq_uart2 = {
448 .name = "s3c-uart2", 433 .name = "s3c-uart2",
449 .mask = s3c_irq_uart2_mask, 434 .mask = s3c_irq_uart2_mask,
450 .unmask = s3c_irq_uart2_unmask, 435 .unmask = s3c_irq_uart2_unmask,
@@ -471,7 +456,7 @@ s3c_irq_adc_ack(unsigned int irqno)
471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); 456 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
472} 457}
473 458
474static struct irqchip s3c_irq_adc = { 459static struct irq_chip s3c_irq_adc = {
475 .name = "s3c-adc", 460 .name = "s3c-adc",
476 .mask = s3c_irq_adc_mask, 461 .mask = s3c_irq_adc_mask,
477 .unmask = s3c_irq_adc_unmask, 462 .unmask = s3c_irq_adc_unmask,
@@ -480,11 +465,11 @@ static struct irqchip s3c_irq_adc = {
480 465
481/* irq demux for adc */ 466/* irq demux for adc */
482static void s3c_irq_demux_adc(unsigned int irq, 467static void s3c_irq_demux_adc(unsigned int irq,
483 struct irqdesc *desc) 468 struct irq_desc *desc)
484{ 469{
485 unsigned int subsrc, submsk; 470 unsigned int subsrc, submsk;
486 unsigned int offset = 9; 471 unsigned int offset = 9;
487 struct irqdesc *mydesc; 472 struct irq_desc *mydesc;
488 473
489 /* read the current pending interrupts, and the mask 474 /* read the current pending interrupts, and the mask
490 * for what it is available */ 475 * for what it is available */
@@ -512,7 +497,7 @@ static void s3c_irq_demux_uart(unsigned int start)
512{ 497{
513 unsigned int subsrc, submsk; 498 unsigned int subsrc, submsk;
514 unsigned int offset = start - IRQ_S3CUART_RX0; 499 unsigned int offset = start - IRQ_S3CUART_RX0;
515 struct irqdesc *desc; 500 struct irq_desc *desc;
516 501
517 /* read the current pending interrupts, and the mask 502 /* read the current pending interrupts, and the mask
518 * for what it is available */ 503 * for what it is available */
@@ -549,7 +534,7 @@ static void s3c_irq_demux_uart(unsigned int start)
549 534
550static void 535static void
551s3c_irq_demux_uart0(unsigned int irq, 536s3c_irq_demux_uart0(unsigned int irq,
552 struct irqdesc *desc) 537 struct irq_desc *desc)
553{ 538{
554 irq = irq; 539 irq = irq;
555 s3c_irq_demux_uart(IRQ_S3CUART_RX0); 540 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@@ -557,7 +542,7 @@ s3c_irq_demux_uart0(unsigned int irq,
557 542
558static void 543static void
559s3c_irq_demux_uart1(unsigned int irq, 544s3c_irq_demux_uart1(unsigned int irq,
560 struct irqdesc *desc) 545 struct irq_desc *desc)
561{ 546{
562 irq = irq; 547 irq = irq;
563 s3c_irq_demux_uart(IRQ_S3CUART_RX1); 548 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@@ -565,7 +550,7 @@ s3c_irq_demux_uart1(unsigned int irq,
565 550
566static void 551static void
567s3c_irq_demux_uart2(unsigned int irq, 552s3c_irq_demux_uart2(unsigned int irq,
568 struct irqdesc *desc) 553 struct irq_desc *desc)
569{ 554{
570 irq = irq; 555 irq = irq;
571 s3c_irq_demux_uart(IRQ_S3CUART_RX2); 556 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@@ -573,7 +558,7 @@ s3c_irq_demux_uart2(unsigned int irq,
573 558
574static void 559static void
575s3c_irq_demux_extint8(unsigned int irq, 560s3c_irq_demux_extint8(unsigned int irq,
576 struct irqdesc *desc) 561 struct irq_desc *desc)
577{ 562{
578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 563 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 564 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -595,7 +580,7 @@ s3c_irq_demux_extint8(unsigned int irq,
595 580
596static void 581static void
597s3c_irq_demux_extint4t7(unsigned int irq, 582s3c_irq_demux_extint4t7(unsigned int irq,
598 struct irqdesc *desc) 583 struct irq_desc *desc)
599{ 584{
600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 585 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 586 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -738,7 +723,7 @@ void __init s3c24xx_init_irq(void)
738 case IRQ_UART2: 723 case IRQ_UART2:
739 case IRQ_ADCPARENT: 724 case IRQ_ADCPARENT:
740 set_irq_chip(irqno, &s3c_irq_level_chip); 725 set_irq_chip(irqno, &s3c_irq_level_chip);
741 set_irq_handler(irqno, do_level_IRQ); 726 set_irq_handler(irqno, handle_level_irq);
742 break; 727 break;
743 728
744 case IRQ_RESERVED6: 729 case IRQ_RESERVED6:
@@ -749,7 +734,7 @@ void __init s3c24xx_init_irq(void)
749 default: 734 default:
750 //irqdbf("registering irq %d (s3c irq)\n", irqno); 735 //irqdbf("registering irq %d (s3c irq)\n", irqno);
751 set_irq_chip(irqno, &s3c_irq_chip); 736 set_irq_chip(irqno, &s3c_irq_chip);
752 set_irq_handler(irqno, do_edge_IRQ); 737 set_irq_handler(irqno, handle_edge_irq);
753 set_irq_flags(irqno, IRQF_VALID); 738 set_irq_flags(irqno, IRQF_VALID);
754 } 739 }
755 } 740 }
@@ -769,14 +754,14 @@ void __init s3c24xx_init_irq(void)
769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 754 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
770 irqdbf("registering irq %d (ext int)\n", irqno); 755 irqdbf("registering irq %d (ext int)\n", irqno);
771 set_irq_chip(irqno, &s3c_irq_eint0t4); 756 set_irq_chip(irqno, &s3c_irq_eint0t4);
772 set_irq_handler(irqno, do_edge_IRQ); 757 set_irq_handler(irqno, handle_edge_irq);
773 set_irq_flags(irqno, IRQF_VALID); 758 set_irq_flags(irqno, IRQF_VALID);
774 } 759 }
775 760
776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 761 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
777 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 762 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
778 set_irq_chip(irqno, &s3c_irqext_chip); 763 set_irq_chip(irqno, &s3c_irqext_chip);
779 set_irq_handler(irqno, do_edge_IRQ); 764 set_irq_handler(irqno, handle_edge_irq);
780 set_irq_flags(irqno, IRQF_VALID); 765 set_irq_flags(irqno, IRQF_VALID);
781 } 766 }
782 767
@@ -787,28 +772,28 @@ void __init s3c24xx_init_irq(void)
787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 772 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 773 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
789 set_irq_chip(irqno, &s3c_irq_uart0); 774 set_irq_chip(irqno, &s3c_irq_uart0);
790 set_irq_handler(irqno, do_level_IRQ); 775 set_irq_handler(irqno, handle_level_irq);
791 set_irq_flags(irqno, IRQF_VALID); 776 set_irq_flags(irqno, IRQF_VALID);
792 } 777 }
793 778
794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 779 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 780 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
796 set_irq_chip(irqno, &s3c_irq_uart1); 781 set_irq_chip(irqno, &s3c_irq_uart1);
797 set_irq_handler(irqno, do_level_IRQ); 782 set_irq_handler(irqno, handle_level_irq);
798 set_irq_flags(irqno, IRQF_VALID); 783 set_irq_flags(irqno, IRQF_VALID);
799 } 784 }
800 785
801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 786 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 787 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
803 set_irq_chip(irqno, &s3c_irq_uart2); 788 set_irq_chip(irqno, &s3c_irq_uart2);
804 set_irq_handler(irqno, do_level_IRQ); 789 set_irq_handler(irqno, handle_level_irq);
805 set_irq_flags(irqno, IRQF_VALID); 790 set_irq_flags(irqno, IRQF_VALID);
806 } 791 }
807 792
808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 793 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
809 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 794 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
810 set_irq_chip(irqno, &s3c_irq_adc); 795 set_irq_chip(irqno, &s3c_irq_adc);
811 set_irq_handler(irqno, do_edge_IRQ); 796 set_irq_handler(irqno, handle_edge_irq);
812 set_irq_flags(irqno, IRQF_VALID); 797 set_irq_flags(irqno, IRQF_VALID);
813 } 798 }
814 799
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
index 842a9f42c97b..3686a0082245 100644
--- a/arch/arm/mach-s3c2410/irq.h
+++ b/arch/arm/mach-s3c2410/irq.h
@@ -17,7 +17,7 @@
17 17
18#define EXTINT_OFF (IRQ_EINT4 - 4) 18#define EXTINT_OFF (IRQ_EINT4 - 4)
19 19
20extern struct irqchip s3c_irq_level_chip; 20extern struct irq_chip s3c_irq_level_chip;
21 21
22static inline void 22static inline void
23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, 23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 8c895c077d22..f5b98099a5d9 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -33,6 +33,7 @@
33#include <asm/arch/regs-serial.h> 33#include <asm/arch/regs-serial.h>
34#include <asm/arch/regs-lcd.h> 34#include <asm/arch/regs-lcd.h>
35 35
36#include <asm/arch/h1940.h>
36#include <asm/arch/h1940-latch.h> 37#include <asm/arch/h1940-latch.h>
37#include <asm/arch/fb.h> 38#include <asm/arch/fb.h>
38 39
@@ -41,6 +42,7 @@
41#include "clock.h" 42#include "clock.h"
42#include "devs.h" 43#include "devs.h"
43#include "cpu.h" 44#include "cpu.h"
45#include "pm.h"
44 46
45static struct map_desc h1940_iodesc[] __initdata = { 47static struct map_desc h1940_iodesc[] __initdata = {
46 [0] = { 48 [0] = {
@@ -164,12 +166,16 @@ static void __init h1940_map_io(void)
164 s3c24xx_init_clocks(0); 166 s3c24xx_init_clocks(0);
165 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); 167 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
166 s3c24xx_set_board(&h1940_board); 168 s3c24xx_set_board(&h1940_board);
169
170 /* setup PM */
171
172 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
173 s3c2410_pm_init();
167} 174}
168 175
169static void __init h1940_init_irq(void) 176static void __init h1940_init_irq(void)
170{ 177{
171 s3c24xx_init_irq(); 178 s3c24xx_init_irq();
172
173} 179}
174 180
175static void __init h1940_init(void) 181static void __init h1940_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c
index e193ba69e652..a4ab144e7292 100644
--- a/arch/arm/mach-s3c2410/mach-osiris.c
+++ b/arch/arm/mach-s3c2410/mach-osiris.c
@@ -114,6 +114,15 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
114 .clocks = osiris_serial_clocks, 114 .clocks = osiris_serial_clocks,
115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks), 115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
116 }, 116 },
117 [2] = {
118 .hwport = 2,
119 .flags = 0,
120 .ucon = UCON,
121 .ulcon = ULCON,
122 .ufcon = UFCON,
123 .clocks = osiris_serial_clocks,
124 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
125 }
117}; 126};
118 127
119/* NAND Flash on Osiris board */ 128/* NAND Flash on Osiris board */
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
index 23d7c052013c..ecbcdf79d739 100644
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ b/arch/arm/mach-s3c2410/mach-rx3715.c
@@ -42,6 +42,7 @@
42#include <asm/arch/regs-gpio.h> 42#include <asm/arch/regs-gpio.h>
43#include <asm/arch/regs-lcd.h> 43#include <asm/arch/regs-lcd.h>
44 44
45#include <asm/arch/h1940.h>
45#include <asm/arch/nand.h> 46#include <asm/arch/nand.h>
46#include <asm/arch/fb.h> 47#include <asm/arch/fb.h>
47 48
@@ -224,7 +225,9 @@ static void __init rx3715_init_irq(void)
224 225
225static void __init rx3715_init_machine(void) 226static void __init rx3715_init_machine(void)
226{ 227{
228 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
227 s3c2410_pm_init(); 229 s3c2410_pm_init();
230
228 s3c24xx_fb_set_platdata(&rx3715_lcdcfg); 231 s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
229} 232}
230 233
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index a0d7692cdb2b..e2eda3937ab0 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -41,6 +41,7 @@
41 41
42#include <asm/arch/regs-serial.h> 42#include <asm/arch/regs-serial.h>
43#include <asm/arch/regs-gpio.h> 43#include <asm/arch/regs-gpio.h>
44#include <asm/arch/leds-gpio.h>
44 45
45#include "clock.h" 46#include "clock.h"
46#include "devs.h" 47#include "devs.h"
@@ -313,6 +314,50 @@ static struct platform_device vr1000_dm9k1 = {
313 } 314 }
314}; 315};
315 316
317/* LEDS */
318
319static struct s3c24xx_led_platdata vr1000_led1_pdata = {
320 .name = "led1",
321 .gpio = S3C2410_GPB0,
322 .def_trigger = "",
323};
324
325static struct s3c24xx_led_platdata vr1000_led2_pdata = {
326 .name = "led2",
327 .gpio = S3C2410_GPB1,
328 .def_trigger = "",
329};
330
331static struct s3c24xx_led_platdata vr1000_led3_pdata = {
332 .name = "led3",
333 .gpio = S3C2410_GPB2,
334 .def_trigger = "",
335};
336
337static struct platform_device vr1000_led1 = {
338 .name = "s3c24xx_led",
339 .id = 1,
340 .dev = {
341 .platform_data = &vr1000_led1_pdata,
342 },
343};
344
345static struct platform_device vr1000_led2 = {
346 .name = "s3c24xx_led",
347 .id = 2,
348 .dev = {
349 .platform_data = &vr1000_led2_pdata,
350 },
351};
352
353static struct platform_device vr1000_led3 = {
354 .name = "s3c24xx_led",
355 .id = 1,
356 .dev = {
357 .platform_data = &vr1000_led3_pdata,
358 },
359};
360
316/* devices for this board */ 361/* devices for this board */
317 362
318static struct platform_device *vr1000_devices[] __initdata = { 363static struct platform_device *vr1000_devices[] __initdata = {
@@ -325,7 +370,10 @@ static struct platform_device *vr1000_devices[] __initdata = {
325 &serial_device, 370 &serial_device,
326 &vr1000_nor, 371 &vr1000_nor,
327 &vr1000_dm9k0, 372 &vr1000_dm9k0,
328 &vr1000_dm9k1 373 &vr1000_dm9k1,
374 &vr1000_led1,
375 &vr1000_led2,
376 &vr1000_led3,
329}; 377};
330 378
331static struct clk *vr1000_clocks[] = { 379static struct clk *vr1000_clocks[] = {
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c2410/pm-h1940.S
new file mode 100644
index 000000000000..7d66de7ff7db
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pm-h1940.S
@@ -0,0 +1,33 @@
1/* linux/arch/arm/mach-s3c2410/pm-h1940.S
2 *
3 * Copyright (c) 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 Suspend to RAM
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/linkage.h>
22#include <asm/assembler.h>
23#include <asm/hardware.h>
24#include <asm/arch/map.h>
25
26#include <asm/arch/regs-gpio.h>
27
28 .text
29 .global h1940_pm_return
30
31h1940_pm_return:
32 mov r0, #S3C2410_PA_GPIO
33 ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
diff --git a/arch/arm/mach-s3c2410/s3c2410-pm.c b/arch/arm/mach-s3c2410/s3c2410-pm.c
index e51d76669512..77c6814c0f05 100644
--- a/arch/arm/mach-s3c2410/s3c2410-pm.c
+++ b/arch/arm/mach-s3c2410/s3c2410-pm.c
@@ -32,6 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33 33
34#include <asm/arch/regs-gpio.h> 34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/h1940.h>
35 36
36#include "cpu.h" 37#include "cpu.h"
37#include "pm.h" 38#include "pm.h"
@@ -52,6 +53,35 @@ static void s3c2410_pm_prepare(void)
52 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); 53 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
53 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); 54 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
54 55
56 if (machine_is_h1940()) {
57 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
58 unsigned long ptr;
59 unsigned long calc = 0;
60
61 /* generate check for the bootloader to check on resume */
62
63 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
64 calc += __raw_readl(base+ptr);
65
66 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
67 }
68
69 /* the RX3715 uses similar code and the same H1940 and the
70 * same offsets for resume and checksum pointers */
71
72 if (machine_is_rx3715()) {
73 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
74 unsigned long ptr;
75 unsigned long calc = 0;
76
77 /* generate check for the bootloader to check on resume */
78
79 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
80 calc += __raw_readl(base+ptr);
81
82 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
83 }
84
55 if ( machine_is_aml_m5900() ) 85 if ( machine_is_aml_m5900() )
56 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 86 s3c2410_gpio_setpin(S3C2410_GPF2, 1);
57 87
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
index 7f741547658f..ffcc30b23a80 100644
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2412-irq.c
@@ -98,7 +98,7 @@ s3c2412_irq_unmask(unsigned int irqno)
98 __raw_writel(mask & ~bitval, S3C2410_INTMSK); 98 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
99} 99}
100 100
101static struct irqchip s3c2412_irq_eint0t4 = { 101static struct irq_chip s3c2412_irq_eint0t4 = {
102 .ack = s3c2412_irq_ack, 102 .ack = s3c2412_irq_ack,
103 .mask = s3c2412_irq_mask, 103 .mask = s3c2412_irq_mask,
104 .unmask = s3c2412_irq_unmask, 104 .unmask = s3c2412_irq_unmask,
@@ -112,7 +112,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
112 112
113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
114 set_irq_chip(irqno, &s3c2412_irq_eint0t4); 114 set_irq_chip(irqno, &s3c2412_irq_eint0t4);
115 set_irq_handler(irqno, do_edge_IRQ); 115 set_irq_handler(irqno, handle_edge_irq);
116 set_irq_flags(irqno, IRQF_VALID); 116 set_irq_flags(irqno, IRQF_VALID);
117 } 117 }
118 118
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 39db0752d53b..1ba19b27ab05 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -42,10 +42,10 @@
42/* WDT/AC97 */ 42/* WDT/AC97 */
43 43
44static void s3c_irq_demux_wdtac97(unsigned int irq, 44static void s3c_irq_demux_wdtac97(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -90,7 +90,7 @@ s3c_irq_wdtac97_ack(unsigned int irqno)
90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); 90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
91} 91}
92 92
93static struct irqchip s3c_irq_wdtac97 = { 93static struct irq_chip s3c_irq_wdtac97 = {
94 .mask = s3c_irq_wdtac97_mask, 94 .mask = s3c_irq_wdtac97_mask,
95 .unmask = s3c_irq_wdtac97_unmask, 95 .unmask = s3c_irq_wdtac97_unmask,
96 .ack = s3c_irq_wdtac97_ack, 96 .ack = s3c_irq_wdtac97_ack,
@@ -105,12 +105,12 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
105 /* add new chained handler for wdt, ac7 */ 105 /* add new chained handler for wdt, ac7 */
106 106
107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); 107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
108 set_irq_handler(IRQ_WDT, do_level_IRQ); 108 set_irq_handler(IRQ_WDT, handle_level_irq);
109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); 109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
110 110
111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { 111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
112 set_irq_chip(irqno, &s3c_irq_wdtac97); 112 set_irq_chip(irqno, &s3c_irq_wdtac97);
113 set_irq_handler(irqno, do_level_IRQ); 113 set_irq_handler(irqno, handle_level_irq);
114 set_irq_flags(irqno, IRQF_VALID); 114 set_irq_flags(irqno, IRQF_VALID);
115 } 115 }
116 116
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
index 146f2109dd90..ede94636a72a 100644
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -42,10 +42,10 @@
42/* camera irq */ 42/* camera irq */
43 43
44static void s3c_irq_demux_cam(unsigned int irq, 44static void s3c_irq_demux_cam(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -89,7 +89,7 @@ s3c_irq_cam_ack(unsigned int irqno)
89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); 89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
90} 90}
91 91
92static struct irqchip s3c_irq_cam = { 92static struct irq_chip s3c_irq_cam = {
93 .mask = s3c_irq_cam_mask, 93 .mask = s3c_irq_cam_mask,
94 .unmask = s3c_irq_cam_unmask, 94 .unmask = s3c_irq_cam_unmask,
95 .ack = s3c_irq_cam_ack, 95 .ack = s3c_irq_cam_ack,
@@ -100,18 +100,18 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
100 unsigned int irqno; 100 unsigned int irqno;
101 101
102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); 102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
103 set_irq_handler(IRQ_NFCON, do_level_IRQ); 103 set_irq_handler(IRQ_NFCON, handle_level_irq);
104 set_irq_flags(IRQ_NFCON, IRQF_VALID); 104 set_irq_flags(IRQ_NFCON, IRQF_VALID);
105 105
106 /* add chained handler for camera */ 106 /* add chained handler for camera */
107 107
108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); 108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
109 set_irq_handler(IRQ_CAM, do_level_IRQ); 109 set_irq_handler(IRQ_CAM, handle_level_irq);
110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); 110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
111 111
112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { 112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
113 set_irq_chip(irqno, &s3c_irq_cam); 113 set_irq_chip(irqno, &s3c_irq_cam);
114 set_irq_handler(irqno, do_level_IRQ); 114 set_irq_handler(irqno, handle_level_irq);
115 set_irq_flags(irqno, IRQF_VALID); 115 set_irq_flags(irqno, IRQF_VALID);
116 } 116 }
117 117
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 4575f316e141..e510295c2580 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -20,6 +20,7 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21 21
22#include <asm/div64.h> 22#include <asm/div64.h>
23#include <asm/cnt32_to_63.h>
23#include <asm/hardware.h> 24#include <asm/hardware.h>
24#include <asm/system.h> 25#include <asm/system.h>
25#include <asm/pgtable.h> 26#include <asm/pgtable.h>
@@ -118,15 +119,21 @@ EXPORT_SYMBOL(cpufreq_get);
118 119
119/* 120/*
120 * This is the SA11x0 sched_clock implementation. This has 121 * This is the SA11x0 sched_clock implementation. This has
121 * a resolution of 271ns, and a maximum value of 1165s. 122 * a resolution of 271ns, and a maximum value of 32025597s (370 days).
123 *
124 * The return value is guaranteed to be monotonic in that range as
125 * long as there is always less than 582 seconds between successive
126 * calls to this function.
127 *
122 * ( * 1E9 / 3686400 => * 78125 / 288) 128 * ( * 1E9 / 3686400 => * 78125 / 288)
123 */ 129 */
124unsigned long long sched_clock(void) 130unsigned long long sched_clock(void)
125{ 131{
126 unsigned long long v; 132 unsigned long long v = cnt32_to_63(OSCR);
127 133
128 v = (unsigned long long)OSCR * 78125; 134 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
129 do_div(v, 288); 135 v *= 78125<<1;
136 do_div(v, 288<<1);
130 137
131 return v; 138 return v;
132} 139}
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index fa6dc71bd6ad..b034ad69a324 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -702,7 +702,7 @@ static u32 gpio_irq_mask[] = {
702 GPIO2_SD_CON_SLT, 702 GPIO2_SD_CON_SLT,
703}; 703};
704 704
705static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc) 705static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc)
706{ 706{
707 int i; 707 int i;
708 708
@@ -719,14 +719,14 @@ static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
719 if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq); 719 if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
720 for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) 720 for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
721 if (irq & kpio_irq_mask[j]) 721 if (irq & kpio_irq_mask[j])
722 do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); 722 handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
723 723
724 /* GPIO2 */ 724 /* GPIO2 */
725 irq = H3800_ASIC2_GPIINTFLAG; 725 irq = H3800_ASIC2_GPIINTFLAG;
726 if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq); 726 if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
727 for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) 727 for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
728 if (irq & gpio_irq_mask[j]) 728 if (irq & gpio_irq_mask[j])
729 do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); 729 handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
730 } 730 }
731 731
732 if (i >= MAX_ASIC_ISR_LOOPS) 732 if (i >= MAX_ASIC_ISR_LOOPS)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index f4c6322ca33e..5642aeca079e 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -110,7 +110,7 @@ static struct irq_chip sa1100_low_gpio_chip = {
110 * and call the handler. 110 * and call the handler.
111 */ 111 */
112static void 112static void
113sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc) 113sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
114{ 114{
115 unsigned int mask; 115 unsigned int mask;
116 116
@@ -327,19 +327,19 @@ void __init sa1100_init_irq(void)
327 327
328 for (irq = 0; irq <= 10; irq++) { 328 for (irq = 0; irq <= 10; irq++) {
329 set_irq_chip(irq, &sa1100_low_gpio_chip); 329 set_irq_chip(irq, &sa1100_low_gpio_chip);
330 set_irq_handler(irq, do_edge_IRQ); 330 set_irq_handler(irq, handle_edge_irq);
331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
332 } 332 }
333 333
334 for (irq = 12; irq <= 31; irq++) { 334 for (irq = 12; irq <= 31; irq++) {
335 set_irq_chip(irq, &sa1100_normal_chip); 335 set_irq_chip(irq, &sa1100_normal_chip);
336 set_irq_handler(irq, do_level_IRQ); 336 set_irq_handler(irq, handle_level_irq);
337 set_irq_flags(irq, IRQF_VALID); 337 set_irq_flags(irq, IRQF_VALID);
338 } 338 }
339 339
340 for (irq = 32; irq <= 48; irq++) { 340 for (irq = 32; irq <= 48; irq++) {
341 set_irq_chip(irq, &sa1100_high_gpio_chip); 341 set_irq_chip(irq, &sa1100_high_gpio_chip);
342 set_irq_handler(irq, do_edge_IRQ); 342 set_irq_handler(irq, handle_edge_irq);
343 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 343 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
344 } 344 }
345 345
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 17f5a43acdb7..54ecdaa373d6 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -1,5 +1,15 @@
1/* 1/*
2 * linux/arch/arm/mach-sa1100/jornada720.c 2 * linux/arch/arm/mach-sa1100/jornada720.c
3 *
4 * HP Jornada720 init code
5 *
6 * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
7 * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
3 */ 13 */
4 14
5#include <linux/init.h> 15#include <linux/init.h>
@@ -10,13 +20,13 @@
10#include <linux/ioport.h> 20#include <linux/ioport.h>
11#include <linux/mtd/mtd.h> 21#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h> 22#include <linux/mtd/partitions.h>
23#include <video/s1d13xxxfb.h>
13 24
14#include <asm/hardware.h> 25#include <asm/hardware.h>
15#include <asm/hardware/sa1111.h> 26#include <asm/hardware/sa1111.h>
16#include <asm/irq.h> 27#include <asm/irq.h>
17#include <asm/mach-types.h> 28#include <asm/mach-types.h>
18#include <asm/setup.h> 29#include <asm/setup.h>
19
20#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
21#include <asm/mach/flash.h> 31#include <asm/mach/flash.h>
22#include <asm/mach/map.h> 32#include <asm/mach/map.h>
@@ -24,13 +34,170 @@
24 34
25#include "generic.h" 35#include "generic.h"
26 36
37/*
38 * HP Documentation referred in this file:
39 * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
40 */
41
42/* line 110 of HP's doc */
43#define TUCR_VAL 0x20000400
44
45/* memory space (line 52 of HP's doc) */
46#define SA1111REGSTART 0x40000000
47#define SA1111REGLEN 0x00001fff
48#define EPSONREGSTART 0x48000000
49#define EPSONREGLEN 0x00100000
50#define EPSONFBSTART 0x48200000
51/* 512kB framebuffer */
52#define EPSONFBLEN 512*1024
53
54static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
55 /* line 344 of HP's doc */
56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
64 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x01}, // MediaPlug Clock Configuration Register
66 {0x001E,0x01}, // CPU To Memory Wait State Select Register
67 {0x0020,0x00}, // Memory Configuration Register
68 {0x0021,0x45}, // DRAM Refresh Rate Register
69 {0x002A,0x01}, // DRAM Timings Control Register 0
70 {0x002B,0x03}, // DRAM Timings Control Register 1
71 {0x0030,0x1c}, // Panel Type Register
72 {0x0031,0x00}, // MOD Rate Register
73 {0x0032,0x4F}, // LCD Horizontal Display Width Register
74 {0x0034,0x07}, // LCD Horizontal Non-Display Period Register
75 {0x0035,0x01}, // TFT FPLINE Start Position Register
76 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
77 {0x0038,0xEF}, // LCD Vertical Display Height Register 0
78 {0x0039,0x00}, // LCD Vertical Display Height Register 1
79 {0x003A,0x13}, // LCD Vertical Non-Display Period Register
80 {0x003B,0x0B}, // TFT FPFRAME Start Position Register
81 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
82 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
83 {0x0041,0x00}, // LCD Miscellaneous Register
84 {0x0042,0x00}, // LCD Display Start Address Register 0
85 {0x0043,0x00}, // LCD Display Start Address Register 1
86 {0x0044,0x00}, // LCD Display Start Address Register 2
87 {0x0046,0x80}, // LCD Memory Address Offset Register 0
88 {0x0047,0x02}, // LCD Memory Address Offset Register 1
89 {0x0048,0x00}, // LCD Pixel Panning Register
90 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
91 {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
92 {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
93 {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
94 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
95 {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
96 {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
97 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
98 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
99 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
100 {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
101 {0x005B,0x10}, // TV Output Control Register
102 {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
103 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
104 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
105 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
106 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
107 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
108 {0x0068,0x00}, // CRT/TV Pixel Panning Register
109 {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
110 {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
111 {0x0070,0x00}, // LCD Ink/Cursor Control Register
112 {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
113 {0x0072,0x00}, // LCD Cursor X Position Register 0
114 {0x0073,0x00}, // LCD Cursor X Position Register 1
115 {0x0074,0x00}, // LCD Cursor Y Position Register 0
116 {0x0075,0x00}, // LCD Cursor Y Position Register 1
117 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
118 {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
119 {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
120 {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
121 {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
122 {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
123 {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
124 {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
125 {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
126 {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
127 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
128 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
129 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
130 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
131 {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
132 {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
133 {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
134 {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
135 {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
136 {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
137 {0x0100,0x00}, // BitBlt Control Register 0
138 {0x0101,0x00}, // BitBlt Control Register 1
139 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
140 {0x0103,0x00}, // BitBlt Operation Register
141 {0x0104,0x00}, // BitBlt Source Start Address Register 0
142 {0x0105,0x00}, // BitBlt Source Start Address Register 1
143 {0x0106,0x00}, // BitBlt Source Start Address Register 2
144 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
145 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
146 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
147 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
148 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
149 {0x0110,0x00}, // BitBlt Width Register 0
150 {0x0111,0x00}, // BitBlt Width Register 1
151 {0x0112,0x00}, // BitBlt Height Register 0
152 {0x0113,0x00}, // BitBlt Height Register 1
153 {0x0114,0x00}, // BitBlt Background Color Register 0
154 {0x0115,0x00}, // BitBlt Background Color Register 1
155 {0x0118,0x00}, // BitBlt Foreground Color Register 0
156 {0x0119,0x00}, // BitBlt Foreground Color Register 1
157 {0x01E0,0x00}, // Look-Up Table Mode Register
158 {0x01E2,0x00}, // Look-Up Table Address Register
159 /* not sure, wouldn't like to mess with the driver */
160 {0x01E4,0x00}, // Look-Up Table Data Register
161 /* jornada doc says 0x00, but I trust the driver */
162 {0x01F0,0x10}, // Power Save Configuration Register
163 {0x01F1,0x00}, // Power Save Status Register
164 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
165 {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
166};
167
168static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
169 .initregs = s1d13xxxfb_initregs,
170 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
171 .platform_init_video = NULL
172};
27 173
28#define JORTUCR_VAL 0x20000400 174static struct resource s1d13xxxfb_resources[] = {
175 [0] = {
176 .start = EPSONFBSTART,
177 .end = EPSONFBSTART + EPSONFBLEN,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = EPSONREGSTART,
182 .end = EPSONREGSTART + EPSONREGLEN,
183 .flags = IORESOURCE_MEM,
184 }
185};
186
187static struct platform_device s1d13xxxfb_device = {
188 .name = S1D_DEVICENAME,
189 .id = 0,
190 .dev = {
191 .platform_data = &s1d13xxxfb_data,
192 },
193 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
194 .resource = s1d13xxxfb_resources,
195};
29 196
30static struct resource sa1111_resources[] = { 197static struct resource sa1111_resources[] = {
31 [0] = { 198 [0] = {
32 .start = 0x40000000, 199 .start = SA1111REGSTART,
33 .end = 0x40001fff, 200 .end = SA1111REGSTART + SA1111REGLEN,
34 .flags = IORESOURCE_MEM, 201 .flags = IORESOURCE_MEM,
35 }, 202 },
36 [1] = { 203 [1] = {
@@ -53,18 +220,32 @@ static struct platform_device sa1111_device = {
53 .resource = sa1111_resources, 220 .resource = sa1111_resources,
54}; 221};
55 222
223static struct platform_device jornada720_mcu_device = {
224 .name = "jornada720_mcu",
225 .id = -1,
226};
227
56static struct platform_device *devices[] __initdata = { 228static struct platform_device *devices[] __initdata = {
57 &sa1111_device, 229 &sa1111_device,
230 &jornada720_mcu_device,
231 &s1d13xxxfb_device,
58}; 232};
59 233
234/* a stub for now, we theoretically cannot suspend without a flashboard */
235int pm_suspend(suspend_state_t state)
236{
237 return -1;
238}
239
60static int __init jornada720_init(void) 240static int __init jornada720_init(void)
61{ 241{
62 int ret = -ENODEV; 242 int ret = -ENODEV;
63 243
64 if (machine_is_jornada720()) { 244 if (machine_is_jornada720()) {
65 GPDR |= GPIO_GPIO20; 245 GPDR |= GPIO_GPIO20;
66 TUCR = JORTUCR_VAL; /* set the oscillator out to the SA-1101 */ 246 /* oscillator setup (line 116 of HP's doc) */
67 247 TUCR = TUCR_VAL;
248 /* resetting SA1111 (line 118 of HP's doc) */
68 GPSR = GPIO_GPIO20; 249 GPSR = GPIO_GPIO20;
69 udelay(1); 250 udelay(1);
70 GPCR = GPIO_GPIO20; 251 GPCR = GPIO_GPIO20;
@@ -72,10 +253,6 @@ static int __init jornada720_init(void)
72 GPSR = GPIO_GPIO20; 253 GPSR = GPIO_GPIO20;
73 udelay(20); 254 udelay(20);
74 255
75 /* LDD4 is speaker, LDD3 is microphone */
76 PPSR &= ~(PPC_LDD3 | PPC_LDD4);
77 PPDR |= PPC_LDD3 | PPC_LDD4;
78
79 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 256 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
80 } 257 }
81 return ret; 258 return ret;
@@ -85,19 +262,19 @@ arch_initcall(jornada720_init);
85 262
86static struct map_desc jornada720_io_desc[] __initdata = { 263static struct map_desc jornada720_io_desc[] __initdata = {
87 { /* Epson registers */ 264 { /* Epson registers */
88 .virtual = 0xf0000000, 265 .virtual = 0xf0000000,
89 .pfn = __phys_to_pfn(0x48000000), 266 .pfn = __phys_to_pfn(EPSONREGSTART),
90 .length = 0x00100000, 267 .length = EPSONREGLEN,
91 .type = MT_DEVICE 268 .type = MT_DEVICE
92 }, { /* Epson frame buffer */ 269 }, { /* Epson frame buffer */
93 .virtual = 0xf1000000, 270 .virtual = 0xf1000000,
94 .pfn = __phys_to_pfn(0x48200000), 271 .pfn = __phys_to_pfn(EPSONFBSTART),
95 .length = 0x00100000, 272 .length = EPSONFBLEN,
96 .type = MT_DEVICE 273 .type = MT_DEVICE
97 }, { /* SA-1111 */ 274 }, { /* SA-1111 */
98 .virtual = 0xf4000000, 275 .virtual = 0xf4000000,
99 .pfn = __phys_to_pfn(0x40000000), 276 .pfn = __phys_to_pfn(SA1111REGSTART),
100 .length = 0x00100000, 277 .length = SA1111REGLEN,
101 .type = MT_DEVICE 278 .type = MT_DEVICE
102 } 279 }
103}; 280};
@@ -106,7 +283,7 @@ static void __init jornada720_map_io(void)
106{ 283{
107 sa1100_map_io(); 284 sa1100_map_io();
108 iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc)); 285 iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
109 286
110 sa1100_register_uart(0, 3); 287 sa1100_register_uart(0, 3);
111 sa1100_register_uart(1, 1); 288 sa1100_register_uart(1, 1);
112} 289}
@@ -116,7 +293,7 @@ static struct mtd_partition jornada720_partitions[] = {
116 .name = "JORNADA720 boot firmware", 293 .name = "JORNADA720 boot firmware",
117 .size = 0x00040000, 294 .size = 0x00040000,
118 .offset = 0, 295 .offset = 0,
119 .mask_flags = MTD_WRITEABLE, /* force read-only */ 296 .mask_flags = MTD_WRITEABLE, /* force read-only */
120 }, { 297 }, {
121 .name = "JORNADA720 kernel", 298 .name = "JORNADA720 kernel",
122 .size = 0x000c0000, 299 .size = 0x000c0000,
@@ -139,7 +316,7 @@ static struct mtd_partition jornada720_partitions[] = {
139 .offset = 0x00540000, 316 .offset = 0x00540000,
140 }, { 317 }, {
141 .name = "JORNADA720 usr local", 318 .name = "JORNADA720 usr local",
142 .size = 0, /* will expand to the end of the flash */ 319 .size = 0, /* will expand to the end of the flash */
143 .offset = 0x00d00000, 320 .offset = 0x00d00000,
144 } 321 }
145}; 322};
@@ -147,10 +324,12 @@ static struct mtd_partition jornada720_partitions[] = {
147static void jornada720_set_vpp(int vpp) 324static void jornada720_set_vpp(int vpp)
148{ 325{
149 if (vpp) 326 if (vpp)
150 PPSR |= 0x80; 327 /* enabling flash write (line 470 of HP's doc) */
328 PPSR |= PPC_LDD7;
151 else 329 else
152 PPSR &= ~0x80; 330 /* disabling flash write (line 470 of HP's doc) */
153 PPDR |= 0x80; 331 PPSR &= ~PPC_LDD7;
332 PPDR |= PPC_LDD7;
154} 333}
155 334
156static struct flash_platform_data jornada720_flash_data = { 335static struct flash_platform_data jornada720_flash_data = {
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 354d5e91da59..075d4d1d63be 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -29,12 +29,12 @@
29 * is rather unfortunate. 29 * is rather unfortunate.
30 */ 30 */
31static void 31static void
32neponset_irq_handler(unsigned int irq, struct irqdesc *desc) 32neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
33{ 33{
34 unsigned int irr; 34 unsigned int irr;
35 35
36 while (1) { 36 while (1) {
37 struct irqdesc *d; 37 struct irq_desc *d;
38 38
39 /* 39 /*
40 * Acknowledge the parent IRQ. 40 * Acknowledge the parent IRQ.
@@ -168,9 +168,9 @@ static int neponset_probe(struct platform_device *dev)
168 * Setup other Neponset IRQs. SA1111 will be done by the 168 * Setup other Neponset IRQs. SA1111 will be done by the
169 * generic SA1111 code. 169 * generic SA1111 code.
170 */ 170 */
171 set_irq_handler(IRQ_NEPONSET_SMC9196, do_simple_IRQ); 171 set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
172 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); 172 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
173 set_irq_handler(IRQ_NEPONSET_USAR, do_simple_IRQ); 173 set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
174 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); 174 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
175 175
176 /* 176 /*
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 4284bd6f7a1f..29c89f9eb2ce 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -118,6 +118,7 @@ static struct irqaction sa1100_timer_irq = {
118static void __init sa1100_timer_init(void) 118static void __init sa1100_timer_init(void)
119{ 119{
120 struct timespec tv; 120 struct timespec tv;
121 unsigned long flags;
121 122
122 set_rtc = sa1100_set_rtc; 123 set_rtc = sa1100_set_rtc;
123 124
@@ -126,12 +127,12 @@ static void __init sa1100_timer_init(void)
126 do_settimeofday(&tv); 127 do_settimeofday(&tv);
127 128
128 OIER = 0; /* disable any timer interrupts */ 129 OIER = 0; /* disable any timer interrupts */
129 OSCR = LATCH*2; /* push OSCR out of the way */
130 OSMR0 = LATCH; /* set initial match */
131 OSSR = 0xf; /* clear status on all timers */ 130 OSSR = 0xf; /* clear status on all timers */
132 setup_irq(IRQ_OST0, &sa1100_timer_irq); 131 setup_irq(IRQ_OST0, &sa1100_timer_irq);
132 local_irq_save(flags);
133 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ 133 OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
134 OSCR = 0; /* initialize free-running timer */ 134 OSMR0 = OSCR + LATCH; /* set initial match */
135 local_irq_restore(flags);
135} 136}
136 137
137#ifdef CONFIG_NO_IDLE_HZ 138#ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 297ecf130650..00a6c1466867 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -82,7 +82,7 @@ void __init shark_init_irq(void)
82 82
83 for (irq = 0; irq < NR_IRQS; irq++) { 83 for (irq = 0; irq < NR_IRQS; irq++) {
84 set_irq_chip(irq, &fb_chip); 84 set_irq_chip(irq, &fb_chip);
85 set_irq_handler(irq, do_edge_IRQ); 85 set_irq_handler(irq, handle_edge_irq);
86 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 86 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
87 } 87 }
88 88
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3b8576111c16..bf71507c76fd 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -27,6 +27,7 @@
27#include <linux/amba/bus.h> 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h> 28#include <linux/amba/clcd.h>
29 29
30#include <asm/cnt32_to_63.h>
30#include <asm/system.h> 31#include <asm/system.h>
31#include <asm/hardware.h> 32#include <asm/hardware.h>
32#include <asm/io.h> 33#include <asm/io.h>
@@ -77,7 +78,7 @@ static struct irq_chip sic_chip = {
77}; 78};
78 79
79static void 80static void
80sic_handle_irq(unsigned int irq, struct irqdesc *desc) 81sic_handle_irq(unsigned int irq, struct irq_desc *desc)
81{ 82{
82 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS); 83 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
83 84
@@ -123,7 +124,7 @@ void __init versatile_init_irq(void)
123 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { 124 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
124 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) { 125 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
125 set_irq_chip(i, &sic_chip); 126 set_irq_chip(i, &sic_chip);
126 set_irq_handler(i, do_level_IRQ); 127 set_irq_handler(i, handle_level_irq);
127 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 128 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
128 } 129 }
129 } 130 }
@@ -228,14 +229,19 @@ void __init versatile_map_io(void)
228 229
229/* 230/*
230 * This is the Versatile sched_clock implementation. This has 231 * This is the Versatile sched_clock implementation. This has
231 * a resolution of 41.7ns, and a maximum value of about 179s. 232 * a resolution of 41.7ns, and a maximum value of about 35583 days.
233 *
234 * The return value is guaranteed to be monotonic in that range as
235 * long as there is always less than 89 seconds between successive
236 * calls to this function.
232 */ 237 */
233unsigned long long sched_clock(void) 238unsigned long long sched_clock(void)
234{ 239{
235 unsigned long long v; 240 unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
236 241
237 v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125; 242 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
238 do_div(v, 3); 243 v *= 125<<1;
244 do_div(v, 3<<1);
239 245
240 return v; 246 return v;
241} 247}
@@ -319,6 +325,19 @@ static struct platform_device smc91x_device = {
319 .resource = smc91x_resources, 325 .resource = smc91x_resources,
320}; 326};
321 327
328static struct resource versatile_i2c_resource = {
329 .start = VERSATILE_I2C_BASE,
330 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
331 .flags = IORESOURCE_MEM,
332};
333
334static struct platform_device versatile_i2c_device = {
335 .name = "versatile-i2c",
336 .id = -1,
337 .num_resources = 1,
338 .resource = &versatile_i2c_resource,
339};
340
322#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) 341#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
323 342
324unsigned int mmc_status(struct device *dev) 343unsigned int mmc_status(struct device *dev)
@@ -769,6 +788,7 @@ void __init versatile_init(void)
769 clk_register(&versatile_clcd_clk); 788 clk_register(&versatile_clcd_clk);
770 789
771 platform_device_register(&versatile_flash_device); 790 platform_device_register(&versatile_flash_device);
791 platform_device_register(&versatile_i2c_device);
772 platform_device_register(&smc91x_device); 792 platform_device_register(&smc91x_device);
773 793
774 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 794 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 503725b166fc..be439bb9d450 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -81,22 +81,18 @@ static struct amba_device *amba_devs[] __initdata = {
81 &mmc1_device, 81 &mmc1_device,
82}; 82};
83 83
84static int __init versatile_pb_init(void) 84static void __init versatile_pb_init(void)
85{ 85{
86 int i; 86 int i;
87 87
88 if (machine_is_versatile_pb()) { 88 versatile_init();
89 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
90 struct amba_device *d = amba_devs[i];
91 amba_device_register(d, &iomem_resource);
92 }
93 }
94 89
95 return 0; 90 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
91 struct amba_device *d = amba_devs[i];
92 amba_device_register(d, &iomem_resource);
93 }
96} 94}
97 95
98arch_initcall(versatile_pb_init);
99
100MACHINE_START(VERSATILE_PB, "ARM-Versatile PB") 96MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
101 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 97 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
102 .phys_io = 0x101f1000, 98 .phys_io = 0x101f1000,
@@ -105,5 +101,5 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
105 .map_io = versatile_map_io, 101 .map_io = versatile_map_io,
106 .init_irq = versatile_init_irq, 102 .init_irq = versatile_init_irq,
107 .timer = &versatile_timer, 103 .timer = &versatile_timer,
108 .init_machine = versatile_init, 104 .init_machine = versatile_pb_init,
109MACHINE_END 105MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c0bfb8212b77..aade2f72c920 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -197,7 +197,7 @@ config CPU_ARM940T
197 select CPU_CP15_MPU 197 select CPU_CP15_MPU
198 help 198 help
199 ARM940T is a member of the ARM9TDMI family of general- 199 ARM940T is a member of the ARM9TDMI family of general-
200 purpose microprocessors with MPU and seperate 4KB 200 purpose microprocessors with MPU and separate 4KB
201 instruction and 4KB data cases, each with a 4-word line 201 instruction and 4KB data cases, each with a 4-word line
202 length. 202 length.
203 203
@@ -333,7 +333,7 @@ config CPU_XSCALE
333# XScale Core Version 3 333# XScale Core Version 3
334config CPU_XSC3 334config CPU_XSC3
335 bool 335 bool
336 depends on ARCH_IXP23XX 336 depends on ARCH_IXP23XX || ARCH_IOP13XX
337 default y 337 default y
338 select CPU_32v5 338 select CPU_32v5
339 select CPU_ABRT_EV5T 339 select CPU_ABRT_EV5T
@@ -580,7 +580,7 @@ config CPU_CACHE_ROUND_ROBIN
580 580
581config CPU_BPREDICT_DISABLE 581config CPU_BPREDICT_DISABLE
582 bool "Disable branch prediction" 582 bool "Disable branch prediction"
583 depends on CPU_ARM1020 || CPU_V6 583 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
584 help 584 help
585 Say Y here to disable branch prediction. If unsure, say N. 585 Say Y here to disable branch prediction. If unsure, say N.
586 586
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
index b797217e82be..6a9c362fef5e 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/consistent.c
@@ -238,7 +238,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
238 * x86 does not mark the pages reserved... 238 * x86 does not mark the pages reserved...
239 */ 239 */
240 SetPageReserved(page); 240 SetPageReserved(page);
241 set_pte(pte, mk_pte(page, prot)); 241 set_pte_ext(pte, mk_pte(page, prot), 0);
242 page++; 242 page++;
243 pte++; 243 pte++;
244 off++; 244 off++;
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index df1645e14b4c..408b05ae6b9b 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -71,7 +71,7 @@ void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
71{ 71{
72 spin_lock(&minicache_lock); 72 spin_lock(&minicache_lock);
73 73
74 set_pte(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); 74 set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
75 flush_tlb_kernel_page(0xffff8000); 75 flush_tlb_kernel_page(0xffff8000);
76 76
77 mc_copy_user_page((void *)0xffff8000, kto); 77 mc_copy_user_page((void *)0xffff8000, kto);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 3d0d3a963d20..865777dec161 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -70,8 +70,8 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo
70 */ 70 */
71 spin_lock(&v6_lock); 71 spin_lock(&v6_lock);
72 72
73 set_pte(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL)); 73 set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL), 0);
74 set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL)); 74 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL), 0);
75 75
76 from = from_address + (offset << PAGE_SHIFT); 76 from = from_address + (offset << PAGE_SHIFT);
77 to = to_address + (offset << PAGE_SHIFT); 77 to = to_address + (offset << PAGE_SHIFT);
@@ -110,7 +110,7 @@ static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
110 */ 110 */
111 spin_lock(&v6_lock); 111 spin_lock(&v6_lock);
112 112
113 set_pte(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL)); 113 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL), 0);
114 flush_tlb_kernel_page(to); 114 flush_tlb_kernel_page(to);
115 clear_page((void *)to); 115 clear_page((void *)to);
116 116
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 84ebe0aa379e..aea5da723596 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -93,7 +93,7 @@ void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
93{ 93{
94 spin_lock(&minicache_lock); 94 spin_lock(&minicache_lock);
95 95
96 set_pte(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); 96 set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
97 flush_tlb_kernel_page(COPYPAGE_MINICACHE); 97 flush_tlb_kernel_page(COPYPAGE_MINICACHE);
98 98
99 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); 99 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 7fc1b35a6746..cf95c5d0ce4c 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -61,7 +61,7 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
61 if (pte_present(entry) && pte_val(entry) & shared_pte_mask) { 61 if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
62 flush_cache_page(vma, address, pte_pfn(entry)); 62 flush_cache_page(vma, address, pte_pfn(entry));
63 pte_val(entry) &= ~shared_pte_mask; 63 pte_val(entry) &= ~shared_pte_mask;
64 set_pte(pte, entry); 64 set_pte_at(vma->vm_mm, address, pte, entry);
65 flush_tlb_page(vma, address); 65 flush_tlb_page(vma, address);
66 ret = 1; 66 ret = 1;
67 } 67 }
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5e658a874498..9fd6d2eafb40 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -230,7 +230,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
230 * If we're in an interrupt or have no user 230 * If we're in an interrupt or have no user
231 * context, we must not take the fault.. 231 * context, we must not take the fault..
232 */ 232 */
233 if (in_interrupt() || !mm) 233 if (in_atomic() || !mm)
234 goto no_context; 234 goto no_context;
235 235
236 /* 236 /*
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 454205b789d5..628348c9f6c5 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -26,7 +26,7 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
26 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); 26 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
27 const int zero = 0; 27 const int zero = 0;
28 28
29 set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); 29 set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0);
30 flush_tlb_kernel_page(to); 30 flush_tlb_kernel_page(to);
31 31
32 asm( "mcrr p15, 0, %1, %0, c14\n" 32 asm( "mcrr p15, 0, %1, %0, c14\n"
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 465440592791..3bb3951920bc 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -38,89 +38,71 @@
38 */ 38 */
39#define VM_ARM_SECTION_MAPPING 0x80000000 39#define VM_ARM_SECTION_MAPPING 0x80000000
40 40
41static inline void 41static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
42remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, 42 unsigned long phys_addr, pgprot_t prot)
43 unsigned long phys_addr, pgprot_t pgprot)
44{ 43{
45 unsigned long end; 44 pte_t *pte;
45
46 pte = pte_alloc_kernel(pmd, addr);
47 if (!pte)
48 return -ENOMEM;
46 49
47 address &= ~PMD_MASK;
48 end = address + size;
49 if (end > PMD_SIZE)
50 end = PMD_SIZE;
51 BUG_ON(address >= end);
52 do { 50 do {
53 if (!pte_none(*pte)) 51 if (!pte_none(*pte))
54 goto bad; 52 goto bad;
55 53
56 set_pte(pte, pfn_pte(phys_addr >> PAGE_SHIFT, pgprot)); 54 set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
57 address += PAGE_SIZE;
58 phys_addr += PAGE_SIZE; 55 phys_addr += PAGE_SIZE;
59 pte++; 56 } while (pte++, addr += PAGE_SIZE, addr != end);
60 } while (address && (address < end)); 57 return 0;
61 return;
62 58
63 bad: 59 bad:
64 printk("remap_area_pte: page already exists\n"); 60 printk(KERN_CRIT "remap_area_pte: page already exists\n");
65 BUG(); 61 BUG();
66} 62}
67 63
68static inline int 64static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
69remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size, 65 unsigned long end, unsigned long phys_addr,
70 unsigned long phys_addr, unsigned long flags) 66 pgprot_t prot)
71{ 67{
72 unsigned long end; 68 unsigned long next;
73 pgprot_t pgprot; 69 pmd_t *pmd;
74 70 int ret = 0;
75 address &= ~PGDIR_MASK;
76 end = address + size;
77 71
78 if (end > PGDIR_SIZE) 72 pmd = pmd_alloc(&init_mm, pgd, addr);
79 end = PGDIR_SIZE; 73 if (!pmd)
74 return -ENOMEM;
80 75
81 phys_addr -= address;
82 BUG_ON(address >= end);
83
84 pgprot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_WRITE | flags);
85 do { 76 do {
86 pte_t * pte = pte_alloc_kernel(pmd, address); 77 next = pmd_addr_end(addr, end);
87 if (!pte) 78 ret = remap_area_pte(pmd, addr, next, phys_addr, prot);
88 return -ENOMEM; 79 if (ret)
89 remap_area_pte(pte, address, end - address, address + phys_addr, pgprot); 80 return ret;
90 address = (address + PMD_SIZE) & PMD_MASK; 81 phys_addr += next - addr;
91 pmd++; 82 } while (pmd++, addr = next, addr != end);
92 } while (address && (address < end)); 83 return ret;
93 return 0;
94} 84}
95 85
96static int 86static int remap_area_pages(unsigned long start, unsigned long pfn,
97remap_area_pages(unsigned long start, unsigned long pfn, 87 unsigned long size, unsigned long flags)
98 unsigned long size, unsigned long flags)
99{ 88{
100 unsigned long address = start; 89 unsigned long addr = start;
101 unsigned long end = start + size; 90 unsigned long next, end = start + size;
102 unsigned long phys_addr = __pfn_to_phys(pfn); 91 unsigned long phys_addr = __pfn_to_phys(pfn);
92 pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
93 L_PTE_DIRTY | L_PTE_WRITE | flags);
94 pgd_t *pgd;
103 int err = 0; 95 int err = 0;
104 pgd_t * dir;
105 96
106 phys_addr -= address; 97 BUG_ON(addr >= end);
107 dir = pgd_offset(&init_mm, address); 98 pgd = pgd_offset_k(addr);
108 BUG_ON(address >= end);
109 do { 99 do {
110 pmd_t *pmd = pmd_alloc(&init_mm, dir, address); 100 next = pgd_addr_end(addr, end);
111 if (!pmd) { 101 err = remap_area_pmd(pgd, addr, next, phys_addr, prot);
112 err = -ENOMEM; 102 if (err)
113 break;
114 }
115 if (remap_area_pmd(pmd, address, end - address,
116 phys_addr + address, flags)) {
117 err = -ENOMEM;
118 break; 103 break;
119 } 104 phys_addr += next - addr;
120 105 } while (pgd++, addr = next, addr != end);
121 address = (address + PGDIR_SIZE) & PGDIR_MASK;
122 dir++;
123 } while (address && (address < end));
124 106
125 return err; 107 return err;
126} 108}
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index bb2bc9ab6bd3..a44e30970635 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -1,4 +1,7 @@
1/* the upper-most page table pointer */ 1/* the upper-most page table pointer */
2
3#ifdef CONFIG_MMU
4
2extern pmd_t *top_pmd; 5extern pmd_t *top_pmd;
3 6
4#define TOP_PTE(x) pte_offset_kernel(top_pmd, x) 7#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
@@ -13,6 +16,8 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
13 return pmd_off(pgd_offset_k(virt), virt); 16 return pmd_off(pgd_offset_k(virt), virt);
14} 17}
15 18
19#endif
20
16struct map_desc; 21struct map_desc;
17struct meminfo; 22struct meminfo;
18struct pglist_data; 23struct pglist_data;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f866bf6b97d4..f028aef9a861 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -265,7 +265,7 @@ static void __init build_mem_type_table(void)
265 if (arch_is_coherent()) { 265 if (arch_is_coherent()) {
266 if (cpu_is_xsc3()) { 266 if (cpu_is_xsc3()) {
267 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 267 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
268 mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT; 268 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
269 } 269 }
270 } 270 }
271 271
@@ -294,12 +294,6 @@ static void __init build_mem_type_table(void)
294 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE; 294 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
295 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 295 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
296 296
297 /*
298 * User pages need to be mapped with the ASID
299 * (iow, non-global)
300 */
301 user_pgprot |= L_PTE_ASID;
302
303#ifdef CONFIG_SMP 297#ifdef CONFIG_SMP
304 /* 298 /*
305 * Mark memory with the "shared" attribute for SMP systems 299 * Mark memory with the "shared" attribute for SMP systems
@@ -408,7 +402,7 @@ alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pg
408 } 402 }
409 ptep = pte_offset_kernel(pmdp, virt); 403 ptep = pte_offset_kernel(pmdp, virt);
410 404
411 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot)); 405 set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0);
412} 406}
413 407
414/* 408/*
@@ -619,6 +613,13 @@ void __init reserve_node_zero(pg_data_t *pgdat)
619 if (machine_is_p720t()) 613 if (machine_is_p720t())
620 res_size = 0x00014000; 614 res_size = 0x00014000;
621 615
616 /* H1940 and RX3715 need to reserve this for suspend */
617
618 if (machine_is_h1940() || machine_is_rx3715()) {
619 reserve_bootmem_node(pgdat, 0x30003000, 0x1000);
620 reserve_bootmem_node(pgdat, 0x30081000, 0x1000);
621 }
622
622#ifdef CONFIG_SA1111 623#ifdef CONFIG_SA1111
623 /* 624 /*
624 * Because of the SA1111 DMA bug, we want to preserve our 625 * Because of the SA1111 DMA bug, we want to preserve our
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d0e66424a597..05818fc0c705 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -6,10 +6,12 @@
6#include <linux/module.h> 6#include <linux/module.h>
7#include <linux/mm.h> 7#include <linux/mm.h>
8#include <linux/pagemap.h> 8#include <linux/pagemap.h>
9#include <linux/bootmem.h>
9 10
10#include <asm/cacheflush.h> 11#include <asm/cacheflush.h>
11#include <asm/io.h> 12#include <asm/io.h>
12#include <asm/page.h> 13#include <asm/page.h>
14#include <asm/mach/arch.h>
13 15
14#include "mm.h" 16#include "mm.h"
15 17
@@ -76,7 +78,7 @@ void __iomem *__ioremap(unsigned long phys_addr, size_t size,
76} 78}
77EXPORT_SYMBOL(__ioremap); 79EXPORT_SYMBOL(__ioremap);
78 80
79void __iounmap(void __iomem *addr) 81void __iounmap(volatile void __iomem *addr)
80{ 82{
81} 83}
82EXPORT_SYMBOL(__iounmap); 84EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index 20c1b0df75f2..50b9aed6000d 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -57,7 +57,7 @@ pgd_t *get_pgd_slow(struct mm_struct *mm)
57 57
58 init_pmd = pmd_offset(init_pgd, 0); 58 init_pmd = pmd_offset(init_pgd, 0);
59 init_pte = pte_offset_map_nested(init_pmd, 0); 59 init_pte = pte_offset_map_nested(init_pmd, 0);
60 set_pte(new_pte, *init_pte); 60 set_pte_ext(new_pte, *init_pte, 0);
61 pte_unmap_nested(init_pte); 61 pte_unmap_nested(init_pte);
62 pte_unmap(new_pte); 62 pte_unmap(new_pte);
63 } 63 }
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 1d8316f3cecf..700c04d6996e 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,9 +29,9 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/elf.h>
32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/procinfo.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36 36
37#include "proc-macros.S" 37#include "proc-macros.S"
@@ -397,7 +397,7 @@ ENTRY(cpu_arm1020_switch_mm)
397 * Set a PTE and flush it out 397 * Set a PTE and flush it out
398 */ 398 */
399 .align 5 399 .align 5
400ENTRY(cpu_arm1020_set_pte) 400ENTRY(cpu_arm1020_set_pte_ext)
401#ifdef CONFIG_MMU 401#ifdef CONFIG_MMU
402 str r1, [r0], #-2048 @ linux version 402 str r1, [r0], #-2048 @ linux version
403 403
@@ -477,7 +477,7 @@ arm1020_processor_functions:
477 .word cpu_arm1020_do_idle 477 .word cpu_arm1020_do_idle
478 .word cpu_arm1020_dcache_clean_area 478 .word cpu_arm1020_dcache_clean_area
479 .word cpu_arm1020_switch_mm 479 .word cpu_arm1020_switch_mm
480 .word cpu_arm1020_set_pte 480 .word cpu_arm1020_set_pte_ext
481 .size arm1020_processor_functions, . - arm1020_processor_functions 481 .size arm1020_processor_functions, . - arm1020_processor_functions
482 482
483 .section ".rodata" 483 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 89b1d6d3d7c0..1cc206ab5eae 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,9 +29,9 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/elf.h>
32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/procinfo.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36 36
37#include "proc-macros.S" 37#include "proc-macros.S"
@@ -381,7 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm)
381 * Set a PTE and flush it out 381 * Set a PTE and flush it out
382 */ 382 */
383 .align 5 383 .align 5
384ENTRY(cpu_arm1020e_set_pte) 384ENTRY(cpu_arm1020e_set_pte_ext)
385#ifdef CONFIG_MMU 385#ifdef CONFIG_MMU
386 str r1, [r0], #-2048 @ linux version 386 str r1, [r0], #-2048 @ linux version
387 387
@@ -458,7 +458,7 @@ arm1020e_processor_functions:
458 .word cpu_arm1020e_do_idle 458 .word cpu_arm1020e_do_idle
459 .word cpu_arm1020e_dcache_clean_area 459 .word cpu_arm1020e_dcache_clean_area
460 .word cpu_arm1020e_switch_mm 460 .word cpu_arm1020e_switch_mm
461 .word cpu_arm1020e_set_pte 461 .word cpu_arm1020e_set_pte_ext
462 .size arm1020e_processor_functions, . - arm1020e_processor_functions 462 .size arm1020e_processor_functions, . - arm1020e_processor_functions
463 463
464 .section ".rodata" 464 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index a089528e6bce..aff0ea08e2f8 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,9 +18,9 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/elf.h>
21#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
22#include <asm/pgtable.h> 23#include <asm/pgtable.h>
23#include <asm/procinfo.h>
24#include <asm/ptrace.h> 24#include <asm/ptrace.h>
25 25
26#include "proc-macros.S" 26#include "proc-macros.S"
@@ -358,12 +358,12 @@ ENTRY(cpu_arm1022_switch_mm)
358 mov pc, lr 358 mov pc, lr
359 359
360/* 360/*
361 * cpu_arm1022_set_pte(ptep, pte) 361 * cpu_arm1022_set_pte_ext(ptep, pte, ext)
362 * 362 *
363 * Set a PTE and flush it out 363 * Set a PTE and flush it out
364 */ 364 */
365 .align 5 365 .align 5
366ENTRY(cpu_arm1022_set_pte) 366ENTRY(cpu_arm1022_set_pte_ext)
367#ifdef CONFIG_MMU 367#ifdef CONFIG_MMU
368 str r1, [r0], #-2048 @ linux version 368 str r1, [r0], #-2048 @ linux version
369 369
@@ -441,7 +441,7 @@ arm1022_processor_functions:
441 .word cpu_arm1022_do_idle 441 .word cpu_arm1022_do_idle
442 .word cpu_arm1022_dcache_clean_area 442 .word cpu_arm1022_dcache_clean_area
443 .word cpu_arm1022_switch_mm 443 .word cpu_arm1022_switch_mm
444 .word cpu_arm1022_set_pte 444 .word cpu_arm1022_set_pte_ext
445 .size arm1022_processor_functions, . - arm1022_processor_functions 445 .size arm1022_processor_functions, . - arm1022_processor_functions
446 446
447 .section ".rodata" 447 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index d6d84d92c7c7..65e43a109085 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,9 +18,9 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/elf.h>
21#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
22#include <asm/pgtable.h> 23#include <asm/pgtable.h>
23#include <asm/procinfo.h>
24#include <asm/ptrace.h> 24#include <asm/ptrace.h>
25 25
26#include "proc-macros.S" 26#include "proc-macros.S"
@@ -347,12 +347,12 @@ ENTRY(cpu_arm1026_switch_mm)
347 mov pc, lr 347 mov pc, lr
348 348
349/* 349/*
350 * cpu_arm1026_set_pte(ptep, pte) 350 * cpu_arm1026_set_pte_ext(ptep, pte, ext)
351 * 351 *
352 * Set a PTE and flush it out 352 * Set a PTE and flush it out
353 */ 353 */
354 .align 5 354 .align 5
355ENTRY(cpu_arm1026_set_pte) 355ENTRY(cpu_arm1026_set_pte_ext)
356#ifdef CONFIG_MMU 356#ifdef CONFIG_MMU
357 str r1, [r0], #-2048 @ linux version 357 str r1, [r0], #-2048 @ linux version
358 358
@@ -436,7 +436,7 @@ arm1026_processor_functions:
436 .word cpu_arm1026_do_idle 436 .word cpu_arm1026_do_idle
437 .word cpu_arm1026_dcache_clean_area 437 .word cpu_arm1026_dcache_clean_area
438 .word cpu_arm1026_switch_mm 438 .word cpu_arm1026_switch_mm
439 .word cpu_arm1026_set_pte 439 .word cpu_arm1026_set_pte_ext
440 .size arm1026_processor_functions, . - arm1026_processor_functions 440 .size arm1026_processor_functions, . - arm1026_processor_functions
441 441
442 .section .rodata 442 .section .rodata
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 0432e4806888..123a7dc7a433 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -15,9 +15,9 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <asm/assembler.h> 16#include <asm/assembler.h>
17#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
18#include <asm/elf.h>
18#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable-hwdef.h>
19#include <asm/pgtable.h> 20#include <asm/pgtable.h>
20#include <asm/procinfo.h>
21#include <asm/ptrace.h> 21#include <asm/ptrace.h>
22 22
23ENTRY(cpu_arm6_dcache_clean_area) 23ENTRY(cpu_arm6_dcache_clean_area)
@@ -209,14 +209,14 @@ ENTRY(cpu_arm7_switch_mm)
209 mov pc, lr 209 mov pc, lr
210 210
211/* 211/*
212 * Function: arm6_7_set_pte(pte_t *ptep, pte_t pte) 212 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
213 * Params : r0 = Address to set 213 * Params : r0 = Address to set
214 * : r1 = value to set 214 * : r1 = value to set
215 * Purpose : Set a PTE and flush it out of any WB cache 215 * Purpose : Set a PTE and flush it out of any WB cache
216 */ 216 */
217 .align 5 217 .align 5
218ENTRY(cpu_arm6_set_pte) 218ENTRY(cpu_arm6_set_pte_ext)
219ENTRY(cpu_arm7_set_pte) 219ENTRY(cpu_arm7_set_pte_ext)
220#ifdef CONFIG_MMU 220#ifdef CONFIG_MMU
221 str r1, [r0], #-2048 @ linux version 221 str r1, [r0], #-2048 @ linux version
222 222
@@ -299,7 +299,7 @@ ENTRY(arm6_processor_functions)
299 .word cpu_arm6_do_idle 299 .word cpu_arm6_do_idle
300 .word cpu_arm6_dcache_clean_area 300 .word cpu_arm6_dcache_clean_area
301 .word cpu_arm6_switch_mm 301 .word cpu_arm6_switch_mm
302 .word cpu_arm6_set_pte 302 .word cpu_arm6_set_pte_ext
303 .size arm6_processor_functions, . - arm6_processor_functions 303 .size arm6_processor_functions, . - arm6_processor_functions
304 304
305/* 305/*
@@ -315,7 +315,7 @@ ENTRY(arm7_processor_functions)
315 .word cpu_arm7_do_idle 315 .word cpu_arm7_do_idle
316 .word cpu_arm7_dcache_clean_area 316 .word cpu_arm7_dcache_clean_area
317 .word cpu_arm7_switch_mm 317 .word cpu_arm7_switch_mm
318 .word cpu_arm7_set_pte 318 .word cpu_arm7_set_pte_ext
319 .size arm7_processor_functions, . - arm7_processor_functions 319 .size arm7_processor_functions, . - arm7_processor_functions
320 320
321 .section ".rodata" 321 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index c2f0705bfd49..dc763be43362 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -36,9 +36,9 @@
36#include <linux/init.h> 36#include <linux/init.h>
37#include <asm/assembler.h> 37#include <asm/assembler.h>
38#include <asm/asm-offsets.h> 38#include <asm/asm-offsets.h>
39#include <asm/elf.h>
39#include <asm/pgtable-hwdef.h> 40#include <asm/pgtable-hwdef.h>
40#include <asm/pgtable.h> 41#include <asm/pgtable.h>
41#include <asm/procinfo.h>
42#include <asm/ptrace.h> 42#include <asm/ptrace.h>
43 43
44#include "proc-macros.S" 44#include "proc-macros.S"
@@ -88,13 +88,13 @@ ENTRY(cpu_arm720_switch_mm)
88 mov pc, lr 88 mov pc, lr
89 89
90/* 90/*
91 * Function: arm720_set_pte(pte_t *ptep, pte_t pte) 91 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
92 * Params : r0 = Address to set 92 * Params : r0 = Address to set
93 * : r1 = value to set 93 * : r1 = value to set
94 * Purpose : Set a PTE and flush it out of any WB cache 94 * Purpose : Set a PTE and flush it out of any WB cache
95 */ 95 */
96 .align 5 96 .align 5
97ENTRY(cpu_arm720_set_pte) 97ENTRY(cpu_arm720_set_pte_ext)
98#ifdef CONFIG_MMU 98#ifdef CONFIG_MMU
99 str r1, [r0], #-2048 @ linux version 99 str r1, [r0], #-2048 @ linux version
100 100
@@ -204,7 +204,7 @@ ENTRY(arm720_processor_functions)
204 .word cpu_arm720_do_idle 204 .word cpu_arm720_do_idle
205 .word cpu_arm720_dcache_clean_area 205 .word cpu_arm720_dcache_clean_area
206 .word cpu_arm720_switch_mm 206 .word cpu_arm720_switch_mm
207 .word cpu_arm720_set_pte 207 .word cpu_arm720_set_pte_ext
208 .size arm720_processor_functions, . - arm720_processor_functions 208 .size arm720_processor_functions, . - arm720_processor_functions
209 209
210 .section ".rodata" 210 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 40713818a87b..7069f495cf9b 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -12,9 +12,9 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h>
15#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h> 17#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19 19
20 .text 20 .text
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 22d7e3100ea6..d091c2571823 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -12,9 +12,9 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h>
15#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h> 17#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19 19
20 .text 20 .text
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 4adb46b3a4e0..75c945ed6c4d 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,9 +28,9 @@
28#include <linux/linkage.h> 28#include <linux/linkage.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/elf.h>
31#include <asm/pgtable-hwdef.h> 32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h>
34#include <asm/page.h> 34#include <asm/page.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36#include "proc-macros.S" 36#include "proc-macros.S"
@@ -344,12 +344,12 @@ ENTRY(cpu_arm920_switch_mm)
344 mov pc, lr 344 mov pc, lr
345 345
346/* 346/*
347 * cpu_arm920_set_pte(ptep, pte) 347 * cpu_arm920_set_pte(ptep, pte, ext)
348 * 348 *
349 * Set a PTE and flush it out 349 * Set a PTE and flush it out
350 */ 350 */
351 .align 5 351 .align 5
352ENTRY(cpu_arm920_set_pte) 352ENTRY(cpu_arm920_set_pte_ext)
353#ifdef CONFIG_MMU 353#ifdef CONFIG_MMU
354 str r1, [r0], #-2048 @ linux version 354 str r1, [r0], #-2048 @ linux version
355 355
@@ -423,7 +423,7 @@ arm920_processor_functions:
423 .word cpu_arm920_do_idle 423 .word cpu_arm920_do_idle
424 .word cpu_arm920_dcache_clean_area 424 .word cpu_arm920_dcache_clean_area
425 .word cpu_arm920_switch_mm 425 .word cpu_arm920_switch_mm
426 .word cpu_arm920_set_pte 426 .word cpu_arm920_set_pte_ext
427 .size arm920_processor_functions, . - arm920_processor_functions 427 .size arm920_processor_functions, . - arm920_processor_functions
428 428
429 .section ".rodata" 429 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 571f082f0247..ffb751b877ff 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,9 +29,9 @@
29#include <linux/linkage.h> 29#include <linux/linkage.h>
30#include <linux/init.h> 30#include <linux/init.h>
31#include <asm/assembler.h> 31#include <asm/assembler.h>
32#include <asm/elf.h>
32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/procinfo.h>
35#include <asm/page.h> 35#include <asm/page.h>
36#include <asm/ptrace.h> 36#include <asm/ptrace.h>
37#include "proc-macros.S" 37#include "proc-macros.S"
@@ -348,12 +348,12 @@ ENTRY(cpu_arm922_switch_mm)
348 mov pc, lr 348 mov pc, lr
349 349
350/* 350/*
351 * cpu_arm922_set_pte(ptep, pte) 351 * cpu_arm922_set_pte_ext(ptep, pte, ext)
352 * 352 *
353 * Set a PTE and flush it out 353 * Set a PTE and flush it out
354 */ 354 */
355 .align 5 355 .align 5
356ENTRY(cpu_arm922_set_pte) 356ENTRY(cpu_arm922_set_pte_ext)
357#ifdef CONFIG_MMU 357#ifdef CONFIG_MMU
358 str r1, [r0], #-2048 @ linux version 358 str r1, [r0], #-2048 @ linux version
359 359
@@ -427,7 +427,7 @@ arm922_processor_functions:
427 .word cpu_arm922_do_idle 427 .word cpu_arm922_do_idle
428 .word cpu_arm922_dcache_clean_area 428 .word cpu_arm922_dcache_clean_area
429 .word cpu_arm922_switch_mm 429 .word cpu_arm922_switch_mm
430 .word cpu_arm922_set_pte 430 .word cpu_arm922_set_pte_ext
431 .size arm922_processor_functions, . - arm922_processor_functions 431 .size arm922_processor_functions, . - arm922_processor_functions
432 432
433 .section ".rodata" 433 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 8d9a9f93b011..44c2c997819f 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -52,9 +52,9 @@
52#include <linux/linkage.h> 52#include <linux/linkage.h>
53#include <linux/init.h> 53#include <linux/init.h>
54#include <asm/assembler.h> 54#include <asm/assembler.h>
55#include <asm/elf.h>
55#include <asm/pgtable-hwdef.h> 56#include <asm/pgtable-hwdef.h>
56#include <asm/pgtable.h> 57#include <asm/pgtable.h>
57#include <asm/procinfo.h>
58#include <asm/page.h> 58#include <asm/page.h>
59#include <asm/ptrace.h> 59#include <asm/ptrace.h>
60#include "proc-macros.S" 60#include "proc-macros.S"
@@ -391,12 +391,12 @@ ENTRY(cpu_arm925_switch_mm)
391 mov pc, lr 391 mov pc, lr
392 392
393/* 393/*
394 * cpu_arm925_set_pte(ptep, pte) 394 * cpu_arm925_set_pte_ext(ptep, pte, ext)
395 * 395 *
396 * Set a PTE and flush it out 396 * Set a PTE and flush it out
397 */ 397 */
398 .align 5 398 .align 5
399ENTRY(cpu_arm925_set_pte) 399ENTRY(cpu_arm925_set_pte_ext)
400#ifdef CONFIG_MMU 400#ifdef CONFIG_MMU
401 str r1, [r0], #-2048 @ linux version 401 str r1, [r0], #-2048 @ linux version
402 402
@@ -490,7 +490,7 @@ arm925_processor_functions:
490 .word cpu_arm925_do_idle 490 .word cpu_arm925_do_idle
491 .word cpu_arm925_dcache_clean_area 491 .word cpu_arm925_dcache_clean_area
492 .word cpu_arm925_switch_mm 492 .word cpu_arm925_switch_mm
493 .word cpu_arm925_set_pte 493 .word cpu_arm925_set_pte_ext
494 .size arm925_processor_functions, . - arm925_processor_functions 494 .size arm925_processor_functions, . - arm925_processor_functions
495 495
496 .section ".rodata" 496 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 44a7a652d625..5b80b6bdd0cb 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,9 +28,9 @@
28#include <linux/linkage.h> 28#include <linux/linkage.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/elf.h>
31#include <asm/pgtable-hwdef.h> 32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h>
34#include <asm/page.h> 34#include <asm/page.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36#include "proc-macros.S" 36#include "proc-macros.S"
@@ -348,12 +348,12 @@ ENTRY(cpu_arm926_switch_mm)
348 mov pc, lr 348 mov pc, lr
349 349
350/* 350/*
351 * cpu_arm926_set_pte(ptep, pte) 351 * cpu_arm926_set_pte_ext(ptep, pte, ext)
352 * 352 *
353 * Set a PTE and flush it out 353 * Set a PTE and flush it out
354 */ 354 */
355 .align 5 355 .align 5
356ENTRY(cpu_arm926_set_pte) 356ENTRY(cpu_arm926_set_pte_ext)
357#ifdef CONFIG_MMU 357#ifdef CONFIG_MMU
358 str r1, [r0], #-2048 @ linux version 358 str r1, [r0], #-2048 @ linux version
359 359
@@ -439,7 +439,7 @@ arm926_processor_functions:
439 .word cpu_arm926_do_idle 439 .word cpu_arm926_do_idle
440 .word cpu_arm926_dcache_clean_area 440 .word cpu_arm926_dcache_clean_area
441 .word cpu_arm926_switch_mm 441 .word cpu_arm926_switch_mm
442 .word cpu_arm926_set_pte 442 .word cpu_arm926_set_pte_ext
443 .size arm926_processor_functions, . - arm926_processor_functions 443 .size arm926_processor_functions, . - arm926_processor_functions
444 444
445 .section ".rodata" 445 .section ".rodata"
@@ -480,7 +480,7 @@ __arm926_proc_info:
480 b __arm926_setup 480 b __arm926_setup
481 .long cpu_arch_name 481 .long cpu_arch_name
482 .long cpu_elf_name 482 .long cpu_elf_name
483 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA 483 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
484 .long cpu_arm926_name 484 .long cpu_arm926_name
485 .long arm926_processor_functions 485 .long arm926_processor_functions
486 .long v4wbi_tlb_fns 486 .long v4wbi_tlb_fns
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 2397f4b6e151..786c593778f0 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -11,9 +11,9 @@
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/elf.h>
14#include <asm/pgtable-hwdef.h> 15#include <asm/pgtable-hwdef.h>
15#include <asm/pgtable.h> 16#include <asm/pgtable.h>
16#include <asm/procinfo.h>
17#include <asm/ptrace.h> 17#include <asm/ptrace.h>
18 18
19/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */ 19/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index e18617564421..a60c1421d450 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -13,9 +13,9 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/assembler.h> 15#include <asm/assembler.h>
16#include <asm/elf.h>
16#include <asm/pgtable-hwdef.h> 17#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 18#include <asm/pgtable.h>
18#include <asm/procinfo.h>
19#include <asm/ptrace.h> 19#include <asm/ptrace.h>
20 20
21/* 21/*
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 918ebf65d4f6..4848eeac86b6 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -12,9 +12,9 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h>
15#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h> 17#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19 19
20 .text 20 .text
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c878064e9b88..6e226e12989f 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -17,7 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <asm/assembler.h> 18#include <asm/assembler.h>
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/procinfo.h> 20#include <asm/elf.h>
21#include <asm/hardware.h> 21#include <asm/hardware.h>
22#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
@@ -146,12 +146,12 @@ ENTRY(cpu_sa110_switch_mm)
146#endif 146#endif
147 147
148/* 148/*
149 * cpu_sa110_set_pte(ptep, pte) 149 * cpu_sa110_set_pte_ext(ptep, pte, ext)
150 * 150 *
151 * Set a PTE and flush it out 151 * Set a PTE and flush it out
152 */ 152 */
153 .align 5 153 .align 5
154ENTRY(cpu_sa110_set_pte) 154ENTRY(cpu_sa110_set_pte_ext)
155#ifdef CONFIG_MMU 155#ifdef CONFIG_MMU
156 str r1, [r0], #-2048 @ linux version 156 str r1, [r0], #-2048 @ linux version
157 157
@@ -222,7 +222,7 @@ ENTRY(sa110_processor_functions)
222 .word cpu_sa110_do_idle 222 .word cpu_sa110_do_idle
223 .word cpu_sa110_dcache_clean_area 223 .word cpu_sa110_dcache_clean_area
224 .word cpu_sa110_switch_mm 224 .word cpu_sa110_switch_mm
225 .word cpu_sa110_set_pte 225 .word cpu_sa110_set_pte_ext
226 .size sa110_processor_functions, . - sa110_processor_functions 226 .size sa110_processor_functions, . - sa110_processor_functions
227 227
228 .section ".rodata" 228 .section ".rodata"
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index b23b66a6155a..9afb11d089fe 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -22,7 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <asm/assembler.h> 23#include <asm/assembler.h>
24#include <asm/asm-offsets.h> 24#include <asm/asm-offsets.h>
25#include <asm/procinfo.h> 25#include <asm/elf.h>
26#include <asm/hardware.h> 26#include <asm/hardware.h>
27#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable-hwdef.h>
28#include <asm/pgtable.h> 28#include <asm/pgtable.h>
@@ -159,12 +159,12 @@ ENTRY(cpu_sa1100_switch_mm)
159#endif 159#endif
160 160
161/* 161/*
162 * cpu_sa1100_set_pte(ptep, pte) 162 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
163 * 163 *
164 * Set a PTE and flush it out 164 * Set a PTE and flush it out
165 */ 165 */
166 .align 5 166 .align 5
167ENTRY(cpu_sa1100_set_pte) 167ENTRY(cpu_sa1100_set_pte_ext)
168#ifdef CONFIG_MMU 168#ifdef CONFIG_MMU
169 str r1, [r0], #-2048 @ linux version 169 str r1, [r0], #-2048 @ linux version
170 170
@@ -237,7 +237,7 @@ ENTRY(sa1100_processor_functions)
237 .word cpu_sa1100_do_idle 237 .word cpu_sa1100_do_idle
238 .word cpu_sa1100_dcache_clean_area 238 .word cpu_sa1100_dcache_clean_area
239 .word cpu_sa1100_switch_mm 239 .word cpu_sa1100_switch_mm
240 .word cpu_sa1100_set_pte 240 .word cpu_sa1100_set_pte_ext
241 .size sa1100_processor_functions, . - sa1100_processor_functions 241 .size sa1100_processor_functions, . - sa1100_processor_functions
242 242
243 .section ".rodata" 243 .section ".rodata"
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index ab143557e688..9f396b4fa0b7 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -17,7 +17,7 @@
17 17
18#ifndef MULTI_CPU 18#ifndef MULTI_CPU
19EXPORT_SYMBOL(cpu_dcache_clean_area); 19EXPORT_SYMBOL(cpu_dcache_clean_area);
20EXPORT_SYMBOL(cpu_set_pte); 20EXPORT_SYMBOL(cpu_set_pte_ext);
21#else 21#else
22EXPORT_SYMBOL(processor); 22EXPORT_SYMBOL(processor);
23#endif 23#endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 6f72549f8843..7b1843befb9c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -13,8 +13,8 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <asm/assembler.h> 14#include <asm/assembler.h>
15#include <asm/asm-offsets.h> 15#include <asm/asm-offsets.h>
16#include <asm/elf.h>
16#include <asm/hardware/arm_scu.h> 17#include <asm/hardware/arm_scu.h>
17#include <asm/procinfo.h>
18#include <asm/pgtable-hwdef.h> 18#include <asm/pgtable-hwdef.h>
19#include <asm/pgtable.h> 19#include <asm/pgtable.h>
20 20
@@ -103,13 +103,14 @@ ENTRY(cpu_v6_switch_mm)
103 mov pc, lr 103 mov pc, lr
104 104
105/* 105/*
106 * cpu_v6_set_pte(ptep, pte) 106 * cpu_v6_set_pte_ext(ptep, pte, ext)
107 * 107 *
108 * Set a level 2 translation table entry. 108 * Set a level 2 translation table entry.
109 * 109 *
110 * - ptep - pointer to level 2 translation table entry 110 * - ptep - pointer to level 2 translation table entry
111 * (hardware version is stored at -1024 bytes) 111 * (hardware version is stored at -1024 bytes)
112 * - pte - PTE value to store 112 * - pte - PTE value to store
113 * - ext - value for extended PTE bits
113 * 114 *
114 * Permissions: 115 * Permissions:
115 * YUWD APX AP1 AP0 SVC User 116 * YUWD APX AP1 AP0 SVC User
@@ -121,33 +122,34 @@ ENTRY(cpu_v6_switch_mm)
121 * 11x0 0 1 0 r/w r/o 122 * 11x0 0 1 0 r/w r/o
122 * 1111 0 1 1 r/w r/w 123 * 1111 0 1 1 r/w r/w
123 */ 124 */
124ENTRY(cpu_v6_set_pte) 125ENTRY(cpu_v6_set_pte_ext)
125#ifdef CONFIG_MMU 126#ifdef CONFIG_MMU
126 str r1, [r0], #-2048 @ linux version 127 str r1, [r0], #-2048 @ linux version
127 128
128 bic r2, r1, #0x000003f0 129 bic r3, r1, #0x000003f0
129 bic r2, r2, #0x00000003 130 bic r3, r3, #0x00000003
130 orr r2, r2, #PTE_EXT_AP0 | 2 131 orr r3, r3, r2
132 orr r3, r3, #PTE_EXT_AP0 | 2
131 133
132 tst r1, #L_PTE_WRITE 134 tst r1, #L_PTE_WRITE
133 tstne r1, #L_PTE_DIRTY 135 tstne r1, #L_PTE_DIRTY
134 orreq r2, r2, #PTE_EXT_APX 136 orreq r3, r3, #PTE_EXT_APX
135 137
136 tst r1, #L_PTE_USER 138 tst r1, #L_PTE_USER
137 orrne r2, r2, #PTE_EXT_AP1 139 orrne r3, r3, #PTE_EXT_AP1
138 tstne r2, #PTE_EXT_APX 140 tstne r3, #PTE_EXT_APX
139 bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0 141 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
140 142
141 tst r1, #L_PTE_YOUNG 143 tst r1, #L_PTE_YOUNG
142 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK 144 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
143 145
144 tst r1, #L_PTE_EXEC 146 tst r1, #L_PTE_EXEC
145 orreq r2, r2, #PTE_EXT_XN 147 orreq r3, r3, #PTE_EXT_XN
146 148
147 tst r1, #L_PTE_PRESENT 149 tst r1, #L_PTE_PRESENT
148 moveq r2, #0 150 moveq r3, #0
149 151
150 str r2, [r0] 152 str r3, [r0]
151 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 153 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
152#endif 154#endif
153 mov pc, lr 155 mov pc, lr
@@ -156,7 +158,7 @@ ENTRY(cpu_v6_set_pte)
156 158
157 159
158cpu_v6_name: 160cpu_v6_name:
159 .asciz "Some Random V6 Processor" 161 .asciz "ARMv6-compatible processor"
160 .align 162 .align
161 163
162 .section ".text.init", #alloc, #execinstr 164 .section ".text.init", #alloc, #execinstr
@@ -207,11 +209,6 @@ __v6_setup:
207#endif 209#endif
208 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 210 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
209#endif /* CONFIG_MMU */ 211#endif /* CONFIG_MMU */
210#ifdef CONFIG_VFP
211 mrc p15, 0, r0, c1, c0, 2
212 orr r0, r0, #(0xf << 20)
213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
214#endif
215 adr r5, v6_crval 212 adr r5, v6_crval
216 ldmia r5, {r5, r6} 213 ldmia r5, {r5, r6}
217 mrc p15, 0, r0, c1, c0, 0 @ read control register 214 mrc p15, 0, r0, c1, c0, 0 @ read control register
@@ -238,7 +235,7 @@ ENTRY(v6_processor_functions)
238 .word cpu_v6_do_idle 235 .word cpu_v6_do_idle
239 .word cpu_v6_dcache_clean_area 236 .word cpu_v6_dcache_clean_area
240 .word cpu_v6_switch_mm 237 .word cpu_v6_switch_mm
241 .word cpu_v6_set_pte 238 .word cpu_v6_set_pte_ext
242 .size v6_processor_functions, . - v6_processor_functions 239 .size v6_processor_functions, . - v6_processor_functions
243 240
244 .type cpu_arch_name, #object 241 .type cpu_arch_name, #object
@@ -273,7 +270,7 @@ __v6_proc_info:
273 b __v6_setup 270 b __v6_setup
274 .long cpu_arch_name 271 .long cpu_arch_name
275 .long cpu_elf_name 272 .long cpu_elf_name
276 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA 273 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
277 .long cpu_v6_name 274 .long cpu_v6_name
278 .long v6_processor_functions 275 .long v6_processor_functions
279 .long v6wbi_tlb_fns 276 .long v6wbi_tlb_fns
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 4ace2d8090c7..43494ae8f01a 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -27,7 +27,7 @@
27#include <linux/linkage.h> 27#include <linux/linkage.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <asm/assembler.h> 29#include <asm/assembler.h>
30#include <asm/procinfo.h> 30#include <asm/elf.h>
31#include <asm/hardware.h> 31#include <asm/hardware.h>
32#include <asm/pgtable.h> 32#include <asm/pgtable.h>
33#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
@@ -57,11 +57,6 @@
57#define L2_CACHE_ENABLE 1 57#define L2_CACHE_ENABLE 1
58 58
59/* 59/*
60 * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
61 */
62#define BTB_ENABLE 0
63
64/*
65 * This macro is used to wait for a CP15 write and is needed 60 * This macro is used to wait for a CP15 write and is needed
66 * when we have to ensure that the last operation to the co-pro 61 * when we have to ensure that the last operation to the co-pro
67 * was completed before continuing with operation. 62 * was completed before continuing with operation.
@@ -362,17 +357,19 @@ ENTRY(cpu_xsc3_switch_mm)
362 cpwait_ret lr, ip 357 cpwait_ret lr, ip
363 358
364/* 359/*
365 * cpu_xsc3_set_pte(ptep, pte) 360 * cpu_xsc3_set_pte_ext(ptep, pte, ext)
366 * 361 *
367 * Set a PTE and flush it out 362 * Set a PTE and flush it out
368 * 363 *
369 */ 364 */
370 .align 5 365 .align 5
371ENTRY(cpu_xsc3_set_pte) 366ENTRY(cpu_xsc3_set_pte_ext)
372 str r1, [r0], #-2048 @ linux version 367 str r1, [r0], #-2048 @ linux version
373 368
374 bic r2, r1, #0xdf0 @ Keep C, B, coherency bits 369 bic r2, r1, #0xff0 @ Keep C, B bits
375 orr r2, r2, #PTE_TYPE_EXT @ extended page 370 orr r2, r2, #PTE_TYPE_EXT @ extended page
371 tst r1, #L_PTE_SHARED @ Shared?
372 orrne r2, r2, #0x200
376 373
377 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 374 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
378 375
@@ -432,9 +429,7 @@ __xsc3_setup:
432 mrc p15, 0, r0, c1, c0, 0 @ get control register 429 mrc p15, 0, r0, c1, c0, 0 @ get control register
433 bic r0, r0, r5 @ .... .... .... ..A. 430 bic r0, r0, r5 @ .... .... .... ..A.
434 orr r0, r0, r6 @ .... .... .... .C.M 431 orr r0, r0, r6 @ .... .... .... .C.M
435#if BTB_ENABLE
436 orr r0, r0, #0x00000800 @ ..VI Z..S .... .... 432 orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
437#endif
438#if L2_CACHE_ENABLE 433#if L2_CACHE_ENABLE
439 orr r0, r0, #0x04000000 @ L2 enable 434 orr r0, r0, #0x04000000 @ L2 enable
440#endif 435#endif
@@ -462,7 +457,7 @@ ENTRY(xsc3_processor_functions)
462 .word cpu_xsc3_do_idle 457 .word cpu_xsc3_do_idle
463 .word cpu_xsc3_dcache_clean_area 458 .word cpu_xsc3_dcache_clean_area
464 .word cpu_xsc3_switch_mm 459 .word cpu_xsc3_switch_mm
465 .word cpu_xsc3_set_pte 460 .word cpu_xsc3_set_pte_ext
466 .size xsc3_processor_functions, . - xsc3_processor_functions 461 .size xsc3_processor_functions, . - xsc3_processor_functions
467 462
468 .section ".rodata" 463 .section ".rodata"
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2749c1f88d7d..490e11b34231 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -23,7 +23,7 @@
23#include <linux/linkage.h> 23#include <linux/linkage.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <asm/assembler.h> 25#include <asm/assembler.h>
26#include <asm/procinfo.h> 26#include <asm/elf.h>
27#include <asm/pgtable.h> 27#include <asm/pgtable.h>
28#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable-hwdef.h>
29#include <asm/page.h> 29#include <asm/page.h>
@@ -421,14 +421,14 @@ ENTRY(cpu_xscale_switch_mm)
421 cpwait_ret lr, ip 421 cpwait_ret lr, ip
422 422
423/* 423/*
424 * cpu_xscale_set_pte(ptep, pte) 424 * cpu_xscale_set_pte_ext(ptep, pte, ext)
425 * 425 *
426 * Set a PTE and flush it out 426 * Set a PTE and flush it out
427 * 427 *
428 * Errata 40: must set memory to write-through for user read-only pages. 428 * Errata 40: must set memory to write-through for user read-only pages.
429 */ 429 */
430 .align 5 430 .align 5
431ENTRY(cpu_xscale_set_pte) 431ENTRY(cpu_xscale_set_pte_ext)
432 str r1, [r0], #-2048 @ linux version 432 str r1, [r0], #-2048 @ linux version
433 433
434 bic r2, r1, #0xff0 434 bic r2, r1, #0xff0
@@ -491,12 +491,7 @@ __xscale_setup:
491 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 491 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
492 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 492 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
493 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 493 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
494#ifdef CONFIG_IWMMXT 494 mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
495 mov r0, #0 @ initially disallow access to CP0/CP1
496#else
497 mov r0, #1 @ Allow access to CP0
498#endif
499 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
500 orr r0, r0, #1 << 13 @ Its undefined whether this 495 orr r0, r0, #1 << 13 @ Its undefined whether this
501 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 496 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
502 497
@@ -534,7 +529,7 @@ ENTRY(xscale_processor_functions)
534 .word cpu_xscale_do_idle 529 .word cpu_xscale_do_idle
535 .word cpu_xscale_dcache_clean_area 530 .word cpu_xscale_dcache_clean_area
536 .word cpu_xscale_switch_mm 531 .word cpu_xscale_switch_mm
537 .word cpu_xscale_set_pte 532 .word cpu_xscale_set_pte_ext
538 .size xscale_processor_functions, . - xscale_processor_functions 533 .size xscale_processor_functions, . - xscale_processor_functions
539 534
540 .section ".rodata" 535 .section ".rodata"
@@ -909,7 +904,7 @@ __pxa270_proc_info:
909 b __xscale_setup 904 b __xscale_setup
910 .long cpu_arch_name 905 .long cpu_arch_name
911 .long cpu_elf_name 906 .long cpu_elf_name
912 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_IWMMXT 907 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
913 .long cpu_pxa270_name 908 .long cpu_pxa270_name
914 .long xscale_processor_functions 909 .long xscale_processor_functions
915 .long v4wbi_tlb_fns 910 .long v4wbi_tlb_fns
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8162eed8b500..4f2fd5591337 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -410,7 +410,7 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
410 trigger & __IRQT_RISEDGE); 410 trigger & __IRQT_RISEDGE);
411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
412 trigger & __IRQT_FALEDGE); 412 trigger & __IRQT_FALEDGE);
413 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level 413 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
414 * triggering requested. */ 414 * triggering requested. */
415} 415}
416 416
@@ -783,7 +783,7 @@ void omap_free_gpio(int gpio)
783 * line's interrupt handler has been run, we may miss some nested 783 * line's interrupt handler has been run, we may miss some nested
784 * interrupts. 784 * interrupts.
785 */ 785 */
786static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc) 786static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
787{ 787{
788 void __iomem *isr_reg = NULL; 788 void __iomem *isr_reg = NULL;
789 u32 isr; 789 u32 isr;
@@ -853,7 +853,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
853 853
854 gpio_irq = bank->virtual_irq_start; 854 gpio_irq = bank->virtual_irq_start;
855 for (; isr != 0; isr >>= 1, gpio_irq++) { 855 for (; isr != 0; isr >>= 1, gpio_irq++) {
856 struct irqdesc *d; 856 struct irq_desc *d;
857 int irq_mask; 857 int irq_mask;
858 if (!(isr & 1)) 858 if (!(isr & 1))
859 continue; 859 continue;
@@ -1092,7 +1092,7 @@ static int __init _omap_gpio_init(void)
1092 set_irq_chip(j, &mpuio_irq_chip); 1092 set_irq_chip(j, &mpuio_irq_chip);
1093 else 1093 else
1094 set_irq_chip(j, &gpio_irq_chip); 1094 set_irq_chip(j, &gpio_irq_chip);
1095 set_irq_handler(j, do_simple_IRQ); 1095 set_irq_handler(j, handle_simple_irq);
1096 set_irq_flags(j, IRQF_VALID); 1096 set_irq_flags(j, IRQF_VALID);
1097 } 1097 }
1098 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1098 set_irq_chained_handler(bank->irq, gpio_irq_handler);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 579c69ae9ff7..8bcb838e5444 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Mon Oct 16 21:13:36 2006 15# Last update: Thu Dec 7 17:19:20 2006
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -79,7 +79,7 @@ psionw ARCH_PSIONW PSIONW 60
79aln SA1100_ALN ALN 61 79aln SA1100_ALN ALN 61
80epxa ARCH_CAMELOT CAMELOT 62 80epxa ARCH_CAMELOT CAMELOT 62
81gds2200 SA1100_GDS2200 GDS2200 63 81gds2200 SA1100_GDS2200 GDS2200 63
82psion_series7 SA1100_PSION_SERIES7 PSION_SERIES7 64 82netbook SA1100_PSION_SERIES7 PSION_SERIES7 64
83xfile SA1100_XFILE XFILE 65 83xfile SA1100_XFILE XFILE 65
84accelent_ep9312 ARCH_ACCELENT_EP9312 ACCELENT_EP9312 66 84accelent_ep9312 ARCH_ACCELENT_EP9312 ACCELENT_EP9312 66
85ic200 ARCH_IC200 IC200 67 85ic200 ARCH_IC200 IC200 67
@@ -810,9 +810,9 @@ sb3010 MACH_SB3010 SB3010 795
810rm9200 MACH_RM9200 RM9200 796 810rm9200 MACH_RM9200 RM9200 796
811dma03 MACH_DMA03 DMA03 797 811dma03 MACH_DMA03 DMA03 797
812road_s101 MACH_ROAD_S101 ROAD_S101 798 812road_s101 MACH_ROAD_S101 ROAD_S101 798
813iq_nextgen_a MACH_IQ_NEXTGEN_A IQ_NEXTGEN_A 799 813iq81340sc MACH_IQ81340SC IQ81340SC 799
814iq_nextgen_b MACH_IQ_NEXTGEN_B IQ_NEXTGEN_B 800 814iq_nextgen_b MACH_IQ_NEXTGEN_B IQ_NEXTGEN_B 800
815iq_nextgen_c MACH_IQ_NEXTGEN_C IQ_NEXTGEN_C 801 815iq81340mc MACH_IQ81340MC IQ81340MC 801
816iq_nextgen_d MACH_IQ_NEXTGEN_D IQ_NEXTGEN_D 802 816iq_nextgen_d MACH_IQ_NEXTGEN_D IQ_NEXTGEN_D 802
817iq_nextgen_e MACH_IQ_NEXTGEN_E IQ_NEXTGEN_E 803 817iq_nextgen_e MACH_IQ_NEXTGEN_E IQ_NEXTGEN_E 803
818mallow_at91 MACH_MALLOW_AT91 MALLOW_AT91 804 818mallow_at91 MACH_MALLOW_AT91 MALLOW_AT91 804
@@ -1165,9 +1165,57 @@ pnx4010 MACH_PNX4010 PNX4010 1151
1165oxnas MACH_OXNAS OXNAS 1152 1165oxnas MACH_OXNAS OXNAS 1152
1166fiori MACH_FIORI FIORI 1153 1166fiori MACH_FIORI FIORI 1153
1167ml1200 MACH_ML1200 ML1200 1154 1167ml1200 MACH_ML1200 ML1200 1154
1168cactus MACH_CACTUS CACTUS 1155 1168pecos MACH_PECOS PECOS 1155
1169nb2xxx MACH_NB2XXX NB2XXX 1156 1169nb2xxx MACH_NB2XXX NB2XXX 1156
1170hw6900 MACH_HW6900 HW6900 1157 1170hw6900 MACH_HW6900 HW6900 1157
1171cdcs_quoll MACH_CDCS_QUOLL CDCS_QUOLL 1158 1171cdcs_quoll MACH_CDCS_QUOLL CDCS_QUOLL 1158
1172quicksilver MACH_QUICKSILVER QUICKSILVER 1159 1172quicksilver MACH_QUICKSILVER QUICKSILVER 1159
1173uplat926 MACH_UPLAT926 UPLAT926 1160 1173uplat926 MACH_UPLAT926 UPLAT926 1160
1174dep2410_dep2410 MACH_DEP2410_THOMAS DEP2410_THOMAS 1161
1175dtk2410 MACH_DTK2410 DTK2410 1162
1176chili MACH_CHILI CHILI 1163
1177demeter MACH_DEMETER DEMETER 1164
1178dionysus MACH_DIONYSUS DIONYSUS 1165
1179as352x MACH_AS352X AS352X 1166
1180service MACH_SERVICE SERVICE 1167
1181cs_e9301 MACH_CS_E9301 CS_E9301 1168
1182micro9m MACH_MICRO9M MICRO9M 1169
1183ia_mospck MACH_IA_MOSPCK IA_MOSPCK 1170
1184ql201b MACH_QL201B QL201B 1171
1185bbm MACH_BBM BBM 1174
1186exxx MACH_EXXX EXXX 1175
1187wma11b MACH_WMA11B WMA11B 1176
1188pelco_atlas MACH_PELCO_ATLAS PELCO_ATLAS 1177
1189g500 MACH_G500 G500 1178
1190bug MACH_BUG BUG 1179
1191mx33ads MACH_MX33ADS MX33ADS 1180
1192chub MACH_CHUB CHUB 1181
1193gta01 MACH_GTA01 GTA01 1182
1194w90n740 MACH_W90N740 W90N740 1183
1195medallion_sa2410 MACH_MEDALLION_SA2410 MEDALLION_SA2410 1184
1196ia_cpu_9200_2 MACH_IA_CPU_9200_2 IA_CPU_9200_2 1185
1197dimmrm9200 MACH_DIMMRM9200 DIMMRM9200 1186
1198pm9261 MACH_PM9261 PM9261 1187
1199mx21 MACH_MX21 MX21 1188
1200ml7304 MACH_ML7304 ML7304 1189
1201ucp250 MACH_UCP250 UCP250 1190
1202intboard MACH_INTBOARD INTBOARD 1191
1203gulfstream MACH_GULFSTREAM GULFSTREAM 1192
1204labquest MACH_LABQUEST LABQUEST 1193
1205vcmx313 MACH_VCMX313 VCMX313 1194
1206urg200 MACH_URG200 URG200 1195
1207cpux255lcdnet MACH_CPUX255LCDNET CPUX255LCDNET 1196
1208netdcu9 MACH_NETDCU9 NETDCU9 1197
1209netdcu10 MACH_NETDCU10 NETDCU10 1198
1210dspg_dga MACH_DSPG_DGA DSPG_DGA 1199
1211dspg_dvw MACH_DSPG_DVW DSPG_DVW 1200
1212solos MACH_SOLOS SOLOS 1201
1213at91sam9263ek MACH_AT91SAM9263EK AT91SAM9263EK 1202
1214osstbox MACH_OSSTBOX OSSTBOX 1203
1215kbat9261 MACH_KBAT9261 KBAT9261 1204
1216ct1100 MACH_CT1100 CT1100 1205
1217akcppxa MACH_AKCPPXA AKCPPXA 1206
1218zevio_1020 MACH_ZEVIO_1020 ZEVIO_1020 1207
1219hitrack MACH_HITRACK HITRACK 1208
1220syme1 MACH_SYME1 SYME1 1209
1221syhl1 MACH_SYHL1 SYHL1 1210
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index f08eafbddcc1..e26cc1f59948 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -263,13 +263,24 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
263 if (exceptions) 263 if (exceptions)
264 vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); 264 vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
265} 265}
266 266
267/* 267/*
268 * VFP support code initialisation. 268 * VFP support code initialisation.
269 */ 269 */
270static int __init vfp_init(void) 270static int __init vfp_init(void)
271{ 271{
272 unsigned int vfpsid; 272 unsigned int vfpsid;
273 unsigned int cpu_arch = cpu_architecture();
274 u32 access = 0;
275
276 if (cpu_arch >= CPU_ARCH_ARMv6) {
277 access = get_copro_access();
278
279 /*
280 * Enable full access to VFP (cp10 and cp11)
281 */
282 set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
283 }
273 284
274 /* 285 /*
275 * First check that there is a VFP that we can use. 286 * First check that there is a VFP that we can use.
@@ -281,6 +292,12 @@ static int __init vfp_init(void)
281 printk(KERN_INFO "VFP support v0.3: "); 292 printk(KERN_INFO "VFP support v0.3: ");
282 if (VFP_arch) { 293 if (VFP_arch) {
283 printk("not present\n"); 294 printk("not present\n");
295
296 /*
297 * Restore the copro access register.
298 */
299 if (cpu_arch >= CPU_ARCH_ARMv6)
300 set_copro_access(access);
284 } else if (vfpsid & FPSID_NODOUBLE) { 301 } else if (vfpsid & FPSID_NODOUBLE) {
285 printk("no double precision support\n"); 302 printk("no double precision support\n");
286 } else { 303 } else {
@@ -291,9 +308,16 @@ static int __init vfp_init(void)
291 (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, 308 (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
292 (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT, 309 (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
293 (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT); 310 (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
311
294 vfp_vector = vfp_support_entry; 312 vfp_vector = vfp_support_entry;
295 313
296 thread_register_notifier(&vfp_notifier_block); 314 thread_register_notifier(&vfp_notifier_block);
315
316 /*
317 * We detected VFP, and the support code is
318 * in place; report VFP support to userspace.
319 */
320 elf_hwcap |= HWCAP_VFP;
297 } 321 }
298 return 0; 322 return 0;
299} 323}
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