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-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts4
-rw-r--r--arch/arm/boot/dts/imx27.dtsi1
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts44
-rw-r--r--arch/arm/boot/dts/imx51.dtsi146
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts59
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts39
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts42
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts46
-rw-r--r--arch/arm/boot/dts/imx53.dtsi199
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts21
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts27
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts25
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi224
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig4
-rw-r--r--arch/arm/mach-imx/Kconfig106
-rw-r--r--arch/arm/mach-imx/Makefile9
-rw-r--r--arch/arm/mach-imx/Makefile.boot8
-rw-r--r--arch/arm/mach-imx/devices-imx53.h48
-rw-r--r--arch/arm/mach-imx/efika.h10
-rw-r--r--arch/arm/mach-imx/imx51-dt.c21
-rw-r--r--arch/arm/mach-imx/mach-imx53.c (renamed from arch/arm/mach-imx/imx53-dt.c)27
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c10
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikamx.c300
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikasb.c296
-rw-r--r--arch/arm/mach-imx/mach-mx53_ard.c272
-rw-r--r--arch/arm/mach-imx/mach-mx53_evk.c179
-rw-r--r--arch/arm/mach-imx/mach-mx53_loco.c321
-rw-r--r--arch/arm/mach-imx/mach-mx53_smd.c168
-rw-r--r--arch/arm/mach-imx/mm-imx5.c47
-rw-r--r--arch/arm/mach-imx/mx51_efika.c633
-rw-r--r--arch/arm/mach-mmp/Kconfig3
-rw-r--r--arch/arm/mach-prima2/Makefile1
-rw-r--r--arch/arm/mach-prima2/clock.c510
-rw-r--r--arch/arm/mach-prima2/prima2.c1
-rw-r--r--arch/arm/mach-prima2/timer.c8
-rw-r--r--arch/arm/mach-realview/core.c106
-rw-r--r--arch/arm/mach-realview/include/mach/clkdev.h16
-rw-r--r--arch/arm/mach-realview/realview_eb.c2
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c2
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c2
-rw-r--r--arch/arm/mach-realview/realview_pba8.c2
-rw-r--r--arch/arm/mach-realview/realview_pbx.c2
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/Makefile2
-rw-r--r--arch/arm/mach-ux500/clock.c715
-rw-r--r--arch/arm/mach-ux500/clock.h164
-rw-r--r--arch/arm/mach-ux500/cpu.c14
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx53.h1219
50 files changed, 807 insertions, 5314 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18fee9fe..1a01ffa331d0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -273,7 +273,7 @@ config ARCH_INTEGRATOR
273 select ARM_AMBA 273 select ARM_AMBA
274 select ARCH_HAS_CPUFREQ 274 select ARCH_HAS_CPUFREQ
275 select COMMON_CLK 275 select COMMON_CLK
276 select CLK_VERSATILE 276 select COMMON_CLK_VERSATILE
277 select HAVE_TCM 277 select HAVE_TCM
278 select ICST 278 select ICST
279 select GENERIC_CLOCKEVENTS 279 select GENERIC_CLOCKEVENTS
@@ -289,13 +289,12 @@ config ARCH_INTEGRATOR
289config ARCH_REALVIEW 289config ARCH_REALVIEW
290 bool "ARM Ltd. RealView family" 290 bool "ARM Ltd. RealView family"
291 select ARM_AMBA 291 select ARM_AMBA
292 select CLKDEV_LOOKUP 292 select COMMON_CLK
293 select HAVE_MACH_CLKDEV 293 select COMMON_CLK_VERSATILE
294 select ICST 294 select ICST
295 select GENERIC_CLOCKEVENTS 295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB 296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE 297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLOCK
299 select PLAT_VERSATILE_CLCD 298 select PLAT_VERSATILE_CLCD
300 select ARM_TIMER_SP804 299 select ARM_TIMER_SP804
301 select GPIO_PL061 if GPIOLIB 300 select GPIO_PL061 if GPIOLIB
@@ -413,7 +412,7 @@ config ARCH_PRIMA2
413 select NO_IOPORT 412 select NO_IOPORT
414 select ARCH_REQUIRE_GPIOLIB 413 select ARCH_REQUIRE_GPIOLIB
415 select GENERIC_CLOCKEVENTS 414 select GENERIC_CLOCKEVENTS
416 select CLKDEV_LOOKUP 415 select COMMON_CLK
417 select GENERIC_IRQ_CHIP 416 select GENERIC_IRQ_CHIP
418 select MIGHT_HAVE_CACHE_L2X0 417 select MIGHT_HAVE_CACHE_L2X0
419 select PINCTRL 418 select PINCTRL
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2b0ff60247a4..777caa33cd85 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -23,10 +23,6 @@
23 soc { 23 soc {
24 aipi@10000000 { /* aipi */ 24 aipi@10000000 { /* aipi */
25 25
26 wdog@10002000 {
27 status = "okay";
28 };
29
30 serial@1000a000 { 26 serial@1000a000 {
31 fsl,uart-has-rtscts; 27 fsl,uart-has-rtscts;
32 status = "okay"; 28 status = "okay";
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5303ab680a34..3e54f1498841 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -62,7 +62,6 @@
62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
63 reg = <0x10002000 0x4000>; 63 reg = <0x10002000 0x4000>;
64 interrupts = <27>; 64 interrupts = <27>;
65 status = "disabled";
66 }; 65 };
67 66
68 uart1: serial@1000a000 { 67 uart1: serial@1000a000 {
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index cd86177a3ea2..6f4c80e26c57 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,23 +25,31 @@
25 aips@70000000 { /* aips-1 */ 25 aips@70000000 { /* aips-1 */
26 spba@70000000 { 26 spba@70000000 {
27 esdhc@70004000 { /* ESDHC1 */ 27 esdhc@70004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 fsl,cd-internal; 30 fsl,cd-internal;
29 fsl,wp-internal; 31 fsl,wp-internal;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 34
33 esdhc@70008000 { /* ESDHC2 */ 35 esdhc@70008000 { /* ESDHC2 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc2_1>;
34 cd-gpios = <&gpio1 6 0>; 38 cd-gpios = <&gpio1 6 0>;
35 wp-gpios = <&gpio1 5 0>; 39 wp-gpios = <&gpio1 5 0>;
36 status = "okay"; 40 status = "okay";
37 }; 41 };
38 42
39 uart3: serial@7000c000 { 43 uart3: serial@7000c000 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_uart3_1>;
40 fsl,uart-has-rtscts; 46 fsl,uart-has-rtscts;
41 status = "okay"; 47 status = "okay";
42 }; 48 };
43 49
44 ecspi@70010000 { /* ECSPI1 */ 50 ecspi@70010000 { /* ECSPI1 */
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_ecspi1_1>;
45 fsl,spi-num-chipselects = <2>; 53 fsl,spi-num-chipselects = <2>;
46 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; 54 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
47 status = "okay"; 55 status = "okay";
@@ -169,31 +177,43 @@
169 }; 177 };
170 }; 178 };
171 179
172 wdog@73f98000 { /* WDOG1 */
173 status = "okay";
174 };
175
176 iomuxc@73fa8000 { 180 iomuxc@73fa8000 {
177 compatible = "fsl,imx51-iomuxc-babbage"; 181 pinctrl-names = "default";
178 reg = <0x73fa8000 0x4000>; 182 pinctrl-0 = <&pinctrl_hog>;
183
184 hog {
185 pinctrl_hog: hoggrp {
186 fsl,pins = <
187 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
188 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
189 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
190 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
191 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
192 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
193 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
194 >;
195 };
196 };
179 }; 197 };
180 198
181 uart1: serial@73fbc000 { 199 uart1: serial@73fbc000 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_uart1_1>;
182 fsl,uart-has-rtscts; 202 fsl,uart-has-rtscts;
183 status = "okay"; 203 status = "okay";
184 }; 204 };
185 205
186 uart2: serial@73fc0000 { 206 uart2: serial@73fc0000 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart2_1>;
187 status = "okay"; 209 status = "okay";
188 }; 210 };
189 }; 211 };
190 212
191 aips@80000000 { /* aips-2 */ 213 aips@80000000 { /* aips-2 */
192 sdma@83fb0000 {
193 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
194 };
195
196 i2c@83fc4000 { /* I2C2 */ 214 i2c@83fc4000 { /* I2C2 */
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_i2c2_1>;
197 status = "okay"; 217 status = "okay";
198 218
199 sgtl5000: codec@0a { 219 sgtl5000: codec@0a {
@@ -206,10 +226,14 @@
206 }; 226 };
207 227
208 audmux@83fd0000 { 228 audmux@83fd0000 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_audmux_1>;
209 status = "okay"; 231 status = "okay";
210 }; 232 };
211 233
212 ethernet@83fec000 { 234 ethernet@83fec000 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_fec_1>;
213 phy-mode = "mii"; 237 phy-mode = "mii";
214 status = "okay"; 238 status = "okay";
215 }; 239 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc87fc8..2f71a91ca98e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
130 }; 130 };
131 }; 131 };
132 132
133 usb@73f80000 {
134 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
135 reg = <0x73f80000 0x0200>;
136 interrupts = <18>;
137 status = "disabled";
138 };
139
140 usb@73f80200 {
141 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
142 reg = <0x73f80200 0x0200>;
143 interrupts = <14>;
144 status = "disabled";
145 };
146
147 usb@73f80400 {
148 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
149 reg = <0x73f80400 0x0200>;
150 interrupts = <16>;
151 status = "disabled";
152 };
153
154 usb@73f80600 {
155 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156 reg = <0x73f80600 0x0200>;
157 interrupts = <17>;
158 status = "disabled";
159 };
160
133 gpio1: gpio@73f84000 { 161 gpio1: gpio@73f84000 {
134 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 162 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
135 reg = <0x73f84000 0x4000>; 163 reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@
174 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 202 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
175 reg = <0x73f98000 0x4000>; 203 reg = <0x73f98000 0x4000>;
176 interrupts = <58>; 204 interrupts = <58>;
177 status = "disabled";
178 }; 205 };
179 206
180 wdog@73f9c000 { /* WDOG2 */ 207 wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@
184 status = "disabled"; 211 status = "disabled";
185 }; 212 };
186 213
214 iomuxc@73fa8000 {
215 compatible = "fsl,imx51-iomuxc";
216 reg = <0x73fa8000 0x4000>;
217
218 audmux {
219 pinctrl_audmux_1: audmuxgrp-1 {
220 fsl,pins = <
221 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
222 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
223 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
224 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
225 >;
226 };
227 };
228
229 fec {
230 pinctrl_fec_1: fecgrp-1 {
231 fsl,pins = <
232 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
233 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
234 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
235 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
236 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
237 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
238 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
239 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
240 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
241 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
242 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
243 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
244 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
245 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
246 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
247 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
248 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
249 >;
250 };
251 };
252
253 ecspi1 {
254 pinctrl_ecspi1_1: ecspi1grp-1 {
255 fsl,pins = <
256 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
257 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
258 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
259 >;
260 };
261 };
262
263 esdhc1 {
264 pinctrl_esdhc1_1: esdhc1grp-1 {
265 fsl,pins = <
266 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
267 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
268 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
269 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
270 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
271 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
272 >;
273 };
274 };
275
276 esdhc2 {
277 pinctrl_esdhc2_1: esdhc2grp-1 {
278 fsl,pins = <
279 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
280 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
281 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
282 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
283 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
284 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
285 >;
286 };
287 };
288
289 i2c2 {
290 pinctrl_i2c2_1: i2c2grp-1 {
291 fsl,pins = <
292 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
293 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
294 >;
295 };
296 };
297
298 uart1 {
299 pinctrl_uart1_1: uart1grp-1 {
300 fsl,pins = <
301 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
302 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
303 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
304 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
305 >;
306 };
307 };
308
309 uart2 {
310 pinctrl_uart2_1: uart2grp-1 {
311 fsl,pins = <
312 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
313 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
314 >;
315 };
316 };
317
318 uart3 {
319 pinctrl_uart3_1: uart3grp-1 {
320 fsl,pins = <
321 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
322 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
323 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
324 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
325 >;
326 };
327 };
328 };
329
187 uart1: serial@73fbc000 { 330 uart1: serial@73fbc000 {
188 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 331 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
189 reg = <0x73fbc000 0x4000>; 332 reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@
219 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 362 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
220 reg = <0x83fb0000 0x4000>; 363 reg = <0x83fb0000 0x4000>;
221 interrupts = <6>; 364 interrupts = <6>;
365 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
222 }; 366 };
223 367
224 cspi@83fc0000 { 368 cspi@83fc0000 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index da895e93a999..4be76f223526 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -25,31 +25,66 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_2>;
28 cd-gpios = <&gpio1 1 0>; 30 cd-gpios = <&gpio1 1 0>;
29 wp-gpios = <&gpio1 9 0>; 31 wp-gpios = <&gpio1 9 0>;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 }; 34 };
33 35
34 wdog@53f98000 { /* WDOG1 */
35 status = "okay";
36 };
37
38 iomuxc@53fa8000 { 36 iomuxc@53fa8000 {
39 compatible = "fsl,imx53-iomuxc-ard"; 37 pinctrl-names = "default";
40 reg = <0x53fa8000 0x4000>; 38 pinctrl-0 = <&pinctrl_hog>;
39
40 hog {
41 pinctrl_hog: hoggrp {
42 fsl,pins = <
43 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
44 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
45 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
46 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
47 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
48 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
49 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
50 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
51 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
52 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
53 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
54 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
55 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
56 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
57 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
58 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
59 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
60 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
61 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
62 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
63 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
64 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
65 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
66 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
67 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
68 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
69 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
70 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
71 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
72 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
73 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
74 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
75 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
76 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
77 >;
78 };
79 };
41 }; 80 };
42 81
43 uart1: serial@53fbc000 { 82 uart1: serial@53fbc000 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1_2>;
44 status = "okay"; 85 status = "okay";
45 }; 86 };
46 }; 87 };
47
48 aips@60000000 { /* AIPS2 */
49 sdma@63fb0000 {
50 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
51 };
52 };
53 }; 88 };
54 89
55 eim-cs1@f4000000 { 90 eim-cs1@f4000000 {
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 9c798034675e..a124d1e25258 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -25,12 +25,16 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 cd-gpios = <&gpio3 13 0>; 30 cd-gpios = <&gpio3 13 0>;
29 wp-gpios = <&gpio3 14 0>; 31 wp-gpios = <&gpio3 14 0>;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 34
33 ecspi@50010000 { /* ECSPI1 */ 35 ecspi@50010000 { /* ECSPI1 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_ecspi1_1>;
34 fsl,spi-num-chipselects = <2>; 38 fsl,spi-num-chipselects = <2>;
35 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; 39 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
36 status = "okay"; 40 status = "okay";
@@ -56,32 +60,45 @@
56 }; 60 };
57 61
58 esdhc@50020000 { /* ESDHC3 */ 62 esdhc@50020000 { /* ESDHC3 */
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_esdhc3_1>;
59 cd-gpios = <&gpio3 11 0>; 65 cd-gpios = <&gpio3 11 0>;
60 wp-gpios = <&gpio3 12 0>; 66 wp-gpios = <&gpio3 12 0>;
61 status = "okay"; 67 status = "okay";
62 }; 68 };
63 }; 69 };
64 70
65 wdog@53f98000 { /* WDOG1 */
66 status = "okay";
67 };
68
69 iomuxc@53fa8000 { 71 iomuxc@53fa8000 {
70 compatible = "fsl,imx53-iomuxc-evk"; 72 pinctrl-names = "default";
71 reg = <0x53fa8000 0x4000>; 73 pinctrl-0 = <&pinctrl_hog>;
74
75 hog {
76 pinctrl_hog: hoggrp {
77 fsl,pins = <
78 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
79 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
80 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
81 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
82 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
83 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
84 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
85 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
86 >;
87 };
88 };
72 }; 89 };
73 90
74 uart1: serial@53fbc000 { 91 uart1: serial@53fbc000 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_uart1_1>;
75 status = "okay"; 94 status = "okay";
76 }; 95 };
77 }; 96 };
78 97
79 aips@60000000 { /* AIPS2 */ 98 aips@60000000 { /* AIPS2 */
80 sdma@63fb0000 {
81 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
82 };
83
84 i2c@63fc4000 { /* I2C2 */ 99 i2c@63fc4000 { /* I2C2 */
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2_1>;
85 status = "okay"; 102 status = "okay";
86 103
87 pmic: mc13892@08 { 104 pmic: mc13892@08 {
@@ -96,6 +113,8 @@
96 }; 113 };
97 114
98 ethernet@63fec000 { 115 ethernet@63fec000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_fec_1>;
99 phy-mode = "rmii"; 118 phy-mode = "rmii";
100 phy-reset-gpios = <&gpio7 6 0>; 119 phy-reset-gpios = <&gpio7 6 0>;
101 status = "okay"; 120 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 2d803a9a6949..08948af86d1a 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -25,6 +25,8 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 cd-gpios = <&gpio3 13 0>; 30 cd-gpios = <&gpio3 13 0>;
29 status = "okay"; 31 status = "okay";
30 }; 32 };
@@ -35,32 +37,46 @@
35 }; 37 };
36 38
37 esdhc@50020000 { /* ESDHC3 */ 39 esdhc@50020000 { /* ESDHC3 */
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_esdhc3_1>;
38 cd-gpios = <&gpio3 11 0>; 42 cd-gpios = <&gpio3 11 0>;
39 wp-gpios = <&gpio3 12 0>; 43 wp-gpios = <&gpio3 12 0>;
40 status = "okay"; 44 status = "okay";
41 }; 45 };
42 }; 46 };
43 47
44 wdog@53f98000 { /* WDOG1 */
45 status = "okay";
46 };
47
48 iomuxc@53fa8000 { 48 iomuxc@53fa8000 {
49 compatible = "fsl,imx53-iomuxc-qsb"; 49 pinctrl-names = "default";
50 reg = <0x53fa8000 0x4000>; 50 pinctrl-0 = <&pinctrl_hog>;
51
52 hog {
53 pinctrl_hog: hoggrp {
54 fsl,pins = <
55 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
56 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
57 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
58 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
59 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
64 >;
65 };
66 };
51 }; 67 };
52 68
53 uart1: serial@53fbc000 { 69 uart1: serial@53fbc000 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_uart1_1>;
54 status = "okay"; 72 status = "okay";
55 }; 73 };
56 }; 74 };
57 75
58 aips@60000000 { /* AIPS2 */ 76 aips@60000000 { /* AIPS2 */
59 sdma@63fb0000 {
60 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
61 };
62
63 i2c@63fc4000 { /* I2C2 */ 77 i2c@63fc4000 { /* I2C2 */
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_i2c2_1>;
64 status = "okay"; 80 status = "okay";
65 81
66 sgtl5000: codec@0a { 82 sgtl5000: codec@0a {
@@ -72,6 +88,8 @@
72 }; 88 };
73 89
74 i2c@63fc8000 { /* I2C1 */ 90 i2c@63fc8000 { /* I2C1 */
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_i2c1_1>;
75 status = "okay"; 93 status = "okay";
76 94
77 accelerometer: mma8450@1c { 95 accelerometer: mma8450@1c {
@@ -158,10 +176,14 @@
158 }; 176 };
159 177
160 audmux@63fd0000 { 178 audmux@63fd0000 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_audmux_1>;
161 status = "okay"; 181 status = "okay";
162 }; 182 };
163 183
164 ethernet@63fec000 { 184 ethernet@63fec000 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_fec_1>;
165 phy-mode = "rmii"; 187 phy-mode = "rmii";
166 phy-reset-gpios = <&gpio7 6 0>; 188 phy-reset-gpios = <&gpio7 6 0>;
167 status = "okay"; 189 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 08091029168e..06c68580c842 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -25,22 +25,30 @@
25 aips@50000000 { /* AIPS1 */ 25 aips@50000000 { /* AIPS1 */
26 spba@50000000 { 26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */ 27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
28 cd-gpios = <&gpio3 13 0>; 30 cd-gpios = <&gpio3 13 0>;
29 wp-gpios = <&gpio4 11 0>; 31 wp-gpios = <&gpio4 11 0>;
30 status = "okay"; 32 status = "okay";
31 }; 33 };
32 34
33 esdhc@50008000 { /* ESDHC2 */ 35 esdhc@50008000 { /* ESDHC2 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc2_1>;
34 non-removable; 38 non-removable;
35 status = "okay"; 39 status = "okay";
36 }; 40 };
37 41
38 uart3: serial@5000c000 { 42 uart3: serial@5000c000 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_uart3_1>;
39 fsl,uart-has-rtscts; 45 fsl,uart-has-rtscts;
40 status = "okay"; 46 status = "okay";
41 }; 47 };
42 48
43 ecspi@50010000 { /* ECSPI1 */ 49 ecspi@50010000 { /* ECSPI1 */
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_ecspi1_1>;
44 fsl,spi-num-chipselects = <2>; 52 fsl,spi-num-chipselects = <2>;
45 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; 53 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
46 status = "okay"; 54 status = "okay";
@@ -72,35 +80,49 @@
72 }; 80 };
73 81
74 esdhc@50020000 { /* ESDHC3 */ 82 esdhc@50020000 { /* ESDHC3 */
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_esdhc3_1>;
75 non-removable; 85 non-removable;
76 status = "okay"; 86 status = "okay";
77 }; 87 };
78 }; 88 };
79 89
80 wdog@53f98000 { /* WDOG1 */
81 status = "okay";
82 };
83
84 iomuxc@53fa8000 { 90 iomuxc@53fa8000 {
85 compatible = "fsl,imx53-iomuxc-smd"; 91 pinctrl-names = "default";
86 reg = <0x53fa8000 0x4000>; 92 pinctrl-0 = <&pinctrl_hog>;
93
94 hog {
95 pinctrl_hog: hoggrp {
96 fsl,pins = <
97 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
98 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
99 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
100 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
101 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
102 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
103 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
104 >;
105 };
106 };
87 }; 107 };
88 108
89 uart1: serial@53fbc000 { 109 uart1: serial@53fbc000 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_uart1_1>;
90 status = "okay"; 112 status = "okay";
91 }; 113 };
92 114
93 uart2: serial@53fc0000 { 115 uart2: serial@53fc0000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2_1>;
94 status = "okay"; 118 status = "okay";
95 }; 119 };
96 }; 120 };
97 121
98 aips@60000000 { /* AIPS2 */ 122 aips@60000000 { /* AIPS2 */
99 sdma@63fb0000 {
100 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
101 };
102
103 i2c@63fc4000 { /* I2C2 */ 123 i2c@63fc4000 { /* I2C2 */
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c2_1>;
104 status = "okay"; 126 status = "okay";
105 127
106 codec: sgtl5000@0a { 128 codec: sgtl5000@0a {
@@ -120,6 +142,8 @@
120 }; 142 };
121 143
122 i2c@63fc8000 { /* I2C1 */ 144 i2c@63fc8000 { /* I2C1 */
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c1_1>;
123 status = "okay"; 147 status = "okay";
124 148
125 accelerometer: mma8450@1c { 149 accelerometer: mma8450@1c {
@@ -139,6 +163,8 @@
139 }; 163 };
140 164
141 ethernet@63fec000 { 165 ethernet@63fec000 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_fec_1>;
142 phy-mode = "rmii"; 168 phy-mode = "rmii";
143 phy-reset-gpios = <&gpio7 6 0>; 169 phy-reset-gpios = <&gpio7 6 0>;
144 status = "okay"; 170 status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165edce5..221cf3321b0a 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
135 }; 135 };
136 }; 136 };
137 137
138 usb@53f80000 {
139 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
140 reg = <0x53f80000 0x0200>;
141 interrupts = <18>;
142 status = "disabled";
143 };
144
145 usb@53f80200 {
146 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
147 reg = <0x53f80200 0x0200>;
148 interrupts = <14>;
149 status = "disabled";
150 };
151
152 usb@53f80400 {
153 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
154 reg = <0x53f80400 0x0200>;
155 interrupts = <16>;
156 status = "disabled";
157 };
158
159 usb@53f80600 {
160 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
161 reg = <0x53f80600 0x0200>;
162 interrupts = <17>;
163 status = "disabled";
164 };
165
138 gpio1: gpio@53f84000 { 166 gpio1: gpio@53f84000 {
139 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 167 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
140 reg = <0x53f84000 0x4000>; 168 reg = <0x53f84000 0x4000>;
@@ -179,7 +207,6 @@
179 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 207 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
180 reg = <0x53f98000 0x4000>; 208 reg = <0x53f98000 0x4000>;
181 interrupts = <58>; 209 interrupts = <58>;
182 status = "disabled";
183 }; 210 };
184 211
185 wdog@53f9c000 { /* WDOG2 */ 212 wdog@53f9c000 { /* WDOG2 */
@@ -189,6 +216,161 @@
189 status = "disabled"; 216 status = "disabled";
190 }; 217 };
191 218
219 iomuxc@53fa8000 {
220 compatible = "fsl,imx53-iomuxc";
221 reg = <0x53fa8000 0x4000>;
222
223 audmux {
224 pinctrl_audmux_1: audmuxgrp-1 {
225 fsl,pins = <
226 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
227 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
228 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
229 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
230 >;
231 };
232 };
233
234 fec {
235 pinctrl_fec_1: fecgrp-1 {
236 fsl,pins = <
237 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
238 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
239 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
240 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
241 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
242 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
243 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
244 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
245 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
246 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
247 >;
248 };
249 };
250
251 ecspi1 {
252 pinctrl_ecspi1_1: ecspi1grp-1 {
253 fsl,pins = <
254 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
255 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
256 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
257 >;
258 };
259 };
260
261 esdhc1 {
262 pinctrl_esdhc1_1: esdhc1grp-1 {
263 fsl,pins = <
264 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
265 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
266 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
267 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
268 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
269 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
270 >;
271 };
272
273 pinctrl_esdhc1_2: esdhc1grp-2 {
274 fsl,pins = <
275 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
276 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
277 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
278 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
279 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
280 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
281 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
282 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
283 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
284 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
285 >;
286 };
287 };
288
289 esdhc2 {
290 pinctrl_esdhc2_1: esdhc2grp-1 {
291 fsl,pins = <
292 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
293 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
294 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
295 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
296 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
297 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
298 >;
299 };
300 };
301
302 esdhc3 {
303 pinctrl_esdhc3_1: esdhc3grp-1 {
304 fsl,pins = <
305 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
306 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
307 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
308 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
309 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
310 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
311 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
312 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
313 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
314 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
315 >;
316 };
317 };
318
319 i2c1 {
320 pinctrl_i2c1_1: i2c1grp-1 {
321 fsl,pins = <
322 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
323 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
324 >;
325 };
326 };
327
328 i2c2 {
329 pinctrl_i2c2_1: i2c2grp-1 {
330 fsl,pins = <
331 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
332 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
333 >;
334 };
335 };
336
337 uart1 {
338 pinctrl_uart1_1: uart1grp-1 {
339 fsl,pins = <
340 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
341 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
342 >;
343 };
344
345 pinctrl_uart1_2: uart1grp-2 {
346 fsl,pins = <
347 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
348 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
349 >;
350 };
351 };
352
353 uart2 {
354 pinctrl_uart2_1: uart2grp-1 {
355 fsl,pins = <
356 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
357 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
358 >;
359 };
360 };
361
362 uart3 {
363 pinctrl_uart3_1: uart3grp-1 {
364 fsl,pins = <
365 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
366 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
367 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
368 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
369 >;
370 };
371 };
372 };
373
192 uart1: serial@53fbc000 { 374 uart1: serial@53fbc000 {
193 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 375 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
194 reg = <0x53fbc000 0x4000>; 376 reg = <0x53fbc000 0x4000>;
@@ -203,6 +385,20 @@
203 status = "disabled"; 385 status = "disabled";
204 }; 386 };
205 387
388 can1: can@53fc8000 {
389 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
390 reg = <0x53fc8000 0x4000>;
391 interrupts = <82>;
392 status = "disabled";
393 };
394
395 can2: can@53fcc000 {
396 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
397 reg = <0x53fcc000 0x4000>;
398 interrupts = <83>;
399 status = "disabled";
400 };
401
206 gpio5: gpio@53fdc000 { 402 gpio5: gpio@53fdc000 {
207 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
208 reg = <0x53fdc000 0x4000>; 404 reg = <0x53fdc000 0x4000>;
@@ -277,6 +473,7 @@
277 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 473 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
278 reg = <0x63fb0000 0x4000>; 474 reg = <0x63fb0000 0x4000>;
279 interrupts = <6>; 475 interrupts = <6>;
476 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
280 }; 477 };
281 478
282 cspi@63fc0000 { 479 cspi@63fc0000 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d792581672cc..15df4c105e89 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -28,8 +28,27 @@
28 status = "disabled"; /* gpmi nand conflicts with SD */ 28 status = "disabled"; /* gpmi nand conflicts with SD */
29 }; 29 };
30 30
31 aips-bus@02000000 { /* AIPS1 */
32 iomuxc@020e0000 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_hog>;
35
36 hog {
37 pinctrl_hog: hoggrp {
38 fsl,pins = <
39 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
40 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
41 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
42 >;
43 };
44 };
45 };
46 };
47
31 aips-bus@02100000 { /* AIPS2 */ 48 aips-bus@02100000 { /* AIPS2 */
32 ethernet@02188000 { 49 ethernet@02188000 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_enet_2>;
33 phy-mode = "rgmii"; 52 phy-mode = "rgmii";
34 status = "okay"; 53 status = "okay";
35 }; 54 };
@@ -52,6 +71,8 @@
52 }; 71 };
53 72
54 uart4: serial@021f0000 { 73 uart4: serial@021f0000 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_uart4_1>;
55 status = "okay"; 76 status = "okay";
56 }; 77 };
57 }; 78 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index cfdbe539c43e..0fb29ca7a9e1 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -46,15 +46,20 @@
46 46
47 iomuxc@020e0000 { 47 iomuxc@020e0000 {
48 pinctrl-names = "default"; 48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpio_hog>; 49 pinctrl-0 = <&pinctrl_hog>;
50 50
51 gpios { 51 hog {
52 pinctrl_gpio_hog: gpiohog { 52 pinctrl_hog: hoggrp {
53 fsl,pins = < 53 fsl,pins = <
54 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ 54 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
55 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ 55 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
56 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ 56 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
57 >; 57 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
58 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
59 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
60 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
61 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
62 >;
58 }; 63 };
59 }; 64 };
60 }; 65 };
@@ -71,12 +76,16 @@
71 }; 76 };
72 77
73 ethernet@02188000 { 78 ethernet@02188000 {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_enet_1>;
74 phy-mode = "rgmii"; 81 phy-mode = "rgmii";
75 phy-reset-gpios = <&gpio3 23 0>; 82 phy-reset-gpios = <&gpio3 23 0>;
76 status = "okay"; 83 status = "okay";
77 }; 84 };
78 85
79 usdhc@02198000 { /* uSDHC3 */ 86 usdhc@02198000 { /* uSDHC3 */
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_usdhc3_2>;
80 cd-gpios = <&gpio7 0 0>; 89 cd-gpios = <&gpio7 0 0>;
81 wp-gpios = <&gpio7 1 0>; 90 wp-gpios = <&gpio7 1 0>;
82 vmmc-supply = <&reg_3p3v>; 91 vmmc-supply = <&reg_3p3v>;
@@ -84,6 +93,8 @@
84 }; 93 };
85 94
86 usdhc@0219c000 { /* uSDHC4 */ 95 usdhc@0219c000 { /* uSDHC4 */
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usdhc4_2>;
87 cd-gpios = <&gpio2 6 0>; 98 cd-gpios = <&gpio2 6 0>;
88 wp-gpios = <&gpio2 7 0>; 99 wp-gpios = <&gpio2 7 0>;
89 vmmc-supply = <&reg_3p3v>; 100 vmmc-supply = <&reg_3p3v>;
@@ -99,7 +110,7 @@
99 uart2: serial@021e8000 { 110 uart2: serial@021e8000 {
100 status = "okay"; 111 status = "okay";
101 pinctrl-names = "default"; 112 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_serial2_1>; 113 pinctrl-0 = <&pinctrl_uart2_1>;
103 }; 114 };
104 115
105 i2c@021a0000 { /* I2C1 */ 116 i2c@021a0000 { /* I2C1 */
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 07509a181178..e596c28c214d 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -22,28 +22,51 @@
22 }; 22 };
23 23
24 soc { 24 soc {
25
26 aips-bus@02000000 { /* AIPS1 */ 25 aips-bus@02000000 { /* AIPS1 */
27 spba-bus@02000000 { 26 spba-bus@02000000 {
28 uart1: serial@02020000 { 27 uart1: serial@02020000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_uart1_1>;
29 status = "okay"; 30 status = "okay";
30 }; 31 };
31 }; 32 };
33
34 iomuxc@020e0000 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_hog>;
37
38 hog {
39 pinctrl_hog: hoggrp {
40 fsl,pins = <
41 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
42 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
43 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
44 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
45 >;
46 };
47 };
48 };
32 }; 49 };
33 50
34 aips-bus@02100000 { /* AIPS2 */ 51 aips-bus@02100000 { /* AIPS2 */
35 ethernet@02188000 { 52 ethernet@02188000 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_enet_1>;
36 phy-mode = "rgmii"; 55 phy-mode = "rgmii";
37 status = "okay"; 56 status = "okay";
38 }; 57 };
39 58
40 usdhc@02194000 { /* uSDHC2 */ 59 usdhc@02194000 { /* uSDHC2 */
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_usdhc2_1>;
41 cd-gpios = <&gpio2 2 0>; 62 cd-gpios = <&gpio2 2 0>;
42 wp-gpios = <&gpio2 3 0>; 63 wp-gpios = <&gpio2 3 0>;
43 status = "okay"; 64 status = "okay";
44 }; 65 };
45 66
46 usdhc@02198000 { /* uSDHC3 */ 67 usdhc@02198000 { /* uSDHC3 */
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_usdhc3_1>;
47 cd-gpios = <&gpio2 0 0>; 70 cd-gpios = <&gpio2 0 0>;
48 wp-gpios = <&gpio2 1 0>; 71 wp-gpios = <&gpio2 1 0>;
49 status = "okay"; 72 status = "okay";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 925da33420e2..e45476dc6d32 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -383,7 +383,6 @@
383 reg = <0x020bc000 0x4000>; 383 reg = <0x020bc000 0x4000>;
384 interrupts = <0 80 0x04>; 384 interrupts = <0 80 0x04>;
385 clocks = <&clks 0>; 385 clocks = <&clks 0>;
386 status = "disabled";
387 }; 386 };
388 387
389 wdog@020c0000 { /* WDOG2 */ 388 wdog@020c0000 { /* WDOG2 */
@@ -539,86 +538,199 @@
539 /* shared pinctrl settings */ 538 /* shared pinctrl settings */
540 audmux { 539 audmux {
541 pinctrl_audmux_1: audmux-1 { 540 pinctrl_audmux_1: audmux-1 {
542 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ 541 fsl,pins = <
543 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ 542 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
544 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ 543 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
545 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ 544 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
545 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
546 >;
547 };
548 };
549
550 ecspi1 {
551 pinctrl_ecspi1_1: ecspi1grp-1 {
552 fsl,pins = <
553 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
554 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
555 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
556 >;
557 };
558 };
559
560 enet {
561 pinctrl_enet_1: enetgrp-1 {
562 fsl,pins = <
563 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
564 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
565 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
566 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
567 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
568 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
569 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
570 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
571 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
572 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
573 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
574 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
575 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
576 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
577 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
578 >;
579 };
580
581 pinctrl_enet_2: enetgrp-2 {
582 fsl,pins = <
583 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
584 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
585 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
586 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
587 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
588 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
589 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
590 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
591 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
592 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
593 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
594 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
595 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
596 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
597 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
598 >;
546 }; 599 };
547 }; 600 };
548 601
549 gpmi-nand { 602 gpmi-nand {
550 pinctrl_gpmi_nand_1: gpmi-nand-1 { 603 pinctrl_gpmi_nand_1: gpmi-nand-1 {
551 fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ 604 fsl,pins = <
552 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ 605 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
553 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ 606 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
554 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ 607 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
555 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ 608 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
556 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ 609 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
557 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ 610 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
558 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ 611 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
559 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ 612 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
560 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ 613 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
561 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ 614 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
562 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ 615 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
563 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ 616 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
564 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ 617 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
565 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ 618 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
566 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ 619 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
567 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ 620 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
568 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ 621 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
569 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ 622 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
623 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
624 >;
570 }; 625 };
571 }; 626 };
572 627
573 i2c1 { 628 i2c1 {
574 pinctrl_i2c1_1: i2c1grp-1 { 629 pinctrl_i2c1_1: i2c1grp-1 {
575 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ 630 fsl,pins = <
576 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */ 631 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
632 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
633 >;
577 }; 634 };
578 }; 635 };
579 636
580 serial2 { 637 uart1 {
581 pinctrl_serial2_1: serial2grp-1 { 638 pinctrl_uart1_1: uart1grp-1 {
582 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ 639 fsl,pins = <
583 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */ 640 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
641 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
642 >;
643 };
644 };
645
646 uart2 {
647 pinctrl_uart2_1: uart2grp-1 {
648 fsl,pins = <
649 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
650 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
651 >;
652 };
653 };
654
655 uart4 {
656 pinctrl_uart4_1: uart4grp-1 {
657 fsl,pins = <
658 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
659 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
660 >;
661 };
662 };
663
664 usdhc2 {
665 pinctrl_usdhc2_1: usdhc2grp-1 {
666 fsl,pins = <
667 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
668 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
669 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
670 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
671 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
672 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
673 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
674 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
675 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
676 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
677 >;
584 }; 678 };
585 }; 679 };
586 680
587 usdhc3 { 681 usdhc3 {
588 pinctrl_usdhc3_1: usdhc3grp-1 { 682 pinctrl_usdhc3_1: usdhc3grp-1 {
589 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ 683 fsl,pins = <
590 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ 684 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
591 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ 685 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
592 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ 686 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
593 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ 687 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
594 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ 688 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
595 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ 689 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
596 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ 690 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
597 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ 691 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
598 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ 692 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
693 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
694 >;
695 };
696
697 pinctrl_usdhc3_2: usdhc3grp-2 {
698 fsl,pins = <
699 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
700 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
701 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
702 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
703 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
704 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
705 >;
599 }; 706 };
600 }; 707 };
601 708
602 usdhc4 { 709 usdhc4 {
603 pinctrl_usdhc4_1: usdhc4grp-1 { 710 pinctrl_usdhc4_1: usdhc4grp-1 {
604 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ 711 fsl,pins = <
605 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ 712 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
606 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ 713 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
607 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ 714 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
608 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ 715 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
609 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ 716 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
610 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ 717 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
611 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ 718 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
612 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ 719 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
613 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ 720 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
721 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
722 >;
614 }; 723 };
615 };
616 724
617 ecspi1 { 725 pinctrl_usdhc4_2: usdhc4grp-2 {
618 pinctrl_ecspi1_1: ecspi1grp-1 { 726 fsl,pins = <
619 fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ 727 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
620 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ 728 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
621 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ 729 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
730 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
731 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
732 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
733 >;
622 }; 734 };
623 }; 735 };
624 }; 736 };
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 3c9f32f9b6b4..565132d02105 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y
32CONFIG_MACH_IMX51_DT=y 32CONFIG_MACH_IMX51_DT=y
33CONFIG_MACH_MX51_3DS=y 33CONFIG_MACH_MX51_3DS=y
34CONFIG_MACH_EUKREA_CPUIMX51SD=y 34CONFIG_MACH_EUKREA_CPUIMX51SD=y
35CONFIG_MACH_MX51_EFIKAMX=y 35CONFIG_SOC_IMX53=y
36CONFIG_MACH_MX51_EFIKASB=y
37CONFIG_MACH_IMX53_DT=y
38CONFIG_SOC_IMX6Q=y 36CONFIG_SOC_IMX6Q=y
39CONFIG_MXC_PWM=y 37CONFIG_MXC_PWM=y
40CONFIG_SMP=y 38CONFIG_SMP=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542ad6f97..7ca5fe45945f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -101,13 +101,8 @@ config SOC_IMX51
101 select SOC_IMX5 101 select SOC_IMX5
102 select ARCH_MX5 102 select ARCH_MX5
103 select ARCH_MX51 103 select ARCH_MX51
104 104 select PINCTRL
105config SOC_IMX53 105 select PINCTRL_IMX51
106 bool
107 select SOC_IMX5
108 select ARCH_MX5
109 select ARCH_MX53
110 select HAVE_CAN_FLEXCAN if CAN
111 106
112if ARCH_IMX_V4_V5 107if ARCH_IMX_V4_V5
113 108
@@ -561,7 +556,6 @@ config MACH_BUG
561config MACH_IMX31_DT 556config MACH_IMX31_DT
562 bool "Support i.MX31 platforms from device tree" 557 bool "Support i.MX31 platforms from device tree"
563 select SOC_IMX31 558 select SOC_IMX31
564 select USE_OF
565 help 559 help
566 Include support for Freescale i.MX31 based platforms 560 Include support for Freescale i.MX31 based platforms
567 using the device tree for discovery. 561 using the device tree for discovery.
@@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
737 731
738endchoice 732endchoice
739 733
740config MX51_EFIKA_COMMON 734comment "Device tree only"
741 bool
742 select SOC_IMX51
743 select IMX_HAVE_PLATFORM_IMX_UART
744 select IMX_HAVE_PLATFORM_MXC_EHCI
745 select IMX_HAVE_PLATFORM_PATA_IMX
746 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
747 select IMX_HAVE_PLATFORM_SPI_IMX
748 select MXC_ULPI if USB_ULPI
749
750config MACH_MX51_EFIKAMX
751 bool "Support MX51 Genesi Efika MX nettop"
752 select LEDS_GPIO_REGISTER
753 select MX51_EFIKA_COMMON
754 help
755 Include support for Genesi Efika MX nettop. This includes specific
756 configurations for the board and its peripherals.
757
758config MACH_MX51_EFIKASB
759 bool "Support MX51 Genesi Efika Smartbook"
760 select LEDS_GPIO_REGISTER
761 select MX51_EFIKA_COMMON
762 help
763 Include support for Genesi Efika Smartbook. This includes specific
764 configurations for the board and its peripherals.
765
766comment "i.MX53 machines:"
767
768config MACH_IMX53_DT
769 bool "Support i.MX53 platforms from device tree"
770 select SOC_IMX53
771 select MACH_MX53_ARD
772 select MACH_MX53_EVK
773 select MACH_MX53_LOCO
774 select MACH_MX53_SMD
775 help
776 Include support for Freescale i.MX53 based platforms
777 using the device tree for discovery
778
779config MACH_MX53_EVK
780 bool "Support MX53 EVK platforms"
781 select SOC_IMX53
782 select IMX_HAVE_PLATFORM_IMX2_WDT
783 select IMX_HAVE_PLATFORM_IMX_UART
784 select IMX_HAVE_PLATFORM_IMX_I2C
785 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
786 select IMX_HAVE_PLATFORM_SPI_IMX
787 select LEDS_GPIO_REGISTER
788 help
789 Include support for MX53 EVK platform. This includes specific
790 configurations for the board and its peripherals.
791
792config MACH_MX53_SMD
793 bool "Support MX53 SMD platforms"
794 select SOC_IMX53
795 select IMX_HAVE_PLATFORM_IMX2_WDT
796 select IMX_HAVE_PLATFORM_IMX_I2C
797 select IMX_HAVE_PLATFORM_IMX_UART
798 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
799 help
800 Include support for MX53 SMD platform. This includes specific
801 configurations for the board and its peripherals.
802 735
803config MACH_MX53_LOCO 736config SOC_IMX53
804 bool "Support MX53 LOCO platforms" 737 bool "i.MX53 support"
805 select SOC_IMX53 738 select SOC_IMX5
806 select IMX_HAVE_PLATFORM_IMX2_WDT 739 select ARCH_MX5
807 select IMX_HAVE_PLATFORM_IMX_I2C 740 select ARCH_MX53
808 select IMX_HAVE_PLATFORM_IMX_UART 741 select HAVE_CAN_FLEXCAN if CAN
809 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 742 select PINCTRL
810 select IMX_HAVE_PLATFORM_GPIO_KEYS 743 select PINCTRL_IMX53
811 select LEDS_GPIO_REGISTER
812 help
813 Include support for MX53 LOCO platform. This includes specific
814 configurations for the board and its peripherals.
815 744
816config MACH_MX53_ARD
817 bool "Support MX53 ARD platforms"
818 select SOC_IMX53
819 select IMX_HAVE_PLATFORM_IMX2_WDT
820 select IMX_HAVE_PLATFORM_IMX_I2C
821 select IMX_HAVE_PLATFORM_IMX_UART
822 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
823 select IMX_HAVE_PLATFORM_GPIO_KEYS
824 help 745 help
825 Include support for MX53 ARD platform. This includes specific 746 This enables support for Freescale i.MX53 processor.
826 configurations for the board and its peripherals.
827
828comment "i.MX6 family:"
829 747
830config SOC_IMX6Q 748config SOC_IMX6Q
831 bool "i.MX6 Quad support" 749 bool "i.MX6 Quad support"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 07f7c226e4cf..58dc7c67d606 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -83,16 +83,9 @@ endif
83# i.MX5 based machines 83# i.MX5 based machines
84obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o 84obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
85obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o 85obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
86obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
87obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
88obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
89obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
90obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o 86obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
91obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o 87obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
92obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
93obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
94obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
95obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o 88obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
96 89
97obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 90obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
98obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o 91obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 05541cf4a878..c60967629e27 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
39initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 39initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
40 40
41dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb 41dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
42dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ 42
43 imx53-qsb.dtb imx53-smd.dtb 43dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \
44 imx53-evk.dtb \
45 imx53-qsb.dtb \
46 imx53-smd.dtb \
47
44dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ 48dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
45 imx6q-sabrelite.dtb \ 49 imx6q-sabrelite.dtb \
46 imx6q-sabresd.dtb \ 50 imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
deleted file mode 100644
index 77e0db96c448..000000000000
--- a/arch/arm/mach-imx/devices-imx53.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <mach/mx53.h>
9#include <mach/devices-common.h>
10
11extern const struct imx_fec_data imx53_fec_data;
12#define imx53_add_fec(pdata) \
13 imx_add_fec(&imx53_fec_data, pdata)
14
15extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
16#define imx53_add_imx_uart(id, pdata) \
17 imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
18
19
20extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
21#define imx53_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
23
24extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
25#define imx53_add_sdhci_esdhc_imx(id, pdata) \
26 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
27
28extern const struct imx_spi_imx_data imx53_ecspi_data[];
29#define imx53_add_ecspi(id, pdata) \
30 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
31
32extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
33#define imx53_add_imx2_wdt(id) \
34 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
35
36extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
37#define imx53_add_imx_ssi(id, pdata) \
38 imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
39
40extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
41#define imx53_add_imx_keypad(pdata) \
42 imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
43
44extern const struct imx_pata_imx_data imx53_pata_imx_data;
45#define imx53_add_pata_imx() \
46 imx_add_pata_imx(&imx53_pata_imx_data)
47
48extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h
deleted file mode 100644
index 014aa985faae..000000000000
--- a/arch/arm/mach-imx/efika.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _EFIKA_H
2#define _EFIKA_H
3
4#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
5#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
6#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
7
8void __init efika_board_common_init(void);
9
10#endif
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index d4067fe36357..f233b4bb2342 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -13,7 +13,6 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/of_irq.h> 14#include <linux/of_irq.h>
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16#include <linux/pinctrl/machine.h>
17#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
18#include <asm/mach/time.h> 17#include <asm/mach/time.h>
19#include <mach/common.h> 18#include <mach/common.h>
@@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
44 { /* sentinel */ } 43 { /* sentinel */ }
45}; 44};
46 45
47static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
48 { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
49 { /* sentinel */ }
50};
51
52static void __init imx51_dt_init(void) 46static void __init imx51_dt_init(void)
53{ 47{
54 struct device_node *node;
55 const struct of_device_id *of_id;
56 void (*func)(void);
57
58 pinctrl_provide_dummies();
59
60 node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
61 if (node) {
62 of_id = of_match_node(imx51_iomuxc_of_match, node);
63 func = of_id->data;
64 func();
65 of_node_put(node);
66 }
67
68 of_platform_populate(NULL, of_default_bus_match_table, 48 of_platform_populate(NULL, of_default_bus_match_table,
69 imx51_auxdata_lookup, NULL); 49 imx51_auxdata_lookup, NULL);
70} 50}
@@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = {
79}; 59};
80 60
81static const char *imx51_dt_board_compat[] __initdata = { 61static const char *imx51_dt_board_compat[] __initdata = {
82 "fsl,imx51-babbage",
83 "fsl,imx51", 62 "fsl,imx51",
84 NULL 63 NULL
85}; 64};
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c
index 1b7a2fc36591..29711e95579f 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -17,7 +17,6 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <linux/of_platform.h> 19#include <linux/of_platform.h>
20#include <linux/pinctrl/machine.h>
21#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
22#include <asm/mach/time.h> 21#include <asm/mach/time.h>
23#include <mach/common.h> 22#include <mach/common.h>
@@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
51 { /* sentinel */ } 50 { /* sentinel */ }
52}; 51};
53 52
54static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
55 { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
56 { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
57 { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
58 { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
59 { /* sentinel */ }
60};
61
62static void __init imx53_qsb_init(void) 53static void __init imx53_qsb_init(void)
63{ 54{
64 struct clk *clk; 55 struct clk *clk;
@@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void)
74 65
75static void __init imx53_dt_init(void) 66static void __init imx53_dt_init(void)
76{ 67{
77 struct device_node *node;
78 const struct of_device_id *of_id;
79 void (*func)(void);
80
81 pinctrl_provide_dummies();
82
83 node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
84 if (node) {
85 of_id = of_match_node(imx53_iomuxc_of_match, node);
86 func = of_id->data;
87 func();
88 of_node_put(node);
89 }
90
91 if (of_machine_is_compatible("fsl,imx53-qsb")) 68 if (of_machine_is_compatible("fsl,imx53-qsb"))
92 imx53_qsb_init(); 69 imx53_qsb_init();
93 70
@@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = {
105}; 82};
106 83
107static const char *imx53_dt_board_compat[] __initdata = { 84static const char *imx53_dt_board_compat[] __initdata = {
108 "fsl,imx53-ard",
109 "fsl,imx53-evk",
110 "fsl,imx53-qsb",
111 "fsl,imx53-smd",
112 "fsl,imx53", 85 "fsl,imx53",
113 NULL 86 NULL
114}; 87};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 0b30aa8799d2..715029ec7abf 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -22,7 +22,6 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/of_irq.h> 23#include <linux/of_irq.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/phy.h> 25#include <linux/phy.h>
27#include <linux/micrel_phy.h> 26#include <linux/micrel_phy.h>
28#include <linux/mfd/anatop.h> 27#include <linux/mfd/anatop.h>
@@ -158,12 +157,6 @@ static void __init imx6q_usb_init(void)
158 157
159static void __init imx6q_init_machine(void) 158static void __init imx6q_init_machine(void)
160{ 159{
161 /*
162 * This should be removed when all imx6q boards have pinctrl
163 * states for devices defined in device tree.
164 */
165 pinctrl_provide_dummies();
166
167 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 160 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
168 imx6q_sabrelite_init(); 161 imx6q_sabrelite_init();
169 162
@@ -217,9 +210,6 @@ static struct sys_timer imx6q_timer = {
217}; 210};
218 211
219static const char *imx6q_dt_compat[] __initdata = { 212static const char *imx6q_dt_compat[] __initdata = {
220 "fsl,imx6q-arm2",
221 "fsl,imx6q-sabrelite",
222 "fsl,imx6q-sabresd",
223 "fsl,imx6q", 213 "fsl,imx6q",
224 NULL, 214 NULL,
225}; 215};
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
deleted file mode 100644
index 8d09c0126cab..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30
31#include <mach/common.h>
32#include <mach/hardware.h>
33#include <mach/iomux-mx51.h>
34
35#include <asm/setup.h>
36#include <asm/system_info.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40
41#include "devices-imx51.h"
42#include "efika.h"
43
44#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
45#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
46#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
47
48#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
49#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
50#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
51
52#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
53
54/* board 1.1 doesn't have same reset gpio */
55#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
56#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
57
58#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13)
59
60#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
61
62/* the pci ids pin have pull up. they're driven low according to board id */
63#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
64#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
66#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
67
68static iomux_v3_cfg_t mx51efikamx_pads[] = {
69 /* board id */
70 MX51_PAD_PCBID0,
71 MX51_PAD_PCBID1,
72 MX51_PAD_PCBID2,
73
74 /* leds */
75 MX51_PAD_CSI1_D9__GPIO3_13,
76 MX51_PAD_CSI1_VSYNC__GPIO3_14,
77 MX51_PAD_CSI1_HSYNC__GPIO3_15,
78
79 /* power key */
80 MX51_PAD_PWRKEY,
81
82 /* reset */
83 MX51_PAD_DI1_PIN13__GPIO3_2,
84 MX51_PAD_GPIO1_4__GPIO1_4,
85
86 /* power off */
87 MX51_PAD_CSI2_VSYNC__GPIO4_13,
88};
89
90/* PCBID2 PCBID1 PCBID0 STATE
91 1 1 1 ER1:rev1.1
92 1 1 0 ER2:rev1.2
93 1 0 1 ER3:rev1.3
94 1 0 0 ER4:rev1.4
95*/
96static void __init mx51_efikamx_board_id(void)
97{
98 int id;
99
100 /* things are taking time to settle */
101 msleep(150);
102
103 gpio_request(EFIKAMX_PCBID0, "pcbid0");
104 gpio_direction_input(EFIKAMX_PCBID0);
105 gpio_request(EFIKAMX_PCBID1, "pcbid1");
106 gpio_direction_input(EFIKAMX_PCBID1);
107 gpio_request(EFIKAMX_PCBID2, "pcbid2");
108 gpio_direction_input(EFIKAMX_PCBID2);
109
110 id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
111 id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
112 id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
113
114 switch (id) {
115 case 7:
116 system_rev = 0x11;
117 break;
118 case 6:
119 system_rev = 0x12;
120 break;
121 case 5:
122 system_rev = 0x13;
123 break;
124 case 4:
125 system_rev = 0x14;
126 break;
127 default:
128 system_rev = 0x10;
129 break;
130 }
131
132 if ((system_rev == 0x10)
133 || (system_rev == 0x12)
134 || (system_rev == 0x14)) {
135 printk(KERN_WARNING
136 "EfikaMX: Unsupported board revision 1.%u!\n",
137 system_rev & 0xf);
138 }
139}
140
141static struct gpio_led mx51_efikamx_leds[] __initdata = {
142 {
143 .name = "efikamx:green",
144 .default_trigger = "default-on",
145 .gpio = EFIKAMX_GREEN_LED,
146 },
147 {
148 .name = "efikamx:red",
149 .default_trigger = "ide-disk",
150 .gpio = EFIKAMX_RED_LED,
151 },
152 {
153 .name = "efikamx:blue",
154 .default_trigger = "mmc0",
155 .gpio = EFIKAMX_BLUE_LED,
156 },
157};
158
159static const struct gpio_led_platform_data
160 mx51_efikamx_leds_data __initconst = {
161 .leds = mx51_efikamx_leds,
162 .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
163};
164
165static struct esdhc_platform_data sd_pdata = {
166 .cd_type = ESDHC_CD_CONTROLLER,
167 .wp_type = ESDHC_WP_CONTROLLER,
168};
169
170static struct gpio_keys_button mx51_efikamx_powerkey[] = {
171 {
172 .code = KEY_POWER,
173 .gpio = EFIKAMX_POWER_KEY,
174 .type = EV_PWR,
175 .desc = "Power Button (CM)",
176 .wakeup = 1,
177 .debounce_interval = 10, /* ms */
178 },
179};
180
181static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
182 .buttons = mx51_efikamx_powerkey,
183 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
184};
185
186static void mx51_efikamx_restart(char mode, const char *cmd)
187{
188 if (system_rev == 0x11)
189 gpio_direction_output(EFIKAMX_RESET1_1, 0);
190 else
191 gpio_direction_output(EFIKAMX_RESET, 0);
192}
193
194static struct regulator *pwgt1, *pwgt2, *coincell;
195
196static void mx51_efikamx_power_off(void)
197{
198 if (!IS_ERR(coincell))
199 regulator_disable(coincell);
200
201 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
202 regulator_disable(pwgt2);
203 regulator_disable(pwgt1);
204 }
205 gpio_direction_output(EFIKAMX_POWEROFF, 1);
206}
207
208static int __init mx51_efikamx_power_init(void)
209{
210 pwgt1 = regulator_get(NULL, "pwgt1");
211 pwgt2 = regulator_get(NULL, "pwgt2");
212 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
213 regulator_enable(pwgt1);
214 regulator_enable(pwgt2);
215 }
216 gpio_request(EFIKAMX_POWEROFF, "poweroff");
217 pm_power_off = mx51_efikamx_power_off;
218
219 /* enable coincell charger. maybe need a small power driver ? */
220 coincell = regulator_get(NULL, "coincell");
221 if (!IS_ERR(coincell)) {
222 regulator_set_voltage(coincell, 3000000, 3000000);
223 regulator_enable(coincell);
224 }
225
226 regulator_has_full_constraints();
227
228 return 0;
229}
230
231static void __init mx51_efikamx_init_late(void)
232{
233 imx51_init_late();
234 mx51_efikamx_power_init();
235}
236
237static void __init mx51_efikamx_init(void)
238{
239 imx51_soc_init();
240
241 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
242 ARRAY_SIZE(mx51efikamx_pads));
243 efika_board_common_init();
244
245 mx51_efikamx_board_id();
246
247 /* on < 1.2 boards both SD controllers are used */
248 if (system_rev < 0x12) {
249 imx51_add_sdhci_esdhc_imx(0, NULL);
250 imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
251 mx51_efikamx_leds[2].default_trigger = "mmc1";
252 } else
253 imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
254
255 gpio_led_register_device(-1, &mx51_efikamx_leds_data);
256 imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
257
258 if (system_rev == 0x11) {
259 gpio_request(EFIKAMX_RESET1_1, "reset");
260 gpio_direction_output(EFIKAMX_RESET1_1, 1);
261 } else {
262 gpio_request(EFIKAMX_RESET, "reset");
263 gpio_direction_output(EFIKAMX_RESET, 1);
264 }
265
266 /*
267 * enable wifi by default only on mx
268 * sb and mx have same wlan pin but the value to enable it are
269 * different :/
270 */
271 gpio_request(EFIKA_WLAN_EN, "wlan_en");
272 gpio_direction_output(EFIKA_WLAN_EN, 0);
273 msleep(10);
274
275 gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
276 gpio_direction_output(EFIKA_WLAN_RESET, 0);
277 msleep(10);
278 gpio_set_value(EFIKA_WLAN_RESET, 1);
279}
280
281static void __init mx51_efikamx_timer_init(void)
282{
283 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
284}
285
286static struct sys_timer mx51_efikamx_timer = {
287 .init = mx51_efikamx_timer_init,
288};
289
290MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
291 .atag_offset = 0x100,
292 .map_io = mx51_map_io,
293 .init_early = imx51_init_early,
294 .init_irq = mx51_init_irq,
295 .handle_irq = imx51_handle_irq,
296 .timer = &mx51_efikamx_timer,
297 .init_machine = mx51_efikamx_init,
298 .init_late = mx51_efikamx_init_late,
299 .restart = mx51_efikamx_restart,
300MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
deleted file mode 100644
index fdbd181b97ef..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32#include <mach/ulpi.h>
33
34#include <mach/common.h>
35#include <mach/hardware.h>
36#include <mach/iomux-mx51.h>
37
38#include <asm/setup.h>
39#include <asm/system_info.h>
40#include <asm/mach-types.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/time.h>
43
44#include "devices-imx51.h"
45#include "efika.h"
46
47#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
48#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3)
49#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25)
50#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28)
51#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29)
52#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31)
53#define EFIKASB_LID IMX_GPIO_NR(3, 14)
54#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13)
55#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1)
56
57#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
58#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
59
60static iomux_v3_cfg_t mx51efikasb_pads[] = {
61 /* USB HOST2 */
62 MX51_PAD_EIM_D16__USBH2_DATA0,
63 MX51_PAD_EIM_D17__USBH2_DATA1,
64 MX51_PAD_EIM_D18__USBH2_DATA2,
65 MX51_PAD_EIM_D19__USBH2_DATA3,
66 MX51_PAD_EIM_D20__USBH2_DATA4,
67 MX51_PAD_EIM_D21__USBH2_DATA5,
68 MX51_PAD_EIM_D22__USBH2_DATA6,
69 MX51_PAD_EIM_D23__USBH2_DATA7,
70 MX51_PAD_EIM_A24__USBH2_CLK,
71 MX51_PAD_EIM_A25__USBH2_DIR,
72 MX51_PAD_EIM_A26__USBH2_STP,
73 MX51_PAD_EIM_A27__USBH2_NXT,
74
75 /* leds */
76 MX51_PAD_EIM_CS0__GPIO2_25,
77 MX51_PAD_GPIO1_3__GPIO1_3,
78
79 /* pcb id */
80 MX51_PAD_EIM_CS3__GPIO2_28,
81 MX51_PAD_EIM_CS4__GPIO2_29,
82
83 /* lid */
84 MX51_PAD_CSI1_VSYNC__GPIO3_14,
85
86 /* power key*/
87 MX51_PAD_PWRKEY,
88
89 /* wifi/bt button */
90 MX51_PAD_DI1_PIN12__GPIO3_1,
91
92 /* power off */
93 MX51_PAD_CSI2_VSYNC__GPIO4_13,
94
95 /* wdog reset */
96 MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
97
98 /* BT */
99 MX51_PAD_EIM_A17__GPIO2_11,
100
101 MX51_PAD_SD1_CD,
102};
103
104static int initialize_usbh2_port(struct platform_device *pdev)
105{
106 iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
107 iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
108
109 mxc_iomux_v3_setup_pad(usbh2gpio);
110 gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
111 gpio_direction_output(EFIKASB_USBH2_STP, 0);
112 msleep(1);
113 gpio_set_value(EFIKASB_USBH2_STP, 1);
114 msleep(1);
115
116 gpio_free(EFIKASB_USBH2_STP);
117 mxc_iomux_v3_setup_pad(usbh2stp);
118
119 mdelay(10);
120
121 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
122}
123
124static struct mxc_usbh_platform_data usbh2_config __initdata = {
125 .init = initialize_usbh2_port,
126 .portsc = MXC_EHCI_MODE_ULPI,
127};
128
129static void __init mx51_efikasb_usb(void)
130{
131 usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
132 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
133 if (usbh2_config.otg)
134 imx51_add_mxc_ehci_hs(2, &usbh2_config);
135}
136
137static const struct gpio_led mx51_efikasb_leds[] __initconst = {
138 {
139 .name = "efikasb:green",
140 .default_trigger = "default-on",
141 .gpio = EFIKASB_GREEN_LED,
142 .active_low = 1,
143 },
144 {
145 .name = "efikasb:white",
146 .default_trigger = "caps",
147 .gpio = EFIKASB_WHITE_LED,
148 },
149};
150
151static const struct gpio_led_platform_data
152 mx51_efikasb_leds_data __initconst = {
153 .leds = mx51_efikasb_leds,
154 .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
155};
156
157static struct gpio_keys_button mx51_efikasb_keys[] = {
158 {
159 .code = KEY_POWER,
160 .gpio = EFIKASB_PWRKEY,
161 .type = EV_KEY,
162 .desc = "Power Button",
163 .wakeup = 1,
164 .active_low = 1,
165 },
166 {
167 .code = SW_LID,
168 .gpio = EFIKASB_LID,
169 .type = EV_SW,
170 .desc = "Lid Switch",
171 .active_low = 1,
172 },
173 {
174 .code = KEY_RFKILL,
175 .gpio = EFIKASB_RFKILL,
176 .type = EV_KEY,
177 .desc = "rfkill",
178 .active_low = 1,
179 },
180};
181
182static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
183 .buttons = mx51_efikasb_keys,
184 .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
185};
186
187static struct esdhc_platform_data sd0_pdata = {
188#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27)
189 .cd_gpio = EFIKASB_SD1_CD,
190 .cd_type = ESDHC_CD_GPIO,
191 .wp_type = ESDHC_WP_CONTROLLER,
192};
193
194static struct esdhc_platform_data sd1_pdata = {
195 .cd_type = ESDHC_CD_CONTROLLER,
196 .wp_type = ESDHC_WP_CONTROLLER,
197};
198
199static struct regulator *pwgt1, *pwgt2;
200
201static void mx51_efikasb_power_off(void)
202{
203 gpio_set_value(EFIKA_USB_PHY_RESET, 0);
204
205 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
206 regulator_disable(pwgt2);
207 regulator_disable(pwgt1);
208 }
209 gpio_direction_output(EFIKASB_POWEROFF, 1);
210}
211
212static int __init mx51_efikasb_power_init(void)
213{
214 pwgt1 = regulator_get(NULL, "pwgt1");
215 pwgt2 = regulator_get(NULL, "pwgt2");
216 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
217 regulator_enable(pwgt1);
218 regulator_enable(pwgt2);
219 }
220 gpio_request(EFIKASB_POWEROFF, "poweroff");
221 pm_power_off = mx51_efikasb_power_off;
222
223 regulator_has_full_constraints();
224
225 return 0;
226}
227
228static void __init mx51_efikasb_init_late(void)
229{
230 imx51_init_late();
231 mx51_efikasb_power_init();
232}
233
234/* 01 R1.3 board
235 10 R2.0 board */
236static void __init mx51_efikasb_board_id(void)
237{
238 int id;
239
240 gpio_request(EFIKASB_PCBID0, "pcb id0");
241 gpio_direction_input(EFIKASB_PCBID0);
242 gpio_request(EFIKASB_PCBID1, "pcb id1");
243 gpio_direction_input(EFIKASB_PCBID1);
244
245 id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
246 id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
247
248 switch (id) {
249 default:
250 break;
251 case 1:
252 system_rev = 0x13;
253 break;
254 case 2:
255 system_rev = 0x20;
256 break;
257 }
258}
259
260static void __init efikasb_board_init(void)
261{
262 imx51_soc_init();
263
264 mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
265 ARRAY_SIZE(mx51efikasb_pads));
266 efika_board_common_init();
267
268 mx51_efikasb_board_id();
269 mx51_efikasb_usb();
270 imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
271 imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
272
273 gpio_led_register_device(-1, &mx51_efikasb_leds_data);
274 imx_add_gpio_keys(&mx51_efikasb_keys_data);
275}
276
277static void __init mx51_efikasb_timer_init(void)
278{
279 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
280}
281
282static struct sys_timer mx51_efikasb_timer = {
283 .init = mx51_efikasb_timer_init,
284};
285
286MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
287 .atag_offset = 0x100,
288 .map_io = mx51_map_io,
289 .init_early = imx51_init_early,
290 .init_irq = mx51_init_irq,
291 .handle_irq = imx51_handle_irq,
292 .init_machine = efikasb_board_init,
293 .init_late = mx51_efikasb_init_late,
294 .timer = &mx51_efikasb_timer,
295 .restart = mxc_restart,
296MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
deleted file mode 100644
index 6c28e65f424d..000000000000
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/smsc911x.h>
26#include <linux/regulator/machine.h>
27#include <linux/regulator/fixed.h>
28
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx53.h>
32
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
37#include "devices-imx53.h"
38
39#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
40#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
41#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
42#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
43#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
44#define ARD_HOME IMX_GPIO_NR(5, 10)
45#define ARD_BACK IMX_GPIO_NR(5, 11)
46#define ARD_PROG IMX_GPIO_NR(5, 12)
47#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
48
49static iomux_v3_cfg_t mx53_ard_pads[] = {
50 /* UART1 */
51 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
52 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
53 /* WEIM for CS1 */
54 MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
55 MX53_PAD_EIM_D16__EMI_WEIM_D_16,
56 MX53_PAD_EIM_D17__EMI_WEIM_D_17,
57 MX53_PAD_EIM_D18__EMI_WEIM_D_18,
58 MX53_PAD_EIM_D19__EMI_WEIM_D_19,
59 MX53_PAD_EIM_D20__EMI_WEIM_D_20,
60 MX53_PAD_EIM_D21__EMI_WEIM_D_21,
61 MX53_PAD_EIM_D22__EMI_WEIM_D_22,
62 MX53_PAD_EIM_D23__EMI_WEIM_D_23,
63 MX53_PAD_EIM_D24__EMI_WEIM_D_24,
64 MX53_PAD_EIM_D25__EMI_WEIM_D_25,
65 MX53_PAD_EIM_D26__EMI_WEIM_D_26,
66 MX53_PAD_EIM_D27__EMI_WEIM_D_27,
67 MX53_PAD_EIM_D28__EMI_WEIM_D_28,
68 MX53_PAD_EIM_D29__EMI_WEIM_D_29,
69 MX53_PAD_EIM_D30__EMI_WEIM_D_30,
70 MX53_PAD_EIM_D31__EMI_WEIM_D_31,
71 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
72 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
73 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
74 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
75 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
76 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
77 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
78 MX53_PAD_EIM_OE__EMI_WEIM_OE,
79 MX53_PAD_EIM_RW__EMI_WEIM_RW,
80 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
81 /* SDHC1 */
82 MX53_PAD_SD1_CMD__ESDHC1_CMD,
83 MX53_PAD_SD1_CLK__ESDHC1_CLK,
84 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
85 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
86 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
87 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
88 MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
89 MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
90 MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
91 MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
92 MX53_PAD_GPIO_1__GPIO1_1,
93 MX53_PAD_GPIO_9__GPIO1_9,
94 /* I2C2 */
95 MX53_PAD_EIM_EB2__I2C2_SCL,
96 MX53_PAD_KEY_ROW3__I2C2_SDA,
97 /* I2C3 */
98 MX53_PAD_GPIO_3__I2C3_SCL,
99 MX53_PAD_GPIO_16__I2C3_SDA,
100 /* GPIO */
101 MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
102 MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
103 MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
104 MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
105 MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
106};
107
108#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
109{ \
110 .gpio = gpio_num, \
111 .type = EV_KEY, \
112 .code = ev_code, \
113 .active_low = act_low, \
114 .desc = "btn " descr, \
115 .wakeup = wake, \
116}
117
118static struct gpio_keys_button ard_buttons[] = {
119 GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
120 GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
121 GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
122 GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
123 GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
124};
125
126static const struct gpio_keys_platform_data ard_button_data __initconst = {
127 .buttons = ard_buttons,
128 .nbuttons = ARRAY_SIZE(ard_buttons),
129};
130
131static struct resource ard_smsc911x_resources[] = {
132 {
133 .start = MX53_CS1_64MB_BASE_ADDR,
134 .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
135 .flags = IORESOURCE_MEM,
136 },
137 {
138 /* irq number is run-time assigned */
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143struct smsc911x_platform_config ard_smsc911x_config = {
144 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
145 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
146 .flags = SMSC911X_USE_32BIT,
147};
148
149static struct platform_device ard_smsc_lan9220_device = {
150 .name = "smsc911x",
151 .id = -1,
152 .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
153 .resource = ard_smsc911x_resources,
154 .dev = {
155 .platform_data = &ard_smsc911x_config,
156 },
157};
158
159static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
160 .cd_gpio = ARD_SD1_CD,
161 .wp_gpio = ARD_SD1_WP,
162};
163
164static struct imxi2c_platform_data mx53_ard_i2c2_data = {
165 .bitrate = 50000,
166};
167
168static struct imxi2c_platform_data mx53_ard_i2c3_data = {
169 .bitrate = 400000,
170};
171
172static void __init mx53_ard_io_init(void)
173{
174 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
175 gpio_direction_input(ARD_ETHERNET_INT_B);
176
177 gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
178 gpio_direction_output(ARD_I2CPORTEXP_B, 1);
179}
180
181/* Config CS1 settings for ethernet controller */
182static int weim_cs_config(void)
183{
184 u32 reg;
185 void __iomem *weim_base, *iomuxc_base;
186
187 weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
188 if (!weim_base)
189 return -ENOMEM;
190
191 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
192 if (!iomuxc_base) {
193 iounmap(weim_base);
194 return -ENOMEM;
195 }
196
197 /* CS1 timings for LAN9220 */
198 writel(0x20001, (weim_base + 0x18));
199 writel(0x0, (weim_base + 0x1C));
200 writel(0x16000202, (weim_base + 0x20));
201 writel(0x00000002, (weim_base + 0x24));
202 writel(0x16002082, (weim_base + 0x28));
203 writel(0x00000000, (weim_base + 0x2C));
204 writel(0x00000000, (weim_base + 0x90));
205
206 /* specify 64 MB on CS1 and CS0 on GPR1 */
207 reg = readl(iomuxc_base + 0x4);
208 reg &= ~0x3F;
209 reg |= 0x1B;
210 writel(reg, (iomuxc_base + 0x4));
211
212 iounmap(iomuxc_base);
213 iounmap(weim_base);
214
215 return 0;
216}
217
218static struct regulator_consumer_supply dummy_supplies[] = {
219 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
220 REGULATOR_SUPPLY("vddvario", "smsc911x"),
221};
222
223void __init imx53_ard_common_init(void)
224{
225 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
226 ARRAY_SIZE(mx53_ard_pads));
227 weim_cs_config();
228}
229
230static struct platform_device *devices[] __initdata = {
231 &ard_smsc_lan9220_device,
232};
233
234static void __init mx53_ard_board_init(void)
235{
236 imx53_soc_init();
237 imx53_add_imx_uart(0, NULL);
238
239 imx53_ard_common_init();
240 mx53_ard_io_init();
241 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
242 ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
243 ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
244 platform_add_devices(devices, ARRAY_SIZE(devices));
245
246 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
247 imx53_add_imx2_wdt(0);
248 imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
249 imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
250 imx_add_gpio_keys(&ard_button_data);
251 imx53_add_ahci_imx();
252}
253
254static void __init mx53_ard_timer_init(void)
255{
256 mx53_clocks_init(32768, 24000000, 22579200, 0);
257}
258
259static struct sys_timer mx53_ard_timer = {
260 .init = mx53_ard_timer_init,
261};
262
263MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
264 .map_io = mx53_map_io,
265 .init_early = imx53_init_early,
266 .init_irq = mx53_init_irq,
267 .handle_irq = imx53_handle_irq,
268 .timer = &mx53_ard_timer,
269 .init_machine = mx53_ard_board_init,
270 .init_late = imx53_init_late,
271 .restart = mxc_restart,
272MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
deleted file mode 100644
index 09fe2197b491..000000000000
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/gpio.h>
26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
28#include <mach/common.h>
29#include <mach/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <mach/iomux-mx53.h>
34
35#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
36#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
37#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
38#define MX53EVK_LED IMX_GPIO_NR(7, 7)
39
40#include "devices-imx53.h"
41
42static iomux_v3_cfg_t mx53_evk_pads[] = {
43 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
44 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
45
46 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
47 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
48 MX53_PAD_PATA_DIOR__UART2_RTS,
49 MX53_PAD_PATA_INTRQ__UART2_CTS,
50
51 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
52 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
53
54 MX53_PAD_EIM_D16__ECSPI1_SCLK,
55 MX53_PAD_EIM_D17__ECSPI1_MISO,
56 MX53_PAD_EIM_D18__ECSPI1_MOSI,
57
58 /* ecspi chip select lines */
59 MX53_PAD_EIM_EB2__GPIO2_30,
60 MX53_PAD_EIM_D19__GPIO3_19,
61 /* LED */
62 MX53_PAD_PATA_DA_1__GPIO7_7,
63};
64
65static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
66 .flags = IMXUART_HAVE_RTSCTS,
67};
68
69static const struct gpio_led mx53evk_leds[] __initconst = {
70 {
71 .name = "green",
72 .default_trigger = "heartbeat",
73 .gpio = MX53EVK_LED,
74 },
75};
76
77static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
78 .leds = mx53evk_leds,
79 .num_leds = ARRAY_SIZE(mx53evk_leds),
80};
81
82static inline void mx53_evk_init_uart(void)
83{
84 imx53_add_imx_uart(0, NULL);
85 imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
86 imx53_add_imx_uart(2, NULL);
87}
88
89static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
90 .bitrate = 100000,
91};
92
93static inline void mx53_evk_fec_reset(void)
94{
95 int ret;
96
97 /* reset FEC PHY */
98 ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
99 "fec-phy-reset");
100 if (ret) {
101 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
102 return;
103 }
104 msleep(1);
105 gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
106}
107
108static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
109 .phy = PHY_INTERFACE_MODE_RMII,
110};
111
112static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
113 {
114 .modalias = "mtd_dataflash",
115 .max_speed_hz = 25000000,
116 .bus_num = 0,
117 .chip_select = 1,
118 .mode = SPI_MODE_0,
119 .platform_data = NULL,
120 },
121};
122
123static int mx53_evk_spi_cs[] = {
124 EVK_ECSPI1_CS0,
125 EVK_ECSPI1_CS1,
126};
127
128static const struct spi_imx_master mx53_evk_spi_data __initconst = {
129 .chipselect = mx53_evk_spi_cs,
130 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
131};
132
133void __init imx53_evk_common_init(void)
134{
135 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
136 ARRAY_SIZE(mx53_evk_pads));
137}
138
139static void __init mx53_evk_board_init(void)
140{
141 imx53_soc_init();
142 imx53_evk_common_init();
143
144 mx53_evk_init_uart();
145 mx53_evk_fec_reset();
146 imx53_add_fec(&mx53_evk_fec_pdata);
147
148 imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
149 imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
150
151 imx53_add_sdhci_esdhc_imx(0, NULL);
152 imx53_add_sdhci_esdhc_imx(1, NULL);
153
154 spi_register_board_info(mx53_evk_spi_board_info,
155 ARRAY_SIZE(mx53_evk_spi_board_info));
156 imx53_add_ecspi(0, &mx53_evk_spi_data);
157 imx53_add_imx2_wdt(0);
158 gpio_led_register_device(-1, &mx53evk_leds_data);
159}
160
161static void __init mx53_evk_timer_init(void)
162{
163 mx53_clocks_init(32768, 24000000, 22579200, 0);
164}
165
166static struct sys_timer mx53_evk_timer = {
167 .init = mx53_evk_timer_init,
168};
169
170MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
171 .map_io = mx53_map_io,
172 .init_early = imx53_init_early,
173 .init_irq = mx53_init_irq,
174 .handle_irq = imx53_handle_irq,
175 .timer = &mx53_evk_timer,
176 .init_machine = mx53_evk_board_init,
177 .init_late = imx53_init_late,
178 .restart = mxc_restart,
179MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
deleted file mode 100644
index 8abe23c1d3c8..000000000000
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/i2c.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx53.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34
35#include "devices-imx53.h"
36
37#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
38#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
39#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
40#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
41#define LOCO_LED IMX_GPIO_NR(7, 7)
42#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
43#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
44#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
45#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14)
46
47static iomux_v3_cfg_t mx53_loco_pads[] = {
48 /* FEC */
49 MX53_PAD_FEC_MDC__FEC_MDC,
50 MX53_PAD_FEC_MDIO__FEC_MDIO,
51 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
52 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
53 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
54 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
55 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
56 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
57 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
58 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
59 /* FEC_nRST */
60 MX53_PAD_PATA_DA_0__GPIO7_6,
61 /* FEC_nINT */
62 MX53_PAD_PATA_DATA4__GPIO2_4,
63 /* AUDMUX5 */
64 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
65 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
66 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
67 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
68 /* I2C1 */
69 MX53_PAD_CSI0_DAT8__I2C1_SDA,
70 MX53_PAD_CSI0_DAT9__I2C1_SCL,
71 MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */
72 /* I2C2 */
73 MX53_PAD_KEY_COL3__I2C2_SCL,
74 MX53_PAD_KEY_ROW3__I2C2_SDA,
75 /* SD1 */
76 MX53_PAD_SD1_CMD__ESDHC1_CMD,
77 MX53_PAD_SD1_CLK__ESDHC1_CLK,
78 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
79 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
80 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
81 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
82 /* SD1_CD */
83 MX53_PAD_EIM_DA13__GPIO3_13,
84 /* SD3 */
85 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
86 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
87 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
88 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
89 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
90 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
91 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
92 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
93 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
94 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
95 /* SD3_CD */
96 MX53_PAD_EIM_DA11__GPIO3_11,
97 /* SD3_WP */
98 MX53_PAD_EIM_DA12__GPIO3_12,
99 /* VGA */
100 MX53_PAD_EIM_OE__IPU_DI1_PIN7,
101 MX53_PAD_EIM_RW__IPU_DI1_PIN8,
102 /* DISPLB */
103 MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
104 MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
105 MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
106 MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
107 /* DISP0_POWER_EN */
108 MX53_PAD_EIM_D24__GPIO3_24,
109 /* DISP0 DET INT */
110 MX53_PAD_EIM_D31__GPIO3_31,
111 /* LVDS */
112 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
113 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
114 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
115 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
116 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
117 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
118 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
119 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
120 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
121 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
122 /* I2C1 */
123 MX53_PAD_CSI0_DAT8__I2C1_SDA,
124 MX53_PAD_CSI0_DAT9__I2C1_SCL,
125 /* UART1 */
126 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
127 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
128 /* CSI0 */
129 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
130 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
131 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
132 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
133 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
134 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
135 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
136 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
137 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
138 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
139 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
140 /* DISPLAY */
141 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
142 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
143 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
144 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
145 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
146 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
147 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
148 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
149 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
150 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
151 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
152 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
153 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
154 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
155 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
156 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
157 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
158 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
159 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
160 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
161 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
162 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
163 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
164 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
165 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
166 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
167 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
168 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
169 /* Audio CLK*/
170 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
171 /* PWM */
172 MX53_PAD_GPIO_1__PWM2_PWMO,
173 /* SPDIF */
174 MX53_PAD_GPIO_7__SPDIF_PLOCK,
175 MX53_PAD_GPIO_17__SPDIF_OUT1,
176 /* GPIO */
177 MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
178 MX53_PAD_PATA_DA_2__GPIO7_8,
179 MX53_PAD_PATA_DATA5__GPIO2_5,
180 MX53_PAD_PATA_DATA6__GPIO2_6,
181 MX53_PAD_PATA_DATA14__GPIO2_14,
182 MX53_PAD_PATA_DATA15__GPIO2_15,
183 MX53_PAD_PATA_INTRQ__GPIO7_2,
184 MX53_PAD_EIM_WAIT__GPIO5_0,
185 MX53_PAD_NANDF_WP_B__GPIO6_9,
186 MX53_PAD_NANDF_RB0__GPIO6_10,
187 MX53_PAD_NANDF_CS1__GPIO6_14,
188 MX53_PAD_NANDF_CS2__GPIO6_15,
189 MX53_PAD_NANDF_CS3__GPIO6_16,
190 MX53_PAD_GPIO_5__GPIO1_5,
191 MX53_PAD_GPIO_16__GPIO7_11,
192 MX53_PAD_GPIO_8__GPIO1_8,
193};
194
195#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
196{ \
197 .gpio = gpio_num, \
198 .type = EV_KEY, \
199 .code = ev_code, \
200 .active_low = act_low, \
201 .desc = "btn " descr, \
202 .wakeup = wake, \
203}
204
205static struct gpio_keys_button loco_buttons[] = {
206 GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
207 GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
208 GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
209};
210
211static const struct gpio_keys_platform_data loco_button_data __initconst = {
212 .buttons = loco_buttons,
213 .nbuttons = ARRAY_SIZE(loco_buttons),
214};
215
216static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
217 .cd_gpio = LOCO_SD1_CD,
218 .cd_type = ESDHC_CD_GPIO,
219 .wp_type = ESDHC_WP_NONE,
220};
221
222static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
223 .cd_gpio = LOCO_SD3_CD,
224 .wp_gpio = LOCO_SD3_WP,
225 .cd_type = ESDHC_CD_GPIO,
226 .wp_type = ESDHC_WP_GPIO,
227};
228
229static inline void mx53_loco_fec_reset(void)
230{
231 int ret;
232
233 /* reset FEC PHY */
234 ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
235 if (ret) {
236 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
237 return;
238 }
239 gpio_direction_output(LOCO_FEC_PHY_RST, 0);
240 msleep(1);
241 gpio_set_value(LOCO_FEC_PHY_RST, 1);
242}
243
244static const struct fec_platform_data mx53_loco_fec_data __initconst = {
245 .phy = PHY_INTERFACE_MODE_RMII,
246};
247
248static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
249 .bitrate = 100000,
250};
251
252static const struct gpio_led mx53loco_leds[] __initconst = {
253 {
254 .name = "green",
255 .default_trigger = "heartbeat",
256 .gpio = LOCO_LED,
257 },
258};
259
260static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
261 .leds = mx53loco_leds,
262 .num_leds = ARRAY_SIZE(mx53loco_leds),
263};
264
265void __init imx53_qsb_common_init(void)
266{
267 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
268 ARRAY_SIZE(mx53_loco_pads));
269}
270
271static struct i2c_board_info mx53loco_i2c_devices[] = {
272 {
273 I2C_BOARD_INFO("mma8450", 0x1C),
274 },
275};
276
277static void __init mx53_loco_board_init(void)
278{
279 int ret;
280 imx53_soc_init();
281 imx53_qsb_common_init();
282
283 imx53_add_imx_uart(0, NULL);
284 mx53_loco_fec_reset();
285 imx53_add_fec(&mx53_loco_fec_data);
286 imx53_add_imx2_wdt(0);
287
288 ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
289 if (ret)
290 pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
291
292 i2c_register_board_info(0, mx53loco_i2c_devices,
293 ARRAY_SIZE(mx53loco_i2c_devices));
294 imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
295 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
296 imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
297 imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
298 imx_add_gpio_keys(&loco_button_data);
299 gpio_led_register_device(-1, &mx53loco_leds_data);
300 imx53_add_ahci_imx();
301}
302
303static void __init mx53_loco_timer_init(void)
304{
305 mx53_clocks_init(32768, 24000000, 0, 0);
306}
307
308static struct sys_timer mx53_loco_timer = {
309 .init = mx53_loco_timer_init,
310};
311
312MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
313 .map_io = mx53_map_io,
314 .init_early = imx53_init_early,
315 .init_irq = mx53_init_irq,
316 .handle_irq = imx53_handle_irq,
317 .timer = &mx53_loco_timer,
318 .init_machine = mx53_loco_board_init,
319 .init_late = imx53_init_late,
320 .restart = mxc_restart,
321MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
deleted file mode 100644
index b15d6a6d3b68..000000000000
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ /dev/null
@@ -1,168 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/iomux-mx53.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33
34#include "devices-imx53.h"
35
36#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
37#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3)
38
39static iomux_v3_cfg_t mx53_smd_pads[] = {
40 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
41 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
42
43 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
44 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
45
46 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
47 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
48 MX53_PAD_PATA_DA_1__UART3_CTS,
49 MX53_PAD_PATA_DA_2__UART3_RTS,
50 /* I2C1 */
51 MX53_PAD_CSI0_DAT8__I2C1_SDA,
52 MX53_PAD_CSI0_DAT9__I2C1_SCL,
53 /* SD1 */
54 MX53_PAD_SD1_CMD__ESDHC1_CMD,
55 MX53_PAD_SD1_CLK__ESDHC1_CLK,
56 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
57 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
58 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
59 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
60 /* SD2 */
61 MX53_PAD_SD2_CMD__ESDHC2_CMD,
62 MX53_PAD_SD2_CLK__ESDHC2_CLK,
63 MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
64 MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
65 MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
66 MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
67 /* SD3 */
68 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
69 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
70 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
71 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
72 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
73 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
74 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
75 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
76 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
77 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
78};
79
80static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
81 .flags = IMXUART_HAVE_RTSCTS,
82};
83
84static inline void mx53_smd_init_uart(void)
85{
86 imx53_add_imx_uart(0, NULL);
87 imx53_add_imx_uart(1, NULL);
88 imx53_add_imx_uart(2, &mx53_smd_uart_data);
89}
90
91static inline void mx53_smd_fec_reset(void)
92{
93 int ret;
94
95 /* reset FEC PHY */
96 ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
97 if (ret) {
98 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
99 return;
100 }
101 gpio_direction_output(SMD_FEC_PHY_RST, 0);
102 msleep(1);
103 gpio_set_value(SMD_FEC_PHY_RST, 1);
104}
105
106static const struct fec_platform_data mx53_smd_fec_data __initconst = {
107 .phy = PHY_INTERFACE_MODE_RMII,
108};
109
110static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
111 .bitrate = 100000,
112};
113
114static inline void mx53_smd_ahci_pwr_on(void)
115{
116 int ret;
117
118 /* Enable SATA PWR */
119 ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
120 GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
121 if (ret) {
122 pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
123 return;
124 }
125}
126
127void __init imx53_smd_common_init(void)
128{
129 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
130 ARRAY_SIZE(mx53_smd_pads));
131}
132
133static void __init mx53_smd_board_init(void)
134{
135 imx53_soc_init();
136 imx53_smd_common_init();
137
138 mx53_smd_init_uart();
139 mx53_smd_fec_reset();
140 imx53_add_fec(&mx53_smd_fec_data);
141 imx53_add_imx2_wdt(0);
142 imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
143 imx53_add_sdhci_esdhc_imx(0, NULL);
144 imx53_add_sdhci_esdhc_imx(1, NULL);
145 imx53_add_sdhci_esdhc_imx(2, NULL);
146 mx53_smd_ahci_pwr_on();
147 imx53_add_ahci_imx();
148}
149
150static void __init mx53_smd_timer_init(void)
151{
152 mx53_clocks_init(32768, 24000000, 22579200, 0);
153}
154
155static struct sys_timer mx53_smd_timer = {
156 .init = mx53_smd_timer_init,
157};
158
159MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
160 .map_io = mx53_map_io,
161 .init_early = imx53_init_early,
162 .init_irq = mx53_init_irq,
163 .handle_irq = imx53_handle_irq,
164 .timer = &mx53_smd_timer,
165 .init_machine = mx53_smd_board_init,
166 .init_late = imx53_init_late,
167 .restart = mxc_restart,
168MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 52d8f534be10..acb0aadb4255 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
128 .script_addrs = &imx51_sdma_script, 128 .script_addrs = &imx51_sdma_script,
129}; 129};
130 130
131static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
132 .ap_2_ap_addr = 642,
133 .app_2_mcu_addr = 683,
134 .mcu_2_app_addr = 747,
135 .uart_2_mcu_addr = 817,
136 .shp_2_mcu_addr = 891,
137 .mcu_2_shp_addr = 960,
138 .uartsh_2_mcu_addr = 1032,
139 .spdif_2_mcu_addr = 1100,
140 .mcu_2_spdif_addr = 1134,
141 .firi_2_mcu_addr = 1193,
142 .mcu_2_firi_addr = 1290,
143};
144
145static struct sdma_platform_data imx53_sdma_pdata __initdata = {
146 .fw_name = "sdma-imx53.bin",
147 .script_addrs = &imx53_sdma_script,
148};
149
150static const struct resource imx50_audmux_res[] __initconst = { 131static const struct resource imx50_audmux_res[] __initconst = {
151 DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), 132 DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
152}; 133};
@@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = {
155 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), 136 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
156}; 137};
157 138
158static const struct resource imx53_audmux_res[] __initconst = {
159 DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
160};
161
162void __init imx50_soc_init(void) 139void __init imx50_soc_init(void)
163{ 140{
164 /* i.mx50 has the i.mx35 type gpio */ 141 /* i.mx50 has the i.mx35 type gpio */
@@ -196,30 +173,6 @@ void __init imx51_soc_init(void)
196 ARRAY_SIZE(imx51_audmux_res)); 173 ARRAY_SIZE(imx51_audmux_res));
197} 174}
198 175
199void __init imx53_soc_init(void)
200{
201 /* i.mx53 has the i.mx35 type gpio */
202 mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
203 mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
204 mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
205 mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
206 mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
207 mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
208 mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
209
210 pinctrl_provide_dummies();
211 /* i.mx53 has the i.mx35 type sdma */
212 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
213
214 /* Setup AIPS registers */
215 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
216 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
217
218 /* i.mx53 has the i.mx31 type audmux */
219 platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
220 ARRAY_SIZE(imx53_audmux_res));
221}
222
223void __init imx51_init_late(void) 176void __init imx51_init_late(void)
224{ 177{
225 mx51_neon_fixup(); 178 mx51_neon_fixup();
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
deleted file mode 100644
index ee870c49bc63..000000000000
--- a/arch/arm/mach-imx/mx51_efika.c
+++ /dev/null
@@ -1,633 +0,0 @@
1/*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20#include <linux/input.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/spi/flash.h>
24#include <linux/spi/spi.h>
25#include <linux/mfd/mc13892.h>
26#include <linux/regulator/machine.h>
27#include <linux/regulator/consumer.h>
28
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx51.h>
32
33#include <linux/usb/otg.h>
34#include <linux/usb/ulpi.h>
35#include <mach/ulpi.h>
36
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41
42#include "devices-imx51.h"
43#include "efika.h"
44#include "cpu_op-mx51.h"
45
46#define MX51_USB_CTRL_1_OFFSET 0x10
47#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
49
50#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
51#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
52
53#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
54#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
55
56#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
57
58static iomux_v3_cfg_t mx51efika_pads[] = {
59 /* UART1 */
60 MX51_PAD_UART1_RXD__UART1_RXD,
61 MX51_PAD_UART1_TXD__UART1_TXD,
62 MX51_PAD_UART1_RTS__UART1_RTS,
63 MX51_PAD_UART1_CTS__UART1_CTS,
64
65 /* SD 1 */
66 MX51_PAD_SD1_CMD__SD1_CMD,
67 MX51_PAD_SD1_CLK__SD1_CLK,
68 MX51_PAD_SD1_DATA0__SD1_DATA0,
69 MX51_PAD_SD1_DATA1__SD1_DATA1,
70 MX51_PAD_SD1_DATA2__SD1_DATA2,
71 MX51_PAD_SD1_DATA3__SD1_DATA3,
72
73 /* SD 2 */
74 MX51_PAD_SD2_CMD__SD2_CMD,
75 MX51_PAD_SD2_CLK__SD2_CLK,
76 MX51_PAD_SD2_DATA0__SD2_DATA0,
77 MX51_PAD_SD2_DATA1__SD2_DATA1,
78 MX51_PAD_SD2_DATA2__SD2_DATA2,
79 MX51_PAD_SD2_DATA3__SD2_DATA3,
80
81 /* SD/MMC WP/CD */
82 MX51_PAD_GPIO1_0__SD1_CD,
83 MX51_PAD_GPIO1_1__SD1_WP,
84 MX51_PAD_GPIO1_7__SD2_WP,
85 MX51_PAD_GPIO1_8__SD2_CD,
86
87 /* spi */
88 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
89 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
90 MX51_PAD_CSPI1_SS0__GPIO4_24,
91 MX51_PAD_CSPI1_SS1__GPIO4_25,
92 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
93 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
94 MX51_PAD_GPIO1_6__GPIO1_6,
95
96 /* USB HOST1 */
97 MX51_PAD_USBH1_CLK__USBH1_CLK,
98 MX51_PAD_USBH1_DIR__USBH1_DIR,
99 MX51_PAD_USBH1_NXT__USBH1_NXT,
100 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
101 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
102 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
103 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
104 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
105 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
106 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
107 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
108
109 /* USB HUB RESET */
110 MX51_PAD_GPIO1_5__GPIO1_5,
111
112 /* WLAN */
113 MX51_PAD_EIM_A22__GPIO2_16,
114 MX51_PAD_EIM_A16__GPIO2_10,
115
116 /* USB PHY RESET */
117 MX51_PAD_EIM_D27__GPIO2_9,
118};
119
120/* Serial ports */
121static const struct imxuart_platform_data uart_pdata = {
122 .flags = IMXUART_HAVE_RTSCTS,
123};
124
125/* This function is board specific as the bit mask for the plldiv will also
126 * be different for other Freescale SoCs, thus a common bitmask is not
127 * possible and cannot get place in /plat-mxc/ehci.c.
128 */
129static int initialize_otg_port(struct platform_device *pdev)
130{
131 u32 v;
132 void __iomem *usb_base;
133 void __iomem *usbother_base;
134 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
135 if (!usb_base)
136 return -ENOMEM;
137 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
138
139 /* Set the PHY clock to 19.2MHz */
140 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
141 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
142 v |= MX51_USB_PLL_DIV_19_2_MHZ;
143 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
144 iounmap(usb_base);
145
146 mdelay(10);
147
148 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
149}
150
151static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
152 .init = initialize_otg_port,
153 .portsc = MXC_EHCI_UTMI_16BIT,
154};
155
156static int initialize_usbh1_port(struct platform_device *pdev)
157{
158 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
159 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
160 u32 v;
161 void __iomem *usb_base;
162 void __iomem *socregs_base;
163
164 mxc_iomux_v3_setup_pad(usbh1gpio);
165 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
166 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
167 msleep(1);
168 gpio_set_value(EFIKAMX_USBH1_STP, 1);
169 msleep(1);
170
171 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
172 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
173
174 /* The clock for the USBH1 ULPI port will come externally */
175 /* from the PHY. */
176 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
177 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
178 socregs_base + MX51_USB_CTRL_1_OFFSET);
179
180 iounmap(usb_base);
181
182 gpio_free(EFIKAMX_USBH1_STP);
183 mxc_iomux_v3_setup_pad(usbh1stp);
184
185 mdelay(10);
186
187 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
188}
189
190static struct mxc_usbh_platform_data usbh1_config __initdata = {
191 .init = initialize_usbh1_port,
192 .portsc = MXC_EHCI_MODE_ULPI,
193};
194
195static void mx51_efika_hubreset(void)
196{
197 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
198 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
199 msleep(1);
200 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
201 msleep(1);
202 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
203}
204
205static void __init mx51_efika_usb(void)
206{
207 mx51_efika_hubreset();
208
209 /* pulling it low, means no USB at all... */
210 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
211 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
212 msleep(1);
213 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
214
215 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
216 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
217
218 imx51_add_mxc_ehci_otg(&dr_utmi_config);
219 if (usbh1_config.otg)
220 imx51_add_mxc_ehci_hs(1, &usbh1_config);
221}
222
223static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
224 {
225 .name = "u-boot",
226 .offset = 0,
227 .size = SZ_256K,
228 },
229 {
230 .name = "config",
231 .offset = MTDPART_OFS_APPEND,
232 .size = SZ_64K,
233 },
234};
235
236static struct flash_platform_data mx51_efika_spi_flash_data = {
237 .name = "spi_flash",
238 .parts = mx51_efika_spi_nor_partitions,
239 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
240 .type = "sst25vf032b",
241};
242
243static struct regulator_consumer_supply sw1_consumers[] = {
244 {
245 .supply = "cpu_vcc",
246 }
247};
248
249static struct regulator_consumer_supply vdig_consumers[] = {
250 /* sgtl5000 */
251 REGULATOR_SUPPLY("VDDA", "1-000a"),
252 REGULATOR_SUPPLY("VDDD", "1-000a"),
253};
254
255static struct regulator_consumer_supply vvideo_consumers[] = {
256 /* sgtl5000 */
257 REGULATOR_SUPPLY("VDDIO", "1-000a"),
258};
259
260static struct regulator_consumer_supply vsd_consumers[] = {
261 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
262 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
263};
264
265static struct regulator_consumer_supply pwgt1_consumer[] = {
266 {
267 .supply = "pwgt1",
268 }
269};
270
271static struct regulator_consumer_supply pwgt2_consumer[] = {
272 {
273 .supply = "pwgt2",
274 }
275};
276
277static struct regulator_consumer_supply coincell_consumer[] = {
278 {
279 .supply = "coincell",
280 }
281};
282
283static struct regulator_init_data sw1_init = {
284 .constraints = {
285 .name = "SW1",
286 .min_uV = 600000,
287 .max_uV = 1375000,
288 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
289 .valid_modes_mask = 0,
290 .always_on = 1,
291 .boot_on = 1,
292 .state_mem = {
293 .uV = 850000,
294 .mode = REGULATOR_MODE_NORMAL,
295 .enabled = 1,
296 },
297 },
298 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
299 .consumer_supplies = sw1_consumers,
300};
301
302static struct regulator_init_data sw2_init = {
303 .constraints = {
304 .name = "SW2",
305 .min_uV = 900000,
306 .max_uV = 1850000,
307 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
308 .always_on = 1,
309 .boot_on = 1,
310 .state_mem = {
311 .uV = 950000,
312 .mode = REGULATOR_MODE_NORMAL,
313 .enabled = 1,
314 },
315 }
316};
317
318static struct regulator_init_data sw3_init = {
319 .constraints = {
320 .name = "SW3",
321 .min_uV = 1100000,
322 .max_uV = 1850000,
323 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
324 .always_on = 1,
325 .boot_on = 1,
326 }
327};
328
329static struct regulator_init_data sw4_init = {
330 .constraints = {
331 .name = "SW4",
332 .min_uV = 1100000,
333 .max_uV = 1850000,
334 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
335 .always_on = 1,
336 .boot_on = 1,
337 }
338};
339
340static struct regulator_init_data viohi_init = {
341 .constraints = {
342 .name = "VIOHI",
343 .boot_on = 1,
344 .always_on = 1,
345 }
346};
347
348static struct regulator_init_data vusb_init = {
349 .constraints = {
350 .name = "VUSB",
351 .boot_on = 1,
352 .always_on = 1,
353 }
354};
355
356static struct regulator_init_data swbst_init = {
357 .constraints = {
358 .name = "SWBST",
359 }
360};
361
362static struct regulator_init_data vdig_init = {
363 .constraints = {
364 .name = "VDIG",
365 .min_uV = 1050000,
366 .max_uV = 1800000,
367 .valid_ops_mask =
368 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
369 .boot_on = 1,
370 .always_on = 1,
371 },
372 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
373 .consumer_supplies = vdig_consumers,
374};
375
376static struct regulator_init_data vpll_init = {
377 .constraints = {
378 .name = "VPLL",
379 .min_uV = 1050000,
380 .max_uV = 1800000,
381 .valid_ops_mask =
382 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
383 .boot_on = 1,
384 .always_on = 1,
385 }
386};
387
388static struct regulator_init_data vusb2_init = {
389 .constraints = {
390 .name = "VUSB2",
391 .min_uV = 2400000,
392 .max_uV = 2775000,
393 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
394 .boot_on = 1,
395 .always_on = 1,
396 }
397};
398
399static struct regulator_init_data vvideo_init = {
400 .constraints = {
401 .name = "VVIDEO",
402 .min_uV = 2775000,
403 .max_uV = 2775000,
404 .valid_ops_mask =
405 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
406 .boot_on = 1,
407 .apply_uV = 1,
408 },
409 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
410 .consumer_supplies = vvideo_consumers,
411};
412
413static struct regulator_init_data vaudio_init = {
414 .constraints = {
415 .name = "VAUDIO",
416 .min_uV = 2300000,
417 .max_uV = 3000000,
418 .valid_ops_mask =
419 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
420 .boot_on = 1,
421 }
422};
423
424static struct regulator_init_data vsd_init = {
425 .constraints = {
426 .name = "VSD",
427 .min_uV = 1800000,
428 .max_uV = 3150000,
429 .valid_ops_mask =
430 REGULATOR_CHANGE_VOLTAGE,
431 .boot_on = 1,
432 },
433 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
434 .consumer_supplies = vsd_consumers,
435};
436
437static struct regulator_init_data vcam_init = {
438 .constraints = {
439 .name = "VCAM",
440 .min_uV = 2500000,
441 .max_uV = 3000000,
442 .valid_ops_mask =
443 REGULATOR_CHANGE_VOLTAGE |
444 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
445 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
446 .boot_on = 1,
447 }
448};
449
450static struct regulator_init_data vgen1_init = {
451 .constraints = {
452 .name = "VGEN1",
453 .min_uV = 1200000,
454 .max_uV = 3150000,
455 .valid_ops_mask =
456 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
457 .boot_on = 1,
458 .always_on = 1,
459 }
460};
461
462static struct regulator_init_data vgen2_init = {
463 .constraints = {
464 .name = "VGEN2",
465 .min_uV = 1200000,
466 .max_uV = 3150000,
467 .valid_ops_mask =
468 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
469 .boot_on = 1,
470 .always_on = 1,
471 }
472};
473
474static struct regulator_init_data vgen3_init = {
475 .constraints = {
476 .name = "VGEN3",
477 .min_uV = 1800000,
478 .max_uV = 2900000,
479 .valid_ops_mask =
480 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
481 .boot_on = 1,
482 .always_on = 1,
483 }
484};
485
486static struct regulator_init_data gpo1_init = {
487 .constraints = {
488 .name = "GPO1",
489 }
490};
491
492static struct regulator_init_data gpo2_init = {
493 .constraints = {
494 .name = "GPO2",
495 }
496};
497
498static struct regulator_init_data gpo3_init = {
499 .constraints = {
500 .name = "GPO3",
501 }
502};
503
504static struct regulator_init_data gpo4_init = {
505 .constraints = {
506 .name = "GPO4",
507 }
508};
509
510static struct regulator_init_data pwgt1_init = {
511 .constraints = {
512 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
513 .boot_on = 1,
514 },
515 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
516 .consumer_supplies = pwgt1_consumer,
517};
518
519static struct regulator_init_data pwgt2_init = {
520 .constraints = {
521 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
522 .boot_on = 1,
523 },
524 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
525 .consumer_supplies = pwgt2_consumer,
526};
527
528static struct regulator_init_data vcoincell_init = {
529 .constraints = {
530 .name = "COINCELL",
531 .min_uV = 3000000,
532 .max_uV = 3000000,
533 .valid_ops_mask =
534 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
535 },
536 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
537 .consumer_supplies = coincell_consumer,
538};
539
540static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
541 { .id = MC13892_SW1, .init_data = &sw1_init },
542 { .id = MC13892_SW2, .init_data = &sw2_init },
543 { .id = MC13892_SW3, .init_data = &sw3_init },
544 { .id = MC13892_SW4, .init_data = &sw4_init },
545 { .id = MC13892_SWBST, .init_data = &swbst_init },
546 { .id = MC13892_VIOHI, .init_data = &viohi_init },
547 { .id = MC13892_VPLL, .init_data = &vpll_init },
548 { .id = MC13892_VDIG, .init_data = &vdig_init },
549 { .id = MC13892_VSD, .init_data = &vsd_init },
550 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
551 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
552 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
553 { .id = MC13892_VCAM, .init_data = &vcam_init },
554 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
555 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
556 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
557 { .id = MC13892_VUSB, .init_data = &vusb_init },
558 { .id = MC13892_GPO1, .init_data = &gpo1_init },
559 { .id = MC13892_GPO2, .init_data = &gpo2_init },
560 { .id = MC13892_GPO3, .init_data = &gpo3_init },
561 { .id = MC13892_GPO4, .init_data = &gpo4_init },
562 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
563 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
564 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
565};
566
567static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
568 .flags = MC13XXX_USE_RTC,
569 .regulators = {
570 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
571 .regulators = mx51_efika_regulators,
572 },
573};
574
575static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
576 {
577 .modalias = "m25p80",
578 .max_speed_hz = 25000000,
579 .bus_num = 0,
580 .chip_select = 1,
581 .platform_data = &mx51_efika_spi_flash_data,
582 .irq = -1,
583 },
584 {
585 .modalias = "mc13892",
586 .max_speed_hz = 1000000,
587 .bus_num = 0,
588 .chip_select = 0,
589 .platform_data = &mx51_efika_mc13892_data,
590 /* irq number is run-time assigned */
591 },
592};
593
594static int mx51_efika_spi_cs[] = {
595 EFIKAMX_SPI_CS0,
596 EFIKAMX_SPI_CS1,
597};
598
599static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
600 .chipselect = mx51_efika_spi_cs,
601 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
602};
603
604void __init efika_board_common_init(void)
605{
606 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
607 ARRAY_SIZE(mx51efika_pads));
608 imx51_add_imx_uart(0, &uart_pdata);
609 mx51_efika_usb();
610
611 /* FIXME: comes from original code. check this. */
612 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
613 sw2_init.constraints.state_mem.uV = 1100000;
614 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
615 sw2_init.constraints.state_mem.uV = 1250000;
616 sw1_init.constraints.state_mem.uV = 1000000;
617 }
618 if (machine_is_mx51_efikasb())
619 vgen1_init.constraints.max_uV = 1200000;
620
621 gpio_request(EFIKAMX_PMIC, "pmic irq");
622 gpio_direction_input(EFIKAMX_PMIC);
623 mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
624 spi_register_board_info(mx51_efika_spi_board_info,
625 ARRAY_SIZE(mx51_efika_spi_board_info));
626 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
627
628 imx51_add_pata_imx();
629
630#if defined(CONFIG_CPU_FREQ_IMX)
631 get_cpu_op = mx51_get_cpu_op;
632#endif
633}
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01b85b9..d697d07a1bf0 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -108,18 +108,21 @@ endmenu
108config CPU_PXA168 108config CPU_PXA168
109 bool 109 bool
110 select CPU_MOHAWK 110 select CPU_MOHAWK
111 select COMMON_CLK
111 help 112 help
112 Select code specific to PXA168 113 Select code specific to PXA168
113 114
114config CPU_PXA910 115config CPU_PXA910
115 bool 116 bool
116 select CPU_MOHAWK 117 select CPU_MOHAWK
118 select COMMON_CLK
117 help 119 help
118 Select code specific to PXA910 120 Select code specific to PXA910
119 121
120config CPU_MMP2 122config CPU_MMP2
121 bool 123 bool
122 select CPU_PJ4 124 select CPU_PJ4
125 select COMMON_CLK
123 help 126 help
124 Select code specific to MMP2. MMP2 is ARMv7 compatible. 127 Select code specific to MMP2. MMP2 is ARMv7 compatible.
125 128
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 13dd1604d951..841847d56032 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,6 +1,5 @@
1obj-y := timer.o 1obj-y := timer.o
2obj-y += irq.o 2obj-y += irq.o
3obj-y += clock.o
4obj-y += rstc.o 3obj-y += rstc.o
5obj-y += prima2.o 4obj-y += prima2.o
6obj-y += rtciobrg.o 5obj-y += rtciobrg.o
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
deleted file mode 100644
index aebad7e565cf..000000000000
--- a/arch/arm/mach-prima2/clock.c
+++ /dev/null
@@ -1,510 +0,0 @@
1/*
2 * Clock tree for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/bitops.h>
11#include <linux/err.h>
12#include <linux/errno.h>
13#include <linux/io.h>
14#include <linux/clkdev.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <asm/mach/map.h>
20#include <mach/map.h>
21
22#define SIRFSOC_CLKC_CLK_EN0 0x0000
23#define SIRFSOC_CLKC_CLK_EN1 0x0004
24#define SIRFSOC_CLKC_REF_CFG 0x0014
25#define SIRFSOC_CLKC_CPU_CFG 0x0018
26#define SIRFSOC_CLKC_MEM_CFG 0x001c
27#define SIRFSOC_CLKC_SYS_CFG 0x0020
28#define SIRFSOC_CLKC_IO_CFG 0x0024
29#define SIRFSOC_CLKC_DSP_CFG 0x0028
30#define SIRFSOC_CLKC_GFX_CFG 0x002c
31#define SIRFSOC_CLKC_MM_CFG 0x0030
32#define SIRFSOC_LKC_LCD_CFG 0x0034
33#define SIRFSOC_CLKC_MMC_CFG 0x0038
34#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
35#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
36#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
37#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
38#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
39#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
40#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
41#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
42#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
43
44#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000)
45
46#define KHZ 1000
47#define MHZ (KHZ * KHZ)
48
49struct clk_ops {
50 unsigned long (*get_rate)(struct clk *clk);
51 long (*round_rate)(struct clk *clk, unsigned long rate);
52 int (*set_rate)(struct clk *clk, unsigned long rate);
53 int (*enable)(struct clk *clk);
54 int (*disable)(struct clk *clk);
55 struct clk *(*get_parent)(struct clk *clk);
56 int (*set_parent)(struct clk *clk, struct clk *parent);
57};
58
59struct clk {
60 struct clk *parent; /* parent clk */
61 unsigned long rate; /* clock rate in Hz */
62 signed char usage; /* clock enable count */
63 signed char enable_bit; /* enable bit: 0 ~ 63 */
64 unsigned short regofs; /* register offset */
65 struct clk_ops *ops; /* clock operation */
66};
67
68static DEFINE_SPINLOCK(clocks_lock);
69
70static inline unsigned long clkc_readl(unsigned reg)
71{
72 return readl(SIRFSOC_CLOCK_VA_BASE + reg);
73}
74
75static inline void clkc_writel(u32 val, unsigned reg)
76{
77 writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
78}
79
80/*
81 * osc_rtc - real time oscillator - 32.768KHz
82 * osc_sys - high speed oscillator - 26MHz
83 */
84
85static struct clk clk_rtc = {
86 .rate = 32768,
87};
88
89static struct clk clk_osc = {
90 .rate = 26 * MHZ,
91};
92
93/*
94 * std pll
95 */
96static unsigned long std_pll_get_rate(struct clk *clk)
97{
98 unsigned long fin = clk_get_rate(clk->parent);
99 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
100 SIRFSOC_CLKC_PLL1_CFG0;
101
102 if (clkc_readl(regcfg2) & BIT(2)) {
103 /* pll bypass mode */
104 clk->rate = fin;
105 } else {
106 /* fout = fin * nf / nr / od */
107 u32 cfg0 = clkc_readl(clk->regofs);
108 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
109 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
110 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
111 WARN_ON(fin % MHZ);
112 clk->rate = fin / MHZ * nf / nr / od * MHZ;
113 }
114
115 return clk->rate;
116}
117
118static int std_pll_set_rate(struct clk *clk, unsigned long rate)
119{
120 unsigned long fin, nf, nr, od, reg;
121
122 /*
123 * fout = fin * nf / (nr * od);
124 * set od = 1, nr = fin/MHz, so fout = nf * MHz
125 */
126
127 nf = rate / MHZ;
128 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
129 return -EINVAL;
130
131 fin = clk_get_rate(clk->parent);
132 BUG_ON(fin < MHZ);
133
134 nr = fin / MHZ;
135 BUG_ON((fin % MHZ) || nr > BIT(6));
136
137 od = 1;
138
139 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
140 clkc_writel(reg, clk->regofs);
141
142 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
143 clkc_writel((nf >> 1) - 1, reg);
144
145 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
146 while (!(clkc_readl(reg) & BIT(6)))
147 cpu_relax();
148
149 clk->rate = 0; /* set to zero will force recalculation */
150 return 0;
151}
152
153static struct clk_ops std_pll_ops = {
154 .get_rate = std_pll_get_rate,
155 .set_rate = std_pll_set_rate,
156};
157
158static struct clk clk_pll1 = {
159 .parent = &clk_osc,
160 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
161 .ops = &std_pll_ops,
162};
163
164static struct clk clk_pll2 = {
165 .parent = &clk_osc,
166 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
167 .ops = &std_pll_ops,
168};
169
170static struct clk clk_pll3 = {
171 .parent = &clk_osc,
172 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
173 .ops = &std_pll_ops,
174};
175
176/*
177 * clock domains - cpu, mem, sys/io
178 */
179
180static struct clk clk_mem;
181
182static struct clk *dmn_get_parent(struct clk *clk)
183{
184 struct clk *clks[] = {
185 &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
186 };
187 u32 cfg = clkc_readl(clk->regofs);
188 WARN_ON((cfg & (BIT(3) - 1)) > 4);
189 return clks[cfg & (BIT(3) - 1)];
190}
191
192static int dmn_set_parent(struct clk *clk, struct clk *parent)
193{
194 const struct clk *clks[] = {
195 &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
196 };
197 u32 cfg = clkc_readl(clk->regofs);
198 int i;
199 for (i = 0; i < ARRAY_SIZE(clks); i++) {
200 if (clks[i] == parent) {
201 cfg &= ~(BIT(3) - 1);
202 clkc_writel(cfg | i, clk->regofs);
203 /* BIT(3) - switching status: 1 - busy, 0 - done */
204 while (clkc_readl(clk->regofs) & BIT(3))
205 cpu_relax();
206 return 0;
207 }
208 }
209 return -EINVAL;
210}
211
212static unsigned long dmn_get_rate(struct clk *clk)
213{
214 unsigned long fin = clk_get_rate(clk->parent);
215 u32 cfg = clkc_readl(clk->regofs);
216 if (cfg & BIT(24)) {
217 /* fcd bypass mode */
218 clk->rate = fin;
219 } else {
220 /*
221 * wait count: bit[19:16], hold count: bit[23:20]
222 */
223 u32 wait = (cfg >> 16) & (BIT(4) - 1);
224 u32 hold = (cfg >> 20) & (BIT(4) - 1);
225
226 clk->rate = fin / (wait + hold + 2);
227 }
228
229 return clk->rate;
230}
231
232static int dmn_set_rate(struct clk *clk, unsigned long rate)
233{
234 unsigned long fin;
235 unsigned ratio, wait, hold, reg;
236 unsigned bits = (clk == &clk_mem) ? 3 : 4;
237
238 fin = clk_get_rate(clk->parent);
239 ratio = fin / rate;
240
241 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
242 return -EINVAL;
243
244 WARN_ON(fin % rate);
245
246 wait = (ratio >> 1) - 1;
247 hold = ratio - wait - 2;
248
249 reg = clkc_readl(clk->regofs);
250 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
251 reg |= (wait << 16) | (hold << 20) | BIT(25);
252 clkc_writel(reg, clk->regofs);
253
254 /* waiting FCD been effective */
255 while (clkc_readl(clk->regofs) & BIT(25))
256 cpu_relax();
257
258 clk->rate = 0; /* set to zero will force recalculation */
259
260 return 0;
261}
262
263/*
264 * cpu clock has no FCD register in Prima2, can only change pll
265 */
266static int cpu_set_rate(struct clk *clk, unsigned long rate)
267{
268 int ret1, ret2;
269 struct clk *cur_parent, *tmp_parent;
270
271 cur_parent = dmn_get_parent(clk);
272 BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
273
274 /* switch to tmp pll before setting parent clock's rate */
275 tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
276 ret1 = dmn_set_parent(clk, tmp_parent);
277 BUG_ON(ret1);
278
279 ret2 = clk_set_rate(cur_parent, rate);
280
281 ret1 = dmn_set_parent(clk, cur_parent);
282
283 clk->rate = 0; /* set to zero will force recalculation */
284
285 return ret2 ? ret2 : ret1;
286}
287
288static struct clk_ops cpu_ops = {
289 .get_parent = dmn_get_parent,
290 .set_parent = dmn_set_parent,
291 .set_rate = cpu_set_rate,
292};
293
294static struct clk clk_cpu = {
295 .parent = &clk_pll1,
296 .regofs = SIRFSOC_CLKC_CPU_CFG,
297 .ops = &cpu_ops,
298};
299
300
301static struct clk_ops msi_ops = {
302 .set_rate = dmn_set_rate,
303 .get_rate = dmn_get_rate,
304 .set_parent = dmn_set_parent,
305 .get_parent = dmn_get_parent,
306};
307
308static struct clk clk_mem = {
309 .parent = &clk_pll2,
310 .regofs = SIRFSOC_CLKC_MEM_CFG,
311 .ops = &msi_ops,
312};
313
314static struct clk clk_sys = {
315 .parent = &clk_pll3,
316 .regofs = SIRFSOC_CLKC_SYS_CFG,
317 .ops = &msi_ops,
318};
319
320static struct clk clk_io = {
321 .parent = &clk_pll3,
322 .regofs = SIRFSOC_CLKC_IO_CFG,
323 .ops = &msi_ops,
324};
325
326/*
327 * on-chip clock sets
328 */
329static struct clk_lookup onchip_clks[] = {
330 {
331 .dev_id = "rtc",
332 .clk = &clk_rtc,
333 }, {
334 .dev_id = "osc",
335 .clk = &clk_osc,
336 }, {
337 .dev_id = "pll1",
338 .clk = &clk_pll1,
339 }, {
340 .dev_id = "pll2",
341 .clk = &clk_pll2,
342 }, {
343 .dev_id = "pll3",
344 .clk = &clk_pll3,
345 }, {
346 .dev_id = "cpu",
347 .clk = &clk_cpu,
348 }, {
349 .dev_id = "mem",
350 .clk = &clk_mem,
351 }, {
352 .dev_id = "sys",
353 .clk = &clk_sys,
354 }, {
355 .dev_id = "io",
356 .clk = &clk_io,
357 },
358};
359
360int clk_enable(struct clk *clk)
361{
362 unsigned long flags;
363
364 if (unlikely(IS_ERR_OR_NULL(clk)))
365 return -EINVAL;
366
367 if (clk->parent)
368 clk_enable(clk->parent);
369
370 spin_lock_irqsave(&clocks_lock, flags);
371 if (!clk->usage++ && clk->ops && clk->ops->enable)
372 clk->ops->enable(clk);
373 spin_unlock_irqrestore(&clocks_lock, flags);
374 return 0;
375}
376EXPORT_SYMBOL(clk_enable);
377
378void clk_disable(struct clk *clk)
379{
380 unsigned long flags;
381
382 if (unlikely(IS_ERR_OR_NULL(clk)))
383 return;
384
385 WARN_ON(!clk->usage);
386
387 spin_lock_irqsave(&clocks_lock, flags);
388 if (--clk->usage == 0 && clk->ops && clk->ops->disable)
389 clk->ops->disable(clk);
390 spin_unlock_irqrestore(&clocks_lock, flags);
391
392 if (clk->parent)
393 clk_disable(clk->parent);
394}
395EXPORT_SYMBOL(clk_disable);
396
397unsigned long clk_get_rate(struct clk *clk)
398{
399 if (unlikely(IS_ERR_OR_NULL(clk)))
400 return 0;
401
402 if (clk->rate)
403 return clk->rate;
404
405 if (clk->ops && clk->ops->get_rate)
406 return clk->ops->get_rate(clk);
407
408 return clk_get_rate(clk->parent);
409}
410EXPORT_SYMBOL(clk_get_rate);
411
412long clk_round_rate(struct clk *clk, unsigned long rate)
413{
414 if (unlikely(IS_ERR_OR_NULL(clk)))
415 return 0;
416
417 if (clk->ops && clk->ops->round_rate)
418 return clk->ops->round_rate(clk, rate);
419
420 return 0;
421}
422EXPORT_SYMBOL(clk_round_rate);
423
424int clk_set_rate(struct clk *clk, unsigned long rate)
425{
426 if (unlikely(IS_ERR_OR_NULL(clk)))
427 return -EINVAL;
428
429 if (!clk->ops || !clk->ops->set_rate)
430 return -EINVAL;
431
432 return clk->ops->set_rate(clk, rate);
433}
434EXPORT_SYMBOL(clk_set_rate);
435
436int clk_set_parent(struct clk *clk, struct clk *parent)
437{
438 int ret;
439 unsigned long flags;
440
441 if (unlikely(IS_ERR_OR_NULL(clk)))
442 return -EINVAL;
443
444 if (!clk->ops || !clk->ops->set_parent)
445 return -EINVAL;
446
447 spin_lock_irqsave(&clocks_lock, flags);
448 ret = clk->ops->set_parent(clk, parent);
449 if (!ret) {
450 parent->usage += clk->usage;
451 clk->parent->usage -= clk->usage;
452 BUG_ON(clk->parent->usage < 0);
453 clk->parent = parent;
454 }
455 spin_unlock_irqrestore(&clocks_lock, flags);
456 return ret;
457}
458EXPORT_SYMBOL(clk_set_parent);
459
460struct clk *clk_get_parent(struct clk *clk)
461{
462 unsigned long flags;
463
464 if (unlikely(IS_ERR_OR_NULL(clk)))
465 return NULL;
466
467 if (!clk->ops || !clk->ops->get_parent)
468 return clk->parent;
469
470 spin_lock_irqsave(&clocks_lock, flags);
471 clk->parent = clk->ops->get_parent(clk);
472 spin_unlock_irqrestore(&clocks_lock, flags);
473 return clk->parent;
474}
475EXPORT_SYMBOL(clk_get_parent);
476
477static void __init sirfsoc_clk_init(void)
478{
479 clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
480}
481
482static struct of_device_id clkc_ids[] = {
483 { .compatible = "sirf,prima2-clkc" },
484 {},
485};
486
487void __init sirfsoc_of_clk_init(void)
488{
489 struct device_node *np;
490 struct resource res;
491 struct map_desc sirfsoc_clkc_iodesc = {
492 .virtual = SIRFSOC_CLOCK_VA_BASE,
493 .type = MT_DEVICE,
494 };
495
496 np = of_find_matching_node(NULL, clkc_ids);
497 if (!np)
498 panic("unable to find compatible clkc node in dtb\n");
499
500 if (of_address_to_resource(np, 0, &res))
501 panic("unable to find clkc range in dtb");
502 of_node_put(np);
503
504 sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
505 sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
506
507 iotable_init(&sirfsoc_clkc_iodesc, 1);
508
509 sirfsoc_clk_init();
510}
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index 8f0429d4b79f..e9a17aebe0d6 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -38,7 +38,6 @@ static const char *prima2cb_dt_match[] __initdata = {
38MACHINE_START(PRIMA2_EVB, "prima2cb") 38MACHINE_START(PRIMA2_EVB, "prima2cb")
39 /* Maintainer: Barry Song <baohua.song@csr.com> */ 39 /* Maintainer: Barry Song <baohua.song@csr.com> */
40 .atag_offset = 0x100, 40 .atag_offset = 0x100,
41 .init_early = sirfsoc_of_clk_init,
42 .map_io = sirfsoc_map_lluart, 41 .map_io = sirfsoc_map_lluart,
43 .init_irq = sirfsoc_of_irq_init, 42 .init_irq = sirfsoc_of_irq_init,
44 .timer = &sirfsoc_timer, 43 .timer = &sirfsoc_timer,
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index f224107de7bc..d95bf252f694 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -21,6 +21,8 @@
21#include <asm/sched_clock.h> 21#include <asm/sched_clock.h>
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23 23
24#include "common.h"
25
24#define SIRFSOC_TIMER_COUNTER_LO 0x0000 26#define SIRFSOC_TIMER_COUNTER_LO 0x0000
25#define SIRFSOC_TIMER_COUNTER_HI 0x0004 27#define SIRFSOC_TIMER_COUNTER_HI 0x0004
26#define SIRFSOC_TIMER_MATCH_0 0x0008 28#define SIRFSOC_TIMER_MATCH_0 0x0008
@@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void)
188static void __init sirfsoc_timer_init(void) 190static void __init sirfsoc_timer_init(void)
189{ 191{
190 unsigned long rate; 192 unsigned long rate;
193 struct clk *clk;
194
195 /* initialize clocking early, we want to set the OS timer */
196 sirfsoc_of_clk_init();
191 197
192 /* timer's input clock is io clock */ 198 /* timer's input clock is io clock */
193 struct clk *clk = clk_get_sys("io", NULL); 199 clk = clk_get_sys("io", NULL);
194 200
195 BUG_ON(IS_ERR(clk)); 201 BUG_ON(IS_ERR(clk));
196 202
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 45868bb43cbd..ff007d15e0ec 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -30,7 +30,6 @@
30#include <linux/ata_platform.h> 30#include <linux/ata_platform.h>
31#include <linux/amba/mmci.h> 31#include <linux/amba/mmci.h>
32#include <linux/gfp.h> 32#include <linux/gfp.h>
33#include <linux/clkdev.h>
34#include <linux/mtd/physmap.h> 33#include <linux/mtd/physmap.h>
35 34
36#include <mach/hardware.h> 35#include <mach/hardware.h>
@@ -226,115 +225,10 @@ struct mmci_platform_data realview_mmc1_plat_data = {
226 .cd_invert = true, 225 .cd_invert = true,
227}; 226};
228 227
229/*
230 * Clock handling
231 */
232static const struct icst_params realview_oscvco_params = {
233 .ref = 24000000,
234 .vco_max = ICST307_VCO_MAX,
235 .vco_min = ICST307_VCO_MIN,
236 .vd_min = 4 + 8,
237 .vd_max = 511 + 8,
238 .rd_min = 1 + 2,
239 .rd_max = 127 + 2,
240 .s2div = icst307_s2div,
241 .idx2s = icst307_idx2s,
242};
243
244static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
245{
246 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
247 u32 val;
248
249 val = readl(clk->vcoreg) & ~0x7ffff;
250 val |= vco.v | (vco.r << 9) | (vco.s << 16);
251
252 writel(0xa05f, sys_lock);
253 writel(val, clk->vcoreg);
254 writel(0, sys_lock);
255}
256
257static const struct clk_ops oscvco_clk_ops = {
258 .round = icst_clk_round,
259 .set = icst_clk_set,
260 .setvco = realview_oscvco_set,
261};
262
263static struct clk oscvco_clk = {
264 .ops = &oscvco_clk_ops,
265 .params = &realview_oscvco_params,
266};
267
268/*
269 * These are fixed clocks.
270 */
271static struct clk ref24_clk = {
272 .rate = 24000000,
273};
274
275static struct clk sp804_clk = {
276 .rate = 1000000,
277};
278
279static struct clk dummy_apb_pclk;
280
281static struct clk_lookup lookups[] = {
282 { /* Bus clock */
283 .con_id = "apb_pclk",
284 .clk = &dummy_apb_pclk,
285 }, { /* UART0 */
286 .dev_id = "dev:uart0",
287 .clk = &ref24_clk,
288 }, { /* UART1 */
289 .dev_id = "dev:uart1",
290 .clk = &ref24_clk,
291 }, { /* UART2 */
292 .dev_id = "dev:uart2",
293 .clk = &ref24_clk,
294 }, { /* UART3 */
295 .dev_id = "fpga:uart3",
296 .clk = &ref24_clk,
297 }, { /* UART3 is on the dev chip in PB1176 */
298 .dev_id = "dev:uart3",
299 .clk = &ref24_clk,
300 }, { /* UART4 only exists in PB1176 */
301 .dev_id = "fpga:uart4",
302 .clk = &ref24_clk,
303 }, { /* KMI0 */
304 .dev_id = "fpga:kmi0",
305 .clk = &ref24_clk,
306 }, { /* KMI1 */
307 .dev_id = "fpga:kmi1",
308 .clk = &ref24_clk,
309 }, { /* MMC0 */
310 .dev_id = "fpga:mmc0",
311 .clk = &ref24_clk,
312 }, { /* CLCD is in the PB1176 and EB DevChip */
313 .dev_id = "dev:clcd",
314 .clk = &oscvco_clk,
315 }, { /* PB:CLCD */
316 .dev_id = "issp:clcd",
317 .clk = &oscvco_clk,
318 }, { /* SSP */
319 .dev_id = "dev:ssp0",
320 .clk = &ref24_clk,
321 }, { /* SP804 timers */
322 .dev_id = "sp804",
323 .clk = &sp804_clk,
324 },
325};
326
327void __init realview_init_early(void) 228void __init realview_init_early(void)
328{ 229{
329 void __iomem *sys = __io_address(REALVIEW_SYS_BASE); 230 void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
330 231
331 if (machine_is_realview_pb1176())
332 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
333 else
334 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
335
336 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
337
338 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); 232 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
339} 233}
340 234
diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h
deleted file mode 100644
index e58d0771b64e..000000000000
--- a/arch/arm/mach-realview/include/mach/clkdev.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#include <plat/clock.h>
5
6struct clk {
7 unsigned long rate;
8 const struct clk_ops *ops;
9 const struct icst_params *params;
10 void __iomem *vcoreg;
11};
12
13#define __clk_get(clk) ({ 1; })
14#define __clk_put(clk) do { } while (0)
15
16#endif
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c5e776..a33e33b76733 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -27,6 +27,7 @@
27#include <linux/amba/mmci.h> 27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h> 28#include <linux/amba/pl022.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/platform_data/clk-realview.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
@@ -414,6 +415,7 @@ static void __init realview_eb_timer_init(void)
414 else 415 else
415 timer_irq = IRQ_EB_TIMER0_1; 416 timer_irq = IRQ_EB_TIMER0_1;
416 417
418 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
417 realview_timer_init(timer_irq); 419 realview_timer_init(timer_irq);
418 realview_eb_twd_init(); 420 realview_eb_twd_init();
419} 421}
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7cafa1a6d..f0298cbc203e 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -29,6 +29,7 @@
29#include <linux/mtd/physmap.h> 29#include <linux/mtd/physmap.h>
30#include <linux/mtd/partitions.h> 30#include <linux/mtd/partitions.h>
31#include <linux/io.h> 31#include <linux/io.h>
32#include <linux/platform_data/clk-realview.h>
32 33
33#include <mach/hardware.h> 34#include <mach/hardware.h>
34#include <asm/irq.h> 35#include <asm/irq.h>
@@ -326,6 +327,7 @@ static void __init realview_pb1176_timer_init(void)
326 timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); 327 timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
327 timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; 328 timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
328 329
330 realview_clk_init(__io_address(REALVIEW_SYS_BASE), true);
329 realview_timer_init(IRQ_DC1176_TIMER0); 331 realview_timer_init(IRQ_DC1176_TIMER0);
330} 332}
331 333
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536e3327..1f019f76f7b5 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -27,6 +27,7 @@
27#include <linux/amba/mmci.h> 27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h> 28#include <linux/amba/pl022.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/platform_data/clk-realview.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
@@ -312,6 +313,7 @@ static void __init realview_pb11mp_timer_init(void)
312 timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); 313 timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
313 timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; 314 timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
314 315
316 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
315 realview_timer_init(IRQ_TC11MP_TIMER0_1); 317 realview_timer_init(IRQ_TC11MP_TIMER0_1);
316 realview_pb11mp_twd_init(); 318 realview_pb11mp_twd_init();
317} 319}
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 59650174e6ed..5032775dbfee 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -27,6 +27,7 @@
27#include <linux/amba/mmci.h> 27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h> 28#include <linux/amba/pl022.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/platform_data/clk-realview.h>
30 31
31#include <asm/irq.h> 32#include <asm/irq.h>
32#include <asm/leds.h> 33#include <asm/leds.h>
@@ -261,6 +262,7 @@ static void __init realview_pba8_timer_init(void)
261 timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); 262 timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE);
262 timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; 263 timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20;
263 264
265 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
264 realview_timer_init(IRQ_PBA8_TIMER0_1); 266 realview_timer_init(IRQ_PBA8_TIMER0_1);
265} 267}
266 268
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605624e9..de64ba0ddb95 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -26,6 +26,7 @@
26#include <linux/amba/mmci.h> 26#include <linux/amba/mmci.h>
27#include <linux/amba/pl022.h> 27#include <linux/amba/pl022.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/platform_data/clk-realview.h>
29 30
30#include <asm/irq.h> 31#include <asm/irq.h>
31#include <asm/leds.h> 32#include <asm/leds.h>
@@ -320,6 +321,7 @@ static void __init realview_pbx_timer_init(void)
320 timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE); 321 timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
321 timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20; 322 timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
322 323
324 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
323 realview_timer_init(IRQ_PBX_TIMER0_1); 325 realview_timer_init(IRQ_PBX_TIMER0_1);
324 realview_pbx_twd_init(); 326 realview_pbx_twd_init();
325} 327}
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c013bbf79cac..2d76e4f9c97e 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
11 select CACHE_L2X0 11 select CACHE_L2X0
12 select PINCTRL 12 select PINCTRL
13 select PINCTRL_NOMADIK 13 select PINCTRL_NOMADIK
14 select COMMON_CLK
14 15
15config UX500_SOC_DB8500 16config UX500_SOC_DB8500
16 bool 17 bool
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086ff9e6c..5691ef679d01 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel, U8500 machine. 2# Makefile for the linux kernel, U8500 machine.
3# 3#
4 4
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := cpu.o devices.o devices-common.o \
6 id.o usb.o timer.o 6 id.o usb.o timer.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o 7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 8obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
deleted file mode 100644
index 8d73b066a18d..000000000000
--- a/arch/arm/mach-ux500/clock.c
+++ /dev/null
@@ -1,715 +0,0 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/list.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/clkdev.h>
17#include <linux/cpufreq.h>
18
19#include <plat/mtu.h>
20#include <mach/hardware.h>
21#include "clock.h"
22
23#ifdef CONFIG_DEBUG_FS
24#include <linux/debugfs.h>
25#include <linux/uaccess.h> /* for copy_from_user */
26static LIST_HEAD(clk_list);
27#endif
28
29#define PRCC_PCKEN 0x00
30#define PRCC_PCKDIS 0x04
31#define PRCC_KCKEN 0x08
32#define PRCC_KCKDIS 0x0C
33
34#define PRCM_YYCLKEN0_MGT_SET 0x510
35#define PRCM_YYCLKEN1_MGT_SET 0x514
36#define PRCM_YYCLKEN0_MGT_CLR 0x518
37#define PRCM_YYCLKEN1_MGT_CLR 0x51C
38#define PRCM_YYCLKEN0_MGT_VAL 0x520
39#define PRCM_YYCLKEN1_MGT_VAL 0x524
40
41#define PRCM_SVAMMDSPCLK_MGT 0x008
42#define PRCM_SIAMMDSPCLK_MGT 0x00C
43#define PRCM_SGACLK_MGT 0x014
44#define PRCM_UARTCLK_MGT 0x018
45#define PRCM_MSP02CLK_MGT 0x01C
46#define PRCM_MSP1CLK_MGT 0x288
47#define PRCM_I2CCLK_MGT 0x020
48#define PRCM_SDMMCCLK_MGT 0x024
49#define PRCM_SLIMCLK_MGT 0x028
50#define PRCM_PER1CLK_MGT 0x02C
51#define PRCM_PER2CLK_MGT 0x030
52#define PRCM_PER3CLK_MGT 0x034
53#define PRCM_PER5CLK_MGT 0x038
54#define PRCM_PER6CLK_MGT 0x03C
55#define PRCM_PER7CLK_MGT 0x040
56#define PRCM_LCDCLK_MGT 0x044
57#define PRCM_BMLCLK_MGT 0x04C
58#define PRCM_HSITXCLK_MGT 0x050
59#define PRCM_HSIRXCLK_MGT 0x054
60#define PRCM_HDMICLK_MGT 0x058
61#define PRCM_APEATCLK_MGT 0x05C
62#define PRCM_APETRACECLK_MGT 0x060
63#define PRCM_MCDECLK_MGT 0x064
64#define PRCM_IPI2CCLK_MGT 0x068
65#define PRCM_DSIALTCLK_MGT 0x06C
66#define PRCM_DMACLK_MGT 0x074
67#define PRCM_B2R2CLK_MGT 0x078
68#define PRCM_TVCLK_MGT 0x07C
69#define PRCM_TCR 0x1C8
70#define PRCM_TCR_STOPPED (1 << 16)
71#define PRCM_TCR_DOZE_MODE (1 << 17)
72#define PRCM_UNIPROCLK_MGT 0x278
73#define PRCM_SSPCLK_MGT 0x280
74#define PRCM_RNGCLK_MGT 0x284
75#define PRCM_UICCCLK_MGT 0x27C
76
77#define PRCM_MGT_ENABLE (1 << 8)
78
79static DEFINE_SPINLOCK(clocks_lock);
80
81static void __clk_enable(struct clk *clk)
82{
83 if (clk->enabled++ == 0) {
84 if (clk->parent_cluster)
85 __clk_enable(clk->parent_cluster);
86
87 if (clk->parent_periph)
88 __clk_enable(clk->parent_periph);
89
90 if (clk->ops && clk->ops->enable)
91 clk->ops->enable(clk);
92 }
93}
94
95int clk_enable(struct clk *clk)
96{
97 unsigned long flags;
98
99 spin_lock_irqsave(&clocks_lock, flags);
100 __clk_enable(clk);
101 spin_unlock_irqrestore(&clocks_lock, flags);
102
103 return 0;
104}
105EXPORT_SYMBOL(clk_enable);
106
107static void __clk_disable(struct clk *clk)
108{
109 if (--clk->enabled == 0) {
110 if (clk->ops && clk->ops->disable)
111 clk->ops->disable(clk);
112
113 if (clk->parent_periph)
114 __clk_disable(clk->parent_periph);
115
116 if (clk->parent_cluster)
117 __clk_disable(clk->parent_cluster);
118 }
119}
120
121void clk_disable(struct clk *clk)
122{
123 unsigned long flags;
124
125 WARN_ON(!clk->enabled);
126
127 spin_lock_irqsave(&clocks_lock, flags);
128 __clk_disable(clk);
129 spin_unlock_irqrestore(&clocks_lock, flags);
130}
131EXPORT_SYMBOL(clk_disable);
132
133/*
134 * The MTU has a separate, rather complex muxing setup
135 * with alternative parents (peripheral cluster or
136 * ULP or fixed 32768 Hz) depending on settings
137 */
138static unsigned long clk_mtu_get_rate(struct clk *clk)
139{
140 void __iomem *addr;
141 u32 tcr;
142 int mtu = (int) clk->data;
143 /*
144 * One of these is selected eventually
145 * TODO: Replace the constant with a reference
146 * to the ULP source once this is modeled.
147 */
148 unsigned long clk32k = 32768;
149 unsigned long mturate;
150 unsigned long retclk;
151
152 if (cpu_is_u8500_family())
153 addr = __io_address(U8500_PRCMU_BASE);
154 else
155 ux500_unknown_soc();
156
157 /*
158 * On a startup, always conifgure the TCR to the doze mode;
159 * bootloaders do it for us. Do this in the kernel too.
160 */
161 writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
162
163 tcr = readl(addr + PRCM_TCR);
164
165 /* Get the rate from the parent as a default */
166 if (clk->parent_periph)
167 mturate = clk_get_rate(clk->parent_periph);
168 else if (clk->parent_cluster)
169 mturate = clk_get_rate(clk->parent_cluster);
170 else
171 /* We need to be connected SOMEWHERE */
172 BUG();
173
174 /* Return the clock selected for this MTU */
175 if (tcr & (1 << mtu))
176 retclk = clk32k;
177 else
178 retclk = mturate;
179
180 pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
181 return retclk;
182}
183
184unsigned long clk_get_rate(struct clk *clk)
185{
186 unsigned long rate;
187
188 /*
189 * If there is a custom getrate callback for this clock,
190 * it will take precedence.
191 */
192 if (clk->get_rate)
193 return clk->get_rate(clk);
194
195 if (clk->ops && clk->ops->get_rate)
196 return clk->ops->get_rate(clk);
197
198 rate = clk->rate;
199 if (!rate) {
200 if (clk->parent_periph)
201 rate = clk_get_rate(clk->parent_periph);
202 else if (clk->parent_cluster)
203 rate = clk_get_rate(clk->parent_cluster);
204 }
205
206 return rate;
207}
208EXPORT_SYMBOL(clk_get_rate);
209
210long clk_round_rate(struct clk *clk, unsigned long rate)
211{
212 /*TODO*/
213 return rate;
214}
215EXPORT_SYMBOL(clk_round_rate);
216
217int clk_set_rate(struct clk *clk, unsigned long rate)
218{
219 clk->rate = rate;
220 return 0;
221}
222EXPORT_SYMBOL(clk_set_rate);
223
224int clk_set_parent(struct clk *clk, struct clk *parent)
225{
226 /*TODO*/
227 return -ENOSYS;
228}
229EXPORT_SYMBOL(clk_set_parent);
230
231static void clk_prcmu_enable(struct clk *clk)
232{
233 void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
234 + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
235
236 writel(1 << clk->prcmu_cg_bit, cg_set_reg);
237}
238
239static void clk_prcmu_disable(struct clk *clk)
240{
241 void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
242 + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
243
244 writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
245}
246
247static struct clkops clk_prcmu_ops = {
248 .enable = clk_prcmu_enable,
249 .disable = clk_prcmu_disable,
250};
251
252static unsigned int clkrst_base[] = {
253 [1] = U8500_CLKRST1_BASE,
254 [2] = U8500_CLKRST2_BASE,
255 [3] = U8500_CLKRST3_BASE,
256 [5] = U8500_CLKRST5_BASE,
257 [6] = U8500_CLKRST6_BASE,
258};
259
260static void clk_prcc_enable(struct clk *clk)
261{
262 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
263
264 if (clk->prcc_kernel != -1)
265 writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
266
267 if (clk->prcc_bus != -1)
268 writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
269}
270
271static void clk_prcc_disable(struct clk *clk)
272{
273 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
274
275 if (clk->prcc_bus != -1)
276 writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
277
278 if (clk->prcc_kernel != -1)
279 writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
280}
281
282static struct clkops clk_prcc_ops = {
283 .enable = clk_prcc_enable,
284 .disable = clk_prcc_disable,
285};
286
287static struct clk clk_32khz = {
288 .name = "clk_32khz",
289 .rate = 32000,
290};
291
292/*
293 * PRCMU level clock gating
294 */
295
296/* Bank 0 */
297static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
298static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
299static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
300static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
301static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
302static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
303static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
304static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000);
305static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
306static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
307static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
308static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
309static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
310static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
311static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
312static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
313static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
314static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
315static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
316static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
317static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
318static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
319static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
320static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
321static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
322static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
323static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
324static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
325static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
326
327/* Bank 1 */
328static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
329static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
330
331/*
332 * PRCC level clock gating
333 * Format: per#, clk, PCKEN bit, KCKEN bit, parent
334 */
335
336/* Peripheral Cluster #1 */
337static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk);
338static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
339static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
340static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
341static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL);
342static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
343static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
344static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk);
345static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
346static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
347static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
348static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
349
350/* Peripheral Cluster #2 */
351static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL);
352static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL);
353static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL);
354static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL);
355static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk);
356static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk);
357static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk);
358static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk);
359static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL);
360static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL);
361static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL);
362static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk);
363
364/* Peripheral Cluster #3 */
365static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
366static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
367static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
368static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
369static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
370static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
371static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk);
372static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk);
373static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
374
375/* Peripheral Cluster #4 is in the always on domain */
376
377/* Peripheral Cluster #5 */
378static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
379static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
380
381/* Peripheral Cluster #6 */
382
383/* MTU ID in data */
384static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
385static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
386static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL);
387static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL);
388static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk);
389static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL);
390static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL);
391static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL);
392static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL);
393static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
394
395static struct clk clk_dummy_apb_pclk = {
396 .name = "apb_pclk",
397};
398
399static struct clk_lookup u8500_clks[] = {
400 CLK(dummy_apb_pclk, NULL, "apb_pclk"),
401
402 /* Peripheral Cluster #1 */
403 CLK(gpio0, "gpio.0", NULL),
404 CLK(gpio0, "gpio.1", NULL),
405 CLK(slimbus0, "slimbus0", NULL),
406 CLK(i2c2, "nmk-i2c.2", NULL),
407 CLK(sdi0, "sdi0", NULL),
408 CLK(msp0, "ux500-msp-i2s.0", NULL),
409 CLK(i2c1, "nmk-i2c.1", NULL),
410 CLK(uart1, "uart1", NULL),
411 CLK(uart0, "uart0", NULL),
412
413 /* Peripheral Cluster #3 */
414 CLK(gpio2, "gpio.2", NULL),
415 CLK(gpio2, "gpio.3", NULL),
416 CLK(gpio2, "gpio.4", NULL),
417 CLK(gpio2, "gpio.5", NULL),
418 CLK(sdi5, "sdi5", NULL),
419 CLK(uart2, "uart2", NULL),
420 CLK(ske, "ske", NULL),
421 CLK(ske, "nmk-ske-keypad", NULL),
422 CLK(sdi2, "sdi2", NULL),
423 CLK(i2c0, "nmk-i2c.0", NULL),
424 CLK(fsmc, "fsmc", NULL),
425
426 /* Peripheral Cluster #5 */
427 CLK(gpio3, "gpio.8", NULL),
428
429 /* Peripheral Cluster #6 */
430 CLK(hash1, "hash1", NULL),
431 CLK(pka, "pka", NULL),
432 CLK(hash0, "hash0", NULL),
433 CLK(cryp0, "cryp0", NULL),
434 CLK(cryp1, "cryp1", NULL),
435
436 /* PRCMU level clock gating */
437
438 /* Bank 0 */
439 CLK(svaclk, "sva", NULL),
440 CLK(siaclk, "sia", NULL),
441 CLK(sgaclk, "sga", NULL),
442 CLK(slimclk, "slim", NULL),
443 CLK(lcdclk, "lcd", NULL),
444 CLK(bmlclk, "bml", NULL),
445 CLK(hsitxclk, "stm-hsi.0", NULL),
446 CLK(hsirxclk, "stm-hsi.1", NULL),
447 CLK(hdmiclk, "hdmi", NULL),
448 CLK(apeatclk, "apeat", NULL),
449 CLK(apetraceclk, "apetrace", NULL),
450 CLK(mcdeclk, "mcde", NULL),
451 CLK(ipi2clk, "ipi2", NULL),
452 CLK(dmaclk, "dma40.0", NULL),
453 CLK(b2r2clk, "b2r2", NULL),
454 CLK(tvclk, "tv", NULL),
455
456 /* Peripheral Cluster #1 */
457 CLK(i2c4, "nmk-i2c.4", NULL),
458 CLK(spi3, "spi3", NULL),
459 CLK(msp1, "ux500-msp-i2s.1", NULL),
460 CLK(msp3, "ux500-msp-i2s.3", NULL),
461
462 /* Peripheral Cluster #2 */
463 CLK(gpio1, "gpio.6", NULL),
464 CLK(gpio1, "gpio.7", NULL),
465 CLK(ssitx, "ssitx", NULL),
466 CLK(ssirx, "ssirx", NULL),
467 CLK(spi0, "spi0", NULL),
468 CLK(sdi3, "sdi3", NULL),
469 CLK(sdi1, "sdi1", NULL),
470 CLK(msp2, "ux500-msp-i2s.2", NULL),
471 CLK(sdi4, "sdi4", NULL),
472 CLK(pwl, "pwl", NULL),
473 CLK(spi1, "spi1", NULL),
474 CLK(spi2, "spi2", NULL),
475 CLK(i2c3, "nmk-i2c.3", NULL),
476
477 /* Peripheral Cluster #3 */
478 CLK(ssp1, "ssp1", NULL),
479 CLK(ssp0, "ssp0", NULL),
480
481 /* Peripheral Cluster #5 */
482 CLK(usb, "musb-ux500.0", "usb"),
483
484 /* Peripheral Cluster #6 */
485 CLK(mtu1, "mtu1", NULL),
486 CLK(mtu0, "mtu0", NULL),
487 CLK(cfgreg, "cfgreg", NULL),
488 CLK(hash1, "hash1", NULL),
489 CLK(unipro, "unipro", NULL),
490 CLK(rng, "rng", NULL),
491
492 /* PRCMU level clock gating */
493
494 /* Bank 0 */
495 CLK(uniproclk, "uniproclk", NULL),
496 CLK(dsialtclk, "dsialt", NULL),
497
498 /* Bank 1 */
499 CLK(rngclk, "rng", NULL),
500 CLK(uiccclk, "uicc", NULL),
501};
502
503#ifdef CONFIG_DEBUG_FS
504/*
505 * debugfs support to trace clock tree hierarchy and attributes with
506 * powerdebug
507 */
508static struct dentry *clk_debugfs_root;
509
510void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
511{
512 while (num--) {
513 /* Check that the clock has not been already registered */
514 if (!(cl->clk->list.prev != cl->clk->list.next))
515 list_add_tail(&cl->clk->list, &clk_list);
516
517 cl++;
518 }
519}
520
521static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
522 size_t size, loff_t *off)
523{
524 struct clk *clk = file->f_dentry->d_inode->i_private;
525 char cusecount[128];
526 unsigned int len;
527
528 len = sprintf(cusecount, "%u\n", clk->enabled);
529 return simple_read_from_buffer(buf, size, off, cusecount, len);
530}
531
532static ssize_t rate_dbg_read(struct file *file, char __user *buf,
533 size_t size, loff_t *off)
534{
535 struct clk *clk = file->f_dentry->d_inode->i_private;
536 char crate[128];
537 unsigned int rate;
538 unsigned int len;
539
540 rate = clk_get_rate(clk);
541 len = sprintf(crate, "%u\n", rate);
542 return simple_read_from_buffer(buf, size, off, crate, len);
543}
544
545static const struct file_operations usecount_fops = {
546 .read = usecount_dbg_read,
547};
548
549static const struct file_operations set_rate_fops = {
550 .read = rate_dbg_read,
551};
552
553static struct dentry *clk_debugfs_register_dir(struct clk *c,
554 struct dentry *p_dentry)
555{
556 struct dentry *d, *clk_d;
557 const char *p = c->name;
558
559 if (!p)
560 p = "BUG";
561
562 clk_d = debugfs_create_dir(p, p_dentry);
563 if (!clk_d)
564 return NULL;
565
566 d = debugfs_create_file("usecount", S_IRUGO,
567 clk_d, c, &usecount_fops);
568 if (!d)
569 goto err_out;
570 d = debugfs_create_file("rate", S_IRUGO,
571 clk_d, c, &set_rate_fops);
572 if (!d)
573 goto err_out;
574 /*
575 * TODO : not currently available in ux500
576 * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
577 * if (!d)
578 * goto err_out;
579 */
580
581 return clk_d;
582
583err_out:
584 debugfs_remove_recursive(clk_d);
585 return NULL;
586}
587
588static int clk_debugfs_register_one(struct clk *c)
589{
590 struct clk *pa = c->parent_periph;
591 struct clk *bpa = c->parent_cluster;
592
593 if (!(bpa && !pa)) {
594 c->dent = clk_debugfs_register_dir(c,
595 pa ? pa->dent : clk_debugfs_root);
596 if (!c->dent)
597 return -ENOMEM;
598 }
599
600 if (bpa) {
601 c->dent_bus = clk_debugfs_register_dir(c,
602 bpa->dent_bus ? bpa->dent_bus : bpa->dent);
603 if ((!c->dent_bus) && (c->dent)) {
604 debugfs_remove_recursive(c->dent);
605 c->dent = NULL;
606 return -ENOMEM;
607 }
608 }
609 return 0;
610}
611
612static int clk_debugfs_register(struct clk *c)
613{
614 int err;
615 struct clk *pa = c->parent_periph;
616 struct clk *bpa = c->parent_cluster;
617
618 if (pa && (!pa->dent && !pa->dent_bus)) {
619 err = clk_debugfs_register(pa);
620 if (err)
621 return err;
622 }
623
624 if (bpa && (!bpa->dent && !bpa->dent_bus)) {
625 err = clk_debugfs_register(bpa);
626 if (err)
627 return err;
628 }
629
630 if ((!c->dent) && (!c->dent_bus)) {
631 err = clk_debugfs_register_one(c);
632 if (err)
633 return err;
634 }
635 return 0;
636}
637
638int __init clk_debugfs_init(void)
639{
640 struct clk *c;
641 struct dentry *d;
642 int err;
643
644 d = debugfs_create_dir("clock", NULL);
645 if (!d)
646 return -ENOMEM;
647 clk_debugfs_root = d;
648
649 list_for_each_entry(c, &clk_list, list) {
650 err = clk_debugfs_register(c);
651 if (err)
652 goto err_out;
653 }
654 return 0;
655err_out:
656 debugfs_remove_recursive(clk_debugfs_root);
657 return err;
658}
659
660#endif /* defined(CONFIG_DEBUG_FS) */
661
662unsigned long clk_smp_twd_rate = 500000000;
663
664unsigned long clk_smp_twd_get_rate(struct clk *clk)
665{
666 return clk_smp_twd_rate;
667}
668
669static struct clk clk_smp_twd = {
670 .get_rate = clk_smp_twd_get_rate,
671 .name = "smp_twd",
672};
673
674static struct clk_lookup clk_smp_twd_lookup = {
675 .dev_id = "smp_twd",
676 .clk = &clk_smp_twd,
677};
678
679#ifdef CONFIG_CPU_FREQ
680
681static int clk_twd_cpufreq_transition(struct notifier_block *nb,
682 unsigned long state, void *data)
683{
684 struct cpufreq_freqs *f = data;
685
686 if (state == CPUFREQ_PRECHANGE) {
687 /* Save frequency in simple Hz */
688 clk_smp_twd_rate = (f->new * 1000) / 2;
689 }
690
691 return NOTIFY_OK;
692}
693
694static struct notifier_block clk_twd_cpufreq_nb = {
695 .notifier_call = clk_twd_cpufreq_transition,
696};
697
698int clk_init_smp_twd_cpufreq(void)
699{
700 return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
701 CPUFREQ_TRANSITION_NOTIFIER);
702}
703
704#endif
705
706int __init clk_init(void)
707{
708 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
709 clkdev_add(&clk_smp_twd_lookup);
710
711#ifdef CONFIG_DEBUG_FS
712 clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
713#endif
714 return 0;
715}
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
deleted file mode 100644
index 65d27a13f46d..000000000000
--- a/arch/arm/mach-ux500/clock.h
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * Copyright (C) 2010 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10/**
11 * struct clkops - ux500 clock operations
12 * @enable: function to enable the clock
13 * @disable: function to disable the clock
14 * @get_rate: function to get the current clock rate
15 *
16 * This structure contains function pointers to functions that will be used to
17 * control the clock. All of these functions are optional. If get_rate is
18 * NULL, the rate in the struct clk will be used.
19 */
20struct clkops {
21 void (*enable) (struct clk *);
22 void (*disable) (struct clk *);
23 unsigned long (*get_rate) (struct clk *);
24 int (*set_parent)(struct clk *, struct clk *);
25};
26
27/**
28 * struct clk - ux500 clock structure
29 * @ops: pointer to clkops struct used to control this clock
30 * @name: name, for debugging
31 * @enabled: refcount. positive if enabled, zero if disabled
32 * @get_rate: custom callback for getting the clock rate
33 * @data: custom per-clock data for example for the get_rate
34 * callback
35 * @rate: fixed rate for clocks which don't implement
36 * ops->getrate
37 * @prcmu_cg_off: address offset of the combined enable/disable register
38 * (used on u8500v1)
39 * @prcmu_cg_bit: bit in the combined enable/disable register (used on
40 * u8500v1)
41 * @prcmu_cg_mgt: address of the enable/disable register (used on
42 * u8500ed)
43 * @cluster: peripheral cluster number
44 * @prcc_bus: bit for the bus clock in the peripheral's CLKRST
45 * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST.
46 * -1 if no kernel clock exists.
47 * @parent_cluster: pointer to parent's cluster clk struct
48 * @parent_periph: pointer to parent's peripheral clk struct
49 *
50 * Peripherals are organised into clusters, and each cluster has an associated
51 * bus clock. Some peripherals also have a parent peripheral clock.
52 *
53 * In order to enable a clock for a peripheral, we need to enable:
54 * (1) the parent cluster (bus) clock at the PRCMU level
55 * (2) the parent peripheral clock (if any) at the PRCMU level
56 * (3) the peripheral's bus & kernel clock at the PRCC level
57 *
58 * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
59 * of the cluster and peripheral clocks, and hooking these as the parents of
60 * the individual peripheral clocks.
61 *
62 * (3) is handled by specifying the bits in the PRCC control registers required
63 * to enable these clocks and modifying them in the ->enable and
64 * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
65 *
66 * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
67 * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
68 * prcc, and parent pointers are only used for the PRCC-level clocks.
69 */
70struct clk {
71 const struct clkops *ops;
72 const char *name;
73 unsigned int enabled;
74 unsigned long (*get_rate)(struct clk *);
75 void *data;
76
77 unsigned long rate;
78 struct list_head list;
79
80 /* These three are only for PRCMU clks */
81
82 unsigned int prcmu_cg_off;
83 unsigned int prcmu_cg_bit;
84 unsigned int prcmu_cg_mgt;
85
86 /* The rest are only for PRCC clks */
87
88 int cluster;
89 unsigned int prcc_bus;
90 unsigned int prcc_kernel;
91
92 struct clk *parent_cluster;
93 struct clk *parent_periph;
94#if defined(CONFIG_DEBUG_FS)
95 struct dentry *dent; /* For visible tree hierarchy */
96 struct dentry *dent_bus; /* For visible tree hierarchy */
97#endif
98};
99
100#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \
101struct clk clk_##_name = { \
102 .name = #_name, \
103 .ops = &clk_prcmu_ops, \
104 .prcmu_cg_off = _cg_off, \
105 .prcmu_cg_bit = _cg_bit, \
106 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
107 }
108
109#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \
110struct clk clk_##_name = { \
111 .name = #_name, \
112 .ops = &clk_prcmu_ops, \
113 .prcmu_cg_off = _cg_off, \
114 .prcmu_cg_bit = _cg_bit, \
115 .rate = _rate, \
116 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
117 }
118
119#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \
120struct clk clk_##_name = { \
121 .name = #_name, \
122 .ops = &clk_prcc_ops, \
123 .cluster = _pclust, \
124 .prcc_bus = _bus_en, \
125 .prcc_kernel = _kernel_en, \
126 .parent_cluster = &clk_per##_pclust##clk, \
127 .parent_periph = _kernclk \
128 }
129
130#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
131struct clk clk_##_name = { \
132 .name = #_name, \
133 .ops = &clk_prcc_ops, \
134 .cluster = _pclust, \
135 .prcc_bus = _bus_en, \
136 .prcc_kernel = _kernel_en, \
137 .parent_cluster = &clk_per##_pclust##clk, \
138 .parent_periph = _kernclk, \
139 .get_rate = _callback, \
140 .data = (void *) _data \
141 }
142
143
144#define CLK(_clk, _devname, _conname) \
145 { \
146 .clk = &clk_##_clk, \
147 .dev_id = _devname, \
148 .con_id = _conname, \
149 }
150
151int __init clk_db8500_ed_fixup(void);
152int __init clk_init(void);
153
154#ifdef CONFIG_DEBUG_FS
155int clk_debugfs_init(void);
156#else
157static inline int clk_debugfs_init(void) { return 0; }
158#endif
159
160#ifdef CONFIG_CPU_FREQ
161int clk_init_smp_twd_cpufreq(void);
162#else
163static inline int clk_init_smp_twd_cpufreq(void) { return 0; }
164#endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7c770d..17a78ec516ff 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,6 @@
8 8
9#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/io.h> 10#include <linux/io.h>
11#include <linux/clk.h>
12#include <linux/mfd/db8500-prcmu.h> 11#include <linux/mfd/db8500-prcmu.h>
13#include <linux/clksrc-dbx500-prcmu.h> 12#include <linux/clksrc-dbx500-prcmu.h>
14#include <linux/sys_soc.h> 13#include <linux/sys_soc.h>
@@ -17,6 +16,7 @@
17#include <linux/stat.h> 16#include <linux/stat.h>
18#include <linux/of.h> 17#include <linux/of.h>
19#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <linux/platform_data/clk-ux500.h>
20 20
21#include <asm/hardware/gic.h> 21#include <asm/hardware/gic.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
@@ -25,8 +25,6 @@
25#include <mach/setup.h> 25#include <mach/setup.h>
26#include <mach/devices.h> 26#include <mach/devices.h>
27 27
28#include "clock.h"
29
30void __iomem *_PRCMU_BASE; 28void __iomem *_PRCMU_BASE;
31 29
32/* 30/*
@@ -70,13 +68,17 @@ void __init ux500_init_irq(void)
70 */ 68 */
71 if (cpu_is_u8500_family()) 69 if (cpu_is_u8500_family())
72 db8500_prcmu_early_init(); 70 db8500_prcmu_early_init();
73 clk_init(); 71
72 if (cpu_is_u8500_family())
73 u8500_clk_init();
74 else if (cpu_is_u9540())
75 u9540_clk_init();
76 else if (cpu_is_u8540())
77 u8540_clk_init();
74} 78}
75 79
76void __init ux500_init_late(void) 80void __init ux500_init_late(void)
77{ 81{
78 clk_debugfs_init();
79 clk_init_smp_twd_cpufreq();
80} 82}
81 83
82static const char * __init ux500_get_machine(void) 84static const char * __init ux500_get_machine(void)
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7128e9710417..28ba09f4ebb9 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -52,7 +52,6 @@ extern void imx31_soc_init(void);
52extern void imx35_soc_init(void); 52extern void imx35_soc_init(void);
53extern void imx50_soc_init(void); 53extern void imx50_soc_init(void);
54extern void imx51_soc_init(void); 54extern void imx51_soc_init(void);
55extern void imx53_soc_init(void);
56extern void imx51_init_late(void); 55extern void imx51_init_late(void);
57extern void imx53_init_late(void); 56extern void imx53_init_late(void);
58extern void epit_timer_init(void __iomem *base, int irq); 57extern void epit_timer_init(void __iomem *base, int irq);
@@ -137,11 +136,6 @@ extern void imx_src_prepare_restart(void);
137extern void imx_gpc_init(void); 136extern void imx_gpc_init(void);
138extern void imx_gpc_pre_suspend(void); 137extern void imx_gpc_pre_suspend(void);
139extern void imx_gpc_post_resume(void); 138extern void imx_gpc_post_resume(void);
140extern void imx51_babbage_common_init(void);
141extern void imx53_ard_common_init(void);
142extern void imx53_evk_common_init(void);
143extern void imx53_qsb_common_init(void);
144extern void imx53_smd_common_init(void);
145extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 139extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
146extern void imx6q_clock_map_io(void); 140extern void imx6q_clock_map_io(void);
147 141
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
deleted file mode 100644
index 9761e003bde2..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ /dev/null
@@ -1,1219 +0,0 @@
1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc..
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_IOMUX_MX53_H__
20#define __MACH_IOMUX_MX53_H__
21
22#include <mach/iomux-v3.h>
23
24/* These 2 defines are for pins that may not have a mux register, but could
25 * have a pad setting register, and vice-versa. */
26#define __NA_ 0x00
27
28#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
29 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
30#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
32 PAD_CTL_SRE_FAST)
33
34
35#define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
36#define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
37#define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
38#define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
39#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
40#define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
41#define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
42#define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
43#define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
44#define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
45#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
46#define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
47#define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
48#define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
49#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
50#define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
51#define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
52#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
53#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
54#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
55#define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
56#define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
57#define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
58#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
59#define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
60#define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
61#define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
62#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
63#define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
64#define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
65#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
66#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
67#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
68#define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
69#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
70#define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
71#define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
72#define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
73#define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
74#define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
75#define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
76#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
77#define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
78#define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
79#define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
80#define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
81#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
82#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
83#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
84#define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
85#define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
86#define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
87#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
88#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
89#define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
90#define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
91#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
92#define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
93#define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
94#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
95#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
96#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
97#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
98#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
99#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
100#define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
101#define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
102#define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
103#define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
104#define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
105#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
106#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
107#define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
108#define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
109#define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
110#define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
111#define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
112#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
113#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
114#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
115#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
116#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
117#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
118#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
119#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
120#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
121#define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
122#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
123#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
124#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
125#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
126#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
127#define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
128#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
129#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
130#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
131#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
132#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
133#define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
134#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
135#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
136#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
137#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
138#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
139#define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
140#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
141#define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
142#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
143#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
144#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
145#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
146#define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
147#define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
148#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
149#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
150#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
151#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
152#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
153#define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
154#define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
155#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
156#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
157 IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
158#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
159#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
160#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
161#define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
162#define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
163#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
164#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
165#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
166#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
167#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
168#define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
169#define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
170#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
171#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
172#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
173#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
174#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
175#define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
176#define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
177#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
178#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
179#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
180#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
181#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
182#define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
183#define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
184#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
185#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
186#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
187#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
188#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
189#define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
190#define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
191#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
192#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
193#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
194#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
195#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
196#define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
197#define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
198#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
199#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
200#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
201#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
202#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
203#define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
204#define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
205#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
206#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
207#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
208#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
209#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
210#define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
211#define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
212#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
213#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
214#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
215#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
216#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
217#define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
218#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
219#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
220 IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
221#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
222#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
223#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
224#define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
225#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
226#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
227 IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
228#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
229#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
230#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
231#define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
232#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
233#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
234 IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
235#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
236#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
237#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
238#define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
239#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
240#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
241 IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
242#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
243#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
244#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
245#define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
246#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
247#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
248 IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
249#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
250#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
251#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
252#define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
253#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
254#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
255#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
256 IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
257#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
258#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
259#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
260#define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
261#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
262#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
263#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
264#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \
265 IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
266#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
267#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
268#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
269#define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
270#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
271#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
272#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
273#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \
274 IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
275#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
276#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
277#define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
278#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
279#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
280#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
281#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \
282 IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
283#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
284#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
285#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
286#define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
287#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
288#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
289#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
290#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \
291 IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
292#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
293#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
294#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
295#define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
296#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
297#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
298#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
299 IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
300#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
301#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
302#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
303#define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
304#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
305#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
306#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
307#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
308#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
309#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
310#define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
311#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
312#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
313#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
314#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
315#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
316#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
317#define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
318#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
319#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
320#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
321#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
322#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
323#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
324#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
325#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
326#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
327#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
328#define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
329#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
330#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
331#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
332#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
333#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
334#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
335#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
336#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
337#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
338#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
339#define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
340#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
341#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
342#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
343#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
344#define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
345#define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
346#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
347#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
348#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
349#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
350#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
351#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
352#define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
353#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
354#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
355#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
356#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
357#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
358#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
359#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
360#define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
361#define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
362#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
363#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
364#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
365#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
366#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
367#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
368#define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
369#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
370#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
371#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
372#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
373#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
374#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
375#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
376#define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
377#define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
378#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
379#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
380#define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
381#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
382#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
383#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
384#define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
385#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
386#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
387#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
388#define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
389#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
390#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
391#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
392#define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
393#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
394#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
395#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
396#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
397#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
398#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
399#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
400#define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
401#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
402#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
403#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
404#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
405#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
406#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
407#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
408#define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
409#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
410#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
411#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
412#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
413#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
414#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
415#define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
416#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
417#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
418#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
419#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
420#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
421#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
422#define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
423#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
424#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
425#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
426#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
427#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
428#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
429#define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
430#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
431#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
432#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
433#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
434#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
435#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
436#define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
437#define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
438#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
439#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
440#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
441#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
442#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
443#define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
444#define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
445#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
446#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
447#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
448#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
449#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
450#define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
451#define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
452#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
453#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
454#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
455#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
456#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
457#define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
458#define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
459#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
460#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
461#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
462#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
463#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
464#define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
465#define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
466#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
467#define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
468#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
469#define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
470#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
471#define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
472#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
473#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
474#define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
475#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
476#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
477#define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
478#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
479#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
480#define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
481#define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
482#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
483#define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
484#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
485#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
486#define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
487#define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
488#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
489#define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
490#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
491#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
492#define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
493#define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
494#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
495#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
496#define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
497#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
498#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
499#define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
500#define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
501#define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
502#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
503#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
504#define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
505#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
506#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
507#define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
508#define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
509#define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
510#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
511#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
512#define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
513#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
514#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
515#define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
516#define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
517#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
518#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
519#define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
520#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
521#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
522#define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
523#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
524#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
525#define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
526#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
527#define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
528#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
529#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
530#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
531#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
532#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
533#define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
534#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
535#define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
536#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
537#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
538#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
539#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
540#define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
541#define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
542#define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
543#define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
544#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
545#define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
546#define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
547#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
548#define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
549#define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
550#define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
551#define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
552#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
553#define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
554#define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
555#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
556#define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
557#define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
558#define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
559#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
560#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
561#define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
562#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
563#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
564#define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
565#define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
566#define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
567#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
568#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
569#define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
570#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
571#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
572#define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
573#define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
574#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
575#define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
576#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
577#define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
578#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
579#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
580#define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
581#define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
582#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
583#define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
584#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
585#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
586#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
587#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
588#define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
589#define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
590#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
591#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
592#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
593#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
594#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
595#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
596#define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
597#define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
598#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
599#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
600#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
601#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
602#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
603#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
604#define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
605#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
606#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
607#define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
608#define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
609#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
610#define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
611#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
612#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
613#define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
614#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
615#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
616#define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
617#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
618#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
619#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
620#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
621#define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
622#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
623#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
624#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
625#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
626#define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
627#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
628#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
629#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
630#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
631#define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
632#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
633#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
634#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
635#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
636#define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
637#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
638#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
639#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
640#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
641#define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
642#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
643#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
644#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
645#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
646#define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
647#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
648#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
649#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
650#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
651#define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
652#define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
653#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
654#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
655#define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
656#define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
657#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
658#define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
659#define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
660#define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
661#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
662#define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
663#define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
664#define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
665#define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
666#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
667#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
668#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
669#define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
670#define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
671#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
672#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
673#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
674#define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
675#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
676#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
677#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
678#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
679#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
680#define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
681#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
682#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
683#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
684#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
685#define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
686#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
687#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
688#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
689#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
690#define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
691#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
692#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
693#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
694#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
695#define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
696#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
697#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
698#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
699#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
700#define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
701#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
702#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
703#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
704#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
705#define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
706#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
707#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
708#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
709#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
710#define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
711#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
712#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
713#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
714#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
715#define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
716#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
717#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
718#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
719#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
720#define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
721#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
722#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
723#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
724#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
725#define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
726#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
727#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
728#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
729#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
730#define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
731#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
732#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
733#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
734#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
735#define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
736#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
737#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
738#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
739#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
740#define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
741#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
742#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
743#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
744#define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
745#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
746#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
747#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
748#define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
749#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
750#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
751#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
752#define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
753#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
754#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
755#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
756#define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
757#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
758#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
759#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
760#define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
761#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
762#define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
763#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
764#define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
765#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
766#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
767#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
768#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
769#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
770#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
771#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
772#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
773#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
774#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
775#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
776#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
777#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
778#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
779#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
780#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
781#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
782#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
783#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
784#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
785#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
786#define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
787#define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
788#define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
789#define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
790#define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
791#define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
792#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
793#define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
794#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
795#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
796#define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
797#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
798#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
799#define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
800#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
801#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
802#define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
803#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
804#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
805#define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
806#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
807#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
808#define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
809#define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
810#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
811#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
812#define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
813#define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
814#define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
815#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
816#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
817#define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
818#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
819#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
820#define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
821#define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
822#define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
823#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
824#define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
825#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
826#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
827#define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
828#define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
829#define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
830#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
831#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
832#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
833#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
834#define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
835#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
836#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
837#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
838#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
839#define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
840#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
841#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
842#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
843#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
844#define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
845#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
846#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
847#define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
848#define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
849#define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
850#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
851#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
852#define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
853#define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
854#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
855#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
856#define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
857#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
858#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
859#define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
860#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
861#define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
862#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
863#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
864#define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
865#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
866#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
867#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
868#define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
869#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
870#define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
871#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
872#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
873#define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
874#define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
875#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
876#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
877#define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
878#define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
879#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
880#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
881#define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
882#define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
883#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
884#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
885#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
886#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
887#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
888#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
889#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
890#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
891#define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
892#define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
893#define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
894#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
895#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
896#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
897#define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
898#define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
899#define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
900#define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
901#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
902#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
903#define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
904#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
905#define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
906#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
907#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
908#define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
909#define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
910#define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
911#define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
912#define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
913#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
914#define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
915#define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
916#define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
917#define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
918#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
919#define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
920#define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
921#define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
922#define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
923#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
924#define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
925#define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
926#define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
927#define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
928#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
929#define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
930#define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
931#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
932#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
933#define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
934#define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
935#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
936#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
937#define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
938#define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
939#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
940#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
941#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
942#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
943#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
944#define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
945#define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
946#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
947#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
948#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
949#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
950#define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
951#define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
952#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
953#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
954#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
955#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
956#define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
957#define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
958#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
959#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
960#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
961#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
962#define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
963#define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
964#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
965#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
966#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
967#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
968#define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
969#define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
970#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
971#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
972#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
973#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
974#define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
975#define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
976#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
977#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
978#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
979#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
980#define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
981#define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
982#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
983#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
984#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
985#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
986#define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
987#define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
988#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
989#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
990#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
991#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
992#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
993#define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
994#define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
995#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
996#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
997#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
998#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
999#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
1000#define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
1001#define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
1002#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
1003#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
1004#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
1005#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
1006#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
1007#define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
1008#define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
1009#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
1010#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
1011#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
1012#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
1013#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
1014#define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
1015#define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
1016#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
1017#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
1018#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
1019#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
1020#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
1021#define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
1022#define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
1023#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
1024#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
1025#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
1026#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
1027#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
1028#define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
1029#define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
1030#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
1031#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
1032#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
1033#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
1034#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
1035#define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
1036#define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
1037#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
1038#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
1039#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
1040#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
1041#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
1042#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1043#define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
1044#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
1045#define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
1046#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
1047#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1048#define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
1049#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
1050#define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
1051#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
1052#define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
1053#define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
1054#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
1055#define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
1056#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
1057#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1058#define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
1059#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
1060#define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
1061#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
1062#define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
1063#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
1064#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
1065#define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1066#define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
1067#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
1068#define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
1069#define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
1070#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
1071#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1072#define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
1073#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
1074#define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
1075#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
1076#define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
1077#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
1078#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
1079#define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1080#define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
1081#define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
1082#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
1083#define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
1084#define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
1085#define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1086#define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
1087#define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
1088#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
1089#define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
1090#define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
1091#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1092#define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
1093#define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
1094#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
1095#define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
1096#define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
1097#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1098#define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
1099#define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
1100#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
1101#define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
1102#define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
1103#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1104#define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
1105#define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
1106#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
1107#define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
1108#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
1109#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
1110#define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
1111#define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
1112#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
1113#define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
1114#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
1115#define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
1116#define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
1117#define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
1118#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
1119#define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
1120#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
1121#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
1122#define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
1123#define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
1124#define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
1125#define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
1126#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
1127#define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
1128#define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
1129#define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
1130#define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
1131#define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
1132#define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
1133#define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
1134#define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
1135#define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
1136#define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
1137#define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
1138#define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
1139#define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
1140#define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
1141#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
1142#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
1143#define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
1144#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
1145#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
1146#define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
1147#define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
1148#define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
1149#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
1150#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
1151#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
1152#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
1153#define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
1154#define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
1155#define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
1156#define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
1157#define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
1158#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
1159#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
1160#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
1161#define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
1162#define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
1163#define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
1164#define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
1165#define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
1166#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
1167#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
1168#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
1169#define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
1170#define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
1171#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
1172#define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
1173#define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
1174#define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
1175#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
1176#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
1177#define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
1178#define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
1179#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
1180#define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
1181#define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
1182#define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
1183#define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
1184#define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
1185#define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
1186#define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
1187#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
1188#define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
1189#define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
1190#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
1191#define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
1192#define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
1193#define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
1194#define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
1195#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
1196#define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
1197#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
1198#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
1199#define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
1200#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
1201#define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
1202#define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
1203#define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
1204#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
1205#define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
1206#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
1207#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
1208#define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
1209#define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
1210#define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
1211#define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
1212#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
1213#define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
1214#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
1215#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
1216#define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
1217#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
1218
1219#endif /* __MACH_IOMUX_MX53_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 14:06:47 -0500