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-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c4
-rw-r--r--arch/arm/mach-omap1/board-fsample.c4
-rw-r--r--arch/arm/mach-omap1/board-generic.c4
-rw-r--r--arch/arm/mach-omap1/board-h2.c4
-rw-r--r--arch/arm/mach-omap1/board-h3.c4
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c4
-rw-r--r--arch/arm/mach-omap1/board-innovator.c4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c4
-rw-r--r--arch/arm/mach-omap1/board-osk.c4
-rw-r--r--arch/arm/mach-omap1/board-palmte.c4
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c4
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c4
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c4
-rw-r--r--arch/arm/mach-omap1/board-sx1.c4
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c4
-rw-r--r--arch/arm/mach-omap1/irq.c2
-rw-r--r--arch/arm/mach-omap1/mcbsp.c4
-rw-r--r--arch/arm/mach-omap1/pm_bus.c8
-rw-r--r--arch/arm/mach-omap1/time.c6
-rw-r--r--arch/arm/mach-omap1/timer32k.c4
-rw-r--r--arch/arm/mach-omap2/Makefile20
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c93
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c156
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c4
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c4
-rw-r--r--arch/arm/mach-omap2/board-apollon.c4
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c81
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c5
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c64
-rw-r--r--arch/arm/mach-omap2/board-flash.c4
-rw-r--r--arch/arm/mach-omap2/board-generic.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c4
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c79
-rw-r--r--arch/arm/mach-omap2/board-ldp.c29
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c12
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c89
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c111
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c19
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c122
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c99
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c97
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c161
-rw-r--r--arch/arm/mach-omap2/board-overo.c83
-rw-r--r--arch/arm/mach-omap2/board-rm680.c12
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c67
-rw-r--r--arch/arm/mach-omap2/board-rx51.c4
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c9
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c128
-rw-r--r--arch/arm/mach-omap2/board-zoom.c8
-rw-r--r--arch/arm/mach-omap2/clock44xx.h7
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c245
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c124
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h623
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h64
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h73
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c27
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h26
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c10
-rw-r--r--arch/arm/mach-omap2/i2c.c68
-rw-r--r--arch/arm/mach-omap2/io.c17
-rw-r--r--arch/arm/mach-omap2/irq.c32
-rw-r--r--arch/arm/mach-omap2/omap4-common.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c250
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c841
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c917
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c173
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c322
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c130
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c150
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c672
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c553
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.c20
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h93
-rw-r--r--arch/arm/mach-omap2/pm-debug.c372
-rw-r--r--arch/arm/mach-omap2/pm.c2
-rw-r--r--arch/arm/mach-omap2/pm.h16
-rw-r--r--arch/arm/mach-omap2/pm24xx.c6
-rw-r--r--arch/arm/mach-omap2/pm34xx.c6
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c25
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h69
-rw-r--r--arch/arm/mach-omap2/prm44xx.h34
-rw-r--r--arch/arm/mach-omap2/smartreflex.c38
-rw-r--r--arch/arm/mach-omap2/timer-gp.c266
-rw-r--r--arch/arm/mach-omap2/timer-gp.h16
-rw-r--r--arch/arm/mach-omap2/timer.c342
-rw-r--r--arch/arm/mach-omap2/twl-common.c304
-rw-r--r--arch/arm/mach-omap2/twl-common.h59
-rw-r--r--arch/arm/plat-omap/Kconfig3
-rw-r--r--arch/arm/plat-omap/counter_32k.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c209
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h6
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h251
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h6
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h6
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h74
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h6
-rw-r--r--arch/arm/plat-omap/include/plat/omap-pm.h8
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h21
-rw-r--r--arch/arm/plat-omap/mcbsp.c599
-rw-r--r--arch/arm/plat-omap/omap_device.c34
104 files changed, 3805 insertions, 6092 deletions
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index af98117043d2..5b114d1558c8 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -4,14 +4,14 @@
4 4
5# Common support 5# Common support
6obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o 6obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
7obj-y += clock.o clock_data.o opp_data.o reset.o 7obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o
8 8
9obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 9obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
10 10
11obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o 11obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
12 12
13# Power Management 13# Power Management
14obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o 14obj-$(CONFIG_PM) += pm.o sleep.o
15 15
16# DSP 16# DSP
17obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 17obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index de88c9297b68..f1ac7fbf54a9 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -138,7 +138,7 @@ void ams_delta_latch2_write(u16 mask, u16 value)
138static void __init ams_delta_init_irq(void) 138static void __init ams_delta_init_irq(void)
139{ 139{
140 omap1_init_common_hw(); 140 omap1_init_common_hw();
141 omap_init_irq(); 141 omap1_init_irq();
142} 142}
143 143
144static struct map_desc ams_delta_io_desc[] __initdata = { 144static struct map_desc ams_delta_io_desc[] __initdata = {
@@ -391,7 +391,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
391 .reserve = omap_reserve, 391 .reserve = omap_reserve,
392 .init_irq = ams_delta_init_irq, 392 .init_irq = ams_delta_init_irq,
393 .init_machine = ams_delta_init, 393 .init_machine = ams_delta_init,
394 .timer = &omap_timer, 394 .timer = &omap1_timer,
395MACHINE_END 395MACHINE_END
396 396
397EXPORT_SYMBOL(ams_delta_latch1_write); 397EXPORT_SYMBOL(ams_delta_latch1_write);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 87f173d93557..a6b1bea50371 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -329,7 +329,7 @@ static void __init omap_fsample_init(void)
329static void __init omap_fsample_init_irq(void) 329static void __init omap_fsample_init_irq(void)
330{ 330{
331 omap1_init_common_hw(); 331 omap1_init_common_hw();
332 omap_init_irq(); 332 omap1_init_irq();
333} 333}
334 334
335/* Only FPGA needs to be mapped here. All others are done with ioremap */ 335/* Only FPGA needs to be mapped here. All others are done with ioremap */
@@ -394,5 +394,5 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
394 .reserve = omap_reserve, 394 .reserve = omap_reserve,
395 .init_irq = omap_fsample_init_irq, 395 .init_irq = omap_fsample_init_irq,
396 .init_machine = omap_fsample_init, 396 .init_machine = omap_fsample_init,
397 .timer = &omap_timer, 397 .timer = &omap1_timer,
398MACHINE_END 398MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 23f4ab9e2651..04fc356c40fa 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -31,7 +31,7 @@
31static void __init omap_generic_init_irq(void) 31static void __init omap_generic_init_irq(void)
32{ 32{
33 omap1_init_common_hw(); 33 omap1_init_common_hw();
34 omap_init_irq(); 34 omap1_init_irq();
35} 35}
36 36
37/* assume no Mini-AB port */ 37/* assume no Mini-AB port */
@@ -99,5 +99,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
99 .reserve = omap_reserve, 99 .reserve = omap_reserve,
100 .init_irq = omap_generic_init_irq, 100 .init_irq = omap_generic_init_irq,
101 .init_machine = omap_generic_init, 101 .init_machine = omap_generic_init,
102 .timer = &omap_timer, 102 .timer = &omap1_timer,
103MACHINE_END 103MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index ba3bd09c4754..cb7fb1aa3dca 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -376,7 +376,7 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
376static void __init h2_init_irq(void) 376static void __init h2_init_irq(void)
377{ 377{
378 omap1_init_common_hw(); 378 omap1_init_common_hw();
379 omap_init_irq(); 379 omap1_init_irq();
380} 380}
381 381
382static struct omap_usb_config h2_usb_config __initdata = { 382static struct omap_usb_config h2_usb_config __initdata = {
@@ -466,5 +466,5 @@ MACHINE_START(OMAP_H2, "TI-H2")
466 .reserve = omap_reserve, 466 .reserve = omap_reserve,
467 .init_irq = h2_init_irq, 467 .init_irq = h2_init_irq,
468 .init_machine = h2_init, 468 .init_machine = h2_init,
469 .timer = &omap_timer, 469 .timer = &omap1_timer,
470MACHINE_END 470MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index ac48677672ee..31f34875ffad 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -439,7 +439,7 @@ static void __init h3_init(void)
439static void __init h3_init_irq(void) 439static void __init h3_init_irq(void)
440{ 440{
441 omap1_init_common_hw(); 441 omap1_init_common_hw();
442 omap_init_irq(); 442 omap1_init_irq();
443} 443}
444 444
445static void __init h3_map_io(void) 445static void __init h3_map_io(void)
@@ -454,5 +454,5 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
454 .reserve = omap_reserve, 454 .reserve = omap_reserve,
455 .init_irq = h3_init_irq, 455 .init_irq = h3_init_irq,
456 .init_machine = h3_init, 456 .init_machine = h3_init,
457 .timer = &omap_timer, 457 .timer = &omap1_timer,
458MACHINE_END 458MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index ba05a51f9408..36e06ea7ec65 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -605,7 +605,7 @@ static void __init htcherald_init_irq(void)
605{ 605{
606 printk(KERN_INFO "htcherald_init_irq.\n"); 606 printk(KERN_INFO "htcherald_init_irq.\n");
607 omap1_init_common_hw(); 607 omap1_init_common_hw();
608 omap_init_irq(); 608 omap1_init_irq();
609} 609}
610 610
611MACHINE_START(HERALD, "HTC Herald") 611MACHINE_START(HERALD, "HTC Herald")
@@ -616,5 +616,5 @@ MACHINE_START(HERALD, "HTC Herald")
616 .reserve = omap_reserve, 616 .reserve = omap_reserve,
617 .init_irq = htcherald_init_irq, 617 .init_irq = htcherald_init_irq,
618 .init_machine = htcherald_init, 618 .init_machine = htcherald_init,
619 .timer = &omap_timer, 619 .timer = &omap1_timer,
620MACHINE_END 620MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 2d9b8cbd7a14..0b1ba462d388 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -292,7 +292,7 @@ static void __init innovator_init_smc91x(void)
292static void __init innovator_init_irq(void) 292static void __init innovator_init_irq(void)
293{ 293{
294 omap1_init_common_hw(); 294 omap1_init_common_hw();
295 omap_init_irq(); 295 omap1_init_irq();
296} 296}
297 297
298#ifdef CONFIG_ARCH_OMAP15XX 298#ifdef CONFIG_ARCH_OMAP15XX
@@ -464,5 +464,5 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
464 .reserve = omap_reserve, 464 .reserve = omap_reserve,
465 .init_irq = innovator_init_irq, 465 .init_irq = innovator_init_irq,
466 .init_machine = innovator_init, 466 .init_machine = innovator_init,
467 .timer = &omap_timer, 467 .timer = &omap1_timer,
468MACHINE_END 468MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index cfd084926146..5469ce247ffe 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -51,7 +51,7 @@ static void __init omap_nokia770_init_irq(void)
51 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004); 51 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
52 52
53 omap1_init_common_hw(); 53 omap1_init_common_hw();
54 omap_init_irq(); 54 omap1_init_irq();
55} 55}
56 56
57static const unsigned int nokia770_keymap[] = { 57static const unsigned int nokia770_keymap[] = {
@@ -269,5 +269,5 @@ MACHINE_START(NOKIA770, "Nokia 770")
269 .reserve = omap_reserve, 269 .reserve = omap_reserve,
270 .init_irq = omap_nokia770_init_irq, 270 .init_irq = omap_nokia770_init_irq,
271 .init_machine = omap_nokia770_init, 271 .init_machine = omap_nokia770_init,
272 .timer = &omap_timer, 272 .timer = &omap1_timer,
273MACHINE_END 273MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e68dfde1918e..b08a21380772 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -282,7 +282,7 @@ static void __init osk_init_cf(void)
282static void __init osk_init_irq(void) 282static void __init osk_init_irq(void)
283{ 283{
284 omap1_init_common_hw(); 284 omap1_init_common_hw();
285 omap_init_irq(); 285 omap1_init_irq();
286} 286}
287 287
288static struct omap_usb_config osk_usb_config __initdata = { 288static struct omap_usb_config osk_usb_config __initdata = {
@@ -588,5 +588,5 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
588 .reserve = omap_reserve, 588 .reserve = omap_reserve,
589 .init_irq = osk_init_irq, 589 .init_irq = osk_init_irq,
590 .init_machine = osk_init, 590 .init_machine = osk_init,
591 .timer = &omap_timer, 591 .timer = &omap1_timer,
592MACHINE_END 592MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index c9d38f47845f..459cb6bfed55 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -62,7 +62,7 @@
62static void __init omap_palmte_init_irq(void) 62static void __init omap_palmte_init_irq(void)
63{ 63{
64 omap1_init_common_hw(); 64 omap1_init_common_hw();
65 omap_init_irq(); 65 omap1_init_irq();
66} 66}
67 67
68static const unsigned int palmte_keymap[] = { 68static const unsigned int palmte_keymap[] = {
@@ -280,5 +280,5 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
280 .reserve = omap_reserve, 280 .reserve = omap_reserve,
281 .init_irq = omap_palmte_init_irq, 281 .init_irq = omap_palmte_init_irq,
282 .init_machine = omap_palmte_init, 282 .init_machine = omap_palmte_init,
283 .timer = &omap_timer, 283 .timer = &omap1_timer,
284MACHINE_END 284MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index f04f2d36e7d3..b214f45f646c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -266,7 +266,7 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
266static void __init omap_palmtt_init_irq(void) 266static void __init omap_palmtt_init_irq(void)
267{ 267{
268 omap1_init_common_hw(); 268 omap1_init_common_hw();
269 omap_init_irq(); 269 omap1_init_irq();
270} 270}
271 271
272static struct omap_usb_config palmtt_usb_config __initdata = { 272static struct omap_usb_config palmtt_usb_config __initdata = {
@@ -326,5 +326,5 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
326 .reserve = omap_reserve, 326 .reserve = omap_reserve,
327 .init_irq = omap_palmtt_init_irq, 327 .init_irq = omap_palmtt_init_irq,
328 .init_machine = omap_palmtt_init, 328 .init_machine = omap_palmtt_init,
329 .timer = &omap_timer, 329 .timer = &omap1_timer,
330MACHINE_END 330MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 45f01d2c3a7a..9b0ea48d35fd 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -61,7 +61,7 @@ static void __init
61omap_palmz71_init_irq(void) 61omap_palmz71_init_irq(void)
62{ 62{
63 omap1_init_common_hw(); 63 omap1_init_common_hw();
64 omap_init_irq(); 64 omap1_init_irq();
65} 65}
66 66
67static const unsigned int palmz71_keymap[] = { 67static const unsigned int palmz71_keymap[] = {
@@ -346,5 +346,5 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
346 .reserve = omap_reserve, 346 .reserve = omap_reserve,
347 .init_irq = omap_palmz71_init_irq, 347 .init_irq = omap_palmz71_init_irq,
348 .init_machine = omap_palmz71_init, 348 .init_machine = omap_palmz71_init,
349 .timer = &omap_timer, 349 .timer = &omap1_timer,
350MACHINE_END 350MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 3c8ee8489458..67acd4142639 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -297,7 +297,7 @@ static void __init omap_perseus2_init(void)
297static void __init omap_perseus2_init_irq(void) 297static void __init omap_perseus2_init_irq(void)
298{ 298{
299 omap1_init_common_hw(); 299 omap1_init_common_hw();
300 omap_init_irq(); 300 omap1_init_irq();
301} 301}
302/* Only FPGA needs to be mapped here. All others are done with ioremap */ 302/* Only FPGA needs to be mapped here. All others are done with ioremap */
303static struct map_desc omap_perseus2_io_desc[] __initdata = { 303static struct map_desc omap_perseus2_io_desc[] __initdata = {
@@ -355,5 +355,5 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
355 .reserve = omap_reserve, 355 .reserve = omap_reserve,
356 .init_irq = omap_perseus2_init_irq, 356 .init_irq = omap_perseus2_init_irq,
357 .init_machine = omap_perseus2_init, 357 .init_machine = omap_perseus2_init,
358 .timer = &omap_timer, 358 .timer = &omap1_timer,
359MACHINE_END 359MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0ad781db4e66..9c3b7c52d9cf 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -411,7 +411,7 @@ static void __init omap_sx1_init(void)
411static void __init omap_sx1_init_irq(void) 411static void __init omap_sx1_init_irq(void)
412{ 412{
413 omap1_init_common_hw(); 413 omap1_init_common_hw();
414 omap_init_irq(); 414 omap1_init_irq();
415} 415}
416/*----------------------------------------*/ 416/*----------------------------------------*/
417 417
@@ -426,5 +426,5 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
426 .reserve = omap_reserve, 426 .reserve = omap_reserve,
427 .init_irq = omap_sx1_init_irq, 427 .init_irq = omap_sx1_init_irq,
428 .init_machine = omap_sx1_init, 428 .init_machine = omap_sx1_init,
429 .timer = &omap_timer, 429 .timer = &omap1_timer,
430MACHINE_END 430MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 65d24204937a..036edc0ee9b6 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -162,7 +162,7 @@ static struct omap_board_config_kernel voiceblue_config[] = {
162static void __init voiceblue_init_irq(void) 162static void __init voiceblue_init_irq(void)
163{ 163{
164 omap1_init_common_hw(); 164 omap1_init_common_hw();
165 omap_init_irq(); 165 omap1_init_irq();
166} 166}
167 167
168static void __init voiceblue_map_io(void) 168static void __init voiceblue_map_io(void)
@@ -306,5 +306,5 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
306 .reserve = omap_reserve, 306 .reserve = omap_reserve,
307 .init_irq = voiceblue_init_irq, 307 .init_irq = voiceblue_init_irq,
308 .init_machine = voiceblue_init, 308 .init_machine = voiceblue_init,
309 .timer = &omap_timer, 309 .timer = &omap1_timer,
310MACHINE_END 310MACHINE_END
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 5d3da7a63af3..e2b9c901ab67 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -175,7 +175,7 @@ static struct irq_chip omap_irq_chip = {
175 .irq_set_wake = omap_wake_irq, 175 .irq_set_wake = omap_wake_irq,
176}; 176};
177 177
178void __init omap_init_irq(void) 178void __init omap1_init_irq(void)
179{ 179{
180 int i, j; 180 int i, j;
181 181
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index d9af9811dedd..ab7395d84bc8 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -38,7 +38,7 @@ static void omap1_mcbsp_request(unsigned int id)
38 * On 1510, 1610 and 1710, McBSP1 and McBSP3 38 * On 1510, 1610 and 1710, McBSP1 and McBSP3
39 * are DSP public peripherals. 39 * are DSP public peripherals.
40 */ 40 */
41 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { 41 if (id == 0 || id == 2) {
42 if (dsp_use++ == 0) { 42 if (dsp_use++ == 0) {
43 api_clk = clk_get(NULL, "api_ck"); 43 api_clk = clk_get(NULL, "api_ck");
44 dsp_clk = clk_get(NULL, "dsp_ck"); 44 dsp_clk = clk_get(NULL, "dsp_ck");
@@ -59,7 +59,7 @@ static void omap1_mcbsp_request(unsigned int id)
59 59
60static void omap1_mcbsp_free(unsigned int id) 60static void omap1_mcbsp_free(unsigned int id)
61{ 61{
62 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { 62 if (id == 0 || id == 2) {
63 if (--dsp_use == 0) { 63 if (--dsp_use == 0) {
64 if (!IS_ERR(api_clk)) { 64 if (!IS_ERR(api_clk)) {
65 clk_disable(api_clk); 65 clk_disable(api_clk);
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
index fe31d933f0ed..334fb8871bc3 100644
--- a/arch/arm/mach-omap1/pm_bus.c
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -56,9 +56,13 @@ static struct dev_power_domain default_power_domain = {
56 USE_PLATFORM_PM_SLEEP_OPS 56 USE_PLATFORM_PM_SLEEP_OPS
57 }, 57 },
58}; 58};
59#define OMAP1_PWR_DOMAIN (&default_power_domain)
60#else
61#define OMAP1_PWR_DOMAIN NULL
62#endif /* CONFIG_PM_RUNTIME */
59 63
60static struct pm_clk_notifier_block platform_bus_notifier = { 64static struct pm_clk_notifier_block platform_bus_notifier = {
61 .pwr_domain = &default_power_domain, 65 .pwr_domain = OMAP1_PWR_DOMAIN,
62 .con_ids = { "ick", "fck", NULL, }, 66 .con_ids = { "ick", "fck", NULL, },
63}; 67};
64 68
@@ -72,4 +76,4 @@ static int __init omap1_pm_runtime_init(void)
72 return 0; 76 return 0;
73} 77}
74core_initcall(omap1_pm_runtime_init); 78core_initcall(omap1_pm_runtime_init);
75#endif /* CONFIG_PM_RUNTIME */ 79
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 03e1e1062ad4..a1837771e031 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -297,7 +297,7 @@ static inline int omap_32k_timer_usable(void)
297 * Timer initialization 297 * Timer initialization
298 * --------------------------------------------------------------------------- 298 * ---------------------------------------------------------------------------
299 */ 299 */
300static void __init omap_timer_init(void) 300static void __init omap1_timer_init(void)
301{ 301{
302 if (omap_32k_timer_usable()) { 302 if (omap_32k_timer_usable()) {
303 preferred_sched_clock_init(1); 303 preferred_sched_clock_init(1);
@@ -307,6 +307,6 @@ static void __init omap_timer_init(void)
307 } 307 }
308} 308}
309 309
310struct sys_timer omap_timer = { 310struct sys_timer omap1_timer = {
311 .init = omap_timer_init, 311 .init = omap1_timer_init,
312}; 312};
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 13d7b8f145bd..96604a50c4fe 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -183,10 +183,6 @@ static __init void omap_init_32k_timer(void)
183bool __init omap_32k_timer_init(void) 183bool __init omap_32k_timer_init(void)
184{ 184{
185 omap_init_clocksource_32k(); 185 omap_init_clocksource_32k();
186
187#ifdef CONFIG_OMAP_DM_TIMER
188 omap_dm_timer_init();
189#endif
190 omap_init_32k_timer(); 186 omap_init_32k_timer();
191 187
192 return true; 188 return true;
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b14807794401..f34336560437 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o 7 common.o gpio.o dma.o wd_timer.o
8 8
9omap-2-3-common = irq.o sdrc.o 9omap-2-3-common = irq.o sdrc.o
@@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
145obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o 145obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
146 146
147# hwmod data 147# hwmod data
148obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o 148obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
149obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o 149 omap_hwmod_2xxx_3xxx_ipblock_data.o \
150obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 150 omap_hwmod_2xxx_interconnect_data.o \
151 omap_hwmod_2xxx_3xxx_interconnect_data.o \
152 omap_hwmod_2420_data.o
153obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
154 omap_hwmod_2xxx_3xxx_ipblock_data.o \
155 omap_hwmod_2xxx_interconnect_data.o \
156 omap_hwmod_2xxx_3xxx_interconnect_data.o \
157 omap_hwmod_2430_data.o
158obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
159 omap_hwmod_2xxx_3xxx_interconnect_data.o \
160 omap_hwmod_3xxx_data.o
151obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 161obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
152 162
153# EMU peripherals 163# EMU peripherals
@@ -269,4 +279,4 @@ obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
269disp-$(CONFIG_OMAP2_DSS) := display.o 279disp-$(CONFIG_OMAP2_DSS) := display.o
270obj-y += $(disp-m) $(disp-y) 280obj-y += $(disp-m) $(disp-y)
271 281
272obj-y += common-board-devices.o 282obj-y += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 5de6eac0a725..2028464cf5b9 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -260,7 +260,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
260 .reserve = omap_reserve, 260 .reserve = omap_reserve,
261 .map_io = omap_2430sdp_map_io, 261 .map_io = omap_2430sdp_map_io,
262 .init_early = omap_2430sdp_init_early, 262 .init_early = omap_2430sdp_init_early,
263 .init_irq = omap_init_irq, 263 .init_irq = omap2_init_irq,
264 .init_machine = omap_2430sdp_init, 264 .init_machine = omap_2430sdp_init,
265 .timer = &omap_timer, 265 .timer = &omap2_timer,
266MACHINE_END 266MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5dac974be625..bd600cfb7f80 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -231,22 +231,6 @@ static void __init omap_3430sdp_init_early(void)
231 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); 231 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
232} 232}
233 233
234static int sdp3430_batt_table[] = {
235/* 0 C*/
23630800, 29500, 28300, 27100,
23726000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
23817200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
23911600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
2408020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
2415640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
2424040, 3910, 3790, 3670, 3550
243};
244
245static struct twl4030_bci_platform_data sdp3430_bci_data = {
246 .battery_tmp_tbl = sdp3430_batt_table,
247 .tblsize = ARRAY_SIZE(sdp3430_batt_table),
248};
249
250static struct omap2_hsmmc_info mmc[] = { 234static struct omap2_hsmmc_info mmc[] = {
251 { 235 {
252 .mmc = 1, 236 .mmc = 1,
@@ -292,14 +276,6 @@ static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
292 .setup = sdp3430_twl_gpio_setup, 276 .setup = sdp3430_twl_gpio_setup,
293}; 277};
294 278
295static struct twl4030_usb_data sdp3430_usb_data = {
296 .usb_mode = T2_USB_MODE_ULPI,
297};
298
299static struct twl4030_madc_platform_data sdp3430_madc_data = {
300 .irq_line = 1,
301};
302
303/* regulator consumer mappings */ 279/* regulator consumer mappings */
304 280
305/* ads7846 on SPI */ 281/* ads7846 on SPI */
@@ -307,16 +283,6 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
307 REGULATOR_SUPPLY("vcc", "spi1.0"), 283 REGULATOR_SUPPLY("vcc", "spi1.0"),
308}; 284};
309 285
310static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
311 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
312};
313
314/* VPLL2 for digital video outputs */
315static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
316 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
317 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
318};
319
320static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { 286static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
321 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), 287 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
322}; 288};
@@ -433,54 +399,10 @@ static struct regulator_init_data sdp3430_vsim = {
433 .consumer_supplies = sdp3430_vsim_supplies, 399 .consumer_supplies = sdp3430_vsim_supplies,
434}; 400};
435 401
436/* VDAC for DSS driving S-Video */
437static struct regulator_init_data sdp3430_vdac = {
438 .constraints = {
439 .min_uV = 1800000,
440 .max_uV = 1800000,
441 .apply_uV = true,
442 .valid_modes_mask = REGULATOR_MODE_NORMAL
443 | REGULATOR_MODE_STANDBY,
444 .valid_ops_mask = REGULATOR_CHANGE_MODE
445 | REGULATOR_CHANGE_STATUS,
446 },
447 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
448 .consumer_supplies = sdp3430_vdda_dac_supplies,
449};
450
451static struct regulator_init_data sdp3430_vpll2 = {
452 .constraints = {
453 .name = "VDVI",
454 .min_uV = 1800000,
455 .max_uV = 1800000,
456 .apply_uV = true,
457 .valid_modes_mask = REGULATOR_MODE_NORMAL
458 | REGULATOR_MODE_STANDBY,
459 .valid_ops_mask = REGULATOR_CHANGE_MODE
460 | REGULATOR_CHANGE_STATUS,
461 },
462 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
463 .consumer_supplies = sdp3430_vpll2_supplies,
464};
465
466static struct twl4030_codec_audio_data sdp3430_audio;
467
468static struct twl4030_codec_data sdp3430_codec = {
469 .audio_mclk = 26000000,
470 .audio = &sdp3430_audio,
471};
472
473static struct twl4030_platform_data sdp3430_twldata = { 402static struct twl4030_platform_data sdp3430_twldata = {
474 .irq_base = TWL4030_IRQ_BASE,
475 .irq_end = TWL4030_IRQ_END,
476
477 /* platform_data for children goes here */ 403 /* platform_data for children goes here */
478 .bci = &sdp3430_bci_data,
479 .gpio = &sdp3430_gpio_data, 404 .gpio = &sdp3430_gpio_data,
480 .madc = &sdp3430_madc_data,
481 .keypad = &sdp3430_kp_data, 405 .keypad = &sdp3430_kp_data,
482 .usb = &sdp3430_usb_data,
483 .codec = &sdp3430_codec,
484 406
485 .vaux1 = &sdp3430_vaux1, 407 .vaux1 = &sdp3430_vaux1,
486 .vaux2 = &sdp3430_vaux2, 408 .vaux2 = &sdp3430_vaux2,
@@ -489,14 +411,21 @@ static struct twl4030_platform_data sdp3430_twldata = {
489 .vmmc1 = &sdp3430_vmmc1, 411 .vmmc1 = &sdp3430_vmmc1,
490 .vmmc2 = &sdp3430_vmmc2, 412 .vmmc2 = &sdp3430_vmmc2,
491 .vsim = &sdp3430_vsim, 413 .vsim = &sdp3430_vsim,
492 .vdac = &sdp3430_vdac,
493 .vpll2 = &sdp3430_vpll2,
494}; 414};
495 415
496static int __init omap3430_i2c_init(void) 416static int __init omap3430_i2c_init(void)
497{ 417{
498 /* i2c1 for PMIC only */ 418 /* i2c1 for PMIC only */
419 omap3_pmic_get_config(&sdp3430_twldata,
420 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
421 TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
422 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
423 sdp3430_twldata.vdac->constraints.apply_uV = true;
424 sdp3430_twldata.vpll2->constraints.apply_uV = true;
425 sdp3430_twldata.vpll2->constraints.name = "VDVI";
426
499 omap3_pmic_init("twl4030", &sdp3430_twldata); 427 omap3_pmic_init("twl4030", &sdp3430_twldata);
428
500 /* i2c2 on camera connector (for sensor control) and optional isp1301 */ 429 /* i2c2 on camera connector (for sensor control) and optional isp1301 */
501 omap_register_i2c_bus(2, 400, NULL, 0); 430 omap_register_i2c_bus(2, 400, NULL, 0);
502 /* i2c3 on display connector (for DVI, tfp410) */ 431 /* i2c3 on display connector (for DVI, tfp410) */
@@ -804,7 +733,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
804 .reserve = omap_reserve, 733 .reserve = omap_reserve,
805 .map_io = omap3_map_io, 734 .map_io = omap3_map_io,
806 .init_early = omap_3430sdp_init_early, 735 .init_early = omap_3430sdp_init_early,
807 .init_irq = omap_init_irq, 736 .init_irq = omap3_init_irq,
808 .init_machine = omap_3430sdp_init, 737 .init_machine = omap_3430sdp_init,
809 .timer = &omap_timer, 738 .timer = &omap3_timer,
810MACHINE_END 739MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index a5933cc15caa..e4f37b57a0c4 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -219,7 +219,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
219 .reserve = omap_reserve, 219 .reserve = omap_reserve,
220 .map_io = omap3_map_io, 220 .map_io = omap3_map_io,
221 .init_early = omap_sdp_init_early, 221 .init_early = omap_sdp_init_early,
222 .init_irq = omap_init_irq, 222 .init_irq = omap3_init_irq,
223 .init_machine = omap_sdp_init, 223 .init_machine = omap_sdp_init,
224 .timer = &omap_timer, 224 .timer = &omap3_timer,
225MACHINE_END 225MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 63de2d396e2d..933b25bb10de 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -40,7 +40,6 @@
40 40
41#include "mux.h" 41#include "mux.h"
42#include "hsmmc.h" 42#include "hsmmc.h"
43#include "timer-gp.h"
44#include "control.h" 43#include "control.h"
45#include "common-board-devices.h" 44#include "common-board-devices.h"
46 45
@@ -295,9 +294,6 @@ static void __init omap_4430sdp_init_early(void)
295{ 294{
296 omap2_init_common_infrastructure(); 295 omap2_init_common_infrastructure();
297 omap2_init_common_devices(NULL, NULL); 296 omap2_init_common_devices(NULL, NULL);
298#ifdef CONFIG_OMAP_32K_TIMER
299 omap2_gp_clockevent_set_gptimer(1);
300#endif
301} 297}
302 298
303static struct omap_musb_board_data musb_board_data = { 299static struct omap_musb_board_data musb_board_data = {
@@ -306,14 +302,6 @@ static struct omap_musb_board_data musb_board_data = {
306 .power = 100, 302 .power = 100,
307}; 303};
308 304
309static struct twl4030_usb_data omap4_usbphy_data = {
310 .phy_init = omap4430_phy_init,
311 .phy_exit = omap4430_phy_exit,
312 .phy_power = omap4430_phy_power,
313 .phy_set_clock = omap4430_phy_set_clk,
314 .phy_suspend = omap4430_phy_suspend,
315};
316
317static struct omap2_hsmmc_info mmc[] = { 305static struct omap2_hsmmc_info mmc[] = {
318 { 306 {
319 .mmc = 2, 307 .mmc = 2,
@@ -333,16 +321,7 @@ static struct omap2_hsmmc_info mmc[] = {
333}; 321};
334 322
335static struct regulator_consumer_supply sdp4430_vaux_supply[] = { 323static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
336 { 324 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
337 .supply = "vmmc",
338 .dev_name = "omap_hsmmc.1",
339 },
340};
341static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
342 {
343 .supply = "vmmc",
344 .dev_name = "omap_hsmmc.0",
345 },
346}; 325};
347 326
348static int omap4_twl6030_hsmmc_late_init(struct device *dev) 327static int omap4_twl6030_hsmmc_late_init(struct device *dev)
@@ -399,65 +378,10 @@ static struct regulator_init_data sdp4430_vaux1 = {
399 | REGULATOR_CHANGE_MODE 378 | REGULATOR_CHANGE_MODE
400 | REGULATOR_CHANGE_STATUS, 379 | REGULATOR_CHANGE_STATUS,
401 }, 380 },
402 .num_consumer_supplies = 1, 381 .num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply),
403 .consumer_supplies = sdp4430_vaux_supply, 382 .consumer_supplies = sdp4430_vaux_supply,
404}; 383};
405 384
406static struct regulator_init_data sdp4430_vaux2 = {
407 .constraints = {
408 .min_uV = 1200000,
409 .max_uV = 2800000,
410 .apply_uV = true,
411 .valid_modes_mask = REGULATOR_MODE_NORMAL
412 | REGULATOR_MODE_STANDBY,
413 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
414 | REGULATOR_CHANGE_MODE
415 | REGULATOR_CHANGE_STATUS,
416 },
417};
418
419static struct regulator_init_data sdp4430_vaux3 = {
420 .constraints = {
421 .min_uV = 1000000,
422 .max_uV = 3000000,
423 .apply_uV = true,
424 .valid_modes_mask = REGULATOR_MODE_NORMAL
425 | REGULATOR_MODE_STANDBY,
426 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
427 | REGULATOR_CHANGE_MODE
428 | REGULATOR_CHANGE_STATUS,
429 },
430};
431
432/* VMMC1 for MMC1 card */
433static struct regulator_init_data sdp4430_vmmc = {
434 .constraints = {
435 .min_uV = 1200000,
436 .max_uV = 3000000,
437 .apply_uV = true,
438 .valid_modes_mask = REGULATOR_MODE_NORMAL
439 | REGULATOR_MODE_STANDBY,
440 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
441 | REGULATOR_CHANGE_MODE
442 | REGULATOR_CHANGE_STATUS,
443 },
444 .num_consumer_supplies = 1,
445 .consumer_supplies = sdp4430_vmmc_supply,
446};
447
448static struct regulator_init_data sdp4430_vpp = {
449 .constraints = {
450 .min_uV = 1800000,
451 .max_uV = 2500000,
452 .apply_uV = true,
453 .valid_modes_mask = REGULATOR_MODE_NORMAL
454 | REGULATOR_MODE_STANDBY,
455 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
456 | REGULATOR_CHANGE_MODE
457 | REGULATOR_CHANGE_STATUS,
458 },
459};
460
461static struct regulator_init_data sdp4430_vusim = { 385static struct regulator_init_data sdp4430_vusim = {
462 .constraints = { 386 .constraints = {
463 .min_uV = 1200000, 387 .min_uV = 1200000,
@@ -471,74 +395,10 @@ static struct regulator_init_data sdp4430_vusim = {
471 }, 395 },
472}; 396};
473 397
474static struct regulator_init_data sdp4430_vana = {
475 .constraints = {
476 .min_uV = 2100000,
477 .max_uV = 2100000,
478 .valid_modes_mask = REGULATOR_MODE_NORMAL
479 | REGULATOR_MODE_STANDBY,
480 .valid_ops_mask = REGULATOR_CHANGE_MODE
481 | REGULATOR_CHANGE_STATUS,
482 },
483};
484
485static struct regulator_init_data sdp4430_vcxio = {
486 .constraints = {
487 .min_uV = 1800000,
488 .max_uV = 1800000,
489 .valid_modes_mask = REGULATOR_MODE_NORMAL
490 | REGULATOR_MODE_STANDBY,
491 .valid_ops_mask = REGULATOR_CHANGE_MODE
492 | REGULATOR_CHANGE_STATUS,
493 },
494};
495
496static struct regulator_init_data sdp4430_vdac = {
497 .constraints = {
498 .min_uV = 1800000,
499 .max_uV = 1800000,
500 .valid_modes_mask = REGULATOR_MODE_NORMAL
501 | REGULATOR_MODE_STANDBY,
502 .valid_ops_mask = REGULATOR_CHANGE_MODE
503 | REGULATOR_CHANGE_STATUS,
504 },
505};
506
507static struct regulator_init_data sdp4430_vusb = {
508 .constraints = {
509 .min_uV = 3300000,
510 .max_uV = 3300000,
511 .apply_uV = true,
512 .valid_modes_mask = REGULATOR_MODE_NORMAL
513 | REGULATOR_MODE_STANDBY,
514 .valid_ops_mask = REGULATOR_CHANGE_MODE
515 | REGULATOR_CHANGE_STATUS,
516 },
517};
518
519static struct regulator_init_data sdp4430_clk32kg = {
520 .constraints = {
521 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
522 },
523};
524
525static struct twl4030_platform_data sdp4430_twldata = { 398static struct twl4030_platform_data sdp4430_twldata = {
526 .irq_base = TWL6030_IRQ_BASE,
527 .irq_end = TWL6030_IRQ_END,
528
529 /* Regulators */ 399 /* Regulators */
530 .vmmc = &sdp4430_vmmc,
531 .vpp = &sdp4430_vpp,
532 .vusim = &sdp4430_vusim, 400 .vusim = &sdp4430_vusim,
533 .vana = &sdp4430_vana,
534 .vcxio = &sdp4430_vcxio,
535 .vdac = &sdp4430_vdac,
536 .vusb = &sdp4430_vusb,
537 .vaux1 = &sdp4430_vaux1, 401 .vaux1 = &sdp4430_vaux1,
538 .vaux2 = &sdp4430_vaux2,
539 .vaux3 = &sdp4430_vaux3,
540 .clk32kg = &sdp4430_clk32kg,
541 .usb = &omap4_usbphy_data
542}; 402};
543 403
544static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { 404static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
@@ -556,6 +416,16 @@ static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
556}; 416};
557static int __init omap4_i2c_init(void) 417static int __init omap4_i2c_init(void)
558{ 418{
419 omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
420 TWL_COMMON_REGULATOR_VDAC |
421 TWL_COMMON_REGULATOR_VAUX2 |
422 TWL_COMMON_REGULATOR_VAUX3 |
423 TWL_COMMON_REGULATOR_VMMC |
424 TWL_COMMON_REGULATOR_VPP |
425 TWL_COMMON_REGULATOR_VANA |
426 TWL_COMMON_REGULATOR_VCXIO |
427 TWL_COMMON_REGULATOR_VUSB |
428 TWL_COMMON_REGULATOR_CLK32KG);
559 omap4_pmic_init("twl6030", &sdp4430_twldata); 429 omap4_pmic_init("twl6030", &sdp4430_twldata);
560 omap_register_i2c_bus(2, 400, NULL, 0); 430 omap_register_i2c_bus(2, 400, NULL, 0);
561 omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, 431 omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
@@ -773,5 +643,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
773 .init_early = omap_4430sdp_init_early, 643 .init_early = omap_4430sdp_init_early,
774 .init_irq = gic_init_irq, 644 .init_irq = gic_init_irq,
775 .init_machine = omap_4430sdp_init, 645 .init_machine = omap_4430sdp_init,
776 .timer = &omap_timer, 646 .timer = &omap4_timer,
777MACHINE_END 647MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 5e438a77cd72..5f2b55ff04ff 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -104,7 +104,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
104 .reserve = omap_reserve, 104 .reserve = omap_reserve,
105 .map_io = omap3_map_io, 105 .map_io = omap3_map_io,
106 .init_early = am3517_crane_init_early, 106 .init_early = am3517_crane_init_early,
107 .init_irq = omap_init_irq, 107 .init_irq = omap3_init_irq,
108 .init_machine = am3517_crane_init, 108 .init_machine = am3517_crane_init,
109 .timer = &omap_timer, 109 .timer = &omap3_timer,
110MACHINE_END 110MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 63af4171c043..f3006c304150 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -494,7 +494,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
494 .reserve = omap_reserve, 494 .reserve = omap_reserve,
495 .map_io = omap3_map_io, 495 .map_io = omap3_map_io,
496 .init_early = am3517_evm_init_early, 496 .init_early = am3517_evm_init_early,
497 .init_irq = omap_init_irq, 497 .init_irq = omap3_init_irq,
498 .init_machine = am3517_evm_init, 498 .init_machine = am3517_evm_init,
499 .timer = &omap_timer, 499 .timer = &omap3_timer,
500MACHINE_END 500MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index b124bdfb4239..70211703ff9f 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -354,7 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
354 .reserve = omap_reserve, 354 .reserve = omap_reserve,
355 .map_io = omap_apollon_map_io, 355 .map_io = omap_apollon_map_io,
356 .init_early = omap_apollon_init_early, 356 .init_early = omap_apollon_init_early,
357 .init_irq = omap_init_irq, 357 .init_irq = omap2_init_irq,
358 .init_machine = omap_apollon_init, 358 .init_machine = omap_apollon_init,
359 .timer = &omap_timer, 359 .timer = &omap2_timer,
360MACHINE_END 360MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 77456dec93ea..35891d49c631 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -162,9 +162,7 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
162static struct omap_nand_platform_data cm_t35_nand_data = { 162static struct omap_nand_platform_data cm_t35_nand_data = {
163 .parts = cm_t35_nand_partitions, 163 .parts = cm_t35_nand_partitions,
164 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), 164 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
165 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
166 .cs = 0, 165 .cs = 0,
167
168}; 166};
169 167
170static void __init cm_t35_init_nand(void) 168static void __init cm_t35_init_nand(void)
@@ -337,19 +335,17 @@ static void __init cm_t35_init_display(void)
337 } 335 }
338} 336}
339 337
340static struct regulator_consumer_supply cm_t35_vmmc1_supply = { 338static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
341 .supply = "vmmc", 339 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
342}; 340};
343 341
344static struct regulator_consumer_supply cm_t35_vsim_supply = { 342static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
345 .supply = "vmmc_aux", 343 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
346}; 344};
347 345
348static struct regulator_consumer_supply cm_t35_vdac_supply = 346static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
349 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 347 REGULATOR_SUPPLY("vdvi", "omapdss"),
350 348};
351static struct regulator_consumer_supply cm_t35_vdvi_supply =
352 REGULATOR_SUPPLY("vdvi", "omapdss");
353 349
354/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 350/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
355static struct regulator_init_data cm_t35_vmmc1 = { 351static struct regulator_init_data cm_t35_vmmc1 = {
@@ -362,8 +358,8 @@ static struct regulator_init_data cm_t35_vmmc1 = {
362 | REGULATOR_CHANGE_MODE 358 | REGULATOR_CHANGE_MODE
363 | REGULATOR_CHANGE_STATUS, 359 | REGULATOR_CHANGE_STATUS,
364 }, 360 },
365 .num_consumer_supplies = 1, 361 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
366 .consumer_supplies = &cm_t35_vmmc1_supply, 362 .consumer_supplies = cm_t35_vmmc1_supply,
367}; 363};
368 364
369/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 365/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -377,41 +373,8 @@ static struct regulator_init_data cm_t35_vsim = {
377 | REGULATOR_CHANGE_MODE 373 | REGULATOR_CHANGE_MODE
378 | REGULATOR_CHANGE_STATUS, 374 | REGULATOR_CHANGE_STATUS,
379 }, 375 },
380 .num_consumer_supplies = 1, 376 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
381 .consumer_supplies = &cm_t35_vsim_supply, 377 .consumer_supplies = cm_t35_vsim_supply,
382};
383
384/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
385static struct regulator_init_data cm_t35_vdac = {
386 .constraints = {
387 .min_uV = 1800000,
388 .max_uV = 1800000,
389 .valid_modes_mask = REGULATOR_MODE_NORMAL
390 | REGULATOR_MODE_STANDBY,
391 .valid_ops_mask = REGULATOR_CHANGE_MODE
392 | REGULATOR_CHANGE_STATUS,
393 },
394 .num_consumer_supplies = 1,
395 .consumer_supplies = &cm_t35_vdac_supply,
396};
397
398/* VPLL2 for digital video outputs */
399static struct regulator_init_data cm_t35_vpll2 = {
400 .constraints = {
401 .name = "VDVI",
402 .min_uV = 1800000,
403 .max_uV = 1800000,
404 .valid_modes_mask = REGULATOR_MODE_NORMAL
405 | REGULATOR_MODE_STANDBY,
406 .valid_ops_mask = REGULATOR_CHANGE_MODE
407 | REGULATOR_CHANGE_STATUS,
408 },
409 .num_consumer_supplies = 1,
410 .consumer_supplies = &cm_t35_vdvi_supply,
411};
412
413static struct twl4030_usb_data cm_t35_usb_data = {
414 .usb_mode = T2_USB_MODE_ULPI,
415}; 378};
416 379
417static uint32_t cm_t35_keymap[] = { 380static uint32_t cm_t35_keymap[] = {
@@ -481,10 +444,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
481 mmc[0].gpio_cd = gpio + 0; 444 mmc[0].gpio_cd = gpio + 0;
482 omap2_hsmmc_init(mmc); 445 omap2_hsmmc_init(mmc);
483 446
484 /* link regulators to MMC adapters */
485 cm_t35_vmmc1_supply.dev = mmc[0].dev;
486 cm_t35_vsim_supply.dev = mmc[0].dev;
487
488 return 0; 447 return 0;
489} 448}
490 449
@@ -496,21 +455,23 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
496}; 455};
497 456
498static struct twl4030_platform_data cm_t35_twldata = { 457static struct twl4030_platform_data cm_t35_twldata = {
499 .irq_base = TWL4030_IRQ_BASE,
500 .irq_end = TWL4030_IRQ_END,
501
502 /* platform_data for children goes here */ 458 /* platform_data for children goes here */
503 .keypad = &cm_t35_kp_data, 459 .keypad = &cm_t35_kp_data,
504 .usb = &cm_t35_usb_data,
505 .gpio = &cm_t35_gpio_data, 460 .gpio = &cm_t35_gpio_data,
506 .vmmc1 = &cm_t35_vmmc1, 461 .vmmc1 = &cm_t35_vmmc1,
507 .vsim = &cm_t35_vsim, 462 .vsim = &cm_t35_vsim,
508 .vdac = &cm_t35_vdac,
509 .vpll2 = &cm_t35_vpll2,
510}; 463};
511 464
512static void __init cm_t35_init_i2c(void) 465static void __init cm_t35_init_i2c(void)
513{ 466{
467 omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
468 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
469
470 cm_t35_twldata.vpll2->constraints.name = "VDVI";
471 cm_t35_twldata.vpll2->num_consumer_supplies =
472 ARRAY_SIZE(cm_t35_vdvi_supply);
473 cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
474
514 omap3_pmic_init("tps65930", &cm_t35_twldata); 475 omap3_pmic_init("tps65930", &cm_t35_twldata);
515} 476}
516 477
@@ -646,7 +607,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
646 .reserve = omap_reserve, 607 .reserve = omap_reserve,
647 .map_io = omap3_map_io, 608 .map_io = omap3_map_io,
648 .init_early = cm_t35_init_early, 609 .init_early = cm_t35_init_early,
649 .init_irq = omap_init_irq, 610 .init_irq = omap3_init_irq,
650 .init_machine = cm_t35_init, 611 .init_machine = cm_t35_init,
651 .timer = &omap_timer, 612 .timer = &omap3_timer,
652MACHINE_END 613MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index c3a9fd35034a..05c72f4c1b57 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -236,7 +236,6 @@ static struct mtd_partition cm_t3517_nand_partitions[] = {
236static struct omap_nand_platform_data cm_t3517_nand_data = { 236static struct omap_nand_platform_data cm_t3517_nand_data = {
237 .parts = cm_t3517_nand_partitions, 237 .parts = cm_t3517_nand_partitions,
238 .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions), 238 .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions),
239 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
240 .cs = 0, 239 .cs = 0,
241}; 240};
242 241
@@ -304,7 +303,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
304 .reserve = omap_reserve, 303 .reserve = omap_reserve,
305 .map_io = omap3_map_io, 304 .map_io = omap3_map_io,
306 .init_early = cm_t3517_init_early, 305 .init_early = cm_t3517_init_early,
307 .init_irq = omap_init_irq, 306 .init_irq = omap3_init_irq,
308 .init_machine = cm_t3517_init, 307 .init_machine = cm_t3517_init,
309 .timer = &omap_timer, 308 .timer = &omap3_timer,
310MACHINE_END 309MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 34956ec83296..b6002ec31c6a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -58,7 +58,6 @@
58 58
59#include "mux.h" 59#include "mux.h"
60#include "hsmmc.h" 60#include "hsmmc.h"
61#include "timer-gp.h"
62#include "common-board-devices.h" 61#include "common-board-devices.h"
63 62
64#define OMAP_DM9000_GPIO_IRQ 25 63#define OMAP_DM9000_GPIO_IRQ 25
@@ -130,13 +129,14 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
130 gpio_set_value_cansleep(dssdev->reset_gpio, 0); 129 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
131} 130}
132 131
133static struct regulator_consumer_supply devkit8000_vmmc1_supply = 132static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
134 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 133 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
135 134};
136 135
137/* ads7846 on SPI */ 136/* ads7846 on SPI */
138static struct regulator_consumer_supply devkit8000_vio_supply = 137static struct regulator_consumer_supply devkit8000_vio_supply[] = {
139 REGULATOR_SUPPLY("vcc", "spi2.0"); 138 REGULATOR_SUPPLY("vcc", "spi2.0"),
139};
140 140
141static struct panel_generic_dpi_data lcd_panel = { 141static struct panel_generic_dpi_data lcd_panel = {
142 .name = "generic", 142 .name = "generic",
@@ -186,9 +186,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
186 .default_device = &devkit8000_lcd_device, 186 .default_device = &devkit8000_lcd_device,
187}; 187};
188 188
189static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
190 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
191
192static uint32_t board_keymap[] = { 189static uint32_t board_keymap[] = {
193 KEY(0, 0, KEY_1), 190 KEY(0, 0, KEY_1),
194 KEY(1, 0, KEY_2), 191 KEY(1, 0, KEY_2),
@@ -284,22 +281,8 @@ static struct regulator_init_data devkit8000_vmmc1 = {
284 | REGULATOR_CHANGE_MODE 281 | REGULATOR_CHANGE_MODE
285 | REGULATOR_CHANGE_STATUS, 282 | REGULATOR_CHANGE_STATUS,
286 }, 283 },
287 .num_consumer_supplies = 1, 284 .num_consumer_supplies = ARRAY_SIZE(devkit8000_vmmc1_supply),
288 .consumer_supplies = &devkit8000_vmmc1_supply, 285 .consumer_supplies = devkit8000_vmmc1_supply,
289};
290
291/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
292static struct regulator_init_data devkit8000_vdac = {
293 .constraints = {
294 .min_uV = 1800000,
295 .max_uV = 1800000,
296 .valid_modes_mask = REGULATOR_MODE_NORMAL
297 | REGULATOR_MODE_STANDBY,
298 .valid_ops_mask = REGULATOR_CHANGE_MODE
299 | REGULATOR_CHANGE_STATUS,
300 },
301 .num_consumer_supplies = 1,
302 .consumer_supplies = &devkit8000_vdda_dac_supply,
303}; 286};
304 287
305/* VPLL1 for digital video outputs */ 288/* VPLL1 for digital video outputs */
@@ -327,31 +310,14 @@ static struct regulator_init_data devkit8000_vio = {
327 .valid_ops_mask = REGULATOR_CHANGE_MODE 310 .valid_ops_mask = REGULATOR_CHANGE_MODE
328 | REGULATOR_CHANGE_STATUS, 311 | REGULATOR_CHANGE_STATUS,
329 }, 312 },
330 .num_consumer_supplies = 1, 313 .num_consumer_supplies = ARRAY_SIZE(devkit8000_vio_supply),
331 .consumer_supplies = &devkit8000_vio_supply, 314 .consumer_supplies = devkit8000_vio_supply,
332};
333
334static struct twl4030_usb_data devkit8000_usb_data = {
335 .usb_mode = T2_USB_MODE_ULPI,
336};
337
338static struct twl4030_codec_audio_data devkit8000_audio_data;
339
340static struct twl4030_codec_data devkit8000_codec_data = {
341 .audio_mclk = 26000000,
342 .audio = &devkit8000_audio_data,
343}; 315};
344 316
345static struct twl4030_platform_data devkit8000_twldata = { 317static struct twl4030_platform_data devkit8000_twldata = {
346 .irq_base = TWL4030_IRQ_BASE,
347 .irq_end = TWL4030_IRQ_END,
348
349 /* platform_data for children goes here */ 318 /* platform_data for children goes here */
350 .usb = &devkit8000_usb_data,
351 .gpio = &devkit8000_gpio_data, 319 .gpio = &devkit8000_gpio_data,
352 .codec = &devkit8000_codec_data,
353 .vmmc1 = &devkit8000_vmmc1, 320 .vmmc1 = &devkit8000_vmmc1,
354 .vdac = &devkit8000_vdac,
355 .vpll1 = &devkit8000_vpll1, 321 .vpll1 = &devkit8000_vpll1,
356 .vio = &devkit8000_vio, 322 .vio = &devkit8000_vio,
357 .keypad = &devkit8000_kp_data, 323 .keypad = &devkit8000_kp_data,
@@ -359,6 +325,9 @@ static struct twl4030_platform_data devkit8000_twldata = {
359 325
360static int __init devkit8000_i2c_init(void) 326static int __init devkit8000_i2c_init(void)
361{ 327{
328 omap3_pmic_get_config(&devkit8000_twldata,
329 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
330 TWL_COMMON_REGULATOR_VDAC);
362 omap3_pmic_init("tps65930", &devkit8000_twldata); 331 omap3_pmic_init("tps65930", &devkit8000_twldata);
363 /* Bus 3 is attached to the DVI port where devices like the pico DLP 332 /* Bus 3 is attached to the DVI port where devices like the pico DLP
364 * projector don't work reliably with 400kHz */ 333 * projector don't work reliably with 400kHz */
@@ -438,10 +407,7 @@ static void __init devkit8000_init_early(void)
438 407
439static void __init devkit8000_init_irq(void) 408static void __init devkit8000_init_irq(void)
440{ 409{
441 omap_init_irq(); 410 omap3_init_irq();
442#ifdef CONFIG_OMAP_32K_TIMER
443 omap2_gp_clockevent_set_gptimer(12);
444#endif
445} 411}
446 412
447#define OMAP_DM9000_BASE 0x2c000000 413#define OMAP_DM9000_BASE 0x2c000000
@@ -707,5 +673,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
707 .init_early = devkit8000_init_early, 673 .init_early = devkit8000_init_early,
708 .init_irq = devkit8000_init_irq, 674 .init_irq = devkit8000_init_irq,
709 .init_machine = devkit8000_init, 675 .init_machine = devkit8000_init,
710 .timer = &omap_timer, 676 .timer = &omap3_secure_timer,
711MACHINE_END 677MACHINE_END
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 729892fdcf2e..aa1b0cbe19d2 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -132,11 +132,7 @@ static struct gpmc_timings nand_timings = {
132}; 132};
133 133
134static struct omap_nand_platform_data board_nand_data = { 134static struct omap_nand_platform_data board_nand_data = {
135 .nand_setup = NULL,
136 .gpmc_t = &nand_timings, 135 .gpmc_t = &nand_timings,
137 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
138 .dev_ready = NULL,
139 .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */
140}; 136};
141 137
142void 138void
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 73e3c31e8508..54db41a84a9b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -70,7 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
70 .reserve = omap_reserve, 70 .reserve = omap_reserve,
71 .map_io = omap_generic_map_io, 71 .map_io = omap_generic_map_io,
72 .init_early = omap_generic_init_early, 72 .init_early = omap_generic_init_early,
73 .init_irq = omap_init_irq, 73 .init_irq = omap2_init_irq,
74 .init_machine = omap_generic_init, 74 .init_machine = omap_generic_init,
75 .timer = &omap_timer, 75 .timer = &omap2_timer,
76MACHINE_END 76MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index bac7933b8cbb..45de2b319ec9 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -298,7 +298,7 @@ static void __init omap_h4_init_early(void)
298 298
299static void __init omap_h4_init_irq(void) 299static void __init omap_h4_init_irq(void)
300{ 300{
301 omap_init_irq(); 301 omap2_init_irq();
302} 302}
303 303
304static struct at24_platform_data m24c01 = { 304static struct at24_platform_data m24c01 = {
@@ -388,5 +388,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
388 .init_early = omap_h4_init_early, 388 .init_early = omap_h4_init_early,
389 .init_irq = omap_h4_init_irq, 389 .init_irq = omap_h4_init_irq,
390 .init_machine = omap_h4_init, 390 .init_machine = omap_h4_init,
391 .timer = &omap_timer, 391 .timer = &omap2_timer,
392MACHINE_END 392MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 0c1bfca3f731..35be778caf1b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -222,8 +222,9 @@ static inline void __init igep2_init_smsc911x(void)
222static inline void __init igep2_init_smsc911x(void) { } 222static inline void __init igep2_init_smsc911x(void) { }
223#endif 223#endif
224 224
225static struct regulator_consumer_supply igep_vmmc1_supply = 225static struct regulator_consumer_supply igep_vmmc1_supply[] = {
226 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 226 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
227};
227 228
228/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 229/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
229static struct regulator_init_data igep_vmmc1 = { 230static struct regulator_init_data igep_vmmc1 = {
@@ -236,12 +237,13 @@ static struct regulator_init_data igep_vmmc1 = {
236 | REGULATOR_CHANGE_MODE 237 | REGULATOR_CHANGE_MODE
237 | REGULATOR_CHANGE_STATUS, 238 | REGULATOR_CHANGE_STATUS,
238 }, 239 },
239 .num_consumer_supplies = 1, 240 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply),
240 .consumer_supplies = &igep_vmmc1_supply, 241 .consumer_supplies = igep_vmmc1_supply,
241}; 242};
242 243
243static struct regulator_consumer_supply igep_vio_supply = 244static struct regulator_consumer_supply igep_vio_supply[] = {
244 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); 245 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
246};
245 247
246static struct regulator_init_data igep_vio = { 248static struct regulator_init_data igep_vio = {
247 .constraints = { 249 .constraints = {
@@ -254,20 +256,21 @@ static struct regulator_init_data igep_vio = {
254 | REGULATOR_CHANGE_MODE 256 | REGULATOR_CHANGE_MODE
255 | REGULATOR_CHANGE_STATUS, 257 | REGULATOR_CHANGE_STATUS,
256 }, 258 },
257 .num_consumer_supplies = 1, 259 .num_consumer_supplies = ARRAY_SIZE(igep_vio_supply),
258 .consumer_supplies = &igep_vio_supply, 260 .consumer_supplies = igep_vio_supply,
259}; 261};
260 262
261static struct regulator_consumer_supply igep_vmmc2_supply = 263static struct regulator_consumer_supply igep_vmmc2_supply[] = {
262 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); 264 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
265};
263 266
264static struct regulator_init_data igep_vmmc2 = { 267static struct regulator_init_data igep_vmmc2 = {
265 .constraints = { 268 .constraints = {
266 .valid_modes_mask = REGULATOR_MODE_NORMAL, 269 .valid_modes_mask = REGULATOR_MODE_NORMAL,
267 .always_on = 1, 270 .always_on = 1,
268 }, 271 },
269 .num_consumer_supplies = 1, 272 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply),
270 .consumer_supplies = &igep_vmmc2_supply, 273 .consumer_supplies = igep_vmmc2_supply,
271}; 274};
272 275
273static struct fixed_voltage_config igep_vwlan = { 276static struct fixed_voltage_config igep_vwlan = {
@@ -440,10 +443,6 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
440 .setup = igep_twl_gpio_setup, 443 .setup = igep_twl_gpio_setup,
441}; 444};
442 445
443static struct twl4030_usb_data igep_usb_data = {
444 .usb_mode = T2_USB_MODE_ULPI,
445};
446
447static int igep2_enable_dvi(struct omap_dss_device *dssdev) 446static int igep2_enable_dvi(struct omap_dss_device *dssdev)
448{ 447{
449 gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1); 448 gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
@@ -480,26 +479,6 @@ static struct omap_dss_board_info igep2_dss_data = {
480 .default_device = &igep2_dvi_device, 479 .default_device = &igep2_dvi_device,
481}; 480};
482 481
483static struct regulator_consumer_supply igep2_vpll2_supplies[] = {
484 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
485 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
486};
487
488static struct regulator_init_data igep2_vpll2 = {
489 .constraints = {
490 .name = "VDVI",
491 .min_uV = 1800000,
492 .max_uV = 1800000,
493 .apply_uV = true,
494 .valid_modes_mask = REGULATOR_MODE_NORMAL
495 | REGULATOR_MODE_STANDBY,
496 .valid_ops_mask = REGULATOR_CHANGE_MODE
497 | REGULATOR_CHANGE_STATUS,
498 },
499 .num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies),
500 .consumer_supplies = igep2_vpll2_supplies,
501};
502
503static void __init igep2_display_init(void) 482static void __init igep2_display_init(void)
504{ 483{
505 int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH, 484 int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
@@ -519,13 +498,6 @@ static void __init igep_init_early(void)
519 m65kxxxxam_sdrc_params); 498 m65kxxxxam_sdrc_params);
520} 499}
521 500
522static struct twl4030_codec_audio_data igep2_audio_data;
523
524static struct twl4030_codec_data igep2_codec_data = {
525 .audio_mclk = 26000000,
526 .audio = &igep2_audio_data,
527};
528
529static int igep2_keymap[] = { 501static int igep2_keymap[] = {
530 KEY(0, 0, KEY_LEFT), 502 KEY(0, 0, KEY_LEFT),
531 KEY(0, 1, KEY_RIGHT), 503 KEY(0, 1, KEY_RIGHT),
@@ -558,11 +530,7 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
558}; 530};
559 531
560static struct twl4030_platform_data igep_twldata = { 532static struct twl4030_platform_data igep_twldata = {
561 .irq_base = TWL4030_IRQ_BASE,
562 .irq_end = TWL4030_IRQ_END,
563
564 /* platform_data for children goes here */ 533 /* platform_data for children goes here */
565 .usb = &igep_usb_data,
566 .gpio = &igep_twl4030_gpio_pdata, 534 .gpio = &igep_twl4030_gpio_pdata,
567 .vmmc1 = &igep_vmmc1, 535 .vmmc1 = &igep_vmmc1,
568 .vio = &igep_vio, 536 .vio = &igep_vio,
@@ -578,6 +546,8 @@ static void __init igep_i2c_init(void)
578{ 546{
579 int ret; 547 int ret;
580 548
549 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
550
581 if (machine_is_igep0020()) { 551 if (machine_is_igep0020()) {
582 /* 552 /*
583 * Bus 3 is attached to the DVI port where devices like the 553 * Bus 3 is attached to the DVI port where devices like the
@@ -588,9 +558,12 @@ static void __init igep_i2c_init(void)
588 if (ret) 558 if (ret)
589 pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret); 559 pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
590 560
591 igep_twldata.codec = &igep2_codec_data;
592 igep_twldata.keypad = &igep2_keypad_pdata; 561 igep_twldata.keypad = &igep2_keypad_pdata;
593 igep_twldata.vpll2 = &igep2_vpll2; 562 /* Get common pmic data */
563 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
564 TWL_COMMON_REGULATOR_VPLL2);
565 igep_twldata.vpll2->constraints.apply_uV = true;
566 igep_twldata.vpll2->constraints.name = "VDVI";
594 } 567 }
595 568
596 omap3_pmic_init("twl4030", &igep_twldata); 569 omap3_pmic_init("twl4030", &igep_twldata);
@@ -703,9 +676,9 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
703 .reserve = omap_reserve, 676 .reserve = omap_reserve,
704 .map_io = omap3_map_io, 677 .map_io = omap3_map_io,
705 .init_early = igep_init_early, 678 .init_early = igep_init_early,
706 .init_irq = omap_init_irq, 679 .init_irq = omap3_init_irq,
707 .init_machine = igep_init, 680 .init_machine = igep_init,
708 .timer = &omap_timer, 681 .timer = &omap3_timer,
709MACHINE_END 682MACHINE_END
710 683
711MACHINE_START(IGEP0030, "IGEP OMAP3 module") 684MACHINE_START(IGEP0030, "IGEP OMAP3 module")
@@ -713,7 +686,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
713 .reserve = omap_reserve, 686 .reserve = omap_reserve,
714 .map_io = omap3_map_io, 687 .map_io = omap3_map_io,
715 .init_early = igep_init_early, 688 .init_early = igep_init_early,
716 .init_irq = omap_init_irq, 689 .init_irq = omap3_init_irq,
717 .init_machine = igep_init, 690 .init_machine = igep_init,
718 .timer = &omap_timer, 691 .timer = &omap3_timer,
719MACHINE_END 692MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f7d6038075f0..218764c9377e 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -199,22 +199,14 @@ static void __init omap_ldp_init_early(void)
199 omap2_init_common_devices(NULL, NULL); 199 omap2_init_common_devices(NULL, NULL);
200} 200}
201 201
202static struct twl4030_usb_data ldp_usb_data = {
203 .usb_mode = T2_USB_MODE_ULPI,
204};
205
206static struct twl4030_gpio_platform_data ldp_gpio_data = { 202static struct twl4030_gpio_platform_data ldp_gpio_data = {
207 .gpio_base = OMAP_MAX_GPIO_LINES, 203 .gpio_base = OMAP_MAX_GPIO_LINES,
208 .irq_base = TWL4030_GPIO_IRQ_BASE, 204 .irq_base = TWL4030_GPIO_IRQ_BASE,
209 .irq_end = TWL4030_GPIO_IRQ_END, 205 .irq_end = TWL4030_GPIO_IRQ_END,
210}; 206};
211 207
212static struct twl4030_madc_platform_data ldp_madc_data = { 208static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
213 .irq_line = 1, 209 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
214};
215
216static struct regulator_consumer_supply ldp_vmmc1_supply = {
217 .supply = "vmmc",
218}; 210};
219 211
220/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 212/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -228,8 +220,8 @@ static struct regulator_init_data ldp_vmmc1 = {
228 | REGULATOR_CHANGE_MODE 220 | REGULATOR_CHANGE_MODE
229 | REGULATOR_CHANGE_STATUS, 221 | REGULATOR_CHANGE_STATUS,
230 }, 222 },
231 .num_consumer_supplies = 1, 223 .num_consumer_supplies = ARRAY_SIZE(ldp_vmmc1_supply),
232 .consumer_supplies = &ldp_vmmc1_supply, 224 .consumer_supplies = ldp_vmmc1_supply,
233}; 225};
234 226
235/* ads7846 on SPI */ 227/* ads7846 on SPI */
@@ -253,12 +245,7 @@ static struct regulator_init_data ldp_vaux1 = {
253}; 245};
254 246
255static struct twl4030_platform_data ldp_twldata = { 247static struct twl4030_platform_data ldp_twldata = {
256 .irq_base = TWL4030_IRQ_BASE,
257 .irq_end = TWL4030_IRQ_END,
258
259 /* platform_data for children goes here */ 248 /* platform_data for children goes here */
260 .madc = &ldp_madc_data,
261 .usb = &ldp_usb_data,
262 .vmmc1 = &ldp_vmmc1, 249 .vmmc1 = &ldp_vmmc1,
263 .vaux1 = &ldp_vaux1, 250 .vaux1 = &ldp_vaux1,
264 .gpio = &ldp_gpio_data, 251 .gpio = &ldp_gpio_data,
@@ -267,6 +254,8 @@ static struct twl4030_platform_data ldp_twldata = {
267 254
268static int __init omap_i2c_init(void) 255static int __init omap_i2c_init(void)
269{ 256{
257 omap3_pmic_get_config(&ldp_twldata,
258 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
270 omap3_pmic_init("twl4030", &ldp_twldata); 259 omap3_pmic_init("twl4030", &ldp_twldata);
271 omap_register_i2c_bus(2, 400, NULL, 0); 260 omap_register_i2c_bus(2, 400, NULL, 0);
272 omap_register_i2c_bus(3, 400, NULL, 0); 261 omap_register_i2c_bus(3, 400, NULL, 0);
@@ -341,8 +330,6 @@ static void __init omap_ldp_init(void)
341 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); 330 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
342 331
343 omap2_hsmmc_init(mmc); 332 omap2_hsmmc_init(mmc);
344 /* link regulators to MMC adapters */
345 ldp_vmmc1_supply.dev = mmc[0].dev;
346} 333}
347 334
348MACHINE_START(OMAP_LDP, "OMAP LDP board") 335MACHINE_START(OMAP_LDP, "OMAP LDP board")
@@ -350,7 +337,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
350 .reserve = omap_reserve, 337 .reserve = omap_reserve,
351 .map_io = omap3_map_io, 338 .map_io = omap3_map_io,
352 .init_early = omap_ldp_init_early, 339 .init_early = omap_ldp_init_early,
353 .init_irq = omap_init_irq, 340 .init_irq = omap3_init_irq,
354 .init_machine = omap_ldp_init, 341 .init_machine = omap_ldp_init,
355 .timer = &omap_timer, 342 .timer = &omap3_timer,
356MACHINE_END 343MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 8d74318ed495..e11f0c5d608a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -699,9 +699,9 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
699 .reserve = omap_reserve, 699 .reserve = omap_reserve,
700 .map_io = n8x0_map_io, 700 .map_io = n8x0_map_io,
701 .init_early = n8x0_init_early, 701 .init_early = n8x0_init_early,
702 .init_irq = omap_init_irq, 702 .init_irq = omap2_init_irq,
703 .init_machine = n8x0_init_machine, 703 .init_machine = n8x0_init_machine,
704 .timer = &omap_timer, 704 .timer = &omap2_timer,
705MACHINE_END 705MACHINE_END
706 706
707MACHINE_START(NOKIA_N810, "Nokia N810") 707MACHINE_START(NOKIA_N810, "Nokia N810")
@@ -709,9 +709,9 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
709 .reserve = omap_reserve, 709 .reserve = omap_reserve,
710 .map_io = n8x0_map_io, 710 .map_io = n8x0_map_io,
711 .init_early = n8x0_init_early, 711 .init_early = n8x0_init_early,
712 .init_irq = omap_init_irq, 712 .init_irq = omap2_init_irq,
713 .init_machine = n8x0_init_machine, 713 .init_machine = n8x0_init_machine,
714 .timer = &omap_timer, 714 .timer = &omap2_timer,
715MACHINE_END 715MACHINE_END
716 716
717MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") 717MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
@@ -719,7 +719,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
719 .reserve = omap_reserve, 719 .reserve = omap_reserve,
720 .map_io = n8x0_map_io, 720 .map_io = n8x0_map_io,
721 .init_early = n8x0_init_early, 721 .init_early = n8x0_init_early,
722 .init_irq = omap_init_irq, 722 .init_irq = omap2_init_irq,
723 .init_machine = n8x0_init_machine, 723 .init_machine = n8x0_init_machine,
724 .timer = &omap_timer, 724 .timer = &omap2_timer,
725MACHINE_END 725MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7f21d24bd437..34f841112768 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -50,7 +50,6 @@
50 50
51#include "mux.h" 51#include "mux.h"
52#include "hsmmc.h" 52#include "hsmmc.h"
53#include "timer-gp.h"
54#include "pm.h" 53#include "pm.h"
55#include "common-board-devices.h" 54#include "common-board-devices.h"
56 55
@@ -210,14 +209,6 @@ static struct omap_dss_board_info beagle_dss_data = {
210 .default_device = &beagle_dvi_device, 209 .default_device = &beagle_dvi_device,
211}; 210};
212 211
213static struct regulator_consumer_supply beagle_vdac_supply =
214 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
215
216static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
217 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
218 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
219};
220
221static void __init beagle_display_init(void) 212static void __init beagle_display_init(void)
222{ 213{
223 int r; 214 int r;
@@ -239,12 +230,12 @@ static struct omap2_hsmmc_info mmc[] = {
239 {} /* Terminator */ 230 {} /* Terminator */
240}; 231};
241 232
242static struct regulator_consumer_supply beagle_vmmc1_supply = { 233static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
243 .supply = "vmmc", 234 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
244}; 235};
245 236
246static struct regulator_consumer_supply beagle_vsim_supply = { 237static struct regulator_consumer_supply beagle_vsim_supply[] = {
247 .supply = "vmmc_aux", 238 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
248}; 239};
249 240
250static struct gpio_led gpio_leds[]; 241static struct gpio_led gpio_leds[];
@@ -267,10 +258,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
267 mmc[0].gpio_cd = gpio + 0; 258 mmc[0].gpio_cd = gpio + 0;
268 omap2_hsmmc_init(mmc); 259 omap2_hsmmc_init(mmc);
269 260
270 /* link regulators to MMC adapters */
271 beagle_vmmc1_supply.dev = mmc[0].dev;
272 beagle_vsim_supply.dev = mmc[0].dev;
273
274 /* 261 /*
275 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active 262 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
276 * high / others active low) 263 * high / others active low)
@@ -336,8 +323,8 @@ static struct regulator_init_data beagle_vmmc1 = {
336 | REGULATOR_CHANGE_MODE 323 | REGULATOR_CHANGE_MODE
337 | REGULATOR_CHANGE_STATUS, 324 | REGULATOR_CHANGE_STATUS,
338 }, 325 },
339 .num_consumer_supplies = 1, 326 .num_consumer_supplies = ARRAY_SIZE(beagle_vmmc1_supply),
340 .consumer_supplies = &beagle_vmmc1_supply, 327 .consumer_supplies = beagle_vmmc1_supply,
341}; 328};
342 329
343/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 330/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -351,62 +338,15 @@ static struct regulator_init_data beagle_vsim = {
351 | REGULATOR_CHANGE_MODE 338 | REGULATOR_CHANGE_MODE
352 | REGULATOR_CHANGE_STATUS, 339 | REGULATOR_CHANGE_STATUS,
353 }, 340 },
354 .num_consumer_supplies = 1, 341 .num_consumer_supplies = ARRAY_SIZE(beagle_vsim_supply),
355 .consumer_supplies = &beagle_vsim_supply, 342 .consumer_supplies = beagle_vsim_supply,
356};
357
358/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
359static struct regulator_init_data beagle_vdac = {
360 .constraints = {
361 .min_uV = 1800000,
362 .max_uV = 1800000,
363 .valid_modes_mask = REGULATOR_MODE_NORMAL
364 | REGULATOR_MODE_STANDBY,
365 .valid_ops_mask = REGULATOR_CHANGE_MODE
366 | REGULATOR_CHANGE_STATUS,
367 },
368 .num_consumer_supplies = 1,
369 .consumer_supplies = &beagle_vdac_supply,
370};
371
372/* VPLL2 for digital video outputs */
373static struct regulator_init_data beagle_vpll2 = {
374 .constraints = {
375 .name = "VDVI",
376 .min_uV = 1800000,
377 .max_uV = 1800000,
378 .valid_modes_mask = REGULATOR_MODE_NORMAL
379 | REGULATOR_MODE_STANDBY,
380 .valid_ops_mask = REGULATOR_CHANGE_MODE
381 | REGULATOR_CHANGE_STATUS,
382 },
383 .num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies),
384 .consumer_supplies = beagle_vdvi_supplies,
385};
386
387static struct twl4030_usb_data beagle_usb_data = {
388 .usb_mode = T2_USB_MODE_ULPI,
389};
390
391static struct twl4030_codec_audio_data beagle_audio_data;
392
393static struct twl4030_codec_data beagle_codec_data = {
394 .audio_mclk = 26000000,
395 .audio = &beagle_audio_data,
396}; 343};
397 344
398static struct twl4030_platform_data beagle_twldata = { 345static struct twl4030_platform_data beagle_twldata = {
399 .irq_base = TWL4030_IRQ_BASE,
400 .irq_end = TWL4030_IRQ_END,
401
402 /* platform_data for children goes here */ 346 /* platform_data for children goes here */
403 .usb = &beagle_usb_data,
404 .gpio = &beagle_gpio_data, 347 .gpio = &beagle_gpio_data,
405 .codec = &beagle_codec_data,
406 .vmmc1 = &beagle_vmmc1, 348 .vmmc1 = &beagle_vmmc1,
407 .vsim = &beagle_vsim, 349 .vsim = &beagle_vsim,
408 .vdac = &beagle_vdac,
409 .vpll2 = &beagle_vpll2,
410}; 350};
411 351
412static struct i2c_board_info __initdata beagle_i2c_eeprom[] = { 352static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
@@ -417,6 +357,12 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
417 357
418static int __init omap3_beagle_i2c_init(void) 358static int __init omap3_beagle_i2c_init(void)
419{ 359{
360 omap3_pmic_get_config(&beagle_twldata,
361 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
362 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
363
364 beagle_twldata.vpll2->constraints.name = "VDVI";
365
420 omap3_pmic_init("twl4030", &beagle_twldata); 366 omap3_pmic_init("twl4030", &beagle_twldata);
421 /* Bus 3 is attached to the DVI port where devices like the pico DLP 367 /* Bus 3 is attached to the DVI port where devices like the pico DLP
422 * projector don't work reliably with 400kHz */ 368 * projector don't work reliably with 400kHz */
@@ -486,10 +432,7 @@ static void __init omap3_beagle_init_early(void)
486 432
487static void __init omap3_beagle_init_irq(void) 433static void __init omap3_beagle_init_irq(void)
488{ 434{
489 omap_init_irq(); 435 omap3_init_irq();
490#ifdef CONFIG_OMAP_32K_TIMER
491 omap2_gp_clockevent_set_gptimer(12);
492#endif
493} 436}
494 437
495static struct platform_device *omap3_beagle_devices[] __initdata = { 438static struct platform_device *omap3_beagle_devices[] __initdata = {
@@ -599,5 +542,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
599 .init_early = omap3_beagle_init_early, 542 .init_early = omap3_beagle_init_early,
600 .init_irq = omap3_beagle_init_irq, 543 .init_irq = omap3_beagle_init_irq,
601 .init_machine = omap3_beagle_init, 544 .init_machine = omap3_beagle_init,
602 .timer = &omap_timer, 545 .timer = &omap3_secure_timer,
603MACHINE_END 546MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b4d43464a303..c452b3f3331a 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -273,12 +273,12 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
273 .default_device = &omap3_evm_lcd_device, 273 .default_device = &omap3_evm_lcd_device,
274}; 274};
275 275
276static struct regulator_consumer_supply omap3evm_vmmc1_supply = { 276static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
277 .supply = "vmmc", 277 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
278}; 278};
279 279
280static struct regulator_consumer_supply omap3evm_vsim_supply = { 280static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
281 .supply = "vmmc_aux", 281 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
282}; 282};
283 283
284/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 284/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -292,8 +292,8 @@ static struct regulator_init_data omap3evm_vmmc1 = {
292 | REGULATOR_CHANGE_MODE 292 | REGULATOR_CHANGE_MODE
293 | REGULATOR_CHANGE_STATUS, 293 | REGULATOR_CHANGE_STATUS,
294 }, 294 },
295 .num_consumer_supplies = 1, 295 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
296 .consumer_supplies = &omap3evm_vmmc1_supply, 296 .consumer_supplies = omap3evm_vmmc1_supply,
297}; 297};
298 298
299/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 299/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -307,8 +307,8 @@ static struct regulator_init_data omap3evm_vsim = {
307 | REGULATOR_CHANGE_MODE 307 | REGULATOR_CHANGE_MODE
308 | REGULATOR_CHANGE_STATUS, 308 | REGULATOR_CHANGE_STATUS,
309 }, 309 },
310 .num_consumer_supplies = 1, 310 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
311 .consumer_supplies = &omap3evm_vsim_supply, 311 .consumer_supplies = omap3evm_vsim_supply,
312}; 312};
313 313
314static struct omap2_hsmmc_info mmc[] = { 314static struct omap2_hsmmc_info mmc[] = {
@@ -365,10 +365,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
365 mmc[0].gpio_cd = gpio + 0; 365 mmc[0].gpio_cd = gpio + 0;
366 omap2_hsmmc_init(mmc); 366 omap2_hsmmc_init(mmc);
367 367
368 /* link regulators to MMC adapters */
369 omap3evm_vmmc1_supply.dev = mmc[0].dev;
370 omap3evm_vsim_supply.dev = mmc[0].dev;
371
372 /* 368 /*
373 * Most GPIOs are for USB OTG. Some are mostly sent to 369 * Most GPIOs are for USB OTG. Some are mostly sent to
374 * the P2 connector; notably LEDA for the LCD backlight. 370 * the P2 connector; notably LEDA for the LCD backlight.
@@ -400,10 +396,6 @@ static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
400 .setup = omap3evm_twl_gpio_setup, 396 .setup = omap3evm_twl_gpio_setup,
401}; 397};
402 398
403static struct twl4030_usb_data omap3evm_usb_data = {
404 .usb_mode = T2_USB_MODE_ULPI,
405};
406
407static uint32_t board_keymap[] = { 399static uint32_t board_keymap[] = {
408 KEY(0, 0, KEY_LEFT), 400 KEY(0, 0, KEY_LEFT),
409 KEY(0, 1, KEY_DOWN), 401 KEY(0, 1, KEY_DOWN),
@@ -438,58 +430,10 @@ static struct twl4030_keypad_data omap3evm_kp_data = {
438 .rep = 1, 430 .rep = 1,
439}; 431};
440 432
441static struct twl4030_madc_platform_data omap3evm_madc_data = {
442 .irq_line = 1,
443};
444
445static struct twl4030_codec_audio_data omap3evm_audio_data;
446
447static struct twl4030_codec_data omap3evm_codec_data = {
448 .audio_mclk = 26000000,
449 .audio = &omap3evm_audio_data,
450};
451
452static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
453 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
454
455/* VDAC for DSS driving S-Video */
456static struct regulator_init_data omap3_evm_vdac = {
457 .constraints = {
458 .min_uV = 1800000,
459 .max_uV = 1800000,
460 .apply_uV = true,
461 .valid_modes_mask = REGULATOR_MODE_NORMAL
462 | REGULATOR_MODE_STANDBY,
463 .valid_ops_mask = REGULATOR_CHANGE_MODE
464 | REGULATOR_CHANGE_STATUS,
465 },
466 .num_consumer_supplies = 1,
467 .consumer_supplies = &omap3_evm_vdda_dac_supply,
468};
469
470/* VPLL2 for digital video outputs */
471static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
472 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
473 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
474};
475
476static struct regulator_init_data omap3_evm_vpll2 = {
477 .constraints = {
478 .min_uV = 1800000,
479 .max_uV = 1800000,
480 .apply_uV = true,
481 .valid_modes_mask = REGULATOR_MODE_NORMAL
482 | REGULATOR_MODE_STANDBY,
483 .valid_ops_mask = REGULATOR_CHANGE_MODE
484 | REGULATOR_CHANGE_STATUS,
485 },
486 .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies),
487 .consumer_supplies = omap3_evm_vpll2_supplies,
488};
489
490/* ads7846 on SPI */ 433/* ads7846 on SPI */
491static struct regulator_consumer_supply omap3evm_vio_supply = 434static struct regulator_consumer_supply omap3evm_vio_supply[] = {
492 REGULATOR_SUPPLY("vcc", "spi1.0"); 435 REGULATOR_SUPPLY("vcc", "spi1.0"),
436};
493 437
494/* VIO for ads7846 */ 438/* VIO for ads7846 */
495static struct regulator_init_data omap3evm_vio = { 439static struct regulator_init_data omap3evm_vio = {
@@ -502,8 +446,8 @@ static struct regulator_init_data omap3evm_vio = {
502 .valid_ops_mask = REGULATOR_CHANGE_MODE 446 .valid_ops_mask = REGULATOR_CHANGE_MODE
503 | REGULATOR_CHANGE_STATUS, 447 | REGULATOR_CHANGE_STATUS,
504 }, 448 },
505 .num_consumer_supplies = 1, 449 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
506 .consumer_supplies = &omap3evm_vio_supply, 450 .consumer_supplies = omap3evm_vio_supply,
507}; 451};
508 452
509#ifdef CONFIG_WL12XX_PLATFORM_DATA 453#ifdef CONFIG_WL12XX_PLATFORM_DATA
@@ -511,16 +455,17 @@ static struct regulator_init_data omap3evm_vio = {
511#define OMAP3EVM_WLAN_PMENA_GPIO (150) 455#define OMAP3EVM_WLAN_PMENA_GPIO (150)
512#define OMAP3EVM_WLAN_IRQ_GPIO (149) 456#define OMAP3EVM_WLAN_IRQ_GPIO (149)
513 457
514static struct regulator_consumer_supply omap3evm_vmmc2_supply = 458static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
515 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); 459 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
460};
516 461
517/* VMMC2 for driving the WL12xx module */ 462/* VMMC2 for driving the WL12xx module */
518static struct regulator_init_data omap3evm_vmmc2 = { 463static struct regulator_init_data omap3evm_vmmc2 = {
519 .constraints = { 464 .constraints = {
520 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 465 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
521 }, 466 },
522 .num_consumer_supplies = 1, 467 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
523 .consumer_supplies = &omap3evm_vmmc2_supply, 468 .consumer_supplies = omap3evm_vmmc2_supply,
524}; 469};
525 470
526static struct fixed_voltage_config omap3evm_vwlan = { 471static struct fixed_voltage_config omap3evm_vwlan = {
@@ -548,17 +493,9 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
548#endif 493#endif
549 494
550static struct twl4030_platform_data omap3evm_twldata = { 495static struct twl4030_platform_data omap3evm_twldata = {
551 .irq_base = TWL4030_IRQ_BASE,
552 .irq_end = TWL4030_IRQ_END,
553
554 /* platform_data for children goes here */ 496 /* platform_data for children goes here */
555 .keypad = &omap3evm_kp_data, 497 .keypad = &omap3evm_kp_data,
556 .madc = &omap3evm_madc_data,
557 .usb = &omap3evm_usb_data,
558 .gpio = &omap3evm_gpio_data, 498 .gpio = &omap3evm_gpio_data,
559 .codec = &omap3evm_codec_data,
560 .vdac = &omap3_evm_vdac,
561 .vpll2 = &omap3_evm_vpll2,
562 .vio = &omap3evm_vio, 499 .vio = &omap3evm_vio,
563 .vmmc1 = &omap3evm_vmmc1, 500 .vmmc1 = &omap3evm_vmmc1,
564 .vsim = &omap3evm_vsim, 501 .vsim = &omap3evm_vsim,
@@ -566,6 +503,14 @@ static struct twl4030_platform_data omap3evm_twldata = {
566 503
567static int __init omap3_evm_i2c_init(void) 504static int __init omap3_evm_i2c_init(void)
568{ 505{
506 omap3_pmic_get_config(&omap3evm_twldata,
507 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
508 TWL_COMMON_PDATA_AUDIO,
509 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
510
511 omap3evm_twldata.vdac->constraints.apply_uV = true;
512 omap3evm_twldata.vpll2->constraints.apply_uV = true;
513
569 omap3_pmic_init("twl4030", &omap3evm_twldata); 514 omap3_pmic_init("twl4030", &omap3evm_twldata);
570 omap_register_i2c_bus(2, 400, NULL, 0); 515 omap_register_i2c_bus(2, 400, NULL, 0);
571 omap_register_i2c_bus(3, 400, NULL, 0); 516 omap_register_i2c_bus(3, 400, NULL, 0);
@@ -740,7 +685,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
740 .reserve = omap_reserve, 685 .reserve = omap_reserve,
741 .map_io = omap3_map_io, 686 .map_io = omap3_map_io,
742 .init_early = omap3_evm_init_early, 687 .init_early = omap3_evm_init_early,
743 .init_irq = omap_init_irq, 688 .init_irq = omap3_init_irq,
744 .init_machine = omap3_evm_init, 689 .init_machine = omap3_evm_init,
745 .timer = &omap_timer, 690 .timer = &omap3_timer,
746MACHINE_END 691MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 60d9be49dbab..703aeb5b8fd4 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -35,7 +35,6 @@
35 35
36#include "mux.h" 36#include "mux.h"
37#include "hsmmc.h" 37#include "hsmmc.h"
38#include "timer-gp.h"
39#include "control.h" 38#include "control.h"
40#include "common-board-devices.h" 39#include "common-board-devices.h"
41 40
@@ -55,8 +54,8 @@
55#define OMAP3_TORPEDO_MMC_GPIO_CD 127 54#define OMAP3_TORPEDO_MMC_GPIO_CD 127
56#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129 55#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129
57 56
58static struct regulator_consumer_supply omap3logic_vmmc1_supply = { 57static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = {
59 .supply = "vmmc", 58 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
60}; 59};
61 60
62/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 61/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -71,8 +70,8 @@ static struct regulator_init_data omap3logic_vmmc1 = {
71 | REGULATOR_CHANGE_MODE 70 | REGULATOR_CHANGE_MODE
72 | REGULATOR_CHANGE_STATUS, 71 | REGULATOR_CHANGE_STATUS,
73 }, 72 },
74 .num_consumer_supplies = 1, 73 .num_consumer_supplies = ARRAY_SIZE(omap3logic_vmmc1_supply),
75 .consumer_supplies = &omap3logic_vmmc1_supply, 74 .consumer_supplies = omap3logic_vmmc1_supply,
76}; 75};
77 76
78static struct twl4030_gpio_platform_data omap3logic_gpio_data = { 77static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
@@ -130,8 +129,6 @@ static void __init board_mmc_init(void)
130 } 129 }
131 130
132 omap2_hsmmc_init(board_mmc_info); 131 omap2_hsmmc_init(board_mmc_info);
133 /* link regulators to MMC adapters */
134 omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
135} 132}
136 133
137static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = { 134static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
@@ -215,16 +212,16 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
215 .boot_params = 0x80000100, 212 .boot_params = 0x80000100,
216 .map_io = omap3_map_io, 213 .map_io = omap3_map_io,
217 .init_early = omap3logic_init_early, 214 .init_early = omap3logic_init_early,
218 .init_irq = omap_init_irq, 215 .init_irq = omap3_init_irq,
219 .init_machine = omap3logic_init, 216 .init_machine = omap3logic_init,
220 .timer = &omap_timer, 217 .timer = &omap3_timer,
221MACHINE_END 218MACHINE_END
222 219
223MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") 220MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
224 .boot_params = 0x80000100, 221 .boot_params = 0x80000100,
225 .map_io = omap3_map_io, 222 .map_io = omap3_map_io,
226 .init_early = omap3logic_init_early, 223 .init_early = omap3logic_init_early,
227 .init_irq = omap_init_irq, 224 .init_irq = omap3_init_irq,
228 .init_machine = omap3logic_init, 225 .init_machine = omap3logic_init,
229 .timer = &omap_timer, 226 .timer = &omap3_timer,
230MACHINE_END 227MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 2a0bb4818cae..080d7bd6795e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -84,7 +84,8 @@ static struct mtd_partition omap3pandora_nand_partitions[] = {
84 84
85static struct omap_nand_platform_data pandora_nand_data = { 85static struct omap_nand_platform_data pandora_nand_data = {
86 .cs = 0, 86 .cs = 0,
87 .devsize = 1, /* '0' for 8-bit, '1' for 16-bit device */ 87 .devsize = NAND_BUSWIDTH_16,
88 .xfer_type = NAND_OMAP_PREFETCH_DMA,
88 .parts = omap3pandora_nand_partitions, 89 .parts = omap3pandora_nand_partitions,
89 .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions), 90 .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions),
90}; 91};
@@ -319,17 +320,17 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
319 .setup = omap3pandora_twl_gpio_setup, 320 .setup = omap3pandora_twl_gpio_setup,
320}; 321};
321 322
322static struct regulator_consumer_supply pandora_vmmc1_supply = 323static struct regulator_consumer_supply pandora_vmmc1_supply[] = {
323 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 324 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
324 325};
325static struct regulator_consumer_supply pandora_vmmc2_supply =
326 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
327 326
328static struct regulator_consumer_supply pandora_vmmc3_supply = 327static struct regulator_consumer_supply pandora_vmmc2_supply[] = {
329 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"); 328 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1")
329};
330 330
331static struct regulator_consumer_supply pandora_vdda_dac_supply = 331static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
332 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); 332 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
333};
333 334
334static struct regulator_consumer_supply pandora_vdds_supplies[] = { 335static struct regulator_consumer_supply pandora_vdds_supplies[] = {
335 REGULATOR_SUPPLY("vdds_sdi", "omapdss"), 336 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
@@ -337,11 +338,13 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
337 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), 338 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
338}; 339};
339 340
340static struct regulator_consumer_supply pandora_vcc_lcd_supply = 341static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
341 REGULATOR_SUPPLY("vcc", "display0"); 342 REGULATOR_SUPPLY("vcc", "display0"),
343};
342 344
343static struct regulator_consumer_supply pandora_usb_phy_supply = 345static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
344 REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"); 346 REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
347};
345 348
346/* ads7846 on SPI and 2 nub controllers on I2C */ 349/* ads7846 on SPI and 2 nub controllers on I2C */
347static struct regulator_consumer_supply pandora_vaux4_supplies[] = { 350static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
@@ -350,8 +353,9 @@ static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
350 REGULATOR_SUPPLY("vcc", "3-0067"), 353 REGULATOR_SUPPLY("vcc", "3-0067"),
351}; 354};
352 355
353static struct regulator_consumer_supply pandora_adac_supply = 356static struct regulator_consumer_supply pandora_adac_supply[] = {
354 REGULATOR_SUPPLY("vcc", "soc-audio"); 357 REGULATOR_SUPPLY("vcc", "soc-audio"),
358};
355 359
356/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 360/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
357static struct regulator_init_data pandora_vmmc1 = { 361static struct regulator_init_data pandora_vmmc1 = {
@@ -364,8 +368,8 @@ static struct regulator_init_data pandora_vmmc1 = {
364 | REGULATOR_CHANGE_MODE 368 | REGULATOR_CHANGE_MODE
365 | REGULATOR_CHANGE_STATUS, 369 | REGULATOR_CHANGE_STATUS,
366 }, 370 },
367 .num_consumer_supplies = 1, 371 .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc1_supply),
368 .consumer_supplies = &pandora_vmmc1_supply, 372 .consumer_supplies = pandora_vmmc1_supply,
369}; 373};
370 374
371/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */ 375/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
@@ -379,38 +383,8 @@ static struct regulator_init_data pandora_vmmc2 = {
379 | REGULATOR_CHANGE_MODE 383 | REGULATOR_CHANGE_MODE
380 | REGULATOR_CHANGE_STATUS, 384 | REGULATOR_CHANGE_STATUS,
381 }, 385 },
382 .num_consumer_supplies = 1, 386 .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc2_supply),
383 .consumer_supplies = &pandora_vmmc2_supply, 387 .consumer_supplies = pandora_vmmc2_supply,
384};
385
386/* VDAC for DSS driving S-Video */
387static struct regulator_init_data pandora_vdac = {
388 .constraints = {
389 .min_uV = 1800000,
390 .max_uV = 1800000,
391 .apply_uV = true,
392 .valid_modes_mask = REGULATOR_MODE_NORMAL
393 | REGULATOR_MODE_STANDBY,
394 .valid_ops_mask = REGULATOR_CHANGE_MODE
395 | REGULATOR_CHANGE_STATUS,
396 },
397 .num_consumer_supplies = 1,
398 .consumer_supplies = &pandora_vdda_dac_supply,
399};
400
401/* VPLL2 for digital video outputs */
402static struct regulator_init_data pandora_vpll2 = {
403 .constraints = {
404 .min_uV = 1800000,
405 .max_uV = 1800000,
406 .apply_uV = true,
407 .valid_modes_mask = REGULATOR_MODE_NORMAL
408 | REGULATOR_MODE_STANDBY,
409 .valid_ops_mask = REGULATOR_CHANGE_MODE
410 | REGULATOR_CHANGE_STATUS,
411 },
412 .num_consumer_supplies = ARRAY_SIZE(pandora_vdds_supplies),
413 .consumer_supplies = pandora_vdds_supplies,
414}; 388};
415 389
416/* VAUX1 for LCD */ 390/* VAUX1 for LCD */
@@ -424,8 +398,8 @@ static struct regulator_init_data pandora_vaux1 = {
424 .valid_ops_mask = REGULATOR_CHANGE_MODE 398 .valid_ops_mask = REGULATOR_CHANGE_MODE
425 | REGULATOR_CHANGE_STATUS, 399 | REGULATOR_CHANGE_STATUS,
426 }, 400 },
427 .num_consumer_supplies = 1, 401 .num_consumer_supplies = ARRAY_SIZE(pandora_vcc_lcd_supply),
428 .consumer_supplies = &pandora_vcc_lcd_supply, 402 .consumer_supplies = pandora_vcc_lcd_supply,
429}; 403};
430 404
431/* VAUX2 for USB host PHY */ 405/* VAUX2 for USB host PHY */
@@ -439,8 +413,8 @@ static struct regulator_init_data pandora_vaux2 = {
439 .valid_ops_mask = REGULATOR_CHANGE_MODE 413 .valid_ops_mask = REGULATOR_CHANGE_MODE
440 | REGULATOR_CHANGE_STATUS, 414 | REGULATOR_CHANGE_STATUS,
441 }, 415 },
442 .num_consumer_supplies = 1, 416 .num_consumer_supplies = ARRAY_SIZE(pandora_usb_phy_supply),
443 .consumer_supplies = &pandora_usb_phy_supply, 417 .consumer_supplies = pandora_usb_phy_supply,
444}; 418};
445 419
446/* VAUX4 for ads7846 and nubs */ 420/* VAUX4 for ads7846 and nubs */
@@ -469,8 +443,8 @@ static struct regulator_init_data pandora_vsim = {
469 .valid_ops_mask = REGULATOR_CHANGE_MODE 443 .valid_ops_mask = REGULATOR_CHANGE_MODE
470 | REGULATOR_CHANGE_STATUS, 444 | REGULATOR_CHANGE_STATUS,
471 }, 445 },
472 .num_consumer_supplies = 1, 446 .num_consumer_supplies = ARRAY_SIZE(pandora_adac_supply),
473 .consumer_supplies = &pandora_adac_supply, 447 .consumer_supplies = pandora_adac_supply,
474}; 448};
475 449
476/* Fixed regulator internal to Wifi module */ 450/* Fixed regulator internal to Wifi module */
@@ -478,8 +452,8 @@ static struct regulator_init_data pandora_vmmc3 = {
478 .constraints = { 452 .constraints = {
479 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 453 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
480 }, 454 },
481 .num_consumer_supplies = 1, 455 .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply),
482 .consumer_supplies = &pandora_vmmc3_supply, 456 .consumer_supplies = pandora_vmmc3_supply,
483}; 457};
484 458
485static struct fixed_voltage_config pandora_vwlan = { 459static struct fixed_voltage_config pandora_vwlan = {
@@ -500,29 +474,12 @@ static struct platform_device pandora_vwlan_device = {
500 }, 474 },
501}; 475};
502 476
503static struct twl4030_usb_data omap3pandora_usb_data = {
504 .usb_mode = T2_USB_MODE_ULPI,
505};
506
507static struct twl4030_codec_audio_data omap3pandora_audio_data;
508
509static struct twl4030_codec_data omap3pandora_codec_data = {
510 .audio_mclk = 26000000,
511 .audio = &omap3pandora_audio_data,
512};
513
514static struct twl4030_bci_platform_data pandora_bci_data; 477static struct twl4030_bci_platform_data pandora_bci_data;
515 478
516static struct twl4030_platform_data omap3pandora_twldata = { 479static struct twl4030_platform_data omap3pandora_twldata = {
517 .irq_base = TWL4030_IRQ_BASE,
518 .irq_end = TWL4030_IRQ_END,
519 .gpio = &omap3pandora_gpio_data, 480 .gpio = &omap3pandora_gpio_data,
520 .usb = &omap3pandora_usb_data,
521 .codec = &omap3pandora_codec_data,
522 .vmmc1 = &pandora_vmmc1, 481 .vmmc1 = &pandora_vmmc1,
523 .vmmc2 = &pandora_vmmc2, 482 .vmmc2 = &pandora_vmmc2,
524 .vdac = &pandora_vdac,
525 .vpll2 = &pandora_vpll2,
526 .vaux1 = &pandora_vaux1, 483 .vaux1 = &pandora_vaux1,
527 .vaux2 = &pandora_vaux2, 484 .vaux2 = &pandora_vaux2,
528 .vaux4 = &pandora_vaux4, 485 .vaux4 = &pandora_vaux4,
@@ -540,6 +497,17 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
540 497
541static int __init omap3pandora_i2c_init(void) 498static int __init omap3pandora_i2c_init(void)
542{ 499{
500 omap3_pmic_get_config(&omap3pandora_twldata,
501 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
502 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
503
504 omap3pandora_twldata.vdac->constraints.apply_uV = true;
505
506 omap3pandora_twldata.vpll2->constraints.apply_uV = true;
507 omap3pandora_twldata.vpll2->num_consumer_supplies =
508 ARRAY_SIZE(pandora_vdds_supplies);
509 omap3pandora_twldata.vpll2->consumer_supplies = pandora_vdds_supplies;
510
543 omap3_pmic_init("tps65950", &omap3pandora_twldata); 511 omap3_pmic_init("tps65950", &omap3pandora_twldata);
544 /* i2c2 pins are not connected */ 512 /* i2c2 pins are not connected */
545 omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo, 513 omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
@@ -642,7 +610,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
642 .reserve = omap_reserve, 610 .reserve = omap_reserve,
643 .map_io = omap3_map_io, 611 .map_io = omap3_map_io,
644 .init_early = omap3pandora_init_early, 612 .init_early = omap3pandora_init_early,
645 .init_irq = omap_init_irq, 613 .init_irq = omap3_init_irq,
646 .init_machine = omap3pandora_init, 614 .init_machine = omap3pandora_init,
647 .timer = &omap_timer, 615 .timer = &omap3_timer,
648MACHINE_END 616MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 0c108a212ea2..8e104980ea26 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -52,7 +52,6 @@
52#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
53#include "mux.h" 53#include "mux.h"
54#include "hsmmc.h" 54#include "hsmmc.h"
55#include "timer-gp.h"
56#include "common-board-devices.h" 55#include "common-board-devices.h"
57 56
58#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) 57#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@@ -206,12 +205,12 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
206 .default_device = &omap3_stalker_dvi_device, 205 .default_device = &omap3_stalker_dvi_device,
207}; 206};
208 207
209static struct regulator_consumer_supply omap3stalker_vmmc1_supply = { 208static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = {
210 .supply = "vmmc", 209 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
211}; 210};
212 211
213static struct regulator_consumer_supply omap3stalker_vsim_supply = { 212static struct regulator_consumer_supply omap3stalker_vsim_supply[] = {
214 .supply = "vmmc_aux", 213 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
215}; 214};
216 215
217/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 216/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -224,8 +223,8 @@ static struct regulator_init_data omap3stalker_vmmc1 = {
224 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE 223 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
225 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, 224 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
226 }, 225 },
227 .num_consumer_supplies = 1, 226 .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vmmc1_supply),
228 .consumer_supplies = &omap3stalker_vmmc1_supply, 227 .consumer_supplies = omap3stalker_vmmc1_supply,
229}; 228};
230 229
231/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 230/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -238,8 +237,8 @@ static struct regulator_init_data omap3stalker_vsim = {
238 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE 237 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
239 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, 238 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
240 }, 239 },
241 .num_consumer_supplies = 1, 240 .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vsim_supply),
242 .consumer_supplies = &omap3stalker_vsim_supply, 241 .consumer_supplies = omap3stalker_vsim_supply,
243}; 242};
244 243
245static struct omap2_hsmmc_info mmc[] = { 244static struct omap2_hsmmc_info mmc[] = {
@@ -321,10 +320,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
321 mmc[0].gpio_cd = gpio + 0; 320 mmc[0].gpio_cd = gpio + 0;
322 omap2_hsmmc_init(mmc); 321 omap2_hsmmc_init(mmc);
323 322
324 /* link regulators to MMC adapters */
325 omap3stalker_vmmc1_supply.dev = mmc[0].dev;
326 omap3stalker_vsim_supply.dev = mmc[0].dev;
327
328 /* 323 /*
329 * Most GPIOs are for USB OTG. Some are mostly sent to 324 * Most GPIOs are for USB OTG. Some are mostly sent to
330 * the P2 connector; notably LEDA for the LCD backlight. 325 * the P2 connector; notably LEDA for the LCD backlight.
@@ -354,10 +349,6 @@ static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
354 .setup = omap3stalker_twl_gpio_setup, 349 .setup = omap3stalker_twl_gpio_setup,
355}; 350};
356 351
357static struct twl4030_usb_data omap3stalker_usb_data = {
358 .usb_mode = T2_USB_MODE_ULPI,
359};
360
361static uint32_t board_keymap[] = { 352static uint32_t board_keymap[] = {
362 KEY(0, 0, KEY_LEFT), 353 KEY(0, 0, KEY_LEFT),
363 KEY(0, 1, KEY_DOWN), 354 KEY(0, 1, KEY_DOWN),
@@ -392,68 +383,10 @@ static struct twl4030_keypad_data omap3stalker_kp_data = {
392 .rep = 1, 383 .rep = 1,
393}; 384};
394 385
395static struct twl4030_madc_platform_data omap3stalker_madc_data = {
396 .irq_line = 1,
397};
398
399static struct twl4030_codec_audio_data omap3stalker_audio_data;
400
401static struct twl4030_codec_data omap3stalker_codec_data = {
402 .audio_mclk = 26000000,
403 .audio = &omap3stalker_audio_data,
404};
405
406static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
407 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
408
409/* VDAC for DSS driving S-Video */
410static struct regulator_init_data omap3_stalker_vdac = {
411 .constraints = {
412 .min_uV = 1800000,
413 .max_uV = 1800000,
414 .apply_uV = true,
415 .valid_modes_mask = REGULATOR_MODE_NORMAL
416 | REGULATOR_MODE_STANDBY,
417 .valid_ops_mask = REGULATOR_CHANGE_MODE
418 | REGULATOR_CHANGE_STATUS,
419 },
420 .num_consumer_supplies = 1,
421 .consumer_supplies = &omap3_stalker_vdda_dac_supply,
422};
423
424/* VPLL2 for digital video outputs */
425static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = {
426 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
427 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
428};
429
430static struct regulator_init_data omap3_stalker_vpll2 = {
431 .constraints = {
432 .name = "VDVI",
433 .min_uV = 1800000,
434 .max_uV = 1800000,
435 .apply_uV = true,
436 .valid_modes_mask = REGULATOR_MODE_NORMAL
437 | REGULATOR_MODE_STANDBY,
438 .valid_ops_mask = REGULATOR_CHANGE_MODE
439 | REGULATOR_CHANGE_STATUS,
440 },
441 .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies),
442 .consumer_supplies = omap3_stalker_vpll2_supplies,
443};
444
445static struct twl4030_platform_data omap3stalker_twldata = { 386static struct twl4030_platform_data omap3stalker_twldata = {
446 .irq_base = TWL4030_IRQ_BASE,
447 .irq_end = TWL4030_IRQ_END,
448
449 /* platform_data for children goes here */ 387 /* platform_data for children goes here */
450 .keypad = &omap3stalker_kp_data, 388 .keypad = &omap3stalker_kp_data,
451 .madc = &omap3stalker_madc_data,
452 .usb = &omap3stalker_usb_data,
453 .gpio = &omap3stalker_gpio_data, 389 .gpio = &omap3stalker_gpio_data,
454 .codec = &omap3stalker_codec_data,
455 .vdac = &omap3_stalker_vdac,
456 .vpll2 = &omap3_stalker_vpll2,
457 .vmmc1 = &omap3stalker_vmmc1, 390 .vmmc1 = &omap3stalker_vmmc1,
458 .vsim = &omap3stalker_vsim, 391 .vsim = &omap3stalker_vsim,
459}; 392};
@@ -474,6 +407,15 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
474 407
475static int __init omap3_stalker_i2c_init(void) 408static int __init omap3_stalker_i2c_init(void)
476{ 409{
410 omap3_pmic_get_config(&omap3stalker_twldata,
411 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
412 TWL_COMMON_PDATA_AUDIO,
413 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
414
415 omap3stalker_twldata.vdac->constraints.apply_uV = true;
416 omap3stalker_twldata.vpll2->constraints.apply_uV = true;
417 omap3stalker_twldata.vpll2->constraints.name = "VDVI";
418
477 omap3_pmic_init("twl4030", &omap3stalker_twldata); 419 omap3_pmic_init("twl4030", &omap3stalker_twldata);
478 omap_register_i2c_bus(2, 400, NULL, 0); 420 omap_register_i2c_bus(2, 400, NULL, 0);
479 omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3, 421 omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
@@ -494,10 +436,7 @@ static void __init omap3_stalker_init_early(void)
494 436
495static void __init omap3_stalker_init_irq(void) 437static void __init omap3_stalker_init_irq(void)
496{ 438{
497 omap_init_irq(); 439 omap3_init_irq();
498#ifdef CONFIG_OMAP_32K_TIMER
499 omap2_gp_clockevent_set_gptimer(12);
500#endif
501} 440}
502 441
503static struct platform_device *omap3_stalker_devices[] __initdata = { 442static struct platform_device *omap3_stalker_devices[] __initdata = {
@@ -560,5 +499,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
560 .init_early = omap3_stalker_init_early, 499 .init_early = omap3_stalker_init_early,
561 .init_irq = omap3_stalker_init_irq, 500 .init_irq = omap3_stalker_init_irq,
562 .init_machine = omap3_stalker_init, 501 .init_machine = omap3_stalker_init,
563 .timer = &omap_timer, 502 .timer = &omap3_secure_timer,
564MACHINE_END 503MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 5f649faf7377..852ea0464057 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -51,7 +51,6 @@
51 51
52#include "mux.h" 52#include "mux.h"
53#include "hsmmc.h" 53#include "hsmmc.h"
54#include "timer-gp.h"
55#include "common-board-devices.h" 54#include "common-board-devices.h"
56 55
57#include <asm/setup.h> 56#include <asm/setup.h>
@@ -114,12 +113,12 @@ static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
114 .ctrl_name = "internal", 113 .ctrl_name = "internal",
115}; 114};
116 115
117static struct regulator_consumer_supply touchbook_vmmc1_supply = { 116static struct regulator_consumer_supply touchbook_vmmc1_supply[] = {
118 .supply = "vmmc", 117 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
119}; 118};
120 119
121static struct regulator_consumer_supply touchbook_vsim_supply = { 120static struct regulator_consumer_supply touchbook_vsim_supply[] = {
122 .supply = "vmmc_aux", 121 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
123}; 122};
124 123
125static struct gpio_led gpio_leds[]; 124static struct gpio_led gpio_leds[];
@@ -137,10 +136,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
137 mmc[0].gpio_cd = gpio + 0; 136 mmc[0].gpio_cd = gpio + 0;
138 omap2_hsmmc_init(mmc); 137 omap2_hsmmc_init(mmc);
139 138
140 /* link regulators to MMC adapters */
141 touchbook_vmmc1_supply.dev = mmc[0].dev;
142 touchbook_vsim_supply.dev = mmc[0].dev;
143
144 /* REVISIT: need ehci-omap hooks for external VBUS 139 /* REVISIT: need ehci-omap hooks for external VBUS
145 * power switch and overcurrent detect 140 * power switch and overcurrent detect
146 */ 141 */
@@ -167,14 +162,18 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = {
167 .setup = touchbook_twl_gpio_setup, 162 .setup = touchbook_twl_gpio_setup,
168}; 163};
169 164
170static struct regulator_consumer_supply touchbook_vdac_supply = { 165static struct regulator_consumer_supply touchbook_vdac_supply[] = {
166{
171 .supply = "vdac", 167 .supply = "vdac",
172 .dev = &omap3_touchbook_lcd_device.dev, 168 .dev = &omap3_touchbook_lcd_device.dev,
169},
173}; 170};
174 171
175static struct regulator_consumer_supply touchbook_vdvi_supply = { 172static struct regulator_consumer_supply touchbook_vdvi_supply[] = {
173{
176 .supply = "vdvi", 174 .supply = "vdvi",
177 .dev = &omap3_touchbook_lcd_device.dev, 175 .dev = &omap3_touchbook_lcd_device.dev,
176},
178}; 177};
179 178
180/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 179/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -188,8 +187,8 @@ static struct regulator_init_data touchbook_vmmc1 = {
188 | REGULATOR_CHANGE_MODE 187 | REGULATOR_CHANGE_MODE
189 | REGULATOR_CHANGE_STATUS, 188 | REGULATOR_CHANGE_STATUS,
190 }, 189 },
191 .num_consumer_supplies = 1, 190 .num_consumer_supplies = ARRAY_SIZE(touchbook_vmmc1_supply),
192 .consumer_supplies = &touchbook_vmmc1_supply, 191 .consumer_supplies = touchbook_vmmc1_supply,
193}; 192};
194 193
195/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ 194/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -203,62 +202,15 @@ static struct regulator_init_data touchbook_vsim = {
203 | REGULATOR_CHANGE_MODE 202 | REGULATOR_CHANGE_MODE
204 | REGULATOR_CHANGE_STATUS, 203 | REGULATOR_CHANGE_STATUS,
205 }, 204 },
206 .num_consumer_supplies = 1, 205 .num_consumer_supplies = ARRAY_SIZE(touchbook_vsim_supply),
207 .consumer_supplies = &touchbook_vsim_supply, 206 .consumer_supplies = touchbook_vsim_supply,
208};
209
210/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
211static struct regulator_init_data touchbook_vdac = {
212 .constraints = {
213 .min_uV = 1800000,
214 .max_uV = 1800000,
215 .valid_modes_mask = REGULATOR_MODE_NORMAL
216 | REGULATOR_MODE_STANDBY,
217 .valid_ops_mask = REGULATOR_CHANGE_MODE
218 | REGULATOR_CHANGE_STATUS,
219 },
220 .num_consumer_supplies = 1,
221 .consumer_supplies = &touchbook_vdac_supply,
222};
223
224/* VPLL2 for digital video outputs */
225static struct regulator_init_data touchbook_vpll2 = {
226 .constraints = {
227 .name = "VDVI",
228 .min_uV = 1800000,
229 .max_uV = 1800000,
230 .valid_modes_mask = REGULATOR_MODE_NORMAL
231 | REGULATOR_MODE_STANDBY,
232 .valid_ops_mask = REGULATOR_CHANGE_MODE
233 | REGULATOR_CHANGE_STATUS,
234 },
235 .num_consumer_supplies = 1,
236 .consumer_supplies = &touchbook_vdvi_supply,
237};
238
239static struct twl4030_usb_data touchbook_usb_data = {
240 .usb_mode = T2_USB_MODE_ULPI,
241};
242
243static struct twl4030_codec_audio_data touchbook_audio_data;
244
245static struct twl4030_codec_data touchbook_codec_data = {
246 .audio_mclk = 26000000,
247 .audio = &touchbook_audio_data,
248}; 207};
249 208
250static struct twl4030_platform_data touchbook_twldata = { 209static struct twl4030_platform_data touchbook_twldata = {
251 .irq_base = TWL4030_IRQ_BASE,
252 .irq_end = TWL4030_IRQ_END,
253
254 /* platform_data for children goes here */ 210 /* platform_data for children goes here */
255 .usb = &touchbook_usb_data,
256 .gpio = &touchbook_gpio_data, 211 .gpio = &touchbook_gpio_data,
257 .codec = &touchbook_codec_data,
258 .vmmc1 = &touchbook_vmmc1, 212 .vmmc1 = &touchbook_vmmc1,
259 .vsim = &touchbook_vsim, 213 .vsim = &touchbook_vsim,
260 .vdac = &touchbook_vdac,
261 .vpll2 = &touchbook_vpll2,
262}; 214};
263 215
264static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = { 216static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
@@ -270,8 +222,20 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
270static int __init omap3_touchbook_i2c_init(void) 222static int __init omap3_touchbook_i2c_init(void)
271{ 223{
272 /* Standard TouchBook bus */ 224 /* Standard TouchBook bus */
273 omap3_pmic_init("twl4030", &touchbook_twldata); 225 omap3_pmic_get_config(&touchbook_twldata,
226 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
227 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
228
229 touchbook_twldata.vdac->num_consumer_supplies =
230 ARRAY_SIZE(touchbook_vdac_supply);
231 touchbook_twldata.vdac->consumer_supplies = touchbook_vdac_supply;
274 232
233 touchbook_twldata.vpll2->constraints.name = "VDVI";
234 touchbook_twldata.vpll2->num_consumer_supplies =
235 ARRAY_SIZE(touchbook_vdvi_supply);
236 touchbook_twldata.vpll2->consumer_supplies = touchbook_vdvi_supply;
237
238 omap3_pmic_init("twl4030", &touchbook_twldata);
275 /* Additional TouchBook bus */ 239 /* Additional TouchBook bus */
276 omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo, 240 omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
277 ARRAY_SIZE(touchBook_i2c_boardinfo)); 241 ARRAY_SIZE(touchBook_i2c_boardinfo));
@@ -371,10 +335,7 @@ static void __init omap3_touchbook_init_early(void)
371 335
372static void __init omap3_touchbook_init_irq(void) 336static void __init omap3_touchbook_init_irq(void)
373{ 337{
374 omap_init_irq(); 338 omap3_init_irq();
375#ifdef CONFIG_OMAP_32K_TIMER
376 omap2_gp_clockevent_set_gptimer(12);
377#endif
378} 339}
379 340
380static struct platform_device *omap3_touchbook_devices[] __initdata = { 341static struct platform_device *omap3_touchbook_devices[] __initdata = {
@@ -449,5 +410,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
449 .init_early = omap3_touchbook_init_early, 410 .init_early = omap3_touchbook_init_early,
450 .init_irq = omap3_touchbook_init_irq, 411 .init_irq = omap3_touchbook_init_irq,
451 .init_machine = omap3_touchbook_init, 412 .init_machine = omap3_touchbook_init,
452 .timer = &omap_timer, 413 .timer = &omap3_secure_timer,
453MACHINE_END 414MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 0cfe2005cb50..9aaa96057666 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -41,7 +41,6 @@
41#include <plat/usb.h> 41#include <plat/usb.h>
42#include <plat/mmc.h> 42#include <plat/mmc.h>
43#include <video/omap-panel-generic-dpi.h> 43#include <video/omap-panel-generic-dpi.h>
44#include "timer-gp.h"
45 44
46#include "hsmmc.h" 45#include "hsmmc.h"
47#include "control.h" 46#include "control.h"
@@ -155,14 +154,6 @@ static struct omap_musb_board_data musb_board_data = {
155 .power = 100, 154 .power = 100,
156}; 155};
157 156
158static struct twl4030_usb_data omap4_usbphy_data = {
159 .phy_init = omap4430_phy_init,
160 .phy_exit = omap4430_phy_exit,
161 .phy_power = omap4430_phy_power,
162 .phy_set_clock = omap4430_phy_set_clk,
163 .phy_suspend = omap4430_phy_suspend,
164};
165
166static struct omap2_hsmmc_info mmc[] = { 157static struct omap2_hsmmc_info mmc[] = {
167 { 158 {
168 .mmc = 1, 159 .mmc = 1,
@@ -182,24 +173,16 @@ static struct omap2_hsmmc_info mmc[] = {
182 {} /* Terminator */ 173 {} /* Terminator */
183}; 174};
184 175
185static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { 176static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
186 { 177 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
187 .supply = "vmmc",
188 .dev_name = "omap_hsmmc.0",
189 },
190};
191
192static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
193 .supply = "vmmc",
194 .dev_name = "omap_hsmmc.4",
195}; 178};
196 179
197static struct regulator_init_data panda_vmmc5 = { 180static struct regulator_init_data panda_vmmc5 = {
198 .constraints = { 181 .constraints = {
199 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 182 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
200 }, 183 },
201 .num_consumer_supplies = 1, 184 .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
202 .consumer_supplies = &omap4_panda_vmmc5_supply, 185 .consumer_supplies = omap4_panda_vmmc5_supply,
203}; 186};
204 187
205static struct fixed_voltage_config panda_vwlan = { 188static struct fixed_voltage_config panda_vwlan = {
@@ -274,128 +257,8 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
274 return 0; 257 return 0;
275} 258}
276 259
277static struct regulator_init_data omap4_panda_vaux2 = { 260/* Panda board uses the common PMIC configuration */
278 .constraints = { 261static struct twl4030_platform_data omap4_panda_twldata;
279 .min_uV = 1200000,
280 .max_uV = 2800000,
281 .apply_uV = true,
282 .valid_modes_mask = REGULATOR_MODE_NORMAL
283 | REGULATOR_MODE_STANDBY,
284 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
285 | REGULATOR_CHANGE_MODE
286 | REGULATOR_CHANGE_STATUS,
287 },
288};
289
290static struct regulator_init_data omap4_panda_vaux3 = {
291 .constraints = {
292 .min_uV = 1000000,
293 .max_uV = 3000000,
294 .apply_uV = true,
295 .valid_modes_mask = REGULATOR_MODE_NORMAL
296 | REGULATOR_MODE_STANDBY,
297 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
298 | REGULATOR_CHANGE_MODE
299 | REGULATOR_CHANGE_STATUS,
300 },
301};
302
303/* VMMC1 for MMC1 card */
304static struct regulator_init_data omap4_panda_vmmc = {
305 .constraints = {
306 .min_uV = 1200000,
307 .max_uV = 3000000,
308 .apply_uV = true,
309 .valid_modes_mask = REGULATOR_MODE_NORMAL
310 | REGULATOR_MODE_STANDBY,
311 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
312 | REGULATOR_CHANGE_MODE
313 | REGULATOR_CHANGE_STATUS,
314 },
315 .num_consumer_supplies = 1,
316 .consumer_supplies = omap4_panda_vmmc_supply,
317};
318
319static struct regulator_init_data omap4_panda_vpp = {
320 .constraints = {
321 .min_uV = 1800000,
322 .max_uV = 2500000,
323 .apply_uV = true,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL
325 | REGULATOR_MODE_STANDBY,
326 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
327 | REGULATOR_CHANGE_MODE
328 | REGULATOR_CHANGE_STATUS,
329 },
330};
331
332static struct regulator_init_data omap4_panda_vana = {
333 .constraints = {
334 .min_uV = 2100000,
335 .max_uV = 2100000,
336 .valid_modes_mask = REGULATOR_MODE_NORMAL
337 | REGULATOR_MODE_STANDBY,
338 .valid_ops_mask = REGULATOR_CHANGE_MODE
339 | REGULATOR_CHANGE_STATUS,
340 },
341};
342
343static struct regulator_init_data omap4_panda_vcxio = {
344 .constraints = {
345 .min_uV = 1800000,
346 .max_uV = 1800000,
347 .valid_modes_mask = REGULATOR_MODE_NORMAL
348 | REGULATOR_MODE_STANDBY,
349 .valid_ops_mask = REGULATOR_CHANGE_MODE
350 | REGULATOR_CHANGE_STATUS,
351 },
352};
353
354static struct regulator_init_data omap4_panda_vdac = {
355 .constraints = {
356 .min_uV = 1800000,
357 .max_uV = 1800000,
358 .valid_modes_mask = REGULATOR_MODE_NORMAL
359 | REGULATOR_MODE_STANDBY,
360 .valid_ops_mask = REGULATOR_CHANGE_MODE
361 | REGULATOR_CHANGE_STATUS,
362 },
363};
364
365static struct regulator_init_data omap4_panda_vusb = {
366 .constraints = {
367 .min_uV = 3300000,
368 .max_uV = 3300000,
369 .apply_uV = true,
370 .valid_modes_mask = REGULATOR_MODE_NORMAL
371 | REGULATOR_MODE_STANDBY,
372 .valid_ops_mask = REGULATOR_CHANGE_MODE
373 | REGULATOR_CHANGE_STATUS,
374 },
375};
376
377static struct regulator_init_data omap4_panda_clk32kg = {
378 .constraints = {
379 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
380 },
381};
382
383static struct twl4030_platform_data omap4_panda_twldata = {
384 .irq_base = TWL6030_IRQ_BASE,
385 .irq_end = TWL6030_IRQ_END,
386
387 /* Regulators */
388 .vmmc = &omap4_panda_vmmc,
389 .vpp = &omap4_panda_vpp,
390 .vana = &omap4_panda_vana,
391 .vcxio = &omap4_panda_vcxio,
392 .vdac = &omap4_panda_vdac,
393 .vusb = &omap4_panda_vusb,
394 .vaux2 = &omap4_panda_vaux2,
395 .vaux3 = &omap4_panda_vaux3,
396 .clk32kg = &omap4_panda_clk32kg,
397 .usb = &omap4_usbphy_data,
398};
399 262
400/* 263/*
401 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM 264 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -409,6 +272,16 @@ static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
409 272
410static int __init omap4_panda_i2c_init(void) 273static int __init omap4_panda_i2c_init(void)
411{ 274{
275 omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
276 TWL_COMMON_REGULATOR_VDAC |
277 TWL_COMMON_REGULATOR_VAUX2 |
278 TWL_COMMON_REGULATOR_VAUX3 |
279 TWL_COMMON_REGULATOR_VMMC |
280 TWL_COMMON_REGULATOR_VPP |
281 TWL_COMMON_REGULATOR_VANA |
282 TWL_COMMON_REGULATOR_VCXIO |
283 TWL_COMMON_REGULATOR_VUSB |
284 TWL_COMMON_REGULATOR_CLK32KG);
412 omap4_pmic_init("twl6030", &omap4_panda_twldata); 285 omap4_pmic_init("twl6030", &omap4_panda_twldata);
413 omap_register_i2c_bus(2, 400, NULL, 0); 286 omap_register_i2c_bus(2, 400, NULL, 0);
414 /* 287 /*
@@ -716,5 +589,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
716 .init_early = omap4_panda_init_early, 589 .init_early = omap4_panda_init_early,
717 .init_irq = gic_init_irq, 590 .init_irq = gic_init_irq,
718 .init_machine = omap4_panda_init, 591 .init_machine = omap4_panda_init,
719 .timer = &omap_timer, 592 .timer = &omap4_timer,
720MACHINE_END 593MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 175e1ab2b04d..f1f18d03d24c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -74,15 +74,16 @@
74 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 74 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
75 75
76/* fixed regulator for ads7846 */ 76/* fixed regulator for ads7846 */
77static struct regulator_consumer_supply ads7846_supply = 77static struct regulator_consumer_supply ads7846_supply[] = {
78 REGULATOR_SUPPLY("vcc", "spi1.0"); 78 REGULATOR_SUPPLY("vcc", "spi1.0"),
79};
79 80
80static struct regulator_init_data vads7846_regulator = { 81static struct regulator_init_data vads7846_regulator = {
81 .constraints = { 82 .constraints = {
82 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 83 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
83 }, 84 },
84 .num_consumer_supplies = 1, 85 .num_consumer_supplies = ARRAY_SIZE(ads7846_supply),
85 .consumer_supplies = &ads7846_supply, 86 .consumer_supplies = ads7846_supply,
86}; 87};
87 88
88static struct fixed_voltage_config vads7846 = { 89static struct fixed_voltage_config vads7846 = {
@@ -264,14 +265,6 @@ static struct omap_dss_board_info overo_dss_data = {
264 .default_device = &overo_dvi_device, 265 .default_device = &overo_dvi_device,
265}; 266};
266 267
267static struct regulator_consumer_supply overo_vdda_dac_supply =
268 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
269
270static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
271 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
272 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
273};
274
275static struct mtd_partition overo_nand_partitions[] = { 268static struct mtd_partition overo_nand_partitions[] = {
276 { 269 {
277 .name = "xloader", 270 .name = "xloader",
@@ -319,8 +312,8 @@ static struct omap2_hsmmc_info mmc[] = {
319 {} /* Terminator */ 312 {} /* Terminator */
320}; 313};
321 314
322static struct regulator_consumer_supply overo_vmmc1_supply = { 315static struct regulator_consumer_supply overo_vmmc1_supply[] = {
323 .supply = "vmmc", 316 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
324}; 317};
325 318
326#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 319#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
@@ -415,8 +408,6 @@ static int overo_twl_gpio_setup(struct device *dev,
415{ 408{
416 omap2_hsmmc_init(mmc); 409 omap2_hsmmc_init(mmc);
417 410
418 overo_vmmc1_supply.dev = mmc[0].dev;
419
420#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 411#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
421 /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ 412 /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
422 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; 413 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -433,10 +424,6 @@ static struct twl4030_gpio_platform_data overo_gpio_data = {
433 .setup = overo_twl_gpio_setup, 424 .setup = overo_twl_gpio_setup,
434}; 425};
435 426
436static struct twl4030_usb_data overo_usb_data = {
437 .usb_mode = T2_USB_MODE_ULPI,
438};
439
440static struct regulator_init_data overo_vmmc1 = { 427static struct regulator_init_data overo_vmmc1 = {
441 .constraints = { 428 .constraints = {
442 .min_uV = 1850000, 429 .min_uV = 1850000,
@@ -447,59 +434,23 @@ static struct regulator_init_data overo_vmmc1 = {
447 | REGULATOR_CHANGE_MODE 434 | REGULATOR_CHANGE_MODE
448 | REGULATOR_CHANGE_STATUS, 435 | REGULATOR_CHANGE_STATUS,
449 }, 436 },
450 .num_consumer_supplies = 1, 437 .num_consumer_supplies = ARRAY_SIZE(overo_vmmc1_supply),
451 .consumer_supplies = &overo_vmmc1_supply, 438 .consumer_supplies = overo_vmmc1_supply,
452};
453
454/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
455static struct regulator_init_data overo_vdac = {
456 .constraints = {
457 .min_uV = 1800000,
458 .max_uV = 1800000,
459 .valid_modes_mask = REGULATOR_MODE_NORMAL
460 | REGULATOR_MODE_STANDBY,
461 .valid_ops_mask = REGULATOR_CHANGE_MODE
462 | REGULATOR_CHANGE_STATUS,
463 },
464 .num_consumer_supplies = 1,
465 .consumer_supplies = &overo_vdda_dac_supply,
466};
467
468/* VPLL2 for digital video outputs */
469static struct regulator_init_data overo_vpll2 = {
470 .constraints = {
471 .name = "VDVI",
472 .min_uV = 1800000,
473 .max_uV = 1800000,
474 .valid_modes_mask = REGULATOR_MODE_NORMAL
475 | REGULATOR_MODE_STANDBY,
476 .valid_ops_mask = REGULATOR_CHANGE_MODE
477 | REGULATOR_CHANGE_STATUS,
478 },
479 .num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply),
480 .consumer_supplies = overo_vdds_dsi_supply,
481};
482
483static struct twl4030_codec_audio_data overo_audio_data;
484
485static struct twl4030_codec_data overo_codec_data = {
486 .audio_mclk = 26000000,
487 .audio = &overo_audio_data,
488}; 439};
489 440
490static struct twl4030_platform_data overo_twldata = { 441static struct twl4030_platform_data overo_twldata = {
491 .irq_base = TWL4030_IRQ_BASE,
492 .irq_end = TWL4030_IRQ_END,
493 .gpio = &overo_gpio_data, 442 .gpio = &overo_gpio_data,
494 .usb = &overo_usb_data,
495 .codec = &overo_codec_data,
496 .vmmc1 = &overo_vmmc1, 443 .vmmc1 = &overo_vmmc1,
497 .vdac = &overo_vdac,
498 .vpll2 = &overo_vpll2,
499}; 444};
500 445
501static int __init overo_i2c_init(void) 446static int __init overo_i2c_init(void)
502{ 447{
448 omap3_pmic_get_config(&overo_twldata,
449 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
450 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
451
452 overo_twldata.vpll2->constraints.name = "VDVI";
453
503 omap3_pmic_init("tps65950", &overo_twldata); 454 omap3_pmic_init("tps65950", &overo_twldata);
504 /* i2c2 pins are used for gpio */ 455 /* i2c2 pins are used for gpio */
505 omap_register_i2c_bus(3, 400, NULL, 0); 456 omap_register_i2c_bus(3, 400, NULL, 0);
@@ -615,7 +566,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
615 .reserve = omap_reserve, 566 .reserve = omap_reserve,
616 .map_io = omap3_map_io, 567 .map_io = omap3_map_io,
617 .init_early = overo_init_early, 568 .init_early = overo_init_early,
618 .init_irq = omap_init_irq, 569 .init_irq = omap3_init_irq,
619 .init_machine = overo_init, 570 .init_machine = overo_init,
620 .timer = &omap_timer, 571 .timer = &omap3_timer,
621MACHINE_END 572MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 42d10b12da3c..7dfed24ee12e 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -79,20 +79,14 @@ static struct twl4030_gpio_platform_data rm680_gpio_data = {
79 .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), 79 .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15),
80}; 80};
81 81
82static struct twl4030_usb_data rm680_usb_data = {
83 .usb_mode = T2_USB_MODE_ULPI,
84};
85
86static struct twl4030_platform_data rm680_twl_data = { 82static struct twl4030_platform_data rm680_twl_data = {
87 .irq_base = TWL4030_IRQ_BASE,
88 .irq_end = TWL4030_IRQ_END,
89 .gpio = &rm680_gpio_data, 83 .gpio = &rm680_gpio_data,
90 .usb = &rm680_usb_data,
91 /* add rest of the children here */ 84 /* add rest of the children here */
92}; 85};
93 86
94static void __init rm680_i2c_init(void) 87static void __init rm680_i2c_init(void)
95{ 88{
89 omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
96 omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data); 90 omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
97 omap_register_i2c_bus(2, 400, NULL, 0); 91 omap_register_i2c_bus(2, 400, NULL, 0);
98 omap_register_i2c_bus(3, 400, NULL, 0); 92 omap_register_i2c_bus(3, 400, NULL, 0);
@@ -163,7 +157,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
163 .reserve = omap_reserve, 157 .reserve = omap_reserve,
164 .map_io = rm680_map_io, 158 .map_io = rm680_map_io,
165 .init_early = rm680_init_early, 159 .init_early = rm680_init_early,
166 .init_irq = omap_init_irq, 160 .init_irq = omap3_init_irq,
167 .init_machine = rm680_init, 161 .init_machine = rm680_init,
168 .timer = &omap_timer, 162 .timer = &omap3_timer,
169MACHINE_END 163MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 990366726c58..6140290721a0 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -288,10 +288,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
288 .rep = 1, 288 .rep = 1,
289}; 289};
290 290
291static struct twl4030_madc_platform_data rx51_madc_data = {
292 .irq_line = 1,
293};
294
295/* Enable input logic and pull all lines up when eMMC is on. */ 291/* Enable input logic and pull all lines up when eMMC is on. */
296static struct omap_board_mux rx51_mmc2_on_mux[] = { 292static struct omap_board_mux rx51_mmc2_on_mux[] = {
297 OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), 293 OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
@@ -358,14 +354,17 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
358 {} /* Terminator */ 354 {} /* Terminator */
359}; 355};
360 356
361static struct regulator_consumer_supply rx51_vmmc1_supply = 357static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
362 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); 358 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
359};
363 360
364static struct regulator_consumer_supply rx51_vaux3_supply = 361static struct regulator_consumer_supply rx51_vaux3_supply[] = {
365 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); 362 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
363};
366 364
367static struct regulator_consumer_supply rx51_vsim_supply = 365static struct regulator_consumer_supply rx51_vsim_supply[] = {
368 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); 366 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
367};
369 368
370static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { 369static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
371 /* tlv320aic3x analog supplies */ 370 /* tlv320aic3x analog supplies */
@@ -395,10 +394,6 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
395 REGULATOR_SUPPLY("vdd", "2-0063"), 394 REGULATOR_SUPPLY("vdd", "2-0063"),
396}; 395};
397 396
398static struct regulator_consumer_supply rx51_vdac_supply[] = {
399 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
400};
401
402static struct regulator_init_data rx51_vaux1 = { 397static struct regulator_init_data rx51_vaux1 = {
403 .constraints = { 398 .constraints = {
404 .name = "V28", 399 .name = "V28",
@@ -452,8 +447,8 @@ static struct regulator_init_data rx51_vaux3_mmc = {
452 | REGULATOR_CHANGE_MODE 447 | REGULATOR_CHANGE_MODE
453 | REGULATOR_CHANGE_STATUS, 448 | REGULATOR_CHANGE_STATUS,
454 }, 449 },
455 .num_consumer_supplies = 1, 450 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
456 .consumer_supplies = &rx51_vaux3_supply, 451 .consumer_supplies = rx51_vaux3_supply,
457}; 452};
458 453
459static struct regulator_init_data rx51_vaux4 = { 454static struct regulator_init_data rx51_vaux4 = {
@@ -479,8 +474,8 @@ static struct regulator_init_data rx51_vmmc1 = {
479 | REGULATOR_CHANGE_MODE 474 | REGULATOR_CHANGE_MODE
480 | REGULATOR_CHANGE_STATUS, 475 | REGULATOR_CHANGE_STATUS,
481 }, 476 },
482 .num_consumer_supplies = 1, 477 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
483 .consumer_supplies = &rx51_vmmc1_supply, 478 .consumer_supplies = rx51_vmmc1_supply,
484}; 479};
485 480
486static struct regulator_init_data rx51_vmmc2 = { 481static struct regulator_init_data rx51_vmmc2 = {
@@ -511,23 +506,8 @@ static struct regulator_init_data rx51_vsim = {
511 .valid_ops_mask = REGULATOR_CHANGE_MODE 506 .valid_ops_mask = REGULATOR_CHANGE_MODE
512 | REGULATOR_CHANGE_STATUS, 507 | REGULATOR_CHANGE_STATUS,
513 }, 508 },
514 .num_consumer_supplies = 1, 509 .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
515 .consumer_supplies = &rx51_vsim_supply, 510 .consumer_supplies = rx51_vsim_supply,
516};
517
518static struct regulator_init_data rx51_vdac = {
519 .constraints = {
520 .name = "VDAC",
521 .min_uV = 1800000,
522 .max_uV = 1800000,
523 .apply_uV = true,
524 .valid_modes_mask = REGULATOR_MODE_NORMAL
525 | REGULATOR_MODE_STANDBY,
526 .valid_ops_mask = REGULATOR_CHANGE_MODE
527 | REGULATOR_CHANGE_STATUS,
528 },
529 .num_consumer_supplies = 1,
530 .consumer_supplies = rx51_vdac_supply,
531}; 511};
532 512
533static struct regulator_init_data rx51_vio = { 513static struct regulator_init_data rx51_vio = {
@@ -600,10 +580,6 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
600 .setup = rx51_twlgpio_setup, 580 .setup = rx51_twlgpio_setup,
601}; 581};
602 582
603static struct twl4030_usb_data rx51_usb_data = {
604 .usb_mode = T2_USB_MODE_ULPI,
605};
606
607static struct twl4030_ins sleep_on_seq[] __initdata = { 583static struct twl4030_ins sleep_on_seq[] __initdata = {
608/* 584/*
609 * Turn off everything 585 * Turn off everything
@@ -775,14 +751,9 @@ struct twl4030_codec_data rx51_codec_data __initdata = {
775}; 751};
776 752
777static struct twl4030_platform_data rx51_twldata __initdata = { 753static struct twl4030_platform_data rx51_twldata __initdata = {
778 .irq_base = TWL4030_IRQ_BASE,
779 .irq_end = TWL4030_IRQ_END,
780
781 /* platform_data for children goes here */ 754 /* platform_data for children goes here */
782 .gpio = &rx51_gpio_data, 755 .gpio = &rx51_gpio_data,
783 .keypad = &rx51_kp_data, 756 .keypad = &rx51_kp_data,
784 .madc = &rx51_madc_data,
785 .usb = &rx51_usb_data,
786 .power = &rx51_t2scripts_data, 757 .power = &rx51_t2scripts_data,
787 .codec = &rx51_codec_data, 758 .codec = &rx51_codec_data,
788 759
@@ -791,7 +762,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
791 .vaux4 = &rx51_vaux4, 762 .vaux4 = &rx51_vaux4,
792 .vmmc1 = &rx51_vmmc1, 763 .vmmc1 = &rx51_vmmc1,
793 .vsim = &rx51_vsim, 764 .vsim = &rx51_vsim,
794 .vdac = &rx51_vdac,
795 .vio = &rx51_vio, 765 .vio = &rx51_vio,
796}; 766};
797 767
@@ -847,6 +817,13 @@ static int __init rx51_i2c_init(void)
847 rx51_twldata.vaux3 = &rx51_vaux3_cam; 817 rx51_twldata.vaux3 = &rx51_vaux3_cam;
848 } 818 }
849 rx51_twldata.vmmc2 = &rx51_vmmc2; 819 rx51_twldata.vmmc2 = &rx51_vmmc2;
820 omap3_pmic_get_config(&rx51_twldata,
821 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
822 TWL_COMMON_REGULATOR_VDAC);
823
824 rx51_twldata.vdac->constraints.apply_uV = true;
825 rx51_twldata.vdac->constraints.name = "VDAC";
826
850 omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata); 827 omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
851 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, 828 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
852 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); 829 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index fec4cac8fa0a..5ea142f9bc97 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -160,7 +160,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
160 .reserve = rx51_reserve, 160 .reserve = rx51_reserve,
161 .map_io = rx51_map_io, 161 .map_io = rx51_map_io,
162 .init_early = rx51_init_early, 162 .init_early = rx51_init_early,
163 .init_irq = omap_init_irq, 163 .init_irq = omap3_init_irq,
164 .init_machine = rx51_init, 164 .init_machine = rx51_init,
165 .timer = &omap_timer, 165 .timer = &omap3_timer,
166MACHINE_END 166MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 09fa7bfff8d6..a85d5b0b11da 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -33,11 +33,6 @@ static void __init ti8168_init_early(void)
33 omap2_init_common_devices(NULL, NULL); 33 omap2_init_common_devices(NULL, NULL);
34} 34}
35 35
36static void __init ti8168_evm_init_irq(void)
37{
38 omap_init_irq();
39}
40
41static void __init ti8168_evm_init(void) 36static void __init ti8168_evm_init(void)
42{ 37{
43 omap_serial_init(); 38 omap_serial_init();
@@ -56,7 +51,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
56 .boot_params = 0x80000100, 51 .boot_params = 0x80000100,
57 .map_io = ti8168_evm_map_io, 52 .map_io = ti8168_evm_map_io,
58 .init_early = ti8168_init_early, 53 .init_early = ti8168_init_early,
59 .init_irq = ti8168_evm_init_irq, 54 .init_irq = ti816x_init_irq,
60 .timer = &omap_timer, 55 .timer = &omap3_timer,
61 .init_machine = ti8168_evm_init, 56 .init_machine = ti8168_evm_init,
62MACHINE_END 57MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 118c6f53c5eb..13a644233667 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -105,21 +105,20 @@ static struct twl4030_keypad_data zoom_kp_twl4030_data = {
105 .rep = 1, 105 .rep = 1,
106}; 106};
107 107
108static struct regulator_consumer_supply zoom_vmmc1_supply = { 108static struct regulator_consumer_supply zoom_vmmc1_supply[] = {
109 .supply = "vmmc", 109 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
110}; 110};
111 111
112static struct regulator_consumer_supply zoom_vsim_supply = { 112static struct regulator_consumer_supply zoom_vsim_supply[] = {
113 .supply = "vmmc_aux", 113 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
114}; 114};
115 115
116static struct regulator_consumer_supply zoom_vmmc2_supply = { 116static struct regulator_consumer_supply zoom_vmmc2_supply[] = {
117 .supply = "vmmc", 117 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
118}; 118};
119 119
120static struct regulator_consumer_supply zoom_vmmc3_supply = { 120static struct regulator_consumer_supply zoom_vmmc3_supply[] = {
121 .supply = "vmmc", 121 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
122 .dev_name = "omap_hsmmc.2",
123}; 122};
124 123
125/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 124/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -133,8 +132,8 @@ static struct regulator_init_data zoom_vmmc1 = {
133 | REGULATOR_CHANGE_MODE 132 | REGULATOR_CHANGE_MODE
134 | REGULATOR_CHANGE_STATUS, 133 | REGULATOR_CHANGE_STATUS,
135 }, 134 },
136 .num_consumer_supplies = 1, 135 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc1_supply),
137 .consumer_supplies = &zoom_vmmc1_supply, 136 .consumer_supplies = zoom_vmmc1_supply,
138}; 137};
139 138
140/* VMMC2 for MMC2 card */ 139/* VMMC2 for MMC2 card */
@@ -148,8 +147,8 @@ static struct regulator_init_data zoom_vmmc2 = {
148 .valid_ops_mask = REGULATOR_CHANGE_MODE 147 .valid_ops_mask = REGULATOR_CHANGE_MODE
149 | REGULATOR_CHANGE_STATUS, 148 | REGULATOR_CHANGE_STATUS,
150 }, 149 },
151 .num_consumer_supplies = 1, 150 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc2_supply),
152 .consumer_supplies = &zoom_vmmc2_supply, 151 .consumer_supplies = zoom_vmmc2_supply,
153}; 152};
154 153
155/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ 154/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -163,16 +162,16 @@ static struct regulator_init_data zoom_vsim = {
163 | REGULATOR_CHANGE_MODE 162 | REGULATOR_CHANGE_MODE
164 | REGULATOR_CHANGE_STATUS, 163 | REGULATOR_CHANGE_STATUS,
165 }, 164 },
166 .num_consumer_supplies = 1, 165 .num_consumer_supplies = ARRAY_SIZE(zoom_vsim_supply),
167 .consumer_supplies = &zoom_vsim_supply, 166 .consumer_supplies = zoom_vsim_supply,
168}; 167};
169 168
170static struct regulator_init_data zoom_vmmc3 = { 169static struct regulator_init_data zoom_vmmc3 = {
171 .constraints = { 170 .constraints = {
172 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 171 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
173 }, 172 },
174 .num_consumer_supplies = 1, 173 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc3_supply),
175 .consumer_supplies = &zoom_vmmc3_supply, 174 .consumer_supplies = zoom_vmmc3_supply,
176}; 175};
177 176
178static struct fixed_voltage_config zoom_vwlan = { 177static struct fixed_voltage_config zoom_vwlan = {
@@ -227,40 +226,6 @@ static struct omap2_hsmmc_info mmc[] = {
227 {} /* Terminator */ 226 {} /* Terminator */
228}; 227};
229 228
230static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
231 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
232 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
233};
234
235static struct regulator_consumer_supply zoom_vdda_dac_supply =
236 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
237
238static struct regulator_init_data zoom_vpll2 = {
239 .constraints = {
240 .min_uV = 1800000,
241 .max_uV = 1800000,
242 .valid_modes_mask = REGULATOR_MODE_NORMAL
243 | REGULATOR_MODE_STANDBY,
244 .valid_ops_mask = REGULATOR_CHANGE_MODE
245 | REGULATOR_CHANGE_STATUS,
246 },
247 .num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies),
248 .consumer_supplies = zoom_vpll2_supplies,
249};
250
251static struct regulator_init_data zoom_vdac = {
252 .constraints = {
253 .min_uV = 1800000,
254 .max_uV = 1800000,
255 .valid_modes_mask = REGULATOR_MODE_NORMAL
256 | REGULATOR_MODE_STANDBY,
257 .valid_ops_mask = REGULATOR_CHANGE_MODE
258 | REGULATOR_CHANGE_STATUS,
259 },
260 .num_consumer_supplies = 1,
261 .consumer_supplies = &zoom_vdda_dac_supply,
262};
263
264static int zoom_twl_gpio_setup(struct device *dev, 229static int zoom_twl_gpio_setup(struct device *dev,
265 unsigned gpio, unsigned ngpio) 230 unsigned gpio, unsigned ngpio)
266{ 231{
@@ -270,13 +235,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
270 mmc[0].gpio_cd = gpio + 0; 235 mmc[0].gpio_cd = gpio + 0;
271 omap2_hsmmc_init(mmc); 236 omap2_hsmmc_init(mmc);
272 237
273 /* link regulators to MMC adapters ... we "know" the
274 * regulators will be set up only *after* we return.
275 */
276 zoom_vmmc1_supply.dev = mmc[0].dev;
277 zoom_vsim_supply.dev = mmc[0].dev;
278 zoom_vmmc2_supply.dev = mmc[1].dev;
279
280 ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, 238 ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
281 "lcd enable"); 239 "lcd enable");
282 if (ret) 240 if (ret)
@@ -292,26 +250,6 @@ static void zoom2_set_hs_extmute(int mute)
292 gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); 250 gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
293} 251}
294 252
295static int zoom_batt_table[] = {
296/* 0 C*/
29730800, 29500, 28300, 27100,
29826000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
29917200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
30011600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
3018020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
3025640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
3034040, 3910, 3790, 3670, 3550
304};
305
306static struct twl4030_bci_platform_data zoom_bci_data = {
307 .battery_tmp_tbl = zoom_batt_table,
308 .tblsize = ARRAY_SIZE(zoom_batt_table),
309};
310
311static struct twl4030_usb_data zoom_usb_data = {
312 .usb_mode = T2_USB_MODE_ULPI,
313};
314
315static struct twl4030_gpio_platform_data zoom_gpio_data = { 253static struct twl4030_gpio_platform_data zoom_gpio_data = {
316 .gpio_base = OMAP_MAX_GPIO_LINES, 254 .gpio_base = OMAP_MAX_GPIO_LINES,
317 .irq_base = TWL4030_GPIO_IRQ_BASE, 255 .irq_base = TWL4030_GPIO_IRQ_BASE,
@@ -319,41 +257,29 @@ static struct twl4030_gpio_platform_data zoom_gpio_data = {
319 .setup = zoom_twl_gpio_setup, 257 .setup = zoom_twl_gpio_setup,
320}; 258};
321 259
322static struct twl4030_madc_platform_data zoom_madc_data = {
323 .irq_line = 1,
324};
325
326static struct twl4030_codec_audio_data zoom_audio_data;
327
328static struct twl4030_codec_data zoom_codec_data = {
329 .audio_mclk = 26000000,
330 .audio = &zoom_audio_data,
331};
332
333static struct twl4030_platform_data zoom_twldata = { 260static struct twl4030_platform_data zoom_twldata = {
334 .irq_base = TWL4030_IRQ_BASE,
335 .irq_end = TWL4030_IRQ_END,
336
337 /* platform_data for children goes here */ 261 /* platform_data for children goes here */
338 .bci = &zoom_bci_data,
339 .madc = &zoom_madc_data,
340 .usb = &zoom_usb_data,
341 .gpio = &zoom_gpio_data, 262 .gpio = &zoom_gpio_data,
342 .keypad = &zoom_kp_twl4030_data, 263 .keypad = &zoom_kp_twl4030_data,
343 .codec = &zoom_codec_data,
344 .vmmc1 = &zoom_vmmc1, 264 .vmmc1 = &zoom_vmmc1,
345 .vmmc2 = &zoom_vmmc2, 265 .vmmc2 = &zoom_vmmc2,
346 .vsim = &zoom_vsim, 266 .vsim = &zoom_vsim,
347 .vpll2 = &zoom_vpll2,
348 .vdac = &zoom_vdac,
349}; 267};
350 268
351static int __init omap_i2c_init(void) 269static int __init omap_i2c_init(void)
352{ 270{
271 omap3_pmic_get_config(&zoom_twldata,
272 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
273 TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
274 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
275
353 if (machine_is_omap_zoom2()) { 276 if (machine_is_omap_zoom2()) {
354 zoom_audio_data.ramp_delay_value = 3; /* 161 ms */ 277 struct twl4030_codec_audio_data *audio_data;
355 zoom_audio_data.hs_extmute = 1; 278 audio_data = zoom_twldata.codec->audio;
356 zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute; 279
280 audio_data->ramp_delay_value = 3; /* 161 ms */
281 audio_data->hs_extmute = 1;
282 audio_data->set_hs_extmute = zoom2_set_hs_extmute;
357 } 283 }
358 omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata); 284 omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
359 omap_register_i2c_bus(2, 400, NULL, 0); 285 omap_register_i2c_bus(2, 400, NULL, 0);
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4b133d75c935..8a98c3c303fc 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -137,9 +137,9 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
137 .reserve = omap_reserve, 137 .reserve = omap_reserve,
138 .map_io = omap3_map_io, 138 .map_io = omap3_map_io,
139 .init_early = omap_zoom_init_early, 139 .init_early = omap_zoom_init_early,
140 .init_irq = omap_init_irq, 140 .init_irq = omap3_init_irq,
141 .init_machine = omap_zoom_init, 141 .init_machine = omap_zoom_init,
142 .timer = &omap_timer, 142 .timer = &omap3_timer,
143MACHINE_END 143MACHINE_END
144 144
145MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") 145MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
@@ -147,7 +147,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
147 .reserve = omap_reserve, 147 .reserve = omap_reserve,
148 .map_io = omap3_map_io, 148 .map_io = omap3_map_io,
149 .init_early = omap_zoom_init_early, 149 .init_early = omap_zoom_init_early,
150 .init_irq = omap_init_irq, 150 .init_irq = omap3_init_irq,
151 .init_machine = omap_zoom_init, 151 .init_machine = omap_zoom_init,
152 .timer = &omap_timer, 152 .timer = &omap3_timer,
153MACHINE_END 153MACHINE_END
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index 6be1095936db..7ceb870e7ab8 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -8,13 +8,6 @@
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
10 10
11/*
12 * XXX Missing values for the OMAP4 DPLL_USB
13 * XXX Missing min_multiplier values for all OMAP4 DPLLs
14 */
15#define OMAP4430_MAX_DPLL_MULT 2047
16#define OMAP4430_MAX_DPLL_DIV 128
17
18int omap4xxx_clk_init(void); 11int omap4xxx_clk_init(void);
19 12
20#endif 13#endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 72a3976d6c43..257882028492 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
53static struct clk pad_clks_ck = { 53static struct clk pad_clks_ck = {
54 .name = "pad_clks_ck", 54 .name = "pad_clks_ck",
55 .rate = 12000000, 55 .rate = 12000000,
56 .ops = &clkops_omap2_dflt, 56 .ops = &clkops_omap2_dflt,
57 .enable_reg = OMAP4430_CM_CLKSEL_ABE, 57 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, 58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
59}; 59};
60 60
61static struct clk pad_slimbus_core_clks_ck = { 61static struct clk pad_slimbus_core_clks_ck = {
@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
73static struct clk slimbus_clk = { 73static struct clk slimbus_clk = {
74 .name = "slimbus_clk", 74 .name = "slimbus_clk",
75 .rate = 12000000, 75 .rate = 12000000,
76 .ops = &clkops_omap2_dflt, 76 .ops = &clkops_omap2_dflt,
77 .enable_reg = OMAP4430_CM_CLKSEL_ABE, 77 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, 78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
79}; 79};
80 80
81static struct clk sys_32k_ck = { 81static struct clk sys_32k_ck = {
@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
258 .enable_mask = OMAP4430_DPLL_EN_MASK, 258 .enable_mask = OMAP4430_DPLL_EN_MASK,
259 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 259 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
260 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 260 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
261 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 261 .max_multiplier = 2047,
262 .max_divider = OMAP4430_MAX_DPLL_DIV, 262 .max_divider = 128,
263 .min_divider = 1, 263 .min_divider = 1,
264}; 264};
265 265
@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
278static struct clk dpll_abe_x2_ck = { 278static struct clk dpll_abe_x2_ck = {
279 .name = "dpll_abe_x2_ck", 279 .name = "dpll_abe_x2_ck",
280 .parent = &dpll_abe_ck, 280 .parent = &dpll_abe_ck,
281 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
281 .flags = CLOCK_CLKOUTX2, 282 .flags = CLOCK_CLKOUTX2,
282 .ops = &clkops_omap4_dpllmx_ops, 283 .ops = &clkops_omap4_dpllmx_ops,
283 .recalc = &omap3_clkoutx2_recalc, 284 .recalc = &omap3_clkoutx2_recalc,
284 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
285}; 285};
286 286
287static const struct clksel_rate div31_1to31_rates[] = { 287static const struct clksel_rate div31_1to31_rates[] = {
@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
434 .enable_mask = OMAP4430_DPLL_EN_MASK, 434 .enable_mask = OMAP4430_DPLL_EN_MASK,
435 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 435 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
436 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 436 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
437 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 437 .max_multiplier = 2047,
438 .max_divider = OMAP4430_MAX_DPLL_DIV, 438 .max_divider = 128,
439 .min_divider = 1, 439 .min_divider = 1,
440}; 440};
441 441
@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, 622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
624 .ops = &clkops_omap2_dflt, 624 .ops = &clkops_omap2_dflt,
625 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
626 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
627 .recalc = &omap2_clksel_recalc, 625 .recalc = &omap2_clksel_recalc,
628 .round_rate = &omap2_clksel_round_rate, 626 .round_rate = &omap2_clksel_round_rate,
629 .set_rate = &omap2_clksel_set_rate, 627 .set_rate = &omap2_clksel_set_rate,
628 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
629 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
630}; 630};
631 631
632static struct clk dpll_core_m7x2_ck = { 632static struct clk dpll_core_m7x2_ck = {
@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
672 .enable_mask = OMAP4430_DPLL_EN_MASK, 672 .enable_mask = OMAP4430_DPLL_EN_MASK,
673 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 673 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
674 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 674 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
675 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 675 .max_multiplier = 2047,
676 .max_divider = OMAP4430_MAX_DPLL_DIV, 676 .max_divider = 128,
677 .min_divider = 1, 677 .min_divider = 1,
678}; 678};
679 679
@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
740 .enable_mask = OMAP4430_DPLL_EN_MASK, 740 .enable_mask = OMAP4430_DPLL_EN_MASK,
741 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 741 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
742 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 742 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
743 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 743 .max_multiplier = 2047,
744 .max_divider = OMAP4430_MAX_DPLL_DIV, 744 .max_divider = 128,
745 .min_divider = 1, 745 .min_divider = 1,
746}; 746};
747 747
@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
813 .enable_mask = OMAP4430_DPLL_EN_MASK, 813 .enable_mask = OMAP4430_DPLL_EN_MASK,
814 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 814 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
815 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 815 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
816 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 816 .max_multiplier = 2047,
817 .max_divider = OMAP4430_MAX_DPLL_DIV, 817 .max_divider = 128,
818 .min_divider = 1, 818 .min_divider = 1,
819}; 819};
820 820
@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
850static struct clk dpll_per_x2_ck = { 850static struct clk dpll_per_x2_ck = {
851 .name = "dpll_per_x2_ck", 851 .name = "dpll_per_x2_ck",
852 .parent = &dpll_per_ck, 852 .parent = &dpll_per_ck,
853 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
853 .flags = CLOCK_CLKOUTX2, 854 .flags = CLOCK_CLKOUTX2,
854 .ops = &clkops_omap4_dpllmx_ops, 855 .ops = &clkops_omap4_dpllmx_ops,
855 .recalc = &omap3_clkoutx2_recalc, 856 .recalc = &omap3_clkoutx2_recalc,
856 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
857}; 857};
858 858
859static const struct clksel dpll_per_m2x2_div[] = { 859static const struct clksel dpll_per_m2x2_div[] = {
@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
880 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, 880 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
881 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 881 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
882 .ops = &clkops_omap2_dflt, 882 .ops = &clkops_omap2_dflt,
883 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
884 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
885 .recalc = &omap2_clksel_recalc, 883 .recalc = &omap2_clksel_recalc,
886 .round_rate = &omap2_clksel_round_rate, 884 .round_rate = &omap2_clksel_round_rate,
887 .set_rate = &omap2_clksel_set_rate, 885 .set_rate = &omap2_clksel_set_rate,
886 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
887 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
888}; 888};
889 889
890static struct clk dpll_per_m4x2_ck = { 890static struct clk dpll_per_m4x2_ck = {
@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
935 .set_rate = &omap2_clksel_set_rate, 935 .set_rate = &omap2_clksel_set_rate,
936}; 936};
937 937
938/* DPLL_UNIPRO */
939static struct dpll_data dpll_unipro_dd = {
940 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
941 .clk_bypass = &sys_clkin_ck,
942 .clk_ref = &sys_clkin_ck,
943 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
944 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
945 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
946 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
947 .mult_mask = OMAP4430_DPLL_MULT_MASK,
948 .div1_mask = OMAP4430_DPLL_DIV_MASK,
949 .enable_mask = OMAP4430_DPLL_EN_MASK,
950 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
951 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
952 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
953 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
954 .max_divider = OMAP4430_MAX_DPLL_DIV,
955 .min_divider = 1,
956};
957
958
959static struct clk dpll_unipro_ck = {
960 .name = "dpll_unipro_ck",
961 .parent = &sys_clkin_ck,
962 .dpll_data = &dpll_unipro_dd,
963 .init = &omap2_init_dpll_parent,
964 .ops = &clkops_omap3_noncore_dpll_ops,
965 .recalc = &omap3_dpll_recalc,
966 .round_rate = &omap2_dpll_round_rate,
967 .set_rate = &omap3_noncore_dpll_set_rate,
968};
969
970static struct clk dpll_unipro_x2_ck = {
971 .name = "dpll_unipro_x2_ck",
972 .parent = &dpll_unipro_ck,
973 .flags = CLOCK_CLKOUTX2,
974 .ops = &clkops_null,
975 .recalc = &omap3_clkoutx2_recalc,
976};
977
978static const struct clksel dpll_unipro_m2x2_div[] = {
979 { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
980 { .parent = NULL },
981};
982
983static struct clk dpll_unipro_m2x2_ck = {
984 .name = "dpll_unipro_m2x2_ck",
985 .parent = &dpll_unipro_x2_ck,
986 .clksel = dpll_unipro_m2x2_div,
987 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
988 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
989 .ops = &clkops_omap4_dpllmx_ops,
990 .recalc = &omap2_clksel_recalc,
991 .round_rate = &omap2_clksel_round_rate,
992 .set_rate = &omap2_clksel_set_rate,
993};
994
995static struct clk usb_hs_clk_div_ck = { 938static struct clk usb_hs_clk_div_ck = {
996 .name = "usb_hs_clk_div_ck", 939 .name = "usb_hs_clk_div_ck",
997 .parent = &dpll_abe_m3x2_ck, 940 .parent = &dpll_abe_m3x2_ck,
@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
1015 .enable_mask = OMAP4430_DPLL_EN_MASK, 958 .enable_mask = OMAP4430_DPLL_EN_MASK,
1016 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 959 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
1017 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 960 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
1018 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 961 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
1019 .max_divider = OMAP4430_MAX_DPLL_DIV, 962 .max_multiplier = 4095,
963 .max_divider = 256,
1020 .min_divider = 1, 964 .min_divider = 1,
1021}; 965};
1022 966
@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
1035static struct clk dpll_usb_clkdcoldo_ck = { 979static struct clk dpll_usb_clkdcoldo_ck = {
1036 .name = "dpll_usb_clkdcoldo_ck", 980 .name = "dpll_usb_clkdcoldo_ck",
1037 .parent = &dpll_usb_ck, 981 .parent = &dpll_usb_ck,
1038 .ops = &clkops_omap4_dpllmx_ops,
1039 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, 982 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
983 .ops = &clkops_omap4_dpllmx_ops,
1040 .recalc = &followparent_recalc, 984 .recalc = &followparent_recalc,
1041}; 985};
1042 986
@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
1169 .set_rate = &omap2_clksel_set_rate, 1113 .set_rate = &omap2_clksel_set_rate,
1170}; 1114};
1171 1115
1172static const struct clksel hsmmc6_fclk_sel[] = {
1173 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1174 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1175 { .parent = NULL },
1176};
1177
1178static struct clk hsmmc6_fclk = {
1179 .name = "hsmmc6_fclk",
1180 .parent = &func_64m_fclk,
1181 .ops = &clkops_null,
1182 .recalc = &followparent_recalc,
1183};
1184
1185static const struct clksel_rate div2_1to8_rates[] = { 1116static const struct clksel_rate div2_1to8_rates[] = {
1186 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 1117 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1187 { .div = 8, .val = 1, .flags = RATE_IN_4430 }, 1118 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
1264 .recalc = &omap2_clksel_recalc, 1195 .recalc = &omap2_clksel_recalc,
1265}; 1196};
1266 1197
1198static struct clk ocp_abe_iclk = {
1199 .name = "ocp_abe_iclk",
1200 .parent = &aess_fclk,
1201 .ops = &clkops_null,
1202 .recalc = &followparent_recalc,
1203};
1204
1205static struct clk per_abe_24m_fclk = {
1206 .name = "per_abe_24m_fclk",
1207 .parent = &dpll_abe_m2_ck,
1208 .ops = &clkops_null,
1209 .fixed_div = 4,
1210 .recalc = &omap_fixed_divisor_recalc,
1211};
1212
1267static const struct clksel per_abe_nc_fclk_div[] = { 1213static const struct clksel per_abe_nc_fclk_div[] = {
1268 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, 1214 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1269 { .parent = NULL }, 1215 { .parent = NULL },
@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
1281 .set_rate = &omap2_clksel_set_rate, 1227 .set_rate = &omap2_clksel_set_rate,
1282}; 1228};
1283 1229
1284static const struct clksel mcasp2_fclk_sel[] = {
1285 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1286 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1287 { .parent = NULL },
1288};
1289
1290static struct clk mcasp2_fclk = {
1291 .name = "mcasp2_fclk",
1292 .parent = &func_96m_fclk,
1293 .ops = &clkops_null,
1294 .recalc = &followparent_recalc,
1295};
1296
1297static struct clk mcasp3_fclk = {
1298 .name = "mcasp3_fclk",
1299 .parent = &func_96m_fclk,
1300 .ops = &clkops_null,
1301 .recalc = &followparent_recalc,
1302};
1303
1304static struct clk ocp_abe_iclk = {
1305 .name = "ocp_abe_iclk",
1306 .parent = &aess_fclk,
1307 .ops = &clkops_null,
1308 .recalc = &followparent_recalc,
1309};
1310
1311static struct clk per_abe_24m_fclk = {
1312 .name = "per_abe_24m_fclk",
1313 .parent = &dpll_abe_m2_ck,
1314 .ops = &clkops_null,
1315 .fixed_div = 4,
1316 .recalc = &omap_fixed_divisor_recalc,
1317};
1318
1319static const struct clksel pmd_stm_clock_mux_sel[] = { 1230static const struct clksel pmd_stm_clock_mux_sel[] = {
1320 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1231 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1321 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, 1232 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@@ -1847,8 +1758,8 @@ static struct clk l3_instr_ick = {
1847 .ops = &clkops_omap2_dflt, 1758 .ops = &clkops_omap2_dflt,
1848 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1759 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1849 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1760 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1850 .clkdm_name = "l3_instr_clkdm",
1851 .flags = ENABLE_ON_INIT, 1761 .flags = ENABLE_ON_INIT,
1762 .clkdm_name = "l3_instr_clkdm",
1852 .parent = &l3_div_ck, 1763 .parent = &l3_div_ck,
1853 .recalc = &followparent_recalc, 1764 .recalc = &followparent_recalc,
1854}; 1765};
@@ -1858,8 +1769,8 @@ static struct clk l3_main_3_ick = {
1858 .ops = &clkops_omap2_dflt, 1769 .ops = &clkops_omap2_dflt,
1859 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1770 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1860 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1771 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1861 .clkdm_name = "l3_instr_clkdm",
1862 .flags = ENABLE_ON_INIT, 1772 .flags = ENABLE_ON_INIT,
1773 .clkdm_name = "l3_instr_clkdm",
1863 .parent = &l3_div_ck, 1774 .parent = &l3_div_ck,
1864 .recalc = &followparent_recalc, 1775 .recalc = &followparent_recalc,
1865}; 1776};
@@ -1996,10 +1907,16 @@ static struct clk mcbsp3_fck = {
1996 .clkdm_name = "abe_clkdm", 1907 .clkdm_name = "abe_clkdm",
1997}; 1908};
1998 1909
1910static const struct clksel mcbsp4_sync_mux_sel[] = {
1911 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1912 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1913 { .parent = NULL },
1914};
1915
1999static struct clk mcbsp4_sync_mux_ck = { 1916static struct clk mcbsp4_sync_mux_ck = {
2000 .name = "mcbsp4_sync_mux_ck", 1917 .name = "mcbsp4_sync_mux_ck",
2001 .parent = &func_96m_fclk, 1918 .parent = &func_96m_fclk,
2002 .clksel = mcasp2_fclk_sel, 1919 .clksel = mcbsp4_sync_mux_sel,
2003 .init = &omap2_init_clksel_parent, 1920 .init = &omap2_init_clksel_parent,
2004 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 1921 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2005 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1922 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@@ -2078,11 +1995,17 @@ static struct clk mcspi4_fck = {
2078 .recalc = &followparent_recalc, 1995 .recalc = &followparent_recalc,
2079}; 1996};
2080 1997
1998static const struct clksel hsmmc1_fclk_sel[] = {
1999 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2000 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2001 { .parent = NULL },
2002};
2003
2081/* Merged hsmmc1_fclk into mmc1 */ 2004/* Merged hsmmc1_fclk into mmc1 */
2082static struct clk mmc1_fck = { 2005static struct clk mmc1_fck = {
2083 .name = "mmc1_fck", 2006 .name = "mmc1_fck",
2084 .parent = &func_64m_fclk, 2007 .parent = &func_64m_fclk,
2085 .clksel = hsmmc6_fclk_sel, 2008 .clksel = hsmmc1_fclk_sel,
2086 .init = &omap2_init_clksel_parent, 2009 .init = &omap2_init_clksel_parent,
2087 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 2010 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2088 .clksel_mask = OMAP4430_CLKSEL_MASK, 2011 .clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -2097,7 +2020,7 @@ static struct clk mmc1_fck = {
2097static struct clk mmc2_fck = { 2020static struct clk mmc2_fck = {
2098 .name = "mmc2_fck", 2021 .name = "mmc2_fck",
2099 .parent = &func_64m_fclk, 2022 .parent = &func_64m_fclk,
2100 .clksel = hsmmc6_fclk_sel, 2023 .clksel = hsmmc1_fclk_sel,
2101 .init = &omap2_init_clksel_parent, 2024 .init = &omap2_init_clksel_parent,
2102 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 2025 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2103 .clksel_mask = OMAP4430_CLKSEL_MASK, 2026 .clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -2163,8 +2086,8 @@ static struct clk ocp_wp_noc_ick = {
2163 .ops = &clkops_omap2_dflt, 2086 .ops = &clkops_omap2_dflt,
2164 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2087 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2165 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2088 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2166 .clkdm_name = "l3_instr_clkdm",
2167 .flags = ENABLE_ON_INIT, 2089 .flags = ENABLE_ON_INIT,
2090 .clkdm_name = "l3_instr_clkdm",
2168 .parent = &l3_div_ck, 2091 .parent = &l3_div_ck,
2169 .recalc = &followparent_recalc, 2092 .recalc = &followparent_recalc,
2170}; 2093};
@@ -2896,6 +2819,7 @@ static struct clk auxclk2_ck = {
2896 .enable_reg = OMAP4_SCRM_AUXCLK2, 2819 .enable_reg = OMAP4_SCRM_AUXCLK2,
2897 .enable_bit = OMAP4_ENABLE_SHIFT, 2820 .enable_bit = OMAP4_ENABLE_SHIFT,
2898}; 2821};
2822
2899static struct clk auxclk3_ck = { 2823static struct clk auxclk3_ck = {
2900 .name = "auxclk3_ck", 2824 .name = "auxclk3_ck",
2901 .parent = &sys_clkin_ck, 2825 .parent = &sys_clkin_ck,
@@ -3078,9 +3002,6 @@ static struct omap_clk omap44xx_clks[] = {
3078 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), 3002 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
3079 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), 3003 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
3080 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), 3004 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
3081 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
3082 CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
3083 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
3084 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), 3005 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
3085 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), 3006 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
3086 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), 3007 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
@@ -3093,17 +3014,14 @@ static struct omap_clk omap44xx_clks[] = {
3093 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), 3014 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3094 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), 3015 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3095 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), 3016 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3096 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
3097 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), 3017 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3098 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), 3018 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3099 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), 3019 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3100 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), 3020 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3101 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), 3021 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3102 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3103 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
3104 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
3105 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), 3022 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3106 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), 3023 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3024 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3107 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 3025 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3108 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 3026 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3109 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 3027 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
@@ -3115,10 +3033,10 @@ static struct omap_clk omap44xx_clks[] = {
3115 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 3033 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3116 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 3034 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3117 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), 3035 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
3118 CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), 3036 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
3119 CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), 3037 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
3120 CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), 3038 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
3121 CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X), 3039 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
3122 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 3040 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3123 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), 3041 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3124 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), 3042 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@@ -3205,7 +3123,6 @@ static struct omap_clk omap44xx_clks[] = {
3205 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), 3123 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
3206 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 3124 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3207 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 3125 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3208 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
3209 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), 3126 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
3210 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 3127 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3211 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), 3128 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
@@ -3217,9 +3134,7 @@ static struct omap_clk omap44xx_clks[] = {
3217 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), 3134 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3218 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), 3135 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3219 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), 3136 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3220 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
3221 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), 3137 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
3222 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
3223 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), 3138 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3224 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), 3139 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3225 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), 3140 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
@@ -3227,17 +3142,26 @@ static struct omap_clk omap44xx_clks[] = {
3227 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), 3142 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3228 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), 3143 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3229 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), 3144 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3230 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
3231 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 3145 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3232 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
3233 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 3146 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3234 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 3147 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3235 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3148 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3236 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), 3149 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
3237 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3238 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), 3150 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3239 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 3151 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3240 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 3152 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3153 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3154 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3155 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3156 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3157 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3158 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3159 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3160 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3161 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3162 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3163 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3164 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3241 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3165 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3242 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 3166 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
3243 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), 3167 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
@@ -3254,6 +3178,7 @@ static struct omap_clk omap44xx_clks[] = {
3254 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 3178 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3255 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 3179 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3256 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), 3180 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3181 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3257 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), 3182 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3258 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), 3183 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3259 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), 3184 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
@@ -3271,19 +3196,9 @@ static struct omap_clk omap44xx_clks[] = {
3271 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 3196 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3272 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 3197 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3273 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 3198 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3199 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
3200 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
3274 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3201 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3275 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3276 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3277 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3278 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3279 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3280 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3281 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3282 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3283 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3284 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3285 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3286 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3287}; 3202};
3288 3203
3289int __init omap4xxx_clk_init(void) 3204int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index a607ec196e8b..66090f2676ce 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -1,11 +1,12 @@
1/* 1/*
2 * OMAP4 Clock domains framework 2 * OMAP4 Clock domains framework
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2011 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com) 8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley (paul@pwsan.com)
9 * 10 *
10 * This file is automatically generated from the OMAP hardware databases. 11 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated 12 * We respectfully ask that any modifications to this file be coordinated
@@ -32,7 +33,7 @@
32 33
33/* Static Dependencies for OMAP4 Clock Domains */ 34/* Static Dependencies for OMAP4 Clock Domains */
34 35
35static struct clkdm_dep ducati_wkup_sleep_deps[] = { 36static struct clkdm_dep d2d_wkup_sleep_deps[] = {
36 { 37 {
37 .clkdm_name = "abe_clkdm", 38 .clkdm_name = "abe_clkdm",
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 39 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = {
50 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 51 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
51 }, 52 },
52 { 53 {
53 .clkdm_name = "l3_dss_clkdm", 54 .clkdm_name = "l3_emif_clkdm",
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 55 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
55 }, 56 },
56 { 57 {
57 .clkdm_name = "l3_emif_clkdm", 58 .clkdm_name = "l3_init_clkdm",
58 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 59 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
59 }, 60 },
60 { 61 {
61 .clkdm_name = "l3_gfx_clkdm", 62 .clkdm_name = "l4_cfg_clkdm",
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 63 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
63 }, 64 },
64 { 65 {
65 .clkdm_name = "l3_init_clkdm", 66 .clkdm_name = "l4_per_clkdm",
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 67 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
67 }, 68 },
69 { NULL },
70};
71
72static struct clkdm_dep ducati_wkup_sleep_deps[] = {
68 { 73 {
69 .clkdm_name = "l4_cfg_clkdm", 74 .clkdm_name = "abe_clkdm",
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
71 }, 76 },
72 { 77 {
73 .clkdm_name = "l4_per_clkdm", 78 .clkdm_name = "ivahd_clkdm",
74 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
75 }, 80 },
76 { 81 {
77 .clkdm_name = "l4_secure_clkdm", 82 .clkdm_name = "l3_1_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 83 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
79 }, 84 },
80 { 85 {
81 .clkdm_name = "l4_wkup_clkdm", 86 .clkdm_name = "l3_2_clkdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
83 }, 88 },
84 { 89 {
85 .clkdm_name = "tesla_clkdm", 90 .clkdm_name = "l3_dss_clkdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 91 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
87 }, 92 },
88 { NULL },
89};
90
91static struct clkdm_dep iss_wkup_sleep_deps[] = {
92 { 93 {
93 .clkdm_name = "ivahd_clkdm", 94 .clkdm_name = "l3_emif_clkdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
95 }, 96 },
96 { 97 {
97 .clkdm_name = "l3_1_clkdm", 98 .clkdm_name = "l3_gfx_clkdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 99 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
99 }, 100 },
100 { 101 {
101 .clkdm_name = "l3_emif_clkdm", 102 .clkdm_name = "l3_init_clkdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
103 }, 104 },
104 { NULL },
105};
106
107static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
108 { 105 {
109 .clkdm_name = "l3_1_clkdm", 106 .clkdm_name = "l4_cfg_clkdm",
110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
111 }, 108 },
112 { 109 {
113 .clkdm_name = "l3_emif_clkdm", 110 .clkdm_name = "l4_per_clkdm",
114 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
115 }, 112 },
116 { NULL },
117};
118
119static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
120 { 113 {
121 .clkdm_name = "abe_clkdm", 114 .clkdm_name = "l4_secure_clkdm",
122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
123 }, 116 },
124 { 117 {
125 .clkdm_name = "ivahd_clkdm", 118 .clkdm_name = "l4_wkup_clkdm",
126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
127 }, 120 },
128 { 121 {
129 .clkdm_name = "l3_1_clkdm", 122 .clkdm_name = "tesla_clkdm",
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
131 }, 124 },
125 { NULL },
126};
127
128static struct clkdm_dep iss_wkup_sleep_deps[] = {
132 { 129 {
133 .clkdm_name = "l3_2_clkdm", 130 .clkdm_name = "ivahd_clkdm",
134 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 131 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
135 }, 132 },
136 { 133 {
137 .clkdm_name = "l3_emif_clkdm", 134 .clkdm_name = "l3_1_clkdm",
138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
139 }, 136 },
140 { 137 {
141 .clkdm_name = "l3_init_clkdm", 138 .clkdm_name = "l3_emif_clkdm",
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 139 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
143 }, 140 },
141 { NULL },
142};
143
144static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
144 { 145 {
145 .clkdm_name = "l4_cfg_clkdm", 146 .clkdm_name = "l3_1_clkdm",
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
147 }, 148 },
148 { 149 {
149 .clkdm_name = "l4_per_clkdm", 150 .clkdm_name = "l3_emif_clkdm",
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
151 }, 152 },
152 { NULL }, 153 { NULL },
@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
280 { NULL }, 281 { NULL },
281}; 282};
282 283
283static struct clkdm_dep mpuss_wkup_sleep_deps[] = { 284static struct clkdm_dep mpu_wkup_sleep_deps[] = {
284 { 285 {
285 .clkdm_name = "abe_clkdm", 286 .clkdm_name = "abe_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
498}; 499};
499 500
500static struct clockdomain mpuss_44xx_clkdm = { 501static struct clockdomain d2d_44xx_clkdm = {
501 .name = "mpuss_clkdm", 502 .name = "d2d_clkdm",
502 .pwrdm = { .name = "mpu_pwrdm" }, 503 .pwrdm = { .name = "core_pwrdm" },
503 .prcm_partition = OMAP4430_CM1_PARTITION, 504 .prcm_partition = OMAP4430_CM2_PARTITION,
504 .cm_inst = OMAP4430_CM1_MPU_INST, 505 .cm_inst = OMAP4430_CM2_CORE_INST,
505 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, 506 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
506 .wkdep_srcs = mpuss_wkup_sleep_deps, 507 .wkdep_srcs = d2d_wkup_sleep_deps,
507 .sleepdep_srcs = mpuss_wkup_sleep_deps, 508 .sleepdep_srcs = d2d_wkup_sleep_deps,
508 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 509 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
510}; 511};
@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 564 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
564}; 565};
565 566
567static struct clockdomain mpu_44xx_clkdm = {
568 .name = "mpu_clkdm",
569 .pwrdm = { .name = "mpu_pwrdm" },
570 .prcm_partition = OMAP4430_CM1_PARTITION,
571 .cm_inst = OMAP4430_CM1_MPU_INST,
572 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
573 .wkdep_srcs = mpu_wkup_sleep_deps,
574 .sleepdep_srcs = mpu_wkup_sleep_deps,
575 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
577};
578
566static struct clockdomain l3_2_44xx_clkdm = { 579static struct clockdomain l3_2_44xx_clkdm = {
567 .name = "l3_2_clkdm", 580 .name = "l3_2_clkdm",
568 .pwrdm = { .name = "core_pwrdm" }, 581 .pwrdm = { .name = "core_pwrdm" },
@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 598 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
586}; 599};
587 600
588static struct clockdomain l3_d2d_44xx_clkdm = {
589 .name = "l3_d2d_clkdm",
590 .pwrdm = { .name = "core_pwrdm" },
591 .prcm_partition = OMAP4430_CM2_PARTITION,
592 .cm_inst = OMAP4430_CM2_CORE_INST,
593 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
594 .wkdep_srcs = l3_d2d_wkup_sleep_deps,
595 .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
596 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
598};
599
600static struct clockdomain iss_44xx_clkdm = { 601static struct clockdomain iss_44xx_clkdm = {
601 .name = "iss_clkdm", 602 .name = "iss_clkdm",
602 .pwrdm = { .name = "cam_pwrdm" }, 603 .pwrdm = { .name = "cam_pwrdm" },
@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 656 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
656}; 657};
657 658
659/* As clockdomains are added or removed above, this list must also be changed */
658static struct clockdomain *clockdomains_omap44xx[] __initdata = { 660static struct clockdomain *clockdomains_omap44xx[] __initdata = {
659 &l4_cefuse_44xx_clkdm, 661 &l4_cefuse_44xx_clkdm,
660 &l4_cfg_44xx_clkdm, 662 &l4_cfg_44xx_clkdm,
@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
666 &abe_44xx_clkdm, 668 &abe_44xx_clkdm,
667 &l3_instr_44xx_clkdm, 669 &l3_instr_44xx_clkdm,
668 &l3_init_44xx_clkdm, 670 &l3_init_44xx_clkdm,
669 &mpuss_44xx_clkdm, 671 &d2d_44xx_clkdm,
670 &mpu0_44xx_clkdm, 672 &mpu0_44xx_clkdm,
671 &mpu1_44xx_clkdm, 673 &mpu1_44xx_clkdm,
672 &l3_emif_44xx_clkdm, 674 &l3_emif_44xx_clkdm,
673 &l4_ao_44xx_clkdm, 675 &l4_ao_44xx_clkdm,
674 &ducati_44xx_clkdm, 676 &ducati_44xx_clkdm,
677 &mpu_44xx_clkdm,
675 &l3_2_44xx_clkdm, 678 &l3_2_44xx_clkdm,
676 &l3_1_44xx_clkdm, 679 &l3_1_44xx_clkdm,
677 &l3_d2d_44xx_clkdm,
678 &iss_44xx_clkdm, 680 &iss_44xx_clkdm,
679 &l3_dss_44xx_clkdm, 681 &l3_dss_44xx_clkdm,
680 &l4_wkup_44xx_clkdm, 682 &l4_wkup_44xx_clkdm,
681 &emu_sys_44xx_clkdm, 683 &emu_sys_44xx_clkdm,
682 &l3_dma_44xx_clkdm, 684 &l3_dma_44xx_clkdm,
683 NULL, 685 NULL
684}; 686};
685 687
686void __init omap44xx_clockdomains_init(void) 688void __init omap44xx_clockdomains_init(void)
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 9d47a05b17b4..0e77945d26ec 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,22 +22,18 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
24 24
25/* 25/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
26 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
27 * CM_TESLA_DYNAMICDEP
28 */
29#define OMAP4430_ABE_DYNDEP_SHIFT 3 26#define OMAP4430_ABE_DYNDEP_SHIFT 3
30#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) 27#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
31 28
32/* 29/*
33 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 30 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
34 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 31 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
35 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
36 */ 32 */
37#define OMAP4430_ABE_STATDEP_SHIFT 3 33#define OMAP4430_ABE_STATDEP_SHIFT 3
38#define OMAP4430_ABE_STATDEP_MASK (1 << 3) 34#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
39 35
40/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 36/* Used by CM_L4CFG_DYNAMICDEP */
41#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 37#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
42#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) 38#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
43 39
@@ -47,14 +43,13 @@
47 43
48/* 44/*
49 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, 45 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
50 * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, 46 * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
51 * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, 47 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
52 * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
53 */ 48 */
54#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 49#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
55#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 50#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
56 51
57/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 52/* Used by CM_L4CFG_DYNAMICDEP */
58#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 53#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
59#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) 54#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
60 55
@@ -82,15 +77,15 @@
82#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 77#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
83#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) 78#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
84 79
85/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 80/* Used by CM_MEMIF_CLKSTCTRL */
86#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 81#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
87#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) 82#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
88 83
89/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 84/* Used by CM_MEMIF_CLKSTCTRL */
90#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 85#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
91#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) 86#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
92 87
93/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 88/* Used by CM_MEMIF_CLKSTCTRL */
94#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 89#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
95#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) 90#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
96 91
@@ -110,31 +105,31 @@
110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 105#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
111#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 106#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
112 107
113/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 108/* Used by CM_MEMIF_CLKSTCTRL */
114#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 109#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
115#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) 110#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
116 111
117/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 112/* Used by CM_L4PER_CLKSTCTRL */
118#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 113#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
119#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) 114#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
120 115
121/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 116/* Used by CM_L4PER_CLKSTCTRL */
122#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 117#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
123#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) 118#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
124 119
125/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 120/* Used by CM_L4PER_CLKSTCTRL */
126#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 121#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
127#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) 122#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
128 123
129/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 124/* Used by CM_L4PER_CLKSTCTRL */
130#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 125#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
131#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) 126#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
132 127
133/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 128/* Used by CM_L4PER_CLKSTCTRL */
134#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 129#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
135#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) 130#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
136 131
137/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 132/* Used by CM_L4PER_CLKSTCTRL */
138#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 133#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
139#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) 134#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
140 135
@@ -158,7 +153,7 @@
158#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 153#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
159#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) 154#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
160 155
161/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 156/* Used by CM_L4PER_CLKSTCTRL */
162#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 157#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
163#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) 158#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
164 159
@@ -170,55 +165,55 @@
170#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 165#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
171#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) 166#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
172 167
173/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 168/* Used by CM_L3INIT_CLKSTCTRL */
174#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 169#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
175#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) 170#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
176 171
177/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 172/* Used by CM_L3INIT_CLKSTCTRL */
178#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 173#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
179#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) 174#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
180 175
181/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 176/* Used by CM_L3INIT_CLKSTCTRL */
182#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 177#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
183#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) 178#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
184 179
185/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 180/* Used by CM_L3INIT_CLKSTCTRL */
186#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 181#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
187#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) 182#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
188 183
189/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 184/* Used by CM_L3INIT_CLKSTCTRL */
190#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 185#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
191#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) 186#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
192 187
193/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 188/* Used by CM_L3INIT_CLKSTCTRL */
194#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 189#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
195#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) 190#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
196 191
197/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 192/* Used by CM_L3INIT_CLKSTCTRL */
198#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 193#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
199#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) 194#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
200 195
201/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 196/* Used by CM_L3INIT_CLKSTCTRL */
202#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 197#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
203#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) 198#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
204 199
205/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 200/* Used by CM_L3INIT_CLKSTCTRL */
206#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 201#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
207#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) 202#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
208 203
209/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 204/* Used by CM_L3INIT_CLKSTCTRL */
210#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 205#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
211#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) 206#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
212 207
213/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 208/* Used by CM_L3INIT_CLKSTCTRL */
214#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 209#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
215#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) 210#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
216 211
217/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 212/* Used by CM_L3INIT_CLKSTCTRL */
218#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 213#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
219#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) 214#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
220 215
221/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 216/* Used by CM_L3INIT_CLKSTCTRL */
222#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 217#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
223#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) 218#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
224 219
@@ -234,11 +229,11 @@
234#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 229#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
235#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) 230#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
236 231
237/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ 232/* Used by CM_L3_1_CLKSTCTRL */
238#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 233#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
239#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) 234#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
240 235
241/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ 236/* Used by CM_L3_2_CLKSTCTRL */
242#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 237#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
243#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) 238#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
244 239
@@ -254,7 +249,7 @@
254#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 249#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
255#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) 250#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
256 251
257/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 252/* Used by CM_MEMIF_CLKSTCTRL */
258#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 253#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
259#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) 254#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
260 255
@@ -262,7 +257,7 @@
262#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 257#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
263#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) 258#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
264 259
265/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 260/* Used by CM_L3INIT_CLKSTCTRL */
266#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 261#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
267#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) 262#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
268 263
@@ -282,7 +277,7 @@
282#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 277#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
283#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) 278#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
284 279
285/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ 280/* Used by CM_L4CFG_CLKSTCTRL */
286#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 281#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
287#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) 282#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
288 283
@@ -290,11 +285,11 @@
290#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 285#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
291#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) 286#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
292 287
293/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 288/* Used by CM_L3INIT_CLKSTCTRL */
294#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 289#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
295#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) 290#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
296 291
297/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 292/* Used by CM_L4PER_CLKSTCTRL */
298#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 293#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
299#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) 294#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
300 295
@@ -306,7 +301,7 @@
306#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 301#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
307#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) 302#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
308 303
309/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ 304/* Used by CM_MPU_CLKSTCTRL */
310#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 305#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
311#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) 306#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
312 307
@@ -314,43 +309,43 @@
314#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 309#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
315#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) 310#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
316 311
317/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 312/* Used by CM_L4PER_CLKSTCTRL */
318#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 313#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
319#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) 314#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
320 315
321/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 316/* Used by CM_L4PER_CLKSTCTRL */
322#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 317#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
323#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) 318#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
324 319
325/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 320/* Used by CM_L4PER_CLKSTCTRL */
326#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 321#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
327#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) 322#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
328 323
329/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 324/* Used by CM_L4PER_CLKSTCTRL */
330#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 325#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
331#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) 326#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
332 327
333/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 328/* Used by CM_L4PER_CLKSTCTRL */
334#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 329#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
335#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) 330#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
336 331
337/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 332/* Used by CM_L4PER_CLKSTCTRL */
338#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 333#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
339#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) 334#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
340 335
341/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 336/* Used by CM_L4PER_CLKSTCTRL */
342#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 337#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
343#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) 338#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
344 339
345/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 340/* Used by CM_L4PER_CLKSTCTRL */
346#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 341#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
347#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) 342#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
348 343
349/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 344/* Used by CM_L4PER_CLKSTCTRL */
350#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 345#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
351#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) 346#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
352 347
353/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 348/* Used by CM_MEMIF_CLKSTCTRL */
354#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 349#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
355#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) 350#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
356 351
@@ -378,27 +373,27 @@
378#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 373#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
379#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) 374#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
380 375
381/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 376/* Used by CM_L3INIT_CLKSTCTRL */
382#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 377#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
383#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) 378#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
384 379
385/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 380/* Used by CM_L3INIT_CLKSTCTRL */
386#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 381#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
387#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) 382#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
388 383
389/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 384/* Used by CM_L3INIT_CLKSTCTRL */
390#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 385#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
391#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) 386#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
392 387
393/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 388/* Used by CM_L3INIT_CLKSTCTRL */
394#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 389#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
395#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) 390#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
396 391
397/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 392/* Used by CM_L3INIT_CLKSTCTRL */
398#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 393#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
399#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) 394#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
400 395
401/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 396/* Used by CM_L3INIT_CLKSTCTRL */
402#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 397#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
403#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) 398#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
404 399
@@ -406,11 +401,11 @@
406#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 401#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
407#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) 402#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
408 403
409/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 404/* Used by CM_L3INIT_CLKSTCTRL */
410#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 405#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
411#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) 406#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
412 407
413/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 408/* Used by CM_L3INIT_CLKSTCTRL */
414#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 409#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
415#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) 410#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
416 411
@@ -432,7 +427,7 @@
432 427
433/* 428/*
434 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, 429 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
435 * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ 430 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
436 */ 431 */
437#define OMAP4430_CLKSEL_0_0_SHIFT 0 432#define OMAP4430_CLKSEL_0_0_SHIFT 0
438#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) 433#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
@@ -453,14 +448,11 @@
453#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 448#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
454#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 449#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
455 450
456/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 451/* Used by CM_CLKSEL_CORE */
457#define OMAP4430_CLKSEL_CORE_SHIFT 0 452#define OMAP4430_CLKSEL_CORE_SHIFT 0
458#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) 453#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
459 454
460/* 455/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
461 * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
462 * CM_SHADOW_FREQ_CONFIG2
463 */
464#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 456#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
465#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) 457#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
466 458
@@ -484,18 +476,15 @@
484#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 476#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
485#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) 477#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
486 478
487/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 479/* Used by CM_CLKSEL_CORE */
488#define OMAP4430_CLKSEL_L3_SHIFT 4 480#define OMAP4430_CLKSEL_L3_SHIFT 4
489#define OMAP4430_CLKSEL_L3_MASK (1 << 4) 481#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
490 482
491/* 483/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
492 * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
493 * CM_SHADOW_FREQ_CONFIG2
494 */
495#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 484#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
496#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) 485#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
497 486
498/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 487/* Used by CM_CLKSEL_CORE */
499#define OMAP4430_CLKSEL_L4_SHIFT 8 488#define OMAP4430_CLKSEL_L4_SHIFT 8
500#define OMAP4430_CLKSEL_L4_MASK (1 << 8) 489#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
501 490
@@ -526,11 +515,11 @@
526#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 515#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
527#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 516#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
528 517
529/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 518/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
530#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 519#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
531#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) 520#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
532 521
533/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 522/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
534#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 523#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
535#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) 524#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
536 525
@@ -538,13 +527,10 @@
538 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, 527 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
539 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, 528 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
540 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, 529 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
541 * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, 530 * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
542 * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, 531 * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
543 * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, 532 * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
544 * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, 533 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
545 * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
546 * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
547 * CM_WKUP_CLKSTCTRL
548 */ 534 */
549#define OMAP4430_CLKTRCTRL_SHIFT 0 535#define OMAP4430_CLKTRCTRL_SHIFT 0
550#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 536#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
@@ -561,10 +547,7 @@
561#define OMAP4430_CUSTOM_SHIFT 6 547#define OMAP4430_CUSTOM_SHIFT 6
562#define OMAP4430_CUSTOM_MASK (0x3 << 6) 548#define OMAP4430_CUSTOM_MASK (0x3 << 6)
563 549
564/* 550/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
565 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
566 * CM_L4CFG_DYNAMICDEP_RESTORE
567 */
568#define OMAP4430_D2D_DYNDEP_SHIFT 18 551#define OMAP4430_D2D_DYNDEP_SHIFT 18
569#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) 552#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
570 553
@@ -574,31 +557,29 @@
574 557
575/* 558/*
576 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 559 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
577 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, 560 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
578 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, 561 * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
579 * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, 562 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
580 * CM_SSC_DELTAMSTEP_DPLL_USB
581 */ 563 */
582#define OMAP4430_DELTAMSTEP_SHIFT 0 564#define OMAP4430_DELTAMSTEP_SHIFT 0
583#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 565#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
584 566
585/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 567/* Used by CM_DLL_CTRL */
586#define OMAP4430_DLL_OVERRIDE_SHIFT 2 568#define OMAP4430_DLL_OVERRIDE_SHIFT 0
587#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) 569#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
588 570
589/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ 571/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
590#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 572#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
591#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) 573#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
592 574
593/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 575/* Used by CM_SHADOW_FREQ_CONFIG1 */
594#define OMAP4430_DLL_RESET_SHIFT 3 576#define OMAP4430_DLL_RESET_SHIFT 3
595#define OMAP4430_DLL_RESET_MASK (1 << 3) 577#define OMAP4430_DLL_RESET_MASK (1 << 3)
596 578
597/* 579/*
598 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 580 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
599 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 581 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
600 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 582 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
601 * CM_CLKSEL_DPLL_USB
602 */ 583 */
603#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 584#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
604#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) 585#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
@@ -607,28 +588,19 @@
607#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 588#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
608#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) 589#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
609 590
610/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ 591/* Used by CM_CLKSEL_DPLL_CORE */
611#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 592#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
612#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) 593#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
613 594
614/* 595/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
615 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
616 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
617 */
618#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 596#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
619#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 597#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
620 598
621/* 599/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
622 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
623 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
624 */
625#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 600#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
626#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) 601#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
627 602
628/* 603/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
629 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
630 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
631 */
632#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 604#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
633#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) 605#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
634 606
@@ -637,9 +609,8 @@
637#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 609#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
638 610
639/* 611/*
640 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 612 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
641 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 613 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
642 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
643 */ 614 */
644#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 615#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
645#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 616#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
@@ -649,9 +620,8 @@
649#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 620#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
650 621
651/* 622/*
652 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 623 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
653 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 624 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
654 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
655 */ 625 */
656#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 626#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
657#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) 627#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
@@ -661,29 +631,28 @@
661#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) 631#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
662 632
663/* 633/*
664 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 634 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
665 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 635 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
666 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
667 */ 636 */
668#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 637#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
669#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 638#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
670 639
671/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 640/* Used by CM_SHADOW_FREQ_CONFIG1 */
672#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 641#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
673#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) 642#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
674 643
675/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 644/* Used by CM_SHADOW_FREQ_CONFIG1 */
676#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 645#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
677#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) 646#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
678 647
679/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 648/* Used by CM_SHADOW_FREQ_CONFIG2 */
680#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 649#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
681#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) 650#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
682 651
683/* 652/*
684 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 653 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
685 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 654 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
686 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 655 * CM_CLKSEL_DPLL_UNIPRO
687 */ 656 */
688#define OMAP4430_DPLL_DIV_SHIFT 0 657#define OMAP4430_DPLL_DIV_SHIFT 0
689#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 658#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
@@ -693,9 +662,8 @@
693#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 662#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
694 663
695/* 664/*
696 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 665 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
697 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 666 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
698 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
699 */ 667 */
700#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 668#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
701#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 669#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
@@ -705,26 +673,25 @@
705#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) 673#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
706 674
707/* 675/*
708 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 676 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
709 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 677 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
710 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 678 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
711 * CM_CLKMODE_DPLL_USB
712 */ 679 */
713#define OMAP4430_DPLL_EN_SHIFT 0 680#define OMAP4430_DPLL_EN_SHIFT 0
714#define OMAP4430_DPLL_EN_MASK (0x7 << 0) 681#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
715 682
716/* 683/*
717 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 684 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
718 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 685 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
719 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 686 * CM_CLKMODE_DPLL_UNIPRO
720 */ 687 */
721#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 688#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
722#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 689#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
723 690
724/* 691/*
725 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 692 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
726 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 693 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
727 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 694 * CM_CLKSEL_DPLL_UNIPRO
728 */ 695 */
729#define OMAP4430_DPLL_MULT_SHIFT 8 696#define OMAP4430_DPLL_MULT_SHIFT 8
730#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 697#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
@@ -734,9 +701,9 @@
734#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 701#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
735 702
736/* 703/*
737 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 704 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
738 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 705 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
739 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 706 * CM_CLKMODE_DPLL_UNIPRO
740 */ 707 */
741#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 708#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
742#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 709#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
@@ -746,55 +713,46 @@
746#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 713#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
747 714
748/* 715/*
749 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 716 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
750 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 717 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
751 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 718 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
752 * CM_CLKMODE_DPLL_USB
753 */ 719 */
754#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 720#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
755#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) 721#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
756 722
757/* 723/*
758 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 724 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
759 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 725 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
760 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 726 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
761 * CM_CLKMODE_DPLL_USB
762 */ 727 */
763#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 728#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
764#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 729#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
765 730
766/* 731/*
767 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 732 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
768 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 733 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
769 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 734 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
770 * CM_CLKMODE_DPLL_USB
771 */ 735 */
772#define OMAP4430_DPLL_SSC_EN_SHIFT 12 736#define OMAP4430_DPLL_SSC_EN_SHIFT 12
773#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) 737#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
774 738
775/* 739/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
776 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
777 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
778 */
779#define OMAP4430_DSS_DYNDEP_SHIFT 8 740#define OMAP4430_DSS_DYNDEP_SHIFT 8
780#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) 741#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
781 742
782/* 743/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
783 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
784 * CM_SDMA_STATICDEP_RESTORE
785 */
786#define OMAP4430_DSS_STATDEP_SHIFT 8 744#define OMAP4430_DSS_STATDEP_SHIFT 8
787#define OMAP4430_DSS_STATDEP_MASK (1 << 8) 745#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
788 746
789/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 747/* Used by CM_L3_2_DYNAMICDEP */
790#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 748#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
791#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) 749#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
792 750
793/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ 751/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
794#define OMAP4430_DUCATI_STATDEP_SHIFT 0 752#define OMAP4430_DUCATI_STATDEP_SHIFT 0
795#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) 753#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
796 754
797/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 755/* Used by CM_SHADOW_FREQ_CONFIG1 */
798#define OMAP4430_FREQ_UPDATE_SHIFT 0 756#define OMAP4430_FREQ_UPDATE_SHIFT 0
799#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) 757#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
800 758
@@ -802,7 +760,7 @@
802#define OMAP4430_FUNC_SHIFT 16 760#define OMAP4430_FUNC_SHIFT 16
803#define OMAP4430_FUNC_MASK (0xfff << 16) 761#define OMAP4430_FUNC_MASK (0xfff << 16)
804 762
805/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 763/* Used by CM_L3_2_DYNAMICDEP */
806#define OMAP4430_GFX_DYNDEP_SHIFT 10 764#define OMAP4430_GFX_DYNDEP_SHIFT 10
807#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) 765#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
808 766
@@ -810,119 +768,95 @@
810#define OMAP4430_GFX_STATDEP_SHIFT 10 768#define OMAP4430_GFX_STATDEP_SHIFT 10
811#define OMAP4430_GFX_STATDEP_MASK (1 << 10) 769#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
812 770
813/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 771/* Used by CM_SHADOW_FREQ_CONFIG2 */
814#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 772#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
815#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) 773#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
816 774
817/* 775/*
818 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 776 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
819 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 777 * CM_DIV_M4_DPLL_PER
820 */ 778 */
821#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 779#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
822#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 780#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
823 781
824/* 782/*
825 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 783 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
826 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 784 * CM_DIV_M4_DPLL_PER
827 */ 785 */
828#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 786#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
829#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) 787#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
830 788
831/* 789/*
832 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 790 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
833 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 791 * CM_DIV_M4_DPLL_PER
834 */ 792 */
835#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 793#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
836#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) 794#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
837 795
838/* 796/*
839 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 797 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
840 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 798 * CM_DIV_M4_DPLL_PER
841 */ 799 */
842#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 800#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
843#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) 801#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
844 802
845/* 803/*
846 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 804 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
847 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 805 * CM_DIV_M5_DPLL_PER
848 */ 806 */
849#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 807#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
850#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 808#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
851 809
852/* 810/*
853 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 811 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
854 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 812 * CM_DIV_M5_DPLL_PER
855 */ 813 */
856#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 814#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
857#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) 815#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
858 816
859/* 817/*
860 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 818 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
861 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 819 * CM_DIV_M5_DPLL_PER
862 */ 820 */
863#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 821#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
864#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) 822#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
865 823
866/* 824/*
867 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 825 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
868 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 826 * CM_DIV_M5_DPLL_PER
869 */ 827 */
870#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 828#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
871#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) 829#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
872 830
873/* 831/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
874 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
875 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
876 */
877#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 832#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
878#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 833#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
879 834
880/* 835/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
881 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
882 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
883 */
884#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 836#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
885#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) 837#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
886 838
887/* 839/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
888 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
889 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
890 */
891#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 840#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
892#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) 841#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
893 842
894/* 843/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
895 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
896 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
897 */
898#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 844#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
899#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) 845#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
900 846
901/* 847/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
902 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
903 * CM_DIV_M7_DPLL_PER
904 */
905#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 848#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
906#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 849#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
907 850
908/* 851/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
909 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
910 * CM_DIV_M7_DPLL_PER
911 */
912#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 852#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
913#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) 853#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
914 854
915/* 855/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
916 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
917 * CM_DIV_M7_DPLL_PER
918 */
919#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 856#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
920#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) 857#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
921 858
922/* 859/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
923 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
924 * CM_DIV_M7_DPLL_PER
925 */
926#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 860#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
927#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) 861#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
928 862
@@ -934,8 +868,7 @@
934 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 868 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
935 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 869 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
936 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 870 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
937 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 871 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
938 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
939 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 872 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
940 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 873 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
941 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 874 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -944,30 +877,24 @@
944 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 877 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
945 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 878 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
946 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 879 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
947 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 880 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
948 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 881 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
949 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 882 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
950 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
951 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
952 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
953 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 883 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
954 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 884 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
955 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 885 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
956 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 886 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
957 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 887 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
958 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 888 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
959 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 889 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
960 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 890 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
961 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 891 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
962 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 892 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
963 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 893 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
964 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 894 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
965 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 895 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
966 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 896 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
967 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 897 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
968 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
969 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
970 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
971 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 898 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
972 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 899 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
973 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 900 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -983,166 +910,148 @@
983#define OMAP4430_IDLEST_SHIFT 16 910#define OMAP4430_IDLEST_SHIFT 16
984#define OMAP4430_IDLEST_MASK (0x3 << 16) 911#define OMAP4430_IDLEST_MASK (0x3 << 16)
985 912
986/* 913/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
987 * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
988 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
989 */
990#define OMAP4430_ISS_DYNDEP_SHIFT 9 914#define OMAP4430_ISS_DYNDEP_SHIFT 9
991#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) 915#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
992 916
993/* 917/*
994 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 918 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
995 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 919 * CM_TESLA_STATICDEP
996 */ 920 */
997#define OMAP4430_ISS_STATDEP_SHIFT 9 921#define OMAP4430_ISS_STATDEP_SHIFT 9
998#define OMAP4430_ISS_STATDEP_MASK (1 << 9) 922#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
999 923
1000/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ 924/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
1001#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 925#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
1002#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) 926#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
1003 927
1004/* 928/*
1005 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 929 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1006 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, 930 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
1007 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 931 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1008 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1009 */ 932 */
1010#define OMAP4430_IVAHD_STATDEP_SHIFT 2 933#define OMAP4430_IVAHD_STATDEP_SHIFT 2
1011#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) 934#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
1012 935
1013/* 936/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1014 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1015 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
1016 */
1017#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 937#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
1018#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) 938#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
1019 939
1020/* 940/*
1021 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 941 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
1022 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 942 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1023 * CM_TESLA_STATICDEP
1024 */ 943 */
1025#define OMAP4430_L3INIT_STATDEP_SHIFT 7 944#define OMAP4430_L3INIT_STATDEP_SHIFT 7
1026#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) 945#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
1027 946
1028/* 947/*
1029 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, 948 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1030 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 949 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1031 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1032 */ 950 */
1033#define OMAP4430_L3_1_DYNDEP_SHIFT 5 951#define OMAP4430_L3_1_DYNDEP_SHIFT 5
1034#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) 952#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
1035 953
1036/* 954/*
1037 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 955 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1038 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 956 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1039 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 957 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1040 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 958 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1041 */ 959 */
1042#define OMAP4430_L3_1_STATDEP_SHIFT 5 960#define OMAP4430_L3_1_STATDEP_SHIFT 5
1043#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) 961#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
1044 962
1045/* 963/*
1046 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, 964 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
1047 * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, 965 * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
1048 * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, 966 * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1049 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 967 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1050 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1051 */ 968 */
1052#define OMAP4430_L3_2_DYNDEP_SHIFT 6 969#define OMAP4430_L3_2_DYNDEP_SHIFT 6
1053#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) 970#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
1054 971
1055/* 972/*
1056 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 973 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1057 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 974 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1058 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 975 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1059 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 976 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1060 */ 977 */
1061#define OMAP4430_L3_2_STATDEP_SHIFT 6 978#define OMAP4430_L3_2_STATDEP_SHIFT 6
1062#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) 979#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
1063 980
1064/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ 981/* Used by CM_L3_1_DYNAMICDEP */
1065#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 982#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
1066#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) 983#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
1067 984
1068/* 985/*
1069 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 986 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1070 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 987 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1071 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1072 */ 988 */
1073#define OMAP4430_L4CFG_STATDEP_SHIFT 12 989#define OMAP4430_L4CFG_STATDEP_SHIFT 12
1074#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) 990#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
1075 991
1076/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 992/* Used by CM_L3_2_DYNAMICDEP */
1077#define OMAP4430_L4PER_DYNDEP_SHIFT 13 993#define OMAP4430_L4PER_DYNDEP_SHIFT 13
1078#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) 994#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
1079 995
1080/* 996/*
1081 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 997 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1082 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 998 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1083 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1084 */ 999 */
1085#define OMAP4430_L4PER_STATDEP_SHIFT 13 1000#define OMAP4430_L4PER_STATDEP_SHIFT 13
1086#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) 1001#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
1087 1002
1088/* 1003/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1089 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1090 * CM_L4PER_DYNAMICDEP_RESTORE
1091 */
1092#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1004#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
1093#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) 1005#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
1094 1006
1095/* 1007/*
1096 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1008 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1097 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE 1009 * CM_SDMA_STATICDEP
1098 */ 1010 */
1099#define OMAP4430_L4SEC_STATDEP_SHIFT 14 1011#define OMAP4430_L4SEC_STATDEP_SHIFT 14
1100#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) 1012#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
1101 1013
1102/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1014/* Used by CM_L4CFG_DYNAMICDEP */
1103#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1015#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
1104#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) 1016#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
1105 1017
1106/* 1018/*
1107 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1019 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1108 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1020 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1109 */ 1021 */
1110#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1022#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
1111#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) 1023#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
1112 1024
1113/* 1025/*
1114 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, 1026 * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1115 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1027 * CM_MPU_DYNAMICDEP
1116 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
1117 */ 1028 */
1118#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1029#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
1119#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) 1030#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
1120 1031
1121/* 1032/*
1122 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1033 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1123 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1034 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1124 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1035 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1125 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1036 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1126 */ 1037 */
1127#define OMAP4430_MEMIF_STATDEP_SHIFT 4 1038#define OMAP4430_MEMIF_STATDEP_SHIFT 4
1128#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) 1039#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
1129 1040
1130/* 1041/*
1131 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1042 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1132 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1043 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1133 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1044 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1134 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1045 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1135 * CM_SSC_MODFREQDIV_DPLL_USB
1136 */ 1046 */
1137#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1047#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
1138#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) 1048#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1139 1049
1140/* 1050/*
1141 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1051 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1142 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1052 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1143 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1053 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1144 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1054 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1145 * CM_SSC_MODFREQDIV_DPLL_USB
1146 */ 1055 */
1147#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1056#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
1148#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) 1057#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
@@ -1155,8 +1064,7 @@
1155 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 1064 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1156 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 1065 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1157 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1066 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1158 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 1067 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
1159 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
1160 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 1068 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1161 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 1069 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1162 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 1070 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -1165,30 +1073,24 @@
1165 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1073 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1166 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1074 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1167 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1075 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1168 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1076 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1169 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 1077 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
1170 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 1078 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
1171 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
1172 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
1173 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
1174 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 1079 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1175 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 1080 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1176 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 1081 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1177 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 1082 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1178 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 1083 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1179 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 1084 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1180 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1085 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1181 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1086 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1182 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1087 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
1183 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 1088 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
1184 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 1089 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
1185 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 1090 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
1186 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 1091 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
1187 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 1092 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
1188 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 1093 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1189 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
1190 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1191 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1192 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 1094 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1193 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 1095 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1194 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 1096 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -1221,11 +1123,9 @@
1221#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) 1123#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1222 1124
1223/* 1125/*
1224 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1126 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1225 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1127 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1226 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1128 * CM_WKUP_GPIO1_CLKCTRL
1227 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1228 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
1229 */ 1129 */
1230#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1130#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
1231#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) 1131#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
@@ -1254,23 +1154,23 @@
1254#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1154#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
1255#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) 1155#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
1256 1156
1257/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1157/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1258#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1158#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
1259#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) 1159#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
1260 1160
1261/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1161/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1262#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1162#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1263#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) 1163#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1264 1164
1265/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1165/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1266#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1166#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1267#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) 1167#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1268 1168
1269/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1169/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1270#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1170#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1271#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) 1171#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1272 1172
1273/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1173/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1274#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1174#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1275#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) 1175#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1276 1176
@@ -1306,27 +1206,27 @@
1306#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1206#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
1307#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) 1207#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
1308 1208
1309/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1209/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1310#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1210#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1311#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) 1211#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1312 1212
1313/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1213/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1314#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1214#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1315#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) 1215#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1316 1216
1317/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1217/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1318#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1218#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1319#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) 1219#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1320 1220
1321/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1221/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1322#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1222#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1323#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) 1223#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1324 1224
1325/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1225/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1326#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1226#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1327#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) 1227#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1328 1228
1329/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1229/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1330#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1230#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1331#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) 1231#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1332 1232
@@ -1374,7 +1274,7 @@
1374#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1274#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
1375#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) 1275#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
1376 1276
1377/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ 1277/* Used by CM_DYN_DEP_PRESCAL */
1378#define OMAP4430_PRESCAL_SHIFT 0 1278#define OMAP4430_PRESCAL_SHIFT 0
1379#define OMAP4430_PRESCAL_MASK (0x3f << 0) 1279#define OMAP4430_PRESCAL_MASK (0x3f << 0)
1380 1280
@@ -1382,10 +1282,7 @@
1382#define OMAP4430_R_RTL_SHIFT 11 1282#define OMAP4430_R_RTL_SHIFT 11
1383#define OMAP4430_R_RTL_MASK (0x1f << 11) 1283#define OMAP4430_R_RTL_MASK (0x1f << 11)
1384 1284
1385/* 1285/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
1386 * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1387 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
1388 */
1389#define OMAP4430_SAR_MODE_SHIFT 4 1286#define OMAP4430_SAR_MODE_SHIFT 4
1390#define OMAP4430_SAR_MODE_MASK (1 << 4) 1287#define OMAP4430_SAR_MODE_MASK (1 << 4)
1391 1288
@@ -1397,7 +1294,7 @@
1397#define OMAP4430_SCHEME_SHIFT 30 1294#define OMAP4430_SCHEME_SHIFT 30
1398#define OMAP4430_SCHEME_MASK (0x3 << 30) 1295#define OMAP4430_SCHEME_MASK (0x3 << 30)
1399 1296
1400/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1297/* Used by CM_L4CFG_DYNAMICDEP */
1401#define OMAP4430_SDMA_DYNDEP_SHIFT 11 1298#define OMAP4430_SDMA_DYNDEP_SHIFT 11
1402#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) 1299#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
1403 1300
@@ -1417,10 +1314,10 @@
1417 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1314 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1418 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1315 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1419 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1316 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1420 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1317 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1421 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1318 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
1422 * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, 1319 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1423 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL 1320 * CM_TESLA_TESLA_CLKCTRL
1424 */ 1321 */
1425#define OMAP4430_STBYST_SHIFT 18 1322#define OMAP4430_STBYST_SHIFT 18
1426#define OMAP4430_STBYST_MASK (1 << 18) 1323#define OMAP4430_STBYST_MASK (1 << 18)
@@ -1438,17 +1335,13 @@
1438#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) 1335#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1439 1336
1440/* 1337/*
1441 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 1338 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
1442 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 1339 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1443 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1444 */ 1340 */
1445#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1341#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
1446#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) 1342#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
1447 1343
1448/* 1344/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
1449 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
1450 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
1451 */
1452#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1345#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
1453#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) 1346#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
1454 1347
@@ -1457,30 +1350,24 @@
1457#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) 1350#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
1458 1351
1459/* 1352/*
1460 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 1353 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
1461 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 1354 * CM_DIV_M4_DPLL_PER
1462 */ 1355 */
1463#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1356#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
1464#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) 1357#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
1465 1358
1466/* 1359/*
1467 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 1360 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1468 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 1361 * CM_DIV_M5_DPLL_PER
1469 */ 1362 */
1470#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1363#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
1471#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) 1364#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
1472 1365
1473/* 1366/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1474 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
1475 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
1476 */
1477#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1367#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
1478#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) 1368#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
1479 1369
1480/* 1370/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1481 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
1482 * CM_DIV_M7_DPLL_PER
1483 */
1484#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1371#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
1485#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) 1372#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
1486 1373
@@ -1496,7 +1383,7 @@
1496#define OMAP4430_SYS_CLKSEL_SHIFT 0 1383#define OMAP4430_SYS_CLKSEL_SHIFT 0
1497#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) 1384#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
1498 1385
1499/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1386/* Used by CM_L4CFG_DYNAMICDEP */
1500#define OMAP4430_TESLA_DYNDEP_SHIFT 1 1387#define OMAP4430_TESLA_DYNDEP_SHIFT 1
1501#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) 1388#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
1502 1389
@@ -1505,11 +1392,9 @@
1505#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) 1392#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
1506 1393
1507/* 1394/*
1508 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, 1395 * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1509 * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, 1396 * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1510 * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1397 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1511 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1512 * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1513 */ 1398 */
1514#define OMAP4430_WINDOWSIZE_SHIFT 24 1399#define OMAP4430_WINDOWSIZE_SHIFT 24
1515#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) 1400#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index e2d7a56b2ad6..1bc00dc4876c 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP44xx CM1 instance offset macros 2 * OMAP44xx CM1 instance offset macros
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -41,9 +41,9 @@
41#define OMAP4430_CM1_INSTR_INST 0x0f00 41#define OMAP4430_CM1_INSTR_INST 0x0f00
42 42
43/* CM1 clockdomain register offsets (from instance start) */ 43/* CM1 clockdomain register offsets (from instance start) */
44#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 44#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
45#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 45#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
46#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 46#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
47 47
48/* CM1 */ 48/* CM1 */
49 49
@@ -82,8 +82,8 @@
82#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 82#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
83#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 83#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
84#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 84#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
85#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c 85#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
86#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 86#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
87#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 87#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
88#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 88#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
89#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 89#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
@@ -98,8 +98,8 @@
98#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 98#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
99#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 99#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
101#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c 101#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
102#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 102#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
@@ -116,8 +116,8 @@
116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
119#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc 119#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
120#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 120#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
@@ -134,8 +134,8 @@
134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
137#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c 137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
138#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
@@ -154,8 +154,8 @@
154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
157#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 157#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
158#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 158#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
@@ -217,42 +217,6 @@
217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
219 219
220/* CM1.RESTORE_CM1 register offsets */
221#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
222#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
223#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
224#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
225#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
226#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
227#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
228#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
229#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
230#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
231#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
232#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
233#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
234#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
235#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
236#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
237#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
238#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
239#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
240#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
241#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
242#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
243#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
244#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
245#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
246#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
247#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
248#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
249#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
250#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
251#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
252#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
253#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
254#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
255
256/* Function prototypes */ 220/* Function prototypes */
257extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); 221extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
258extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); 222extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index aa4745044065..b9de72da1a8e 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP44xx CM2 instance offset macros 2 * OMAP44xx CM2 instance offset macros
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -40,9 +40,9 @@
40#define OMAP4430_CM2_CAM_INST 0x1000 40#define OMAP4430_CM2_CAM_INST 0x1000
41#define OMAP4430_CM2_DSS_INST 0x1100 41#define OMAP4430_CM2_DSS_INST 0x1100
42#define OMAP4430_CM2_GFX_INST 0x1200 42#define OMAP4430_CM2_GFX_INST 0x1200
43#define OMAP4430_CM2_L3INIT_INST 0x1300 43#define OMAP4430_CM2_L3INIT_INST 0x1300
44#define OMAP4430_CM2_L4PER_INST 0x1400 44#define OMAP4430_CM2_L4PER_INST 0x1400
45#define OMAP4430_CM2_CEFUSE_INST 0x1600 45#define OMAP4430_CM2_CEFUSE_INST 0x1600
46#define OMAP4430_CM2_RESTORE_INST 0x1e00 46#define OMAP4430_CM2_RESTORE_INST 0x1e00
47#define OMAP4430_CM2_INSTR_INST 0x1f00 47#define OMAP4430_CM2_INSTR_INST 0x1f00
48 48
@@ -65,7 +65,6 @@
65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
67 67
68
69/* CM2 */ 68/* CM2 */
70 69
71/* CM2.OCP_SOCKET_CM2 register offsets */ 70/* CM2.OCP_SOCKET_CM2 register offsets */
@@ -121,8 +120,8 @@
121#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) 120#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
122#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 121#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
123#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) 122#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
124#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c 123#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
125#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) 124#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
126#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 125#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
127#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) 126#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
128#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 127#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
@@ -135,8 +134,8 @@
135#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) 134#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
136#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
137#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) 136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
138#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac 137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
139#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) 138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
140#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 139#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
141#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) 140#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
142#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 141#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
@@ -151,8 +150,8 @@
151#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) 150#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
152#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 151#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
153#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) 152#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
154#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 153#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
155#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) 154#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
156 155
157/* CM2.ALWAYS_ON_CM2 register offsets */ 156/* CM2.ALWAYS_ON_CM2 register offsets */
158#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 157#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
@@ -227,8 +226,8 @@
227#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) 226#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
228#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 227#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
229#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) 228#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
230#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528 229#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
231#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) 230#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
232#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 231#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
233#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) 232#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
234#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 233#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
@@ -450,56 +449,6 @@
450#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 449#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
451#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 450#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
452 451
453/* CM2.RESTORE_CM2 register offsets */
454#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
455#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
456#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
457#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
458#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
459#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
460#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
461#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
462#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
463#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
464#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
465#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
466#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
467#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
468#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
469#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
470#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
471#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
472#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
473#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
474#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
475#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
476#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
477#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
478#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
479#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
480#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
481#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
482#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
483#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
484#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
485#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
486#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
487#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
488#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
489#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
490#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
491#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
492#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
493#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
494#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
495#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
496#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
497#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
498#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
499#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
500#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
501#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
502
503/* Function prototypes */ 452/* Function prototypes */
504extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); 453extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
505extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); 454extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 94ccf464677b..bcb0c5817167 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -20,36 +20,15 @@
20 * 20 *
21 */ 21 */
22 22
23#include <linux/i2c.h>
24#include <linux/i2c/twl.h>
25
26#include <linux/gpio.h> 23#include <linux/gpio.h>
27#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
28#include <linux/spi/ads7846.h> 25#include <linux/spi/ads7846.h>
29 26
30#include <plat/i2c.h>
31#include <plat/mcspi.h> 27#include <plat/mcspi.h>
32#include <plat/nand.h> 28#include <plat/nand.h>
33 29
34#include "common-board-devices.h" 30#include "common-board-devices.h"
35 31
36static struct i2c_board_info __initdata pmic_i2c_board_info = {
37 .addr = 0x48,
38 .flags = I2C_CLIENT_WAKE,
39};
40
41void __init omap_pmic_init(int bus, u32 clkrate,
42 const char *pmic_type, int pmic_irq,
43 struct twl4030_platform_data *pmic_data)
44{
45 strncpy(pmic_i2c_board_info.type, pmic_type,
46 sizeof(pmic_i2c_board_info.type));
47 pmic_i2c_board_info.irq = pmic_irq;
48 pmic_i2c_board_info.platform_data = pmic_data;
49
50 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
51}
52
53#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ 32#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
54 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 33 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
55static struct omap2_mcspi_device_config ads7846_mcspi_config = { 34static struct omap2_mcspi_device_config ads7846_mcspi_config = {
@@ -115,9 +94,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
115#endif 94#endif
116 95
117#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) 96#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
118static struct omap_nand_platform_data nand_data = { 97static struct omap_nand_platform_data nand_data;
119 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
120};
121 98
122void __init omap_nand_flash_init(int options, struct mtd_partition *parts, 99void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
123 int nr_parts) 100 int nr_parts)
@@ -148,7 +125,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
148 nand_data.cs = nandcs; 125 nand_data.cs = nandcs;
149 nand_data.parts = parts; 126 nand_data.parts = parts;
150 nand_data.nr_parts = nr_parts; 127 nand_data.nr_parts = nr_parts;
151 nand_data.options = options; 128 nand_data.devsize = options;
152 129
153 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); 130 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
154 if (gpmc_nand_init(&nand_data) < 0) 131 if (gpmc_nand_init(&nand_data) < 0)
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 679719051df5..a0b4a42836ab 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -1,33 +1,11 @@
1#ifndef __OMAP_COMMON_BOARD_DEVICES__ 1#ifndef __OMAP_COMMON_BOARD_DEVICES__
2#define __OMAP_COMMON_BOARD_DEVICES__ 2#define __OMAP_COMMON_BOARD_DEVICES__
3 3
4#include "twl-common.h"
5
4#define NAND_BLOCK_SIZE SZ_128K 6#define NAND_BLOCK_SIZE SZ_128K
5 7
6struct twl4030_platform_data;
7struct mtd_partition; 8struct mtd_partition;
8
9void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
10 struct twl4030_platform_data *pmic_data);
11
12static inline void omap2_pmic_init(const char *pmic_type,
13 struct twl4030_platform_data *pmic_data)
14{
15 omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
16}
17
18static inline void omap3_pmic_init(const char *pmic_type,
19 struct twl4030_platform_data *pmic_data)
20{
21 omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
22}
23
24static inline void omap4_pmic_init(const char *pmic_type,
25 struct twl4030_platform_data *pmic_data)
26{
27 /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
28 omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
29}
30
31struct ads7846_platform_data; 9struct ads7846_platform_data;
32 10
33void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, 11void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index c1791d08ae56..8ad210bda9a9 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -20,8 +20,6 @@
20#include <plat/board.h> 20#include <plat/board.h>
21#include <plat/gpmc.h> 21#include <plat/gpmc.h>
22 22
23static struct omap_nand_platform_data *gpmc_nand_data;
24
25static struct resource gpmc_nand_resource = { 23static struct resource gpmc_nand_resource = {
26 .flags = IORESOURCE_MEM, 24 .flags = IORESOURCE_MEM,
27}; 25};
@@ -33,7 +31,7 @@ static struct platform_device gpmc_nand_device = {
33 .resource = &gpmc_nand_resource, 31 .resource = &gpmc_nand_resource,
34}; 32};
35 33
36static int omap2_nand_gpmc_retime(void) 34static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
37{ 35{
38 struct gpmc_timings t; 36 struct gpmc_timings t;
39 int err; 37 int err;
@@ -83,13 +81,11 @@ static int omap2_nand_gpmc_retime(void)
83 return 0; 81 return 0;
84} 82}
85 83
86int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) 84int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
87{ 85{
88 int err = 0; 86 int err = 0;
89 struct device *dev = &gpmc_nand_device.dev; 87 struct device *dev = &gpmc_nand_device.dev;
90 88
91 gpmc_nand_data = _nand_data;
92 gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime;
93 gpmc_nand_device.dev.platform_data = gpmc_nand_data; 89 gpmc_nand_device.dev.platform_data = gpmc_nand_data;
94 90
95 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, 91 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
@@ -100,7 +96,7 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
100 } 96 }
101 97
102 /* Set timings in GPMC */ 98 /* Set timings in GPMC */
103 err = omap2_nand_gpmc_retime(); 99 err = omap2_nand_gpmc_retime(gpmc_nand_data);
104 if (err < 0) { 100 if (err < 0) {
105 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 101 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
106 return err; 102 return err;
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 79c478c4cb1c..ace99944e96f 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -21,9 +21,19 @@
21 21
22#include <plat/cpu.h> 22#include <plat/cpu.h>
23#include <plat/i2c.h> 23#include <plat/i2c.h>
24#include <plat/common.h>
25#include <plat/omap_hwmod.h>
24 26
25#include "mux.h" 27#include "mux.h"
26 28
29/* In register I2C_CON, Bit 15 is the I2C enable bit */
30#define I2C_EN BIT(15)
31#define OMAP2_I2C_CON_OFFSET 0x24
32#define OMAP4_I2C_CON_OFFSET 0xA4
33
34/* Maximum microseconds to wait for OMAP module to softreset */
35#define MAX_MODULE_SOFTRESET_WAIT 10000
36
27void __init omap2_i2c_mux_pins(int bus_id) 37void __init omap2_i2c_mux_pins(int bus_id)
28{ 38{
29 char mux_name[sizeof("i2c2_scl.i2c2_scl")]; 39 char mux_name[sizeof("i2c2_scl.i2c2_scl")];
@@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
37 sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); 47 sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
38 omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); 48 omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
39} 49}
50
51/**
52 * omap_i2c_reset - reset the omap i2c module.
53 * @oh: struct omap_hwmod *
54 *
55 * The i2c moudle in omap2, omap3 had a special sequence to reset. The
56 * sequence is:
57 * - Disable the I2C.
58 * - Write to SOFTRESET bit.
59 * - Enable the I2C.
60 * - Poll on the RESETDONE bit.
61 * The sequence is implemented in below function. This is called for 2420,
62 * 2430 and omap3.
63 */
64int omap_i2c_reset(struct omap_hwmod *oh)
65{
66 u32 v;
67 u16 i2c_con;
68 int c = 0;
69
70 if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
71 i2c_con = OMAP4_I2C_CON_OFFSET;
72 } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
73 i2c_con = OMAP2_I2C_CON_OFFSET;
74 } else {
75 WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
76 oh->name);
77 return -EINVAL;
78 }
79
80 /* Disable I2C */
81 v = omap_hwmod_read(oh, i2c_con);
82 v &= ~I2C_EN;
83 omap_hwmod_write(v, oh, i2c_con);
84
85 /* Write to the SOFTRESET bit */
86 omap_hwmod_softreset(oh);
87
88 /* Enable I2C */
89 v = omap_hwmod_read(oh, i2c_con);
90 v |= I2C_EN;
91 omap_hwmod_write(v, oh, i2c_con);
92
93 /* Poll on RESETDONE bit */
94 omap_test_timeout((omap_hwmod_read(oh,
95 oh->class->sysc->syss_offs)
96 & SYSS_RESETDONE_MASK),
97 MAX_MODULE_SOFTRESET_WAIT, c);
98
99 if (c == MAX_MODULE_SOFTRESET_WAIT)
100 pr_warning("%s: %s: softreset failed (waited %d usec)\n",
101 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
102 else
103 pr_debug("%s: %s: softreset in %d usec\n", __func__,
104 oh->name, c);
105
106 return 0;
107}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 441e79d043a7..2ce1ce6fb4db 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -333,23 +333,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
334} 334}
335 335
336/* See irq.c, omap4-common.c and entry-macro.S */
336void __iomem *omap_irq_base; 337void __iomem *omap_irq_base;
337 338
338/*
339 * Initialize asm_irq_base for entry-macro.S
340 */
341static inline void omap_irq_base_init(void)
342{
343 if (cpu_is_omap24xx())
344 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
345 else if (cpu_is_omap34xx())
346 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
347 else if (cpu_is_omap44xx())
348 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
349 else
350 pr_err("Could not initialize omap_irq_base\n");
351}
352
353void __init omap2_init_common_infrastructure(void) 339void __init omap2_init_common_infrastructure(void)
354{ 340{
355 u8 postsetup_state; 341 u8 postsetup_state;
@@ -422,7 +408,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
422 _omap2_init_reprogram_sdrc(); 408 _omap2_init_reprogram_sdrc();
423 } 409 }
424 410
425 omap_irq_base_init();
426} 411}
427 412
428/* 413/*
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3af2b7a1045e..3a12f7586a4c 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -141,25 +141,20 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
141 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 141 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
142} 142}
143 143
144void __init omap_init_irq(void) 144static void __init omap_init_irq(u32 base, int nr_irqs)
145{ 145{
146 unsigned long nr_of_irqs = 0; 146 unsigned long nr_of_irqs = 0;
147 unsigned int nr_banks = 0; 147 unsigned int nr_banks = 0;
148 int i, j; 148 int i, j;
149 149
150 omap_irq_base = ioremap(base, SZ_4K);
151 if (WARN_ON(!omap_irq_base))
152 return;
153
150 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 154 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
151 unsigned long base = 0;
152 struct omap_irq_bank *bank = irq_banks + i; 155 struct omap_irq_bank *bank = irq_banks + i;
153 156
154 if (cpu_is_omap24xx()) 157 bank->nr_irqs = nr_irqs;
155 base = OMAP24XX_IC_BASE;
156 else if (cpu_is_omap34xx())
157 base = OMAP34XX_IC_BASE;
158
159 BUG_ON(!base);
160
161 if (cpu_is_ti816x())
162 bank->nr_irqs = 128;
163 158
164 /* Static mapping, never released */ 159 /* Static mapping, never released */
165 bank->base_reg = ioremap(base, SZ_4K); 160 bank->base_reg = ioremap(base, SZ_4K);
@@ -181,6 +176,21 @@ void __init omap_init_irq(void)
181 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); 176 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
182} 177}
183 178
179void __init omap2_init_irq(void)
180{
181 omap_init_irq(OMAP24XX_IC_BASE, 96);
182}
183
184void __init omap3_init_irq(void)
185{
186 omap_init_irq(OMAP34XX_IC_BASE, 96);
187}
188
189void __init ti816x_init_irq(void)
190{
191 omap_init_irq(OMAP34XX_IC_BASE, 128);
192}
193
184#ifdef CONFIG_ARCH_OMAP3 194#ifdef CONFIG_ARCH_OMAP3
185static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; 195static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
186 196
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 9ef8c29dd817..35ac3e5f6e94 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -19,6 +19,8 @@
19#include <asm/hardware/gic.h> 19#include <asm/hardware/gic.h>
20#include <asm/hardware/cache-l2x0.h> 20#include <asm/hardware/cache-l2x0.h>
21 21
22#include <plat/irqs.h>
23
22#include <mach/hardware.h> 24#include <mach/hardware.h>
23#include <mach/omap4-common.h> 25#include <mach/omap4-common.h>
24 26
@@ -31,17 +33,15 @@ void __iomem *gic_dist_base_addr;
31 33
32void __init gic_init_irq(void) 34void __init gic_init_irq(void)
33{ 35{
34 void __iomem *gic_cpu_base;
35
36 /* Static mapping, never released */ 36 /* Static mapping, never released */
37 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); 37 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
38 BUG_ON(!gic_dist_base_addr); 38 BUG_ON(!gic_dist_base_addr);
39 39
40 /* Static mapping, never released */ 40 /* Static mapping, never released */
41 gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); 41 omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
42 BUG_ON(!gic_cpu_base); 42 BUG_ON(!omap_irq_base);
43 43
44 gic_init(0, 29, gic_dist_base_addr, gic_cpu_base); 44 gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
45} 45}
46 46
47#ifdef CONFIG_CACHE_L2X0 47#ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 293fa6cd50e1..02b6016393a8 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,6 +2,7 @@
2 * omap_hwmod implementation for OMAP2/3/4 2 * omap_hwmod implementation for OMAP2/3/4
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc.
5 * 6 *
6 * Paul Walmsley, Benoît Cousson, Kevin Hilman 7 * Paul Walmsley, Benoît Cousson, Kevin Hilman
7 * 8 *
@@ -387,11 +388,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
387 */ 388 */
388static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) 389static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
389{ 390{
390 u32 wakeup_mask;
391
392 if (!oh->class->sysc || 391 if (!oh->class->sysc ||
393 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || 392 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
394 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) 393 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
394 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
395 return -EINVAL; 395 return -EINVAL;
396 396
397 if (!oh->class->sysc->sysc_fields) { 397 if (!oh->class->sysc->sysc_fields) {
@@ -399,12 +399,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
399 return -EINVAL; 399 return -EINVAL;
400 } 400 }
401 401
402 wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); 402 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
403 403 *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
404 *v |= wakeup_mask;
405 404
406 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) 405 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
407 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); 406 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
407 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
408 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
408 409
409 /* XXX test pwrdm_get_wken for this hwmod's subsystem */ 410 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
410 411
@@ -422,11 +423,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
422 */ 423 */
423static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) 424static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
424{ 425{
425 u32 wakeup_mask;
426
427 if (!oh->class->sysc || 426 if (!oh->class->sysc ||
428 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || 427 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
429 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) 428 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
429 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
430 return -EINVAL; 430 return -EINVAL;
431 431
432 if (!oh->class->sysc->sysc_fields) { 432 if (!oh->class->sysc->sysc_fields) {
@@ -434,12 +434,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
434 return -EINVAL; 434 return -EINVAL;
435 } 435 }
436 436
437 wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); 437 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
438 438 *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
439 *v &= ~wakeup_mask;
440 439
441 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) 440 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
442 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); 441 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
442 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
443 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
443 444
444 /* XXX test pwrdm_get_wken for this hwmod's subsystem */ 445 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
445 446
@@ -678,6 +679,75 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
678} 679}
679 680
680/** 681/**
682 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
683 * @oh: struct omap_hwmod *oh
684 *
685 * Count and return the number of MPU IRQs associated with the hwmod
686 * @oh. Used to allocate struct resource data. Returns 0 if @oh is
687 * NULL.
688 */
689static int _count_mpu_irqs(struct omap_hwmod *oh)
690{
691 struct omap_hwmod_irq_info *ohii;
692 int i = 0;
693
694 if (!oh || !oh->mpu_irqs)
695 return 0;
696
697 do {
698 ohii = &oh->mpu_irqs[i++];
699 } while (ohii->irq != -1);
700
701 return i;
702}
703
704/**
705 * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
706 * @oh: struct omap_hwmod *oh
707 *
708 * Count and return the number of SDMA request lines associated with
709 * the hwmod @oh. Used to allocate struct resource data. Returns 0
710 * if @oh is NULL.
711 */
712static int _count_sdma_reqs(struct omap_hwmod *oh)
713{
714 struct omap_hwmod_dma_info *ohdi;
715 int i = 0;
716
717 if (!oh || !oh->sdma_reqs)
718 return 0;
719
720 do {
721 ohdi = &oh->sdma_reqs[i++];
722 } while (ohdi->dma_req != -1);
723
724 return i;
725}
726
727/**
728 * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
729 * @oh: struct omap_hwmod *oh
730 *
731 * Count and return the number of address space ranges associated with
732 * the hwmod @oh. Used to allocate struct resource data. Returns 0
733 * if @oh is NULL.
734 */
735static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
736{
737 struct omap_hwmod_addr_space *mem;
738 int i = 0;
739
740 if (!os || !os->addr)
741 return 0;
742
743 do {
744 mem = &os->addr[i++];
745 } while (mem->pa_start != mem->pa_end);
746
747 return i;
748}
749
750/**
681 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use 751 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
682 * @oh: struct omap_hwmod * 752 * @oh: struct omap_hwmod *
683 * 753 *
@@ -722,8 +792,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
722{ 792{
723 struct omap_hwmod_ocp_if *os; 793 struct omap_hwmod_ocp_if *os;
724 struct omap_hwmod_addr_space *mem; 794 struct omap_hwmod_addr_space *mem;
725 int i; 795 int i = 0, found = 0;
726 int found = 0;
727 void __iomem *va_start; 796 void __iomem *va_start;
728 797
729 if (!oh || oh->slaves_cnt == 0) 798 if (!oh || oh->slaves_cnt == 0)
@@ -731,12 +800,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
731 800
732 os = oh->slaves[index]; 801 os = oh->slaves[index];
733 802
734 for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { 803 if (!os->addr)
735 if (mem->flags & ADDR_TYPE_RT) { 804 return NULL;
805
806 do {
807 mem = &os->addr[i++];
808 if (mem->flags & ADDR_TYPE_RT)
736 found = 1; 809 found = 1;
737 break; 810 } while (!found && mem->pa_start != mem->pa_end);
738 }
739 }
740 811
741 if (found) { 812 if (found) {
742 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); 813 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
@@ -781,8 +852,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
781 } 852 }
782 853
783 if (sf & SYSC_HAS_MIDLEMODE) { 854 if (sf & SYSC_HAS_MIDLEMODE) {
784 idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? 855 if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
785 HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; 856 idlemode = HWMOD_IDLEMODE_NO;
857 } else {
858 if (sf & SYSC_HAS_ENAWAKEUP)
859 _enable_wakeup(oh, &v);
860 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
861 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
862 else
863 idlemode = HWMOD_IDLEMODE_SMART;
864 }
786 _set_master_standbymode(oh, idlemode, &v); 865 _set_master_standbymode(oh, idlemode, &v);
787 } 866 }
788 867
@@ -840,8 +919,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
840 } 919 }
841 920
842 if (sf & SYSC_HAS_MIDLEMODE) { 921 if (sf & SYSC_HAS_MIDLEMODE) {
843 idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? 922 if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
844 HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; 923 idlemode = HWMOD_IDLEMODE_FORCE;
924 } else {
925 if (sf & SYSC_HAS_ENAWAKEUP)
926 _enable_wakeup(oh, &v);
927 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
928 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
929 else
930 idlemode = HWMOD_IDLEMODE_SMART;
931 }
845 _set_master_standbymode(oh, idlemode, &v); 932 _set_master_standbymode(oh, idlemode, &v);
846 } 933 }
847 934
@@ -928,6 +1015,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
928 1015
929 if (!ret) 1016 if (!ret)
930 oh->_state = _HWMOD_STATE_CLKS_INITED; 1017 oh->_state = _HWMOD_STATE_CLKS_INITED;
1018 else
1019 pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
931 1020
932 return ret; 1021 return ret;
933} 1022}
@@ -1224,6 +1313,8 @@ static int _enable(struct omap_hwmod *oh)
1224{ 1313{
1225 int r; 1314 int r;
1226 1315
1316 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1317
1227 if (oh->_state != _HWMOD_STATE_INITIALIZED && 1318 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1228 oh->_state != _HWMOD_STATE_IDLE && 1319 oh->_state != _HWMOD_STATE_IDLE &&
1229 oh->_state != _HWMOD_STATE_DISABLED) { 1320 oh->_state != _HWMOD_STATE_DISABLED) {
@@ -1232,17 +1323,6 @@ static int _enable(struct omap_hwmod *oh)
1232 return -EINVAL; 1323 return -EINVAL;
1233 } 1324 }
1234 1325
1235 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1236
1237 /*
1238 * If an IP contains only one HW reset line, then de-assert it in order
1239 * to allow to enable the clocks. Otherwise the PRCM will return
1240 * Intransition status, and the init will failed.
1241 */
1242 if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
1243 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
1244 _deassert_hardreset(oh, oh->rst_lines[0].name);
1245
1246 /* Mux pins for device runtime if populated */ 1326 /* Mux pins for device runtime if populated */
1247 if (oh->mux && (!oh->mux->enabled || 1327 if (oh->mux && (!oh->mux->enabled ||
1248 ((oh->_state == _HWMOD_STATE_IDLE) && 1328 ((oh->_state == _HWMOD_STATE_IDLE) &&
@@ -1252,20 +1332,31 @@ static int _enable(struct omap_hwmod *oh)
1252 _add_initiator_dep(oh, mpu_oh); 1332 _add_initiator_dep(oh, mpu_oh);
1253 _enable_clocks(oh); 1333 _enable_clocks(oh);
1254 1334
1255 r = _wait_target_ready(oh); 1335 /*
1256 if (!r) { 1336 * If an IP contains only one HW reset line, then de-assert it in order
1257 oh->_state = _HWMOD_STATE_ENABLED; 1337 * to allow the module state transition. Otherwise the PRCM will return
1338 * Intransition status, and the init will failed.
1339 */
1340 if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
1341 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
1342 _deassert_hardreset(oh, oh->rst_lines[0].name);
1258 1343
1259 /* Access the sysconfig only if the target is ready */ 1344 r = _wait_target_ready(oh);
1260 if (oh->class->sysc) { 1345 if (r) {
1261 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1262 _update_sysc_cache(oh);
1263 _enable_sysc(oh);
1264 }
1265 } else {
1266 _disable_clocks(oh);
1267 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", 1346 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
1268 oh->name, r); 1347 oh->name, r);
1348 _disable_clocks(oh);
1349
1350 return r;
1351 }
1352
1353 oh->_state = _HWMOD_STATE_ENABLED;
1354
1355 /* Access the sysconfig only if the target is ready */
1356 if (oh->class->sysc) {
1357 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1358 _update_sysc_cache(oh);
1359 _enable_sysc(oh);
1269 } 1360 }
1270 1361
1271 return r; 1362 return r;
@@ -1281,14 +1372,14 @@ static int _enable(struct omap_hwmod *oh)
1281 */ 1372 */
1282static int _idle(struct omap_hwmod *oh) 1373static int _idle(struct omap_hwmod *oh)
1283{ 1374{
1375 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1376
1284 if (oh->_state != _HWMOD_STATE_ENABLED) { 1377 if (oh->_state != _HWMOD_STATE_ENABLED) {
1285 WARN(1, "omap_hwmod: %s: idle state can only be entered from " 1378 WARN(1, "omap_hwmod: %s: idle state can only be entered from "
1286 "enabled state\n", oh->name); 1379 "enabled state\n", oh->name);
1287 return -EINVAL; 1380 return -EINVAL;
1288 } 1381 }
1289 1382
1290 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1291
1292 if (oh->class->sysc) 1383 if (oh->class->sysc)
1293 _idle_sysc(oh); 1384 _idle_sysc(oh);
1294 _del_initiator_dep(oh, mpu_oh); 1385 _del_initiator_dep(oh, mpu_oh);
@@ -1374,15 +1465,11 @@ static int _shutdown(struct omap_hwmod *oh)
1374 } 1465 }
1375 } 1466 }
1376 1467
1377 if (oh->class->sysc) 1468 if (oh->class->sysc) {
1469 if (oh->_state == _HWMOD_STATE_IDLE)
1470 _enable(oh);
1378 _shutdown_sysc(oh); 1471 _shutdown_sysc(oh);
1379 1472 }
1380 /*
1381 * If an IP contains only one HW reset line, then assert it
1382 * before disabling the clocks and shutting down the IP.
1383 */
1384 if (oh->rst_lines_cnt == 1)
1385 _assert_hardreset(oh, oh->rst_lines[0].name);
1386 1473
1387 /* clocks and deps are already disabled in idle */ 1474 /* clocks and deps are already disabled in idle */
1388 if (oh->_state == _HWMOD_STATE_ENABLED) { 1475 if (oh->_state == _HWMOD_STATE_ENABLED) {
@@ -1392,6 +1479,13 @@ static int _shutdown(struct omap_hwmod *oh)
1392 } 1479 }
1393 /* XXX Should this code also force-disable the optional clocks? */ 1480 /* XXX Should this code also force-disable the optional clocks? */
1394 1481
1482 /*
1483 * If an IP contains only one HW reset line, then assert it
1484 * after disabling the clocks and before shutting down the IP.
1485 */
1486 if (oh->rst_lines_cnt == 1)
1487 _assert_hardreset(oh, oh->rst_lines[0].name);
1488
1395 /* Mux pins to safe mode or use populated off mode values */ 1489 /* Mux pins to safe mode or use populated off mode values */
1396 if (oh->mux) 1490 if (oh->mux)
1397 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); 1491 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
@@ -1562,6 +1656,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
1562} 1656}
1563 1657
1564/** 1658/**
1659 * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
1660 * @oh: struct omap_hwmod *
1661 *
1662 * This is a public function exposed to drivers. Some drivers may need to do
1663 * some settings before and after resetting the device. Those drivers after
1664 * doing the necessary settings could use this function to start a reset by
1665 * setting the SYSCONFIG.SOFTRESET bit.
1666 */
1667int omap_hwmod_softreset(struct omap_hwmod *oh)
1668{
1669 u32 v;
1670 int ret;
1671
1672 if (!oh || !(oh->_sysc_cache))
1673 return -EINVAL;
1674
1675 v = oh->_sysc_cache;
1676 ret = _set_softreset(oh, &v);
1677 if (ret)
1678 goto error;
1679 _write_sysconfig(v, oh);
1680
1681error:
1682 return ret;
1683}
1684
1685/**
1565 * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode 1686 * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
1566 * @oh: struct omap_hwmod * 1687 * @oh: struct omap_hwmod *
1567 * @idlemode: SIDLEMODE field bits (shifted to bit 0) 1688 * @idlemode: SIDLEMODE field bits (shifted to bit 0)
@@ -1685,9 +1806,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
1685 return 0; 1806 return 0;
1686 1807
1687 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); 1808 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
1688 if (!oh->_mpu_rt_va)
1689 pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
1690 __func__, oh->name);
1691 1809
1692 return 0; 1810 return 0;
1693} 1811}
@@ -1939,10 +2057,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
1939{ 2057{
1940 int ret, i; 2058 int ret, i;
1941 2059
1942 ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; 2060 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
1943 2061
1944 for (i = 0; i < oh->slaves_cnt; i++) 2062 for (i = 0; i < oh->slaves_cnt; i++)
1945 ret += oh->slaves[i]->addr_cnt; 2063 ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
1946 2064
1947 return ret; 2065 return ret;
1948} 2066}
@@ -1959,12 +2077,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
1959 */ 2077 */
1960int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) 2078int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1961{ 2079{
1962 int i, j; 2080 int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
1963 int r = 0; 2081 int r = 0;
1964 2082
1965 /* For each IRQ, DMA, memory area, fill in array.*/ 2083 /* For each IRQ, DMA, memory area, fill in array.*/
1966 2084
1967 for (i = 0; i < oh->mpu_irqs_cnt; i++) { 2085 mpu_irqs_cnt = _count_mpu_irqs(oh);
2086 for (i = 0; i < mpu_irqs_cnt; i++) {
1968 (res + r)->name = (oh->mpu_irqs + i)->name; 2087 (res + r)->name = (oh->mpu_irqs + i)->name;
1969 (res + r)->start = (oh->mpu_irqs + i)->irq; 2088 (res + r)->start = (oh->mpu_irqs + i)->irq;
1970 (res + r)->end = (oh->mpu_irqs + i)->irq; 2089 (res + r)->end = (oh->mpu_irqs + i)->irq;
@@ -1972,7 +2091,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1972 r++; 2091 r++;
1973 } 2092 }
1974 2093
1975 for (i = 0; i < oh->sdma_reqs_cnt; i++) { 2094 sdma_reqs_cnt = _count_sdma_reqs(oh);
2095 for (i = 0; i < sdma_reqs_cnt; i++) {
1976 (res + r)->name = (oh->sdma_reqs + i)->name; 2096 (res + r)->name = (oh->sdma_reqs + i)->name;
1977 (res + r)->start = (oh->sdma_reqs + i)->dma_req; 2097 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
1978 (res + r)->end = (oh->sdma_reqs + i)->dma_req; 2098 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
@@ -1982,10 +2102,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1982 2102
1983 for (i = 0; i < oh->slaves_cnt; i++) { 2103 for (i = 0; i < oh->slaves_cnt; i++) {
1984 struct omap_hwmod_ocp_if *os; 2104 struct omap_hwmod_ocp_if *os;
2105 int addr_cnt;
1985 2106
1986 os = oh->slaves[i]; 2107 os = oh->slaves[i];
2108 addr_cnt = _count_ocp_if_addr_spaces(os);
1987 2109
1988 for (j = 0; j < os->addr_cnt; j++) { 2110 for (j = 0; j < addr_cnt; j++) {
1989 (res + r)->name = (os->addr + j)->name; 2111 (res + r)->name = (os->addr + j)->name;
1990 (res + r)->start = (os->addr + j)->pa_start; 2112 (res + r)->start = (os->addr + j)->pa_start;
1991 (res + r)->end = (os->addr + j)->pa_end; 2113 (res + r)->end = (os->addr + j)->pa_end;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index c4d0ae87d62a..a015c69068f6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
114static struct omap_hwmod omap2420_mcbsp2_hwmod; 114static struct omap_hwmod omap2420_mcbsp2_hwmod;
115 115
116/* l4 core -> mcspi1 interface */ 116/* l4 core -> mcspi1 interface */
117static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
118 {
119 .pa_start = 0x48098000,
120 .pa_end = 0x480980ff,
121 .flags = ADDR_TYPE_RT,
122 },
123};
124
125static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { 117static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
126 .master = &omap2420_l4_core_hwmod, 118 .master = &omap2420_l4_core_hwmod,
127 .slave = &omap2420_mcspi1_hwmod, 119 .slave = &omap2420_mcspi1_hwmod,
128 .clk = "mcspi1_ick", 120 .clk = "mcspi1_ick",
129 .addr = omap2420_mcspi1_addr_space, 121 .addr = omap2_mcspi1_addr_space,
130 .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
131 .user = OCP_USER_MPU | OCP_USER_SDMA, 122 .user = OCP_USER_MPU | OCP_USER_SDMA,
132}; 123};
133 124
134/* l4 core -> mcspi2 interface */ 125/* l4 core -> mcspi2 interface */
135static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
136 {
137 .pa_start = 0x4809a000,
138 .pa_end = 0x4809a0ff,
139 .flags = ADDR_TYPE_RT,
140 },
141};
142
143static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { 126static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
144 .master = &omap2420_l4_core_hwmod, 127 .master = &omap2420_l4_core_hwmod,
145 .slave = &omap2420_mcspi2_hwmod, 128 .slave = &omap2420_mcspi2_hwmod,
146 .clk = "mcspi2_ick", 129 .clk = "mcspi2_ick",
147 .addr = omap2420_mcspi2_addr_space, 130 .addr = omap2_mcspi2_addr_space,
148 .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
149 .user = OCP_USER_MPU | OCP_USER_SDMA, 131 .user = OCP_USER_MPU | OCP_USER_SDMA,
150}; 132};
151 133
@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
157}; 139};
158 140
159/* L4 CORE -> UART1 interface */ 141/* L4 CORE -> UART1 interface */
160static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
161 {
162 .pa_start = OMAP2_UART1_BASE,
163 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
164 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
165 },
166};
167
168static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 142static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
169 .master = &omap2420_l4_core_hwmod, 143 .master = &omap2420_l4_core_hwmod,
170 .slave = &omap2420_uart1_hwmod, 144 .slave = &omap2420_uart1_hwmod,
171 .clk = "uart1_ick", 145 .clk = "uart1_ick",
172 .addr = omap2420_uart1_addr_space, 146 .addr = omap2xxx_uart1_addr_space,
173 .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
174 .user = OCP_USER_MPU | OCP_USER_SDMA, 147 .user = OCP_USER_MPU | OCP_USER_SDMA,
175}; 148};
176 149
177/* L4 CORE -> UART2 interface */ 150/* L4 CORE -> UART2 interface */
178static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
179 {
180 .pa_start = OMAP2_UART2_BASE,
181 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
182 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
183 },
184};
185
186static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 151static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
187 .master = &omap2420_l4_core_hwmod, 152 .master = &omap2420_l4_core_hwmod,
188 .slave = &omap2420_uart2_hwmod, 153 .slave = &omap2420_uart2_hwmod,
189 .clk = "uart2_ick", 154 .clk = "uart2_ick",
190 .addr = omap2420_uart2_addr_space, 155 .addr = omap2xxx_uart2_addr_space,
191 .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
192 .user = OCP_USER_MPU | OCP_USER_SDMA, 156 .user = OCP_USER_MPU | OCP_USER_SDMA,
193}; 157};
194 158
195/* L4 PER -> UART3 interface */ 159/* L4 PER -> UART3 interface */
196static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
197 {
198 .pa_start = OMAP2_UART3_BASE,
199 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
200 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
201 },
202};
203
204static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 160static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
205 .master = &omap2420_l4_core_hwmod, 161 .master = &omap2420_l4_core_hwmod,
206 .slave = &omap2420_uart3_hwmod, 162 .slave = &omap2420_uart3_hwmod,
207 .clk = "uart3_ick", 163 .clk = "uart3_ick",
208 .addr = omap2420_uart3_addr_space, 164 .addr = omap2xxx_uart3_addr_space,
209 .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
210 .user = OCP_USER_MPU | OCP_USER_SDMA, 165 .user = OCP_USER_MPU | OCP_USER_SDMA,
211}; 166};
212 167
213/* I2C IP block address space length (in bytes) */
214#define OMAP2_I2C_AS_LEN 128
215
216/* L4 CORE -> I2C1 interface */ 168/* L4 CORE -> I2C1 interface */
217static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
218 {
219 .pa_start = 0x48070000,
220 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
221 .flags = ADDR_TYPE_RT,
222 },
223};
224
225static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { 169static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
226 .master = &omap2420_l4_core_hwmod, 170 .master = &omap2420_l4_core_hwmod,
227 .slave = &omap2420_i2c1_hwmod, 171 .slave = &omap2420_i2c1_hwmod,
228 .clk = "i2c1_ick", 172 .clk = "i2c1_ick",
229 .addr = omap2420_i2c1_addr_space, 173 .addr = omap2_i2c1_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA, 174 .user = OCP_USER_MPU | OCP_USER_SDMA,
232}; 175};
233 176
234/* L4 CORE -> I2C2 interface */ 177/* L4 CORE -> I2C2 interface */
235static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
236 {
237 .pa_start = 0x48072000,
238 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
239 .flags = ADDR_TYPE_RT,
240 },
241};
242
243static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { 178static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
244 .master = &omap2420_l4_core_hwmod, 179 .master = &omap2420_l4_core_hwmod,
245 .slave = &omap2420_i2c2_hwmod, 180 .slave = &omap2420_i2c2_hwmod,
246 .clk = "i2c2_ick", 181 .clk = "i2c2_ick",
247 .addr = omap2420_i2c2_addr_space, 182 .addr = omap2_i2c2_addr_space,
248 .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
249 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 .user = OCP_USER_MPU | OCP_USER_SDMA,
250}; 184};
251 185
@@ -340,29 +274,8 @@ static struct omap_hwmod omap2420_iva_hwmod = {
340 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
341}; 275};
342 276
343/* Timer Common */
344static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
345 .rev_offs = 0x0000,
346 .sysc_offs = 0x0010,
347 .syss_offs = 0x0014,
348 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
349 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
350 SYSC_HAS_AUTOIDLE),
351 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
352 .sysc_fields = &omap_hwmod_sysc_type1,
353};
354
355static struct omap_hwmod_class omap2420_timer_hwmod_class = {
356 .name = "timer",
357 .sysc = &omap2420_timer_sysc,
358 .rev = OMAP_TIMER_IP_VERSION_1,
359};
360
361/* timer1 */ 277/* timer1 */
362static struct omap_hwmod omap2420_timer1_hwmod; 278static struct omap_hwmod omap2420_timer1_hwmod;
363static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
364 { .irq = 37, },
365};
366 279
367static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { 280static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
368 { 281 {
@@ -370,6 +283,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
370 .pa_end = 0x48028000 + SZ_1K - 1, 283 .pa_end = 0x48028000 + SZ_1K - 1,
371 .flags = ADDR_TYPE_RT 284 .flags = ADDR_TYPE_RT
372 }, 285 },
286 { }
373}; 287};
374 288
375/* l4_wkup -> timer1 */ 289/* l4_wkup -> timer1 */
@@ -378,7 +292,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
378 .slave = &omap2420_timer1_hwmod, 292 .slave = &omap2420_timer1_hwmod,
379 .clk = "gpt1_ick", 293 .clk = "gpt1_ick",
380 .addr = omap2420_timer1_addrs, 294 .addr = omap2420_timer1_addrs,
381 .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
382 .user = OCP_USER_MPU | OCP_USER_SDMA, 295 .user = OCP_USER_MPU | OCP_USER_SDMA,
383}; 296};
384 297
@@ -390,8 +303,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
390/* timer1 hwmod */ 303/* timer1 hwmod */
391static struct omap_hwmod omap2420_timer1_hwmod = { 304static struct omap_hwmod omap2420_timer1_hwmod = {
392 .name = "timer1", 305 .name = "timer1",
393 .mpu_irqs = omap2420_timer1_mpu_irqs, 306 .mpu_irqs = omap2_timer1_mpu_irqs,
394 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
395 .main_clk = "gpt1_fck", 307 .main_clk = "gpt1_fck",
396 .prcm = { 308 .prcm = {
397 .omap2 = { 309 .omap2 = {
@@ -404,31 +316,19 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
404 }, 316 },
405 .slaves = omap2420_timer1_slaves, 317 .slaves = omap2420_timer1_slaves,
406 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), 318 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
407 .class = &omap2420_timer_hwmod_class, 319 .class = &omap2xxx_timer_hwmod_class,
408 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
409}; 321};
410 322
411/* timer2 */ 323/* timer2 */
412static struct omap_hwmod omap2420_timer2_hwmod; 324static struct omap_hwmod omap2420_timer2_hwmod;
413static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
414 { .irq = 38, },
415};
416
417static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
418 {
419 .pa_start = 0x4802a000,
420 .pa_end = 0x4802a000 + SZ_1K - 1,
421 .flags = ADDR_TYPE_RT
422 },
423};
424 325
425/* l4_core -> timer2 */ 326/* l4_core -> timer2 */
426static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { 327static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
427 .master = &omap2420_l4_core_hwmod, 328 .master = &omap2420_l4_core_hwmod,
428 .slave = &omap2420_timer2_hwmod, 329 .slave = &omap2420_timer2_hwmod,
429 .clk = "gpt2_ick", 330 .clk = "gpt2_ick",
430 .addr = omap2420_timer2_addrs, 331 .addr = omap2xxx_timer2_addrs,
431 .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
432 .user = OCP_USER_MPU | OCP_USER_SDMA, 332 .user = OCP_USER_MPU | OCP_USER_SDMA,
433}; 333};
434 334
@@ -440,8 +340,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
440/* timer2 hwmod */ 340/* timer2 hwmod */
441static struct omap_hwmod omap2420_timer2_hwmod = { 341static struct omap_hwmod omap2420_timer2_hwmod = {
442 .name = "timer2", 342 .name = "timer2",
443 .mpu_irqs = omap2420_timer2_mpu_irqs, 343 .mpu_irqs = omap2_timer2_mpu_irqs,
444 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
445 .main_clk = "gpt2_fck", 344 .main_clk = "gpt2_fck",
446 .prcm = { 345 .prcm = {
447 .omap2 = { 346 .omap2 = {
@@ -454,31 +353,19 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
454 }, 353 },
455 .slaves = omap2420_timer2_slaves, 354 .slaves = omap2420_timer2_slaves,
456 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), 355 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
457 .class = &omap2420_timer_hwmod_class, 356 .class = &omap2xxx_timer_hwmod_class,
458 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
459}; 358};
460 359
461/* timer3 */ 360/* timer3 */
462static struct omap_hwmod omap2420_timer3_hwmod; 361static struct omap_hwmod omap2420_timer3_hwmod;
463static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
464 { .irq = 39, },
465};
466
467static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
468 {
469 .pa_start = 0x48078000,
470 .pa_end = 0x48078000 + SZ_1K - 1,
471 .flags = ADDR_TYPE_RT
472 },
473};
474 362
475/* l4_core -> timer3 */ 363/* l4_core -> timer3 */
476static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { 364static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
477 .master = &omap2420_l4_core_hwmod, 365 .master = &omap2420_l4_core_hwmod,
478 .slave = &omap2420_timer3_hwmod, 366 .slave = &omap2420_timer3_hwmod,
479 .clk = "gpt3_ick", 367 .clk = "gpt3_ick",
480 .addr = omap2420_timer3_addrs, 368 .addr = omap2xxx_timer3_addrs,
481 .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
482 .user = OCP_USER_MPU | OCP_USER_SDMA, 369 .user = OCP_USER_MPU | OCP_USER_SDMA,
483}; 370};
484 371
@@ -490,8 +377,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
490/* timer3 hwmod */ 377/* timer3 hwmod */
491static struct omap_hwmod omap2420_timer3_hwmod = { 378static struct omap_hwmod omap2420_timer3_hwmod = {
492 .name = "timer3", 379 .name = "timer3",
493 .mpu_irqs = omap2420_timer3_mpu_irqs, 380 .mpu_irqs = omap2_timer3_mpu_irqs,
494 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
495 .main_clk = "gpt3_fck", 381 .main_clk = "gpt3_fck",
496 .prcm = { 382 .prcm = {
497 .omap2 = { 383 .omap2 = {
@@ -504,31 +390,19 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
504 }, 390 },
505 .slaves = omap2420_timer3_slaves, 391 .slaves = omap2420_timer3_slaves,
506 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 392 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
507 .class = &omap2420_timer_hwmod_class, 393 .class = &omap2xxx_timer_hwmod_class,
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
509}; 395};
510 396
511/* timer4 */ 397/* timer4 */
512static struct omap_hwmod omap2420_timer4_hwmod; 398static struct omap_hwmod omap2420_timer4_hwmod;
513static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
514 { .irq = 40, },
515};
516
517static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
518 {
519 .pa_start = 0x4807a000,
520 .pa_end = 0x4807a000 + SZ_1K - 1,
521 .flags = ADDR_TYPE_RT
522 },
523};
524 399
525/* l4_core -> timer4 */ 400/* l4_core -> timer4 */
526static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { 401static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
527 .master = &omap2420_l4_core_hwmod, 402 .master = &omap2420_l4_core_hwmod,
528 .slave = &omap2420_timer4_hwmod, 403 .slave = &omap2420_timer4_hwmod,
529 .clk = "gpt4_ick", 404 .clk = "gpt4_ick",
530 .addr = omap2420_timer4_addrs, 405 .addr = omap2xxx_timer4_addrs,
531 .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
532 .user = OCP_USER_MPU | OCP_USER_SDMA, 406 .user = OCP_USER_MPU | OCP_USER_SDMA,
533}; 407};
534 408
@@ -540,8 +414,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
540/* timer4 hwmod */ 414/* timer4 hwmod */
541static struct omap_hwmod omap2420_timer4_hwmod = { 415static struct omap_hwmod omap2420_timer4_hwmod = {
542 .name = "timer4", 416 .name = "timer4",
543 .mpu_irqs = omap2420_timer4_mpu_irqs, 417 .mpu_irqs = omap2_timer4_mpu_irqs,
544 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
545 .main_clk = "gpt4_fck", 418 .main_clk = "gpt4_fck",
546 .prcm = { 419 .prcm = {
547 .omap2 = { 420 .omap2 = {
@@ -554,31 +427,19 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
554 }, 427 },
555 .slaves = omap2420_timer4_slaves, 428 .slaves = omap2420_timer4_slaves,
556 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), 429 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
557 .class = &omap2420_timer_hwmod_class, 430 .class = &omap2xxx_timer_hwmod_class,
558 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
559}; 432};
560 433
561/* timer5 */ 434/* timer5 */
562static struct omap_hwmod omap2420_timer5_hwmod; 435static struct omap_hwmod omap2420_timer5_hwmod;
563static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
564 { .irq = 41, },
565};
566
567static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
568 {
569 .pa_start = 0x4807c000,
570 .pa_end = 0x4807c000 + SZ_1K - 1,
571 .flags = ADDR_TYPE_RT
572 },
573};
574 436
575/* l4_core -> timer5 */ 437/* l4_core -> timer5 */
576static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { 438static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
577 .master = &omap2420_l4_core_hwmod, 439 .master = &omap2420_l4_core_hwmod,
578 .slave = &omap2420_timer5_hwmod, 440 .slave = &omap2420_timer5_hwmod,
579 .clk = "gpt5_ick", 441 .clk = "gpt5_ick",
580 .addr = omap2420_timer5_addrs, 442 .addr = omap2xxx_timer5_addrs,
581 .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
582 .user = OCP_USER_MPU | OCP_USER_SDMA, 443 .user = OCP_USER_MPU | OCP_USER_SDMA,
583}; 444};
584 445
@@ -590,8 +451,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
590/* timer5 hwmod */ 451/* timer5 hwmod */
591static struct omap_hwmod omap2420_timer5_hwmod = { 452static struct omap_hwmod omap2420_timer5_hwmod = {
592 .name = "timer5", 453 .name = "timer5",
593 .mpu_irqs = omap2420_timer5_mpu_irqs, 454 .mpu_irqs = omap2_timer5_mpu_irqs,
594 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
595 .main_clk = "gpt5_fck", 455 .main_clk = "gpt5_fck",
596 .prcm = { 456 .prcm = {
597 .omap2 = { 457 .omap2 = {
@@ -604,32 +464,20 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
604 }, 464 },
605 .slaves = omap2420_timer5_slaves, 465 .slaves = omap2420_timer5_slaves,
606 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), 466 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
607 .class = &omap2420_timer_hwmod_class, 467 .class = &omap2xxx_timer_hwmod_class,
608 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 468 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
609}; 469};
610 470
611 471
612/* timer6 */ 472/* timer6 */
613static struct omap_hwmod omap2420_timer6_hwmod; 473static struct omap_hwmod omap2420_timer6_hwmod;
614static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
615 { .irq = 42, },
616};
617
618static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
619 {
620 .pa_start = 0x4807e000,
621 .pa_end = 0x4807e000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625 474
626/* l4_core -> timer6 */ 475/* l4_core -> timer6 */
627static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { 476static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
628 .master = &omap2420_l4_core_hwmod, 477 .master = &omap2420_l4_core_hwmod,
629 .slave = &omap2420_timer6_hwmod, 478 .slave = &omap2420_timer6_hwmod,
630 .clk = "gpt6_ick", 479 .clk = "gpt6_ick",
631 .addr = omap2420_timer6_addrs, 480 .addr = omap2xxx_timer6_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 481 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 482};
635 483
@@ -641,8 +489,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
641/* timer6 hwmod */ 489/* timer6 hwmod */
642static struct omap_hwmod omap2420_timer6_hwmod = { 490static struct omap_hwmod omap2420_timer6_hwmod = {
643 .name = "timer6", 491 .name = "timer6",
644 .mpu_irqs = omap2420_timer6_mpu_irqs, 492 .mpu_irqs = omap2_timer6_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
646 .main_clk = "gpt6_fck", 493 .main_clk = "gpt6_fck",
647 .prcm = { 494 .prcm = {
648 .omap2 = { 495 .omap2 = {
@@ -655,31 +502,19 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
655 }, 502 },
656 .slaves = omap2420_timer6_slaves, 503 .slaves = omap2420_timer6_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), 504 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
658 .class = &omap2420_timer_hwmod_class, 505 .class = &omap2xxx_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
660}; 507};
661 508
662/* timer7 */ 509/* timer7 */
663static struct omap_hwmod omap2420_timer7_hwmod; 510static struct omap_hwmod omap2420_timer7_hwmod;
664static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
665 { .irq = 43, },
666};
667
668static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
669 {
670 .pa_start = 0x48080000,
671 .pa_end = 0x48080000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675 511
676/* l4_core -> timer7 */ 512/* l4_core -> timer7 */
677static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { 513static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
678 .master = &omap2420_l4_core_hwmod, 514 .master = &omap2420_l4_core_hwmod,
679 .slave = &omap2420_timer7_hwmod, 515 .slave = &omap2420_timer7_hwmod,
680 .clk = "gpt7_ick", 516 .clk = "gpt7_ick",
681 .addr = omap2420_timer7_addrs, 517 .addr = omap2xxx_timer7_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 518 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 519};
685 520
@@ -691,8 +526,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
691/* timer7 hwmod */ 526/* timer7 hwmod */
692static struct omap_hwmod omap2420_timer7_hwmod = { 527static struct omap_hwmod omap2420_timer7_hwmod = {
693 .name = "timer7", 528 .name = "timer7",
694 .mpu_irqs = omap2420_timer7_mpu_irqs, 529 .mpu_irqs = omap2_timer7_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
696 .main_clk = "gpt7_fck", 530 .main_clk = "gpt7_fck",
697 .prcm = { 531 .prcm = {
698 .omap2 = { 532 .omap2 = {
@@ -705,31 +539,19 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
705 }, 539 },
706 .slaves = omap2420_timer7_slaves, 540 .slaves = omap2420_timer7_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), 541 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
708 .class = &omap2420_timer_hwmod_class, 542 .class = &omap2xxx_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 543 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
710}; 544};
711 545
712/* timer8 */ 546/* timer8 */
713static struct omap_hwmod omap2420_timer8_hwmod; 547static struct omap_hwmod omap2420_timer8_hwmod;
714static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
715 { .irq = 44, },
716};
717
718static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
719 {
720 .pa_start = 0x48082000,
721 .pa_end = 0x48082000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725 548
726/* l4_core -> timer8 */ 549/* l4_core -> timer8 */
727static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { 550static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
728 .master = &omap2420_l4_core_hwmod, 551 .master = &omap2420_l4_core_hwmod,
729 .slave = &omap2420_timer8_hwmod, 552 .slave = &omap2420_timer8_hwmod,
730 .clk = "gpt8_ick", 553 .clk = "gpt8_ick",
731 .addr = omap2420_timer8_addrs, 554 .addr = omap2xxx_timer8_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 555 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 556};
735 557
@@ -741,8 +563,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
741/* timer8 hwmod */ 563/* timer8 hwmod */
742static struct omap_hwmod omap2420_timer8_hwmod = { 564static struct omap_hwmod omap2420_timer8_hwmod = {
743 .name = "timer8", 565 .name = "timer8",
744 .mpu_irqs = omap2420_timer8_mpu_irqs, 566 .mpu_irqs = omap2_timer8_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
746 .main_clk = "gpt8_fck", 567 .main_clk = "gpt8_fck",
747 .prcm = { 568 .prcm = {
748 .omap2 = { 569 .omap2 = {
@@ -755,31 +576,19 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
755 }, 576 },
756 .slaves = omap2420_timer8_slaves, 577 .slaves = omap2420_timer8_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), 578 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
758 .class = &omap2420_timer_hwmod_class, 579 .class = &omap2xxx_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
760}; 581};
761 582
762/* timer9 */ 583/* timer9 */
763static struct omap_hwmod omap2420_timer9_hwmod; 584static struct omap_hwmod omap2420_timer9_hwmod;
764static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
765 { .irq = 45, },
766};
767
768static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
769 {
770 .pa_start = 0x48084000,
771 .pa_end = 0x48084000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775 585
776/* l4_core -> timer9 */ 586/* l4_core -> timer9 */
777static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { 587static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
778 .master = &omap2420_l4_core_hwmod, 588 .master = &omap2420_l4_core_hwmod,
779 .slave = &omap2420_timer9_hwmod, 589 .slave = &omap2420_timer9_hwmod,
780 .clk = "gpt9_ick", 590 .clk = "gpt9_ick",
781 .addr = omap2420_timer9_addrs, 591 .addr = omap2xxx_timer9_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 592 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 593};
785 594
@@ -791,8 +600,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
791/* timer9 hwmod */ 600/* timer9 hwmod */
792static struct omap_hwmod omap2420_timer9_hwmod = { 601static struct omap_hwmod omap2420_timer9_hwmod = {
793 .name = "timer9", 602 .name = "timer9",
794 .mpu_irqs = omap2420_timer9_mpu_irqs, 603 .mpu_irqs = omap2_timer9_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
796 .main_clk = "gpt9_fck", 604 .main_clk = "gpt9_fck",
797 .prcm = { 605 .prcm = {
798 .omap2 = { 606 .omap2 = {
@@ -805,31 +613,19 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
805 }, 613 },
806 .slaves = omap2420_timer9_slaves, 614 .slaves = omap2420_timer9_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), 615 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
808 .class = &omap2420_timer_hwmod_class, 616 .class = &omap2xxx_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
810}; 618};
811 619
812/* timer10 */ 620/* timer10 */
813static struct omap_hwmod omap2420_timer10_hwmod; 621static struct omap_hwmod omap2420_timer10_hwmod;
814static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
815 { .irq = 46, },
816};
817
818static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
819 {
820 .pa_start = 0x48086000,
821 .pa_end = 0x48086000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825 622
826/* l4_core -> timer10 */ 623/* l4_core -> timer10 */
827static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { 624static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
828 .master = &omap2420_l4_core_hwmod, 625 .master = &omap2420_l4_core_hwmod,
829 .slave = &omap2420_timer10_hwmod, 626 .slave = &omap2420_timer10_hwmod,
830 .clk = "gpt10_ick", 627 .clk = "gpt10_ick",
831 .addr = omap2420_timer10_addrs, 628 .addr = omap2_timer10_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 629 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 630};
835 631
@@ -841,8 +637,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
841/* timer10 hwmod */ 637/* timer10 hwmod */
842static struct omap_hwmod omap2420_timer10_hwmod = { 638static struct omap_hwmod omap2420_timer10_hwmod = {
843 .name = "timer10", 639 .name = "timer10",
844 .mpu_irqs = omap2420_timer10_mpu_irqs, 640 .mpu_irqs = omap2_timer10_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
846 .main_clk = "gpt10_fck", 641 .main_clk = "gpt10_fck",
847 .prcm = { 642 .prcm = {
848 .omap2 = { 643 .omap2 = {
@@ -855,31 +650,19 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
855 }, 650 },
856 .slaves = omap2420_timer10_slaves, 651 .slaves = omap2420_timer10_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), 652 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
858 .class = &omap2420_timer_hwmod_class, 653 .class = &omap2xxx_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 654 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
860}; 655};
861 656
862/* timer11 */ 657/* timer11 */
863static struct omap_hwmod omap2420_timer11_hwmod; 658static struct omap_hwmod omap2420_timer11_hwmod;
864static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
865 { .irq = 47, },
866};
867
868static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
869 {
870 .pa_start = 0x48088000,
871 .pa_end = 0x48088000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875 659
876/* l4_core -> timer11 */ 660/* l4_core -> timer11 */
877static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { 661static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
878 .master = &omap2420_l4_core_hwmod, 662 .master = &omap2420_l4_core_hwmod,
879 .slave = &omap2420_timer11_hwmod, 663 .slave = &omap2420_timer11_hwmod,
880 .clk = "gpt11_ick", 664 .clk = "gpt11_ick",
881 .addr = omap2420_timer11_addrs, 665 .addr = omap2_timer11_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 666 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 667};
885 668
@@ -891,8 +674,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
891/* timer11 hwmod */ 674/* timer11 hwmod */
892static struct omap_hwmod omap2420_timer11_hwmod = { 675static struct omap_hwmod omap2420_timer11_hwmod = {
893 .name = "timer11", 676 .name = "timer11",
894 .mpu_irqs = omap2420_timer11_mpu_irqs, 677 .mpu_irqs = omap2_timer11_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
896 .main_clk = "gpt11_fck", 678 .main_clk = "gpt11_fck",
897 .prcm = { 679 .prcm = {
898 .omap2 = { 680 .omap2 = {
@@ -905,31 +687,19 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
905 }, 687 },
906 .slaves = omap2420_timer11_slaves, 688 .slaves = omap2420_timer11_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), 689 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
908 .class = &omap2420_timer_hwmod_class, 690 .class = &omap2xxx_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
910}; 692};
911 693
912/* timer12 */ 694/* timer12 */
913static struct omap_hwmod omap2420_timer12_hwmod; 695static struct omap_hwmod omap2420_timer12_hwmod;
914static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
915 { .irq = 48, },
916};
917
918static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
919 {
920 .pa_start = 0x4808a000,
921 .pa_end = 0x4808a000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925 696
926/* l4_core -> timer12 */ 697/* l4_core -> timer12 */
927static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { 698static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
928 .master = &omap2420_l4_core_hwmod, 699 .master = &omap2420_l4_core_hwmod,
929 .slave = &omap2420_timer12_hwmod, 700 .slave = &omap2420_timer12_hwmod,
930 .clk = "gpt12_ick", 701 .clk = "gpt12_ick",
931 .addr = omap2420_timer12_addrs, 702 .addr = omap2xxx_timer12_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 703 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 704};
935 705
@@ -941,8 +711,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
941/* timer12 hwmod */ 711/* timer12 hwmod */
942static struct omap_hwmod omap2420_timer12_hwmod = { 712static struct omap_hwmod omap2420_timer12_hwmod = {
943 .name = "timer12", 713 .name = "timer12",
944 .mpu_irqs = omap2420_timer12_mpu_irqs, 714 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
946 .main_clk = "gpt12_fck", 715 .main_clk = "gpt12_fck",
947 .prcm = { 716 .prcm = {
948 .omap2 = { 717 .omap2 = {
@@ -955,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
955 }, 724 },
956 .slaves = omap2420_timer12_slaves, 725 .slaves = omap2420_timer12_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), 726 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
958 .class = &omap2420_timer_hwmod_class, 727 .class = &omap2xxx_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
960}; 729};
961 730
@@ -966,6 +735,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
966 .pa_end = 0x4802207f, 735 .pa_end = 0x4802207f,
967 .flags = ADDR_TYPE_RT 736 .flags = ADDR_TYPE_RT
968 }, 737 },
738 { }
969}; 739};
970 740
971static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 741static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
@@ -973,31 +743,9 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
973 .slave = &omap2420_wd_timer2_hwmod, 743 .slave = &omap2420_wd_timer2_hwmod,
974 .clk = "mpu_wdt_ick", 744 .clk = "mpu_wdt_ick",
975 .addr = omap2420_wd_timer2_addrs, 745 .addr = omap2420_wd_timer2_addrs,
976 .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
977 .user = OCP_USER_MPU | OCP_USER_SDMA, 746 .user = OCP_USER_MPU | OCP_USER_SDMA,
978}; 747};
979 748
980/*
981 * 'wd_timer' class
982 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
983 * overflow condition
984 */
985
986static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
987 .rev_offs = 0x0000,
988 .sysc_offs = 0x0010,
989 .syss_offs = 0x0014,
990 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
991 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
992 .sysc_fields = &omap_hwmod_sysc_type1,
993};
994
995static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
996 .name = "wd_timer",
997 .sysc = &omap2420_wd_timer_sysc,
998 .pre_shutdown = &omap2_wd_timer_disable
999};
1000
1001/* wd_timer2 */ 749/* wd_timer2 */
1002static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { 750static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1003 &omap2420_l4_wkup__wd_timer2, 751 &omap2420_l4_wkup__wd_timer2,
@@ -1005,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1005 753
1006static struct omap_hwmod omap2420_wd_timer2_hwmod = { 754static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1007 .name = "wd_timer2", 755 .name = "wd_timer2",
1008 .class = &omap2420_wd_timer_hwmod_class, 756 .class = &omap2xxx_wd_timer_hwmod_class,
1009 .main_clk = "mpu_wdt_fck", 757 .main_clk = "mpu_wdt_fck",
1010 .prcm = { 758 .prcm = {
1011 .omap2 = { 759 .omap2 = {
@@ -1021,45 +769,16 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1022}; 770};
1023 771
1024/* UART */
1025
1026static struct omap_hwmod_class_sysconfig uart_sysc = {
1027 .rev_offs = 0x50,
1028 .sysc_offs = 0x54,
1029 .syss_offs = 0x58,
1030 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1032 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1034 .sysc_fields = &omap_hwmod_sysc_type1,
1035};
1036
1037static struct omap_hwmod_class uart_class = {
1038 .name = "uart",
1039 .sysc = &uart_sysc,
1040};
1041
1042/* UART1 */ 772/* UART1 */
1043 773
1044static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1045 { .irq = INT_24XX_UART1_IRQ, },
1046};
1047
1048static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1049 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1050 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1051};
1052
1053static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { 774static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
1054 &omap2_l4_core__uart1, 775 &omap2_l4_core__uart1,
1055}; 776};
1056 777
1057static struct omap_hwmod omap2420_uart1_hwmod = { 778static struct omap_hwmod omap2420_uart1_hwmod = {
1058 .name = "uart1", 779 .name = "uart1",
1059 .mpu_irqs = uart1_mpu_irqs, 780 .mpu_irqs = omap2_uart1_mpu_irqs,
1060 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 781 .sdma_reqs = omap2_uart1_sdma_reqs,
1061 .sdma_reqs = uart1_sdma_reqs,
1062 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1063 .main_clk = "uart1_fck", 782 .main_clk = "uart1_fck",
1064 .prcm = { 783 .prcm = {
1065 .omap2 = { 784 .omap2 = {
@@ -1072,31 +791,20 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
1072 }, 791 },
1073 .slaves = omap2420_uart1_slaves, 792 .slaves = omap2420_uart1_slaves,
1074 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), 793 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
1075 .class = &uart_class, 794 .class = &omap2_uart_class,
1076 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 795 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1077}; 796};
1078 797
1079/* UART2 */ 798/* UART2 */
1080 799
1081static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1082 { .irq = INT_24XX_UART2_IRQ, },
1083};
1084
1085static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1086 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1087 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1088};
1089
1090static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { 800static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
1091 &omap2_l4_core__uart2, 801 &omap2_l4_core__uart2,
1092}; 802};
1093 803
1094static struct omap_hwmod omap2420_uart2_hwmod = { 804static struct omap_hwmod omap2420_uart2_hwmod = {
1095 .name = "uart2", 805 .name = "uart2",
1096 .mpu_irqs = uart2_mpu_irqs, 806 .mpu_irqs = omap2_uart2_mpu_irqs,
1097 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 807 .sdma_reqs = omap2_uart2_sdma_reqs,
1098 .sdma_reqs = uart2_sdma_reqs,
1099 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1100 .main_clk = "uart2_fck", 808 .main_clk = "uart2_fck",
1101 .prcm = { 809 .prcm = {
1102 .omap2 = { 810 .omap2 = {
@@ -1109,31 +817,20 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
1109 }, 817 },
1110 .slaves = omap2420_uart2_slaves, 818 .slaves = omap2420_uart2_slaves,
1111 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), 819 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
1112 .class = &uart_class, 820 .class = &omap2_uart_class,
1113 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 821 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1114}; 822};
1115 823
1116/* UART3 */ 824/* UART3 */
1117 825
1118static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1119 { .irq = INT_24XX_UART3_IRQ, },
1120};
1121
1122static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1123 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1124 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1125};
1126
1127static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { 826static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
1128 &omap2_l4_core__uart3, 827 &omap2_l4_core__uart3,
1129}; 828};
1130 829
1131static struct omap_hwmod omap2420_uart3_hwmod = { 830static struct omap_hwmod omap2420_uart3_hwmod = {
1132 .name = "uart3", 831 .name = "uart3",
1133 .mpu_irqs = uart3_mpu_irqs, 832 .mpu_irqs = omap2_uart3_mpu_irqs,
1134 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 833 .sdma_reqs = omap2_uart3_sdma_reqs,
1135 .sdma_reqs = uart3_sdma_reqs,
1136 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1137 .main_clk = "uart3_fck", 834 .main_clk = "uart3_fck",
1138 .prcm = { 835 .prcm = {
1139 .omap2 = { 836 .omap2 = {
@@ -1146,53 +843,22 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
1146 }, 843 },
1147 .slaves = omap2420_uart3_slaves, 844 .slaves = omap2420_uart3_slaves,
1148 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), 845 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
1149 .class = &uart_class, 846 .class = &omap2_uart_class,
1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1151}; 848};
1152 849
1153/*
1154 * 'dss' class
1155 * display sub-system
1156 */
1157
1158static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
1159 .rev_offs = 0x0000,
1160 .sysc_offs = 0x0010,
1161 .syss_offs = 0x0014,
1162 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1163 .sysc_fields = &omap_hwmod_sysc_type1,
1164};
1165
1166static struct omap_hwmod_class omap2420_dss_hwmod_class = {
1167 .name = "dss",
1168 .sysc = &omap2420_dss_sysc,
1169};
1170
1171static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
1172 { .name = "dispc", .dma_req = 5 },
1173};
1174
1175/* dss */ 850/* dss */
1176/* dss master ports */ 851/* dss master ports */
1177static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { 852static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
1178 &omap2420_dss__l3, 853 &omap2420_dss__l3,
1179}; 854};
1180 855
1181static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
1182 {
1183 .pa_start = 0x48050000,
1184 .pa_end = 0x480503FF,
1185 .flags = ADDR_TYPE_RT
1186 },
1187};
1188
1189/* l4_core -> dss */ 856/* l4_core -> dss */
1190static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { 857static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
1191 .master = &omap2420_l4_core_hwmod, 858 .master = &omap2420_l4_core_hwmod,
1192 .slave = &omap2420_dss_core_hwmod, 859 .slave = &omap2420_dss_core_hwmod,
1193 .clk = "dss_ick", 860 .clk = "dss_ick",
1194 .addr = omap2420_dss_addrs, 861 .addr = omap2_dss_addrs,
1195 .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
1196 .fw = { 862 .fw = {
1197 .omap2 = { 863 .omap2 = {
1198 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 864 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1214,10 +880,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1214 880
1215static struct omap_hwmod omap2420_dss_core_hwmod = { 881static struct omap_hwmod omap2420_dss_core_hwmod = {
1216 .name = "dss_core", 882 .name = "dss_core",
1217 .class = &omap2420_dss_hwmod_class, 883 .class = &omap2_dss_hwmod_class,
1218 .main_clk = "dss1_fck", /* instead of dss_fck */ 884 .main_clk = "dss1_fck", /* instead of dss_fck */
1219 .sdma_reqs = omap2420_dss_sdma_chs, 885 .sdma_reqs = omap2xxx_dss_sdma_chs,
1220 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
1221 .prcm = { 886 .prcm = {
1222 .omap2 = { 887 .omap2 = {
1223 .prcm_reg_id = 1, 888 .prcm_reg_id = 1,
@@ -1237,46 +902,12 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
1237 .flags = HWMOD_NO_IDLEST, 902 .flags = HWMOD_NO_IDLEST,
1238}; 903};
1239 904
1240/*
1241 * 'dispc' class
1242 * display controller
1243 */
1244
1245static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
1246 .rev_offs = 0x0000,
1247 .sysc_offs = 0x0010,
1248 .syss_offs = 0x0014,
1249 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1250 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1252 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1253 .sysc_fields = &omap_hwmod_sysc_type1,
1254};
1255
1256static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
1257 .name = "dispc",
1258 .sysc = &omap2420_dispc_sysc,
1259};
1260
1261static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
1262 { .irq = 25 },
1263};
1264
1265static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
1266 {
1267 .pa_start = 0x48050400,
1268 .pa_end = 0x480507FF,
1269 .flags = ADDR_TYPE_RT
1270 },
1271};
1272
1273/* l4_core -> dss_dispc */ 905/* l4_core -> dss_dispc */
1274static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { 906static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1275 .master = &omap2420_l4_core_hwmod, 907 .master = &omap2420_l4_core_hwmod,
1276 .slave = &omap2420_dss_dispc_hwmod, 908 .slave = &omap2420_dss_dispc_hwmod,
1277 .clk = "dss_ick", 909 .clk = "dss_ick",
1278 .addr = omap2420_dss_dispc_addrs, 910 .addr = omap2_dss_dispc_addrs,
1279 .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
1280 .fw = { 911 .fw = {
1281 .omap2 = { 912 .omap2 = {
1282 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 913 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1293,9 +924,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1293 924
1294static struct omap_hwmod omap2420_dss_dispc_hwmod = { 925static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1295 .name = "dss_dispc", 926 .name = "dss_dispc",
1296 .class = &omap2420_dispc_hwmod_class, 927 .class = &omap2_dispc_hwmod_class,
1297 .mpu_irqs = omap2420_dispc_irqs, 928 .mpu_irqs = omap2_dispc_irqs,
1298 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
1299 .main_clk = "dss1_fck", 929 .main_clk = "dss1_fck",
1300 .prcm = { 930 .prcm = {
1301 .omap2 = { 931 .omap2 = {
@@ -1312,41 +942,12 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1312 .flags = HWMOD_NO_IDLEST, 942 .flags = HWMOD_NO_IDLEST,
1313}; 943};
1314 944
1315/*
1316 * 'rfbi' class
1317 * remote frame buffer interface
1318 */
1319
1320static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1321 .rev_offs = 0x0000,
1322 .sysc_offs = 0x0010,
1323 .syss_offs = 0x0014,
1324 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1325 SYSC_HAS_AUTOIDLE),
1326 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1327 .sysc_fields = &omap_hwmod_sysc_type1,
1328};
1329
1330static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1331 .name = "rfbi",
1332 .sysc = &omap2420_rfbi_sysc,
1333};
1334
1335static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
1336 {
1337 .pa_start = 0x48050800,
1338 .pa_end = 0x48050BFF,
1339 .flags = ADDR_TYPE_RT
1340 },
1341};
1342
1343/* l4_core -> dss_rfbi */ 945/* l4_core -> dss_rfbi */
1344static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { 946static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1345 .master = &omap2420_l4_core_hwmod, 947 .master = &omap2420_l4_core_hwmod,
1346 .slave = &omap2420_dss_rfbi_hwmod, 948 .slave = &omap2420_dss_rfbi_hwmod,
1347 .clk = "dss_ick", 949 .clk = "dss_ick",
1348 .addr = omap2420_dss_rfbi_addrs, 950 .addr = omap2_dss_rfbi_addrs,
1349 .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
1350 .fw = { 951 .fw = {
1351 .omap2 = { 952 .omap2 = {
1352 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 953 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1363,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1363 964
1364static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 965static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1365 .name = "dss_rfbi", 966 .name = "dss_rfbi",
1366 .class = &omap2420_rfbi_hwmod_class, 967 .class = &omap2_rfbi_hwmod_class,
1367 .main_clk = "dss1_fck", 968 .main_clk = "dss1_fck",
1368 .prcm = { 969 .prcm = {
1369 .omap2 = { 970 .omap2 = {
@@ -1378,31 +979,12 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1378 .flags = HWMOD_NO_IDLEST, 979 .flags = HWMOD_NO_IDLEST,
1379}; 980};
1380 981
1381/*
1382 * 'venc' class
1383 * video encoder
1384 */
1385
1386static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1387 .name = "venc",
1388};
1389
1390/* dss_venc */
1391static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
1392 {
1393 .pa_start = 0x48050C00,
1394 .pa_end = 0x48050FFF,
1395 .flags = ADDR_TYPE_RT
1396 },
1397};
1398
1399/* l4_core -> dss_venc */ 982/* l4_core -> dss_venc */
1400static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 983static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1401 .master = &omap2420_l4_core_hwmod, 984 .master = &omap2420_l4_core_hwmod,
1402 .slave = &omap2420_dss_venc_hwmod, 985 .slave = &omap2420_dss_venc_hwmod,
1403 .clk = "dss_54m_fck", 986 .clk = "dss_54m_fck",
1404 .addr = omap2420_dss_venc_addrs, 987 .addr = omap2_dss_venc_addrs,
1405 .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
1406 .fw = { 988 .fw = {
1407 .omap2 = { 989 .omap2 = {
1408 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 990 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
@@ -1420,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1420 1002
1421static struct omap_hwmod omap2420_dss_venc_hwmod = { 1003static struct omap_hwmod omap2420_dss_venc_hwmod = {
1422 .name = "dss_venc", 1004 .name = "dss_venc",
1423 .class = &omap2420_venc_hwmod_class, 1005 .class = &omap2_venc_hwmod_class,
1424 .main_clk = "dss1_fck", 1006 .main_clk = "dss1_fck",
1425 .prcm = { 1007 .prcm = {
1426 .omap2 = { 1008 .omap2 = {
@@ -1447,20 +1029,18 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
1447static struct omap_hwmod_class i2c_class = { 1029static struct omap_hwmod_class i2c_class = {
1448 .name = "i2c", 1030 .name = "i2c",
1449 .sysc = &i2c_sysc, 1031 .sysc = &i2c_sysc,
1032 .rev = OMAP_I2C_IP_VERSION_1,
1033 .reset = &omap_i2c_reset,
1450}; 1034};
1451 1035
1452static struct omap_i2c_dev_attr i2c_dev_attr; 1036static struct omap_i2c_dev_attr i2c_dev_attr = {
1453 1037 .flags = OMAP_I2C_FLAG_NO_FIFO |
1454/* I2C1 */ 1038 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1455 1039 OMAP_I2C_FLAG_16BIT_DATA_REG |
1456static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { 1040 OMAP_I2C_FLAG_BUS_SHIFT_2,
1457 { .irq = INT_24XX_I2C1_IRQ, },
1458}; 1041};
1459 1042
1460static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { 1043/* I2C1 */
1461 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1462 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1463};
1464 1044
1465static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { 1045static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1466 &omap2420_l4_core__i2c1, 1046 &omap2420_l4_core__i2c1,
@@ -1468,10 +1048,8 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1468 1048
1469static struct omap_hwmod omap2420_i2c1_hwmod = { 1049static struct omap_hwmod omap2420_i2c1_hwmod = {
1470 .name = "i2c1", 1050 .name = "i2c1",
1471 .mpu_irqs = i2c1_mpu_irqs, 1051 .mpu_irqs = omap2_i2c1_mpu_irqs,
1472 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1052 .sdma_reqs = omap2_i2c1_sdma_reqs,
1473 .sdma_reqs = i2c1_sdma_reqs,
1474 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1475 .main_clk = "i2c1_fck", 1053 .main_clk = "i2c1_fck",
1476 .prcm = { 1054 .prcm = {
1477 .omap2 = { 1055 .omap2 = {
@@ -1492,25 +1070,14 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
1492 1070
1493/* I2C2 */ 1071/* I2C2 */
1494 1072
1495static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1496 { .irq = INT_24XX_I2C2_IRQ, },
1497};
1498
1499static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1500 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1501 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1502};
1503
1504static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { 1073static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1505 &omap2420_l4_core__i2c2, 1074 &omap2420_l4_core__i2c2,
1506}; 1075};
1507 1076
1508static struct omap_hwmod omap2420_i2c2_hwmod = { 1077static struct omap_hwmod omap2420_i2c2_hwmod = {
1509 .name = "i2c2", 1078 .name = "i2c2",
1510 .mpu_irqs = i2c2_mpu_irqs, 1079 .mpu_irqs = omap2_i2c2_mpu_irqs,
1511 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1080 .sdma_reqs = omap2_i2c2_sdma_reqs,
1512 .sdma_reqs = i2c2_sdma_reqs,
1513 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1514 .main_clk = "i2c2_fck", 1081 .main_clk = "i2c2_fck",
1515 .prcm = { 1082 .prcm = {
1516 .omap2 = { 1083 .omap2 = {
@@ -1536,6 +1103,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1536 .pa_end = 0x480181ff, 1103 .pa_end = 0x480181ff,
1537 .flags = ADDR_TYPE_RT 1104 .flags = ADDR_TYPE_RT
1538 }, 1105 },
1106 { }
1539}; 1107};
1540 1108
1541static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 1109static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
@@ -1543,7 +1111,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1543 .slave = &omap2420_gpio1_hwmod, 1111 .slave = &omap2420_gpio1_hwmod,
1544 .clk = "gpios_ick", 1112 .clk = "gpios_ick",
1545 .addr = omap2420_gpio1_addr_space, 1113 .addr = omap2420_gpio1_addr_space,
1546 .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
1547 .user = OCP_USER_MPU | OCP_USER_SDMA, 1114 .user = OCP_USER_MPU | OCP_USER_SDMA,
1548}; 1115};
1549 1116
@@ -1554,6 +1121,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1554 .pa_end = 0x4801a1ff, 1121 .pa_end = 0x4801a1ff,
1555 .flags = ADDR_TYPE_RT 1122 .flags = ADDR_TYPE_RT
1556 }, 1123 },
1124 { }
1557}; 1125};
1558 1126
1559static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 1127static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
@@ -1561,7 +1129,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1561 .slave = &omap2420_gpio2_hwmod, 1129 .slave = &omap2420_gpio2_hwmod,
1562 .clk = "gpios_ick", 1130 .clk = "gpios_ick",
1563 .addr = omap2420_gpio2_addr_space, 1131 .addr = omap2420_gpio2_addr_space,
1564 .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
1565 .user = OCP_USER_MPU | OCP_USER_SDMA, 1132 .user = OCP_USER_MPU | OCP_USER_SDMA,
1566}; 1133};
1567 1134
@@ -1572,6 +1139,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1572 .pa_end = 0x4801c1ff, 1139 .pa_end = 0x4801c1ff,
1573 .flags = ADDR_TYPE_RT 1140 .flags = ADDR_TYPE_RT
1574 }, 1141 },
1142 { }
1575}; 1143};
1576 1144
1577static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 1145static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
@@ -1579,7 +1147,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1579 .slave = &omap2420_gpio3_hwmod, 1147 .slave = &omap2420_gpio3_hwmod,
1580 .clk = "gpios_ick", 1148 .clk = "gpios_ick",
1581 .addr = omap2420_gpio3_addr_space, 1149 .addr = omap2420_gpio3_addr_space,
1582 .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
1583 .user = OCP_USER_MPU | OCP_USER_SDMA, 1150 .user = OCP_USER_MPU | OCP_USER_SDMA,
1584}; 1151};
1585 1152
@@ -1590,6 +1157,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1590 .pa_end = 0x4801e1ff, 1157 .pa_end = 0x4801e1ff,
1591 .flags = ADDR_TYPE_RT 1158 .flags = ADDR_TYPE_RT
1592 }, 1159 },
1160 { }
1593}; 1161};
1594 1162
1595static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 1163static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
@@ -1597,7 +1165,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1597 .slave = &omap2420_gpio4_hwmod, 1165 .slave = &omap2420_gpio4_hwmod,
1598 .clk = "gpios_ick", 1166 .clk = "gpios_ick",
1599 .addr = omap2420_gpio4_addr_space, 1167 .addr = omap2420_gpio4_addr_space,
1600 .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
1601 .user = OCP_USER_MPU | OCP_USER_SDMA, 1168 .user = OCP_USER_MPU | OCP_USER_SDMA,
1602}; 1169};
1603 1170
@@ -1607,32 +1174,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1607 .dbck_flag = false, 1174 .dbck_flag = false,
1608}; 1175};
1609 1176
1610static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1611 .rev_offs = 0x0000,
1612 .sysc_offs = 0x0010,
1613 .syss_offs = 0x0014,
1614 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1615 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1616 SYSS_HAS_RESET_STATUS),
1617 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1618 .sysc_fields = &omap_hwmod_sysc_type1,
1619};
1620
1621/*
1622 * 'gpio' class
1623 * general purpose io module
1624 */
1625static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1626 .name = "gpio",
1627 .sysc = &omap242x_gpio_sysc,
1628 .rev = 0,
1629};
1630
1631/* gpio1 */ 1177/* gpio1 */
1632static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
1633 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1634};
1635
1636static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { 1178static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1637 &omap2420_l4_wkup__gpio1, 1179 &omap2420_l4_wkup__gpio1,
1638}; 1180};
@@ -1640,8 +1182,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1640static struct omap_hwmod omap2420_gpio1_hwmod = { 1182static struct omap_hwmod omap2420_gpio1_hwmod = {
1641 .name = "gpio1", 1183 .name = "gpio1",
1642 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1184 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1643 .mpu_irqs = omap242x_gpio1_irqs, 1185 .mpu_irqs = omap2_gpio1_irqs,
1644 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
1645 .main_clk = "gpios_fck", 1186 .main_clk = "gpios_fck",
1646 .prcm = { 1187 .prcm = {
1647 .omap2 = { 1188 .omap2 = {
@@ -1654,16 +1195,12 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
1654 }, 1195 },
1655 .slaves = omap2420_gpio1_slaves, 1196 .slaves = omap2420_gpio1_slaves,
1656 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), 1197 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1657 .class = &omap242x_gpio_hwmod_class, 1198 .class = &omap2xxx_gpio_hwmod_class,
1658 .dev_attr = &gpio_dev_attr, 1199 .dev_attr = &gpio_dev_attr,
1659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1660}; 1201};
1661 1202
1662/* gpio2 */ 1203/* gpio2 */
1663static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
1664 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1665};
1666
1667static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { 1204static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1668 &omap2420_l4_wkup__gpio2, 1205 &omap2420_l4_wkup__gpio2,
1669}; 1206};
@@ -1671,8 +1208,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1671static struct omap_hwmod omap2420_gpio2_hwmod = { 1208static struct omap_hwmod omap2420_gpio2_hwmod = {
1672 .name = "gpio2", 1209 .name = "gpio2",
1673 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1210 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1674 .mpu_irqs = omap242x_gpio2_irqs, 1211 .mpu_irqs = omap2_gpio2_irqs,
1675 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
1676 .main_clk = "gpios_fck", 1212 .main_clk = "gpios_fck",
1677 .prcm = { 1213 .prcm = {
1678 .omap2 = { 1214 .omap2 = {
@@ -1685,16 +1221,12 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
1685 }, 1221 },
1686 .slaves = omap2420_gpio2_slaves, 1222 .slaves = omap2420_gpio2_slaves,
1687 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), 1223 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1688 .class = &omap242x_gpio_hwmod_class, 1224 .class = &omap2xxx_gpio_hwmod_class,
1689 .dev_attr = &gpio_dev_attr, 1225 .dev_attr = &gpio_dev_attr,
1690 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1691}; 1227};
1692 1228
1693/* gpio3 */ 1229/* gpio3 */
1694static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
1695 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1696};
1697
1698static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { 1230static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1699 &omap2420_l4_wkup__gpio3, 1231 &omap2420_l4_wkup__gpio3,
1700}; 1232};
@@ -1702,8 +1234,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1702static struct omap_hwmod omap2420_gpio3_hwmod = { 1234static struct omap_hwmod omap2420_gpio3_hwmod = {
1703 .name = "gpio3", 1235 .name = "gpio3",
1704 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1236 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1705 .mpu_irqs = omap242x_gpio3_irqs, 1237 .mpu_irqs = omap2_gpio3_irqs,
1706 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
1707 .main_clk = "gpios_fck", 1238 .main_clk = "gpios_fck",
1708 .prcm = { 1239 .prcm = {
1709 .omap2 = { 1240 .omap2 = {
@@ -1716,16 +1247,12 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
1716 }, 1247 },
1717 .slaves = omap2420_gpio3_slaves, 1248 .slaves = omap2420_gpio3_slaves,
1718 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), 1249 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1719 .class = &omap242x_gpio_hwmod_class, 1250 .class = &omap2xxx_gpio_hwmod_class,
1720 .dev_attr = &gpio_dev_attr, 1251 .dev_attr = &gpio_dev_attr,
1721 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1252 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1722}; 1253};
1723 1254
1724/* gpio4 */ 1255/* gpio4 */
1725static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
1726 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1727};
1728
1729static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { 1256static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1730 &omap2420_l4_wkup__gpio4, 1257 &omap2420_l4_wkup__gpio4,
1731}; 1258};
@@ -1733,8 +1260,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1733static struct omap_hwmod omap2420_gpio4_hwmod = { 1260static struct omap_hwmod omap2420_gpio4_hwmod = {
1734 .name = "gpio4", 1261 .name = "gpio4",
1735 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1262 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1736 .mpu_irqs = omap242x_gpio4_irqs, 1263 .mpu_irqs = omap2_gpio4_irqs,
1737 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
1738 .main_clk = "gpios_fck", 1264 .main_clk = "gpios_fck",
1739 .prcm = { 1265 .prcm = {
1740 .omap2 = { 1266 .omap2 = {
@@ -1747,28 +1273,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
1747 }, 1273 },
1748 .slaves = omap2420_gpio4_slaves, 1274 .slaves = omap2420_gpio4_slaves,
1749 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), 1275 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1750 .class = &omap242x_gpio_hwmod_class, 1276 .class = &omap2xxx_gpio_hwmod_class,
1751 .dev_attr = &gpio_dev_attr, 1277 .dev_attr = &gpio_dev_attr,
1752 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1753}; 1279};
1754 1280
1755/* system dma */
1756static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1757 .rev_offs = 0x0000,
1758 .sysc_offs = 0x002c,
1759 .syss_offs = 0x0028,
1760 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1761 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1762 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1763 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1764 .sysc_fields = &omap_hwmod_sysc_type1,
1765};
1766
1767static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1768 .name = "dma",
1769 .sysc = &omap2420_dma_sysc,
1770};
1771
1772/* dma attributes */ 1281/* dma attributes */
1773static struct omap_dma_dev_attr dma_dev_attr = { 1282static struct omap_dma_dev_attr dma_dev_attr = {
1774 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1283 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1776,21 +1285,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
1776 .lch_count = 32, 1285 .lch_count = 32,
1777}; 1286};
1778 1287
1779static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
1780 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1781 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1782 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1783 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1784};
1785
1786static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
1787 {
1788 .pa_start = 0x48056000,
1789 .pa_end = 0x48056fff,
1790 .flags = ADDR_TYPE_RT
1791 },
1792};
1793
1794/* dma_system -> L3 */ 1288/* dma_system -> L3 */
1795static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 1289static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1796 .master = &omap2420_dma_system_hwmod, 1290 .master = &omap2420_dma_system_hwmod,
@@ -1809,8 +1303,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1809 .master = &omap2420_l4_core_hwmod, 1303 .master = &omap2420_l4_core_hwmod,
1810 .slave = &omap2420_dma_system_hwmod, 1304 .slave = &omap2420_dma_system_hwmod,
1811 .clk = "sdma_ick", 1305 .clk = "sdma_ick",
1812 .addr = omap2420_dma_system_addrs, 1306 .addr = omap2_dma_system_addrs,
1813 .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
1814 .user = OCP_USER_MPU | OCP_USER_SDMA, 1307 .user = OCP_USER_MPU | OCP_USER_SDMA,
1815}; 1308};
1816 1309
@@ -1821,9 +1314,8 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1821 1314
1822static struct omap_hwmod omap2420_dma_system_hwmod = { 1315static struct omap_hwmod omap2420_dma_system_hwmod = {
1823 .name = "dma", 1316 .name = "dma",
1824 .class = &omap2420_dma_hwmod_class, 1317 .class = &omap2xxx_dma_hwmod_class,
1825 .mpu_irqs = omap2420_dma_system_irqs, 1318 .mpu_irqs = omap2_dma_system_irqs,
1826 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
1827 .main_clk = "core_l3_ck", 1319 .main_clk = "core_l3_ck",
1828 .slaves = omap2420_dma_system_slaves, 1320 .slaves = omap2420_dma_system_slaves,
1829 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), 1321 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
@@ -1834,48 +1326,19 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
1834 .flags = HWMOD_NO_IDLEST, 1326 .flags = HWMOD_NO_IDLEST,
1835}; 1327};
1836 1328
1837/*
1838 * 'mailbox' class
1839 * mailbox module allowing communication between the on-chip processors
1840 * using a queued mailbox-interrupt mechanism.
1841 */
1842
1843static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1844 .rev_offs = 0x000,
1845 .sysc_offs = 0x010,
1846 .syss_offs = 0x014,
1847 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1848 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1849 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1850 .sysc_fields = &omap_hwmod_sysc_type1,
1851};
1852
1853static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1854 .name = "mailbox",
1855 .sysc = &omap2420_mailbox_sysc,
1856};
1857
1858/* mailbox */ 1329/* mailbox */
1859static struct omap_hwmod omap2420_mailbox_hwmod; 1330static struct omap_hwmod omap2420_mailbox_hwmod;
1860static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 1331static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1861 { .name = "dsp", .irq = 26 }, 1332 { .name = "dsp", .irq = 26 },
1862 { .name = "iva", .irq = 34 }, 1333 { .name = "iva", .irq = 34 },
1863}; 1334 { .irq = -1 }
1864
1865static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
1866 {
1867 .pa_start = 0x48094000,
1868 .pa_end = 0x480941ff,
1869 .flags = ADDR_TYPE_RT,
1870 },
1871}; 1335};
1872 1336
1873/* l4_core -> mailbox */ 1337/* l4_core -> mailbox */
1874static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 1338static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1875 .master = &omap2420_l4_core_hwmod, 1339 .master = &omap2420_l4_core_hwmod,
1876 .slave = &omap2420_mailbox_hwmod, 1340 .slave = &omap2420_mailbox_hwmod,
1877 .addr = omap2420_mailbox_addrs, 1341 .addr = omap2_mailbox_addrs,
1878 .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
1879 .user = OCP_USER_MPU | OCP_USER_SDMA, 1342 .user = OCP_USER_MPU | OCP_USER_SDMA,
1880}; 1343};
1881 1344
@@ -1886,9 +1349,8 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1886 1349
1887static struct omap_hwmod omap2420_mailbox_hwmod = { 1350static struct omap_hwmod omap2420_mailbox_hwmod = {
1888 .name = "mailbox", 1351 .name = "mailbox",
1889 .class = &omap2420_mailbox_hwmod_class, 1352 .class = &omap2xxx_mailbox_hwmod_class,
1890 .mpu_irqs = omap2420_mailbox_irqs, 1353 .mpu_irqs = omap2420_mailbox_irqs,
1891 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
1892 .main_clk = "mailboxes_ick", 1354 .main_clk = "mailboxes_ick",
1893 .prcm = { 1355 .prcm = {
1894 .omap2 = { 1356 .omap2 = {
@@ -1904,45 +1366,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
1904 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1905}; 1367};
1906 1368
1907/*
1908 * 'mcspi' class
1909 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1910 * bus
1911 */
1912
1913static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1914 .rev_offs = 0x0000,
1915 .sysc_offs = 0x0010,
1916 .syss_offs = 0x0014,
1917 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1918 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1919 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1921 .sysc_fields = &omap_hwmod_sysc_type1,
1922};
1923
1924static struct omap_hwmod_class omap2420_mcspi_class = {
1925 .name = "mcspi",
1926 .sysc = &omap2420_mcspi_sysc,
1927 .rev = OMAP2_MCSPI_REV,
1928};
1929
1930/* mcspi1 */ 1369/* mcspi1 */
1931static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
1932 { .irq = 65 },
1933};
1934
1935static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
1936 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1937 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1938 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1939 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1940 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1941 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1942 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1943 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1944};
1945
1946static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { 1370static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1947 &omap2420_l4_core__mcspi1, 1371 &omap2420_l4_core__mcspi1,
1948}; 1372};
@@ -1953,10 +1377,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1953 1377
1954static struct omap_hwmod omap2420_mcspi1_hwmod = { 1378static struct omap_hwmod omap2420_mcspi1_hwmod = {
1955 .name = "mcspi1_hwmod", 1379 .name = "mcspi1_hwmod",
1956 .mpu_irqs = omap2420_mcspi1_mpu_irqs, 1380 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1957 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), 1381 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1958 .sdma_reqs = omap2420_mcspi1_sdma_reqs,
1959 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
1960 .main_clk = "mcspi1_fck", 1382 .main_clk = "mcspi1_fck",
1961 .prcm = { 1383 .prcm = {
1962 .omap2 = { 1384 .omap2 = {
@@ -1969,23 +1391,12 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
1969 }, 1391 },
1970 .slaves = omap2420_mcspi1_slaves, 1392 .slaves = omap2420_mcspi1_slaves,
1971 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), 1393 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1972 .class = &omap2420_mcspi_class, 1394 .class = &omap2xxx_mcspi_class,
1973 .dev_attr = &omap_mcspi1_dev_attr, 1395 .dev_attr = &omap_mcspi1_dev_attr,
1974 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1396 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1975}; 1397};
1976 1398
1977/* mcspi2 */ 1399/* mcspi2 */
1978static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
1979 { .irq = 66 },
1980};
1981
1982static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
1983 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1984 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1985 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1986 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1987};
1988
1989static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { 1400static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1990 &omap2420_l4_core__mcspi2, 1401 &omap2420_l4_core__mcspi2,
1991}; 1402};
@@ -1996,10 +1407,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1996 1407
1997static struct omap_hwmod omap2420_mcspi2_hwmod = { 1408static struct omap_hwmod omap2420_mcspi2_hwmod = {
1998 .name = "mcspi2_hwmod", 1409 .name = "mcspi2_hwmod",
1999 .mpu_irqs = omap2420_mcspi2_mpu_irqs, 1410 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2000 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), 1411 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2001 .sdma_reqs = omap2420_mcspi2_sdma_reqs,
2002 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
2003 .main_clk = "mcspi2_fck", 1412 .main_clk = "mcspi2_fck",
2004 .prcm = { 1413 .prcm = {
2005 .omap2 = { 1414 .omap2 = {
@@ -2012,8 +1421,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
2012 }, 1421 },
2013 .slaves = omap2420_mcspi2_slaves, 1422 .slaves = omap2420_mcspi2_slaves,
2014 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), 1423 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
2015 .class = &omap2420_mcspi_class, 1424 .class = &omap2xxx_mcspi_class,
2016 .dev_attr = &omap_mcspi2_dev_attr, 1425 .dev_attr = &omap_mcspi2_dev_attr,
2017 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1426 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2018}; 1427};
2019 1428
@@ -2030,20 +1439,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
2030static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { 1439static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
2031 { .name = "tx", .irq = 59 }, 1440 { .name = "tx", .irq = 59 },
2032 { .name = "rx", .irq = 60 }, 1441 { .name = "rx", .irq = 60 },
2033}; 1442 { .irq = -1 }
2034
2035static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
2036 { .name = "rx", .dma_req = 32 },
2037 { .name = "tx", .dma_req = 31 },
2038};
2039
2040static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
2041 {
2042 .name = "mpu",
2043 .pa_start = 0x48074000,
2044 .pa_end = 0x480740ff,
2045 .flags = ADDR_TYPE_RT
2046 },
2047}; 1443};
2048 1444
2049/* l4_core -> mcbsp1 */ 1445/* l4_core -> mcbsp1 */
@@ -2051,8 +1447,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
2051 .master = &omap2420_l4_core_hwmod, 1447 .master = &omap2420_l4_core_hwmod,
2052 .slave = &omap2420_mcbsp1_hwmod, 1448 .slave = &omap2420_mcbsp1_hwmod,
2053 .clk = "mcbsp1_ick", 1449 .clk = "mcbsp1_ick",
2054 .addr = omap2420_mcbsp1_addrs, 1450 .addr = omap2_mcbsp1_addrs,
2055 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
2056 .user = OCP_USER_MPU | OCP_USER_SDMA, 1451 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057}; 1452};
2058 1453
@@ -2065,9 +1460,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2065 .name = "mcbsp1", 1460 .name = "mcbsp1",
2066 .class = &omap2420_mcbsp_hwmod_class, 1461 .class = &omap2420_mcbsp_hwmod_class,
2067 .mpu_irqs = omap2420_mcbsp1_irqs, 1462 .mpu_irqs = omap2420_mcbsp1_irqs,
2068 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), 1463 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2069 .sdma_reqs = omap2420_mcbsp1_sdma_chs,
2070 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
2071 .main_clk = "mcbsp1_fck", 1464 .main_clk = "mcbsp1_fck",
2072 .prcm = { 1465 .prcm = {
2073 .omap2 = { 1466 .omap2 = {
@@ -2087,20 +1480,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2087static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { 1480static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
2088 { .name = "tx", .irq = 62 }, 1481 { .name = "tx", .irq = 62 },
2089 { .name = "rx", .irq = 63 }, 1482 { .name = "rx", .irq = 63 },
2090}; 1483 { .irq = -1 }
2091
2092static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
2093 { .name = "rx", .dma_req = 34 },
2094 { .name = "tx", .dma_req = 33 },
2095};
2096
2097static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
2098 {
2099 .name = "mpu",
2100 .pa_start = 0x48076000,
2101 .pa_end = 0x480760ff,
2102 .flags = ADDR_TYPE_RT
2103 },
2104}; 1484};
2105 1485
2106/* l4_core -> mcbsp2 */ 1486/* l4_core -> mcbsp2 */
@@ -2108,8 +1488,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
2108 .master = &omap2420_l4_core_hwmod, 1488 .master = &omap2420_l4_core_hwmod,
2109 .slave = &omap2420_mcbsp2_hwmod, 1489 .slave = &omap2420_mcbsp2_hwmod,
2110 .clk = "mcbsp2_ick", 1490 .clk = "mcbsp2_ick",
2111 .addr = omap2420_mcbsp2_addrs, 1491 .addr = omap2xxx_mcbsp2_addrs,
2112 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
2113 .user = OCP_USER_MPU | OCP_USER_SDMA, 1492 .user = OCP_USER_MPU | OCP_USER_SDMA,
2114}; 1493};
2115 1494
@@ -2122,9 +1501,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
2122 .name = "mcbsp2", 1501 .name = "mcbsp2",
2123 .class = &omap2420_mcbsp_hwmod_class, 1502 .class = &omap2420_mcbsp_hwmod_class,
2124 .mpu_irqs = omap2420_mcbsp2_irqs, 1503 .mpu_irqs = omap2420_mcbsp2_irqs,
2125 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), 1504 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2126 .sdma_reqs = omap2420_mcbsp2_sdma_chs,
2127 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
2128 .main_clk = "mcbsp2_fck", 1505 .main_clk = "mcbsp2_fck",
2129 .prcm = { 1506 .prcm = {
2130 .omap2 = { 1507 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 9682dd519f8d..16743c7d6e8e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
131 .user = OCP_USER_MPU, 131 .user = OCP_USER_MPU,
132}; 132};
133 133
134/* I2C IP block address space length (in bytes) */
135#define OMAP2_I2C_AS_LEN 128
136
137/* L4 CORE -> I2C1 interface */ 134/* L4 CORE -> I2C1 interface */
138static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
139 {
140 .pa_start = 0x48070000,
141 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
142 .flags = ADDR_TYPE_RT,
143 },
144};
145
146static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 135static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
147 .master = &omap2430_l4_core_hwmod, 136 .master = &omap2430_l4_core_hwmod,
148 .slave = &omap2430_i2c1_hwmod, 137 .slave = &omap2430_i2c1_hwmod,
149 .clk = "i2c1_ick", 138 .clk = "i2c1_ick",
150 .addr = omap2430_i2c1_addr_space, 139 .addr = omap2_i2c1_addr_space,
151 .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
152 .user = OCP_USER_MPU | OCP_USER_SDMA, 140 .user = OCP_USER_MPU | OCP_USER_SDMA,
153}; 141};
154 142
155/* L4 CORE -> I2C2 interface */ 143/* L4 CORE -> I2C2 interface */
156static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
157 {
158 .pa_start = 0x48072000,
159 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
160 .flags = ADDR_TYPE_RT,
161 },
162};
163
164static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 144static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
165 .master = &omap2430_l4_core_hwmod, 145 .master = &omap2430_l4_core_hwmod,
166 .slave = &omap2430_i2c2_hwmod, 146 .slave = &omap2430_i2c2_hwmod,
167 .clk = "i2c2_ick", 147 .clk = "i2c2_ick",
168 .addr = omap2430_i2c2_addr_space, 148 .addr = omap2_i2c2_addr_space,
169 .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
170 .user = OCP_USER_MPU | OCP_USER_SDMA, 149 .user = OCP_USER_MPU | OCP_USER_SDMA,
171}; 150};
172 151
@@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
178}; 157};
179 158
180/* L4 CORE -> UART1 interface */ 159/* L4 CORE -> UART1 interface */
181static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
182 {
183 .pa_start = OMAP2_UART1_BASE,
184 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
185 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
186 },
187};
188
189static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 160static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
190 .master = &omap2430_l4_core_hwmod, 161 .master = &omap2430_l4_core_hwmod,
191 .slave = &omap2430_uart1_hwmod, 162 .slave = &omap2430_uart1_hwmod,
192 .clk = "uart1_ick", 163 .clk = "uart1_ick",
193 .addr = omap2430_uart1_addr_space, 164 .addr = omap2xxx_uart1_addr_space,
194 .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
195 .user = OCP_USER_MPU | OCP_USER_SDMA, 165 .user = OCP_USER_MPU | OCP_USER_SDMA,
196}; 166};
197 167
198/* L4 CORE -> UART2 interface */ 168/* L4 CORE -> UART2 interface */
199static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
200 {
201 .pa_start = OMAP2_UART2_BASE,
202 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
203 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
204 },
205};
206
207static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 169static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
208 .master = &omap2430_l4_core_hwmod, 170 .master = &omap2430_l4_core_hwmod,
209 .slave = &omap2430_uart2_hwmod, 171 .slave = &omap2430_uart2_hwmod,
210 .clk = "uart2_ick", 172 .clk = "uart2_ick",
211 .addr = omap2430_uart2_addr_space, 173 .addr = omap2xxx_uart2_addr_space,
212 .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
213 .user = OCP_USER_MPU | OCP_USER_SDMA, 174 .user = OCP_USER_MPU | OCP_USER_SDMA,
214}; 175};
215 176
216/* L4 PER -> UART3 interface */ 177/* L4 PER -> UART3 interface */
217static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
218 {
219 .pa_start = OMAP2_UART3_BASE,
220 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
221 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
222 },
223};
224
225static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 178static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
226 .master = &omap2430_l4_core_hwmod, 179 .master = &omap2430_l4_core_hwmod,
227 .slave = &omap2430_uart3_hwmod, 180 .slave = &omap2430_uart3_hwmod,
228 .clk = "uart3_ick", 181 .clk = "uart3_ick",
229 .addr = omap2430_uart3_addr_space, 182 .addr = omap2xxx_uart3_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 .user = OCP_USER_MPU | OCP_USER_SDMA,
232}; 184};
233 185
@@ -248,7 +200,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
248 .slave = &omap2430_usbhsotg_hwmod, 200 .slave = &omap2430_usbhsotg_hwmod,
249 .clk = "usb_l4_ick", 201 .clk = "usb_l4_ick",
250 .addr = omap2430_usbhsotg_addrs, 202 .addr = omap2430_usbhsotg_addrs,
251 .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
252 .user = OCP_USER_MPU, 203 .user = OCP_USER_MPU,
253}; 204};
254 205
@@ -261,38 +212,20 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
261}; 212};
262 213
263/* L4 CORE -> MMC1 interface */ 214/* L4 CORE -> MMC1 interface */
264static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
265 {
266 .pa_start = 0x4809c000,
267 .pa_end = 0x4809c1ff,
268 .flags = ADDR_TYPE_RT,
269 },
270};
271
272static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { 215static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
273 .master = &omap2430_l4_core_hwmod, 216 .master = &omap2430_l4_core_hwmod,
274 .slave = &omap2430_mmc1_hwmod, 217 .slave = &omap2430_mmc1_hwmod,
275 .clk = "mmchs1_ick", 218 .clk = "mmchs1_ick",
276 .addr = omap2430_mmc1_addr_space, 219 .addr = omap2430_mmc1_addr_space,
277 .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
278 .user = OCP_USER_MPU | OCP_USER_SDMA, 220 .user = OCP_USER_MPU | OCP_USER_SDMA,
279}; 221};
280 222
281/* L4 CORE -> MMC2 interface */ 223/* L4 CORE -> MMC2 interface */
282static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
283 {
284 .pa_start = 0x480b4000,
285 .pa_end = 0x480b41ff,
286 .flags = ADDR_TYPE_RT,
287 },
288};
289
290static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { 224static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
291 .master = &omap2430_l4_core_hwmod, 225 .master = &omap2430_l4_core_hwmod,
292 .slave = &omap2430_mmc2_hwmod, 226 .slave = &omap2430_mmc2_hwmod,
293 .addr = omap2430_mmc2_addr_space,
294 .clk = "mmchs2_ick", 227 .clk = "mmchs2_ick",
295 .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space), 228 .addr = omap2430_mmc2_addr_space,
296 .user = OCP_USER_MPU | OCP_USER_SDMA, 229 .user = OCP_USER_MPU | OCP_USER_SDMA,
297}; 230};
298 231
@@ -333,56 +266,29 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
333}; 266};
334 267
335/* l4 core -> mcspi1 interface */ 268/* l4 core -> mcspi1 interface */
336static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
337 {
338 .pa_start = 0x48098000,
339 .pa_end = 0x480980ff,
340 .flags = ADDR_TYPE_RT,
341 },
342};
343
344static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { 269static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
345 .master = &omap2430_l4_core_hwmod, 270 .master = &omap2430_l4_core_hwmod,
346 .slave = &omap2430_mcspi1_hwmod, 271 .slave = &omap2430_mcspi1_hwmod,
347 .clk = "mcspi1_ick", 272 .clk = "mcspi1_ick",
348 .addr = omap2430_mcspi1_addr_space, 273 .addr = omap2_mcspi1_addr_space,
349 .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
350 .user = OCP_USER_MPU | OCP_USER_SDMA, 274 .user = OCP_USER_MPU | OCP_USER_SDMA,
351}; 275};
352 276
353/* l4 core -> mcspi2 interface */ 277/* l4 core -> mcspi2 interface */
354static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
355 {
356 .pa_start = 0x4809a000,
357 .pa_end = 0x4809a0ff,
358 .flags = ADDR_TYPE_RT,
359 },
360};
361
362static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { 278static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
363 .master = &omap2430_l4_core_hwmod, 279 .master = &omap2430_l4_core_hwmod,
364 .slave = &omap2430_mcspi2_hwmod, 280 .slave = &omap2430_mcspi2_hwmod,
365 .clk = "mcspi2_ick", 281 .clk = "mcspi2_ick",
366 .addr = omap2430_mcspi2_addr_space, 282 .addr = omap2_mcspi2_addr_space,
367 .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
368 .user = OCP_USER_MPU | OCP_USER_SDMA, 283 .user = OCP_USER_MPU | OCP_USER_SDMA,
369}; 284};
370 285
371/* l4 core -> mcspi3 interface */ 286/* l4 core -> mcspi3 interface */
372static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
373 {
374 .pa_start = 0x480b8000,
375 .pa_end = 0x480b80ff,
376 .flags = ADDR_TYPE_RT,
377 },
378};
379
380static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 287static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
381 .master = &omap2430_l4_core_hwmod, 288 .master = &omap2430_l4_core_hwmod,
382 .slave = &omap2430_mcspi3_hwmod, 289 .slave = &omap2430_mcspi3_hwmod,
383 .clk = "mcspi3_ick", 290 .clk = "mcspi3_ick",
384 .addr = omap2430_mcspi3_addr_space, 291 .addr = omap2430_mcspi3_addr_space,
385 .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
386 .user = OCP_USER_MPU | OCP_USER_SDMA, 292 .user = OCP_USER_MPU | OCP_USER_SDMA,
387}; 293};
388 294
@@ -441,29 +347,8 @@ static struct omap_hwmod omap2430_iva_hwmod = {
441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
442}; 348};
443 349
444/* Timer Common */
445static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
446 .rev_offs = 0x0000,
447 .sysc_offs = 0x0010,
448 .syss_offs = 0x0014,
449 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
450 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
451 SYSC_HAS_AUTOIDLE),
452 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454};
455
456static struct omap_hwmod_class omap2430_timer_hwmod_class = {
457 .name = "timer",
458 .sysc = &omap2430_timer_sysc,
459 .rev = OMAP_TIMER_IP_VERSION_1,
460};
461
462/* timer1 */ 350/* timer1 */
463static struct omap_hwmod omap2430_timer1_hwmod; 351static struct omap_hwmod omap2430_timer1_hwmod;
464static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
465 { .irq = 37, },
466};
467 352
468static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { 353static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
469 { 354 {
@@ -471,6 +356,7 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
471 .pa_end = 0x49018000 + SZ_1K - 1, 356 .pa_end = 0x49018000 + SZ_1K - 1,
472 .flags = ADDR_TYPE_RT 357 .flags = ADDR_TYPE_RT
473 }, 358 },
359 { }
474}; 360};
475 361
476/* l4_wkup -> timer1 */ 362/* l4_wkup -> timer1 */
@@ -479,7 +365,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
479 .slave = &omap2430_timer1_hwmod, 365 .slave = &omap2430_timer1_hwmod,
480 .clk = "gpt1_ick", 366 .clk = "gpt1_ick",
481 .addr = omap2430_timer1_addrs, 367 .addr = omap2430_timer1_addrs,
482 .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
483 .user = OCP_USER_MPU | OCP_USER_SDMA, 368 .user = OCP_USER_MPU | OCP_USER_SDMA,
484}; 369};
485 370
@@ -491,8 +376,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
491/* timer1 hwmod */ 376/* timer1 hwmod */
492static struct omap_hwmod omap2430_timer1_hwmod = { 377static struct omap_hwmod omap2430_timer1_hwmod = {
493 .name = "timer1", 378 .name = "timer1",
494 .mpu_irqs = omap2430_timer1_mpu_irqs, 379 .mpu_irqs = omap2_timer1_mpu_irqs,
495 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
496 .main_clk = "gpt1_fck", 380 .main_clk = "gpt1_fck",
497 .prcm = { 381 .prcm = {
498 .omap2 = { 382 .omap2 = {
@@ -505,31 +389,19 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
505 }, 389 },
506 .slaves = omap2430_timer1_slaves, 390 .slaves = omap2430_timer1_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), 391 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
508 .class = &omap2430_timer_hwmod_class, 392 .class = &omap2xxx_timer_hwmod_class,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
510}; 394};
511 395
512/* timer2 */ 396/* timer2 */
513static struct omap_hwmod omap2430_timer2_hwmod; 397static struct omap_hwmod omap2430_timer2_hwmod;
514static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
515 { .irq = 38, },
516};
517
518static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
519 {
520 .pa_start = 0x4802a000,
521 .pa_end = 0x4802a000 + SZ_1K - 1,
522 .flags = ADDR_TYPE_RT
523 },
524};
525 398
526/* l4_core -> timer2 */ 399/* l4_core -> timer2 */
527static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { 400static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
528 .master = &omap2430_l4_core_hwmod, 401 .master = &omap2430_l4_core_hwmod,
529 .slave = &omap2430_timer2_hwmod, 402 .slave = &omap2430_timer2_hwmod,
530 .clk = "gpt2_ick", 403 .clk = "gpt2_ick",
531 .addr = omap2430_timer2_addrs, 404 .addr = omap2xxx_timer2_addrs,
532 .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
533 .user = OCP_USER_MPU | OCP_USER_SDMA, 405 .user = OCP_USER_MPU | OCP_USER_SDMA,
534}; 406};
535 407
@@ -541,8 +413,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
541/* timer2 hwmod */ 413/* timer2 hwmod */
542static struct omap_hwmod omap2430_timer2_hwmod = { 414static struct omap_hwmod omap2430_timer2_hwmod = {
543 .name = "timer2", 415 .name = "timer2",
544 .mpu_irqs = omap2430_timer2_mpu_irqs, 416 .mpu_irqs = omap2_timer2_mpu_irqs,
545 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
546 .main_clk = "gpt2_fck", 417 .main_clk = "gpt2_fck",
547 .prcm = { 418 .prcm = {
548 .omap2 = { 419 .omap2 = {
@@ -555,31 +426,19 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
555 }, 426 },
556 .slaves = omap2430_timer2_slaves, 427 .slaves = omap2430_timer2_slaves,
557 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), 428 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
558 .class = &omap2430_timer_hwmod_class, 429 .class = &omap2xxx_timer_hwmod_class,
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 430 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
560}; 431};
561 432
562/* timer3 */ 433/* timer3 */
563static struct omap_hwmod omap2430_timer3_hwmod; 434static struct omap_hwmod omap2430_timer3_hwmod;
564static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
565 { .irq = 39, },
566};
567
568static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
569 {
570 .pa_start = 0x48078000,
571 .pa_end = 0x48078000 + SZ_1K - 1,
572 .flags = ADDR_TYPE_RT
573 },
574};
575 435
576/* l4_core -> timer3 */ 436/* l4_core -> timer3 */
577static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { 437static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
578 .master = &omap2430_l4_core_hwmod, 438 .master = &omap2430_l4_core_hwmod,
579 .slave = &omap2430_timer3_hwmod, 439 .slave = &omap2430_timer3_hwmod,
580 .clk = "gpt3_ick", 440 .clk = "gpt3_ick",
581 .addr = omap2430_timer3_addrs, 441 .addr = omap2xxx_timer3_addrs,
582 .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
583 .user = OCP_USER_MPU | OCP_USER_SDMA, 442 .user = OCP_USER_MPU | OCP_USER_SDMA,
584}; 443};
585 444
@@ -591,8 +450,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
591/* timer3 hwmod */ 450/* timer3 hwmod */
592static struct omap_hwmod omap2430_timer3_hwmod = { 451static struct omap_hwmod omap2430_timer3_hwmod = {
593 .name = "timer3", 452 .name = "timer3",
594 .mpu_irqs = omap2430_timer3_mpu_irqs, 453 .mpu_irqs = omap2_timer3_mpu_irqs,
595 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
596 .main_clk = "gpt3_fck", 454 .main_clk = "gpt3_fck",
597 .prcm = { 455 .prcm = {
598 .omap2 = { 456 .omap2 = {
@@ -605,31 +463,19 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
605 }, 463 },
606 .slaves = omap2430_timer3_slaves, 464 .slaves = omap2430_timer3_slaves,
607 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), 465 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
608 .class = &omap2430_timer_hwmod_class, 466 .class = &omap2xxx_timer_hwmod_class,
609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 467 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
610}; 468};
611 469
612/* timer4 */ 470/* timer4 */
613static struct omap_hwmod omap2430_timer4_hwmod; 471static struct omap_hwmod omap2430_timer4_hwmod;
614static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
615 { .irq = 40, },
616};
617
618static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
619 {
620 .pa_start = 0x4807a000,
621 .pa_end = 0x4807a000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625 472
626/* l4_core -> timer4 */ 473/* l4_core -> timer4 */
627static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { 474static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
628 .master = &omap2430_l4_core_hwmod, 475 .master = &omap2430_l4_core_hwmod,
629 .slave = &omap2430_timer4_hwmod, 476 .slave = &omap2430_timer4_hwmod,
630 .clk = "gpt4_ick", 477 .clk = "gpt4_ick",
631 .addr = omap2430_timer4_addrs, 478 .addr = omap2xxx_timer4_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 479 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 480};
635 481
@@ -641,8 +487,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
641/* timer4 hwmod */ 487/* timer4 hwmod */
642static struct omap_hwmod omap2430_timer4_hwmod = { 488static struct omap_hwmod omap2430_timer4_hwmod = {
643 .name = "timer4", 489 .name = "timer4",
644 .mpu_irqs = omap2430_timer4_mpu_irqs, 490 .mpu_irqs = omap2_timer4_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
646 .main_clk = "gpt4_fck", 491 .main_clk = "gpt4_fck",
647 .prcm = { 492 .prcm = {
648 .omap2 = { 493 .omap2 = {
@@ -655,31 +500,19 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
655 }, 500 },
656 .slaves = omap2430_timer4_slaves, 501 .slaves = omap2430_timer4_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), 502 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
658 .class = &omap2430_timer_hwmod_class, 503 .class = &omap2xxx_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 504 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
660}; 505};
661 506
662/* timer5 */ 507/* timer5 */
663static struct omap_hwmod omap2430_timer5_hwmod; 508static struct omap_hwmod omap2430_timer5_hwmod;
664static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
665 { .irq = 41, },
666};
667
668static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
669 {
670 .pa_start = 0x4807c000,
671 .pa_end = 0x4807c000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675 509
676/* l4_core -> timer5 */ 510/* l4_core -> timer5 */
677static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { 511static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
678 .master = &omap2430_l4_core_hwmod, 512 .master = &omap2430_l4_core_hwmod,
679 .slave = &omap2430_timer5_hwmod, 513 .slave = &omap2430_timer5_hwmod,
680 .clk = "gpt5_ick", 514 .clk = "gpt5_ick",
681 .addr = omap2430_timer5_addrs, 515 .addr = omap2xxx_timer5_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 516 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 517};
685 518
@@ -691,8 +524,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
691/* timer5 hwmod */ 524/* timer5 hwmod */
692static struct omap_hwmod omap2430_timer5_hwmod = { 525static struct omap_hwmod omap2430_timer5_hwmod = {
693 .name = "timer5", 526 .name = "timer5",
694 .mpu_irqs = omap2430_timer5_mpu_irqs, 527 .mpu_irqs = omap2_timer5_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
696 .main_clk = "gpt5_fck", 528 .main_clk = "gpt5_fck",
697 .prcm = { 529 .prcm = {
698 .omap2 = { 530 .omap2 = {
@@ -705,31 +537,19 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
705 }, 537 },
706 .slaves = omap2430_timer5_slaves, 538 .slaves = omap2430_timer5_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), 539 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
708 .class = &omap2430_timer_hwmod_class, 540 .class = &omap2xxx_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 541 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
710}; 542};
711 543
712/* timer6 */ 544/* timer6 */
713static struct omap_hwmod omap2430_timer6_hwmod; 545static struct omap_hwmod omap2430_timer6_hwmod;
714static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
715 { .irq = 42, },
716};
717
718static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
719 {
720 .pa_start = 0x4807e000,
721 .pa_end = 0x4807e000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725 546
726/* l4_core -> timer6 */ 547/* l4_core -> timer6 */
727static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { 548static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
728 .master = &omap2430_l4_core_hwmod, 549 .master = &omap2430_l4_core_hwmod,
729 .slave = &omap2430_timer6_hwmod, 550 .slave = &omap2430_timer6_hwmod,
730 .clk = "gpt6_ick", 551 .clk = "gpt6_ick",
731 .addr = omap2430_timer6_addrs, 552 .addr = omap2xxx_timer6_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 553 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 554};
735 555
@@ -741,8 +561,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
741/* timer6 hwmod */ 561/* timer6 hwmod */
742static struct omap_hwmod omap2430_timer6_hwmod = { 562static struct omap_hwmod omap2430_timer6_hwmod = {
743 .name = "timer6", 563 .name = "timer6",
744 .mpu_irqs = omap2430_timer6_mpu_irqs, 564 .mpu_irqs = omap2_timer6_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
746 .main_clk = "gpt6_fck", 565 .main_clk = "gpt6_fck",
747 .prcm = { 566 .prcm = {
748 .omap2 = { 567 .omap2 = {
@@ -755,31 +574,19 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
755 }, 574 },
756 .slaves = omap2430_timer6_slaves, 575 .slaves = omap2430_timer6_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), 576 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
758 .class = &omap2430_timer_hwmod_class, 577 .class = &omap2xxx_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 578 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
760}; 579};
761 580
762/* timer7 */ 581/* timer7 */
763static struct omap_hwmod omap2430_timer7_hwmod; 582static struct omap_hwmod omap2430_timer7_hwmod;
764static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
765 { .irq = 43, },
766};
767
768static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
769 {
770 .pa_start = 0x48080000,
771 .pa_end = 0x48080000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775 583
776/* l4_core -> timer7 */ 584/* l4_core -> timer7 */
777static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { 585static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
778 .master = &omap2430_l4_core_hwmod, 586 .master = &omap2430_l4_core_hwmod,
779 .slave = &omap2430_timer7_hwmod, 587 .slave = &omap2430_timer7_hwmod,
780 .clk = "gpt7_ick", 588 .clk = "gpt7_ick",
781 .addr = omap2430_timer7_addrs, 589 .addr = omap2xxx_timer7_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 590 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 591};
785 592
@@ -791,8 +598,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
791/* timer7 hwmod */ 598/* timer7 hwmod */
792static struct omap_hwmod omap2430_timer7_hwmod = { 599static struct omap_hwmod omap2430_timer7_hwmod = {
793 .name = "timer7", 600 .name = "timer7",
794 .mpu_irqs = omap2430_timer7_mpu_irqs, 601 .mpu_irqs = omap2_timer7_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
796 .main_clk = "gpt7_fck", 602 .main_clk = "gpt7_fck",
797 .prcm = { 603 .prcm = {
798 .omap2 = { 604 .omap2 = {
@@ -805,31 +611,19 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
805 }, 611 },
806 .slaves = omap2430_timer7_slaves, 612 .slaves = omap2430_timer7_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), 613 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
808 .class = &omap2430_timer_hwmod_class, 614 .class = &omap2xxx_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 615 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
810}; 616};
811 617
812/* timer8 */ 618/* timer8 */
813static struct omap_hwmod omap2430_timer8_hwmod; 619static struct omap_hwmod omap2430_timer8_hwmod;
814static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
815 { .irq = 44, },
816};
817
818static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
819 {
820 .pa_start = 0x48082000,
821 .pa_end = 0x48082000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825 620
826/* l4_core -> timer8 */ 621/* l4_core -> timer8 */
827static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { 622static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
828 .master = &omap2430_l4_core_hwmod, 623 .master = &omap2430_l4_core_hwmod,
829 .slave = &omap2430_timer8_hwmod, 624 .slave = &omap2430_timer8_hwmod,
830 .clk = "gpt8_ick", 625 .clk = "gpt8_ick",
831 .addr = omap2430_timer8_addrs, 626 .addr = omap2xxx_timer8_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 627 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 628};
835 629
@@ -841,8 +635,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
841/* timer8 hwmod */ 635/* timer8 hwmod */
842static struct omap_hwmod omap2430_timer8_hwmod = { 636static struct omap_hwmod omap2430_timer8_hwmod = {
843 .name = "timer8", 637 .name = "timer8",
844 .mpu_irqs = omap2430_timer8_mpu_irqs, 638 .mpu_irqs = omap2_timer8_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
846 .main_clk = "gpt8_fck", 639 .main_clk = "gpt8_fck",
847 .prcm = { 640 .prcm = {
848 .omap2 = { 641 .omap2 = {
@@ -855,31 +648,19 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
855 }, 648 },
856 .slaves = omap2430_timer8_slaves, 649 .slaves = omap2430_timer8_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), 650 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
858 .class = &omap2430_timer_hwmod_class, 651 .class = &omap2xxx_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 652 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
860}; 653};
861 654
862/* timer9 */ 655/* timer9 */
863static struct omap_hwmod omap2430_timer9_hwmod; 656static struct omap_hwmod omap2430_timer9_hwmod;
864static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
865 { .irq = 45, },
866};
867
868static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
869 {
870 .pa_start = 0x48084000,
871 .pa_end = 0x48084000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875 657
876/* l4_core -> timer9 */ 658/* l4_core -> timer9 */
877static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { 659static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
878 .master = &omap2430_l4_core_hwmod, 660 .master = &omap2430_l4_core_hwmod,
879 .slave = &omap2430_timer9_hwmod, 661 .slave = &omap2430_timer9_hwmod,
880 .clk = "gpt9_ick", 662 .clk = "gpt9_ick",
881 .addr = omap2430_timer9_addrs, 663 .addr = omap2xxx_timer9_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 664 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 665};
885 666
@@ -891,8 +672,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
891/* timer9 hwmod */ 672/* timer9 hwmod */
892static struct omap_hwmod omap2430_timer9_hwmod = { 673static struct omap_hwmod omap2430_timer9_hwmod = {
893 .name = "timer9", 674 .name = "timer9",
894 .mpu_irqs = omap2430_timer9_mpu_irqs, 675 .mpu_irqs = omap2_timer9_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
896 .main_clk = "gpt9_fck", 676 .main_clk = "gpt9_fck",
897 .prcm = { 677 .prcm = {
898 .omap2 = { 678 .omap2 = {
@@ -905,31 +685,19 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
905 }, 685 },
906 .slaves = omap2430_timer9_slaves, 686 .slaves = omap2430_timer9_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), 687 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
908 .class = &omap2430_timer_hwmod_class, 688 .class = &omap2xxx_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 689 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
910}; 690};
911 691
912/* timer10 */ 692/* timer10 */
913static struct omap_hwmod omap2430_timer10_hwmod; 693static struct omap_hwmod omap2430_timer10_hwmod;
914static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
915 { .irq = 46, },
916};
917
918static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
919 {
920 .pa_start = 0x48086000,
921 .pa_end = 0x48086000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925 694
926/* l4_core -> timer10 */ 695/* l4_core -> timer10 */
927static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { 696static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
928 .master = &omap2430_l4_core_hwmod, 697 .master = &omap2430_l4_core_hwmod,
929 .slave = &omap2430_timer10_hwmod, 698 .slave = &omap2430_timer10_hwmod,
930 .clk = "gpt10_ick", 699 .clk = "gpt10_ick",
931 .addr = omap2430_timer10_addrs, 700 .addr = omap2_timer10_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 701 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 702};
935 703
@@ -941,8 +709,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
941/* timer10 hwmod */ 709/* timer10 hwmod */
942static struct omap_hwmod omap2430_timer10_hwmod = { 710static struct omap_hwmod omap2430_timer10_hwmod = {
943 .name = "timer10", 711 .name = "timer10",
944 .mpu_irqs = omap2430_timer10_mpu_irqs, 712 .mpu_irqs = omap2_timer10_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
946 .main_clk = "gpt10_fck", 713 .main_clk = "gpt10_fck",
947 .prcm = { 714 .prcm = {
948 .omap2 = { 715 .omap2 = {
@@ -955,31 +722,19 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
955 }, 722 },
956 .slaves = omap2430_timer10_slaves, 723 .slaves = omap2430_timer10_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), 724 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
958 .class = &omap2430_timer_hwmod_class, 725 .class = &omap2xxx_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 726 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
960}; 727};
961 728
962/* timer11 */ 729/* timer11 */
963static struct omap_hwmod omap2430_timer11_hwmod; 730static struct omap_hwmod omap2430_timer11_hwmod;
964static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
965 { .irq = 47, },
966};
967
968static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
969 {
970 .pa_start = 0x48088000,
971 .pa_end = 0x48088000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT
973 },
974};
975 731
976/* l4_core -> timer11 */ 732/* l4_core -> timer11 */
977static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { 733static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
978 .master = &omap2430_l4_core_hwmod, 734 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_timer11_hwmod, 735 .slave = &omap2430_timer11_hwmod,
980 .clk = "gpt11_ick", 736 .clk = "gpt11_ick",
981 .addr = omap2430_timer11_addrs, 737 .addr = omap2_timer11_addrs,
982 .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA, 738 .user = OCP_USER_MPU | OCP_USER_SDMA,
984}; 739};
985 740
@@ -991,8 +746,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
991/* timer11 hwmod */ 746/* timer11 hwmod */
992static struct omap_hwmod omap2430_timer11_hwmod = { 747static struct omap_hwmod omap2430_timer11_hwmod = {
993 .name = "timer11", 748 .name = "timer11",
994 .mpu_irqs = omap2430_timer11_mpu_irqs, 749 .mpu_irqs = omap2_timer11_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
996 .main_clk = "gpt11_fck", 750 .main_clk = "gpt11_fck",
997 .prcm = { 751 .prcm = {
998 .omap2 = { 752 .omap2 = {
@@ -1005,31 +759,19 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
1005 }, 759 },
1006 .slaves = omap2430_timer11_slaves, 760 .slaves = omap2430_timer11_slaves,
1007 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), 761 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
1008 .class = &omap2430_timer_hwmod_class, 762 .class = &omap2xxx_timer_hwmod_class,
1009 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 763 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1010}; 764};
1011 765
1012/* timer12 */ 766/* timer12 */
1013static struct omap_hwmod omap2430_timer12_hwmod; 767static struct omap_hwmod omap2430_timer12_hwmod;
1014static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1015 { .irq = 48, },
1016};
1017
1018static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1019 {
1020 .pa_start = 0x4808a000,
1021 .pa_end = 0x4808a000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT
1023 },
1024};
1025 768
1026/* l4_core -> timer12 */ 769/* l4_core -> timer12 */
1027static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { 770static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1028 .master = &omap2430_l4_core_hwmod, 771 .master = &omap2430_l4_core_hwmod,
1029 .slave = &omap2430_timer12_hwmod, 772 .slave = &omap2430_timer12_hwmod,
1030 .clk = "gpt12_ick", 773 .clk = "gpt12_ick",
1031 .addr = omap2430_timer12_addrs, 774 .addr = omap2xxx_timer12_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA, 775 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034}; 776};
1035 777
@@ -1041,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1041/* timer12 hwmod */ 783/* timer12 hwmod */
1042static struct omap_hwmod omap2430_timer12_hwmod = { 784static struct omap_hwmod omap2430_timer12_hwmod = {
1043 .name = "timer12", 785 .name = "timer12",
1044 .mpu_irqs = omap2430_timer12_mpu_irqs, 786 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1046 .main_clk = "gpt12_fck", 787 .main_clk = "gpt12_fck",
1047 .prcm = { 788 .prcm = {
1048 .omap2 = { 789 .omap2 = {
@@ -1055,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
1055 }, 796 },
1056 .slaves = omap2430_timer12_slaves, 797 .slaves = omap2430_timer12_slaves,
1057 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), 798 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
1058 .class = &omap2430_timer_hwmod_class, 799 .class = &omap2xxx_timer_hwmod_class,
1059 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1060}; 801};
1061 802
@@ -1066,6 +807,7 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
1066 .pa_end = 0x4901607f, 807 .pa_end = 0x4901607f,
1067 .flags = ADDR_TYPE_RT 808 .flags = ADDR_TYPE_RT
1068 }, 809 },
810 { }
1069}; 811};
1070 812
1071static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 813static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
@@ -1073,31 +815,9 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
1073 .slave = &omap2430_wd_timer2_hwmod, 815 .slave = &omap2430_wd_timer2_hwmod,
1074 .clk = "mpu_wdt_ick", 816 .clk = "mpu_wdt_ick",
1075 .addr = omap2430_wd_timer2_addrs, 817 .addr = omap2430_wd_timer2_addrs,
1076 .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
1077 .user = OCP_USER_MPU | OCP_USER_SDMA, 818 .user = OCP_USER_MPU | OCP_USER_SDMA,
1078}; 819};
1079 820
1080/*
1081 * 'wd_timer' class
1082 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1083 * overflow condition
1084 */
1085
1086static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
1087 .rev_offs = 0x0,
1088 .sysc_offs = 0x0010,
1089 .syss_offs = 0x0014,
1090 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
1091 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1092 .sysc_fields = &omap_hwmod_sysc_type1,
1093};
1094
1095static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
1096 .name = "wd_timer",
1097 .sysc = &omap2430_wd_timer_sysc,
1098 .pre_shutdown = &omap2_wd_timer_disable
1099};
1100
1101/* wd_timer2 */ 821/* wd_timer2 */
1102static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { 822static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1103 &omap2430_l4_wkup__wd_timer2, 823 &omap2430_l4_wkup__wd_timer2,
@@ -1105,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1105 825
1106static struct omap_hwmod omap2430_wd_timer2_hwmod = { 826static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1107 .name = "wd_timer2", 827 .name = "wd_timer2",
1108 .class = &omap2430_wd_timer_hwmod_class, 828 .class = &omap2xxx_wd_timer_hwmod_class,
1109 .main_clk = "mpu_wdt_fck", 829 .main_clk = "mpu_wdt_fck",
1110 .prcm = { 830 .prcm = {
1111 .omap2 = { 831 .omap2 = {
@@ -1121,45 +841,16 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1121 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 841 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1122}; 842};
1123 843
1124/* UART */
1125
1126static struct omap_hwmod_class_sysconfig uart_sysc = {
1127 .rev_offs = 0x50,
1128 .sysc_offs = 0x54,
1129 .syss_offs = 0x58,
1130 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1131 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1132 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1133 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1134 .sysc_fields = &omap_hwmod_sysc_type1,
1135};
1136
1137static struct omap_hwmod_class uart_class = {
1138 .name = "uart",
1139 .sysc = &uart_sysc,
1140};
1141
1142/* UART1 */ 844/* UART1 */
1143 845
1144static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1145 { .irq = INT_24XX_UART1_IRQ, },
1146};
1147
1148static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1149 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1150 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1151};
1152
1153static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { 846static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
1154 &omap2_l4_core__uart1, 847 &omap2_l4_core__uart1,
1155}; 848};
1156 849
1157static struct omap_hwmod omap2430_uart1_hwmod = { 850static struct omap_hwmod omap2430_uart1_hwmod = {
1158 .name = "uart1", 851 .name = "uart1",
1159 .mpu_irqs = uart1_mpu_irqs, 852 .mpu_irqs = omap2_uart1_mpu_irqs,
1160 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 853 .sdma_reqs = omap2_uart1_sdma_reqs,
1161 .sdma_reqs = uart1_sdma_reqs,
1162 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1163 .main_clk = "uart1_fck", 854 .main_clk = "uart1_fck",
1164 .prcm = { 855 .prcm = {
1165 .omap2 = { 856 .omap2 = {
@@ -1172,31 +863,20 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
1172 }, 863 },
1173 .slaves = omap2430_uart1_slaves, 864 .slaves = omap2430_uart1_slaves,
1174 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), 865 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
1175 .class = &uart_class, 866 .class = &omap2_uart_class,
1176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 867 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1177}; 868};
1178 869
1179/* UART2 */ 870/* UART2 */
1180 871
1181static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1182 { .irq = INT_24XX_UART2_IRQ, },
1183};
1184
1185static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1186 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1187 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1188};
1189
1190static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { 872static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
1191 &omap2_l4_core__uart2, 873 &omap2_l4_core__uart2,
1192}; 874};
1193 875
1194static struct omap_hwmod omap2430_uart2_hwmod = { 876static struct omap_hwmod omap2430_uart2_hwmod = {
1195 .name = "uart2", 877 .name = "uart2",
1196 .mpu_irqs = uart2_mpu_irqs, 878 .mpu_irqs = omap2_uart2_mpu_irqs,
1197 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 879 .sdma_reqs = omap2_uart2_sdma_reqs,
1198 .sdma_reqs = uart2_sdma_reqs,
1199 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1200 .main_clk = "uart2_fck", 880 .main_clk = "uart2_fck",
1201 .prcm = { 881 .prcm = {
1202 .omap2 = { 882 .omap2 = {
@@ -1209,31 +889,20 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
1209 }, 889 },
1210 .slaves = omap2430_uart2_slaves, 890 .slaves = omap2430_uart2_slaves,
1211 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), 891 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
1212 .class = &uart_class, 892 .class = &omap2_uart_class,
1213 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 893 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1214}; 894};
1215 895
1216/* UART3 */ 896/* UART3 */
1217 897
1218static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1219 { .irq = INT_24XX_UART3_IRQ, },
1220};
1221
1222static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1223 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1224 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1225};
1226
1227static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { 898static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1228 &omap2_l4_core__uart3, 899 &omap2_l4_core__uart3,
1229}; 900};
1230 901
1231static struct omap_hwmod omap2430_uart3_hwmod = { 902static struct omap_hwmod omap2430_uart3_hwmod = {
1232 .name = "uart3", 903 .name = "uart3",
1233 .mpu_irqs = uart3_mpu_irqs, 904 .mpu_irqs = omap2_uart3_mpu_irqs,
1234 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 905 .sdma_reqs = omap2_uart3_sdma_reqs,
1235 .sdma_reqs = uart3_sdma_reqs,
1236 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1237 .main_clk = "uart3_fck", 906 .main_clk = "uart3_fck",
1238 .prcm = { 907 .prcm = {
1239 .omap2 = { 908 .omap2 = {
@@ -1246,53 +915,22 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
1246 }, 915 },
1247 .slaves = omap2430_uart3_slaves, 916 .slaves = omap2430_uart3_slaves,
1248 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), 917 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
1249 .class = &uart_class, 918 .class = &omap2_uart_class,
1250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 919 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1251}; 920};
1252 921
1253/*
1254 * 'dss' class
1255 * display sub-system
1256 */
1257
1258static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1259 .rev_offs = 0x0000,
1260 .sysc_offs = 0x0010,
1261 .syss_offs = 0x0014,
1262 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1263 .sysc_fields = &omap_hwmod_sysc_type1,
1264};
1265
1266static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1267 .name = "dss",
1268 .sysc = &omap2430_dss_sysc,
1269};
1270
1271static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1272 { .name = "dispc", .dma_req = 5 },
1273};
1274
1275/* dss */ 922/* dss */
1276/* dss master ports */ 923/* dss master ports */
1277static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { 924static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1278 &omap2430_dss__l3, 925 &omap2430_dss__l3,
1279}; 926};
1280 927
1281static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1282 {
1283 .pa_start = 0x48050000,
1284 .pa_end = 0x480503FF,
1285 .flags = ADDR_TYPE_RT
1286 },
1287};
1288
1289/* l4_core -> dss */ 928/* l4_core -> dss */
1290static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { 929static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1291 .master = &omap2430_l4_core_hwmod, 930 .master = &omap2430_l4_core_hwmod,
1292 .slave = &omap2430_dss_core_hwmod, 931 .slave = &omap2430_dss_core_hwmod,
1293 .clk = "dss_ick", 932 .clk = "dss_ick",
1294 .addr = omap2430_dss_addrs, 933 .addr = omap2_dss_addrs,
1295 .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
1296 .user = OCP_USER_MPU | OCP_USER_SDMA, 934 .user = OCP_USER_MPU | OCP_USER_SDMA,
1297}; 935};
1298 936
@@ -1308,10 +946,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1308 946
1309static struct omap_hwmod omap2430_dss_core_hwmod = { 947static struct omap_hwmod omap2430_dss_core_hwmod = {
1310 .name = "dss_core", 948 .name = "dss_core",
1311 .class = &omap2430_dss_hwmod_class, 949 .class = &omap2_dss_hwmod_class,
1312 .main_clk = "dss1_fck", /* instead of dss_fck */ 950 .main_clk = "dss1_fck", /* instead of dss_fck */
1313 .sdma_reqs = omap2430_dss_sdma_chs, 951 .sdma_reqs = omap2xxx_dss_sdma_chs,
1314 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
1315 .prcm = { 952 .prcm = {
1316 .omap2 = { 953 .omap2 = {
1317 .prcm_reg_id = 1, 954 .prcm_reg_id = 1,
@@ -1331,46 +968,12 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
1331 .flags = HWMOD_NO_IDLEST, 968 .flags = HWMOD_NO_IDLEST,
1332}; 969};
1333 970
1334/*
1335 * 'dispc' class
1336 * display controller
1337 */
1338
1339static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1340 .rev_offs = 0x0000,
1341 .sysc_offs = 0x0010,
1342 .syss_offs = 0x0014,
1343 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1344 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1347 .sysc_fields = &omap_hwmod_sysc_type1,
1348};
1349
1350static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1351 .name = "dispc",
1352 .sysc = &omap2430_dispc_sysc,
1353};
1354
1355static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
1356 { .irq = 25 },
1357};
1358
1359static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1360 {
1361 .pa_start = 0x48050400,
1362 .pa_end = 0x480507FF,
1363 .flags = ADDR_TYPE_RT
1364 },
1365};
1366
1367/* l4_core -> dss_dispc */ 971/* l4_core -> dss_dispc */
1368static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { 972static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1369 .master = &omap2430_l4_core_hwmod, 973 .master = &omap2430_l4_core_hwmod,
1370 .slave = &omap2430_dss_dispc_hwmod, 974 .slave = &omap2430_dss_dispc_hwmod,
1371 .clk = "dss_ick", 975 .clk = "dss_ick",
1372 .addr = omap2430_dss_dispc_addrs, 976 .addr = omap2_dss_dispc_addrs,
1373 .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
1374 .user = OCP_USER_MPU | OCP_USER_SDMA, 977 .user = OCP_USER_MPU | OCP_USER_SDMA,
1375}; 978};
1376 979
@@ -1381,9 +984,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1381 984
1382static struct omap_hwmod omap2430_dss_dispc_hwmod = { 985static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1383 .name = "dss_dispc", 986 .name = "dss_dispc",
1384 .class = &omap2430_dispc_hwmod_class, 987 .class = &omap2_dispc_hwmod_class,
1385 .mpu_irqs = omap2430_dispc_irqs, 988 .mpu_irqs = omap2_dispc_irqs,
1386 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs),
1387 .main_clk = "dss1_fck", 989 .main_clk = "dss1_fck",
1388 .prcm = { 990 .prcm = {
1389 .omap2 = { 991 .omap2 = {
@@ -1400,41 +1002,12 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1400 .flags = HWMOD_NO_IDLEST, 1002 .flags = HWMOD_NO_IDLEST,
1401}; 1003};
1402 1004
1403/*
1404 * 'rfbi' class
1405 * remote frame buffer interface
1406 */
1407
1408static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1409 .rev_offs = 0x0000,
1410 .sysc_offs = 0x0010,
1411 .syss_offs = 0x0014,
1412 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1413 SYSC_HAS_AUTOIDLE),
1414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1415 .sysc_fields = &omap_hwmod_sysc_type1,
1416};
1417
1418static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1419 .name = "rfbi",
1420 .sysc = &omap2430_rfbi_sysc,
1421};
1422
1423static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1424 {
1425 .pa_start = 0x48050800,
1426 .pa_end = 0x48050BFF,
1427 .flags = ADDR_TYPE_RT
1428 },
1429};
1430
1431/* l4_core -> dss_rfbi */ 1005/* l4_core -> dss_rfbi */
1432static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { 1006static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1433 .master = &omap2430_l4_core_hwmod, 1007 .master = &omap2430_l4_core_hwmod,
1434 .slave = &omap2430_dss_rfbi_hwmod, 1008 .slave = &omap2430_dss_rfbi_hwmod,
1435 .clk = "dss_ick", 1009 .clk = "dss_ick",
1436 .addr = omap2430_dss_rfbi_addrs, 1010 .addr = omap2_dss_rfbi_addrs,
1437 .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
1438 .user = OCP_USER_MPU | OCP_USER_SDMA, 1011 .user = OCP_USER_MPU | OCP_USER_SDMA,
1439}; 1012};
1440 1013
@@ -1445,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1445 1018
1446static struct omap_hwmod omap2430_dss_rfbi_hwmod = { 1019static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1447 .name = "dss_rfbi", 1020 .name = "dss_rfbi",
1448 .class = &omap2430_rfbi_hwmod_class, 1021 .class = &omap2_rfbi_hwmod_class,
1449 .main_clk = "dss1_fck", 1022 .main_clk = "dss1_fck",
1450 .prcm = { 1023 .prcm = {
1451 .omap2 = { 1024 .omap2 = {
@@ -1460,31 +1033,12 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1460 .flags = HWMOD_NO_IDLEST, 1033 .flags = HWMOD_NO_IDLEST,
1461}; 1034};
1462 1035
1463/*
1464 * 'venc' class
1465 * video encoder
1466 */
1467
1468static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1469 .name = "venc",
1470};
1471
1472/* dss_venc */
1473static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1474 {
1475 .pa_start = 0x48050C00,
1476 .pa_end = 0x48050FFF,
1477 .flags = ADDR_TYPE_RT
1478 },
1479};
1480
1481/* l4_core -> dss_venc */ 1036/* l4_core -> dss_venc */
1482static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { 1037static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1483 .master = &omap2430_l4_core_hwmod, 1038 .master = &omap2430_l4_core_hwmod,
1484 .slave = &omap2430_dss_venc_hwmod, 1039 .slave = &omap2430_dss_venc_hwmod,
1485 .clk = "dss_54m_fck", 1040 .clk = "dss_54m_fck",
1486 .addr = omap2430_dss_venc_addrs, 1041 .addr = omap2_dss_venc_addrs,
1487 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
1488 .flags = OCPIF_SWSUP_IDLE, 1042 .flags = OCPIF_SWSUP_IDLE,
1489 .user = OCP_USER_MPU | OCP_USER_SDMA, 1043 .user = OCP_USER_MPU | OCP_USER_SDMA,
1490}; 1044};
@@ -1496,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1496 1050
1497static struct omap_hwmod omap2430_dss_venc_hwmod = { 1051static struct omap_hwmod omap2430_dss_venc_hwmod = {
1498 .name = "dss_venc", 1052 .name = "dss_venc",
1499 .class = &omap2430_venc_hwmod_class, 1053 .class = &omap2_venc_hwmod_class,
1500 .main_clk = "dss1_fck", 1054 .main_clk = "dss1_fck",
1501 .prcm = { 1055 .prcm = {
1502 .omap2 = { 1056 .omap2 = {
@@ -1524,33 +1078,28 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
1524static struct omap_hwmod_class i2c_class = { 1078static struct omap_hwmod_class i2c_class = {
1525 .name = "i2c", 1079 .name = "i2c",
1526 .sysc = &i2c_sysc, 1080 .sysc = &i2c_sysc,
1081 .rev = OMAP_I2C_IP_VERSION_1,
1082 .reset = &omap_i2c_reset,
1527}; 1083};
1528 1084
1529static struct omap_i2c_dev_attr i2c_dev_attr = { 1085static struct omap_i2c_dev_attr i2c_dev_attr = {
1530 .fifo_depth = 8, /* bytes */ 1086 .fifo_depth = 8, /* bytes */
1087 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1088 OMAP_I2C_FLAG_BUS_SHIFT_2 |
1089 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1531}; 1090};
1532 1091
1533/* I2C1 */ 1092/* I2C1 */
1534 1093
1535static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1536 { .irq = INT_24XX_I2C1_IRQ, },
1537};
1538
1539static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1540 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1541 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1542};
1543
1544static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { 1094static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1545 &omap2430_l4_core__i2c1, 1095 &omap2430_l4_core__i2c1,
1546}; 1096};
1547 1097
1548static struct omap_hwmod omap2430_i2c1_hwmod = { 1098static struct omap_hwmod omap2430_i2c1_hwmod = {
1549 .name = "i2c1", 1099 .name = "i2c1",
1550 .mpu_irqs = i2c1_mpu_irqs, 1100 .flags = HWMOD_16BIT_REG,
1551 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1101 .mpu_irqs = omap2_i2c1_mpu_irqs,
1552 .sdma_reqs = i2c1_sdma_reqs, 1102 .sdma_reqs = omap2_i2c1_sdma_reqs,
1553 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1554 .main_clk = "i2chs1_fck", 1103 .main_clk = "i2chs1_fck",
1555 .prcm = { 1104 .prcm = {
1556 .omap2 = { 1105 .omap2 = {
@@ -1578,25 +1127,15 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
1578 1127
1579/* I2C2 */ 1128/* I2C2 */
1580 1129
1581static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1582 { .irq = INT_24XX_I2C2_IRQ, },
1583};
1584
1585static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1586 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1587 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1588};
1589
1590static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { 1130static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1591 &omap2430_l4_core__i2c2, 1131 &omap2430_l4_core__i2c2,
1592}; 1132};
1593 1133
1594static struct omap_hwmod omap2430_i2c2_hwmod = { 1134static struct omap_hwmod omap2430_i2c2_hwmod = {
1595 .name = "i2c2", 1135 .name = "i2c2",
1596 .mpu_irqs = i2c2_mpu_irqs, 1136 .flags = HWMOD_16BIT_REG,
1597 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1137 .mpu_irqs = omap2_i2c2_mpu_irqs,
1598 .sdma_reqs = i2c2_sdma_reqs, 1138 .sdma_reqs = omap2_i2c2_sdma_reqs,
1599 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1600 .main_clk = "i2chs2_fck", 1139 .main_clk = "i2chs2_fck",
1601 .prcm = { 1140 .prcm = {
1602 .omap2 = { 1141 .omap2 = {
@@ -1621,6 +1160,7 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1621 .pa_end = 0x4900C1ff, 1160 .pa_end = 0x4900C1ff,
1622 .flags = ADDR_TYPE_RT 1161 .flags = ADDR_TYPE_RT
1623 }, 1162 },
1163 { }
1624}; 1164};
1625 1165
1626static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 1166static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
@@ -1628,7 +1168,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1628 .slave = &omap2430_gpio1_hwmod, 1168 .slave = &omap2430_gpio1_hwmod,
1629 .clk = "gpios_ick", 1169 .clk = "gpios_ick",
1630 .addr = omap2430_gpio1_addr_space, 1170 .addr = omap2430_gpio1_addr_space,
1631 .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
1632 .user = OCP_USER_MPU | OCP_USER_SDMA, 1171 .user = OCP_USER_MPU | OCP_USER_SDMA,
1633}; 1172};
1634 1173
@@ -1639,6 +1178,7 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1639 .pa_end = 0x4900E1ff, 1178 .pa_end = 0x4900E1ff,
1640 .flags = ADDR_TYPE_RT 1179 .flags = ADDR_TYPE_RT
1641 }, 1180 },
1181 { }
1642}; 1182};
1643 1183
1644static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 1184static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
@@ -1646,7 +1186,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1646 .slave = &omap2430_gpio2_hwmod, 1186 .slave = &omap2430_gpio2_hwmod,
1647 .clk = "gpios_ick", 1187 .clk = "gpios_ick",
1648 .addr = omap2430_gpio2_addr_space, 1188 .addr = omap2430_gpio2_addr_space,
1649 .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
1650 .user = OCP_USER_MPU | OCP_USER_SDMA, 1189 .user = OCP_USER_MPU | OCP_USER_SDMA,
1651}; 1190};
1652 1191
@@ -1657,6 +1196,7 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1657 .pa_end = 0x490101ff, 1196 .pa_end = 0x490101ff,
1658 .flags = ADDR_TYPE_RT 1197 .flags = ADDR_TYPE_RT
1659 }, 1198 },
1199 { }
1660}; 1200};
1661 1201
1662static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 1202static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
@@ -1664,7 +1204,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1664 .slave = &omap2430_gpio3_hwmod, 1204 .slave = &omap2430_gpio3_hwmod,
1665 .clk = "gpios_ick", 1205 .clk = "gpios_ick",
1666 .addr = omap2430_gpio3_addr_space, 1206 .addr = omap2430_gpio3_addr_space,
1667 .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
1668 .user = OCP_USER_MPU | OCP_USER_SDMA, 1207 .user = OCP_USER_MPU | OCP_USER_SDMA,
1669}; 1208};
1670 1209
@@ -1675,6 +1214,7 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1675 .pa_end = 0x490121ff, 1214 .pa_end = 0x490121ff,
1676 .flags = ADDR_TYPE_RT 1215 .flags = ADDR_TYPE_RT
1677 }, 1216 },
1217 { }
1678}; 1218};
1679 1219
1680static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 1220static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
@@ -1682,7 +1222,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1682 .slave = &omap2430_gpio4_hwmod, 1222 .slave = &omap2430_gpio4_hwmod,
1683 .clk = "gpios_ick", 1223 .clk = "gpios_ick",
1684 .addr = omap2430_gpio4_addr_space, 1224 .addr = omap2430_gpio4_addr_space,
1685 .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
1686 .user = OCP_USER_MPU | OCP_USER_SDMA, 1225 .user = OCP_USER_MPU | OCP_USER_SDMA,
1687}; 1226};
1688 1227
@@ -1693,6 +1232,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1693 .pa_end = 0x480B61ff, 1232 .pa_end = 0x480B61ff,
1694 .flags = ADDR_TYPE_RT 1233 .flags = ADDR_TYPE_RT
1695 }, 1234 },
1235 { }
1696}; 1236};
1697 1237
1698static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 1238static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
@@ -1700,7 +1240,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1700 .slave = &omap2430_gpio5_hwmod, 1240 .slave = &omap2430_gpio5_hwmod,
1701 .clk = "gpio5_ick", 1241 .clk = "gpio5_ick",
1702 .addr = omap2430_gpio5_addr_space, 1242 .addr = omap2430_gpio5_addr_space,
1703 .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
1704 .user = OCP_USER_MPU | OCP_USER_SDMA, 1243 .user = OCP_USER_MPU | OCP_USER_SDMA,
1705}; 1244};
1706 1245
@@ -1710,32 +1249,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1710 .dbck_flag = false, 1249 .dbck_flag = false,
1711}; 1250};
1712 1251
1713static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1714 .rev_offs = 0x0000,
1715 .sysc_offs = 0x0010,
1716 .syss_offs = 0x0014,
1717 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1718 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1719 SYSS_HAS_RESET_STATUS),
1720 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1721 .sysc_fields = &omap_hwmod_sysc_type1,
1722};
1723
1724/*
1725 * 'gpio' class
1726 * general purpose io module
1727 */
1728static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1729 .name = "gpio",
1730 .sysc = &omap243x_gpio_sysc,
1731 .rev = 0,
1732};
1733
1734/* gpio1 */ 1252/* gpio1 */
1735static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1736 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1737};
1738
1739static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { 1253static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1740 &omap2430_l4_wkup__gpio1, 1254 &omap2430_l4_wkup__gpio1,
1741}; 1255};
@@ -1743,8 +1257,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1743static struct omap_hwmod omap2430_gpio1_hwmod = { 1257static struct omap_hwmod omap2430_gpio1_hwmod = {
1744 .name = "gpio1", 1258 .name = "gpio1",
1745 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1259 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1746 .mpu_irqs = omap243x_gpio1_irqs, 1260 .mpu_irqs = omap2_gpio1_irqs,
1747 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
1748 .main_clk = "gpios_fck", 1261 .main_clk = "gpios_fck",
1749 .prcm = { 1262 .prcm = {
1750 .omap2 = { 1263 .omap2 = {
@@ -1757,16 +1270,12 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
1757 }, 1270 },
1758 .slaves = omap2430_gpio1_slaves, 1271 .slaves = omap2430_gpio1_slaves,
1759 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), 1272 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1760 .class = &omap243x_gpio_hwmod_class, 1273 .class = &omap2xxx_gpio_hwmod_class,
1761 .dev_attr = &gpio_dev_attr, 1274 .dev_attr = &gpio_dev_attr,
1762 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1275 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1763}; 1276};
1764 1277
1765/* gpio2 */ 1278/* gpio2 */
1766static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1767 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1768};
1769
1770static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { 1279static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1771 &omap2430_l4_wkup__gpio2, 1280 &omap2430_l4_wkup__gpio2,
1772}; 1281};
@@ -1774,8 +1283,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1774static struct omap_hwmod omap2430_gpio2_hwmod = { 1283static struct omap_hwmod omap2430_gpio2_hwmod = {
1775 .name = "gpio2", 1284 .name = "gpio2",
1776 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1285 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1777 .mpu_irqs = omap243x_gpio2_irqs, 1286 .mpu_irqs = omap2_gpio2_irqs,
1778 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
1779 .main_clk = "gpios_fck", 1287 .main_clk = "gpios_fck",
1780 .prcm = { 1288 .prcm = {
1781 .omap2 = { 1289 .omap2 = {
@@ -1788,16 +1296,12 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
1788 }, 1296 },
1789 .slaves = omap2430_gpio2_slaves, 1297 .slaves = omap2430_gpio2_slaves,
1790 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), 1298 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1791 .class = &omap243x_gpio_hwmod_class, 1299 .class = &omap2xxx_gpio_hwmod_class,
1792 .dev_attr = &gpio_dev_attr, 1300 .dev_attr = &gpio_dev_attr,
1793 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1301 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1794}; 1302};
1795 1303
1796/* gpio3 */ 1304/* gpio3 */
1797static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1798 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1799};
1800
1801static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { 1305static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1802 &omap2430_l4_wkup__gpio3, 1306 &omap2430_l4_wkup__gpio3,
1803}; 1307};
@@ -1805,8 +1309,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1805static struct omap_hwmod omap2430_gpio3_hwmod = { 1309static struct omap_hwmod omap2430_gpio3_hwmod = {
1806 .name = "gpio3", 1310 .name = "gpio3",
1807 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1311 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1808 .mpu_irqs = omap243x_gpio3_irqs, 1312 .mpu_irqs = omap2_gpio3_irqs,
1809 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
1810 .main_clk = "gpios_fck", 1313 .main_clk = "gpios_fck",
1811 .prcm = { 1314 .prcm = {
1812 .omap2 = { 1315 .omap2 = {
@@ -1819,16 +1322,12 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
1819 }, 1322 },
1820 .slaves = omap2430_gpio3_slaves, 1323 .slaves = omap2430_gpio3_slaves,
1821 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), 1324 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1822 .class = &omap243x_gpio_hwmod_class, 1325 .class = &omap2xxx_gpio_hwmod_class,
1823 .dev_attr = &gpio_dev_attr, 1326 .dev_attr = &gpio_dev_attr,
1824 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1327 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1825}; 1328};
1826 1329
1827/* gpio4 */ 1330/* gpio4 */
1828static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1829 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1830};
1831
1832static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { 1331static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1833 &omap2430_l4_wkup__gpio4, 1332 &omap2430_l4_wkup__gpio4,
1834}; 1333};
@@ -1836,8 +1335,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1836static struct omap_hwmod omap2430_gpio4_hwmod = { 1335static struct omap_hwmod omap2430_gpio4_hwmod = {
1837 .name = "gpio4", 1336 .name = "gpio4",
1838 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1337 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1839 .mpu_irqs = omap243x_gpio4_irqs, 1338 .mpu_irqs = omap2_gpio4_irqs,
1840 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
1841 .main_clk = "gpios_fck", 1339 .main_clk = "gpios_fck",
1842 .prcm = { 1340 .prcm = {
1843 .omap2 = { 1341 .omap2 = {
@@ -1850,7 +1348,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
1850 }, 1348 },
1851 .slaves = omap2430_gpio4_slaves, 1349 .slaves = omap2430_gpio4_slaves,
1852 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), 1350 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1853 .class = &omap243x_gpio_hwmod_class, 1351 .class = &omap2xxx_gpio_hwmod_class,
1854 .dev_attr = &gpio_dev_attr, 1352 .dev_attr = &gpio_dev_attr,
1855 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1353 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1856}; 1354};
@@ -1858,6 +1356,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
1858/* gpio5 */ 1356/* gpio5 */
1859static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { 1357static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1860 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ 1358 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1359 { .irq = -1 }
1861}; 1360};
1862 1361
1863static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { 1362static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
@@ -1868,7 +1367,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
1868 .name = "gpio5", 1367 .name = "gpio5",
1869 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1368 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1870 .mpu_irqs = omap243x_gpio5_irqs, 1369 .mpu_irqs = omap243x_gpio5_irqs,
1871 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
1872 .main_clk = "gpio5_fck", 1370 .main_clk = "gpio5_fck",
1873 .prcm = { 1371 .prcm = {
1874 .omap2 = { 1372 .omap2 = {
@@ -1881,28 +1379,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
1881 }, 1379 },
1882 .slaves = omap2430_gpio5_slaves, 1380 .slaves = omap2430_gpio5_slaves,
1883 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), 1381 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1884 .class = &omap243x_gpio_hwmod_class, 1382 .class = &omap2xxx_gpio_hwmod_class,
1885 .dev_attr = &gpio_dev_attr, 1383 .dev_attr = &gpio_dev_attr,
1886 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1384 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1887}; 1385};
1888 1386
1889/* dma_system */
1890static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1891 .rev_offs = 0x0000,
1892 .sysc_offs = 0x002c,
1893 .syss_offs = 0x0028,
1894 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1895 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1896 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1897 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1898 .sysc_fields = &omap_hwmod_sysc_type1,
1899};
1900
1901static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1902 .name = "dma",
1903 .sysc = &omap2430_dma_sysc,
1904};
1905
1906/* dma attributes */ 1387/* dma attributes */
1907static struct omap_dma_dev_attr dma_dev_attr = { 1388static struct omap_dma_dev_attr dma_dev_attr = {
1908 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1389 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1910,21 +1391,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
1910 .lch_count = 32, 1391 .lch_count = 32,
1911}; 1392};
1912 1393
1913static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1914 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1915 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1916 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1917 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1918};
1919
1920static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1921 {
1922 .pa_start = 0x48056000,
1923 .pa_end = 0x48056fff,
1924 .flags = ADDR_TYPE_RT
1925 },
1926};
1927
1928/* dma_system -> L3 */ 1394/* dma_system -> L3 */
1929static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 1395static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1930 .master = &omap2430_dma_system_hwmod, 1396 .master = &omap2430_dma_system_hwmod,
@@ -1943,8 +1409,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1943 .master = &omap2430_l4_core_hwmod, 1409 .master = &omap2430_l4_core_hwmod,
1944 .slave = &omap2430_dma_system_hwmod, 1410 .slave = &omap2430_dma_system_hwmod,
1945 .clk = "sdma_ick", 1411 .clk = "sdma_ick",
1946 .addr = omap2430_dma_system_addrs, 1412 .addr = omap2_dma_system_addrs,
1947 .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
1948 .user = OCP_USER_MPU | OCP_USER_SDMA, 1413 .user = OCP_USER_MPU | OCP_USER_SDMA,
1949}; 1414};
1950 1415
@@ -1955,9 +1420,8 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1955 1420
1956static struct omap_hwmod omap2430_dma_system_hwmod = { 1421static struct omap_hwmod omap2430_dma_system_hwmod = {
1957 .name = "dma", 1422 .name = "dma",
1958 .class = &omap2430_dma_hwmod_class, 1423 .class = &omap2xxx_dma_hwmod_class,
1959 .mpu_irqs = omap2430_dma_system_irqs, 1424 .mpu_irqs = omap2_dma_system_irqs,
1960 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
1961 .main_clk = "core_l3_ck", 1425 .main_clk = "core_l3_ck",
1962 .slaves = omap2430_dma_system_slaves, 1426 .slaves = omap2430_dma_system_slaves,
1963 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), 1427 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
@@ -1968,47 +1432,18 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
1968 .flags = HWMOD_NO_IDLEST, 1432 .flags = HWMOD_NO_IDLEST,
1969}; 1433};
1970 1434
1971/*
1972 * 'mailbox' class
1973 * mailbox module allowing communication between the on-chip processors
1974 * using a queued mailbox-interrupt mechanism.
1975 */
1976
1977static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1978 .rev_offs = 0x000,
1979 .sysc_offs = 0x010,
1980 .syss_offs = 0x014,
1981 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1982 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1983 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1984 .sysc_fields = &omap_hwmod_sysc_type1,
1985};
1986
1987static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1988 .name = "mailbox",
1989 .sysc = &omap2430_mailbox_sysc,
1990};
1991
1992/* mailbox */ 1435/* mailbox */
1993static struct omap_hwmod omap2430_mailbox_hwmod; 1436static struct omap_hwmod omap2430_mailbox_hwmod;
1994static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 1437static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1995 { .irq = 26 }, 1438 { .irq = 26 },
1996}; 1439 { .irq = -1 }
1997
1998static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1999 {
2000 .pa_start = 0x48094000,
2001 .pa_end = 0x480941ff,
2002 .flags = ADDR_TYPE_RT,
2003 },
2004}; 1440};
2005 1441
2006/* l4_core -> mailbox */ 1442/* l4_core -> mailbox */
2007static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 1443static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2008 .master = &omap2430_l4_core_hwmod, 1444 .master = &omap2430_l4_core_hwmod,
2009 .slave = &omap2430_mailbox_hwmod, 1445 .slave = &omap2430_mailbox_hwmod,
2010 .addr = omap2430_mailbox_addrs, 1446 .addr = omap2_mailbox_addrs,
2011 .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
2012 .user = OCP_USER_MPU | OCP_USER_SDMA, 1447 .user = OCP_USER_MPU | OCP_USER_SDMA,
2013}; 1448};
2014 1449
@@ -2019,9 +1454,8 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2019 1454
2020static struct omap_hwmod omap2430_mailbox_hwmod = { 1455static struct omap_hwmod omap2430_mailbox_hwmod = {
2021 .name = "mailbox", 1456 .name = "mailbox",
2022 .class = &omap2430_mailbox_hwmod_class, 1457 .class = &omap2xxx_mailbox_hwmod_class,
2023 .mpu_irqs = omap2430_mailbox_irqs, 1458 .mpu_irqs = omap2430_mailbox_irqs,
2024 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
2025 .main_clk = "mailboxes_ick", 1459 .main_clk = "mailboxes_ick",
2026 .prcm = { 1460 .prcm = {
2027 .omap2 = { 1461 .omap2 = {
@@ -2037,45 +1471,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
2037 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2038}; 1472};
2039 1473
2040/*
2041 * 'mcspi' class
2042 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2043 * bus
2044 */
2045
2046static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
2047 .rev_offs = 0x0000,
2048 .sysc_offs = 0x0010,
2049 .syss_offs = 0x0014,
2050 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2051 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2052 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2053 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2054 .sysc_fields = &omap_hwmod_sysc_type1,
2055};
2056
2057static struct omap_hwmod_class omap2430_mcspi_class = {
2058 .name = "mcspi",
2059 .sysc = &omap2430_mcspi_sysc,
2060 .rev = OMAP2_MCSPI_REV,
2061};
2062
2063/* mcspi1 */ 1474/* mcspi1 */
2064static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
2065 { .irq = 65 },
2066};
2067
2068static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
2069 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
2070 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
2071 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
2072 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
2073 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
2074 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
2075 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
2076 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
2077};
2078
2079static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { 1475static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
2080 &omap2430_l4_core__mcspi1, 1476 &omap2430_l4_core__mcspi1,
2081}; 1477};
@@ -2086,10 +1482,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2086 1482
2087static struct omap_hwmod omap2430_mcspi1_hwmod = { 1483static struct omap_hwmod omap2430_mcspi1_hwmod = {
2088 .name = "mcspi1_hwmod", 1484 .name = "mcspi1_hwmod",
2089 .mpu_irqs = omap2430_mcspi1_mpu_irqs, 1485 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2090 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), 1486 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2091 .sdma_reqs = omap2430_mcspi1_sdma_reqs,
2092 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
2093 .main_clk = "mcspi1_fck", 1487 .main_clk = "mcspi1_fck",
2094 .prcm = { 1488 .prcm = {
2095 .omap2 = { 1489 .omap2 = {
@@ -2102,23 +1496,12 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
2102 }, 1496 },
2103 .slaves = omap2430_mcspi1_slaves, 1497 .slaves = omap2430_mcspi1_slaves,
2104 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), 1498 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
2105 .class = &omap2430_mcspi_class, 1499 .class = &omap2xxx_mcspi_class,
2106 .dev_attr = &omap_mcspi1_dev_attr, 1500 .dev_attr = &omap_mcspi1_dev_attr,
2107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1501 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2108}; 1502};
2109 1503
2110/* mcspi2 */ 1504/* mcspi2 */
2111static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
2112 { .irq = 66 },
2113};
2114
2115static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
2116 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
2117 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
2118 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
2119 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
2120};
2121
2122static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { 1505static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
2123 &omap2430_l4_core__mcspi2, 1506 &omap2430_l4_core__mcspi2,
2124}; 1507};
@@ -2129,10 +1512,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2129 1512
2130static struct omap_hwmod omap2430_mcspi2_hwmod = { 1513static struct omap_hwmod omap2430_mcspi2_hwmod = {
2131 .name = "mcspi2_hwmod", 1514 .name = "mcspi2_hwmod",
2132 .mpu_irqs = omap2430_mcspi2_mpu_irqs, 1515 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2133 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), 1516 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2134 .sdma_reqs = omap2430_mcspi2_sdma_reqs,
2135 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2136 .main_clk = "mcspi2_fck", 1517 .main_clk = "mcspi2_fck",
2137 .prcm = { 1518 .prcm = {
2138 .omap2 = { 1519 .omap2 = {
@@ -2145,14 +1526,15 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
2145 }, 1526 },
2146 .slaves = omap2430_mcspi2_slaves, 1527 .slaves = omap2430_mcspi2_slaves,
2147 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), 1528 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
2148 .class = &omap2430_mcspi_class, 1529 .class = &omap2xxx_mcspi_class,
2149 .dev_attr = &omap_mcspi2_dev_attr, 1530 .dev_attr = &omap_mcspi2_dev_attr,
2150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1531 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2151}; 1532};
2152 1533
2153/* mcspi3 */ 1534/* mcspi3 */
2154static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { 1535static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2155 { .irq = 91 }, 1536 { .irq = 91 },
1537 { .irq = -1 }
2156}; 1538};
2157 1539
2158static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { 1540static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
@@ -2160,6 +1542,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2160 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ 1542 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2161 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ 1543 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2162 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ 1544 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1545 { .dma_req = -1 }
2163}; 1546};
2164 1547
2165static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { 1548static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
@@ -2173,9 +1556,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2173static struct omap_hwmod omap2430_mcspi3_hwmod = { 1556static struct omap_hwmod omap2430_mcspi3_hwmod = {
2174 .name = "mcspi3_hwmod", 1557 .name = "mcspi3_hwmod",
2175 .mpu_irqs = omap2430_mcspi3_mpu_irqs, 1558 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
2176 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2177 .sdma_reqs = omap2430_mcspi3_sdma_reqs, 1559 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
2178 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2179 .main_clk = "mcspi3_fck", 1560 .main_clk = "mcspi3_fck",
2180 .prcm = { 1561 .prcm = {
2181 .omap2 = { 1562 .omap2 = {
@@ -2188,8 +1569,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
2188 }, 1569 },
2189 .slaves = omap2430_mcspi3_slaves, 1570 .slaves = omap2430_mcspi3_slaves,
2190 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), 1571 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
2191 .class = &omap2430_mcspi_class, 1572 .class = &omap2xxx_mcspi_class,
2192 .dev_attr = &omap_mcspi3_dev_attr, 1573 .dev_attr = &omap_mcspi3_dev_attr,
2193 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2194}; 1575};
2195 1576
@@ -2218,12 +1599,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2218 1599
2219 { .name = "mc", .irq = 92 }, 1600 { .name = "mc", .irq = 92 },
2220 { .name = "dma", .irq = 93 }, 1601 { .name = "dma", .irq = 93 },
1602 { .irq = -1 }
2221}; 1603};
2222 1604
2223static struct omap_hwmod omap2430_usbhsotg_hwmod = { 1605static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2224 .name = "usb_otg_hs", 1606 .name = "usb_otg_hs",
2225 .mpu_irqs = omap2430_usbhsotg_mpu_irqs, 1607 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
2226 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2227 .main_clk = "usbhs_ick", 1608 .main_clk = "usbhs_ick",
2228 .prcm = { 1609 .prcm = {
2229 .omap2 = { 1610 .omap2 = {
@@ -2273,20 +1654,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2273 { .name = "rx", .irq = 60 }, 1654 { .name = "rx", .irq = 60 },
2274 { .name = "ovr", .irq = 61 }, 1655 { .name = "ovr", .irq = 61 },
2275 { .name = "common", .irq = 64 }, 1656 { .name = "common", .irq = 64 },
2276}; 1657 { .irq = -1 }
2277
2278static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2279 { .name = "rx", .dma_req = 32 },
2280 { .name = "tx", .dma_req = 31 },
2281};
2282
2283static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2284 {
2285 .name = "mpu",
2286 .pa_start = 0x48074000,
2287 .pa_end = 0x480740ff,
2288 .flags = ADDR_TYPE_RT
2289 },
2290}; 1658};
2291 1659
2292/* l4_core -> mcbsp1 */ 1660/* l4_core -> mcbsp1 */
@@ -2294,8 +1662,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2294 .master = &omap2430_l4_core_hwmod, 1662 .master = &omap2430_l4_core_hwmod,
2295 .slave = &omap2430_mcbsp1_hwmod, 1663 .slave = &omap2430_mcbsp1_hwmod,
2296 .clk = "mcbsp1_ick", 1664 .clk = "mcbsp1_ick",
2297 .addr = omap2430_mcbsp1_addrs, 1665 .addr = omap2_mcbsp1_addrs,
2298 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
2299 .user = OCP_USER_MPU | OCP_USER_SDMA, 1666 .user = OCP_USER_MPU | OCP_USER_SDMA,
2300}; 1667};
2301 1668
@@ -2308,9 +1675,7 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2308 .name = "mcbsp1", 1675 .name = "mcbsp1",
2309 .class = &omap2430_mcbsp_hwmod_class, 1676 .class = &omap2430_mcbsp_hwmod_class,
2310 .mpu_irqs = omap2430_mcbsp1_irqs, 1677 .mpu_irqs = omap2430_mcbsp1_irqs,
2311 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), 1678 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2312 .sdma_reqs = omap2430_mcbsp1_sdma_chs,
2313 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2314 .main_clk = "mcbsp1_fck", 1679 .main_clk = "mcbsp1_fck",
2315 .prcm = { 1680 .prcm = {
2316 .omap2 = { 1681 .omap2 = {
@@ -2331,20 +1696,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2331 { .name = "tx", .irq = 62 }, 1696 { .name = "tx", .irq = 62 },
2332 { .name = "rx", .irq = 63 }, 1697 { .name = "rx", .irq = 63 },
2333 { .name = "common", .irq = 16 }, 1698 { .name = "common", .irq = 16 },
2334}; 1699 { .irq = -1 }
2335
2336static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2337 { .name = "rx", .dma_req = 34 },
2338 { .name = "tx", .dma_req = 33 },
2339};
2340
2341static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2342 {
2343 .name = "mpu",
2344 .pa_start = 0x48076000,
2345 .pa_end = 0x480760ff,
2346 .flags = ADDR_TYPE_RT
2347 },
2348}; 1700};
2349 1701
2350/* l4_core -> mcbsp2 */ 1702/* l4_core -> mcbsp2 */
@@ -2352,8 +1704,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2352 .master = &omap2430_l4_core_hwmod, 1704 .master = &omap2430_l4_core_hwmod,
2353 .slave = &omap2430_mcbsp2_hwmod, 1705 .slave = &omap2430_mcbsp2_hwmod,
2354 .clk = "mcbsp2_ick", 1706 .clk = "mcbsp2_ick",
2355 .addr = omap2430_mcbsp2_addrs, 1707 .addr = omap2xxx_mcbsp2_addrs,
2356 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
2357 .user = OCP_USER_MPU | OCP_USER_SDMA, 1708 .user = OCP_USER_MPU | OCP_USER_SDMA,
2358}; 1709};
2359 1710
@@ -2366,9 +1717,7 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2366 .name = "mcbsp2", 1717 .name = "mcbsp2",
2367 .class = &omap2430_mcbsp_hwmod_class, 1718 .class = &omap2430_mcbsp_hwmod_class,
2368 .mpu_irqs = omap2430_mcbsp2_irqs, 1719 .mpu_irqs = omap2430_mcbsp2_irqs,
2369 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs), 1720 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2370 .sdma_reqs = omap2430_mcbsp2_sdma_chs,
2371 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2372 .main_clk = "mcbsp2_fck", 1721 .main_clk = "mcbsp2_fck",
2373 .prcm = { 1722 .prcm = {
2374 .omap2 = { 1723 .omap2 = {
@@ -2389,11 +1738,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2389 { .name = "tx", .irq = 89 }, 1738 { .name = "tx", .irq = 89 },
2390 { .name = "rx", .irq = 90 }, 1739 { .name = "rx", .irq = 90 },
2391 { .name = "common", .irq = 17 }, 1740 { .name = "common", .irq = 17 },
2392}; 1741 { .irq = -1 }
2393
2394static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2395 { .name = "rx", .dma_req = 18 },
2396 { .name = "tx", .dma_req = 17 },
2397}; 1742};
2398 1743
2399static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { 1744static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
@@ -2403,6 +1748,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2403 .pa_end = 0x4808C0ff, 1748 .pa_end = 0x4808C0ff,
2404 .flags = ADDR_TYPE_RT 1749 .flags = ADDR_TYPE_RT
2405 }, 1750 },
1751 { }
2406}; 1752};
2407 1753
2408/* l4_core -> mcbsp3 */ 1754/* l4_core -> mcbsp3 */
@@ -2411,7 +1757,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2411 .slave = &omap2430_mcbsp3_hwmod, 1757 .slave = &omap2430_mcbsp3_hwmod,
2412 .clk = "mcbsp3_ick", 1758 .clk = "mcbsp3_ick",
2413 .addr = omap2430_mcbsp3_addrs, 1759 .addr = omap2430_mcbsp3_addrs,
2414 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
2415 .user = OCP_USER_MPU | OCP_USER_SDMA, 1760 .user = OCP_USER_MPU | OCP_USER_SDMA,
2416}; 1761};
2417 1762
@@ -2424,9 +1769,7 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2424 .name = "mcbsp3", 1769 .name = "mcbsp3",
2425 .class = &omap2430_mcbsp_hwmod_class, 1770 .class = &omap2430_mcbsp_hwmod_class,
2426 .mpu_irqs = omap2430_mcbsp3_irqs, 1771 .mpu_irqs = omap2430_mcbsp3_irqs,
2427 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs), 1772 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2428 .sdma_reqs = omap2430_mcbsp3_sdma_chs,
2429 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2430 .main_clk = "mcbsp3_fck", 1773 .main_clk = "mcbsp3_fck",
2431 .prcm = { 1774 .prcm = {
2432 .omap2 = { 1775 .omap2 = {
@@ -2447,11 +1790,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2447 { .name = "tx", .irq = 54 }, 1790 { .name = "tx", .irq = 54 },
2448 { .name = "rx", .irq = 55 }, 1791 { .name = "rx", .irq = 55 },
2449 { .name = "common", .irq = 18 }, 1792 { .name = "common", .irq = 18 },
1793 { .irq = -1 }
2450}; 1794};
2451 1795
2452static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { 1796static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2453 { .name = "rx", .dma_req = 20 }, 1797 { .name = "rx", .dma_req = 20 },
2454 { .name = "tx", .dma_req = 19 }, 1798 { .name = "tx", .dma_req = 19 },
1799 { .dma_req = -1 }
2455}; 1800};
2456 1801
2457static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { 1802static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
@@ -2461,6 +1806,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2461 .pa_end = 0x4808E0ff, 1806 .pa_end = 0x4808E0ff,
2462 .flags = ADDR_TYPE_RT 1807 .flags = ADDR_TYPE_RT
2463 }, 1808 },
1809 { }
2464}; 1810};
2465 1811
2466/* l4_core -> mcbsp4 */ 1812/* l4_core -> mcbsp4 */
@@ -2469,7 +1815,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2469 .slave = &omap2430_mcbsp4_hwmod, 1815 .slave = &omap2430_mcbsp4_hwmod,
2470 .clk = "mcbsp4_ick", 1816 .clk = "mcbsp4_ick",
2471 .addr = omap2430_mcbsp4_addrs, 1817 .addr = omap2430_mcbsp4_addrs,
2472 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
2473 .user = OCP_USER_MPU | OCP_USER_SDMA, 1818 .user = OCP_USER_MPU | OCP_USER_SDMA,
2474}; 1819};
2475 1820
@@ -2482,9 +1827,7 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2482 .name = "mcbsp4", 1827 .name = "mcbsp4",
2483 .class = &omap2430_mcbsp_hwmod_class, 1828 .class = &omap2430_mcbsp_hwmod_class,
2484 .mpu_irqs = omap2430_mcbsp4_irqs, 1829 .mpu_irqs = omap2430_mcbsp4_irqs,
2485 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2486 .sdma_reqs = omap2430_mcbsp4_sdma_chs, 1830 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
2487 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2488 .main_clk = "mcbsp4_fck", 1831 .main_clk = "mcbsp4_fck",
2489 .prcm = { 1832 .prcm = {
2490 .omap2 = { 1833 .omap2 = {
@@ -2505,11 +1848,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2505 { .name = "tx", .irq = 81 }, 1848 { .name = "tx", .irq = 81 },
2506 { .name = "rx", .irq = 82 }, 1849 { .name = "rx", .irq = 82 },
2507 { .name = "common", .irq = 19 }, 1850 { .name = "common", .irq = 19 },
1851 { .irq = -1 }
2508}; 1852};
2509 1853
2510static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { 1854static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2511 { .name = "rx", .dma_req = 22 }, 1855 { .name = "rx", .dma_req = 22 },
2512 { .name = "tx", .dma_req = 21 }, 1856 { .name = "tx", .dma_req = 21 },
1857 { .dma_req = -1 }
2513}; 1858};
2514 1859
2515static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { 1860static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
@@ -2519,6 +1864,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2519 .pa_end = 0x480960ff, 1864 .pa_end = 0x480960ff,
2520 .flags = ADDR_TYPE_RT 1865 .flags = ADDR_TYPE_RT
2521 }, 1866 },
1867 { }
2522}; 1868};
2523 1869
2524/* l4_core -> mcbsp5 */ 1870/* l4_core -> mcbsp5 */
@@ -2527,7 +1873,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2527 .slave = &omap2430_mcbsp5_hwmod, 1873 .slave = &omap2430_mcbsp5_hwmod,
2528 .clk = "mcbsp5_ick", 1874 .clk = "mcbsp5_ick",
2529 .addr = omap2430_mcbsp5_addrs, 1875 .addr = omap2430_mcbsp5_addrs,
2530 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
2531 .user = OCP_USER_MPU | OCP_USER_SDMA, 1876 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532}; 1877};
2533 1878
@@ -2540,9 +1885,7 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2540 .name = "mcbsp5", 1885 .name = "mcbsp5",
2541 .class = &omap2430_mcbsp_hwmod_class, 1886 .class = &omap2430_mcbsp_hwmod_class,
2542 .mpu_irqs = omap2430_mcbsp5_irqs, 1887 .mpu_irqs = omap2430_mcbsp5_irqs,
2543 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2544 .sdma_reqs = omap2430_mcbsp5_sdma_chs, 1888 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
2545 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2546 .main_clk = "mcbsp5_fck", 1889 .main_clk = "mcbsp5_fck",
2547 .prcm = { 1890 .prcm = {
2548 .omap2 = { 1891 .omap2 = {
@@ -2580,11 +1923,13 @@ static struct omap_hwmod_class omap2430_mmc_class = {
2580 1923
2581static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { 1924static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2582 { .irq = 83 }, 1925 { .irq = 83 },
1926 { .irq = -1 }
2583}; 1927};
2584 1928
2585static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { 1929static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2586 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ 1930 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2587 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ 1931 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
1932 { .dma_req = -1 }
2588}; 1933};
2589 1934
2590static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 1935static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
@@ -2603,9 +1948,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
2603 .name = "mmc1", 1948 .name = "mmc1",
2604 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1949 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2605 .mpu_irqs = omap2430_mmc1_mpu_irqs, 1950 .mpu_irqs = omap2430_mmc1_mpu_irqs,
2606 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2607 .sdma_reqs = omap2430_mmc1_sdma_reqs, 1951 .sdma_reqs = omap2430_mmc1_sdma_reqs,
2608 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2609 .opt_clks = omap2430_mmc1_opt_clks, 1952 .opt_clks = omap2430_mmc1_opt_clks,
2610 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 1953 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2611 .main_clk = "mmchs1_fck", 1954 .main_clk = "mmchs1_fck",
@@ -2629,11 +1972,13 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
2629 1972
2630static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { 1973static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2631 { .irq = 86 }, 1974 { .irq = 86 },
1975 { .irq = -1 }
2632}; 1976};
2633 1977
2634static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { 1978static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2635 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ 1979 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2636 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ 1980 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
1981 { .dma_req = -1 }
2637}; 1982};
2638 1983
2639static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 1984static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
@@ -2648,9 +1993,7 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
2648 .name = "mmc2", 1993 .name = "mmc2",
2649 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1994 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2650 .mpu_irqs = omap2430_mmc2_mpu_irqs, 1995 .mpu_irqs = omap2430_mmc2_mpu_irqs,
2651 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2652 .sdma_reqs = omap2430_mmc2_sdma_reqs, 1996 .sdma_reqs = omap2430_mmc2_sdma_reqs,
2653 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2654 .opt_clks = omap2430_mmc2_opt_clks, 1997 .opt_clks = omap2430_mmc2_opt_clks,
2655 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 1998 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2656 .main_clk = "mmchs2_fck", 1999 .main_clk = "mmchs2_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
new file mode 100644
index 000000000000..04637fabadd2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -0,0 +1,173 @@
1/*
2 * omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <asm/sizes.h>
15
16#include <plat/omap_hwmod.h>
17#include <plat/serial.h>
18
19#include "omap_hwmod_common_data.h"
20
21struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
22 {
23 .pa_start = 0x4809c000,
24 .pa_end = 0x4809c1ff,
25 .flags = ADDR_TYPE_RT,
26 },
27 { }
28};
29
30struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
31 {
32 .pa_start = 0x480b4000,
33 .pa_end = 0x480b41ff,
34 .flags = ADDR_TYPE_RT,
35 },
36 { }
37};
38
39struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
40 {
41 .pa_start = 0x48070000,
42 .pa_end = 0x48070000 + SZ_128 - 1,
43 .flags = ADDR_TYPE_RT,
44 },
45 { }
46};
47
48struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
49 {
50 .pa_start = 0x48072000,
51 .pa_end = 0x48072000 + SZ_128 - 1,
52 .flags = ADDR_TYPE_RT,
53 },
54 { }
55};
56
57struct omap_hwmod_addr_space omap2_dss_addrs[] = {
58 {
59 .pa_start = 0x48050000,
60 .pa_end = 0x48050000 + SZ_1K - 1,
61 .flags = ADDR_TYPE_RT
62 },
63 { }
64};
65
66struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
67 {
68 .pa_start = 0x48050400,
69 .pa_end = 0x48050400 + SZ_1K - 1,
70 .flags = ADDR_TYPE_RT
71 },
72 { }
73};
74
75struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
76 {
77 .pa_start = 0x48050800,
78 .pa_end = 0x48050800 + SZ_1K - 1,
79 .flags = ADDR_TYPE_RT
80 },
81 { }
82};
83
84struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
85 {
86 .pa_start = 0x48050C00,
87 .pa_end = 0x48050C00 + SZ_1K - 1,
88 .flags = ADDR_TYPE_RT
89 },
90 { }
91};
92
93struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
94 {
95 .pa_start = 0x48086000,
96 .pa_end = 0x48086000 + SZ_1K - 1,
97 .flags = ADDR_TYPE_RT
98 },
99 { }
100};
101
102struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
103 {
104 .pa_start = 0x48088000,
105 .pa_end = 0x48088000 + SZ_1K - 1,
106 .flags = ADDR_TYPE_RT
107 },
108 { }
109};
110
111struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
112 {
113 .pa_start = 0x4808a000,
114 .pa_end = 0x4808a000 + SZ_1K - 1,
115 .flags = ADDR_TYPE_RT
116 },
117 { }
118};
119
120struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
121 {
122 .pa_start = 0x48098000,
123 .pa_end = 0x48098000 + SZ_256 - 1,
124 .flags = ADDR_TYPE_RT,
125 },
126 { }
127};
128
129struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
130 {
131 .pa_start = 0x4809a000,
132 .pa_end = 0x4809a000 + SZ_256 - 1,
133 .flags = ADDR_TYPE_RT,
134 },
135 { }
136};
137
138struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
139 {
140 .pa_start = 0x480b8000,
141 .pa_end = 0x480b8000 + SZ_256 - 1,
142 .flags = ADDR_TYPE_RT,
143 },
144 { }
145};
146
147struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
148 {
149 .pa_start = 0x48056000,
150 .pa_end = 0x48056000 + SZ_4K - 1,
151 .flags = ADDR_TYPE_RT
152 },
153 { }
154};
155
156struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
157 {
158 .pa_start = 0x48094000,
159 .pa_end = 0x48094000 + SZ_512 - 1,
160 .flags = ADDR_TYPE_RT,
161 },
162 { }
163};
164
165struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
166 {
167 .name = "mpu",
168 .pa_start = 0x48074000,
169 .pa_end = 0x480740ff,
170 .flags = ADDR_TYPE_RT
171 },
172 { }
173};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
new file mode 100644
index 000000000000..c451729d289a
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -0,0 +1,322 @@
1/*
2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>
13#include <plat/dma.h>
14
15#include <mach/irqs.h>
16
17#include "omap_hwmod_common_data.h"
18
19/* UART */
20
21static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
22 .rev_offs = 0x50,
23 .sysc_offs = 0x54,
24 .syss_offs = 0x58,
25 .sysc_flags = (SYSC_HAS_SIDLEMODE |
26 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
27 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
29 .sysc_fields = &omap_hwmod_sysc_type1,
30};
31
32struct omap_hwmod_class omap2_uart_class = {
33 .name = "uart",
34 .sysc = &omap2_uart_sysc,
35};
36
37/*
38 * 'dss' class
39 * display sub-system
40 */
41
42static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
43 .rev_offs = 0x0000,
44 .sysc_offs = 0x0010,
45 .syss_offs = 0x0014,
46 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50struct omap_hwmod_class omap2_dss_hwmod_class = {
51 .name = "dss",
52 .sysc = &omap2_dss_sysc,
53};
54
55/*
56 * 'dispc' class
57 * display controller
58 */
59
60static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
61 .rev_offs = 0x0000,
62 .sysc_offs = 0x0010,
63 .syss_offs = 0x0014,
64 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
65 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
66 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
67 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
68 .sysc_fields = &omap_hwmod_sysc_type1,
69};
70
71struct omap_hwmod_class omap2_dispc_hwmod_class = {
72 .name = "dispc",
73 .sysc = &omap2_dispc_sysc,
74};
75
76/*
77 * 'rfbi' class
78 * remote frame buffer interface
79 */
80
81static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
86 SYSC_HAS_AUTOIDLE),
87 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
88 .sysc_fields = &omap_hwmod_sysc_type1,
89};
90
91struct omap_hwmod_class omap2_rfbi_hwmod_class = {
92 .name = "rfbi",
93 .sysc = &omap2_rfbi_sysc,
94};
95
96/*
97 * 'venc' class
98 * video encoder
99 */
100
101struct omap_hwmod_class omap2_venc_hwmod_class = {
102 .name = "venc",
103};
104
105
106/* Common DMA request line data */
107struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
108 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
109 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
110 { .dma_req = -1 }
111};
112
113struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
114 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
115 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
116 { .dma_req = -1 }
117};
118
119struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
120 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
121 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
122 { .dma_req = -1 }
123};
124
125struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
126 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
127 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
128 { .dma_req = -1 }
129};
130
131struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
132 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
133 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
134 { .dma_req = -1 }
135};
136
137struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
138 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
139 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
140 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
141 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
142 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
143 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
144 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
145 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
146 { .dma_req = -1 }
147};
148
149struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
150 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
151 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
152 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
153 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
154 { .dma_req = -1 }
155};
156
157struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
158 { .name = "rx", .dma_req = 32 },
159 { .name = "tx", .dma_req = 31 },
160 { .dma_req = -1 }
161};
162
163struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
164 { .name = "rx", .dma_req = 34 },
165 { .name = "tx", .dma_req = 33 },
166 { .dma_req = -1 }
167};
168
169struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
170 { .name = "rx", .dma_req = 18 },
171 { .name = "tx", .dma_req = 17 },
172 { .dma_req = -1 }
173};
174
175/* Other IP block data */
176
177
178/*
179 * omap_hwmod class data
180 */
181
182struct omap_hwmod_class l3_hwmod_class = {
183 .name = "l3"
184};
185
186struct omap_hwmod_class l4_hwmod_class = {
187 .name = "l4"
188};
189
190struct omap_hwmod_class mpu_hwmod_class = {
191 .name = "mpu"
192};
193
194struct omap_hwmod_class iva_hwmod_class = {
195 .name = "iva"
196};
197
198/* Common MPU IRQ line data */
199
200struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
201 { .irq = 37, },
202 { .irq = -1 }
203};
204
205struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
206 { .irq = 38, },
207 { .irq = -1 }
208};
209
210struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
211 { .irq = 39, },
212 { .irq = -1 }
213};
214
215struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
216 { .irq = 40, },
217 { .irq = -1 }
218};
219
220struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
221 { .irq = 41, },
222 { .irq = -1 }
223};
224
225struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
226 { .irq = 42, },
227 { .irq = -1 }
228};
229
230struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
231 { .irq = 43, },
232 { .irq = -1 }
233};
234
235struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
236 { .irq = 44, },
237 { .irq = -1 }
238};
239
240struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
241 { .irq = 45, },
242 { .irq = -1 }
243};
244
245struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
246 { .irq = 46, },
247 { .irq = -1 }
248};
249
250struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
251 { .irq = 47, },
252 { .irq = -1 }
253};
254
255struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
256 { .irq = INT_24XX_UART1_IRQ, },
257 { .irq = -1 }
258};
259
260struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
261 { .irq = INT_24XX_UART2_IRQ, },
262 { .irq = -1 }
263};
264
265struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
266 { .irq = INT_24XX_UART3_IRQ, },
267 { .irq = -1 }
268};
269
270struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
271 { .irq = 25 },
272 { .irq = -1 }
273};
274
275struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
276 { .irq = INT_24XX_I2C1_IRQ, },
277 { .irq = -1 }
278};
279
280struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
281 { .irq = INT_24XX_I2C2_IRQ, },
282 { .irq = -1 }
283};
284
285struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
286 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
287 { .irq = -1 }
288};
289
290struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
291 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
292 { .irq = -1 }
293};
294
295struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
296 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
297 { .irq = -1 }
298};
299
300struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
301 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
302 { .irq = -1 }
303};
304
305struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
306 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
307 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
308 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
309 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
310 { .irq = -1 }
311};
312
313struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
314 { .irq = 65 },
315 { .irq = -1 }
316};
317
318struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
319 { .irq = 66 },
320 { .irq = -1 }
321};
322
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
new file mode 100644
index 000000000000..4f3547c2a49e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -0,0 +1,130 @@
1/*
2 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <asm/sizes.h>
15
16#include <plat/omap_hwmod.h>
17#include <plat/serial.h>
18
19#include "omap_hwmod_common_data.h"
20
21struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
22 {
23 .pa_start = OMAP2_UART1_BASE,
24 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
25 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
26 },
27 { }
28};
29
30struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
31 {
32 .pa_start = OMAP2_UART2_BASE,
33 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
34 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
35 },
36 { }
37};
38
39struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
40 {
41 .pa_start = OMAP2_UART3_BASE,
42 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
43 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
44 },
45 { }
46};
47
48struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
49 {
50 .pa_start = 0x4802a000,
51 .pa_end = 0x4802a000 + SZ_1K - 1,
52 .flags = ADDR_TYPE_RT
53 },
54 { }
55};
56
57struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
58 {
59 .pa_start = 0x48078000,
60 .pa_end = 0x48078000 + SZ_1K - 1,
61 .flags = ADDR_TYPE_RT
62 },
63 { }
64};
65
66struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
67 {
68 .pa_start = 0x4807a000,
69 .pa_end = 0x4807a000 + SZ_1K - 1,
70 .flags = ADDR_TYPE_RT
71 },
72 { }
73};
74
75struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
76 {
77 .pa_start = 0x4807c000,
78 .pa_end = 0x4807c000 + SZ_1K - 1,
79 .flags = ADDR_TYPE_RT
80 },
81 { }
82};
83
84struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
85 {
86 .pa_start = 0x4807e000,
87 .pa_end = 0x4807e000 + SZ_1K - 1,
88 .flags = ADDR_TYPE_RT
89 },
90 { }
91};
92
93struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
94 {
95 .pa_start = 0x48080000,
96 .pa_end = 0x48080000 + SZ_1K - 1,
97 .flags = ADDR_TYPE_RT
98 },
99 { }
100};
101
102struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
103 {
104 .pa_start = 0x48082000,
105 .pa_end = 0x48082000 + SZ_1K - 1,
106 .flags = ADDR_TYPE_RT
107 },
108 { }
109};
110
111struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
112 {
113 .pa_start = 0x48084000,
114 .pa_end = 0x48084000 + SZ_1K - 1,
115 .flags = ADDR_TYPE_RT
116 },
117 { }
118};
119
120struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
121 {
122 .name = "mpu",
123 .pa_start = 0x48076000,
124 .pa_end = 0x480760ff,
125 .flags = ADDR_TYPE_RT
126 },
127 { }
128};
129
130
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
new file mode 100644
index 000000000000..177dee20faef
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -0,0 +1,150 @@
1/*
2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>
13#include <plat/dma.h>
14#include <plat/dmtimer.h>
15#include <plat/mcspi.h>
16
17#include <mach/irqs.h>
18
19#include "omap_hwmod_common_data.h"
20#include "wd_timer.h"
21
22struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
23 { .irq = 48, },
24 { .irq = -1 }
25};
26
27struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
28 { .name = "dispc", .dma_req = 5 },
29 { .dma_req = -1 }
30};
31/* OMAP2xxx Timer Common */
32static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
33 .rev_offs = 0x0000,
34 .sysc_offs = 0x0010,
35 .syss_offs = 0x0014,
36 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
37 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
38 SYSC_HAS_AUTOIDLE),
39 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
40 .sysc_fields = &omap_hwmod_sysc_type1,
41};
42
43struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
44 .name = "timer",
45 .sysc = &omap2xxx_timer_sysc,
46 .rev = OMAP_TIMER_IP_VERSION_1,
47};
48
49/*
50 * 'wd_timer' class
51 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
52 * overflow condition
53 */
54
55static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
56 .rev_offs = 0x0000,
57 .sysc_offs = 0x0010,
58 .syss_offs = 0x0014,
59 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
60 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
61 .sysc_fields = &omap_hwmod_sysc_type1,
62};
63
64struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
65 .name = "wd_timer",
66 .sysc = &omap2xxx_wd_timer_sysc,
67 .pre_shutdown = &omap2_wd_timer_disable
68};
69
70/*
71 * 'gpio' class
72 * general purpose io module
73 */
74static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
75 .rev_offs = 0x0000,
76 .sysc_offs = 0x0010,
77 .syss_offs = 0x0014,
78 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
79 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
80 SYSS_HAS_RESET_STATUS),
81 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
82 .sysc_fields = &omap_hwmod_sysc_type1,
83};
84
85struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
86 .name = "gpio",
87 .sysc = &omap2xxx_gpio_sysc,
88 .rev = 0,
89};
90
91/* system dma */
92static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
93 .rev_offs = 0x0000,
94 .sysc_offs = 0x002c,
95 .syss_offs = 0x0028,
96 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
97 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
98 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
99 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
100 .sysc_fields = &omap_hwmod_sysc_type1,
101};
102
103struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
104 .name = "dma",
105 .sysc = &omap2xxx_dma_sysc,
106};
107
108/*
109 * 'mailbox' class
110 * mailbox module allowing communication between the on-chip processors
111 * using a queued mailbox-interrupt mechanism.
112 */
113
114static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
115 .rev_offs = 0x000,
116 .sysc_offs = 0x010,
117 .syss_offs = 0x014,
118 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
119 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
120 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
121 .sysc_fields = &omap_hwmod_sysc_type1,
122};
123
124struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
125 .name = "mailbox",
126 .sysc = &omap2xxx_mailbox_sysc,
127};
128
129/*
130 * 'mcspi' class
131 * multichannel serial port interface (mcspi) / master/slave synchronous serial
132 * bus
133 */
134
135static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
136 .rev_offs = 0x0000,
137 .sysc_offs = 0x0010,
138 .syss_offs = 0x0014,
139 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
141 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
142 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
143 .sysc_fields = &omap_hwmod_sysc_type1,
144};
145
146struct omap_hwmod_class omap2xxx_mcspi_class = {
147 .name = "mcspi",
148 .sysc = &omap2xxx_mcspi_sysc,
149 .rev = OMAP2_MCSPI_REV,
150};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 909a84de6682..25bf43b5a4ec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
103static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 103static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ }, 104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ }, 105 { .irq = INT_34XX_L3_APP_IRQ },
106 { .irq = -1 }
106}; 107};
107 108
108static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { 109static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
@@ -111,6 +112,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_end = 0x6800ffff, 112 .pa_end = 0x6800ffff,
112 .flags = ADDR_TYPE_RT, 113 .flags = ADDR_TYPE_RT,
113 }, 114 },
115 { }
114}; 116};
115 117
116/* MPU -> L3 interface */ 118/* MPU -> L3 interface */
@@ -118,7 +120,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
118 .master = &omap3xxx_mpu_hwmod, 120 .master = &omap3xxx_mpu_hwmod,
119 .slave = &omap3xxx_l3_main_hwmod, 121 .slave = &omap3xxx_l3_main_hwmod,
120 .addr = omap3xxx_l3_main_addrs, 122 .addr = omap3xxx_l3_main_addrs,
121 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
122 .user = OCP_USER_MPU, 123 .user = OCP_USER_MPU,
123}; 124};
124 125
@@ -150,8 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
150static struct omap_hwmod omap3xxx_l3_main_hwmod = { 151static struct omap_hwmod omap3xxx_l3_main_hwmod = {
151 .name = "l3_main", 152 .name = "l3_main",
152 .class = &l3_hwmod_class, 153 .class = &l3_hwmod_class,
153 .mpu_irqs = omap3xxx_l3_main_irqs, 154 .mpu_irqs = omap3xxx_l3_main_irqs,
154 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
155 .masters = omap3xxx_l3_main_masters, 155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves, 157 .slaves = omap3xxx_l3_main_slaves,
@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190}; 190};
191 191
192/* L4 CORE -> MMC1 interface */ 192/* L4 CORE -> MMC1 interface */
193static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
194 {
195 .pa_start = 0x4809c000,
196 .pa_end = 0x4809c1ff,
197 .flags = ADDR_TYPE_RT,
198 },
199};
200
201static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { 193static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
202 .master = &omap3xxx_l4_core_hwmod, 194 .master = &omap3xxx_l4_core_hwmod,
203 .slave = &omap3xxx_mmc1_hwmod, 195 .slave = &omap3xxx_mmc1_hwmod,
204 .clk = "mmchs1_ick", 196 .clk = "mmchs1_ick",
205 .addr = omap3xxx_mmc1_addr_space, 197 .addr = omap2430_mmc1_addr_space,
206 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
207 .user = OCP_USER_MPU | OCP_USER_SDMA, 198 .user = OCP_USER_MPU | OCP_USER_SDMA,
208 .flags = OMAP_FIREWALL_L4 199 .flags = OMAP_FIREWALL_L4
209}; 200};
210 201
211/* L4 CORE -> MMC2 interface */ 202/* L4 CORE -> MMC2 interface */
212static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
213 {
214 .pa_start = 0x480b4000,
215 .pa_end = 0x480b41ff,
216 .flags = ADDR_TYPE_RT,
217 },
218};
219
220static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { 203static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
221 .master = &omap3xxx_l4_core_hwmod, 204 .master = &omap3xxx_l4_core_hwmod,
222 .slave = &omap3xxx_mmc2_hwmod, 205 .slave = &omap3xxx_mmc2_hwmod,
223 .clk = "mmchs2_ick", 206 .clk = "mmchs2_ick",
224 .addr = omap3xxx_mmc2_addr_space, 207 .addr = omap2430_mmc2_addr_space,
225 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
226 .user = OCP_USER_MPU | OCP_USER_SDMA, 208 .user = OCP_USER_MPU | OCP_USER_SDMA,
227 .flags = OMAP_FIREWALL_L4 209 .flags = OMAP_FIREWALL_L4
228}; 210};
@@ -234,6 +216,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
234 .pa_end = 0x480ad1ff, 216 .pa_end = 0x480ad1ff,
235 .flags = ADDR_TYPE_RT, 217 .flags = ADDR_TYPE_RT,
236 }, 218 },
219 { }
237}; 220};
238 221
239static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 222static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
@@ -241,7 +224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
241 .slave = &omap3xxx_mmc3_hwmod, 224 .slave = &omap3xxx_mmc3_hwmod,
242 .clk = "mmchs3_ick", 225 .clk = "mmchs3_ick",
243 .addr = omap3xxx_mmc3_addr_space, 226 .addr = omap3xxx_mmc3_addr_space,
244 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
245 .user = OCP_USER_MPU | OCP_USER_SDMA, 227 .user = OCP_USER_MPU | OCP_USER_SDMA,
246 .flags = OMAP_FIREWALL_L4 228 .flags = OMAP_FIREWALL_L4
247}; 229};
@@ -253,6 +235,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
253 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
255 }, 237 },
238 { }
256}; 239};
257 240
258static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 241static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
@@ -260,7 +243,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
260 .slave = &omap3xxx_uart1_hwmod, 243 .slave = &omap3xxx_uart1_hwmod,
261 .clk = "uart1_ick", 244 .clk = "uart1_ick",
262 .addr = omap3xxx_uart1_addr_space, 245 .addr = omap3xxx_uart1_addr_space,
263 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
264 .user = OCP_USER_MPU | OCP_USER_SDMA, 246 .user = OCP_USER_MPU | OCP_USER_SDMA,
265}; 247};
266 248
@@ -271,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
271 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
273 }, 255 },
256 { }
274}; 257};
275 258
276static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 259static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
@@ -278,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
278 .slave = &omap3xxx_uart2_hwmod, 261 .slave = &omap3xxx_uart2_hwmod,
279 .clk = "uart2_ick", 262 .clk = "uart2_ick",
280 .addr = omap3xxx_uart2_addr_space, 263 .addr = omap3xxx_uart2_addr_space,
281 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
282 .user = OCP_USER_MPU | OCP_USER_SDMA, 264 .user = OCP_USER_MPU | OCP_USER_SDMA,
283}; 265};
284 266
@@ -289,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
289 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
291 }, 273 },
274 { }
292}; 275};
293 276
294static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 277static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
@@ -296,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
296 .slave = &omap3xxx_uart3_hwmod, 279 .slave = &omap3xxx_uart3_hwmod,
297 .clk = "uart3_ick", 280 .clk = "uart3_ick",
298 .addr = omap3xxx_uart3_addr_space, 281 .addr = omap3xxx_uart3_addr_space,
299 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
300 .user = OCP_USER_MPU | OCP_USER_SDMA, 282 .user = OCP_USER_MPU | OCP_USER_SDMA,
301}; 283};
302 284
@@ -307,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
307 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
308 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
309 }, 291 },
292 { }
310}; 293};
311 294
312static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { 295static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
@@ -314,28 +297,15 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
314 .slave = &omap3xxx_uart4_hwmod, 297 .slave = &omap3xxx_uart4_hwmod,
315 .clk = "uart4_ick", 298 .clk = "uart4_ick",
316 .addr = omap3xxx_uart4_addr_space, 299 .addr = omap3xxx_uart4_addr_space,
317 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
318 .user = OCP_USER_MPU | OCP_USER_SDMA, 300 .user = OCP_USER_MPU | OCP_USER_SDMA,
319}; 301};
320 302
321/* I2C IP block address space length (in bytes) */
322#define OMAP2_I2C_AS_LEN 128
323
324/* L4 CORE -> I2C1 interface */ 303/* L4 CORE -> I2C1 interface */
325static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
326 {
327 .pa_start = 0x48070000,
328 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
329 .flags = ADDR_TYPE_RT,
330 },
331};
332
333static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 304static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
334 .master = &omap3xxx_l4_core_hwmod, 305 .master = &omap3xxx_l4_core_hwmod,
335 .slave = &omap3xxx_i2c1_hwmod, 306 .slave = &omap3xxx_i2c1_hwmod,
336 .clk = "i2c1_ick", 307 .clk = "i2c1_ick",
337 .addr = omap3xxx_i2c1_addr_space, 308 .addr = omap2_i2c1_addr_space,
338 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
339 .fw = { 309 .fw = {
340 .omap2 = { 310 .omap2 = {
341 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
347}; 317};
348 318
349/* L4 CORE -> I2C2 interface */ 319/* L4 CORE -> I2C2 interface */
350static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
351 {
352 .pa_start = 0x48072000,
353 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
354 .flags = ADDR_TYPE_RT,
355 },
356};
357
358static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 320static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
359 .master = &omap3xxx_l4_core_hwmod, 321 .master = &omap3xxx_l4_core_hwmod,
360 .slave = &omap3xxx_i2c2_hwmod, 322 .slave = &omap3xxx_i2c2_hwmod,
361 .clk = "i2c2_ick", 323 .clk = "i2c2_ick",
362 .addr = omap3xxx_i2c2_addr_space, 324 .addr = omap2_i2c2_addr_space,
363 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
364 .fw = { 325 .fw = {
365 .omap2 = { 326 .omap2 = {
366 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
@@ -375,9 +336,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
375static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { 336static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
376 { 337 {
377 .pa_start = 0x48060000, 338 .pa_start = 0x48060000,
378 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, 339 .pa_end = 0x48060000 + SZ_128 - 1,
379 .flags = ADDR_TYPE_RT, 340 .flags = ADDR_TYPE_RT,
380 }, 341 },
342 { }
381}; 343};
382 344
383static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 345static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
@@ -385,7 +347,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
385 .slave = &omap3xxx_i2c3_hwmod, 347 .slave = &omap3xxx_i2c3_hwmod,
386 .clk = "i2c3_ick", 348 .clk = "i2c3_ick",
387 .addr = omap3xxx_i2c3_addr_space, 349 .addr = omap3xxx_i2c3_addr_space,
388 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
389 .fw = { 350 .fw = {
390 .omap2 = { 351 .omap2 = {
391 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
@@ -403,6 +364,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
403 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
404 .flags = ADDR_TYPE_RT, 365 .flags = ADDR_TYPE_RT,
405 }, 366 },
367 { }
406}; 368};
407 369
408static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { 370static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
@@ -410,7 +372,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
410 .slave = &omap34xx_sr1_hwmod, 372 .slave = &omap34xx_sr1_hwmod,
411 .clk = "sr_l4_ick", 373 .clk = "sr_l4_ick",
412 .addr = omap3_sr1_addr_space, 374 .addr = omap3_sr1_addr_space,
413 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
414 .user = OCP_USER_MPU, 375 .user = OCP_USER_MPU,
415}; 376};
416 377
@@ -421,6 +382,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
421 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
422 .flags = ADDR_TYPE_RT, 383 .flags = ADDR_TYPE_RT,
423 }, 384 },
385 { }
424}; 386};
425 387
426static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { 388static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
@@ -428,7 +390,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
428 .slave = &omap34xx_sr2_hwmod, 390 .slave = &omap34xx_sr2_hwmod,
429 .clk = "sr_l4_ick", 391 .clk = "sr_l4_ick",
430 .addr = omap3_sr2_addr_space, 392 .addr = omap3_sr2_addr_space,
431 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
432 .user = OCP_USER_MPU, 393 .user = OCP_USER_MPU,
433}; 394};
434 395
@@ -442,6 +403,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
442 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, 403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
443 .flags = ADDR_TYPE_RT 404 .flags = ADDR_TYPE_RT
444 }, 405 },
406 { }
445}; 407};
446 408
447/* l4_core -> usbhsotg */ 409/* l4_core -> usbhsotg */
@@ -450,7 +412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
450 .slave = &omap3xxx_usbhsotg_hwmod, 412 .slave = &omap3xxx_usbhsotg_hwmod,
451 .clk = "l4_ick", 413 .clk = "l4_ick",
452 .addr = omap3xxx_usbhsotg_addrs, 414 .addr = omap3xxx_usbhsotg_addrs,
453 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
454 .user = OCP_USER_MPU, 415 .user = OCP_USER_MPU,
455}; 416};
456 417
@@ -468,6 +429,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
468 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, 429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
469 .flags = ADDR_TYPE_RT 430 .flags = ADDR_TYPE_RT
470 }, 431 },
432 { }
471}; 433};
472 434
473/* l4_core -> usbhsotg */ 435/* l4_core -> usbhsotg */
@@ -476,7 +438,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
476 .slave = &am35xx_usbhsotg_hwmod, 438 .slave = &am35xx_usbhsotg_hwmod,
477 .clk = "l4_ick", 439 .clk = "l4_ick",
478 .addr = am35xx_usbhsotg_addrs, 440 .addr = am35xx_usbhsotg_addrs,
479 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
480 .user = OCP_USER_MPU, 441 .user = OCP_USER_MPU,
481}; 442};
482 443
@@ -611,9 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
611 572
612/* timer1 */ 573/* timer1 */
613static struct omap_hwmod omap3xxx_timer1_hwmod; 574static struct omap_hwmod omap3xxx_timer1_hwmod;
614static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
615 { .irq = 37, },
616};
617 575
618static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { 576static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
619 { 577 {
@@ -621,6 +579,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
621 .pa_end = 0x48318000 + SZ_1K - 1, 579 .pa_end = 0x48318000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT 580 .flags = ADDR_TYPE_RT
623 }, 581 },
582 { }
624}; 583};
625 584
626/* l4_wkup -> timer1 */ 585/* l4_wkup -> timer1 */
@@ -629,7 +588,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
629 .slave = &omap3xxx_timer1_hwmod, 588 .slave = &omap3xxx_timer1_hwmod,
630 .clk = "gpt1_ick", 589 .clk = "gpt1_ick",
631 .addr = omap3xxx_timer1_addrs, 590 .addr = omap3xxx_timer1_addrs,
632 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 591 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 592};
635 593
@@ -641,8 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
641/* timer1 hwmod */ 599/* timer1 hwmod */
642static struct omap_hwmod omap3xxx_timer1_hwmod = { 600static struct omap_hwmod omap3xxx_timer1_hwmod = {
643 .name = "timer1", 601 .name = "timer1",
644 .mpu_irqs = omap3xxx_timer1_mpu_irqs, 602 .mpu_irqs = omap2_timer1_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
646 .main_clk = "gpt1_fck", 603 .main_clk = "gpt1_fck",
647 .prcm = { 604 .prcm = {
648 .omap2 = { 605 .omap2 = {
@@ -661,9 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
661 618
662/* timer2 */ 619/* timer2 */
663static struct omap_hwmod omap3xxx_timer2_hwmod; 620static struct omap_hwmod omap3xxx_timer2_hwmod;
664static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
665 { .irq = 38, },
666};
667 621
668static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { 622static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
669 { 623 {
@@ -671,6 +625,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
671 .pa_end = 0x49032000 + SZ_1K - 1, 625 .pa_end = 0x49032000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT 626 .flags = ADDR_TYPE_RT
673 }, 627 },
628 { }
674}; 629};
675 630
676/* l4_per -> timer2 */ 631/* l4_per -> timer2 */
@@ -679,7 +634,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
679 .slave = &omap3xxx_timer2_hwmod, 634 .slave = &omap3xxx_timer2_hwmod,
680 .clk = "gpt2_ick", 635 .clk = "gpt2_ick",
681 .addr = omap3xxx_timer2_addrs, 636 .addr = omap3xxx_timer2_addrs,
682 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 637 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 638};
685 639
@@ -691,8 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
691/* timer2 hwmod */ 645/* timer2 hwmod */
692static struct omap_hwmod omap3xxx_timer2_hwmod = { 646static struct omap_hwmod omap3xxx_timer2_hwmod = {
693 .name = "timer2", 647 .name = "timer2",
694 .mpu_irqs = omap3xxx_timer2_mpu_irqs, 648 .mpu_irqs = omap2_timer2_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
696 .main_clk = "gpt2_fck", 649 .main_clk = "gpt2_fck",
697 .prcm = { 650 .prcm = {
698 .omap2 = { 651 .omap2 = {
@@ -711,9 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
711 664
712/* timer3 */ 665/* timer3 */
713static struct omap_hwmod omap3xxx_timer3_hwmod; 666static struct omap_hwmod omap3xxx_timer3_hwmod;
714static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
715 { .irq = 39, },
716};
717 667
718static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { 668static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
719 { 669 {
@@ -721,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
721 .pa_end = 0x49034000 + SZ_1K - 1, 671 .pa_end = 0x49034000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT 672 .flags = ADDR_TYPE_RT
723 }, 673 },
674 { }
724}; 675};
725 676
726/* l4_per -> timer3 */ 677/* l4_per -> timer3 */
@@ -729,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
729 .slave = &omap3xxx_timer3_hwmod, 680 .slave = &omap3xxx_timer3_hwmod,
730 .clk = "gpt3_ick", 681 .clk = "gpt3_ick",
731 .addr = omap3xxx_timer3_addrs, 682 .addr = omap3xxx_timer3_addrs,
732 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 683 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 684};
735 685
@@ -741,8 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
741/* timer3 hwmod */ 691/* timer3 hwmod */
742static struct omap_hwmod omap3xxx_timer3_hwmod = { 692static struct omap_hwmod omap3xxx_timer3_hwmod = {
743 .name = "timer3", 693 .name = "timer3",
744 .mpu_irqs = omap3xxx_timer3_mpu_irqs, 694 .mpu_irqs = omap2_timer3_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
746 .main_clk = "gpt3_fck", 695 .main_clk = "gpt3_fck",
747 .prcm = { 696 .prcm = {
748 .omap2 = { 697 .omap2 = {
@@ -761,9 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
761 710
762/* timer4 */ 711/* timer4 */
763static struct omap_hwmod omap3xxx_timer4_hwmod; 712static struct omap_hwmod omap3xxx_timer4_hwmod;
764static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
765 { .irq = 40, },
766};
767 713
768static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { 714static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
769 { 715 {
@@ -771,6 +717,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
771 .pa_end = 0x49036000 + SZ_1K - 1, 717 .pa_end = 0x49036000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT 718 .flags = ADDR_TYPE_RT
773 }, 719 },
720 { }
774}; 721};
775 722
776/* l4_per -> timer4 */ 723/* l4_per -> timer4 */
@@ -779,7 +726,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
779 .slave = &omap3xxx_timer4_hwmod, 726 .slave = &omap3xxx_timer4_hwmod,
780 .clk = "gpt4_ick", 727 .clk = "gpt4_ick",
781 .addr = omap3xxx_timer4_addrs, 728 .addr = omap3xxx_timer4_addrs,
782 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 729 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 730};
785 731
@@ -791,8 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
791/* timer4 hwmod */ 737/* timer4 hwmod */
792static struct omap_hwmod omap3xxx_timer4_hwmod = { 738static struct omap_hwmod omap3xxx_timer4_hwmod = {
793 .name = "timer4", 739 .name = "timer4",
794 .mpu_irqs = omap3xxx_timer4_mpu_irqs, 740 .mpu_irqs = omap2_timer4_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
796 .main_clk = "gpt4_fck", 741 .main_clk = "gpt4_fck",
797 .prcm = { 742 .prcm = {
798 .omap2 = { 743 .omap2 = {
@@ -811,9 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
811 756
812/* timer5 */ 757/* timer5 */
813static struct omap_hwmod omap3xxx_timer5_hwmod; 758static struct omap_hwmod omap3xxx_timer5_hwmod;
814static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
815 { .irq = 41, },
816};
817 759
818static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { 760static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
819 { 761 {
@@ -821,6 +763,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
821 .pa_end = 0x49038000 + SZ_1K - 1, 763 .pa_end = 0x49038000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT 764 .flags = ADDR_TYPE_RT
823 }, 765 },
766 { }
824}; 767};
825 768
826/* l4_per -> timer5 */ 769/* l4_per -> timer5 */
@@ -829,7 +772,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
829 .slave = &omap3xxx_timer5_hwmod, 772 .slave = &omap3xxx_timer5_hwmod,
830 .clk = "gpt5_ick", 773 .clk = "gpt5_ick",
831 .addr = omap3xxx_timer5_addrs, 774 .addr = omap3xxx_timer5_addrs,
832 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 775 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 776};
835 777
@@ -841,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
841/* timer5 hwmod */ 783/* timer5 hwmod */
842static struct omap_hwmod omap3xxx_timer5_hwmod = { 784static struct omap_hwmod omap3xxx_timer5_hwmod = {
843 .name = "timer5", 785 .name = "timer5",
844 .mpu_irqs = omap3xxx_timer5_mpu_irqs, 786 .mpu_irqs = omap2_timer5_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
846 .main_clk = "gpt5_fck", 787 .main_clk = "gpt5_fck",
847 .prcm = { 788 .prcm = {
848 .omap2 = { 789 .omap2 = {
@@ -861,9 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
861 802
862/* timer6 */ 803/* timer6 */
863static struct omap_hwmod omap3xxx_timer6_hwmod; 804static struct omap_hwmod omap3xxx_timer6_hwmod;
864static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
865 { .irq = 42, },
866};
867 805
868static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { 806static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
869 { 807 {
@@ -871,6 +809,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
871 .pa_end = 0x4903A000 + SZ_1K - 1, 809 .pa_end = 0x4903A000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT 810 .flags = ADDR_TYPE_RT
873 }, 811 },
812 { }
874}; 813};
875 814
876/* l4_per -> timer6 */ 815/* l4_per -> timer6 */
@@ -879,7 +818,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
879 .slave = &omap3xxx_timer6_hwmod, 818 .slave = &omap3xxx_timer6_hwmod,
880 .clk = "gpt6_ick", 819 .clk = "gpt6_ick",
881 .addr = omap3xxx_timer6_addrs, 820 .addr = omap3xxx_timer6_addrs,
882 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 821 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 822};
885 823
@@ -891,8 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
891/* timer6 hwmod */ 829/* timer6 hwmod */
892static struct omap_hwmod omap3xxx_timer6_hwmod = { 830static struct omap_hwmod omap3xxx_timer6_hwmod = {
893 .name = "timer6", 831 .name = "timer6",
894 .mpu_irqs = omap3xxx_timer6_mpu_irqs, 832 .mpu_irqs = omap2_timer6_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
896 .main_clk = "gpt6_fck", 833 .main_clk = "gpt6_fck",
897 .prcm = { 834 .prcm = {
898 .omap2 = { 835 .omap2 = {
@@ -911,9 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
911 848
912/* timer7 */ 849/* timer7 */
913static struct omap_hwmod omap3xxx_timer7_hwmod; 850static struct omap_hwmod omap3xxx_timer7_hwmod;
914static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
915 { .irq = 43, },
916};
917 851
918static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { 852static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
919 { 853 {
@@ -921,6 +855,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
921 .pa_end = 0x4903C000 + SZ_1K - 1, 855 .pa_end = 0x4903C000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT 856 .flags = ADDR_TYPE_RT
923 }, 857 },
858 { }
924}; 859};
925 860
926/* l4_per -> timer7 */ 861/* l4_per -> timer7 */
@@ -929,7 +864,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
929 .slave = &omap3xxx_timer7_hwmod, 864 .slave = &omap3xxx_timer7_hwmod,
930 .clk = "gpt7_ick", 865 .clk = "gpt7_ick",
931 .addr = omap3xxx_timer7_addrs, 866 .addr = omap3xxx_timer7_addrs,
932 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 867 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 868};
935 869
@@ -941,8 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
941/* timer7 hwmod */ 875/* timer7 hwmod */
942static struct omap_hwmod omap3xxx_timer7_hwmod = { 876static struct omap_hwmod omap3xxx_timer7_hwmod = {
943 .name = "timer7", 877 .name = "timer7",
944 .mpu_irqs = omap3xxx_timer7_mpu_irqs, 878 .mpu_irqs = omap2_timer7_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
946 .main_clk = "gpt7_fck", 879 .main_clk = "gpt7_fck",
947 .prcm = { 880 .prcm = {
948 .omap2 = { 881 .omap2 = {
@@ -961,9 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
961 894
962/* timer8 */ 895/* timer8 */
963static struct omap_hwmod omap3xxx_timer8_hwmod; 896static struct omap_hwmod omap3xxx_timer8_hwmod;
964static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
965 { .irq = 44, },
966};
967 897
968static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { 898static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
969 { 899 {
@@ -971,6 +901,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
971 .pa_end = 0x4903E000 + SZ_1K - 1, 901 .pa_end = 0x4903E000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT 902 .flags = ADDR_TYPE_RT
973 }, 903 },
904 { }
974}; 905};
975 906
976/* l4_per -> timer8 */ 907/* l4_per -> timer8 */
@@ -979,7 +910,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
979 .slave = &omap3xxx_timer8_hwmod, 910 .slave = &omap3xxx_timer8_hwmod,
980 .clk = "gpt8_ick", 911 .clk = "gpt8_ick",
981 .addr = omap3xxx_timer8_addrs, 912 .addr = omap3xxx_timer8_addrs,
982 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA, 913 .user = OCP_USER_MPU | OCP_USER_SDMA,
984}; 914};
985 915
@@ -991,8 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
991/* timer8 hwmod */ 921/* timer8 hwmod */
992static struct omap_hwmod omap3xxx_timer8_hwmod = { 922static struct omap_hwmod omap3xxx_timer8_hwmod = {
993 .name = "timer8", 923 .name = "timer8",
994 .mpu_irqs = omap3xxx_timer8_mpu_irqs, 924 .mpu_irqs = omap2_timer8_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
996 .main_clk = "gpt8_fck", 925 .main_clk = "gpt8_fck",
997 .prcm = { 926 .prcm = {
998 .omap2 = { 927 .omap2 = {
@@ -1011,9 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
1011 940
1012/* timer9 */ 941/* timer9 */
1013static struct omap_hwmod omap3xxx_timer9_hwmod; 942static struct omap_hwmod omap3xxx_timer9_hwmod;
1014static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1015 { .irq = 45, },
1016};
1017 943
1018static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { 944static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1019 { 945 {
@@ -1021,6 +947,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1021 .pa_end = 0x49040000 + SZ_1K - 1, 947 .pa_end = 0x49040000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT 948 .flags = ADDR_TYPE_RT
1023 }, 949 },
950 { }
1024}; 951};
1025 952
1026/* l4_per -> timer9 */ 953/* l4_per -> timer9 */
@@ -1029,7 +956,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1029 .slave = &omap3xxx_timer9_hwmod, 956 .slave = &omap3xxx_timer9_hwmod,
1030 .clk = "gpt9_ick", 957 .clk = "gpt9_ick",
1031 .addr = omap3xxx_timer9_addrs, 958 .addr = omap3xxx_timer9_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA, 959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034}; 960};
1035 961
@@ -1041,8 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1041/* timer9 hwmod */ 967/* timer9 hwmod */
1042static struct omap_hwmod omap3xxx_timer9_hwmod = { 968static struct omap_hwmod omap3xxx_timer9_hwmod = {
1043 .name = "timer9", 969 .name = "timer9",
1044 .mpu_irqs = omap3xxx_timer9_mpu_irqs, 970 .mpu_irqs = omap2_timer9_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1046 .main_clk = "gpt9_fck", 971 .main_clk = "gpt9_fck",
1047 .prcm = { 972 .prcm = {
1048 .omap2 = { 973 .omap2 = {
@@ -1061,25 +986,13 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
1061 986
1062/* timer10 */ 987/* timer10 */
1063static struct omap_hwmod omap3xxx_timer10_hwmod; 988static struct omap_hwmod omap3xxx_timer10_hwmod;
1064static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1065 { .irq = 46, },
1066};
1067
1068static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1069 {
1070 .pa_start = 0x48086000,
1071 .pa_end = 0x48086000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1073 },
1074};
1075 989
1076/* l4_core -> timer10 */ 990/* l4_core -> timer10 */
1077static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 991static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1078 .master = &omap3xxx_l4_core_hwmod, 992 .master = &omap3xxx_l4_core_hwmod,
1079 .slave = &omap3xxx_timer10_hwmod, 993 .slave = &omap3xxx_timer10_hwmod,
1080 .clk = "gpt10_ick", 994 .clk = "gpt10_ick",
1081 .addr = omap3xxx_timer10_addrs, 995 .addr = omap2_timer10_addrs,
1082 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1083 .user = OCP_USER_MPU | OCP_USER_SDMA, 996 .user = OCP_USER_MPU | OCP_USER_SDMA,
1084}; 997};
1085 998
@@ -1091,8 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1091/* timer10 hwmod */ 1004/* timer10 hwmod */
1092static struct omap_hwmod omap3xxx_timer10_hwmod = { 1005static struct omap_hwmod omap3xxx_timer10_hwmod = {
1093 .name = "timer10", 1006 .name = "timer10",
1094 .mpu_irqs = omap3xxx_timer10_mpu_irqs, 1007 .mpu_irqs = omap2_timer10_mpu_irqs,
1095 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1096 .main_clk = "gpt10_fck", 1008 .main_clk = "gpt10_fck",
1097 .prcm = { 1009 .prcm = {
1098 .omap2 = { 1010 .omap2 = {
@@ -1111,25 +1023,13 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
1111 1023
1112/* timer11 */ 1024/* timer11 */
1113static struct omap_hwmod omap3xxx_timer11_hwmod; 1025static struct omap_hwmod omap3xxx_timer11_hwmod;
1114static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1115 { .irq = 47, },
1116};
1117
1118static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1119 {
1120 .pa_start = 0x48088000,
1121 .pa_end = 0x48088000 + SZ_1K - 1,
1122 .flags = ADDR_TYPE_RT
1123 },
1124};
1125 1026
1126/* l4_core -> timer11 */ 1027/* l4_core -> timer11 */
1127static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 1028static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1128 .master = &omap3xxx_l4_core_hwmod, 1029 .master = &omap3xxx_l4_core_hwmod,
1129 .slave = &omap3xxx_timer11_hwmod, 1030 .slave = &omap3xxx_timer11_hwmod,
1130 .clk = "gpt11_ick", 1031 .clk = "gpt11_ick",
1131 .addr = omap3xxx_timer11_addrs, 1032 .addr = omap2_timer11_addrs,
1132 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1133 .user = OCP_USER_MPU | OCP_USER_SDMA, 1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1134}; 1034};
1135 1035
@@ -1141,8 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1141/* timer11 hwmod */ 1041/* timer11 hwmod */
1142static struct omap_hwmod omap3xxx_timer11_hwmod = { 1042static struct omap_hwmod omap3xxx_timer11_hwmod = {
1143 .name = "timer11", 1043 .name = "timer11",
1144 .mpu_irqs = omap3xxx_timer11_mpu_irqs, 1044 .mpu_irqs = omap2_timer11_mpu_irqs,
1145 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1146 .main_clk = "gpt11_fck", 1045 .main_clk = "gpt11_fck",
1147 .prcm = { 1046 .prcm = {
1148 .omap2 = { 1047 .omap2 = {
@@ -1163,6 +1062,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
1163static struct omap_hwmod omap3xxx_timer12_hwmod; 1062static struct omap_hwmod omap3xxx_timer12_hwmod;
1164static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 1063static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1165 { .irq = 95, }, 1064 { .irq = 95, },
1065 { .irq = -1 }
1166}; 1066};
1167 1067
1168static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { 1068static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
@@ -1171,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1171 .pa_end = 0x48304000 + SZ_1K - 1, 1071 .pa_end = 0x48304000 + SZ_1K - 1,
1172 .flags = ADDR_TYPE_RT 1072 .flags = ADDR_TYPE_RT
1173 }, 1073 },
1074 { }
1174}; 1075};
1175 1076
1176/* l4_core -> timer12 */ 1077/* l4_core -> timer12 */
@@ -1179,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1179 .slave = &omap3xxx_timer12_hwmod, 1080 .slave = &omap3xxx_timer12_hwmod,
1180 .clk = "gpt12_ick", 1081 .clk = "gpt12_ick",
1181 .addr = omap3xxx_timer12_addrs, 1082 .addr = omap3xxx_timer12_addrs,
1182 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1183 .user = OCP_USER_MPU | OCP_USER_SDMA, 1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1184}; 1084};
1185 1085
@@ -1192,7 +1092,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1192static struct omap_hwmod omap3xxx_timer12_hwmod = { 1092static struct omap_hwmod omap3xxx_timer12_hwmod = {
1193 .name = "timer12", 1093 .name = "timer12",
1194 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 1094 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1195 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1196 .main_clk = "gpt12_fck", 1095 .main_clk = "gpt12_fck",
1197 .prcm = { 1096 .prcm = {
1198 .omap2 = { 1097 .omap2 = {
@@ -1216,6 +1115,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1216 .pa_end = 0x4831407f, 1115 .pa_end = 0x4831407f,
1217 .flags = ADDR_TYPE_RT 1116 .flags = ADDR_TYPE_RT
1218 }, 1117 },
1118 { }
1219}; 1119};
1220 1120
1221static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 1121static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@@ -1223,7 +1123,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1223 .slave = &omap3xxx_wd_timer2_hwmod, 1123 .slave = &omap3xxx_wd_timer2_hwmod,
1224 .clk = "wdt2_ick", 1124 .clk = "wdt2_ick",
1225 .addr = omap3xxx_wd_timer2_addrs, 1125 .addr = omap3xxx_wd_timer2_addrs,
1226 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1227 .user = OCP_USER_MPU | OCP_USER_SDMA, 1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1228}; 1127};
1229 1128
@@ -1291,45 +1190,16 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1291 .flags = HWMOD_SWSUP_SIDLE, 1190 .flags = HWMOD_SWSUP_SIDLE,
1292}; 1191};
1293 1192
1294/* UART common */
1295
1296static struct omap_hwmod_class_sysconfig uart_sysc = {
1297 .rev_offs = 0x50,
1298 .sysc_offs = 0x54,
1299 .syss_offs = 0x58,
1300 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1301 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1302 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304 .sysc_fields = &omap_hwmod_sysc_type1,
1305};
1306
1307static struct omap_hwmod_class uart_class = {
1308 .name = "uart",
1309 .sysc = &uart_sysc,
1310};
1311
1312/* UART1 */ 1193/* UART1 */
1313 1194
1314static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1315 { .irq = INT_24XX_UART1_IRQ, },
1316};
1317
1318static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1319 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1320 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1321};
1322
1323static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { 1195static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1324 &omap3_l4_core__uart1, 1196 &omap3_l4_core__uart1,
1325}; 1197};
1326 1198
1327static struct omap_hwmod omap3xxx_uart1_hwmod = { 1199static struct omap_hwmod omap3xxx_uart1_hwmod = {
1328 .name = "uart1", 1200 .name = "uart1",
1329 .mpu_irqs = uart1_mpu_irqs, 1201 .mpu_irqs = omap2_uart1_mpu_irqs,
1330 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 1202 .sdma_reqs = omap2_uart1_sdma_reqs,
1331 .sdma_reqs = uart1_sdma_reqs,
1332 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1333 .main_clk = "uart1_fck", 1203 .main_clk = "uart1_fck",
1334 .prcm = { 1204 .prcm = {
1335 .omap2 = { 1205 .omap2 = {
@@ -1342,31 +1212,20 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
1342 }, 1212 },
1343 .slaves = omap3xxx_uart1_slaves, 1213 .slaves = omap3xxx_uart1_slaves,
1344 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), 1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1345 .class = &uart_class, 1215 .class = &omap2_uart_class,
1346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1347}; 1217};
1348 1218
1349/* UART2 */ 1219/* UART2 */
1350 1220
1351static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1352 { .irq = INT_24XX_UART2_IRQ, },
1353};
1354
1355static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1356 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1357 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1358};
1359
1360static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { 1221static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1361 &omap3_l4_core__uart2, 1222 &omap3_l4_core__uart2,
1362}; 1223};
1363 1224
1364static struct omap_hwmod omap3xxx_uart2_hwmod = { 1225static struct omap_hwmod omap3xxx_uart2_hwmod = {
1365 .name = "uart2", 1226 .name = "uart2",
1366 .mpu_irqs = uart2_mpu_irqs, 1227 .mpu_irqs = omap2_uart2_mpu_irqs,
1367 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 1228 .sdma_reqs = omap2_uart2_sdma_reqs,
1368 .sdma_reqs = uart2_sdma_reqs,
1369 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1370 .main_clk = "uart2_fck", 1229 .main_clk = "uart2_fck",
1371 .prcm = { 1230 .prcm = {
1372 .omap2 = { 1231 .omap2 = {
@@ -1379,31 +1238,20 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
1379 }, 1238 },
1380 .slaves = omap3xxx_uart2_slaves, 1239 .slaves = omap3xxx_uart2_slaves,
1381 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), 1240 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1382 .class = &uart_class, 1241 .class = &omap2_uart_class,
1383 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1384}; 1243};
1385 1244
1386/* UART3 */ 1245/* UART3 */
1387 1246
1388static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1389 { .irq = INT_24XX_UART3_IRQ, },
1390};
1391
1392static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1393 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1394 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1395};
1396
1397static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { 1247static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1398 &omap3_l4_per__uart3, 1248 &omap3_l4_per__uart3,
1399}; 1249};
1400 1250
1401static struct omap_hwmod omap3xxx_uart3_hwmod = { 1251static struct omap_hwmod omap3xxx_uart3_hwmod = {
1402 .name = "uart3", 1252 .name = "uart3",
1403 .mpu_irqs = uart3_mpu_irqs, 1253 .mpu_irqs = omap2_uart3_mpu_irqs,
1404 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 1254 .sdma_reqs = omap2_uart3_sdma_reqs,
1405 .sdma_reqs = uart3_sdma_reqs,
1406 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1407 .main_clk = "uart3_fck", 1255 .main_clk = "uart3_fck",
1408 .prcm = { 1256 .prcm = {
1409 .omap2 = { 1257 .omap2 = {
@@ -1416,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1416 }, 1264 },
1417 .slaves = omap3xxx_uart3_slaves, 1265 .slaves = omap3xxx_uart3_slaves,
1418 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), 1266 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1419 .class = &uart_class, 1267 .class = &omap2_uart_class,
1420 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1421}; 1269};
1422 1270
@@ -1424,11 +1272,13 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1424 1272
1425static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 1273static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1426 { .irq = INT_36XX_UART4_IRQ, }, 1274 { .irq = INT_36XX_UART4_IRQ, },
1275 { .irq = -1 }
1427}; 1276};
1428 1277
1429static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 1278static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1430 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, 1279 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1431 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, 1280 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1281 { .dma_req = -1 }
1432}; 1282};
1433 1283
1434static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 1284static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
@@ -1438,9 +1288,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1438static struct omap_hwmod omap3xxx_uart4_hwmod = { 1288static struct omap_hwmod omap3xxx_uart4_hwmod = {
1439 .name = "uart4", 1289 .name = "uart4",
1440 .mpu_irqs = uart4_mpu_irqs, 1290 .mpu_irqs = uart4_mpu_irqs,
1441 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1442 .sdma_reqs = uart4_sdma_reqs, 1291 .sdma_reqs = uart4_sdma_reqs,
1443 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1444 .main_clk = "uart4_fck", 1292 .main_clk = "uart4_fck",
1445 .prcm = { 1293 .prcm = {
1446 .omap2 = { 1294 .omap2 = {
@@ -1453,36 +1301,21 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1453 }, 1301 },
1454 .slaves = omap3xxx_uart4_slaves, 1302 .slaves = omap3xxx_uart4_slaves,
1455 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), 1303 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1456 .class = &uart_class, 1304 .class = &omap2_uart_class,
1457 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 1305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1458}; 1306};
1459 1307
1460static struct omap_hwmod_class i2c_class = { 1308static struct omap_hwmod_class i2c_class = {
1461 .name = "i2c", 1309 .name = "i2c",
1462 .sysc = &i2c_sysc, 1310 .sysc = &i2c_sysc,
1463}; 1311 .rev = OMAP_I2C_IP_VERSION_1,
1464 1312 .reset = &omap_i2c_reset,
1465/*
1466 * 'dss' class
1467 * display sub-system
1468 */
1469
1470static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1471 .rev_offs = 0x0000,
1472 .sysc_offs = 0x0010,
1473 .syss_offs = 0x0014,
1474 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1475 .sysc_fields = &omap_hwmod_sysc_type1,
1476};
1477
1478static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1479 .name = "dss",
1480 .sysc = &omap3xxx_dss_sysc,
1481}; 1313};
1482 1314
1483static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 1315static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1484 { .name = "dispc", .dma_req = 5 }, 1316 { .name = "dispc", .dma_req = 5 },
1485 { .name = "dsi1", .dma_req = 74 }, 1317 { .name = "dsi1", .dma_req = 74 },
1318 { .dma_req = -1 }
1486}; 1319};
1487 1320
1488/* dss */ 1321/* dss */
@@ -1491,21 +1324,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1491 &omap3xxx_dss__l3, 1324 &omap3xxx_dss__l3,
1492}; 1325};
1493 1326
1494static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1495 {
1496 .pa_start = 0x48050000,
1497 .pa_end = 0x480503FF,
1498 .flags = ADDR_TYPE_RT
1499 },
1500};
1501
1502/* l4_core -> dss */ 1327/* l4_core -> dss */
1503static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 1328static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1504 .master = &omap3xxx_l4_core_hwmod, 1329 .master = &omap3xxx_l4_core_hwmod,
1505 .slave = &omap3430es1_dss_core_hwmod, 1330 .slave = &omap3430es1_dss_core_hwmod,
1506 .clk = "dss_ick", 1331 .clk = "dss_ick",
1507 .addr = omap3xxx_dss_addrs, 1332 .addr = omap2_dss_addrs,
1508 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1509 .fw = { 1333 .fw = {
1510 .omap2 = { 1334 .omap2 = {
1511 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 1335 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
@@ -1520,8 +1344,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1520 .master = &omap3xxx_l4_core_hwmod, 1344 .master = &omap3xxx_l4_core_hwmod,
1521 .slave = &omap3xxx_dss_core_hwmod, 1345 .slave = &omap3xxx_dss_core_hwmod,
1522 .clk = "dss_ick", 1346 .clk = "dss_ick",
1523 .addr = omap3xxx_dss_addrs, 1347 .addr = omap2_dss_addrs,
1524 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1525 .fw = { 1348 .fw = {
1526 .omap2 = { 1349 .omap2 = {
1527 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 1350 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
@@ -1549,11 +1372,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1549 1372
1550static struct omap_hwmod omap3430es1_dss_core_hwmod = { 1373static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1551 .name = "dss_core", 1374 .name = "dss_core",
1552 .class = &omap3xxx_dss_hwmod_class, 1375 .class = &omap2_dss_hwmod_class,
1553 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1376 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1554 .sdma_reqs = omap3xxx_dss_sdma_chs, 1377 .sdma_reqs = omap3xxx_dss_sdma_chs,
1555 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1556
1557 .prcm = { 1378 .prcm = {
1558 .omap2 = { 1379 .omap2 = {
1559 .prcm_reg_id = 1, 1380 .prcm_reg_id = 1,
@@ -1575,11 +1396,9 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1575 1396
1576static struct omap_hwmod omap3xxx_dss_core_hwmod = { 1397static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1577 .name = "dss_core", 1398 .name = "dss_core",
1578 .class = &omap3xxx_dss_hwmod_class, 1399 .class = &omap2_dss_hwmod_class,
1579 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1400 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1580 .sdma_reqs = omap3xxx_dss_sdma_chs, 1401 .sdma_reqs = omap3xxx_dss_sdma_chs,
1581 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1582
1583 .prcm = { 1402 .prcm = {
1584 .omap2 = { 1403 .omap2 = {
1585 .prcm_reg_id = 1, 1404 .prcm_reg_id = 1,
@@ -1600,47 +1419,12 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1600 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), 1419 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1601}; 1420};
1602 1421
1603/*
1604 * 'dispc' class
1605 * display controller
1606 */
1607
1608static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1609 .rev_offs = 0x0000,
1610 .sysc_offs = 0x0010,
1611 .syss_offs = 0x0014,
1612 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1613 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1614 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1615 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1616 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1617 .sysc_fields = &omap_hwmod_sysc_type1,
1618};
1619
1620static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1621 .name = "dispc",
1622 .sysc = &omap3xxx_dispc_sysc,
1623};
1624
1625static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1626 { .irq = 25 },
1627};
1628
1629static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1630 {
1631 .pa_start = 0x48050400,
1632 .pa_end = 0x480507FF,
1633 .flags = ADDR_TYPE_RT
1634 },
1635};
1636
1637/* l4_core -> dss_dispc */ 1422/* l4_core -> dss_dispc */
1638static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 1423static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1639 .master = &omap3xxx_l4_core_hwmod, 1424 .master = &omap3xxx_l4_core_hwmod,
1640 .slave = &omap3xxx_dss_dispc_hwmod, 1425 .slave = &omap3xxx_dss_dispc_hwmod,
1641 .clk = "dss_ick", 1426 .clk = "dss_ick",
1642 .addr = omap3xxx_dss_dispc_addrs, 1427 .addr = omap2_dss_dispc_addrs,
1643 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1644 .fw = { 1428 .fw = {
1645 .omap2 = { 1429 .omap2 = {
1646 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 1430 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1658,9 +1442,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1658 1442
1659static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 1443static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1660 .name = "dss_dispc", 1444 .name = "dss_dispc",
1661 .class = &omap3xxx_dispc_hwmod_class, 1445 .class = &omap2_dispc_hwmod_class,
1662 .mpu_irqs = omap3xxx_dispc_irqs, 1446 .mpu_irqs = omap2_dispc_irqs,
1663 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
1664 .main_clk = "dss1_alwon_fck", 1447 .main_clk = "dss1_alwon_fck",
1665 .prcm = { 1448 .prcm = {
1666 .omap2 = { 1449 .omap2 = {
@@ -1688,6 +1471,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1688 1471
1689static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { 1472static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1690 { .irq = 25 }, 1473 { .irq = 25 },
1474 { .irq = -1 }
1691}; 1475};
1692 1476
1693/* dss_dsi1 */ 1477/* dss_dsi1 */
@@ -1697,6 +1481,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1697 .pa_end = 0x4804FFFF, 1481 .pa_end = 0x4804FFFF,
1698 .flags = ADDR_TYPE_RT 1482 .flags = ADDR_TYPE_RT
1699 }, 1483 },
1484 { }
1700}; 1485};
1701 1486
1702/* l4_core -> dss_dsi1 */ 1487/* l4_core -> dss_dsi1 */
@@ -1704,7 +1489,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1704 .master = &omap3xxx_l4_core_hwmod, 1489 .master = &omap3xxx_l4_core_hwmod,
1705 .slave = &omap3xxx_dss_dsi1_hwmod, 1490 .slave = &omap3xxx_dss_dsi1_hwmod,
1706 .addr = omap3xxx_dss_dsi1_addrs, 1491 .addr = omap3xxx_dss_dsi1_addrs,
1707 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1708 .fw = { 1492 .fw = {
1709 .omap2 = { 1493 .omap2 = {
1710 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 1494 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
@@ -1724,7 +1508,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1724 .name = "dss_dsi1", 1508 .name = "dss_dsi1",
1725 .class = &omap3xxx_dsi_hwmod_class, 1509 .class = &omap3xxx_dsi_hwmod_class,
1726 .mpu_irqs = omap3xxx_dsi1_irqs, 1510 .mpu_irqs = omap3xxx_dsi1_irqs,
1727 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
1728 .main_clk = "dss1_alwon_fck", 1511 .main_clk = "dss1_alwon_fck",
1729 .prcm = { 1512 .prcm = {
1730 .omap2 = { 1513 .omap2 = {
@@ -1741,41 +1524,12 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1741 .flags = HWMOD_NO_IDLEST, 1524 .flags = HWMOD_NO_IDLEST,
1742}; 1525};
1743 1526
1744/*
1745 * 'rfbi' class
1746 * remote frame buffer interface
1747 */
1748
1749static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1750 .rev_offs = 0x0000,
1751 .sysc_offs = 0x0010,
1752 .syss_offs = 0x0014,
1753 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1754 SYSC_HAS_AUTOIDLE),
1755 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1756 .sysc_fields = &omap_hwmod_sysc_type1,
1757};
1758
1759static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1760 .name = "rfbi",
1761 .sysc = &omap3xxx_rfbi_sysc,
1762};
1763
1764static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1765 {
1766 .pa_start = 0x48050800,
1767 .pa_end = 0x48050BFF,
1768 .flags = ADDR_TYPE_RT
1769 },
1770};
1771
1772/* l4_core -> dss_rfbi */ 1527/* l4_core -> dss_rfbi */
1773static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 1528static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1774 .master = &omap3xxx_l4_core_hwmod, 1529 .master = &omap3xxx_l4_core_hwmod,
1775 .slave = &omap3xxx_dss_rfbi_hwmod, 1530 .slave = &omap3xxx_dss_rfbi_hwmod,
1776 .clk = "dss_ick", 1531 .clk = "dss_ick",
1777 .addr = omap3xxx_dss_rfbi_addrs, 1532 .addr = omap2_dss_rfbi_addrs,
1778 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1779 .fw = { 1533 .fw = {
1780 .omap2 = { 1534 .omap2 = {
1781 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 1535 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
@@ -1793,7 +1547,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1793 1547
1794static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 1548static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1795 .name = "dss_rfbi", 1549 .name = "dss_rfbi",
1796 .class = &omap3xxx_rfbi_hwmod_class, 1550 .class = &omap2_rfbi_hwmod_class,
1797 .main_clk = "dss1_alwon_fck", 1551 .main_clk = "dss1_alwon_fck",
1798 .prcm = { 1552 .prcm = {
1799 .omap2 = { 1553 .omap2 = {
@@ -1810,31 +1564,12 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1810 .flags = HWMOD_NO_IDLEST, 1564 .flags = HWMOD_NO_IDLEST,
1811}; 1565};
1812 1566
1813/*
1814 * 'venc' class
1815 * video encoder
1816 */
1817
1818static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1819 .name = "venc",
1820};
1821
1822/* dss_venc */
1823static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1824 {
1825 .pa_start = 0x48050C00,
1826 .pa_end = 0x48050FFF,
1827 .flags = ADDR_TYPE_RT
1828 },
1829};
1830
1831/* l4_core -> dss_venc */ 1567/* l4_core -> dss_venc */
1832static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1568static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1833 .master = &omap3xxx_l4_core_hwmod, 1569 .master = &omap3xxx_l4_core_hwmod,
1834 .slave = &omap3xxx_dss_venc_hwmod, 1570 .slave = &omap3xxx_dss_venc_hwmod,
1835 .clk = "dss_tv_fck", 1571 .clk = "dss_tv_fck",
1836 .addr = omap3xxx_dss_venc_addrs, 1572 .addr = omap2_dss_venc_addrs,
1837 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1838 .fw = { 1573 .fw = {
1839 .omap2 = { 1574 .omap2 = {
1840 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 1575 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
@@ -1853,7 +1588,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1853 1588
1854static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 1589static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1855 .name = "dss_venc", 1590 .name = "dss_venc",
1856 .class = &omap3xxx_venc_hwmod_class, 1591 .class = &omap2_venc_hwmod_class,
1857 .main_clk = "dss1_alwon_fck", 1592 .main_clk = "dss1_alwon_fck",
1858 .prcm = { 1593 .prcm = {
1859 .omap2 = { 1594 .omap2 = {
@@ -1874,15 +1609,9 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1874 1609
1875static struct omap_i2c_dev_attr i2c1_dev_attr = { 1610static struct omap_i2c_dev_attr i2c1_dev_attr = {
1876 .fifo_depth = 8, /* bytes */ 1611 .fifo_depth = 8, /* bytes */
1877}; 1612 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1878 1613 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1879static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { 1614 OMAP_I2C_FLAG_BUS_SHIFT_2,
1880 { .irq = INT_24XX_I2C1_IRQ, },
1881};
1882
1883static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1884 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1885 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1886}; 1615};
1887 1616
1888static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { 1617static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
@@ -1891,10 +1620,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1891 1620
1892static struct omap_hwmod omap3xxx_i2c1_hwmod = { 1621static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1893 .name = "i2c1", 1622 .name = "i2c1",
1894 .mpu_irqs = i2c1_mpu_irqs, 1623 .flags = HWMOD_16BIT_REG,
1895 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1624 .mpu_irqs = omap2_i2c1_mpu_irqs,
1896 .sdma_reqs = i2c1_sdma_reqs, 1625 .sdma_reqs = omap2_i2c1_sdma_reqs,
1897 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1898 .main_clk = "i2c1_fck", 1626 .main_clk = "i2c1_fck",
1899 .prcm = { 1627 .prcm = {
1900 .omap2 = { 1628 .omap2 = {
@@ -1916,15 +1644,9 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1916 1644
1917static struct omap_i2c_dev_attr i2c2_dev_attr = { 1645static struct omap_i2c_dev_attr i2c2_dev_attr = {
1918 .fifo_depth = 8, /* bytes */ 1646 .fifo_depth = 8, /* bytes */
1919}; 1647 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1920 1648 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1921static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { 1649 OMAP_I2C_FLAG_BUS_SHIFT_2,
1922 { .irq = INT_24XX_I2C2_IRQ, },
1923};
1924
1925static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1926 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1927 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1928}; 1650};
1929 1651
1930static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { 1652static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
@@ -1933,10 +1655,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1933 1655
1934static struct omap_hwmod omap3xxx_i2c2_hwmod = { 1656static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1935 .name = "i2c2", 1657 .name = "i2c2",
1936 .mpu_irqs = i2c2_mpu_irqs, 1658 .flags = HWMOD_16BIT_REG,
1937 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1659 .mpu_irqs = omap2_i2c2_mpu_irqs,
1938 .sdma_reqs = i2c2_sdma_reqs, 1660 .sdma_reqs = omap2_i2c2_sdma_reqs,
1939 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1940 .main_clk = "i2c2_fck", 1661 .main_clk = "i2c2_fck",
1941 .prcm = { 1662 .prcm = {
1942 .omap2 = { 1663 .omap2 = {
@@ -1958,15 +1679,20 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1958 1679
1959static struct omap_i2c_dev_attr i2c3_dev_attr = { 1680static struct omap_i2c_dev_attr i2c3_dev_attr = {
1960 .fifo_depth = 64, /* bytes */ 1681 .fifo_depth = 64, /* bytes */
1682 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1683 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1684 OMAP_I2C_FLAG_BUS_SHIFT_2,
1961}; 1685};
1962 1686
1963static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 1687static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1964 { .irq = INT_34XX_I2C3_IRQ, }, 1688 { .irq = INT_34XX_I2C3_IRQ, },
1689 { .irq = -1 }
1965}; 1690};
1966 1691
1967static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 1692static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1968 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, 1693 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1969 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, 1694 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1695 { .dma_req = -1 }
1970}; 1696};
1971 1697
1972static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { 1698static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
@@ -1975,10 +1701,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1975 1701
1976static struct omap_hwmod omap3xxx_i2c3_hwmod = { 1702static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1977 .name = "i2c3", 1703 .name = "i2c3",
1704 .flags = HWMOD_16BIT_REG,
1978 .mpu_irqs = i2c3_mpu_irqs, 1705 .mpu_irqs = i2c3_mpu_irqs,
1979 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1980 .sdma_reqs = i2c3_sdma_reqs, 1706 .sdma_reqs = i2c3_sdma_reqs,
1981 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1982 .main_clk = "i2c3_fck", 1707 .main_clk = "i2c3_fck",
1983 .prcm = { 1708 .prcm = {
1984 .omap2 = { 1709 .omap2 = {
@@ -2003,13 +1728,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2003 .pa_end = 0x483101ff, 1728 .pa_end = 0x483101ff,
2004 .flags = ADDR_TYPE_RT 1729 .flags = ADDR_TYPE_RT
2005 }, 1730 },
1731 { }
2006}; 1732};
2007 1733
2008static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 1734static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2009 .master = &omap3xxx_l4_wkup_hwmod, 1735 .master = &omap3xxx_l4_wkup_hwmod,
2010 .slave = &omap3xxx_gpio1_hwmod, 1736 .slave = &omap3xxx_gpio1_hwmod,
2011 .addr = omap3xxx_gpio1_addrs, 1737 .addr = omap3xxx_gpio1_addrs,
2012 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2013 .user = OCP_USER_MPU | OCP_USER_SDMA, 1738 .user = OCP_USER_MPU | OCP_USER_SDMA,
2014}; 1739};
2015 1740
@@ -2020,13 +1745,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2020 .pa_end = 0x490501ff, 1745 .pa_end = 0x490501ff,
2021 .flags = ADDR_TYPE_RT 1746 .flags = ADDR_TYPE_RT
2022 }, 1747 },
1748 { }
2023}; 1749};
2024 1750
2025static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 1751static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2026 .master = &omap3xxx_l4_per_hwmod, 1752 .master = &omap3xxx_l4_per_hwmod,
2027 .slave = &omap3xxx_gpio2_hwmod, 1753 .slave = &omap3xxx_gpio2_hwmod,
2028 .addr = omap3xxx_gpio2_addrs, 1754 .addr = omap3xxx_gpio2_addrs,
2029 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2030 .user = OCP_USER_MPU | OCP_USER_SDMA, 1755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2031}; 1756};
2032 1757
@@ -2037,13 +1762,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2037 .pa_end = 0x490521ff, 1762 .pa_end = 0x490521ff,
2038 .flags = ADDR_TYPE_RT 1763 .flags = ADDR_TYPE_RT
2039 }, 1764 },
1765 { }
2040}; 1766};
2041 1767
2042static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 1768static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2043 .master = &omap3xxx_l4_per_hwmod, 1769 .master = &omap3xxx_l4_per_hwmod,
2044 .slave = &omap3xxx_gpio3_hwmod, 1770 .slave = &omap3xxx_gpio3_hwmod,
2045 .addr = omap3xxx_gpio3_addrs, 1771 .addr = omap3xxx_gpio3_addrs,
2046 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2047 .user = OCP_USER_MPU | OCP_USER_SDMA, 1772 .user = OCP_USER_MPU | OCP_USER_SDMA,
2048}; 1773};
2049 1774
@@ -2054,13 +1779,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2054 .pa_end = 0x490541ff, 1779 .pa_end = 0x490541ff,
2055 .flags = ADDR_TYPE_RT 1780 .flags = ADDR_TYPE_RT
2056 }, 1781 },
1782 { }
2057}; 1783};
2058 1784
2059static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 1785static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2060 .master = &omap3xxx_l4_per_hwmod, 1786 .master = &omap3xxx_l4_per_hwmod,
2061 .slave = &omap3xxx_gpio4_hwmod, 1787 .slave = &omap3xxx_gpio4_hwmod,
2062 .addr = omap3xxx_gpio4_addrs, 1788 .addr = omap3xxx_gpio4_addrs,
2063 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2064 .user = OCP_USER_MPU | OCP_USER_SDMA, 1789 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065}; 1790};
2066 1791
@@ -2071,13 +1796,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2071 .pa_end = 0x490561ff, 1796 .pa_end = 0x490561ff,
2072 .flags = ADDR_TYPE_RT 1797 .flags = ADDR_TYPE_RT
2073 }, 1798 },
1799 { }
2074}; 1800};
2075 1801
2076static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 1802static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2077 .master = &omap3xxx_l4_per_hwmod, 1803 .master = &omap3xxx_l4_per_hwmod,
2078 .slave = &omap3xxx_gpio5_hwmod, 1804 .slave = &omap3xxx_gpio5_hwmod,
2079 .addr = omap3xxx_gpio5_addrs, 1805 .addr = omap3xxx_gpio5_addrs,
2080 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2081 .user = OCP_USER_MPU | OCP_USER_SDMA, 1806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2082}; 1807};
2083 1808
@@ -2088,13 +1813,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2088 .pa_end = 0x490581ff, 1813 .pa_end = 0x490581ff,
2089 .flags = ADDR_TYPE_RT 1814 .flags = ADDR_TYPE_RT
2090 }, 1815 },
1816 { }
2091}; 1817};
2092 1818
2093static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 1819static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2094 .master = &omap3xxx_l4_per_hwmod, 1820 .master = &omap3xxx_l4_per_hwmod,
2095 .slave = &omap3xxx_gpio6_hwmod, 1821 .slave = &omap3xxx_gpio6_hwmod,
2096 .addr = omap3xxx_gpio6_addrs, 1822 .addr = omap3xxx_gpio6_addrs,
2097 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2098 .user = OCP_USER_MPU | OCP_USER_SDMA, 1823 .user = OCP_USER_MPU | OCP_USER_SDMA,
2099}; 1824};
2100 1825
@@ -2127,10 +1852,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
2127}; 1852};
2128 1853
2129/* gpio1 */ 1854/* gpio1 */
2130static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2131 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2132};
2133
2134static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1855static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2135 { .role = "dbclk", .clk = "gpio1_dbck", }, 1856 { .role = "dbclk", .clk = "gpio1_dbck", },
2136}; 1857};
@@ -2142,8 +1863,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2142static struct omap_hwmod omap3xxx_gpio1_hwmod = { 1863static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2143 .name = "gpio1", 1864 .name = "gpio1",
2144 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1865 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2145 .mpu_irqs = omap3xxx_gpio1_irqs, 1866 .mpu_irqs = omap2_gpio1_irqs,
2146 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2147 .main_clk = "gpio1_ick", 1867 .main_clk = "gpio1_ick",
2148 .opt_clks = gpio1_opt_clks, 1868 .opt_clks = gpio1_opt_clks,
2149 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 1869 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
@@ -2164,10 +1884,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2164}; 1884};
2165 1885
2166/* gpio2 */ 1886/* gpio2 */
2167static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2168 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2169};
2170
2171static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 1887static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2172 { .role = "dbclk", .clk = "gpio2_dbck", }, 1888 { .role = "dbclk", .clk = "gpio2_dbck", },
2173}; 1889};
@@ -2179,8 +1895,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2179static struct omap_hwmod omap3xxx_gpio2_hwmod = { 1895static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2180 .name = "gpio2", 1896 .name = "gpio2",
2181 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1897 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2182 .mpu_irqs = omap3xxx_gpio2_irqs, 1898 .mpu_irqs = omap2_gpio2_irqs,
2183 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2184 .main_clk = "gpio2_ick", 1899 .main_clk = "gpio2_ick",
2185 .opt_clks = gpio2_opt_clks, 1900 .opt_clks = gpio2_opt_clks,
2186 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 1901 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
@@ -2201,10 +1916,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2201}; 1916};
2202 1917
2203/* gpio3 */ 1918/* gpio3 */
2204static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2205 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2206};
2207
2208static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 1919static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2209 { .role = "dbclk", .clk = "gpio3_dbck", }, 1920 { .role = "dbclk", .clk = "gpio3_dbck", },
2210}; 1921};
@@ -2216,8 +1927,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2216static struct omap_hwmod omap3xxx_gpio3_hwmod = { 1927static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2217 .name = "gpio3", 1928 .name = "gpio3",
2218 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1929 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2219 .mpu_irqs = omap3xxx_gpio3_irqs, 1930 .mpu_irqs = omap2_gpio3_irqs,
2220 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2221 .main_clk = "gpio3_ick", 1931 .main_clk = "gpio3_ick",
2222 .opt_clks = gpio3_opt_clks, 1932 .opt_clks = gpio3_opt_clks,
2223 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 1933 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
@@ -2238,10 +1948,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2238}; 1948};
2239 1949
2240/* gpio4 */ 1950/* gpio4 */
2241static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2242 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2243};
2244
2245static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 1951static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2246 { .role = "dbclk", .clk = "gpio4_dbck", }, 1952 { .role = "dbclk", .clk = "gpio4_dbck", },
2247}; 1953};
@@ -2253,8 +1959,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2253static struct omap_hwmod omap3xxx_gpio4_hwmod = { 1959static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2254 .name = "gpio4", 1960 .name = "gpio4",
2255 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1961 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2256 .mpu_irqs = omap3xxx_gpio4_irqs, 1962 .mpu_irqs = omap2_gpio4_irqs,
2257 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2258 .main_clk = "gpio4_ick", 1963 .main_clk = "gpio4_ick",
2259 .opt_clks = gpio4_opt_clks, 1964 .opt_clks = gpio4_opt_clks,
2260 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 1965 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
@@ -2277,6 +1982,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2277/* gpio5 */ 1982/* gpio5 */
2278static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { 1983static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2279 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ 1984 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1985 { .irq = -1 }
2280}; 1986};
2281 1987
2282static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1988static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -2291,7 +1997,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2291 .name = "gpio5", 1997 .name = "gpio5",
2292 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1998 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2293 .mpu_irqs = omap3xxx_gpio5_irqs, 1999 .mpu_irqs = omap3xxx_gpio5_irqs,
2294 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2295 .main_clk = "gpio5_ick", 2000 .main_clk = "gpio5_ick",
2296 .opt_clks = gpio5_opt_clks, 2001 .opt_clks = gpio5_opt_clks,
2297 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 2002 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
@@ -2314,6 +2019,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2314/* gpio6 */ 2019/* gpio6 */
2315static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { 2020static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2316 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ 2021 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2022 { .irq = -1 }
2317}; 2023};
2318 2024
2319static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 2025static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -2328,7 +2034,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2328 .name = "gpio6", 2034 .name = "gpio6",
2329 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2035 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2330 .mpu_irqs = omap3xxx_gpio6_irqs, 2036 .mpu_irqs = omap3xxx_gpio6_irqs,
2331 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2332 .main_clk = "gpio6_ick", 2037 .main_clk = "gpio6_ick",
2333 .opt_clks = gpio6_opt_clks, 2038 .opt_clks = gpio6_opt_clks,
2334 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 2039 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
@@ -2382,19 +2087,13 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2382}; 2087};
2383 2088
2384/* dma_system */ 2089/* dma_system */
2385static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2386 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2387 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2388 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2389 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2390};
2391
2392static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 2090static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2393 { 2091 {
2394 .pa_start = 0x48056000, 2092 .pa_start = 0x48056000,
2395 .pa_end = 0x48056fff, 2093 .pa_end = 0x48056fff,
2396 .flags = ADDR_TYPE_RT 2094 .flags = ADDR_TYPE_RT
2397 }, 2095 },
2096 { }
2398}; 2097};
2399 2098
2400/* dma_system master ports */ 2099/* dma_system master ports */
@@ -2408,7 +2107,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2408 .slave = &omap3xxx_dma_system_hwmod, 2107 .slave = &omap3xxx_dma_system_hwmod,
2409 .clk = "core_l4_ick", 2108 .clk = "core_l4_ick",
2410 .addr = omap3xxx_dma_system_addrs, 2109 .addr = omap3xxx_dma_system_addrs,
2411 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2412 .user = OCP_USER_MPU | OCP_USER_SDMA, 2110 .user = OCP_USER_MPU | OCP_USER_SDMA,
2413}; 2111};
2414 2112
@@ -2420,8 +2118,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2420static struct omap_hwmod omap3xxx_dma_system_hwmod = { 2118static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2421 .name = "dma", 2119 .name = "dma",
2422 .class = &omap3xxx_dma_hwmod_class, 2120 .class = &omap3xxx_dma_hwmod_class,
2423 .mpu_irqs = omap3xxx_dma_system_irqs, 2121 .mpu_irqs = omap2_dma_system_irqs,
2424 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2425 .main_clk = "core_l3_ick", 2122 .main_clk = "core_l3_ick",
2426 .prcm = { 2123 .prcm = {
2427 .omap2 = { 2124 .omap2 = {
@@ -2466,11 +2163,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2466 { .name = "irq", .irq = 16 }, 2163 { .name = "irq", .irq = 16 },
2467 { .name = "tx", .irq = 59 }, 2164 { .name = "tx", .irq = 59 },
2468 { .name = "rx", .irq = 60 }, 2165 { .name = "rx", .irq = 60 },
2469}; 2166 { .irq = -1 }
2470
2471static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2472 { .name = "rx", .dma_req = 32 },
2473 { .name = "tx", .dma_req = 31 },
2474}; 2167};
2475 2168
2476static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { 2169static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
@@ -2480,6 +2173,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2480 .pa_end = 0x480740ff, 2173 .pa_end = 0x480740ff,
2481 .flags = ADDR_TYPE_RT 2174 .flags = ADDR_TYPE_RT
2482 }, 2175 },
2176 { }
2483}; 2177};
2484 2178
2485/* l4_core -> mcbsp1 */ 2179/* l4_core -> mcbsp1 */
@@ -2488,7 +2182,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2488 .slave = &omap3xxx_mcbsp1_hwmod, 2182 .slave = &omap3xxx_mcbsp1_hwmod,
2489 .clk = "mcbsp1_ick", 2183 .clk = "mcbsp1_ick",
2490 .addr = omap3xxx_mcbsp1_addrs, 2184 .addr = omap3xxx_mcbsp1_addrs,
2491 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2492 .user = OCP_USER_MPU | OCP_USER_SDMA, 2185 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493}; 2186};
2494 2187
@@ -2501,9 +2194,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2501 .name = "mcbsp1", 2194 .name = "mcbsp1",
2502 .class = &omap3xxx_mcbsp_hwmod_class, 2195 .class = &omap3xxx_mcbsp_hwmod_class,
2503 .mpu_irqs = omap3xxx_mcbsp1_irqs, 2196 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2504 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), 2197 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2505 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2506 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2507 .main_clk = "mcbsp1_fck", 2198 .main_clk = "mcbsp1_fck",
2508 .prcm = { 2199 .prcm = {
2509 .omap2 = { 2200 .omap2 = {
@@ -2524,11 +2215,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2524 { .name = "irq", .irq = 17 }, 2215 { .name = "irq", .irq = 17 },
2525 { .name = "tx", .irq = 62 }, 2216 { .name = "tx", .irq = 62 },
2526 { .name = "rx", .irq = 63 }, 2217 { .name = "rx", .irq = 63 },
2527}; 2218 { .irq = -1 }
2528
2529static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2530 { .name = "rx", .dma_req = 34 },
2531 { .name = "tx", .dma_req = 33 },
2532}; 2219};
2533 2220
2534static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { 2221static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
@@ -2538,6 +2225,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2538 .pa_end = 0x490220ff, 2225 .pa_end = 0x490220ff,
2539 .flags = ADDR_TYPE_RT 2226 .flags = ADDR_TYPE_RT
2540 }, 2227 },
2228 { }
2541}; 2229};
2542 2230
2543/* l4_per -> mcbsp2 */ 2231/* l4_per -> mcbsp2 */
@@ -2546,7 +2234,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2546 .slave = &omap3xxx_mcbsp2_hwmod, 2234 .slave = &omap3xxx_mcbsp2_hwmod,
2547 .clk = "mcbsp2_ick", 2235 .clk = "mcbsp2_ick",
2548 .addr = omap3xxx_mcbsp2_addrs, 2236 .addr = omap3xxx_mcbsp2_addrs,
2549 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2550 .user = OCP_USER_MPU | OCP_USER_SDMA, 2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2551}; 2238};
2552 2239
@@ -2563,9 +2250,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2563 .name = "mcbsp2", 2250 .name = "mcbsp2",
2564 .class = &omap3xxx_mcbsp_hwmod_class, 2251 .class = &omap3xxx_mcbsp_hwmod_class,
2565 .mpu_irqs = omap3xxx_mcbsp2_irqs, 2252 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2566 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), 2253 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2567 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2568 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2569 .main_clk = "mcbsp2_fck", 2254 .main_clk = "mcbsp2_fck",
2570 .prcm = { 2255 .prcm = {
2571 .omap2 = { 2256 .omap2 = {
@@ -2587,11 +2272,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2587 { .name = "irq", .irq = 22 }, 2272 { .name = "irq", .irq = 22 },
2588 { .name = "tx", .irq = 89 }, 2273 { .name = "tx", .irq = 89 },
2589 { .name = "rx", .irq = 90 }, 2274 { .name = "rx", .irq = 90 },
2590}; 2275 { .irq = -1 }
2591
2592static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2593 { .name = "rx", .dma_req = 18 },
2594 { .name = "tx", .dma_req = 17 },
2595}; 2276};
2596 2277
2597static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { 2278static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
@@ -2601,6 +2282,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2601 .pa_end = 0x490240ff, 2282 .pa_end = 0x490240ff,
2602 .flags = ADDR_TYPE_RT 2283 .flags = ADDR_TYPE_RT
2603 }, 2284 },
2285 { }
2604}; 2286};
2605 2287
2606/* l4_per -> mcbsp3 */ 2288/* l4_per -> mcbsp3 */
@@ -2609,7 +2291,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2609 .slave = &omap3xxx_mcbsp3_hwmod, 2291 .slave = &omap3xxx_mcbsp3_hwmod,
2610 .clk = "mcbsp3_ick", 2292 .clk = "mcbsp3_ick",
2611 .addr = omap3xxx_mcbsp3_addrs, 2293 .addr = omap3xxx_mcbsp3_addrs,
2612 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2613 .user = OCP_USER_MPU | OCP_USER_SDMA, 2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2614}; 2295};
2615 2296
@@ -2626,9 +2307,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2626 .name = "mcbsp3", 2307 .name = "mcbsp3",
2627 .class = &omap3xxx_mcbsp_hwmod_class, 2308 .class = &omap3xxx_mcbsp_hwmod_class,
2628 .mpu_irqs = omap3xxx_mcbsp3_irqs, 2309 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2629 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), 2310 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2630 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2631 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2632 .main_clk = "mcbsp3_fck", 2311 .main_clk = "mcbsp3_fck",
2633 .prcm = { 2312 .prcm = {
2634 .omap2 = { 2313 .omap2 = {
@@ -2650,11 +2329,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2650 { .name = "irq", .irq = 23 }, 2329 { .name = "irq", .irq = 23 },
2651 { .name = "tx", .irq = 54 }, 2330 { .name = "tx", .irq = 54 },
2652 { .name = "rx", .irq = 55 }, 2331 { .name = "rx", .irq = 55 },
2332 { .irq = -1 }
2653}; 2333};
2654 2334
2655static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { 2335static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2656 { .name = "rx", .dma_req = 20 }, 2336 { .name = "rx", .dma_req = 20 },
2657 { .name = "tx", .dma_req = 19 }, 2337 { .name = "tx", .dma_req = 19 },
2338 { .dma_req = -1 }
2658}; 2339};
2659 2340
2660static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { 2341static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
@@ -2664,6 +2345,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2664 .pa_end = 0x490260ff, 2345 .pa_end = 0x490260ff,
2665 .flags = ADDR_TYPE_RT 2346 .flags = ADDR_TYPE_RT
2666 }, 2347 },
2348 { }
2667}; 2349};
2668 2350
2669/* l4_per -> mcbsp4 */ 2351/* l4_per -> mcbsp4 */
@@ -2672,7 +2354,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2672 .slave = &omap3xxx_mcbsp4_hwmod, 2354 .slave = &omap3xxx_mcbsp4_hwmod,
2673 .clk = "mcbsp4_ick", 2355 .clk = "mcbsp4_ick",
2674 .addr = omap3xxx_mcbsp4_addrs, 2356 .addr = omap3xxx_mcbsp4_addrs,
2675 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2676 .user = OCP_USER_MPU | OCP_USER_SDMA, 2357 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677}; 2358};
2678 2359
@@ -2685,9 +2366,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2685 .name = "mcbsp4", 2366 .name = "mcbsp4",
2686 .class = &omap3xxx_mcbsp_hwmod_class, 2367 .class = &omap3xxx_mcbsp_hwmod_class,
2687 .mpu_irqs = omap3xxx_mcbsp4_irqs, 2368 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2688 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2689 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, 2369 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2690 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2691 .main_clk = "mcbsp4_fck", 2370 .main_clk = "mcbsp4_fck",
2692 .prcm = { 2371 .prcm = {
2693 .omap2 = { 2372 .omap2 = {
@@ -2708,11 +2387,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2708 { .name = "irq", .irq = 27 }, 2387 { .name = "irq", .irq = 27 },
2709 { .name = "tx", .irq = 81 }, 2388 { .name = "tx", .irq = 81 },
2710 { .name = "rx", .irq = 82 }, 2389 { .name = "rx", .irq = 82 },
2390 { .irq = -1 }
2711}; 2391};
2712 2392
2713static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { 2393static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2714 { .name = "rx", .dma_req = 22 }, 2394 { .name = "rx", .dma_req = 22 },
2715 { .name = "tx", .dma_req = 21 }, 2395 { .name = "tx", .dma_req = 21 },
2396 { .dma_req = -1 }
2716}; 2397};
2717 2398
2718static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { 2399static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
@@ -2722,6 +2403,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2722 .pa_end = 0x480960ff, 2403 .pa_end = 0x480960ff,
2723 .flags = ADDR_TYPE_RT 2404 .flags = ADDR_TYPE_RT
2724 }, 2405 },
2406 { }
2725}; 2407};
2726 2408
2727/* l4_core -> mcbsp5 */ 2409/* l4_core -> mcbsp5 */
@@ -2730,7 +2412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2730 .slave = &omap3xxx_mcbsp5_hwmod, 2412 .slave = &omap3xxx_mcbsp5_hwmod,
2731 .clk = "mcbsp5_ick", 2413 .clk = "mcbsp5_ick",
2732 .addr = omap3xxx_mcbsp5_addrs, 2414 .addr = omap3xxx_mcbsp5_addrs,
2733 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2734 .user = OCP_USER_MPU | OCP_USER_SDMA, 2415 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735}; 2416};
2736 2417
@@ -2743,9 +2424,7 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2743 .name = "mcbsp5", 2424 .name = "mcbsp5",
2744 .class = &omap3xxx_mcbsp_hwmod_class, 2425 .class = &omap3xxx_mcbsp_hwmod_class,
2745 .mpu_irqs = omap3xxx_mcbsp5_irqs, 2426 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2746 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2747 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, 2427 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2748 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2749 .main_clk = "mcbsp5_fck", 2428 .main_clk = "mcbsp5_fck",
2750 .prcm = { 2429 .prcm = {
2751 .omap2 = { 2430 .omap2 = {
@@ -2776,6 +2455,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2776/* mcbsp2_sidetone */ 2455/* mcbsp2_sidetone */
2777static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { 2456static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2778 { .name = "irq", .irq = 4 }, 2457 { .name = "irq", .irq = 4 },
2458 { .irq = -1 }
2779}; 2459};
2780 2460
2781static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { 2461static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
@@ -2785,6 +2465,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2785 .pa_end = 0x490280ff, 2465 .pa_end = 0x490280ff,
2786 .flags = ADDR_TYPE_RT 2466 .flags = ADDR_TYPE_RT
2787 }, 2467 },
2468 { }
2788}; 2469};
2789 2470
2790/* l4_per -> mcbsp2_sidetone */ 2471/* l4_per -> mcbsp2_sidetone */
@@ -2793,7 +2474,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2793 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2474 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2794 .clk = "mcbsp2_ick", 2475 .clk = "mcbsp2_ick",
2795 .addr = omap3xxx_mcbsp2_sidetone_addrs, 2476 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2796 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2797 .user = OCP_USER_MPU, 2477 .user = OCP_USER_MPU,
2798}; 2478};
2799 2479
@@ -2806,7 +2486,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2806 .name = "mcbsp2_sidetone", 2486 .name = "mcbsp2_sidetone",
2807 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2487 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2808 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, 2488 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2809 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2810 .main_clk = "mcbsp2_fck", 2489 .main_clk = "mcbsp2_fck",
2811 .prcm = { 2490 .prcm = {
2812 .omap2 = { 2491 .omap2 = {
@@ -2825,6 +2504,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2825/* mcbsp3_sidetone */ 2504/* mcbsp3_sidetone */
2826static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { 2505static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2827 { .name = "irq", .irq = 5 }, 2506 { .name = "irq", .irq = 5 },
2507 { .irq = -1 }
2828}; 2508};
2829 2509
2830static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { 2510static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
@@ -2834,6 +2514,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2834 .pa_end = 0x4902A0ff, 2514 .pa_end = 0x4902A0ff,
2835 .flags = ADDR_TYPE_RT 2515 .flags = ADDR_TYPE_RT
2836 }, 2516 },
2517 { }
2837}; 2518};
2838 2519
2839/* l4_per -> mcbsp3_sidetone */ 2520/* l4_per -> mcbsp3_sidetone */
@@ -2842,7 +2523,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2842 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2523 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2843 .clk = "mcbsp3_ick", 2524 .clk = "mcbsp3_ick",
2844 .addr = omap3xxx_mcbsp3_sidetone_addrs, 2525 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2845 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2846 .user = OCP_USER_MPU, 2526 .user = OCP_USER_MPU,
2847}; 2527};
2848 2528
@@ -2855,7 +2535,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2855 .name = "mcbsp3_sidetone", 2535 .name = "mcbsp3_sidetone",
2856 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2536 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2857 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, 2537 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2858 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2859 .main_clk = "mcbsp3_fck", 2538 .main_clk = "mcbsp3_fck",
2860 .prcm = { 2539 .prcm = {
2861 .omap2 = { 2540 .omap2 = {
@@ -3025,6 +2704,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3025static struct omap_hwmod omap3xxx_mailbox_hwmod; 2704static struct omap_hwmod omap3xxx_mailbox_hwmod;
3026static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 2705static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3027 { .irq = 26 }, 2706 { .irq = 26 },
2707 { .irq = -1 }
3028}; 2708};
3029 2709
3030static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { 2710static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
@@ -3033,6 +2713,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3033 .pa_end = 0x480941ff, 2713 .pa_end = 0x480941ff,
3034 .flags = ADDR_TYPE_RT, 2714 .flags = ADDR_TYPE_RT,
3035 }, 2715 },
2716 { }
3036}; 2717};
3037 2718
3038/* l4_core -> mailbox */ 2719/* l4_core -> mailbox */
@@ -3040,7 +2721,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3040 .master = &omap3xxx_l4_core_hwmod, 2721 .master = &omap3xxx_l4_core_hwmod,
3041 .slave = &omap3xxx_mailbox_hwmod, 2722 .slave = &omap3xxx_mailbox_hwmod,
3042 .addr = omap3xxx_mailbox_addrs, 2723 .addr = omap3xxx_mailbox_addrs,
3043 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3044 .user = OCP_USER_MPU | OCP_USER_SDMA, 2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045}; 2725};
3046 2726
@@ -3053,7 +2733,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3053 .name = "mailbox", 2733 .name = "mailbox",
3054 .class = &omap3xxx_mailbox_hwmod_class, 2734 .class = &omap3xxx_mailbox_hwmod_class,
3055 .mpu_irqs = omap3xxx_mailbox_irqs, 2735 .mpu_irqs = omap3xxx_mailbox_irqs,
3056 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3057 .main_clk = "mailboxes_ick", 2736 .main_clk = "mailboxes_ick",
3058 .prcm = { 2737 .prcm = {
3059 .omap2 = { 2738 .omap2 = {
@@ -3070,56 +2749,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3070}; 2749};
3071 2750
3072/* l4 core -> mcspi1 interface */ 2751/* l4 core -> mcspi1 interface */
3073static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3074 {
3075 .pa_start = 0x48098000,
3076 .pa_end = 0x480980ff,
3077 .flags = ADDR_TYPE_RT,
3078 },
3079};
3080
3081static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 2752static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3082 .master = &omap3xxx_l4_core_hwmod, 2753 .master = &omap3xxx_l4_core_hwmod,
3083 .slave = &omap34xx_mcspi1, 2754 .slave = &omap34xx_mcspi1,
3084 .clk = "mcspi1_ick", 2755 .clk = "mcspi1_ick",
3085 .addr = omap34xx_mcspi1_addr_space, 2756 .addr = omap2_mcspi1_addr_space,
3086 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3087 .user = OCP_USER_MPU | OCP_USER_SDMA, 2757 .user = OCP_USER_MPU | OCP_USER_SDMA,
3088}; 2758};
3089 2759
3090/* l4 core -> mcspi2 interface */ 2760/* l4 core -> mcspi2 interface */
3091static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3092 {
3093 .pa_start = 0x4809a000,
3094 .pa_end = 0x4809a0ff,
3095 .flags = ADDR_TYPE_RT,
3096 },
3097};
3098
3099static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 2761static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3100 .master = &omap3xxx_l4_core_hwmod, 2762 .master = &omap3xxx_l4_core_hwmod,
3101 .slave = &omap34xx_mcspi2, 2763 .slave = &omap34xx_mcspi2,
3102 .clk = "mcspi2_ick", 2764 .clk = "mcspi2_ick",
3103 .addr = omap34xx_mcspi2_addr_space, 2765 .addr = omap2_mcspi2_addr_space,
3104 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3105 .user = OCP_USER_MPU | OCP_USER_SDMA, 2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106}; 2767};
3107 2768
3108/* l4 core -> mcspi3 interface */ 2769/* l4 core -> mcspi3 interface */
3109static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3110 {
3111 .pa_start = 0x480b8000,
3112 .pa_end = 0x480b80ff,
3113 .flags = ADDR_TYPE_RT,
3114 },
3115};
3116
3117static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 2770static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3118 .master = &omap3xxx_l4_core_hwmod, 2771 .master = &omap3xxx_l4_core_hwmod,
3119 .slave = &omap34xx_mcspi3, 2772 .slave = &omap34xx_mcspi3,
3120 .clk = "mcspi3_ick", 2773 .clk = "mcspi3_ick",
3121 .addr = omap34xx_mcspi3_addr_space, 2774 .addr = omap2430_mcspi3_addr_space,
3122 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3123 .user = OCP_USER_MPU | OCP_USER_SDMA, 2775 .user = OCP_USER_MPU | OCP_USER_SDMA,
3124}; 2776};
3125 2777
@@ -3130,6 +2782,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3130 .pa_end = 0x480ba0ff, 2782 .pa_end = 0x480ba0ff,
3131 .flags = ADDR_TYPE_RT, 2783 .flags = ADDR_TYPE_RT,
3132 }, 2784 },
2785 { }
3133}; 2786};
3134 2787
3135static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2788static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
@@ -3137,7 +2790,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3137 .slave = &omap34xx_mcspi4, 2790 .slave = &omap34xx_mcspi4,
3138 .clk = "mcspi4_ick", 2791 .clk = "mcspi4_ick",
3139 .addr = omap34xx_mcspi4_addr_space, 2792 .addr = omap34xx_mcspi4_addr_space,
3140 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3141 .user = OCP_USER_MPU | OCP_USER_SDMA, 2793 .user = OCP_USER_MPU | OCP_USER_SDMA,
3142}; 2794};
3143 2795
@@ -3165,21 +2817,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
3165}; 2817};
3166 2818
3167/* mcspi1 */ 2819/* mcspi1 */
3168static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3169 { .name = "irq", .irq = 65 },
3170};
3171
3172static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3173 { .name = "tx0", .dma_req = 35 },
3174 { .name = "rx0", .dma_req = 36 },
3175 { .name = "tx1", .dma_req = 37 },
3176 { .name = "rx1", .dma_req = 38 },
3177 { .name = "tx2", .dma_req = 39 },
3178 { .name = "rx2", .dma_req = 40 },
3179 { .name = "tx3", .dma_req = 41 },
3180 { .name = "rx3", .dma_req = 42 },
3181};
3182
3183static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { 2820static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3184 &omap34xx_l4_core__mcspi1, 2821 &omap34xx_l4_core__mcspi1,
3185}; 2822};
@@ -3190,10 +2827,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3190 2827
3191static struct omap_hwmod omap34xx_mcspi1 = { 2828static struct omap_hwmod omap34xx_mcspi1 = {
3192 .name = "mcspi1", 2829 .name = "mcspi1",
3193 .mpu_irqs = omap34xx_mcspi1_mpu_irqs, 2830 .mpu_irqs = omap2_mcspi1_mpu_irqs,
3194 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), 2831 .sdma_reqs = omap2_mcspi1_sdma_reqs,
3195 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3196 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3197 .main_clk = "mcspi1_fck", 2832 .main_clk = "mcspi1_fck",
3198 .prcm = { 2833 .prcm = {
3199 .omap2 = { 2834 .omap2 = {
@@ -3212,17 +2847,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
3212}; 2847};
3213 2848
3214/* mcspi2 */ 2849/* mcspi2 */
3215static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3216 { .name = "irq", .irq = 66 },
3217};
3218
3219static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3220 { .name = "tx0", .dma_req = 43 },
3221 { .name = "rx0", .dma_req = 44 },
3222 { .name = "tx1", .dma_req = 45 },
3223 { .name = "rx1", .dma_req = 46 },
3224};
3225
3226static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { 2850static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3227 &omap34xx_l4_core__mcspi2, 2851 &omap34xx_l4_core__mcspi2,
3228}; 2852};
@@ -3233,10 +2857,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3233 2857
3234static struct omap_hwmod omap34xx_mcspi2 = { 2858static struct omap_hwmod omap34xx_mcspi2 = {
3235 .name = "mcspi2", 2859 .name = "mcspi2",
3236 .mpu_irqs = omap34xx_mcspi2_mpu_irqs, 2860 .mpu_irqs = omap2_mcspi2_mpu_irqs,
3237 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), 2861 .sdma_reqs = omap2_mcspi2_sdma_reqs,
3238 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3239 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3240 .main_clk = "mcspi2_fck", 2862 .main_clk = "mcspi2_fck",
3241 .prcm = { 2863 .prcm = {
3242 .omap2 = { 2864 .omap2 = {
@@ -3257,6 +2879,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
3257/* mcspi3 */ 2879/* mcspi3 */
3258static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { 2880static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3259 { .name = "irq", .irq = 91 }, /* 91 */ 2881 { .name = "irq", .irq = 91 }, /* 91 */
2882 { .irq = -1 }
3260}; 2883};
3261 2884
3262static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { 2885static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -3264,6 +2887,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3264 { .name = "rx0", .dma_req = 16 }, 2887 { .name = "rx0", .dma_req = 16 },
3265 { .name = "tx1", .dma_req = 23 }, 2888 { .name = "tx1", .dma_req = 23 },
3266 { .name = "rx1", .dma_req = 24 }, 2889 { .name = "rx1", .dma_req = 24 },
2890 { .dma_req = -1 }
3267}; 2891};
3268 2892
3269static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { 2893static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
@@ -3277,9 +2901,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3277static struct omap_hwmod omap34xx_mcspi3 = { 2901static struct omap_hwmod omap34xx_mcspi3 = {
3278 .name = "mcspi3", 2902 .name = "mcspi3",
3279 .mpu_irqs = omap34xx_mcspi3_mpu_irqs, 2903 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3280 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3281 .sdma_reqs = omap34xx_mcspi3_sdma_reqs, 2904 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3282 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3283 .main_clk = "mcspi3_fck", 2905 .main_clk = "mcspi3_fck",
3284 .prcm = { 2906 .prcm = {
3285 .omap2 = { 2907 .omap2 = {
@@ -3300,11 +2922,13 @@ static struct omap_hwmod omap34xx_mcspi3 = {
3300/* SPI4 */ 2922/* SPI4 */
3301static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 2923static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3302 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 2924 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2925 { .irq = -1 }
3303}; 2926};
3304 2927
3305static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { 2928static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3306 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ 2929 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3307 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ 2930 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2931 { .dma_req = -1 }
3308}; 2932};
3309 2933
3310static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { 2934static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
@@ -3318,9 +2942,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3318static struct omap_hwmod omap34xx_mcspi4 = { 2942static struct omap_hwmod omap34xx_mcspi4 = {
3319 .name = "mcspi4", 2943 .name = "mcspi4",
3320 .mpu_irqs = omap34xx_mcspi4_mpu_irqs, 2944 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3321 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3322 .sdma_reqs = omap34xx_mcspi4_sdma_reqs, 2945 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3323 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3324 .main_clk = "mcspi4_fck", 2946 .main_clk = "mcspi4_fck",
3325 .prcm = { 2947 .prcm = {
3326 .omap2 = { 2948 .omap2 = {
@@ -3362,12 +2984,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3362 2984
3363 { .name = "mc", .irq = 92 }, 2985 { .name = "mc", .irq = 92 },
3364 { .name = "dma", .irq = 93 }, 2986 { .name = "dma", .irq = 93 },
2987 { .irq = -1 }
3365}; 2988};
3366 2989
3367static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 2990static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3368 .name = "usb_otg_hs", 2991 .name = "usb_otg_hs",
3369 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, 2992 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3370 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3371 .main_clk = "hsotgusb_ick", 2993 .main_clk = "hsotgusb_ick",
3372 .prcm = { 2994 .prcm = {
3373 .omap2 = { 2995 .omap2 = {
@@ -3399,6 +3021,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3399static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 3021static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3400 3022
3401 { .name = "mc", .irq = 71 }, 3023 { .name = "mc", .irq = 71 },
3024 { .irq = -1 }
3402}; 3025};
3403 3026
3404static struct omap_hwmod_class am35xx_usbotg_class = { 3027static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -3409,7 +3032,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
3409static struct omap_hwmod am35xx_usbhsotg_hwmod = { 3032static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3410 .name = "am35x_otg_hs", 3033 .name = "am35x_otg_hs",
3411 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 3034 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3412 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3413 .main_clk = NULL, 3035 .main_clk = NULL,
3414 .prcm = { 3036 .prcm = {
3415 .omap2 = { 3037 .omap2 = {
@@ -3445,11 +3067,13 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
3445 3067
3446static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { 3068static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3447 { .irq = 83, }, 3069 { .irq = 83, },
3070 { .irq = -1 }
3448}; 3071};
3449 3072
3450static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { 3073static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3451 { .name = "tx", .dma_req = 61, }, 3074 { .name = "tx", .dma_req = 61, },
3452 { .name = "rx", .dma_req = 62, }, 3075 { .name = "rx", .dma_req = 62, },
3076 { .dma_req = -1 }
3453}; 3077};
3454 3078
3455static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 3079static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
@@ -3467,9 +3091,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
3467static struct omap_hwmod omap3xxx_mmc1_hwmod = { 3091static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3468 .name = "mmc1", 3092 .name = "mmc1",
3469 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 3093 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3470 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3471 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 3094 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3472 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3473 .opt_clks = omap34xx_mmc1_opt_clks, 3095 .opt_clks = omap34xx_mmc1_opt_clks,
3474 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 3096 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3475 .main_clk = "mmchs1_fck", 3097 .main_clk = "mmchs1_fck",
@@ -3493,11 +3115,13 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3493 3115
3494static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { 3116static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3495 { .irq = INT_24XX_MMC2_IRQ, }, 3117 { .irq = INT_24XX_MMC2_IRQ, },
3118 { .irq = -1 }
3496}; 3119};
3497 3120
3498static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { 3121static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3499 { .name = "tx", .dma_req = 47, }, 3122 { .name = "tx", .dma_req = 47, },
3500 { .name = "rx", .dma_req = 48, }, 3123 { .name = "rx", .dma_req = 48, },
3124 { .dma_req = -1 }
3501}; 3125};
3502 3126
3503static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 3127static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
@@ -3511,9 +3135,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3511static struct omap_hwmod omap3xxx_mmc2_hwmod = { 3135static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3512 .name = "mmc2", 3136 .name = "mmc2",
3513 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 3137 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3514 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3515 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 3138 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3516 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3517 .opt_clks = omap34xx_mmc2_opt_clks, 3139 .opt_clks = omap34xx_mmc2_opt_clks,
3518 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 3140 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3519 .main_clk = "mmchs2_fck", 3141 .main_clk = "mmchs2_fck",
@@ -3536,11 +3158,13 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3536 3158
3537static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { 3159static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3538 { .irq = 94, }, 3160 { .irq = 94, },
3161 { .irq = -1 }
3539}; 3162};
3540 3163
3541static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { 3164static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3542 { .name = "tx", .dma_req = 77, }, 3165 { .name = "tx", .dma_req = 77, },
3543 { .name = "rx", .dma_req = 78, }, 3166 { .name = "rx", .dma_req = 78, },
3167 { .dma_req = -1 }
3544}; 3168};
3545 3169
3546static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 3170static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
@@ -3554,9 +3178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3554static struct omap_hwmod omap3xxx_mmc3_hwmod = { 3178static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3555 .name = "mmc3", 3179 .name = "mmc3",
3556 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 3180 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3557 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3558 .sdma_reqs = omap34xx_mmc3_sdma_reqs, 3181 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3559 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3560 .opt_clks = omap34xx_mmc3_opt_clks, 3182 .opt_clks = omap34xx_mmc3_opt_clks,
3561 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 3183 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3562 .main_clk = "mmchs3_fck", 3184 .main_clk = "mmchs3_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e1c69ffe0f69..5d5df49749df 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,11 +22,13 @@
22 22
23#include <plat/omap_hwmod.h> 23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h> 24#include <plat/cpu.h>
25#include <plat/i2c.h>
25#include <plat/gpio.h> 26#include <plat/gpio.h>
26#include <plat/dma.h> 27#include <plat/dma.h>
27#include <plat/mcspi.h> 28#include <plat/mcspi.h>
28#include <plat/mcbsp.h> 29#include <plat/mcbsp.h>
29#include <plat/mmc.h> 30#include <plat/mmc.h>
31#include <plat/i2c.h>
30 32
31#include "omap_hwmod_common_data.h" 33#include "omap_hwmod_common_data.h"
32 34
@@ -80,7 +82,12 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
80 .name = "dmm", 82 .name = "dmm",
81}; 83};
82 84
83/* dmm interface data */ 85/* dmm */
86static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
87 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
88 { .irq = -1 }
89};
90
84/* l3_main_1 -> dmm */ 91/* l3_main_1 -> dmm */
85static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { 92static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
86 .master = &omap44xx_l3_main_1_hwmod, 93 .master = &omap44xx_l3_main_1_hwmod,
@@ -95,6 +102,7 @@ static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
95 .pa_end = 0x4e0007ff, 102 .pa_end = 0x4e0007ff,
96 .flags = ADDR_TYPE_RT 103 .flags = ADDR_TYPE_RT
97 }, 104 },
105 { }
98}; 106};
99 107
100/* mpu -> dmm */ 108/* mpu -> dmm */
@@ -103,7 +111,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
103 .slave = &omap44xx_dmm_hwmod, 111 .slave = &omap44xx_dmm_hwmod,
104 .clk = "l3_div_ck", 112 .clk = "l3_div_ck",
105 .addr = omap44xx_dmm_addrs, 113 .addr = omap44xx_dmm_addrs,
106 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
107 .user = OCP_USER_MPU, 114 .user = OCP_USER_MPU,
108}; 115};
109 116
@@ -113,17 +120,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
113 &omap44xx_mpu__dmm, 120 &omap44xx_mpu__dmm,
114}; 121};
115 122
116static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
117 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
118};
119
120static struct omap_hwmod omap44xx_dmm_hwmod = { 123static struct omap_hwmod omap44xx_dmm_hwmod = {
121 .name = "dmm", 124 .name = "dmm",
122 .class = &omap44xx_dmm_hwmod_class, 125 .class = &omap44xx_dmm_hwmod_class,
126 .mpu_irqs = omap44xx_dmm_irqs,
123 .slaves = omap44xx_dmm_slaves, 127 .slaves = omap44xx_dmm_slaves,
124 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), 128 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
125 .mpu_irqs = omap44xx_dmm_irqs,
126 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 129 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
128}; 130};
129 131
@@ -135,7 +137,7 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
135 .name = "emif_fw", 137 .name = "emif_fw",
136}; 138};
137 139
138/* emif_fw interface data */ 140/* emif_fw */
139/* dmm -> emif_fw */ 141/* dmm -> emif_fw */
140static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { 142static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
141 .master = &omap44xx_dmm_hwmod, 143 .master = &omap44xx_dmm_hwmod,
@@ -150,6 +152,7 @@ static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
150 .pa_end = 0x4a20c0ff, 152 .pa_end = 0x4a20c0ff,
151 .flags = ADDR_TYPE_RT 153 .flags = ADDR_TYPE_RT
152 }, 154 },
155 { }
153}; 156};
154 157
155/* l4_cfg -> emif_fw */ 158/* l4_cfg -> emif_fw */
@@ -158,7 +161,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
158 .slave = &omap44xx_emif_fw_hwmod, 161 .slave = &omap44xx_emif_fw_hwmod,
159 .clk = "l4_div_ck", 162 .clk = "l4_div_ck",
160 .addr = omap44xx_emif_fw_addrs, 163 .addr = omap44xx_emif_fw_addrs,
161 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
162 .user = OCP_USER_MPU, 164 .user = OCP_USER_MPU,
163}; 165};
164 166
@@ -184,7 +186,7 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
184 .name = "l3", 186 .name = "l3",
185}; 187};
186 188
187/* l3_instr interface data */ 189/* l3_instr */
188/* iva -> l3_instr */ 190/* iva -> l3_instr */
189static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { 191static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
190 .master = &omap44xx_iva_hwmod, 192 .master = &omap44xx_iva_hwmod,
@@ -215,7 +217,13 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 217 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216}; 218};
217 219
218/* l3_main_1 interface data */ 220/* l3_main_1 */
221static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
222 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
223 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
224 { .irq = -1 }
225};
226
219/* dsp -> l3_main_1 */ 227/* dsp -> l3_main_1 */
220static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { 228static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
221 .master = &omap44xx_dsp_hwmod, 229 .master = &omap44xx_dsp_hwmod,
@@ -264,18 +272,13 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
264 .user = OCP_USER_MPU | OCP_USER_SDMA, 272 .user = OCP_USER_MPU | OCP_USER_SDMA,
265}; 273};
266 274
267/* L3 target configuration and error log registers */
268static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
269 { .irq = 9 + OMAP44XX_IRQ_GIC_START },
270 { .irq = 10 + OMAP44XX_IRQ_GIC_START },
271};
272
273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { 275static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 { 276 {
275 .pa_start = 0x44000000, 277 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff, 278 .pa_end = 0x44000fff,
277 .flags = ADDR_TYPE_RT, 279 .flags = ADDR_TYPE_RT
278 }, 280 },
281 { }
279}; 282};
280 283
281/* mpu -> l3_main_1 */ 284/* mpu -> l3_main_1 */
@@ -284,8 +287,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
284 .slave = &omap44xx_l3_main_1_hwmod, 287 .slave = &omap44xx_l3_main_1_hwmod,
285 .clk = "l3_div_ck", 288 .clk = "l3_div_ck",
286 .addr = omap44xx_l3_main_1_addrs, 289 .addr = omap44xx_l3_main_1_addrs,
287 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs), 290 .user = OCP_USER_MPU,
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
289}; 291};
290 292
291/* l3_main_1 slave ports */ 293/* l3_main_1 slave ports */
@@ -302,14 +304,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
302static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 304static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
303 .name = "l3_main_1", 305 .name = "l3_main_1",
304 .class = &omap44xx_l3_hwmod_class, 306 .class = &omap44xx_l3_hwmod_class,
305 .mpu_irqs = omap44xx_l3_targ_irqs, 307 .mpu_irqs = omap44xx_l3_main_1_irqs,
306 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
307 .slaves = omap44xx_l3_main_1_slaves, 308 .slaves = omap44xx_l3_main_1_slaves,
308 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 309 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
309 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
310}; 311};
311 312
312/* l3_main_2 interface data */ 313/* l3_main_2 */
313/* dma_system -> l3_main_2 */ 314/* dma_system -> l3_main_2 */
314static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { 315static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
315 .master = &omap44xx_dma_system_hwmod, 316 .master = &omap44xx_dma_system_hwmod,
@@ -354,8 +355,9 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
354 { 355 {
355 .pa_start = 0x44800000, 356 .pa_start = 0x44800000,
356 .pa_end = 0x44801fff, 357 .pa_end = 0x44801fff,
357 .flags = ADDR_TYPE_RT, 358 .flags = ADDR_TYPE_RT
358 }, 359 },
360 { }
359}; 361};
360 362
361/* l3_main_1 -> l3_main_2 */ 363/* l3_main_1 -> l3_main_2 */
@@ -364,8 +366,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
364 .slave = &omap44xx_l3_main_2_hwmod, 366 .slave = &omap44xx_l3_main_2_hwmod,
365 .clk = "l3_div_ck", 367 .clk = "l3_div_ck",
366 .addr = omap44xx_l3_main_2_addrs, 368 .addr = omap44xx_l3_main_2_addrs,
367 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs), 369 .user = OCP_USER_MPU,
368 .user = OCP_USER_MPU | OCP_USER_SDMA,
369}; 370};
370 371
371/* l4_cfg -> l3_main_2 */ 372/* l4_cfg -> l3_main_2 */
@@ -404,13 +405,14 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
404 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 405 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
405}; 406};
406 407
407/* l3_main_3 interface data */ 408/* l3_main_3 */
408static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { 409static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
409 { 410 {
410 .pa_start = 0x45000000, 411 .pa_start = 0x45000000,
411 .pa_end = 0x45000fff, 412 .pa_end = 0x45000fff,
412 .flags = ADDR_TYPE_RT, 413 .flags = ADDR_TYPE_RT
413 }, 414 },
415 { }
414}; 416};
415 417
416/* l3_main_1 -> l3_main_3 */ 418/* l3_main_1 -> l3_main_3 */
@@ -419,8 +421,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
419 .slave = &omap44xx_l3_main_3_hwmod, 421 .slave = &omap44xx_l3_main_3_hwmod,
420 .clk = "l3_div_ck", 422 .clk = "l3_div_ck",
421 .addr = omap44xx_l3_main_3_addrs, 423 .addr = omap44xx_l3_main_3_addrs,
422 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs), 424 .user = OCP_USER_MPU,
423 .user = OCP_USER_MPU | OCP_USER_SDMA,
424}; 425};
425 426
426/* l3_main_2 -> l3_main_3 */ 427/* l3_main_2 -> l3_main_3 */
@@ -462,7 +463,7 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
462 .name = "l4", 463 .name = "l4",
463}; 464};
464 465
465/* l4_abe interface data */ 466/* l4_abe */
466/* aess -> l4_abe */ 467/* aess -> l4_abe */
467static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { 468static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
468 .master = &omap44xx_aess_hwmod, 469 .master = &omap44xx_aess_hwmod,
@@ -511,7 +512,7 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
511 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 512 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
512}; 513};
513 514
514/* l4_cfg interface data */ 515/* l4_cfg */
515/* l3_main_1 -> l4_cfg */ 516/* l3_main_1 -> l4_cfg */
516static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { 517static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
517 .master = &omap44xx_l3_main_1_hwmod, 518 .master = &omap44xx_l3_main_1_hwmod,
@@ -533,7 +534,7 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
533 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 534 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
534}; 535};
535 536
536/* l4_per interface data */ 537/* l4_per */
537/* l3_main_2 -> l4_per */ 538/* l3_main_2 -> l4_per */
538static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { 539static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
539 .master = &omap44xx_l3_main_2_hwmod, 540 .master = &omap44xx_l3_main_2_hwmod,
@@ -555,7 +556,7 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
555 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
556}; 557};
557 558
558/* l4_wkup interface data */ 559/* l4_wkup */
559/* l4_cfg -> l4_wkup */ 560/* l4_cfg -> l4_wkup */
560static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { 561static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
561 .master = &omap44xx_l4_cfg_hwmod, 562 .master = &omap44xx_l4_cfg_hwmod,
@@ -585,7 +586,7 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
585 .name = "mpu_bus", 586 .name = "mpu_bus",
586}; 587};
587 588
588/* mpu_private interface data */ 589/* mpu_private */
589/* mpu -> mpu_private */ 590/* mpu -> mpu_private */
590static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { 591static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
591 .master = &omap44xx_mpu_hwmod, 592 .master = &omap44xx_mpu_hwmod,
@@ -633,7 +634,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
633 * gpmc 634 * gpmc
634 * gpu 635 * gpu
635 * hdq1w 636 * hdq1w
636 * hsi 637 * mcasp
638 * mpu_c0
639 * mpu_c1
637 * ocmc_ram 640 * ocmc_ram
638 * ocp2scp_usb_phy 641 * ocp2scp_usb_phy
639 * ocp_wp_noc 642 * ocp_wp_noc
@@ -660,7 +663,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
660 .sysc_offs = 0x0010, 663 .sysc_offs = 0x0010,
661 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), 664 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
662 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 665 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
663 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 666 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
667 MSTANDBY_SMART_WKUP),
664 .sysc_fields = &omap_hwmod_sysc_type2, 668 .sysc_fields = &omap_hwmod_sysc_type2,
665}; 669};
666 670
@@ -672,6 +676,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
672/* aess */ 676/* aess */
673static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { 677static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
674 { .irq = 99 + OMAP44XX_IRQ_GIC_START }, 678 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
679 { .irq = -1 }
675}; 680};
676 681
677static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { 682static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
@@ -683,6 +688,7 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
683 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, 688 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
684 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, 689 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
685 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, 690 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
691 { .dma_req = -1 }
686}; 692};
687 693
688/* aess master ports */ 694/* aess master ports */
@@ -696,6 +702,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
696 .pa_end = 0x401f13ff, 702 .pa_end = 0x401f13ff,
697 .flags = ADDR_TYPE_RT 703 .flags = ADDR_TYPE_RT
698 }, 704 },
705 { }
699}; 706};
700 707
701/* l4_abe -> aess */ 708/* l4_abe -> aess */
@@ -704,7 +711,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
704 .slave = &omap44xx_aess_hwmod, 711 .slave = &omap44xx_aess_hwmod,
705 .clk = "ocp_abe_iclk", 712 .clk = "ocp_abe_iclk",
706 .addr = omap44xx_aess_addrs, 713 .addr = omap44xx_aess_addrs,
707 .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
708 .user = OCP_USER_MPU, 714 .user = OCP_USER_MPU,
709}; 715};
710 716
@@ -714,6 +720,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
714 .pa_end = 0x490f13ff, 720 .pa_end = 0x490f13ff,
715 .flags = ADDR_TYPE_RT 721 .flags = ADDR_TYPE_RT
716 }, 722 },
723 { }
717}; 724};
718 725
719/* l4_abe -> aess (dma) */ 726/* l4_abe -> aess (dma) */
@@ -722,7 +729,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
722 .slave = &omap44xx_aess_hwmod, 729 .slave = &omap44xx_aess_hwmod,
723 .clk = "ocp_abe_iclk", 730 .clk = "ocp_abe_iclk",
724 .addr = omap44xx_aess_dma_addrs, 731 .addr = omap44xx_aess_dma_addrs,
725 .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
726 .user = OCP_USER_SDMA, 732 .user = OCP_USER_SDMA,
727}; 733};
728 734
@@ -736,11 +742,9 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
736 .name = "aess", 742 .name = "aess",
737 .class = &omap44xx_aess_hwmod_class, 743 .class = &omap44xx_aess_hwmod_class,
738 .mpu_irqs = omap44xx_aess_irqs, 744 .mpu_irqs = omap44xx_aess_irqs,
739 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
740 .sdma_reqs = omap44xx_aess_sdma_reqs, 745 .sdma_reqs = omap44xx_aess_sdma_reqs,
741 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
742 .main_clk = "aess_fck", 746 .main_clk = "aess_fck",
743 .prcm = { 747 .prcm = {
744 .omap4 = { 748 .omap4 = {
745 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, 749 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
746 }, 750 },
@@ -769,7 +773,7 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
769static struct omap_hwmod omap44xx_bandgap_hwmod = { 773static struct omap_hwmod omap44xx_bandgap_hwmod = {
770 .name = "bandgap", 774 .name = "bandgap",
771 .class = &omap44xx_bandgap_hwmod_class, 775 .class = &omap44xx_bandgap_hwmod_class,
772 .prcm = { 776 .prcm = {
773 .omap4 = { 777 .omap4 = {
774 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, 778 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
775 }, 779 },
@@ -806,6 +810,7 @@ static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
806 .pa_end = 0x4a30401f, 810 .pa_end = 0x4a30401f,
807 .flags = ADDR_TYPE_RT 811 .flags = ADDR_TYPE_RT
808 }, 812 },
813 { }
809}; 814};
810 815
811/* l4_wkup -> counter_32k */ 816/* l4_wkup -> counter_32k */
@@ -814,7 +819,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
814 .slave = &omap44xx_counter_32k_hwmod, 819 .slave = &omap44xx_counter_32k_hwmod,
815 .clk = "l4_wkup_clk_mux_ck", 820 .clk = "l4_wkup_clk_mux_ck",
816 .addr = omap44xx_counter_32k_addrs, 821 .addr = omap44xx_counter_32k_addrs,
817 .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
818 .user = OCP_USER_MPU | OCP_USER_SDMA, 822 .user = OCP_USER_MPU | OCP_USER_SDMA,
819}; 823};
820 824
@@ -828,7 +832,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
828 .class = &omap44xx_counter_hwmod_class, 832 .class = &omap44xx_counter_hwmod_class,
829 .flags = HWMOD_SWSUP_SIDLE, 833 .flags = HWMOD_SWSUP_SIDLE,
830 .main_clk = "sys_32k_ck", 834 .main_clk = "sys_32k_ck",
831 .prcm = { 835 .prcm = {
832 .omap4 = { 836 .omap4 = {
833 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, 837 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
834 }, 838 },
@@ -875,6 +879,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
875 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, 879 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
876 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, 880 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
877 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, 881 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
882 { .irq = -1 }
878}; 883};
879 884
880/* dma_system master ports */ 885/* dma_system master ports */
@@ -888,6 +893,7 @@ static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
888 .pa_end = 0x4a056fff, 893 .pa_end = 0x4a056fff,
889 .flags = ADDR_TYPE_RT 894 .flags = ADDR_TYPE_RT
890 }, 895 },
896 { }
891}; 897};
892 898
893/* l4_cfg -> dma_system */ 899/* l4_cfg -> dma_system */
@@ -896,7 +902,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
896 .slave = &omap44xx_dma_system_hwmod, 902 .slave = &omap44xx_dma_system_hwmod,
897 .clk = "l4_div_ck", 903 .clk = "l4_div_ck",
898 .addr = omap44xx_dma_system_addrs, 904 .addr = omap44xx_dma_system_addrs,
899 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
900 .user = OCP_USER_MPU | OCP_USER_SDMA, 905 .user = OCP_USER_MPU | OCP_USER_SDMA,
901}; 906};
902 907
@@ -909,7 +914,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
909 .name = "dma_system", 914 .name = "dma_system",
910 .class = &omap44xx_dma_hwmod_class, 915 .class = &omap44xx_dma_hwmod_class,
911 .mpu_irqs = omap44xx_dma_system_irqs, 916 .mpu_irqs = omap44xx_dma_system_irqs,
912 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
913 .main_clk = "l3_div_ck", 917 .main_clk = "l3_div_ck",
914 .prcm = { 918 .prcm = {
915 .omap4 = { 919 .omap4 = {
@@ -948,10 +952,12 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
948static struct omap_hwmod omap44xx_dmic_hwmod; 952static struct omap_hwmod omap44xx_dmic_hwmod;
949static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { 953static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
950 { .irq = 114 + OMAP44XX_IRQ_GIC_START }, 954 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
955 { .irq = -1 }
951}; 956};
952 957
953static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { 958static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
954 { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, 959 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
960 { .dma_req = -1 }
955}; 961};
956 962
957static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { 963static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
@@ -960,6 +966,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
960 .pa_end = 0x4012e07f, 966 .pa_end = 0x4012e07f,
961 .flags = ADDR_TYPE_RT 967 .flags = ADDR_TYPE_RT
962 }, 968 },
969 { }
963}; 970};
964 971
965/* l4_abe -> dmic */ 972/* l4_abe -> dmic */
@@ -968,7 +975,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
968 .slave = &omap44xx_dmic_hwmod, 975 .slave = &omap44xx_dmic_hwmod,
969 .clk = "ocp_abe_iclk", 976 .clk = "ocp_abe_iclk",
970 .addr = omap44xx_dmic_addrs, 977 .addr = omap44xx_dmic_addrs,
971 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
972 .user = OCP_USER_MPU, 978 .user = OCP_USER_MPU,
973}; 979};
974 980
@@ -978,6 +984,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
978 .pa_end = 0x4902e07f, 984 .pa_end = 0x4902e07f,
979 .flags = ADDR_TYPE_RT 985 .flags = ADDR_TYPE_RT
980 }, 986 },
987 { }
981}; 988};
982 989
983/* l4_abe -> dmic (dma) */ 990/* l4_abe -> dmic (dma) */
@@ -986,7 +993,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
986 .slave = &omap44xx_dmic_hwmod, 993 .slave = &omap44xx_dmic_hwmod,
987 .clk = "ocp_abe_iclk", 994 .clk = "ocp_abe_iclk",
988 .addr = omap44xx_dmic_dma_addrs, 995 .addr = omap44xx_dmic_dma_addrs,
989 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
990 .user = OCP_USER_SDMA, 996 .user = OCP_USER_SDMA,
991}; 997};
992 998
@@ -1000,11 +1006,9 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
1000 .name = "dmic", 1006 .name = "dmic",
1001 .class = &omap44xx_dmic_hwmod_class, 1007 .class = &omap44xx_dmic_hwmod_class,
1002 .mpu_irqs = omap44xx_dmic_irqs, 1008 .mpu_irqs = omap44xx_dmic_irqs,
1003 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
1004 .sdma_reqs = omap44xx_dmic_sdma_reqs, 1009 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1005 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
1006 .main_clk = "dmic_fck", 1010 .main_clk = "dmic_fck",
1007 .prcm = { 1011 .prcm = {
1008 .omap4 = { 1012 .omap4 = {
1009 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, 1013 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1010 }, 1014 },
@@ -1026,6 +1030,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1026/* dsp */ 1030/* dsp */
1027static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { 1031static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1028 { .irq = 28 + OMAP44XX_IRQ_GIC_START }, 1032 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1033 { .irq = -1 }
1029}; 1034};
1030 1035
1031static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 1036static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
@@ -1082,7 +1087,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
1082 .name = "dsp", 1087 .name = "dsp",
1083 .class = &omap44xx_dsp_hwmod_class, 1088 .class = &omap44xx_dsp_hwmod_class,
1084 .mpu_irqs = omap44xx_dsp_irqs, 1089 .mpu_irqs = omap44xx_dsp_irqs,
1085 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
1086 .rst_lines = omap44xx_dsp_resets, 1090 .rst_lines = omap44xx_dsp_resets,
1087 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), 1091 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1088 .main_clk = "dsp_fck", 1092 .main_clk = "dsp_fck",
@@ -1127,15 +1131,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1127 .pa_end = 0x5800007f, 1131 .pa_end = 0x5800007f,
1128 .flags = ADDR_TYPE_RT 1132 .flags = ADDR_TYPE_RT
1129 }, 1133 },
1134 { }
1130}; 1135};
1131 1136
1132/* l3_main_2 -> dss */ 1137/* l3_main_2 -> dss */
1133static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { 1138static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1134 .master = &omap44xx_l3_main_2_hwmod, 1139 .master = &omap44xx_l3_main_2_hwmod,
1135 .slave = &omap44xx_dss_hwmod, 1140 .slave = &omap44xx_dss_hwmod,
1136 .clk = "l3_div_ck", 1141 .clk = "dss_fck",
1137 .addr = omap44xx_dss_dma_addrs, 1142 .addr = omap44xx_dss_dma_addrs,
1138 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1139 .user = OCP_USER_SDMA, 1143 .user = OCP_USER_SDMA,
1140}; 1144};
1141 1145
@@ -1145,6 +1149,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1145 .pa_end = 0x4804007f, 1149 .pa_end = 0x4804007f,
1146 .flags = ADDR_TYPE_RT 1150 .flags = ADDR_TYPE_RT
1147 }, 1151 },
1152 { }
1148}; 1153};
1149 1154
1150/* l4_per -> dss */ 1155/* l4_per -> dss */
@@ -1153,7 +1158,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1153 .slave = &omap44xx_dss_hwmod, 1158 .slave = &omap44xx_dss_hwmod,
1154 .clk = "l4_div_ck", 1159 .clk = "l4_div_ck",
1155 .addr = omap44xx_dss_addrs, 1160 .addr = omap44xx_dss_addrs,
1156 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
1157 .user = OCP_USER_MPU, 1161 .user = OCP_USER_MPU,
1158}; 1162};
1159 1163
@@ -1173,7 +1177,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1173static struct omap_hwmod omap44xx_dss_hwmod = { 1177static struct omap_hwmod omap44xx_dss_hwmod = {
1174 .name = "dss_core", 1178 .name = "dss_core",
1175 .class = &omap44xx_dss_hwmod_class, 1179 .class = &omap44xx_dss_hwmod_class,
1176 .main_clk = "dss_fck", 1180 .main_clk = "dss_dss_clk",
1177 .prcm = { 1181 .prcm = {
1178 .omap4 = { 1182 .omap4 = {
1179 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1183 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -1215,10 +1219,12 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1215static struct omap_hwmod omap44xx_dss_dispc_hwmod; 1219static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1216static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { 1220static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1217 { .irq = 25 + OMAP44XX_IRQ_GIC_START }, 1221 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1222 { .irq = -1 }
1218}; 1223};
1219 1224
1220static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { 1225static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1221 { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, 1226 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1227 { .dma_req = -1 }
1222}; 1228};
1223 1229
1224static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { 1230static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
@@ -1227,15 +1233,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1227 .pa_end = 0x58001fff, 1233 .pa_end = 0x58001fff,
1228 .flags = ADDR_TYPE_RT 1234 .flags = ADDR_TYPE_RT
1229 }, 1235 },
1236 { }
1230}; 1237};
1231 1238
1232/* l3_main_2 -> dss_dispc */ 1239/* l3_main_2 -> dss_dispc */
1233static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { 1240static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1234 .master = &omap44xx_l3_main_2_hwmod, 1241 .master = &omap44xx_l3_main_2_hwmod,
1235 .slave = &omap44xx_dss_dispc_hwmod, 1242 .slave = &omap44xx_dss_dispc_hwmod,
1236 .clk = "l3_div_ck", 1243 .clk = "dss_fck",
1237 .addr = omap44xx_dss_dispc_dma_addrs, 1244 .addr = omap44xx_dss_dispc_dma_addrs,
1238 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1239 .user = OCP_USER_SDMA, 1245 .user = OCP_USER_SDMA,
1240}; 1246};
1241 1247
@@ -1245,6 +1251,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1245 .pa_end = 0x48041fff, 1251 .pa_end = 0x48041fff,
1246 .flags = ADDR_TYPE_RT 1252 .flags = ADDR_TYPE_RT
1247 }, 1253 },
1254 { }
1248}; 1255};
1249 1256
1250/* l4_per -> dss_dispc */ 1257/* l4_per -> dss_dispc */
@@ -1253,7 +1260,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1253 .slave = &omap44xx_dss_dispc_hwmod, 1260 .slave = &omap44xx_dss_dispc_hwmod,
1254 .clk = "l4_div_ck", 1261 .clk = "l4_div_ck",
1255 .addr = omap44xx_dss_dispc_addrs, 1262 .addr = omap44xx_dss_dispc_addrs,
1256 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1257 .user = OCP_USER_MPU, 1263 .user = OCP_USER_MPU,
1258}; 1264};
1259 1265
@@ -1263,19 +1269,26 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1263 &omap44xx_l4_per__dss_dispc, 1269 &omap44xx_l4_per__dss_dispc,
1264}; 1270};
1265 1271
1272static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1273 { .role = "sys_clk", .clk = "dss_sys_clk" },
1274 { .role = "tv_clk", .clk = "dss_tv_clk" },
1275 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1276};
1277
1266static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 1278static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1267 .name = "dss_dispc", 1279 .name = "dss_dispc",
1268 .class = &omap44xx_dispc_hwmod_class, 1280 .class = &omap44xx_dispc_hwmod_class,
1281 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1269 .mpu_irqs = omap44xx_dss_dispc_irqs, 1282 .mpu_irqs = omap44xx_dss_dispc_irqs,
1270 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1271 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, 1283 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1272 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), 1284 .main_clk = "dss_dss_clk",
1273 .main_clk = "dss_fck",
1274 .prcm = { 1285 .prcm = {
1275 .omap4 = { 1286 .omap4 = {
1276 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1287 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1277 }, 1288 },
1278 }, 1289 },
1290 .opt_clks = dss_dispc_opt_clks,
1291 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
1279 .slaves = omap44xx_dss_dispc_slaves, 1292 .slaves = omap44xx_dss_dispc_slaves,
1280 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), 1293 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1281 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1306,10 +1319,12 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1306static struct omap_hwmod omap44xx_dss_dsi1_hwmod; 1319static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1307static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { 1320static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1308 { .irq = 53 + OMAP44XX_IRQ_GIC_START }, 1321 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1322 { .irq = -1 }
1309}; 1323};
1310 1324
1311static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { 1325static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1312 { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, 1326 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1327 { .dma_req = -1 }
1313}; 1328};
1314 1329
1315static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { 1330static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
@@ -1318,15 +1333,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1318 .pa_end = 0x580041ff, 1333 .pa_end = 0x580041ff,
1319 .flags = ADDR_TYPE_RT 1334 .flags = ADDR_TYPE_RT
1320 }, 1335 },
1336 { }
1321}; 1337};
1322 1338
1323/* l3_main_2 -> dss_dsi1 */ 1339/* l3_main_2 -> dss_dsi1 */
1324static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { 1340static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1325 .master = &omap44xx_l3_main_2_hwmod, 1341 .master = &omap44xx_l3_main_2_hwmod,
1326 .slave = &omap44xx_dss_dsi1_hwmod, 1342 .slave = &omap44xx_dss_dsi1_hwmod,
1327 .clk = "l3_div_ck", 1343 .clk = "dss_fck",
1328 .addr = omap44xx_dss_dsi1_dma_addrs, 1344 .addr = omap44xx_dss_dsi1_dma_addrs,
1329 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1330 .user = OCP_USER_SDMA, 1345 .user = OCP_USER_SDMA,
1331}; 1346};
1332 1347
@@ -1336,6 +1351,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1336 .pa_end = 0x480441ff, 1351 .pa_end = 0x480441ff,
1337 .flags = ADDR_TYPE_RT 1352 .flags = ADDR_TYPE_RT
1338 }, 1353 },
1354 { }
1339}; 1355};
1340 1356
1341/* l4_per -> dss_dsi1 */ 1357/* l4_per -> dss_dsi1 */
@@ -1344,7 +1360,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1344 .slave = &omap44xx_dss_dsi1_hwmod, 1360 .slave = &omap44xx_dss_dsi1_hwmod,
1345 .clk = "l4_div_ck", 1361 .clk = "l4_div_ck",
1346 .addr = omap44xx_dss_dsi1_addrs, 1362 .addr = omap44xx_dss_dsi1_addrs,
1347 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1348 .user = OCP_USER_MPU, 1363 .user = OCP_USER_MPU,
1349}; 1364};
1350 1365
@@ -1354,19 +1369,23 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1354 &omap44xx_l4_per__dss_dsi1, 1369 &omap44xx_l4_per__dss_dsi1,
1355}; 1370};
1356 1371
1372static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1373 { .role = "sys_clk", .clk = "dss_sys_clk" },
1374};
1375
1357static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { 1376static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1358 .name = "dss_dsi1", 1377 .name = "dss_dsi1",
1359 .class = &omap44xx_dsi_hwmod_class, 1378 .class = &omap44xx_dsi_hwmod_class,
1360 .mpu_irqs = omap44xx_dss_dsi1_irqs, 1379 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1361 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1362 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, 1380 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1363 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), 1381 .main_clk = "dss_dss_clk",
1364 .main_clk = "dss_fck",
1365 .prcm = { 1382 .prcm = {
1366 .omap4 = { 1383 .omap4 = {
1367 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1384 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1368 }, 1385 },
1369 }, 1386 },
1387 .opt_clks = dss_dsi1_opt_clks,
1388 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1370 .slaves = omap44xx_dss_dsi1_slaves, 1389 .slaves = omap44xx_dss_dsi1_slaves,
1371 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), 1390 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1372 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1391 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1376,10 +1395,12 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1376static struct omap_hwmod omap44xx_dss_dsi2_hwmod; 1395static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1377static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { 1396static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1378 { .irq = 84 + OMAP44XX_IRQ_GIC_START }, 1397 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1398 { .irq = -1 }
1379}; 1399};
1380 1400
1381static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { 1401static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1382 { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, 1402 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1403 { .dma_req = -1 }
1383}; 1404};
1384 1405
1385static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { 1406static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
@@ -1388,15 +1409,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1388 .pa_end = 0x580051ff, 1409 .pa_end = 0x580051ff,
1389 .flags = ADDR_TYPE_RT 1410 .flags = ADDR_TYPE_RT
1390 }, 1411 },
1412 { }
1391}; 1413};
1392 1414
1393/* l3_main_2 -> dss_dsi2 */ 1415/* l3_main_2 -> dss_dsi2 */
1394static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { 1416static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1395 .master = &omap44xx_l3_main_2_hwmod, 1417 .master = &omap44xx_l3_main_2_hwmod,
1396 .slave = &omap44xx_dss_dsi2_hwmod, 1418 .slave = &omap44xx_dss_dsi2_hwmod,
1397 .clk = "l3_div_ck", 1419 .clk = "dss_fck",
1398 .addr = omap44xx_dss_dsi2_dma_addrs, 1420 .addr = omap44xx_dss_dsi2_dma_addrs,
1399 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1400 .user = OCP_USER_SDMA, 1421 .user = OCP_USER_SDMA,
1401}; 1422};
1402 1423
@@ -1406,6 +1427,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1406 .pa_end = 0x480451ff, 1427 .pa_end = 0x480451ff,
1407 .flags = ADDR_TYPE_RT 1428 .flags = ADDR_TYPE_RT
1408 }, 1429 },
1430 { }
1409}; 1431};
1410 1432
1411/* l4_per -> dss_dsi2 */ 1433/* l4_per -> dss_dsi2 */
@@ -1414,7 +1436,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1414 .slave = &omap44xx_dss_dsi2_hwmod, 1436 .slave = &omap44xx_dss_dsi2_hwmod,
1415 .clk = "l4_div_ck", 1437 .clk = "l4_div_ck",
1416 .addr = omap44xx_dss_dsi2_addrs, 1438 .addr = omap44xx_dss_dsi2_addrs,
1417 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1418 .user = OCP_USER_MPU, 1439 .user = OCP_USER_MPU,
1419}; 1440};
1420 1441
@@ -1424,19 +1445,23 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1424 &omap44xx_l4_per__dss_dsi2, 1445 &omap44xx_l4_per__dss_dsi2,
1425}; 1446};
1426 1447
1448static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1449 { .role = "sys_clk", .clk = "dss_sys_clk" },
1450};
1451
1427static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { 1452static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1428 .name = "dss_dsi2", 1453 .name = "dss_dsi2",
1429 .class = &omap44xx_dsi_hwmod_class, 1454 .class = &omap44xx_dsi_hwmod_class,
1430 .mpu_irqs = omap44xx_dss_dsi2_irqs, 1455 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1431 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1432 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, 1456 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1433 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), 1457 .main_clk = "dss_dss_clk",
1434 .main_clk = "dss_fck",
1435 .prcm = { 1458 .prcm = {
1436 .omap4 = { 1459 .omap4 = {
1437 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1460 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1438 }, 1461 },
1439 }, 1462 },
1463 .opt_clks = dss_dsi2_opt_clks,
1464 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1440 .slaves = omap44xx_dss_dsi2_slaves, 1465 .slaves = omap44xx_dss_dsi2_slaves,
1441 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), 1466 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1442 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1467 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1466,10 +1491,12 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1466static struct omap_hwmod omap44xx_dss_hdmi_hwmod; 1491static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1467static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { 1492static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1468 { .irq = 101 + OMAP44XX_IRQ_GIC_START }, 1493 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1494 { .irq = -1 }
1469}; 1495};
1470 1496
1471static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { 1497static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1472 { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, 1498 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1499 { .dma_req = -1 }
1473}; 1500};
1474 1501
1475static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { 1502static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
@@ -1478,15 +1505,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1478 .pa_end = 0x58006fff, 1505 .pa_end = 0x58006fff,
1479 .flags = ADDR_TYPE_RT 1506 .flags = ADDR_TYPE_RT
1480 }, 1507 },
1508 { }
1481}; 1509};
1482 1510
1483/* l3_main_2 -> dss_hdmi */ 1511/* l3_main_2 -> dss_hdmi */
1484static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { 1512static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1485 .master = &omap44xx_l3_main_2_hwmod, 1513 .master = &omap44xx_l3_main_2_hwmod,
1486 .slave = &omap44xx_dss_hdmi_hwmod, 1514 .slave = &omap44xx_dss_hdmi_hwmod,
1487 .clk = "l3_div_ck", 1515 .clk = "dss_fck",
1488 .addr = omap44xx_dss_hdmi_dma_addrs, 1516 .addr = omap44xx_dss_hdmi_dma_addrs,
1489 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1490 .user = OCP_USER_SDMA, 1517 .user = OCP_USER_SDMA,
1491}; 1518};
1492 1519
@@ -1496,6 +1523,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1496 .pa_end = 0x48046fff, 1523 .pa_end = 0x48046fff,
1497 .flags = ADDR_TYPE_RT 1524 .flags = ADDR_TYPE_RT
1498 }, 1525 },
1526 { }
1499}; 1527};
1500 1528
1501/* l4_per -> dss_hdmi */ 1529/* l4_per -> dss_hdmi */
@@ -1504,7 +1532,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1504 .slave = &omap44xx_dss_hdmi_hwmod, 1532 .slave = &omap44xx_dss_hdmi_hwmod,
1505 .clk = "l4_div_ck", 1533 .clk = "l4_div_ck",
1506 .addr = omap44xx_dss_hdmi_addrs, 1534 .addr = omap44xx_dss_hdmi_addrs,
1507 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1508 .user = OCP_USER_MPU, 1535 .user = OCP_USER_MPU,
1509}; 1536};
1510 1537
@@ -1514,19 +1541,23 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1514 &omap44xx_l4_per__dss_hdmi, 1541 &omap44xx_l4_per__dss_hdmi,
1515}; 1542};
1516 1543
1544static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1545 { .role = "sys_clk", .clk = "dss_sys_clk" },
1546};
1547
1517static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { 1548static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1518 .name = "dss_hdmi", 1549 .name = "dss_hdmi",
1519 .class = &omap44xx_hdmi_hwmod_class, 1550 .class = &omap44xx_hdmi_hwmod_class,
1520 .mpu_irqs = omap44xx_dss_hdmi_irqs, 1551 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1521 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1522 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 1552 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1523 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), 1553 .main_clk = "dss_dss_clk",
1524 .main_clk = "dss_fck",
1525 .prcm = { 1554 .prcm = {
1526 .omap4 = { 1555 .omap4 = {
1527 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1556 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1528 }, 1557 },
1529 }, 1558 },
1559 .opt_clks = dss_hdmi_opt_clks,
1560 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1530 .slaves = omap44xx_dss_hdmi_slaves, 1561 .slaves = omap44xx_dss_hdmi_slaves,
1531 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), 1562 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1556,6 +1587,7 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1556static struct omap_hwmod omap44xx_dss_rfbi_hwmod; 1587static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1557static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { 1588static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1558 { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, 1589 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1590 { .dma_req = -1 }
1559}; 1591};
1560 1592
1561static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { 1593static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
@@ -1564,15 +1596,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1564 .pa_end = 0x580020ff, 1596 .pa_end = 0x580020ff,
1565 .flags = ADDR_TYPE_RT 1597 .flags = ADDR_TYPE_RT
1566 }, 1598 },
1599 { }
1567}; 1600};
1568 1601
1569/* l3_main_2 -> dss_rfbi */ 1602/* l3_main_2 -> dss_rfbi */
1570static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { 1603static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1571 .master = &omap44xx_l3_main_2_hwmod, 1604 .master = &omap44xx_l3_main_2_hwmod,
1572 .slave = &omap44xx_dss_rfbi_hwmod, 1605 .slave = &omap44xx_dss_rfbi_hwmod,
1573 .clk = "l3_div_ck", 1606 .clk = "dss_fck",
1574 .addr = omap44xx_dss_rfbi_dma_addrs, 1607 .addr = omap44xx_dss_rfbi_dma_addrs,
1575 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1576 .user = OCP_USER_SDMA, 1608 .user = OCP_USER_SDMA,
1577}; 1609};
1578 1610
@@ -1582,6 +1614,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1582 .pa_end = 0x480420ff, 1614 .pa_end = 0x480420ff,
1583 .flags = ADDR_TYPE_RT 1615 .flags = ADDR_TYPE_RT
1584 }, 1616 },
1617 { }
1585}; 1618};
1586 1619
1587/* l4_per -> dss_rfbi */ 1620/* l4_per -> dss_rfbi */
@@ -1590,7 +1623,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1590 .slave = &omap44xx_dss_rfbi_hwmod, 1623 .slave = &omap44xx_dss_rfbi_hwmod,
1591 .clk = "l4_div_ck", 1624 .clk = "l4_div_ck",
1592 .addr = omap44xx_dss_rfbi_addrs, 1625 .addr = omap44xx_dss_rfbi_addrs,
1593 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1594 .user = OCP_USER_MPU, 1626 .user = OCP_USER_MPU,
1595}; 1627};
1596 1628
@@ -1600,17 +1632,22 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1600 &omap44xx_l4_per__dss_rfbi, 1632 &omap44xx_l4_per__dss_rfbi,
1601}; 1633};
1602 1634
1635static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1636 { .role = "ick", .clk = "dss_fck" },
1637};
1638
1603static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { 1639static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1604 .name = "dss_rfbi", 1640 .name = "dss_rfbi",
1605 .class = &omap44xx_rfbi_hwmod_class, 1641 .class = &omap44xx_rfbi_hwmod_class,
1606 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, 1642 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1607 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs), 1643 .main_clk = "dss_dss_clk",
1608 .main_clk = "dss_fck",
1609 .prcm = { 1644 .prcm = {
1610 .omap4 = { 1645 .omap4 = {
1611 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1646 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1612 }, 1647 },
1613 }, 1648 },
1649 .opt_clks = dss_rfbi_opt_clks,
1650 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1614 .slaves = omap44xx_dss_rfbi_slaves, 1651 .slaves = omap44xx_dss_rfbi_slaves,
1615 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), 1652 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1616 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1653 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1633,15 +1670,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1633 .pa_end = 0x580030ff, 1670 .pa_end = 0x580030ff,
1634 .flags = ADDR_TYPE_RT 1671 .flags = ADDR_TYPE_RT
1635 }, 1672 },
1673 { }
1636}; 1674};
1637 1675
1638/* l3_main_2 -> dss_venc */ 1676/* l3_main_2 -> dss_venc */
1639static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { 1677static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1640 .master = &omap44xx_l3_main_2_hwmod, 1678 .master = &omap44xx_l3_main_2_hwmod,
1641 .slave = &omap44xx_dss_venc_hwmod, 1679 .slave = &omap44xx_dss_venc_hwmod,
1642 .clk = "l3_div_ck", 1680 .clk = "dss_fck",
1643 .addr = omap44xx_dss_venc_dma_addrs, 1681 .addr = omap44xx_dss_venc_dma_addrs,
1644 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1645 .user = OCP_USER_SDMA, 1682 .user = OCP_USER_SDMA,
1646}; 1683};
1647 1684
@@ -1651,6 +1688,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1651 .pa_end = 0x480430ff, 1688 .pa_end = 0x480430ff,
1652 .flags = ADDR_TYPE_RT 1689 .flags = ADDR_TYPE_RT
1653 }, 1690 },
1691 { }
1654}; 1692};
1655 1693
1656/* l4_per -> dss_venc */ 1694/* l4_per -> dss_venc */
@@ -1659,7 +1697,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1659 .slave = &omap44xx_dss_venc_hwmod, 1697 .slave = &omap44xx_dss_venc_hwmod,
1660 .clk = "l4_div_ck", 1698 .clk = "l4_div_ck",
1661 .addr = omap44xx_dss_venc_addrs, 1699 .addr = omap44xx_dss_venc_addrs,
1662 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1663 .user = OCP_USER_MPU, 1700 .user = OCP_USER_MPU,
1664}; 1701};
1665 1702
@@ -1672,7 +1709,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1672static struct omap_hwmod omap44xx_dss_venc_hwmod = { 1709static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1673 .name = "dss_venc", 1710 .name = "dss_venc",
1674 .class = &omap44xx_venc_hwmod_class, 1711 .class = &omap44xx_venc_hwmod_class,
1675 .main_clk = "dss_fck", 1712 .main_clk = "dss_dss_clk",
1676 .prcm = { 1713 .prcm = {
1677 .omap4 = { 1714 .omap4 = {
1678 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1715 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -1716,6 +1753,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1716static struct omap_hwmod omap44xx_gpio1_hwmod; 1753static struct omap_hwmod omap44xx_gpio1_hwmod;
1717static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { 1754static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1718 { .irq = 29 + OMAP44XX_IRQ_GIC_START }, 1755 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1756 { .irq = -1 }
1719}; 1757};
1720 1758
1721static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { 1759static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
@@ -1724,6 +1762,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1724 .pa_end = 0x4a3101ff, 1762 .pa_end = 0x4a3101ff,
1725 .flags = ADDR_TYPE_RT 1763 .flags = ADDR_TYPE_RT
1726 }, 1764 },
1765 { }
1727}; 1766};
1728 1767
1729/* l4_wkup -> gpio1 */ 1768/* l4_wkup -> gpio1 */
@@ -1732,7 +1771,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1732 .slave = &omap44xx_gpio1_hwmod, 1771 .slave = &omap44xx_gpio1_hwmod,
1733 .clk = "l4_wkup_clk_mux_ck", 1772 .clk = "l4_wkup_clk_mux_ck",
1734 .addr = omap44xx_gpio1_addrs, 1773 .addr = omap44xx_gpio1_addrs,
1735 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
1736 .user = OCP_USER_MPU | OCP_USER_SDMA, 1774 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737}; 1775};
1738 1776
@@ -1749,7 +1787,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1749 .name = "gpio1", 1787 .name = "gpio1",
1750 .class = &omap44xx_gpio_hwmod_class, 1788 .class = &omap44xx_gpio_hwmod_class,
1751 .mpu_irqs = omap44xx_gpio1_irqs, 1789 .mpu_irqs = omap44xx_gpio1_irqs,
1752 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1753 .main_clk = "gpio1_ick", 1790 .main_clk = "gpio1_ick",
1754 .prcm = { 1791 .prcm = {
1755 .omap4 = { 1792 .omap4 = {
@@ -1768,6 +1805,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1768static struct omap_hwmod omap44xx_gpio2_hwmod; 1805static struct omap_hwmod omap44xx_gpio2_hwmod;
1769static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { 1806static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1770 { .irq = 30 + OMAP44XX_IRQ_GIC_START }, 1807 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1808 { .irq = -1 }
1771}; 1809};
1772 1810
1773static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { 1811static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
@@ -1776,6 +1814,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1776 .pa_end = 0x480551ff, 1814 .pa_end = 0x480551ff,
1777 .flags = ADDR_TYPE_RT 1815 .flags = ADDR_TYPE_RT
1778 }, 1816 },
1817 { }
1779}; 1818};
1780 1819
1781/* l4_per -> gpio2 */ 1820/* l4_per -> gpio2 */
@@ -1784,7 +1823,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1784 .slave = &omap44xx_gpio2_hwmod, 1823 .slave = &omap44xx_gpio2_hwmod,
1785 .clk = "l4_div_ck", 1824 .clk = "l4_div_ck",
1786 .addr = omap44xx_gpio2_addrs, 1825 .addr = omap44xx_gpio2_addrs,
1787 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
1788 .user = OCP_USER_MPU | OCP_USER_SDMA, 1826 .user = OCP_USER_MPU | OCP_USER_SDMA,
1789}; 1827};
1790 1828
@@ -1802,7 +1840,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1802 .class = &omap44xx_gpio_hwmod_class, 1840 .class = &omap44xx_gpio_hwmod_class,
1803 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1841 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1804 .mpu_irqs = omap44xx_gpio2_irqs, 1842 .mpu_irqs = omap44xx_gpio2_irqs,
1805 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1806 .main_clk = "gpio2_ick", 1843 .main_clk = "gpio2_ick",
1807 .prcm = { 1844 .prcm = {
1808 .omap4 = { 1845 .omap4 = {
@@ -1821,6 +1858,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1821static struct omap_hwmod omap44xx_gpio3_hwmod; 1858static struct omap_hwmod omap44xx_gpio3_hwmod;
1822static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { 1859static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1823 { .irq = 31 + OMAP44XX_IRQ_GIC_START }, 1860 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1861 { .irq = -1 }
1824}; 1862};
1825 1863
1826static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { 1864static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
@@ -1829,6 +1867,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1829 .pa_end = 0x480571ff, 1867 .pa_end = 0x480571ff,
1830 .flags = ADDR_TYPE_RT 1868 .flags = ADDR_TYPE_RT
1831 }, 1869 },
1870 { }
1832}; 1871};
1833 1872
1834/* l4_per -> gpio3 */ 1873/* l4_per -> gpio3 */
@@ -1837,7 +1876,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1837 .slave = &omap44xx_gpio3_hwmod, 1876 .slave = &omap44xx_gpio3_hwmod,
1838 .clk = "l4_div_ck", 1877 .clk = "l4_div_ck",
1839 .addr = omap44xx_gpio3_addrs, 1878 .addr = omap44xx_gpio3_addrs,
1840 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
1841 .user = OCP_USER_MPU | OCP_USER_SDMA, 1879 .user = OCP_USER_MPU | OCP_USER_SDMA,
1842}; 1880};
1843 1881
@@ -1855,7 +1893,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1855 .class = &omap44xx_gpio_hwmod_class, 1893 .class = &omap44xx_gpio_hwmod_class,
1856 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1894 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1857 .mpu_irqs = omap44xx_gpio3_irqs, 1895 .mpu_irqs = omap44xx_gpio3_irqs,
1858 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
1859 .main_clk = "gpio3_ick", 1896 .main_clk = "gpio3_ick",
1860 .prcm = { 1897 .prcm = {
1861 .omap4 = { 1898 .omap4 = {
@@ -1874,6 +1911,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1874static struct omap_hwmod omap44xx_gpio4_hwmod; 1911static struct omap_hwmod omap44xx_gpio4_hwmod;
1875static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { 1912static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1876 { .irq = 32 + OMAP44XX_IRQ_GIC_START }, 1913 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1914 { .irq = -1 }
1877}; 1915};
1878 1916
1879static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { 1917static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
@@ -1882,6 +1920,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1882 .pa_end = 0x480591ff, 1920 .pa_end = 0x480591ff,
1883 .flags = ADDR_TYPE_RT 1921 .flags = ADDR_TYPE_RT
1884 }, 1922 },
1923 { }
1885}; 1924};
1886 1925
1887/* l4_per -> gpio4 */ 1926/* l4_per -> gpio4 */
@@ -1890,7 +1929,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1890 .slave = &omap44xx_gpio4_hwmod, 1929 .slave = &omap44xx_gpio4_hwmod,
1891 .clk = "l4_div_ck", 1930 .clk = "l4_div_ck",
1892 .addr = omap44xx_gpio4_addrs, 1931 .addr = omap44xx_gpio4_addrs,
1893 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
1894 .user = OCP_USER_MPU | OCP_USER_SDMA, 1932 .user = OCP_USER_MPU | OCP_USER_SDMA,
1895}; 1933};
1896 1934
@@ -1908,7 +1946,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
1908 .class = &omap44xx_gpio_hwmod_class, 1946 .class = &omap44xx_gpio_hwmod_class,
1909 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1947 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1910 .mpu_irqs = omap44xx_gpio4_irqs, 1948 .mpu_irqs = omap44xx_gpio4_irqs,
1911 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1912 .main_clk = "gpio4_ick", 1949 .main_clk = "gpio4_ick",
1913 .prcm = { 1950 .prcm = {
1914 .omap4 = { 1951 .omap4 = {
@@ -1927,6 +1964,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
1927static struct omap_hwmod omap44xx_gpio5_hwmod; 1964static struct omap_hwmod omap44xx_gpio5_hwmod;
1928static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { 1965static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1929 { .irq = 33 + OMAP44XX_IRQ_GIC_START }, 1966 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1967 { .irq = -1 }
1930}; 1968};
1931 1969
1932static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { 1970static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
@@ -1935,6 +1973,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1935 .pa_end = 0x4805b1ff, 1973 .pa_end = 0x4805b1ff,
1936 .flags = ADDR_TYPE_RT 1974 .flags = ADDR_TYPE_RT
1937 }, 1975 },
1976 { }
1938}; 1977};
1939 1978
1940/* l4_per -> gpio5 */ 1979/* l4_per -> gpio5 */
@@ -1943,7 +1982,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1943 .slave = &omap44xx_gpio5_hwmod, 1982 .slave = &omap44xx_gpio5_hwmod,
1944 .clk = "l4_div_ck", 1983 .clk = "l4_div_ck",
1945 .addr = omap44xx_gpio5_addrs, 1984 .addr = omap44xx_gpio5_addrs,
1946 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1947 .user = OCP_USER_MPU | OCP_USER_SDMA, 1985 .user = OCP_USER_MPU | OCP_USER_SDMA,
1948}; 1986};
1949 1987
@@ -1961,7 +1999,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
1961 .class = &omap44xx_gpio_hwmod_class, 1999 .class = &omap44xx_gpio_hwmod_class,
1962 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2000 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1963 .mpu_irqs = omap44xx_gpio5_irqs, 2001 .mpu_irqs = omap44xx_gpio5_irqs,
1964 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1965 .main_clk = "gpio5_ick", 2002 .main_clk = "gpio5_ick",
1966 .prcm = { 2003 .prcm = {
1967 .omap4 = { 2004 .omap4 = {
@@ -1980,6 +2017,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
1980static struct omap_hwmod omap44xx_gpio6_hwmod; 2017static struct omap_hwmod omap44xx_gpio6_hwmod;
1981static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { 2018static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1982 { .irq = 34 + OMAP44XX_IRQ_GIC_START }, 2019 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2020 { .irq = -1 }
1983}; 2021};
1984 2022
1985static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { 2023static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
@@ -1988,6 +2026,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1988 .pa_end = 0x4805d1ff, 2026 .pa_end = 0x4805d1ff,
1989 .flags = ADDR_TYPE_RT 2027 .flags = ADDR_TYPE_RT
1990 }, 2028 },
2029 { }
1991}; 2030};
1992 2031
1993/* l4_per -> gpio6 */ 2032/* l4_per -> gpio6 */
@@ -1996,7 +2035,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1996 .slave = &omap44xx_gpio6_hwmod, 2035 .slave = &omap44xx_gpio6_hwmod,
1997 .clk = "l4_div_ck", 2036 .clk = "l4_div_ck",
1998 .addr = omap44xx_gpio6_addrs, 2037 .addr = omap44xx_gpio6_addrs,
1999 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
2000 .user = OCP_USER_MPU | OCP_USER_SDMA, 2038 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001}; 2039};
2002 2040
@@ -2014,7 +2052,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
2014 .class = &omap44xx_gpio_hwmod_class, 2052 .class = &omap44xx_gpio_hwmod_class,
2015 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2053 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2016 .mpu_irqs = omap44xx_gpio6_irqs, 2054 .mpu_irqs = omap44xx_gpio6_irqs,
2017 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
2018 .main_clk = "gpio6_ick", 2055 .main_clk = "gpio6_ick",
2019 .prcm = { 2056 .prcm = {
2020 .omap4 = { 2057 .omap4 = {
@@ -2044,7 +2081,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2044 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2081 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2045 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2082 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2046 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 2083 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2047 MSTANDBY_SMART), 2084 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2048 .sysc_fields = &omap_hwmod_sysc_type1, 2085 .sysc_fields = &omap_hwmod_sysc_type1,
2049}; 2086};
2050 2087
@@ -2058,6 +2095,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2058 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, 2095 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2059 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, 2096 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2060 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, 2097 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2098 { .irq = -1 }
2061}; 2099};
2062 2100
2063/* hsi master ports */ 2101/* hsi master ports */
@@ -2071,6 +2109,7 @@ static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2071 .pa_end = 0x4a05bfff, 2109 .pa_end = 0x4a05bfff,
2072 .flags = ADDR_TYPE_RT 2110 .flags = ADDR_TYPE_RT
2073 }, 2111 },
2112 { }
2074}; 2113};
2075 2114
2076/* l4_cfg -> hsi */ 2115/* l4_cfg -> hsi */
@@ -2079,7 +2118,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2079 .slave = &omap44xx_hsi_hwmod, 2118 .slave = &omap44xx_hsi_hwmod,
2080 .clk = "l4_div_ck", 2119 .clk = "l4_div_ck",
2081 .addr = omap44xx_hsi_addrs, 2120 .addr = omap44xx_hsi_addrs,
2082 .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
2083 .user = OCP_USER_MPU | OCP_USER_SDMA, 2121 .user = OCP_USER_MPU | OCP_USER_SDMA,
2084}; 2122};
2085 2123
@@ -2092,9 +2130,8 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
2092 .name = "hsi", 2130 .name = "hsi",
2093 .class = &omap44xx_hsi_hwmod_class, 2131 .class = &omap44xx_hsi_hwmod_class,
2094 .mpu_irqs = omap44xx_hsi_irqs, 2132 .mpu_irqs = omap44xx_hsi_irqs,
2095 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
2096 .main_clk = "hsi_fck", 2133 .main_clk = "hsi_fck",
2097 .prcm = { 2134 .prcm = {
2098 .omap4 = { 2135 .omap4 = {
2099 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 2136 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2100 }, 2137 },
@@ -2125,17 +2162,25 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2125static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { 2162static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2126 .name = "i2c", 2163 .name = "i2c",
2127 .sysc = &omap44xx_i2c_sysc, 2164 .sysc = &omap44xx_i2c_sysc,
2165 .rev = OMAP_I2C_IP_VERSION_2,
2166 .reset = &omap_i2c_reset,
2167};
2168
2169static struct omap_i2c_dev_attr i2c_dev_attr = {
2170 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2128}; 2171};
2129 2172
2130/* i2c1 */ 2173/* i2c1 */
2131static struct omap_hwmod omap44xx_i2c1_hwmod; 2174static struct omap_hwmod omap44xx_i2c1_hwmod;
2132static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { 2175static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2133 { .irq = 56 + OMAP44XX_IRQ_GIC_START }, 2176 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2177 { .irq = -1 }
2134}; 2178};
2135 2179
2136static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { 2180static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2137 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, 2181 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2138 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, 2182 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2183 { .dma_req = -1 }
2139}; 2184};
2140 2185
2141static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { 2186static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
@@ -2144,6 +2189,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2144 .pa_end = 0x480700ff, 2189 .pa_end = 0x480700ff,
2145 .flags = ADDR_TYPE_RT 2190 .flags = ADDR_TYPE_RT
2146 }, 2191 },
2192 { }
2147}; 2193};
2148 2194
2149/* l4_per -> i2c1 */ 2195/* l4_per -> i2c1 */
@@ -2152,7 +2198,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2152 .slave = &omap44xx_i2c1_hwmod, 2198 .slave = &omap44xx_i2c1_hwmod,
2153 .clk = "l4_div_ck", 2199 .clk = "l4_div_ck",
2154 .addr = omap44xx_i2c1_addrs, 2200 .addr = omap44xx_i2c1_addrs,
2155 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
2156 .user = OCP_USER_MPU | OCP_USER_SDMA, 2201 .user = OCP_USER_MPU | OCP_USER_SDMA,
2157}; 2202};
2158 2203
@@ -2164,11 +2209,9 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2164static struct omap_hwmod omap44xx_i2c1_hwmod = { 2209static struct omap_hwmod omap44xx_i2c1_hwmod = {
2165 .name = "i2c1", 2210 .name = "i2c1",
2166 .class = &omap44xx_i2c_hwmod_class, 2211 .class = &omap44xx_i2c_hwmod_class,
2167 .flags = HWMOD_INIT_NO_RESET, 2212 .flags = HWMOD_16BIT_REG,
2168 .mpu_irqs = omap44xx_i2c1_irqs, 2213 .mpu_irqs = omap44xx_i2c1_irqs,
2169 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
2170 .sdma_reqs = omap44xx_i2c1_sdma_reqs, 2214 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2171 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2172 .main_clk = "i2c1_fck", 2215 .main_clk = "i2c1_fck",
2173 .prcm = { 2216 .prcm = {
2174 .omap4 = { 2217 .omap4 = {
@@ -2177,6 +2220,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2177 }, 2220 },
2178 .slaves = omap44xx_i2c1_slaves, 2221 .slaves = omap44xx_i2c1_slaves,
2179 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), 2222 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2223 .dev_attr = &i2c_dev_attr,
2180 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2224 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2181}; 2225};
2182 2226
@@ -2184,11 +2228,13 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2184static struct omap_hwmod omap44xx_i2c2_hwmod; 2228static struct omap_hwmod omap44xx_i2c2_hwmod;
2185static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { 2229static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2186 { .irq = 57 + OMAP44XX_IRQ_GIC_START }, 2230 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2231 { .irq = -1 }
2187}; 2232};
2188 2233
2189static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { 2234static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2190 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, 2235 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2191 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, 2236 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2237 { .dma_req = -1 }
2192}; 2238};
2193 2239
2194static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { 2240static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
@@ -2197,6 +2243,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2197 .pa_end = 0x480720ff, 2243 .pa_end = 0x480720ff,
2198 .flags = ADDR_TYPE_RT 2244 .flags = ADDR_TYPE_RT
2199 }, 2245 },
2246 { }
2200}; 2247};
2201 2248
2202/* l4_per -> i2c2 */ 2249/* l4_per -> i2c2 */
@@ -2205,7 +2252,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2205 .slave = &omap44xx_i2c2_hwmod, 2252 .slave = &omap44xx_i2c2_hwmod,
2206 .clk = "l4_div_ck", 2253 .clk = "l4_div_ck",
2207 .addr = omap44xx_i2c2_addrs, 2254 .addr = omap44xx_i2c2_addrs,
2208 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
2209 .user = OCP_USER_MPU | OCP_USER_SDMA, 2255 .user = OCP_USER_MPU | OCP_USER_SDMA,
2210}; 2256};
2211 2257
@@ -2217,11 +2263,9 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2217static struct omap_hwmod omap44xx_i2c2_hwmod = { 2263static struct omap_hwmod omap44xx_i2c2_hwmod = {
2218 .name = "i2c2", 2264 .name = "i2c2",
2219 .class = &omap44xx_i2c_hwmod_class, 2265 .class = &omap44xx_i2c_hwmod_class,
2220 .flags = HWMOD_INIT_NO_RESET, 2266 .flags = HWMOD_16BIT_REG,
2221 .mpu_irqs = omap44xx_i2c2_irqs, 2267 .mpu_irqs = omap44xx_i2c2_irqs,
2222 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
2223 .sdma_reqs = omap44xx_i2c2_sdma_reqs, 2268 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2224 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2225 .main_clk = "i2c2_fck", 2269 .main_clk = "i2c2_fck",
2226 .prcm = { 2270 .prcm = {
2227 .omap4 = { 2271 .omap4 = {
@@ -2230,6 +2274,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
2230 }, 2274 },
2231 .slaves = omap44xx_i2c2_slaves, 2275 .slaves = omap44xx_i2c2_slaves,
2232 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), 2276 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2277 .dev_attr = &i2c_dev_attr,
2233 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2234}; 2279};
2235 2280
@@ -2237,11 +2282,13 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
2237static struct omap_hwmod omap44xx_i2c3_hwmod; 2282static struct omap_hwmod omap44xx_i2c3_hwmod;
2238static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { 2283static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2239 { .irq = 61 + OMAP44XX_IRQ_GIC_START }, 2284 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2285 { .irq = -1 }
2240}; 2286};
2241 2287
2242static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { 2288static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2243 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, 2289 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2244 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, 2290 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2291 { .dma_req = -1 }
2245}; 2292};
2246 2293
2247static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { 2294static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
@@ -2250,6 +2297,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2250 .pa_end = 0x480600ff, 2297 .pa_end = 0x480600ff,
2251 .flags = ADDR_TYPE_RT 2298 .flags = ADDR_TYPE_RT
2252 }, 2299 },
2300 { }
2253}; 2301};
2254 2302
2255/* l4_per -> i2c3 */ 2303/* l4_per -> i2c3 */
@@ -2258,7 +2306,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2258 .slave = &omap44xx_i2c3_hwmod, 2306 .slave = &omap44xx_i2c3_hwmod,
2259 .clk = "l4_div_ck", 2307 .clk = "l4_div_ck",
2260 .addr = omap44xx_i2c3_addrs, 2308 .addr = omap44xx_i2c3_addrs,
2261 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
2262 .user = OCP_USER_MPU | OCP_USER_SDMA, 2309 .user = OCP_USER_MPU | OCP_USER_SDMA,
2263}; 2310};
2264 2311
@@ -2270,11 +2317,9 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2270static struct omap_hwmod omap44xx_i2c3_hwmod = { 2317static struct omap_hwmod omap44xx_i2c3_hwmod = {
2271 .name = "i2c3", 2318 .name = "i2c3",
2272 .class = &omap44xx_i2c_hwmod_class, 2319 .class = &omap44xx_i2c_hwmod_class,
2273 .flags = HWMOD_INIT_NO_RESET, 2320 .flags = HWMOD_16BIT_REG,
2274 .mpu_irqs = omap44xx_i2c3_irqs, 2321 .mpu_irqs = omap44xx_i2c3_irqs,
2275 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
2276 .sdma_reqs = omap44xx_i2c3_sdma_reqs, 2322 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2277 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2278 .main_clk = "i2c3_fck", 2323 .main_clk = "i2c3_fck",
2279 .prcm = { 2324 .prcm = {
2280 .omap4 = { 2325 .omap4 = {
@@ -2283,6 +2328,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
2283 }, 2328 },
2284 .slaves = omap44xx_i2c3_slaves, 2329 .slaves = omap44xx_i2c3_slaves,
2285 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), 2330 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2331 .dev_attr = &i2c_dev_attr,
2286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2332 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2287}; 2333};
2288 2334
@@ -2290,11 +2336,13 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
2290static struct omap_hwmod omap44xx_i2c4_hwmod; 2336static struct omap_hwmod omap44xx_i2c4_hwmod;
2291static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { 2337static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2292 { .irq = 62 + OMAP44XX_IRQ_GIC_START }, 2338 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2339 { .irq = -1 }
2293}; 2340};
2294 2341
2295static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { 2342static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2296 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, 2343 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2297 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, 2344 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2345 { .dma_req = -1 }
2298}; 2346};
2299 2347
2300static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { 2348static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
@@ -2303,6 +2351,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2303 .pa_end = 0x483500ff, 2351 .pa_end = 0x483500ff,
2304 .flags = ADDR_TYPE_RT 2352 .flags = ADDR_TYPE_RT
2305 }, 2353 },
2354 { }
2306}; 2355};
2307 2356
2308/* l4_per -> i2c4 */ 2357/* l4_per -> i2c4 */
@@ -2311,7 +2360,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2311 .slave = &omap44xx_i2c4_hwmod, 2360 .slave = &omap44xx_i2c4_hwmod,
2312 .clk = "l4_div_ck", 2361 .clk = "l4_div_ck",
2313 .addr = omap44xx_i2c4_addrs, 2362 .addr = omap44xx_i2c4_addrs,
2314 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
2315 .user = OCP_USER_MPU | OCP_USER_SDMA, 2363 .user = OCP_USER_MPU | OCP_USER_SDMA,
2316}; 2364};
2317 2365
@@ -2323,11 +2371,9 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2323static struct omap_hwmod omap44xx_i2c4_hwmod = { 2371static struct omap_hwmod omap44xx_i2c4_hwmod = {
2324 .name = "i2c4", 2372 .name = "i2c4",
2325 .class = &omap44xx_i2c_hwmod_class, 2373 .class = &omap44xx_i2c_hwmod_class,
2326 .flags = HWMOD_INIT_NO_RESET, 2374 .flags = HWMOD_16BIT_REG,
2327 .mpu_irqs = omap44xx_i2c4_irqs, 2375 .mpu_irqs = omap44xx_i2c4_irqs,
2328 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
2329 .sdma_reqs = omap44xx_i2c4_sdma_reqs, 2376 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2330 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2331 .main_clk = "i2c4_fck", 2377 .main_clk = "i2c4_fck",
2332 .prcm = { 2378 .prcm = {
2333 .omap4 = { 2379 .omap4 = {
@@ -2336,6 +2382,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
2336 }, 2382 },
2337 .slaves = omap44xx_i2c4_slaves, 2383 .slaves = omap44xx_i2c4_slaves,
2338 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), 2384 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2385 .dev_attr = &i2c_dev_attr,
2339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2386 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2340}; 2387};
2341 2388
@@ -2351,6 +2398,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2351/* ipu */ 2398/* ipu */
2352static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { 2399static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2353 { .irq = 100 + OMAP44XX_IRQ_GIC_START }, 2400 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2401 { .irq = -1 }
2354}; 2402};
2355 2403
2356static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { 2404static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
@@ -2390,7 +2438,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2390 .flags = HWMOD_INIT_NO_RESET, 2438 .flags = HWMOD_INIT_NO_RESET,
2391 .rst_lines = omap44xx_ipu_c0_resets, 2439 .rst_lines = omap44xx_ipu_c0_resets,
2392 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), 2440 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2393 .prcm = { 2441 .prcm = {
2394 .omap4 = { 2442 .omap4 = {
2395 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2443 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2396 }, 2444 },
@@ -2405,7 +2453,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2405 .flags = HWMOD_INIT_NO_RESET, 2453 .flags = HWMOD_INIT_NO_RESET,
2406 .rst_lines = omap44xx_ipu_c1_resets, 2454 .rst_lines = omap44xx_ipu_c1_resets,
2407 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), 2455 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2408 .prcm = { 2456 .prcm = {
2409 .omap4 = { 2457 .omap4 = {
2410 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2458 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2411 }, 2459 },
@@ -2417,11 +2465,10 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
2417 .name = "ipu", 2465 .name = "ipu",
2418 .class = &omap44xx_ipu_hwmod_class, 2466 .class = &omap44xx_ipu_hwmod_class,
2419 .mpu_irqs = omap44xx_ipu_irqs, 2467 .mpu_irqs = omap44xx_ipu_irqs,
2420 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
2421 .rst_lines = omap44xx_ipu_resets, 2468 .rst_lines = omap44xx_ipu_resets,
2422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), 2469 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2423 .main_clk = "ipu_fck", 2470 .main_clk = "ipu_fck",
2424 .prcm = { 2471 .prcm = {
2425 .omap4 = { 2472 .omap4 = {
2426 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 2473 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2427 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2474 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
@@ -2446,7 +2493,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2446 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2493 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2494 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2448 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 2495 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2449 MSTANDBY_SMART), 2496 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2450 .sysc_fields = &omap_hwmod_sysc_type2, 2497 .sysc_fields = &omap_hwmod_sysc_type2,
2451}; 2498};
2452 2499
@@ -2458,6 +2505,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2458/* iss */ 2505/* iss */
2459static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { 2506static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2460 { .irq = 24 + OMAP44XX_IRQ_GIC_START }, 2507 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2508 { .irq = -1 }
2461}; 2509};
2462 2510
2463static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { 2511static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
@@ -2465,6 +2513,7 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2465 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, 2513 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2466 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, 2514 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2467 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, 2515 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2516 { .dma_req = -1 }
2468}; 2517};
2469 2518
2470/* iss master ports */ 2519/* iss master ports */
@@ -2478,6 +2527,7 @@ static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2478 .pa_end = 0x520000ff, 2527 .pa_end = 0x520000ff,
2479 .flags = ADDR_TYPE_RT 2528 .flags = ADDR_TYPE_RT
2480 }, 2529 },
2530 { }
2481}; 2531};
2482 2532
2483/* l3_main_2 -> iss */ 2533/* l3_main_2 -> iss */
@@ -2486,7 +2536,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2486 .slave = &omap44xx_iss_hwmod, 2536 .slave = &omap44xx_iss_hwmod,
2487 .clk = "l3_div_ck", 2537 .clk = "l3_div_ck",
2488 .addr = omap44xx_iss_addrs, 2538 .addr = omap44xx_iss_addrs,
2489 .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
2490 .user = OCP_USER_MPU | OCP_USER_SDMA, 2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2491}; 2540};
2492 2541
@@ -2503,11 +2552,9 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
2503 .name = "iss", 2552 .name = "iss",
2504 .class = &omap44xx_iss_hwmod_class, 2553 .class = &omap44xx_iss_hwmod_class,
2505 .mpu_irqs = omap44xx_iss_irqs, 2554 .mpu_irqs = omap44xx_iss_irqs,
2506 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
2507 .sdma_reqs = omap44xx_iss_sdma_reqs, 2555 .sdma_reqs = omap44xx_iss_sdma_reqs,
2508 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2509 .main_clk = "iss_fck", 2556 .main_clk = "iss_fck",
2510 .prcm = { 2557 .prcm = {
2511 .omap4 = { 2558 .omap4 = {
2512 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, 2559 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2513 }, 2560 },
@@ -2535,6 +2582,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2535 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, 2582 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2536 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, 2583 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2537 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, 2584 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2585 { .irq = -1 }
2538}; 2586};
2539 2587
2540static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { 2588static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
@@ -2561,6 +2609,7 @@ static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2561 .pa_end = 0x5a07ffff, 2609 .pa_end = 0x5a07ffff,
2562 .flags = ADDR_TYPE_RT 2610 .flags = ADDR_TYPE_RT
2563 }, 2611 },
2612 { }
2564}; 2613};
2565 2614
2566/* l3_main_2 -> iva */ 2615/* l3_main_2 -> iva */
@@ -2569,7 +2618,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2569 .slave = &omap44xx_iva_hwmod, 2618 .slave = &omap44xx_iva_hwmod,
2570 .clk = "l3_div_ck", 2619 .clk = "l3_div_ck",
2571 .addr = omap44xx_iva_addrs, 2620 .addr = omap44xx_iva_addrs,
2572 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
2573 .user = OCP_USER_MPU, 2621 .user = OCP_USER_MPU,
2574}; 2622};
2575 2623
@@ -2613,7 +2661,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
2613 .name = "iva", 2661 .name = "iva",
2614 .class = &omap44xx_iva_hwmod_class, 2662 .class = &omap44xx_iva_hwmod_class,
2615 .mpu_irqs = omap44xx_iva_irqs, 2663 .mpu_irqs = omap44xx_iva_irqs,
2616 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
2617 .rst_lines = omap44xx_iva_resets, 2664 .rst_lines = omap44xx_iva_resets,
2618 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), 2665 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2619 .main_clk = "iva_fck", 2666 .main_clk = "iva_fck",
@@ -2656,6 +2703,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2656static struct omap_hwmod omap44xx_kbd_hwmod; 2703static struct omap_hwmod omap44xx_kbd_hwmod;
2657static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { 2704static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2658 { .irq = 120 + OMAP44XX_IRQ_GIC_START }, 2705 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2706 { .irq = -1 }
2659}; 2707};
2660 2708
2661static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { 2709static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
@@ -2664,6 +2712,7 @@ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2664 .pa_end = 0x4a31c07f, 2712 .pa_end = 0x4a31c07f,
2665 .flags = ADDR_TYPE_RT 2713 .flags = ADDR_TYPE_RT
2666 }, 2714 },
2715 { }
2667}; 2716};
2668 2717
2669/* l4_wkup -> kbd */ 2718/* l4_wkup -> kbd */
@@ -2672,7 +2721,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2672 .slave = &omap44xx_kbd_hwmod, 2721 .slave = &omap44xx_kbd_hwmod,
2673 .clk = "l4_wkup_clk_mux_ck", 2722 .clk = "l4_wkup_clk_mux_ck",
2674 .addr = omap44xx_kbd_addrs, 2723 .addr = omap44xx_kbd_addrs,
2675 .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
2676 .user = OCP_USER_MPU | OCP_USER_SDMA, 2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677}; 2725};
2678 2726
@@ -2685,9 +2733,8 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
2685 .name = "kbd", 2733 .name = "kbd",
2686 .class = &omap44xx_kbd_hwmod_class, 2734 .class = &omap44xx_kbd_hwmod_class,
2687 .mpu_irqs = omap44xx_kbd_irqs, 2735 .mpu_irqs = omap44xx_kbd_irqs,
2688 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
2689 .main_clk = "kbd_fck", 2736 .main_clk = "kbd_fck",
2690 .prcm = { 2737 .prcm = {
2691 .omap4 = { 2738 .omap4 = {
2692 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 2739 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2693 }, 2740 },
@@ -2721,6 +2768,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2721static struct omap_hwmod omap44xx_mailbox_hwmod; 2768static struct omap_hwmod omap44xx_mailbox_hwmod;
2722static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { 2769static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2723 { .irq = 26 + OMAP44XX_IRQ_GIC_START }, 2770 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2771 { .irq = -1 }
2724}; 2772};
2725 2773
2726static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { 2774static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
@@ -2729,6 +2777,7 @@ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2729 .pa_end = 0x4a0f41ff, 2777 .pa_end = 0x4a0f41ff,
2730 .flags = ADDR_TYPE_RT 2778 .flags = ADDR_TYPE_RT
2731 }, 2779 },
2780 { }
2732}; 2781};
2733 2782
2734/* l4_cfg -> mailbox */ 2783/* l4_cfg -> mailbox */
@@ -2737,7 +2786,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2737 .slave = &omap44xx_mailbox_hwmod, 2786 .slave = &omap44xx_mailbox_hwmod,
2738 .clk = "l4_div_ck", 2787 .clk = "l4_div_ck",
2739 .addr = omap44xx_mailbox_addrs, 2788 .addr = omap44xx_mailbox_addrs,
2740 .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
2741 .user = OCP_USER_MPU | OCP_USER_SDMA, 2789 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742}; 2790};
2743 2791
@@ -2750,8 +2798,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
2750 .name = "mailbox", 2798 .name = "mailbox",
2751 .class = &omap44xx_mailbox_hwmod_class, 2799 .class = &omap44xx_mailbox_hwmod_class,
2752 .mpu_irqs = omap44xx_mailbox_irqs, 2800 .mpu_irqs = omap44xx_mailbox_irqs,
2753 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs), 2801 .prcm = {
2754 .prcm = {
2755 .omap4 = { 2802 .omap4 = {
2756 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, 2803 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2757 }, 2804 },
@@ -2784,11 +2831,13 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2784static struct omap_hwmod omap44xx_mcbsp1_hwmod; 2831static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2785static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { 2832static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2786 { .irq = 17 + OMAP44XX_IRQ_GIC_START }, 2833 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2834 { .irq = -1 }
2787}; 2835};
2788 2836
2789static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { 2837static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2790 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, 2838 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2791 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, 2839 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2840 { .dma_req = -1 }
2792}; 2841};
2793 2842
2794static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { 2843static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
@@ -2798,6 +2847,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2798 .pa_end = 0x401220ff, 2847 .pa_end = 0x401220ff,
2799 .flags = ADDR_TYPE_RT 2848 .flags = ADDR_TYPE_RT
2800 }, 2849 },
2850 { }
2801}; 2851};
2802 2852
2803/* l4_abe -> mcbsp1 */ 2853/* l4_abe -> mcbsp1 */
@@ -2806,7 +2856,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2806 .slave = &omap44xx_mcbsp1_hwmod, 2856 .slave = &omap44xx_mcbsp1_hwmod,
2807 .clk = "ocp_abe_iclk", 2857 .clk = "ocp_abe_iclk",
2808 .addr = omap44xx_mcbsp1_addrs, 2858 .addr = omap44xx_mcbsp1_addrs,
2809 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2810 .user = OCP_USER_MPU, 2859 .user = OCP_USER_MPU,
2811}; 2860};
2812 2861
@@ -2817,6 +2866,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2817 .pa_end = 0x490220ff, 2866 .pa_end = 0x490220ff,
2818 .flags = ADDR_TYPE_RT 2867 .flags = ADDR_TYPE_RT
2819 }, 2868 },
2869 { }
2820}; 2870};
2821 2871
2822/* l4_abe -> mcbsp1 (dma) */ 2872/* l4_abe -> mcbsp1 (dma) */
@@ -2825,7 +2875,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2825 .slave = &omap44xx_mcbsp1_hwmod, 2875 .slave = &omap44xx_mcbsp1_hwmod,
2826 .clk = "ocp_abe_iclk", 2876 .clk = "ocp_abe_iclk",
2827 .addr = omap44xx_mcbsp1_dma_addrs, 2877 .addr = omap44xx_mcbsp1_dma_addrs,
2828 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2829 .user = OCP_USER_SDMA, 2878 .user = OCP_USER_SDMA,
2830}; 2879};
2831 2880
@@ -2839,9 +2888,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2839 .name = "mcbsp1", 2888 .name = "mcbsp1",
2840 .class = &omap44xx_mcbsp_hwmod_class, 2889 .class = &omap44xx_mcbsp_hwmod_class,
2841 .mpu_irqs = omap44xx_mcbsp1_irqs, 2890 .mpu_irqs = omap44xx_mcbsp1_irqs,
2842 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2843 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, 2891 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
2844 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2845 .main_clk = "mcbsp1_fck", 2892 .main_clk = "mcbsp1_fck",
2846 .prcm = { 2893 .prcm = {
2847 .omap4 = { 2894 .omap4 = {
@@ -2857,11 +2904,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2857static struct omap_hwmod omap44xx_mcbsp2_hwmod; 2904static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2858static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { 2905static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2859 { .irq = 22 + OMAP44XX_IRQ_GIC_START }, 2906 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2907 { .irq = -1 }
2860}; 2908};
2861 2909
2862static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { 2910static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2863 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, 2911 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2864 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, 2912 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2913 { .dma_req = -1 }
2865}; 2914};
2866 2915
2867static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { 2916static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
@@ -2871,6 +2920,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2871 .pa_end = 0x401240ff, 2920 .pa_end = 0x401240ff,
2872 .flags = ADDR_TYPE_RT 2921 .flags = ADDR_TYPE_RT
2873 }, 2922 },
2923 { }
2874}; 2924};
2875 2925
2876/* l4_abe -> mcbsp2 */ 2926/* l4_abe -> mcbsp2 */
@@ -2879,7 +2929,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2879 .slave = &omap44xx_mcbsp2_hwmod, 2929 .slave = &omap44xx_mcbsp2_hwmod,
2880 .clk = "ocp_abe_iclk", 2930 .clk = "ocp_abe_iclk",
2881 .addr = omap44xx_mcbsp2_addrs, 2931 .addr = omap44xx_mcbsp2_addrs,
2882 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2883 .user = OCP_USER_MPU, 2932 .user = OCP_USER_MPU,
2884}; 2933};
2885 2934
@@ -2890,6 +2939,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2890 .pa_end = 0x490240ff, 2939 .pa_end = 0x490240ff,
2891 .flags = ADDR_TYPE_RT 2940 .flags = ADDR_TYPE_RT
2892 }, 2941 },
2942 { }
2893}; 2943};
2894 2944
2895/* l4_abe -> mcbsp2 (dma) */ 2945/* l4_abe -> mcbsp2 (dma) */
@@ -2898,7 +2948,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2898 .slave = &omap44xx_mcbsp2_hwmod, 2948 .slave = &omap44xx_mcbsp2_hwmod,
2899 .clk = "ocp_abe_iclk", 2949 .clk = "ocp_abe_iclk",
2900 .addr = omap44xx_mcbsp2_dma_addrs, 2950 .addr = omap44xx_mcbsp2_dma_addrs,
2901 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2902 .user = OCP_USER_SDMA, 2951 .user = OCP_USER_SDMA,
2903}; 2952};
2904 2953
@@ -2912,9 +2961,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2912 .name = "mcbsp2", 2961 .name = "mcbsp2",
2913 .class = &omap44xx_mcbsp_hwmod_class, 2962 .class = &omap44xx_mcbsp_hwmod_class,
2914 .mpu_irqs = omap44xx_mcbsp2_irqs, 2963 .mpu_irqs = omap44xx_mcbsp2_irqs,
2915 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2916 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, 2964 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2917 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2918 .main_clk = "mcbsp2_fck", 2965 .main_clk = "mcbsp2_fck",
2919 .prcm = { 2966 .prcm = {
2920 .omap4 = { 2967 .omap4 = {
@@ -2930,11 +2977,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2930static struct omap_hwmod omap44xx_mcbsp3_hwmod; 2977static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2931static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { 2978static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2932 { .irq = 23 + OMAP44XX_IRQ_GIC_START }, 2979 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2980 { .irq = -1 }
2933}; 2981};
2934 2982
2935static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { 2983static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2936 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, 2984 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2937 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, 2985 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2986 { .dma_req = -1 }
2938}; 2987};
2939 2988
2940static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { 2989static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
@@ -2944,6 +2993,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2944 .pa_end = 0x401260ff, 2993 .pa_end = 0x401260ff,
2945 .flags = ADDR_TYPE_RT 2994 .flags = ADDR_TYPE_RT
2946 }, 2995 },
2996 { }
2947}; 2997};
2948 2998
2949/* l4_abe -> mcbsp3 */ 2999/* l4_abe -> mcbsp3 */
@@ -2952,7 +3002,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2952 .slave = &omap44xx_mcbsp3_hwmod, 3002 .slave = &omap44xx_mcbsp3_hwmod,
2953 .clk = "ocp_abe_iclk", 3003 .clk = "ocp_abe_iclk",
2954 .addr = omap44xx_mcbsp3_addrs, 3004 .addr = omap44xx_mcbsp3_addrs,
2955 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2956 .user = OCP_USER_MPU, 3005 .user = OCP_USER_MPU,
2957}; 3006};
2958 3007
@@ -2963,6 +3012,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2963 .pa_end = 0x490260ff, 3012 .pa_end = 0x490260ff,
2964 .flags = ADDR_TYPE_RT 3013 .flags = ADDR_TYPE_RT
2965 }, 3014 },
3015 { }
2966}; 3016};
2967 3017
2968/* l4_abe -> mcbsp3 (dma) */ 3018/* l4_abe -> mcbsp3 (dma) */
@@ -2971,7 +3021,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2971 .slave = &omap44xx_mcbsp3_hwmod, 3021 .slave = &omap44xx_mcbsp3_hwmod,
2972 .clk = "ocp_abe_iclk", 3022 .clk = "ocp_abe_iclk",
2973 .addr = omap44xx_mcbsp3_dma_addrs, 3023 .addr = omap44xx_mcbsp3_dma_addrs,
2974 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2975 .user = OCP_USER_SDMA, 3024 .user = OCP_USER_SDMA,
2976}; 3025};
2977 3026
@@ -2985,9 +3034,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2985 .name = "mcbsp3", 3034 .name = "mcbsp3",
2986 .class = &omap44xx_mcbsp_hwmod_class, 3035 .class = &omap44xx_mcbsp_hwmod_class,
2987 .mpu_irqs = omap44xx_mcbsp3_irqs, 3036 .mpu_irqs = omap44xx_mcbsp3_irqs,
2988 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2989 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, 3037 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2990 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2991 .main_clk = "mcbsp3_fck", 3038 .main_clk = "mcbsp3_fck",
2992 .prcm = { 3039 .prcm = {
2993 .omap4 = { 3040 .omap4 = {
@@ -3003,11 +3050,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3003static struct omap_hwmod omap44xx_mcbsp4_hwmod; 3050static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3004static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { 3051static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3005 { .irq = 16 + OMAP44XX_IRQ_GIC_START }, 3052 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3053 { .irq = -1 }
3006}; 3054};
3007 3055
3008static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { 3056static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3009 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, 3057 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3010 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, 3058 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3059 { .dma_req = -1 }
3011}; 3060};
3012 3061
3013static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { 3062static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
@@ -3016,6 +3065,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3016 .pa_end = 0x480960ff, 3065 .pa_end = 0x480960ff,
3017 .flags = ADDR_TYPE_RT 3066 .flags = ADDR_TYPE_RT
3018 }, 3067 },
3068 { }
3019}; 3069};
3020 3070
3021/* l4_per -> mcbsp4 */ 3071/* l4_per -> mcbsp4 */
@@ -3024,7 +3074,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3024 .slave = &omap44xx_mcbsp4_hwmod, 3074 .slave = &omap44xx_mcbsp4_hwmod,
3025 .clk = "l4_div_ck", 3075 .clk = "l4_div_ck",
3026 .addr = omap44xx_mcbsp4_addrs, 3076 .addr = omap44xx_mcbsp4_addrs,
3027 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
3028 .user = OCP_USER_MPU | OCP_USER_SDMA, 3077 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029}; 3078};
3030 3079
@@ -3037,9 +3086,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3037 .name = "mcbsp4", 3086 .name = "mcbsp4",
3038 .class = &omap44xx_mcbsp_hwmod_class, 3087 .class = &omap44xx_mcbsp_hwmod_class,
3039 .mpu_irqs = omap44xx_mcbsp4_irqs, 3088 .mpu_irqs = omap44xx_mcbsp4_irqs,
3040 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
3041 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, 3089 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3042 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
3043 .main_clk = "mcbsp4_fck", 3090 .main_clk = "mcbsp4_fck",
3044 .prcm = { 3091 .prcm = {
3045 .omap4 = { 3092 .omap4 = {
@@ -3076,11 +3123,13 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3076static struct omap_hwmod omap44xx_mcpdm_hwmod; 3123static struct omap_hwmod omap44xx_mcpdm_hwmod;
3077static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { 3124static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3078 { .irq = 112 + OMAP44XX_IRQ_GIC_START }, 3125 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3126 { .irq = -1 }
3079}; 3127};
3080 3128
3081static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { 3129static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3082 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, 3130 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3083 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, 3131 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3132 { .dma_req = -1 }
3084}; 3133};
3085 3134
3086static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { 3135static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
@@ -3089,6 +3138,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3089 .pa_end = 0x4013207f, 3138 .pa_end = 0x4013207f,
3090 .flags = ADDR_TYPE_RT 3139 .flags = ADDR_TYPE_RT
3091 }, 3140 },
3141 { }
3092}; 3142};
3093 3143
3094/* l4_abe -> mcpdm */ 3144/* l4_abe -> mcpdm */
@@ -3097,7 +3147,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3097 .slave = &omap44xx_mcpdm_hwmod, 3147 .slave = &omap44xx_mcpdm_hwmod,
3098 .clk = "ocp_abe_iclk", 3148 .clk = "ocp_abe_iclk",
3099 .addr = omap44xx_mcpdm_addrs, 3149 .addr = omap44xx_mcpdm_addrs,
3100 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3101 .user = OCP_USER_MPU, 3150 .user = OCP_USER_MPU,
3102}; 3151};
3103 3152
@@ -3107,6 +3156,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3107 .pa_end = 0x4903207f, 3156 .pa_end = 0x4903207f,
3108 .flags = ADDR_TYPE_RT 3157 .flags = ADDR_TYPE_RT
3109 }, 3158 },
3159 { }
3110}; 3160};
3111 3161
3112/* l4_abe -> mcpdm (dma) */ 3162/* l4_abe -> mcpdm (dma) */
@@ -3115,7 +3165,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3115 .slave = &omap44xx_mcpdm_hwmod, 3165 .slave = &omap44xx_mcpdm_hwmod,
3116 .clk = "ocp_abe_iclk", 3166 .clk = "ocp_abe_iclk",
3117 .addr = omap44xx_mcpdm_dma_addrs, 3167 .addr = omap44xx_mcpdm_dma_addrs,
3118 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3119 .user = OCP_USER_SDMA, 3168 .user = OCP_USER_SDMA,
3120}; 3169};
3121 3170
@@ -3129,11 +3178,9 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3129 .name = "mcpdm", 3178 .name = "mcpdm",
3130 .class = &omap44xx_mcpdm_hwmod_class, 3179 .class = &omap44xx_mcpdm_hwmod_class,
3131 .mpu_irqs = omap44xx_mcpdm_irqs, 3180 .mpu_irqs = omap44xx_mcpdm_irqs,
3132 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3133 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 3181 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3134 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3135 .main_clk = "mcpdm_fck", 3182 .main_clk = "mcpdm_fck",
3136 .prcm = { 3183 .prcm = {
3137 .omap4 = { 3184 .omap4 = {
3138 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 3185 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3139 }, 3186 },
@@ -3169,6 +3216,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3169static struct omap_hwmod omap44xx_mcspi1_hwmod; 3216static struct omap_hwmod omap44xx_mcspi1_hwmod;
3170static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { 3217static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3171 { .irq = 65 + OMAP44XX_IRQ_GIC_START }, 3218 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3219 { .irq = -1 }
3172}; 3220};
3173 3221
3174static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { 3222static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
@@ -3180,6 +3228,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3180 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, 3228 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3181 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, 3229 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3182 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, 3230 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3231 { .dma_req = -1 }
3183}; 3232};
3184 3233
3185static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { 3234static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
@@ -3188,6 +3237,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3188 .pa_end = 0x480981ff, 3237 .pa_end = 0x480981ff,
3189 .flags = ADDR_TYPE_RT 3238 .flags = ADDR_TYPE_RT
3190 }, 3239 },
3240 { }
3191}; 3241};
3192 3242
3193/* l4_per -> mcspi1 */ 3243/* l4_per -> mcspi1 */
@@ -3196,7 +3246,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3196 .slave = &omap44xx_mcspi1_hwmod, 3246 .slave = &omap44xx_mcspi1_hwmod,
3197 .clk = "l4_div_ck", 3247 .clk = "l4_div_ck",
3198 .addr = omap44xx_mcspi1_addrs, 3248 .addr = omap44xx_mcspi1_addrs,
3199 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3200 .user = OCP_USER_MPU | OCP_USER_SDMA, 3249 .user = OCP_USER_MPU | OCP_USER_SDMA,
3201}; 3250};
3202 3251
@@ -3214,9 +3263,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3214 .name = "mcspi1", 3263 .name = "mcspi1",
3215 .class = &omap44xx_mcspi_hwmod_class, 3264 .class = &omap44xx_mcspi_hwmod_class,
3216 .mpu_irqs = omap44xx_mcspi1_irqs, 3265 .mpu_irqs = omap44xx_mcspi1_irqs,
3217 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3218 .sdma_reqs = omap44xx_mcspi1_sdma_reqs, 3266 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3219 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3220 .main_clk = "mcspi1_fck", 3267 .main_clk = "mcspi1_fck",
3221 .prcm = { 3268 .prcm = {
3222 .omap4 = { 3269 .omap4 = {
@@ -3233,6 +3280,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3233static struct omap_hwmod omap44xx_mcspi2_hwmod; 3280static struct omap_hwmod omap44xx_mcspi2_hwmod;
3234static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { 3281static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3235 { .irq = 66 + OMAP44XX_IRQ_GIC_START }, 3282 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3283 { .irq = -1 }
3236}; 3284};
3237 3285
3238static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { 3286static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
@@ -3240,6 +3288,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3240 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, 3288 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3241 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, 3289 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3242 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, 3290 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3291 { .dma_req = -1 }
3243}; 3292};
3244 3293
3245static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { 3294static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
@@ -3248,6 +3297,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3248 .pa_end = 0x4809a1ff, 3297 .pa_end = 0x4809a1ff,
3249 .flags = ADDR_TYPE_RT 3298 .flags = ADDR_TYPE_RT
3250 }, 3299 },
3300 { }
3251}; 3301};
3252 3302
3253/* l4_per -> mcspi2 */ 3303/* l4_per -> mcspi2 */
@@ -3256,7 +3306,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3256 .slave = &omap44xx_mcspi2_hwmod, 3306 .slave = &omap44xx_mcspi2_hwmod,
3257 .clk = "l4_div_ck", 3307 .clk = "l4_div_ck",
3258 .addr = omap44xx_mcspi2_addrs, 3308 .addr = omap44xx_mcspi2_addrs,
3259 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3260 .user = OCP_USER_MPU | OCP_USER_SDMA, 3309 .user = OCP_USER_MPU | OCP_USER_SDMA,
3261}; 3310};
3262 3311
@@ -3274,9 +3323,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3274 .name = "mcspi2", 3323 .name = "mcspi2",
3275 .class = &omap44xx_mcspi_hwmod_class, 3324 .class = &omap44xx_mcspi_hwmod_class,
3276 .mpu_irqs = omap44xx_mcspi2_irqs, 3325 .mpu_irqs = omap44xx_mcspi2_irqs,
3277 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3278 .sdma_reqs = omap44xx_mcspi2_sdma_reqs, 3326 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3279 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3280 .main_clk = "mcspi2_fck", 3327 .main_clk = "mcspi2_fck",
3281 .prcm = { 3328 .prcm = {
3282 .omap4 = { 3329 .omap4 = {
@@ -3293,6 +3340,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3293static struct omap_hwmod omap44xx_mcspi3_hwmod; 3340static struct omap_hwmod omap44xx_mcspi3_hwmod;
3294static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { 3341static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3295 { .irq = 91 + OMAP44XX_IRQ_GIC_START }, 3342 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3343 { .irq = -1 }
3296}; 3344};
3297 3345
3298static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { 3346static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
@@ -3300,6 +3348,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3300 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, 3348 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3301 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, 3349 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3302 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, 3350 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3351 { .dma_req = -1 }
3303}; 3352};
3304 3353
3305static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { 3354static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
@@ -3308,6 +3357,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3308 .pa_end = 0x480b81ff, 3357 .pa_end = 0x480b81ff,
3309 .flags = ADDR_TYPE_RT 3358 .flags = ADDR_TYPE_RT
3310 }, 3359 },
3360 { }
3311}; 3361};
3312 3362
3313/* l4_per -> mcspi3 */ 3363/* l4_per -> mcspi3 */
@@ -3316,7 +3366,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3316 .slave = &omap44xx_mcspi3_hwmod, 3366 .slave = &omap44xx_mcspi3_hwmod,
3317 .clk = "l4_div_ck", 3367 .clk = "l4_div_ck",
3318 .addr = omap44xx_mcspi3_addrs, 3368 .addr = omap44xx_mcspi3_addrs,
3319 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3320 .user = OCP_USER_MPU | OCP_USER_SDMA, 3369 .user = OCP_USER_MPU | OCP_USER_SDMA,
3321}; 3370};
3322 3371
@@ -3334,9 +3383,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3334 .name = "mcspi3", 3383 .name = "mcspi3",
3335 .class = &omap44xx_mcspi_hwmod_class, 3384 .class = &omap44xx_mcspi_hwmod_class,
3336 .mpu_irqs = omap44xx_mcspi3_irqs, 3385 .mpu_irqs = omap44xx_mcspi3_irqs,
3337 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3338 .sdma_reqs = omap44xx_mcspi3_sdma_reqs, 3386 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3339 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3340 .main_clk = "mcspi3_fck", 3387 .main_clk = "mcspi3_fck",
3341 .prcm = { 3388 .prcm = {
3342 .omap4 = { 3389 .omap4 = {
@@ -3353,11 +3400,13 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3353static struct omap_hwmod omap44xx_mcspi4_hwmod; 3400static struct omap_hwmod omap44xx_mcspi4_hwmod;
3354static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { 3401static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3355 { .irq = 48 + OMAP44XX_IRQ_GIC_START }, 3402 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3403 { .irq = -1 }
3356}; 3404};
3357 3405
3358static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { 3406static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3359 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, 3407 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3360 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, 3408 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3409 { .dma_req = -1 }
3361}; 3410};
3362 3411
3363static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { 3412static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
@@ -3366,6 +3415,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3366 .pa_end = 0x480ba1ff, 3415 .pa_end = 0x480ba1ff,
3367 .flags = ADDR_TYPE_RT 3416 .flags = ADDR_TYPE_RT
3368 }, 3417 },
3418 { }
3369}; 3419};
3370 3420
3371/* l4_per -> mcspi4 */ 3421/* l4_per -> mcspi4 */
@@ -3374,7 +3424,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3374 .slave = &omap44xx_mcspi4_hwmod, 3424 .slave = &omap44xx_mcspi4_hwmod,
3375 .clk = "l4_div_ck", 3425 .clk = "l4_div_ck",
3376 .addr = omap44xx_mcspi4_addrs, 3426 .addr = omap44xx_mcspi4_addrs,
3377 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3378 .user = OCP_USER_MPU | OCP_USER_SDMA, 3427 .user = OCP_USER_MPU | OCP_USER_SDMA,
3379}; 3428};
3380 3429
@@ -3392,9 +3441,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3392 .name = "mcspi4", 3441 .name = "mcspi4",
3393 .class = &omap44xx_mcspi_hwmod_class, 3442 .class = &omap44xx_mcspi_hwmod_class,
3394 .mpu_irqs = omap44xx_mcspi4_irqs, 3443 .mpu_irqs = omap44xx_mcspi4_irqs,
3395 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3396 .sdma_reqs = omap44xx_mcspi4_sdma_reqs, 3444 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3397 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3398 .main_clk = "mcspi4_fck", 3445 .main_clk = "mcspi4_fck",
3399 .prcm = { 3446 .prcm = {
3400 .omap4 = { 3447 .omap4 = {
@@ -3420,7 +3467,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3420 SYSC_HAS_SOFTRESET), 3467 SYSC_HAS_SOFTRESET),
3421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3468 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3422 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 3469 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3423 MSTANDBY_SMART), 3470 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3424 .sysc_fields = &omap_hwmod_sysc_type2, 3471 .sysc_fields = &omap_hwmod_sysc_type2,
3425}; 3472};
3426 3473
@@ -3430,14 +3477,15 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3430}; 3477};
3431 3478
3432/* mmc1 */ 3479/* mmc1 */
3433
3434static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { 3480static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3435 { .irq = 83 + OMAP44XX_IRQ_GIC_START }, 3481 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3482 { .irq = -1 }
3436}; 3483};
3437 3484
3438static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { 3485static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3439 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, 3486 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3440 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, 3487 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3488 { .dma_req = -1 }
3441}; 3489};
3442 3490
3443/* mmc1 master ports */ 3491/* mmc1 master ports */
@@ -3451,6 +3499,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3451 .pa_end = 0x4809c3ff, 3499 .pa_end = 0x4809c3ff,
3452 .flags = ADDR_TYPE_RT 3500 .flags = ADDR_TYPE_RT
3453 }, 3501 },
3502 { }
3454}; 3503};
3455 3504
3456/* l4_per -> mmc1 */ 3505/* l4_per -> mmc1 */
@@ -3459,7 +3508,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3459 .slave = &omap44xx_mmc1_hwmod, 3508 .slave = &omap44xx_mmc1_hwmod,
3460 .clk = "l4_div_ck", 3509 .clk = "l4_div_ck",
3461 .addr = omap44xx_mmc1_addrs, 3510 .addr = omap44xx_mmc1_addrs,
3462 .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
3463 .user = OCP_USER_MPU | OCP_USER_SDMA, 3511 .user = OCP_USER_MPU | OCP_USER_SDMA,
3464}; 3512};
3465 3513
@@ -3477,11 +3525,9 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3477 .name = "mmc1", 3525 .name = "mmc1",
3478 .class = &omap44xx_mmc_hwmod_class, 3526 .class = &omap44xx_mmc_hwmod_class,
3479 .mpu_irqs = omap44xx_mmc1_irqs, 3527 .mpu_irqs = omap44xx_mmc1_irqs,
3480 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
3481 .sdma_reqs = omap44xx_mmc1_sdma_reqs, 3528 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3482 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3483 .main_clk = "mmc1_fck", 3529 .main_clk = "mmc1_fck",
3484 .prcm = { 3530 .prcm = {
3485 .omap4 = { 3531 .omap4 = {
3486 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 3532 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3487 }, 3533 },
@@ -3497,11 +3543,13 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3497/* mmc2 */ 3543/* mmc2 */
3498static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { 3544static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3499 { .irq = 86 + OMAP44XX_IRQ_GIC_START }, 3545 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3546 { .irq = -1 }
3500}; 3547};
3501 3548
3502static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { 3549static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3503 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, 3550 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3504 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, 3551 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3552 { .dma_req = -1 }
3505}; 3553};
3506 3554
3507/* mmc2 master ports */ 3555/* mmc2 master ports */
@@ -3515,6 +3563,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3515 .pa_end = 0x480b43ff, 3563 .pa_end = 0x480b43ff,
3516 .flags = ADDR_TYPE_RT 3564 .flags = ADDR_TYPE_RT
3517 }, 3565 },
3566 { }
3518}; 3567};
3519 3568
3520/* l4_per -> mmc2 */ 3569/* l4_per -> mmc2 */
@@ -3523,7 +3572,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3523 .slave = &omap44xx_mmc2_hwmod, 3572 .slave = &omap44xx_mmc2_hwmod,
3524 .clk = "l4_div_ck", 3573 .clk = "l4_div_ck",
3525 .addr = omap44xx_mmc2_addrs, 3574 .addr = omap44xx_mmc2_addrs,
3526 .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
3527 .user = OCP_USER_MPU | OCP_USER_SDMA, 3575 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528}; 3576};
3529 3577
@@ -3536,11 +3584,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
3536 .name = "mmc2", 3584 .name = "mmc2",
3537 .class = &omap44xx_mmc_hwmod_class, 3585 .class = &omap44xx_mmc_hwmod_class,
3538 .mpu_irqs = omap44xx_mmc2_irqs, 3586 .mpu_irqs = omap44xx_mmc2_irqs,
3539 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
3540 .sdma_reqs = omap44xx_mmc2_sdma_reqs, 3587 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3541 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3542 .main_clk = "mmc2_fck", 3588 .main_clk = "mmc2_fck",
3543 .prcm = { 3589 .prcm = {
3544 .omap4 = { 3590 .omap4 = {
3545 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 3591 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3546 }, 3592 },
@@ -3556,11 +3602,13 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
3556static struct omap_hwmod omap44xx_mmc3_hwmod; 3602static struct omap_hwmod omap44xx_mmc3_hwmod;
3557static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { 3603static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3558 { .irq = 94 + OMAP44XX_IRQ_GIC_START }, 3604 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3605 { .irq = -1 }
3559}; 3606};
3560 3607
3561static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { 3608static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3562 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, 3609 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3563 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, 3610 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3611 { .dma_req = -1 }
3564}; 3612};
3565 3613
3566static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { 3614static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
@@ -3569,6 +3617,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3569 .pa_end = 0x480ad3ff, 3617 .pa_end = 0x480ad3ff,
3570 .flags = ADDR_TYPE_RT 3618 .flags = ADDR_TYPE_RT
3571 }, 3619 },
3620 { }
3572}; 3621};
3573 3622
3574/* l4_per -> mmc3 */ 3623/* l4_per -> mmc3 */
@@ -3577,7 +3626,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3577 .slave = &omap44xx_mmc3_hwmod, 3626 .slave = &omap44xx_mmc3_hwmod,
3578 .clk = "l4_div_ck", 3627 .clk = "l4_div_ck",
3579 .addr = omap44xx_mmc3_addrs, 3628 .addr = omap44xx_mmc3_addrs,
3580 .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
3581 .user = OCP_USER_MPU | OCP_USER_SDMA, 3629 .user = OCP_USER_MPU | OCP_USER_SDMA,
3582}; 3630};
3583 3631
@@ -3590,11 +3638,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
3590 .name = "mmc3", 3638 .name = "mmc3",
3591 .class = &omap44xx_mmc_hwmod_class, 3639 .class = &omap44xx_mmc_hwmod_class,
3592 .mpu_irqs = omap44xx_mmc3_irqs, 3640 .mpu_irqs = omap44xx_mmc3_irqs,
3593 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
3594 .sdma_reqs = omap44xx_mmc3_sdma_reqs, 3641 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3595 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3596 .main_clk = "mmc3_fck", 3642 .main_clk = "mmc3_fck",
3597 .prcm = { 3643 .prcm = {
3598 .omap4 = { 3644 .omap4 = {
3599 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, 3645 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3600 }, 3646 },
@@ -3608,11 +3654,13 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
3608static struct omap_hwmod omap44xx_mmc4_hwmod; 3654static struct omap_hwmod omap44xx_mmc4_hwmod;
3609static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { 3655static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3610 { .irq = 96 + OMAP44XX_IRQ_GIC_START }, 3656 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3657 { .irq = -1 }
3611}; 3658};
3612 3659
3613static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { 3660static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3614 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, 3661 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3615 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, 3662 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3663 { .dma_req = -1 }
3616}; 3664};
3617 3665
3618static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { 3666static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
@@ -3621,6 +3669,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3621 .pa_end = 0x480d13ff, 3669 .pa_end = 0x480d13ff,
3622 .flags = ADDR_TYPE_RT 3670 .flags = ADDR_TYPE_RT
3623 }, 3671 },
3672 { }
3624}; 3673};
3625 3674
3626/* l4_per -> mmc4 */ 3675/* l4_per -> mmc4 */
@@ -3629,7 +3678,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3629 .slave = &omap44xx_mmc4_hwmod, 3678 .slave = &omap44xx_mmc4_hwmod,
3630 .clk = "l4_div_ck", 3679 .clk = "l4_div_ck",
3631 .addr = omap44xx_mmc4_addrs, 3680 .addr = omap44xx_mmc4_addrs,
3632 .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
3633 .user = OCP_USER_MPU | OCP_USER_SDMA, 3681 .user = OCP_USER_MPU | OCP_USER_SDMA,
3634}; 3682};
3635 3683
@@ -3642,11 +3690,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
3642 .name = "mmc4", 3690 .name = "mmc4",
3643 .class = &omap44xx_mmc_hwmod_class, 3691 .class = &omap44xx_mmc_hwmod_class,
3644 .mpu_irqs = omap44xx_mmc4_irqs, 3692 .mpu_irqs = omap44xx_mmc4_irqs,
3645 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs), 3693
3646 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 3694 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3647 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3648 .main_clk = "mmc4_fck", 3695 .main_clk = "mmc4_fck",
3649 .prcm = { 3696 .prcm = {
3650 .omap4 = { 3697 .omap4 = {
3651 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, 3698 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3652 }, 3699 },
@@ -3660,11 +3707,13 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
3660static struct omap_hwmod omap44xx_mmc5_hwmod; 3707static struct omap_hwmod omap44xx_mmc5_hwmod;
3661static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { 3708static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3662 { .irq = 59 + OMAP44XX_IRQ_GIC_START }, 3709 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3710 { .irq = -1 }
3663}; 3711};
3664 3712
3665static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { 3713static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3666 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, 3714 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3667 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, 3715 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3716 { .dma_req = -1 }
3668}; 3717};
3669 3718
3670static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { 3719static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
@@ -3673,6 +3722,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3673 .pa_end = 0x480d53ff, 3722 .pa_end = 0x480d53ff,
3674 .flags = ADDR_TYPE_RT 3723 .flags = ADDR_TYPE_RT
3675 }, 3724 },
3725 { }
3676}; 3726};
3677 3727
3678/* l4_per -> mmc5 */ 3728/* l4_per -> mmc5 */
@@ -3681,7 +3731,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3681 .slave = &omap44xx_mmc5_hwmod, 3731 .slave = &omap44xx_mmc5_hwmod,
3682 .clk = "l4_div_ck", 3732 .clk = "l4_div_ck",
3683 .addr = omap44xx_mmc5_addrs, 3733 .addr = omap44xx_mmc5_addrs,
3684 .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
3685 .user = OCP_USER_MPU | OCP_USER_SDMA, 3734 .user = OCP_USER_MPU | OCP_USER_SDMA,
3686}; 3735};
3687 3736
@@ -3694,11 +3743,9 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
3694 .name = "mmc5", 3743 .name = "mmc5",
3695 .class = &omap44xx_mmc_hwmod_class, 3744 .class = &omap44xx_mmc_hwmod_class,
3696 .mpu_irqs = omap44xx_mmc5_irqs, 3745 .mpu_irqs = omap44xx_mmc5_irqs,
3697 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
3698 .sdma_reqs = omap44xx_mmc5_sdma_reqs, 3746 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3699 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3700 .main_clk = "mmc5_fck", 3747 .main_clk = "mmc5_fck",
3701 .prcm = { 3748 .prcm = {
3702 .omap4 = { 3749 .omap4 = {
3703 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, 3750 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3704 }, 3751 },
@@ -3722,6 +3769,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3722 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, 3769 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3723 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, 3770 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3724 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, 3771 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3772 { .irq = -1 }
3725}; 3773};
3726 3774
3727/* mpu master ports */ 3775/* mpu master ports */
@@ -3734,9 +3782,8 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3734static struct omap_hwmod omap44xx_mpu_hwmod = { 3782static struct omap_hwmod omap44xx_mpu_hwmod = {
3735 .name = "mpu", 3783 .name = "mpu",
3736 .class = &omap44xx_mpu_hwmod_class, 3784 .class = &omap44xx_mpu_hwmod_class,
3737 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 3785 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3738 .mpu_irqs = omap44xx_mpu_irqs, 3786 .mpu_irqs = omap44xx_mpu_irqs,
3739 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
3740 .main_clk = "dpll_mpu_m2_ck", 3787 .main_clk = "dpll_mpu_m2_ck",
3741 .prcm = { 3788 .prcm = {
3742 .omap4 = { 3789 .omap4 = {
@@ -3778,6 +3825,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3778static struct omap_hwmod omap44xx_smartreflex_core_hwmod; 3825static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3779static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { 3826static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3780 { .irq = 19 + OMAP44XX_IRQ_GIC_START }, 3827 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3828 { .irq = -1 }
3781}; 3829};
3782 3830
3783static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { 3831static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
@@ -3786,6 +3834,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3786 .pa_end = 0x4a0dd03f, 3834 .pa_end = 0x4a0dd03f,
3787 .flags = ADDR_TYPE_RT 3835 .flags = ADDR_TYPE_RT
3788 }, 3836 },
3837 { }
3789}; 3838};
3790 3839
3791/* l4_cfg -> smartreflex_core */ 3840/* l4_cfg -> smartreflex_core */
@@ -3794,7 +3843,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3794 .slave = &omap44xx_smartreflex_core_hwmod, 3843 .slave = &omap44xx_smartreflex_core_hwmod,
3795 .clk = "l4_div_ck", 3844 .clk = "l4_div_ck",
3796 .addr = omap44xx_smartreflex_core_addrs, 3845 .addr = omap44xx_smartreflex_core_addrs,
3797 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3798 .user = OCP_USER_MPU | OCP_USER_SDMA, 3846 .user = OCP_USER_MPU | OCP_USER_SDMA,
3799}; 3847};
3800 3848
@@ -3807,7 +3855,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3807 .name = "smartreflex_core", 3855 .name = "smartreflex_core",
3808 .class = &omap44xx_smartreflex_hwmod_class, 3856 .class = &omap44xx_smartreflex_hwmod_class,
3809 .mpu_irqs = omap44xx_smartreflex_core_irqs, 3857 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3810 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), 3858
3811 .main_clk = "smartreflex_core_fck", 3859 .main_clk = "smartreflex_core_fck",
3812 .vdd_name = "core", 3860 .vdd_name = "core",
3813 .prcm = { 3861 .prcm = {
@@ -3824,6 +3872,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3824static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; 3872static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3825static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { 3873static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3826 { .irq = 102 + OMAP44XX_IRQ_GIC_START }, 3874 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3875 { .irq = -1 }
3827}; 3876};
3828 3877
3829static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { 3878static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
@@ -3832,6 +3881,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3832 .pa_end = 0x4a0db03f, 3881 .pa_end = 0x4a0db03f,
3833 .flags = ADDR_TYPE_RT 3882 .flags = ADDR_TYPE_RT
3834 }, 3883 },
3884 { }
3835}; 3885};
3836 3886
3837/* l4_cfg -> smartreflex_iva */ 3887/* l4_cfg -> smartreflex_iva */
@@ -3840,7 +3890,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3840 .slave = &omap44xx_smartreflex_iva_hwmod, 3890 .slave = &omap44xx_smartreflex_iva_hwmod,
3841 .clk = "l4_div_ck", 3891 .clk = "l4_div_ck",
3842 .addr = omap44xx_smartreflex_iva_addrs, 3892 .addr = omap44xx_smartreflex_iva_addrs,
3843 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3844 .user = OCP_USER_MPU | OCP_USER_SDMA, 3893 .user = OCP_USER_MPU | OCP_USER_SDMA,
3845}; 3894};
3846 3895
@@ -3853,7 +3902,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3853 .name = "smartreflex_iva", 3902 .name = "smartreflex_iva",
3854 .class = &omap44xx_smartreflex_hwmod_class, 3903 .class = &omap44xx_smartreflex_hwmod_class,
3855 .mpu_irqs = omap44xx_smartreflex_iva_irqs, 3904 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3856 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3857 .main_clk = "smartreflex_iva_fck", 3905 .main_clk = "smartreflex_iva_fck",
3858 .vdd_name = "iva", 3906 .vdd_name = "iva",
3859 .prcm = { 3907 .prcm = {
@@ -3870,6 +3918,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3870static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; 3918static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3871static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { 3919static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3872 { .irq = 18 + OMAP44XX_IRQ_GIC_START }, 3920 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3921 { .irq = -1 }
3873}; 3922};
3874 3923
3875static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { 3924static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
@@ -3878,6 +3927,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3878 .pa_end = 0x4a0d903f, 3927 .pa_end = 0x4a0d903f,
3879 .flags = ADDR_TYPE_RT 3928 .flags = ADDR_TYPE_RT
3880 }, 3929 },
3930 { }
3881}; 3931};
3882 3932
3883/* l4_cfg -> smartreflex_mpu */ 3933/* l4_cfg -> smartreflex_mpu */
@@ -3886,7 +3936,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3886 .slave = &omap44xx_smartreflex_mpu_hwmod, 3936 .slave = &omap44xx_smartreflex_mpu_hwmod,
3887 .clk = "l4_div_ck", 3937 .clk = "l4_div_ck",
3888 .addr = omap44xx_smartreflex_mpu_addrs, 3938 .addr = omap44xx_smartreflex_mpu_addrs,
3889 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3890 .user = OCP_USER_MPU | OCP_USER_SDMA, 3939 .user = OCP_USER_MPU | OCP_USER_SDMA,
3891}; 3940};
3892 3941
@@ -3899,7 +3948,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3899 .name = "smartreflex_mpu", 3948 .name = "smartreflex_mpu",
3900 .class = &omap44xx_smartreflex_hwmod_class, 3949 .class = &omap44xx_smartreflex_hwmod_class,
3901 .mpu_irqs = omap44xx_smartreflex_mpu_irqs, 3950 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3902 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3903 .main_clk = "smartreflex_mpu_fck", 3951 .main_clk = "smartreflex_mpu_fck",
3904 .vdd_name = "mpu", 3952 .vdd_name = "mpu",
3905 .prcm = { 3953 .prcm = {
@@ -3943,6 +3991,7 @@ static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3943 .pa_end = 0x4a0f6fff, 3991 .pa_end = 0x4a0f6fff,
3944 .flags = ADDR_TYPE_RT 3992 .flags = ADDR_TYPE_RT
3945 }, 3993 },
3994 { }
3946}; 3995};
3947 3996
3948/* l4_cfg -> spinlock */ 3997/* l4_cfg -> spinlock */
@@ -3951,7 +4000,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3951 .slave = &omap44xx_spinlock_hwmod, 4000 .slave = &omap44xx_spinlock_hwmod,
3952 .clk = "l4_div_ck", 4001 .clk = "l4_div_ck",
3953 .addr = omap44xx_spinlock_addrs, 4002 .addr = omap44xx_spinlock_addrs,
3954 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
3955 .user = OCP_USER_MPU | OCP_USER_SDMA, 4003 .user = OCP_USER_MPU | OCP_USER_SDMA,
3956}; 4004};
3957 4005
@@ -4015,6 +4063,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4015static struct omap_hwmod omap44xx_timer1_hwmod; 4063static struct omap_hwmod omap44xx_timer1_hwmod;
4016static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { 4064static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4017 { .irq = 37 + OMAP44XX_IRQ_GIC_START }, 4065 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4066 { .irq = -1 }
4018}; 4067};
4019 4068
4020static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { 4069static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
@@ -4023,6 +4072,7 @@ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4023 .pa_end = 0x4a31807f, 4072 .pa_end = 0x4a31807f,
4024 .flags = ADDR_TYPE_RT 4073 .flags = ADDR_TYPE_RT
4025 }, 4074 },
4075 { }
4026}; 4076};
4027 4077
4028/* l4_wkup -> timer1 */ 4078/* l4_wkup -> timer1 */
@@ -4031,7 +4081,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4031 .slave = &omap44xx_timer1_hwmod, 4081 .slave = &omap44xx_timer1_hwmod,
4032 .clk = "l4_wkup_clk_mux_ck", 4082 .clk = "l4_wkup_clk_mux_ck",
4033 .addr = omap44xx_timer1_addrs, 4083 .addr = omap44xx_timer1_addrs,
4034 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
4035 .user = OCP_USER_MPU | OCP_USER_SDMA, 4084 .user = OCP_USER_MPU | OCP_USER_SDMA,
4036}; 4085};
4037 4086
@@ -4044,7 +4093,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
4044 .name = "timer1", 4093 .name = "timer1",
4045 .class = &omap44xx_timer_1ms_hwmod_class, 4094 .class = &omap44xx_timer_1ms_hwmod_class,
4046 .mpu_irqs = omap44xx_timer1_irqs, 4095 .mpu_irqs = omap44xx_timer1_irqs,
4047 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
4048 .main_clk = "timer1_fck", 4096 .main_clk = "timer1_fck",
4049 .prcm = { 4097 .prcm = {
4050 .omap4 = { 4098 .omap4 = {
@@ -4060,6 +4108,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
4060static struct omap_hwmod omap44xx_timer2_hwmod; 4108static struct omap_hwmod omap44xx_timer2_hwmod;
4061static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { 4109static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4062 { .irq = 38 + OMAP44XX_IRQ_GIC_START }, 4110 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4111 { .irq = -1 }
4063}; 4112};
4064 4113
4065static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { 4114static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
@@ -4068,6 +4117,7 @@ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4068 .pa_end = 0x4803207f, 4117 .pa_end = 0x4803207f,
4069 .flags = ADDR_TYPE_RT 4118 .flags = ADDR_TYPE_RT
4070 }, 4119 },
4120 { }
4071}; 4121};
4072 4122
4073/* l4_per -> timer2 */ 4123/* l4_per -> timer2 */
@@ -4076,7 +4126,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4076 .slave = &omap44xx_timer2_hwmod, 4126 .slave = &omap44xx_timer2_hwmod,
4077 .clk = "l4_div_ck", 4127 .clk = "l4_div_ck",
4078 .addr = omap44xx_timer2_addrs, 4128 .addr = omap44xx_timer2_addrs,
4079 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
4080 .user = OCP_USER_MPU | OCP_USER_SDMA, 4129 .user = OCP_USER_MPU | OCP_USER_SDMA,
4081}; 4130};
4082 4131
@@ -4089,7 +4138,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
4089 .name = "timer2", 4138 .name = "timer2",
4090 .class = &omap44xx_timer_1ms_hwmod_class, 4139 .class = &omap44xx_timer_1ms_hwmod_class,
4091 .mpu_irqs = omap44xx_timer2_irqs, 4140 .mpu_irqs = omap44xx_timer2_irqs,
4092 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
4093 .main_clk = "timer2_fck", 4141 .main_clk = "timer2_fck",
4094 .prcm = { 4142 .prcm = {
4095 .omap4 = { 4143 .omap4 = {
@@ -4105,6 +4153,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
4105static struct omap_hwmod omap44xx_timer3_hwmod; 4153static struct omap_hwmod omap44xx_timer3_hwmod;
4106static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { 4154static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4107 { .irq = 39 + OMAP44XX_IRQ_GIC_START }, 4155 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4156 { .irq = -1 }
4108}; 4157};
4109 4158
4110static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { 4159static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
@@ -4113,6 +4162,7 @@ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4113 .pa_end = 0x4803407f, 4162 .pa_end = 0x4803407f,
4114 .flags = ADDR_TYPE_RT 4163 .flags = ADDR_TYPE_RT
4115 }, 4164 },
4165 { }
4116}; 4166};
4117 4167
4118/* l4_per -> timer3 */ 4168/* l4_per -> timer3 */
@@ -4121,7 +4171,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4121 .slave = &omap44xx_timer3_hwmod, 4171 .slave = &omap44xx_timer3_hwmod,
4122 .clk = "l4_div_ck", 4172 .clk = "l4_div_ck",
4123 .addr = omap44xx_timer3_addrs, 4173 .addr = omap44xx_timer3_addrs,
4124 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
4125 .user = OCP_USER_MPU | OCP_USER_SDMA, 4174 .user = OCP_USER_MPU | OCP_USER_SDMA,
4126}; 4175};
4127 4176
@@ -4134,7 +4183,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
4134 .name = "timer3", 4183 .name = "timer3",
4135 .class = &omap44xx_timer_hwmod_class, 4184 .class = &omap44xx_timer_hwmod_class,
4136 .mpu_irqs = omap44xx_timer3_irqs, 4185 .mpu_irqs = omap44xx_timer3_irqs,
4137 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
4138 .main_clk = "timer3_fck", 4186 .main_clk = "timer3_fck",
4139 .prcm = { 4187 .prcm = {
4140 .omap4 = { 4188 .omap4 = {
@@ -4150,6 +4198,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
4150static struct omap_hwmod omap44xx_timer4_hwmod; 4198static struct omap_hwmod omap44xx_timer4_hwmod;
4151static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { 4199static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4152 { .irq = 40 + OMAP44XX_IRQ_GIC_START }, 4200 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4201 { .irq = -1 }
4153}; 4202};
4154 4203
4155static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { 4204static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
@@ -4158,6 +4207,7 @@ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4158 .pa_end = 0x4803607f, 4207 .pa_end = 0x4803607f,
4159 .flags = ADDR_TYPE_RT 4208 .flags = ADDR_TYPE_RT
4160 }, 4209 },
4210 { }
4161}; 4211};
4162 4212
4163/* l4_per -> timer4 */ 4213/* l4_per -> timer4 */
@@ -4166,7 +4216,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4166 .slave = &omap44xx_timer4_hwmod, 4216 .slave = &omap44xx_timer4_hwmod,
4167 .clk = "l4_div_ck", 4217 .clk = "l4_div_ck",
4168 .addr = omap44xx_timer4_addrs, 4218 .addr = omap44xx_timer4_addrs,
4169 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
4170 .user = OCP_USER_MPU | OCP_USER_SDMA, 4219 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171}; 4220};
4172 4221
@@ -4179,7 +4228,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
4179 .name = "timer4", 4228 .name = "timer4",
4180 .class = &omap44xx_timer_hwmod_class, 4229 .class = &omap44xx_timer_hwmod_class,
4181 .mpu_irqs = omap44xx_timer4_irqs, 4230 .mpu_irqs = omap44xx_timer4_irqs,
4182 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
4183 .main_clk = "timer4_fck", 4231 .main_clk = "timer4_fck",
4184 .prcm = { 4232 .prcm = {
4185 .omap4 = { 4233 .omap4 = {
@@ -4195,6 +4243,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
4195static struct omap_hwmod omap44xx_timer5_hwmod; 4243static struct omap_hwmod omap44xx_timer5_hwmod;
4196static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { 4244static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4197 { .irq = 41 + OMAP44XX_IRQ_GIC_START }, 4245 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4246 { .irq = -1 }
4198}; 4247};
4199 4248
4200static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { 4249static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
@@ -4203,6 +4252,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4203 .pa_end = 0x4013807f, 4252 .pa_end = 0x4013807f,
4204 .flags = ADDR_TYPE_RT 4253 .flags = ADDR_TYPE_RT
4205 }, 4254 },
4255 { }
4206}; 4256};
4207 4257
4208/* l4_abe -> timer5 */ 4258/* l4_abe -> timer5 */
@@ -4211,7 +4261,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4211 .slave = &omap44xx_timer5_hwmod, 4261 .slave = &omap44xx_timer5_hwmod,
4212 .clk = "ocp_abe_iclk", 4262 .clk = "ocp_abe_iclk",
4213 .addr = omap44xx_timer5_addrs, 4263 .addr = omap44xx_timer5_addrs,
4214 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
4215 .user = OCP_USER_MPU, 4264 .user = OCP_USER_MPU,
4216}; 4265};
4217 4266
@@ -4221,6 +4270,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4221 .pa_end = 0x4903807f, 4270 .pa_end = 0x4903807f,
4222 .flags = ADDR_TYPE_RT 4271 .flags = ADDR_TYPE_RT
4223 }, 4272 },
4273 { }
4224}; 4274};
4225 4275
4226/* l4_abe -> timer5 (dma) */ 4276/* l4_abe -> timer5 (dma) */
@@ -4229,7 +4279,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4229 .slave = &omap44xx_timer5_hwmod, 4279 .slave = &omap44xx_timer5_hwmod,
4230 .clk = "ocp_abe_iclk", 4280 .clk = "ocp_abe_iclk",
4231 .addr = omap44xx_timer5_dma_addrs, 4281 .addr = omap44xx_timer5_dma_addrs,
4232 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4233 .user = OCP_USER_SDMA, 4282 .user = OCP_USER_SDMA,
4234}; 4283};
4235 4284
@@ -4243,7 +4292,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
4243 .name = "timer5", 4292 .name = "timer5",
4244 .class = &omap44xx_timer_hwmod_class, 4293 .class = &omap44xx_timer_hwmod_class,
4245 .mpu_irqs = omap44xx_timer5_irqs, 4294 .mpu_irqs = omap44xx_timer5_irqs,
4246 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
4247 .main_clk = "timer5_fck", 4295 .main_clk = "timer5_fck",
4248 .prcm = { 4296 .prcm = {
4249 .omap4 = { 4297 .omap4 = {
@@ -4259,6 +4307,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
4259static struct omap_hwmod omap44xx_timer6_hwmod; 4307static struct omap_hwmod omap44xx_timer6_hwmod;
4260static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { 4308static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4261 { .irq = 42 + OMAP44XX_IRQ_GIC_START }, 4309 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4310 { .irq = -1 }
4262}; 4311};
4263 4312
4264static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { 4313static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
@@ -4267,6 +4316,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4267 .pa_end = 0x4013a07f, 4316 .pa_end = 0x4013a07f,
4268 .flags = ADDR_TYPE_RT 4317 .flags = ADDR_TYPE_RT
4269 }, 4318 },
4319 { }
4270}; 4320};
4271 4321
4272/* l4_abe -> timer6 */ 4322/* l4_abe -> timer6 */
@@ -4275,7 +4325,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4275 .slave = &omap44xx_timer6_hwmod, 4325 .slave = &omap44xx_timer6_hwmod,
4276 .clk = "ocp_abe_iclk", 4326 .clk = "ocp_abe_iclk",
4277 .addr = omap44xx_timer6_addrs, 4327 .addr = omap44xx_timer6_addrs,
4278 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
4279 .user = OCP_USER_MPU, 4328 .user = OCP_USER_MPU,
4280}; 4329};
4281 4330
@@ -4285,6 +4334,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4285 .pa_end = 0x4903a07f, 4334 .pa_end = 0x4903a07f,
4286 .flags = ADDR_TYPE_RT 4335 .flags = ADDR_TYPE_RT
4287 }, 4336 },
4337 { }
4288}; 4338};
4289 4339
4290/* l4_abe -> timer6 (dma) */ 4340/* l4_abe -> timer6 (dma) */
@@ -4293,7 +4343,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4293 .slave = &omap44xx_timer6_hwmod, 4343 .slave = &omap44xx_timer6_hwmod,
4294 .clk = "ocp_abe_iclk", 4344 .clk = "ocp_abe_iclk",
4295 .addr = omap44xx_timer6_dma_addrs, 4345 .addr = omap44xx_timer6_dma_addrs,
4296 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4297 .user = OCP_USER_SDMA, 4346 .user = OCP_USER_SDMA,
4298}; 4347};
4299 4348
@@ -4307,7 +4356,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
4307 .name = "timer6", 4356 .name = "timer6",
4308 .class = &omap44xx_timer_hwmod_class, 4357 .class = &omap44xx_timer_hwmod_class,
4309 .mpu_irqs = omap44xx_timer6_irqs, 4358 .mpu_irqs = omap44xx_timer6_irqs,
4310 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), 4359
4311 .main_clk = "timer6_fck", 4360 .main_clk = "timer6_fck",
4312 .prcm = { 4361 .prcm = {
4313 .omap4 = { 4362 .omap4 = {
@@ -4323,6 +4372,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
4323static struct omap_hwmod omap44xx_timer7_hwmod; 4372static struct omap_hwmod omap44xx_timer7_hwmod;
4324static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { 4373static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4325 { .irq = 43 + OMAP44XX_IRQ_GIC_START }, 4374 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4375 { .irq = -1 }
4326}; 4376};
4327 4377
4328static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { 4378static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
@@ -4331,6 +4381,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4331 .pa_end = 0x4013c07f, 4381 .pa_end = 0x4013c07f,
4332 .flags = ADDR_TYPE_RT 4382 .flags = ADDR_TYPE_RT
4333 }, 4383 },
4384 { }
4334}; 4385};
4335 4386
4336/* l4_abe -> timer7 */ 4387/* l4_abe -> timer7 */
@@ -4339,7 +4390,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4339 .slave = &omap44xx_timer7_hwmod, 4390 .slave = &omap44xx_timer7_hwmod,
4340 .clk = "ocp_abe_iclk", 4391 .clk = "ocp_abe_iclk",
4341 .addr = omap44xx_timer7_addrs, 4392 .addr = omap44xx_timer7_addrs,
4342 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
4343 .user = OCP_USER_MPU, 4393 .user = OCP_USER_MPU,
4344}; 4394};
4345 4395
@@ -4349,6 +4399,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4349 .pa_end = 0x4903c07f, 4399 .pa_end = 0x4903c07f,
4350 .flags = ADDR_TYPE_RT 4400 .flags = ADDR_TYPE_RT
4351 }, 4401 },
4402 { }
4352}; 4403};
4353 4404
4354/* l4_abe -> timer7 (dma) */ 4405/* l4_abe -> timer7 (dma) */
@@ -4357,7 +4408,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4357 .slave = &omap44xx_timer7_hwmod, 4408 .slave = &omap44xx_timer7_hwmod,
4358 .clk = "ocp_abe_iclk", 4409 .clk = "ocp_abe_iclk",
4359 .addr = omap44xx_timer7_dma_addrs, 4410 .addr = omap44xx_timer7_dma_addrs,
4360 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4361 .user = OCP_USER_SDMA, 4411 .user = OCP_USER_SDMA,
4362}; 4412};
4363 4413
@@ -4371,7 +4421,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
4371 .name = "timer7", 4421 .name = "timer7",
4372 .class = &omap44xx_timer_hwmod_class, 4422 .class = &omap44xx_timer_hwmod_class,
4373 .mpu_irqs = omap44xx_timer7_irqs, 4423 .mpu_irqs = omap44xx_timer7_irqs,
4374 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
4375 .main_clk = "timer7_fck", 4424 .main_clk = "timer7_fck",
4376 .prcm = { 4425 .prcm = {
4377 .omap4 = { 4426 .omap4 = {
@@ -4387,6 +4436,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
4387static struct omap_hwmod omap44xx_timer8_hwmod; 4436static struct omap_hwmod omap44xx_timer8_hwmod;
4388static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { 4437static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4389 { .irq = 44 + OMAP44XX_IRQ_GIC_START }, 4438 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4439 { .irq = -1 }
4390}; 4440};
4391 4441
4392static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { 4442static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
@@ -4395,6 +4445,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4395 .pa_end = 0x4013e07f, 4445 .pa_end = 0x4013e07f,
4396 .flags = ADDR_TYPE_RT 4446 .flags = ADDR_TYPE_RT
4397 }, 4447 },
4448 { }
4398}; 4449};
4399 4450
4400/* l4_abe -> timer8 */ 4451/* l4_abe -> timer8 */
@@ -4403,7 +4454,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4403 .slave = &omap44xx_timer8_hwmod, 4454 .slave = &omap44xx_timer8_hwmod,
4404 .clk = "ocp_abe_iclk", 4455 .clk = "ocp_abe_iclk",
4405 .addr = omap44xx_timer8_addrs, 4456 .addr = omap44xx_timer8_addrs,
4406 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
4407 .user = OCP_USER_MPU, 4457 .user = OCP_USER_MPU,
4408}; 4458};
4409 4459
@@ -4413,6 +4463,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4413 .pa_end = 0x4903e07f, 4463 .pa_end = 0x4903e07f,
4414 .flags = ADDR_TYPE_RT 4464 .flags = ADDR_TYPE_RT
4415 }, 4465 },
4466 { }
4416}; 4467};
4417 4468
4418/* l4_abe -> timer8 (dma) */ 4469/* l4_abe -> timer8 (dma) */
@@ -4421,7 +4472,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4421 .slave = &omap44xx_timer8_hwmod, 4472 .slave = &omap44xx_timer8_hwmod,
4422 .clk = "ocp_abe_iclk", 4473 .clk = "ocp_abe_iclk",
4423 .addr = omap44xx_timer8_dma_addrs, 4474 .addr = omap44xx_timer8_dma_addrs,
4424 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4425 .user = OCP_USER_SDMA, 4475 .user = OCP_USER_SDMA,
4426}; 4476};
4427 4477
@@ -4435,7 +4485,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
4435 .name = "timer8", 4485 .name = "timer8",
4436 .class = &omap44xx_timer_hwmod_class, 4486 .class = &omap44xx_timer_hwmod_class,
4437 .mpu_irqs = omap44xx_timer8_irqs, 4487 .mpu_irqs = omap44xx_timer8_irqs,
4438 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
4439 .main_clk = "timer8_fck", 4488 .main_clk = "timer8_fck",
4440 .prcm = { 4489 .prcm = {
4441 .omap4 = { 4490 .omap4 = {
@@ -4451,6 +4500,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
4451static struct omap_hwmod omap44xx_timer9_hwmod; 4500static struct omap_hwmod omap44xx_timer9_hwmod;
4452static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { 4501static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4453 { .irq = 45 + OMAP44XX_IRQ_GIC_START }, 4502 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4503 { .irq = -1 }
4454}; 4504};
4455 4505
4456static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { 4506static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
@@ -4459,6 +4509,7 @@ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4459 .pa_end = 0x4803e07f, 4509 .pa_end = 0x4803e07f,
4460 .flags = ADDR_TYPE_RT 4510 .flags = ADDR_TYPE_RT
4461 }, 4511 },
4512 { }
4462}; 4513};
4463 4514
4464/* l4_per -> timer9 */ 4515/* l4_per -> timer9 */
@@ -4467,7 +4518,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4467 .slave = &omap44xx_timer9_hwmod, 4518 .slave = &omap44xx_timer9_hwmod,
4468 .clk = "l4_div_ck", 4519 .clk = "l4_div_ck",
4469 .addr = omap44xx_timer9_addrs, 4520 .addr = omap44xx_timer9_addrs,
4470 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
4471 .user = OCP_USER_MPU | OCP_USER_SDMA, 4521 .user = OCP_USER_MPU | OCP_USER_SDMA,
4472}; 4522};
4473 4523
@@ -4480,7 +4530,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
4480 .name = "timer9", 4530 .name = "timer9",
4481 .class = &omap44xx_timer_hwmod_class, 4531 .class = &omap44xx_timer_hwmod_class,
4482 .mpu_irqs = omap44xx_timer9_irqs, 4532 .mpu_irqs = omap44xx_timer9_irqs,
4483 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
4484 .main_clk = "timer9_fck", 4533 .main_clk = "timer9_fck",
4485 .prcm = { 4534 .prcm = {
4486 .omap4 = { 4535 .omap4 = {
@@ -4496,6 +4545,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
4496static struct omap_hwmod omap44xx_timer10_hwmod; 4545static struct omap_hwmod omap44xx_timer10_hwmod;
4497static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { 4546static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4498 { .irq = 46 + OMAP44XX_IRQ_GIC_START }, 4547 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4548 { .irq = -1 }
4499}; 4549};
4500 4550
4501static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { 4551static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
@@ -4504,6 +4554,7 @@ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4504 .pa_end = 0x4808607f, 4554 .pa_end = 0x4808607f,
4505 .flags = ADDR_TYPE_RT 4555 .flags = ADDR_TYPE_RT
4506 }, 4556 },
4557 { }
4507}; 4558};
4508 4559
4509/* l4_per -> timer10 */ 4560/* l4_per -> timer10 */
@@ -4512,7 +4563,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4512 .slave = &omap44xx_timer10_hwmod, 4563 .slave = &omap44xx_timer10_hwmod,
4513 .clk = "l4_div_ck", 4564 .clk = "l4_div_ck",
4514 .addr = omap44xx_timer10_addrs, 4565 .addr = omap44xx_timer10_addrs,
4515 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
4516 .user = OCP_USER_MPU | OCP_USER_SDMA, 4566 .user = OCP_USER_MPU | OCP_USER_SDMA,
4517}; 4567};
4518 4568
@@ -4525,7 +4575,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
4525 .name = "timer10", 4575 .name = "timer10",
4526 .class = &omap44xx_timer_1ms_hwmod_class, 4576 .class = &omap44xx_timer_1ms_hwmod_class,
4527 .mpu_irqs = omap44xx_timer10_irqs, 4577 .mpu_irqs = omap44xx_timer10_irqs,
4528 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
4529 .main_clk = "timer10_fck", 4578 .main_clk = "timer10_fck",
4530 .prcm = { 4579 .prcm = {
4531 .omap4 = { 4580 .omap4 = {
@@ -4541,6 +4590,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
4541static struct omap_hwmod omap44xx_timer11_hwmod; 4590static struct omap_hwmod omap44xx_timer11_hwmod;
4542static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { 4591static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4543 { .irq = 47 + OMAP44XX_IRQ_GIC_START }, 4592 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4593 { .irq = -1 }
4544}; 4594};
4545 4595
4546static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { 4596static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
@@ -4549,6 +4599,7 @@ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4549 .pa_end = 0x4808807f, 4599 .pa_end = 0x4808807f,
4550 .flags = ADDR_TYPE_RT 4600 .flags = ADDR_TYPE_RT
4551 }, 4601 },
4602 { }
4552}; 4603};
4553 4604
4554/* l4_per -> timer11 */ 4605/* l4_per -> timer11 */
@@ -4557,7 +4608,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4557 .slave = &omap44xx_timer11_hwmod, 4608 .slave = &omap44xx_timer11_hwmod,
4558 .clk = "l4_div_ck", 4609 .clk = "l4_div_ck",
4559 .addr = omap44xx_timer11_addrs, 4610 .addr = omap44xx_timer11_addrs,
4560 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
4561 .user = OCP_USER_MPU | OCP_USER_SDMA, 4611 .user = OCP_USER_MPU | OCP_USER_SDMA,
4562}; 4612};
4563 4613
@@ -4570,7 +4620,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
4570 .name = "timer11", 4620 .name = "timer11",
4571 .class = &omap44xx_timer_hwmod_class, 4621 .class = &omap44xx_timer_hwmod_class,
4572 .mpu_irqs = omap44xx_timer11_irqs, 4622 .mpu_irqs = omap44xx_timer11_irqs,
4573 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
4574 .main_clk = "timer11_fck", 4623 .main_clk = "timer11_fck",
4575 .prcm = { 4624 .prcm = {
4576 .omap4 = { 4625 .omap4 = {
@@ -4608,11 +4657,13 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4608static struct omap_hwmod omap44xx_uart1_hwmod; 4657static struct omap_hwmod omap44xx_uart1_hwmod;
4609static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { 4658static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4610 { .irq = 72 + OMAP44XX_IRQ_GIC_START }, 4659 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4660 { .irq = -1 }
4611}; 4661};
4612 4662
4613static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { 4663static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4614 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, 4664 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4615 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, 4665 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4666 { .dma_req = -1 }
4616}; 4667};
4617 4668
4618static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { 4669static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
@@ -4621,6 +4672,7 @@ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4621 .pa_end = 0x4806a0ff, 4672 .pa_end = 0x4806a0ff,
4622 .flags = ADDR_TYPE_RT 4673 .flags = ADDR_TYPE_RT
4623 }, 4674 },
4675 { }
4624}; 4676};
4625 4677
4626/* l4_per -> uart1 */ 4678/* l4_per -> uart1 */
@@ -4629,7 +4681,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4629 .slave = &omap44xx_uart1_hwmod, 4681 .slave = &omap44xx_uart1_hwmod,
4630 .clk = "l4_div_ck", 4682 .clk = "l4_div_ck",
4631 .addr = omap44xx_uart1_addrs, 4683 .addr = omap44xx_uart1_addrs,
4632 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
4633 .user = OCP_USER_MPU | OCP_USER_SDMA, 4684 .user = OCP_USER_MPU | OCP_USER_SDMA,
4634}; 4685};
4635 4686
@@ -4642,9 +4693,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
4642 .name = "uart1", 4693 .name = "uart1",
4643 .class = &omap44xx_uart_hwmod_class, 4694 .class = &omap44xx_uart_hwmod_class,
4644 .mpu_irqs = omap44xx_uart1_irqs, 4695 .mpu_irqs = omap44xx_uart1_irqs,
4645 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
4646 .sdma_reqs = omap44xx_uart1_sdma_reqs, 4696 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4647 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4648 .main_clk = "uart1_fck", 4697 .main_clk = "uart1_fck",
4649 .prcm = { 4698 .prcm = {
4650 .omap4 = { 4699 .omap4 = {
@@ -4660,11 +4709,13 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
4660static struct omap_hwmod omap44xx_uart2_hwmod; 4709static struct omap_hwmod omap44xx_uart2_hwmod;
4661static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { 4710static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4662 { .irq = 73 + OMAP44XX_IRQ_GIC_START }, 4711 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4712 { .irq = -1 }
4663}; 4713};
4664 4714
4665static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { 4715static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4666 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, 4716 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4667 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, 4717 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4718 { .dma_req = -1 }
4668}; 4719};
4669 4720
4670static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { 4721static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
@@ -4673,6 +4724,7 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4673 .pa_end = 0x4806c0ff, 4724 .pa_end = 0x4806c0ff,
4674 .flags = ADDR_TYPE_RT 4725 .flags = ADDR_TYPE_RT
4675 }, 4726 },
4727 { }
4676}; 4728};
4677 4729
4678/* l4_per -> uart2 */ 4730/* l4_per -> uart2 */
@@ -4681,7 +4733,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4681 .slave = &omap44xx_uart2_hwmod, 4733 .slave = &omap44xx_uart2_hwmod,
4682 .clk = "l4_div_ck", 4734 .clk = "l4_div_ck",
4683 .addr = omap44xx_uart2_addrs, 4735 .addr = omap44xx_uart2_addrs,
4684 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
4685 .user = OCP_USER_MPU | OCP_USER_SDMA, 4736 .user = OCP_USER_MPU | OCP_USER_SDMA,
4686}; 4737};
4687 4738
@@ -4694,9 +4745,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
4694 .name = "uart2", 4745 .name = "uart2",
4695 .class = &omap44xx_uart_hwmod_class, 4746 .class = &omap44xx_uart_hwmod_class,
4696 .mpu_irqs = omap44xx_uart2_irqs, 4747 .mpu_irqs = omap44xx_uart2_irqs,
4697 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
4698 .sdma_reqs = omap44xx_uart2_sdma_reqs, 4748 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4699 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4700 .main_clk = "uart2_fck", 4749 .main_clk = "uart2_fck",
4701 .prcm = { 4750 .prcm = {
4702 .omap4 = { 4751 .omap4 = {
@@ -4712,11 +4761,13 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
4712static struct omap_hwmod omap44xx_uart3_hwmod; 4761static struct omap_hwmod omap44xx_uart3_hwmod;
4713static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { 4762static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4714 { .irq = 74 + OMAP44XX_IRQ_GIC_START }, 4763 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4764 { .irq = -1 }
4715}; 4765};
4716 4766
4717static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { 4767static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4718 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, 4768 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4719 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, 4769 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4770 { .dma_req = -1 }
4720}; 4771};
4721 4772
4722static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { 4773static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
@@ -4725,6 +4776,7 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4725 .pa_end = 0x480200ff, 4776 .pa_end = 0x480200ff,
4726 .flags = ADDR_TYPE_RT 4777 .flags = ADDR_TYPE_RT
4727 }, 4778 },
4779 { }
4728}; 4780};
4729 4781
4730/* l4_per -> uart3 */ 4782/* l4_per -> uart3 */
@@ -4733,7 +4785,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4733 .slave = &omap44xx_uart3_hwmod, 4785 .slave = &omap44xx_uart3_hwmod,
4734 .clk = "l4_div_ck", 4786 .clk = "l4_div_ck",
4735 .addr = omap44xx_uart3_addrs, 4787 .addr = omap44xx_uart3_addrs,
4736 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
4737 .user = OCP_USER_MPU | OCP_USER_SDMA, 4788 .user = OCP_USER_MPU | OCP_USER_SDMA,
4738}; 4789};
4739 4790
@@ -4745,11 +4796,9 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4745static struct omap_hwmod omap44xx_uart3_hwmod = { 4796static struct omap_hwmod omap44xx_uart3_hwmod = {
4746 .name = "uart3", 4797 .name = "uart3",
4747 .class = &omap44xx_uart_hwmod_class, 4798 .class = &omap44xx_uart_hwmod_class,
4748 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 4799 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4749 .mpu_irqs = omap44xx_uart3_irqs, 4800 .mpu_irqs = omap44xx_uart3_irqs,
4750 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
4751 .sdma_reqs = omap44xx_uart3_sdma_reqs, 4801 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4752 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4753 .main_clk = "uart3_fck", 4802 .main_clk = "uart3_fck",
4754 .prcm = { 4803 .prcm = {
4755 .omap4 = { 4804 .omap4 = {
@@ -4765,11 +4814,13 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
4765static struct omap_hwmod omap44xx_uart4_hwmod; 4814static struct omap_hwmod omap44xx_uart4_hwmod;
4766static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { 4815static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4767 { .irq = 70 + OMAP44XX_IRQ_GIC_START }, 4816 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4817 { .irq = -1 }
4768}; 4818};
4769 4819
4770static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { 4820static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4771 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, 4821 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4772 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, 4822 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4823 { .dma_req = -1 }
4773}; 4824};
4774 4825
4775static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { 4826static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
@@ -4778,6 +4829,7 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4778 .pa_end = 0x4806e0ff, 4829 .pa_end = 0x4806e0ff,
4779 .flags = ADDR_TYPE_RT 4830 .flags = ADDR_TYPE_RT
4780 }, 4831 },
4832 { }
4781}; 4833};
4782 4834
4783/* l4_per -> uart4 */ 4835/* l4_per -> uart4 */
@@ -4786,7 +4838,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4786 .slave = &omap44xx_uart4_hwmod, 4838 .slave = &omap44xx_uart4_hwmod,
4787 .clk = "l4_div_ck", 4839 .clk = "l4_div_ck",
4788 .addr = omap44xx_uart4_addrs, 4840 .addr = omap44xx_uart4_addrs,
4789 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
4790 .user = OCP_USER_MPU | OCP_USER_SDMA, 4841 .user = OCP_USER_MPU | OCP_USER_SDMA,
4791}; 4842};
4792 4843
@@ -4799,9 +4850,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
4799 .name = "uart4", 4850 .name = "uart4",
4800 .class = &omap44xx_uart_hwmod_class, 4851 .class = &omap44xx_uart_hwmod_class,
4801 .mpu_irqs = omap44xx_uart4_irqs, 4852 .mpu_irqs = omap44xx_uart4_irqs,
4802 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
4803 .sdma_reqs = omap44xx_uart4_sdma_reqs, 4853 .sdma_reqs = omap44xx_uart4_sdma_reqs,
4804 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4805 .main_clk = "uart4_fck", 4854 .main_clk = "uart4_fck",
4806 .prcm = { 4855 .prcm = {
4807 .omap4 = { 4856 .omap4 = {
@@ -4832,14 +4881,15 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4832}; 4881};
4833 4882
4834static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { 4883static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4835 .name = "usb_otg_hs", 4884 .name = "usb_otg_hs",
4836 .sysc = &omap44xx_usb_otg_hs_sysc, 4885 .sysc = &omap44xx_usb_otg_hs_sysc,
4837}; 4886};
4838 4887
4839/* usb_otg_hs */ 4888/* usb_otg_hs */
4840static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { 4889static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4841 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, 4890 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4842 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, 4891 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4892 { .irq = -1 }
4843}; 4893};
4844 4894
4845/* usb_otg_hs master ports */ 4895/* usb_otg_hs master ports */
@@ -4853,6 +4903,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4853 .pa_end = 0x4a0ab003, 4903 .pa_end = 0x4a0ab003,
4854 .flags = ADDR_TYPE_RT 4904 .flags = ADDR_TYPE_RT
4855 }, 4905 },
4906 { }
4856}; 4907};
4857 4908
4858/* l4_cfg -> usb_otg_hs */ 4909/* l4_cfg -> usb_otg_hs */
@@ -4861,7 +4912,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4861 .slave = &omap44xx_usb_otg_hs_hwmod, 4912 .slave = &omap44xx_usb_otg_hs_hwmod,
4862 .clk = "l4_div_ck", 4913 .clk = "l4_div_ck",
4863 .addr = omap44xx_usb_otg_hs_addrs, 4914 .addr = omap44xx_usb_otg_hs_addrs,
4864 .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4865 .user = OCP_USER_MPU | OCP_USER_SDMA, 4915 .user = OCP_USER_MPU | OCP_USER_SDMA,
4866}; 4916};
4867 4917
@@ -4879,7 +4929,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4879 .class = &omap44xx_usb_otg_hs_hwmod_class, 4929 .class = &omap44xx_usb_otg_hs_hwmod_class,
4880 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 4930 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4881 .mpu_irqs = omap44xx_usb_otg_hs_irqs, 4931 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
4882 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4883 .main_clk = "usb_otg_hs_ick", 4932 .main_clk = "usb_otg_hs_ick",
4884 .prcm = { 4933 .prcm = {
4885 .omap4 = { 4934 .omap4 = {
@@ -4887,7 +4936,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4887 }, 4936 },
4888 }, 4937 },
4889 .opt_clks = usb_otg_hs_opt_clks, 4938 .opt_clks = usb_otg_hs_opt_clks,
4890 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), 4939 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4891 .slaves = omap44xx_usb_otg_hs_slaves, 4940 .slaves = omap44xx_usb_otg_hs_slaves,
4892 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), 4941 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4893 .masters = omap44xx_usb_otg_hs_masters, 4942 .masters = omap44xx_usb_otg_hs_masters,
@@ -4922,6 +4971,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4922static struct omap_hwmod omap44xx_wd_timer2_hwmod; 4971static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4923static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { 4972static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4924 { .irq = 80 + OMAP44XX_IRQ_GIC_START }, 4973 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4974 { .irq = -1 }
4925}; 4975};
4926 4976
4927static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { 4977static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
@@ -4930,6 +4980,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4930 .pa_end = 0x4a31407f, 4980 .pa_end = 0x4a31407f,
4931 .flags = ADDR_TYPE_RT 4981 .flags = ADDR_TYPE_RT
4932 }, 4982 },
4983 { }
4933}; 4984};
4934 4985
4935/* l4_wkup -> wd_timer2 */ 4986/* l4_wkup -> wd_timer2 */
@@ -4938,7 +4989,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4938 .slave = &omap44xx_wd_timer2_hwmod, 4989 .slave = &omap44xx_wd_timer2_hwmod,
4939 .clk = "l4_wkup_clk_mux_ck", 4990 .clk = "l4_wkup_clk_mux_ck",
4940 .addr = omap44xx_wd_timer2_addrs, 4991 .addr = omap44xx_wd_timer2_addrs,
4941 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4942 .user = OCP_USER_MPU | OCP_USER_SDMA, 4992 .user = OCP_USER_MPU | OCP_USER_SDMA,
4943}; 4993};
4944 4994
@@ -4951,7 +5001,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4951 .name = "wd_timer2", 5001 .name = "wd_timer2",
4952 .class = &omap44xx_wd_timer_hwmod_class, 5002 .class = &omap44xx_wd_timer_hwmod_class,
4953 .mpu_irqs = omap44xx_wd_timer2_irqs, 5003 .mpu_irqs = omap44xx_wd_timer2_irqs,
4954 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4955 .main_clk = "wd_timer2_fck", 5004 .main_clk = "wd_timer2_fck",
4956 .prcm = { 5005 .prcm = {
4957 .omap4 = { 5006 .omap4 = {
@@ -4967,6 +5016,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4967static struct omap_hwmod omap44xx_wd_timer3_hwmod; 5016static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4968static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { 5017static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4969 { .irq = 36 + OMAP44XX_IRQ_GIC_START }, 5018 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5019 { .irq = -1 }
4970}; 5020};
4971 5021
4972static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { 5022static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
@@ -4975,6 +5025,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4975 .pa_end = 0x4013007f, 5025 .pa_end = 0x4013007f,
4976 .flags = ADDR_TYPE_RT 5026 .flags = ADDR_TYPE_RT
4977 }, 5027 },
5028 { }
4978}; 5029};
4979 5030
4980/* l4_abe -> wd_timer3 */ 5031/* l4_abe -> wd_timer3 */
@@ -4983,7 +5034,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4983 .slave = &omap44xx_wd_timer3_hwmod, 5034 .slave = &omap44xx_wd_timer3_hwmod,
4984 .clk = "ocp_abe_iclk", 5035 .clk = "ocp_abe_iclk",
4985 .addr = omap44xx_wd_timer3_addrs, 5036 .addr = omap44xx_wd_timer3_addrs,
4986 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4987 .user = OCP_USER_MPU, 5037 .user = OCP_USER_MPU,
4988}; 5038};
4989 5039
@@ -4993,6 +5043,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4993 .pa_end = 0x4903007f, 5043 .pa_end = 0x4903007f,
4994 .flags = ADDR_TYPE_RT 5044 .flags = ADDR_TYPE_RT
4995 }, 5045 },
5046 { }
4996}; 5047};
4997 5048
4998/* l4_abe -> wd_timer3 (dma) */ 5049/* l4_abe -> wd_timer3 (dma) */
@@ -5001,7 +5052,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5001 .slave = &omap44xx_wd_timer3_hwmod, 5052 .slave = &omap44xx_wd_timer3_hwmod,
5002 .clk = "ocp_abe_iclk", 5053 .clk = "ocp_abe_iclk",
5003 .addr = omap44xx_wd_timer3_dma_addrs, 5054 .addr = omap44xx_wd_timer3_dma_addrs,
5004 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
5005 .user = OCP_USER_SDMA, 5055 .user = OCP_USER_SDMA,
5006}; 5056};
5007 5057
@@ -5015,7 +5065,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5015 .name = "wd_timer3", 5065 .name = "wd_timer3",
5016 .class = &omap44xx_wd_timer_hwmod_class, 5066 .class = &omap44xx_wd_timer_hwmod_class,
5017 .mpu_irqs = omap44xx_wd_timer3_irqs, 5067 .mpu_irqs = omap44xx_wd_timer3_irqs,
5018 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
5019 .main_clk = "wd_timer3_fck", 5068 .main_clk = "wd_timer3_fck",
5020 .prcm = { 5069 .prcm = {
5021 .omap4 = { 5070 .omap4 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 08a134243ecb..de832ebc93a9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, 49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
50}; 50};
51 51
52
53/*
54 * omap_hwmod class data
55 */
56
57struct omap_hwmod_class l3_hwmod_class = {
58 .name = "l3"
59};
60
61struct omap_hwmod_class l4_hwmod_class = {
62 .name = "l4"
63};
64
65struct omap_hwmod_class mpu_hwmod_class = {
66 .name = "mpu"
67};
68
69struct omap_hwmod_class iva_hwmod_class = {
70 .name = "iva"
71};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index c34e98bf1242..39a7c37f4587 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -1,10 +1,10 @@
1/* 1/*
2 * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations 2 * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
3 * 3 *
4 * Copyright (C) 2010 Nokia Corporation 4 * Copyright (C) 2010-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * Copyright (C) 2010 Texas Instruments, Inc. 7 * Copyright (C) 2010-2011 Texas Instruments, Inc.
8 * Benoît Cousson 8 * Benoît Cousson
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
@@ -16,10 +16,99 @@
16 16
17#include <plat/omap_hwmod.h> 17#include <plat/omap_hwmod.h>
18 18
19/* Common address space across OMAP2xxx */
20extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
21extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
22extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
23extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
24extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
25extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
26extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
27extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
28extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
29extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
30extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
31extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
32extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
33
34/* Common address space across OMAP2xxx/3xxx */
35extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
36extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
37extern struct omap_hwmod_addr_space omap2_dss_addrs[];
38extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
39extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
40extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
41extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
42extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
43extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
44extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
45extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
46extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
47extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
48extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
49extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
50extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
51
52/* Common IP block data across OMAP2xxx */
53extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
54extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
55
56/* Common IP block data */
57extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
58extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
59extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
60extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
61extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
62extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
63extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
64extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
65extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
66
67/* Common IP block data on OMAP2430/OMAP3 */
68extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
69
70/* Common IP block data across OMAP2/3 */
71extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
72extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
73extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
74extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
75extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
76extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
77extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
78extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
79extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
80extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
81extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
82extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
83extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
84extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
85extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
86extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
87extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
88extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
89extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
90extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
91extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
92extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
93extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
94extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
95
19/* OMAP hwmod classes - forward declarations */ 96/* OMAP hwmod classes - forward declarations */
20extern struct omap_hwmod_class l3_hwmod_class; 97extern struct omap_hwmod_class l3_hwmod_class;
21extern struct omap_hwmod_class l4_hwmod_class; 98extern struct omap_hwmod_class l4_hwmod_class;
22extern struct omap_hwmod_class mpu_hwmod_class; 99extern struct omap_hwmod_class mpu_hwmod_class;
23extern struct omap_hwmod_class iva_hwmod_class; 100extern struct omap_hwmod_class iva_hwmod_class;
101extern struct omap_hwmod_class omap2_uart_class;
102extern struct omap_hwmod_class omap2_dss_hwmod_class;
103extern struct omap_hwmod_class omap2_dispc_hwmod_class;
104extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
105extern struct omap_hwmod_class omap2_venc_hwmod_class;
106
107extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
108extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
109extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
110extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
111extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
112extern struct omap_hwmod_class omap2xxx_mcspi_class;
24 113
25#endif 114#endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a5a83b358ddd..4411163e012d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -38,318 +38,21 @@
38#include "prm2xxx_3xxx.h" 38#include "prm2xxx_3xxx.h"
39#include "pm.h" 39#include "pm.h"
40 40
41int omap2_pm_debug;
42u32 enable_off_mode; 41u32 enable_off_mode;
43u32 sleep_while_idle;
44u32 wakeup_timer_seconds;
45u32 wakeup_timer_milliseconds;
46
47#define DUMP_PRM_MOD_REG(mod, reg) \
48 regs[reg_count].name = #mod "." #reg; \
49 regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
50#define DUMP_CM_MOD_REG(mod, reg) \
51 regs[reg_count].name = #mod "." #reg; \
52 regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
53#define DUMP_PRM_REG(reg) \
54 regs[reg_count].name = #reg; \
55 regs[reg_count++].val = __raw_readl(reg)
56#define DUMP_CM_REG(reg) \
57 regs[reg_count].name = #reg; \
58 regs[reg_count++].val = __raw_readl(reg)
59#define DUMP_INTC_REG(reg, off) \
60 regs[reg_count].name = #reg; \
61 regs[reg_count++].val = \
62 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
63
64void omap2_pm_dump(int mode, int resume, unsigned int us)
65{
66 struct reg {
67 const char *name;
68 u32 val;
69 } regs[32];
70 int reg_count = 0, i;
71 const char *s1 = NULL, *s2 = NULL;
72
73 if (!resume) {
74#if 0
75 /* MPU */
76 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
77 DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
78 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
79 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
80 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
81#endif
82#if 0
83 /* INTC */
84 DUMP_INTC_REG(INTC_MIR0, 0x0084);
85 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
86 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
87#endif
88#if 0
89 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
90 if (cpu_is_omap24xx()) {
91 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
92 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
93 OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
94 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
95 OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
96 }
97 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
98 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
99 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
100 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
101 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
102 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
103 DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
104#endif
105#if 0
106 /* DSP */
107 if (cpu_is_omap24xx()) {
108 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
109 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
110 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
111 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
112 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
113 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
114 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
115 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
116 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
117 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
118 }
119#endif
120 } else {
121 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
122 if (cpu_is_omap24xx())
123 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
124 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
125 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
126#if 1
127 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
128 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
129 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
130#endif
131 }
132
133 switch (mode) {
134 case 0:
135 s1 = "full";
136 s2 = "retention";
137 break;
138 case 1:
139 s1 = "MPU";
140 s2 = "retention";
141 break;
142 case 2:
143 s1 = "MPU";
144 s2 = "idle";
145 break;
146 }
147
148 if (!resume)
149#ifdef CONFIG_NO_HZ
150 printk(KERN_INFO
151 "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
152 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
153 jiffies));
154#else
155 printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
156#endif
157 else
158 printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
159 us / 1000, us % 1000);
160
161 for (i = 0; i < reg_count; i++)
162 printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
163}
164
165void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
166{
167 u32 tick_rate, cycles;
168
169 if (!seconds && !milliseconds)
170 return;
171
172 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
173 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
174 omap_dm_timer_stop(gptimer_wakeup);
175 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
176
177 pr_info("PM: Resume timer in %u.%03u secs"
178 " (%d ticks at %d ticks/sec.)\n",
179 seconds, milliseconds, cycles, tick_rate);
180}
181 42
182#ifdef CONFIG_DEBUG_FS 43#ifdef CONFIG_DEBUG_FS
183#include <linux/debugfs.h> 44#include <linux/debugfs.h>
184#include <linux/seq_file.h> 45#include <linux/seq_file.h>
185 46
186static void pm_dbg_regset_store(u32 *ptr);
187
188static struct dentry *pm_dbg_dir;
189
190static int pm_dbg_init_done; 47static int pm_dbg_init_done;
191 48
192static int __init pm_dbg_init(void); 49static int pm_dbg_init(void);
193 50
194enum { 51enum {
195 DEBUG_FILE_COUNTERS = 0, 52 DEBUG_FILE_COUNTERS = 0,
196 DEBUG_FILE_TIMERS, 53 DEBUG_FILE_TIMERS,
197}; 54};
198 55
199struct pm_module_def {
200 char name[8]; /* Name of the module */
201 short type; /* CM or PRM */
202 unsigned short offset;
203 int low; /* First register address on this module */
204 int high; /* Last register address on this module */
205};
206
207#define MOD_CM 0
208#define MOD_PRM 1
209
210static const struct pm_module_def *pm_dbg_reg_modules;
211static const struct pm_module_def omap3_pm_reg_modules[] = {
212 { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
213 { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
214 { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
215 { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
216 { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
217 { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
218 { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
219 { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
220 { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
221 { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
222 { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
223 { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
224 { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
225
226 { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
227 { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
228 { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
229 { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
230 { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
231 { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
232 { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
233 { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
234 { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
235 { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
236 { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
237 { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
238 { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
239 { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
240 { "", 0, 0, 0, 0 },
241};
242
243#define PM_DBG_MAX_REG_SETS 4
244
245static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
246
247static int pm_dbg_get_regset_size(void)
248{
249 static int regset_size;
250
251 if (regset_size == 0) {
252 int i = 0;
253
254 while (pm_dbg_reg_modules[i].name[0] != 0) {
255 regset_size += pm_dbg_reg_modules[i].high +
256 4 - pm_dbg_reg_modules[i].low;
257 i++;
258 }
259 }
260 return regset_size;
261}
262
263static int pm_dbg_show_regs(struct seq_file *s, void *unused)
264{
265 int i, j;
266 unsigned long val;
267 int reg_set = (int)s->private;
268 u32 *ptr;
269 void *store = NULL;
270 int regs;
271 int linefeed;
272
273 if (reg_set == 0) {
274 store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
275 ptr = store;
276 pm_dbg_regset_store(ptr);
277 } else {
278 ptr = pm_dbg_reg_set[reg_set - 1];
279 }
280
281 i = 0;
282
283 while (pm_dbg_reg_modules[i].name[0] != 0) {
284 regs = 0;
285 linefeed = 0;
286 if (pm_dbg_reg_modules[i].type == MOD_CM)
287 seq_printf(s, "MOD: CM_%s (%08x)\n",
288 pm_dbg_reg_modules[i].name,
289 (u32)(OMAP3430_CM_BASE +
290 pm_dbg_reg_modules[i].offset));
291 else
292 seq_printf(s, "MOD: PRM_%s (%08x)\n",
293 pm_dbg_reg_modules[i].name,
294 (u32)(OMAP3430_PRM_BASE +
295 pm_dbg_reg_modules[i].offset));
296
297 for (j = pm_dbg_reg_modules[i].low;
298 j <= pm_dbg_reg_modules[i].high; j += 4) {
299 val = *(ptr++);
300 if (val != 0) {
301 regs++;
302 if (linefeed) {
303 seq_printf(s, "\n");
304 linefeed = 0;
305 }
306 seq_printf(s, " %02x => %08lx", j, val);
307 if (regs % 4 == 0)
308 linefeed = 1;
309 }
310 }
311 seq_printf(s, "\n");
312 i++;
313 }
314
315 if (store != NULL)
316 kfree(store);
317
318 return 0;
319}
320
321static void pm_dbg_regset_store(u32 *ptr)
322{
323 int i, j;
324 u32 val;
325
326 i = 0;
327
328 while (pm_dbg_reg_modules[i].name[0] != 0) {
329 for (j = pm_dbg_reg_modules[i].low;
330 j <= pm_dbg_reg_modules[i].high; j += 4) {
331 if (pm_dbg_reg_modules[i].type == MOD_CM)
332 val = omap2_cm_read_mod_reg(
333 pm_dbg_reg_modules[i].offset, j);
334 else
335 val = omap2_prm_read_mod_reg(
336 pm_dbg_reg_modules[i].offset, j);
337 *(ptr++) = val;
338 }
339 i++;
340 }
341}
342
343int pm_dbg_regset_save(int reg_set)
344{
345 if (pm_dbg_reg_set[reg_set-1] == NULL)
346 return -EINVAL;
347
348 pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
349
350 return 0;
351}
352
353static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = { 56static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
354 "OFF", 57 "OFF",
355 "RET", 58 "RET",
@@ -469,11 +172,6 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
469 }; 172 };
470} 173}
471 174
472static int pm_dbg_reg_open(struct inode *inode, struct file *file)
473{
474 return single_open(file, pm_dbg_show_regs, inode->i_private);
475}
476
477static const struct file_operations debug_fops = { 175static const struct file_operations debug_fops = {
478 .open = pm_dbg_open, 176 .open = pm_dbg_open,
479 .read = seq_read, 177 .read = seq_read,
@@ -481,40 +179,6 @@ static const struct file_operations debug_fops = {
481 .release = single_release, 179 .release = single_release,
482}; 180};
483 181
484static const struct file_operations debug_reg_fops = {
485 .open = pm_dbg_reg_open,
486 .read = seq_read,
487 .llseek = seq_lseek,
488 .release = single_release,
489};
490
491int pm_dbg_regset_init(int reg_set)
492{
493 char name[2];
494
495 if (!pm_dbg_init_done)
496 pm_dbg_init();
497
498 if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
499 pm_dbg_reg_set[reg_set-1] != NULL)
500 return -EINVAL;
501
502 pm_dbg_reg_set[reg_set-1] =
503 kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
504
505 if (pm_dbg_reg_set[reg_set-1] == NULL)
506 return -ENOMEM;
507
508 if (pm_dbg_dir != NULL) {
509 sprintf(name, "%d", reg_set);
510
511 (void) debugfs_create_file(name, S_IRUGO,
512 pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
513 }
514
515 return 0;
516}
517
518static int pwrdm_suspend_get(void *data, u64 *val) 182static int pwrdm_suspend_get(void *data, u64 *val)
519{ 183{
520 int ret = -EINVAL; 184 int ret = -EINVAL;
@@ -576,9 +240,6 @@ static int option_set(void *data, u64 val)
576{ 240{
577 u32 *option = data; 241 u32 *option = data;
578 242
579 if (option == &wakeup_timer_milliseconds && val >= 1000)
580 return -EINVAL;
581
582 *option = val; 243 *option = val;
583 244
584 if (option == &enable_off_mode) { 245 if (option == &enable_off_mode) {
@@ -597,20 +258,11 @@ DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
597 258
598static int __init pm_dbg_init(void) 259static int __init pm_dbg_init(void)
599{ 260{
600 int i;
601 struct dentry *d; 261 struct dentry *d;
602 char name[2];
603 262
604 if (pm_dbg_init_done) 263 if (pm_dbg_init_done)
605 return 0; 264 return 0;
606 265
607 if (cpu_is_omap34xx())
608 pm_dbg_reg_modules = omap3_pm_reg_modules;
609 else {
610 printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
611 return -ENODEV;
612 }
613
614 d = debugfs_create_dir("pm_debug", NULL); 266 d = debugfs_create_dir("pm_debug", NULL);
615 if (IS_ERR(d)) 267 if (IS_ERR(d))
616 return PTR_ERR(d); 268 return PTR_ERR(d);
@@ -622,30 +274,8 @@ static int __init pm_dbg_init(void)
622 274
623 pwrdm_for_each(pwrdms_setup, (void *)d); 275 pwrdm_for_each(pwrdms_setup, (void *)d);
624 276
625 pm_dbg_dir = debugfs_create_dir("registers", d);
626 if (IS_ERR(pm_dbg_dir))
627 return PTR_ERR(pm_dbg_dir);
628
629 (void) debugfs_create_file("current", S_IRUGO,
630 pm_dbg_dir, (void *)0, &debug_reg_fops);
631
632 for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
633 if (pm_dbg_reg_set[i] != NULL) {
634 sprintf(name, "%d", i+1);
635 (void) debugfs_create_file(name, S_IRUGO,
636 pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
637
638 }
639
640 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d, 277 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
641 &enable_off_mode, &pm_dbg_option_fops); 278 &enable_off_mode, &pm_dbg_option_fops);
642 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
643 &sleep_while_idle, &pm_dbg_option_fops);
644 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
645 &wakeup_timer_seconds, &pm_dbg_option_fops);
646 (void) debugfs_create_file("wakeup_timer_milliseconds",
647 S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
648 &pm_dbg_option_fops);
649 pm_dbg_init_done = 1; 279 pm_dbg_init_done = 1;
650 280
651 return 0; 281 return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 49486f522dca..d48813fd62de 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -106,7 +106,7 @@ static void omap2_init_processor_devices(void)
106int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 106int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
107{ 107{
108 u32 cur_state; 108 u32 cur_state;
109 int sleep_switch = 0; 109 int sleep_switch = -1;
110 int ret = 0; 110 int ret = 0;
111 111
112 if (pwrdm == NULL || IS_ERR(pwrdm)) 112 if (pwrdm == NULL || IS_ERR(pwrdm))
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 45bcfce77352..babac19e3ec1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -60,32 +60,16 @@ inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
60extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); 60extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
61extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); 61extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
62 62
63extern u32 wakeup_timer_seconds;
64extern u32 wakeup_timer_milliseconds;
65extern struct omap_dm_timer *gptimer_wakeup;
66
67#ifdef CONFIG_PM_DEBUG 63#ifdef CONFIG_PM_DEBUG
68extern void omap2_pm_dump(int mode, int resume, unsigned int us);
69extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
70extern int omap2_pm_debug;
71extern u32 enable_off_mode; 64extern u32 enable_off_mode;
72extern u32 sleep_while_idle;
73#else 65#else
74#define omap2_pm_dump(mode, resume, us) do {} while (0);
75#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
76#define omap2_pm_debug 0
77#define enable_off_mode 0 66#define enable_off_mode 0
78#define sleep_while_idle 0
79#endif 67#endif
80 68
81#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 69#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
82extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); 70extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
83extern int pm_dbg_regset_save(int reg_set);
84extern int pm_dbg_regset_init(int reg_set);
85#else 71#else
86#define pm_dbg_update_time(pwrdm, prev) do {} while (0); 72#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
87#define pm_dbg_regset_save(reg_set) do {} while (0);
88#define pm_dbg_regset_init(reg_set) do {} while (0);
89#endif /* CONFIG_PM_DEBUG */ 73#endif /* CONFIG_PM_DEBUG */
90 74
91extern void omap24xx_idle_loop_suspend(void); 75extern void omap24xx_idle_loop_suspend(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index df3ded6fe194..bf089e743ed9 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,6 +53,8 @@
53#include "powerdomain.h" 53#include "powerdomain.h"
54#include "clockdomain.h" 54#include "clockdomain.h"
55 55
56static int omap2_pm_debug;
57
56#ifdef CONFIG_SUSPEND 58#ifdef CONFIG_SUSPEND
57static suspend_state_t suspend_state = PM_SUSPEND_ON; 59static suspend_state_t suspend_state = PM_SUSPEND_ON;
58static inline bool is_suspending(void) 60static inline bool is_suspending(void)
@@ -123,7 +125,6 @@ static void omap2_enter_full_retention(void)
123 omap2_gpio_prepare_for_idle(0); 125 omap2_gpio_prepare_for_idle(0);
124 126
125 if (omap2_pm_debug) { 127 if (omap2_pm_debug) {
126 omap2_pm_dump(0, 0, 0);
127 getnstimeofday(&ts_preidle); 128 getnstimeofday(&ts_preidle);
128 } 129 }
129 130
@@ -160,7 +161,6 @@ no_sleep:
160 getnstimeofday(&ts_postidle); 161 getnstimeofday(&ts_postidle);
161 ts_idle = timespec_sub(ts_postidle, ts_preidle); 162 ts_idle = timespec_sub(ts_postidle, ts_preidle);
162 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; 163 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
163 omap2_pm_dump(0, 1, tmp);
164 } 164 }
165 omap2_gpio_resume_after_idle(); 165 omap2_gpio_resume_after_idle();
166 166
@@ -247,7 +247,6 @@ static void omap2_enter_mpu_retention(void)
247 } 247 }
248 248
249 if (omap2_pm_debug) { 249 if (omap2_pm_debug) {
250 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
251 getnstimeofday(&ts_preidle); 250 getnstimeofday(&ts_preidle);
252 } 251 }
253 252
@@ -259,7 +258,6 @@ static void omap2_enter_mpu_retention(void)
259 getnstimeofday(&ts_postidle); 258 getnstimeofday(&ts_postidle);
260 ts_idle = timespec_sub(ts_postidle, ts_preidle); 259 ts_idle = timespec_sub(ts_postidle, ts_preidle);
261 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; 260 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
262 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
263 } 261 }
264} 262}
265 263
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c155c9d1c82c..96a76245284c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -497,8 +497,6 @@ console_still_active:
497 497
498int omap3_can_sleep(void) 498int omap3_can_sleep(void)
499{ 499{
500 if (!sleep_while_idle)
501 return 0;
502 if (!omap_uart_can_sleep()) 500 if (!omap_uart_can_sleep())
503 return 0; 501 return 0;
504 return 1; 502 return 1;
@@ -534,10 +532,6 @@ static int omap3_pm_suspend(void)
534 struct power_state *pwrst; 532 struct power_state *pwrst;
535 int state, ret = 0; 533 int state, ret = 0;
536 534
537 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
538 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
539 wakeup_timer_milliseconds);
540
541 /* Read current next_pwrsts */ 535 /* Read current next_pwrsts */
542 list_for_each_entry(pwrst, &pwrst_list, node) 536 list_for_each_entry(pwrst, &pwrst_list, node)
543 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 537 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 8f86e60399ac..247e79495115 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 Power domains framework 2 * OMAP4 Power domains framework
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2009-2011 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
@@ -41,19 +41,19 @@ static struct powerdomain core_44xx_pwrdm = {
41 .banks = 5, 41 .banks = 5,
42 .pwrsts_mem_ret = { 42 .pwrsts_mem_ret = {
43 [0] = PWRSTS_OFF, /* core_nret_bank */ 43 [0] = PWRSTS_OFF, /* core_nret_bank */
44 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 44 [1] = PWRSTS_RET, /* core_ocmram */
45 [2] = PWRSTS_RET, /* core_other_bank */ 45 [2] = PWRSTS_RET, /* core_other_bank */
46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ 46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */ 47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */
48 }, 48 },
49 .pwrsts_mem_on = { 49 .pwrsts_mem_on = {
50 [0] = PWRSTS_ON, /* core_nret_bank */ 50 [0] = PWRSTS_ON, /* core_nret_bank */
51 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 51 [1] = PWRSTS_ON, /* core_ocmram */
52 [2] = PWRSTS_ON, /* core_other_bank */ 52 [2] = PWRSTS_ON, /* core_other_bank */
53 [3] = PWRSTS_ON, /* ducati_l2ram */ 53 [3] = PWRSTS_ON, /* ducati_l2ram */
54 [4] = PWRSTS_ON, /* ducati_unicache */ 54 [4] = PWRSTS_ON, /* ducati_unicache */
55 }, 55 },
56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
57}; 57};
58 58
59/* gfx_44xx_pwrdm: 3D accelerator power domain */ 59/* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
70 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
71 [0] = PWRSTS_ON, /* gfx_mem */ 71 [0] = PWRSTS_ON, /* gfx_mem */
72 }, 72 },
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
74}; 74};
75 75
76/* abe_44xx_pwrdm: Audio back end power domain */ 76/* abe_44xx_pwrdm: Audio back end power domain */
@@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
90 [0] = PWRSTS_ON, /* aessmem */ 90 [0] = PWRSTS_ON, /* aessmem */
91 [1] = PWRSTS_ON, /* periphmem */ 91 [1] = PWRSTS_ON, /* periphmem */
92 }, 92 },
93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
94}; 94};
95 95
96/* dss_44xx_pwrdm: Display subsystem power domain */ 96/* dss_44xx_pwrdm: Display subsystem power domain */
@@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
108 .pwrsts_mem_on = { 108 .pwrsts_mem_on = {
109 [0] = PWRSTS_ON, /* dss_mem */ 109 [0] = PWRSTS_ON, /* dss_mem */
110 }, 110 },
111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
112}; 112};
113 113
114/* tesla_44xx_pwrdm: Tesla processor power domain */ 114/* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
130 [1] = PWRSTS_ON, /* tesla_l1 */ 130 [1] = PWRSTS_ON, /* tesla_l1 */
131 [2] = PWRSTS_ON, /* tesla_l2 */ 131 [2] = PWRSTS_ON, /* tesla_l2 */
132 }, 132 },
133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
134}; 134};
135 135
136/* wkup_44xx_pwrdm: Wake-up power domain */ 136/* wkup_44xx_pwrdm: Wake-up power domain */
@@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
241 [2] = PWRSTS_ON, /* tcm1_mem */ 241 [2] = PWRSTS_ON, /* tcm1_mem */
242 [3] = PWRSTS_ON, /* tcm2_mem */ 242 [3] = PWRSTS_ON, /* tcm2_mem */
243 }, 243 },
244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
245}; 245};
246 246
247/* cam_44xx_pwrdm: Camera subsystem power domain */ 247/* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
258 .pwrsts_mem_on = { 258 .pwrsts_mem_on = {
259 [0] = PWRSTS_ON, /* cam_mem */ 259 [0] = PWRSTS_ON, /* cam_mem */
260 }, 260 },
261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
262}; 262};
263 263
264/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ 264/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
@@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
276 .pwrsts_mem_on = { 276 .pwrsts_mem_on = {
277 [0] = PWRSTS_ON, /* l3init_bank1 */ 277 [0] = PWRSTS_ON, /* l3init_bank1 */
278 }, 278 },
279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
280}; 280};
281 281
282/* l4per_44xx_pwrdm: Target peripherals power domain */ 282/* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
296 [0] = PWRSTS_ON, /* nonretained_bank */ 296 [0] = PWRSTS_ON, /* nonretained_bank */
297 [1] = PWRSTS_ON, /* retained_bank */ 297 [1] = PWRSTS_ON, /* retained_bank */
298 }, 298 },
299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
300}; 300};
301 301
302/* 302/*
@@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
318 .prcm_partition = OMAP4430_PRM_PARTITION, 318 .prcm_partition = OMAP4430_PRM_PARTITION,
319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
320 .pwrsts = PWRSTS_OFF_ON, 320 .pwrsts = PWRSTS_OFF_ON,
321 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
321}; 322};
322 323
323/* 324/*
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index d22d1b43bccd..8a6e250f04b5 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -31,7 +31,6 @@
31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) 31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
32 32
33/* PRCM_MPU instances */ 33/* PRCM_MPU instances */
34
35#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 34#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
36#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 35#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
37#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 36#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
@@ -52,46 +51,46 @@
52 */ 51 */
53 52
54/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ 53/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
55#define OMAP4_REVISION_PRCM_OFFSET 0x0000 54#define OMAP4_REVISION_PRCM_OFFSET 0x0000
56#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) 55#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 56
58/* PRCM_MPU.DEVICE_PRM register offsets */ 57/* PRCM_MPU.DEVICE_PRM register offsets */
59#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 58#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
60#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) 59#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
61#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 60#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
62#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) 61#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
63 62
64/* PRCM_MPU.CPU0 register offsets */ 63/* PRCM_MPU.CPU0 register offsets */
65#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 64#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
66#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) 65#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
67#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 66#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
68#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) 67#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
69#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 68#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
70#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) 69#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
71#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c 70#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
72#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) 71#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
73#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 72#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
74#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) 73#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
75#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 74#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
76#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) 75#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
77#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 76#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
78#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) 77#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
79 78
80/* PRCM_MPU.CPU1 register offsets */ 79/* PRCM_MPU.CPU1 register offsets */
81#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 80#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
82#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) 81#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
83#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 82#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
84#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) 83#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
85#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 84#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
86#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) 85#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
87#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c 86#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
88#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) 87#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
89#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 88#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
90#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) 89#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
91#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 90#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
92#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) 91#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
93#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 92#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
94#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) 93#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
95 94
96/* Function prototypes */ 95/* Function prototypes */
97# ifndef __ASSEMBLER__ 96# ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 67a0d3feb3f6..6e53120fd6cb 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -31,7 +31,7 @@
31#define OMAP4430_PRM_BASE 0x4a306000 31#define OMAP4430_PRM_BASE 0x4a306000
32 32
33#define OMAP44XX_PRM_REGADDR(inst, reg) \ 33#define OMAP44XX_PRM_REGADDR(inst, reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) 34 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
35 35
36 36
37/* PRM instances */ 37/* PRM instances */
@@ -46,30 +46,18 @@
46#define OMAP4430_PRM_CAM_INST 0x1000 46#define OMAP4430_PRM_CAM_INST 0x1000
47#define OMAP4430_PRM_DSS_INST 0x1100 47#define OMAP4430_PRM_DSS_INST 0x1100
48#define OMAP4430_PRM_GFX_INST 0x1200 48#define OMAP4430_PRM_GFX_INST 0x1200
49#define OMAP4430_PRM_L3INIT_INST 0x1300 49#define OMAP4430_PRM_L3INIT_INST 0x1300
50#define OMAP4430_PRM_L4PER_INST 0x1400 50#define OMAP4430_PRM_L4PER_INST 0x1400
51#define OMAP4430_PRM_CEFUSE_INST 0x1600 51#define OMAP4430_PRM_CEFUSE_INST 0x1600
52#define OMAP4430_PRM_WKUP_INST 0x1700 52#define OMAP4430_PRM_WKUP_INST 0x1700
53#define OMAP4430_PRM_WKUP_CM_INST 0x1800 53#define OMAP4430_PRM_WKUP_CM_INST 0x1800
54#define OMAP4430_PRM_EMU_INST 0x1900 54#define OMAP4430_PRM_EMU_INST 0x1900
55#define OMAP4430_PRM_EMU_CM_INST 0x1a00 55#define OMAP4430_PRM_EMU_CM_INST 0x1a00
56#define OMAP4430_PRM_DEVICE_INST 0x1b00 56#define OMAP4430_PRM_DEVICE_INST 0x1b00
57#define OMAP4430_PRM_INSTR_INST 0x1f00 57#define OMAP4430_PRM_INSTR_INST 0x1f00
58 58
59/* PRM clockdomain register offsets (from instance start) */ 59/* PRM clockdomain register offsets (from instance start) */
60#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
61#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
62#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
63#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
64#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
65#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
66#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
67#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
68#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
69#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
70#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
71#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 60#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
72#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
73#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 61#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
74 62
75/* OMAP4 specific register offsets */ 63/* OMAP4 specific register offsets */
@@ -247,8 +235,8 @@
247#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) 235#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
248#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 236#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
249#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) 237#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
250#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c 238#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
251#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) 239#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
252#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 240#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
253#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) 241#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
254#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 242#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
@@ -713,8 +701,8 @@
713#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) 701#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
714#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 702#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
715#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) 703#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
716#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8 704#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
717#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) 705#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
718#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac 706#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
719#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) 707#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
720#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 708#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
@@ -751,8 +739,8 @@
751#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) 739#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
752#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 740#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
753#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) 741#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
754#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4 742#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
755#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) 743#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
756#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 744#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
757#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) 745#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
758 746
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index fb7dc52394a8..2ce2fb7664bc 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -143,7 +143,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
143 sr_write_reg(sr_info, IRQSTATUS, status); 143 sr_write_reg(sr_info, IRQSTATUS, status);
144 } 144 }
145 145
146 if (sr_class->class_type == SR_CLASS2 && sr_class->notify) 146 if (sr_class->notify)
147 sr_class->notify(sr_info->voltdm, status); 147 sr_class->notify(sr_info->voltdm, status);
148 148
149 return IRQ_HANDLED; 149 return IRQ_HANDLED;
@@ -258,9 +258,7 @@ static int sr_late_init(struct omap_sr *sr_info)
258 struct resource *mem; 258 struct resource *mem;
259 int ret = 0; 259 int ret = 0;
260 260
261 if (sr_class->class_type == SR_CLASS2 && 261 if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
262 sr_class->notify_flags && sr_info->irq) {
263
264 name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name); 262 name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
265 if (name == NULL) { 263 if (name == NULL) {
266 ret = -ENOMEM; 264 ret = -ENOMEM;
@@ -270,6 +268,7 @@ static int sr_late_init(struct omap_sr *sr_info)
270 0, name, (void *)sr_info); 268 0, name, (void *)sr_info);
271 if (ret) 269 if (ret)
272 goto error; 270 goto error;
271 disable_irq(sr_info->irq);
273 } 272 }
274 273
275 if (pdata && pdata->enable_on_init) 274 if (pdata && pdata->enable_on_init)
@@ -278,16 +277,16 @@ static int sr_late_init(struct omap_sr *sr_info)
278 return ret; 277 return ret;
279 278
280error: 279error:
281 iounmap(sr_info->base); 280 iounmap(sr_info->base);
282 mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0); 281 mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
283 release_mem_region(mem->start, resource_size(mem)); 282 release_mem_region(mem->start, resource_size(mem));
284 list_del(&sr_info->node); 283 list_del(&sr_info->node);
285 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering" 284 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
286 "interrupt handler. Smartreflex will" 285 "interrupt handler. Smartreflex will"
287 "not function as desired\n", __func__); 286 "not function as desired\n", __func__);
288 kfree(name); 287 kfree(name);
289 kfree(sr_info); 288 kfree(sr_info);
290 return ret; 289 return ret;
291} 290}
292 291
293static void sr_v1_disable(struct omap_sr *sr) 292static void sr_v1_disable(struct omap_sr *sr)
@@ -808,10 +807,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
808 return -EINVAL; 807 return -EINVAL;
809 } 808 }
810 809
811 if (!val) 810 /* control enable/disable only if there is a delta in value */
812 sr_stop_vddautocomp(sr_info); 811 if (sr_info->autocomp_active != val) {
813 else 812 if (!val)
814 sr_start_vddautocomp(sr_info); 813 sr_stop_vddautocomp(sr_info);
814 else
815 sr_start_vddautocomp(sr_info);
816 }
815 817
816 return 0; 818 return 0;
817} 819}
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
deleted file mode 100644
index 3b9cf85f4bb9..000000000000
--- a/arch/arm/mach-omap2/timer-gp.c
+++ /dev/null
@@ -1,266 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/timer-gp.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/clocksource.h>
37#include <linux/clockchips.h>
38
39#include <asm/mach/time.h>
40#include <plat/dmtimer.h>
41#include <asm/localtimer.h>
42#include <asm/sched_clock.h>
43#include <plat/common.h>
44#include <plat/omap_hwmod.h>
45
46#include "timer-gp.h"
47
48
49/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
50#define MAX_GPTIMER_ID 12
51
52static struct omap_dm_timer *gptimer;
53static struct clock_event_device clockevent_gpt;
54static u8 __initdata gptimer_id = 1;
55static u8 __initdata inited;
56struct omap_dm_timer *gptimer_wakeup;
57
58static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
59{
60 struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
61 struct clock_event_device *evt = &clockevent_gpt;
62
63 omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
64
65 evt->event_handler(evt);
66 return IRQ_HANDLED;
67}
68
69static struct irqaction omap2_gp_timer_irq = {
70 .name = "gp timer",
71 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
72 .handler = omap2_gp_timer_interrupt,
73};
74
75static int omap2_gp_timer_set_next_event(unsigned long cycles,
76 struct clock_event_device *evt)
77{
78 omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
79
80 return 0;
81}
82
83static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
84 struct clock_event_device *evt)
85{
86 u32 period;
87
88 omap_dm_timer_stop(gptimer);
89
90 switch (mode) {
91 case CLOCK_EVT_MODE_PERIODIC:
92 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
93 period -= 1;
94 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
95 break;
96 case CLOCK_EVT_MODE_ONESHOT:
97 break;
98 case CLOCK_EVT_MODE_UNUSED:
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 case CLOCK_EVT_MODE_RESUME:
101 break;
102 }
103}
104
105static struct clock_event_device clockevent_gpt = {
106 .name = "gp timer",
107 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
108 .shift = 32,
109 .set_next_event = omap2_gp_timer_set_next_event,
110 .set_mode = omap2_gp_timer_set_mode,
111};
112
113/**
114 * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
115 * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
116 *
117 * Define the GPTIMER that the system should use for the tick timer.
118 * Meant to be called from board-*.c files in the event that GPTIMER1, the
119 * default, is unsuitable. Returns -EINVAL on error or 0 on success.
120 */
121int __init omap2_gp_clockevent_set_gptimer(u8 id)
122{
123 if (id < 1 || id > MAX_GPTIMER_ID)
124 return -EINVAL;
125
126 BUG_ON(inited);
127
128 gptimer_id = id;
129
130 return 0;
131}
132
133static void __init omap2_gp_clockevent_init(void)
134{
135 u32 tick_rate;
136 int src;
137 char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
138
139 inited = 1;
140
141 sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
142 omap_hwmod_setup_one(clockevent_hwmod_name);
143
144 gptimer = omap_dm_timer_request_specific(gptimer_id);
145 BUG_ON(gptimer == NULL);
146 gptimer_wakeup = gptimer;
147
148#if defined(CONFIG_OMAP_32K_TIMER)
149 src = OMAP_TIMER_SRC_32_KHZ;
150#else
151 src = OMAP_TIMER_SRC_SYS_CLK;
152 WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
153 "secure 32KiHz clock source\n");
154#endif
155
156 if (gptimer_id != 12)
157 WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
158 "timer-gp: omap_dm_timer_set_source() failed\n");
159
160 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
161
162 pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
163 gptimer_id, tick_rate);
164
165 omap2_gp_timer_irq.dev_id = (void *)gptimer;
166 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
167 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
168
169 clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
170 clockevent_gpt.shift);
171 clockevent_gpt.max_delta_ns =
172 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
173 clockevent_gpt.min_delta_ns =
174 clockevent_delta2ns(3, &clockevent_gpt);
175 /* Timer internal resynch latency. */
176
177 clockevent_gpt.cpumask = cpumask_of(0);
178 clockevents_register_device(&clockevent_gpt);
179}
180
181/* Clocksource code */
182
183#ifdef CONFIG_OMAP_32K_TIMER
184/*
185 * When 32k-timer is enabled, don't use GPTimer for clocksource
186 * instead, just leave default clocksource which uses the 32k
187 * sync counter. See clocksource setup in plat-omap/counter_32k.c
188 */
189
190static void __init omap2_gp_clocksource_init(void)
191{
192 omap_init_clocksource_32k();
193}
194
195#else
196/*
197 * clocksource
198 */
199static DEFINE_CLOCK_DATA(cd);
200static struct omap_dm_timer *gpt_clocksource;
201static cycle_t clocksource_read_cycles(struct clocksource *cs)
202{
203 return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
204}
205
206static struct clocksource clocksource_gpt = {
207 .name = "gp timer",
208 .rating = 300,
209 .read = clocksource_read_cycles,
210 .mask = CLOCKSOURCE_MASK(32),
211 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
212};
213
214static void notrace dmtimer_update_sched_clock(void)
215{
216 u32 cyc;
217
218 cyc = omap_dm_timer_read_counter(gpt_clocksource);
219
220 update_sched_clock(&cd, cyc, (u32)~0);
221}
222
223/* Setup free-running counter for clocksource */
224static void __init omap2_gp_clocksource_init(void)
225{
226 static struct omap_dm_timer *gpt;
227 u32 tick_rate;
228 static char err1[] __initdata = KERN_ERR
229 "%s: failed to request dm-timer\n";
230 static char err2[] __initdata = KERN_ERR
231 "%s: can't register clocksource!\n";
232
233 gpt = omap_dm_timer_request();
234 if (!gpt)
235 printk(err1, clocksource_gpt.name);
236 gpt_clocksource = gpt;
237
238 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
239 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
240
241 omap_dm_timer_set_load_start(gpt, 1, 0);
242
243 init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
244
245 if (clocksource_register_hz(&clocksource_gpt, tick_rate))
246 printk(err2, clocksource_gpt.name);
247}
248#endif
249
250static void __init omap2_gp_timer_init(void)
251{
252#ifdef CONFIG_LOCAL_TIMERS
253 if (cpu_is_omap44xx()) {
254 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
255 BUG_ON(!twd_base);
256 }
257#endif
258 omap_dm_timer_init();
259
260 omap2_gp_clockevent_init();
261 omap2_gp_clocksource_init();
262}
263
264struct sys_timer omap_timer = {
265 .init = omap2_gp_timer_init,
266};
diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
deleted file mode 100644
index 5c1072c6783b..000000000000
--- a/arch/arm/mach-omap2/timer-gp.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * OMAP2/3 GPTIMER support.headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
12#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
13
14extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
15
16#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
new file mode 100644
index 000000000000..e9640728239b
--- /dev/null
+++ b/arch/arm/mach-omap2/timer.c
@@ -0,0 +1,342 @@
1/*
2 * linux/arch/arm/mach-omap2/timer.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/clocksource.h>
37#include <linux/clockchips.h>
38
39#include <asm/mach/time.h>
40#include <plat/dmtimer.h>
41#include <asm/localtimer.h>
42#include <asm/sched_clock.h>
43#include <plat/common.h>
44#include <plat/omap_hwmod.h>
45
46/* Parent clocks, eventually these will come from the clock framework */
47
48#define OMAP2_MPU_SOURCE "sys_ck"
49#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
50#define OMAP4_MPU_SOURCE "sys_clkin_ck"
51#define OMAP2_32K_SOURCE "func_32k_ck"
52#define OMAP3_32K_SOURCE "omap_32k_fck"
53#define OMAP4_32K_SOURCE "sys_32k_ck"
54
55#ifdef CONFIG_OMAP_32K_TIMER
56#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
57#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
58#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
59#define OMAP3_SECURE_TIMER 12
60#else
61#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
62#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
63#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
64#define OMAP3_SECURE_TIMER 1
65#endif
66
67/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
68#define MAX_GPTIMER_ID 12
69
70u32 sys_timer_reserved;
71
72/* Clockevent code */
73
74static struct omap_dm_timer clkev;
75static struct clock_event_device clockevent_gpt;
76
77static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
78{
79 struct clock_event_device *evt = &clockevent_gpt;
80
81 __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
82
83 evt->event_handler(evt);
84 return IRQ_HANDLED;
85}
86
87static struct irqaction omap2_gp_timer_irq = {
88 .name = "gp timer",
89 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
90 .handler = omap2_gp_timer_interrupt,
91};
92
93static int omap2_gp_timer_set_next_event(unsigned long cycles,
94 struct clock_event_device *evt)
95{
96 __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
97 0xffffffff - cycles, 1);
98
99 return 0;
100}
101
102static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
103 struct clock_event_device *evt)
104{
105 u32 period;
106
107 __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
108
109 switch (mode) {
110 case CLOCK_EVT_MODE_PERIODIC:
111 period = clkev.rate / HZ;
112 period -= 1;
113 /* Looks like we need to first set the load value separately */
114 __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
115 0xffffffff - period, 1);
116 __omap_dm_timer_load_start(clkev.io_base,
117 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
118 0xffffffff - period, 1);
119 break;
120 case CLOCK_EVT_MODE_ONESHOT:
121 break;
122 case CLOCK_EVT_MODE_UNUSED:
123 case CLOCK_EVT_MODE_SHUTDOWN:
124 case CLOCK_EVT_MODE_RESUME:
125 break;
126 }
127}
128
129static struct clock_event_device clockevent_gpt = {
130 .name = "gp timer",
131 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
132 .shift = 32,
133 .set_next_event = omap2_gp_timer_set_next_event,
134 .set_mode = omap2_gp_timer_set_mode,
135};
136
137static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
138 int gptimer_id,
139 const char *fck_source)
140{
141 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
142 struct omap_hwmod *oh;
143 size_t size;
144 int res = 0;
145
146 sprintf(name, "timer%d", gptimer_id);
147 omap_hwmod_setup_one(name);
148 oh = omap_hwmod_lookup(name);
149 if (!oh)
150 return -ENODEV;
151
152 timer->irq = oh->mpu_irqs[0].irq;
153 timer->phys_base = oh->slaves[0]->addr->pa_start;
154 size = oh->slaves[0]->addr->pa_end - timer->phys_base;
155
156 /* Static mapping, never released */
157 timer->io_base = ioremap(timer->phys_base, size);
158 if (!timer->io_base)
159 return -ENXIO;
160
161 /* After the dmtimer is using hwmod these clocks won't be needed */
162 sprintf(name, "gpt%d_fck", gptimer_id);
163 timer->fclk = clk_get(NULL, name);
164 if (IS_ERR(timer->fclk))
165 return -ENODEV;
166
167 sprintf(name, "gpt%d_ick", gptimer_id);
168 timer->iclk = clk_get(NULL, name);
169 if (IS_ERR(timer->iclk)) {
170 clk_put(timer->fclk);
171 return -ENODEV;
172 }
173
174 omap_hwmod_enable(oh);
175
176 sys_timer_reserved |= (1 << (gptimer_id - 1));
177
178 if (gptimer_id != 12) {
179 struct clk *src;
180
181 src = clk_get(NULL, fck_source);
182 if (IS_ERR(src)) {
183 res = -EINVAL;
184 } else {
185 res = __omap_dm_timer_set_source(timer->fclk, src);
186 if (IS_ERR_VALUE(res))
187 pr_warning("%s: timer%i cannot set source\n",
188 __func__, gptimer_id);
189 clk_put(src);
190 }
191 }
192 __omap_dm_timer_reset(timer->io_base, 1, 1);
193 timer->posted = 1;
194
195 timer->rate = clk_get_rate(timer->fclk);
196
197 timer->reserved = 1;
198
199 return res;
200}
201
202static void __init omap2_gp_clockevent_init(int gptimer_id,
203 const char *fck_source)
204{
205 int res;
206
207 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
208 BUG_ON(res);
209
210 omap2_gp_timer_irq.dev_id = (void *)&clkev;
211 setup_irq(clkev.irq, &omap2_gp_timer_irq);
212
213 __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
214
215 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
216 clockevent_gpt.shift);
217 clockevent_gpt.max_delta_ns =
218 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
219 clockevent_gpt.min_delta_ns =
220 clockevent_delta2ns(3, &clockevent_gpt);
221 /* Timer internal resynch latency. */
222
223 clockevent_gpt.cpumask = cpumask_of(0);
224 clockevents_register_device(&clockevent_gpt);
225
226 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
227 gptimer_id, clkev.rate);
228}
229
230/* Clocksource code */
231
232#ifdef CONFIG_OMAP_32K_TIMER
233/*
234 * When 32k-timer is enabled, don't use GPTimer for clocksource
235 * instead, just leave default clocksource which uses the 32k
236 * sync counter. See clocksource setup in plat-omap/counter_32k.c
237 */
238
239static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
240{
241 omap_init_clocksource_32k();
242}
243
244#else
245
246static struct omap_dm_timer clksrc;
247
248/*
249 * clocksource
250 */
251static DEFINE_CLOCK_DATA(cd);
252static cycle_t clocksource_read_cycles(struct clocksource *cs)
253{
254 return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
255}
256
257static struct clocksource clocksource_gpt = {
258 .name = "gp timer",
259 .rating = 300,
260 .read = clocksource_read_cycles,
261 .mask = CLOCKSOURCE_MASK(32),
262 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
263};
264
265static void notrace dmtimer_update_sched_clock(void)
266{
267 u32 cyc;
268
269 cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
270
271 update_sched_clock(&cd, cyc, (u32)~0);
272}
273
274unsigned long long notrace sched_clock(void)
275{
276 u32 cyc = 0;
277
278 if (clksrc.reserved)
279 cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
280
281 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
282}
283
284/* Setup free-running counter for clocksource */
285static void __init omap2_gp_clocksource_init(int gptimer_id,
286 const char *fck_source)
287{
288 int res;
289
290 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
291 BUG_ON(res);
292
293 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
294 gptimer_id, clksrc.rate);
295
296 __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
297 init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
298
299 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
300 pr_err("Could not register clocksource %s\n",
301 clocksource_gpt.name);
302}
303#endif
304
305#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
306 clksrc_nr, clksrc_src) \
307static void __init omap##name##_timer_init(void) \
308{ \
309 omap2_gp_clockevent_init((clkev_nr), clkev_src); \
310 omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
311}
312
313#define OMAP_SYS_TIMER(name) \
314struct sys_timer omap##name##_timer = { \
315 .init = omap##name##_timer_init, \
316};
317
318#ifdef CONFIG_ARCH_OMAP2
319OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
320OMAP_SYS_TIMER(2)
321#endif
322
323#ifdef CONFIG_ARCH_OMAP3
324OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
325OMAP_SYS_TIMER(3)
326OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
327 2, OMAP3_MPU_SOURCE)
328OMAP_SYS_TIMER(3_secure)
329#endif
330
331#ifdef CONFIG_ARCH_OMAP4
332static void __init omap4_timer_init(void)
333{
334#ifdef CONFIG_LOCAL_TIMERS
335 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
336 BUG_ON(!twd_base);
337#endif
338 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
339 omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
340}
341OMAP_SYS_TIMER(4)
342#endif
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
new file mode 100644
index 000000000000..3aaa46f6cd12
--- /dev/null
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -0,0 +1,304 @@
1/*
2 * twl-common.c
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc..
5 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#include <linux/i2c.h>
24#include <linux/i2c/twl.h>
25#include <linux/gpio.h>
26#include <linux/regulator/machine.h>
27#include <linux/regulator/fixed.h>
28
29#include <plat/i2c.h>
30#include <plat/usb.h>
31
32#include "twl-common.h"
33
34static struct i2c_board_info __initdata pmic_i2c_board_info = {
35 .addr = 0x48,
36 .flags = I2C_CLIENT_WAKE,
37};
38
39void __init omap_pmic_init(int bus, u32 clkrate,
40 const char *pmic_type, int pmic_irq,
41 struct twl4030_platform_data *pmic_data)
42{
43 strncpy(pmic_i2c_board_info.type, pmic_type,
44 sizeof(pmic_i2c_board_info.type));
45 pmic_i2c_board_info.irq = pmic_irq;
46 pmic_i2c_board_info.platform_data = pmic_data;
47
48 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
49}
50
51static struct twl4030_usb_data omap4_usb_pdata = {
52 .phy_init = omap4430_phy_init,
53 .phy_exit = omap4430_phy_exit,
54 .phy_power = omap4430_phy_power,
55 .phy_set_clock = omap4430_phy_set_clk,
56 .phy_suspend = omap4430_phy_suspend,
57};
58
59static struct twl4030_usb_data omap3_usb_pdata = {
60 .usb_mode = T2_USB_MODE_ULPI,
61};
62
63static int omap3_batt_table[] = {
64/* 0 C */
6530800, 29500, 28300, 27100,
6626000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
6717200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
6811600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
698020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
705640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
714040, 3910, 3790, 3670, 3550
72};
73
74static struct twl4030_bci_platform_data omap3_bci_pdata = {
75 .battery_tmp_tbl = omap3_batt_table,
76 .tblsize = ARRAY_SIZE(omap3_batt_table),
77};
78
79static struct twl4030_madc_platform_data omap3_madc_pdata = {
80 .irq_line = 1,
81};
82
83static struct twl4030_codec_audio_data omap3_audio;
84
85static struct twl4030_codec_data omap3_codec_pdata = {
86 .audio_mclk = 26000000,
87 .audio = &omap3_audio,
88};
89
90static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
91 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
92};
93
94static struct regulator_init_data omap3_vdac_idata = {
95 .constraints = {
96 .min_uV = 1800000,
97 .max_uV = 1800000,
98 .valid_modes_mask = REGULATOR_MODE_NORMAL
99 | REGULATOR_MODE_STANDBY,
100 .valid_ops_mask = REGULATOR_CHANGE_MODE
101 | REGULATOR_CHANGE_STATUS,
102 },
103 .num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
104 .consumer_supplies = omap3_vdda_dac_supplies,
105};
106
107static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
108 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
109 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
110};
111
112static struct regulator_init_data omap3_vpll2_idata = {
113 .constraints = {
114 .min_uV = 1800000,
115 .max_uV = 1800000,
116 .valid_modes_mask = REGULATOR_MODE_NORMAL
117 | REGULATOR_MODE_STANDBY,
118 .valid_ops_mask = REGULATOR_CHANGE_MODE
119 | REGULATOR_CHANGE_STATUS,
120 },
121 .num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
122 .consumer_supplies = omap3_vpll2_supplies,
123};
124
125static struct regulator_init_data omap4_vdac_idata = {
126 .constraints = {
127 .min_uV = 1800000,
128 .max_uV = 1800000,
129 .valid_modes_mask = REGULATOR_MODE_NORMAL
130 | REGULATOR_MODE_STANDBY,
131 .valid_ops_mask = REGULATOR_CHANGE_MODE
132 | REGULATOR_CHANGE_STATUS,
133 },
134};
135
136static struct regulator_init_data omap4_vaux2_idata = {
137 .constraints = {
138 .min_uV = 1200000,
139 .max_uV = 2800000,
140 .apply_uV = true,
141 .valid_modes_mask = REGULATOR_MODE_NORMAL
142 | REGULATOR_MODE_STANDBY,
143 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
144 | REGULATOR_CHANGE_MODE
145 | REGULATOR_CHANGE_STATUS,
146 },
147};
148
149static struct regulator_init_data omap4_vaux3_idata = {
150 .constraints = {
151 .min_uV = 1000000,
152 .max_uV = 3000000,
153 .apply_uV = true,
154 .valid_modes_mask = REGULATOR_MODE_NORMAL
155 | REGULATOR_MODE_STANDBY,
156 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
157 | REGULATOR_CHANGE_MODE
158 | REGULATOR_CHANGE_STATUS,
159 },
160};
161
162static struct regulator_consumer_supply omap4_vmmc_supply[] = {
163 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
164};
165
166/* VMMC1 for MMC1 card */
167static struct regulator_init_data omap4_vmmc_idata = {
168 .constraints = {
169 .min_uV = 1200000,
170 .max_uV = 3000000,
171 .apply_uV = true,
172 .valid_modes_mask = REGULATOR_MODE_NORMAL
173 | REGULATOR_MODE_STANDBY,
174 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
175 | REGULATOR_CHANGE_MODE
176 | REGULATOR_CHANGE_STATUS,
177 },
178 .num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
179 .consumer_supplies = omap4_vmmc_supply,
180};
181
182static struct regulator_init_data omap4_vpp_idata = {
183 .constraints = {
184 .min_uV = 1800000,
185 .max_uV = 2500000,
186 .apply_uV = true,
187 .valid_modes_mask = REGULATOR_MODE_NORMAL
188 | REGULATOR_MODE_STANDBY,
189 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
190 | REGULATOR_CHANGE_MODE
191 | REGULATOR_CHANGE_STATUS,
192 },
193};
194
195static struct regulator_init_data omap4_vana_idata = {
196 .constraints = {
197 .min_uV = 2100000,
198 .max_uV = 2100000,
199 .valid_modes_mask = REGULATOR_MODE_NORMAL
200 | REGULATOR_MODE_STANDBY,
201 .valid_ops_mask = REGULATOR_CHANGE_MODE
202 | REGULATOR_CHANGE_STATUS,
203 },
204};
205
206static struct regulator_init_data omap4_vcxio_idata = {
207 .constraints = {
208 .min_uV = 1800000,
209 .max_uV = 1800000,
210 .valid_modes_mask = REGULATOR_MODE_NORMAL
211 | REGULATOR_MODE_STANDBY,
212 .valid_ops_mask = REGULATOR_CHANGE_MODE
213 | REGULATOR_CHANGE_STATUS,
214 },
215};
216
217static struct regulator_init_data omap4_vusb_idata = {
218 .constraints = {
219 .min_uV = 3300000,
220 .max_uV = 3300000,
221 .apply_uV = true,
222 .valid_modes_mask = REGULATOR_MODE_NORMAL
223 | REGULATOR_MODE_STANDBY,
224 .valid_ops_mask = REGULATOR_CHANGE_MODE
225 | REGULATOR_CHANGE_STATUS,
226 },
227};
228
229static struct regulator_init_data omap4_clk32kg_idata = {
230 .constraints = {
231 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
232 },
233};
234
235void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
236 u32 pdata_flags, u32 regulators_flags)
237{
238 if (!pmic_data->irq_base)
239 pmic_data->irq_base = TWL6030_IRQ_BASE;
240 if (!pmic_data->irq_end)
241 pmic_data->irq_end = TWL6030_IRQ_END;
242
243 /* Common platform data configurations */
244 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
245 pmic_data->usb = &omap4_usb_pdata;
246
247 /* Common regulator configurations */
248 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
249 pmic_data->vdac = &omap4_vdac_idata;
250
251 if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
252 pmic_data->vaux2 = &omap4_vaux2_idata;
253
254 if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
255 pmic_data->vaux3 = &omap4_vaux3_idata;
256
257 if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
258 pmic_data->vmmc = &omap4_vmmc_idata;
259
260 if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
261 pmic_data->vpp = &omap4_vpp_idata;
262
263 if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
264 pmic_data->vana = &omap4_vana_idata;
265
266 if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
267 pmic_data->vcxio = &omap4_vcxio_idata;
268
269 if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
270 pmic_data->vusb = &omap4_vusb_idata;
271
272 if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
273 !pmic_data->clk32kg)
274 pmic_data->clk32kg = &omap4_clk32kg_idata;
275}
276
277void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
278 u32 pdata_flags, u32 regulators_flags)
279{
280 if (!pmic_data->irq_base)
281 pmic_data->irq_base = TWL4030_IRQ_BASE;
282 if (!pmic_data->irq_end)
283 pmic_data->irq_end = TWL4030_IRQ_END;
284
285 /* Common platform data configurations */
286 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
287 pmic_data->usb = &omap3_usb_pdata;
288
289 if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
290 pmic_data->bci = &omap3_bci_pdata;
291
292 if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
293 pmic_data->madc = &omap3_madc_pdata;
294
295 if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->codec)
296 pmic_data->codec = &omap3_codec_pdata;
297
298 /* Common regulator configurations */
299 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
300 pmic_data->vdac = &omap3_vdac_idata;
301
302 if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
303 pmic_data->vpll2 = &omap3_vpll2_idata;
304}
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
new file mode 100644
index 000000000000..5e83a5bd37fb
--- /dev/null
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -0,0 +1,59 @@
1#ifndef __OMAP_PMIC_COMMON__
2#define __OMAP_PMIC_COMMON__
3
4#define TWL_COMMON_PDATA_USB (1 << 0)
5#define TWL_COMMON_PDATA_BCI (1 << 1)
6#define TWL_COMMON_PDATA_MADC (1 << 2)
7#define TWL_COMMON_PDATA_AUDIO (1 << 3)
8
9/* Common LDO regulators for TWL4030/TWL6030 */
10#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
11#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
12#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
13#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
14
15/* TWL6030 LDO regulators */
16#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
17#define TWL_COMMON_REGULATOR_VPP (1 << 5)
18#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
19#define TWL_COMMON_REGULATOR_VANA (1 << 7)
20#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
21#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
22#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
23
24/* TWL4030 LDO regulators */
25#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
26#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
27
28
29struct twl4030_platform_data;
30
31void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
32 struct twl4030_platform_data *pmic_data);
33
34static inline void omap2_pmic_init(const char *pmic_type,
35 struct twl4030_platform_data *pmic_data)
36{
37 omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
38}
39
40static inline void omap3_pmic_init(const char *pmic_type,
41 struct twl4030_platform_data *pmic_data)
42{
43 omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
44}
45
46static inline void omap4_pmic_init(const char *pmic_type,
47 struct twl4030_platform_data *pmic_data)
48{
49 /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
50 omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
51}
52
53void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
54 u32 pdata_flags, u32 regulators_flags);
55
56void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
57 u32 pdata_flags, u32 regulators_flags);
58
59#endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 49a4c75243fc..6e6735f04ee3 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -211,9 +211,6 @@ choice
211 depends on ARCH_OMAP 211 depends on ARCH_OMAP
212 default OMAP_PM_NOOP 212 default OMAP_PM_NOOP
213 213
214config OMAP_PM_NONE
215 bool "No PM layer"
216
217config OMAP_PM_NOOP 214config OMAP_PM_NOOP
218 bool "No-op/debug PM layer" 215 bool "No-op/debug PM layer"
219 216
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index f7fed6080190..c13bc3d3eb2c 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -126,7 +126,7 @@ static inline unsigned long long notrace _omap_32k_sched_clock(void)
126 return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); 126 return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
127} 127}
128 128
129#ifndef CONFIG_OMAP_MPU_TIMER 129#if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
130unsigned long long notrace sched_clock(void) 130unsigned long long notrace sched_clock(void)
131{ 131{
132 return _omap_32k_sched_clock(); 132 return _omap_32k_sched_clock();
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index ee9f6ebba29b..8dfb8186b2c2 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -41,127 +41,6 @@
41#include <plat/dmtimer.h> 41#include <plat/dmtimer.h>
42#include <mach/irqs.h> 42#include <mach/irqs.h>
43 43
44/* register offsets */
45#define _OMAP_TIMER_ID_OFFSET 0x00
46#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
47#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
48#define _OMAP_TIMER_STAT_OFFSET 0x18
49#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
50#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
51#define _OMAP_TIMER_CTRL_OFFSET 0x24
52#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
53#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
54#define OMAP_TIMER_CTRL_PT (1 << 12)
55#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
56#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
57#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
58#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
59#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
60#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
61#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
62#define OMAP_TIMER_CTRL_POSTED (1 << 2)
63#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
64#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
65#define _OMAP_TIMER_COUNTER_OFFSET 0x28
66#define _OMAP_TIMER_LOAD_OFFSET 0x2c
67#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
68#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
69#define WP_NONE 0 /* no write pending bit */
70#define WP_TCLR (1 << 0)
71#define WP_TCRR (1 << 1)
72#define WP_TLDR (1 << 2)
73#define WP_TTGR (1 << 3)
74#define WP_TMAR (1 << 4)
75#define WP_TPIR (1 << 5)
76#define WP_TNIR (1 << 6)
77#define WP_TCVR (1 << 7)
78#define WP_TOCR (1 << 8)
79#define WP_TOWR (1 << 9)
80#define _OMAP_TIMER_MATCH_OFFSET 0x38
81#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
82#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
83#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
84#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
85#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
86#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
87#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
88#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
89
90/* register offsets with the write pending bit encoded */
91#define WPSHIFT 16
92
93#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
94 | (WP_NONE << WPSHIFT))
95
96#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
97 | (WP_NONE << WPSHIFT))
98
99#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
100 | (WP_NONE << WPSHIFT))
101
102#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
103 | (WP_NONE << WPSHIFT))
104
105#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
106 | (WP_NONE << WPSHIFT))
107
108#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
109 | (WP_NONE << WPSHIFT))
110
111#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
112 | (WP_TCLR << WPSHIFT))
113
114#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
115 | (WP_TCRR << WPSHIFT))
116
117#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
118 | (WP_TLDR << WPSHIFT))
119
120#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
121 | (WP_TTGR << WPSHIFT))
122
123#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
124 | (WP_NONE << WPSHIFT))
125
126#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
127 | (WP_TMAR << WPSHIFT))
128
129#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
130 | (WP_NONE << WPSHIFT))
131
132#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
133 | (WP_NONE << WPSHIFT))
134
135#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
136 | (WP_NONE << WPSHIFT))
137
138#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
139 | (WP_TPIR << WPSHIFT))
140
141#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
142 | (WP_TNIR << WPSHIFT))
143
144#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
145 | (WP_TCVR << WPSHIFT))
146
147#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
148 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
149
150#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
151 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
152
153struct omap_dm_timer {
154 unsigned long phys_base;
155 int irq;
156#ifdef CONFIG_ARCH_OMAP2PLUS
157 struct clk *iclk, *fclk;
158#endif
159 void __iomem *io_base;
160 unsigned reserved:1;
161 unsigned enabled:1;
162 unsigned posted:1;
163};
164
165static int dm_timer_count; 44static int dm_timer_count;
166 45
167#ifdef CONFIG_ARCH_OMAP1 46#ifdef CONFIG_ARCH_OMAP1
@@ -291,11 +170,7 @@ static spinlock_t dm_timer_lock;
291 */ 170 */
292static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) 171static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
293{ 172{
294 if (timer->posted) 173 return __omap_dm_timer_read(timer->io_base, reg, timer->posted);
295 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
296 & (reg >> WPSHIFT))
297 cpu_relax();
298 return readl(timer->io_base + (reg & 0xff));
299} 174}
300 175
301/* 176/*
@@ -307,11 +182,7 @@ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
307static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, 182static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
308 u32 value) 183 u32 value)
309{ 184{
310 if (timer->posted) 185 __omap_dm_timer_write(timer->io_base, reg, value, timer->posted);
311 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
312 & (reg >> WPSHIFT))
313 cpu_relax();
314 writel(value, timer->io_base + (reg & 0xff));
315} 186}
316 187
317static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) 188static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -330,7 +201,7 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
330 201
331static void omap_dm_timer_reset(struct omap_dm_timer *timer) 202static void omap_dm_timer_reset(struct omap_dm_timer *timer)
332{ 203{
333 u32 l; 204 int autoidle = 0, wakeup = 0;
334 205
335 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) { 206 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
336 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 207 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
@@ -338,28 +209,21 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
338 } 209 }
339 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); 210 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
340 211
341 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
342 l |= 0x02 << 3; /* Set to smart-idle mode */
343 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
344
345 /* Enable autoidle on OMAP2 / OMAP3 */ 212 /* Enable autoidle on OMAP2 / OMAP3 */
346 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 213 if (cpu_is_omap24xx() || cpu_is_omap34xx())
347 l |= 0x1 << 0; 214 autoidle = 1;
348 215
349 /* 216 /*
350 * Enable wake-up on OMAP2 CPUs. 217 * Enable wake-up on OMAP2 CPUs.
351 */ 218 */
352 if (cpu_class_is_omap2()) 219 if (cpu_class_is_omap2())
353 l |= 1 << 2; 220 wakeup = 1;
354 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
355 221
356 /* Match hardware reset default of posted mode */ 222 __omap_dm_timer_reset(timer->io_base, autoidle, wakeup);
357 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
358 OMAP_TIMER_CTRL_POSTED);
359 timer->posted = 1; 223 timer->posted = 1;
360} 224}
361 225
362static void omap_dm_timer_prepare(struct omap_dm_timer *timer) 226void omap_dm_timer_prepare(struct omap_dm_timer *timer)
363{ 227{
364 omap_dm_timer_enable(timer); 228 omap_dm_timer_enable(timer);
365 omap_dm_timer_reset(timer); 229 omap_dm_timer_reset(timer);
@@ -531,25 +395,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
531 395
532void omap_dm_timer_stop(struct omap_dm_timer *timer) 396void omap_dm_timer_stop(struct omap_dm_timer *timer)
533{ 397{
534 u32 l; 398 unsigned long rate = 0;
535 399
536 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
537 if (l & OMAP_TIMER_CTRL_ST) {
538 l &= ~0x1;
539 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
540#ifdef CONFIG_ARCH_OMAP2PLUS 400#ifdef CONFIG_ARCH_OMAP2PLUS
541 /* Readback to make sure write has completed */ 401 rate = clk_get_rate(timer->fclk);
542 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
543 /*
544 * Wait for functional clock period x 3.5 to make sure that
545 * timer is stopped
546 */
547 udelay(3500000 / clk_get_rate(timer->fclk) + 1);
548#endif 402#endif
549 } 403
550 /* Ack possibly pending interrupt */ 404 __omap_dm_timer_stop(timer->io_base, timer->posted, rate);
551 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
552 OMAP_TIMER_INT_OVERFLOW);
553} 405}
554EXPORT_SYMBOL_GPL(omap_dm_timer_stop); 406EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
555 407
@@ -572,22 +424,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
572 424
573int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 425int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
574{ 426{
575 int ret = -EINVAL;
576
577 if (source < 0 || source >= 3) 427 if (source < 0 || source >= 3)
578 return -EINVAL; 428 return -EINVAL;
579 429
580 clk_disable(timer->fclk); 430 return __omap_dm_timer_set_source(timer->fclk,
581 ret = clk_set_parent(timer->fclk, dm_source_clocks[source]); 431 dm_source_clocks[source]);
582 clk_enable(timer->fclk);
583
584 /*
585 * When the functional clock disappears, too quick writes seem
586 * to cause an abort. XXX Is this still necessary?
587 */
588 __delay(300000);
589
590 return ret;
591} 432}
592EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); 433EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
593 434
@@ -625,8 +466,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
625 } 466 }
626 l |= OMAP_TIMER_CTRL_ST; 467 l |= OMAP_TIMER_CTRL_ST;
627 468
628 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); 469 __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted);
629 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
630} 470}
631EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); 471EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
632 472
@@ -679,8 +519,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
679void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, 519void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
680 unsigned int value) 520 unsigned int value)
681{ 521{
682 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); 522 __omap_dm_timer_int_enable(timer->io_base, value);
683 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
684} 523}
685EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); 524EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
686 525
@@ -696,17 +535,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
696 535
697void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 536void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
698{ 537{
699 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); 538 __omap_dm_timer_write_status(timer->io_base, value);
700} 539}
701EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); 540EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
702 541
703unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 542unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
704{ 543{
705 unsigned int l; 544 return __omap_dm_timer_read_counter(timer->io_base, timer->posted);
706
707 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
708
709 return l;
710} 545}
711EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); 546EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
712 547
@@ -737,7 +572,7 @@ int omap_dm_timers_active(void)
737} 572}
738EXPORT_SYMBOL_GPL(omap_dm_timers_active); 573EXPORT_SYMBOL_GPL(omap_dm_timers_active);
739 574
740int __init omap_dm_timer_init(void) 575static int __init omap_dm_timer_init(void)
741{ 576{
742 struct omap_dm_timer *timer; 577 struct omap_dm_timer *timer;
743 int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ 578 int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
@@ -790,8 +625,16 @@ int __init omap_dm_timer_init(void)
790 sprintf(clk_name, "gpt%d_fck", i + 1); 625 sprintf(clk_name, "gpt%d_fck", i + 1);
791 timer->fclk = clk_get(NULL, clk_name); 626 timer->fclk = clk_get(NULL, clk_name);
792 } 627 }
628
629 /* One or two timers may be set up early for sys_timer */
630 if (sys_timer_reserved & (1 << i)) {
631 timer->reserved = 1;
632 timer->posted = 1;
633 }
793#endif 634#endif
794 } 635 }
795 636
796 return 0; 637 return 0;
797} 638}
639
640arch_initcall(omap_dm_timer_init);
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 006e599c6613..f57e0649ab30 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -152,7 +152,7 @@ struct dpll_data {
152 u16 max_multiplier; 152 u16 max_multiplier;
153 u8 last_rounded_n; 153 u8 last_rounded_n;
154 u8 min_divider; 154 u8 min_divider;
155 u8 max_divider; 155 u16 max_divider;
156 u8 modes; 156 u8 modes;
157#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 157#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
158 void __iomem *autoidle_reg; 158 void __iomem *autoidle_reg;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 5288130be96e..4564cc697d7f 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -34,7 +34,11 @@
34struct sys_timer; 34struct sys_timer;
35 35
36extern void omap_map_common_io(void); 36extern void omap_map_common_io(void);
37extern struct sys_timer omap_timer; 37extern struct sys_timer omap1_timer;
38extern struct sys_timer omap2_timer;
39extern struct sys_timer omap3_timer;
40extern struct sys_timer omap3_secure_timer;
41extern struct sys_timer omap4_timer;
38extern bool omap_32k_timer_init(void); 42extern bool omap_32k_timer_init(void);
39extern int __init omap_init_clocksource_32k(void); 43extern int __init omap_init_clocksource_32k(void);
40extern unsigned long long notrace omap_32k_sched_clock(void); 44extern unsigned long long notrace omap_32k_sched_clock(void);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index d6c70d2f4030..eb5d16c60cd9 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -32,6 +32,10 @@
32 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 */ 33 */
34 34
35#include <linux/clk.h>
36#include <linux/delay.h>
37#include <linux/io.h>
38
35#ifndef __ASM_ARCH_DMTIMER_H 39#ifndef __ASM_ARCH_DMTIMER_H
36#define __ASM_ARCH_DMTIMER_H 40#define __ASM_ARCH_DMTIMER_H
37 41
@@ -56,12 +60,8 @@
56 */ 60 */
57#define OMAP_TIMER_IP_VERSION_1 0x1 61#define OMAP_TIMER_IP_VERSION_1 0x1
58struct omap_dm_timer; 62struct omap_dm_timer;
59extern struct omap_dm_timer *gptimer_wakeup;
60extern struct sys_timer omap_timer;
61struct clk; 63struct clk;
62 64
63int omap_dm_timer_init(void);
64
65struct omap_dm_timer *omap_dm_timer_request(void); 65struct omap_dm_timer *omap_dm_timer_request(void);
66struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); 66struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
67void omap_dm_timer_free(struct omap_dm_timer *timer); 67void omap_dm_timer_free(struct omap_dm_timer *timer);
@@ -93,5 +93,248 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value
93 93
94int omap_dm_timers_active(void); 94int omap_dm_timers_active(void);
95 95
96/*
97 * Do not use the defines below, they are not needed. They should be only
98 * used by dmtimer.c and sys_timer related code.
99 */
100
101/* register offsets */
102#define _OMAP_TIMER_ID_OFFSET 0x00
103#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
104#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
105#define _OMAP_TIMER_STAT_OFFSET 0x18
106#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
107#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
108#define _OMAP_TIMER_CTRL_OFFSET 0x24
109#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
110#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
111#define OMAP_TIMER_CTRL_PT (1 << 12)
112#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
113#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
114#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
115#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
116#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
117#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
118#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
119#define OMAP_TIMER_CTRL_POSTED (1 << 2)
120#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
121#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
122#define _OMAP_TIMER_COUNTER_OFFSET 0x28
123#define _OMAP_TIMER_LOAD_OFFSET 0x2c
124#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
125#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
126#define WP_NONE 0 /* no write pending bit */
127#define WP_TCLR (1 << 0)
128#define WP_TCRR (1 << 1)
129#define WP_TLDR (1 << 2)
130#define WP_TTGR (1 << 3)
131#define WP_TMAR (1 << 4)
132#define WP_TPIR (1 << 5)
133#define WP_TNIR (1 << 6)
134#define WP_TCVR (1 << 7)
135#define WP_TOCR (1 << 8)
136#define WP_TOWR (1 << 9)
137#define _OMAP_TIMER_MATCH_OFFSET 0x38
138#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
139#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
140#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
141#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
142#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
143#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
144#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
145#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
146
147/* register offsets with the write pending bit encoded */
148#define WPSHIFT 16
149
150#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
151 | (WP_NONE << WPSHIFT))
152
153#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
154 | (WP_NONE << WPSHIFT))
155
156#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
157 | (WP_NONE << WPSHIFT))
158
159#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
160 | (WP_NONE << WPSHIFT))
161
162#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
163 | (WP_NONE << WPSHIFT))
164
165#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
166 | (WP_NONE << WPSHIFT))
167
168#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
169 | (WP_TCLR << WPSHIFT))
170
171#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
172 | (WP_TCRR << WPSHIFT))
173
174#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
175 | (WP_TLDR << WPSHIFT))
176
177#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
178 | (WP_TTGR << WPSHIFT))
179
180#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
181 | (WP_NONE << WPSHIFT))
182
183#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
184 | (WP_TMAR << WPSHIFT))
185
186#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
187 | (WP_NONE << WPSHIFT))
188
189#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
190 | (WP_NONE << WPSHIFT))
191
192#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
193 | (WP_NONE << WPSHIFT))
194
195#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
196 | (WP_TPIR << WPSHIFT))
197
198#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
199 | (WP_TNIR << WPSHIFT))
200
201#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
202 | (WP_TCVR << WPSHIFT))
203
204#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
205 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
206
207#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
208 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
209
210struct omap_dm_timer {
211 unsigned long phys_base;
212 int irq;
213#ifdef CONFIG_ARCH_OMAP2PLUS
214 struct clk *iclk, *fclk;
215#endif
216 void __iomem *io_base;
217 unsigned long rate;
218 unsigned reserved:1;
219 unsigned enabled:1;
220 unsigned posted:1;
221};
222
223extern u32 sys_timer_reserved;
224void omap_dm_timer_prepare(struct omap_dm_timer *timer);
225
226static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
227 int posted)
228{
229 if (posted)
230 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
231 & (reg >> WPSHIFT))
232 cpu_relax();
233
234 return __raw_readl(base + (reg & 0xff));
235}
236
237static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
238 int posted)
239{
240 if (posted)
241 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
242 & (reg >> WPSHIFT))
243 cpu_relax();
244
245 __raw_writel(val, base + (reg & 0xff));
246}
247
248/* Assumes the source clock has been set by caller */
249static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
250 int wakeup)
251{
252 u32 l;
253
254 l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
255 l |= 0x02 << 3; /* Set to smart-idle mode */
256 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
257
258 if (autoidle)
259 l |= 0x1 << 0;
260
261 if (wakeup)
262 l |= 1 << 2;
263
264 __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
265
266 /* Match hardware reset default of posted mode */
267 __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
268 OMAP_TIMER_CTRL_POSTED, 0);
269}
270
271static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
272 struct clk *parent)
273{
274 int ret;
275
276 clk_disable(timer_fck);
277 ret = clk_set_parent(timer_fck, parent);
278 clk_enable(timer_fck);
279
280 /*
281 * When the functional clock disappears, too quick writes seem
282 * to cause an abort. XXX Is this still necessary?
283 */
284 __delay(300000);
285
286 return ret;
287}
288
289static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
290 unsigned long rate)
291{
292 u32 l;
293
294 l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
295 if (l & OMAP_TIMER_CTRL_ST) {
296 l &= ~0x1;
297 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
298#ifdef CONFIG_ARCH_OMAP2PLUS
299 /* Readback to make sure write has completed */
300 __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
301 /*
302 * Wait for functional clock period x 3.5 to make sure that
303 * timer is stopped
304 */
305 udelay(3500000 / rate + 1);
306#endif
307 }
308
309 /* Ack possibly pending interrupt */
310 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
311 OMAP_TIMER_INT_OVERFLOW, 0);
312}
313
314static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
315 unsigned int load, int posted)
316{
317 __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
318 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
319}
320
321static inline void __omap_dm_timer_int_enable(void __iomem *base,
322 unsigned int value)
323{
324 __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
325 __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
326}
327
328static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
329 int posted)
330{
331 return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
332}
333
334static inline void __omap_dm_timer_write_status(void __iomem *base,
335 unsigned int value)
336{
337 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
338}
96 339
97#endif /* __ASM_ARCH_DMTIMER_H */ 340#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 878d632c4092..7c22b9e10dc3 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -22,6 +22,7 @@
22#define __ASM__ARCH_OMAP_I2C_H 22#define __ASM__ARCH_OMAP_I2C_H
23 23
24#include <linux/i2c.h> 24#include <linux/i2c.h>
25#include <linux/i2c-omap.h>
25 26
26#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) 27#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
27extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 28extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -46,10 +47,13 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
46 */ 47 */
47struct omap_i2c_dev_attr { 48struct omap_i2c_dev_attr {
48 u8 fifo_depth; 49 u8 fifo_depth;
49 u8 flags; 50 u32 flags;
50}; 51};
51 52
52void __init omap1_i2c_mux_pins(int bus_id); 53void __init omap1_i2c_mux_pins(int bus_id);
53void __init omap2_i2c_mux_pins(int bus_id); 54void __init omap2_i2c_mux_pins(int bus_id);
54 55
56struct omap_hwmod;
57int omap_i2c_reset(struct omap_hwmod *oh);
58
55#endif /* __ASM__ARCH_OMAP_I2C_H */ 59#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 5a25098ea7ea..c88432005665 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,7 +428,11 @@
428#define INTCPS_NR_IRQS 96 428#define INTCPS_NR_IRQS 96
429 429
430#ifndef __ASSEMBLY__ 430#ifndef __ASSEMBLY__
431extern void omap_init_irq(void); 431extern void __iomem *omap_irq_base;
432void omap1_init_irq(void);
433void omap2_init_irq(void);
434void omap3_init_irq(void);
435void ti816x_init_irq(void);
432extern int omap_irq_pending(void); 436extern int omap_irq_pending(void);
433void omap_intc_save_context(void); 437void omap_intc_save_context(void);
434void omap_intc_restore_context(void); 438void omap_intc_restore_context(void);
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index f8f690ab2997..9882c657b2d4 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -24,7 +24,6 @@
24#ifndef __ASM_ARCH_OMAP_MCBSP_H 24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/completion.h>
28#include <linux/spinlock.h> 27#include <linux/spinlock.h>
29 28
30#include <mach/hardware.h> 29#include <mach/hardware.h>
@@ -34,7 +33,7 @@
34#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ 33#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
35static struct platform_device omap_mcbsp##port_nr = { \ 34static struct platform_device omap_mcbsp##port_nr = { \
36 .name = "omap-mcbsp-dai", \ 35 .name = "omap-mcbsp-dai", \
37 .id = OMAP_MCBSP##port_nr, \ 36 .id = port_nr - 1, \
38} 37}
39 38
40#define MCBSP_CONFIG_TYPE2 0x2 39#define MCBSP_CONFIG_TYPE2 0x2
@@ -333,18 +332,6 @@ struct omap_mcbsp_reg_cfg {
333}; 332};
334 333
335typedef enum { 334typedef enum {
336 OMAP_MCBSP1 = 0,
337 OMAP_MCBSP2,
338 OMAP_MCBSP3,
339 OMAP_MCBSP4,
340 OMAP_MCBSP5
341} omap_mcbsp_id;
342
343typedef int __bitwise omap_mcbsp_io_type_t;
344#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
345#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
346
347typedef enum {
348 OMAP_MCBSP_WORD_8 = 0, 335 OMAP_MCBSP_WORD_8 = 0,
349 OMAP_MCBSP_WORD_12, 336 OMAP_MCBSP_WORD_12,
350 OMAP_MCBSP_WORD_16, 337 OMAP_MCBSP_WORD_16,
@@ -353,38 +340,6 @@ typedef enum {
353 OMAP_MCBSP_WORD_32, 340 OMAP_MCBSP_WORD_32,
354} omap_mcbsp_word_length; 341} omap_mcbsp_word_length;
355 342
356typedef enum {
357 OMAP_MCBSP_CLK_RISING = 0,
358 OMAP_MCBSP_CLK_FALLING,
359} omap_mcbsp_clk_polarity;
360
361typedef enum {
362 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
363 OMAP_MCBSP_FS_ACTIVE_LOW,
364} omap_mcbsp_fs_polarity;
365
366typedef enum {
367 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
368 OMAP_MCBSP_CLK_STP_MODE_DELAY,
369} omap_mcbsp_clk_stp_mode;
370
371
372/******* SPI specific mode **********/
373typedef enum {
374 OMAP_MCBSP_SPI_MASTER = 0,
375 OMAP_MCBSP_SPI_SLAVE,
376} omap_mcbsp_spi_mode;
377
378struct omap_mcbsp_spi_cfg {
379 omap_mcbsp_spi_mode spi_mode;
380 omap_mcbsp_clk_polarity rx_clock_polarity;
381 omap_mcbsp_clk_polarity tx_clock_polarity;
382 omap_mcbsp_fs_polarity fsx_polarity;
383 u8 clk_div;
384 omap_mcbsp_clk_stp_mode clk_stp_mode;
385 omap_mcbsp_word_length word_length;
386};
387
388/* Platform specific configuration */ 343/* Platform specific configuration */
389struct omap_mcbsp_ops { 344struct omap_mcbsp_ops {
390 void (*request)(unsigned int); 345 void (*request)(unsigned int);
@@ -422,25 +377,13 @@ struct omap_mcbsp {
422 void __iomem *io_base; 377 void __iomem *io_base;
423 u8 id; 378 u8 id;
424 u8 free; 379 u8 free;
425 omap_mcbsp_word_length rx_word_length;
426 omap_mcbsp_word_length tx_word_length;
427 380
428 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
429 /* IRQ based TX/RX */
430 int rx_irq; 381 int rx_irq;
431 int tx_irq; 382 int tx_irq;
432 383
433 /* DMA stuff */ 384 /* DMA stuff */
434 u8 dma_rx_sync; 385 u8 dma_rx_sync;
435 short dma_rx_lch;
436 u8 dma_tx_sync; 386 u8 dma_tx_sync;
437 short dma_tx_lch;
438
439 /* Completion queues */
440 struct completion tx_irq_completion;
441 struct completion rx_irq_completion;
442 struct completion tx_dma_completion;
443 struct completion rx_dma_completion;
444 387
445 /* Protect the field .free, while checking if the mcbsp is in use */ 388 /* Protect the field .free, while checking if the mcbsp is in use */
446 spinlock_t lock; 389 spinlock_t lock;
@@ -499,24 +442,9 @@ int omap_mcbsp_request(unsigned int id);
499void omap_mcbsp_free(unsigned int id); 442void omap_mcbsp_free(unsigned int id);
500void omap_mcbsp_start(unsigned int id, int tx, int rx); 443void omap_mcbsp_start(unsigned int id, int tx, int rx);
501void omap_mcbsp_stop(unsigned int id, int tx, int rx); 444void omap_mcbsp_stop(unsigned int id, int tx, int rx);
502void omap_mcbsp_xmit_word(unsigned int id, u32 word);
503u32 omap_mcbsp_recv_word(unsigned int id);
504
505int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
506int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
507int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
508int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
509
510 445
511/* McBSP functional clock source changing function */ 446/* McBSP functional clock source changing function */
512extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); 447extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
513/* SPI specific API */
514void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
515
516/* Polled read/write functions */
517int omap_mcbsp_pollread(unsigned int id, u16 * buf);
518int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
519int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
520 448
521/* McBSP signal muxing API */ 449/* McBSP signal muxing API */
522void omap2_mcbsp1_mux_clkr_src(u8 mux); 450void omap2_mcbsp1_mux_clkr_src(u8 mux);
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index d86d1ecf0068..67fc5060183e 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -19,15 +19,11 @@ enum nand_io {
19}; 19};
20 20
21struct omap_nand_platform_data { 21struct omap_nand_platform_data {
22 unsigned int options;
23 int cs; 22 int cs;
24 int gpio_irq;
25 struct mtd_partition *parts; 23 struct mtd_partition *parts;
26 struct gpmc_timings *gpmc_t; 24 struct gpmc_timings *gpmc_t;
27 int nr_parts; 25 int nr_parts;
28 int (*nand_setup)(void); 26 bool dev_ready;
29 int (*dev_ready)(struct omap_nand_platform_data *);
30 int dma_channel;
31 int gpmc_irq; 27 int gpmc_irq;
32 enum nand_io xfer_type; 28 enum nand_io xfer_type;
33 unsigned long phys_base; 29 unsigned long phys_base;
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index c0a752053039..0840df813f4f 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -40,11 +40,7 @@
40 * framework starts. The "_if_" is to avoid name collisions with the 40 * framework starts. The "_if_" is to avoid name collisions with the
41 * PM idle-loop code. 41 * PM idle-loop code.
42 */ 42 */
43#ifdef CONFIG_OMAP_PM_NONE
44#define omap_pm_if_early_init() 0
45#else
46int __init omap_pm_if_early_init(void); 43int __init omap_pm_if_early_init(void);
47#endif
48 44
49/** 45/**
50 * omap_pm_if_init - OMAP PM init code called after clock fw init 46 * omap_pm_if_init - OMAP PM init code called after clock fw init
@@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void);
52 * The main initialization code. OPP tables are passed in here. The 48 * The main initialization code. OPP tables are passed in here. The
53 * "_if_" is to avoid name collisions with the PM idle-loop code. 49 * "_if_" is to avoid name collisions with the PM idle-loop code.
54 */ 50 */
55#ifdef CONFIG_OMAP_PM_NONE
56#define omap_pm_if_init() 0
57#else
58int __init omap_pm_if_init(void); 51int __init omap_pm_if_init(void);
59#endif
60 52
61/** 53/**
62 * omap_pm_if_exit - OMAP PM exit code 54 * omap_pm_if_exit - OMAP PM exit code
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1adea9c62984..fafdfe3c8d4e 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -77,7 +77,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
77#define HWMOD_IDLEMODE_FORCE (1 << 0) 77#define HWMOD_IDLEMODE_FORCE (1 << 0)
78#define HWMOD_IDLEMODE_NO (1 << 1) 78#define HWMOD_IDLEMODE_NO (1 << 1)
79#define HWMOD_IDLEMODE_SMART (1 << 2) 79#define HWMOD_IDLEMODE_SMART (1 << 2)
80/* Slave idle mode flag only */
81#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) 80#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
82 81
83/** 82/**
@@ -98,7 +97,7 @@ struct omap_hwmod_mux_info {
98/** 97/**
99 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod 98 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
100 * @name: name of the IRQ channel (module local name) 99 * @name: name of the IRQ channel (module local name)
101 * @irq_ch: IRQ channel ID 100 * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
102 * 101 *
103 * @name should be something short, e.g., "tx" or "rx". It is for use 102 * @name should be something short, e.g., "tx" or "rx". It is for use
104 * by platform_get_resource_byname(). It is defined locally to the 103 * by platform_get_resource_byname(). It is defined locally to the
@@ -106,13 +105,13 @@ struct omap_hwmod_mux_info {
106 */ 105 */
107struct omap_hwmod_irq_info { 106struct omap_hwmod_irq_info {
108 const char *name; 107 const char *name;
109 u16 irq; 108 s16 irq;
110}; 109};
111 110
112/** 111/**
113 * struct omap_hwmod_dma_info - DMA channels used by the hwmod 112 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
114 * @name: name of the DMA channel (module local name) 113 * @name: name of the DMA channel (module local name)
115 * @dma_req: DMA request ID 114 * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
116 * 115 *
117 * @name should be something short, e.g., "tx" or "rx". It is for use 116 * @name should be something short, e.g., "tx" or "rx". It is for use
118 * by platform_get_resource_byname(). It is defined locally to the 117 * by platform_get_resource_byname(). It is defined locally to the
@@ -120,7 +119,7 @@ struct omap_hwmod_irq_info {
120 */ 119 */
121struct omap_hwmod_dma_info { 120struct omap_hwmod_dma_info {
122 const char *name; 121 const char *name;
123 u16 dma_req; 122 s16 dma_req;
124}; 123};
125 124
126/** 125/**
@@ -220,7 +219,6 @@ struct omap_hwmod_addr_space {
220 * @clk: interface clock: OMAP clock name 219 * @clk: interface clock: OMAP clock name
221 * @_clk: pointer to the interface struct clk (filled in at runtime) 220 * @_clk: pointer to the interface struct clk (filled in at runtime)
222 * @fw: interface firewall data 221 * @fw: interface firewall data
223 * @addr_cnt: ARRAY_SIZE(@addr)
224 * @width: OCP data width 222 * @width: OCP data width
225 * @user: initiators using this interface (see OCP_USER_* macros above) 223 * @user: initiators using this interface (see OCP_USER_* macros above)
226 * @flags: OCP interface flags (see OCPIF_* macros above) 224 * @flags: OCP interface flags (see OCPIF_* macros above)
@@ -239,7 +237,6 @@ struct omap_hwmod_ocp_if {
239 union { 237 union {
240 struct omap_hwmod_omap2_firewall omap2; 238 struct omap_hwmod_omap2_firewall omap2;
241 } fw; 239 } fw;
242 u8 addr_cnt;
243 u8 width; 240 u8 width;
244 u8 user; 241 u8 user;
245 u8 flags; 242 u8 flags;
@@ -258,6 +255,7 @@ struct omap_hwmod_ocp_if {
258#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) 255#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
259#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) 256#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
260#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) 257#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
258#define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
261 259
262/* omap_hwmod_sysconfig.sysc_flags capability flags */ 260/* omap_hwmod_sysconfig.sysc_flags capability flags */
263#define SYSC_HAS_AUTOIDLE (1 << 0) 261#define SYSC_HAS_AUTOIDLE (1 << 0)
@@ -468,8 +466,8 @@ struct omap_hwmod_class {
468 * @name: name of the hwmod 466 * @name: name of the hwmod
469 * @class: struct omap_hwmod_class * to the class of this hwmod 467 * @class: struct omap_hwmod_class * to the class of this hwmod
470 * @od: struct omap_device currently associated with this hwmod (internal use) 468 * @od: struct omap_device currently associated with this hwmod (internal use)
471 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) 469 * @mpu_irqs: ptr to an array of MPU IRQs
472 * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) 470 * @sdma_reqs: ptr to an array of System DMA request IDs
473 * @prcm: PRCM data pertaining to this hwmod 471 * @prcm: PRCM data pertaining to this hwmod
474 * @main_clk: main clock: OMAP clock name 472 * @main_clk: main clock: OMAP clock name
475 * @_clk: pointer to the main struct clk (filled in at runtime) 473 * @_clk: pointer to the main struct clk (filled in at runtime)
@@ -482,8 +480,6 @@ struct omap_hwmod_class {
482 * @_sysc_cache: internal-use hwmod flags 480 * @_sysc_cache: internal-use hwmod flags
483 * @_mpu_rt_va: cached register target start address (internal use) 481 * @_mpu_rt_va: cached register target start address (internal use)
484 * @_mpu_port_index: cached MPU register target slave ID (internal use) 482 * @_mpu_port_index: cached MPU register target slave ID (internal use)
485 * @mpu_irqs_cnt: number of @mpu_irqs
486 * @sdma_reqs_cnt: number of @sdma_reqs
487 * @opt_clks_cnt: number of @opt_clks 483 * @opt_clks_cnt: number of @opt_clks
488 * @master_cnt: number of @master entries 484 * @master_cnt: number of @master entries
489 * @slaves_cnt: number of @slave entries 485 * @slaves_cnt: number of @slave entries
@@ -531,8 +527,6 @@ struct omap_hwmod {
531 u16 flags; 527 u16 flags;
532 u8 _mpu_port_index; 528 u8 _mpu_port_index;
533 u8 response_lat; 529 u8 response_lat;
534 u8 mpu_irqs_cnt;
535 u8 sdma_reqs_cnt;
536 u8 rst_lines_cnt; 530 u8 rst_lines_cnt;
537 u8 opt_clks_cnt; 531 u8 opt_clks_cnt;
538 u8 masters_cnt; 532 u8 masters_cnt;
@@ -572,6 +566,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
572 566
573void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); 567void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
574u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); 568u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
569int omap_hwmod_softreset(struct omap_hwmod *oh);
575 570
576int omap_hwmod_count_resources(struct omap_hwmod *oh); 571int omap_hwmod_count_resources(struct omap_hwmod *oh);
577int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); 572int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 5587acf0eb2c..3c1fbdc92468 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -16,8 +16,6 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/wait.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h> 19#include <linux/interrupt.h>
22#include <linux/err.h> 20#include <linux/err.h>
23#include <linux/clk.h> 21#include <linux/clk.h>
@@ -25,7 +23,6 @@
25#include <linux/io.h> 23#include <linux/io.h>
26#include <linux/slab.h> 24#include <linux/slab.h>
27 25
28#include <plat/dma.h>
29#include <plat/mcbsp.h> 26#include <plat/mcbsp.h>
30#include <plat/omap_device.h> 27#include <plat/omap_device.h>
31#include <linux/pm_runtime.h> 28#include <linux/pm_runtime.h>
@@ -136,8 +133,6 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
136 irqst_spcr2); 133 irqst_spcr2);
137 /* Writing zero to XSYNC_ERR clears the IRQ */ 134 /* Writing zero to XSYNC_ERR clears the IRQ */
138 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2)); 135 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
139 } else {
140 complete(&mcbsp_tx->tx_irq_completion);
141 } 136 }
142 137
143 return IRQ_HANDLED; 138 return IRQ_HANDLED;
@@ -156,41 +151,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
156 irqst_spcr1); 151 irqst_spcr1);
157 /* Writing zero to RSYNC_ERR clears the IRQ */ 152 /* Writing zero to RSYNC_ERR clears the IRQ */
158 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1)); 153 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
159 } else {
160 complete(&mcbsp_rx->rx_irq_completion);
161 } 154 }
162 155
163 return IRQ_HANDLED; 156 return IRQ_HANDLED;
164} 157}
165 158
166static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
167{
168 struct omap_mcbsp *mcbsp_dma_tx = data;
169
170 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
171 MCBSP_READ(mcbsp_dma_tx, SPCR2));
172
173 /* We can free the channels */
174 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
175 mcbsp_dma_tx->dma_tx_lch = -1;
176
177 complete(&mcbsp_dma_tx->tx_dma_completion);
178}
179
180static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
181{
182 struct omap_mcbsp *mcbsp_dma_rx = data;
183
184 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
185 MCBSP_READ(mcbsp_dma_rx, SPCR2));
186
187 /* We can free the channels */
188 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
189 mcbsp_dma_rx->dma_rx_lch = -1;
190
191 complete(&mcbsp_dma_rx->rx_dma_completion);
192}
193
194/* 159/*
195 * omap_mcbsp_config simply write a config to the 160 * omap_mcbsp_config simply write a config to the
196 * appropriate McBSP. 161 * appropriate McBSP.
@@ -758,37 +723,6 @@ static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
758static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {} 723static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
759#endif 724#endif
760 725
761/*
762 * We can choose between IRQ based or polled IO.
763 * This needs to be called before omap_mcbsp_request().
764 */
765int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
766{
767 struct omap_mcbsp *mcbsp;
768
769 if (!omap_mcbsp_check_valid_id(id)) {
770 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
771 return -ENODEV;
772 }
773 mcbsp = id_to_mcbsp_ptr(id);
774
775 spin_lock(&mcbsp->lock);
776
777 if (!mcbsp->free) {
778 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
779 mcbsp->id);
780 spin_unlock(&mcbsp->lock);
781 return -EINVAL;
782 }
783
784 mcbsp->io_type = io_type;
785
786 spin_unlock(&mcbsp->lock);
787
788 return 0;
789}
790EXPORT_SYMBOL(omap_mcbsp_set_io_type);
791
792int omap_mcbsp_request(unsigned int id) 726int omap_mcbsp_request(unsigned int id)
793{ 727{
794 struct omap_mcbsp *mcbsp; 728 struct omap_mcbsp *mcbsp;
@@ -833,29 +767,24 @@ int omap_mcbsp_request(unsigned int id)
833 MCBSP_WRITE(mcbsp, SPCR1, 0); 767 MCBSP_WRITE(mcbsp, SPCR1, 0);
834 MCBSP_WRITE(mcbsp, SPCR2, 0); 768 MCBSP_WRITE(mcbsp, SPCR2, 0);
835 769
836 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { 770 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
837 /* We need to get IRQs here */ 771 0, "McBSP", (void *)mcbsp);
838 init_completion(&mcbsp->tx_irq_completion); 772 if (err != 0) {
839 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 773 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
840 0, "McBSP", (void *)mcbsp); 774 "for McBSP%d\n", mcbsp->tx_irq,
775 mcbsp->id);
776 goto err_clk_disable;
777 }
778
779 if (mcbsp->rx_irq) {
780 err = request_irq(mcbsp->rx_irq,
781 omap_mcbsp_rx_irq_handler,
782 0, "McBSP", (void *)mcbsp);
841 if (err != 0) { 783 if (err != 0) {
842 dev_err(mcbsp->dev, "Unable to request TX IRQ %d " 784 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
843 "for McBSP%d\n", mcbsp->tx_irq, 785 "for McBSP%d\n", mcbsp->rx_irq,
844 mcbsp->id); 786 mcbsp->id);
845 goto err_clk_disable; 787 goto err_free_irq;
846 }
847
848 if (mcbsp->rx_irq) {
849 init_completion(&mcbsp->rx_irq_completion);
850 err = request_irq(mcbsp->rx_irq,
851 omap_mcbsp_rx_irq_handler,
852 0, "McBSP", (void *)mcbsp);
853 if (err != 0) {
854 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
855 "for McBSP%d\n", mcbsp->rx_irq,
856 mcbsp->id);
857 goto err_free_irq;
858 }
859 } 788 }
860 } 789 }
861 790
@@ -901,12 +830,9 @@ void omap_mcbsp_free(unsigned int id)
901 830
902 pm_runtime_put_sync(mcbsp->dev); 831 pm_runtime_put_sync(mcbsp->dev);
903 832
904 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { 833 if (mcbsp->rx_irq)
905 /* Free IRQs */ 834 free_irq(mcbsp->rx_irq, (void *)mcbsp);
906 if (mcbsp->rx_irq) 835 free_irq(mcbsp->tx_irq, (void *)mcbsp);
907 free_irq(mcbsp->rx_irq, (void *)mcbsp);
908 free_irq(mcbsp->tx_irq, (void *)mcbsp);
909 }
910 836
911 reg_cache = mcbsp->reg_cache; 837 reg_cache = mcbsp->reg_cache;
912 838
@@ -943,9 +869,6 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
943 if (cpu_is_omap34xx()) 869 if (cpu_is_omap34xx())
944 omap_st_start(mcbsp); 870 omap_st_start(mcbsp);
945 871
946 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
947 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
948
949 /* Only enable SRG, if McBSP is master */ 872 /* Only enable SRG, if McBSP is master */
950 w = MCBSP_READ_CACHE(mcbsp, PCR0); 873 w = MCBSP_READ_CACHE(mcbsp, PCR0);
951 if (w & (FSXM | FSRM | CLKXM | CLKRM)) 874 if (w & (FSXM | FSRM | CLKXM | CLKRM))
@@ -1043,485 +966,6 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
1043} 966}
1044EXPORT_SYMBOL(omap_mcbsp_stop); 967EXPORT_SYMBOL(omap_mcbsp_stop);
1045 968
1046/* polled mcbsp i/o operations */
1047int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
1048{
1049 struct omap_mcbsp *mcbsp;
1050
1051 if (!omap_mcbsp_check_valid_id(id)) {
1052 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1053 return -ENODEV;
1054 }
1055
1056 mcbsp = id_to_mcbsp_ptr(id);
1057
1058 MCBSP_WRITE(mcbsp, DXR1, buf);
1059 /* if frame sync error - clear the error */
1060 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1061 /* clear error */
1062 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1063 /* resend */
1064 return -1;
1065 } else {
1066 /* wait for transmit confirmation */
1067 int attemps = 0;
1068 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1069 if (attemps++ > 1000) {
1070 MCBSP_WRITE(mcbsp, SPCR2,
1071 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1072 (~XRST));
1073 udelay(10);
1074 MCBSP_WRITE(mcbsp, SPCR2,
1075 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1076 (XRST));
1077 udelay(10);
1078 dev_err(mcbsp->dev, "Could not write to"
1079 " McBSP%d Register\n", mcbsp->id);
1080 return -2;
1081 }
1082 }
1083 }
1084
1085 return 0;
1086}
1087EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1088
1089int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1090{
1091 struct omap_mcbsp *mcbsp;
1092
1093 if (!omap_mcbsp_check_valid_id(id)) {
1094 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1095 return -ENODEV;
1096 }
1097 mcbsp = id_to_mcbsp_ptr(id);
1098
1099 /* if frame sync error - clear the error */
1100 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1101 /* clear error */
1102 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1103 /* resend */
1104 return -1;
1105 } else {
1106 /* wait for receive confirmation */
1107 int attemps = 0;
1108 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1109 if (attemps++ > 1000) {
1110 MCBSP_WRITE(mcbsp, SPCR1,
1111 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1112 (~RRST));
1113 udelay(10);
1114 MCBSP_WRITE(mcbsp, SPCR1,
1115 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1116 (RRST));
1117 udelay(10);
1118 dev_err(mcbsp->dev, "Could not read from"
1119 " McBSP%d Register\n", mcbsp->id);
1120 return -2;
1121 }
1122 }
1123 }
1124 *buf = MCBSP_READ(mcbsp, DRR1);
1125
1126 return 0;
1127}
1128EXPORT_SYMBOL(omap_mcbsp_pollread);
1129
1130/*
1131 * IRQ based word transmission.
1132 */
1133void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1134{
1135 struct omap_mcbsp *mcbsp;
1136 omap_mcbsp_word_length word_length;
1137
1138 if (!omap_mcbsp_check_valid_id(id)) {
1139 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1140 return;
1141 }
1142
1143 mcbsp = id_to_mcbsp_ptr(id);
1144 word_length = mcbsp->tx_word_length;
1145
1146 wait_for_completion(&mcbsp->tx_irq_completion);
1147
1148 if (word_length > OMAP_MCBSP_WORD_16)
1149 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1150 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1151}
1152EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1153
1154u32 omap_mcbsp_recv_word(unsigned int id)
1155{
1156 struct omap_mcbsp *mcbsp;
1157 u16 word_lsb, word_msb = 0;
1158 omap_mcbsp_word_length word_length;
1159
1160 if (!omap_mcbsp_check_valid_id(id)) {
1161 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1162 return -ENODEV;
1163 }
1164 mcbsp = id_to_mcbsp_ptr(id);
1165
1166 word_length = mcbsp->rx_word_length;
1167
1168 wait_for_completion(&mcbsp->rx_irq_completion);
1169
1170 if (word_length > OMAP_MCBSP_WORD_16)
1171 word_msb = MCBSP_READ(mcbsp, DRR2);
1172 word_lsb = MCBSP_READ(mcbsp, DRR1);
1173
1174 return (word_lsb | (word_msb << 16));
1175}
1176EXPORT_SYMBOL(omap_mcbsp_recv_word);
1177
1178int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1179{
1180 struct omap_mcbsp *mcbsp;
1181 omap_mcbsp_word_length tx_word_length;
1182 omap_mcbsp_word_length rx_word_length;
1183 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1184
1185 if (!omap_mcbsp_check_valid_id(id)) {
1186 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1187 return -ENODEV;
1188 }
1189 mcbsp = id_to_mcbsp_ptr(id);
1190 tx_word_length = mcbsp->tx_word_length;
1191 rx_word_length = mcbsp->rx_word_length;
1192
1193 if (tx_word_length != rx_word_length)
1194 return -EINVAL;
1195
1196 /* First we wait for the transmitter to be ready */
1197 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1198 while (!(spcr2 & XRDY)) {
1199 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1200 if (attempts++ > 1000) {
1201 /* We must reset the transmitter */
1202 MCBSP_WRITE(mcbsp, SPCR2,
1203 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1204 udelay(10);
1205 MCBSP_WRITE(mcbsp, SPCR2,
1206 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1207 udelay(10);
1208 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1209 "ready\n", mcbsp->id);
1210 return -EAGAIN;
1211 }
1212 }
1213
1214 /* Now we can push the data */
1215 if (tx_word_length > OMAP_MCBSP_WORD_16)
1216 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1217 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1218
1219 /* We wait for the receiver to be ready */
1220 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1221 while (!(spcr1 & RRDY)) {
1222 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1223 if (attempts++ > 1000) {
1224 /* We must reset the receiver */
1225 MCBSP_WRITE(mcbsp, SPCR1,
1226 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1227 udelay(10);
1228 MCBSP_WRITE(mcbsp, SPCR1,
1229 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1230 udelay(10);
1231 dev_err(mcbsp->dev, "McBSP%d receiver not "
1232 "ready\n", mcbsp->id);
1233 return -EAGAIN;
1234 }
1235 }
1236
1237 /* Receiver is ready, let's read the dummy data */
1238 if (rx_word_length > OMAP_MCBSP_WORD_16)
1239 word_msb = MCBSP_READ(mcbsp, DRR2);
1240 word_lsb = MCBSP_READ(mcbsp, DRR1);
1241
1242 return 0;
1243}
1244EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1245
1246int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1247{
1248 struct omap_mcbsp *mcbsp;
1249 u32 clock_word = 0;
1250 omap_mcbsp_word_length tx_word_length;
1251 omap_mcbsp_word_length rx_word_length;
1252 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1253
1254 if (!omap_mcbsp_check_valid_id(id)) {
1255 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1256 return -ENODEV;
1257 }
1258
1259 mcbsp = id_to_mcbsp_ptr(id);
1260
1261 tx_word_length = mcbsp->tx_word_length;
1262 rx_word_length = mcbsp->rx_word_length;
1263
1264 if (tx_word_length != rx_word_length)
1265 return -EINVAL;
1266
1267 /* First we wait for the transmitter to be ready */
1268 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1269 while (!(spcr2 & XRDY)) {
1270 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1271 if (attempts++ > 1000) {
1272 /* We must reset the transmitter */
1273 MCBSP_WRITE(mcbsp, SPCR2,
1274 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1275 udelay(10);
1276 MCBSP_WRITE(mcbsp, SPCR2,
1277 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1278 udelay(10);
1279 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1280 "ready\n", mcbsp->id);
1281 return -EAGAIN;
1282 }
1283 }
1284
1285 /* We first need to enable the bus clock */
1286 if (tx_word_length > OMAP_MCBSP_WORD_16)
1287 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1288 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1289
1290 /* We wait for the receiver to be ready */
1291 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1292 while (!(spcr1 & RRDY)) {
1293 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1294 if (attempts++ > 1000) {
1295 /* We must reset the receiver */
1296 MCBSP_WRITE(mcbsp, SPCR1,
1297 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1298 udelay(10);
1299 MCBSP_WRITE(mcbsp, SPCR1,
1300 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1301 udelay(10);
1302 dev_err(mcbsp->dev, "McBSP%d receiver not "
1303 "ready\n", mcbsp->id);
1304 return -EAGAIN;
1305 }
1306 }
1307
1308 /* Receiver is ready, there is something for us */
1309 if (rx_word_length > OMAP_MCBSP_WORD_16)
1310 word_msb = MCBSP_READ(mcbsp, DRR2);
1311 word_lsb = MCBSP_READ(mcbsp, DRR1);
1312
1313 word[0] = (word_lsb | (word_msb << 16));
1314
1315 return 0;
1316}
1317EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1318
1319/*
1320 * Simple DMA based buffer rx/tx routines.
1321 * Nothing fancy, just a single buffer tx/rx through DMA.
1322 * The DMA resources are released once the transfer is done.
1323 * For anything fancier, you should use your own customized DMA
1324 * routines and callbacks.
1325 */
1326int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1327 unsigned int length)
1328{
1329 struct omap_mcbsp *mcbsp;
1330 int dma_tx_ch;
1331 int src_port = 0;
1332 int dest_port = 0;
1333 int sync_dev = 0;
1334
1335 if (!omap_mcbsp_check_valid_id(id)) {
1336 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1337 return -ENODEV;
1338 }
1339 mcbsp = id_to_mcbsp_ptr(id);
1340
1341 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1342 omap_mcbsp_tx_dma_callback,
1343 mcbsp,
1344 &dma_tx_ch)) {
1345 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1346 "McBSP%d TX. Trying IRQ based TX\n",
1347 mcbsp->id);
1348 return -EAGAIN;
1349 }
1350 mcbsp->dma_tx_lch = dma_tx_ch;
1351
1352 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1353 dma_tx_ch);
1354
1355 init_completion(&mcbsp->tx_dma_completion);
1356
1357 if (cpu_class_is_omap1()) {
1358 src_port = OMAP_DMA_PORT_TIPB;
1359 dest_port = OMAP_DMA_PORT_EMIFF;
1360 }
1361 if (cpu_class_is_omap2())
1362 sync_dev = mcbsp->dma_tx_sync;
1363
1364 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1365 OMAP_DMA_DATA_TYPE_S16,
1366 length >> 1, 1,
1367 OMAP_DMA_SYNC_ELEMENT,
1368 sync_dev, 0);
1369
1370 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1371 src_port,
1372 OMAP_DMA_AMODE_CONSTANT,
1373 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1374 0, 0);
1375
1376 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1377 dest_port,
1378 OMAP_DMA_AMODE_POST_INC,
1379 buffer,
1380 0, 0);
1381
1382 omap_start_dma(mcbsp->dma_tx_lch);
1383 wait_for_completion(&mcbsp->tx_dma_completion);
1384
1385 return 0;
1386}
1387EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1388
1389int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1390 unsigned int length)
1391{
1392 struct omap_mcbsp *mcbsp;
1393 int dma_rx_ch;
1394 int src_port = 0;
1395 int dest_port = 0;
1396 int sync_dev = 0;
1397
1398 if (!omap_mcbsp_check_valid_id(id)) {
1399 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1400 return -ENODEV;
1401 }
1402 mcbsp = id_to_mcbsp_ptr(id);
1403
1404 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1405 omap_mcbsp_rx_dma_callback,
1406 mcbsp,
1407 &dma_rx_ch)) {
1408 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1409 "McBSP%d RX. Trying IRQ based RX\n",
1410 mcbsp->id);
1411 return -EAGAIN;
1412 }
1413 mcbsp->dma_rx_lch = dma_rx_ch;
1414
1415 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1416 dma_rx_ch);
1417
1418 init_completion(&mcbsp->rx_dma_completion);
1419
1420 if (cpu_class_is_omap1()) {
1421 src_port = OMAP_DMA_PORT_TIPB;
1422 dest_port = OMAP_DMA_PORT_EMIFF;
1423 }
1424 if (cpu_class_is_omap2())
1425 sync_dev = mcbsp->dma_rx_sync;
1426
1427 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1428 OMAP_DMA_DATA_TYPE_S16,
1429 length >> 1, 1,
1430 OMAP_DMA_SYNC_ELEMENT,
1431 sync_dev, 0);
1432
1433 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1434 src_port,
1435 OMAP_DMA_AMODE_CONSTANT,
1436 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1437 0, 0);
1438
1439 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1440 dest_port,
1441 OMAP_DMA_AMODE_POST_INC,
1442 buffer,
1443 0, 0);
1444
1445 omap_start_dma(mcbsp->dma_rx_lch);
1446 wait_for_completion(&mcbsp->rx_dma_completion);
1447
1448 return 0;
1449}
1450EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1451
1452/*
1453 * SPI wrapper.
1454 * Since SPI setup is much simpler than the generic McBSP one,
1455 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1456 * Once this is done, you can call omap_mcbsp_start().
1457 */
1458void omap_mcbsp_set_spi_mode(unsigned int id,
1459 const struct omap_mcbsp_spi_cfg *spi_cfg)
1460{
1461 struct omap_mcbsp *mcbsp;
1462 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1463
1464 if (!omap_mcbsp_check_valid_id(id)) {
1465 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1466 return;
1467 }
1468 mcbsp = id_to_mcbsp_ptr(id);
1469
1470 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1471
1472 /* SPI has only one frame */
1473 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1474 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1475
1476 /* Clock stop mode */
1477 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1478 mcbsp_cfg.spcr1 |= (1 << 12);
1479 else
1480 mcbsp_cfg.spcr1 |= (3 << 11);
1481
1482 /* Set clock parities */
1483 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1484 mcbsp_cfg.pcr0 |= CLKRP;
1485 else
1486 mcbsp_cfg.pcr0 &= ~CLKRP;
1487
1488 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1489 mcbsp_cfg.pcr0 &= ~CLKXP;
1490 else
1491 mcbsp_cfg.pcr0 |= CLKXP;
1492
1493 /* Set SCLKME to 0 and CLKSM to 1 */
1494 mcbsp_cfg.pcr0 &= ~SCLKME;
1495 mcbsp_cfg.srgr2 |= CLKSM;
1496
1497 /* Set FSXP */
1498 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1499 mcbsp_cfg.pcr0 &= ~FSXP;
1500 else
1501 mcbsp_cfg.pcr0 |= FSXP;
1502
1503 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1504 mcbsp_cfg.pcr0 |= CLKXM;
1505 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1506 mcbsp_cfg.pcr0 |= FSXM;
1507 mcbsp_cfg.srgr2 &= ~FSGM;
1508 mcbsp_cfg.xcr2 |= XDATDLY(1);
1509 mcbsp_cfg.rcr2 |= RDATDLY(1);
1510 } else {
1511 mcbsp_cfg.pcr0 &= ~CLKXM;
1512 mcbsp_cfg.srgr1 |= CLKGDV(1);
1513 mcbsp_cfg.pcr0 &= ~FSXM;
1514 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1515 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1516 }
1517
1518 mcbsp_cfg.xcr2 &= ~XPHASE;
1519 mcbsp_cfg.rcr2 &= ~RPHASE;
1520
1521 omap_mcbsp_config(id, &mcbsp_cfg);
1522}
1523EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1524
1525#ifdef CONFIG_ARCH_OMAP3 969#ifdef CONFIG_ARCH_OMAP3
1526#define max_thres(m) (mcbsp->pdata->buffer_size) 970#define max_thres(m) (mcbsp->pdata->buffer_size)
1527#define valid_threshold(m, val) ((val) <= max_thres(m)) 971#define valid_threshold(m, val) ((val) <= max_thres(m))
@@ -1833,8 +1277,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1833 spin_lock_init(&mcbsp->lock); 1277 spin_lock_init(&mcbsp->lock);
1834 mcbsp->id = id + 1; 1278 mcbsp->id = id + 1;
1835 mcbsp->free = true; 1279 mcbsp->free = true;
1836 mcbsp->dma_tx_lch = -1;
1837 mcbsp->dma_rx_lch = -1;
1838 1280
1839 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 1281 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1840 if (!res) { 1282 if (!res) {
@@ -1860,9 +1302,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1860 else 1302 else
1861 mcbsp->phys_dma_base = res->start; 1303 mcbsp->phys_dma_base = res->start;
1862 1304
1863 /* Default I/O is IRQ based */
1864 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1865
1866 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); 1305 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1867 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); 1306 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1868 1307
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index a37b8eb65b76..c8b9cd1716ba 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -84,6 +84,7 @@
84#include <linux/io.h> 84#include <linux/io.h>
85#include <linux/clk.h> 85#include <linux/clk.h>
86#include <linux/clkdev.h> 86#include <linux/clkdev.h>
87#include <linux/pm_runtime.h>
87 88
88#include <plat/omap_device.h> 89#include <plat/omap_device.h>
89#include <plat/omap_hwmod.h> 90#include <plat/omap_hwmod.h>
@@ -235,11 +236,6 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
235 return 0; 236 return 0;
236} 237}
237 238
238static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
239{
240 return container_of(pdev, struct omap_device, pdev);
241}
242
243/** 239/**
244 * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks 240 * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
245 * @od: struct omap_device *od 241 * @od: struct omap_device *od
@@ -315,7 +311,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
315 struct omap_device *od; 311 struct omap_device *od;
316 u32 ret = 0; 312 u32 ret = 0;
317 313
318 od = _find_by_pdev(pdev); 314 od = to_omap_device(pdev);
319 315
320 if (od->hwmods_cnt) 316 if (od->hwmods_cnt)
321 ret = omap_hwmod_get_context_loss_count(od->hwmods[0]); 317 ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
@@ -539,20 +535,34 @@ int omap_early_device_register(struct omap_device *od)
539static int _od_runtime_suspend(struct device *dev) 535static int _od_runtime_suspend(struct device *dev)
540{ 536{
541 struct platform_device *pdev = to_platform_device(dev); 537 struct platform_device *pdev = to_platform_device(dev);
538 int ret;
539
540 ret = pm_generic_runtime_suspend(dev);
541
542 if (!ret)
543 omap_device_idle(pdev);
542 544
543 return omap_device_idle(pdev); 545 return ret;
546}
547
548static int _od_runtime_idle(struct device *dev)
549{
550 return pm_generic_runtime_idle(dev);
544} 551}
545 552
546static int _od_runtime_resume(struct device *dev) 553static int _od_runtime_resume(struct device *dev)
547{ 554{
548 struct platform_device *pdev = to_platform_device(dev); 555 struct platform_device *pdev = to_platform_device(dev);
549 556
550 return omap_device_enable(pdev); 557 omap_device_enable(pdev);
558
559 return pm_generic_runtime_resume(dev);
551} 560}
552 561
553static struct dev_power_domain omap_device_power_domain = { 562static struct dev_power_domain omap_device_power_domain = {
554 .ops = { 563 .ops = {
555 .runtime_suspend = _od_runtime_suspend, 564 .runtime_suspend = _od_runtime_suspend,
565 .runtime_idle = _od_runtime_idle,
556 .runtime_resume = _od_runtime_resume, 566 .runtime_resume = _od_runtime_resume,
557 USE_PLATFORM_PM_SLEEP_OPS 567 USE_PLATFORM_PM_SLEEP_OPS
558 } 568 }
@@ -596,7 +606,7 @@ int omap_device_enable(struct platform_device *pdev)
596 int ret; 606 int ret;
597 struct omap_device *od; 607 struct omap_device *od;
598 608
599 od = _find_by_pdev(pdev); 609 od = to_omap_device(pdev);
600 610
601 if (od->_state == OMAP_DEVICE_STATE_ENABLED) { 611 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
602 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 612 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -635,7 +645,7 @@ int omap_device_idle(struct platform_device *pdev)
635 int ret; 645 int ret;
636 struct omap_device *od; 646 struct omap_device *od;
637 647
638 od = _find_by_pdev(pdev); 648 od = to_omap_device(pdev);
639 649
640 if (od->_state != OMAP_DEVICE_STATE_ENABLED) { 650 if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
641 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 651 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -666,7 +676,7 @@ int omap_device_shutdown(struct platform_device *pdev)
666 int ret, i; 676 int ret, i;
667 struct omap_device *od; 677 struct omap_device *od;
668 678
669 od = _find_by_pdev(pdev); 679 od = to_omap_device(pdev);
670 680
671 if (od->_state != OMAP_DEVICE_STATE_ENABLED && 681 if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
672 od->_state != OMAP_DEVICE_STATE_IDLE) { 682 od->_state != OMAP_DEVICE_STATE_IDLE) {
@@ -707,7 +717,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
707 int ret = -EINVAL; 717 int ret = -EINVAL;
708 struct omap_device *od; 718 struct omap_device *od;
709 719
710 od = _find_by_pdev(pdev); 720 od = to_omap_device(pdev);
711 721
712 if (new_wakeup_lat_limit == od->dev_wakeup_lat) 722 if (new_wakeup_lat_limit == od->dev_wakeup_lat)
713 return 0; 723 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 15:36:52 -0500