1315 files changed, 47663 insertions, 43521 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 05900997af90..8c83d98424c7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -5,8 +5,9 @@ config ARM
        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
        select ARCH_HAVE_CUSTOM_GPIO_H
        select ARCH_WANT_IPC_PARSE_VERSION
+        select BUILDTIME_EXTABLE_SORT if MMU
        select CPU_PM if (SUSPEND || CPU_IDLE)
-        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
+        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
        select GENERIC_IRQ_PROBE
@@ -21,6 +22,7 @@ config ARM
        select HAVE_AOUT
        select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
        select HAVE_ARCH_KGDB
+        select HAVE_ARCH_SECCOMP_FILTER
        select HAVE_ARCH_TRACEHOOK
        select HAVE_BPF_JIT
        select HAVE_C_RECORDMCOUNT
@@ -55,6 +57,7 @@ config ARM
        select SYS_SUPPORTS_APM_EMULATION
        select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
        select MODULES_USE_ELF_REL
+        select CLONE_BACKWARDS
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -284,8 +287,8 @@ config ARCH_INTEGRATOR
        select MULTI_IRQ_HANDLER
        select NEED_MACH_MEMORY_H
        select PLAT_VERSATILE
-        select PLAT_VERSATILE_FPGA_IRQ
        select SPARSE_IRQ
+        select VERSATILE_FPGA_IRQ
        help
          Support for ARM's Integrator platform.
@@ -318,7 +321,7 @@ config ARCH_VERSATILE
        select PLAT_VERSATILE
        select PLAT_VERSATILE_CLCD
        select PLAT_VERSATILE_CLOCK
-        select PLAT_VERSATILE_FPGA_IRQ
+        select VERSATILE_FPGA_IRQ
        help
          This enables support for ARM Ltd Versatile board.
@@ -330,13 +333,15 @@ config ARCH_AT91
        select IRQ_DOMAIN
        select NEED_MACH_GPIO_H
        select NEED_MACH_IO_H if PCCARD
+        select PINCTRL
+        select PINCTRL_AT91 if USE_OF
        help
          This enables support for systems based on Atmel
          AT91RM9200 and AT91SAM9* processors.
 config ARCH_BCM2835
        bool "Broadcom BCM2835 family"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select ARM_ERRATA_411920
        select ARM_TIMER_SP804
@@ -344,7 +349,10 @@ config ARCH_BCM2835
        select COMMON_CLK
        select CPU_V6
        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
        select MULTI_IRQ_HANDLER
+        select PINCTRL
+        select PINCTRL_BCM2835
        select SPARSE_IRQ
        select USE_OF
        help
@@ -364,11 +372,16 @@ config ARCH_CNS3XXX
 config ARCH_CLPS711X
        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
+        select ARCH_REQUIRE_GPIOLIB
        select ARCH_USES_GETTIMEOFFSET
+        select AUTO_ZRELADDR
        select CLKDEV_LOOKUP
        select COMMON_CLK
        select CPU_ARM720T
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
        select NEED_MACH_MEMORY_H
+        select SPARSE_IRQ
        help
          Support for Cirrus Logic 711x/721x/731x based boards.
@@ -433,19 +446,6 @@ config ARCH_FOOTBRIDGE
          Support for systems based on the DC21285 companion chip
          ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
-config ARCH_MXC
-        bool "Freescale MXC/iMX-based"
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_IRQ_CHIP
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          Support for Freescale MXC/iMX-based family of processors
 config ARCH_MXS
        bool "Freescale MXS-based"
        select ARCH_REQUIRE_GPIOLIB
@@ -537,6 +537,8 @@ config ARCH_DOVE
        select CPU_V7
        select GENERIC_CLOCKEVENTS
        select MIGHT_HAVE_PCI
+        select PINCTRL
+        select PINCTRL_DOVE
        select PLAT_ORION_LEGACY
        select USB_ARCH_HAS_EHCI
        help
@@ -548,6 +550,9 @@ config ARCH_KIRKWOOD
        select CPU_FEROCEON
        select GENERIC_CLOCKEVENTS
        select PCI
+        select PCI_QUIRKS
+        select PINCTRL
+        select PINCTRL_KIRKWOOD
        select PLAT_ORION_LEGACY
        help
          Support for the following Marvell Kirkwood series SoCs:
@@ -587,6 +592,7 @@ config ARCH_MMP
        select GPIO_PXA
        select IRQ_DOMAIN
        select NEED_MACH_GPIO_H
+        select PINCTRL
        select PLAT_PXA
        select SPARSE_IRQ
        help
@@ -645,6 +651,7 @@ config ARCH_TEGRA
        select HAVE_CLK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
+        select SPARSE_IRQ
        select USE_OF
        help
          This enables support for NVIDIA Tegra based systems (Tegra APX,
@@ -886,6 +893,7 @@ config ARCH_U8500
        select GENERIC_CLOCKEVENTS
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
+        select SPARSE_IRQ
        help
          Support for ST-Ericsson's Ux500 architecture
@@ -900,11 +908,13 @@ config ARCH_NOMADIK
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
        select PINCTRL_STN8815
+        select SPARSE_IRQ
        help
          Support for the Nomadik platform by ST-Ericsson
 config PLAT_SPEAR
        bool "ST SPEAr"
+        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select CLKDEV_LOOKUP
@@ -925,6 +935,7 @@ config ARCH_DAVINCI
        select GENERIC_IRQ_CHIP
        select HAVE_IDE
        select NEED_MACH_GPIO_H
+        select USE_OF
        select ZONE_DMA
        help
          Support for TI's DaVinci platform.
@@ -938,11 +949,10 @@ config ARCH_OMAP
        select CLKSRC_MMIO
        select GENERIC_CLOCKEVENTS
        select HAVE_CLK
-        select NEED_MACH_GPIO_H
        help
          Support for TI's OMAP platform (OMAP1/2/3/4).
-config ARCH_VT8500
+config ARCH_VT8500_SINGLE
        bool "VIA/WonderMedia 85xx"
        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
@@ -952,22 +962,12 @@ config ARCH_VT8500
        select GENERIC_CLOCKEVENTS
        select GENERIC_GPIO
        select HAVE_CLK
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
        select USE_OF
        help
          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
-config ARCH_ZYNQ
-        bool "Xilinx Zynq ARM Cortex A9 Platform"
-        select ARM_AMBA
-        select ARM_GIC
-        select CLKDEV_LOOKUP
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
-        select ICST
-        select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
-        help
-          Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
 menu "Multiple platform selection"
@@ -1023,6 +1023,8 @@ source "arch/arm/mach-mvebu/Kconfig"
 source "arch/arm/mach-at91/Kconfig"
+source "arch/arm/mach-bcm/Kconfig"
 source "arch/arm/mach-clps711x/Kconfig"
 source "arch/arm/mach-cns3xxx/Kconfig"
@@ -1059,14 +1061,13 @@ source "arch/arm/mach-msm/Kconfig"
 source "arch/arm/mach-mv78xx0/Kconfig"
-source "arch/arm/plat-mxc/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
 source "arch/arm/mach-mxs/Kconfig"
 source "arch/arm/mach-netx/Kconfig"
 source "arch/arm/mach-nomadik/Kconfig"
-source "arch/arm/plat-nomadik/Kconfig"
 source "arch/arm/plat-omap/Kconfig"
@@ -1114,6 +1115,8 @@ source "arch/arm/mach-exynos/Kconfig"
 source "arch/arm/mach-shmobile/Kconfig"
+source "arch/arm/mach-sunxi/Kconfig"
 source "arch/arm/mach-prima2/Kconfig"
 source "arch/arm/mach-tegra/Kconfig"
@@ -1127,8 +1130,12 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
+source "arch/arm/mach-vt8500/Kconfig"
 source "arch/arm/mach-w90x900/Kconfig"
+source "arch/arm/mach-zynq/Kconfig"
 # Definitions to make life easier
 config ARCH_ACORN
        bool
@@ -1169,7 +1176,7 @@ config ARM_NR_BANKS
 config IWMMXT
        bool "Enable iWMMXt support"
        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
-        default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
+        default y if PXA27x || PXA3xx || ARCH_MMP
        help
          Enable support for iWMMXt context switching at run time if
          running on a CPU that supports it.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b0f3857b3a4c..661030d6bc6c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -132,6 +132,23 @@ choice
                  their output to UART1 serial port on DaVinci TNETV107X
                  devices.
+        config DEBUG_ZYNQ_UART0
+                bool "Kernel low-level debugging on Xilinx Zynq using UART0"
+                depends on ARCH_ZYNQ
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART0 on the Zynq platform.
+        config DEBUG_ZYNQ_UART1
+                bool "Kernel low-level debugging on Xilinx Zynq using UART1"
+                depends on ARCH_ZYNQ
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART1 on the Zynq platform.
+                  If you have a ZC702 board and want early boot messages to
+                  appear on the USB serial adaptor, select this option.
        config DEBUG_DC21285_PORT
                bool "Kernel low-level debugging messages via footbridge serial port"
                depends on FOOTBRIDGE
@@ -209,20 +226,12 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on i.MX50 or i.MX53.
-        config DEBUG_IMX6Q_UART2
+        config DEBUG_IMX6Q_UART
-                bool "i.MX6Q Debug UART2"
+                bool "i.MX6Q Debug UART"
-                depends on SOC_IMX6Q
-                help
-                  Say Y here if you want kernel low-level debugging support
-                  on i.MX6Q UART2. This is correct for e.g. the SabreLite
-                  board.
-        config DEBUG_IMX6Q_UART4
-                bool "i.MX6Q Debug UART4"
                depends on SOC_IMX6Q
                help
                  Say Y here if you want kernel low-level debugging support
-                  on i.MX6Q UART4.
+                  on i.MX6Q.
        config DEBUG_MMP_UART2
                bool "Kernel low-level debugging message via MMP UART2"
@@ -338,6 +347,17 @@ choice
                  The uncompressor code port configuration is now handled
                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_S3C_UART3
+                depends on PLAT_SAMSUNG && ARCH_EXYNOS
+                bool "Use S3C UART 3 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 3. The port must have been initialised
+                  by the boot-loader before use.
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
        config DEBUG_SOCFPGA_UART
                depends on ARCH_SOCFPGA
                bool "Use SOCFPGA UART for low-level debug"
@@ -345,6 +365,27 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on SOCFPGA based platforms.
+        config DEBUG_SUNXI_UART0
+                bool "Kernel low-level debugging messages via sunXi UART0"
+                depends on ARCH_SUNXI
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Allwinner A1X based platforms on the UART0.
+        config DEBUG_SUNXI_UART1
+                bool "Kernel low-level debugging messages via sunXi UART1"
+                depends on ARCH_SUNXI
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Allwinner A1X based platforms on the UART1.
+        config DEBUG_TEGRA_UART
+                depends on ARCH_TEGRA
+                bool "Use Tegra UART for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Tegra based platforms.
        config DEBUG_VEXPRESS_UART0_DETECT
                bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -409,15 +450,64 @@ choice
 endchoice
+config DEBUG_IMX6Q_UART_PORT
+        int "i.MX6Q Debug UART Port (1-5)" if DEBUG_IMX6Q_UART
+        range 1 5
+        default 1
+        depends on SOC_IMX6Q
+        help
+          Choose UART port on which kernel low-level debug messages
+          should be output.
+choice
+        prompt "Low-level debug console UART"
+        depends on DEBUG_LL && DEBUG_TEGRA_UART
+        config TEGRA_DEBUG_UART_AUTO_ODMDATA
+        bool "Via ODMDATA"
+        help
+          Automatically determines which UART to use for low-level debug based
+          on the ODMDATA value. This value is part of the BCT, and is written
+          to the boot memory device using nvflash, or other flashing tool.
+          When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
+          0/1/2/3/4 are UART A/B/C/D/E.
+        config TEGRA_DEBUG_UARTA
+                bool "UART A"
+        config TEGRA_DEBUG_UARTB
+                bool "UART B"
+        config TEGRA_DEBUG_UARTC
+                bool "UART C"
+        config TEGRA_DEBUG_UARTD
+                bool "UART D"
+        config TEGRA_DEBUG_UARTE
+                bool "UART E"
+endchoice
 config DEBUG_LL_INCLUDE
        string
        default "debug/icedcc.S" if DEBUG_ICEDCC
+        default "debug/imx.S" if DEBUG_IMX1_UART || \
+                                 DEBUG_IMX25_UART || \
+                                 DEBUG_IMX21_IMX27_UART || \
+                                 DEBUG_IMX31_IMX35_UART || \
+                                 DEBUG_IMX51_UART || \
+                                 DEBUG_IMX50_IMX53_UART ||\
+                                 DEBUG_IMX6Q_UART
        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
        default "debug/mvebu.S" if DEBUG_MVEBU_UART
        default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
        default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+        default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
        default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+        default "debug/tegra.S" if DEBUG_TEGRA_UART
+        default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
        default "mach/debug-macro.S"
 config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5f914fca911b..30c443c406f3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -32,6 +32,7 @@ KBUILD_DEFCONFIG := versatile_defconfig
 # defines filename extension depending memory management type.
 ifeq ($(CONFIG_MMU),)
 MMUEXT          := -nommu
+KBUILD_CFLAGS   += $(call cc-option,-mno-unaligned-access)
 endif
 ifeq ($(CONFIG_FRAME_POINTER),y)
@@ -137,6 +138,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)             += at91
+machine-$(CONFIG_ARCH_BCM)              += bcm
 machine-$(CONFIG_ARCH_BCM2835)          += bcm2835
 machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)          += cns3xxx
@@ -193,15 +195,13 @@ machine-$(CONFIG_ARCH_SPEAR13XX)	+= spear13xx
 machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
 machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
+machine-$(CONFIG_ARCH_SUNXI)            += sunxi
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-plat-$(CONFIG_ARCH_MXC)         += mxc
 plat-$(CONFIG_ARCH_OMAP)        += omap
 plat-$(CONFIG_ARCH_S3C64XX)     += samsung
-plat-$(CONFIG_ARCH_ZYNQ)        += versatile
 plat-$(CONFIG_PLAT_IOP)         += iop
-plat-$(CONFIG_PLAT_NOMADIK)     += nomadik
 plat-$(CONFIG_PLAT_ORION)       += orion
 plat-$(CONFIG_PLAT_PXA)         += pxa
 plat-$(CONFIG_PLAT_S3C24XX)     += s3c24xx samsung
@@ -292,10 +292,10 @@ zinstall uinstall install: vmlinux
        $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 %.dtb: scripts
-        $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
+        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
 dtbs: scripts
-        $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
+        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) dtbs
 # We use MRPROPER_FILES and CLEAN_FILES now
 archclean:
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 9137df539b61..abfce280f57b 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -15,8 +15,6 @@ ifneq ($(MACHINE),)
 include $(srctree)/$(MACHINE)/Makefile.boot
 endif
-include $(srctree)/arch/arm/boot/dts/Makefile
 # Note: the following conditions must always be true:
 #   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
@@ -59,16 +57,6 @@ $(obj)/zImage:	$(obj)/compressed/vmlinux FORCE
 endif
-targets += $(dtb-y)
-# Rule to build device tree blobs
-$(obj)/%.dtb: $(src)/dts/%.dts FORCE
-        $(call if_changed_dep,dtc)
-$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
-clean-files := *.dtb
 ifneq ($(LOADADDR),)
  UIMAGE_LOADADDR=$(LOADADDR)
 else
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index a517153a13ea..5cad8a6dadb0 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -45,19 +45,10 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
 OBJS            += head-shark.o ofw-shark.o
 endif
-ifeq ($(CONFIG_ARCH_P720T),y)
-# Borrow this code from SA1100
-OBJS            += head-sa1100.o
-endif
 ifeq ($(CONFIG_ARCH_SA1100),y)
 OBJS            += head-sa1100.o
 endif
-ifeq ($(CONFIG_ARCH_VT8500),y)
-OBJS            += head-vt8500.o
-endif
 ifeq ($(CONFIG_CPU_XSCALE),y)
 OBJS            += head-xscale.o
 endif
diff --git a/arch/arm/boot/compressed/head-vt8500.S b/arch/arm/boot/compressed/head-vt8500.S
deleted file mode 100644
index 1dc1e21a3be3..000000000000
--- a/arch/arm/boot/compressed/head-vt8500.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * linux/arch/arm/boot/compressed/head-vt8500.S
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * VIA VT8500 specific tweaks. This is merged into head.S by the linker.
- *
- */
-#include <linux/linkage.h>
-#include <asm/mach-types.h>
-                .section        ".start", "ax"
-__VT8500_start:
-        @ Compare the SCC ID register against a list of known values
-        ldr     r1, .SCCID
-        ldr     r3, [r1]
-        @ VT8500 override
-        ldr     r4, .VT8500SCC
-        cmp     r3, r4
-        ldreq   r7, .ID_BV07
-        beq     .Lendvt8500
-        @ WM8505 override
-        ldr     r4, .WM8505SCC
-        cmp     r3, r4
-        ldreq   r7, .ID_8505
-        beq     .Lendvt8500
-        @ Otherwise, leave the bootloader's machine id untouched
-.SCCID:
-        .word   0xd8120000
-.VT8500SCC:
-        .word   0x34000102
-.WM8505SCC:
-        .word   0x34260103
-.ID_BV07:
-        .word   MACH_TYPE_BV07
-.ID_8505:
-        .word   MACH_TYPE_WM8505_7IN_NETBOOK
-.Lendvt8500:
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 90275f036cd1..49ca86e37b8d 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -652,6 +652,15 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
                mov     pc, lr
 ENDPROC(__setup_mmu)
+@ Enable unaligned access on v6, to allow better code generation
+@ for the decompressor C code:
+__armv6_mmu_cache_on:
+                mrc     p15, 0, r0, c1, c0, 0   @ read SCTLR
+                bic     r0, r0, #2              @ A (no unaligned access fault)
+                orr     r0, r0, #1 << 22        @ U (v6 unaligned access model)
+                mcr     p15, 0, r0, c1, c0, 0   @ write SCTLR
+                b       __armv4_mmu_cache_on
 __arm926ejs_mmu_cache_on:
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
                mov     r0, #4                  @ put dcache in WT mode
@@ -694,6 +703,9 @@ __armv7_mmu_cache_on:
                bic     r0, r0, #1 << 28        @ clear SCTLR.TRE
                orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                orr     r0, r0, #0x003c         @ write buffer
+                bic     r0, r0, #2              @ A (no unaligned access fault)
+                orr     r0, r0, #1 << 22        @ U (v6 unaligned access model)
+                                                @ (needed for ARM1176)
 #ifdef CONFIG_MMU
 #ifdef CONFIG_CPU_ENDIAN_BE8
                orr     r0, r0, #1 << 25        @ big-endian page tables
@@ -914,7 +926,7 @@ proc_types:
                .word   0x0007b000              @ ARMv6
                .word   0x000ff000
-                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv6_mmu_cache_on
                W(b)    __armv4_mmu_cache_off
                W(b)    __armv6_mmu_cache_flush
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 32d1d404924a..0f441740c22a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,30 +1,54 @@
 ifeq ($(CONFIG_OF),y)
-dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
+# Keep at91 dtb files sorted alphabetically for each SoC
-        at91sam9263ek.dtb \
+# rm9200
-        at91sam9g20ek_2mmc.dtb \
+dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
-        at91sam9g20ek.dtb \
+# sam9260
-        at91sam9g25ek.dtb \
+dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
-        at91sam9m10g45ek.dtb \
+dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
-        at91sam9n12ek.dtb \
+dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
-        ethernut5.dtb \
+dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
-        evk-pro3.dtb \
+dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
-        kizbox.dtb \
+dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
-        tny_a9260.dtb \
+# sam9263
-        tny_a9263.dtb \
+dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
-        tny_a9g20.dtb \
+dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
-        usb_a9260.dtb \
+dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
-        usb_a9263.dtb \
+# sam9g20
-        usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
+dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
+dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
+# sam9g45
+dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
+# sam9n12
+dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
+# sam9x5
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
+dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
+        da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
        dove-cubox.dtb \
        dove-dove-db.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
        exynos4210-smdkv310.dtb \
        exynos4210-trats.dtb \
-        exynos5250-smdk5250.dtb
+        exynos5250-smdk5250.dtb \
-dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+        exynos5440-ssdk5440.dtb \
+        exynos4412-smdk4412.dtb \
+        exynos5250-smdk5250.dtb \
+        exynos5250-snow.dtb
+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
+        ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
        integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
@@ -36,11 +60,20 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
        kirkwood-ib62x0.dtb \
        kirkwood-iconnect.dtb \
        kirkwood-iomega_ix2_200.dtb \
+        kirkwood-is2.dtb \
        kirkwood-km_kirkwood.dtb \
        kirkwood-lschlv2.dtb \
        kirkwood-lsxhl.dtb \
+        kirkwood-mplcec4.dtb \
+        kirkwood-ns2.dtb \
+        kirkwood-ns2lite.dtb \
+        kirkwood-ns2max.dtb \
+        kirkwood-ns2mini.dtb \
+        kirkwood-nsa310.dtb \
+        kirkwood-topkick.dtb \
        kirkwood-ts219-6281.dtb \
-        kirkwood-ts219-6282.dtb
+        kirkwood-ts219-6282.dtb \
+        kirkwood-openblocks_a6.dtb
 dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
        msm8960-cdp.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
@@ -53,39 +86,53 @@ dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
        imx53-qsb.dtb \
        imx53-smd.dtb \
        imx6q-arm2.dtb \
+        imx6q-sabreauto.dtb \
        imx6q-sabrelite.dtb \
        imx6q-sabresd.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx23-olinuxino.dtb \
        imx23-stmp378x_devb.dtb \
+        imx28-apf28.dtb \
+        imx28-apf28dev.dtb \
        imx28-apx4devkit.dtb \
        imx28-cfa10036.dtb \
        imx28-cfa10049.dtb \
        imx28-evk.dtb \
        imx28-m28evk.dtb \
+        imx28-sps1.dtb \
        imx28-tx28.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
+        omap3-beagle.dtb \
        omap3-beagle-xm.dtb \
        omap3-evm.dtb \
        omap3-tobi.dtb \
        omap4-panda.dtb \
-        omap4-pandaES.dtb \
+        omap4-panda-es.dtb \
-        omap4-var_som.dtb \
+        omap4-var-som.dtb \
        omap4-sdp.dtb \
        omap5-evm.dtb \
        am335x-evm.dtb \
+        am335x-evmsk.dtb \
        am335x-bone.dtb
+dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
-dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
+dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
+        hrefprev60.dtb \
+        hrefv60plus.dtb \
+        ccu9540.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
        r8a7740-armadillo800eva.dtb \
-        sh73a0-kzm9g.dtb
+        sh73a0-kzm9g.dtb \
+        sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
        spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
        spear310-evb.dtb \
-        spear320-evb.dtb
+        spear320-evb.dtb \
+        spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
+        sun5i-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra20-medcom-wide.dtb \
        tegra20-paz00.dtb \
@@ -105,5 +152,14 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
 dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
        wm8505-ref.dtb \
        wm8650-mid.dtb
+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
+targets += dtbs
 endif
+# *.dtb used to be generated in the directory above. Clean out the
+# old build results so people don't accidentally use them.
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+        $(Q)rm -f $(obj)/../*.dtb
+clean-files := *.dtb
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index c634f87e230e..11b240c5d323 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -13,11 +13,31 @@
        model = "TI AM335x BeagleBone";
        compatible = "ti,am335x-bone", "ti,am33xx";
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&dcdc2_reg>;
+                };
+        };
        memory {
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
+        am33xx_pinmux: pinmux@44e10800 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
+                user_leds_s0: user_leds_s0 {
+                        pinctrl-single,pins = <
+                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+                                0x58 0x17       /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
+                                0x5c 0x7        /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
+                                0x60 0x17       /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+                        >;
+                };
+        };
        ocp {
                uart1: serial@44e09000 {
                        status = "okay";
@@ -33,6 +53,36 @@
                };
        };
+        leds {
+                compatible = "gpio-leds";
+                led@2 {
+                        label = "beaglebone:green:heartbeat";
+                        gpios = <&gpio2 21 0>;
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+                led@3 {
+                        label = "beaglebone:green:mmc0";
+                        gpios = <&gpio2 22 0>;
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+                led@4 {
+                        label = "beaglebone:green:usr2";
+                        gpios = <&gpio2 23 0>;
+                        default-state = "off";
+                };
+                led@5 {
+                        label = "beaglebone:green:usr3";
+                        gpios = <&gpio2 24 0>;
+                        default-state = "off";
+                };
+        };
 };
 /include/ "tps65217.dtsi"
@@ -78,3 +128,11 @@
                };
        };
 };
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+};
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <1>;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 185d6325a458..d6496440fcea 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -13,11 +13,39 @@
        model = "TI AM335x EVM";
        compatible = "ti,am335x-evm", "ti,am33xx";
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd1_reg>;
+                };
+        };
        memory {
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
+        am33xx_pinmux: pinmux@44e10800 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+                matrix_keypad_s0: matrix_keypad_s0 {
+                        pinctrl-single,pins = <
+                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+                                0x58 0x7        /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
+                                0x64 0x27       /* gpmc_a9.gpio1_25, INPUT | MODE7 */
+                                0x68 0x27       /* gpmc_a10.gpio1_26, INPUT | MODE7 */
+                                0x6c 0x27       /* gpmc_a11.gpio1_27, INPUT | MODE7 */
+                        >;
+                };
+                volume_keys_s0: volume_keys_s0 {
+                        pinctrl-single,pins = <
+                                0x150 0x27      /* spi0_sclk.gpio0_2, INPUT | MODE7 */
+                                0x154 0x27      /* spi0_d0.gpio0_3, INPUT | MODE7 */
+                        >;
+                };
+        };
        ocp {
                uart1: serial@44e09000 {
                        status = "okay";
@@ -31,6 +59,49 @@
                                reg = <0x2d>;
                        };
                };
+                i2c2: i2c@4802a000 {
+                        status = "okay";
+                        clock-frequency = <100000>;
+                        lis331dlh: lis331dlh@18 {
+                                compatible = "st,lis331dlh", "st,lis3lv02d";
+                                reg = <0x18>;
+                                Vdd-supply = <&lis3_reg>;
+                                Vdd_IO-supply = <&lis3_reg>;
+                                st,click-single-x;
+                                st,click-single-y;
+                                st,click-single-z;
+                                st,click-thresh-x = <10>;
+                                st,click-thresh-y = <10>;
+                                st,click-thresh-z = <10>;
+                                st,irq1-click;
+                                st,irq2-click;
+                                st,wakeup-x-lo;
+                                st,wakeup-x-hi;
+                                st,wakeup-y-lo;
+                                st,wakeup-y-hi;
+                                st,wakeup-z-lo;
+                                st,wakeup-z-hi;
+                                st,min-limit-x = <120>;
+                                st,min-limit-y = <120>;
+                                st,min-limit-z = <140>;
+                                st,max-limit-x = <550>;
+                                st,max-limit-y = <550>;
+                                st,max-limit-z = <750>;
+                        };
+                        tsl2550: tsl2550@39 {
+                                compatible = "taos,tsl2550";
+                                reg = <0x39>;
+                        };
+                        tmp275: tmp275@48 {
+                                compatible = "ti,tmp275";
+                                reg = <0x48>;
+                        };
+                };
        };
        vbat: fixedregulator@0 {
@@ -40,6 +111,53 @@
                regulator-max-microvolt = <5000000>;
                regulator-boot-on;
        };
+        lis3_reg: fixedregulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "lis3_reg";
+                regulator-boot-on;
+        };
+        matrix_keypad: matrix_keypad@0 {
+                compatible = "gpio-matrix-keypad";
+                debounce-delay-ms = <5>;
+                col-scan-delay-us = <2>;
+                row-gpios = <&gpio2 25 0        /* Bank1, pin25 */
+                             &gpio2 26 0        /* Bank1, pin26 */
+                             &gpio2 27 0>;      /* Bank1, pin27 */
+                col-gpios = <&gpio2 21 0        /* Bank1, pin21 */
+                             &gpio2 22 0>;      /* Bank1, pin22 */
+                linux,keymap = <0x0000008b      /* MENU */
+                                0x0100009e      /* BACK */
+                                0x02000069      /* LEFT */
+                                0x0001006a      /* RIGHT */
+                                0x0101001c      /* ENTER */
+                                0x0201006c>;    /* DOWN */
+        };
+        gpio_keys: volume_keys@0 {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                switch@9 {
+                        label = "volume-up";
+                        linux,code = <115>;
+                        gpios = <&gpio1 2 1>;
+                        gpio-key,wakeup;
+                };
+                switch@10 {
+                        label = "volume-down";
+                        linux,code = <114>;
+                        gpios = <&gpio1 3 1>;
+                        gpio-key,wakeup;
+                };
+        };
 };
 /include/ "tps65910.dtsi"
@@ -118,3 +236,11 @@
                };
        };
 };
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+};
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <1>;
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
new file mode 100644
index 000000000000..f5a6162a4ff2
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * AM335x Starter Kit
+ * http://www.ti.com/tool/tmdssk3358
+ */
+/dts-v1/;
+/include/ "am33xx.dtsi"
+/ {
+        model = "TI AM335x EVM-SK";
+        compatible = "ti,am335x-evmsk", "ti,am33xx";
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd1_reg>;
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+        am33xx_pinmux: pinmux@44e10800 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
+                user_leds_s0: user_leds_s0 {
+                        pinctrl-single,pins = <
+                                0x10 0x7        /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
+                                0x14 0x7        /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
+                                0x18 0x7        /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
+                                0x1c 0x7        /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
+                        >;
+                };
+                gpio_keys_s0: gpio_keys_s0 {
+                        pinctrl-single,pins = <
+                                0x94 0x27       /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
+                                0x90 0x27       /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
+                                0x70 0x27       /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
+                                0x9c 0x27       /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
+                        >;
+                };
+        };
+        ocp {
+                uart1: serial@44e09000 {
+                        status = "okay";
+                };
+                i2c1: i2c@44e0b000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+                        tps: tps@2d {
+                                reg = <0x2d>;
+                        };
+                        lis331dlh: lis331dlh@18 {
+                                compatible = "st,lis331dlh", "st,lis3lv02d";
+                                reg = <0x18>;
+                                Vdd-supply = <&lis3_reg>;
+                                Vdd_IO-supply = <&lis3_reg>;
+                                st,click-single-x;
+                                st,click-single-y;
+                                st,click-single-z;
+                                st,click-thresh-x = <10>;
+                                st,click-thresh-y = <10>;
+                                st,click-thresh-z = <10>;
+                                st,irq1-click;
+                                st,irq2-click;
+                                st,wakeup-x-lo;
+                                st,wakeup-x-hi;
+                                st,wakeup-y-lo;
+                                st,wakeup-y-hi;
+                                st,wakeup-z-lo;
+                                st,wakeup-z-hi;
+                                st,min-limit-x = <120>;
+                                st,min-limit-y = <120>;
+                                st,min-limit-z = <140>;
+                                st,max-limit-x = <550>;
+                                st,max-limit-y = <550>;
+                                st,max-limit-z = <750>;
+                        };
+                };
+        };
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+        lis3_reg: fixedregulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "lis3_reg";
+                regulator-boot-on;
+        };
+        leds {
+                compatible = "gpio-leds";
+                led@1 {
+                        label = "evmsk:green:usr0";
+                        gpios = <&gpio2 4 0>;
+                        default-state = "off";
+                };
+                led@2 {
+                        label = "evmsk:green:usr1";
+                        gpios = <&gpio2 5 0>;
+                        default-state = "off";
+                };
+                led@3 {
+                        label = "evmsk:green:mmc0";
+                        gpios = <&gpio2 6 0>;
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+                led@4 {
+                        label = "evmsk:green:heartbeat";
+                        gpios = <&gpio2 7 0>;
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+        };
+        gpio_buttons: gpio_buttons@0 {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                switch@1 {
+                        label = "button0";
+                        linux,code = <0x100>;
+                        gpios = <&gpio3 3 0>;
+                };
+                switch@2 {
+                        label = "button1";
+                        linux,code = <0x101>;
+                        gpios = <&gpio3 2 0>;
+                };
+                switch@3 {
+                        label = "button2";
+                        linux,code = <0x102>;
+                        gpios = <&gpio1 30 0>;
+                        gpio-key,wakeup;
+                };
+                switch@4 {
+                        label = "button3";
+                        linux,code = <0x103>;
+                        gpios = <&gpio3 5 0>;
+                };
+        };
+};
+/include/ "tps65910.dtsi"
+&tps {
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+        regulators {
+                vrtc_reg: regulator@0 {
+                        regulator-always-on;
+                };
+                vio_reg: regulator@1 {
+                        regulator-always-on;
+                };
+                vdd1_reg: regulator@2 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1312500>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vdd2_reg: regulator@3 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vdd3_reg: regulator@4 {
+                        regulator-always-on;
+                };
+                vdig1_reg: regulator@5 {
+                        regulator-always-on;
+                };
+                vdig2_reg: regulator@6 {
+                        regulator-always-on;
+                };
+                vpll_reg: regulator@7 {
+                        regulator-always-on;
+                };
+                vdac_reg: regulator@8 {
+                        regulator-always-on;
+                };
+                vaux1_reg: regulator@9 {
+                        regulator-always-on;
+                };
+                vaux2_reg: regulator@10 {
+                        regulator-always-on;
+                };
+                vaux33_reg: regulator@11 {
+                        regulator-always-on;
+                };
+                vmmc_reg: regulator@12 {
+                        regulator-always-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff01998..c2f14e875eb6 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -12,6 +12,7 @@
 / {
        compatible = "ti,am33xx";
+        interrupt-parent = <&intc>;
        aliases {
                serial0 = &uart1;
@@ -25,6 +26,21 @@
        cpus {
                cpu@0 {
                        compatible = "arm,cortex-a8";
+                        /*
+                         * To consider voltage drop between PMIC and SoC,
+                         * tolerance value is reduced to 2% from 4% and
+                         * voltage value is increased as a precaution.
+                         */
+                        operating-points = <
+                                /* kHz    uV */
+                                720000  1285000
+                                600000  1225000
+                                500000  1125000
+                                275000  1125000
+                        >;
+                        voltage-tolerance = <2>; /* 2 percentage */
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
@@ -40,6 +56,15 @@
                };
        };
+        am33xx_pinmux: pinmux@44e10800 {
+                compatible = "pinctrl-single";
+                reg = <0x44e10800 0x0238>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-single,register-width = <32>;
+                pinctrl-single,function-mask = <0x7f>;
+        };
        /*
         * XXX: Use a flat representation of the AM33XX interconnect.
         * The real AM33XX interconnect network is quite complex.Since
@@ -70,7 +95,6 @@
                        interrupt-controller;
                        #interrupt-cells = <1>;
                        reg = <0x44e07000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <96>;
                };
@@ -82,7 +106,6 @@
                        interrupt-controller;
                        #interrupt-cells = <1>;
                        reg = <0x4804c000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <98>;
                };
@@ -94,7 +117,6 @@
                        interrupt-controller;
                        #interrupt-cells = <1>;
                        reg = <0x481ac000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <32>;
                };
@@ -106,7 +128,6 @@
                        interrupt-controller;
                        #interrupt-cells = <1>;
                        reg = <0x481ae000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <62>;
                };
@@ -115,7 +136,6 @@
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                        reg = <0x44e09000 0x2000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <72>;
                        status = "disabled";
                };
@@ -125,7 +145,6 @@
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                        reg = <0x48022000 0x2000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <73>;
                        status = "disabled";
                };
@@ -135,7 +154,6 @@
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                        reg = <0x48024000 0x2000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <74>;
                        status = "disabled";
                };
@@ -145,7 +163,6 @@
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                        reg = <0x481a6000 0x2000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <44>;
                        status = "disabled";
                };
@@ -155,7 +172,6 @@
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
                        reg = <0x481a8000 0x2000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <45>;
                        status = "disabled";
                };
@@ -165,7 +181,6 @@
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                        reg = <0x481aa000 0x2000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <46>;
                        status = "disabled";
                };
@@ -176,7 +191,6 @@
                        #size-cells = <0>;
                        ti,hwmods = "i2c1";
                        reg = <0x44e0b000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <70>;
                        status = "disabled";
                };
@@ -187,7 +201,6 @@
                        #size-cells = <0>;
                        ti,hwmods = "i2c2";
                        reg = <0x4802a000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <71>;
                        status = "disabled";
                };
@@ -198,7 +211,6 @@
                        #size-cells = <0>;
                        ti,hwmods = "i2c3";
                        reg = <0x4819c000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <30>;
                        status = "disabled";
                };
@@ -207,8 +219,171 @@
                        compatible = "ti,omap3-wdt";
                        ti,hwmods = "wd_timer2";
                        reg = <0x44e35000 0x1000>;
-                        interrupt-parent = <&intc>;
                        interrupts = <91>;
                };
+                dcan0: d_can@481cc000 {
+                        compatible = "bosch,d_can";
+                        ti,hwmods = "d_can0";
+                        reg = <0x481cc000 0x2000>;
+                        interrupts = <52>;
+                        status = "disabled";
+                };
+                dcan1: d_can@481d0000 {
+                        compatible = "bosch,d_can";
+                        ti,hwmods = "d_can1";
+                        reg = <0x481d0000 0x2000>;
+                        interrupts = <55>;
+                        status = "disabled";
+                };
+                timer1: timer@44e31000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x44e31000 0x400>;
+                        interrupts = <67>;
+                        ti,hwmods = "timer1";
+                        ti,timer-alwon;
+                };
+                timer2: timer@48040000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48040000 0x400>;
+                        interrupts = <68>;
+                        ti,hwmods = "timer2";
+                };
+                timer3: timer@48042000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48042000 0x400>;
+                        interrupts = <69>;
+                        ti,hwmods = "timer3";
+                };
+                timer4: timer@48044000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48044000 0x400>;
+                        interrupts = <92>;
+                        ti,hwmods = "timer4";
+                        ti,timer-pwm;
+                };
+                timer5: timer@48046000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48046000 0x400>;
+                        interrupts = <93>;
+                        ti,hwmods = "timer5";
+                        ti,timer-pwm;
+                };
+                timer6: timer@48048000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48048000 0x400>;
+                        interrupts = <94>;
+                        ti,hwmods = "timer6";
+                        ti,timer-pwm;
+                };
+                timer7: timer@4804a000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4804a000 0x400>;
+                        interrupts = <95>;
+                        ti,hwmods = "timer7";
+                        ti,timer-pwm;
+                };
+                rtc@44e3e000 {
+                        compatible = "ti,da830-rtc";
+                        reg = <0x44e3e000 0x1000>;
+                        interrupts = <75
+                                      76>;
+                        ti,hwmods = "rtc";
+                };
+                spi0: spi@48030000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x48030000 0x400>;
+                        interrupt = <65>;
+                        ti,spi-num-cs = <2>;
+                        ti,hwmods = "spi0";
+                        status = "disabled";
+                };
+                spi1: spi@481a0000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x481a0000 0x400>;
+                        interrupt = <125>;
+                        ti,spi-num-cs = <2>;
+                        ti,hwmods = "spi1";
+                        status = "disabled";
+                };
+                usb@47400000 {
+                        compatible = "ti,musb-am33xx";
+                        reg = <0x47400000 0x1000        /* usbss */
+                               0x47401000 0x800         /* musb instance 0 */
+                               0x47401800 0x800>;       /* musb instance 1 */
+                        interrupts = <17                /* usbss */
+                                      18                /* musb instance 0 */
+                                      19>;              /* musb instance 1 */
+                        multipoint = <1>;
+                        num-eps = <16>;
+                        ram-bits = <12>;
+                        port0-mode = <3>;
+                        port1-mode = <3>;
+                        power = <250>;
+                        ti,hwmods = "usb_otg_hs";
+                };
+                mac: ethernet@4a100000 {
+                        compatible = "ti,cpsw";
+                        ti,hwmods = "cpgmac0";
+                        cpdma_channels = <8>;
+                        ale_entries = <1024>;
+                        bd_ram_size = <0x2000>;
+                        no_bd_ram = <0>;
+                        rx_descs = <64>;
+                        mac_control = <0x20>;
+                        slaves = <2>;
+                        cpts_active_slave = <0>;
+                        cpts_clock_mult = <0x80000000>;
+                        cpts_clock_shift = <29>;
+                        reg = <0x4a100000 0x800
+                               0x4a101200 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&intc>;
+                        /*
+                         * c0_rx_thresh_pend
+                         * c0_rx_pend
+                         * c0_tx_pend
+                         * c0_misc_pend
+                         */
+                        interrupts = <40 41 42 43>;
+                        ranges;
+                        davinci_mdio: mdio@4a101000 {
+                                compatible = "ti,davinci_mdio";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ti,hwmods = "davinci_mdio";
+                                bus_freq = <1000000>;
+                                reg = <0x4a101000 0x100>;
+                        };
+                        cpsw_emac0: slave@4a100200 {
+                                /* Filled in by U-Boot */
+                                mac-address = [ 00 00 00 00 00 00 ];
+                        };
+                        cpsw_emac1: slave@4a100300 {
+                                /* Filled in by U-Boot */
+                                mac-address = [ 00 00 00 00 00 00 ];
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
new file mode 100644
index 000000000000..74d92cd29d87
--- /dev/null
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -0,0 +1,178 @@
+/*
+ * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
+ *
+ *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+/ {
+        model = "Somfy Animeo IP";
+        compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
+        aliases {
+                serial0 = &usart1;
+                serial1 = &usart2;
+                serial2 = &usart0;
+                serial3 = &dbgu;
+                serial4 = &usart3;
+                serial5 = &uart0;
+                serial6 = &uart1;
+        };
+        chosen {
+                linux,stdout-path = &usart2;
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+        ahb {
+                apb {
+                        usart0: serial@fffb0000 {
+                                pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
+                                linux,rs485-enabled-at-boot-time;
+                                status = "okay";
+                        };
+                        usart1: serial@fffb4000 {
+                                pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>;
+                                linux,rs485-enabled-at-boot-time;
+                                status = "okay";
+                        };
+                        usart2: serial@fffb8000 {
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffc4000 {
+                                pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>;
+                                phy-mode = "mii";
+                                status = "okay";
+                        };
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <&pinctrl_mmc0_clk
+                                             &pinctrl_mmc0_slot1_cmd_dat0
+                                             &pinctrl_mmc0_slot1_dat1_3>;
+                                status = "okay";
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                };
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x8000>;
+                        };
+                        barebox@8000 {
+                                label = "barebox";
+                                reg = <0x8000 0x40000>;
+                        };
+                        bareboxenv@48000 {
+                                label = "bareboxenv";
+                                reg = <0x48000 0x8000>;
+                        };
+                        user_block@0x50000 {
+                                label = "user_block";
+                                reg = <0x50000 0xb0000>;
+                        };
+                        kernel@100000 {
+                                label = "kernel";
+                                reg = <0x100000 0x1b0000>;
+                        };
+                        root@2b0000 {
+                                label = "root";
+                                reg = <0x2b0000 0x1D50000>;
+                        };
+                };
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        atmel,vbus-gpio = <&pioB 15 1>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                power_green {
+                        label = "power_green";
+                        gpios = <&pioC 17 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+                power_red {
+                        label = "power_red";
+                        gpios = <&pioA 2 0>;
+                };
+                tx_green {
+                        label = "tx_green";
+                        gpios = <&pioC 19 0>;
+                };
+                tx_red {
+                        label = "tx_red";
+                        gpios = <&pioC 18 0>;
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                keyswitch_in {
+                        label = "keyswitch_in";
+                        gpios = <&pioB 1 0>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+                error_in {
+                        label = "error_in";
+                        gpios = <&pioB 2 0>;
+                        linux,code = <29>;
+                        gpio-key,wakeup;
+                };
+                btn {
+                        label = "btn";
+                        gpios = <&pioC 23 0>;
+                        linux,code = <31>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
new file mode 100644
index 000000000000..e154f242c680
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -0,0 +1,349 @@
+/*
+ * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
+ *                2012 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Based on at91sam9260.dtsi
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Atmel AT91RM9200 family SoC";
+        compatible = "atmel,at91rm9200";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm920t";
+                };
+        };
+        memory {
+                reg = <0x20000000 0x04000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <3>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <25 26 27 28 29 30 31>;
+                        };
+                        ramc0: ramc@ffffff00 {
+                                compatible = "atmel,at91rm9200-sdramc";
+                                reg = <0xffffff00 0x100>;
+                        };
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+                        st: timer@fffffd00 {
+                                compatible = "atmel,at91rm9200-st";
+                                reg = <0xfffffd00 0x100>;
+                                interrupts = <1 4 7>;
+                        };
+                        tcb0: timer@fffa0000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa0000 0x100>;
+                                interrupts = <17 4 0 18 4 0 19 4 0>;
+                        };
+                        tcb1: timer@fffa4000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa4000 0x100>;
+                                interrupts = <20 4 0 21 4 0 22 4 0>;
+                        };
+                        pinctrl@fffff400 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                                ranges = <0xfffff400 0xfffff400 0x800>;
+                                atmel,mux-mask = <
+                                        /*    A         B     */
+                                         0xffffffff 0xffffffff  /* pioA */
+                                         0xffffffff 0x083fffff  /* pioB */
+                                         0xffff3fff 0x00000000  /* pioC */
+                                         0x03ff87ff 0x0fffff80  /* pioD */
+                                        >;
+                                /* shared pinctrl settings */
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <0 30 0x1 0x0   /* PA30 periph A */
+                                                         0 31 0x1 0x1>; /* PA31 periph with pullup */
+                                        };
+                                };
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <0 17 0x1 0x0   /* PA17 periph A */
+                                                         0 18 0x1 0x0>; /* PA18 periph A */
+                                        };
+                                        pinctrl_uart0_rts: uart0_rts-0 {
+                                                atmel,pins =
+                                                        <0 20 0x1 0x0>; /* PA20 periph A */
+                                        };
+                                        pinctrl_uart0_cts: uart0_cts-0 {
+                                                atmel,pins =
+                                                        <0 21 0x1 0x0>; /* PA21 periph A */
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <1 20 0x1 0x1   /* PB20 periph A with pullup */
+                                                         1 21 0x1 0x0>; /* PB21 periph A */
+                                        };
+                                        pinctrl_uart1_rts: uart1_rts-0 {
+                                                atmel,pins =
+                                                        <1 24 0x1 0x0>; /* PB24 periph A */
+                                        };
+                                        pinctrl_uart1_cts: uart1_cts-0 {
+                                                atmel,pins =
+                                                        <1 26 0x1 0x0>; /* PB26 periph A */
+                                        };
+                                        pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
+                                                atmel,pins =
+                                                        <1 19 0x1 0x0   /* PB19 periph A */
+                                                         1 25 0x1 0x0>; /* PB25 periph A */
+                                        };
+                                        pinctrl_uart1_dcd: uart1_dcd-0 {
+                                                atmel,pins =
+                                                        <1 23 0x1 0x0>; /* PB23 periph A */
+                                        };
+                                        pinctrl_uart1_ri: uart1_ri-0 {
+                                                atmel,pins =
+                                                        <1 18 0x1 0x0>; /* PB18 periph A */
+                                        };
+                                };
+                                uart2 {
+                                        pinctrl_uart2: uart2-0 {
+                                                atmel,pins =
+                                                        <0 22 0x1 0x0   /* PA22 periph A */
+                                                         0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                        };
+                                        pinctrl_uart2_rts: uart2_rts-0 {
+                                                atmel,pins =
+                                                        <0 30 0x2 0x0>; /* PA30 periph B */
+                                        };
+                                        pinctrl_uart2_cts: uart2_cts-0 {
+                                                atmel,pins =
+                                                        <0 31 0x2 0x0>; /* PA31 periph B */
+                                        };
+                                };
+                                uart3 {
+                                        pinctrl_uart3: uart3-0 {
+                                                atmel,pins =
+                                                        <0 5 0x2 0x1    /* PA5 periph B with pullup */
+                                                         0 6 0x2 0x0>;  /* PA6 periph B */
+                                        };
+                                        pinctrl_uart3_rts: uart3_rts-0 {
+                                                atmel,pins =
+                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                        };
+                                        pinctrl_uart3_cts: uart3_cts-0 {
+                                                atmel,pins =
+                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <2 2 0x0 0x1    /* PC2 gpio RDY pin pull_up */
+                                                         1 1 0x0 0x1>;  /* PB1 gpio CD pin pull_up */
+                                        };
+                                };
+                                pioA: gpio@fffff400 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioB: gpio@fffff600 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioC: gpio@fffff800 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <4 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioD: gpio@fffffa00 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x200>;
+                                        interrupts = <5 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                        };
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91rm9200-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
+                                status = "disabled";
+                        };
+                        usart0: serial@fffc0000 {
+                                compatible = "atmel,at91rm9200-usart";
+                                reg = <0xfffc0000 0x200>;
+                                interrupts = <6 4 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                status = "disabled";
+                        };
+                        usart1: serial@fffc4000 {
+                                compatible = "atmel,at91rm9200-usart";
+                                reg = <0xfffc4000 0x200>;
+                                interrupts = <7 4 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1>;
+                                status = "disabled";
+                        };
+                        usart2: serial@fffc8000 {
+                                compatible = "atmel,at91rm9200-usart";
+                                reg = <0xfffc8000 0x200>;
+                                interrupts = <8 4 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart2>;
+                                status = "disabled";
+                        };
+                        usart3: serial@fffcc000 {
+                                compatible = "atmel,at91rm9200-usart";
+                                reg = <0xfffcc000 0x200>;
+                                interrupts = <23 4 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart3>;
+                                status = "disabled";
+                        };
+                        usb1: gadget@fffb0000 {
+                                compatible = "atmel,at91rm9200-udc";
+                                reg = <0xfffb0000 0x4000>;
+                                interrupts = <11 4 2>;
+                                status = "disabled";
+                        };
+                };
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000>;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
+                        nand-ecc-mode = "soft";
+                        gpios = <&pioC 2 0
+                                 0
+                                 &pioB 1 0
+                                >;
+                        status = "disabled";
+                };
+                usb0: ohci@00300000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00300000 0x100000>;
+                        interrupts = <23 4 2>;
+                        status = "disabled";
+                };
+        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 23 0 /* sda */
+                         &pioA 24 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
new file mode 100644
index 000000000000..8aa48931e0a2
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -0,0 +1,79 @@
+/*
+ * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit
+ *
+ *  Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91rm9200.dtsi"
+/ {
+        model = "Atmel AT91RM9200 evaluation kit";
+        compatible = "atmel,at91rm9200ek", "atmel,at91rm9200";
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        usart1: serial@fffc4000 {
+                                pinctrl-0 =
+                                                <&pinctrl_uart1
+                                                 &pinctrl_uart1_rts
+                                                 &pinctrl_uart1_cts
+                                                 &pinctrl_uart1_dtr_dsr
+                                                 &pinctrl_uart1_dcd
+                                                 &pinctrl_uart1_ri>;
+                                status = "okay";
+                        };
+                        usb1: gadget@fffb0000 {
+                                atmel,vbus-gpio = <&pioD 4 0>;
+                                status = "okay";
+                        };
+                };
+                usb0: ohci@00300000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                ds2 {
+                        label = "green";
+                        gpios = <&pioB 0 0x1>;
+                        linux,default-trigger = "mmc0";
+                };
+                ds4 {
+                        label = "yellow";
+                        gpios = <&pioB 1 0x1>;
+                        linux,default-trigger = "heartbeat";
+                };
+                ds6 {
+                        label = "red";
+                        gpios = <&pioB 2 0x1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index d410581a5a85..68bccf41a2c6 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -21,14 +21,15 @@
                serial2 = &usart1;
                serial3 = &usart2;
                serial4 = &usart3;
-                serial5 = &usart4;
+                serial5 = &uart0;
-                serial6 = &usart5;
+                serial6 = &uart1;
                gpio0 = &pioA;
                gpio1 = &pioB;
                gpio2 = &pioC;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
                i2c0 = &i2c0;
+                ssc0 = &ssc0;
        };
        cpus {
                cpu@0 {
@@ -98,40 +99,250 @@
                                interrupts = <26 4 0 27 4 0 28 4 0>;
                        };
-                        pioA: gpio@fffff400 {
+                        pinctrl@fffff400 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                #address-cells = <1>;
-                                reg = <0xfffff400 0x100>;
+                                #size-cells = <1>;
-                                interrupts = <2 4 1>;
+                                compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
-                                #gpio-cells = <2>;
+                                ranges = <0xfffff400 0xfffff400 0x600>;
-                                gpio-controller;
-                                interrupt-controller;
+                                atmel,mux-mask = <
-                                #interrupt-cells = <2>;
+                                      /*    A         B     */
-                        };
+                                       0xffffffff 0xffc00c3b  /* pioA */
+                                       0xffffffff 0x7fff3ccf  /* pioB */
+                                       0xffffffff 0x007fffff  /* pioC */
+                                      >;
+                                /* shared pinctrl settings */
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <1 14 0x1 0x0   /* PB14 periph A */
+                                                         1 15 0x1 0x1>; /* PB15 periph with pullup */
+                                        };
+                                };
-                        pioB: gpio@fffff600 {
+                                usart0 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                        pinctrl_usart0: usart0-0 {
-                                reg = <0xfffff600 0x100>;
+                                                atmel,pins =
-                                interrupts = <3 4 1>;
+                                                        <1 4 0x1 0x0    /* PB4 periph A */
-                                #gpio-cells = <2>;
+                                                         1 5 0x1 0x0>;  /* PB5 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart0_rts: usart0_rts-0 {
-                        };
+                                                atmel,pins =
+                                                        <1 26 0x1 0x0>; /* PB26 periph A */
+                                        };
+                                        pinctrl_usart0_cts: usart0_cts-0 {
+                                                atmel,pins =
+                                                        <1 27 0x1 0x0>; /* PB27 periph A */
+                                        };
+                                        pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
+                                                atmel,pins =
+                                                        <1 24 0x1 0x0   /* PB24 periph A */
+                                                         1 22 0x1 0x0>; /* PB22 periph A */
+                                        };
+                                        pinctrl_usart0_dcd: usart0_dcd-0 {
+                                                atmel,pins =
+                                                        <1 23 0x1 0x0>; /* PB23 periph A */
+                                        };
+                                        pinctrl_usart0_ri: usart0_ri-0 {
+                                                atmel,pins =
+                                                        <1 25 0x1 0x0>; /* PB25 periph A */
+                                        };
+                                };
-                        pioC: gpio@fffff800 {
+                                usart1 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                        pinctrl_usart1: usart1-0 {
-                                reg = <0xfffff800 0x100>;
+                                                atmel,pins =
-                                interrupts = <4 4 1>;
+                                                        <2 6 0x1 0x1    /* PB6 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         2 7 0x1 0x0>;  /* PB7 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart1_rts: usart1_rts-0 {
+                                                atmel,pins =
+                                                        <1 28 0x1 0x0>; /* PB28 periph A */
+                                        };
+                                        pinctrl_usart1_cts: usart1_cts-0 {
+                                                atmel,pins =
+                                                        <1 29 0x1 0x0>; /* PB29 periph A */
+                                        };
+                                };
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <1 8 0x1 0x1    /* PB8 periph A with pullup */
+                                                         1 9 0x1 0x0>;  /* PB9 periph A */
+                                        };
+                                        pinctrl_usart2_rts: usart2_rts-0 {
+                                                atmel,pins =
+                                                        <0 4 0x1 0x0>;  /* PA4 periph A */
+                                        };
+                                        pinctrl_usart2_cts: usart2_cts-0 {
+                                                atmel,pins =
+                                                        <0 5 0x1 0x0>;  /* PA5 periph A */
+                                        };
+                                };
+                                usart3 {
+                                        pinctrl_usart3: usart3-0 {
+                                                atmel,pins =
+                                                        <2 10 0x1 0x1   /* PB10 periph A with pullup */
+                                                         2 11 0x1 0x0>; /* PB11 periph A */
+                                        };
+                                        pinctrl_usart3_rts: usart3_rts-0 {
+                                                atmel,pins =
+                                                        <3 8 0x2 0x0>;  /* PB8 periph B */
+                                        };
+                                        pinctrl_usart3_cts: usart3_cts-0 {
+                                                atmel,pins =
+                                                        <3 10 0x2 0x0>; /* PB10 periph B */
+                                        };
+                                };
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <0 31 0x2 0x1   /* PA31 periph B with pullup */
+                                                         0 30 0x2 0x0>; /* PA30 periph B */
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <2 12 0x1 0x1   /* PB12 periph A with pullup */
+                                                         2 13 0x1 0x0>; /* PB13 periph A */
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
+                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                        };
+                                };
+                                macb {
+                                        pinctrl_macb_rmii: macb_rmii-0 {
+                                                atmel,pins =
+                                                        <0 12 0x1 0x0   /* PA12 periph A */
+                                                         0 13 0x1 0x0   /* PA13 periph A */
+                                                         0 14 0x1 0x0   /* PA14 periph A */
+                                                         0 15 0x1 0x0   /* PA15 periph A */
+                                                         0 16 0x1 0x0   /* PA16 periph A */
+                                                         0 17 0x1 0x0   /* PA17 periph A */
+                                                         0 18 0x1 0x0   /* PA18 periph A */
+                                                         0 19 0x1 0x0   /* PA19 periph A */
+                                                         0 20 0x1 0x0   /* PA20 periph A */
+                                                         0 21 0x1 0x0>; /* PA21 periph A */
+                                        };
+                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                                atmel,pins =
+                                                        <0 22 0x2 0x0   /* PA22 periph B */
+                                                         0 23 0x2 0x0   /* PA23 periph B */
+                                                         0 24 0x2 0x0   /* PA24 periph B */
+                                                         0 25 0x2 0x0   /* PA25 periph B */
+                                                         0 26 0x2 0x0   /* PA26 periph B */
+                                                         0 27 0x2 0x0   /* PA27 periph B */
+                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                        };
+                                        pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
+                                                atmel,pins =
+                                                        <0 10 0x2 0x0   /* PA10 periph B */
+                                                         0 11 0x2 0x0   /* PA11 periph B */
+                                                         0 24 0x2 0x0   /* PA24 periph B */
+                                                         0 25 0x2 0x0   /* PA25 periph B */
+                                                         0 26 0x2 0x0   /* PA26 periph B */
+                                                         0 27 0x2 0x0   /* PA27 periph B */
+                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_clk: mmc0_clk-0 {
+                                                atmel,pins =
+                                                        <0 8 0x1 0x0>;  /* PA8 periph A */
+                                        };
+                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                         0 6 0x1 0x1>;  /* PA6 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 9 0x1 0x1    /* PA9 periph A with pullup */
+                                                         0 10 0x1 0x1   /* PA10 periph A with pullup */
+                                                         0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 1 0x2 0x1    /* PA1 periph B with pullup */
+                                                         0 0 0x2 0x1>;  /* PA0 periph B with pullup */
+                                        };
+                                        pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 5 0x2 0x1    /* PA5 periph B with pullup */
+                                                         0 4 0x2 0x1    /* PA4 periph B with pullup */
+                                                         0 3 0x2 0x1>;  /* PA3 periph B with pullup */
+                                        };
+                                };
+                                pioA: gpio@fffff400 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioB: gpio@fffff600 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioC: gpio@fffff800 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <4 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                        };
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
@@ -141,6 +352,8 @@
                                interrupts = <6 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
@@ -150,6 +363,8 @@
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
@@ -159,6 +374,8 @@
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
@@ -168,24 +385,30 @@
                                interrupts = <23 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
                        };
-                        usart4: serial@fffd4000 {
+                        uart0: serial@fffd4000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd4000 0x200>;
                                interrupts = <24 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
                                status = "disabled";
                        };
-                        usart5: serial@fffd8000 {
+                        uart1: serial@fffd8000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffd8000 0x200>;
                                interrupts = <25 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1>;
                                status = "disabled";
                        };
@@ -193,6 +416,8 @@
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffc4000 0x100>;
                                interrupts = <21 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
                        };
@@ -212,6 +437,22 @@
                                status = "disabled";
                        };
+                        mmc0: mmc@fffa8000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfffa8000 0x600>;
+                                interrupts = <9 4 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        ssc0: ssc@fffbc000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffbc000 0x4000>;
+                                interrupts = <14 4 5>;
+                                status = "disabled";
+                        };
                        adc0: adc@fffe0000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffe0000 0x100>;
@@ -246,6 +487,12 @@
                                        trigger-external;
                                };
                        };
+                        watchdog@fffffd40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffd40 0x10>;
+                                status = "disabled";
+                        };
                };
                nand0: nand@40000000 {
@@ -257,6 +504,8 @@
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioC 13 0
                                 &pioC 14 0
                                 0
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3e6e5c1abbf3..8e6251f1f7a3 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -25,6 +25,8 @@
                gpio4 = &pioE;
                tcb0 = &tcb0;
                i2c0 = &i2c0;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
        };
        cpus {
                cpu@0 {
@@ -89,60 +91,243 @@
                                reg = <0xfffffd10 0x10>;
                        };
-                        pioA: gpio@fffff200 {
+                        pinctrl@fffff200 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                #address-cells = <1>;
-                                reg = <0xfffff200 0x100>;
+                                #size-cells = <1>;
-                                interrupts = <2 4 1>;
+                                compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
-                                #gpio-cells = <2>;
+                                ranges = <0xfffff200 0xfffff200 0xa00>;
-                                gpio-controller;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        pioB: gpio@fffff400 {
+                                atmel,mux-mask = <
-                                compatible = "atmel,at91rm9200-gpio";
+                                      /*    A         B     */
-                                reg = <0xfffff400 0x100>;
+                                       0xfffffffb 0xffffe07f  /* pioA */
-                                interrupts = <3 4 1>;
+                                       0x0007ffff 0x39072fff  /* pioB */
-                                #gpio-cells = <2>;
+                                       0xffffffff 0x3ffffff8  /* pioC */
-                                gpio-controller;
+                                       0xfffffbff 0xffffffff  /* pioD */
-                                interrupt-controller;
+                                       0xffe00fff 0xfbfcff00  /* pioE */
-                                #interrupt-cells = <2>;
+                                      >;
-                        };
-                        pioC: gpio@fffff600 {
+                                /* shared pinctrl settings */
-                                compatible = "atmel,at91rm9200-gpio";
+                                dbgu {
-                                reg = <0xfffff600 0x100>;
+                                        pinctrl_dbgu: dbgu-0 {
-                                interrupts = <4 4 1>;
+                                                atmel,pins =
-                                #gpio-cells = <2>;
+                                                        <2 30 0x1 0x0   /* PC30 periph A */
-                                gpio-controller;
+                                                         2 31 0x1 0x1>; /* PC31 periph with pullup */
-                                interrupt-controller;
+                                        };
-                                #interrupt-cells = <2>;
+                                };
-                        };
-                        pioD: gpio@fffff800 {
+                                usart0 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                        pinctrl_usart0: usart0-0 {
-                                reg = <0xfffff800 0x100>;
+                                                atmel,pins =
-                                interrupts = <4 4 1>;
+                                                        <0 26 0x1 0x1   /* PA26 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         0 27 0x1 0x0>; /* PA27 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        pioE: gpio@fffffa00 {
+                                        pinctrl_usart0_rts: usart0_rts-0 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                                atmel,pins =
-                                reg = <0xfffffa00 0x100>;
+                                                        <0 28 0x1 0x0>; /* PA28 periph A */
-                                interrupts = <4 4 1>;
+                                        };
-                                #gpio-cells = <2>;
-                                gpio-controller;
+                                        pinctrl_usart0_cts: usart0_cts-0 {
-                                interrupt-controller;
+                                                atmel,pins =
-                                #interrupt-cells = <2>;
+                                                        <0 29 0x1 0x0>; /* PA29 periph A */
+                                        };
+                                };
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <3 0 0x1 0x1    /* PD0 periph A with pullup */
+                                                         3 1 0x1 0x0>;  /* PD1 periph A */
+                                        };
+                                        pinctrl_usart1_rts: usart1_rts-0 {
+                                                atmel,pins =
+                                                        <3 7 0x2 0x0>;  /* PD7 periph B */
+                                        };
+                                        pinctrl_usart1_cts: usart1_cts-0 {
+                                                atmel,pins =
+                                                        <3 8 0x2 0x0>;  /* PD8 periph B */
+                                        };
+                                };
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <3 2 0x1 0x1    /* PD2 periph A with pullup */
+                                                         3 3 0x1 0x0>;  /* PD3 periph A */
+                                        };
+                                        pinctrl_usart2_rts: usart2_rts-0 {
+                                                atmel,pins =
+                                                        <3 5 0x2 0x0>;  /* PD5 periph B */
+                                        };
+                                        pinctrl_usart2_cts: usart2_cts-0 {
+                                                atmel,pins =
+                                                        <4 6 0x2 0x0>;  /* PD6 periph B */
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <0 22 0x0 0x1   /* PA22 gpio RDY pin pull_up*/
+                                                         3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
+                                        };
+                                };
+                                macb {
+                                        pinctrl_macb_rmii: macb_rmii-0 {
+                                                atmel,pins =
+                                                        <2 25 0x2 0x0   /* PC25 periph B */
+                                                         4 21 0x1 0x0   /* PE21 periph A */
+                                                         4 23 0x1 0x0   /* PE23 periph A */
+                                                         4 24 0x1 0x0   /* PE24 periph A */
+                                                         4 25 0x1 0x0   /* PE25 periph A */
+                                                         4 26 0x1 0x0   /* PE26 periph A */
+                                                         4 27 0x1 0x0   /* PE27 periph A */
+                                                         4 28 0x1 0x0   /* PE28 periph A */
+                                                         4 29 0x1 0x0   /* PE29 periph A */
+                                                         4 30 0x1 0x0>; /* PE30 periph A */
+                                        };
+                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                                atmel,pins =
+                                                        <2 20 0x2 0x0   /* PC20 periph B */
+                                                         2 21 0x2 0x0   /* PC21 periph B */
+                                                         2 22 0x2 0x0   /* PC22 periph B */
+                                                         2 23 0x2 0x0   /* PC23 periph B */
+                                                         2 24 0x2 0x0   /* PC24 periph B */
+                                                         2 25 0x2 0x0   /* PC25 periph B */
+                                                         2 27 0x2 0x0   /* PC27 periph B */
+                                                         4 22 0x2 0x0>; /* PE22 periph B */
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_clk: mmc0_clk-0 {
+                                                atmel,pins =
+                                                        <0 12 0x1 0x0>; /* PA12 periph A */
+                                        };
+                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                         0 0 0x1 0x1>;  /* PA0 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 3 0x1 0x1    /* PA3 periph A with pullup */
+                                                         0 4 0x1 0x1    /* PA4 periph A with pullup */
+                                                         0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                         0 17 0x1 0x1>; /* PA17 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                        };
+                                };
+                                mmc1 {
+                                        pinctrl_mmc1_clk: mmc1_clk-0 {
+                                                atmel,pins =
+                                                        <0 6 0x1 0x0>;  /* PA6 periph A */
+                                        };
+                                        pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                         0 8 0x1 0x1>;  /* PA8 periph A with pullup */
+                                        };
+                                        pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 9 0x1 0x1    /* PA9 periph A with pullup */
+                                                         0 10 0x1 0x1   /* PA10 periph A with pullup */
+                                                         0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                        };
+                                        pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 21 0x1 0x1   /* PA21 periph A with pullup */
+                                                         0 22 0x1 0x1>; /* PA22 periph A with pullup */
+                                        };
+                                        pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 23 0x1 0x1   /* PA23 periph A with pullup */
+                                                         0 24 0x1 0x1   /* PA24 periph A with pullup */
+                                                         0 25 0x1 0x1>; /* PA25 periph A with pullup */
+                                        };
+                                };
+                                pioA: gpio@fffff200 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff200 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioB: gpio@fffff400 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioC: gpio@fffff600 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <4 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioD: gpio@fffff800 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <4 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioE: gpio@fffffa00 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x200>;
+                                        interrupts = <4 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                        };
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
                                interrupts = <1 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
@@ -152,6 +337,8 @@
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
@@ -161,6 +348,8 @@
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
@@ -170,13 +359,31 @@
                                interrupts = <9 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
+                        ssc0: ssc@fff98000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfff98000 0x4000>;
+                                interrupts = <16 4 5>;
+                                status = "disable";
+                        };
+                        ssc1: ssc@fff9c000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfff9c000 0x4000>;
+                                interrupts = <17 4 5>;
+                                status = "disable";
+                        };
                        macb0: ethernet@fffbc000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffbc000 0x100>;
                                interrupts = <21 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
                        };
@@ -195,6 +402,30 @@
                                #size-cells = <0>;
                                status = "disabled";
                        };
+                        mmc0: mmc@fff80000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfff80000 0x600>;
+                                interrupts = <10 4 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        mmc1: mmc@fff84000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfff84000 0x600>;
+                                interrupts = <11 4 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        watchdog@fffffd40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffd40 0x10>;
+                                status = "disabled";
+                        };
                };
                nand0: nand@40000000 {
@@ -206,6 +437,8 @@
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioA 22 0
                                 &pioD 15 0
                                 0
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b609fc..1eb08728f527 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -38,6 +38,10 @@
                        };
                        usart0: serial@fff8c000 {
+                                pinctrl-0 = <
+                                        &pinctrl_usart0
+                                        &pinctrl_usart0_rts
+                                        &pinctrl_usart0_cts>;
                                status = "okay";
                        };
@@ -50,6 +54,31 @@
                                atmel,vbus-gpio = <&pioA 25 0>;
                                status = "okay";
                        };
+                        mmc0: mmc@fff80000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot0_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioE 18 0>;
+                                        wp-gpios = <&pioE 19 0>;
+                                };
+                        };
+                        pinctrl@fffff200 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <5 18 0x0 0x5   /* PE18 gpio CD pin pull up and deglitch */
+                                                         5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */
+                                        };
+                                };
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
new file mode 100644
index 000000000000..fbe7a7089c2a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/include/ "at91sam9x5.dtsi"
+/ {
+        model = "Atmel AT91SAM9G15 SoC";
+        compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
+        ahb {
+                apb {
+                        pinctrl@fffff400 {
+                                atmel,mux-mask = <
+                                      /*    A         B          C     */
+                                       0xffffffff 0xffe0399f 0x00000000  /* pioA */
+                                       0x00040000 0x00047e3f 0x00000000  /* pioB */
+                                       0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+                                       0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                      >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
new file mode 100644
index 000000000000..86dd3f6d938f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g15.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+/ {
+        model = "Atmel AT91SAM9G25-EK";
+        compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
index f1b2e148ac8c..66467b113126 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -12,6 +12,32 @@
        model = "Atmel at91sam9g20ek 2 mmc";
        compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
+        ahb {
+                apb{
+                        mmc0: mmc@fffa8000 {
+                                /* clk already mux wuth slot0 */
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0_slot0
+                                        &pinctrl_mmc0_slot0_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioC 2 0>;
+                                };
+                        };
+                        pinctrl@fffff400 {
+                                mmc0_slot0 {
+                                        pinctrl_board_mmc0_slot0: mmc0_slot0-board {
+                                                atmel,pins =
+                                                        <2 2 0x0 0x5>;  /* PC2 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                        };
+                };
+        };
        leds {
                compatible = "gpio-leds";
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index e6391a4e6649..da15e83e7f17 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -30,11 +30,28 @@
        ahb {
                apb {
+                        pinctrl@fffff400 {
+                                board {
+                                        pinctrl_pck0_as_mck: pck0_as_mck {
+                                                atmel,pins =
+                                                        <2 1 0x2 0x0>;  /* PC1 periph B */
+                                        };
+                                };
+                        };
                        dbgu: serial@fffff200 {
                                status = "okay";
                        };
                        usart0: serial@fffb0000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart0
+                                         &pinctrl_usart0_rts
+                                         &pinctrl_usart0_cts
+                                         &pinctrl_usart0_dtr_dsr
+                                         &pinctrl_usart0_dcd
+                                         &pinctrl_usart0_ri>;
                                status = "okay";
                        };
@@ -51,6 +68,34 @@
                                atmel,vbus-gpio = <&pioC 5 0>;
                                status = "okay";
                        };
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0_slot1
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot1_cmd_dat0
+                                        &pinctrl_mmc0_slot1_dat1_3>;
+                                status = "okay";
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioC 9 0>;
+                                };
+                        };
+                        pinctrl@fffff400 {
+                                mmc0_slot1 {
+                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                                atmel,pins =
+                                                        <2 9 0x0 0x5>;  /* PC9 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                        };
+                        ssc0: ssc@fffbc000 {
+                                status = "okay";
+                                pinctrl-0 = <&pinctrl_ssc0_tx>;
+                        };
                };
                nand0: nand@40000000 {
@@ -114,7 +159,7 @@
                        reg = <0x50>;
                };
-                wm8731@1b {
+                wm8731: wm8731@1b {
                        compatible = "wm8731";
                        reg = <0x1b>;
                };
@@ -139,4 +184,19 @@
                        gpio-key,wakeup;
                };
        };
+        sound {
+                compatible = "atmel,at91sam9g20ek-wm8731-audio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pck0_as_mck>;
+                atmel,model = "wm8731 @ AT91SAMG20EK";
+                atmel,audio-routing =
+                        "Ext Spk", "LHPOUT",
+                        "Int Mic", "MICIN";
+                atmel,ssc-controller = <&ssc0>;
+                atmel,audio-codec = <&wm8731>;
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
new file mode 100644
index 000000000000..05a718fb83c4
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/include/ "at91sam9x5.dtsi"
+/ {
+        model = "Atmel AT91SAM9G25 SoC";
+        compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
+        ahb {
+                apb {
+                        pinctrl@fffff400 {
+                                atmel,mux-mask = <
+                                      /*    A         B          C     */
+                                       0xffffffff 0xffe0399f 0xc000001c  /* pioA */
+                                       0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
+                                       0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
+                                       0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                      >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 877c08f06763..c5ab16fba059 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,55 +7,10 @@
 * Licensed under GPLv2 or later.
 */
 /dts-v1/;
-/include/ "at91sam9x5.dtsi"
+/include/ "at91sam9g25.dtsi"
-/include/ "at91sam9x5cm.dtsi"
+/include/ "at91sam9x5ek.dtsi"
 / {
        model = "Atmel AT91SAM9G25-EK";
        compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
-        chosen {
-                bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
-        };
-        ahb {
-                apb {
-                        dbgu: serial@fffff200 {
-                                status = "okay";
-                        };
-                        usart0: serial@f801c000 {
-                                status = "okay";
-                        };
-                        macb0: ethernet@f802c000 {
-                                phy-mode = "rmii";
-                                status = "okay";
-                        };
-                        i2c0: i2c@f8010000 {
-                                status = "okay";
-                        };
-                        i2c1: i2c@f8014000 {
-                                status = "okay";
-                        };
-                        i2c2: i2c@f8018000 {
-                                status = "okay";
-                        };
-                };
-                usb0: ohci@00600000 {
-                        status = "okay";
-                        num-ports = <2>;
-                        atmel,vbus-gpio = <&pioD 19 1
-                                           &pioD 20 1
-                                          >;
-                };
-                usb1: ehci@00700000 {
-                        status = "okay";
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
new file mode 100644
index 000000000000..f9d14a722794
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/include/ "at91sam9x5.dtsi"
+/ {
+        model = "Atmel AT91SAM9G35 SoC";
+        compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
+        ahb {
+                apb {
+                        pinctrl@fffff400 {
+                                atmel,mux-mask = <
+                                      /*    A         B          C     */
+                                       0xffffffff 0xffe0399f 0xc000000c  /* pioA */
+                                       0x000406ff 0x00047e3f 0x00000000  /* pioB */
+                                       0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+                                       0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                      >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
new file mode 100644
index 000000000000..95944bdd798d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g35.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+/ {
+        model = "Atmel AT91SAM9G35-EK";
+        compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3add030d61f8..fa1ae0c5479c 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -31,6 +31,8 @@
                tcb1 = &tcb1;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
        };
        cpus {
                cpu@0 {
@@ -108,60 +110,243 @@
                                interrupts = <21 4 0>;
                        };
-                        pioA: gpio@fffff200 {
+                        pinctrl@fffff200 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                #address-cells = <1>;
-                                reg = <0xfffff200 0x100>;
+                                #size-cells = <1>;
-                                interrupts = <2 4 1>;
+                                compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
-                                #gpio-cells = <2>;
+                                ranges = <0xfffff200 0xfffff200 0xa00>;
-                                gpio-controller;
-                                interrupt-controller;
+                                atmel,mux-mask = <
-                                #interrupt-cells = <2>;
+                                      /*    A         B     */
-                        };
+                                       0xffffffff 0xffc003ff  /* pioA */
+                                       0xffffffff 0x800f8f00  /* pioB */
+                                       0xffffffff 0x00000e00  /* pioC */
+                                       0xffffffff 0xff0c1381  /* pioD */
+                                       0xffffffff 0x81ffff81  /* pioE */
+                                      >;
+                                /* shared pinctrl settings */
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <1 12 0x1 0x0   /* PB12 periph A */
+                                                         1 13 0x1 0x0>; /* PB13 periph A */
+                                        };
+                                };
-                        pioB: gpio@fffff400 {
+                                usart0 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                        pinctrl_usart0: usart0-0 {
-                                reg = <0xfffff400 0x100>;
+                                                atmel,pins =
-                                interrupts = <3 4 1>;
+                                                        <1 19 0x1 0x1   /* PB19 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         1 18 0x1 0x0>; /* PB18 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart0_rts: usart0_rts-0 {
-                        };
+                                                atmel,pins =
+                                                        <1 17 0x2 0x0>; /* PB17 periph B */
+                                        };
+                                        pinctrl_usart0_cts: usart0_cts-0 {
+                                                atmel,pins =
+                                                        <1 15 0x2 0x0>; /* PB15 periph B */
+                                        };
+                                };
-                        pioC: gpio@fffff600 {
+                                uart1 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                        pinctrl_usart1: usart1-0 {
-                                reg = <0xfffff600 0x100>;
+                                                atmel,pins =
-                                interrupts = <4 4 1>;
+                                                        <1 4 0x1 0x1    /* PB4 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         1 5 0x1 0x0>;  /* PB5 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart1_rts: usart1_rts-0 {
-                        };
+                                                atmel,pins =
+                                                        <3 16 0x1 0x0>; /* PD16 periph A */
+                                        };
+                                        pinctrl_usart1_cts: usart1_cts-0 {
+                                                atmel,pins =
+                                                        <3 17 0x1 0x0>; /* PD17 periph A */
+                                        };
+                                };
-                        pioD: gpio@fffff800 {
+                                usart2 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                        pinctrl_usart2: usart2-0 {
-                                reg = <0xfffff800 0x100>;
+                                                atmel,pins =
-                                interrupts = <5 4 1>;
+                                                        <1 6 0x1 0x1    /* PB6 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         1 7 0x1 0x0>;  /* PB7 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart2_rts: usart2_rts-0 {
-                        };
+                                                atmel,pins =
+                                                        <2 9 0x2 0x0>;  /* PC9 periph B */
+                                        };
+                                        pinctrl_usart2_cts: usart2_cts-0 {
+                                                atmel,pins =
+                                                        <2 11 0x2 0x0>; /* PC11 periph B */
+                                        };
+                                };
-                        pioE: gpio@fffffa00 {
+                                usart3 {
-                                compatible = "atmel,at91rm9200-gpio";
+                                        pinctrl_usart3: usart3-0 {
-                                reg = <0xfffffa00 0x100>;
+                                                atmel,pins =
-                                interrupts = <5 4 1>;
+                                                        <1 8 0x1 0x1    /* PB9 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         1 9 0x1 0x0>;  /* PB8 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart3_rts: usart3_rts-0 {
+                                                atmel,pins =
+                                                        <0 23 0x2 0x0>; /* PA23 periph B */
+                                        };
+                                        pinctrl_usart3_cts: usart3_cts-0 {
+                                                atmel,pins =
+                                                        <0 24 0x2 0x0>; /* PA24 periph B */
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <2 8 0x0 0x1    /* PC8 gpio RDY pin pull_up*/
+                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                        };
+                                };
+                                macb {
+                                        pinctrl_macb_rmii: macb_rmii-0 {
+                                                atmel,pins =
+                                                        <0 10 0x1 0x0   /* PA10 periph A */
+                                                         0 11 0x1 0x0   /* PA11 periph A */
+                                                         0 12 0x1 0x0   /* PA12 periph A */
+                                                         0 13 0x1 0x0   /* PA13 periph A */
+                                                         0 14 0x1 0x0   /* PA14 periph A */
+                                                         0 15 0x1 0x0   /* PA15 periph A */
+                                                         0 16 0x1 0x0   /* PA16 periph A */
+                                                         0 17 0x1 0x0   /* PA17 periph A */
+                                                         0 18 0x1 0x0   /* PA18 periph A */
+                                                         0 19 0x1 0x0>; /* PA19 periph A */
+                                        };
+                                        pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                                atmel,pins =
+                                                        <0 6 0x2 0x0    /* PA6 periph B */
+                                                         0 7 0x2 0x0    /* PA7 periph B */
+                                                         0 8 0x2 0x0    /* PA8 periph B */
+                                                         0 9 0x2 0x0    /* PA9 periph B */
+                                                         0 27 0x2 0x0   /* PA27 periph B */
+                                                         0 28 0x2 0x0   /* PA28 periph B */
+                                                         0 29 0x2 0x0   /* PA29 periph B */
+                                                         0 30 0x2 0x0>; /* PA30 periph B */
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 0 0x1 0x0    /* PA0 periph A */
+                                                         0 1 0x1 0x1    /* PA1 periph A with pullup */
+                                                         0 2 0x1 0x1>;  /* PA2 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 3 0x1 0x1    /* PA3 periph A with pullup */
+                                                         0 4 0x1 0x1    /* PA4 periph A with pullup */
+                                                         0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+                                                atmel,pins =
+                                                        <0 6 0x1 0x1    /* PA6 periph A with pullup */
+                                                         0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                         0 8 0x1 0x1    /* PA8 periph A with pullup */
+                                                         0 9 0x1 0x1>;  /* PA9 periph A with pullup */
+                                        };
+                                };
+                                mmc1 {
+                                        pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 31 0x1 0x0   /* PA31 periph A */
+                                                         0 22 0x1 0x1   /* PA22 periph A with pullup */
+                                                         0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                        };
+                                        pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 24 0x1 0x1   /* PA24 periph A with pullup */
+                                                         0 25 0x1 0x1   /* PA25 periph A with pullup */
+                                                         0 26 0x1 0x1>; /* PA26 periph A with pullup */
+                                        };
+                                        pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
+                                                atmel,pins =
+                                                        <0 27 0x1 0x1   /* PA27 periph A with pullup */
+                                                         0 28 0x1 0x1   /* PA28 periph A with pullup */
+                                                         0 29 0x1 0x1   /* PA29 periph A with pullup */
+                                                         0 20 0x1 0x1>; /* PA30 periph A with pullup */
+                                        };
+                                };
+                                pioA: gpio@fffff200 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff200 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioB: gpio@fffff400 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioC: gpio@fffff600 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <4 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioD: gpio@fffff800 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <5 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioE: gpio@fffffa00 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x200>;
+                                        interrupts = <5 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                        };
                        dbgu: serial@ffffee00 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xffffee00 0x200>;
                                interrupts = <1 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
@@ -171,6 +356,8 @@
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
@@ -180,6 +367,8 @@
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
@@ -189,6 +378,8 @@
                                interrupts = <9 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
@@ -198,6 +389,8 @@
                                interrupts = <10 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
                        };
@@ -205,6 +398,8 @@
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xfffbc000 0x100>;
                                interrupts = <25 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb_rmii>;
                                status = "disabled";
                        };
@@ -226,6 +421,20 @@
                                status = "disabled";
                        };
+                        ssc0: ssc@fff9c000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xfff9c000 0x4000>;
+                                interrupts = <16 4 5>;
+                                status = "disable";
+                        };
+                        ssc1: ssc@fffa0000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xfffa0000 0x4000>;
+                                interrupts = <17 4 5>;
+                                status = "disable";
+                        };
                        adc0: adc@fffb0000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffb0000 0x100>;
@@ -262,6 +471,30 @@
                                        trigger-value = <0x6>;
                                };
                        };
+                        mmc0: mmc@fff80000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfff80000 0x600>;
+                                interrupts = <11 4 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        mmc1: mmc@fffd0000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfffd0000 0x600>;
+                                interrupts = <29 4 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        watchdog@fffffd40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffd40 0x10>;
+                                status = "disabled";
+                        };
                };
                nand0: nand@40000000 {
@@ -273,6 +506,8 @@
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioC 8 0
                                 &pioC 14 0
                                 0
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 15e1dd43f625..20c31913c270 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -39,6 +39,10 @@
                        };
                        usart1: serial@fff90000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart1
+                                         &pinctrl_usart1_rts
+                                         &pinctrl_usart1_cts>;
                                status = "okay";
                        };
@@ -54,6 +58,50 @@
                        i2c1: i2c@fff88000 {
                                status = "okay";
                        };
+                        mmc0: mmc@fff80000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 10 0>;
+                                };
+                        };
+                        mmc1: mmc@fffd0000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc1
+                                        &pinctrl_mmc1_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc1_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 11 0>;
+                                        wp-gpios = <&pioD 29 0>;
+                                };
+                        };
+                        pinctrl@fffff200 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                                mmc1 {
+                                        pinctrl_board_mmc1: mmc1-board {
+                                                atmel,pins =
+                                                        <3 11 0x0 0x5   /* PD11 gpio CD pin pull up and deglitch */
+                                                         3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */
+                                        };
+                                };
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 82508d68aa7e..e9efb34f4379 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -84,6 +84,15 @@
                                reg = <0xfffffe10 0x10>;
                        };
+                        mmc0: mmc@f0008000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf0008000 0x600>;
+                                interrupts = <12 4 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                        tcb0: timer@f8008000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8008000 0x100>;
@@ -102,50 +111,186 @@
                                interrupts = <20 4 0>;
                        };
-                        pioA: gpio@fffff400 {
+                        pinctrl@fffff400 {
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                #address-cells = <1>;
-                                reg = <0xfffff400 0x100>;
+                                #size-cells = <1>;
-                                interrupts = <2 4 1>;
+                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
-                                #gpio-cells = <2>;
+                                ranges = <0xfffff400 0xfffff400 0x800>;
-                                gpio-controller;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-                        pioB: gpio@fffff600 {
+                                atmel,mux-mask = <
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                      /*    A         B          C     */
-                                reg = <0xfffff600 0x100>;
+                                       0xffffffff 0xffe07983 0x00000000  /* pioA */
-                                interrupts = <2 4 1>;
+                                       0x00040000 0x00047e0f 0x00000000  /* pioB */
-                                #gpio-cells = <2>;
+                                       0xfdffffff 0x07c00000 0xb83fffff  /* pioC */
-                                gpio-controller;
+                                       0x003fffff 0x003f8000 0x00000000  /* pioD */
-                                interrupt-controller;
+                                      >;
-                                #interrupt-cells = <2>;
-                        };
-                        pioC: gpio@fffff800 {
+                                /* shared pinctrl settings */
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                dbgu {
-                                reg = <0xfffff800 0x100>;
+                                        pinctrl_dbgu: dbgu-0 {
-                                interrupts = <3 4 1>;
+                                                atmel,pins =
-                                #gpio-cells = <2>;
+                                                        <0 9 0x1 0x0    /* PA9 periph A */
-                                gpio-controller;
+                                                         0 10 0x1 0x1>; /* PA10 periph with pullup */
-                                interrupt-controller;
+                                        };
-                                #interrupt-cells = <2>;
+                                };
-                        };
-                        pioD: gpio@fffffa00 {
+                                usart0 {
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        pinctrl_usart0: usart0-0 {
-                                reg = <0xfffffa00 0x100>;
+                                                atmel,pins =
-                                interrupts = <3 4 1>;
+                                                        <0 1 0x1 0x1    /* PA1 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         0 0 0x1 0x0>;  /* PA0 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart0_rts: usart0_rts-0 {
+                                                atmel,pins =
+                                                        <0 2 0x1 0x0>;  /* PA2 periph A */
+                                        };
+                                        pinctrl_usart0_cts: usart0_cts-0 {
+                                                atmel,pins =
+                                                        <0 3 0x1 0x0>;  /* PA3 periph A */
+                                        };
+                                };
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <0 6 0x1 0x1    /* PA6 periph A with pullup */
+                                                         0 5 0x1 0x0>;  /* PA5 periph A */
+                                        };
+                                };
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <0 8 0x1 0x1    /* PA8 periph A with pullup */
+                                                         0 7 0x1 0x0>;  /* PA7 periph A */
+                                        };
+                                        pinctrl_usart2_rts: usart2_rts-0 {
+                                                atmel,pins =
+                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                        };
+                                        pinctrl_usart2_cts: usart2_cts-0 {
+                                                atmel,pins =
+                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                        };
+                                };
+                                usart3 {
+                                        pinctrl_usart3: usart3-0 {
+                                                atmel,pins =
+                                                        <2 23 0x2 0x1   /* PC23 periph B with pullup */
+                                                         2 22 0x2 0x0>; /* PC22 periph B */
+                                        };
+                                        pinctrl_usart3_rts: usart3_rts-0 {
+                                                atmel,pins =
+                                                        <2 24 0x2 0x0>; /* PC24 periph B */
+                                        };
+                                        pinctrl_usart3_cts: usart3_cts-0 {
+                                                atmel,pins =
+                                                        <2 25 0x2 0x0>; /* PC25 periph B */
+                                        };
+                                };
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <2 9 0x3 0x1    /* PC9 periph C with pullup */
+                                                         2 8 0x3 0x0>;  /* PC8 periph C */
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <2 16 0x3 0x1   /* PC17 periph C with pullup */
+                                                         2 17 0x3 0x0>; /* PC16 periph C */
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <3 5 0x0 0x1    /* PD5 gpio RDY pin pull_up*/
+                                                         3 4 0x0 0x1>;  /* PD4 gpio enable pin pull_up */
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 17 0x1 0x0   /* PA17 periph A */
+                                                         0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                         0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+                                                atmel,pins =
+                                                        <0 11 0x2 0x1   /* PA11 periph B with pullup */
+                                                         0 12 0x2 0x1   /* PA12 periph B with pullup */
+                                                         0 13 0x2 0x1   /* PA13 periph B with pullup */
+                                                         0 14 0x2 0x1>; /* PA14 periph B with pullup */
+                                        };
+                                };
+                                pioA: gpio@fffff400 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioB: gpio@fffff600 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioC: gpio@fffff800 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioD: gpio@fffffa00 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                        };
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
@@ -155,6 +300,8 @@
                                interrupts = <5 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
@@ -164,6 +311,8 @@
                                interrupts = <6 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
@@ -173,6 +322,8 @@
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
@@ -182,6 +333,8 @@
                                interrupts = <8 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
                                status = "disabled";
                        };
@@ -215,6 +368,8 @@
                               >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioD 5 0
                                 &pioD 4 0
                                 0
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 912b2c283d6f..0376bf4fd66b 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -45,6 +45,28 @@
                        i2c1: i2c@f8014000 {
                                status = "okay";
                        };
+                        mmc0: mmc@f0008000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioA 7 0>;
+                                };
+                        };
+                        pinctrl@fffff400 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <0 7 0x0 0x5>;  /* PA7 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
new file mode 100644
index 000000000000..54eb33ba6d22
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -0,0 +1,49 @@
+/*
+ * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/include/ "at91sam9x5.dtsi"
+/ {
+        model = "Atmel AT91SAM9X25 SoC";
+        compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
+        ahb {
+                apb {
+                        pinctrl@fffff400 {
+                                atmel,mux-mask = <
+                                      /*    A         B          C     */
+                                       0xffffffff 0xffe03fff 0xc000001c  /* pioA */
+                                       0x0007ffff 0x00047e3f 0x00000000  /* pioB */
+                                       0x80000000 0xfffd0000 0xb83fffff  /* pioC */
+                                       0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                      >;
+                                macb1 {
+                                        pinctrl_macb1_rmii: macb1_rmii-0 {
+                                                atmel,pins =
+                                                        <2 16 0x2 0x0   /* PC16 periph B */
+                                                         2 18 0x2 0x0   /* PC18 periph B */
+                                                         2 19 0x2 0x0   /* PC19 periph B */
+                                                         2 20 0x2 0x0   /* PC20 periph B */
+                                                         2 21 0x2 0x0   /* PC21 periph B */
+                                                         2 27 0x2 0x0   /* PC27 periph B */
+                                                         2 28 0x2 0x0   /* PC28 periph B */
+                                                         2 29 0x2 0x0   /* PC29 periph B */
+                                                         2 30 0x2 0x0   /* PC30 periph B */
+                                                         2 31 0x2 0x0>; /* PC31 periph B */
+                                        };
+                                };
+                        };
+                        macb1: ethernet@f8030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb1_rmii>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
new file mode 100644
index 000000000000..af907eaa1f25
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x25.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+/ {
+        model = "Atmel AT91SAM9G25-EK";
+        compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
new file mode 100644
index 000000000000..fb102d6126ce
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/include/ "at91sam9x5.dtsi"
+/ {
+        model = "Atmel AT91SAM9X35 SoC";
+        compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
+        ahb {
+                apb {
+                        pinctrl@fffff400 {
+                                atmel,mux-mask = <
+                                      /*    A         B          C     */
+                                       0xffffffff 0xffe03fff 0xc000000c  /* pioA */
+                                       0x000406ff 0x00047e3f 0x00000000  /* pioB */
+                                       0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+                                       0x003fffff 0x003f8000 0x00000000  /* pioD */
+                                      >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
new file mode 100644
index 000000000000..5ccb607b5414
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x35.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+/ {
+        model = "Atmel AT91SAM9X35-EK";
+        compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 03fc136421c5..617ede541ca2 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -30,6 +30,7 @@
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                i2c2 = &i2c2;
+                ssc0 = &ssc0;
        };
        cpus {
                cpu@0 {
@@ -87,6 +88,13 @@
                                interrupts = <1 4 7>;
                        };
+                        ssc0: ssc@f0010000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf0010000 0x4000>;
+                                interrupts = <28 4 5>;
+                                status = "disable";
+                        };
                        tcb0: timer@f8008000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8008000 0x100>;
@@ -111,50 +119,244 @@
                                interrupts = <21 4 0>;
                        };
-                        pioA: gpio@fffff400 {
+                        pinctrl@fffff400 {
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                #address-cells = <1>;
-                                reg = <0xfffff400 0x100>;
+                                #size-cells = <1>;
-                                interrupts = <2 4 1>;
+                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
-                                #gpio-cells = <2>;
+                                ranges = <0xfffff400 0xfffff400 0x800>;
-                                gpio-controller;
-                                interrupt-controller;
+                                /* shared pinctrl settings */
-                                #interrupt-cells = <2>;
+                                dbgu {
-                        };
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <0 9 0x1 0x0    /* PA9 periph A */
+                                                         0 10 0x1 0x1>; /* PA10 periph A with pullup */
+                                        };
+                                };
-                        pioB: gpio@fffff600 {
+                                usart0 {
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        pinctrl_usart0: usart0-0 {
-                                reg = <0xfffff600 0x100>;
+                                                atmel,pins =
-                                interrupts = <2 4 1>;
+                                                        <0 0 0x1 0x1    /* PA0 periph A with pullup */
-                                #gpio-cells = <2>;
+                                                         0 1 0x1 0x0>;  /* PA1 periph A */
-                                gpio-controller;
+                                        };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                        pinctrl_usart0_rts: usart0_rts-0 {
+                                                atmel,pins =
+                                                        <0 2 0x1 0x0>;  /* PA2 periph A */
+                                        };
+                                        pinctrl_usart0_cts: usart0_cts-0 {
+                                                atmel,pins =
+                                                        <0 3 0x1 0x0>;  /* PA3 periph A */
+                                        };
+                                };
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <0 5 0x1 0x1    /* PA5 periph A with pullup */
+                                                         0 6 0x1 0x0>;  /* PA6 periph A */
+                                        };
+                                        pinctrl_usart1_rts: usart1_rts-0 {
+                                                atmel,pins =
+                                                        <3 27 0x3 0x0>; /* PC27 periph C */
+                                        };
+                                        pinctrl_usart1_cts: usart1_cts-0 {
+                                                atmel,pins =
+                                                        <3 28 0x3 0x0>; /* PC28 periph C */
+                                        };
+                                };
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
+                                                         0 8 0x1 0x0>;  /* PA8 periph A */
+                                        };
+                                        pinctrl_uart2_rts: uart2_rts-0 {
+                                                atmel,pins =
+                                                        <0 0 0x2 0x0>;  /* PB0 periph B */
+                                        };
+                                        pinctrl_uart2_cts: uart2_cts-0 {
+                                                atmel,pins =
+                                                        <0 1 0x2 0x0>;  /* PB1 periph B */
+                                        };
+                                };
+                                usart3 {
+                                        pinctrl_uart3: usart3-0 {
+                                                atmel,pins =
+                                                        <3 23 0x2 0x1   /* PC22 periph B with pullup */
+                                                         3 23 0x2 0x0>; /* PC23 periph B */
+                                        };
+                                        pinctrl_usart3_rts: usart3_rts-0 {
+                                                atmel,pins =
+                                                        <3 24 0x2 0x0>; /* PC24 periph B */
+                                        };
+                                        pinctrl_usart3_cts: usart3_cts-0 {
+                                                atmel,pins =
+                                                        <3 25 0x2 0x0>; /* PC25 periph B */
+                                        };
+                                };
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <3 8 0x3 0x0    /* PC8 periph C */
+                                                         3 9 0x3 0x1>;  /* PC9 periph C with pullup */
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <3 16 0x3 0x0   /* PC16 periph C */
+                                                         3 17 0x3 0x1>; /* PC17 periph C with pullup */
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <3 4 0x0 0x1    /* PD5 gpio RDY pin pull_up */
+                                                         3 5 0x0 0x1>;  /* PD4 gpio enable pin pull_up */
+                                        };
+                                };
+                                macb0 {
+                                        pinctrl_macb0_rmii: macb0_rmii-0 {
+                                                atmel,pins =
+                                                        <1 0 0x1 0x0    /* PB0 periph A */
+                                                         1 1 0x1 0x0    /* PB1 periph A */
+                                                         1 2 0x1 0x0    /* PB2 periph A */
+                                                         1 3 0x1 0x0    /* PB3 periph A */
+                                                         1 4 0x1 0x0    /* PB4 periph A */
+                                                         1 5 0x1 0x0    /* PB5 periph A */
+                                                         1 6 0x1 0x0    /* PB6 periph A */
+                                                         1 7 0x1 0x0    /* PB7 periph A */
+                                                         1 9 0x1 0x0    /* PB9 periph A */
+                                                         1 10 0x1 0x0>; /* PB10 periph A */
+                                        };
+                                        pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+                                                atmel,pins =
+                                                        <1 8 0x1 0x0    /* PA8 periph A */
+                                                         1 11 0x1 0x0   /* PA11 periph A */
+                                                         1 12 0x1 0x0   /* PA12 periph A */
+                                                         1 13 0x1 0x0   /* PA13 periph A */
+                                                         1 14 0x1 0x0   /* PA14 periph A */
+                                                         1 15 0x1 0x0   /* PA15 periph A */
+                                                         1 16 0x1 0x0   /* PA16 periph A */
+                                                         1 17 0x1 0x0>; /* PA17 periph A */
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 17 0x1 0x0   /* PA17 periph A */
+                                                         0 16 0x1 0x1   /* PA16 periph A with pullup */
+                                                         0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
+                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
+                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                        };
+                                };
+                                mmc1 {
+                                        pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <0 13 0x2 0x0   /* PA13 periph B */
+                                                         0 12 0x2 0x1   /* PA12 periph B with pullup */
+                                                         0 11 0x2 0x1>; /* PA11 periph B with pullup */
+                                        };
+                                        pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <0 2 0x2 0x1    /* PA2 periph B with pullup */
+                                                         0 3 0x2 0x1    /* PA3 periph B with pullup */
+                                                         0 4 0x2 0x1>;  /* PA4 periph B with pullup */
+                                        };
+                                };
+                                pioA: gpio@fffff400 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioB: gpio@fffff600 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <2 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        #gpio-lines = <19>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioC: gpio@fffff800 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+                                pioD: gpio@fffffa00 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x200>;
+                                        interrupts = <3 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        #gpio-lines = <22>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                        };
-                        pioC: gpio@fffff800 {
+                        mmc0: mmc@f0008000 {
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                compatible = "atmel,hsmci";
-                                reg = <0xfffff800 0x100>;
+                                reg = <0xf0008000 0x600>;
-                                interrupts = <3 4 1>;
+                                interrupts = <12 4 0>;
-                                #gpio-cells = <2>;
+                                #address-cells = <1>;
-                                gpio-controller;
+                                #size-cells = <0>;
-                                interrupt-controller;
+                                status = "disabled";
-                                #interrupt-cells = <2>;
                        };
-                        pioD: gpio@fffffa00 {
+                        mmc1: mmc@f000c000 {
-                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                compatible = "atmel,hsmci";
-                                reg = <0xfffffa00 0x100>;
+                                reg = <0xf000c000 0x600>;
-                                interrupts = <3 4 1>;
+                                interrupts = <26 4 0>;
-                                #gpio-cells = <2>;
+                                #address-cells = <1>;
-                                gpio-controller;
+                                #size-cells = <0>;
-                                interrupt-controller;
+                                status = "disabled";
-                                #interrupt-cells = <2>;
                        };
                        dbgu: serial@fffff200 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xfffff200 0x200>;
                                interrupts = <1 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
                                status = "disabled";
                        };
@@ -164,6 +366,8 @@
                                interrupts = <5 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
                                status = "disabled";
                        };
@@ -173,6 +377,8 @@
                                interrupts = <6 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
                                status = "disabled";
                        };
@@ -182,6 +388,8 @@
                                interrupts = <7 4 5>;
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
                                status = "disabled";
                        };
@@ -189,6 +397,8 @@
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xf802c000 0x100>;
                                interrupts = <24 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb0_rmii>;
                                status = "disabled";
                        };
@@ -273,6 +483,8 @@
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioD 5 0
                                 &pioD 4 0
                                 0
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
new file mode 100644
index 000000000000..8a7cf1d9cf5d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -0,0 +1,101 @@
+/*
+ * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "at91sam9x5cm.dtsi"
+/ {
+        model = "Atmel AT91SAM9X5-EK";
+        compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+        chosen {
+                bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+        };
+        ahb {
+                apb {
+                        mmc0: mmc@f0008000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 15 0>;
+                                };
+                        };
+                        mmc1: mmc@f000c000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc1
+                                        &pinctrl_mmc1_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc1_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 14 0>;
+                                };
+                        };
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        usart0: serial@f801c000 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                        i2c0: i2c@f8010000 {
+                                status = "okay";
+                        };
+                        i2c1: i2c@f8014000 {
+                                status = "okay";
+                        };
+                        i2c2: i2c@f8018000 {
+                                status = "okay";
+                        };
+                        pinctrl@fffff400 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                                mmc1 {
+                                        pinctrl_board_mmc1: mmc1-board {
+                                                atmel,pins =
+                                                        <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                        };
+                };
+                usb0: ohci@00600000 {
+                        status = "okay";
+                        num-ports = <2>;
+                        atmel,vbus-gpio = <&pioD 19 1
+                                           &pioD 20 1
+                                          >;
+                };
+                usb1: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
new file mode 100644
index 000000000000..248067cf7069
--- /dev/null
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "bcm11351.dtsi"
+/ {
+        model = "BCM11351 BRT board";
+        compatible = "bcm,bcm11351-brt", "bcm,bcm11351";
+        memory {
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+        uart@3e000000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
new file mode 100644
index 000000000000..ad135885bd2a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "BCM11351 SoC";
+        compatible = "bcm,bcm11351";
+        interrupt-parent = <&gic>;
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gic: interrupt-controller@3ff00100 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x3ff01000 0x1000>,
+                      <0x3ff00100 0x100>;
+        };
+        uart@3e000000 {
+                compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
+                status = "disabled";
+                reg = <0x3e000000 0x1000>;
+                clock-frequency = <13000000>;
+                interrupts = <0x0 67 0x4>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
+        L2: l2-cache {
+                    compatible = "arm,pl310-cache";
+                    reg = <0x3ff20000 0x1000>;
+                    cache-unified;
+                    cache-level = <2>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 7dd860f83f96..9b72054a0bc0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -10,3 +10,18 @@
                reg = <0 0x10000000>;
        };
 };
+&gpio {
+        pinctrl-names = "default";
+        pinctrl-0 = <&alt0 &alt3>;
+        alt0: alt0 {
+                brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>;
+                brcm,function = <4>; /* alt0 */
+        };
+        alt3: alt3 {
+                brcm,pins = <48 49 50 51 52 53>;
+                brcm,function = <7>; /* alt3 */
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 0b619398532c..8917550fd1bb 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -29,11 +29,39 @@
                        #interrupt-cells = <2>;
                };
+                watchdog {
+                        compatible = "brcm,bcm2835-pm-wdt";
+                        reg = <0x7e100000 0x28>;
+                };
                uart@20201000 {
                        compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
                        reg = <0x7e201000 0x1000>;
                        interrupts = <2 25>;
                        clock-frequency = <3000000>;
                };
+                gpio: gpio {
+                        compatible = "brcm,bcm2835-gpio";
+                        reg = <0x7e200000 0xb4>;
+                        /*
+                         * The GPIO IP block is designed for 3 banks of GPIOs.
+                         * Each bank has a GPIO interrupt for itself.
+                         * There is an overall "any bank" interrupt.
+                         * In order, these are GIC interrupts 17, 18, 19, 20.
+                         * Since the BCM2835 only has 2 banks, the 2nd bank
+                         * interrupt output appears to be mirrored onto the
+                         * 3rd bank's interrupt signal.
+                         * So, a bank0 interrupt shows up on 17, 20, and
+                         * a bank1 interrupt shows up on 18, 19, 20!
+                         */
+                        interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
new file mode 100644
index 000000000000..04305463f00d
--- /dev/null
+++ b/arch/arm/boot/dts/ccu9540.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "dbx5x0.dtsi"
+/ {
+        model = "ST-Ericsson CCU9540 platform with Device Tree";
+        compatible = "st-ericsson,ccu9540", "st-ericsson,u9540";
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+        soc-u9500 {
+                uart@80120000 {
+                        status = "okay";
+                };
+                uart@80121000 {
+                        status = "okay";
+                };
+                uart@80007000 {
+                        status = "okay";
+                };
+                // External Micro SD slot
+                sdi0_per1@80126000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <100000000>;
+                        bus-width = <4>;
+                        mmc-cap-sd-highspeed;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        cd-gpios  = <&gpio7 6 0x4>; // 230
+                        cd-inverted;
+                        status = "okay";
+                };
+                // WLAN SDIO channel
+                sdi1_per2@80118000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
+                        status = "okay";
+                };
+                // On-board eMMC
+                sdi4_per2@80114000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <100000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
new file mode 100644
index 000000000000..fddd17417433
--- /dev/null
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -0,0 +1,184 @@
+/*
+ * Common device tree include for all Exynos 5250 boards based off of Daisy.
+ *
+ * Copyright (c) 2012 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/ {
+        aliases {
+        };
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+        chosen {
+        };
+        i2c@12C60000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <378000>;
+                gpios = <&gpb3 0 2 3 0>,
+                        <&gpb3 1 2 3 0>;
+        };
+        i2c@12C70000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <378000>;
+                gpios = <&gpb3 2 2 3 0>,
+                        <&gpb3 3 2 3 0>;
+        };
+        i2c@12C80000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <66000>;
+                /*
+                 * Disabled pullups since external part has its own pullups and
+                 * double-pulling gets us out of spec in some cases.
+                 */
+                gpios = <&gpa0 6 3 0 0>,
+                        <&gpa0 7 3 0 0>;
+                hdmiddc@50 {
+                        compatible = "samsung,exynos5-hdmiddc";
+                        reg = <0x50>;
+                };
+        };
+        i2c@12C90000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <66000>;
+                gpios = <&gpa1 2 3 3 0>,
+                        <&gpa1 3 3 3 0>;
+        };
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+        i2c@12CB0000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <66000>;
+                gpios = <&gpa2 2 3 3 0>,
+                        <&gpa2 3 3 3 0>;
+        };
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+        i2c@12CD0000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <66000>;
+                gpios = <&gpb2 2 3 3 0>,
+                        <&gpb2 3 3 3 0>;
+        };
+        i2c@12CE0000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <378000>;
+                hdmiphy@38 {
+                        compatible = "samsung,exynos5-hdmiphy";
+                        reg = <0x38>;
+                };
+        };
+        dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3 3>;
+                samsung,dw-mshc-ddr-timing = <1 2 3>;
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
+                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
+                };
+        };
+        dwmmc1@12210000 {
+                status = "disabled";
+        };
+        dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3 3>;
+                samsung,dw-mshc-ddr-timing = <1 2 3>;
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        wp-gpios = <&gpc2 1 0 0 3>;
+                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
+                };
+        };
+        dwmmc3@12230000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3 3>;
+                samsung,dw-mshc-ddr-timing = <1 2 3>;
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        /* See board-specific dts files for GPIOs */
+                };
+        };
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+        spi_1: spi@12d30000 {
+                gpios = <&gpa2 4 2 3 0>,
+                        <&gpa2 6 2 3 0>,
+                        <&gpa2 7 2 3 0>;
+                samsung,spi-src-clk = <0>;
+                num-cs = <1>;
+        };
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
+        hdmi {
+                hpd-gpio = <&gpx3 7 0xf 1 3>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power";
+                        gpios = <&gpx1 3 0 0x10000 0>;
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
new file mode 100644
index 000000000000..422fdb3fcfc1
--- /dev/null
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -0,0 +1,30 @@
+/*
+ * Device Tree for AM1808 EnBW CMC board
+ *
+ * Copyright 2012 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/include/ "da850.dtsi"
+/ {
+        compatible = "enbw,cmc", "ti,da850";
+        model = "EnBW CMC";
+        soc {
+                serial0: serial@1c42000 {
+                        status = "okay";
+                };
+                serial1: serial@1d0c000 {
+                        status = "okay";
+                };
+                serial2: serial@1d0d000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
new file mode 100644
index 000000000000..37dc5a3243b8
--- /dev/null
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -0,0 +1,28 @@
+/*
+ * Device Tree for DA850 EVM board
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation, version 2.
+ */
+/dts-v1/;
+/include/ "da850.dtsi"
+/ {
+        compatible = "ti,da850-evm", "ti,da850";
+        model = "DA850/AM1808/OMAP-L138 EVM";
+        soc {
+                serial0: serial@1c42000 {
+                        status = "okay";
+                };
+                serial1: serial@1d0c000 {
+                        status = "okay";
+                };
+                serial2: serial@1d0d000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
new file mode 100644
index 000000000000..640ab75c20db
--- /dev/null
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2012 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        arm {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                intc: interrupt-controller {
+                        compatible = "ti,cp-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        ti,intc-size = <100>;
+                        reg = <0xfffee000 0x2000>;
+                };
+        };
+        soc {
+                compatible = "simple-bus";
+                model = "da850";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x01c00000 0x400000>;
+                serial0: serial@1c42000 {
+                        compatible = "ns16550a";
+                        reg = <0x42000 0x100>;
+                        clock-frequency = <150000000>;
+                        reg-shift = <2>;
+                        interrupts = <25>;
+                        interrupt-parent = <&intc>;
+                        status = "disabled";
+                };
+                serial1: serial@1d0c000 {
+                        compatible = "ns16550a";
+                        reg = <0x10c000 0x100>;
+                        clock-frequency = <150000000>;
+                        reg-shift = <2>;
+                        interrupts = <53>;
+                        interrupt-parent = <&intc>;
+                        status = "disabled";
+                };
+                serial2: serial@1d0d000 {
+                        compatible = "ns16550a";
+                        reg = <0x10d000 0x100>;
+                        clock-frequency = <150000000>;
+                        reg-shift = <2>;
+                        interrupts = <61>;
+                        interrupt-parent = <&intc>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 4b0e0ca08f40..2efd9c891bc9 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -203,129 +203,117 @@
                                reg = <0x80157450 0xC>;
                        };
+                        thermal@801573c0 {
+                                compatible = "stericsson,db8500-thermal";
+                                reg = <0x801573c0 0x40>;
+                                interrupts = <21 0x4>, <22 0x4>;
+                                interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
+                                status = "disabled";
+                         };
                        db8500-prcmu-regulators {
                                compatible = "stericsson,db8500-prcmu-regulator";
                                // DB8500_REGULATOR_VAPE
                                db8500_vape_reg: db8500_vape {
                                        regulator-compatible = "db8500_vape";
-                                        regulator-name = "db8500-vape";
                                        regulator-always-on;
                                };
                                // DB8500_REGULATOR_VARM
                                db8500_varm_reg: db8500_varm {
                                        regulator-compatible = "db8500_varm";
-                                        regulator-name = "db8500-varm";
                                };
                                // DB8500_REGULATOR_VMODEM
                                db8500_vmodem_reg: db8500_vmodem {
                                        regulator-compatible = "db8500_vmodem";
-                                        regulator-name = "db8500-vmodem";
                                };
                                // DB8500_REGULATOR_VPLL
                                db8500_vpll_reg: db8500_vpll {
                                        regulator-compatible = "db8500_vpll";
-                                        regulator-name = "db8500-vpll";
                                };
                                // DB8500_REGULATOR_VSMPS1
                                db8500_vsmps1_reg: db8500_vsmps1 {
                                        regulator-compatible = "db8500_vsmps1";
-                                        regulator-name = "db8500-vsmps1";
                                };
                                // DB8500_REGULATOR_VSMPS2
                                db8500_vsmps2_reg: db8500_vsmps2 {
                                        regulator-compatible = "db8500_vsmps2";
-                                        regulator-name = "db8500-vsmps2";
                                };
                                // DB8500_REGULATOR_VSMPS3
                                db8500_vsmps3_reg: db8500_vsmps3 {
                                        regulator-compatible = "db8500_vsmps3";
-                                        regulator-name = "db8500-vsmps3";
                                };
                                // DB8500_REGULATOR_VRF1
                                db8500_vrf1_reg: db8500_vrf1 {
                                        regulator-compatible = "db8500_vrf1";
-                                        regulator-name = "db8500-vrf1";
                                };
                                // DB8500_REGULATOR_SWITCH_SVAMMDSP
                                db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
                                        regulator-compatible = "db8500_sva_mmdsp";
-                                        regulator-name = "db8500-sva-mmdsp";
                                };
                                // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
                                db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
                                        regulator-compatible = "db8500_sva_mmdsp_ret";
-                                        regulator-name = "db8500-sva-mmdsp-ret";
                                };
                                // DB8500_REGULATOR_SWITCH_SVAPIPE
                                db8500_sva_pipe_reg: db8500_sva_pipe {
                                        regulator-compatible = "db8500_sva_pipe";
-                                        regulator-name = "db8500_sva_pipe";
                                };
                                // DB8500_REGULATOR_SWITCH_SIAMMDSP
                                db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
                                        regulator-compatible = "db8500_sia_mmdsp";
-                                        regulator-name = "db8500_sia_mmdsp";
                                };
                                // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
                                db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
-                                        regulator-name = "db8500-sia-mmdsp-ret";
                                };
                                // DB8500_REGULATOR_SWITCH_SIAPIPE
                                db8500_sia_pipe_reg: db8500_sia_pipe {
                                        regulator-compatible = "db8500_sia_pipe";
-                                        regulator-name = "db8500-sia-pipe";
                                };
                                // DB8500_REGULATOR_SWITCH_SGA
                                db8500_sga_reg: db8500_sga {
                                        regulator-compatible = "db8500_sga";
-                                        regulator-name = "db8500-sga";
                                        vin-supply = <&db8500_vape_reg>;
                                };
                                // DB8500_REGULATOR_SWITCH_B2R2_MCDE
                                db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
                                        regulator-compatible = "db8500_b2r2_mcde";
-                                        regulator-name = "db8500-b2r2-mcde";
                                        vin-supply = <&db8500_vape_reg>;
                                };
                                // DB8500_REGULATOR_SWITCH_ESRAM12
                                db8500_esram12_reg: db8500_esram12 {
                                        regulator-compatible = "db8500_esram12";
-                                        regulator-name = "db8500-esram12";
                                };
                                // DB8500_REGULATOR_SWITCH_ESRAM12RET
                                db8500_esram12_ret_reg: db8500_esram12_ret {
                                        regulator-compatible = "db8500_esram12_ret";
-                                        regulator-name = "db8500-esram12-ret";
                                };
                                // DB8500_REGULATOR_SWITCH_ESRAM34
                                db8500_esram34_reg: db8500_esram34 {
                                        regulator-compatible = "db8500_esram34";
-                                        regulator-name = "db8500-esram34";
                                };
                                // DB8500_REGULATOR_SWITCH_ESRAM34RET
                                db8500_esram34_ret_reg: db8500_esram34_ret {
                                        regulator-compatible = "db8500_esram34_ret";
-                                        regulator-name = "db8500-esram34-ret";
                                };
                        };
@@ -352,7 +340,33 @@
                                        vddadc-supply = <&ab8500_ldo_tvout_reg>;
                                };
-                                ab8500-usb {
+                                ab8500_battery: ab8500_battery {
+                                        stericsson,battery-type = "LIPO";
+                                        thermistor-on-batctrl;
+                                };
+                                ab8500_fg {
+                                        compatible = "stericsson,ab8500-fg";
+                                        battery    = <&ab8500_battery>;
+                                };
+                                ab8500_btemp {
+                                        compatible = "stericsson,ab8500-btemp";
+                                        battery    = <&ab8500_battery>;
+                                };
+                                ab8500_charger {
+                                        compatible      = "stericsson,ab8500-charger";
+                                        battery         = <&ab8500_battery>;
+                                        vddadc-supply   = <&ab8500_ldo_tvout_reg>;
+                                };
+                                ab8500_chargalg {
+                                        compatible      = "stericsson,ab8500-chargalg";
+                                        battery         = <&ab8500_battery>;
+                                };
+                                ab8500_usb {
                                        compatible = "stericsson,ab8500-usb";
                                        interrupts = < 90 0x4
                                                       96 0x4
@@ -404,7 +418,6 @@
                                        // supplies to the display/camera
                                        ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
                                                regulator-compatible = "ab8500_ldo_aux1";
-                                                regulator-name = "V-DISPLAY";
                                                regulator-min-microvolt = <2500000>;
                                                regulator-max-microvolt = <2900000>;
                                                regulator-boot-on;
@@ -415,7 +428,6 @@
                                        // supplies to the on-board eMMC
                                        ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
                                                regulator-compatible = "ab8500_ldo_aux2";
-                                                regulator-name = "V-eMMC1";
                                                regulator-min-microvolt = <1100000>;
                                                regulator-max-microvolt = <3300000>;
                                        };
@@ -423,7 +435,6 @@
                                        // supply for VAUX3; SDcard slots
                                        ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
                                                regulator-compatible = "ab8500_ldo_aux3";
-                                                regulator-name = "V-MMC-SD";
                                                regulator-min-microvolt = <1100000>;
                                                regulator-max-microvolt = <3300000>;
                                        };
@@ -431,49 +442,41 @@
                                        // supply for v-intcore12; VINTCORE12 LDO
                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
                                                regulator-compatible = "ab8500_ldo_initcore";
-                                                regulator-name = "V-INTCORE";
                                        };
                                        // supply for tvout; gpadc; TVOUT LDO
                                        ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
                                                regulator-compatible = "ab8500_ldo_tvout";
-                                                regulator-name = "V-TVOUT";
                                        };
                                        // supply for ab8500-usb; USB LDO
                                        ab8500_ldo_usb_reg: ab8500_ldo_usb {
                                                regulator-compatible = "ab8500_ldo_usb";
-                                                regulator-name = "dummy";
                                        };
                                        // supply for ab8500-vaudio; VAUDIO LDO
                                        ab8500_ldo_audio_reg: ab8500_ldo_audio {
                                                regulator-compatible = "ab8500_ldo_audio";
-                                                regulator-name = "V-AUD";
                                        };
                                        // supply for v-anamic1 VAMic1-LDO
                                        ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
                                                regulator-compatible = "ab8500_ldo_anamic1";
-                                                regulator-name = "V-AMIC1";
                                        };
                                        // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
                                                regulator-compatible = "ab8500_ldo_amamic2";
-                                                regulator-name = "V-AMIC2";
                                        };
                                        // supply for v-dmic; VDMIC LDO
                                        ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
                                                regulator-compatible = "ab8500_ldo_dmic";
-                                                regulator-name = "V-DMIC";
                                        };
                                        // supply for U8500 CSI/DSI; VANA LDO
                                        ab8500_ldo_ana_reg: ab8500_ldo_ana {
                                                regulator-compatible = "ab8500_ldo_ana";
-                                                regulator-name = "V-CSI/DSI";
                                        };
                                };
                        };
@@ -577,42 +580,42 @@
                        status = "disabled";
                };
-                sdi@80126000 {
+                sdi0_per1@80126000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80126000 0x1000>;
                        interrupts = <0 60 0x4>;
                        status = "disabled";
                };
-                sdi@80118000 {
+                sdi1_per2@80118000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80118000 0x1000>;
                        interrupts = <0 50 0x4>;
                        status = "disabled";
                };
-                sdi@80005000 {
+                sdi2_per3@80005000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80005000 0x1000>;
                        interrupts = <0 41 0x4>;
                        status = "disabled";
                };
-                sdi@80119000 {
+                sdi3_per2@80119000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80119000 0x1000>;
                        interrupts = <0 59 0x4>;
                        status = "disabled";
                };
-                sdi@80114000 {
+                sdi4_per2@80114000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80114000 0x1000>;
                        interrupts = <0 99 0x4>;
                        status = "disabled";
                };
-                sdi@80008000 {
+                sdi5_per3@80008000 {
                        compatible = "arm,pl18x", "arm,primecell";
                        reg = <0x80008000 0x1000>;
                        interrupts = <0 100 0x4>;
@@ -660,5 +663,24 @@
                        ranges = <0 0x50000000 0x4000000>;
                        status = "disabled";
                };
+                cpufreq-cooling {
+                        compatible = "stericsson,db8500-cpufreq-cooling";
+                        status = "disabled";
+                 };
+                vmmci: regulator-gpio {
+                        compatible = "regulator-gpio";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <2600000>;
+                        regulator-name = "mmci-reg";
+                        regulator-type = "voltage";
+                        states = <1800000 0x1
+                                  2900000 0x0>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 0adbd5a38095..fed7d3f9f431 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -40,3 +40,13 @@
                reg = <0>;
        };
 };
+&pinctrl {
+        pinctrl-0 = <&pmx_gpio_18>;
+        pinctrl-names = "default";
+        pmx_gpio_18: pmx-gpio-18 {
+                marvell,pins = "mpp18";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index b1cfa52ae223..f3f7e9d8adca 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -4,6 +4,12 @@
        compatible = "marvell,dove";
        model = "Marvell Armada 88AP510 SoC";
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
        soc@f1000000 {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -85,7 +91,8 @@
                        #gpio-cells = <2>;
                        gpio-controller;
                        reg = <0xd0400 0x20>;
-                        ngpio = <32>;
+                        ngpios = <32>;
+                        interrupt-controller;
                        interrupts = <12>, <13>, <14>, <60>;
                };
@@ -94,7 +101,8 @@
                        #gpio-cells = <2>;
                        gpio-controller;
                        reg = <0xd0420 0x20>;
-                        ngpio = <32>;
+                        ngpios = <32>;
+                        interrupt-controller;
                        interrupts = <61>;
                };
@@ -103,7 +111,12 @@
                        #gpio-cells = <2>;
                        gpio-controller;
                        reg = <0xe8400 0x0c>;
-                        ngpio = <8>;
+                        ngpios = <8>;
+                };
+                pinctrl: pinctrl@d0200 {
+                        compatible = "marvell,dove-pinctrl";
+                        reg = <0xd0200 0x10>;
                };
                spi0: spi@10600 {
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
new file mode 100644
index 000000000000..46477ac1de99
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/dts-v1/;
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+/ {
+        model = "Calxeda ECX-2000";
+        compatible = "calxeda,ecx-2000";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        clock-ranges;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        reg = <2>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        reg = <3>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
+                };
+        };
+        memory@0 {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
+        };
+        memory@200000000 {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
+        };
+        soc {
+                ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
+                timer {
+                        compatible = "arm,cortex-a15-timer", "arm,armv7-timer";                         interrupts = <1 13 0xf08>,
+                                <1 14 0xf08>,
+                                <1 11 0xf08>,
+                                <1 10 0xf08>;
+                };
+                intc: interrupt-controller@fff11000 {
+                        compatible = "arm,cortex-a15-gic";
+                        #interrupt-cells = <3>;
+                        #size-cells = <0>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        interrupts = <1 9 0xf04>;
+                        reg = <0xfff11000 0x1000>,
+                              <0xfff12000 0x1000>,
+                              <0xfff14000 0x2000>,
+                              <0xfff16000 0x2000>;
+                };
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
+                };
+        };
+};
+/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
new file mode 100644
index 000000000000..d61b535f682a
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/ {
+        chosen {
+                bootargs = "console=ttyAMA0";
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                sata@ffe08000 {
+                        compatible = "calxeda,hb-ahci";
+                        reg = <0xffe08000 0x10000>;
+                        interrupts = <0 83 4>;
+                        dma-coherent;
+                        calxeda,port-phys = <&combophy5 0 &combophy0 0
+                                             &combophy0 1 &combophy0 2
+                                             &combophy0 3>;
+                };
+                sdhci@ffe0e000 {
+                        compatible = "calxeda,hb-sdhci";
+                        reg = <0xffe0e000 0x1000>;
+                        interrupts = <0 90 4>;
+                        clocks = <&eclk>;
+                        status = "disabled";
+                };
+                memory-controller@fff00000 {
+                        compatible = "calxeda,hb-ddr-ctrl";
+                        reg = <0xfff00000 0x1000>;
+                        interrupts = <0 91 4>;
+                };
+                ipc@fff20000 {
+                        compatible = "arm,pl320", "arm,primecell";
+                        reg = <0xfff20000 0x1000>;
+                        interrupts = <0 7 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                gpioe: gpio@fff30000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff30000 0x1000>;
+                        interrupts = <0 14 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+                gpiof: gpio@fff31000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff31000 0x1000>;
+                        interrupts = <0 15 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+                gpiog: gpio@fff32000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff32000 0x1000>;
+                        interrupts = <0 16 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+                gpioh: gpio@fff33000 {
+                        #gpio-cells = <2>;
+                        compatible = "arm,pl061", "arm,primecell";
+                        gpio-controller;
+                        reg = <0xfff33000 0x1000>;
+                        interrupts = <0 17 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+                timer@fff34000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0xfff34000 0x1000>;
+                        interrupts = <0 18 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                rtc@fff35000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0xfff35000 0x1000>;
+                        interrupts = <0 19 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                serial@fff36000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xfff36000 0x1000>;
+                        interrupts = <0 20 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                smic@fff3a000 {
+                        compatible = "ipmi-smic";
+                        device_type = "ipmi";
+                        reg = <0xfff3a000 0x1000>;
+                        interrupts = <0 24 4>;
+                        reg-size = <4>;
+                        reg-spacing = <4>;
+                };
+                sregs@fff3c000 {
+                        compatible = "calxeda,hb-sregs";
+                        reg = <0xfff3c000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                osc: oscillator {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <33333000>;
+                                };
+                                ddrpll: ddrpll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x108>;
+                                };
+                                a9pll: a9pll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x100>;
+                                };
+                                a9periphclk: a9periphclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-a9periph-clock";
+                                        clocks = <&a9pll>;
+                                        reg = <0x104>;
+                                };
+                                a9bclk: a9bclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-a9bus-clock";
+                                        clocks = <&a9pll>;
+                                        reg = <0x104>;
+                                };
+                                emmcpll: emmcpll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x10C>;
+                                };
+                                eclk: eclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-emmc-clock";
+                                        clocks = <&emmcpll>;
+                                        reg = <0x114>;
+                                };
+                                pclk: pclk {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <150000000>;
+                                };
+                        };
+                };
+                dma@fff3d000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0xfff3d000 0x1000>;
+                        interrupts = <0 92 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                ethernet@fff50000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff50000 0x1000>;
+                        interrupts = <0 77 4  0 78 4  0 79 4>;
+                        dma-coherent;
+                };
+                ethernet@fff51000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff51000 0x1000>;
+                        interrupts = <0 80 4  0 81 4  0 82 4>;
+                        dma-coherent;
+                };
+                combophy0: combo-phy@fff58000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff58000 0x1000>;
+                        phydev = <5>;
+                };
+                combophy5: combo-phy@fff5d000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff5d000 0x1000>;
+                        phydev = <31>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index b7354e6506de..96e50f569433 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -22,10 +22,22 @@
                                status = "okay";
                        };
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+                        usart2: serial@fffb8000 {
+                                status = "okay";
+                        };
                        usb1: gadget@fffa4000 {
                                atmel,vbus-gpio = <&pioC 5 0>;
                                status = "okay";
                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                };
                usb0: ohci@00500000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a26c3dd58269..e1347fceb5bc 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -28,6 +28,44 @@
                spi0 = &spi_0;
                spi1 = &spi_1;
                spi2 = &spi_2;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+                i2c2 = &i2c_2;
+                i2c3 = &i2c_3;
+                i2c4 = &i2c_4;
+                i2c5 = &i2c_5;
+                i2c6 = &i2c_6;
+                i2c7 = &i2c_7;
+        };
+        pd_mfc: mfc-power-domain@10023C40 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023C40 0x20>;
+        };
+        pd_g3d: g3d-power-domain@10023C60 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023C60 0x20>;
+        };
+        pd_lcd0: lcd0-power-domain@10023C80 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023C80 0x20>;
+        };
+        pd_tv: tv-power-domain@10023C20 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023C20 0x20>;
+        };
+        pd_cam: cam-power-domain@10023C00 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023C00 0x20>;
+        };
+        pd_gps: gps-power-domain@10023CE0 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023CE0 0x20>;
        };
        gic:interrupt-controller@10490000 {
@@ -121,7 +159,7 @@
                status = "disabled";
        };
-        i2c@13860000 {
+        i2c_0: i2c@13860000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -130,7 +168,7 @@
                status = "disabled";
        };
-        i2c@13870000 {
+        i2c_1: i2c@13870000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -139,7 +177,7 @@
                status = "disabled";
        };
-        i2c@13880000 {
+        i2c_2: i2c@13880000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -148,7 +186,7 @@
                status = "disabled";
        };
-        i2c@13890000 {
+        i2c_3: i2c@13890000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -157,7 +195,7 @@
                status = "disabled";
        };
-        i2c@138A0000 {
+        i2c_4: i2c@138A0000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -166,7 +204,7 @@
                status = "disabled";
        };
-        i2c@138B0000 {
+        i2c_5: i2c@138B0000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -175,7 +213,7 @@
                status = "disabled";
        };
-        i2c@138C0000 {
+        i2c_6: i2c@138C0000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -184,7 +222,7 @@
                status = "disabled";
        };
-        i2c@138D0000 {
+        i2c_7: i2c@138D0000 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "samsung,s3c2440-i2c";
@@ -244,5 +282,11 @@
                        reg = <0x12690000 0x1000>;
                        interrupts = <0 36 0>;
                };
+                mdma1: mdma@12850000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12850000 0x1000>;
+                        interrupts = <0 34 0>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 3e68f52e8454..f2710018e84e 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -22,38 +22,54 @@
        compatible = "insignal,origen", "samsung,exynos4210";
        memory {
-                reg = <0x40000000 0x40000000>;
+                reg = <0x40000000 0x10000000
+                       0x50000000 0x10000000
+                       0x60000000 0x10000000
+                       0x70000000 0x10000000>;
        };
        chosen {
                bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
        };
+        mmc_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpx1 1 0>;
+                enable-active-high;
+        };
        sdhci@12530000 {
-                samsung,sdhci-bus-width = <4>;
+                bus-width = <4>;
-                linux,mmc_cap_4_bit_data;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
-                samsung,sdhci-cd-internal;
+                pinctrl-names = "default";
-                gpio-cd = <&gpk2 2 2 3 3>;
+                vmmc-supply = <&mmc_reg>;
-                gpios = <&gpk2 0 2 0 3>,
-                        <&gpk2 1 2 0 3>,
-                        <&gpk2 3 2 3 3>,
-                        <&gpk2 4 2 3 3>,
-                        <&gpk2 5 2 3 3>,
-                        <&gpk2 6 2 3 3>;
                status = "okay";
        };
        sdhci@12510000 {
-                samsung,sdhci-bus-width = <4>;
+                bus-width = <4>;
-                linux,mmc_cap_4_bit_data;
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>;
-                samsung,sdhci-cd-internal;
+                pinctrl-names = "default";
-                gpio-cd = <&gpk0 2 2 3 3>;
+                vmmc-supply = <&mmc_reg>;
-                gpios = <&gpk0 0 2 0 3>,
+                status = "okay";
-                        <&gpk0 1 2 0 3>,
+        };
-                        <&gpk0 3 2 3 3>,
-                        <&gpk0 4 2 3 3>,
+        serial@13800000 {
-                        <&gpk0 5 2 3 3>,
+                status = "okay";
-                        <&gpk0 6 2 3 3>;
+        };
+        serial@13810000 {
+                status = "okay";
+        };
+        serial@13820000 {
+                status = "okay";
+        };
+        serial@13830000 {
                status = "okay";
        };
@@ -64,35 +80,35 @@
                up {
                        label = "Up";
-                        gpios = <&gpx2 0 0 0x10000 2>;
+                        gpios = <&gpx2 0 1>;
                        linux,code = <103>;
                        gpio-key,wakeup;
                };
                down {
                        label = "Down";
-                        gpios = <&gpx2 1 0 0x10000 2>;
+                        gpios = <&gpx2 1 1>;
                        linux,code = <108>;
                        gpio-key,wakeup;
                };
                back {
                        label = "Back";
-                        gpios = <&gpx1 7 0 0x10000 2>;
+                        gpios = <&gpx1 7 1>;
                        linux,code = <158>;
                        gpio-key,wakeup;
                };
                home {
                        label = "Home";
-                        gpios = <&gpx1 6 0 0x10000 2>;
+                        gpios = <&gpx1 6 1>;
                        linux,code = <102>;
                        gpio-key,wakeup;
                };
                menu {
                        label = "Menu";
-                        gpios = <&gpx1 5 0 0x10000 2>;
+                        gpios = <&gpx1 5 1>;
                        linux,code = <139>;
                        gpio-key,wakeup;
                };
@@ -101,7 +117,7 @@
        leds {
                compatible = "gpio-leds";
                status {
-                        gpios = <&gpx1 3 0 0x10000 2>;
+                        gpios = <&gpx1 3 1>;
                        linux,default-trigger = "heartbeat";
                };
        };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index b12cf272ad0d..55a2efb763d1 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -16,6 +16,134 @@
 / {
        pinctrl@11400000 {
+                gpa0: gpa0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpa1: gpa1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpb: gpb {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc0: gpc0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc1: gpc1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpd0: gpd0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpd1: gpd1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpe0: gpe0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpe1: gpe1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpe2: gpe2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpe3: gpe3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpe4: gpe4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf0: gpf0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf1: gpf1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf2: gpf2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf3: gpf3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
                uart0_data: uart0-data {
                        samsung,pins = "gpa0-0", "gpa0-1";
                        samsung,pin-function = <0x2>;
@@ -205,200 +333,345 @@
        };
        pinctrl@11000000 {
+                gpj0: gpj0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpj1: gpj1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpk0: gpk0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpk1: gpk1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpk2: gpk2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpk3: gpk3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpl0: gpl0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpl1: gpl1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpl2: gpl2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy1: gpy1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy2: gpy2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy3: gpy3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy4: gpy4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy5: gpy5 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy6: gpy6 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+                        #interrupt-cells = <2>;
+                };
+                gpx1: gpx1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+                        #interrupt-cells = <2>;
+                };
+                gpx2: gpx2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpx3: gpx3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
                sd0_clk: sd0-clk {
                        samsung,pins = "gpk0-0";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd0_cmd: sd0-cmd {
                        samsung,pins = "gpk0-1";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd0_cd: sd0-cd {
                        samsung,pins = "gpk0-2";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd0_bus1: sd0-bus-width1 {
                        samsung,pins = "gpk0-3";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd0_bus4: sd0-bus-width4 {
                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd0_bus8: sd0-bus-width8 {
                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd4_clk: sd4-clk {
                        samsung,pins = "gpk0-0";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd4_cmd: sd4-cmd {
                        samsung,pins = "gpk0-1";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd4_cd: sd4-cd {
                        samsung,pins = "gpk0-2";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd4_bus1: sd4-bus-width1 {
                        samsung,pins = "gpk0-3";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd4_bus4: sd4-bus-width4 {
                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd4_bus8: sd4-bus-width8 {
                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <4>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd1_clk: sd1-clk {
                        samsung,pins = "gpk1-0";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd1_cmd: sd1-cmd {
                        samsung,pins = "gpk1-1";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd1_cd: sd1-cd {
                        samsung,pins = "gpk1-2";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd1_bus1: sd1-bus-width1 {
                        samsung,pins = "gpk1-3";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd1_bus4: sd1-bus-width4 {
                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd2_clk: sd2-clk {
                        samsung,pins = "gpk2-0";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd2_cmd: sd2-cmd {
                        samsung,pins = "gpk2-1";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd2_cd: sd2-cd {
                        samsung,pins = "gpk2-2";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd2_bus1: sd2-bus-width1 {
                        samsung,pins = "gpk2-3";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd2_bus4: sd2-bus-width4 {
                        samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd2_bus8: sd2-bus-width8 {
                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
                        samsung,pin-function = <3>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd3_clk: sd3-clk {
                        samsung,pins = "gpk3-0";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd3_cmd: sd3-cmd {
                        samsung,pins = "gpk3-1";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd3_cd: sd3-cd {
                        samsung,pins = "gpk3-2";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd3_bus1: sd3-bus-width1 {
                        samsung,pins = "gpk3-3";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                sd3_bus4: sd3-bus-width4 {
                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
                        samsung,pin-function = <2>;
                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
+                        samsung,pin-drv = <3>;
                };
                eint0: ext-int0 {
@@ -438,6 +711,11 @@
        };
        pinctrl@03860000 {
+                gpz: gpz {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
                i2s0_bus: i2s0-bus {
                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
                                        "gpz-4", "gpz-5", "gpz-6";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 63610c3ba3af..9b23a8255e39 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,22 @@
                status = "okay";
        };
+        serial@13800000 {
+                status = "okay";
+        };
+        serial@13810000 {
+                status = "okay";
+        };
+        serial@13820000 {
+                status = "okay";
+        };
+        serial@13830000 {
+                status = "okay";
+        };
        keypad@100A0000 {
                samsung,keypad-num-rows = <2>;
                samsung,keypad-num-columns = <8>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index a21511c14071..c346b64dff55 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -35,24 +35,15 @@
                regulator-name = "VMEM_VDD_2.8V";
                regulator-min-microvolt = <2800000>;
                regulator-max-microvolt = <2800000>;
-                gpio = <&gpk0 2 1 0 0>;
+                gpio = <&gpk0 2 0>;
                enable-active-high;
        };
        sdhci_emmc: sdhci@12510000 {
                bus-width = <8>;
                non-removable;
-                broken-voltage;
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
-                gpios = <&gpk0 0 2 0 3>,
+                pinctrl-names = "default";
-                        <&gpk0 1 2 0 3>,
-                        <&gpk0 3 2 2 3>,
-                        <&gpk0 4 2 2 3>,
-                        <&gpk0 5 2 2 3>,
-                        <&gpk0 6 2 2 3>,
-                        <&gpk1 3 3 3 3>,
-                        <&gpk1 4 3 3 3>,
-                        <&gpk1 5 3 3 3>,
-                        <&gpk1 6 3 3 3>;
                vmmc-supply = <&vemmc_reg>;
                status = "okay";
        };
@@ -73,12 +64,74 @@
                status = "okay";
        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                vol-down-key {
+                        gpios = <&gpx2 1 1>;
+                        linux,code = <114>;
+                        label = "volume down";
+                        debounce-interval = <10>;
+                };
+                vol-up-key {
+                        gpios = <&gpx2 0 1>;
+                        linux,code = <115>;
+                        label = "volume up";
+                        debounce-interval = <10>;
+                };
+                power-key {
+                        gpios = <&gpx2 7 1>;
+                        linux,code = <116>;
+                        label = "power";
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+                ok-key {
+                        gpios = <&gpx3 5 1>;
+                        linux,code = <352>;
+                        label = "ok";
+                        debounce-interval = <10>;
+                };
+        };
+        tsp_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "TSP_FIXED_VOLTAGES";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpl0 3 0>;
+                enable-active-high;
+        };
+        i2c@13890000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-slave-addr = <0x10>;
+                samsung,i2c-max-bus-freq = <400000>;
+                pinctrl-0 = <&i2c3_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+                mms114-touchscreen@48 {
+                        compatible = "melfas,mms114";
+                        reg = <0x48>;
+                        interrupt-parent = <&gpx0>;
+                        interrupts = <4 2>;
+                        x-size = <720>;
+                        y-size = <1280>;
+                        avdd-supply = <&tsp_reg>;
+                        vdd-supply = <&tsp_reg>;
+                };
+        };
        i2c@138B0000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-slave-addr = <0x10>;
                samsung,i2c-max-bus-freq = <100000>;
-                gpios = <&gpb 6 3 3 0>,
+                pinctrl-0 = <&i2c5_bus>;
-                        <&gpb 7 3 3 0>;
+                pinctrl-names = "default";
                status = "okay";
                max8997_pmic@66 {
@@ -93,9 +146,9 @@
                        max8997,pmic-ignore-gpiodvs-side-effect;
                        max8997,pmic-buck125-default-dvs-idx = <0>;
-                        max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>,
+                        max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>,
-                                                         <&gpx0 6 1 0 0>,
+                                                         <&gpx0 6 0>,
-                                                         <&gpl0 0 1 0 0>;
+                                                         <&gpl0 0 0>;
                        max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
                                                         <1250000>, <1200000>,
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 214c557eda7f..e31bfc4a6f09 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,11 @@
                pinctrl2 = &pinctrl_2;
        };
+        pd_lcd1: lcd1-power-domain@10023CA0 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023CA0 0x20>;
+        };
        gic:interrupt-controller@10490000 {
                cpu-offset = <0x8000>;
        };
@@ -46,27 +51,17 @@
                compatible = "samsung,pinctrl-exynos4210";
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
        };
        pinctrl_1: pinctrl@11000000 {
                compatible = "samsung,pinctrl-exynos4210";
                reg = <0x11000000 0x1000>;
                interrupts = <0 46 0>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
                wakup_eint: wakeup-interrupt-controller {
                        compatible = "samsung,exynos4210-wakeup-eint";
                        interrupt-parent = <&gic>;
-                        interrupt-controller;
+                        interrupts = <0 32 0>;
-                        #interrupt-cells = <2>;
-                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                                     <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                                     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
-                                     <0 32 0>;
                };
        };
@@ -75,232 +70,10 @@
                reg = <0x03860000 0x1000>;
        };
-        gpio-controllers {
+        tmu@100C0000 {
-                #address-cells = <1>;
+                compatible = "samsung,exynos4210-tmu";
-                #size-cells = <1>;
+                interrupt-parent = <&combiner>;
-                gpio-controller;
+                reg = <0x100C0000 0x100>;
-                ranges;
+                interrupts = <2 4>;
-                gpa0: gpio-controller@11400000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400000 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpa1: gpio-controller@11400020 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400020 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpb: gpio-controller@11400040 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400040 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpc0: gpio-controller@11400060 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400060 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpc1: gpio-controller@11400080 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400080 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpd0: gpio-controller@114000A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpd1: gpio-controller@114000C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpe0: gpio-controller@114000E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpe1: gpio-controller@11400100 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400100 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpe2: gpio-controller@11400120 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400120 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpe3: gpio-controller@11400140 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400140 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpe4: gpio-controller@11400160 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400160 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpf0: gpio-controller@11400180 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400180 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpf1: gpio-controller@114001A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpf2: gpio-controller@114001C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpf3: gpio-controller@114001E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpj0: gpio-controller@11000000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000000 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpj1: gpio-controller@11000020 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000020 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpk0: gpio-controller@11000040 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000040 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpk1: gpio-controller@11000060 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000060 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpk2: gpio-controller@11000080 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000080 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpk3: gpio-controller@110000A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110000A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpl0: gpio-controller@110000C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110000C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpl1: gpio-controller@110000E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110000E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpl2: gpio-controller@11000100 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000100 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpy0: gpio-controller@11000120 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000120 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpy1: gpio-controller@11000140 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000140 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpy2: gpio-controller@11000160 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000160 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpy3: gpio-controller@11000180 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000180 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpy4: gpio-controller@110001A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110001A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpy5: gpio-controller@110001C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110001C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpy6: gpio-controller@110001E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x110001E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpx0: gpio-controller@11000C00 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C00 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpx1: gpio-controller@11000C20 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C20 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpx2: gpio-controller@11000C40 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C40 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpx3: gpio-controller@11000C60 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11000C60 0x20>;
-                        #gpio-cells = <4>;
-                };
-                gpz: gpio-controller@03860000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x03860000 0x20>;
-                        #gpio-cells = <4>;
-                };
        };
 };
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
new file mode 100644
index 000000000000..c6ae2005961f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Samsung's Exynos4212 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/include/ "exynos4x12.dtsi"
+/ {
+        compatible = "samsung,exynos4212";
+        gic:interrupt-controller@10490000 {
+                cpu-offset = <0x8000>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
new file mode 100644
index 000000000000..f05bf575cc45
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -0,0 +1,45 @@
+/*
+ * Samsung's Exynos4412 based SMDK board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's SMDK4412 board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+/ {
+        model = "Samsung SMDK evaluation board based on Exynos4412";
+        compatible = "samsung,smdk4412", "samsung,exynos4412";
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+        chosen {
+                bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+        };
+        serial@13800000 {
+                status = "okay";
+        };
+        serial@13810000 {
+                status = "okay";
+        };
+        serial@13820000 {
+                status = "okay";
+        };
+        serial@13830000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
new file mode 100644
index 000000000000..d7dfe312772a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Samsung's Exynos4412 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/include/ "exynos4x12.dtsi"
+/ {
+        compatible = "samsung,exynos4412";
+        gic:interrupt-controller@10490000 {
+                cpu-offset = <0x4000>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
new file mode 100644
index 000000000000..8e6115adcd97
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -0,0 +1,965 @@
+/*
+ * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/ {
+        pinctrl@11400000 {
+                gpa0: gpa0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpa1: gpa1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpb: gpb {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc0: gpc0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpc1: gpc1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpd0: gpd0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpd1: gpd1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf0: gpf0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf1: gpf1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf2: gpf2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpf3: gpf3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpj0: gpj0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpj1: gpj1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                uart0_data: uart0-data {
+                        samsung,pins = "gpa0-0", "gpa0-1";
+                        samsung,pin-function = <0x2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart0_fctl: uart0-fctl {
+                        samsung,pins = "gpa0-2", "gpa0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart1_data: uart1-data {
+                        samsung,pins = "gpa0-4", "gpa0-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart1_fctl: uart1-fctl {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c2_bus: i2c2-bus {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                uart2_data: uart2-data {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart2_fctl: uart2-fctl {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart_audio_a: uart-audio-a {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c3_bus: i2c3-bus {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                uart3_data: uart3-data {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart_audio_b: uart-audio-b {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                spi0_bus: spi0-bus {
+                        samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c4_bus: i2c4-bus {
+                        samsung,pins = "gpb-0", "gpb-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                spi1_bus: spi1-bus {
+                        samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c5_bus: i2c5-bus {
+                        samsung,pins = "gpb-2", "gpb-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2s1_bus: i2s1-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm1_bus: pcm1-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                ac97_bus: ac97-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2s2_bus: i2s2-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                        "gpc1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm2_bus: pcm2-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                        "gpc1-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                spdif_bus: spdif-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c6_bus: i2c6-bus {
+                        samsung,pins = "gpc1-3", "gpc1-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                spi2_bus: spi2-bus {
+                        samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
+                        samsung,pin-function = <5>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm0_out: pwm0-out {
+                        samsung,pins = "gpd0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm1_out: pwm1-out {
+                        samsung,pins = "gpd0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_ctrl: lcd-ctrl {
+                        samsung,pins = "gpd0-0", "gpd0-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c7_bus: i2c7-bus {
+                        samsung,pins = "gpd0-2", "gpd0-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm2_out: pwm2-out {
+                        samsung,pins = "gpd0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm3_out: pwm3-out {
+                        samsung,pins = "gpd0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c0_bus: i2c0-bus {
+                        samsung,pins = "gpd1-0", "gpd1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                mipi0_clk: mipi0-clk {
+                        samsung,pins = "gpd1-0", "gpd1-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c1_bus: i2c1-bus {
+                        samsung,pins = "gpd1-2", "gpd1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                mipi1_clk: mipi1-clk {
+                        samsung,pins = "gpd1-2", "gpd1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_clk: lcd-clk {
+                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_data16: lcd-data-width16 {
+                        samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+                                        "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+                                        "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_data18: lcd-data-width18 {
+                        samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+                                        "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+                                        "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_data24: lcd-data-width24 {
+                        samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+                                        "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+                                        "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                lcd_ldi: lcd-ldi {
+                        samsung,pins = "gpf3-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_port_a: cam-port-a {
+                        samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
+                                        "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
+                                        "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3",
+                                        "gpj1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@11000000 {
+                gpk0: gpk0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpk1: gpk1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpk2: gpk2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpk3: gpk3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpl0: gpl0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpl1: gpl1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpl2: gpl2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpm0: gpm0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpm1: gpm1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpm2: gpm2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpm3: gpm3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpm4: gpm4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy1: gpy1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy2: gpy2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy3: gpy3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy4: gpy4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy5: gpy5 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpy6: gpy6 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+                        #interrupt-cells = <2>;
+                };
+                gpx1: gpx1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+                        #interrupt-cells = <2>;
+                };
+                gpx2: gpx2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpx3: gpx3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                sd0_clk: sd0-clk {
+                        samsung,pins = "gpk0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_cmd: sd0-cmd {
+                        samsung,pins = "gpk0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_cd: sd0-cd {
+                        samsung,pins = "gpk0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_bus1: sd0-bus-width1 {
+                        samsung,pins = "gpk0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_bus4: sd0-bus-width4 {
+                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd0_bus8: sd0-bus-width8 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd4_clk: sd4-clk {
+                        samsung,pins = "gpk0-0";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd4_cmd: sd4-cmd {
+                        samsung,pins = "gpk0-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd4_cd: sd4-cd {
+                        samsung,pins = "gpk0-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd4_bus1: sd4-bus-width1 {
+                        samsung,pins = "gpk0-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd4_bus4: sd4-bus-width4 {
+                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd4_bus8: sd4-bus-width8 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <4>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_clk: sd1-clk {
+                        samsung,pins = "gpk1-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_cmd: sd1-cmd {
+                        samsung,pins = "gpk1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_cd: sd1-cd {
+                        samsung,pins = "gpk1-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_bus1: sd1-bus-width1 {
+                        samsung,pins = "gpk1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd1_bus4: sd1-bus-width4 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_clk: sd2-clk {
+                        samsung,pins = "gpk2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_cmd: sd2-cmd {
+                        samsung,pins = "gpk2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_cd: sd2-cd {
+                        samsung,pins = "gpk2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_bus1: sd2-bus-width1 {
+                        samsung,pins = "gpk2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_bus4: sd2-bus-width4 {
+                        samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd2_bus8: sd2-bus-width8 {
+                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd3_clk: sd3-clk {
+                        samsung,pins = "gpk3-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd3_cmd: sd3-cmd {
+                        samsung,pins = "gpk3-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+                sd3_cd: sd3-cd {
+                        samsung,pins = "gpk3-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd3_bus1: sd3-bus-width1 {
+                        samsung,pins = "gpk3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                sd3_bus4: sd3-bus-width4 {
+                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+                keypad_col0: keypad-col0 {
+                        samsung,pins = "gpl2-0";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_col1: keypad-col1 {
+                        samsung,pins = "gpl2-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_col2: keypad-col2 {
+                        samsung,pins = "gpl2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_col3: keypad-col3 {
+                        samsung,pins = "gpl2-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_col4: keypad-col4 {
+                        samsung,pins = "gpl2-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_col5: keypad-col5 {
+                        samsung,pins = "gpl2-5";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_col6: keypad-col6 {
+                        samsung,pins = "gpl2-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                keypad_col7: keypad-col7 {
+                        samsung,pins = "gpl2-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_port_b: cam-port-b {
+                        samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
+                                        "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
+                                        "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1",
+                                        "gpm2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                eint0: ext-int0 {
+                        samsung,pins = "gpx0-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint8: ext-int8 {
+                        samsung,pins = "gpx1-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint15: ext-int15 {
+                        samsung,pins = "gpx1-7";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint16: ext-int16 {
+                        samsung,pins = "gpx2-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint31: ext-int31 {
+                        samsung,pins = "gpx3-7";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@03860000 {
+                gpz: gpz {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                i2s0_bus: i2s0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4", "gpz-5", "gpz-6";
+                        samsung,pin-function = <0x2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm0_bus: pcm0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4";
+                        samsung,pin-function = <0x3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@106E0000 {
+                gpv0: gpv0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpv1: gpv1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpv2: gpv2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpv3: gpv3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                gpv4: gpv4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                c2c_bus: c2c-bus {
+                        samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
+                                        "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
+                                        "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
+                                        "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
+                                        "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
+                                        "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
+                                        "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
+                                        "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
+                                        "gpv4-0", "gpv4-1";
+                        samsung,pin-function = <0x2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
new file mode 100644
index 000000000000..179a62e46c9d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -0,0 +1,69 @@
+/*
+ * Samsung's Exynos4x12 SoCs device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/include/ "exynos4.dtsi"
+/include/ "exynos4x12-pinctrl.dtsi"
+/ {
+        aliases {
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
+                pinctrl3 = &pinctrl_3;
+        };
+        combiner:interrupt-controller@10440000 {
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                             <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
+        };
+        pinctrl_0: pinctrl@11400000 {
+                compatible = "samsung,pinctrl-exynos4x12";
+                reg = <0x11400000 0x1000>;
+                interrupts = <0 47 0>;
+        };
+        pinctrl_1: pinctrl@11000000 {
+                compatible = "samsung,pinctrl-exynos4x12";
+                reg = <0x11000000 0x1000>;
+                interrupts = <0 46 0>;
+                wakup_eint: wakeup-interrupt-controller {
+                        compatible = "samsung,exynos4210-wakeup-eint";
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 32 0>;
+                };
+        };
+        pinctrl_2: pinctrl@03860000 {
+                compatible = "samsung,pinctrl-exynos4x12";
+                reg = <0x03860000 0x1000>;
+                interrupt-parent = <&combiner>;
+                interrupts = <10 0>;
+        };
+        pinctrl_3: pinctrl@106E0000 {
+                compatible = "samsung,pinctrl-exynos4x12";
+                reg = <0x106E0000 0x1000>;
+                interrupts = <0 72 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a352df403b7a..942d5761ca97 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -17,10 +17,6 @@
        compatible = "samsung,smdk5250", "samsung,exynos5250";
        aliases {
-                mshc0 = &dwmmc_0;
-                mshc1 = &dwmmc_1;
-                mshc2 = &dwmmc_2;
-                mshc3 = &dwmmc_3;
        };
        memory {
@@ -55,8 +51,31 @@
                };
        };
+        i2c@121D0000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <40000>;
+                samsung,i2c-slave-addr = <0x38>;
+                sata-phy {
+                        compatible = "samsung,sata-phy";
+                        reg = <0x38>;
+                };
+        };
+        sata@122F0000 {
+                samsung,sata-freq = <66>;
+        };
        i2c@12C80000 {
-                status = "disabled";
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <66000>;
+                gpios = <&gpa0 6 3 3 0>,
+                        <&gpa0 7 3 3 0>;
+                hdmiddc@50 {
+                        compatible = "samsung,exynos5-hdmiddc";
+                        reg = <0x50>;
+                };
        };
        i2c@12C90000 {
@@ -79,7 +98,17 @@
                status = "disabled";
        };
-        dwmmc_0: dwmmc0@12200000 {
+        i2c@12CE0000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <66000>;
+                hdmiphy@38 {
+                        compatible = "samsung,exynos5-hdmiphy";
+                        reg = <0x38>;
+                };
+        };
+        dwmmc0@12200000 {
                num-slots = <1>;
                supports-highspeed;
                broken-cd;
@@ -100,11 +129,11 @@
                };
        };
-        dwmmc_1: dwmmc1@12210000 {
+        dwmmc1@12210000 {
                status = "disabled";
        };
-        dwmmc_2: dwmmc2@12220000 {
+        dwmmc2@12220000 {
                num-slots = <1>;
                supports-highspeed;
                fifo-depth = <0x80>;
@@ -125,7 +154,7 @@
                };
        };
-        dwmmc_3: dwmmc3@12230000 {
+        dwmmc3@12230000 {
                status = "disabled";
        };
@@ -166,4 +195,13 @@
        spi_2: spi@12d40000 {
                status = "disabled";
        };
+        hdmi {
+                hpd-gpio = <&gpx3 7 0xf 1 3>;
+        };
+        codec@11000000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
new file mode 100644
index 000000000000..17dd951c1cd2
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -0,0 +1,43 @@
+/*
+ * Google Snow board device tree source
+ *
+ * Copyright (c) 2012 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+/include/ "cros5250-common.dtsi"
+/ {
+        model = "Google Snow";
+        compatible = "google,snow", "samsung,exynos5250";
+        gpio-keys {
+                compatible = "gpio-keys";
+                lid-switch {
+                        label = "Lid";
+                        gpios = <&gpx3 5 0 0x10000 0>;
+                        linux,input-type = <5>; /* EV_SW */
+                        linux,code = <0>; /* SW_LID */
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+        };
+        /*
+         * On Snow we've got SIP WiFi and so can keep drive strengths low to
+         * reduce EMI.
+         */
+        dwmmc3@12230000 {
+                slot@0 {
+                        gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
+                                <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
+                                <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e444dc..2e3b6efaf1a2 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -31,6 +31,19 @@
                gsc1 = &gsc_1;
                gsc2 = &gsc_2;
                gsc3 = &gsc_3;
+                mshc0 = &dwmmc_0;
+                mshc1 = &dwmmc_1;
+                mshc2 = &dwmmc_2;
+                mshc3 = &dwmmc_3;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+                i2c2 = &i2c_2;
+                i2c3 = &i2c_3;
+                i2c4 = &i2c_4;
+                i2c5 = &i2c_5;
+                i2c6 = &i2c_6;
+                i2c7 = &i2c_7;
+                i2c8 = &i2c_8;
        };
        gic:interrupt-controller@10481000 {
@@ -62,12 +75,24 @@
                interrupts = <0 42 0>;
        };
+        codec@11000000 {
+                compatible = "samsung,mfc-v6";
+                reg = <0x11000000 0x10000>;
+                interrupts = <0 96 0>;
+        };
        rtc {
                compatible = "samsung,s3c6410-rtc";
                reg = <0x101E0000 0x100>;
                interrupts = <0 43 0>, <0 44 0>;
        };
+        tmu@10060000 {
+                compatible = "samsung,exynos5250-tmu";
+                reg = <0x10060000 0x100>;
+                interrupts = <0 65 0>;
+        };
        serial@12C00000 {
                compatible = "samsung,exynos4210-uart";
                reg = <0x12C00000 0x100>;
@@ -92,7 +117,18 @@
                interrupts = <0 54 0>;
        };
-        i2c@12C60000 {
+        sata@122F0000 {
+                compatible = "samsung,exynos5-sata-ahci";
+                reg = <0x122F0000 0x1ff>;
+                interrupts = <0 115 0>;
+        };
+        sata-phy@12170000 {
+                compatible = "samsung,exynos5-sata-phy";
+                reg = <0x12170000 0x1ff>;
+        };
+        i2c_0: i2c@12C60000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12C60000 0x100>;
                interrupts = <0 56 0>;
@@ -100,7 +136,7 @@
                #size-cells = <0>;
        };
-        i2c@12C70000 {
+        i2c_1: i2c@12C70000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12C70000 0x100>;
                interrupts = <0 57 0>;
@@ -108,7 +144,7 @@
                #size-cells = <0>;
        };
-        i2c@12C80000 {
+        i2c_2: i2c@12C80000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12C80000 0x100>;
                interrupts = <0 58 0>;
@@ -116,7 +152,7 @@
                #size-cells = <0>;
        };
-        i2c@12C90000 {
+        i2c_3: i2c@12C90000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12C90000 0x100>;
                interrupts = <0 59 0>;
@@ -124,7 +160,7 @@
                #size-cells = <0>;
        };
-        i2c@12CA0000 {
+        i2c_4: i2c@12CA0000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12CA0000 0x100>;
                interrupts = <0 60 0>;
@@ -132,7 +168,7 @@
                #size-cells = <0>;
        };
-        i2c@12CB0000 {
+        i2c_5: i2c@12CB0000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12CB0000 0x100>;
                interrupts = <0 61 0>;
@@ -140,7 +176,7 @@
                #size-cells = <0>;
        };
-        i2c@12CC0000 {
+        i2c_6: i2c@12CC0000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12CC0000 0x100>;
                interrupts = <0 62 0>;
@@ -148,7 +184,7 @@
                #size-cells = <0>;
        };
-        i2c@12CD0000 {
+        i2c_7: i2c@12CD0000 {
                compatible = "samsung,s3c2440-i2c";
                reg = <0x12CD0000 0x100>;
                interrupts = <0 63 0>;
@@ -156,6 +192,21 @@
                #size-cells = <0>;
        };
+        i2c_8: i2c@12CE0000 {
+                compatible = "samsung,s3c2440-hdmiphy-i2c";
+                reg = <0x12CE0000 0x1000>;
+                interrupts = <0 64 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        i2c@121D0000 {
+                compatible = "samsung,exynos5-sata-phy-i2c";
+                reg = <0x121D0000 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
        spi_0: spi@12d20000 {
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d20000 0x100>;
@@ -186,7 +237,7 @@
                #size-cells = <0>;
        };
-        dwmmc0@12200000 {
+        dwmmc_0: dwmmc0@12200000 {
                compatible = "samsung,exynos5250-dw-mshc";
                reg = <0x12200000 0x1000>;
                interrupts = <0 75 0>;
@@ -194,7 +245,7 @@
                #size-cells = <0>;
        };
-        dwmmc1@12210000 {
+        dwmmc_1: dwmmc1@12210000 {
                compatible = "samsung,exynos5250-dw-mshc";
                reg = <0x12210000 0x1000>;
                interrupts = <0 76 0>;
@@ -202,7 +253,7 @@
                #size-cells = <0>;
        };
-        dwmmc2@12220000 {
+        dwmmc_2: dwmmc2@12220000 {
                compatible = "samsung,exynos5250-dw-mshc";
                reg = <0x12220000 0x1000>;
                interrupts = <0 77 0>;
@@ -210,7 +261,7 @@
                #size-cells = <0>;
        };
-        dwmmc3@12230000 {
+        dwmmc_3: dwmmc3@12230000 {
                compatible = "samsung,exynos5250-dw-mshc";
                reg = <0x12230000 0x1000>;
                interrupts = <0 78 0>;
@@ -520,4 +571,16 @@
                reg = <0x13e30000 0x1000>;
                interrupts = <0 88 0>;
        };
+        hdmi {
+                compatible = "samsung,exynos5-hdmi";
+                reg = <0x14530000 0x100000>;
+                interrupts = <0 95 0>;
+        };
+        mixer {
+                compatible = "samsung,exynos5-mixer";
+                reg = <0x14450000 0x10000>;
+                interrupts = <0 94 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
new file mode 100644
index 000000000000..921c83cf694f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -0,0 +1,46 @@
+/*
+ * SAMSUNG SSDK5440 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+/include/ "exynos5440.dtsi"
+/ {
+        model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
+        compatible = "samsung,ssdk5440", "samsung,exynos5440";
+        memory {
+                reg = <0x80000000 0x80000000>;
+        };
+        chosen {
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc";
+        };
+        spi {
+                status = "disabled";
+        };
+        i2c@F0000 {
+                status = "disabled";
+        };
+        i2c@100000 {
+                status = "disabled";
+        };
+        watchdog {
+                status = "disabled";
+        };
+        rtc {
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
new file mode 100644
index 000000000000..024269de8ee5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -0,0 +1,159 @@
+/*
+ * SAMSUNG EXYNOS5440 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "samsung,exynos5440";
+        interrupt-parent = <&gic>;
+        gic:interrupt-controller@2E0000 {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 13 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 14 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 14 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                interrupts = <1 14 0xf08>;
+                                clock-frequency = <1000000>;
+                        };
+                };
+        };
+        common {
+                compatible = "samsung,exynos5440";
+        };
+        serial@B0000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0xB0000 0x1000>;
+                interrupts = <0 2 0>;
+        };
+        serial@C0000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0xC0000 0x1000>;
+                interrupts = <0 3 0>;
+        };
+        spi {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0xD0000 0x1000>;
+                interrupts = <0 4 0>;
+                tx-dma-channel = <&pdma0 5>; /* preliminary */
+                rx-dma-channel = <&pdma0 4>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        pinctrl {
+                compatible = "samsung,pinctrl-exynos5440";
+                reg = <0xE0000 0x1000>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                #gpio-cells = <2>;
+                fan: fan {
+                        samsung,exynos5440-pin-function = <1>;
+                };
+                hdd_led0: hdd_led0 {
+                        samsung,exynos5440-pin-function = <2>;
+                };
+                hdd_led1: hdd_led1 {
+                        samsung,exynos5440-pin-function = <3>;
+                };
+                uart1: uart1 {
+                        samsung,exynos5440-pin-function = <4>;
+                };
+        };
+        i2c@F0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0xF0000 0x1000>;
+                interrupts = <0 5 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        i2c@100000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x100000 0x1000>;
+                interrupts = <0 6 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        watchdog {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x110000 0x1000>;
+                interrupts = <0 1 0>;
+        };
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+                pdma0: pdma@121A0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x120000 0x1000>;
+                        interrupts = <0 34 0>;
+                };
+                pdma1: pdma@121B0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121000 0x1000>;
+                        interrupts = <0 35 0>;
+                };
+        };
+        rtc {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x130000 0x1000>;
+                interrupts = <0 16 0>, <0 17 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 0c6fc34821f9..a9ae5d32e80d 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -69,16 +69,8 @@
                reg = <0x00000000 0xff900000>;
        };
-        chosen {
-                bootargs = "console=ttyAMA0";
-        };
        soc {
-                #address-cells = <1>;
+                ranges = <0x00000000 0x00000000 0xffffffff>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
-                ranges;
                timer@fff10600 {
                        compatible = "arm,cortex-a9-twd-timer";
@@ -117,173 +109,6 @@
                        interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
                };
-                sata@ffe08000 {
-                        compatible = "calxeda,hb-ahci";
-                        reg = <0xffe08000 0x10000>;
-                        interrupts = <0 83 4>;
-                        calxeda,port-phys = <&combophy5 0 &combophy0 0
-                                             &combophy0 1 &combophy0 2
-                                             &combophy0 3>;
-                        dma-coherent;
-                };
-                sdhci@ffe0e000 {
-                        compatible = "calxeda,hb-sdhci";
-                        reg = <0xffe0e000 0x1000>;
-                        interrupts = <0 90 4>;
-                        clocks = <&eclk>;
-                };
-                memory-controller@fff00000 {
-                        compatible = "calxeda,hb-ddr-ctrl";
-                        reg = <0xfff00000 0x1000>;
-                        interrupts = <0 91 4>;
-                };
-                ipc@fff20000 {
-                        compatible = "arm,pl320", "arm,primecell";
-                        reg = <0xfff20000 0x1000>;
-                        interrupts = <0 7 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                gpioe: gpio@fff30000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff30000 0x1000>;
-                        interrupts = <0 14 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                gpiof: gpio@fff31000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff31000 0x1000>;
-                        interrupts = <0 15 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                gpiog: gpio@fff32000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff32000 0x1000>;
-                        interrupts = <0 16 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                gpioh: gpio@fff33000 {
-                        #gpio-cells = <2>;
-                        compatible = "arm,pl061", "arm,primecell";
-                        gpio-controller;
-                        reg = <0xfff33000 0x1000>;
-                        interrupts = <0 17 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                timer {
-                        compatible = "arm,sp804", "arm,primecell";
-                        reg = <0xfff34000 0x1000>;
-                        interrupts = <0 18 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                rtc@fff35000 {
-                        compatible = "arm,pl031", "arm,primecell";
-                        reg = <0xfff35000 0x1000>;
-                        interrupts = <0 19 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                serial@fff36000 {
-                        compatible = "arm,pl011", "arm,primecell";
-                        reg = <0xfff36000 0x1000>;
-                        interrupts = <0 20 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                smic@fff3a000 {
-                        compatible = "ipmi-smic";
-                        device_type = "ipmi";
-                        reg = <0xfff3a000 0x1000>;
-                        interrupts = <0 24 4>;
-                        reg-size = <4>;
-                        reg-spacing = <4>;
-                };
-                sregs@fff3c000 {
-                        compatible = "calxeda,hb-sregs";
-                        reg = <0xfff3c000 0x1000>;
-                        clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                osc: oscillator {
-                                        #clock-cells = <0>;
-                                        compatible = "fixed-clock";
-                                        clock-frequency = <33333000>;
-                                };
-                                ddrpll: ddrpll {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-pll-clock";
-                                        clocks = <&osc>;
-                                        reg = <0x108>;
-                                };
-                                a9pll: a9pll {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-pll-clock";
-                                        clocks = <&osc>;
-                                        reg = <0x100>;
-                                };
-                                a9periphclk: a9periphclk {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-a9periph-clock";
-                                        clocks = <&a9pll>;
-                                        reg = <0x104>;
-                                };
-                                a9bclk: a9bclk {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-a9bus-clock";
-                                        clocks = <&a9pll>;
-                                        reg = <0x104>;
-                                };
-                                emmcpll: emmcpll {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-pll-clock";
-                                        clocks = <&osc>;
-                                        reg = <0x10C>;
-                                };
-                                eclk: eclk {
-                                        #clock-cells = <0>;
-                                        compatible = "calxeda,hb-emmc-clock";
-                                        clocks = <&emmcpll>;
-                                        reg = <0x114>;
-                                };
-                                pclk: pclk {
-                                        #clock-cells = <0>;
-                                        compatible = "fixed-clock";
-                                        clock-frequency = <150000000>;
-                                };
-                        };
-                };
                sregs@fff3c200 {
                        compatible = "calxeda,hb-sregs-l2-ecc";
@@ -291,38 +116,7 @@
                        interrupts = <0 71 4  0 72 4>;
                };
-                dma@fff3d000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0xfff3d000 0x1000>;
-                        interrupts = <0 92 4>;
-                        clocks = <&pclk>;
-                        clock-names = "apb_pclk";
-                };
-                ethernet@fff50000 {
-                        compatible = "calxeda,hb-xgmac";
-                        reg = <0xfff50000 0x1000>;
-                        interrupts = <0 77 4  0 78 4  0 79 4>;
-                };
-                ethernet@fff51000 {
-                        compatible = "calxeda,hb-xgmac";
-                        reg = <0xfff51000 0x1000>;
-                        interrupts = <0 80 4  0 81 4  0 82 4>;
-                };
-                combophy0: combo-phy@fff58000 {
-                        compatible = "calxeda,hb-combophy";
-                        #phy-cells = <1>;
-                        reg = <0xfff58000 0x1000>;
-                        phydev = <5>;
-                };
-                combophy5: combo-phy@fff5d000 {
-                        compatible = "calxeda,hb-combophy";
-                        #phy-cells = <1>;
-                        reg = <0xfff5d000 0x1000>;
-                        phydev = <31>;
-                };
        };
 };
+/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
new file mode 100644
index 000000000000..592fb9dc35bd
--- /dev/null
+++ b/arch/arm/boot/dts/href.dtsi
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "dbx5x0.dtsi"
+/ {
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        linux,code = <11>;
+                        label = "SFH7741 Proximity Sensor";
+                };
+        };
+        soc-u9500 {
+                uart@80120000 {
+                        status = "okay";
+                };
+                uart@80121000 {
+                        status = "okay";
+                };
+                uart@80007000 {
+                        status = "okay";
+                };
+                i2c@80004000 {
+                        tc3589x@42 {
+                                compatible = "tc3589x";
+                                reg = <0x42>;
+                                interrupt-parent = <&gpio6>;
+                                interrupts = <25 0x1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                tc3589x_gpio: tc3589x_gpio {
+                                        compatible = "tc3589x-gpio";
+                                        interrupts = <0 0x1>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                        };
+                };
+                i2c@80128000 {
+                        lp5521@0x33 {
+                                compatible = "lp5521";
+                                reg = <0x33>;
+                        };
+                        lp5521@0x34 {
+                                compatible = "lp5521";
+                                reg = <0x34>;
+                        };
+                        bh1780@0x29 {
+                                compatible = "rohm,bh1780gli";
+                                reg = <0x33>;
+                        };
+                };
+                // External Micro SD slot
+                sdi0_per1@80126000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
+                        mmc-cap-sd-highspeed;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        cd-gpios  = <&tc3589x_gpio 3 0x4>;
+                        status = "okay";
+                };
+                // WLAN SDIO channel
+                sdi1_per2@80118000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
+                        status = "okay";
+                };
+                // PoP:ed eMMC
+                sdi2_per3@80005000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
+                        status = "okay";
+                };
+                // On-board eMMC
+                sdi4_per2@80114000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                        status = "okay";
+                };
+                sound {
+                        compatible = "stericsson,snd-soc-mop500";
+                        stericsson,cpu-dai = <&msp1 &msp3>;
+                        stericsson,audio-codec = <&codec>;
+                };
+                msp1: msp@80124000 {
+                        status = "okay";
+                };
+                msp3: msp@80125000 {
+                        status = "okay";
+                };
+                prcmu@80157000 {
+                        db8500-prcmu-regulators {
+                                db8500_vape_reg: db8500_vape {
+                                        regulator-name = "db8500-vape";
+                                };
+                                db8500_varm_reg: db8500_varm {
+                                        regulator-name = "db8500-varm";
+                                };
+                                db8500_vmodem_reg: db8500_vmodem {
+                                        regulator-name = "db8500-vmodem";
+                                };
+                                db8500_vpll_reg: db8500_vpll {
+                                        regulator-name = "db8500-vpll";
+                                };
+                                db8500_vsmps1_reg: db8500_vsmps1 {
+                                        regulator-name = "db8500-vsmps1";
+                                };
+                                db8500_vsmps2_reg: db8500_vsmps2 {
+                                        regulator-name = "db8500-vsmps2";
+                                };
+                                db8500_vsmps3_reg: db8500_vsmps3 {
+                                        regulator-name = "db8500-vsmps3";
+                                };
+                                db8500_vrf1_reg: db8500_vrf1 {
+                                        regulator-name = "db8500-vrf1";
+                                };
+                                db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
+                                        regulator-name = "db8500-sva-mmdsp";
+                                };
+                                db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
+                                        regulator-name = "db8500-sva-mmdsp-ret";
+                                };
+                                db8500_sva_pipe_reg: db8500_sva_pipe {
+                                        regulator-name = "db8500_sva_pipe";
+                                };
+                                db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
+                                        regulator-name = "db8500_sia_mmdsp";
+                                };
+                                db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
+                                        regulator-name = "db8500-sia-mmdsp-ret";
+                                };
+                                db8500_sia_pipe_reg: db8500_sia_pipe {
+                                        regulator-name = "db8500-sia-pipe";
+                                };
+                                db8500_sga_reg: db8500_sga {
+                                        regulator-name = "db8500-sga";
+                                };
+                                db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
+                                        regulator-name = "db8500-b2r2-mcde";
+                                };
+                                db8500_esram12_reg: db8500_esram12 {
+                                        regulator-name = "db8500-esram12";
+                                };
+                                db8500_esram12_ret_reg: db8500_esram12_ret {
+                                        regulator-name = "db8500-esram12-ret";
+                                };
+                                db8500_esram34_reg: db8500_esram34 {
+                                        regulator-name = "db8500-esram34";
+                                };
+                                db8500_esram34_ret_reg: db8500_esram34_ret {
+                                        regulator-name = "db8500-esram34-ret";
+                                };
+                        };
+                        ab8500@5 {
+                                ab8500-regulators {
+                                        ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+                                                regulator-name = "V-DISPLAY";
+                                        };
+                                        ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+                                                regulator-name = "V-eMMC1";
+                                        };
+                                        ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+                                                regulator-name = "V-MMC-SD";
+                                        };
+                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                                regulator-name = "V-INTCORE";
+                                        };
+                                        ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+                                                regulator-name = "V-TVOUT";
+                                        };
+                                        ab8500_ldo_usb_reg: ab8500_ldo_usb {
+                                                regulator-name = "dummy";
+                                        };
+                                        ab8500_ldo_audio_reg: ab8500_ldo_audio {
+                                                regulator-name = "V-AUD";
+                                        };
+                                        ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+                                                regulator-name = "V-AMIC1";
+                                        };
+                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                                regulator-name = "V-AMIC2";
+                                        };
+                                        ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+                                                regulator-name = "V-DMIC";
+                                        };
+                                        ab8500_ldo_ana_reg: ab8500_ldo_ana {
+                                                regulator-name = "V-CSI/DSI";
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
new file mode 100644
index 000000000000..eec29c4a86dc
--- /dev/null
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "dbx5x0.dtsi"
+/include/ "href.dtsi"
+/include/ "stuib.dtsi"
+/ {
+        model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
+        compatible = "st-ericsson,mop500", "st-ericsson,u8500";
+        gpio_keys {
+                button@1 {
+                        gpios = <&tc3589x_gpio 7 0x4>;
+                };
+        };
+        soc-u9500 {
+                i2c@80004000 {
+                        tps61052@33 {
+                                compatible = "tps61052";
+                                reg = <0x33>;
+                        };
+                };
+                i2c@80110000 {
+                        bu21013_tp@0x5c {
+                                reset-gpio = <&tc3589x_gpio 13 0x4>;
+                        };
+                };
+                vmmci: regulator-gpio {
+                        gpios = <&tc3589x_gpio 18 0x4>;
+                        gpio-enable = <&tc3589x_gpio 17 0x4>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 2131d77dc9c9..55f4191a626e 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -11,85 +11,200 @@
 /dts-v1/;
 /include/ "dbx5x0.dtsi"
+/include/ "href.dtsi"
+/include/ "stuib.dtsi"
 / {
-        model = "ST-Ericsson HREF platform with Device Tree";
+        model = "ST-Ericsson HREF (v60+) platform with Device Tree";
-        compatible = "st-ericsson,hrefv60+";
+        compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
-        memory {
+        gpio_keys {
-                reg = <0x00000000 0x20000000>;
+                button@1 {
+                        gpios = <&gpio6 25 0x4>;
+                };
        };
        soc-u9500 {
-                uart@80120000 {
+                i2c@80110000 {
+                        bu21013_tp@0x5c {
+                                reset-gpio = <&gpio4 15 0x4>;
+                        };
+                };
+                // External Micro SD slot
+                sdi0_per1@80126000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
+                        mmc-cap-sd-highspeed;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        cd-gpios  = <&tc3589x_gpio 3 0x4>;
                        status = "okay";
                };
-                uart@80121000 {
+                // WLAN SDIO channel
+                sdi1_per2@80118000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
                        status = "okay";
                };
-                uart@80007000 {
+                // PoP:ed eMMC
+                sdi2_per3@80005000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
                        status = "okay";
                };
-                i2c@80004000 {
+                // On-board eMMC
-                        tc3589x@42 {
+                sdi4_per2@80114000 {
-                                compatible = "tc3589x";
+                        arm,primecell-periphid = <0x10480180>;
-                                reg = <0x42>;
+                        max-frequency = <50000000>;
-                                interrupt-parent = <&gpio6>;
+                        bus-width = <8>;
-                                interrupts = <25 0x1>;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
-                                interrupt-controller;
+                        status = "okay";
-                                #interrupt-cells = <2>;
+                };
-                                tc3589x_gpio: tc3589x_gpio {
+                prcmu@80157000 {
-                                        compatible = "tc3589x-gpio";
+                        db8500-prcmu-regulators {
-                                        interrupts = <0 0x1>;
+                                db8500_vape_reg: db8500_vape {
+                                        regulator-name = "db8500-vape";
+                                };
-                                        interrupt-controller;
+                                db8500_varm_reg: db8500_varm {
-                                        #interrupt-cells = <2>;
+                                        regulator-name = "db8500-varm";
-                                        gpio-controller;
-                                        #gpio-cells = <2>;
                                };
-                        };
-                        tps61052@33 {
+                                db8500_vmodem_reg: db8500_vmodem {
-                                compatible = "tps61052";
+                                        regulator-name = "db8500-vmodem";
-                                reg = <0x33>;
+                                };
-                        };
-                };
-                i2c@80128000 {
+                                db8500_vpll_reg: db8500_vpll {
-                        lp5521@0x33 {
+                                        regulator-name = "db8500-vpll";
-                                compatible = "lp5521";
+                                };
-                                reg = <0x33>;
-                        };
-                        lp5521@0x34 {
+                                db8500_vsmps1_reg: db8500_vsmps1 {
-                                compatible = "lp5521";
+                                        regulator-name = "db8500-vsmps1";
-                                reg = <0x34>;
+                                };
-                        };
+                                db8500_vsmps2_reg: db8500_vsmps2 {
+                                        regulator-name = "db8500-vsmps2";
+                                };
+                                db8500_vsmps3_reg: db8500_vsmps3 {
+                                        regulator-name = "db8500-vsmps3";
+                                };
+                                db8500_vrf1_reg: db8500_vrf1 {
+                                        regulator-name = "db8500-vrf1";
+                                };
+                                db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
+                                        regulator-name = "db8500-sva-mmdsp";
+                                };
+                                db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
+                                        regulator-name = "db8500-sva-mmdsp-ret";
+                                };
+                                db8500_sva_pipe_reg: db8500_sva_pipe {
+                                        regulator-name = "db8500_sva_pipe";
+                                };
-                        bh1780@0x29 {
+                                db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
-                                compatible = "rohm,bh1780gli";
+                                        regulator-name = "db8500_sia_mmdsp";
-                                reg = <0x33>;
+                                };
+                                db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
+                                        regulator-name = "db8500-sia-mmdsp-ret";
+                                };
+                                db8500_sia_pipe_reg: db8500_sia_pipe {
+                                        regulator-name = "db8500-sia-pipe";
+                                };
+                                db8500_sga_reg: db8500_sga {
+                                        regulator-name = "db8500-sga";
+                                };
+                                db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
+                                        regulator-name = "db8500-b2r2-mcde";
+                                };
+                                db8500_esram12_reg: db8500_esram12 {
+                                        regulator-name = "db8500-esram12";
+                                };
+                                db8500_esram12_ret_reg: db8500_esram12_ret {
+                                        regulator-name = "db8500-esram12-ret";
+                                };
+                                db8500_esram34_reg: db8500_esram34 {
+                                        regulator-name = "db8500-esram34";
+                                };
+                                db8500_esram34_ret_reg: db8500_esram34_ret {
+                                        regulator-name = "db8500-esram34-ret";
+                                };
                        };
-                };
-                sound {
+                        ab8500@5 {
-                        compatible = "stericsson,snd-soc-mop500";
+                                ab8500-regulators {
+                                        ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+                                                regulator-name = "V-DISPLAY";
+                                        };
-                        stericsson,cpu-dai = <&msp1 &msp3>;
+                                        ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
-                        stericsson,audio-codec = <&codec>;
+                                                regulator-name = "V-eMMC1";
-                };
+                                        };
-                msp1: msp@80124000 {
+                                        ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
-                        status = "okay";
+                                                regulator-name = "V-MMC-SD";
-                };
+                                        };
-                msp3: msp@80125000 {
+                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
-                        status = "okay";
+                                                regulator-name = "V-INTCORE";
+                                        };
+                                        ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+                                                regulator-name = "V-TVOUT";
+                                        };
+                                        ab8500_ldo_usb_reg: ab8500_ldo_usb {
+                                                regulator-name = "dummy";
+                                        };
+                                        ab8500_ldo_audio_reg: ab8500_ldo_audio {
+                                                regulator-name = "V-AUD";
+                                        };
+                                        ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+                                                regulator-name = "V-AMIC1";
+                                        };
+                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                                regulator-name = "V-AMIC2";
+                                        };
+                                        ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+                                                regulator-name = "V-DMIC";
+                                        };
+                                        ab8500_ldo_ana_reg: ab8500_ldo_ana {
+                                                regulator-name = "V-CSI/DSI";
+                                        };
+                                };
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 384d8b66f337..7c43b8e70b9f 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -40,6 +40,15 @@
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                led_pin_gpio0_17: led_gpio0_17@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
                                                0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
                                        >;
                                        fsl,drive-strength = <0>;
@@ -47,6 +56,15 @@
                                        fsl,pull-up = <0>;
                                };
                        };
+                        ssp1: ssp@80034000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx23-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+                        };
                };
                apbx@80040000 {
@@ -91,11 +109,12 @@
        leds {
                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio0_17>;
                user {
                        label = "green";
-                        gpios = <&gpio2 1 0>;
+                        gpios = <&gpio2 1 1>;
-                        linux,default-trigger = "default-on";
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 6d31aa383460..65415c598a5e 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -279,6 +279,19 @@
                                        fsl,voltage = <1>;
                                        fsl,pull-up = <0>;
                                };
+                                spi2_pins_a: spi2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
+                                                0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
+                                                0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
+                                                0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
                        };
                        digctl@8001c000 {
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
new file mode 100644
index 000000000000..d81f8a0b9794
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx25.dtsi"
+/ {
+        model = "Ka-Ro TX25";
+        compatible = "karo,imx25-tx25", "fsl,imx25";
+        memory {
+                reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
+        };
+        soc {
+                aips@43f00000 {
+                        uart1: serial@43f90000 {
+                                status = "okay";
+                        };
+                };
+                spba@50000000 {
+                        fec: ethernet@50038000 {
+                                status = "okay";
+                                phy-mode = "rmii";
+                        };
+                };
+                emi@80000000 {
+                        nand@bb000000 {
+                                nand-on-flash-bbt;
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
new file mode 100644
index 000000000000..e1b13ebc96d6
--- /dev/null
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -0,0 +1,515 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                usb0 = &usbotg;
+                usb1 = &usbhost1;
+        };
+        asic: asic-interrupt-controller@68000000 {
+                compatible = "fsl,imx25-asic", "fsl,avic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x68000000 0x8000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                osc {
+                        compatible = "fsl,imx-osc", "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&asic>;
+                ranges;
+                aips@43f00000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x43f00000 0x100000>;
+                        ranges;
+                        i2c1: i2c@43f80000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+                                reg = <0x43f80000 0x4000>;
+                                clocks = <&clks 48>;
+                                clock-names = "";
+                                interrupts = <3>;
+                                status = "disabled";
+                        };
+                        i2c3: i2c@43f84000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+                                reg = <0x43f84000 0x4000>;
+                                clocks = <&clks 48>;
+                                clock-names = "";
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
+                        can1: can@43f88000 {
+                                compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x43f88000 0x4000>;
+                                interrupts = <43>;
+                                clocks = <&clks 75>, <&clks 75>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        can2: can@43f8c000 {
+                                compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x43f8c000 0x4000>;
+                                interrupts = <44>;
+                                clocks = <&clks 76>, <&clks 76>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart1: serial@43f90000 {
+                                compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+                                reg = <0x43f90000 0x4000>;
+                                interrupts = <45>;
+                                clocks = <&clks 120>, <&clks 57>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart2: serial@43f94000 {
+                                compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+                                reg = <0x43f94000 0x4000>;
+                                interrupts = <32>;
+                                clocks = <&clks 121>, <&clks 57>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        i2c2: i2c@43f98000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+                                reg = <0x43f98000 0x4000>;
+                                clocks = <&clks 48>;
+                                clock-names = "";
+                                interrupts = <4>;
+                                status = "disabled";
+                        };
+                        owire@43f9c000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x43f9c000 0x4000>;
+                                clocks = <&clks 51>;
+                                clock-names = "";
+                                interrupts = <2>;
+                                status = "disabled";
+                        };
+                        spi1: cspi@43fa4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+                                reg = <0x43fa4000 0x4000>;
+                                clocks = <&clks 62>;
+                                clock-names = "ipg";
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+                        kpp@43fa8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x43fa8000 0x4000>;
+                                clocks = <&clks 102>;
+                                clock-names = "";
+                                interrupts = <24>;
+                                status = "disabled";
+                        };
+                        iomuxc@43fac000{
+                                compatible = "fsl,imx25-iomuxc";
+                                reg = <0x43fac000 0x4000>;
+                        };
+                        audmux@43fb0000 {
+                                compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
+                                reg = <0x43fb0000 0x4000>;
+                                status = "disabled";
+                        };
+                };
+                spba@50000000 {
+                        compatible = "fsl,spba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x50000000 0x40000>;
+                        ranges;
+                        spi3: cspi@50004000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+                                reg = <0x50004000 0x4000>;
+                                interrupts = <0>;
+                                clocks = <&clks 80>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        uart4: serial@50008000 {
+                                compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+                                reg = <0x50008000 0x4000>;
+                                interrupts = <5>;
+                                clocks = <&clks 123>, <&clks 57>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart3: serial@5000c000 {
+                                compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+                                reg = <0x5000c000 0x4000>;
+                                interrupts = <18>;
+                                clocks = <&clks 122>, <&clks 57>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        spi2: cspi@50010000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+                                reg = <0x50010000 0x4000>;
+                                clocks = <&clks 79>;
+                                clock-names = "ipg";
+                                interrupts = <13>;
+                                status = "disabled";
+                        };
+                        ssi2: ssi@50014000 {
+                                compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
+                                reg = <0x50014000 0x4000>;
+                                interrupts = <11>;
+                                status = "disabled";
+                        };
+                        esai@50018000 {
+                                reg = <0x50018000 0x4000>;
+                                interrupts = <7>;
+                        };
+                        uart5: serial@5002c000 {
+                                compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+                                reg = <0x5002c000 0x4000>;
+                                interrupts = <40>;
+                                clocks = <&clks 124>, <&clks 57>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        tsc: tsc@50030000 {
+                                compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
+                                reg = <0x50030000 0x4000>;
+                                interrupts = <46>;
+                                clocks = <&clks 119>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        ssi1: ssi@50034000 {
+                                compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
+                                reg = <0x50034000 0x4000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+                        fec: ethernet@50038000 {
+                                compatible = "fsl,imx25-fec";
+                                reg = <0x50038000 0x4000>;
+                                interrupts = <57>;
+                                clocks = <&clks 88>, <&clks 65>;
+                                clock-names = "ipg", "ahb";
+                                status = "disabled";
+                        };
+                };
+                aips@53f00000 { /* AIPS2 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x53f00000 0x100000>;
+                        ranges;
+                        clks: ccm@53f80000 {
+                                compatible = "fsl,imx25-ccm";
+                                reg = <0x53f80000 0x4000>;
+                                interrupts = <31>;
+                                #clock-cells = <1>;
+                        };
+                        gpt4: timer@53f84000 {
+                                compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+                                reg = <0x53f84000 0x4000>;
+                                clocks = <&clks 9>, <&clks 45>;
+                                clock-names = "ipg", "per";
+                                interrupts = <1>;
+                        };
+                        gpt3: timer@53f88000 {
+                                compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+                                reg = <0x53f88000 0x4000>;
+                                clocks = <&clks 9>, <&clks 47>;
+                                clock-names = "ipg", "per";
+                                interrupts = <29>;
+                        };
+                        gpt2: timer@53f8c000 {
+                                compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+                                reg = <0x53f8c000 0x4000>;
+                                clocks = <&clks 9>, <&clks 47>;
+                                clock-names = "ipg", "per";
+                                interrupts = <53>;
+                        };
+                        gpt1: timer@53f90000 {
+                                compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+                                reg = <0x53f90000 0x4000>;
+                                clocks = <&clks 9>, <&clks 47>;
+                                clock-names = "ipg", "per";
+                                interrupts = <54>;
+                        };
+                        epit1: timer@53f94000 {
+                                compatible = "fsl,imx25-epit";
+                                reg = <0x53f94000 0x4000>;
+                                interrupts = <28>;
+                        };
+                        epit2: timer@53f98000 {
+                                compatible = "fsl,imx25-epit";
+                                reg = <0x53f98000 0x4000>;
+                                interrupts = <27>;
+                        };
+                        gpio4: gpio@53f9c000 {
+                                compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+                                reg = <0x53f9c000 0x4000>;
+                                interrupts = <23>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        pwm2: pwm@53fa0000 {
+                                compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+                                #pwm-cells = <2>;
+                                reg = <0x53fa0000 0x4000>;
+                                clocks = <&clks 106>, <&clks 36>;
+                                clock-names = "ipg", "per";
+                                interrupts = <36>;
+                        };
+                        gpio3: gpio@53fa4000 {
+                                compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+                                reg = <0x53fa4000 0x4000>;
+                                interrupts = <16>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        pwm3: pwm@53fa8000 {
+                                compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+                                #pwm-cells = <2>;
+                                reg = <0x53fa8000 0x4000>;
+                                clocks = <&clks 107>, <&clks 36>;
+                                clock-names = "ipg", "per";
+                                interrupts = <41>;
+                        };
+                        esdhc1: esdhc@53fb4000 {
+                                compatible = "fsl,imx25-esdhc";
+                                reg = <0x53fb4000 0x4000>;
+                                interrupts = <9>;
+                                clocks = <&clks 86>, <&clks 63>, <&clks 45>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        esdhc2: esdhc@53fb8000 {
+                                compatible = "fsl,imx25-esdhc";
+                                reg = <0x53fb8000 0x4000>;
+                                interrupts = <8>;
+                                clocks = <&clks 87>, <&clks 64>, <&clks 46>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        lcdc@53fbc000 {
+                                reg = <0x53fbc000 0x4000>;
+                                interrupts = <39>;
+                                clocks = <&clks 103>, <&clks 66>, <&clks 49>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        slcdc@53fc0000 {
+                                reg = <0x53fc0000 0x4000>;
+                                interrupts = <38>;
+                                status = "disabled";
+                        };
+                        pwm4: pwm@53fc8000 {
+                                compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+                                reg = <0x53fc8000 0x4000>;
+                                clocks = <&clks 108>, <&clks 36>;
+                                clock-names = "ipg", "per";
+                                interrupts = <42>;
+                        };
+                        gpio1: gpio@53fcc000 {
+                                compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+                                reg = <0x53fcc000 0x4000>;
+                                interrupts = <52>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio2: gpio@53fd0000 {
+                                compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+                                reg = <0x53fd0000 0x4000>;
+                                interrupts = <51>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        sdma@53fd4000 {
+                                compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
+                                reg = <0x53fd4000 0x4000>;
+                                clocks = <&clks 112>, <&clks 68>;
+                                clock-names = "ipg", "ahb";
+                                interrupts = <34>;
+                        };
+                        wdog@53fdc000 {
+                                compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
+                                reg = <0x53fdc000 0x4000>;
+                                clocks = <&clks 126>;
+                                clock-names = "";
+                                interrupts = <55>;
+                        };
+                        pwm1: pwm@53fe0000 {
+                                compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+                                #pwm-cells = <2>;
+                                reg = <0x53fe0000 0x4000>;
+                                clocks = <&clks 105>, <&clks 36>;
+                                clock-names = "ipg", "per";
+                                interrupts = <26>;
+                        };
+                        usbphy1: usbphy@1 {
+                                compatible = "nop-usbphy";
+                                status = "disabled";
+                        };
+                        usbphy2: usbphy@2 {
+                                compatible = "nop-usbphy";
+                                status = "disabled";
+                        };
+                        usbotg: usb@53ff4000 {
+                                compatible = "fsl,imx25-usb", "fsl,imx27-usb";
+                                reg = <0x53ff4000 0x0200>;
+                                interrupts = <37>;
+                                clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+                                clock-names = "ipg", "ahb", "per";
+                                fsl,usbmisc = <&usbmisc 0>;
+                                status = "disabled";
+                        };
+                        usbhost1: usb@53ff4400 {
+                                compatible = "fsl,imx25-usb", "fsl,imx27-usb";
+                                reg = <0x53ff4400 0x0200>;
+                                interrupts = <35>;
+                                clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+                                clock-names = "ipg", "ahb", "per";
+                                fsl,usbmisc = <&usbmisc 1>;
+                                status = "disabled";
+                        };
+                        usbmisc: usbmisc@53ff4600 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx25-usbmisc";
+                                clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+                                clock-names = "ipg", "ahb", "per";
+                                reg = <0x53ff4600 0x00f>;
+                                status = "disabled";
+                        };
+                        dryice@53ffc000 {
+                                compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
+                                reg = <0x53ffc000 0x4000>;
+                                clocks = <&clks 81>;
+                                clock-names = "ipg";
+                                interrupts = <25>;
+                        };
+                };
+                emi@80000000 {
+                        compatible = "fsl,emi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80000000 0x3b002000>;
+                        ranges;
+                        nand@bb000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,imx25-nand";
+                                reg = <0xbb000000 0x2000>;
+                                clocks = <&clks 50>;
+                                clock-names = "";
+                                interrupts = <33>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
index 0a8978a40ece..b01c0d745fc5 100644
--- a/arch/arm/boot/dts/imx27-3ds.dts
+++ b/arch/arm/boot/dts/imx27-3ds.dts
@@ -23,10 +23,6 @@
        soc {
                aipi@10000000 { /* aipi */
-                        wdog@10002000 {
-                                status = "okay";
-                        };
                        uart1: serial@1000a000 {
                                fsl,uart-has-rtscts;
                                status = "okay";
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
new file mode 100644
index 000000000000..c0327c054de2
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
+ * Copyright 2012 Armadeus Systems <support@armadeus.com>
+ *
+ * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx27.dtsi"
+/ {
+        model = "Armadeus Systems APF27 module";
+        compatible = "armadeus,imx27-apf27", "fsl,imx27";
+        memory {
+                reg = <0xa0000000 0x04000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                osc26m {
+                        compatible = "fsl,imx-osc26m", "fixed-clock";
+                        clock-frequency = <0>;
+                };
+        };
+        soc {
+                aipi@10000000 {
+                        serial@1000a000 {
+                                status = "okay";
+                        };
+                        ethernet@1002b000 {
+                                status = "okay";
+                        };
+                };
+                nand@d8000000 {
+                        status = "okay";
+                        nand-bus-width = <16>;
+                        nand-ecc-mode = "hw";
+                        nand-on-flash-bbt;
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0 0x100000>;
+                        };
+                        partition@100000 {
+                                label = "env";
+                                reg = <0x100000 0x80000>;
+                        };
+                        partition@180000 {
+                                label = "env2";
+                                reg = <0x180000 0x80000>;
+                        };
+                        partition@200000 {
+                                label = "firmware";
+                                reg = <0x200000 0x80000>;
+                        };
+                        partition@280000 {
+                                label = "dtb";
+                                reg = <0x280000 0x80000>;
+                        };
+                        partition@300000 {
+                                label = "kernel";
+                                reg = <0x300000 0x500000>;
+                        };
+                        partition@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0xf800000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 3e54f1498841..b8d3905915ac 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -58,7 +58,7 @@
                        reg = <0x10000000 0x10000000>;
                        ranges;
-                        wdog@10002000 {
+                        wdog: wdog@10002000 {
                                compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                reg = <0x10002000 0x4000>;
                                interrupts = <27>;
@@ -113,7 +113,7 @@
                        i2c1: i2c@10012000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
                                reg = <0x10012000 0x1000>;
                                interrupts = <12>;
                                status = "disabled";
@@ -205,7 +205,7 @@
                        i2c2: i2c@1001d000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
                                reg = <0x1001d000 0x1000>;
                                interrupts = <1>;
                                status = "disabled";
@@ -218,7 +218,8 @@
                                status = "disabled";
                        };
                };
-                nand@d8000000 {
+                nfc: nand@d8000000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
new file mode 100644
index 000000000000..7eb075876c4c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2012 Armadeus Systems - <support@armadeus.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx28.dtsi"
+/ {
+        model = "Armadeus Systems APF28 module";
+        compatible = "armadeus,imx28-apf28", "fsl,imx28";
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+        apb@80000000 {
+                apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+                                status = "okay";
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0 0x300000>;
+                                };
+                                partition@300000 {
+                                        label = "env";
+                                        reg = <0x300000 0x80000>;
+                                };
+                                partition@380000 {
+                                        label = "env2";
+                                        reg = <0x380000 0x80000>;
+                                };
+                                partition@400000 {
+                                        label = "dtb";
+                                        reg = <0x400000 0x80000>;
+                                };
+                                partition@480000 {
+                                        label = "splash";
+                                        reg = <0x480000 0x80000>;
+                                };
+                                partition@500000 {
+                                        label = "kernel";
+                                        reg = <0x500000 0x800000>;
+                                };
+                                partition@d00000 {
+                                        label = "rootfs";
+                                        reg = <0xd00000 0xf300000>;
+                                };
+                        };
+                };
+                apbx@80040000 {
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio4 13 0>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
new file mode 100644
index 000000000000..6d8865bfb4b7
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2012 Armadeus Systems - <support@armadeus.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* APF28Dev is a docking board for the APF28 SOM */
+/include/ "imx28-apf28.dts"
+/ {
+        model = "Armadeus Systems APF28Dev docking/development board";
+        compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28";
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+                        };
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_apf28dev>;
+                                hog_pins_apf28dev: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */
+                                                0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */
+                                                0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */
+                                                0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */
+                                                0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */
+                                                0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */
+                                                0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                lcdif_pins_apf28dev: lcdif-apf28dev@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_16bit_pins_a
+                                                &lcdif_pins_apf28dev>;
+                                status = "okay";
+                        };
+                };
+                apbx@80040000 {
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+                        };
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>;
+                                status = "okay";
+                        };
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        status = "okay";
+                };
+                usb1: usb@80090000 {
+                        status = "okay";
+                };
+                mac1: ethernet@800f4000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac1_pins_a>;
+                        phy-reset-gpios = <&gpio0 23 0>;
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 23 1>;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio0 21 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 191000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index c03a577beca3..1594694532b9 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -22,6 +22,31 @@
        apb@80000000 {
                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_cfa10036>;
+                                hog_pins_cfa10036: hog-10036@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                led_pins_cfa10036: leds-10036@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
                        ssp0: ssp@80010000 {
                                compatible = "fsl,imx28-mmc";
                                pinctrl-names = "default";
@@ -33,16 +58,37 @@
                };
                apbx@80040000 {
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm4_pins_a>;
+                                status = "okay";
+                        };
                        duart: serial@80074000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&duart_pins_b>;
                                status = "okay";
                        };
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_b>;
+                                status = "okay";
+                                ssd1307: oled@3c {
+                                        compatible = "solomon,ssd1307fb-i2c";
+                                        reg = <0x3c>;
+                                        pwms = <&pwm 4 3000>;
+                                        reset-gpios = <&gpio2 7 0>;
+                                };
+                        };
                };
        };
        leds {
                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_cfa10036>;
                power {
                        gpios = <&gpio3 4 1>;
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 05c892e931e3..b222614ac9e0 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -22,6 +22,22 @@
        apb@80000000 {
                apbh@80000000 {
                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10049>;
+                                hog_pins_cfa10049: hog-10049@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+                                                0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
+                                                0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
+                                                0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                spi3_pins_cfa10049: spi3-cfa10049@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -29,6 +45,7 @@
                                                0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
                                                0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
                                                0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
+                                                0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
                                        >;
                                        fsl,drive-strength = <1>;
                                        fsl,voltage = <1>;
@@ -60,6 +77,11 @@
                                        spi-max-frequency = <100000>;
                                };
+                                dac0: dh2228@2 {
+                                        compatible = "rohm,dh2228fv";
+                                        reg = <2>;
+                                        spi-max-frequency = <100000>;
+                                };
                        };
                };
@@ -96,4 +118,15 @@
                        gpio = <&gpio0 7 1>;
                };
        };
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio2 21 0>;
+                        phy-reset-duration = <100>;
+                        status = "okay";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index a0ad71ca3a44..2da316e04409 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -76,7 +76,6 @@
                                                0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
-                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
                                                0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
                                                0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
                                        >;
@@ -85,6 +84,16 @@
                                        fsl,pull-up = <0>;
                                };
+                                led_pin_gpio3_5: led_gpio3_5@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                gpmi_pins_evk: gpmi-nand-evk@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -288,6 +297,8 @@
        leds {
                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio3_5>;
                user {
                        label = "Heartbeat";
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
new file mode 100644
index 000000000000..e6cde8aa7fff
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx28.dtsi"
+/ {
+        model = "SchulerControl GmbH, SC SPS 1";
+        compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */
+                                                0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */
+                                                0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+                                flash: m25p80@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "everspin,mr25h256", "mr25h256";
+                                        spi-max-frequency = <40000000>;
+                                        reg = <0>;
+                                };
+                        };
+                };
+                apbx@80040000 {
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                rtc: rtc@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+                                eeprom: eeprom@52 {
+                                        compatible = "atmel,24c64";
+                                        reg = <0x52>;
+                                        pagesize = <32>;
+                                };
+                        };
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usbphy0_pins_b>;
+                        status = "okay";
+                };
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        status = "okay";
+                };
+                mac1: ethernet@800f4000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac1_pins_a>;
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 9 0>;
+                };
+        };
+        leds {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "gpio-leds";
+                status = "okay";
+                led@1 {
+                        label = "sps1-1:yellow:user";
+                        gpios = <&gpio0 6 0>;
+                        linux,default-trigger = "heartbeat";
+                        reg = <0>;
+                };
+                led@2 {
+                        label = "sps1-2:red:user";
+                        gpios = <&gpio0 3 0>;
+                        linux,default-trigger = "heartbeat";
+                        reg = <1>;
+                };
+                led@3 {
+                        label = "sps1-3:red:user";
+                        gpios = <&gpio0 0 0>;
+                        default-trigger = "heartbeat";
+                        reg = <2>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 55c57ea6169e..13b7053d799e 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -492,6 +492,16 @@
                                        fsl,pull-up = <0>;
                                };
+                                pwm3_pins_a: pwm3@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x31c0 /* MX28_PAD_PWM3__PWM_3 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                pwm4_pins_a: pwm4@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -535,6 +545,31 @@
                                        fsl,pull-up = <0>;
                                };
+                                lcdif_16bit_pins_a: lcdif-16bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                can0_pins_a: can0@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -799,6 +834,7 @@
                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                reg = <0x8006a000 0x2000>;
                                interrupts = <112 70 71>;
+                                fsl,auart-dma-channel = <8 9>;
                                clocks = <&clks 45>;
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index cbd2b1c7487b..567e7ee72f91 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -22,6 +22,22 @@
        };
        soc {
+                display@di0 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 0>;
+                        interface-pix-fmt = "rgb24";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ipu_disp1_1>;
+                };
+                display@di1 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 1>;
+                        interface-pix-fmt = "rgb565";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ipu_disp2_1>;
+                };
                aips@70000000 { /* aips-1 */
                        spba@70000000 {
                                esdhc@70004000 { /* ESDHC1 */
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 75d069fcf897..1f5d45eff45e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -62,6 +62,13 @@
                interrupt-parent = <&tzic>;
                ranges;
+                ipu: ipu@40000000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx51-ipu";
+                        reg = <0x40000000 0x20000000>;
+                        interrupts = <11 10>;
+                };
                aips@70000000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
@@ -76,17 +83,22 @@
                                reg = <0x70000000 0x40000>;
                                ranges;
-                                esdhc@70004000 { /* ESDHC1 */
+                                esdhc1: esdhc@70004000 {
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70004000 0x4000>;
                                        interrupts = <1>;
+                                        clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+                                        clock-names = "ipg", "ahb", "per";
                                        status = "disabled";
                                };
-                                esdhc@70008000 { /* ESDHC2 */
+                                esdhc2: esdhc@70008000 {
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70008000 0x4000>;
                                        interrupts = <2>;
+                                        clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
                                        status = "disabled";
                                };
@@ -94,15 +106,19 @@
                                        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                        reg = <0x7000c000 0x4000>;
                                        interrupts = <33>;
+                                        clocks = <&clks 32>, <&clks 33>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
-                                ecspi@70010000 { /* ECSPI1 */
+                                ecspi1: ecspi@70010000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        compatible = "fsl,imx51-ecspi";
                                        reg = <0x70010000 0x4000>;
                                        interrupts = <36>;
+                                        clocks = <&clks 51>, <&clks 52>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -110,48 +126,55 @@
                                        compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                        reg = <0x70014000 0x4000>;
                                        interrupts = <30>;
+                                        clocks = <&clks 49>;
                                        fsl,fifo-depth = <15>;
                                        fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
                                        status = "disabled";
                                };
-                                esdhc@70020000 { /* ESDHC3 */
+                                esdhc3: esdhc@70020000 {
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70020000 0x4000>;
                                        interrupts = <3>;
+                                        clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
                                        status = "disabled";
                                };
-                                esdhc@70024000 { /* ESDHC4 */
+                                esdhc4: esdhc@70024000 {
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70024000 0x4000>;
                                        interrupts = <4>;
+                                        clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
                                        status = "disabled";
                                };
                        };
-                        usb@73f80000 {
+                        usbotg: usb@73f80000 {
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80000 0x0200>;
                                interrupts = <18>;
                                status = "disabled";
                        };
-                        usb@73f80200 {
+                        usbh1: usb@73f80200 {
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80200 0x0200>;
                                interrupts = <14>;
                                status = "disabled";
                        };
-                        usb@73f80400 {
+                        usbh2: usb@73f80400 {
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80400 0x0200>;
                                interrupts = <16>;
                                status = "disabled";
                        };
-                        usb@73f80600 {
+                        usbh3: usb@73f80600 {
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80600 0x0200>;
                                interrupts = <17>;
@@ -198,20 +221,22 @@
                                #interrupt-cells = <2>;
                        };
-                        wdog@73f98000 { /* WDOG1 */
+                        wdog1: wdog@73f98000 {
                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                reg = <0x73f98000 0x4000>;
                                interrupts = <58>;
+                                clocks = <&clks 0>;
                        };
-                        wdog@73f9c000 { /* WDOG2 */
+                        wdog2: wdog@73f9c000 {
                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                reg = <0x73f9c000 0x4000>;
                                interrupts = <59>;
+                                clocks = <&clks 0>;
                                status = "disabled";
                        };
-                        iomuxc@73fa8000 {
+                        iomuxc: iomuxc@73fa8000 {
                                compatible = "fsl,imx51-iomuxc";
                                reg = <0x73fa8000 0x4000>;
@@ -295,6 +320,66 @@
                                        };
                                };
+                                ipu_disp1 {
+                                        pinctrl_ipu_disp1_1: ipudisp1grp-1 {
+                                                fsl,pins = <
+                                                        528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
+                                                        529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
+                                                        530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
+                                                        531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
+                                                        532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
+                                                        533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
+                                                        535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
+                                                        537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
+                                                        539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
+                                                        541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
+                                                        543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
+                                                        545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
+                                                        547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
+                                                        549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
+                                                        551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
+                                                        553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
+                                                        555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
+                                                        557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
+                                                        559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
+                                                        563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
+                                                        567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
+                                                        571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
+                                                        575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
+                                                        579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
+                                                        584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
+                                                        583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
+                                                >;
+                                        };
+                                };
+                                ipu_disp2 {
+                                        pinctrl_ipu_disp2_1: ipudisp2grp-1 {
+                                                fsl,pins = <
+                                                        603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
+                                                        608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
+                                                        613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
+                                                        614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
+                                                        615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
+                                                        616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
+                                                        617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
+                                                        622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
+                                                        627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
+                                                        633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
+                                                        637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
+                                                        643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
+                                                        648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
+                                                        652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
+                                                        656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
+                                                        661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
+                                                        593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
+                                                        595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
+                                                        597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
+                                                        599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
+                                                >;
+                                        };
+                                };
                                uart1 {
                                        pinctrl_uart1_1: uart1grp-1 {
                                                fsl,pins = <
@@ -327,10 +412,30 @@
                                };
                        };
+                        pwm1: pwm@73fb4000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+                                reg = <0x73fb4000 0x4000>;
+                                clocks = <&clks 37>, <&clks 38>;
+                                clock-names = "ipg", "per";
+                                interrupts = <61>;
+                        };
+                        pwm2: pwm@73fb8000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+                                reg = <0x73fb8000 0x4000>;
+                                clocks = <&clks 39>, <&clks 40>;
+                                clock-names = "ipg", "per";
+                                interrupts = <94>;
+                        };
                        uart1: serial@73fbc000 {
                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                reg = <0x73fbc000 0x4000>;
                                interrupts = <31>;
+                                clocks = <&clks 28>, <&clks 29>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -338,8 +443,17 @@
                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                reg = <0x73fc0000 0x4000>;
                                interrupts = <32>;
+                                clocks = <&clks 30>, <&clks 31>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
+                        clks: ccm@73fd4000{
+                                compatible = "fsl,imx51-ccm";
+                                reg = <0x73fd4000 0x4000>;
+                                interrupts = <0 71 0x04 0 72 0x04>;
+                                #clock-cells = <1>;
+                        };
                };
                aips@80000000 { /* AIPS2 */
@@ -349,46 +463,54 @@
                        reg = <0x80000000 0x10000000>;
                        ranges;
-                        ecspi@83fac000 { /* ECSPI2 */
+                        ecspi2: ecspi@83fac000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "fsl,imx51-ecspi";
                                reg = <0x83fac000 0x4000>;
                                interrupts = <37>;
+                                clocks = <&clks 53>, <&clks 54>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
-                        sdma@83fb0000 {
+                        sdma: sdma@83fb0000 {
                                compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
                                reg = <0x83fb0000 0x4000>;
                                interrupts = <6>;
+                                clocks = <&clks 56>, <&clks 56>;
+                                clock-names = "ipg", "ahb";
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
                        };
-                        cspi@83fc0000 {
+                        cspi: cspi@83fc0000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
                                reg = <0x83fc0000 0x4000>;
                                interrupts = <38>;
+                                clocks = <&clks 55>, <&clks 0>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
-                        i2c@83fc4000 { /* I2C2 */
+                        i2c2: i2c@83fc4000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
                                reg = <0x83fc4000 0x4000>;
                                interrupts = <63>;
+                                clocks = <&clks 35>;
                                status = "disabled";
                        };
-                        i2c@83fc8000 { /* I2C1 */
+                        i2c1: i2c@83fc8000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
                                reg = <0x83fc8000 0x4000>;
                                interrupts = <62>;
+                                clocks = <&clks 34>;
                                status = "disabled";
                        };
@@ -396,21 +518,23 @@
                                compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                reg = <0x83fcc000 0x4000>;
                                interrupts = <29>;
+                                clocks = <&clks 48>;
                                fsl,fifo-depth = <15>;
                                fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
                                status = "disabled";
                        };
-                        audmux@83fd0000 {
+                        audmux: audmux@83fd0000 {
                                compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
                                reg = <0x83fd0000 0x4000>;
                                status = "disabled";
                        };
-                        nand@83fdb000 {
+                        nfc: nand@83fdb000 {
                                compatible = "fsl,imx51-nand";
                                reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
                                interrupts = <8>;
+                                clocks = <&clks 60>;
                                status = "disabled";
                        };
@@ -418,15 +542,18 @@
                                compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                reg = <0x83fe8000 0x4000>;
                                interrupts = <96>;
+                                clocks = <&clks 50>;
                                fsl,fifo-depth = <15>;
                                fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
                                status = "disabled";
                        };
-                        ethernet@83fec000 {
+                        fec: ethernet@83fec000 {
                                compatible = "fsl,imx51-fec", "fsl,imx27-fec";
                                reg = <0x83fec000 0x4000>;
                                interrupts = <87>;
+                                clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 08948af86d1a..b0075537195b 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -60,10 +60,17 @@
                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                        1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
+                                                >;
+                                        };
+                                        led_pin_gpio7_7: led_gpio7_7@0 {
+                                                fsl,pins = <
                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
                                                >;
                                        };
                                };
                        };
                        uart1: serial@53fbc000 {
@@ -100,76 +107,93 @@
                                pmic: dialog@48 {
                                        compatible = "dlg,da9053-aa", "dlg,da9052";
                                        reg = <0x48>;
+                                        interrupt-parent = <&gpio7>;
+                                        interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
                                        regulators {
-                                                buck0 {
+                                                buck1_reg: buck1 {
                                                        regulator-min-microvolt = <500000>;
                                                        regulator-max-microvolt = <2075000>;
+                                                        regulator-always-on;
                                                };
-                                                buck1 {
+                                                buck2_reg: buck2 {
                                                        regulator-min-microvolt = <500000>;
                                                        regulator-max-microvolt = <2075000>;
+                                                        regulator-always-on;
                                                };
-                                                buck2 {
+                                                buck3_reg: buck3 {
                                                        regulator-min-microvolt = <925000>;
                                                        regulator-max-microvolt = <2500000>;
+                                                        regulator-always-on;
                                                };
-                                                buck3 {
+                                                buck4_reg: buck4 {
                                                        regulator-min-microvolt = <925000>;
                                                        regulator-max-microvolt = <2500000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo4 {
+                                                ldo1_reg: ldo1 {
                                                        regulator-min-microvolt = <600000>;
                                                        regulator-max-microvolt = <1800000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
                                                };
-                                                ldo5 {
+                                                ldo2_reg: ldo2 {
+                                                        regulator-min-microvolt = <600000>;
+                                                        regulator-max-microvolt = <1800000>;
+                                                        regulator-always-on;
+                                                };
+                                                ldo3_reg: ldo3 {
                                                        regulator-min-microvolt = <600000>;
                                                        regulator-max-microvolt = <1800000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo6 {
+                                                ldo4_reg: ldo4 {
                                                        regulator-min-microvolt = <1725000>;
                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo7 {
+                                                ldo5_reg: ldo5 {
                                                        regulator-min-microvolt = <1725000>;
                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo8 {
+                                                ldo6_reg: ldo6 {
                                                        regulator-min-microvolt = <1200000>;
                                                        regulator-max-microvolt = <3600000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo9 {
+                                                ldo7_reg: ldo7 {
                                                        regulator-min-microvolt = <1200000>;
                                                        regulator-max-microvolt = <3600000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo10 {
+                                                ldo8_reg: ldo8 {
                                                        regulator-min-microvolt = <1200000>;
                                                        regulator-max-microvolt = <3600000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo11 {
+                                                ldo9_reg: ldo9 {
                                                        regulator-min-microvolt = <1200000>;
                                                        regulator-max-microvolt = <3600000>;
+                                                        regulator-always-on;
                                                };
-                                                ldo12 {
+                                                ldo10_reg: ldo10 {
                                                        regulator-min-microvolt = <1250000>;
                                                        regulator-max-microvolt = <3650000>;
-                                                };
+                                                        regulator-always-on;
-                                                ldo13 {
-                                                        regulator-min-microvolt = <1200000>;
-                                                        regulator-max-microvolt = <3600000>;
                                                };
                                        };
                                };
@@ -216,6 +240,8 @@
        leds {
                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio7_7>;
                user {
                        label = "Heartbeat";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 76ebb1ad2675..552aed4ff982 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -67,6 +67,13 @@
                interrupt-parent = <&tzic>;
                ranges;
+                ipu: ipu@18000000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx53-ipu";
+                        reg = <0x18000000 0x080000000>;
+                        interrupts = <11 10>;
+                };
                aips@50000000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
@@ -81,17 +88,23 @@
                                reg = <0x50000000 0x40000>;
                                ranges;
-                                esdhc@50004000 { /* ESDHC1 */
+                                esdhc1: esdhc@50004000 {
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50004000 0x4000>;
                                        interrupts = <1>;
+                                        clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
                                        status = "disabled";
                                };
-                                esdhc@50008000 { /* ESDHC2 */
+                                esdhc2: esdhc@50008000 {
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50008000 0x4000>;
                                        interrupts = <2>;
+                                        clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
                                        status = "disabled";
                                };
@@ -99,15 +112,19 @@
                                        compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                        reg = <0x5000c000 0x4000>;
                                        interrupts = <33>;
+                                        clocks = <&clks 32>, <&clks 33>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
-                                ecspi@50010000 { /* ECSPI1 */
+                                ecspi1: ecspi@50010000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x50010000 0x4000>;
                                        interrupts = <36>;
+                                        clocks = <&clks 51>, <&clks 52>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -115,48 +132,55 @@
                                        compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                        reg = <0x50014000 0x4000>;
                                        interrupts = <30>;
+                                        clocks = <&clks 49>;
                                        fsl,fifo-depth = <15>;
                                        fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
                                        status = "disabled";
                                };
-                                esdhc@50020000 { /* ESDHC3 */
+                                esdhc3: esdhc@50020000 {
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50020000 0x4000>;
                                        interrupts = <3>;
+                                        clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
                                        status = "disabled";
                                };
-                                esdhc@50024000 { /* ESDHC4 */
+                                esdhc4: esdhc@50024000 {
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50024000 0x4000>;
                                        interrupts = <4>;
+                                        clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
                                        status = "disabled";
                                };
                        };
-                        usb@53f80000 {
+                        usbotg: usb@53f80000 {
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80000 0x0200>;
                                interrupts = <18>;
                                status = "disabled";
                        };
-                        usb@53f80200 {
+                        usbh1: usb@53f80200 {
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80200 0x0200>;
                                interrupts = <14>;
                                status = "disabled";
                        };
-                        usb@53f80400 {
+                        usbh2: usb@53f80400 {
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80400 0x0200>;
                                interrupts = <16>;
                                status = "disabled";
                        };
-                        usb@53f80600 {
+                        usbh3: usb@53f80600 {
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80600 0x0200>;
                                interrupts = <17>;
@@ -203,20 +227,22 @@
                                #interrupt-cells = <2>;
                        };
-                        wdog@53f98000 { /* WDOG1 */
+                        wdog1: wdog@53f98000 {
                                compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                reg = <0x53f98000 0x4000>;
                                interrupts = <58>;
+                                clocks = <&clks 0>;
                        };
-                        wdog@53f9c000 { /* WDOG2 */
+                        wdog2: wdog@53f9c000 {
                                compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                reg = <0x53f9c000 0x4000>;
                                interrupts = <59>;
+                                clocks = <&clks 0>;
                                status = "disabled";
                        };
-                        iomuxc@53fa8000 {
+                        iomuxc: iomuxc@53fa8000 {
                                compatible = "fsl,imx53-iomuxc";
                                reg = <0x53fa8000 0x4000>;
@@ -316,6 +342,24 @@
                                        };
                                };
+                                can1 {
+                                        pinctrl_can1_1: can1grp-1 {
+                                                fsl,pins = <
+                                                        847 0x80000000  /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
+                                                        853 0x80000000  /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
+                                                >;
+                                        };
+                                };
+                                can2 {
+                                        pinctrl_can2_1: can2grp-1 {
+                                                fsl,pins = <
+                                                        67  0x80000000  /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
+                                                        74  0x80000000  /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
+                                                >;
+                                        };
+                                };
                                i2c1 {
                                        pinctrl_i2c1_1: i2c1grp-1 {
                                                fsl,pins = <
@@ -334,6 +378,15 @@
                                        };
                                };
+                                i2c3 {
+                                        pinctrl_i2c3_1: i2c3grp-1 {
+                                                fsl,pins = <
+                                                        1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
+                                                        1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
+                                                >;
+                                        };
+                                };
                                uart1 {
                                        pinctrl_uart1_1: uart1grp-1 {
                                                fsl,pins = <
@@ -369,12 +422,51 @@
                                                >;
                                        };
                                };
+                                uart4 {
+                                        pinctrl_uart4_1: uart4grp-1 {
+                                                fsl,pins = <
+                                                        11 0x1c5        /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
+                                                        18 0x1c5        /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
+                                                >;
+                                        };
+                                };
+                                uart5 {
+                                        pinctrl_uart5_1: uart5grp-1 {
+                                                fsl,pins = <
+                                                        24 0x1c5        /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
+                                                        31 0x1c5        /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
+                                                >;
+                                        };
+                                };
+                        };
+                        pwm1: pwm@53fb4000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+                                reg = <0x53fb4000 0x4000>;
+                                clocks = <&clks 37>, <&clks 38>;
+                                clock-names = "ipg", "per";
+                                interrupts = <61>;
+                        };
+                        pwm2: pwm@53fb8000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+                                reg = <0x53fb8000 0x4000>;
+                                clocks = <&clks 39>, <&clks 40>;
+                                clock-names = "ipg", "per";
+                                interrupts = <94>;
                        };
                        uart1: serial@53fbc000 {
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53fbc000 0x4000>;
                                interrupts = <31>;
+                                clocks = <&clks 28>, <&clks 29>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -382,6 +474,8 @@
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53fc0000 0x4000>;
                                interrupts = <32>;
+                                clocks = <&clks 30>, <&clks 31>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -389,6 +483,8 @@
                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
                                reg = <0x53fc8000 0x4000>;
                                interrupts = <82>;
+                                clocks = <&clks 158>, <&clks 157>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -396,9 +492,18 @@
                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
                                reg = <0x53fcc000 0x4000>;
                                interrupts = <83>;
+                                clocks = <&clks 158>, <&clks 157>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
+                        clks: ccm@53fd4000{
+                                compatible = "fsl,imx53-ccm";
+                                reg = <0x53fd4000 0x4000>;
+                                interrupts = <0 71 0x04 0 72 0x04>;
+                                #clock-cells = <1>;
+                        };
                        gpio5: gpio@53fdc000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                reg = <0x53fdc000 0x4000>;
@@ -429,12 +534,13 @@
                                #interrupt-cells = <2>;
                        };
-                        i2c@53fec000 { /* I2C3 */
+                        i2c3: i2c@53fec000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                reg = <0x53fec000 0x4000>;
                                interrupts = <64>;
+                                clocks = <&clks 88>;
                                status = "disabled";
                        };
@@ -442,6 +548,8 @@
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53ff0000 0x4000>;
                                interrupts = <13>;
+                                clocks = <&clks 65>, <&clks 66>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
                };
@@ -457,49 +565,59 @@
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x63f90000 0x4000>;
                                interrupts = <86>;
+                                clocks = <&clks 67>, <&clks 68>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
-                        ecspi@63fac000 { /* ECSPI2 */
+                        ecspi2: ecspi@63fac000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
                                reg = <0x63fac000 0x4000>;
                                interrupts = <37>;
+                                clocks = <&clks 53>, <&clks 54>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
-                        sdma@63fb0000 {
+                        sdma: sdma@63fb0000 {
                                compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
                                reg = <0x63fb0000 0x4000>;
                                interrupts = <6>;
+                                clocks = <&clks 56>, <&clks 56>;
+                                clock-names = "ipg", "ahb";
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
                        };
-                        cspi@63fc0000 {
+                        cspi: cspi@63fc0000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
                                reg = <0x63fc0000 0x4000>;
                                interrupts = <38>;
+                                clocks = <&clks 55>, <&clks 0>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
-                        i2c@63fc4000 { /* I2C2 */
+                        i2c2: i2c@63fc4000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                reg = <0x63fc4000 0x4000>;
                                interrupts = <63>;
+                                clocks = <&clks 35>;
                                status = "disabled";
                        };
-                        i2c@63fc8000 { /* I2C1 */
+                        i2c1: i2c@63fc8000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                reg = <0x63fc8000 0x4000>;
                                interrupts = <62>;
+                                clocks = <&clks 34>;
                                status = "disabled";
                        };
@@ -507,21 +625,23 @@
                                compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                reg = <0x63fcc000 0x4000>;
                                interrupts = <29>;
+                                clocks = <&clks 48>;
                                fsl,fifo-depth = <15>;
                                fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
                                status = "disabled";
                        };
-                        audmux@63fd0000 {
+                        audmux: audmux@63fd0000 {
                                compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
                                reg = <0x63fd0000 0x4000>;
                                status = "disabled";
                        };
-                        nand@63fdb000 {
+                        nfc: nand@63fdb000 {
                                compatible = "fsl,imx53-nand";
                                reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
                                interrupts = <8>;
+                                clocks = <&clks 60>;
                                status = "disabled";
                        };
@@ -529,15 +649,18 @@
                                compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                reg = <0x63fe8000 0x4000>;
                                interrupts = <96>;
+                                clocks = <&clks 50>;
                                fsl,fifo-depth = <15>;
                                fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
                                status = "disabled";
                        };
-                        ethernet@63fec000 {
+                        fec: ethernet@63fec000 {
                                compatible = "fsl,imx53-fec", "fsl,imx25-fec";
                                reg = <0x63fec000 0x4000>;
                                interrupts = <87>;
+                                clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
new file mode 100644
index 000000000000..826e4ad1477e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx6q.dtsi"
+/ {
+        model = "Freescale i.MX6 Quad SABRE Automotive Board";
+        compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+        soc {
+                aips-bus@02000000 { /* AIPS1 */
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
+                                                        13   0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
+                                                >;
+                                        };
+                                };
+                        };
+                };
+                aips-bus@02100000 { /* AIPS2 */
+                        uart4: serial@021f0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart4_1>;
+                                status = "okay";
+                        };
+                        ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_2>;
+                                phy-mode = "rgmii";
+                                status = "okay";
+                        };
+                        usdhc@02198000 { /* uSDHC3 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc3_1>;
+                                cd-gpios = <&gpio6 15 0>;
+                                wp-gpios = <&gpio1 13 0>;
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index e596c28c214d..a42402562b7b 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -38,6 +38,8 @@
                                hog {
                                        pinctrl_hog: hoggrp {
                                                fsl,pins = <
+                                                        1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
+                                                        1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
                                                        1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
                                                        1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
                                                        1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
@@ -73,4 +75,20 @@
                        };
                };
        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio1 4 0>;
+                        linux,code = <115>; /* KEY_VOLUMEUP */
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio1 5 0>;
+                        linux,code = <114>; /* KEY_VOLUMEDOWN */
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index f3990b04fecf..d6265ca97119 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -36,6 +36,14 @@
                        compatible = "arm,cortex-a9";
                        reg = <0>;
                        next-level-cache = <&L2>;
+                        operating-points = <
+                                /* kHz    uV */
+                                792000  1100000
+                                396000  950000
+                                198000  850000
+                        >;
+                        clock-latency = <61036>; /* two CLK32 periods */
+                        cpu0-supply = <&reg_cpu>;
                };
                cpu@1 {
@@ -100,7 +108,7 @@
                        clocks = <&clks 106>;
                };
-                gpmi-nand@00112000 {
+                nfc: gpmi-nand@00112000 {
                        compatible = "fsl,imx6q-gpmi-nand";
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -144,12 +152,12 @@
                                reg = <0x02000000 0x40000>;
                                ranges;
-                                spdif@02004000 {
+                                spdif: spdif@02004000 {
                                        reg = <0x02004000 0x4000>;
                                        interrupts = <0 52 0x04>;
                                };
-                                ecspi@02008000 { /* eCSPI1 */
+                                ecspi1: ecspi@02008000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -160,7 +168,7 @@
                                        status = "disabled";
                                };
-                                ecspi@0200c000 { /* eCSPI2 */
+                                ecspi2: ecspi@0200c000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -171,7 +179,7 @@
                                        status = "disabled";
                                };
-                                ecspi@02010000 { /* eCSPI3 */
+                                ecspi3: ecspi@02010000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -182,7 +190,7 @@
                                        status = "disabled";
                                };
-                                ecspi@02014000 { /* eCSPI4 */
+                                ecspi4: ecspi@02014000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -193,7 +201,7 @@
                                        status = "disabled";
                                };
-                                ecspi@02018000 { /* eCSPI5 */
+                                ecspi5: ecspi@02018000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -213,7 +221,7 @@
                                        status = "disabled";
                                };
-                                esai@02024000 {
+                                esai: esai@02024000 {
                                        reg = <0x02024000 0x4000>;
                                        interrupts = <0 51 0x04>;
                                };
@@ -248,7 +256,7 @@
                                        status = "disabled";
                                };
-                                asrc@02034000 {
+                                asrc: asrc@02034000 {
                                        reg = <0x02034000 0x4000>;
                                        interrupts = <0 50 0x04>;
                                };
@@ -258,7 +266,7 @@
                                };
                        };
-                        vpu@02040000 {
+                        vpu: vpu@02040000 {
                                reg = <0x02040000 0x3c000>;
                                interrupts = <0 3 0x04 0 12 0x04>;
                        };
@@ -267,37 +275,53 @@
                                reg = <0x0207c000 0x4000>;
                        };
-                        pwm@02080000 { /* PWM1 */
+                        pwm1: pwm@02080000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x02080000 0x4000>;
                                interrupts = <0 83 0x04>;
+                                clocks = <&clks 62>, <&clks 145>;
+                                clock-names = "ipg", "per";
                        };
-                        pwm@02084000 { /* PWM2 */
+                        pwm2: pwm@02084000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x02084000 0x4000>;
                                interrupts = <0 84 0x04>;
+                                clocks = <&clks 62>, <&clks 146>;
+                                clock-names = "ipg", "per";
                        };
-                        pwm@02088000 { /* PWM3 */
+                        pwm3: pwm@02088000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x02088000 0x4000>;
                                interrupts = <0 85 0x04>;
+                                clocks = <&clks 62>, <&clks 147>;
+                                clock-names = "ipg", "per";
                        };
-                        pwm@0208c000 { /* PWM4 */
+                        pwm4: pwm@0208c000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x0208c000 0x4000>;
                                interrupts = <0 86 0x04>;
+                                clocks = <&clks 62>, <&clks 148>;
+                                clock-names = "ipg", "per";
                        };
-                        flexcan@02090000 { /* CAN1 */
+                        can1: flexcan@02090000 {
                                reg = <0x02090000 0x4000>;
                                interrupts = <0 110 0x04>;
                        };
-                        flexcan@02094000 { /* CAN2 */
+                        can2: flexcan@02094000 {
                                reg = <0x02094000 0x4000>;
                                interrupts = <0 111 0x04>;
                        };
-                        gpt@02098000 {
+                        gpt: gpt@02098000 {
                                compatible = "fsl,imx6q-gpt";
                                reg = <0x02098000 0x4000>;
                                interrupts = <0 55 0x04>;
@@ -373,19 +397,19 @@
                                #interrupt-cells = <2>;
                        };
-                        kpp@020b8000 {
+                        kpp: kpp@020b8000 {
                                reg = <0x020b8000 0x4000>;
                                interrupts = <0 82 0x04>;
                        };
-                        wdog@020bc000 { /* WDOG1 */
+                        wdog1: wdog@020bc000 {
                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                reg = <0x020bc000 0x4000>;
                                interrupts = <0 80 0x04>;
                                clocks = <&clks 0>;
                        };
-                        wdog@020c0000 { /* WDOG2 */
+                        wdog2: wdog@020c0000 {
                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                reg = <0x020c0000 0x4000>;
                                interrupts = <0 81 0x04>;
@@ -447,7 +471,7 @@
                                        anatop-max-voltage = <2750000>;
                                };
-                                regulator-vddcore@140 {
+                                reg_cpu: regulator-vddcore@140 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "cpu";
                                        regulator-min-microvolt = <725000>;
@@ -505,27 +529,35 @@
                        };
                        snvs@020cc000 {
-                                reg = <0x020cc000 0x4000>;
+                                compatible = "fsl,sec-v4.0-mon", "simple-bus";
-                                interrupts = <0 19 0x04 0 20 0x04>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x020cc000 0x4000>;
+                                snvs-rtc-lp@34 {
+                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                        reg = <0x34 0x58>;
+                                        interrupts = <0 19 0x04 0 20 0x04>;
+                                };
                        };
-                        epit@020d0000 { /* EPIT1 */
+                        epit1: epit@020d0000 { /* EPIT1 */
                                reg = <0x020d0000 0x4000>;
                                interrupts = <0 56 0x04>;
                        };
-                        epit@020d4000 { /* EPIT2 */
+                        epit2: epit@020d4000 { /* EPIT2 */
                                reg = <0x020d4000 0x4000>;
                                interrupts = <0 57 0x04>;
                        };
-                        src@020d8000 {
+                        src: src@020d8000 {
                                compatible = "fsl,imx6q-src";
                                reg = <0x020d8000 0x4000>;
                                interrupts = <0 91 0x04 0 96 0x04>;
                        };
-                        gpc@020dc000 {
+                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
                                interrupts = <0 89 0x04 0 90 0x04>;
@@ -536,7 +568,7 @@
                                reg = <0x020e0000 0x38>;
                        };
-                        iomuxc@020e0000 {
+                        iomuxc: iomuxc@020e0000 {
                                compatible = "fsl,imx6q-iomuxc";
                                reg = <0x020e0000 0x4000>;
@@ -580,6 +612,7 @@
                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                        1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
                                                >;
                                        };
@@ -748,17 +781,17 @@
                                };
                        };
-                        dcic@020e4000 { /* DCIC1 */
+                        dcic1: dcic@020e4000 {
                                reg = <0x020e4000 0x4000>;
                                interrupts = <0 124 0x04>;
                        };
-                        dcic@020e8000 { /* DCIC2 */
+                        dcic2: dcic@020e8000 {
                                reg = <0x020e8000 0x4000>;
                                interrupts = <0 125 0x04>;
                        };
-                        sdma@020ec000 {
+                        sdma: sdma@020ec000 {
                                compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <0 2 0x04>;
@@ -784,7 +817,7 @@
                                reg = <0x0217c000 0x4000>;
                        };
-                        usb@02184000 { /* USB OTG */
+                        usbotg: usb@02184000 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184000 0x200>;
                                interrupts = <0 43 0x04>;
@@ -794,7 +827,7 @@
                                status = "disabled";
                        };
-                        usb@02184200 { /* USB1 */
+                        usbh1: usb@02184200 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184200 0x200>;
                                interrupts = <0 40 0x04>;
@@ -804,7 +837,7 @@
                                status = "disabled";
                        };
-                        usb@02184400 { /* USB2 */
+                        usbh2: usb@02184400 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184400 0x200>;
                                interrupts = <0 41 0x04>;
@@ -813,7 +846,7 @@
                                status = "disabled";
                        };
-                        usb@02184600 { /* USB3 */
+                        usbh3: usb@02184600 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184600 0x200>;
                                interrupts = <0 42 0x04>;
@@ -822,19 +855,19 @@
                                status = "disabled";
                        };
-                        usbmisc: usbmisc@02184800 {
+                        usbmisc: usbmisc: usbmisc@02184800 {
                                #index-cells = <1>;
                                compatible = "fsl,imx6q-usbmisc";
                                reg = <0x02184800 0x200>;
                                clocks = <&clks 162>;
                        };
-                        ethernet@02188000 {
+                        fec: ethernet@02188000 {
                                compatible = "fsl,imx6q-fec";
                                reg = <0x02188000 0x4000>;
                                interrupts = <0 118 0x04 0 119 0x04>;
-                                clocks = <&clks 117>, <&clks 117>;
+                                clocks = <&clks 117>, <&clks 117>, <&clks 177>;
-                                clock-names = "ipg", "ahb";
+                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
@@ -843,66 +876,70 @@
                                interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
                        };
-                        usdhc@02190000 { /* uSDHC1 */
+                        usdhc1: usdhc@02190000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02190000 0x4000>;
                                interrupts = <0 22 0x04>;
                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
                                status = "disabled";
                        };
-                        usdhc@02194000 { /* uSDHC2 */
+                        usdhc2: usdhc@02194000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02194000 0x4000>;
                                interrupts = <0 23 0x04>;
                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
                                status = "disabled";
                        };
-                        usdhc@02198000 { /* uSDHC3 */
+                        usdhc3: usdhc@02198000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02198000 0x4000>;
                                interrupts = <0 24 0x04>;
                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
                                status = "disabled";
                        };
-                        usdhc@0219c000 { /* uSDHC4 */
+                        usdhc4: usdhc@0219c000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x0219c000 0x4000>;
                                interrupts = <0 25 0x04>;
                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
                                status = "disabled";
                        };
-                        i2c@021a0000 { /* I2C1 */
+                        i2c1: i2c@021a0000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a0000 0x4000>;
                                interrupts = <0 36 0x04>;
                                clocks = <&clks 125>;
                                status = "disabled";
                        };
-                        i2c@021a4000 { /* I2C2 */
+                        i2c2: i2c@021a4000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a4000 0x4000>;
                                interrupts = <0 37 0x04>;
                                clocks = <&clks 126>;
                                status = "disabled";
                        };
-                        i2c@021a8000 { /* I2C3 */
+                        i2c3: i2c@021a8000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a8000 0x4000>;
                                interrupts = <0 38 0x04>;
                                clocks = <&clks 127>;
@@ -913,12 +950,12 @@
                                reg = <0x021ac000 0x4000>;
                        };
-                        mmdc@021b0000 { /* MMDC0 */
+                        mmdc0: mmdc@021b0000 { /* MMDC0 */
                                compatible = "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
                        };
-                        mmdc@021b4000 { /* MMDC1 */
+                        mmdc1: mmdc@021b4000 { /* MMDC1 */
                                reg = <0x021b4000 0x4000>;
                        };
@@ -946,7 +983,7 @@
                                interrupts = <0 109 0x04>;
                        };
-                        audmux@021d8000 {
+                        audmux: audmux@021d8000 {
                                compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
                                reg = <0x021d8000 0x4000>;
                                status = "disabled";
@@ -1001,5 +1038,23 @@
                                status = "disabled";
                        };
                };
+                ipu1: ipu@02400000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx6q-ipu";
+                        reg = <0x02400000 0x400000>;
+                        interrupts = <0 6 0x4 0 5 0x4>;
+                        clocks = <&clks 130>, <&clks 131>, <&clks 132>;
+                        clock-names = "bus", "di0", "di1";
+                };
+                ipu2: ipu@02800000 {
+                        #crtc-cells = <1>;
+                        compatible = "fsl,imx6q-ipu";
+                        reg = <0x02800000 0x400000>;
+                        interrupts = <0 8 0x4 0 7 0x4>;
+                        clocks = <&clks 133>, <&clks 134>, <&clks 137>;
+                        clock-names = "bus", "di0", "di1";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 61767757b50a..c9c3fa344647 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -18,6 +18,11 @@
                bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
        };
+        syscon {
+                /* AP system controller registers */
+                reg = <0x11000000 0x100>;
+        };
        timer0: timer@13000000 {
                compatible = "arm,integrator-timer";
        };
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 2dd5e4e48481..8b119399025a 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -18,6 +18,11 @@
                bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
        };
+        cpcon {
+                /* CP controller registers */
+                reg = <0xcb000000 0x100>;
+        };
        timer0: timer@13000000 {
                compatible = "arm,sp804", "arm,primecell";
        };
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
new file mode 100644
index 000000000000..d6c9d65cbaeb
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -0,0 +1,44 @@
+/ {
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        compatible = "marvell,88f6281-pinctrl";
+                        reg = <0x10000 0x20>;
+                        pmx_nand: pmx-nand {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                               "mpp4", "mpp5", "mpp18",
+                                               "mpp19";
+                                marvell,function = "nand";
+                        };
+                        pmx_sata0: pmx-sata0 {
+                                marvell,pins = "mpp5", "mpp21", "mpp23";
+                                marvell,function = "sata0";
+                        };
+                        pmx_sata1: pmx-sata1 {
+                                marvell,pins = "mpp4", "mpp20", "mpp22";
+                                marvell,function = "sata1";
+                        };
+                        pmx_spi: pmx-spi {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
+                                marvell,function = "spi";
+                        };
+                        pmx_twsi0: pmx-twsi0 {
+                                marvell,pins = "mpp8", "mpp9";
+                                marvell,function = "twsi0";
+                        };
+                        pmx_uart0: pmx-uart0 {
+                                marvell,pins = "mpp10", "mpp11";
+                                marvell,function = "uart0";
+                        };
+                        pmx_uart1: pmx-uart1 {
+                                marvell,pins = "mpp13", "mpp14";
+                                marvell,function = "uart1";
+                        };
+                        pmx_sdio: pmx-sdio {
+                                marvell,pins = "mpp12", "mpp13", "mpp14",
+                                               "mpp15", "mpp16", "mpp17";
+                                marvell,function = "sdio";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
new file mode 100644
index 000000000000..9ae2004d5675
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -0,0 +1,45 @@
+/ {
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        compatible = "marvell,88f6282-pinctrl";
+                        reg = <0x10000 0x20>;
+                        pmx_sata0: pmx-sata0 {
+                                marvell,pins = "mpp5", "mpp21", "mpp23";
+                                marvell,function = "sata0";
+                        };
+                        pmx_sata1: pmx-sata1 {
+                                marvell,pins = "mpp4", "mpp20", "mpp22";
+                                marvell,function = "sata1";
+                        };
+                        pmx_spi: pmx-spi {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
+                                marvell,function = "spi";
+                        };
+                        pmx_twsi0: pmx-twsi0 {
+                                marvell,pins = "mpp8", "mpp9";
+                                marvell,function = "twsi0";
+                        };
+                        pmx_uart0: pmx-uart0 {
+                                marvell,pins = "mpp10", "mpp11";
+                                marvell,function = "uart0";
+                        };
+                        pmx_uart1: pmx-uart1 {
+                                marvell,pins = "mpp13", "mpp14";
+                                marvell,function = "uart1";
+                        };
+                };
+                i2c@11100 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11100 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <32>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
new file mode 100644
index 000000000000..3271e4c8ea07
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
@@ -0,0 +1,31 @@
+/ {
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        compatible = "marvell,98dx4122-pinctrl";
+                        reg = <0x10000 0x20>;
+                        pmx_nand: pmx-nand {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                               "mpp4", "mpp5", "mpp18",
+                                               "mpp19";
+                                marvell,function = "nand";
+                        };
+                        pmx_spi: pmx-spi {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
+                                marvell,function = "spi";
+                        };
+                        pmx_twsi0: pmx-twsi0 {
+                                marvell,pins = "mpp8", "mpp9";
+                                marvell,function = "twsi0";
+                        };
+                        pmx_uart0: pmx-uart0 {
+                                marvell,pins = "mpp10", "mpp11";
+                                marvell,function = "uart0";
+                        };
+                        pmx_uart1: pmx-uart1 {
+                                marvell,pins = "mpp13", "mpp14";
+                                marvell,function = "uart1";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 9b32d0272825..6875ac00c174 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -1,4 +1,5 @@
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "D-Link DNS NASes (kirkwood-based)";
@@ -35,7 +36,116 @@
                                      6000 2>;
        };
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio1 4 0>;
+        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_nand &pmx_uart1
+                                      &pmx_sata0 &pmx_sata1
+                                      &pmx_led_power
+                                      &pmx_led_red_right_hdd
+                                      &pmx_led_red_left_hdd
+                                      &pmx_led_red_usb_325
+                                      &pmx_button_power
+                                      &pmx_led_red_usb_320
+                                      &pmx_power_off &pmx_power_back_on
+                                      &pmx_power_sata0 &pmx_power_sata1
+                                      &pmx_present_sata0 &pmx_present_sata1
+                                      &pmx_led_white_usb &pmx_fan_tacho
+                                      &pmx_fan_high_speed &pmx_fan_low_speed
+                                      &pmx_button_unmount &pmx_button_reset
+                                      &pmx_temp_alarm >;
+                        pinctrl-names = "default";
+                        pmx_sata0: pmx-sata0 {
+                                marvell,pins = "mpp20";
+                                marvell,function = "sata1";
+                        };
+                        pmx_sata1: pmx-sata1 {
+                                marvell,pins = "mpp21";
+                                marvell,function = "sata0";
+                        };
+                        pmx_led_power: pmx-led-power {
+                                marvell,pins = "mpp26";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red_right_hdd: pmx-led-red-right-hdd {
+                                marvell,pins = "mpp27";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red_left_hdd: pmx-led-red-left-hdd {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red_usb_325: pmx-led-red-usb-325 {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_power: pmx-button-power {
+                                marvell,pins = "mpp34";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red_usb_320: pmx-led-red-usb-320 {
+                                marvell,pins = "mpp35";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_off: pmx-power-off {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_back_on: pmx-power-back-on {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_sata0: pmx-power-sata0 {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_sata1: pmx-power-sata1 {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                        pmx_present_sata0: pmx-present-sata0 {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_present_sata1: pmx-present-sata1 {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_white_usb: pmx-led-white-usb {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fan_tacho: pmx-fan-tacho {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fan_high_speed: pmx-fan-high-speed {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fan_low_speed: pmx-fan-low-speed {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_unmount: pmx-button-unmount {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_reset: pmx-button-reset {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                        pmx_temp_alarm: pmx-temp-alarm {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                };
                sata@80000 {
                        status = "okay";
                        nr-ports = <2>;
@@ -43,6 +153,7 @@
                nand@3000000 {
                        status = "okay";
+                        chip-delay = <35>;
                        partition@0 {
                                label = "u-boot";
@@ -76,4 +187,33 @@
                        };
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                sata0_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "SATA0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 7 0>;
+                };
+                sata1_power: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "SATA1 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 8 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 08a582414b88..2e3dd34e21a5 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "Seagate FreeAgent Dockstar";
@@ -16,6 +17,25 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_usb_power_enable
+                                      &pmx_led_green &pmx_led_orange >;
+                        pinctrl-names = "default";
+                        pmx_usb_power_enable: pmx-usb-power-enable {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_green: pmx-led-green {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_orange: pmx-led-orange {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                };
                serial@12000 {
                        clock-frequency = <200000000>;
                        status = "ok";
@@ -54,4 +74,21 @@
                        gpios = <&gpio1 15 1>;
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 29 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 26e281fbf6bc..f2d386c95b07 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "Globalscale Technologies Dreamplug";
@@ -16,6 +17,26 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_spi
+                                      &pmx_led_bluetooth &pmx_led_wifi
+                                      &pmx_led_wifi_ap >;
+                        pinctrl-names = "default";
+                        pmx_led_bluetooth: pmx-led-bluetooth {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wifi: pmx-led-wifi {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wifi_ap: pmx-led-wifi-ap {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                };
                serial@12000 {
                        clock-frequency = <200000000>;
                        status = "ok";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 7c8238fbb6f9..1b133e0c566e 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "Seagate GoFlex Net";
@@ -16,6 +17,61 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
+                                      &pmx_led_left_cap_0 &pmx_led_left_cap_1
+                                      &pmx_led_left_cap_2 &pmx_led_left_cap_3
+                                      &pmx_led_right_cap_0 &pmx_led_right_cap_1
+                                      &pmx_led_right_cap_2 &pmx_led_right_cap_3
+                                    >;
+                        pinctrl-names = "default";
+                        pmx_usb_power_enable: pmx-usb-power-enable {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_right_cap_0: pmx-led_right_cap_0 {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_right_cap_1: pmx-led_right_cap_1 {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_right_cap_2: pmx-led_right_cap_2 {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_right_cap_3: pmx-led_right_cap_3 {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_left_cap_0: pmx-led_left_cap_0 {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_left_cap_1: pmx-led_left_cap_1 {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_left_cap_2: pmx-led_left_cap_2 {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_left_cap_3: pmx-led_left_cap_3 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_green: pmx-led_green {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_orange: pmx-led_orange {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                };
                serial@12000 {
                        clock-frequency = <200000000>;
                        status = "ok";
@@ -96,4 +152,21 @@
                        gpios = <&gpio1 9 0>;
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 29 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 66794ed75ff1..71902da33d63 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
@@ -16,6 +17,39 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_nand
+                                      &pmx_led_os_red &pmx_power_off
+                                      &pmx_led_os_green &pmx_led_usb_transfer
+                                      &pmx_button_reset &pmx_button_usb_copy >;
+                        pinctrl-names = "default";
+                        pmx_led_os_red: pmx-led-os-red {
+                                marvell,pins = "mpp22";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_off: pmx-power-off {
+                                marvell,pins = "mpp24";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_os_green: pmx-led-os-green {
+                                marvell,pins = "mpp25";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_usb_transfer: pmx-led-usb-transfer {
+                                marvell,pins = "mpp27";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_reset: pmx-button-reset {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_usb_copy: pmx-button-usb-copy {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                };
                serial@12000 {
                        clock-frequency = <200000000>;
                        status = "okay";
@@ -79,4 +113,10 @@
                        gpios = <&gpio0 27 0>;
                };
        };
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 24 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index d97cd9d4753e..504f16be8b54 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "Iomega Iconnect";
@@ -18,6 +19,56 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
+                                      &pmx_gpio_41 &pmx_gpio_42
+                                      &pmx_gpio_43 &pmx_gpio_44
+                                      &pmx_gpio_45 &pmx_gpio_46
+                                      &pmx_gpio_47 &pmx_gpio_48 >;
+                        pinctrl-names = "default";
+                        pmx_gpio_12: pmx-gpio-12 {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_35: pmx-gpio-35 {
+                                marvell,pins = "mpp35";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_41: pmx-gpio-41 {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_42: pmx-gpio-42 {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_43: pmx-gpio-43 {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_44: pmx-gpio-44 {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_45: pmx-gpio-45 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_46: pmx-gpio-46 {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_47: pmx-gpio-47 {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_gpio_48: pmx-gpio-48 {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                };
                i2c@11000 {
                        status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 865aeec40a26..6cae4599c4b3 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        model = "Iomega StorCenter ix2-200";
@@ -16,6 +17,94 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_button_reset &pmx_button_power
+                                      &pmx_led_backup &pmx_led_power
+                                      &pmx_button_otb &pmx_led_rebuild
+                                      &pmx_led_health
+                                      &pmx_led_sata_brt_ctrl_1
+                                      &pmx_led_sata_brt_ctrl_2
+                                      &pmx_led_backup_brt_ctrl_1
+                                      &pmx_led_backup_brt_ctrl_2
+                                      &pmx_led_power_brt_ctrl_1
+                                      &pmx_led_power_brt_ctrl_2
+                                      &pmx_led_health_brt_ctrl_1
+                                      &pmx_led_health_brt_ctrl_2
+                                      &pmx_led_rebuild_brt_ctrl_1
+                                      &pmx_led_rebuild_brt_ctrl_2 >;
+                        pinctrl-names = "default";
+                        pmx_button_reset: pmx-button-reset {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_power: pmx-button-power {
+                                marvell,pins = "mpp14";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_backup: pmx-led-backup {
+                                marvell,pins = "mpp15";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_power: pmx-led-power {
+                                marvell,pins = "mpp16";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_otb: pmx-button-otb {
+                                marvell,pins = "mpp35";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_rebuild: pmx-led-rebuild {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_health: pmx-led_health {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                };
                i2c@11000 {
                        status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
new file mode 100644
index 000000000000..0bdce0ad7277
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+/include/ "kirkwood-ns2-common.dtsi"
+/ {
+        model = "LaCie Internet Space v2";
+        compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+        ns2-leds {
+                compatible = "lacie,ns2-leds";
+                blue-sata {
+                        label = "ns2:blue:sata";
+                        slow-gpio = <&gpio0 29 0>;
+                        cmd-gpio = <&gpio0 30 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 75bdb93fed26..8db3123ac80f 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-98dx4122.dtsi"
 / {
        model = "Keymile Kirkwood Reference Design";
@@ -16,6 +17,22 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
+                                &pmx_i2c_gpio_scl >;
+                        pinctrl-names = "default";
+                        pmx_i2c_gpio_sda: pmx-gpio-sda {
+                                marvell,pins = "mpp8";
+                                marvell,function = "gpio";
+                        };
+                        pmx_i2c_gpio_scl: pmx-gpio-scl {
+                                marvell,pins = "mpp9";
+                                marvell,function = "gpio";
+                        };
+                };
                serial@12000 {
                        clock-frequency = <200000000>;
                        status = "ok";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 8fea375c734d..37d45c4f88fb 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -1,4 +1,5 @@
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
        chosen {
@@ -6,6 +7,71 @@
        };
        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
+                                      &pmx_fan_low &pmx_fan_high
+                                      &pmx_led_function_red &pmx_led_alarm
+                                      &pmx_led_info &pmx_led_power
+                                      &pmx_fan_lock &pmx_button_function
+                                      &pmx_power_switch &pmx_power_auto_switch
+                                      &pmx_led_function_blue >;
+                        pinctrl-names = "default";
+                        pmx_power_hdd: pmx-power-hdd {
+                                marvell,pins = "mpp10";
+                                marvell,function = "gpo";
+                        };
+                        pmx_usb_vbus: pmx-usb-vbus {
+                                marvell,pins = "mpp11";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fan_high: pmx-fan-high {
+                                marvell,pins = "mpp18";
+                                marvell,function = "gpo";
+                        };
+                        pmx_fan_low: pmx-fan-low {
+                                marvell,pins = "mpp19";
+                                marvell,function = "gpo";
+                        };
+                        pmx_led_function_blue: pmx-led-function-blue {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_alarm: pmx-led-alarm {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_info: pmx-led-info {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_power: pmx-led-power {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fan_lock: pmx-fan-lock {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_function: pmx-button-function {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_switch: pmx-power-switch {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_auto_switch: pmx-power-auto-switch {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_function_red: pmx-led-function_red {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                };
                sata@80000 {
                        status = "okay";
                        nr-ports = <1>;
@@ -94,4 +160,44 @@
                        gpios = <&gpio1 16 1>;
                };
        };
+        gpio_fan {
+                compatible = "gpio-fan";
+                gpios = <&gpio0 19 1
+                         &gpio0 18 1>;
+                gpio-fan,speed-map = <0    3
+                                      1500 2
+                                      3250 1
+                                      5000 0>;
+                alarm-gpios = <&gpio1 8 0>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 11 0>;
+                };
+                hdd_power: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "HDD Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 10 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
new file mode 100644
index 000000000000..262c65403760
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -0,0 +1,178 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+/ {
+        model = "MPL CEC4";
+        compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_nand &pmx_uart0
+                                      &pmx_led_health &pmx_sdio
+                                      &pmx_sata0 &pmx_sata1
+                                      &pmx_led_user1o
+                                      &pmx_led_user1g &pmx_led_user0o
+                                      &pmx_led_user0g &pmx_led_misc
+                                      &pmx_sdio_cd
+                                    >;
+                        pinctrl-names = "default";
+                        pmx_led_health: pmx-led-health {
+                                marvell,pins = "mpp7";
+                                marvell,function = "gpo";
+                        };
+                        pmx_sata1: pmx-sata1 {
+                                marvell,pins = "mpp34";
+                                marvell,function = "sata1";
+                        };
+                        pmx_sata0: pmx-sata0 {
+                                marvell,pins = "mpp35";
+                                marvell,function = "sata0";
+                        };
+                        pmx_led_user1o: pmx-led-user1o {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_user1g: pmx-led-user1g {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_user0o: pmx-led-user0o {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_user0g: pmx-led-user0g {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_misc: pmx-led-misc {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_cd: pmx-sdio-cd {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                };
+                i2c@11000 {
+                        status = "okay";
+                        rtc@51 {
+                                compatible = "nxp,pcf8563";
+                                reg = <0x51>;
+                        };
+                        eeprom@57 {
+                                compatible = "atmel,24c02";
+                                reg = <0x57>;
+                        };
+                };
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0000000 0x100000>;
+                        };
+                        partition@100000 {
+                                label = "env";
+                                reg = <0x100000 0x80000>;
+                        };
+                        partition@180000 {
+                                label = "fdt";
+                                reg = <0x180000 0x80000>;
+                        };
+                        partition@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x400000>;
+                        };
+                        partition@600000 {
+                                label = "rootfs";
+                                reg = <0x600000 0x1fa00000>;
+                        };
+                };
+                rtc@10300 {
+                        status = "disabled";
+                };
+                sata@80000 {
+                        nr-ports = <2>;
+                        status = "okay";
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                health {
+                        label = "status:green:health";
+                        gpios = <&gpio0 7 1>;
+                };
+                user1o {
+                        label = "user1:orange";
+                        gpios = <&gpio1 8 1>;
+                        default-state = "on";
+                };
+                user1g {
+                        label = "user1:green";
+                        gpios = <&gpio1 9 1>;
+                        default-state = "on";
+                };
+                user0o {
+                        label = "user0:orange";
+                        gpios = <&gpio1 12 1>;
+                        default-state = "on";
+                };
+                user0g {
+                        label = "user0:green";
+                        gpios = <&gpio1 13 1>;
+                        default-state = "on";
+                };
+                misc {
+                        label = "status:orange:misc";
+                        gpios = <&gpio1 14 1>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
new file mode 100644
index 000000000000..9bc6785ad228
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -0,0 +1,63 @@
+/include/ "kirkwood.dtsi"
+/ {
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <166666667>;
+                        status = "okay";
+                };
+                spi@10600 {
+                        status = "okay";
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "mx25l4005a";
+                                reg = <0>;
+                                spi-max-frequency = <20000000>;
+                                mode = <0>;
+                                partition@0 {
+                                        reg = <0x0 0x80000>;
+                                        label = "u-boot";
+                                };
+                        };
+                };
+                i2c@11000 {
+                        status = "okay";
+                        eeprom@50 {
+                                compatible = "at,24c04";
+                                pagesize = <16>;
+                                reg = <0x50>;
+                        };
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Power push button";
+                        linux,code = <116>;
+                        gpios = <&gpio1 0 0>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                red-fail {
+                        label = "ns2:red:fail";
+                        gpios = <&gpio0 12 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
new file mode 100644
index 000000000000..f2d36ecf36d8
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+/include/ "kirkwood-ns2-common.dtsi"
+/ {
+        model = "LaCie Network Space v2";
+        compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+        ns2-leds {
+                compatible = "lacie,ns2-leds";
+                blue-sata {
+                        label = "ns2:blue:sata";
+                        slow-gpio = <&gpio0 29 0>;
+                        cmd-gpio = <&gpio0 30 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
new file mode 100644
index 000000000000..b02eb4ea1bb4
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+/include/ "kirkwood-ns2-common.dtsi"
+/ {
+        model = "LaCie Network Space Lite v2";
+        compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                blue-sata {
+                        label = "ns2:blue:sata";
+                        gpios = <&gpio0 30 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
new file mode 100644
index 000000000000..bcec4d6cada7
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -0,0 +1,49 @@
+/dts-v1/;
+/include/ "kirkwood-ns2-common.dtsi"
+/ {
+        model = "LaCie Network Space Max v2";
+        compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+        gpio_fan {
+                compatible = "gpio-fan";
+                gpios = <&gpio0 22 1
+                         &gpio0  7 1
+                         &gpio1  1 1
+                         &gpio0 23 1>;
+                gpio-fan,speed-map =
+                        <   0  0
+                         1500 15
+                         1700 14
+                         1800 13
+                         2100 12
+                         3100 11
+                         3300 10
+                         4300  9
+                         5500  8>;
+                alarm-gpios = <&gpio0 25 1>;
+        };
+        ns2-leds {
+                compatible = "lacie,ns2-leds";
+                blue-sata {
+                        label = "ns2:blue:sata";
+                        slow-gpio = <&gpio0 29 0>;
+                        cmd-gpio = <&gpio0 30 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
new file mode 100644
index 000000000000..b79f5eb25589
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -0,0 +1,49 @@
+/dts-v1/;
+/include/ "kirkwood-ns2-common.dtsi"
+/ {
+        model = "LaCie Network Space Mini v2";
+        compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+        gpio_fan {
+                compatible = "gpio-fan";
+                gpios = <&gpio0 22 1
+                         &gpio0  7 1
+                         &gpio1  1 1
+                         &gpio0 23 1>;
+                gpio-fan,speed-map =
+                        <   0  0
+                         3000 15
+                         3180 14
+                         4140 13
+                         4570 12
+                         6760 11
+                         7140 10
+                         7980  9
+                         9200  8>;
+                alarm-gpios = <&gpio0 25 1>;
+        };
+        ns2-leds {
+                compatible = "lacie,ns2-leds";
+                blue-sata {
+                        label = "ns2:blue:sata";
+                        slow-gpio = <&gpio0 29 0>;
+                        cmd-gpio = <&gpio0 30 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
new file mode 100644
index 000000000000..5509f9659546
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -0,0 +1,144 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "ZyXEL NSA310";
+        compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+                i2c@11000 {
+                        status = "okay";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        chip-delay = <35>;
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0000000 0x0100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "uboot_env";
+                                reg = <0x0100000 0x0080000>;
+                        };
+                        partition@180000 {
+                                label = "key_store";
+                                reg = <0x0180000 0x0080000>;
+                        };
+                        partition@200000 {
+                                label = "info";
+                                reg = <0x0200000 0x0080000>;
+                        };
+                        partition@280000 {
+                                label = "etc";
+                                reg = <0x0280000 0x0a00000>;
+                        };
+                        partition@c80000 {
+                                label = "kernel_1";
+                                reg = <0x0c80000 0x0a00000>;
+                        };
+                        partition@1680000 {
+                                label = "rootfs1";
+                                reg = <0x1680000 0x2fc0000>;
+                        };
+                        partition@4640000 {
+                                label = "kernel_2";
+                                reg = <0x4640000 0x0a00000>;
+                        };
+                        partition@5040000 {
+                                label = "rootfs2";
+                                reg = <0x5040000 0x2fc0000>;
+                        };
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Power Button";
+                        linux,code = <116>;
+                        gpios = <&gpio1 14 0>;
+                };
+                button@2 {
+                        label = "Copy Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 5 1>;
+                };
+                button@3 {
+                        label = "Reset Button";
+                        linux,code = <0x198>;
+                        gpios = <&gpio1 4 1>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                green-sys {
+                        label = "nsa310:green:sys";
+                        gpios = <&gpio0 28 0>;
+                };
+                red-sys {
+                        label = "nsa310:red:sys";
+                        gpios = <&gpio0 29 0>;
+                };
+                green-hdd {
+                        label = "nsa310:green:hdd";
+                        gpios = <&gpio1 9 0>;
+                };
+                red-hdd {
+                        label = "nsa310:red:hdd";
+                        gpios = <&gpio1 10 0>;
+                };
+                green-esata {
+                        label = "nsa310:green:esata";
+                        gpios = <&gpio0 12 0>;
+                };
+                red-esata {
+                        label = "nsa310:red:esata";
+                        gpios = <&gpio0 13 0>;
+                };
+                green-usb {
+                        label = "nsa310:green:usb";
+                        gpios = <&gpio0 15 0>;
+                };
+                red-usb {
+                        label = "nsa310:red:usb";
+                        gpios = <&gpio0 16 0>;
+                };
+                green-copy {
+                        label = "nsa310:green:copy";
+                        gpios = <&gpio1 7 0>;
+                };
+                red-copy {
+                        label = "nsa310:red:copy";
+                        gpios = <&gpio1 8 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
new file mode 100644
index 000000000000..49d3d74d4d38
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6282.dtsi"
+/ {
+        model = "Plat'Home OpenBlocksA6";
+        compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                serial@12100 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        chip-delay = <25>;
+                        status = "okay";
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0 0x90000>;
+                        };
+                        partition@90000 {
+                                label = "env";
+                                reg = <0x90000 0x44000>;
+                        };
+                        partition@d4000 {
+                                label = "test";
+                                reg = <0xd4000 0x24000>;
+                        };
+                        partition@f4000 {
+                                label = "conf";
+                                reg = <0xf4000 0x400000>;
+                        };
+                        partition@4f4000 {
+                                label = "linux";
+                                reg = <0x4f4000 0x1d20000>;
+                        };
+                        partition@2214000 {
+                                label = "user";
+                                reg = <0x2214000 0x1dec000>;
+                        };
+                };
+                sata@80000 {
+                        nr-ports = <1>;
+                        status = "okay";
+                };
+                i2c@11100 {
+                        status = "okay";
+                        s35390a: s35390a@30 {
+                                compatible = "s35390a";
+                                reg = <0x30>;
+                        };
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                led-red {
+                        label = "obsa6:red:stat";
+                        gpios = <&gpio1 9 1>;
+                };
+                led-green {
+                        label = "obsa6:green:stat";
+                        gpios = <&gpio1 10 1>;
+                };
+                led-yellow {
+                        label = "obsa6:yellow:stat";
+                        gpios = <&gpio1 11 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
new file mode 100644
index 000000000000..c0de5a7f660d
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "Univeral Scientific Industrial Co. Topkick-1281P2";
+        compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x180000>;
+                        };
+                        partition@180000 {
+                                label = "u-boot env";
+                                reg = <0x0180000 0x20000>;
+                        };
+                        partition@200000 {
+                                label = "uImage";
+                                reg = <0x0200000 0x600000>;
+                        };
+                        partition@800000 {
+                                label = "uInitrd";
+                                reg = <0x0800000 0x1000000>;
+                        };
+                        partition@1800000 {
+                                label = "rootfs";
+                                reg = <0x1800000 0xe800000>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                disk {
+                        label = "topkick:yellow:disk";
+                        gpios = <&gpio0 21 1>;
+                        linux,default-trigger = "ide-disk";
+                };
+                system2 {
+                        label = "topkick:red:system";
+                        gpios = <&gpio1 5 1>;
+                };
+                system {
+                        label = "topkick:blue:system";
+                        gpios = <&gpio1 6 1>;
+                        default-state = "on";
+                };
+                wifi {
+                        label = "topkick:green:wifi";
+                        gpios = <&gpio1 7 1>;
+                };
+                wifi2 {
+                        label = "topkick:yellow:wifi";
+                        gpios = <&gpio1 16 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index ccbf32757800..8295c833887f 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,8 +1,39 @@
 /dts-v1/;
 /include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood-6281.dtsi"
 / {
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
+                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
+                                      &pmx_ram_size &pmx_reset_button
+                                      &pmx_USB_copy_button &pmx_board_id>;
+                        pinctrl-names = "default";
+                        pmx_ram_size: pmx-ram-size {
+                                /* RAM: 0: 256 MB, 1: 512 MB */
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_USB_copy_button: pmx-USB-copy-button {
+                                marvell,pins = "mpp15";
+                                marvell,function = "gpio";
+                        };
+                        pmx_reset_button: pmx-reset-button {
+                                marvell,pins = "mpp16";
+                                marvell,function = "gpio";
+                        };
+                        pmx_board_id: pmx-board-id {
+                                /* 0: TS-11x, 1: TS-21x */
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                };
+        };
        gpio_keys {
                compatible = "gpio-keys";
                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index fbe9932161a1..df3f95dfba33 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,8 +1,39 @@
 /dts-v1/;
 /include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood-6282.dtsi"
 / {
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
+                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
+                                      &pmx_ram_size &pmx_reset_button
+                                      &pmx_USB_copy_button &pmx_board_id>;
+                        pinctrl-names = "default";
+                        pmx_ram_size: pmx-ram-size {
+                                /* RAM: 0: 256 MB, 1: 512 MB */
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_reset_button: pmx-reset-button {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_USB_copy_button: pmx-USB-copy-button {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_board_id: pmx-board-id {
+                                /* 0: TS-11x, 1: TS-21x */
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                };
+        };
        gpio_keys {
                compatible = "gpio-keys";
                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 2388f9936ebf..7735cee4a9c6 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -4,6 +4,10 @@
        compatible = "marvell,kirkwood";
        interrupt-parent = <&intc>;
+        aliases {
+               gpio0 = &gpio0;
+               gpio1 = &gpio1;
+        };
        intc: interrupt-controller {
                compatible = "marvell,orion-intc", "marvell,intc";
                interrupt-controller;
@@ -30,7 +34,8 @@
                        #gpio-cells = <2>;
                        gpio-controller;
                        reg = <0x10100 0x40>;
-                        ngpio = <32>;
+                        ngpios = <32>;
+                        interrupt-controller;
                        interrupts = <35>, <36>, <37>, <38>;
                };
@@ -39,7 +44,8 @@
                        #gpio-cells = <2>;
                        gpio-controller;
                        reg = <0x10140 0x40>;
-                        ngpio = <18>;
+                        ngpios = <18>;
+                        interrupt-controller;
                        interrupts = <39>, <40>, <41>;
                };
@@ -134,6 +140,13 @@
                        };
                };
+                ehci@50000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0x50000 0x1000>;
+                        interrupts = <19>;
+                        status = "okay";
+                };
                sata@80000 {
                        compatible = "marvell,orion-sata";
                        reg = <0x80000 0x5000>;
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index e5ffe960dbf3..1582f484a867 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -182,6 +182,13 @@
                                pnx,timeout = <0x64>;
                        };
+                        mpwm: mpwm@400E8000 {
+                                compatible = "nxp,lpc3220-motor-pwm";
+                                reg = <0x400E8000 0x78>;
+                                status = "disabled";
+                                #pwm-cells = <2>;
+                        };
                        i2cusb: i2c@31020300 {
                                compatible = "nxp,pnx-i2c";
                                reg = <0x31020300 0x100>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 581cb081cb0f..761c4b69b25b 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -12,6 +12,7 @@
 / {
        compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
+        interrupt-parent = <&intc>;
        aliases {
                serial0 = &uart1;
@@ -65,5 +66,90 @@
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
+                timer2: timer@4802a000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4802a000 0x400>;
+                        interrupts = <38>;
+                        ti,hwmods = "timer2";
+                };
+                timer3: timer@48078000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48078000 0x400>;
+                        interrupts = <39>;
+                        ti,hwmods = "timer3";
+                };
+                timer4: timer@4807a000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4807a000 0x400>;
+                        interrupts = <40>;
+                        ti,hwmods = "timer4";
+                };
+                timer5: timer@4807c000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4807c000 0x400>;
+                        interrupts = <41>;
+                        ti,hwmods = "timer5";
+                        ti,timer-dsp;
+                };
+                timer6: timer@4807e000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4807e000 0x400>;
+                        interrupts = <42>;
+                        ti,hwmods = "timer6";
+                        ti,timer-dsp;
+                };
+                timer7: timer@48080000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48080000 0x400>;
+                        interrupts = <43>;
+                        ti,hwmods = "timer7";
+                        ti,timer-dsp;
+                };
+                timer8: timer@48082000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48082000 0x400>;
+                        interrupts = <44>;
+                        ti,hwmods = "timer8";
+                        ti,timer-dsp;
+                };
+                timer9: timer@48084000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48084000 0x400>;
+                        interrupts = <45>;
+                        ti,hwmods = "timer9";
+                        ti,timer-pwm;
+                };
+                timer10: timer@48086000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48086000 0x400>;
+                        interrupts = <46>;
+                        ti,hwmods = "timer10";
+                        ti,timer-pwm;
+                };
+                timer11: timer@48088000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48088000 0x400>;
+                        interrupts = <47>;
+                        ti,hwmods = "timer11";
+                        ti,timer-pwm;
+                };
+                timer12: timer@4808a000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4808a000 0x400>;
+                        interrupts = <48>;
+                        ti,hwmods = "timer12";
+                        ti,timer-pwm;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index bfd76b4a0ddc..af6560908905 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,6 +14,12 @@
        compatible = "ti,omap2420", "ti,omap2";
        ocp {
+                counter32k: counter@48004000 {
+                        compatible = "ti,omap-counter32k";
+                        reg = <0x48004000 0x20>;
+                        ti,hwmods = "counter_32k";
+                };
                omap2420_pmx: pinmux@48000030 {
                        compatible = "ti,omap2420-padconf", "pinctrl-single";
                        reg = <0x48000030 0x0113>;
@@ -30,7 +36,6 @@
                        interrupts = <59>, /* TX interrupt */
                                     <60>; /* RX interrupt */
                        interrupt-names = "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,hwmods = "mcbsp1";
                };
@@ -41,8 +46,15 @@
                        interrupts = <62>, /* TX interrupt */
                                     <63>; /* RX interrupt */
                        interrupt-names = "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,hwmods = "mcbsp2";
                };
+                timer1: timer@48028000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48028000 0x400>;
+                        interrupts = <37>;
+                        ti,hwmods = "timer1";
+                        ti,timer-alwon;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 4565d9750f4d..c3924457c9b6 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,6 +14,12 @@
        compatible = "ti,omap2430", "ti,omap2";
        ocp {
+                counter32k: counter@49020000 {
+                        compatible = "ti,omap-counter32k";
+                        reg = <0x49020000 0x20>;
+                        ti,hwmods = "counter_32k";
+                };
                omap2430_pmx: pinmux@49002030 {
                        compatible = "ti,omap2430-padconf", "pinctrl-single";
                        reg = <0x49002030 0x0154>;
@@ -32,7 +38,6 @@
                                     <60>, /* RX interrupt */
                                     <61>; /* RX overflow interrupt */
                        interrupt-names = "common", "tx", "rx", "rx_overflow";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp1";
                };
@@ -45,7 +50,6 @@
                                     <62>, /* TX interrupt */
                                     <63>; /* RX interrupt */
                        interrupt-names = "common", "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp2";
                };
@@ -58,7 +62,6 @@
                                     <89>, /* TX interrupt */
                                     <90>; /* RX interrupt */
                        interrupt-names = "common", "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp3";
                };
@@ -71,7 +74,6 @@
                                     <54>, /* TX interrupt */
                                     <55>; /* RX interrupt */
                        interrupt-names = "common", "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp4";
                };
@@ -84,9 +86,16 @@
                                     <81>, /* TX interrupt */
                                     <82>; /* RX interrupt */
                        interrupt-names = "common", "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp5";
                };
+                timer1: timer@49018000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x49018000 0x400>;
+                        interrupts = <37>;
+                        ti,hwmods = "timer1";
+                        ti,timer-alwon;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index c38cf76df81f..3705a81c1fc2 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -55,12 +55,6 @@
                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                interrupt-parent = <&intc>;
-                vsim: regulator-vsim {
-                        compatible = "ti,twl4030-vsim";
-                        regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <3000000>;
-                };
                twl_audio: audio {
                        compatible = "ti,twl4030-audio";
                        codec {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
new file mode 100644
index 000000000000..f624dc85d441
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+/include/ "omap3.dtsi"
+/ {
+        model = "TI OMAP3 BeagleBoard";
+        compatible = "ti,omap3-beagle", "ti,omap3";
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+        leds {
+                compatible = "gpio-leds";
+                pmu_stat {
+                        label = "beagleboard::pmu_stat";
+                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                };
+                heartbeat {
+                        label = "beagleboard::usr0";
+                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        linux,default-trigger = "heartbeat";
+                };
+                mmc {
+                        label = "beagleboard::usr1";
+                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        linux,default-trigger = "mmc0";
+                };
+        };
+};
+&i2c1 {
+        clock-frequency = <2600000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+/include/ "twl4030.dtsi"
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        vmmc_aux-supply = <&vsim>;
+        bus-width = <8>;
+};
+&mmc2 {
+        status = "disabled";
+};
+&mmc3 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 696e929d0304..1acc26148ffc 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -12,6 +12,7 @@
 / {
        compatible = "ti,omap3430", "ti,omap3";
+        interrupt-parent = <&intc>;
        aliases {
                serial0 = &uart1;
@@ -60,6 +61,12 @@
                ranges;
                ti,hwmods = "l3_main";
+                counter32k: counter@48320000 {
+                        compatible = "ti,omap-counter32k";
+                        reg = <0x48320000 0x20>;
+                        ti,hwmods = "counter_32k";
+                };
                intc: interrupt-controller@48200000 {
                        compatible = "ti,omap2-intc";
                        interrupt-controller;
@@ -240,7 +247,6 @@
                                     <59>, /* TX interrupt */
                                     <60>; /* RX interrupt */
                        interrupt-names = "common", "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp1";
                };
@@ -255,7 +261,6 @@
                                     <63>, /* RX interrupt */
                                     <4>;  /* Sidetone */
                        interrupt-names = "common", "tx", "rx", "sidetone";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <1280>;
                        ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
                };
@@ -270,7 +275,6 @@
                                     <90>, /* RX interrupt */
                                     <5>;  /* Sidetone */
                        interrupt-names = "common", "tx", "rx", "sidetone";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
                };
@@ -283,7 +287,6 @@
                                     <54>, /* TX interrupt */
                                     <55>; /* RX interrupt */
                        interrupt-names = "common", "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp4";
                };
@@ -296,9 +299,103 @@
                                     <81>, /* TX interrupt */
                                     <82>; /* RX interrupt */
                        interrupt-names = "common", "tx", "rx";
-                        interrupt-parent = <&intc>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp5";
                };
+                timer1: timer@48318000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48318000 0x400>;
+                        interrupts = <37>;
+                        ti,hwmods = "timer1";
+                        ti,timer-alwon;
+                };
+                timer2: timer@49032000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x49032000 0x400>;
+                        interrupts = <38>;
+                        ti,hwmods = "timer2";
+                };
+                timer3: timer@49034000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x49034000 0x400>;
+                        interrupts = <39>;
+                        ti,hwmods = "timer3";
+                };
+                timer4: timer@49036000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x49036000 0x400>;
+                        interrupts = <40>;
+                        ti,hwmods = "timer4";
+                };
+                timer5: timer@49038000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x49038000 0x400>;
+                        interrupts = <41>;
+                        ti,hwmods = "timer5";
+                        ti,timer-dsp;
+                };
+                timer6: timer@4903a000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4903a000 0x400>;
+                        interrupts = <42>;
+                        ti,hwmods = "timer6";
+                        ti,timer-dsp;
+                };
+                timer7: timer@4903c000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4903c000 0x400>;
+                        interrupts = <43>;
+                        ti,hwmods = "timer7";
+                        ti,timer-dsp;
+                };
+                timer8: timer@4903e000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4903e000 0x400>;
+                        interrupts = <44>;
+                        ti,hwmods = "timer8";
+                        ti,timer-pwm;
+                        ti,timer-dsp;
+                };
+                timer9: timer@49040000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x49040000 0x400>;
+                        interrupts = <45>;
+                        ti,hwmods = "timer9";
+                        ti,timer-pwm;
+                };
+                timer10: timer@48086000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48086000 0x400>;
+                        interrupts = <46>;
+                        ti,hwmods = "timer10";
+                        ti,timer-pwm;
+                };
+                timer11: timer@48088000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48088000 0x400>;
+                        interrupts = <47>;
+                        ti,hwmods = "timer11";
+                        ti,timer-pwm;
+                };
+                timer12: timer@48304000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48304000 0x400>;
+                        interrupts = <95>;
+                        ti,hwmods = "timer12";
+                        ti,timer-alwon;
+                        ti,timer-secure;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
new file mode 100644
index 000000000000..75466d2abfb5
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/include/ "omap4-panda.dts"
+/* Pandaboard Rev A4+ have external pullups on SCL & SDA */
+&dss_hdmi_pins {
+        pinctrl-single,pins = <
+                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
+                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                >;
+};
diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index d4ba43a48d9b..73bc1a67e444 100644
--- a/arch/arm/boot/dts/omap4-pandaES.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -22,3 +22,12 @@
                "AFML", "Line In",
                "AFMR", "Line In";
 };
+/* PandaboardES has external pullups on SCL & SDA */
+&dss_hdmi_pins {
+        pinctrl-single,pins = <
+                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
+                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                >;
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index e8f927cbb376..4122efe31cfd 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -65,6 +65,8 @@
                        &twl6040_pins
                        &mcpdm_pins
                        &mcbsp1_pins
+                        &dss_hdmi_pins
+                        &tpd12s015_pins
        >;
        twl6040_pins: pinmux_twl6040_pins {
@@ -92,6 +94,22 @@
                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
                >;
        };
+        dss_hdmi_pins: pinmux_dss_hdmi_pins {
+                pinctrl-single,pins = <
+                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
+                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                >;
+        };
+        tpd12s015_pins: pinmux_tpd12s015_pins {
+                pinctrl-single,pins = <
+                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
+                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
+                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                >;
+        };
 };
 &i2c1 {
@@ -184,3 +202,7 @@
 &dmic {
        status = "disabled";
 };
+&twl_usb_comparator {
+        usb-supply = <&vusb>;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
new file mode 100644
index 000000000000..b4a40ffbce31
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/include/ "omap4-sdp.dts"
+/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
+&dss_hdmi_pins {
+        pinctrl-single,pins = <
+                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
+                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                >;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 5b7e04fbff50..43e5258a9372 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -124,6 +124,8 @@
                        &dmic_pins
                        &mcbsp1_pins
                        &mcbsp2_pins
+                        &dss_hdmi_pins
+                        &tpd12s015_pins
        >;
        uart2_pins: pinmux_uart2_pins {
@@ -194,6 +196,22 @@
                        0xbc 0x100      /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
                >;
        };
+        dss_hdmi_pins: pinmux_dss_hdmi_pins {
+                pinctrl-single,pins = <
+                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
+                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
+                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                >;
+        };
+        tpd12s015_pins: pinmux_tpd12s015_pins {
+                pinctrl-single,pins = <
+                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
+                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
+                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                >;
+        };
 };
 &i2c1 {
@@ -406,3 +424,7 @@
 &mcbsp3 {
        status = "disabled";
 };
+&twl_usb_comparator {
+        usb-supply = <&vusb>;
+};
diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6601e6af6092..6601e6af6092 100644
--- a/arch/arm/boot/dts/omap4-var_som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3883f94fdbd0..739bb79e410e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -95,6 +95,12 @@
                ranges;
                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+                counter32k: counter@4a304000 {
+                        compatible = "ti,omap-counter32k";
+                        reg = <0x4a304000 0x20>;
+                        ti,hwmods = "counter_32k";
+                };
                omap4_pmx_core: pinmux@4a100040 {
                        compatible = "ti,omap4-padconf", "pinctrl-single";
                        reg = <0x4a100040 0x0196>;
@@ -340,7 +346,6 @@
                              <0x49032000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
                        interrupts = <0 112 0x4>;
-                        interrupt-parent = <&gic>;
                        ti,hwmods = "mcpdm";
                };
@@ -350,7 +355,6 @@
                              <0x4902e000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
                        interrupts = <0 114 0x4>;
-                        interrupt-parent = <&gic>;
                        ti,hwmods = "dmic";
                };
@@ -361,7 +365,6 @@
                        reg-names = "mpu", "dma";
                        interrupts = <0 17 0x4>;
                        interrupt-names = "common";
-                        interrupt-parent = <&gic>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp1";
                };
@@ -373,7 +376,6 @@
                        reg-names = "mpu", "dma";
                        interrupts = <0 22 0x4>;
                        interrupt-names = "common";
-                        interrupt-parent = <&gic>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp2";
                };
@@ -385,7 +387,6 @@
                        reg-names = "mpu", "dma";
                        interrupts = <0 23 0x4>;
                        interrupt-names = "common";
-                        interrupt-parent = <&gic>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp3";
                };
@@ -396,7 +397,6 @@
                        reg-names = "mpu";
                        interrupts = <0 16 0x4>;
                        interrupt-names = "common";
-                        interrupt-parent = <&gic>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp4";
                };
@@ -431,12 +431,103 @@
                        hw-caps-temp-alert;
                };
-                ocp2scp {
+                ocp2scp@4a0ad000 {
                        compatible = "ti,omap-ocp2scp";
+                        reg = <0x4a0ad000 0x1f>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
                        ti,hwmods = "ocp2scp_usb_phy";
                };
+                timer1: timer@4a318000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4a318000 0x80>;
+                        interrupts = <0 37 0x4>;
+                        ti,hwmods = "timer1";
+                        ti,timer-alwon;
+                };
+                timer2: timer@48032000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48032000 0x80>;
+                        interrupts = <0 38 0x4>;
+                        ti,hwmods = "timer2";
+                };
+                timer3: timer@48034000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48034000 0x80>;
+                        interrupts = <0 39 0x4>;
+                        ti,hwmods = "timer3";
+                };
+                timer4: timer@48036000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48036000 0x80>;
+                        interrupts = <0 40 0x4>;
+                        ti,hwmods = "timer4";
+                };
+                timer5: timer@40138000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x40138000 0x80>,
+                              <0x49038000 0x80>;
+                        interrupts = <0 41 0x4>;
+                        ti,hwmods = "timer5";
+                        ti,timer-dsp;
+                };
+                timer6: timer@4013a000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4013a000 0x80>,
+                              <0x4903a000 0x80>;
+                        interrupts = <0 42 0x4>;
+                        ti,hwmods = "timer6";
+                        ti,timer-dsp;
+                };
+                timer7: timer@4013c000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4013c000 0x80>,
+                              <0x4903c000 0x80>;
+                        interrupts = <0 43 0x4>;
+                        ti,hwmods = "timer7";
+                        ti,timer-dsp;
+                };
+                timer8: timer@4013e000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4013e000 0x80>,
+                              <0x4903e000 0x80>;
+                        interrupts = <0 44 0x4>;
+                        ti,hwmods = "timer8";
+                        ti,timer-pwm;
+                        ti,timer-dsp;
+                };
+                timer9: timer@4803e000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4803e000 0x80>;
+                        interrupts = <0 45 0x4>;
+                        ti,hwmods = "timer9";
+                        ti,timer-pwm;
+                };
+                timer10: timer@48086000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48086000 0x80>;
+                        interrupts = <0 46 0x4>;
+                        ti,hwmods = "timer10";
+                        ti,timer-pwm;
+                };
+                timer11: timer@48088000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48088000 0x80>;
+                        interrupts = <0 47 0x4>;
+                        ti,hwmods = "timer11";
+                        ti,timer-pwm;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index c663eba73168..8722c15bbba2 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 /include/ "omap5.dtsi"
+/include/ "samsung_k3pe0e000b.dtsi"
 / {
        model = "TI OMAP5 EVM board";
@@ -15,7 +16,7 @@
        memory {
                device_type = "memory";
-                reg = <0x80000000 0x40000000>; /* 1 GB */
+                reg = <0x80000000 0x80000000>; /* 2 GB */
        };
        vmmcsd_fixed: fixedregulator-mmcsd {
@@ -140,3 +141,13 @@
 &mcbsp3 {
        status = "disabled";
 };
+&emif1 {
+        cs1-used;
+        device-handle = <&samsung_K3PE0E000B>;
+};
+&emif2 {
+        cs1-used;
+        device-handle = <&samsung_K3PE0E000B>;
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 42c78beb4fdc..790bb2a4b343 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -77,6 +77,12 @@
                ranges;
                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+                counter32k: counter@4ae04000 {
+                        compatible = "ti,omap-counter32k";
+                        reg = <0x4ae04000 0x40>;
+                        ti,hwmods = "counter_32k";
+                };
                omap5_pmx_core: pinmux@4a002840 {
                        compatible = "ti,omap4-padconf", "pinctrl-single";
                        reg = <0x4a002840 0x01b6>;
@@ -104,6 +110,8 @@
                gpio1: gpio@4ae10000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x4ae10000 0x200>;
+                        interrupts = <0 29 0x4>;
                        ti,hwmods = "gpio1";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -113,6 +121,8 @@
                gpio2: gpio@48055000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48055000 0x200>;
+                        interrupts = <0 30 0x4>;
                        ti,hwmods = "gpio2";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -122,6 +132,8 @@
                gpio3: gpio@48057000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48057000 0x200>;
+                        interrupts = <0 31 0x4>;
                        ti,hwmods = "gpio3";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -131,6 +143,8 @@
                gpio4: gpio@48059000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48059000 0x200>;
+                        interrupts = <0 32 0x4>;
                        ti,hwmods = "gpio4";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -140,6 +154,8 @@
                gpio5: gpio@4805b000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x4805b000 0x200>;
+                        interrupts = <0 33 0x4>;
                        ti,hwmods = "gpio5";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -149,6 +165,8 @@
                gpio6: gpio@4805d000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x4805d000 0x200>;
+                        interrupts = <0 34 0x4>;
                        ti,hwmods = "gpio6";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -158,6 +176,8 @@
                gpio7: gpio@48051000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48051000 0x200>;
+                        interrupts = <0 35 0x4>;
                        ti,hwmods = "gpio7";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -167,6 +187,8 @@
                gpio8: gpio@48053000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48053000 0x200>;
+                        interrupts = <0 121 0x4>;
                        ti,hwmods = "gpio8";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -176,6 +198,8 @@
                i2c1: i2c@48070000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x48070000 0x100>;
+                        interrupts = <0 56 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c1";
@@ -183,6 +207,8 @@
                i2c2: i2c@48072000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x48072000 0x100>;
+                        interrupts = <0 57 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c2";
@@ -190,20 +216,26 @@
                i2c3: i2c@48060000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x48060000 0x100>;
+                        interrupts = <0 61 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c3";
                };
-                i2c4: i2c@4807A000 {
+                i2c4: i2c@4807a000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x4807a000 0x100>;
+                        interrupts = <0 62 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c4";
                };
-                i2c5: i2c@4807C000 {
+                i2c5: i2c@4807c000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x4807c000 0x100>;
+                        interrupts = <0 60 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c5";
@@ -211,42 +243,56 @@
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x4806a000 0x100>;
+                        interrupts = <0 72 0x4>;
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                };
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x4806c000 0x100>;
+                        interrupts = <0 73 0x4>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x48020000 0x100>;
+                        interrupts = <0 74 0x4>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x4806e000 0x100>;
+                        interrupts = <0 70 0x4>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
                uart5: serial@48066000 {
-                        compatible = "ti,omap5-uart";
+                        compatible = "ti,omap4-uart";
+                        reg = <0x48066000 0x100>;
+                        interrupts = <0 105 0x4>;
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
                };
                uart6: serial@48068000 {
-                        compatible = "ti,omap6-uart";
+                        compatible = "ti,omap4-uart";
+                        reg = <0x48068000 0x100>;
+                        interrupts = <0 106 0x4>;
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                };
                mmc1: mmc@4809c000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x4809c000 0x400>;
+                        interrupts = <0 83 0x4>;
                        ti,hwmods = "mmc1";
                        ti,dual-volt;
                        ti,needs-special-reset;
@@ -254,24 +300,32 @@
                mmc2: mmc@480b4000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480b4000 0x400>;
+                        interrupts = <0 86 0x4>;
                        ti,hwmods = "mmc2";
                        ti,needs-special-reset;
                };
                mmc3: mmc@480ad000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480ad000 0x400>;
+                        interrupts = <0 94 0x4>;
                        ti,hwmods = "mmc3";
                        ti,needs-special-reset;
                };
                mmc4: mmc@480d1000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d1000 0x400>;
+                        interrupts = <0 96 0x4>;
                        ti,hwmods = "mmc4";
                        ti,needs-special-reset;
                };
                mmc5: mmc@480d5000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d5000 0x400>;
+                        interrupts = <0 59 0x4>;
                        ti,hwmods = "mmc5";
                        ti,needs-special-reset;
                };
@@ -287,7 +341,6 @@
                              <0x49032000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
                        interrupts = <0 112 0x4>;
-                        interrupt-parent = <&gic>;
                        ti,hwmods = "mcpdm";
                };
@@ -297,7 +350,6 @@
                              <0x4902e000 0x7f>; /* L3 Interconnect */
                        reg-names = "mpu", "dma";
                        interrupts = <0 114 0x4>;
-                        interrupt-parent = <&gic>;
                        ti,hwmods = "dmic";
                };
@@ -308,7 +360,6 @@
                        reg-names = "mpu", "dma";
                        interrupts = <0 17 0x4>;
                        interrupt-names = "common";
-                        interrupt-parent = <&gic>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp1";
                };
@@ -320,7 +371,6 @@
                        reg-names = "mpu", "dma";
                        interrupts = <0 22 0x4>;
                        interrupt-names = "common";
-                        interrupt-parent = <&gic>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp2";
                };
@@ -332,9 +382,119 @@
                        reg-names = "mpu", "dma";
                        interrupts = <0 23 0x4>;
                        interrupt-names = "common";
-                        interrupt-parent = <&gic>;
                        ti,buffer-size = <128>;
                        ti,hwmods = "mcbsp3";
                };
+                timer1: timer@4ae18000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4ae18000 0x80>;
+                        interrupts = <0 37 0x4>;
+                        ti,hwmods = "timer1";
+                        ti,timer-alwon;
+                };
+                timer2: timer@48032000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48032000 0x80>;
+                        interrupts = <0 38 0x4>;
+                        ti,hwmods = "timer2";
+                };
+                timer3: timer@48034000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48034000 0x80>;
+                        interrupts = <0 39 0x4>;
+                        ti,hwmods = "timer3";
+                };
+                timer4: timer@48036000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48036000 0x80>;
+                        interrupts = <0 40 0x4>;
+                        ti,hwmods = "timer4";
+                };
+                timer5: timer@40138000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x40138000 0x80>,
+                              <0x49038000 0x80>;
+                        interrupts = <0 41 0x4>;
+                        ti,hwmods = "timer5";
+                        ti,timer-dsp;
+                };
+                timer6: timer@4013a000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4013a000 0x80>,
+                              <0x4903a000 0x80>;
+                        interrupts = <0 42 0x4>;
+                        ti,hwmods = "timer6";
+                        ti,timer-dsp;
+                        ti,timer-pwm;
+                };
+                timer7: timer@4013c000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4013c000 0x80>,
+                              <0x4903c000 0x80>;
+                        interrupts = <0 43 0x4>;
+                        ti,hwmods = "timer7";
+                        ti,timer-dsp;
+                };
+                timer8: timer@4013e000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4013e000 0x80>,
+                              <0x4903e000 0x80>;
+                        interrupts = <0 44 0x4>;
+                        ti,hwmods = "timer8";
+                        ti,timer-dsp;
+                        ti,timer-pwm;
+                };
+                timer9: timer@4803e000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x4803e000 0x80>;
+                        interrupts = <0 45 0x4>;
+                        ti,hwmods = "timer9";
+                };
+                timer10: timer@48086000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48086000 0x80>;
+                        interrupts = <0 46 0x4>;
+                        ti,hwmods = "timer10";
+                };
+                timer11: timer@48088000 {
+                        compatible = "ti,omap2-timer";
+                        reg = <0x48088000 0x80>;
+                        interrupts = <0 47 0x4>;
+                        ti,hwmods = "timer11";
+                        ti,timer-pwm;
+                };
+                emif1: emif@0x4c000000 {
+                        compatible      = "ti,emif-4d5";
+                        ti,hwmods       = "emif1";
+                        phy-type        = <2>; /* DDR PHY type: Intelli PHY */
+                        reg = <0x4c000000 0x400>;
+                        interrupts = <0 110 0x4>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
+                emif2: emif@0x4d000000 {
+                        compatible      = "ti,emif-4d5";
+                        ti,hwmods       = "emif2";
+                        phy-type        = <2>; /* DDR PHY type: Intelli PHY */
+                        reg = <0x4d000000 0x400>;
+                        interrupts = <0 111 0x4>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
new file mode 100644
index 000000000000..5a3a58b7e18f
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "orion5x.dtsi"
+/ {
+        model = "LaCie Ethernet Disk mini V2";
+        compatible = "lacie,ethernet-disk-mini-v2", "marvell-orion5x-88f5182", "marvell,orion5x";
+        memory {
+                reg = <0x00000000 0x4000000>; /* 64 MB */
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <166666667>;
+                        status = "okay";
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Power-on Switch";
+                        linux,code = <116>; /* KEY_POWER */
+                        gpios = <&gpio0 18 0>;
+                };
+        };
+        gpio_leds {
+                compatible = "gpio-leds";
+                led@1 {
+                        label = "power:blue";
+                        gpios = <&gpio0 16 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
new file mode 100644
index 000000000000..8aad00f81ed9
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Marvell Orion5x SoC";
+        compatible = "marvell,orion5x";
+        interrupt-parent = <&intc>;
+        intc: interrupt-controller {
+                compatible = "marvell,orion-intc", "marvell,intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xf1020204 0x04>;
+        };
+        ocp@f1000000 {
+                compatible = "simple-bus";
+                ranges = <0x00000000 0xf1000000 0x4000000
+                          0xf2200000 0xf2200000 0x0000800>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                gpio0: gpio@10100 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0x10100 0x40>;
+                        ngpio = <32>;
+                        interrupts = <6>, <7>, <8>, <9>;
+                };
+                serial@12000 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <3>;
+                        /* set clock-frequency in board dts */
+                        status = "disabled";
+                };
+                serial@12100 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <4>;
+                        /* set clock-frequency in board dts */
+                        status = "disabled";
+                };
+                spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+                wdt@20300 {
+                        compatible = "marvell,orion-wdt";
+                        reg = <0x20300 0x28>;
+                        status = "okay";
+                };
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+                i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <5>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+                crypto@90000 {
+                        compatible = "marvell,orion-crypto";
+                        reg = <0x90000 0x10000>,
+                              <0xf2200000 0x800>;
+                        reg-names = "regs", "sram";
+                        interrupts = <22>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
new file mode 100644
index 000000000000..387fedb58988
--- /dev/null
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -0,0 +1,165 @@
+/*
+ * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g45.dtsi"
+/ {
+        model = "Ronetix pm9g45";
+        compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                reg = <0x70000000 0x8000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_board_nand: nand0-board {
+                                                atmel,pins =
+                                                        <3 3 0x0 0x1    /* PD3 gpio RDY pin pull_up*/
+                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                        };
+                                };
+                                mmc {
+                                        pinctrl_board_mmc: mmc0-board {
+                                                atmel,pins =
+                                                        <3 6 0x0 0x5>;  /* PD6 gpio CD pin pull_up and deglitch */
+                                        };
+                                };
+                        };
+                        mmc0: mmc@fff80000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 6 0>;
+                                };
+                        };
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        pinctrl-0 = <&pinctrl_board_nand>;
+                        gpios = <&pioD 3 0
+                                 &pioC 14 0
+                                 0
+                                >;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x1A0000>;
+                        };
+                        kernel@200000 {
+                                label = "bareboxenv2";
+                                reg = <0x200000 0x300000>;
+                        };
+                        kernel@500000 {
+                                label = "root";
+                                reg = <0x500000 0x400000>;
+                        };
+                        data@900000 {
+                                label = "data";
+                                reg = <0x900000 0x8340000>;
+                        };
+                };
+                usb0: ohci@00700000 {
+                        status = "okay";
+                        num-ports = <2>;
+                };
+                usb1: ehci@00800000 {
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                led0 {
+                        label = "led0";
+                        gpios = <&pioD 0 1>;
+                        linux,default-trigger = "nand-disk";
+                };
+                led1 {
+                        label = "led1";
+                        gpios = <&pioD 31 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                right {
+                        label = "SW4";
+                        gpios = <&pioE 7 1>;
+                        linux,code = <106>;
+                };
+                up {
+                        label = "SW3";
+                        gpios = <&pioE 8 1>;
+                        linux,code = <103>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
new file mode 100644
index 000000000000..9657a5cbc3ad
--- /dev/null
+++ b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Timings and Geometry for Samsung K3PE0E000B memory part
+ */
+/ {
+        samsung_K3PE0E000B: lpddr2 {
+                compatible      = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
+                density         = <4096>;
+                io-width        = <32>;
+                tRPab-min-tck   = <3>;
+                tRCD-min-tck    = <3>;
+                tWR-min-tck     = <3>;
+                tRASmin-min-tck = <3>;
+                tRRD-min-tck    = <2>;
+                tWTR-min-tck    = <2>;
+                tXP-min-tck     = <2>;
+                tRTP-min-tck    = <2>;
+                tCKE-min-tck    = <3>;
+                tCKESR-min-tck  = <3>;
+                tFAW-min-tck    = <8>;
+                timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <533333333>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <7500>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+                timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <266666666>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <7500>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sh7377.dtsi b/arch/arm/boot/dts/sh7372-mackerel.dts
index 767ee0796daa..286f0caef013 100644
--- a/arch/arm/boot/dts/sh7377.dtsi
+++ b/arch/arm/boot/dts/sh7372-mackerel.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the sh7377 SoC
+ * Device Tree Source for the mackerel board
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
@@ -8,14 +8,15 @@
 * kind, whether express or implied.
 */
+/dts-v1/;
 /include/ "skeleton.dtsi"
 / {
-        compatible = "renesas,sh7377";
+        model = "Mackerel (AP4 EVM 2nd)";
+        compatible = "renesas,mackerel";
-        cpus {
+        memory {
-                cpu@0 {
+                device_type = "memory";
-                        compatible = "arm,cortex-a8";
+                reg = <0x40000000 0x10000000>;
-                };
        };
 };
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 702c0baa6004..27f31a5fa494 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -14,7 +14,7 @@
 / {
        model = "Calao Systems Snowball platform with device tree";
-        compatible = "calaosystems,snowball-a9500";
+        compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
        memory {
                reg = <0x00000000 0x20000000>;
@@ -99,6 +99,33 @@
                        status = "okay";
                };
+                prcmu@80157000 {
+                        thermal@801573c0 {
+                                num-trips = <4>;
+                                trip0-temp = <70000>;
+                                trip0-type = "active";
+                                trip0-cdev-num = <1>;
+                                trip0-cdev-name0 = "thermal-cpufreq-0";
+                                trip1-temp = <75000>;
+                                trip1-type = "active";
+                                trip1-cdev-num = <1>;
+                                trip1-cdev-name0 = "thermal-cpufreq-0";
+                                trip2-temp = <80000>;
+                                trip2-type = "active";
+                                trip2-cdev-num = <1>;
+                                trip2-cdev-name0 = "thermal-cpufreq-0";
+                                trip3-temp = <85000>;
+                                trip3-type = "critical";
+                                trip3-cdev-num = <0>;
+                                status = "okay";
+                         };
+                };
                external-bus@50000000 {
                        status = "okay";
@@ -120,10 +147,10 @@
                };
                // External Micro SD slot
-                sdi@80126000 {
+                sdi0_per1@80126000 {
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <50000000>;
-                        bus-width = <8>;
+                        bus-width = <4>;
                        mmc-cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
@@ -134,7 +161,7 @@
                };
                // On-board eMMC
-                sdi@80114000 {
+                sdi4_per2@80114000 {
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <50000000>;
                        bus-width = <8>;
@@ -183,5 +210,141 @@
                                reg = <0x33>;
                        };
                };
+                cpufreq-cooling {
+                        status = "okay";
+                };
+                prcmu@80157000 {
+                        db8500-prcmu-regulators {
+                                db8500_vape_reg: db8500_vape {
+                                        regulator-name = "db8500-vape";
+                                };
+                                db8500_varm_reg: db8500_varm {
+                                        regulator-name = "db8500-varm";
+                                };
+                                db8500_vmodem_reg: db8500_vmodem {
+                                        regulator-name = "db8500-vmodem";
+                                };
+                                db8500_vpll_reg: db8500_vpll {
+                                        regulator-name = "db8500-vpll";
+                                };
+                                db8500_vsmps1_reg: db8500_vsmps1 {
+                                        regulator-name = "db8500-vsmps1";
+                                };
+                                db8500_vsmps2_reg: db8500_vsmps2 {
+                                        regulator-name = "db8500-vsmps2";
+                                };
+                                db8500_vsmps3_reg: db8500_vsmps3 {
+                                        regulator-name = "db8500-vsmps3";
+                                };
+                                db8500_vrf1_reg: db8500_vrf1 {
+                                        regulator-name = "db8500-vrf1";
+                                };
+                                db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
+                                        regulator-name = "db8500-sva-mmdsp";
+                                };
+                                db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
+                                        regulator-name = "db8500-sva-mmdsp-ret";
+                                };
+                                db8500_sva_pipe_reg: db8500_sva_pipe {
+                                        regulator-name = "db8500_sva_pipe";
+                                };
+                                db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
+                                        regulator-name = "db8500_sia_mmdsp";
+                                };
+                                db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
+                                        regulator-name = "db8500-sia-mmdsp-ret";
+                                };
+                                db8500_sia_pipe_reg: db8500_sia_pipe {
+                                        regulator-name = "db8500-sia-pipe";
+                                };
+                                db8500_sga_reg: db8500_sga {
+                                        regulator-name = "db8500-sga";
+                                };
+                                db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
+                                        regulator-name = "db8500-b2r2-mcde";
+                                };
+                                db8500_esram12_reg: db8500_esram12 {
+                                        regulator-name = "db8500-esram12";
+                                };
+                                db8500_esram12_ret_reg: db8500_esram12_ret {
+                                        regulator-name = "db8500-esram12-ret";
+                                };
+                                db8500_esram34_reg: db8500_esram34 {
+                                        regulator-name = "db8500-esram34";
+                                };
+                                db8500_esram34_ret_reg: db8500_esram34_ret {
+                                        regulator-name = "db8500-esram34-ret";
+                                };
+                        };
+                        ab8500@5 {
+                                ab8500-regulators {
+                                        ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+                                                regulator-name = "V-DISPLAY";
+                                        };
+                                        ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+                                                regulator-name = "V-eMMC1";
+                                        };
+                                        ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+                                                regulator-name = "V-MMC-SD";
+                                        };
+                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                                regulator-name = "V-INTCORE";
+                                        };
+                                        ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+                                                regulator-name = "V-TVOUT";
+                                        };
+                                        ab8500_ldo_usb_reg: ab8500_ldo_usb {
+                                                regulator-name = "dummy";
+                                        };
+                                        ab8500_ldo_audio_reg: ab8500_ldo_audio {
+                                                regulator-name = "V-AUD";
+                                        };
+                                        ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+                                                regulator-name = "V-AMIC1";
+                                        };
+                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                                regulator-name = "V-AMIC2";
+                                        };
+                                        ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+                                                regulator-name = "V-DMIC";
+                                        };
+                                        ab8500_ldo_ana_reg: ab8500_ldo_ana {
+                                                regulator-name = "V-CSI/DSI";
+                                        };
+                                };
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0772f5739f59..19aec421bb26 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -143,5 +143,15 @@
                        reg-shift = <2>;
                        reg-io-width = <4>;
                };
+                rstmgr@ffd05000 {
+                                compatible = "altr,rst-mgr";
+                                reg = <0xffd05000 0x1000>;
+                        };
+                sysmgr@ffd08000 {
+                                compatible = "altr,sys-mgr";
+                                reg = <0xffd08000 0x4000>;
+                        };
        };
 };
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index dd4358bc26e2..b56a801e42a2 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -30,10 +30,14 @@
                        pinctrl-0 = <&state_default>;
                        state_default: pinmux {
-                                i2c0-pmx {
+                                i2c0 {
                                        st,pins = "i2c0_grp";
                                        st,function = "i2c0";
                                };
+                                i2s0 {
+                                        st,pins = "i2s0_grp";
+                                        st,function = "i2s0";
+                                };
                                i2s1 {
                                        st,pins = "i2s1_grp";
                                        st,function = "i2s1";
@@ -42,6 +46,10 @@
                                        st,pins = "arm_gpio_grp";
                                        st,function = "arm_gpio";
                                };
+                                clcd {
+                                        st,pins = "clcd_grp" , "clcd_high_res";
+                                        st,function = "clcd";
+                                };
                                eth {
                                        st,pins = "gmii_grp";
                                        st,function = "gmii";
@@ -74,11 +82,6 @@
                                        st,pins = "i2c_1_2_grp";
                                        st,function = "i2c_1_2";
                                };
-                                pci {
-                                        st,pins = "pcie0_grp","pcie1_grp",
-                                                "pcie2_grp";
-                                        st,function = "pci";
-                                };
                                smii {
                                        st,pins = "smii_0_1_2_grp";
                                        st,function = "smii_0_1_2";
@@ -88,6 +91,14 @@
                                                "nand_16bit_grp";
                                        st,function = "nand";
                                };
+                                sata {
+                                        st,pins = "sata0_grp";
+                                        st,function = "sata";
+                                };
+                                pcie {
+                                        st,pins = "pcie1_grp", "pcie2_grp";
+                                        st,function = "pci_express";
+                                };
                        };
                };
@@ -109,9 +120,49 @@
                fsmc: flash@b0000000 {
                        status = "okay";
+                        partition@0 {
+                                label = "xloader";
+                                reg = <0x0 0x80000>;
+                        };
+                        partition@80000 {
+                                label = "u-boot";
+                                reg = <0x80000 0x140000>;
+                        };
+                        partition@1C0000 {
+                                label = "environment";
+                                reg = <0x1C0000 0x40000>;
+                        };
+                        partition@200000 {
+                                label = "dtb";
+                                reg = <0x200000 0x40000>;
+                        };
+                        partition@240000 {
+                                label = "linux";
+                                reg = <0x240000 0xC00000>;
+                        };
+                        partition@E40000 {
+                                label = "rootfs";
+                                reg = <0xE40000 0x0>;
+                        };
+                };
+                gpio_keys {
+                        compatible = "gpio-keys";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        button@1 {
+                                label = "wakeup";
+                                linux,code = <0x100>;
+                                gpios = <&gpio0 7 0x4>;
+                                debounce-interval = <20>;
+                                gpio-key,wakeup = <1>;
+                        };
                };
                gmac0: eth@e2000000 {
+                        phy-mode = "gmii";
                        status = "okay";
                };
@@ -135,23 +186,27 @@
                                };
                                partition@10000 {
                                        label = "u-boot";
-                                        reg = <0x10000 0x40000>;
+                                        reg = <0x10000 0x50000>;
+                                };
+                                partition@60000 {
+                                        label = "environment";
+                                        reg = <0x60000 0x10000>;
                                };
-                                partition@50000 {
+                                partition@70000 {
+                                        label = "dtb";
+                                        reg = <0x70000 0x10000>;
+                                };
+                                partition@80000 {
                                        label = "linux";
-                                        reg = <0x50000 0x2c0000>;
+                                        reg = <0x80000 0x310000>;
                                };
-                                partition@310000 {
+                                partition@390000 {
                                        label = "rootfs";
-                                        reg = <0x310000 0x4f0000>;
+                                        reg = <0x390000 0x0>;
                                };
                        };
                };
-                spi0: spi@e0100000 {
-                        status = "okay";
-                };
                ehci@e4800000 {
                        status = "okay";
                };
@@ -181,11 +236,11 @@
                               status = "okay";
                        };
-                        i2c0: i2c@e0280000 {
+                        gpio@d8400000 {
                               status = "okay";
                        };
-                        i2c1: i2c@5cd00000 {
+                        i2c0: i2c@e0280000 {
                               status = "okay";
                        };
@@ -273,6 +328,7 @@
                                                 0x08080052 >;
                               autorepeat;
                               st,mode = <0>;
+                               suspended_rate = <2000000>;
                               status = "okay";
                        };
@@ -282,6 +338,81 @@
                        serial@e0000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
+                        };
+                        spi0: spi@e0100000 {
+                                status = "okay";
+                                num-cs = <3>;
+                                cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
+                                stmpe610@0 {
+                                        compatible = "st,stmpe610";
+                                        reg = <0>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        spi-max-frequency = <1000000>;
+                                        spi-cpha;
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable;
+                                        pl022,com-mode = <0>;
+                                        pl022,rx-level-trig = <0>;
+                                        pl022,tx-level-trig = <0>;
+                                        pl022,ctrl-len = <0x7>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+                                        interrupts = <6 0x4>;
+                                        interrupt-parent = <&gpio1>;
+                                        irq-trigger = <0x2>;
+                                        stmpe_touchscreen {
+                                                compatible = "st,stmpe-ts";
+                                                ts,sample-time = <4>;
+                                                ts,mod-12b = <1>;
+                                                ts,ref-sel = <0>;
+                                                ts,adc-freq = <1>;
+                                                ts,ave-ctrl = <1>;
+                                                ts,touch-det-delay = <2>;
+                                                ts,settling = <2>;
+                                                ts,fraction-z = <7>;
+                                                ts,i-drive = <1>;
+                                        };
+                                };
+                                m25p80@1 {
+                                        compatible = "st,m25p80";
+                                        reg = <1>;
+                                        spi-max-frequency = <12000000>;
+                                        spi-cpol;
+                                        spi-cpha;
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable;
+                                        pl022,com-mode = <0x2>;
+                                        pl022,rx-level-trig = <0>;
+                                        pl022,tx-level-trig = <0>;
+                                        pl022,ctrl-len = <0x11>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+                                };
+                                spidev@2 {
+                                        compatible = "spidev";
+                                        reg = <2>;
+                                        spi-max-frequency = <25000000>;
+                                        spi-cpha;
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable;
+                                        pl022,com-mode = <0x2>;
+                                        pl022,rx-level-trig = <0>;
+                                        pl022,tx-level-trig = <0>;
+                                        pl022,ctrl-len = <0x11>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+                                };
                        };
                        wdt@ec800620 {
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 419ea7413d23..1513c1927cc8 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -17,6 +17,18 @@
        compatible = "st,spear1310";
        ahb {
+                spics: spics@e0700000{
+                        compatible = "st,spear-spics-gpio";
+                        reg = <0xe0700000 0x1000>;
+                        st-spics,peripcfg-reg = <0x3b0>;
+                        st-spics,sw-enable-bit = <12>;
+                        st-spics,cs-value-bit = <11>;
+                        st-spics,cs-enable-mask = <3>;
+                        st-spics,cs-enable-shift = <8>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
                ahci@b1000000 {
                        compatible = "snps,spear-ahci";
                        reg = <0xb1000000 0x10000>;
@@ -43,6 +55,7 @@
                        reg = <0x5c400000 0x8000>;
                        interrupts = <0 95 0x4>;
                        interrupt-names = "macirq";
+                        phy-mode = "mii";
                        status = "disabled";
                };
@@ -51,6 +64,7 @@
                        reg = <0x5c500000 0x8000>;
                        interrupts = <0 96 0x4>;
                        interrupt-names = "macirq";
+                        phy-mode = "mii";
                        status = "disabled";
                };
@@ -59,6 +73,7 @@
                        reg = <0x5c600000 0x8000>;
                        interrupts = <0 97 0x4>;
                        interrupt-names = "macirq";
+                        phy-mode = "rmii";
                        status = "disabled";
                };
@@ -67,14 +82,14 @@
                        reg = <0x5c700000 0x8000>;
                        interrupts = <0 98 0x4>;
                        interrupt-names = "macirq";
+                        phy-mode = "rgmii";
                        status = "disabled";
                };
-                spi1: spi@5d400000 {
+                pinmux: pinmux@e0700000 {
-                        compatible = "arm,pl022", "arm,primecell";
+                        compatible = "st,spear1310-pinmux";
-                        reg = <0x5d400000 0x1000>;
+                        reg = <0xe0700000 0x1000>;
-                        interrupts = <0 99 0x4>;
+                        #gpio-range-cells = <2>;
-                        status = "disabled";
                };
                apb {
@@ -141,6 +156,15 @@
                                status = "disabled";
                        };
+                        spi1: spi@5d400000 {
+                                compatible = "arm,pl022", "arm,primecell";
+                                reg = <0x5d400000 0x1000>;
+                                interrupts = <0 99 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                        serial@5c800000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x5c800000 0x1000>;
@@ -179,6 +203,27 @@
                        thermal@e07008c4 {
                                st,thermal-flags = <0x7000>;
                        };
+                        gpiopinctrl: gpio@d8400000 {
+                                compatible = "st,spear-plgpio";
+                                reg = <0xd8400000 0x1000>;
+                                interrupts = <0 100 0x4>;
+                                #interrupt-cells = <1>;
+                                interrupt-controller;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio-ranges = <&pinmux 0 246>;
+                                status = "disabled";
+                                st-plgpio,ngpio = <246>;
+                                st-plgpio,enb-reg = <0xd0>;
+                                st-plgpio,wdata-reg = <0x90>;
+                                st-plgpio,dir-reg = <0xb0>;
+                                st-plgpio,ie-reg = <0x30>;
+                                st-plgpio,rdata-reg = <0x70>;
+                                st-plgpio,mis-reg = <0x10>;
+                                st-plgpio,eit-reg = <0x50>;
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index c9a54e06fb68..d6c30ae0a8d7 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -38,20 +38,15 @@
                                        st,pins = "fsmc_8bit_grp";
                                        st,function = "fsmc";
                                };
-                                kbd {
-                                        st,pins = "keyboard_row_col_grp",
-                                                "keyboard_col5_grp";
-                                        st,function = "keyboard";
-                                };
                                uart0 {
-                                        st,pins = "uart0_grp", "uart0_enh_grp";
+                                        st,pins = "uart0_grp";
                                        st,function = "uart0";
                                };
-                                i2c0-pmx {
+                                i2c0 {
                                        st,pins = "i2c0_grp";
                                        st,function = "i2c0";
                                };
-                                i2c1-pmx {
+                                i2c1 {
                                        st,pins = "i2c1_grp";
                                        st,function = "i2c1";
                                };
@@ -64,14 +59,9 @@
                                        st,function = "spdif_out";
                                };
                                ssp0 {
-                                        st,pins = "ssp0_grp", "ssp0_cs1_grp",
+                                        st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
-                                                "ssp0_cs3_grp";
                                        st,function = "ssp0";
                                };
-                                pwm {
-                                        st,pins = "pwm2_grp", "pwm3_grp";
-                                        st,function = "pwm";
-                                };
                                smi-pmx {
                                        st,pins = "smi_grp";
                                        st,function = "smi";
@@ -84,6 +74,18 @@
                                        st,pins = "gmii_grp", "rgmii_grp";
                                        st,function = "gmac";
                                };
+                                cam0 {
+                                        st,pins = "cam0_grp";
+                                        st,function = "cam0";
+                                };
+                                cam1 {
+                                        st,pins = "cam1_grp";
+                                        st,function = "cam1";
+                                };
+                                cam2 {
+                                        st,pins = "cam2_grp";
+                                        st,function = "cam2";
+                                };
                                cam3 {
                                        st,pins = "cam3_grp";
                                        st,function = "cam3";
@@ -108,9 +110,18 @@
                                        st,pins = "sata_grp";
                                        st,function = "sata";
                                };
+                                pcie {
+                                        st,pins = "pcie_grp";
+                                        st,function = "pcie";
+                                };
                        };
                };
+                ahci@b1000000 {
+                        status = "okay";
+                };
                dma@ea800000 {
                        status = "okay";
                };
@@ -121,9 +132,35 @@
                fsmc: flash@b0000000 {
                        status = "okay";
+                        partition@0 {
+                                label = "xloader";
+                                reg = <0x0 0x200000>;
+                        };
+                        partition@200000 {
+                                label = "u-boot";
+                                reg = <0x200000 0x200000>;
+                        };
+                        partition@400000 {
+                                label = "environment";
+                                reg = <0x400000 0x100000>;
+                        };
+                        partition@500000 {
+                                label = "dtb";
+                                reg = <0x500000 0x100000>;
+                        };
+                        partition@600000 {
+                                label = "linux";
+                                reg = <0x600000 0xC00000>;
+                        };
+                        partition@1200000 {
+                                label = "rootfs";
+                                reg = <0x1200000 0x0>;
+                        };
                };
                gmac0: eth@e2000000 {
+                        phy-mode = "rgmii";
                        status = "okay";
                };
@@ -147,31 +184,62 @@
                                };
                                partition@10000 {
                                        label = "u-boot";
-                                        reg = <0x10000 0x40000>;
+                                        reg = <0x10000 0x50000>;
+                                };
+                                partition@60000 {
+                                        label = "environment";
+                                        reg = <0x60000 0x10000>;
+                                };
+                                partition@70000 {
+                                        label = "dtb";
+                                        reg = <0x70000 0x10000>;
                                };
-                                partition@50000 {
+                                partition@80000 {
                                        label = "linux";
-                                        reg = <0x50000 0x2c0000>;
+                                        reg = <0x80000 0x310000>;
                                };
-                                partition@310000 {
+                                partition@390000 {
                                        label = "rootfs";
-                                        reg = <0x310000 0x4f0000>;
+                                        reg = <0x390000 0x0>;
                                };
                        };
                };
-                spi0: spi@e0100000 {
+                ehci@e4800000 {
                        status = "okay";
                };
-                ehci@e4800000 {
+                gpio_keys {
-                        status = "okay";
+                        compatible = "gpio-keys";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        button@1 {
+                                label = "wakeup";
+                                linux,code = <0x100>;
+                                gpios = <&gpio1 1 0x4>;
+                                debounce-interval = <20>;
+                                gpio-key,wakeup = <1>;
+                        };
                };
                ehci@e5800000 {
                        status = "okay";
                };
+                i2s0: i2s-play@b2400000 {
+                        status = "okay";
+                };
+                i2s1: i2s-rec@b2000000 {
+                        status = "okay";
+                };
+                incodec: dir-hifi {
+                        compatible = "dummy,dir-hifi";
+                        status = "okay";
+                };
                ohci@e4000000 {
                        status = "okay";
                };
@@ -180,11 +248,43 @@
                        status = "okay";
                };
+                outcodec: dit-hifi {
+                        compatible = "dummy,dit-hifi";
+                        status = "okay";
+                };
+                sound {
+                        compatible = "spear,spear-evb";
+                        audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>;
+                        audio-codecs = <&incodec &outcodec &sta529 &sta529>;
+                        codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio";
+                        stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap";
+                        dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm";
+                        nr_controllers = <4>;
+                        status = "okay";
+                };
+                spdif0: spdif-in@d0100000 {
+                        status = "okay";
+                };
+                spdif1: spdif-out@d0000000 {
+                        status = "okay";
+                };
                apb {
                        adc@e0080000 {
                                status = "okay";
                        };
+                        i2s-play@b2400000 {
+                                status = "okay";
+                        };
+                        i2s-rec@b2000000 {
+                                status = "okay";
+                        };
                        gpio0: gpio@e0600000 {
                               status = "okay";
                        };
@@ -193,12 +293,42 @@
                               status = "okay";
                        };
+                        gpio@e2800000 {
+                               status = "okay";
+                        };
                        i2c0: i2c@e0280000 {
                               status = "okay";
+                                sta529: sta529@1a {
+                                        compatible = "st,sta529";
+                                        reg = <0x1a>;
+                                };
                        };
                        i2c1: i2c@b4000000 {
                               status = "okay";
+                                eeprom0@56 {
+                                        compatible = "st,eeprom";
+                                        reg = <0x56>;
+                                };
+                                stmpe801@41 {
+                                        compatible = "st,stmpe801";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0x41>;
+                                        interrupts = <4 0x4>;
+                                        interrupt-parent = <&gpio0>;
+                                        irq-trigger = <0x2>;
+                                        stmpegpio: stmpe_gpio {
+                                                compatible = "st,stmpe-gpio";
+                                                gpio-controller;
+                                                #gpio-cells = <2>;
+                                        };
+                                };
                        };
                        kbd@e0300000 {
@@ -285,6 +415,7 @@
                                                 0x08080052 >;
                               autorepeat;
                               st,mode = <0>;
+                               suspended_rate = <2000000>;
                               status = "okay";
                        };
@@ -294,10 +425,92 @@
                        serial@e0000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@b4100000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
+                        };
+                        spi0: spi@e0100000 {
+                                status = "okay";
+                                num-cs = <3>;
+                                cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
+                                           <&gpiopinctrl 85 0>;
+                                m25p80@0 {
+                                        compatible = "m25p80";
+                                        reg = <0>;
+                                        spi-max-frequency = <12000000>;
+                                        spi-cpol;
+                                        spi-cpha;
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable;
+                                        pl022,com-mode = <0x2>;
+                                        pl022,rx-level-trig = <0>;
+                                        pl022,tx-level-trig = <0>;
+                                        pl022,ctrl-len = <0x11>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+                                };
+                                stmpe610@1 {
+                                        compatible = "st,stmpe610";
+                                        spi-max-frequency = <1000000>;
+                                        spi-cpha;
+                                        reg = <1>;
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable;
+                                        pl022,com-mode = <0>;
+                                        pl022,rx-level-trig = <0>;
+                                        pl022,tx-level-trig = <0>;
+                                        pl022,ctrl-len = <0x7>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+                                        interrupts = <100 0>;
+                                        interrupt-parent = <&gpiopinctrl>;
+                                        irq-trigger = <0x2>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        stmpe_touchscreen {
+                                                compatible = "st,stmpe-ts";
+                                                ts,sample-time = <4>;
+                                                ts,mod-12b = <1>;
+                                                ts,ref-sel = <0>;
+                                                ts,adc-freq = <1>;
+                                                ts,ave-ctrl = <1>;
+                                                ts,touch-det-delay = <2>;
+                                                ts,settling = <2>;
+                                                ts,fraction-z = <7>;
+                                                ts,i-drive = <1>;
+                                        };
+                                };
+                                spidev@2 {
+                                        compatible = "spidev";
+                                        reg = <2>;
+                                        spi-max-frequency = <25000000>;
+                                        spi-cpha;
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable;
+                                        pl022,com-mode = <0x2>;
+                                        pl022,rx-level-trig = <0>;
+                                        pl022,tx-level-trig = <0>;
+                                        pl022,ctrl-len = <0x11>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+                                };
+                        };
+                        timer@ec800600 {
+                                status = "okay";
                        };
                        wdt@ec800620 {
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index d71fe2a68f09..34da11aa6795 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -17,6 +17,20 @@
        compatible = "st,spear1340";
        ahb {
+                spics: spics@e0700000{
+                        compatible = "st,spear-spics-gpio";
+                        reg = <0xe0700000 0x1000>;
+                        st-spics,peripcfg-reg = <0x42c>;
+                        st-spics,sw-enable-bit = <21>;
+                        st-spics,cs-value-bit = <20>;
+                        st-spics,cs-enable-mask = <3>;
+                        st-spics,cs-enable-shift = <18>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        status = "disabled";
+                };
                ahci@b1000000 {
                        compatible = "snps,spear-ahci";
                        reg = <0xb1000000 0x10000>;
@@ -24,9 +38,61 @@
                        status = "disabled";
                };
+                i2s-play@b2400000 {
+                        compatible = "snps,designware-i2s";
+                        reg = <0xb2400000 0x10000>;
+                        interrupt-names = "play_irq";
+                        interrupts = <0 98 0x4
+                                      0 99 0x4>;
+                        play;
+                        channel = <8>;
+                        status = "disabled";
+                };
+                i2s-rec@b2000000 {
+                        compatible = "snps,designware-i2s";
+                        reg = <0xb2000000 0x10000>;
+                        interrupt-names = "record_irq";
+                        interrupts = <0 100  0x4
+                                      0 101 0x4>;
+                        record;
+                        channel = <8>;
+                        status = "disabled";
+                };
+                pinmux: pinmux@e0700000 {
+                        compatible = "st,spear1340-pinmux";
+                        reg = <0xe0700000 0x1000>;
+                        #gpio-range-cells = <2>;
+                };
+                pwm: pwm@e0180000 {
+                        compatible ="st,spear13xx-pwm";
+                        reg = <0xe0180000 0x1000>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+                spdif-in@d0100000 {
+                        compatible = "st,spdif-in";
+                        reg = < 0xd0100000 0x20000
+                                0xd0110000 0x10000 >;
+                        interrupts = <0 84 0x4>;
+                        status = "disabled";
+                };
+                spdif-out@d0000000 {
+                        compatible = "st,spdif-out";
+                        reg = <0xd0000000 0x20000>;
+                        interrupts = <0 85 0x4>;
+                        status = "disabled";
+                };
                spi1: spi@5d400000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0x5d400000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        interrupts = <0 99 0x4>;
                        status = "disabled";
                };
@@ -38,6 +104,7 @@
                                compatible = "snps,designware-i2c";
                                reg = <0xb4000000 0x1000>;
                                interrupts = <0 104 0x4>;
+                                write-16bit;
                                status = "disabled";
                        };
@@ -51,6 +118,26 @@
                        thermal@e07008c4 {
                                st,thermal-flags = <0x2a00>;
                        };
+                        gpiopinctrl: gpio@e2800000 {
+                                compatible = "st,spear-plgpio";
+                                reg = <0xe2800000 0x1000>;
+                                interrupts = <0 107 0x4>;
+                                #interrupt-cells = <1>;
+                                interrupt-controller;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio-ranges = <&pinmux 0 252>;
+                                status = "disabled";
+                                st-plgpio,ngpio = <250>;
+                                st-plgpio,wdata-reg = <0x40>;
+                                st-plgpio,dir-reg = <0x00>;
+                                st-plgpio,ie-reg = <0x80>;
+                                st-plgpio,rdata-reg = <0x20>;
+                                st-plgpio,mis-reg = <0xa0>;
+                                st-plgpio,eit-reg = <0x60>;
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index f7b84aced654..009096d1d2c3 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -64,12 +64,26 @@
                bootargs = "console=ttyAMA0,115200";
        };
+        cpufreq {
+                compatible = "st,cpufreq-spear";
+                cpufreq_tbl = < 166000
+                                200000
+                                250000
+                                300000
+                                400000
+                                500000
+                                600000 >;
+                status = "disable";
+        };
        ahb {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
                ranges = <0x50000000 0x50000000 0x10000000
                          0xb0000000 0xb0000000 0x10000000
+                          0xd0000000 0xd0000000 0x02000000
+                          0xd8000000 0xd8000000 0x01000000
                          0xe0000000 0xe0000000 0x10000000>;
                sdhci@b3000000 {
@@ -81,7 +95,7 @@
                cf@b2800000 {
                        compatible = "arasan,cf-spear1340";
-                        reg = <0xb2800000 0x100>;
+                        reg = <0xb2800000 0x1000>;
                        interrupts = <0 29 0x4>;
                        status = "disabled";
                };
@@ -113,6 +127,7 @@
                                      0 23 0x4>;
                        st,ale-off = <0x20000>;
                        st,cle-off = <0x10000>;
+                        st,mode = <2>;
                        status = "disabled";
                };
@@ -125,6 +140,13 @@
                        status = "disabled";
                };
+                pcm {
+                        compatible = "st,pcm-audio";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        status = "disable";
+                };
                smi: flash@ea000000 {
                        compatible = "st,spear600-smi";
                        #address-cells = <1>;
@@ -134,17 +156,11 @@
                        status = "disabled";
                };
-                spi0: spi@e0100000 {
-                        compatible = "arm,pl022", "arm,primecell";
-                        reg = <0xe0100000 0x1000>;
-                        interrupts = <0 31 0x4>;
-                        status = "disabled";
-                };
                ehci@e4800000 {
                        compatible = "st,spear600-ehci", "usb-ehci";
                        reg = <0xe4800000 0x1000>;
                        interrupts = <0 64 0x4>;
+                        usbh0_id = <0>;
                        status = "disabled";
                };
@@ -152,6 +168,7 @@
                        compatible = "st,spear600-ehci", "usb-ehci";
                        reg = <0xe5800000 0x1000>;
                        interrupts = <0 66 0x4>;
+                        usbh1_id = <1>;
                        status = "disabled";
                };
@@ -159,6 +176,7 @@
                        compatible = "st,spear600-ohci", "usb-ohci";
                        reg = <0xe4000000 0x1000>;
                        interrupts = <0 65 0x4>;
+                        usbh0_id = <0>;
                        status = "disabled";
                };
@@ -166,6 +184,7 @@
                        compatible = "st,spear600-ohci", "usb-ohci";
                        reg = <0xe5000000 0x1000>;
                        interrupts = <0 67 0x4>;
+                        usbh1_id = <1>;
                        status = "disabled";
                };
@@ -175,6 +194,8 @@
                        compatible = "simple-bus";
                        ranges = <0x50000000 0x50000000 0x10000000
                                  0xb0000000 0xb0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x02000000
+                                  0xd8000000 0xd8000000 0x01000000
                                  0xe0000000 0xe0000000 0x10000000>;
                        gpio0: gpio@e0600000 {
@@ -215,8 +236,35 @@
                                status = "disabled";
                        };
+                        i2s@e0180000 {
+                                compatible = "st,designware-i2s";
+                                reg = <0xe0180000 0x1000>;
+                                interrupt-names = "play_irq", "record_irq";
+                                interrupts = <0 10 0x4
+                                              0 11 0x4 >;
+                                status = "disabled";
+                        };
+                        i2s@e0200000 {
+                                compatible = "st,designware-i2s";
+                                reg = <0xe0200000 0x1000>;
+                                interrupt-names = "play_irq", "record_irq";
+                                interrupts = <0 26 0x4
+                                              0 53 0x4>;
+                                status = "disabled";
+                        };
+                        spi0: spi@e0100000 {
+                                compatible = "arm,pl022", "arm,primecell";
+                                reg = <0xe0100000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <0 31 0x4>;
+                                status = "disabled";
+                        };
                        rtc@e0580000 {
-                                compatible = "st,spear-rtc";
+                                compatible = "st,spear600-rtc";
                                reg = <0xe0580000 0x1000>;
                                interrupts = <0 36 0x4>;
                                status = "disabled";
@@ -232,7 +280,7 @@
                        adc@e0080000 {
                                compatible = "st,spear600-adc";
                                reg = <0xe0080000 0x1000>;
-                                interrupts = <0 44 0x4>;
+                                interrupts = <0 12 0x4>;
                                status = "disabled";
                        };
@@ -245,7 +293,8 @@
                        timer@ec800600 {
                                compatible = "arm,cortex-a9-twd-timer";
                                reg = <0xec800600 0x20>;
-                                interrupts = <1 13 0x301>;
+                                interrupts = <1 13 0x4>;
+                                status = "disabled";
                        };
                        wdt@ec800620 {
@@ -257,6 +306,7 @@
                        thermal@e07008c4 {
                                compatible = "st,thermal-spear1340";
                                reg = <0xe07008c4 0x4>;
+                                thermal_flags = <0x7000>;
                        };
                };
        };
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 1e7c7a8e2123..5de1431653e4 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -100,15 +100,23 @@
                                };
                                partition@10000 {
                                        label = "u-boot";
-                                        reg = <0x10000 0x40000>;
+                                        reg = <0x10000 0x50000>;
                                };
-                                partition@50000 {
+                                partition@60000 {
+                                        label = "environment";
+                                        reg = <0x60000 0x10000>;
+                                };
+                                partition@70000 {
+                                        label = "dtb";
+                                        reg = <0x70000 0x10000>;
+                                };
+                                partition@80000 {
                                        label = "linux";
-                                        reg = <0x50000 0x2c0000>;
+                                        reg = <0x80000 0x310000>;
                                };
-                                partition@310000 {
+                                partition@390000 {
                                        label = "rootfs";
-                                        reg = <0x310000 0x4f0000>;
+                                        reg = <0x390000 0x0>;
                                };
                        };
                };
@@ -235,6 +243,8 @@
                        serial@d0000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index ed3627c116cc..090adc656015 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -27,7 +27,7 @@
                };
                clcd@60000000 {
-                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        compatible = "arm,pl110", "arm,primecell";
                        reg = <0x60000000 0x1000>;
                        interrupts = <30>;
                        status = "disabled";
@@ -52,6 +52,14 @@
                        status = "disabled";
                };
+                shirq: interrupt-controller@0x50000000 {
+                        compatible = "st,spear300-shirq";
+                        reg = <0x50000000 0x1000>;
+                        interrupts = <28>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                };
                apb {
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -64,12 +72,16 @@
                                compatible = "arm,pl061", "arm,primecell";
                                gpio-controller;
                                reg = <0xa9000000 0x1000>;
+                                interrupts = <8>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                        kbd@a0000000 {
                                compatible = "st,spear300-kbd";
                                reg = <0xa0000000 0x1000>;
+                                interrupts = <7>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index b00544e0cd5d..b09632963d15 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -114,15 +114,23 @@
                                };
                                partition@10000 {
                                        label = "u-boot";
-                                        reg = <0x10000 0x40000>;
+                                        reg = <0x10000 0x50000>;
                                };
-                                partition@50000 {
+                                partition@60000 {
+                                        label = "environment";
+                                        reg = <0x60000 0x10000>;
+                                };
+                                partition@70000 {
+                                        label = "dtb";
+                                        reg = <0x70000 0x10000>;
+                                };
+                                partition@80000 {
                                        label = "linux";
-                                        reg = <0x50000 0x2c0000>;
+                                        reg = <0x80000 0x310000>;
                                };
-                                partition@310000 {
+                                partition@390000 {
                                        label = "rootfs";
-                                        reg = <0x310000 0x4f0000>;
+                                        reg = <0x390000 0x0>;
                                };
                        };
                };
@@ -158,26 +166,38 @@
                        serial@d0000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@b2000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@b2080000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@b2100000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@b2180000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@b2200000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index 62fc4fb3e5f9..e814e5e97083 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -22,9 +22,10 @@
                          0xb0000000 0xb0000000 0x10000000
                          0xd0000000 0xd0000000 0x30000000>;
-                pinmux@b4000000 {
+                pinmux: pinmux@b4000000 {
                        compatible = "st,spear310-pinmux";
                        reg = <0xb4000000 0x1000>;
+                        #gpio-range-cells = <2>;
                };
                fsmc: flash@44000000 {
@@ -39,6 +40,14 @@
                        status = "disabled";
                };
+                shirq: interrupt-controller@0xb4000000 {
+                        compatible = "st,spear310-shirq";
+                        reg = <0xb4000000 0x1000>;
+                        interrupts = <28 29 30 1>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                };
                apb {
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -49,32 +58,61 @@
                        serial@b2000000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0xb2000000 0x1000>;
+                                interrupts = <8>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                        serial@b2080000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0xb2080000 0x1000>;
+                                interrupts = <9>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                        serial@b2100000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0xb2100000 0x1000>;
+                                interrupts = <10>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                        serial@b2180000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0xb2180000 0x1000>;
+                                interrupts = <11>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                        serial@b2200000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0xb2200000 0x1000>;
+                                interrupts = <12>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
+                        gpiopinctrl: gpio@b4000000 {
+                                compatible = "st,spear-plgpio";
+                                reg = <0xb4000000 0x1000>;
+                                #interrupt-cells = <1>;
+                                interrupt-controller;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio-ranges = <&pinmux 0 102>;
+                                status = "disabled";
+                                st-plgpio,ngpio = <102>;
+                                st-plgpio,enb-reg = <0x10>;
+                                st-plgpio,wdata-reg = <0x20>;
+                                st-plgpio,dir-reg = <0x30>;
+                                st-plgpio,ie-reg = <0x50>;
+                                st-plgpio,rdata-reg = <0x40>;
+                                st-plgpio,mis-reg = <0x60>;
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 082328bd64ab..fdedbb514102 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -76,20 +76,12 @@
                                        st,function = "mii2";
                                };
                                pwm0_1 {
-                                        st,pins = "pwm0_1_pin_14_15_grp";
+                                        st,pins = "pwm0_1_pin_37_38_grp";
                                        st,function = "pwm0_1";
                                };
-                                pwm2 {
-                                        st,pins = "pwm2_pin_13_grp";
-                                        st,function = "pwm2";
-                                };
                        };
                };
-                clcd@90000000 {
-                        status = "okay";
-                };
                dma@fc400000 {
                        status = "okay";
                };
@@ -103,6 +95,7 @@
                };
                sdhci@70000000 {
+                        power-gpio = <&gpiopinctrl 61 1>;
                        status = "okay";
                };
@@ -122,15 +115,23 @@
                                };
                                partition@10000 {
                                        label = "u-boot";
-                                        reg = <0x10000 0x40000>;
+                                        reg = <0x10000 0x50000>;
+                                };
+                                partition@60000 {
+                                        label = "environment";
+                                        reg = <0x60000 0x10000>;
                                };
-                                partition@50000 {
+                                partition@70000 {
+                                        label = "dtb";
+                                        reg = <0x70000 0x10000>;
+                                };
+                                partition@80000 {
                                        label = "linux";
-                                        reg = <0x50000 0x2c0000>;
+                                        reg = <0x80000 0x310000>;
                                };
-                                partition@310000 {
+                                partition@390000 {
                                        label = "rootfs";
-                                        reg = <0x310000 0x4f0000>;
+                                        reg = <0x390000 0x0>;
                                };
                        };
                };
@@ -164,6 +165,10 @@
                               status = "okay";
                        };
+                        gpio@b3000000 {
+                               status = "okay";
+                        };
                        i2c0: i2c@d0180000 {
                               status = "okay";
                        };
@@ -178,14 +183,20 @@
                        serial@d0000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@a3000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@a4000000 {
                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        wdt@fc880000 {
diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts
new file mode 100644
index 000000000000..3075d2d3a8be
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-hmi.dts
@@ -0,0 +1,305 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "spear320.dtsi"
+/ {
+        model = "ST SPEAr320 HMI Board";
+        compatible = "st,spear320-hmi", "st,spear320";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        memory {
+                reg = <0 0x40000000>;
+        };
+        ahb {
+                pinmux@b3000000 {
+                        st,pinmux-mode = <4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                clcd {
+                                        st,pins = "clcd_grp";
+                                        st,function = "clcd";
+                                };
+                                fsmc {
+                                        st,pins = "fsmc_8bit_grp";
+                                        st,function = "fsmc";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_cd_12_grp";
+                                        st,function = "sdhci";
+                                };
+                                i2s {
+                                        st,pins = "i2s_grp";
+                                        st,function = "i2s";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                can0 {
+                                        st,pins = "can0_grp";
+                                        st,function = "can0";
+                                };
+                                can1 {
+                                        st,pins = "can1_grp";
+                                        st,function = "can1";
+                                };
+                                mii0_1 {
+                                        st,pins = "rmii0_1_grp";
+                                        st,function = "mii0_1";
+                                };
+                                pwm0_1 {
+                                        st,pins = "pwm0_1_pin_37_38_grp";
+                                        st,function = "pwm0_1";
+                                };
+                                pwm2 {
+                                        st,pins = "pwm2_pin_34_grp";
+                                        st,function = "pwm2";
+                                };
+                        };
+                };
+                clcd@90000000 {
+                        status = "okay";
+                };
+                dma@fc400000 {
+                        status = "okay";
+                };
+                ehci@e1800000 {
+                        status = "okay";
+                };
+                fsmc: flash@4c000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "xloader";
+                                reg = <0x0 0x80000>;
+                        };
+                        partition@80000 {
+                                label = "u-boot";
+                                reg = <0x80000 0x140000>;
+                        };
+                        partition@1C0000 {
+                                label = "environment";
+                                reg = <0x1C0000 0x40000>;
+                        };
+                        partition@200000 {
+                                label = "dtb";
+                                reg = <0x200000 0x40000>;
+                        };
+                        partition@240000 {
+                                label = "linux";
+                                reg = <0x240000 0xC00000>;
+                        };
+                        partition@E40000 {
+                                label = "rootfs";
+                                reg = <0xE40000 0x0>;
+                        };
+                };
+                gpio_keys {
+                        compatible = "gpio-keys";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        button@1 {
+                                label = "user button 1";
+                                linux,code = <0x100>;
+                                gpios = <&stmpegpio 3 0x4>;
+                                debounce-interval = <20>;
+                                gpio-key,wakeup = <1>;
+                        };
+                        button@2 {
+                                label = "user button 2";
+                                linux,code = <0x200>;
+                                gpios = <&stmpegpio 2 0x4>;
+                                debounce-interval = <20>;
+                                gpio-key,wakeup = <1>;
+                        };
+                };
+                ohci@e1900000 {
+                        status = "okay";
+                };
+                ohci@e2100000 {
+                        status = "okay";
+                };
+                pwm: pwm@a8000000 {
+                        status = "okay";
+                };
+                sdhci@70000000 {
+                        power-gpio = <&gpiopinctrl 50 1>;
+                        power_always_enb;
+                        status = "okay";
+                };
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+                        flash@f8000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xf8000000 0x800000>;
+                                st,smi-fast-mode;
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x50000>;
+                                };
+                                partition@60000 {
+                                        label = "environment";
+                                        reg = <0x60000 0x10000>;
+                                };
+                                partition@70000 {
+                                        label = "dtb";
+                                        reg = <0x70000 0x10000>;
+                                };
+                                partition@80000 {
+                                        label = "linux";
+                                        reg = <0x80000 0x310000>;
+                                };
+                                partition@390000 {
+                                        label = "rootfs";
+                                        reg = <0x390000 0x0>;
+                                };
+                        };
+                };
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+                spi1: spi@a5000000 {
+                        status = "okay";
+                };
+                spi2: spi@a6000000 {
+                        status = "okay";
+                };
+                usbd@e1100000 {
+                        status = "okay";
+                };
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+                        gpio@b3000000 {
+                                status = "okay";
+                        };
+                        i2c0: i2c@d0180000 {
+                                status = "okay";
+                                stmpe811@41 {
+                                        compatible = "st,stmpe811";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0x41>;
+                                        irq-over-gpio;
+                                        irq-gpios = <&gpiopinctrl 29 0x4>;
+                                        id = <0>;
+                                        blocks = <0x5>;
+                                        irq-trigger = <0x1>;
+                                        stmpegpio: stmpe-gpio {
+                                                compatible = "stmpe,gpio";
+                                                reg = <0>;
+                                                gpio-controller;
+                                                #gpio-cells = <2>;
+                                                gpio,norequest-mask = <0xF3>;
+                                        };
+                                        stmpe610-ts {
+                                                compatible = "stmpe,ts";
+                                                reg = <0>;
+                                                ts,sample-time = <4>;
+                                                ts,mod-12b = <1>;
+                                                ts,ref-sel = <0>;
+                                                ts,adc-freq = <1>;
+                                                ts,ave-ctrl = <1>;
+                                                ts,touch-det-delay = <3>;
+                                                ts,settling = <4>;
+                                                ts,fraction-z = <7>;
+                                                ts,i-drive = <1>;
+                                        };
+                                };
+                        };
+                        i2c1: i2c@a7000000 {
+                               status = "okay";
+                        };
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+                        serial@d0000000 {
+                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
+                        };
+                        serial@a3000000 {
+                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
+                        };
+                        serial@a4000000 {
+                               status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
+                        };
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 1f49d69595a0..c056a84deabf 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -21,15 +21,17 @@
                ranges = <0x40000000 0x40000000 0x80000000
                          0xd0000000 0xd0000000 0x30000000>;
-                pinmux@b3000000 {
+                pinmux: pinmux@b3000000 {
                        compatible = "st,spear320-pinmux";
                        reg = <0xb3000000 0x1000>;
+                        #gpio-range-cells = <2>;
                };
                clcd@90000000 {
-                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        compatible = "arm,pl110", "arm,primecell";
                        reg = <0x90000000 0x1000>;
-                        interrupts = <33>;
+                        interrupts = <8>;
+                        interrupt-parent = <&shirq>;
                        status = "disabled";
                };
@@ -48,27 +50,51 @@
                sdhci@70000000 {
                        compatible = "st,sdhci-spear";
                        reg = <0x70000000 0x100>;
-                        interrupts = <29>;
+                        interrupts = <10>;
+                        interrupt-parent = <&shirq>;
                        status = "disabled";
                };
+                shirq: interrupt-controller@0xb3000000 {
+                        compatible = "st,spear320-shirq";
+                        reg = <0xb3000000 0x1000>;
+                        interrupts = <30 28 29 1>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                };
                spi1: spi@a5000000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0xa5000000 0x1000>;
+                        interrupts = <15>;
+                        interrupt-parent = <&shirq>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        status = "disabled";
                };
                spi2: spi@a6000000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0xa6000000 0x1000>;
+                        interrupts = <16>;
+                        interrupt-parent = <&shirq>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        status = "disabled";
                };
+                pwm: pwm@a8000000 {
+                        compatible ="st,spear-pwm";
+                        reg = <0xa8000000 0x1000>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
                apb {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "simple-bus";
-                        ranges = <0xa0000000 0xa0000000 0x10000000
+                        ranges = <0xa0000000 0xa0000000 0x20000000
                                  0xd0000000 0xd0000000 0x30000000>;
                        i2c1: i2c@a7000000 {
@@ -76,20 +102,46 @@
                                #size-cells = <0>;
                                compatible = "snps,designware-i2c";
                                reg = <0xa7000000 0x1000>;
+                                interrupts = <21>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                        serial@a3000000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0xa3000000 0x1000>;
+                                interrupts = <13>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
                        serial@a4000000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0xa4000000 0x1000>;
+                                interrupts = <14>;
+                                interrupt-parent = <&shirq>;
                                status = "disabled";
                        };
+                        gpiopinctrl: gpio@b3000000 {
+                                compatible = "st,spear-plgpio";
+                                reg = <0xb3000000 0x1000>;
+                                #interrupt-cells = <1>;
+                                interrupt-controller;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio-ranges = <&pinmux 0 102>;
+                                status = "disabled";
+                                st-plgpio,ngpio = <102>;
+                                st-plgpio,enb-reg = <0x24>;
+                                st-plgpio,wdata-reg = <0x34>;
+                                st-plgpio,dir-reg = <0x44>;
+                                st-plgpio,ie-reg = <0x64>;
+                                st-plgpio,rdata-reg = <0x54>;
+                                st-plgpio,mis-reg = <0x84>;
+                                st-plgpio,eit-reg = <0x94>;
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 3a8bb5736928..c2a852d43c48 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -53,6 +53,7 @@
                        reg = <0xe0800000 0x8000>;
                        interrupts = <23 22>;
                        interrupt-names = "macirq", "eth_wake_irq";
+                        phy-mode = "mii";
                        status = "disabled";
                };
@@ -69,6 +70,8 @@
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0xd0100000 0x1000>;
                        interrupts = <20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        status = "disabled";
                };
@@ -120,7 +123,7 @@
                        };
                        rtc@fc900000 {
-                                compatible = "st,spear-rtc";
+                                compatible = "st,spear600-rtc";
                                reg = <0xfc900000 0x1000>;
                                interrupts = <10>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 1119c22c9a82..d865a891776d 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,15 +24,35 @@
        };
        ahb {
+                clcd@fc200000 {
+                        status = "okay";
+                };
                dma@fc400000 {
                        status = "okay";
                };
+                ehci@e1800000 {
+                        status = "okay";
+                };
+                ehci@e2000000 {
+                        status = "okay";
+                };
                gmac: ethernet@e0800000 {
                        phy-mode = "gmii";
                        status = "okay";
                };
+                ohci@e1900000 {
+                        status = "okay";
+                };
+                ohci@e2100000 {
+                        status = "okay";
+                };
                smi: flash@fc000000 {
                        status = "okay";
                        clock-rate=<50000000>;
@@ -49,15 +69,23 @@
                                };
                                partition@10000 {
                                        label = "u-boot";
-                                        reg = <0x10000 0x40000>;
+                                        reg = <0x10000 0x50000>;
                                };
-                                partition@50000 {
+                                partition@60000 {
+                                        label = "environment";
+                                        reg = <0x60000 0x10000>;
+                                };
+                                partition@70000 {
+                                        label = "dtb";
+                                        reg = <0x70000 0x10000>;
+                                };
+                                partition@80000 {
                                        label = "linux";
-                                        reg = <0x50000 0x2c0000>;
+                                        reg = <0x80000 0x310000>;
                                };
-                                partition@310000 {
+                                partition@390000 {
                                        label = "rootfs";
-                                        reg = <0x310000 0x4f0000>;
+                                        reg = <0x390000 0x0>;
                                };
                        };
                };
@@ -65,10 +93,18 @@
                apb {
                        serial@d0000000 {
                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
                        };
                        serial@d0080000 {
                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <>;
+                        };
+                        rtc@fc900000 {
+                               status = "okay";
                        };
                        i2c@d0200000 {
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index a3c36e47d7ef..e051dde5181f 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
                        #interrupt-cells = <1>;
                };
+                clcd@fc200000 {
+                        compatible = "arm,pl110", "arm,primecell";
+                        reg = <0xfc200000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <12>;
+                        status = "disabled";
+                };
                dma@fc400000 {
                        compatible = "arm,pl080", "arm,primecell";
                        reg = <0xfc400000 0x1000>;
@@ -59,6 +67,7 @@
                        interrupt-parent = <&vic1>;
                        interrupts = <24 23>;
                        interrupt-names = "macirq", "eth_wake_irq";
+                        phy-mode = "gmii";
                        status = "disabled";
                };
@@ -178,6 +187,13 @@
                                status = "disabled";
                        };
+                        rtc@fc900000 {
+                                compatible = "st,spear600-rtc";
+                                reg = <0xfc900000 0x1000>;
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
                        timer@f0000000 {
                                compatible = "st,spear-timer";
                                reg = <0xf0000000 0x400>;
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
new file mode 100644
index 000000000000..39446a247e79
--- /dev/null
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        soc-u9500 {
+                i2c@80004000 {
+                        stmpe1601: stmpe1601@40 {
+                                compatible = "st,stmpe1601";
+                                reg = <0x40>;
+                                interrupts = <26 0x1>;
+                                interrupt-parent = <&gpio6>;
+                                interrupt-controller;
+                                wakeup-source;
+                                st,autosleep-timeout = <1024>;
+                                stmpe_keypad {
+                                        compatible = "st,stmpe-keypad";
+                                        debounce-interval = <64>;
+                                        st,scan-count = <8>;
+                                        st,no-autorepeat;
+                                        linux,keymap = <0x205006b
+                                                        0x4010074
+                                                        0x3050072
+                                                        0x1030004
+                                                        0x502006a
+                                                        0x500000a
+                                                        0x5008b
+                                                        0x706001c
+                                                        0x405000b
+                                                        0x6070003
+                                                        0x3040067
+                                                        0x303006c
+                                                        0x60400e7
+                                                        0x602009e
+                                                        0x4020073
+                                                        0x5050002
+                                                        0x4030069
+                                                        0x3020008>;
+                                };
+                        };
+                };
+                i2c@80110000 {
+                        bu21013_tp@0x5c {
+                                compatible = "rhom,bu21013_tp";
+                                reg = <0x5c>;
+                                touch-gpio = <&gpio2 20 0x4>;
+                                avdd-supply = <&ab8500_ldo_aux1_reg>;
+                                rhom,touch-max-x = <384>;
+                                rhom,touch-max-y = <704>;
+                                rhom,flip-y;
+                        };
+                        bu21013_tp@0x5d {
+                                compatible = "rhom,bu21013_tp";
+                                reg = <0x5d>;
+                                touch-gpio = <&gpio2 20 0x4>;
+                                avdd-supply = <&ab8500_ldo_aux1_reg>;
+                                rhom,touch-max-x = <384>;
+                                rhom,touch-max-y = <704>;
+                                rhom,flip-y;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-cubieboard.dts b/arch/arm/boot/dts/sun4i-cubieboard.dts
new file mode 100644
index 000000000000..f4ca126ad994
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-cubieboard.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2012 Stefan Roese
+ * Stefan Roese <sr@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun4i.dtsi"
+/ {
+        model = "Cubietech Cubieboard";
+        compatible = "cubietech,cubieboard", "allwinner,sun4i";
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+        soc {
+                uart0: uart@01c28000 {
+                        status = "okay";
+                };
+                uart1: uart@01c28400 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i.dtsi b/arch/arm/boot/dts/sun4i.dtsi
new file mode 100644
index 000000000000..e61fdd47bd01
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2012 Stefan Roese
+ * Stefan Roese <sr@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "sunxi.dtsi"
+/ {
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-olinuxino.dts b/arch/arm/boot/dts/sun5i-olinuxino.dts
new file mode 100644
index 000000000000..d6ff889a5d87
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-olinuxino.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun5i.dtsi"
+/ {
+        model = "Olimex A13-Olinuxino";
+        compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+        soc {
+                uart1: uart@01c28400 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
new file mode 100644
index 000000000000..59a2d265a98e
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "sunxi.dtsi"
+/ {
+        memory {
+                reg = <0x40000000 0x20000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
new file mode 100644
index 000000000000..8bbc2bfef221
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        interrupt-parent = <&intc>;
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                osc: oscillator {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+                timer@01c20c00 {
+                        compatible = "allwinner,sunxi-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc>;
+                };
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sunxi-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sunxi-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                uart0: uart@01c28000 {
+                        compatible = "ns8250";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        clock-frequency = <24000000>;
+                        status = "disabled";
+                };
+                uart1: uart@01c28400 {
+                        compatible = "ns8250";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        clock-frequency = <24000000>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index c3ef1ad26b6a..43eb72af8948 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -10,6 +10,18 @@
                reg = <0x00000000 0x40000000>;
        };
+        host1x {
+                hdmi {
+                        status = "okay";
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
        pinmux {
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
@@ -262,9 +274,9 @@
                };
        };
-        i2c@7000c400 {
+        hdmi_ddc: i2c@7000c400 {
                status = "okay";
-                clock-frequency = <400000>;
+                clock-frequency = <100000>;
        };
        i2c@7000c500 {
@@ -297,131 +309,98 @@
                        vinldo9-supply = <&sm2_reg>;
                        regulators {
-                                #address-cells = <1>;
+                                sys_reg: sys {
-                                #size-cells = <0>;
-                                sys_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "sys";
                                        regulator-name = "vdd_sys";
                                        regulator-always-on;
                                };
-                                regulator@1 {
+                                sm0 {
-                                        reg = <1>;
-                                        regulator-compatible = "sm0";
                                        regulator-name = "vdd_sm0,vdd_core";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                regulator@2 {
+                                sm1 {
-                                        reg = <2>;
-                                        regulator-compatible = "sm1";
                                        regulator-name = "vdd_sm1,vdd_cpu";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
                                        regulator-always-on;
                                };
-                                sm2_reg: regulator@3 {
+                                sm2_reg: sm2 {
-                                        reg = <3>;
-                                        regulator-compatible = "sm2";
                                        regulator-name = "vdd_sm2,vin_ldo*";
                                        regulator-min-microvolt = <3700000>;
                                        regulator-max-microvolt = <3700000>;
                                        regulator-always-on;
                                };
-                                regulator@4 {
+                                ldo0 {
-                                        reg = <4>;
-                                        regulator-compatible = "ldo0";
                                        regulator-name = "vdd_ldo0,vddio_pex_clk";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@5 {
+                                ldo1 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo1";
                                        regulator-name = "vdd_ldo1,avdd_pll*";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1100000>;
                                        regulator-always-on;
                                };
-                                regulator@6 {
+                                ldo2 {
-                                        reg = <6>;
-                                        regulator-compatible = "ldo2";
                                        regulator-name = "vdd_ldo2,vdd_rtc";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                regulator@7 {
+                                ldo3 {
-                                        reg = <7>;
-                                        regulator-compatible = "ldo3";
                                        regulator-name = "vdd_ldo3,avdd_usb*";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                regulator@8 {
+                                ldo4 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo4";
                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                regulator@9 {
+                                ldo5 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo5";
                                        regulator-name = "vdd_ldo5,vcore_mmc";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@10 {
+                                ldo6 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo6";
                                        regulator-name = "vdd_ldo6,avdd_vdac";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@11 {
+                                hdmi_vdd_reg: ldo7 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo7";
                                        regulator-name = "vdd_ldo7,avdd_hdmi";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@12 {
+                                hdmi_pll_reg: ldo8 {
-                                        reg = <12>;
-                                        regulator-compatible = "ldo8";
                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@13 {
+                                ldo9 {
-                                        reg = <13>;
-                                        regulator-compatible = "ldo9";
                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@14 {
+                                ldo_rtc {
-                                        reg = <14>;
-                                        regulator-compatible = "ldo_rtc";
                                        regulator-name = "vdd_rtc_out,vdd_cell";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
@@ -429,6 +408,11 @@
                                };
                        };
                };
+                temperature-sensor@4c {
+                        compatible = "adi,adt7461";
+                        reg = <0x4c>;
+                };
        };
        pmc {
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ddf287f52d49..6a93d1404c76 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -291,37 +291,26 @@
                        vinldo9-supply = <&sm2_reg>;
                        regulators {
-                                #address-cells = <1>;
+                                sys_reg: sys {
-                                #size-cells = <0>;
-                                sys_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "sys";
                                        regulator-name = "vdd_sys";
                                        regulator-always-on;
                                };
-                                regulator@1 {
+                                sm0 {
-                                        reg = <1>;
-                                        regulator-compatible = "sm0";
                                        regulator-name = "+1.2vs_sm0,vdd_core";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                regulator@2 {
+                                sm1 {
-                                        reg = <2>;
-                                        regulator-compatible = "sm1";
                                        regulator-name = "+1.0vs_sm1,vdd_cpu";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
                                        regulator-always-on;
                                };
-                                sm2_reg: regulator@3 {
+                                sm2_reg: sm2 {
-                                        reg = <3>;
-                                        regulator-compatible = "sm2";
                                        regulator-name = "+3.7vs_sm2,vin_ldo*";
                                        regulator-min-microvolt = <3700000>;
                                        regulator-max-microvolt = <3700000>;
@@ -330,53 +319,41 @@
                                /* LDO0 is not connected to anything */
-                                regulator@5 {
+                                ldo1 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo1";
                                        regulator-name = "+1.1vs_ldo1,avdd_pll*";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1100000>;
                                        regulator-always-on;
                                };
-                                regulator@6 {
+                                ldo2 {
-                                        reg = <6>;
-                                        regulator-compatible = "ldo2";
                                        regulator-name = "+1.2vs_ldo2,vdd_rtc";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                regulator@7 {
+                                ldo3 {
-                                        reg = <7>;
-                                        regulator-compatible = "ldo3";
                                        regulator-name = "+3.3vs_ldo3,avdd_usb*";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                regulator@8 {
+                                ldo4 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo4";
                                        regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                regulator@9 {
+                                ldo5 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo5";
                                        regulator-name = "+2.85vs_ldo5,vcore_mmc";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@10 {
+                                ldo6 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo6";
                                        /*
                                         * Research indicates this should be
                                         * 1.8v; other boards that use this
@@ -390,34 +367,26 @@
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@11 {
+                                ldo7 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo7";
                                        regulator-name = "+3.3vs_ldo7,avdd_hdmi";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@12 {
+                                ldo8 {
-                                        reg = <12>;
-                                        regulator-compatible = "ldo8";
                                        regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@13 {
+                                ldo9 {
-                                        reg = <13>;
-                                        regulator-compatible = "ldo9";
                                        regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@14 {
+                                ldo_rtc {
-                                        reg = <14>;
-                                        regulator-compatible = "ldo_rtc";
                                        regulator-name = "+3.3vs_rtc";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 331a3ef24d59..289480026fbf 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,6 +6,12 @@
        model = "Avionic Design Plutux board";
        compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
+        host1x {
+                hdmi {
+                        status = "okay";
+                };
+        };
        i2c@7000c000 {
                wm8903: wm8903@1a {
                        compatible = "wlf,wm8903";
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index f0ba901676ac..420459825b46 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -395,37 +395,26 @@
                        vinldo9-supply = <&sm2_reg>;
                        regulators {
-                                #address-cells = <1>;
+                                sys_reg: sys {
-                                #size-cells = <0>;
-                                sys_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "sys";
                                        regulator-name = "vdd_sys";
                                        regulator-always-on;
                                };
-                                regulator@1 {
+                                sm0 {
-                                        reg = <1>;
-                                        regulator-compatible = "sm0";
                                        regulator-name = "vdd_sm0,vdd_core";
                                        regulator-min-microvolt = <1300000>;
                                        regulator-max-microvolt = <1300000>;
                                        regulator-always-on;
                                };
-                                regulator@2 {
+                                sm1 {
-                                        reg = <2>;
-                                        regulator-compatible = "sm1";
                                        regulator-name = "vdd_sm1,vdd_cpu";
                                        regulator-min-microvolt = <1125000>;
                                        regulator-max-microvolt = <1125000>;
                                        regulator-always-on;
                                };
-                                sm2_reg: regulator@3 {
+                                sm2_reg: sm2 {
-                                        reg = <3>;
-                                        regulator-compatible = "sm2";
                                        regulator-name = "vdd_sm2,vin_ldo*";
                                        regulator-min-microvolt = <3700000>;
                                        regulator-max-microvolt = <3700000>;
@@ -434,86 +423,66 @@
                                /* LDO0 is not connected to anything */
-                                regulator@5 {
+                                ldo1 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo1";
                                        regulator-name = "vdd_ldo1,avdd_pll*";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1100000>;
                                        regulator-always-on;
                                };
-                                regulator@6 {
+                                ldo2 {
-                                        reg = <6>;
-                                        regulator-compatible = "ldo2";
                                        regulator-name = "vdd_ldo2,vdd_rtc";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                regulator@7 {
+                                ldo3 {
-                                        reg = <7>;
-                                        regulator-compatible = "ldo3";
                                        regulator-name = "vdd_ldo3,avdd_usb*";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                regulator@8 {
+                                ldo4 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo4";
                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                regulator@9 {
+                                ldo5 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo5";
                                        regulator-name = "vdd_ldo5,vcore_mmc";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@10 {
+                                ldo6 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo6";
                                        regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@11 {
+                                ldo7 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo7";
                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@12 {
+                                ldo8 {
-                                        reg = <12>;
-                                        regulator-compatible = "ldo8";
                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@13 {
+                                ldo9 {
-                                        reg = <13>;
-                                        regulator-compatible = "ldo9";
                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@14 {
+                                ldo_rtc {
-                                        reg = <14>;
-                                        regulator-compatible = "ldo_rtc";
                                        regulator-name = "vdd_rtc_out,vdd_cell";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
@@ -523,12 +492,12 @@
                };
                temperature-sensor@4c {
-                        compatible = "nct1008";
+                        compatible = "onnn,nct1008";
                        reg = <0x4c>;
                };
                magnetometer@c {
-                        compatible = "ak8975";
+                        compatible = "ak,ak8975";
                        reg = <0xc>;
                        interrupt-parent = <&gpio>;
                        interrupts = <109 0x04>; /* gpio PN5 */
@@ -592,6 +561,12 @@
                status = "okay";
        };
+        sdhci@c8000000 {
+                status = "okay";
+                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                bus-width = <4>;
+        };
        sdhci@c8000400 {
                status = "okay";
                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index f18cec9f6a77..a239ccdfaa52 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -8,6 +8,16 @@
                reg = <0x00000000 0x20000000>;
        };
+        host1x {
+                hdmi {
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
        pinmux {
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
@@ -62,10 +72,6 @@
                                nvidia,pins = "dap4";
                                nvidia,function = "dap4";
                        };
-                        ddc {
-                                nvidia,pins = "ddc";
-                                nvidia,function = "i2c2";
-                        };
                        dta {
                                nvidia,pins = "dta", "dtd";
                                nvidia,function = "sdio2";
@@ -91,7 +97,7 @@
                                nvidia,function = "pcie";
                        };
                        hdint {
-                                nvidia,pins = "hdint", "pta";
+                                nvidia,pins = "hdint";
                                nvidia,function = "hdmi";
                        };
                        i2cp {
@@ -230,6 +236,39 @@
                                nvidia,pull = <1>;
                        };
                };
+                state_i2cmux_ddc: pinmux_i2cmux_ddc {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
+                };
+                state_i2cmux_pta: pinmux_i2cmux_pta {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "i2c2";
+                        };
+                };
+                state_i2cmux_idle: pinmux_i2cmux_idle {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
+                };
        };
        i2s@70002800 {
@@ -246,6 +285,36 @@
                status = "okay";
        };
+        i2c@7000c400 {
+                clock-frequency = <100000>;
+                status = "okay";
+        };
+        i2cmux {
+                compatible = "i2c-mux-pinctrl";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                i2c-parent = <&{/i2c@7000c400}>;
+                pinctrl-names = "ddc", "pta", "idle";
+                pinctrl-0 = <&state_i2cmux_ddc>;
+                pinctrl-1 = <&state_i2cmux_pta>;
+                pinctrl-2 = <&state_i2cmux_idle>;
+                hdmi_ddc: i2c@0 {
+                        reg = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                i2c@1 {
+                        reg = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
        i2c@7000d000 {
                clock-frequency = <400000>;
                status = "okay";
@@ -271,97 +340,72 @@
                        vinldo9-supply = <&sm2_reg>;
                        regulators {
-                                #address-cells = <1>;
+                                sys_reg: sys {
-                                #size-cells = <0>;
-                                sys_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "sys";
                                        regulator-name = "vdd_sys";
                                        regulator-always-on;
                                };
-                                regulator@1 {
+                                sm0 {
-                                        reg = <1>;
-                                        regulator-compatible = "sm0";
                                        regulator-name = "vdd_sys_sm0,vdd_core";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                regulator@2 {
+                                sm1 {
-                                        reg = <2>;
-                                        regulator-compatible = "sm1";
                                        regulator-name = "vdd_sys_sm1,vdd_cpu";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
                                        regulator-always-on;
                                };
-                                sm2_reg: regulator@3 {
+                                sm2_reg: sm2 {
-                                        reg = <3>;
-                                        regulator-compatible = "sm2";
                                        regulator-name = "vdd_sys_sm2,vin_ldo*";
                                        regulator-min-microvolt = <3700000>;
                                        regulator-max-microvolt = <3700000>;
                                        regulator-always-on;
                                };
-                                regulator@4 {
+                                ldo0 {
-                                        reg = <4>;
-                                        regulator-compatible = "ldo0";
                                        regulator-name = "vdd_ldo0,vddio_pex_clk";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@5 {
+                                ldo1 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo1";
                                        regulator-name = "vdd_ldo1,avdd_pll*";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1100000>;
                                        regulator-always-on;
                                };
-                                regulator@6 {
+                                ldo2 {
-                                        reg = <6>;
-                                        regulator-compatible = "ldo2";
                                        regulator-name = "vdd_ldo2,vdd_rtc";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                regulator@7 {
+                                ldo3 {
-                                        reg = <7>;
-                                        regulator-compatible = "ldo3";
                                        regulator-name = "vdd_ldo3,avdd_usb*";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                regulator@8 {
+                                ldo4 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo4";
                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                regulator@9 {
+                                ldo5 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo5";
                                        regulator-name = "vdd_ldo5,vcore_mmc";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                };
-                                regulator@10 {
+                                ldo6 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo6";
                                        regulator-name = "vdd_ldo6,avdd_vdac";
                                        /*
                                         * According to the Tegra 2 Automotive
@@ -373,25 +417,19 @@
                                        regulator-max-microvolt = <2850000>;
                                };
-                                regulator@11 {
+                                hdmi_vdd_reg: ldo7 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo7";
                                        regulator-name = "vdd_ldo7,avdd_hdmi";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@12 {
+                                hdmi_pll_reg: ldo8 {
-                                        reg = <12>;
-                                        regulator-compatible = "ldo8";
                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@13 {
+                                ldo9 {
-                                        reg = <13>;
-                                        regulator-compatible = "ldo9";
                                        regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
                                        /*
                                         * According to the Tegra 2 Automotive
@@ -404,9 +442,7 @@
                                        regulator-always-on;
                                };
-                                regulator@14 {
+                                ldo_rtc {
-                                        reg = <14>;
-                                        regulator-compatible = "ldo_rtc";
                                        regulator-name = "vdd_rtc_out";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
@@ -414,6 +450,11 @@
                                };
                        };
                };
+                temperature-sensor@4c {
+                        compatible = "onnn,nct1008";
+                        reg = <0x4c>;
+                };
        };
        pmc {
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 9aff31b0fe4a..402b21004bef 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,10 +6,13 @@
        model = "Avionic Design Tamonten Evaluation Carrier";
        compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
-        i2c@7000c000 {
+        host1x {
-                clock-frequency = <400000>;
+                hdmi {
-                status = "okay";
+                        status = "okay";
+                };
+        };
+        i2c@7000c000 {
                wm8903: wm8903@1a {
                        compatible = "wlf,wm8903";
                        reg = <0x1a>;
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 27fb8a67ea42..b70b4cb754c8 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -10,6 +10,18 @@
                reg = <0x00000000 0x40000000>;
        };
+        host1x {
+                hdmi {
+                        status = "okay";
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
        pinmux {
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
@@ -249,14 +261,24 @@
                clock-frequency = <216000000>;
        };
-        i2c@7000c000 {
+        dvi_ddc: i2c@7000c000 {
                status = "okay";
-                clock-frequency = <400000>;
+                clock-frequency = <100000>;
        };
-        i2c@7000c400 {
+        spi@7000c380 {
                status = "okay";
-                clock-frequency = <400000>;
+                spi-max-frequency = <48000000>;
+                spi-flash@0 {
+                        compatible = "winbond,w25q80bl";
+                        reg = <0>;
+                        spi-max-frequency = <48000000>;
+                };
+        };
+        hdmi_ddc: i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
        };
        i2c@7000c500 {
@@ -300,6 +322,30 @@
                bus-width = <4>;
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                hdmi_vdd_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "avdd_hdmi";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                hdmi_pll_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "avdd_hdmi_pll";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+        };
        sound {
                compatible = "nvidia,tegra-audio-trimslice";
                nvidia,i2s-controller = <&tegra_i2s1>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 3e5952fcfbc5..adc47547eaae 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -64,11 +64,6 @@
                                nvidia,pins = "dap4";
                                nvidia,function = "dap4";
                        };
-                        ddc {
-                                nvidia,pins = "ddc", "owc", "spdi", "spdo",
-                                        "uac";
-                                nvidia,function = "rsvd2";
-                        };
                        dta {
                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
                                nvidia,function = "vi";
@@ -98,7 +93,7 @@
                                nvidia,function = "pcie";
                        };
                        hdint {
-                                nvidia,pins = "hdint", "pta";
+                                nvidia,pins = "hdint";
                                nvidia,function = "hdmi";
                        };
                        i2cp {
@@ -129,6 +124,10 @@
                                        "lspi", "lvp1", "lvs";
                                nvidia,function = "displaya";
                        };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
                        pmc {
                                nvidia,pins = "pmc";
                                nvidia,function = "pwr_on";
@@ -237,6 +236,49 @@
                                        "ld23_22";
                                nvidia,pull = <1>;
                        };
+                        drive_sdio1 {
+                                nvidia,pins = "drive_sdio1";
+                                nvidia,high-speed-mode = <0>;
+                                nvidia,schmitt = <1>;
+                                nvidia,low-power-mode = <3>;
+                                nvidia,pull-down-strength = <31>;
+                                nvidia,pull-up-strength = <31>;
+                                nvidia,slew-rate-rising = <3>;
+                                nvidia,slew-rate-falling = <3>;
+                        };
+                };
+                state_i2cmux_ddc: pinmux_i2cmux_ddc {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
+                };
+                state_i2cmux_pta: pinmux_i2cmux_pta {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "i2c2";
+                        };
+                };
+                state_i2cmux_idle: pinmux_i2cmux_idle {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
                };
        };
@@ -281,6 +323,31 @@
                clock-frequency = <400000>;
        };
+        i2cmux {
+                compatible = "i2c-mux-pinctrl";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                i2c-parent = <&{/i2c@7000c400}>;
+                pinctrl-names = "ddc", "pta", "idle";
+                pinctrl-0 = <&state_i2cmux_ddc>;
+                pinctrl-1 = <&state_i2cmux_pta>;
+                pinctrl-2 = <&state_i2cmux_idle>;
+                i2c@0 {
+                        reg = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                i2c@1 {
+                        reg = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
        i2c@7000c500 {
                status = "okay";
                clock-frequency = <400000>;
@@ -311,37 +378,26 @@
                        vinldo9-supply = <&sm2_reg>;
                        regulators {
-                                #address-cells = <1>;
+                                sys_reg: sys {
-                                #size-cells = <0>;
-                                sys_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "sys";
                                        regulator-name = "vdd_sys";
                                        regulator-always-on;
                                };
-                                regulator@1 {
+                                sm0 {
-                                        reg = <1>;
-                                        regulator-compatible = "sm0";
                                        regulator-name = "vdd_sm0,vdd_core";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                regulator@2 {
+                                sm1 {
-                                        reg = <2>;
-                                        regulator-compatible = "sm1";
                                        regulator-name = "vdd_sm1,vdd_cpu";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
                                        regulator-always-on;
                                };
-                                sm2_reg: regulator@3 {
+                                sm2_reg: sm2 {
-                                        reg = <3>;
-                                        regulator-compatible = "sm2";
                                        regulator-name = "vdd_sm2,vin_ldo*";
                                        regulator-min-microvolt = <3700000>;
                                        regulator-max-microvolt = <3700000>;
@@ -350,86 +406,66 @@
                                /* LDO0 is not connected to anything */
-                                regulator@5 {
+                                ldo1 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo1";
                                        regulator-name = "vdd_ldo1,avdd_pll*";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1100000>;
                                        regulator-always-on;
                                };
-                                regulator@6 {
+                                ldo2 {
-                                        reg = <6>;
-                                        regulator-compatible = "ldo2";
                                        regulator-name = "vdd_ldo2,vdd_rtc";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                regulator@7 {
+                                ldo3 {
-                                        reg = <7>;
-                                        regulator-compatible = "ldo3";
                                        regulator-name = "vdd_ldo3,avdd_usb*";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                regulator@8 {
+                                ldo4 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo4";
                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                regulator@9 {
+                                ldo5 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo5";
                                        regulator-name = "vdd_ldo5,vcore_mmc";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@10 {
+                                ldo6 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo6";
                                        regulator-name = "vdd_ldo6,avdd_vdac";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@11 {
+                                ldo7 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo7";
                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@12 {
+                                ldo8 {
-                                        reg = <12>;
-                                        regulator-compatible = "ldo8";
                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@13 {
+                                ldo9 {
-                                        reg = <13>;
-                                        regulator-compatible = "ldo9";
                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
                                        regulator-always-on;
                                };
-                                regulator@14 {
+                                ldo_rtc {
-                                        reg = <14>;
-                                        regulator-compatible = "ldo_rtc";
                                        regulator-name = "vdd_rtc_out,vdd_cell";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
@@ -437,6 +473,11 @@
                                };
                        };
                };
+                temperature-sensor@4c {
+                        compatible = "onnn,nct1008";
+                        reg = <0x4c>;
+                };
        };
        pmc {
@@ -456,6 +497,12 @@
                status = "okay";
        };
+        sdhci@c8000000 {
+                status = "okay";
+                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                bus-width = <4>;
+        };
        sdhci@c8000400 {
                status = "okay";
                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index c636d002d6d8..20d576ecd555 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -10,6 +10,18 @@
                reg = <0x00000000 0x20000000>;
        };
+        host1x {
+                hdmi {
+                        status = "okay";
+                        vdd-supply = <&hdmi_vdd_reg>;
+                        pll-supply = <&hdmi_pll_reg>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                };
+        };
        pinmux {
                pinctrl-names = "default";
                pinctrl-0 = <&state_default>;
@@ -246,6 +258,11 @@
                clock-frequency = <216000000>;
        };
+        hdmi_ddc: i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
        i2c@7000d000 {
                status = "okay";
                clock-frequency = <100000>;
@@ -295,243 +312,182 @@
                        in20-supply = <&mbatt_reg>;
                        regulators {
-                                #address-cells = <1>;
+                                mbatt_reg: mbatt {
-                                #size-cells = <0>;
-                                mbatt_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "mbatt";
                                        regulator-name = "vbat_pmu";
                                        regulator-always-on;
                                };
-                                regulator@1 {
+                                sd1 {
-                                        reg = <1>;
-                                        regulator-compatible = "sd1";
                                        regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
                                        regulator-always-on;
                                };
-                                regulator@2 {
+                                sd2 {
-                                        reg = <2>;
-                                        regulator-compatible = "sd2";
                                        regulator-name = "nvvdd_sv2,vdd_core";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                nvvdd_sv3_reg: regulator@3 {
+                                nvvdd_sv3_reg: sd3 {
-                                        reg = <3>;
-                                        regulator-compatible = "sd3";
                                        regulator-name = "nvvdd_sv3";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                regulator@4 {
+                                ldo1 {
-                                        reg = <4>;
-                                        regulator-compatible = "ldo1";
                                        regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                regulator@5 {
+                                ldo2 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo2";
                                        regulator-name = "nvvdd_ldo2,avdd_pll*";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1100000>;
                                        regulator-always-on;
                                };
-                                regulator@6 {
+                                ldo3 {
-                                        reg = <6>;
-                                        regulator-compatible = "ldo3";
                                        regulator-name = "nvvdd_ldo3,vcom_1v8b";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                regulator@7 {
+                                ldo4 {
-                                        reg = <7>;
-                                        regulator-compatible = "ldo4";
                                        regulator-name = "nvvdd_ldo4,avdd_usb*";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                regulator@8 {
+                                ldo5 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo5";
                                        regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                        regulator-always-on;
                                };
-                                regulator@9 {
+                                hdmi_pll_reg: ldo6 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo6";
                                        regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@10 {
+                                ldo7 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo7";
                                        regulator-name = "nvvdd_ldo7,avddio_audio";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                        regulator-always-on;
                                };
-                                regulator@11 {
+                                ldo8 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo8";
                                        regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
                                        regulator-min-microvolt = <3000000>;
                                        regulator-max-microvolt = <3000000>;
                                };
-                                regulator@12 {
+                                ldo9 {
-                                        reg = <12>;
-                                        regulator-compatible = "ldo9";
                                        regulator-name = "nvvdd_ldo9,avdd_cam*";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                };
-                                regulator@13 {
+                                ldo10 {
-                                        reg = <13>;
-                                        regulator-compatible = "ldo10";
                                        regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
                                        regulator-min-microvolt = <3000000>;
                                        regulator-max-microvolt = <3000000>;
                                        regulator-always-on;
                                };
-                                regulator@14 {
+                                hdmi_vdd_reg: ldo11 {
-                                        reg = <14>;
-                                        regulator-compatible = "ldo11";
                                        regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@15 {
+                                ldo12 {
-                                        reg = <15>;
-                                        regulator-compatible = "ldo12";
                                        regulator-name = "nvvdd_ldo12,vddio_sdio";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                        regulator-always-on;
                                };
-                                regulator@16 {
+                                ldo13 {
-                                        reg = <16>;
-                                        regulator-compatible = "ldo13";
                                        regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                };
-                                regulator@17 {
+                                ldo14 {
-                                        reg = <17>;
-                                        regulator-compatible = "ldo14";
                                        regulator-name = "nvvdd_ldo14,avdd_vdac";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                };
-                                regulator@18 {
+                                ldo15 {
-                                        reg = <18>;
-                                        regulator-compatible = "ldo15";
                                        regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                };
-                                regulator@19 {
+                                ldo16 {
-                                        reg = <19>;
-                                        regulator-compatible = "ldo16";
                                        regulator-name = "nvvdd_ldo16,vdd_dbrtr";
                                        regulator-min-microvolt = <1300000>;
                                        regulator-max-microvolt = <1300000>;
                                };
-                                regulator@20 {
+                                ldo17 {
-                                        reg = <20>;
-                                        regulator-compatible = "ldo17";
                                        regulator-name = "nvvdd_ldo17,vddio_mipi";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                regulator@21 {
+                                ldo18 {
-                                        reg = <21>;
-                                        regulator-compatible = "ldo18";
                                        regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
-                                regulator@22 {
+                                ldo19 {
-                                        reg = <22>;
-                                        regulator-compatible = "ldo19";
                                        regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                };
-                                regulator@23 {
+                                ldo20 {
-                                        reg = <23>;
-                                        regulator-compatible = "ldo20";
                                        regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                regulator@24 {
+                                out5v {
-                                        reg = <24>;
-                                        regulator-compatible = "out5v";
                                        regulator-name = "usb0_vbus_reg";
                                };
-                                regulator@25 {
+                                out33v {
-                                        reg = <25>;
-                                        regulator-compatible = "out33v";
                                        regulator-name = "pmu_out3v3";
                                };
-                                regulator@26 {
+                                bbat {
-                                        reg = <26>;
-                                        regulator-compatible = "bbat";
                                        regulator-name = "pmu_bbat";
                                        regulator-min-microvolt = <2400000>;
                                        regulator-max-microvolt = <2400000>;
                                        regulator-always-on;
                                };
-                                regulator@27 {
+                                sdby {
-                                        reg = <27>;
-                                        regulator-compatible = "sdby";
                                        regulator-name = "vdd_aon";
                                        regulator-always-on;
                                };
-                                regulator@28 {
+                                vrtc {
-                                        reg = <28>;
-                                        regulator-compatible = "vrtc";
                                        regulator-name = "vrtc,pmu_vccadc";
                                        regulator-always-on;
                                };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f3a09d0d45bc..b8effa1cbda7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,108 @@
        compatible = "nvidia,tegra20";
        interrupt-parent = <&intc>;
+        host1x {
+                compatible = "nvidia,tegra20-host1x", "simple-bus";
+                reg = <0x50000000 0x00024000>;
+                interrupts = <0 65 0x04   /* mpcore syncpt */
+                              0 67 0x04>; /* mpcore general */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x54000000 0x54000000 0x04000000>;
+                mpe {
+                        compatible = "nvidia,tegra20-mpe";
+                        reg = <0x54040000 0x00040000>;
+                        interrupts = <0 68 0x04>;
+                };
+                vi {
+                        compatible = "nvidia,tegra20-vi";
+                        reg = <0x54080000 0x00040000>;
+                        interrupts = <0 69 0x04>;
+                };
+                epp {
+                        compatible = "nvidia,tegra20-epp";
+                        reg = <0x540c0000 0x00040000>;
+                        interrupts = <0 70 0x04>;
+                };
+                isp {
+                        compatible = "nvidia,tegra20-isp";
+                        reg = <0x54100000 0x00040000>;
+                        interrupts = <0 71 0x04>;
+                };
+                gr2d {
+                        compatible = "nvidia,tegra20-gr2d";
+                        reg = <0x54140000 0x00040000>;
+                        interrupts = <0 72 0x04>;
+                };
+                gr3d {
+                        compatible = "nvidia,tegra20-gr3d";
+                        reg = <0x54180000 0x00040000>;
+                };
+                dc@54200000 {
+                        compatible = "nvidia,tegra20-dc";
+                        reg = <0x54200000 0x00040000>;
+                        interrupts = <0 73 0x04>;
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+                dc@54240000 {
+                        compatible = "nvidia,tegra20-dc";
+                        reg = <0x54240000 0x00040000>;
+                        interrupts = <0 74 0x04>;
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+                hdmi {
+                        compatible = "nvidia,tegra20-hdmi";
+                        reg = <0x54280000 0x00040000>;
+                        interrupts = <0 75 0x04>;
+                        status = "disabled";
+                };
+                tvo {
+                        compatible = "nvidia,tegra20-tvo";
+                        reg = <0x542c0000 0x00040000>;
+                        interrupts = <0 76 0x04>;
+                        status = "disabled";
+                };
+                dsi {
+                        compatible = "nvidia,tegra20-dsi";
+                        reg = <0x54300000 0x00040000>;
+                        status = "disabled";
+                };
+        };
+        timer@50004600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0x50040600 0x20>;
+                interrupts = <1 13 0x304>;
+        };
+        cache-controller@50043000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x50043000 0x1000>;
+                arm,data-latency = <5 5 2>;
+                arm,tag-latency = <4 4 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000
@@ -12,6 +114,15 @@
                #interrupt-cells = <3>;
        };
+        timer@60005000 {
+                compatible = "nvidia,tegra20-timer";
+                reg = <0x60005000 0x60>;
+                interrupts = <0 0 0x04
+                              0 1 0x04
+                              0 41 0x04
+                              0 42 0x04>;
+        };
        apbdma: dma {
                compatible = "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1200>;
@@ -129,6 +240,12 @@
                #pwm-cells = <2>;
        };
+        rtc {
+                compatible = "nvidia,tegra20-rtc";
+                reg = <0x7000e000 0x100>;
+                interrupts = <0 2 0x04>;
+        };
        i2c@7000c000 {
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000c000 0x100>;
@@ -138,6 +255,16 @@
                status = "disabled";
        };
+        spi@7000c380 {
+                compatible = "nvidia,tegra20-sflash";
+                reg = <0x7000c380 0x80>;
+                interrupts = <0 39 0x04>;
+                nvidia,dma-request-selector = <&apbdma 11>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
        i2c@7000c400 {
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000c400 0x100>;
@@ -165,6 +292,46 @@
                status = "disabled";
        };
+        spi@7000d400 {
+                compatible = "nvidia,tegra20-slink";
+                reg = <0x7000d400 0x200>;
+                interrupts = <0 59 0x04>;
+                nvidia,dma-request-selector = <&apbdma 15>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000d600 {
+                compatible = "nvidia,tegra20-slink";
+                reg = <0x7000d600 0x200>;
+                interrupts = <0 82 0x04>;
+                nvidia,dma-request-selector = <&apbdma 16>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000d800 {
+                compatible = "nvidia,tegra20-slink";
+                reg = <0x7000d480 0x200>;
+                interrupts = <0 83 0x04>;
+                nvidia,dma-request-selector = <&apbdma 17>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000da00 {
+                compatible = "nvidia,tegra20-slink";
+                reg = <0x7000da00 0x200>;
+                interrupts = <0 93 0x04>;
+                nvidia,dma-request-selector = <&apbdma 18>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
        pmc {
                compatible = "nvidia,tegra20-pmc";
                reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index dd4222f00eca..adc88aa50eb6 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -83,5 +83,11 @@
                        gpio = <&gpio 83 0>; /* GPIO PK3 */
                };
        };
+        sdhci@78000400 {
+                status = "okay";
+                power-gpios = <&gpio 28 0>; /* gpio PD4 */
+                bus-width = <4>;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index 0828f097ca86..08163e145d57 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -95,4 +95,10 @@
                        gpio = <&gpio 232 0>; /* GPIO PDD0 */
                };
        };
+        sdhci@78000400 {
+                status = "okay";
+                power-gpios = <&gpio 27 0>; /* gpio PD3 */
+                bus-width = <4>;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index d10c9c5a3606..bdb2a660f376 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -52,6 +52,22 @@
                                nvidia,pull = <2>;
                                nvidia,tristate = <0>;
                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins =   "sdmmc3_cmd_pa7",
+                                                "sdmmc3_dat0_pb7",
+                                                "sdmmc3_dat1_pb6",
+                                                "sdmmc3_dat2_pb5",
+                                                "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
                        sdmmc4_clk_pcc4 {
                                nvidia,pins =   "sdmmc4_clk_pcc4",
                                                "sdmmc4_rst_n_pcc3";
@@ -81,6 +97,15 @@
                                nvidia,pull = <0>;
                                nvidia,tristate = <0>;
                        };
+                        sdio3 {
+                                nvidia,pins = "drive_sdio3";
+                                nvidia,high-speed-mode = <0>;
+                                nvidia,schmitt = <0>;
+                                nvidia,pull-down-strength = <46>;
+                                nvidia,pull-up-strength = <42>;
+                                nvidia,slew-rate-rising = <1>;
+                                nvidia,slew-rate-falling = <1>;
+                        };
                };
        };
@@ -171,56 +196,41 @@
                        vccio-supply = <&vdd_ac_bat_reg>;
                        regulators {
-                                #address-cells = <1>;
+                                vdd1_reg: vdd1 {
-                                #size-cells = <0>;
-                                vdd1_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "vdd1";
                                        regulator-name = "vddio_ddr_1v2";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                vdd2_reg: regulator@1 {
+                                vdd2_reg: vdd2 {
-                                        reg = <1>;
-                                        regulator-compatible = "vdd2";
                                        regulator-name = "vdd_1v5_gen";
                                        regulator-min-microvolt = <1500000>;
                                        regulator-max-microvolt = <1500000>;
                                        regulator-always-on;
                                };
-                                vddctrl_reg: regulator@2 {
+                                vddctrl_reg: vddctrl {
-                                        reg = <2>;
-                                        regulator-compatible = "vddctrl";
                                        regulator-name = "vdd_cpu,vdd_sys";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
                                        regulator-always-on;
                                };
-                                vio_reg: regulator@3 {
+                                vio_reg: vio {
-                                        reg = <3>;
-                                        regulator-compatible = "vio";
                                        regulator-name = "vdd_1v8_gen";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                };
-                                ldo1_reg: regulator@4 {
+                                ldo1_reg: ldo1 {
-                                        reg = <4>;
-                                        regulator-compatible = "ldo1";
                                        regulator-name = "vdd_pexa,vdd_pexb";
                                        regulator-min-microvolt = <1050000>;
                                        regulator-max-microvolt = <1050000>;
                                };
-                                ldo2_reg: regulator@5 {
+                                ldo2_reg: ldo2 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo2";
                                        regulator-name = "vdd_sata,avdd_plle";
                                        regulator-min-microvolt = <1050000>;
                                        regulator-max-microvolt = <1050000>;
@@ -228,44 +238,34 @@
                                /* LDO3 is not connected to anything */
-                                ldo4_reg: regulator@7 {
+                                ldo4_reg: ldo4 {
-                                        reg = <7>;
-                                        regulator-compatible = "ldo4";
                                        regulator-name = "vdd_rtc";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                ldo5_reg: regulator@8 {
+                                ldo5_reg: ldo5 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo5";
                                        regulator-name = "vddio_sdmmc,avdd_vdac";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                };
-                                ldo6_reg: regulator@9 {
+                                ldo6_reg: ldo6 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo6";
                                        regulator-name = "avdd_dsi_csi,pwrdet_mipi";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                ldo7_reg: regulator@10 {
+                                ldo7_reg: ldo7 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo7";
                                        regulator-name = "vdd_pllm,x,u,a_p_c_s";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                };
-                                ldo8_reg: regulator@11 {
+                                ldo8_reg: ldo8 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo8";
                                        regulator-name = "vdd_ddr_hs";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
@@ -275,6 +275,16 @@
                };
        };
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                spi-flash@1 {
+                        compatible = "winbond,w25q32";
+                        reg = <1>;
+                        spi-max-frequency = <20000000>;
+                };
+        };
        ahub {
                i2s@70080400 {
                        status = "okay";
@@ -409,6 +419,8 @@
                        regulator-name = "vdd_com";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
                        enable-active-high;
                        gpio = <&gpio 24 0>; /* gpio PD0 */
                        vin-supply = <&sys_3v3_reg>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index df7f2270fc91..529fdb82dfdb 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,108 @@
        compatible = "nvidia,tegra30";
        interrupt-parent = <&intc>;
+        host1x {
+                compatible = "nvidia,tegra30-host1x", "simple-bus";
+                reg = <0x50000000 0x00024000>;
+                interrupts = <0 65 0x04   /* mpcore syncpt */
+                              0 67 0x04>; /* mpcore general */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x54000000 0x54000000 0x04000000>;
+                mpe {
+                        compatible = "nvidia,tegra30-mpe";
+                        reg = <0x54040000 0x00040000>;
+                        interrupts = <0 68 0x04>;
+                };
+                vi {
+                        compatible = "nvidia,tegra30-vi";
+                        reg = <0x54080000 0x00040000>;
+                        interrupts = <0 69 0x04>;
+                };
+                epp {
+                        compatible = "nvidia,tegra30-epp";
+                        reg = <0x540c0000 0x00040000>;
+                        interrupts = <0 70 0x04>;
+                };
+                isp {
+                        compatible = "nvidia,tegra30-isp";
+                        reg = <0x54100000 0x00040000>;
+                        interrupts = <0 71 0x04>;
+                };
+                gr2d {
+                        compatible = "nvidia,tegra30-gr2d";
+                        reg = <0x54140000 0x00040000>;
+                        interrupts = <0 72 0x04>;
+                };
+                gr3d {
+                        compatible = "nvidia,tegra30-gr3d";
+                        reg = <0x54180000 0x00040000>;
+                };
+                dc@54200000 {
+                        compatible = "nvidia,tegra30-dc";
+                        reg = <0x54200000 0x00040000>;
+                        interrupts = <0 73 0x04>;
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+                dc@54240000 {
+                        compatible = "nvidia,tegra30-dc";
+                        reg = <0x54240000 0x00040000>;
+                        interrupts = <0 74 0x04>;
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+                hdmi {
+                        compatible = "nvidia,tegra30-hdmi";
+                        reg = <0x54280000 0x00040000>;
+                        interrupts = <0 75 0x04>;
+                        status = "disabled";
+                };
+                tvo {
+                        compatible = "nvidia,tegra30-tvo";
+                        reg = <0x542c0000 0x00040000>;
+                        interrupts = <0 76 0x04>;
+                        status = "disabled";
+                };
+                dsi {
+                        compatible = "nvidia,tegra30-dsi";
+                        reg = <0x54300000 0x00040000>;
+                        status = "disabled";
+                };
+        };
+        timer@50004600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0x50040600 0x20>;
+                interrupts = <1 13 0xf04>;
+        };
+        cache-controller@50043000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x50043000 0x1000>;
+                arm,data-latency = <6 6 2>;
+                arm,tag-latency = <5 5 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000
@@ -12,6 +114,17 @@
                #interrupt-cells = <3>;
        };
+        timer@60005000 {
+                compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+                reg = <0x60005000 0x400>;
+                interrupts = <0 0 0x04
+                              0 1 0x04
+                              0 41 0x04
+                              0 42 0x04
+                              0 121 0x04
+                              0 122 0x04>;
+        };
        apbdma: dma {
                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1400>;
@@ -123,6 +236,12 @@
                #pwm-cells = <2>;
        };
+        rtc {
+                compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
+                reg = <0x7000e000 0x100>;
+                interrupts = <0 2 0x04>;
+        };
        i2c@7000c000 {
                compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                reg = <0x7000c000 0x100>;
@@ -168,6 +287,66 @@
                status = "disabled";
        };
+        spi@7000d400 {
+                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+                reg = <0x7000d400 0x200>;
+                interrupts = <0 59 0x04>;
+                nvidia,dma-request-selector = <&apbdma 15>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000d600 {
+                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+                reg = <0x7000d600 0x200>;
+                interrupts = <0 82 0x04>;
+                nvidia,dma-request-selector = <&apbdma 16>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000d800 {
+                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+                reg = <0x7000d480 0x200>;
+                interrupts = <0 83 0x04>;
+                nvidia,dma-request-selector = <&apbdma 17>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000da00 {
+                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+                reg = <0x7000da00 0x200>;
+                interrupts = <0 93 0x04>;
+                nvidia,dma-request-selector = <&apbdma 18>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000dc00 {
+                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+                reg = <0x7000dc00 0x200>;
+                interrupts = <0 94 0x04>;
+                nvidia,dma-request-selector = <&apbdma 27>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi@7000de00 {
+                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+                reg = <0x7000de00 0x200>;
+                interrupts = <0 79 0x04>;
+                nvidia,dma-request-selector = <&apbdma 28>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
        pmc {
                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
                reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index ff000172c93c..63411b036932 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -37,6 +37,24 @@
                regulator-max-microvolt = <3150000>;
        };
+        vusb1v5: regulator-vusb1v5 {
+                compatible = "ti,twl4030-vusb1v5";
+        };
+        vusb1v8: regulator-vusb1v8 {
+                compatible = "ti,twl4030-vusb1v8";
+        };
+        vusb3v1: regulator-vusb3v1 {
+                compatible = "ti,twl4030-vusb3v1";
+        };
+        vsim: regulator-vsim {
+                compatible = "ti,twl4030-vsim";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3000000>;
+        };
        twl_gpio: gpio {
                compatible = "ti,twl4030-gpio";
                gpio-controller;
@@ -44,4 +62,13 @@
                interrupt-controller;
                #interrupt-cells = <1>;
        };
+        twl4030-usb {
+                compatible = "ti,twl4030-usb";
+                interrupts = <10>, <4>;
+                usb1v5-supply = <&vusb1v5>;
+                usb1v8-supply = <&vusb1v8>;
+                usb3v1-supply = <&vusb3v1>;
+                usb_mode = <1>;
+        };
 };
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 123e2c40218a..9996cfc5ee80 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -86,4 +86,9 @@
        clk32kg: regulator-clk32kg {
                compatible = "ti,twl6030-clk32kg";
        };
+        twl_usb_comparator: usb-comparator {
+                compatible = "ti,twl6030-usb";
+                interrupts = <4>, <10>;
+        };
 };
diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts
new file mode 100644
index 000000000000..95892ec6c342
--- /dev/null
+++ b/arch/arm/boot/dts/u9540.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "dbx5x0.dtsi"
+/ {
+        model = "ST-Ericsson U9540 platform with Device Tree";
+        compatible = "st-ericsson,u9540";
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+        soc-u9500 {
+                uart@80120000 {
+                        status = "okay";
+                };
+                uart@80121000 {
+                        status = "okay";
+                };
+                uart@80007000 {
+                        status = "okay";
+                };
+                // External Micro SD slot
+                sdi0_per1@80126000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <100000000>;
+                        bus-width = <4>;
+                        mmc-cap-sd-highspeed;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        cd-gpios  = <&gpio7 6 0x4>; // 230
+                        cd-inverted;
+                        status = "okay";
+                };
+                // WLAN SDIO channel
+                sdi1_per2@80118000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
+                        status = "okay";
+                };
+                // On-board eMMC
+                sdi4_per2@80114000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <100000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
+                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index d8a827bd2bf3..ac870fb3fa0d 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -17,17 +17,16 @@
 * CHANGES TO vexpress-v2m.dtsi!
 */
-/ {
-        aliases {
-                arm,v2m_timer = &v2m_timer01;
-        };
        motherboard {
-                compatible = "simple-bus";
+                model = "V2M-P1";
+                arm,hbi = <0x190>;
+                arm,vexpress,site = <0>;
                arm,v2m-memory-map = "rs1";
+                compatible = "arm,vexpress,v2m-p1", "simple-bus";
                #address-cells = <2>; /* SMB chipselect number and offset */
                #size-cells = <1>;
                #interrupt-cells = <1>;
+                ranges;
                flash@0,00000000 {
                        compatible = "arm,vexpress-flash", "cfi-flash";
@@ -72,14 +71,20 @@
                        #size-cells = <1>;
                        ranges = <0 3 0 0x200000>;
-                        sysreg@010000 {
+                        v2m_sysreg: sysreg@010000 {
                                compatible = "arm,vexpress-sysreg";
                                reg = <0x010000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                        };
-                        sysctl@020000 {
+                        v2m_sysctl: sysctl@020000 {
                                compatible = "arm,sp810", "arm,primecell";
                                reg = <0x020000 0x1000>;
+                                clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+                                clock-names = "refclk", "timclk", "apb_pclk";
+                                #clock-cells = <1>;
+                                clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
                        };
                        /* PCI-E I2C bus */
@@ -100,66 +105,92 @@
                                compatible = "arm,pl041", "arm,primecell";
                                reg = <0x040000 0x1000>;
                                interrupts = <11>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                        };
                        mmci@050000 {
                                compatible = "arm,pl180", "arm,primecell";
                                reg = <0x050000 0x1000>;
                                interrupts = <9 10>;
+                                cd-gpios = <&v2m_sysreg 0 0>;
+                                wp-gpios = <&v2m_sysreg 1 0>;
+                                max-frequency = <12000000>;
+                                vmmc-supply = <&v2m_fixed_3v3>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "mclk", "apb_pclk";
                        };
                        kmi@060000 {
                                compatible = "arm,pl050", "arm,primecell";
                                reg = <0x060000 0x1000>;
                                interrupts = <12>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                        };
                        kmi@070000 {
                                compatible = "arm,pl050", "arm,primecell";
                                reg = <0x070000 0x1000>;
                                interrupts = <13>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                        };
                        v2m_serial0: uart@090000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x090000 0x1000>;
                                interrupts = <5>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        v2m_serial1: uart@0a0000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0a0000 0x1000>;
                                interrupts = <6>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        v2m_serial2: uart@0b0000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0b0000 0x1000>;
                                interrupts = <7>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        v2m_serial3: uart@0c0000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0c0000 0x1000>;
                                interrupts = <8>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        wdt@0f0000 {
                                compatible = "arm,sp805", "arm,primecell";
                                reg = <0x0f0000 0x1000>;
                                interrupts = <0>;
+                                clocks = <&v2m_refclk32khz>, <&smbclk>;
+                                clock-names = "wdogclk", "apb_pclk";
                        };
                        v2m_timer01: timer@110000 {
                                compatible = "arm,sp804", "arm,primecell";
                                reg = <0x110000 0x1000>;
                                interrupts = <2>;
+                                clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                        };
                        v2m_timer23: timer@120000 {
                                compatible = "arm,sp804", "arm,primecell";
                                reg = <0x120000 0x1000>;
                                interrupts = <3>;
+                                clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                        };
                        /* DVI I2C bus */
@@ -185,6 +216,8 @@
                                compatible = "arm,pl031", "arm,primecell";
                                reg = <0x170000 0x1000>;
                                interrupts = <4>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                        };
                        compact-flash@1a0000 {
@@ -198,6 +231,8 @@
                                compatible = "arm,pl111", "arm,primecell";
                                reg = <0x1f0000 0x1000>;
                                interrupts = <14>;
+                                clocks = <&v2m_oscclk1>, <&smbclk>;
+                                clock-names = "clcdclk", "apb_pclk";
                        };
                };
@@ -208,5 +243,98 @@
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
+                v2m_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "v2m:clk24mhz";
+                };
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "v2m:refclk1mhz";
+                };
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "v2m:refclk32khz";
+                };
+                mcc {
+                        compatible = "arm,vexpress,config-bus";
+                        arm,vexpress,config-bridge = <&v2m_sysreg>;
+                        osc@0 {
+                                /* MCC static memory clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 0>;
+                                freq-range = <25000000 60000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk0";
+                        };
+                        v2m_oscclk1: osc@1 {
+                                /* CLCD clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 1>;
+                                freq-range = <23750000 63500000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk1";
+                        };
+                        v2m_oscclk2: osc@2 {
+                                /* IO FPGA peripheral clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 2>;
+                                freq-range = <24000000 24000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk2";
+                        };
+                        volt@0 {
+                                /* Logic level voltage */
+                                compatible = "arm,vexpress-volt";
+                                arm,vexpress-sysreg,func = <2 0>;
+                                regulator-name = "VIO";
+                                regulator-always-on;
+                                label = "VIO";
+                        };
+                        temp@0 {
+                                /* MCC internal operating temperature */
+                                compatible = "arm,vexpress-temp";
+                                arm,vexpress-sysreg,func = <4 0>;
+                                label = "MCC";
+                        };
+                        reset@0 {
+                                compatible = "arm,vexpress-reset";
+                                arm,vexpress-sysreg,func = <5 0>;
+                        };
+                        muxfpga@0 {
+                                compatible = "arm,vexpress-muxfpga";
+                                arm,vexpress-sysreg,func = <7 0>;
+                        };
+                        shutdown@0 {
+                                compatible = "arm,vexpress-shutdown";
+                                arm,vexpress-sysreg,func = <8 0>;
+                        };
+                        reboot@0 {
+                                compatible = "arm,vexpress-reboot";
+                                arm,vexpress-sysreg,func = <9 0>;
+                        };
+                        dvimode@0 {
+                                compatible = "arm,vexpress-dvimode";
+                                arm,vexpress-sysreg,func = <11 0>;
+                        };
+                };
        };
-};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index dba53fd026bb..f1420368355b 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -17,16 +17,15 @@
 * CHANGES TO vexpress-v2m-rs1.dtsi!
 */
-/ {
-        aliases {
-                arm,v2m_timer = &v2m_timer01;
-        };
        motherboard {
-                compatible = "simple-bus";
+                model = "V2M-P1";
+                arm,hbi = <0x190>;
+                arm,vexpress,site = <0>;
+                compatible = "arm,vexpress,v2m-p1", "simple-bus";
                #address-cells = <2>; /* SMB chipselect number and offset */
                #size-cells = <1>;
                #interrupt-cells = <1>;
+                ranges;
                flash@0,00000000 {
                        compatible = "arm,vexpress-flash", "cfi-flash";
@@ -71,14 +70,20 @@
                        #size-cells = <1>;
                        ranges = <0 7 0 0x20000>;
-                        sysreg@00000 {
+                        v2m_sysreg: sysreg@00000 {
                                compatible = "arm,vexpress-sysreg";
                                reg = <0x00000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                        };
-                        sysctl@01000 {
+                        v2m_sysctl: sysctl@01000 {
                                compatible = "arm,sp810", "arm,primecell";
                                reg = <0x01000 0x1000>;
+                                clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+                                clock-names = "refclk", "timclk", "apb_pclk";
+                                #clock-cells = <1>;
+                                clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
                        };
                        /* PCI-E I2C bus */
@@ -99,66 +104,92 @@
                                compatible = "arm,pl041", "arm,primecell";
                                reg = <0x04000 0x1000>;
                                interrupts = <11>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                        };
                        mmci@05000 {
                                compatible = "arm,pl180", "arm,primecell";
                                reg = <0x05000 0x1000>;
                                interrupts = <9 10>;
+                                cd-gpios = <&v2m_sysreg 0 0>;
+                                wp-gpios = <&v2m_sysreg 1 0>;
+                                max-frequency = <12000000>;
+                                vmmc-supply = <&v2m_fixed_3v3>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "mclk", "apb_pclk";
                        };
                        kmi@06000 {
                                compatible = "arm,pl050", "arm,primecell";
                                reg = <0x06000 0x1000>;
                                interrupts = <12>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                        };
                        kmi@07000 {
                                compatible = "arm,pl050", "arm,primecell";
                                reg = <0x07000 0x1000>;
                                interrupts = <13>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                        };
                        v2m_serial0: uart@09000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x09000 0x1000>;
                                interrupts = <5>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        v2m_serial1: uart@0a000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0a000 0x1000>;
                                interrupts = <6>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        v2m_serial2: uart@0b000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0b000 0x1000>;
                                interrupts = <7>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        v2m_serial3: uart@0c000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0c000 0x1000>;
                                interrupts = <8>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                        };
                        wdt@0f000 {
                                compatible = "arm,sp805", "arm,primecell";
                                reg = <0x0f000 0x1000>;
                                interrupts = <0>;
+                                clocks = <&v2m_refclk32khz>, <&smbclk>;
+                                clock-names = "wdogclk", "apb_pclk";
                        };
                        v2m_timer01: timer@11000 {
                                compatible = "arm,sp804", "arm,primecell";
                                reg = <0x11000 0x1000>;
                                interrupts = <2>;
+                                clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                        };
                        v2m_timer23: timer@12000 {
                                compatible = "arm,sp804", "arm,primecell";
                                reg = <0x12000 0x1000>;
                                interrupts = <3>;
+                                clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                        };
                        /* DVI I2C bus */
@@ -184,6 +215,8 @@
                                compatible = "arm,pl031", "arm,primecell";
                                reg = <0x17000 0x1000>;
                                interrupts = <4>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                        };
                        compact-flash@1a000 {
@@ -197,6 +230,8 @@
                                compatible = "arm,pl111", "arm,primecell";
                                reg = <0x1f000 0x1000>;
                                interrupts = <14>;
+                                clocks = <&v2m_oscclk1>, <&smbclk>;
+                                clock-names = "clcdclk", "apb_pclk";
                        };
                };
@@ -207,5 +242,98 @@
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
+                v2m_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "v2m:clk24mhz";
+                };
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "v2m:refclk1mhz";
+                };
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "v2m:refclk32khz";
+                };
+                mcc {
+                        compatible = "arm,vexpress,config-bus";
+                        arm,vexpress,config-bridge = <&v2m_sysreg>;
+                        osc@0 {
+                                /* MCC static memory clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 0>;
+                                freq-range = <25000000 60000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk0";
+                        };
+                        v2m_oscclk1: osc@1 {
+                                /* CLCD clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 1>;
+                                freq-range = <23750000 63500000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk1";
+                        };
+                        v2m_oscclk2: osc@2 {
+                                /* IO FPGA peripheral clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 2>;
+                                freq-range = <24000000 24000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk2";
+                        };
+                        volt@0 {
+                                /* Logic level voltage */
+                                compatible = "arm,vexpress-volt";
+                                arm,vexpress-sysreg,func = <2 0>;
+                                regulator-name = "VIO";
+                                regulator-always-on;
+                                label = "VIO";
+                        };
+                        temp@0 {
+                                /* MCC internal operating temperature */
+                                compatible = "arm,vexpress-temp";
+                                arm,vexpress-sysreg,func = <4 0>;
+                                label = "MCC";
+                        };
+                        reset@0 {
+                                compatible = "arm,vexpress-reset";
+                                arm,vexpress-sysreg,func = <5 0>;
+                        };
+                        muxfpga@0 {
+                                compatible = "arm,vexpress-muxfpga";
+                                arm,vexpress-sysreg,func = <7 0>;
+                        };
+                        shutdown@0 {
+                                compatible = "arm,vexpress-shutdown";
+                                arm,vexpress-sysreg,func = <8 0>;
+                        };
+                        reboot@0 {
+                                compatible = "arm,vexpress-reboot";
+                                arm,vexpress-sysreg,func = <9 0>;
+                        };
+                        dvimode@0 {
+                                compatible = "arm,vexpress-dvimode";
+                                arm,vexpress-sysreg,func = <11 0>;
+                        };
+                };
        };
-};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index d12b34ca0568..a3d37ec2655d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -12,6 +12,7 @@
 / {
        model = "V2P-CA15";
        arm,hbi = <0x237>;
+        arm,vexpress,site = <0xf>;
        compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
        interrupt-parent = <&gic>;
        #address-cells = <2>;
@@ -54,17 +55,24 @@
                compatible = "arm,hdlcd";
                reg = <0 0x2b000000 0 0x1000>;
                interrupts = <0 85 4>;
+                clocks = <&oscclk5>;
+                clock-names = "pxlclk";
        };
        memory-controller@2b0a0000 {
                compatible = "arm,pl341", "arm,primecell";
                reg = <0 0x2b0a0000 0 0x1000>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
        };
        wdt@2b060000 {
                compatible = "arm,sp805", "arm,primecell";
+                status = "disabled";
                reg = <0 0x2b060000 0 0x1000>;
                interrupts = <98>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
        };
        gic: interrupt-controller@2c001000 {
@@ -84,6 +92,8 @@
                reg = <0 0x7ffd0000 0 0x1000>;
                interrupts = <0 86 4>,
                             <0 87 4>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
        };
        dma@7ffb0000 {
@@ -94,6 +104,8 @@
                             <0 89 4>,
                             <0 90 4>,
                             <0 91 4>;
+                clocks = <&oscclk7>;
+                clock-names = "apb_pclk";
        };
        timer {
@@ -110,7 +122,109 @@
                             <0 69 4>;
        };
-        motherboard {
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+                osc@0 {
+                        /* CPU PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <50000000 60000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk0";
+                };
+                osc@4 {
+                        /* Multiplexed AXI master clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 4>;
+                        freq-range = <20000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk4";
+                };
+                oscclk5: osc@5 {
+                        /* HDLCD PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 5>;
+                        freq-range = <23750000 165000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk5";
+                };
+                smbclk: osc@6 {
+                        /* SMB clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 6>;
+                        freq-range = <20000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk6";
+                };
+                oscclk7: osc@7 {
+                        /* SYS PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 7>;
+                        freq-range = <20000000 60000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk7";
+                };
+                osc@8 {
+                        /* DDR2 PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 8>;
+                        freq-range = <40000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk8";
+                };
+                volt@0 {
+                        /* CPU core voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 0>;
+                        regulator-name = "Cores";
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <1050000>;
+                        regulator-always-on;
+                        label = "Cores";
+                };
+                amp@0 {
+                        /* Total current for the two cores */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 0>;
+                        label = "Cores";
+                };
+                temp@0 {
+                        /* DCC internal temperature */
+                        compatible = "arm,vexpress-temp";
+                        arm,vexpress-sysreg,func = <4 0>;
+                        label = "DCC";
+                };
+                power@0 {
+                        /* Total power */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 0>;
+                        label = "Cores";
+                };
+                energy@0 {
+                        /* Total energy */
+                        compatible = "arm,vexpress-energy";
+                        arm,vexpress-sysreg,func = <13 0>;
+                        label = "Cores";
+                };
+        };
+        smb {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
                ranges = <0 0 0 0x08000000 0x04000000>,
                         <1 0 0 0x14000000 0x04000000>,
                         <2 0 0 0x18000000 0x04000000>,
@@ -118,6 +232,7 @@
                         <4 0 0 0x0c000000 0x04000000>,
                         <5 0 0 0x10000000 0x04000000>;
+                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
                interrupt-map = <0 0  0 &gic 0  0 4>,
                                <0 0  1 &gic 0  1 4>,
@@ -162,7 +277,7 @@
                                <0 0 40 &gic 0 40 4>,
                                <0 0 41 &gic 0 41 4>,
                                <0 0 42 &gic 0 42 4>;
+                /include/ "vexpress-v2m-rs1.dtsi"
        };
 };
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 4890a81c5467..1fc405a9ecfb 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -12,6 +12,7 @@
 / {
        model = "V2P-CA15_CA7";
        arm,hbi = <0x249>;
+        arm,vexpress,site = <0xf>;
        compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
        interrupt-parent = <&gic>;
        #address-cells = <2>;
@@ -74,17 +75,23 @@
                compatible = "arm,sp805", "arm,primecell";
                reg = <0 0x2a490000 0 0x1000>;
                interrupts = <98>;
+                clocks = <&oscclk6a>, <&oscclk6a>;
+                clock-names = "wdogclk", "apb_pclk";
        };
        hdlcd@2b000000 {
                compatible = "arm,hdlcd";
                reg = <0 0x2b000000 0 0x1000>;
                interrupts = <0 85 4>;
+                clocks = <&oscclk5>;
+                clock-names = "pxlclk";
        };
        memory-controller@2b0a0000 {
                compatible = "arm,pl341", "arm,primecell";
                reg = <0 0x2b0a0000 0 0x1000>;
+                clocks = <&oscclk6a>;
+                clock-names = "apb_pclk";
        };
        gic: interrupt-controller@2c001000 {
@@ -104,6 +111,8 @@
                reg = <0 0x7ffd0000 0 0x1000>;
                interrupts = <0 86 4>,
                             <0 87 4>;
+                clocks = <&oscclk6a>;
+                clock-names = "apb_pclk";
        };
        dma@7ff00000 {
@@ -114,6 +123,8 @@
                             <0 89 4>,
                             <0 90 4>,
                             <0 91 4>;
+                clocks = <&oscclk6a>;
+                clock-names = "apb_pclk";
        };
        timer {
@@ -130,7 +141,175 @@
                             <0 69 4>;
        };
-        motherboard {
+        oscclk6a: oscclk6a {
+                /* Reference 24MHz clock */
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+                clock-output-names = "oscclk6a";
+        };
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+                osc@0 {
+                        /* A15 PLL 0 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk0";
+                };
+                osc@1 {
+                        /* A15 PLL 1 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 1>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk1";
+                };
+                osc@2 {
+                        /* A7 PLL 0 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 2>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk2";
+                };
+                osc@3 {
+                        /* A7 PLL 1 reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 3>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk3";
+                };
+                osc@4 {
+                        /* External AXI master clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 4>;
+                        freq-range = <20000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk4";
+                };
+                oscclk5: osc@5 {
+                        /* HDLCD PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 5>;
+                        freq-range = <23750000 165000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk5";
+                };
+                smbclk: osc@6 {
+                        /* Static memory controller clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 6>;
+                        freq-range = <20000000 40000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk6";
+                };
+                osc@7 {
+                        /* SYS PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 7>;
+                        freq-range = <17000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk7";
+                };
+                osc@8 {
+                        /* DDR2 PLL reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 8>;
+                        freq-range = <20000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk8";
+                };
+                volt@0 {
+                        /* A15 CPU core voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 0>;
+                        regulator-name = "A15 Vcore";
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <1050000>;
+                        regulator-always-on;
+                        label = "A15 Vcore";
+                };
+                volt@1 {
+                        /* A7 CPU core voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 1>;
+                        regulator-name = "A7 Vcore";
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <1050000>;
+                        regulator-always-on;
+                        label = "A7 Vcore";
+                };
+                amp@0 {
+                        /* Total current for the two A15 cores */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 0>;
+                        label = "A15 Icore";
+                };
+                amp@1 {
+                        /* Total current for the three A7 cores */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 1>;
+                        label = "A7 Icore";
+                };
+                temp@0 {
+                        /* DCC internal temperature */
+                        compatible = "arm,vexpress-temp";
+                        arm,vexpress-sysreg,func = <4 0>;
+                        label = "DCC";
+                };
+                power@0 {
+                        /* Total power for the two A15 cores */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 0>;
+                        label = "A15 Pcore";
+                };
+                power@1 {
+                        /* Total power for the three A7 cores */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 1>;
+                        label = "A7 Pcore";
+                };
+                energy@0 {
+                        /* Total energy for the two A15 cores */
+                        compatible = "arm,vexpress-energy";
+                        arm,vexpress-sysreg,func = <13 0>;
+                        label = "A15 Jcore";
+                };
+                energy@2 {
+                        /* Total energy for the three A7 cores */
+                        compatible = "arm,vexpress-energy";
+                        arm,vexpress-sysreg,func = <13 2>;
+                        label = "A7 Jcore";
+                };
+        };
+        smb {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
                ranges = <0 0 0 0x08000000 0x04000000>,
                         <1 0 0 0x14000000 0x04000000>,
                         <2 0 0 0x18000000 0x04000000>,
@@ -138,6 +317,7 @@
                         <4 0 0 0x0c000000 0x04000000>,
                         <5 0 0 0x10000000 0x04000000>;
+                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
                interrupt-map = <0 0  0 &gic 0  0 4>,
                                <0 0  1 &gic 0  1 4>,
@@ -182,7 +362,7 @@
                                <0 0 40 &gic 0 40 4>,
                                <0 0 41 &gic 0 41 4>,
                                <0 0 42 &gic 0 42 4>;
+                /include/ "vexpress-v2m-rs1.dtsi"
        };
 };
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 18917a0f8604..6328cbc71d30 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -12,6 +12,7 @@
 / {
        model = "V2P-CA5s";
        arm,hbi = <0x225>;
+        arm,vexpress,site = <0xf>;
        compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
        interrupt-parent = <&gic>;
        #address-cells = <1>;
@@ -56,11 +57,15 @@
                compatible = "arm,hdlcd";
                reg = <0x2a110000 0x1000>;
                interrupts = <0 85 4>;
+                clocks = <&oscclk3>;
+                clock-names = "pxlclk";
        };
        memory-controller@2a150000 {
                compatible = "arm,pl341", "arm,primecell";
                reg = <0x2a150000 0x1000>;
+                clocks = <&oscclk1>;
+                clock-names = "apb_pclk";
        };
        memory-controller@2a190000 {
@@ -68,6 +73,8 @@
                reg = <0x2a190000 0x1000>;
                interrupts = <0 86 4>,
                             <0 87 4>;
+                clocks = <&oscclk1>;
+                clock-names = "apb_pclk";
        };
        scu@2c000000 {
@@ -109,7 +116,77 @@
                             <0 69 4>;
        };
-        motherboard {
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+                osc@0 {
+                        /* CPU and internal AXI reference clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <50000000 100000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk0";
+                };
+                oscclk1: osc@1 {
+                        /* Multiplexed AXI master clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 1>;
+                        freq-range = <5000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk1";
+                };
+                osc@2 {
+                        /* DDR2 */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 2>;
+                        freq-range = <80000000 120000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk2";
+                };
+                oscclk3: osc@3 {
+                        /* HDLCD */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 3>;
+                        freq-range = <23750000 165000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk3";
+                };
+                osc@4 {
+                        /* Test chip gate configuration */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 4>;
+                        freq-range = <80000000 80000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk4";
+                };
+                smbclk: osc@5 {
+                        /* SMB clock */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 5>;
+                        freq-range = <25000000 60000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "oscclk5";
+                };
+                temp@0 {
+                        /* DCC internal operating temperature */
+                        compatible = "arm,vexpress-temp";
+                        arm,vexpress-sysreg,func = <4 0>;
+                        label = "DCC";
+                };
+        };
+        smb {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
                ranges = <0 0 0x08000000 0x04000000>,
                         <1 0 0x14000000 0x04000000>,
                         <2 0 0x18000000 0x04000000>,
@@ -117,6 +194,7 @@
                         <4 0 0x0c000000 0x04000000>,
                         <5 0 0x10000000 0x04000000>;
+                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
                interrupt-map = <0 0  0 &gic 0  0 4>,
                                <0 0  1 &gic 0  1 4>,
@@ -161,7 +239,7 @@
                                <0 0 40 &gic 0 40 4>,
                                <0 0 41 &gic 0 41 4>,
                                <0 0 42 &gic 0 42 4>;
+                /include/ "vexpress-v2m-rs1.dtsi"
        };
 };
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 3f0c736d31d6..1420bb14d95c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -12,6 +12,7 @@
 / {
        model = "V2P-CA9";
        arm,hbi = <0x191>;
+        arm,vexpress,site = <0xf>;
        compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
        interrupt-parent = <&gic>;
        #address-cells = <1>;
@@ -70,11 +71,15 @@
                compatible = "arm,pl111", "arm,primecell";
                reg = <0x10020000 0x1000>;
                interrupts = <0 44 4>;
+                clocks = <&oscclk1>, <&oscclk2>;
+                clock-names = "clcdclk", "apb_pclk";
        };
        memory-controller@100e0000 {
                compatible = "arm,pl341", "arm,primecell";
                reg = <0x100e0000 0x1000>;
+                clocks = <&oscclk2>;
+                clock-names = "apb_pclk";
        };
        memory-controller@100e1000 {
@@ -82,6 +87,8 @@
                reg = <0x100e1000 0x1000>;
                interrupts = <0 45 4>,
                             <0 46 4>;
+                clocks = <&oscclk2>;
+                clock-names = "apb_pclk";
        };
        timer@100e4000 {
@@ -89,12 +96,16 @@
                reg = <0x100e4000 0x1000>;
                interrupts = <0 48 4>,
                             <0 49 4>;
+                clocks = <&oscclk2>, <&oscclk2>;
+                clock-names = "timclk", "apb_pclk";
        };
        watchdog@100e5000 {
                compatible = "arm,sp805", "arm,primecell";
                reg = <0x100e5000 0x1000>;
                interrupts = <0 51 4>;
+                clocks = <&oscclk2>, <&oscclk2>;
+                clock-names = "wdogclk", "apb_pclk";
        };
        scu@1e000000 {
@@ -140,13 +151,132 @@
                             <0 63 4>;
        };
-        motherboard {
+        dcc {
+                compatible = "arm,vexpress,config-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+                osc@0 {
+                        /* ACLK clock to the AXI master port on the test chip */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                        freq-range = <30000000 50000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "extsaxiclk";
+                };
+                oscclk1: osc@1 {
+                        /* Reference clock for the CLCD */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 1>;
+                        freq-range = <10000000 80000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "clcdclk";
+                };
+                smbclk: oscclk2: osc@2 {
+                        /* Reference clock for the test chip internal PLLs */
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 2>;
+                        freq-range = <33000000 100000000>;
+                        #clock-cells = <0>;
+                        clock-output-names = "tcrefclk";
+                };
+                volt@0 {
+                        /* Test Chip internal logic voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 0>;
+                        regulator-name = "VD10";
+                        regulator-always-on;
+                        label = "VD10";
+                };
+                volt@1 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 1>;
+                        regulator-name = "VD10_S2";
+                        regulator-always-on;
+                        label = "VD10_S2";
+                };
+                volt@2 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 2>;
+                        regulator-name = "VD10_S3";
+                        regulator-always-on;
+                        label = "VD10_S3";
+                };
+                volt@3 {
+                        /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 3>;
+                        regulator-name = "VCC1V8";
+                        regulator-always-on;
+                        label = "VCC1V8";
+                };
+                volt@4 {
+                        /* DDR2 SDRAM VTT termination voltage */
+                        compatible = "arm,vexpress-volt";
+                        arm,vexpress-sysreg,func = <2 4>;
+                        regulator-name = "DDR2VTT";
+                        regulator-always-on;
+                        label = "DDR2VTT";
+                };
+                volt@5 {
+                        /* Local board supply for miscellaneous logic external to the Test Chip */
+                        arm,vexpress-sysreg,func = <2 5>;
+                        compatible = "arm,vexpress-volt";
+                        regulator-name = "VCC3V3";
+                        regulator-always-on;
+                        label = "VCC3V3";
+                };
+                amp@0 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 0>;
+                        label = "VD10_S2";
+                };
+                amp@1 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-amp";
+                        arm,vexpress-sysreg,func = <3 1>;
+                        label = "VD10_S3";
+                };
+                power@0 {
+                        /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 0>;
+                        label = "PVD10_S2";
+                };
+                power@1 {
+                        /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+                        compatible = "arm,vexpress-power";
+                        arm,vexpress-sysreg,func = <12 1>;
+                        label = "PVD10_S3";
+                };
+        };
+        smb {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
                ranges = <0 0 0x40000000 0x04000000>,
                         <1 0 0x44000000 0x04000000>,
                         <2 0 0x48000000 0x04000000>,
                         <3 0 0x4c000000 0x04000000>,
                         <7 0 0x10000000 0x00020000>;
+                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
                interrupt-map = <0 0  0 &gic 0  0 4>,
                                <0 0  1 &gic 0  1 4>,
@@ -191,7 +321,7 @@
                                <0 0 40 &gic 0 40 4>,
                                <0 0 41 &gic 0 41 4>,
                                <0 0 42 &gic 0 42 4>;
+                /include/ "vexpress-v2m.dtsi"
        };
 };
-/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
new file mode 100644
index 000000000000..401c1262d4ed
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -0,0 +1,166 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "xlnx,zynq-7000";
+        amba {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&intc>;
+                ranges;
+                intc: interrupt-controller@f8f01000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        reg = <0xF8F01000 0x1000>,
+                              <0xF8F00100 0x100>;
+                };
+                L2: cache-controller {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xF8F02000 0x1000>;
+                        arm,data-latency = <2 3 2>;
+                        arm,tag-latency = <2 3 2>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+                uart0: uart@e0000000 {
+                        compatible = "xlnx,xuartps";
+                        reg = <0xE0000000 0x1000>;
+                        interrupts = <0 27 4>;
+                        clock = <50000000>;
+                };
+                uart1: uart@e0001000 {
+                        compatible = "xlnx,xuartps";
+                        reg = <0xE0001000 0x1000>;
+                        interrupts = <0 50 4>;
+                        clock = <50000000>;
+                };
+                slcr: slcr@f8000000 {
+                        compatible = "xlnx,zynq-slcr";
+                        reg = <0xF8000000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ps_clk: ps_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        /* clock-frequency set in board-specific file */
+                                        clock-output-names = "ps_clk";
+                                };
+                                armpll: armpll {
+                                        #clock-cells = <0>;
+                                        compatible = "xlnx,zynq-pll";
+                                        clocks = <&ps_clk>;
+                                        reg = <0x100 0x110>;
+                                        clock-output-names = "armpll";
+                                };
+                                ddrpll: ddrpll {
+                                        #clock-cells = <0>;
+                                        compatible = "xlnx,zynq-pll";
+                                        clocks = <&ps_clk>;
+                                        reg = <0x104 0x114>;
+                                        clock-output-names = "ddrpll";
+                                };
+                                iopll: iopll {
+                                        #clock-cells = <0>;
+                                        compatible = "xlnx,zynq-pll";
+                                        clocks = <&ps_clk>;
+                                        reg = <0x108 0x118>;
+                                        clock-output-names = "iopll";
+                                };
+                                uart_clk: uart_clk {
+                                        #clock-cells = <1>;
+                                        compatible = "xlnx,zynq-periph-clock";
+                                        clocks = <&iopll &armpll &ddrpll>;
+                                        reg = <0x154>;
+                                        clock-output-names = "uart0_ref_clk",
+                                                             "uart1_ref_clk";
+                                };
+                                cpu_clk: cpu_clk {
+                                        #clock-cells = <1>;
+                                        compatible = "xlnx,zynq-cpu-clock";
+                                        clocks = <&iopll &armpll &ddrpll>;
+                                        reg = <0x120 0x1C4>;
+                                        clock-output-names = "cpu_6x4x",
+                                                             "cpu_3x2x",
+                                                             "cpu_2x",
+                                                             "cpu_1x";
+                                };
+                        };
+                };
+                ttc0: ttc0@f8001000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "xlnx,ttc";
+                        reg = <0xF8001000 0x1000>;
+                        clocks = <&cpu_clk 3>;
+                        clock-names = "cpu_1x";
+                        clock-ranges;
+                        ttc0_0: ttc0.0 {
+                                status = "disabled";
+                                reg = <0>;
+                                interrupts = <0 10 4>;
+                        };
+                        ttc0_1: ttc0.1 {
+                                status = "disabled";
+                                reg = <1>;
+                                interrupts = <0 11 4>;
+                        };
+                        ttc0_2: ttc0.2 {
+                                status = "disabled";
+                                reg = <2>;
+                                interrupts = <0 12 4>;
+                        };
+                };
+                ttc1: ttc1@f8002000 {
+                        #interrupt-parent = <&intc>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "xlnx,ttc";
+                        reg = <0xF8002000 0x1000>;
+                        clocks = <&cpu_clk 3>;
+                        clock-names = "cpu_1x";
+                        clock-ranges;
+                        ttc1_0: ttc1.0 {
+                                status = "disabled";
+                                reg = <0>;
+                                interrupts = <0 37 4>;
+                        };
+                        ttc1_1: ttc1.1 {
+                                status = "disabled";
+                                reg = <1>;
+                                interrupts = <0 38 4>;
+                        };
+                        ttc1_2: ttc1.2 {
+                                status = "disabled";
+                                reg = <2>;
+                                interrupts = <0 39 4>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
deleted file mode 100644
index 37ca192fb193..000000000000
--- a/arch/arm/boot/dts/zynq-ep107.dts
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-/dts-v1/;
-/ {
-        model = "Xilinx Zynq EP107";
-        compatible = "xlnx,zynq-ep107";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&intc>;
-        memory {
-                device_type = "memory";
-                reg = <0x0 0x10000000>;
-        };
-        chosen {
-                bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
-                linux,stdout-path = &uart0;
-        };
-        amba {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-                intc: interrupt-controller@f8f01000 {
-                        interrupt-controller;
-                        compatible = "arm,gic";
-                        reg = <0xF8F01000 0x1000>;
-                        #interrupt-cells = <2>;
-                };
-                uart0: uart@e0000000 {
-                        compatible = "xlnx,xuartps";
-                        reg = <0xE0000000 0x1000>;
-                        interrupts = <59 0>;
-                        clock = <50000000>;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
new file mode 100644
index 000000000000..c772942a399a
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -0,0 +1,44 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/ {
+        model = "Zynq ZC702 Development Board";
+        compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+        chosen {
+                bootargs = "console=ttyPS1,115200 earlyprintk";
+        };
+};
+&ps_clk {
+        clock-frequency = <33333330>;
+};
+&ttc0_0 {
+        status = "ok";
+        compatible = "xlnx,ttc-counter-clocksource";
+};
+&ttc0_1 {
+        status = "ok";
+        compatible = "xlnx,ttc-counter-clockevent";
+};
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index aa5269984187..36ae03a3f5d1 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -70,6 +70,14 @@ struct gic_chip_data {
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 /*
+ * The GIC mapping of CPU interfaces does not necessarily match
+ * the logical CPU numbering.  Let's use a mapping as returned
+ * by the GIC itself.
+ */
+#define NR_GIC_CPU_IF 8
+static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+/*
 * Supported arch specific GIC irq extension.
 * Default make them NULL.
 */
@@ -238,11 +246,11 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
        unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
        u32 val, mask, bit;
-        if (cpu >= 8 || cpu >= nr_cpu_ids)
+        if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
                return -EINVAL;
        mask = 0xff << shift;
-        bit = 1 << (cpu_logical_map(cpu) + shift);
+        bit = gic_cpu_map[cpu] << shift;
        raw_spin_lock(&irq_controller_lock);
        val = readl_relaxed(reg) & ~mask;
@@ -349,11 +357,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
        u32 cpumask;
        unsigned int gic_irqs = gic->gic_irqs;
        void __iomem *base = gic_data_dist_base(gic);
-        u32 cpu = cpu_logical_map(smp_processor_id());
-        cpumask = 1 << cpu;
-        cpumask |= cpumask << 8;
-        cpumask |= cpumask << 16;
        writel_relaxed(0, base + GIC_DIST_CTRL);
@@ -366,6 +369,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
        /*
         * Set all global interrupts to this CPU only.
         */
+        cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
        for (i = 32; i < gic_irqs; i += 4)
                writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
@@ -389,9 +393,25 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 {
        void __iomem *dist_base = gic_data_dist_base(gic);
        void __iomem *base = gic_data_cpu_base(gic);
+        unsigned int cpu_mask, cpu = smp_processor_id();
        int i;
        /*
+         * Get what the GIC says our CPU mask is.
+         */
+        BUG_ON(cpu >= NR_GIC_CPU_IF);
+        cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
+        gic_cpu_map[cpu] = cpu_mask;
+        /*
+         * Clear our mask from the other map entries in case they're
+         * still undefined.
+         */
+        for (i = 0; i < NR_GIC_CPU_IF; i++)
+                if (i != cpu)
+                        gic_cpu_map[i] &= ~cpu_mask;
+        /*
         * Deal with the banked PPI and SGI interrupts - disable all
         * PPI interrupts, ensure all SGI interrupts are enabled.
         */
@@ -646,7 +666,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 {
        irq_hw_number_t hwirq_base;
        struct gic_chip_data *gic;
-        int gic_irqs, irq_base;
+        int gic_irqs, irq_base, i;
        BUG_ON(gic_nr >= MAX_GIC_NR);
@@ -683,6 +703,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
        }
        /*
+         * Initialize the CPU interface map to all CPUs.
+         * It will be refined as each CPU probes its ID.
+         */
+        for (i = 0; i < NR_GIC_CPU_IF; i++)
+                gic_cpu_map[i] = 0xff;
+        /*
         * For primary GICs, skip over SGIs.
         * For secondary GICs, skip over PPIs, too.
         */
@@ -737,7 +764,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
        /* Convert our logical CPU mask into a physical one. */
        for_each_cpu(cpu, mask)
-                map |= 1 << cpu_logical_map(cpu);
+                map |= gic_cpu_map[cpu];
        /*
         * Ensure that stores to Normal memory are visible to the
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index df13a3ffff35..9d2d3ba339ff 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -162,7 +162,6 @@ static struct clock_event_device sp804_clockevent = {
        .set_mode       = sp804_set_mode,
        .set_next_event = sp804_set_next_event,
        .rating         = 300,
-        .cpumask        = cpu_all_mask,
 };
 static struct irqaction sp804_timer_irq = {
@@ -185,6 +184,7 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
        clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
        evt->name = name;
        evt->irq = irq;
+        evt->cpumask = cpu_possible_mask;
        setup_irq(irq, &sp804_timer_irq);
        clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index e0d538803cc3..e4df17ca90c7 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -218,7 +218,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
        v->resume_sources = resume_sources;
        v->irq = irq;
        vic_id++;
-        v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0,
+        v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
                                          &vic_irqdomain_ops, v);
 }
@@ -350,7 +350,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
        vic_register(base, irq_start, vic_sources, 0, node);
 }
-void __init __vic_init(void __iomem *base, unsigned int irq_start,
+void __init __vic_init(void __iomem *base, int irq_start,
                              u32 vic_sources, u32 resume_sources,
                              struct device_node *node)
 {
@@ -407,7 +407,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 int __init vic_of_init(struct device_node *node, struct device_node *parent)
 {
        void __iomem *regs;
-        int irq_base;
        if (WARN(parent, "non-root VICs are not supported"))
                return -EINVAL;
@@ -416,18 +415,12 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
        if (WARN_ON(!regs))
                return -EIO;
-        irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+        /*
-        if (WARN_ON(irq_base < 0))
+         * Passing -1 as first IRQ makes the simple domain allocate descriptors
-                goto out_unmap;
+         */
+        __vic_init(regs, -1, ~0, ~0, node);
-        __vic_init(regs, irq_base, ~0, ~0, node);
        return 0;
- out_unmap:
-        iounmap(regs);
-        return -EIO;
 }
 #endif /* CONFIG OF */
diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig
deleted file mode 100644
index c285a9d777d9..000000000000
--- a/arch/arm/configs/afeb9260_defconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_AFEB9260=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_SSC=y
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_DEBUG=y
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_SPIDEV=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DEBUG=y
-CONFIG_RTC_DRV_FM3130=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRC_T10DIF=y
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
index 2eef85e3c9b9..66894f736d04 100644
--- a/arch/arm/configs/ap4evb_defconfig
+++ b/arch/arm/configs/ap4evb_defconfig
@@ -46,7 +46,6 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index f78d259f8d23..2e1a82577207 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -7,6 +7,7 @@ CONFIG_LOG_BUF_SHIFT=16
 # CONFIG_IPC_NS is not set
 # CONFIG_PID_NS is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -20,7 +21,7 @@ CONFIG_MACH_ARMADILLO800EVA=y
 # CONFIG_SH_TIMER_TMU is not set
 CONFIG_ARM_THUMB=y
 CONFIG_CPU_BPREDICT_DISABLE=y
-# CONFIG_CACHE_L2X0 is not set
+CONFIG_CACHE_L2X0=y
 CONFIG_ARM_ERRATA_430973=y
 CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 67bc571ed0c3..b175577d7abb 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -111,6 +111,7 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_PINCTRL_AT91=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
index 505b3765f87e..0ea5d2c97fc4 100644
--- a/arch/arm/configs/at91sam9260_defconfig
+++ b/arch/arm/configs/at91sam9260_defconfig
@@ -75,7 +75,7 @@ CONFIG_USB_STORAGE_DEBUG=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_defconfig
index 1e8712ef062e..c87beb973b37 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_defconfig
@@ -125,7 +125,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index d2050cada82d..c5212f43eee6 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -133,7 +133,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_SDIO_UART=m
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index e1b0e80b54a5..3b1881033ad8 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -96,7 +96,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 7aea70253c63..74e27f0ff6ad 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -66,8 +66,6 @@ CONFIG_TTY_PRINTK=y
 # CONFIG_FILE_LOCKING is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_FS is not set
-# CONFIG_SYSFS is not set
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_PRINTK_TIME=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
new file mode 100644
index 000000000000..e3bf2d65618e
--- /dev/null
+++ b/arch/arm/configs/bcm_defconfig
@@ -0,0 +1,114 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_COMPACTION is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M"
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_BLK_DEV is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
+CONFIG_XZ_DEC=y
+CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
deleted file mode 100644
index 14579711d8fc..000000000000
--- a/arch/arm/configs/cam60_defconfig
+++ /dev/null
@@ -1,173 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_AUDIT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_KALLSYMS_ALL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_CAM60=y
-CONFIG_ZBOOT_ROM_BSS=0x20004000
-CONFIG_CMDLINE="console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_CFG80211=m
-CONFIG_MAC80211=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PLATRAM=m
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_VSXXXAA=m
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_LIBUSUAL=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_TEST=m
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_UNUSED_SYMBOLS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC32=m
-CONFIG_LIBCRC32C=m
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
new file mode 100644
index 000000000000..1cd94c36321f
--- /dev/null
+++ b/arch/arm/configs/clps711x_defconfig
@@ -0,0 +1,90 @@
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLOB=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_LBDAF is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_CLPS711X=y
+CONFIG_ARCH_AUTCPU12=y
+CONFIG_ARCH_CDB89712=y
+CONFIG_ARCH_CLEP7312=y
+CONFIG_ARCH_EDB7211=y
+CONFIG_ARCH_P720T=y
+CONFIG_ARCH_FORTUNET=y
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_COREDUMP is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+CONFIG_IRDA=y
+CONFIG_IRTTY_SIR=y
+CONFIG_EP7211_DONGLE=y
+# CONFIG_WIRELESS is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_AUTCPU12=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_GPIO=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+CONFIG_CS89x0=y
+CONFIG_CS89x0_PLATFORM=y
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_CLPS711X_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_CLPS711X=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_PLATFORM=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_MINIX_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index 4b8a25d9e686..1fd1d1de3220 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -218,7 +218,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_MMC_PXA=y
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig
deleted file mode 100644
index 921480c23b98..000000000000
--- a/arch/arm/configs/cpu9260_defconfig
+++ /dev/null
@@ -1,116 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_CPU9260=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_PPP=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=32
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig
deleted file mode 100644
index ea116cbdffa1..000000000000
--- a/arch/arm/configs/cpu9g20_defconfig
+++ /dev/null
@@ -1,116 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
-CONFIG_MACH_CPU9G20=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_PPP=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=32
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index 88ccde058ba4..f29223954af8 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -17,6 +17,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_ARCH_DAVINCI_DA830=y
 CONFIG_ARCH_DAVINCI_DA850=y
+CONFIG_MACH_DA8XX_DT=y
 CONFIG_MACH_MITYOMAPL138=y
 CONFIG_MACH_OMAPL138_HAWKBOARD=y
 CONFIG_DAVINCI_RESET_CLOCKS=y
@@ -26,6 +27,7 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_LEDS=y
+CONFIG_USE_OF=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CPU_FREQ=y
@@ -75,6 +77,7 @@ CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_DAVINCI=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 67b5abb6f857..4ea7c95719d2 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -144,7 +144,7 @@ CONFIG_USB_GADGET_DEBUG_FS=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_USB_G_PRINTER=m
 CONFIG_USB_CDC_COMPOSITE=m
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 40db34cf2771..0b7ee92c5713 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -8,11 +8,19 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_DOVE=y
 CONFIG_MACH_DOVE_DB=y
+CONFIG_MACH_CM_A510=y
+CONFIG_MACH_DOVE_DT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_HIGHMEM=y
+CONFIG_USE_OF=y
+CONFIG_ATAGS=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -62,6 +70,9 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -74,6 +85,18 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_DOVE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_DMADEVICES=y
@@ -122,6 +145,7 @@ CONFIG_CRYPTO_TWOFISH=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_MV_CESA=y
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/edb7211_defconfig b/arch/arm/configs/edb7211_defconfig
deleted file mode 100644
index d52ded350a12..000000000000
--- a/arch/arm/configs/edb7211_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
-CONFIG_ARCH_EDB7211=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_VT is not set
-CONFIG_SERIAL_CLPS711X=y
-CONFIG_SERIAL_CLPS711X_CONSOLE=y
-CONFIG_EXT2_FS=y
-CONFIG_MINIX_FS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/fortunet_defconfig b/arch/arm/configs/fortunet_defconfig
deleted file mode 100644
index 840fced7529f..000000000000
--- a/arch/arm/configs/fortunet_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
-CONFIG_ARCH_FORTUNET=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_FASTFPE=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_CLPS711X=y
-CONFIG_SERIAL_CLPS711X_CONSOLE=y
-CONFIG_EXT2_FS=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig
deleted file mode 100644
index 4a336ab5a0c0..000000000000
--- a/arch/arm/configs/g3evm_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
-CONFIG_ARCH_SH7367=y
-CONFIG_MACH_G3EVM=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC1,115200 earlyprintk=sh-sci.1,115200"
-CONFIG_KEXEC=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig
deleted file mode 100644
index 21c6d0307bc3..000000000000
--- a/arch/arm/configs/g4evm_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
-CONFIG_ARCH_SH7377=y
-CONFIG_MACH_G4EVM=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC4,115200 earlyprintk=sh-sci.4,115200"
-CONFIG_KEXEC=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
index 69405a762423..e16d3f372e2a 100644
--- a/arch/arm/configs/h7202_defconfig
+++ b/arch/arm/configs/h7202_defconfig
@@ -34,8 +34,7 @@ CONFIG_FB_MODE_HELPERS=y
 CONFIG_USB_GADGET=m
 CONFIG_USB_ZERO=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_FILE_STORAGE_TEST=y
 CONFIG_USB_G_SERIAL=m
 CONFIG_EXT2_FS=y
 CONFIG_TMPFS=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 78ed575feb1a..ebbfb27e0e74 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -18,7 +18,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_MXC=y
-CONFIG_ARCH_IMX_V4_V5=y
+CONFIG_ARCH_MULTI_V4T=y
+CONFIG_ARCH_MULTI_V5=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_MX1ADS=y
 CONFIG_MACH_SCB9328=y
 CONFIG_MACH_APF9328=y
@@ -121,6 +123,7 @@ CONFIG_REGULATOR_MC13892=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_VIDEO_MX2=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 394ded624e37..69667133321f 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -17,6 +17,8 @@ CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MXC=y
+CONFIG_ARCH_MULTI_V6=y
+CONFIG_ARCH_MULTI_V7=y
 CONFIG_MACH_MX31LILLY=y
 CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_PCM037=y
@@ -143,15 +145,18 @@ CONFIG_GPIO_MC9S08DZ60=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
+CONFIG_MFD_DA9052_I2C=y
 CONFIG_MFD_MC13XXX_SPI=y
 CONFIG_MFD_MC13XXX_I2C=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_DA9052=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_VIDEO_MX3=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 74eee0c78f28..93f3794ba5cb 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -27,6 +27,14 @@ CONFIG_MACH_GOFLEXNET_DT=y
 CONFIG_MACH_LSXL_DT=y
 CONFIG_MACH_IOMEGA_IX2_200_DT=y
 CONFIG_MACH_KM_KIRKWOOD_DT=y
+CONFIG_MACH_INETSPACE_V2_DT=y
+CONFIG_MACH_MPLCEC4_DT=y
+CONFIG_MACH_NETSPACE_V2_DT=y
+CONFIG_MACH_NETSPACE_MAX_V2_DT=y
+CONFIG_MACH_NETSPACE_LITE_V2_DT=y
+CONFIG_MACH_NETSPACE_MINI_V2_DT=y
+CONFIG_MACH_OPENBLOCKS_A6_DT=y
+CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_DOCKSTAR=y
@@ -40,6 +48,7 @@ CONFIG_MACH_D2NET_V2=y
 CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
+CONFIG_MACH_NSA310_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
index b7735d6347ac..fa83db1ef0eb 100644
--- a/arch/arm/configs/kota2_defconfig
+++ b/arch/arm/configs/kota2_defconfig
@@ -112,7 +112,6 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_RENESAS_TPU=y
 CONFIG_LEDS_TRIGGERS=y
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index c88b57886e79..afbae287436b 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -74,6 +74,8 @@ CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ST1232=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_ADXL34X=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=9
@@ -119,8 +121,9 @@ CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_ASYNC_TX_DMA=y
 CONFIG_STAGING=y
+CONFIG_SENSORS_AK8975=y
+CONFIG_IIO=y
 # CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY_USER=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 306a2e2d3622..2098ce155542 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -70,17 +70,31 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=8
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
 # CONFIG_MFD_SUPPORT is not set
 CONFIG_FB=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FB_SH_MOBILE_HDMI=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_HID_SUPPORT is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_USB_SUPPORT is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SOC_SH4_FSI=y
+CONFIG_USB=y
+CONFIG_USB_RENESAS_USBHS_HCD=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -91,7 +105,6 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index a691ef4c6008..557dd291288b 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -136,7 +136,7 @@ CONFIG_USB_PXA27X=y
 CONFIG_USB_ETH=m
 # CONFIG_USB_ETH_RNDIS is not set
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_USB_CDC_COMPOSITE=m
 CONFIG_USB_GPIO_VBUS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 53382b6c8bb4..728a43c446f8 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -59,9 +61,8 @@ CONFIG_SMSC911X=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
 # CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
@@ -69,14 +70,25 @@ CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=6
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_HSPI=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_RCAR_PHY=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 00630e6af45c..a07948a87caa 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -240,7 +240,7 @@ CONFIG_USB_GADGET_S3C2410=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_USB_CDC_COMPOSITE=m
 CONFIG_MMC=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 048aaca60814..7bf535104e26 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -61,6 +61,8 @@ CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_ENC28J60=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC95XX=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_WLAN is not set
@@ -158,6 +160,10 @@ CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
 CONFIG_PRINTK_TIME=y
 CONFIG_FRAME_WARN=2048
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index dde2a1af7b39..42eab9a2a0fd 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -214,8 +214,7 @@ CONFIG_USB_TEST=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 # CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_FILE_STORAGE_TEST=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 62303043db9c..a1dc5c071e71 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -240,3 +240,6 @@ CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=y
 CONFIG_LIBCRC32C=y
 CONFIG_SOC_OMAP5=y
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
+CONFIG_TI_CPSW=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index cd5e6ba9a54d..952430d9e2d9 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -1,7 +1,8 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_EXPERT=y
 # CONFIG_SLUB_DEBUG is not set
 CONFIG_PROFILING=y
@@ -10,6 +11,8 @@ CONFIG_KPROBES=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
 CONFIG_ARCH_ORION5X=y
 CONFIG_MACH_DB88F5281=y
 CONFIG_MACH_RD88F5182=y
@@ -24,7 +27,7 @@ CONFIG_MACH_TS409=y
 CONFIG_MACH_WRT350N_V2=y
 CONFIG_MACH_TS78XX=y
 CONFIG_MACH_MV2120=y
-CONFIG_MACH_EDMINI_V2=y
+CONFIG_MACH_EDMINI_V2_DT=y
 CONFIG_MACH_D2NET=y
 CONFIG_MACH_BIGDISK=y
 CONFIG_MACH_NET2BIG=y
@@ -33,17 +36,13 @@ CONFIG_MACH_WNR854T=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
 CONFIG_FPE_NWFPE=y
 CONFIG_VFP=y
-# CONFIG_SUSPEND is not set
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -54,13 +53,10 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6131=y
-CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_NET_PKTGEN=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -82,12 +78,11 @@ CONFIG_CHR_DEV_SG=m
 CONFIG_ATA=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_NET_PCI=y
+CONFIG_NET_DSA_MV88E6131=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_MARVELL_PHY=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
@@ -95,11 +90,12 @@ CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
+CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_HW_RANDOM_TIMERIOMEM=m
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -109,10 +105,8 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_SENSORS_LM75=y
 # CONFIG_VGA_ARB is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_PRINTER=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
@@ -140,7 +134,6 @@ CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
 CONFIG_EXT4_FS=m
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -150,25 +143,18 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_LATENCYTOP=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_ECB=m
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index 807d4e2acb17..6a936c7c078a 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -37,7 +37,6 @@ CONFIG_SPI_SIRF=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
 CONFIG_USB_GADGET=y
-CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
deleted file mode 100644
index 42d5db1876ab..000000000000
--- a/arch/arm/configs/qil-a9260_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_QIL_A9260=y
-CONFIG_AT91_SLOW_CLOCK=y
-CONFIG_AT91_EARLY_USART0=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS1,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_M41T94=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_FUSE_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
deleted file mode 100644
index b4384af1bea6..000000000000
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ /dev/null
@@ -1,148 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_AUDIT=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_SAM9_L9260=y
-CONFIG_MTD_AT91_DATAFLASH_CARD=y
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 mem=64M initrd=0x21100000,4194304 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=25
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
-CONFIG_RAID_ATTRS=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_LIBUSUAL=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1553=y
-CONFIG_RTC_DRV_DS1742=y
-CONFIG_RTC_DRV_M48T86=y
-CONFIG_RTC_DRV_V3020=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=y
-CONFIG_NLS_CODEPAGE_775=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_CODEPAGE_855=y
-CONFIG_NLS_CODEPAGE_857=y
-CONFIG_NLS_CODEPAGE_860=y
-CONFIG_NLS_CODEPAGE_861=y
-CONFIG_NLS_CODEPAGE_862=y
-CONFIG_NLS_CODEPAGE_863=y
-CONFIG_NLS_CODEPAGE_864=y
-CONFIG_NLS_CODEPAGE_865=y
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_869=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_CODEPAGE_950=y
-CONFIG_NLS_CODEPAGE_932=y
-CONFIG_NLS_CODEPAGE_949=y
-CONFIG_NLS_CODEPAGE_874=y
-CONFIG_NLS_ISO8859_8=y
-CONFIG_NLS_CODEPAGE_1250=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_3=y
-CONFIG_NLS_ISO8859_4=y
-CONFIG_NLS_ISO8859_5=y
-CONFIG_NLS_ISO8859_6=y
-CONFIG_NLS_ISO8859_7=y
-CONFIG_NLS_ISO8859_9=y
-CONFIG_NLS_ISO8859_13=y
-CONFIG_NLS_ISO8859_14=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_KOI8_U=y
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_UNUSED_SYMBOLS=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 0ac1293dba10..4e1ce211d43f 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -18,9 +18,10 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_MACH_SOCFPGA_CYCLONE5=y
 CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
-CONFIG_VMSPLIT_2G=y
+CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index df77931a4326..2e0419d1b964 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -214,7 +214,7 @@ CONFIG_USB_GADGET_DUMMY_HCD=y
 CONFIG_USB_ZERO=m
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_MMC_PXA=y
diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig
deleted file mode 100644
index 52f1488591c7..000000000000
--- a/arch/arm/configs/stamp9g20_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
-CONFIG_MACH_PORTUXG20=y
-CONFIG_MACH_STAMP9G20=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_AT91_SLOW_CLOCK=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_KEXEC=y
-CONFIG_CPU_IDLE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_W1=y
-CONFIG_W1_MASTER_GPIO=y
-CONFIG_W1_SLAVE_THERM=y
-CONFIG_W1_SLAVE_DS2431=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index e2184f6c20b3..a7827fd0616f 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -80,6 +80,10 @@ CONFIG_RFKILL_GPIO=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_CMA=y
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_M25P80=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_AD525X_DPOT=y
@@ -98,12 +102,12 @@ CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
+CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
-# CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
@@ -116,7 +120,8 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
-CONFIG_SPI_TEGRA=y
+CONFIG_SPI_TEGRA20_SFLASH=y
+CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
@@ -138,6 +143,15 @@ CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
+CONFIG_DRM=y
+CONFIG_DRM_TEGRA=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
@@ -205,6 +219,9 @@ CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index da6845493caa..231dca604737 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -69,6 +69,8 @@ CONFIG_GPIO_TC3589X=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_AB8500_BM=y
 CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
 CONFIG_MFD_STMPE=y
 CONFIG_MFD_TC3589X=y
 CONFIG_AB5500_CORE=y
@@ -76,6 +78,7 @@ CONFIG_AB8500_CORE=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_AB8500=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_GADGET=y
 CONFIG_AB8500_USB=y
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
deleted file mode 100644
index a1501e1e1a90..000000000000
--- a/arch/arm/configs/usb-a9260_defconfig
+++ /dev/null
@@ -1,105 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_USB_A9260=y
-CONFIG_AT91_SLOW_CLOCK=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_FUSE_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
index 1d01ddd33122..d36e0d3c86ec 100644
--- a/arch/arm/configs/viper_defconfig
+++ b/arch/arm/configs/viper_defconfig
@@ -139,7 +139,7 @@ CONFIG_USB_SERIAL_MCT_U232=m
 CONFIG_USB_GADGET=m
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_USB_G_PRINTER=m
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
index 547a3c1e59db..731d4f985310 100644
--- a/arch/arm/configs/zeus_defconfig
+++ b/arch/arm/configs/zeus_defconfig
@@ -143,7 +143,7 @@ CONFIG_USB_GADGET=m
 CONFIG_USB_PXA27X=y
 CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_USB_G_PRINTER=m
 CONFIG_MMC=y
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index f70ae175a3d6..d3db39860b9c 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -16,7 +16,6 @@ generic-y += local64.h
 generic-y += msgbuf.h
 generic-y += param.h
 generic-y += parport.h
-generic-y += percpu.h
 generic-y += poll.h
 generic-y += resource.h
 generic-y += sections.h
@@ -31,5 +30,6 @@ generic-y += sockios.h
 generic-y += termbits.h
 generic-y += termios.h
 generic-y += timex.h
+generic-y += trace_clock.h
 generic-y += types.h
 generic-y += unaligned.h
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 2ef95813fce0..eb87200aa4b5 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -250,6 +250,7 @@
 * Beware, it also clobers LR.
 */
 .macro safe_svcmode_maskall reg:req
+#if __LINUX_ARM_ARCH__ >= 6
        mrs     \reg , cpsr
        mov     lr , \reg
        and     lr , lr , #MODE_MASK
@@ -266,6 +267,13 @@ THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
        __ERET
 1:      msr     cpsr_c, \reg
 2:
+#else
+/*
+ * workaround for possibly broken pre-v6 hardware
+ * (akita, Sharp Zaurus C-1000, PXA270-based)
+ */
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
+#endif
 .endm
 /*
diff --git a/arch/arm/include/asm/cpu.h b/arch/arm/include/asm/cpu.h
index d797223b39d5..2744f0602550 100644
--- a/arch/arm/include/asm/cpu.h
+++ b/arch/arm/include/asm/cpu.h
@@ -15,6 +15,7 @@
 struct cpuinfo_arm {
        struct cpu      cpu;
+        u32             cpuid;
 #ifdef CONFIG_SMP
        unsigned int    loops_per_jiffy;
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb47d28cbe1f..a59dcb5ab5fc 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -25,6 +25,19 @@
 #define CPUID_EXT_ISAR4 "c2, 4"
 #define CPUID_EXT_ISAR5 "c2, 5"
+#define MPIDR_SMP_BITMASK (0x3 << 30)
+#define MPIDR_SMP_VALUE (0x2 << 30)
+#define MPIDR_MT_BITMASK (0x1 << 24)
+#define MPIDR_HWID_BITMASK 0xFFFFFF
+#define MPIDR_LEVEL_BITS 8
+#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
+        ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
 extern unsigned int processor_id;
 #ifdef CONFIG_CPU_CP15
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index a0ada3ea4358..f2e5cad3f306 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)
 */
 static inline void cti_unlock(struct cti *cti)
 {
-        void __iomem *base = cti->base;
+        __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
-        unsigned long val;
-        val = __raw_readl(base + LOCKSTATUS);
-        if (val & 1) {
-                val = LOCKCODE;
-                __raw_writel(val, base + LOCKACCESS);
-        }
 }
 /**
@@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)
 */
 static inline void cti_lock(struct cti *cti)
 {
-        void __iomem *base = cti->base;
+        __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
-        unsigned long val;
-        val = __raw_readl(base + LOCKSTATUS);
-        if (!(val & 1)) {
-                val = ~LOCKCODE;
-                __raw_writel(val, base + LOCKACCESS);
-        }
 }
 #endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 98d4dabb2c10..67d06324e74a 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -213,13 +213,6 @@ static inline void dma_free_writecombine(struct device *dev, size_t size,
 extern void __init init_dma_coherent_pool_size(unsigned long size);
 /*
- * This can be called during boot to increase the size of the consistent
- * DMA region above it's default value of 2MB. It must be called before the
- * memory allocator is initialised, i.e. before any core_initcall.
- */
-static inline void init_consistent_dma_size(unsigned long size) { }
-/*
 * For SA-1111, IXP425, and ADI systems  the dma-mapping functions are "magic"
 * and utilize bounce buffers as needed to work around limited DMA windows.
 *
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index c4c87bc12231..3b2c40b5bfa2 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -102,6 +102,10 @@
 #define L2X0_ADDR_FILTER_EN             1
+#define L2X0_CTRL_EN                    1
+#define L2X0_WAY_SIZE_SHIFT             3
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
@@ -126,6 +130,7 @@ struct l2x0_regs {
        unsigned long filter_end;
        unsigned long prefetch_ctrl;
        unsigned long pwr_ctrl;
+        unsigned long ctrl;
 };
 extern struct l2x0_regs l2x0_saved_regs;
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
index 6b9b077d86b3..6636430dd0e6 100644
--- a/arch/arm/include/asm/hardware/sp810.h
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -50,11 +50,7 @@
 #define SCPCELLID2              0xFF8
 #define SCPCELLID3              0xFFC
-#define SCCTRL_TIMEREN0SEL_REFCLK       (0 << 15)
+#define SCCTRL_TIMERENnSEL_SHIFT(n)     (15 + ((n) * 2))
-#define SCCTRL_TIMEREN0SEL_TIMCLK       (1 << 15)
-#define SCCTRL_TIMEREN1SEL_REFCLK       (0 << 17)
-#define SCCTRL_TIMEREN1SEL_TIMCLK       (1 << 17)
 static inline void sysctl_soft_reset(void __iomem *base)
 {
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index e14af1a1a320..2bebad36fc83 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -47,7 +47,7 @@
 struct device_node;
 struct pt_regs;
-void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
+void __vic_init(void __iomem *base, int irq_start, u32 vic_sources,
                u32 resume_sources, struct device_node *node);
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
 int vic_of_init(struct device_node *node, struct device_node *parent);
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index c190bc992f0e..01169dd723f1 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -98,12 +98,12 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_BASE_WCR            112
 /* Accessor macros for the debug registers. */
-#define ARM_DBG_READ(M, OP2, VAL) do {\
+#define ARM_DBG_READ(N, M, OP2, VAL) do {\
-        asm volatile("mrc p14, 0, %0, c0," #M ", " #OP2 : "=r" (VAL));\
+        asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
 } while (0)
-#define ARM_DBG_WRITE(M, OP2, VAL) do {\
+#define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
-        asm volatile("mcr p14, 0, %0, c0," #M ", " #OP2 : : "r" (VAL));\
+        asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
 } while (0)
 struct notifier_block;
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 42f042ee4ada..652b56086de7 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -374,7 +374,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 #ifdef CONFIG_MMU
 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
-extern int valid_phys_addr_range(unsigned long addr, size_t size);
+extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 extern int devmem_is_allowed(unsigned long pfn);
 #endif
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 195ac2f9d3d3..2fe141fcc8d6 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -40,6 +40,13 @@ extern void iotable_init(struct map_desc *, int);
 extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
                                  void *caller);
+#ifdef CONFIG_DEBUG_LL
+extern void debug_ll_addr(unsigned long *paddr, unsigned long *vaddr);
+extern void debug_ll_io_init(void);
+#else
+static inline void debug_ll_io_init(void) {}
+#endif
 struct mem_type;
 extern const struct mem_type *get_mem_type(unsigned int type);
 /*
diff --git a/arch/arm/include/asm/mach/serial_at91.h b/arch/arm/include/asm/mach/serial_at91.h
deleted file mode 100644
index ea6d063923b8..000000000000
--- a/arch/arm/include/asm/mach/serial_at91.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/include/asm/mach/serial_at91.h
- *
- *  Based on serial_sa1100.h  by Nicolas Pitre
- *
- *  Copyright (C) 2002 ATMEL Rousset
- *
- *  Low level machine dependent UART functions.
- */
-struct uart_port;
-/*
- * This is a temporary structure for registering these
- * functions; it is intended to be discarded after boot.
- */
-struct atmel_port_fns {
-        void    (*set_mctrl)(struct uart_port *, u_int);
-        u_int   (*get_mctrl)(struct uart_port *);
-        void    (*enable_ms)(struct uart_port *);
-        void    (*pm)(struct uart_port *, u_int, u_int);
-        int     (*set_wake)(struct uart_port *, u_int);
-        int     (*open)(struct uart_port *);
-        void    (*close)(struct uart_port *);
-};
-#if defined(CONFIG_SERIAL_ATMEL)
-void atmel_register_uart_fns(struct atmel_port_fns *fns);
-#else
-#define atmel_register_uart_fns(fns) do { } while (0)
-#endif
diff --git a/arch/arm/include/asm/mach/serial_sa1100.h b/arch/arm/include/asm/mach/serial_sa1100.h
deleted file mode 100644
index d09064bf95a0..000000000000
--- a/arch/arm/include/asm/mach/serial_sa1100.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  arch/arm/include/asm/mach/serial_sa1100.h
- *
- *  Author: Nicolas Pitre
- *
- * Moved and changed lots, Russell King
- *
- * Low level machine dependent UART functions.
- */
-struct uart_port;
-struct uart_info;
-/*
- * This is a temporary structure for registering these
- * functions; it is intended to be discarded after boot.
- */
-struct sa1100_port_fns {
-        void    (*set_mctrl)(struct uart_port *, u_int);
-        u_int   (*get_mctrl)(struct uart_port *);
-        void    (*pm)(struct uart_port *, u_int, u_int);
-        int     (*set_wake)(struct uart_port *, u_int);
-};
-#ifdef CONFIG_SERIAL_SA1100
-void sa1100_register_uart_fns(struct sa1100_port_fns *fns);
-void sa1100_register_uart(int idx, int port);
-#else
-#define sa1100_register_uart_fns(fns) do { } while (0)
-#define sa1100_register_uart(idx,port) do { } while (0)
-#endif
diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h
deleted file mode 100644
index ea297ac70bc6..000000000000
--- a/arch/arm/include/asm/mach/udc_pxa2xx.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/include/asm/mach/udc_pxa2xx.h
- *
- * This supports machine-specific differences in how the PXA2xx
- * USB Device Controller (UDC) is wired.
- *
- * It is set in linux/arch/arm/mach-pxa/<machine>.c or in
- * linux/arch/mach-ixp4xx/<machine>.c and used in
- * the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c
- */
-struct pxa2xx_udc_mach_info {
-        int  (*udc_is_connected)(void);         /* do we see host? */
-        void (*udc_command)(int cmd);
-#define PXA2XX_UDC_CMD_CONNECT          0       /* let host see us */
-#define PXA2XX_UDC_CMD_DISCONNECT       1       /* so host won't see us */
-        /* Boards following the design guidelines in the developer's manual,
-         * with on-chip GPIOs not Lubbock's weird hardware, can have a sane
-         * VBUS IRQ and omit the methods above.  Store the GPIO number
-         * here.  Note that sometimes the signals go through inverters...
-         */
-        bool    gpio_pullup_inverted;
-        int     gpio_pullup;                    /* high == pullup activated */
-};
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 14965658a923..9f77e7804f3b 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -5,18 +5,15 @@
 typedef struct {
 #ifdef CONFIG_CPU_HAS_ASID
-        unsigned int id;
+        u64 id;
-        raw_spinlock_t id_lock;
 #endif
-        unsigned int kvm_seq;
+        unsigned int vmalloc_seq;
 } mm_context_t;
 #ifdef CONFIG_CPU_HAS_ASID
-#define ASID(mm)        ((mm)->context.id & 255)
+#define ASID_BITS       8
+#define ASID_MASK       ((~0ULL) << ASID_BITS)
-/* init_mm.context.id_lock should be initialized. */
+#define ASID(mm)        ((mm)->context.id & ~ASID_MASK)
-#define INIT_MM_CONTEXT(name)                                                 \
-        .context.id_lock    = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
 #else
 #define ASID(mm)        (0)
 #endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 0306bc642c0d..e1f644bc7cc5 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -20,88 +20,12 @@
 #include <asm/proc-fns.h>
 #include <asm-generic/mm_hooks.h>
-void __check_kvm_seq(struct mm_struct *mm);
+void __check_vmalloc_seq(struct mm_struct *mm);
 #ifdef CONFIG_CPU_HAS_ASID
-/*
+void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
- * On ARMv6, we have the following structure in the Context ID:
+#define init_new_context(tsk,mm)        ({ mm->context.id = 0; })
- *
- * 31                         7          0
- * +-------------------------+-----------+
- * |      process ID         |   ASID    |
- * +-------------------------+-----------+
- * |              context ID             |
- * +-------------------------------------+
- *
- * The ASID is used to tag entries in the CPU caches and TLBs.
- * The context ID is used by debuggers and trace logic, and
- * should be unique within all running processes.
- */
-#define ASID_BITS               8
-#define ASID_MASK               ((~0) << ASID_BITS)
-#define ASID_FIRST_VERSION      (1 << ASID_BITS)
-extern unsigned int cpu_last_asid;
-void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-void __new_context(struct mm_struct *mm);
-void cpu_set_reserved_ttbr0(void);
-static inline void switch_new_context(struct mm_struct *mm)
-{
-        unsigned long flags;
-        __new_context(mm);
-        local_irq_save(flags);
-        cpu_switch_mm(mm->pgd, mm);
-        local_irq_restore(flags);
-}
-static inline void check_and_switch_context(struct mm_struct *mm,
-                                            struct task_struct *tsk)
-{
-        if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
-                __check_kvm_seq(mm);
-        /*
-         * Required during context switch to avoid speculative page table
-         * walking with the wrong TTBR.
-         */
-        cpu_set_reserved_ttbr0();
-        if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
-                /*
-                 * The ASID is from the current generation, just switch to the
-                 * new pgd. This condition is only true for calls from
-                 * context_switch() and interrupts are already disabled.
-                 */
-                cpu_switch_mm(mm->pgd, mm);
-        else if (irqs_disabled())
-                /*
-                 * Defer the new ASID allocation until after the context
-                 * switch critical region since __new_context() cannot be
-                 * called with interrupts disabled (it sends IPIs).
-                 */
-                set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
-        else
-                /*
-                 * That is a direct call to switch_mm() or activate_mm() with
-                 * interrupts enabled and a new context.
-                 */
-                switch_new_context(mm);
-}
-#define init_new_context(tsk,mm)        (__init_new_context(tsk,mm),0)
-#define finish_arch_post_lock_switch \
-        finish_arch_post_lock_switch
-static inline void finish_arch_post_lock_switch(void)
-{
-        if (test_and_clear_thread_flag(TIF_SWITCH_MM))
-                switch_new_context(current->mm);
-}
 #else   /* !CONFIG_CPU_HAS_ASID */
@@ -110,8 +34,8 @@ static inline void finish_arch_post_lock_switch(void)
 static inline void check_and_switch_context(struct mm_struct *mm,
                                            struct task_struct *tsk)
 {
-        if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
+        if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
-                __check_kvm_seq(mm);
+                __check_vmalloc_seq(mm);
        if (irqs_disabled())
                /*
@@ -143,6 +67,7 @@ static inline void finish_arch_post_lock_switch(void)
 #endif  /* CONFIG_CPU_HAS_ASID */
 #define destroy_context(mm)             do { } while(0)
+#define activate_mm(prev,next)          switch_mm(prev, next, NULL)
 /*
 * This is called when "tsk" is about to enter lazy TLB mode.
@@ -186,6 +111,5 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 }
 #define deactivate_mm(tsk,mm)   do { } while (0)
-#define activate_mm(prev,next)  switch_mm(prev, next, NULL)
 #endif
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
new file mode 100644
index 000000000000..968c0a14e0a3
--- /dev/null
+++ b/arch/arm/include/asm/percpu.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _ASM_ARM_PERCPU_H_
+#define _ASM_ARM_PERCPU_H_
+/*
+ * Same as asm-generic/percpu.h, except that we store the per cpu offset
+ * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7
+ */
+#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6)
+static inline void set_my_cpu_offset(unsigned long off)
+{
+        /* Set TPIDRPRW */
+        asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory");
+}
+static inline unsigned long __my_cpu_offset(void)
+{
+        unsigned long off;
+        /* Read TPIDRPRW */
+        asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory");
+        return off;
+}
+#define __my_cpu_offset __my_cpu_offset()
+#else
+#define set_my_cpu_offset(x)    do {} while(0)
+#endif /* CONFIG_SMP */
+#include <asm-generic/percpu.h>
+#endif /* _ASM_ARM_PERCPU_H_ */
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 625cd621a436..755877527cf9 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -21,4 +21,11 @@
 #define C(_x)                           PERF_COUNT_HW_CACHE_##_x
 #define CACHE_OP_UNSUPPORTED            0xFFFF
+#ifdef CONFIG_HW_PERF_EVENTS
+struct pt_regs;
+extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
+extern unsigned long perf_misc_flags(struct pt_regs *regs);
+#define perf_misc_flags(regs)   perf_misc_flags(regs)
+#endif
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 2317a71c8f8e..f97ee02386ee 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -115,6 +115,7 @@
 * The PTE table pointer refers to the hardware entries; the "Linux"
 * entries are stored 1024 bytes below.
 */
+#define L_PTE_VALID             (_AT(pteval_t, 1) << 0)         /* Valid */
 #define L_PTE_PRESENT           (_AT(pteval_t, 1) << 0)
 #define L_PTE_YOUNG             (_AT(pteval_t, 1) << 1)
 #define L_PTE_FILE              (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
@@ -123,6 +124,7 @@
 #define L_PTE_USER              (_AT(pteval_t, 1) << 8)
 #define L_PTE_XN                (_AT(pteval_t, 1) << 9)
 #define L_PTE_SHARED            (_AT(pteval_t, 1) << 10)        /* shared(v6), coherent(xsc3) */
+#define L_PTE_NONE              (_AT(pteval_t, 1) << 11)
 /*
 * These are the memory types, defined to be compatible with
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index b24903549d1c..a3f37929940a 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -67,7 +67,8 @@
 * These bits overlap with the hardware bits but the naming is preserved for
 * consistency with the classic page table format.
 */
-#define L_PTE_PRESENT           (_AT(pteval_t, 3) << 0)         /* Valid */
+#define L_PTE_VALID             (_AT(pteval_t, 1) << 0)         /* Valid */
+#define L_PTE_PRESENT           (_AT(pteval_t, 3) << 0)         /* Present */
 #define L_PTE_FILE              (_AT(pteval_t, 1) << 2)         /* only when !PRESENT */
 #define L_PTE_USER              (_AT(pteval_t, 1) << 6)         /* AP[1] */
 #define L_PTE_RDONLY            (_AT(pteval_t, 1) << 7)         /* AP[2] */
@@ -76,6 +77,7 @@
 #define L_PTE_XN                (_AT(pteval_t, 1) << 54)        /* XN */
 #define L_PTE_DIRTY             (_AT(pteval_t, 1) << 55)        /* unused */
 #define L_PTE_SPECIAL           (_AT(pteval_t, 1) << 56)        /* unused */
+#define L_PTE_NONE              (_AT(pteval_t, 1) << 57)        /* PROT_NONE */
 /*
 * To be used in assembly code with the upper page attributes.
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 08c12312a1f9..9c82f988c0e3 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -73,7 +73,7 @@ extern pgprot_t		pgprot_kernel;
 #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
-#define PAGE_NONE               _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY)
+#define PAGE_NONE               _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
 #define PAGE_SHARED             _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
 #define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_user, L_PTE_USER)
 #define PAGE_COPY               _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
@@ -83,7 +83,7 @@ extern pgprot_t		pgprot_kernel;
 #define PAGE_KERNEL             _MOD_PROT(pgprot_kernel, L_PTE_XN)
 #define PAGE_KERNEL_EXEC        pgprot_kernel
-#define __PAGE_NONE             __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN)
+#define __PAGE_NONE             __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
 #define __PAGE_SHARED           __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
 #define __PAGE_SHARED_EXEC      __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
 #define __PAGE_COPY             __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
@@ -203,9 +203,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 #define pte_exec(pte)           (!(pte_val(pte) & L_PTE_XN))
 #define pte_special(pte)        (0)
-#define pte_present_user(pte) \
+#define pte_present_user(pte)  (pte_present(pte) && (pte_val(pte) & L_PTE_USER))
-        ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \
-         (L_PTE_PRESENT | L_PTE_USER))
 #if __LINUX_ARM_ARCH__ < 6
 static inline void __sync_icache_dcache(pte_t pteval)
@@ -242,7 +240,7 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-        const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER;
+        const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER | L_PTE_NONE;
        pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
        return pte;
 }
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index a26170dce02e..f24edad26c70 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -67,19 +67,19 @@ struct arm_pmu {
        cpumask_t       active_irqs;
        char            *name;
        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
-        void            (*enable)(struct hw_perf_event *evt, int idx);
+        void            (*enable)(struct perf_event *event);
-        void            (*disable)(struct hw_perf_event *evt, int idx);
+        void            (*disable)(struct perf_event *event);
        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
-                                         struct hw_perf_event *hwc);
+                                         struct perf_event *event);
        int             (*set_event_filter)(struct hw_perf_event *evt,
                                            struct perf_event_attr *attr);
-        u32             (*read_counter)(int idx);
+        u32             (*read_counter)(struct perf_event *event);
-        void            (*write_counter)(int idx, u32 val);
+        void            (*write_counter)(struct perf_event *event, u32 val);
-        void            (*start)(void);
+        void            (*start)(struct arm_pmu *);
-        void            (*stop)(void);
+        void            (*stop)(struct arm_pmu *);
        void            (*reset)(void *);
-        int             (*request_irq)(irq_handler_t handler);
+        int             (*request_irq)(struct arm_pmu *, irq_handler_t handler);
-        void            (*free_irq)(void);
+        void            (*free_irq)(struct arm_pmu *);
        int             (*map_event)(struct perf_event *event);
        int             num_events;
        atomic_t        active_events;
@@ -93,15 +93,11 @@ struct arm_pmu {
 extern const struct dev_pm_ops armpmu_dev_pm_ops;
-int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+int armpmu_register(struct arm_pmu *armpmu, int type);
-u64 armpmu_event_update(struct perf_event *event,
+u64 armpmu_event_update(struct perf_event *event);
-                        struct hw_perf_event *hwc,
-                        int idx);
-int armpmu_event_set_period(struct perf_event *event,
+int armpmu_event_set_period(struct perf_event *event);
-                            struct hw_perf_event *hwc,
-                            int idx);
 int armpmu_map_event(struct perf_event *event,
                     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index aeae9c609df4..a219227c3e43 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -11,10 +11,13 @@
 #ifndef __ASMARM_PROM_H
 #define __ASMARM_PROM_H
+#define HAVE_ARCH_DEVTREE_FIXUPS
 #ifdef CONFIG_OF
 extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
 extern void arm_dt_memblock_reserve(void);
+extern void __init arm_dt_init_cpu_maps(void);
 #else /* CONFIG_OF */
@@ -24,6 +27,7 @@ static inline struct machine_desc *setup_machine_fdt(unsigned int dt_phys)
 }
 static inline void arm_dt_memblock_reserve(void) { }
+static inline void arm_dt_init_cpu_maps(void) { }
 #endif /* CONFIG_OF */
 #endif /* ASMARM_PROM_H */
diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h
index 5a7963dbd3fb..9a0ea6ab988f 100644
--- a/arch/arm/include/asm/signal.h
+++ b/arch/arm/include/asm/signal.h
@@ -35,5 +35,4 @@ struct k_sigaction {
 };
 #include <asm/sigcontext.h>
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
 #endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 2e3be16c6766..d3a22bebe6ce 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -79,6 +79,7 @@ extern void cpu_die(void);
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask);
 struct smp_operations {
 #ifdef CONFIG_SMP
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 558d6c80aca9..aaa61b6f50ff 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -5,6 +5,9 @@
 #ifndef __ASMARM_SMP_PLAT_H
 #define __ASMARM_SMP_PLAT_H
+#include <linux/cpumask.h>
+#include <linux/err.h>
 #include <asm/cputype.h>
 /*
@@ -48,5 +51,19 @@ static inline int cache_ops_need_broadcast(void)
 */
 extern int __cpu_logical_map[];
 #define cpu_logical_map(cpu)    __cpu_logical_map[cpu]
+/*
+ * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
+ *  - mpidr: MPIDR[23:0] to be used for the look-up
+ *
+ * Returns the cpu logical index or -EINVAL on look-up error
+ */
+static inline int get_logical_index(u32 mpidr)
+{
+        int cpu;
+        for (cpu = 0; cpu < nr_cpu_ids; cpu++)
+                if (cpu_logical_map(cpu) == mpidr)
+                        return cpu;
+        return -EINVAL;
+}
 #endif
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index 9fdded6b1089..f1d96d4e8092 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_ARM_SYSCALL_H
 #define _ASM_ARM_SYSCALL_H
+#include <linux/audit.h> /* for AUDIT_ARCH_* */
+#include <linux/elf.h> /* for ELF_EM */
 #include <linux/err.h>
 #include <linux/sched.h>
@@ -95,4 +97,11 @@ static inline void syscall_set_arguments(struct task_struct *task,
        memcpy(&regs->ARM_r0 + i, args, n * sizeof(args[0]));
 }
+static inline int syscall_get_arch(struct task_struct *task,
+                                   struct pt_regs *regs)
+{
+        /* ARM tasks don't change audit architectures on the fly. */
+        return AUDIT_ARCH_ARM;
+}
 #endif /* _ASM_ARM_SYSCALL_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 8477b4c1d39f..cddda1f41f0f 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -151,10 +151,10 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_SYSCALL_TRACE       8
 #define TIF_SYSCALL_AUDIT       9
 #define TIF_SYSCALL_TRACEPOINT  10
+#define TIF_SECCOMP             11      /* seccomp syscall filtering active */
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     20
-#define TIF_SECCOMP             21
 #define TIF_SWITCH_MM           22      /* deferred switch_mm */
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
@@ -163,11 +163,12 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
 #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
-#define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP            (1 << TIF_SECCOMP)
+#define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 /* Checks for any syscall work in entry-common.S */
-#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
+                           _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP)
 /*
 * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 8f60b6e6bd41..7cd13cc62624 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -42,6 +42,9 @@
 #define __ARCH_WANT_SYS_SOCKETCALL
 #endif
 #define __ARCH_WANT_SYS_EXECVE
+#define __ARCH_WANT_SYS_FORK
+#define __ARCH_WANT_SYS_VFORK
+#define __ARCH_WANT_SYS_CLONE
 /*
 * "Conditional" syscalls
diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
index 5000397134b4..1151188bcd83 100644
--- a/arch/arm/include/asm/xen/interface.h
+++ b/arch/arm/include/asm/xen/interface.h
@@ -49,6 +49,7 @@ DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
 DEFINE_GUEST_HANDLE(uint32_t);
 DEFINE_GUEST_HANDLE(xen_pfn_t);
+DEFINE_GUEST_HANDLE(xen_ulong_t);
 /* Maximum number of virtual CPUs in multi-processor guests. */
 #define MAX_VIRT_CPUS 1
diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S
new file mode 100644
index 000000000000..0c4e17d4d359
--- /dev/null
+++ b/arch/arm/include/debug/imx.S
@@ -0,0 +1,74 @@
+/* arch/arm/mach-imx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#define IMX6Q_UART1_BASE_ADDR   0x02020000
+#define IMX6Q_UART2_BASE_ADDR   0x021e8000
+#define IMX6Q_UART3_BASE_ADDR   0x021ec000
+#define IMX6Q_UART4_BASE_ADDR   0x021f0000
+#define IMX6Q_UART5_BASE_ADDR   0x021f4000
+/*
+ * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
+ * of IMX6Q_UART##n##_BASE_ADDR.
+ */
+#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
+#define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
+#define IMX6Q_DEBUG_UART_BASE   IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
+#ifdef CONFIG_DEBUG_IMX1_UART
+#define UART_PADDR      0x00206000
+#elif defined (CONFIG_DEBUG_IMX25_UART)
+#define UART_PADDR      0x43f90000
+#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
+#define UART_PADDR      0x1000a000
+#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
+#define UART_PADDR      0x43f90000
+#elif defined (CONFIG_DEBUG_IMX51_UART)
+#define UART_PADDR      0x73fbc000
+#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
+#define UART_PADDR      0x53fbc000
+#elif defined (CONFIG_DEBUG_IMX6Q_UART)
+#define UART_PADDR      IMX6Q_DEBUG_UART_BASE
+#endif
+/*
+ * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to
+ * stay sync with that.  It's hard to maintain, and should be fixed
+ * globally for multi-platform build to use a fixed virtual address
+ * for low-level debug uart port across platforms.
+ */
+#define IMX_IO_P2V(x)   (                                               \
+                        (((x) & 0x80000000) >> 7) |                     \
+                        (0xf4000000 +                                   \
+                        (((x) & 0x50000000) >> 6) +                     \
+                        (((x) & 0x0b000000) >> 4) +                     \
+                        (((x) & 0x000fffff))))
+#define UART_VADDR      IMX_IO_P2V(UART_PADDR)
+                .macro  addruart, rp, rv, tmp
+                ldr     \rp, =UART_PADDR        @ physical
+                ldr     \rv, =UART_VADDR        @ virtual
+                .endm
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+                .macro  waituart,rd,rx
+                .endm
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S
new file mode 100644
index 000000000000..04eb56d5db2c
--- /dev/null
+++ b/arch/arm/include/debug/sunxi.S
@@ -0,0 +1,27 @@
+/*
+ * Early serial output macro for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#if defined(CONFIG_DEBUG_SUNXI_UART0)
+#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28000
+#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28000
+#elif defined(CONFIG_DEBUG_SUNXI_UART1)
+#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400
+#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400
+#endif
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =SUNXI_UART_DEBUG_PHYS_BASE
+        ldr     \rv, =SUNXI_UART_DEBUG_VIRT_BASE
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
new file mode 100644
index 000000000000..883d7c22fd9d
--- /dev/null
+++ b/arch/arm/include/debug/tegra.S
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2010,2011 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *      Doug Anderson <dianders@chromium.org>
+ *      Stephen Warren <swarren@nvidia.com>
+ *
+ * Portions based on mach-omap2's debug-macro.S
+ * Copyright (C) 1994-1999 Russell King
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/serial_reg.h>
+#define UART_SHIFT 2
+/* Physical addresses */
+#define TEGRA_CLK_RESET_BASE            0x60006000
+#define TEGRA_APB_MISC_BASE             0x70000000
+#define TEGRA_UARTA_BASE                0x70006000
+#define TEGRA_UARTB_BASE                0x70006040
+#define TEGRA_UARTC_BASE                0x70006200
+#define TEGRA_UARTD_BASE                0x70006300
+#define TEGRA_UARTE_BASE                0x70006400
+#define TEGRA_PMC_BASE                  0x7000e400
+#define TEGRA_CLK_RST_DEVICES_L         (TEGRA_CLK_RESET_BASE + 0x04)
+#define TEGRA_CLK_RST_DEVICES_H         (TEGRA_CLK_RESET_BASE + 0x08)
+#define TEGRA_CLK_RST_DEVICES_U         (TEGRA_CLK_RESET_BASE + 0x0c)
+#define TEGRA_CLK_OUT_ENB_L             (TEGRA_CLK_RESET_BASE + 0x10)
+#define TEGRA_CLK_OUT_ENB_H             (TEGRA_CLK_RESET_BASE + 0x14)
+#define TEGRA_CLK_OUT_ENB_U             (TEGRA_CLK_RESET_BASE + 0x18)
+#define TEGRA_PMC_SCRATCH20             (TEGRA_PMC_BASE + 0xa0)
+#define TEGRA_APB_MISC_GP_HIDREV        (TEGRA_APB_MISC_BASE + 0x804)
+/*
+ * Must be 1MB-aligned since a 1MB mapping is used early on.
+ * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
+ */
+#define UART_VIRTUAL_BASE               0xfe100000
+#define checkuart(rp, rv, lhu, bit, uart) \
+                /* Load address of CLK_RST register */ \
+                movw    rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
+                movt    rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
+                /* Load value from CLK_RST register */ \
+                ldr     rp, [rp, #0] ; \
+                /* Test UART's reset bit */ \
+                tst     rp, #(1 << bit) ; \
+                /* If set, can't use UART; jump to save no UART */ \
+                bne     90f ; \
+                /* Load address of CLK_OUT_ENB register */ \
+                movw    rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
+                movt    rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
+                /* Load value from CLK_OUT_ENB register */ \
+                ldr     rp, [rp, #0] ; \
+                /* Test UART's clock enable bit */ \
+                tst     rp, #(1 << bit) ; \
+                /* If clear, can't use UART; jump to save no UART */ \
+                beq     90f ; \
+                /* Passed all tests, load address of UART registers */ \
+                movw    rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
+                movt    rp, #TEGRA_UART##uart##_BASE >> 16 ; \
+                /* Jump to save UART address */ \
+                b 91f
+                .macro  addruart, rp, rv, tmp
+                adr     \rp, 99f                @ actual addr of 99f
+                ldr     \rv, [\rp]              @ linked addr is stored there
+                sub     \rv, \rv, \rp           @ offset between the two
+                ldr     \rp, [\rp, #4]          @ linked tegra_uart_config
+                sub     \tmp, \rp, \rv          @ actual tegra_uart_config
+                ldr     \rp, [\tmp]             @ Load tegra_uart_config
+                cmp     \rp, #1                 @ needs initialization?
+                bne     100f                    @ no; go load the addresses
+                mov     \rv, #0                 @ yes; record init is done
+                str     \rv, [\tmp]
+#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
+                /* Check ODMDATA */
+10:             movw    \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
+                movt    \rp, #TEGRA_PMC_SCRATCH20 >> 16
+                ldr     \rp, [\rp, #0]          @ Load PMC_SCRATCH20
+                ubfx    \rv, \rp, #18, #2       @ 19:18 are console type
+                cmp     \rv, #2                 @ 2 and 3 mean DCC, UART
+                beq     11f                     @ some boards swap the meaning
+                cmp     \rv, #3                 @ so accept either
+                bne     90f
+11:             ubfx    \rv, \rp, #15, #3       @ 17:15 are UART ID
+                cmp     \rv, #0                 @ UART 0?
+                beq     20f
+                cmp     \rv, #1                 @ UART 1?
+                beq     21f
+                cmp     \rv, #2                 @ UART 2?
+                beq     22f
+                cmp     \rv, #3                 @ UART 3?
+                beq     23f
+                cmp     \rv, #4                 @ UART 4?
+                beq     24f
+                b       90f                     @ invalid
+#endif
+#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
+    defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+                /* Check UART A validity */
+20:             checkuart(\rp, \rv, L, 6, A)
+#endif
+#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
+    defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+                /* Check UART B validity */
+21:             checkuart(\rp, \rv, L, 7, B)
+#endif
+#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
+    defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+                /* Check UART C validity */
+22:             checkuart(\rp, \rv, H, 23, C)
+#endif
+#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
+    defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+                /* Check UART D validity */
+23:             checkuart(\rp, \rv, U, 1, D)
+#endif
+#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
+    defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+                /* Check UART E validity */
+24:
+                checkuart(\rp, \rv, U, 2, E)
+#endif
+                /* No valid UART found */
+90:             mov     \rp, #0
+                /* fall through */
+                /* Record whichever UART we chose */
+91:             str     \rp, [\tmp, #4]         @ Store in tegra_uart_phys
+                cmp     \rp, #0                 @ Valid UART address?
+                bne     92f                     @ Yes, go process it
+                str     \rp, [\tmp, #8]         @ Store 0 in tegra_uart_virt
+                b       100f                    @ Done
+92:             and     \rv, \rp, #0xffffff     @ offset within 1MB section
+                add     \rv, \rv, #UART_VIRTUAL_BASE
+                str     \rv, [\tmp, #8]         @ Store in tegra_uart_virt
+                movw    \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
+                movt    \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
+                ldr     \rv, [\rv, #0]          @ Load HIDREV
+                ubfx    \rv, \rv, #8, #8        @ 15:8 are SoC version
+                cmp     \rv, #0x20              @ Tegra20?
+                moveq   \rv, #0x75              @ Tegra20 divisor
+                movne   \rv, #0xdd              @ Tegra30 divisor
+                str     \rv, [\tmp, #12]        @ Save divisor to scratch
+                /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
+                mov     \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
+                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
+                /* uart[UART_DLL] = div & 0xff; */
+                ldr     \rv, [\tmp, #12]
+                and     \rv, \rv, #0xff
+                str     \rv, [\rp, #UART_DLL << UART_SHIFT]
+                /* uart[UART_DLM] = div >> 8; */
+                ldr     \rv, [\tmp, #12]
+                lsr     \rv, \rv, #8
+                str     \rv, [\rp, #UART_DLM << UART_SHIFT]
+                /* uart[UART_LCR] = UART_LCR_WLEN8; */
+                mov     \rv, #UART_LCR_WLEN8
+                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
+                b       100f
+                .align
+99:             .word   .
+                .word   tegra_uart_config
+                .ltorg
+                /* Load previously selected UART address */
+100:            ldr     \rp, [\tmp, #4]         @ Load tegra_uart_phys
+                ldr     \rv, [\tmp, #8]         @ Load tegra_uart_virt
+                .endm
+/*
+ * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
+ * check to make sure that the UART address is actually valid.
+ */
+                .macro  senduart, rd, rx
+                cmp     \rx, #0
+                strneb  \rd, [\rx, #UART_TX << UART_SHIFT]
+1001:
+                .endm
+                .macro  busyuart, rd, rx
+                cmp     \rx, #0
+                beq     1002f
+1001:           ldrb    \rd, [\rx, #UART_LSR << UART_SHIFT]
+                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                bne     1001b
+1002:
+                .endm
+                .macro  waituart, rd, rx
+#ifdef FLOW_CONTROL
+                cmp     \rx, #0
+                beq     1002f
+1001:           ldrb    \rd, [\rx, #UART_MSR << UART_SHIFT]
+                tst     \rd, #UART_MSR_CTS
+                beq     1001b
+1002:
+#endif
+                .endm
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index 9f509f55d078..dc8e882a6257 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -21,14 +21,17 @@
 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
                .macro  addruart,rp,rv,tmp
+                .arch   armv7-a
                @ Make an educated guess regarding the memory map:
-                @ - the original A9 core tile, which has MPCore peripherals
+                @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
-                @   located at 0x1e000000, should use UART at 0x10009000
+                @   should use UART at 0x10009000
                @ - all other (RS1 complaint) tiles use UART mapped
                @   at 0x1c090000
-                mrc     p15, 4, \tmp, c15, c0, 0
+                mrc     p15, 0, \rp, c0, c0, 0
-                cmp     \tmp, #0x1e000000
+                movw    \rv, #0xc091
+                movt    \rv, #0x410f
+                cmp     \rp, \rv
                @ Original memory map
                moveq   \rp, #DEBUG_LL_UART_OFFSET
diff --git a/arch/arm/mach-zynq/include/mach/debug-macro.S b/arch/arm/include/debug/zynq.S
index 3ab0be1f6191..f9aa9740a73f 100644
--- a/arch/arm/mach-zynq/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/zynq.S
@@ -1,5 +1,4 @@
-/* arch/arm/mach-zynq/include/mach/debug-macro.S
+/*
- *
 * Debugging macro include header
 *
 *  Copyright (C) 2011 Xilinx
@@ -13,9 +12,25 @@
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
+#define UART_CR_OFFSET          0x00  /* Control Register [8:0] */
+#define UART_SR_OFFSET          0x2C  /* Channel Status [11:0] */
+#define UART_FIFO_OFFSET        0x30  /* FIFO [15:0] or [7:0] */
+#define UART_SR_TXFULL          0x00000010      /* TX FIFO full */
+#define UART_SR_TXEMPTY         0x00000008      /* TX FIFO empty */
+#define UART0_PHYS              0xE0000000
+#define UART1_PHYS              0xE0001000
+#define UART_SIZE               SZ_4K
+#define UART_VIRT               0xF0001000
+#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
+# define LL_UART_PADDR          UART1_PHYS
+#else
+# define LL_UART_PADDR          UART0_PHYS
+#endif
-#include <mach/zynq_soc.h>
+#define LL_UART_VADDR           UART_VIRT
-#include <mach/uart.h>
                .macro  addruart, rp, rv, tmp
                ldr     \rp, =LL_UART_PADDR     @ physical
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 831cd38c8d99..5935b6a02e6e 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -11,7 +11,7 @@
 */
 /* 0 */         CALL(sys_restart_syscall)
                CALL(sys_exit)
-                CALL(sys_fork_wrapper)
+                CALL(sys_fork)
                CALL(sys_read)
                CALL(sys_write)
 /* 5 */         CALL(sys_open)
@@ -129,7 +129,7 @@
                CALL(OBSOLETE(ABI(sys_ipc, sys_oabi_ipc)))
                CALL(sys_fsync)
                CALL(sys_sigreturn_wrapper)
-/* 120 */       CALL(sys_clone_wrapper)
+/* 120 */       CALL(sys_clone)
                CALL(sys_setdomainname)
                CALL(sys_newuname)
                CALL(sys_ni_syscall)            /* modify_ldt */
@@ -199,7 +199,7 @@
                CALL(sys_sendfile)
                CALL(sys_ni_syscall)            /* getpmsg */
                CALL(sys_ni_syscall)            /* putpmsg */
-/* 190 */       CALL(sys_vfork_wrapper)
+/* 190 */       CALL(sys_vfork)
                CALL(sys_getrlimit)
                CALL(sys_mmap2)
                CALL(ABI(sys_truncate64, sys_oabi_truncate64))
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 66f711b2e0e8..6809200c31fb 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -100,6 +100,13 @@ ENTRY(printch)
                b       1b
 ENDPROC(printch)
+ENTRY(debug_ll_addr)
+                addruart r2, r3, ip
+                str     r2, [r0]
+                str     r3, [r1]
+                mov     pc, lr
+ENDPROC(debug_ll_addr)
 #else
 ENTRY(printascii)
@@ -119,4 +126,11 @@ ENTRY(printch)
                mov     pc, lr
 ENDPROC(printch)
+ENTRY(debug_ll_addr)
+                mov     r2, #0
+                str     r2, [r0]
+                str     r2, [r1]
+                mov     pc, lr
+ENDPROC(debug_ll_addr)
 #endif
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index bee7f9d47f02..70f1bdeb241b 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -19,8 +19,10 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/cputype.h>
 #include <asm/setup.h>
 #include <asm/page.h>
+#include <asm/smp_plat.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -61,6 +63,108 @@ void __init arm_dt_memblock_reserve(void)
        }
 }
+/*
+ * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
+ * and builds the cpu logical map array containing MPIDR values related to
+ * logical cpus
+ *
+ * Updates the cpu possible mask with the number of parsed cpu nodes
+ */
+void __init arm_dt_init_cpu_maps(void)
+{
+        /*
+         * Temp logical map is initialized with UINT_MAX values that are
+         * considered invalid logical map entries since the logical map must
+         * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
+         * read as 0.
+         */
+        struct device_node *cpu, *cpus;
+        u32 i, j, cpuidx = 1;
+        u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
+        u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
+        bool bootcpu_valid = false;
+        cpus = of_find_node_by_path("/cpus");
+        if (!cpus)
+                return;
+        for_each_child_of_node(cpus, cpu) {
+                u32 hwid;
+                pr_debug(" * %s...\n", cpu->full_name);
+                /*
+                 * A device tree containing CPU nodes with missing "reg"
+                 * properties is considered invalid to build the
+                 * cpu_logical_map.
+                 */
+                if (of_property_read_u32(cpu, "reg", &hwid)) {
+                        pr_debug(" * %s missing reg property\n",
+                                     cpu->full_name);
+                        return;
+                }
+                /*
+                 * 8 MSBs must be set to 0 in the DT since the reg property
+                 * defines the MPIDR[23:0].
+                 */
+                if (hwid & ~MPIDR_HWID_BITMASK)
+                        return;
+                /*
+                 * Duplicate MPIDRs are a recipe for disaster.
+                 * Scan all initialized entries and check for
+                 * duplicates. If any is found just bail out.
+                 * temp values were initialized to UINT_MAX
+                 * to avoid matching valid MPIDR[23:0] values.
+                 */
+                for (j = 0; j < cpuidx; j++)
+                        if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
+                                                     "properties in the DT\n"))
+                                return;
+                /*
+                 * Build a stashed array of MPIDR values. Numbering scheme
+                 * requires that if detected the boot CPU must be assigned
+                 * logical id 0. Other CPUs get sequential indexes starting
+                 * from 1. If a CPU node with a reg property matching the
+                 * boot CPU MPIDR is detected, this is recorded so that the
+                 * logical map built from DT is validated and can be used
+                 * to override the map created in smp_setup_processor_id().
+                 */
+                if (hwid == mpidr) {
+                        i = 0;
+                        bootcpu_valid = true;
+                } else {
+                        i = cpuidx++;
+                }
+                if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
+                                               "max cores %u, capping them\n",
+                                               cpuidx, nr_cpu_ids)) {
+                        cpuidx = nr_cpu_ids;
+                        break;
+                }
+                tmp_map[i] = hwid;
+        }
+        if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
+                                 "fall back to default cpu_logical_map\n"))
+                return;
+        /*
+         * Since the boot CPU node contains proper data, and all nodes have
+         * a reg property, the DT CPU list can be considered valid and the
+         * logical map created in smp_setup_processor_id() can be overridden
+         */
+        for (i = 0; i < cpuidx; i++) {
+                set_cpu_possible(i, true);
+                cpu_logical_map(i) = tmp_map[i];
+                pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
+        }
+}
 /**
 * setup_machine_fdt - Machine setup when an dtb was passed to the kernel
 * @dt_phys: physical address of dt blob
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 34711757ba59..a6c301e90a3b 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -417,16 +417,6 @@ local_restart:
        ldr     r10, [tsk, #TI_FLAGS]           @ check for syscall tracing
        stmdb   sp!, {r4, r5}                   @ push fifth and sixth args
-#ifdef CONFIG_SECCOMP
-        tst     r10, #_TIF_SECCOMP
-        beq     1f
-        mov     r0, scno
-        bl      __secure_computing      
-        add     r0, sp, #S_R0 + S_OFF           @ pointer to regs
-        ldmia   r0, {r0 - r3}                   @ have to reload r0 - r3
-1:
-#endif
        tst     r10, #_TIF_SYSCALL_WORK         @ are we tracing syscalls?
        bne     __sys_trace
@@ -458,11 +448,13 @@ __sys_trace:
        ldmccia r1, {r0 - r6}                   @ have to reload r0 - r6
        stmccia sp, {r4, r5}                    @ and update the stack args
        ldrcc   pc, [tbl, scno, lsl #2]         @ call sys_* routine
-        b       2b
+        cmp     scno, #-1                       @ skip the syscall?
+        bne     2b
+        add     sp, sp, #S_OFF                  @ restore stack
+        b       ret_slow_syscall
 __sys_trace_return:
        str     r0, [sp, #S_R0 + S_OFF]!        @ save returned r0
-        mov     r1, scno
        mov     r0, sp
        bl      syscall_trace_exit
        b       ret_slow_syscall
@@ -510,22 +502,6 @@ sys_syscall:
                b       sys_ni_syscall
 ENDPROC(sys_syscall)
-sys_fork_wrapper:
-                add     r0, sp, #S_OFF
-                b       sys_fork
-ENDPROC(sys_fork_wrapper)
-sys_vfork_wrapper:
-                add     r0, sp, #S_OFF
-                b       sys_vfork
-ENDPROC(sys_vfork_wrapper)
-sys_clone_wrapper:
-                add     ip, sp, #S_OFF
-                str     ip, [sp, #4]
-                b       sys_clone
-ENDPROC(sys_clone_wrapper)
 sys_sigreturn_wrapper:
                add     r0, sp, #S_OFF
                mov     why, #0         @ prevent syscall restart handling
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 278cfc144f44..2c228a07e58c 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -68,7 +68,7 @@ __after_proc_init:
         * CP15 system control register value returned in r0 from
         * the CPU init function.
         */
-#ifdef CONFIG_ALIGNMENT_TRAP
+#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
        orr     r0, r0, #CR_A
 #else
        bic     r0, r0, #CR_A
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 281bf3301241..5ff2e77782b1 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -52,14 +52,14 @@ static u8 debug_arch;
 /* Maximum supported watchpoint length. */
 static u8 max_watchpoint_len;
-#define READ_WB_REG_CASE(OP2, M, VAL)           \
+#define READ_WB_REG_CASE(OP2, M, VAL)                   \
-        case ((OP2 << 4) + M):                  \
+        case ((OP2 << 4) + M):                          \
-                ARM_DBG_READ(c ## M, OP2, VAL); \
+                ARM_DBG_READ(c0, c ## M, OP2, VAL);     \
                break
-#define WRITE_WB_REG_CASE(OP2, M, VAL)          \
+#define WRITE_WB_REG_CASE(OP2, M, VAL)                  \
-        case ((OP2 << 4) + M):                  \
+        case ((OP2 << 4) + M):                          \
-                ARM_DBG_WRITE(c ## M, OP2, VAL);\
+                ARM_DBG_WRITE(c0, c ## M, OP2, VAL);    \
                break
 #define GEN_READ_WB_REG_CASES(OP2, VAL)         \
@@ -136,12 +136,12 @@ static u8 get_debug_arch(void)
        /* Do we implement the extended CPUID interface? */
        if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
-                pr_warning("CPUID feature registers not supported. "
+                pr_warn_once("CPUID feature registers not supported. "
-                           "Assuming v6 debug is present.\n");
+                             "Assuming v6 debug is present.\n");
                return ARM_DEBUG_ARCH_V6;
        }
-        ARM_DBG_READ(c0, 0, didr);
+        ARM_DBG_READ(c0, c0, 0, didr);
        return (didr >> 16) & 0xf;
 }
@@ -169,7 +169,7 @@ static int debug_exception_updates_fsr(void)
 static int get_num_wrp_resources(void)
 {
        u32 didr;
-        ARM_DBG_READ(c0, 0, didr);
+        ARM_DBG_READ(c0, c0, 0, didr);
        return ((didr >> 28) & 0xf) + 1;
 }
@@ -177,7 +177,7 @@ static int get_num_wrp_resources(void)
 static int get_num_brp_resources(void)
 {
        u32 didr;
-        ARM_DBG_READ(c0, 0, didr);
+        ARM_DBG_READ(c0, c0, 0, didr);
        return ((didr >> 24) & 0xf) + 1;
 }
@@ -228,19 +228,17 @@ static int get_num_brps(void)
 * be put into halting debug mode at any time by an external debugger
 * but there is nothing we can do to prevent that.
 */
-static int enable_monitor_mode(void)
+static int monitor_mode_enabled(void)
 {
        u32 dscr;
-        int ret = 0;
+        ARM_DBG_READ(c0, c1, 0, dscr);
+        return !!(dscr & ARM_DSCR_MDBGEN);
-        ARM_DBG_READ(c1, 0, dscr);
+}
-        /* Ensure that halting mode is disabled. */
+static int enable_monitor_mode(void)
-        if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN,
+{
-                "halting debug mode enabled. Unable to access hardware resources.\n")) {
+        u32 dscr;
-                ret = -EPERM;
+        ARM_DBG_READ(c0, c1, 0, dscr);
-                goto out;
-        }
        /* If monitor mode is already enabled, just return. */
        if (dscr & ARM_DSCR_MDBGEN)
@@ -250,24 +248,27 @@ static int enable_monitor_mode(void)
        switch (get_debug_arch()) {
        case ARM_DEBUG_ARCH_V6:
        case ARM_DEBUG_ARCH_V6_1:
-                ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
+                ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
                break;
        case ARM_DEBUG_ARCH_V7_ECP14:
        case ARM_DEBUG_ARCH_V7_1:
-                ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
+                ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
+                isb();
                break;
        default:
-                ret = -ENODEV;
+                return -ENODEV;
-                goto out;
        }
        /* Check that the write made it through. */
-        ARM_DBG_READ(c1, 0, dscr);
+        ARM_DBG_READ(c0, c1, 0, dscr);
-        if (!(dscr & ARM_DSCR_MDBGEN))
+        if (!(dscr & ARM_DSCR_MDBGEN)) {
-                ret = -EPERM;
+                pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
+                                smp_processor_id());
+                return -EPERM;
+        }
 out:
-        return ret;
+        return 0;
 }
 int hw_breakpoint_slots(int type)
@@ -328,14 +329,9 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
 {
        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
        struct perf_event **slot, **slots;
-        int i, max_slots, ctrl_base, val_base, ret = 0;
+        int i, max_slots, ctrl_base, val_base;
        u32 addr, ctrl;
-        /* Ensure that we are in monitor mode and halting mode is disabled. */
-        ret = enable_monitor_mode();
-        if (ret)
-                goto out;
        addr = info->address;
        ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
@@ -362,9 +358,9 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
                }
        }
-        if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) {
+        if (i == max_slots) {
-                ret = -EBUSY;
+                pr_warning("Can't find any breakpoint slot\n");
-                goto out;
+                return -EBUSY;
        }
        /* Override the breakpoint data with the step data. */
@@ -383,9 +379,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
        /* Setup the control register. */
        write_wb_reg(ctrl_base + i, ctrl);
+        return 0;
-out:
-        return ret;
 }
 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
@@ -416,8 +410,10 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
                }
        }
-        if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n"))
+        if (i == max_slots) {
+                pr_warning("Can't find any breakpoint slot\n");
                return;
+        }
        /* Ensure that we disable the mismatch breakpoint. */
        if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
@@ -596,6 +592,10 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
        int ret = 0;
        u32 offset, alignment_mask = 0x3;
+        /* Ensure that we are in monitor debug mode. */
+        if (!monitor_mode_enabled())
+                return -ENODEV;
        /* Build the arch_hw_breakpoint. */
        ret = arch_build_bp_info(bp);
        if (ret)
@@ -858,7 +858,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
                local_irq_enable();
        /* We only handle watchpoints and hardware breakpoints. */
-        ARM_DBG_READ(c1, 0, dscr);
+        ARM_DBG_READ(c0, c1, 0, dscr);
        /* Perform perf callbacks. */
        switch (ARM_DSCR_MOE(dscr)) {
@@ -906,7 +906,7 @@ static struct undef_hook debug_reg_hook = {
 static void reset_ctrl_regs(void *unused)
 {
        int i, raw_num_brps, err = 0, cpu = smp_processor_id();
-        u32 dbg_power;
+        u32 val;
        /*
         * v7 debug contains save and restore registers so that debug state
@@ -919,23 +919,30 @@ static void reset_ctrl_regs(void *unused)
        switch (debug_arch) {
        case ARM_DEBUG_ARCH_V6:
        case ARM_DEBUG_ARCH_V6_1:
-                /* ARMv6 cores just need to reset the registers. */
+                /* ARMv6 cores clear the registers out of reset. */
-                goto reset_regs;
+                goto out_mdbgen;
        case ARM_DEBUG_ARCH_V7_ECP14:
                /*
                 * Ensure sticky power-down is clear (i.e. debug logic is
                 * powered up).
                 */
-                asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
+                ARM_DBG_READ(c1, c5, 4, val);
-                if ((dbg_power & 0x1) == 0)
+                if ((val & 0x1) == 0)
                        err = -EPERM;
+                /*
+                 * Check whether we implement OS save and restore.
+                 */
+                ARM_DBG_READ(c1, c1, 4, val);
+                if ((val & 0x9) == 0)
+                        goto clear_vcr;
                break;
        case ARM_DEBUG_ARCH_V7_1:
                /*
                 * Ensure the OS double lock is clear.
                 */
-                asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (dbg_power));
+                ARM_DBG_READ(c1, c3, 4, val);
-                if ((dbg_power & 0x1) == 1)
+                if ((val & 0x1) == 1)
                        err = -EPERM;
                break;
        }
@@ -947,24 +954,29 @@ static void reset_ctrl_regs(void *unused)
        }
        /*
-         * Unconditionally clear the lock by writing a value
+         * Unconditionally clear the OS lock by writing a value
         * other than 0xC5ACCE55 to the access register.
         */
-        asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
+        ARM_DBG_WRITE(c1, c0, 4, 0);
        isb();
        /*
         * Clear any configured vector-catch events before
         * enabling monitor mode.
         */
-        asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
+clear_vcr:
+        ARM_DBG_WRITE(c0, c7, 0, 0);
        isb();
-reset_regs:
+        if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
-        if (enable_monitor_mode())
+                pr_warning("CPU %d failed to disable vector catch\n", cpu);
                return;
+        }
-        /* We must also reset any reserved registers. */
+        /*
+         * The control/value register pairs are UNKNOWN out of reset so
+         * clear them to avoid spurious debug events.
+         */
        raw_num_brps = get_num_brp_resources();
        for (i = 0; i < raw_num_brps; ++i) {
                write_wb_reg(ARM_BASE_BCR + i, 0UL);
@@ -975,6 +987,19 @@ reset_regs:
                write_wb_reg(ARM_BASE_WCR + i, 0UL);
                write_wb_reg(ARM_BASE_WVR + i, 0UL);
        }
+        if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
+                pr_warning("CPU %d failed to clear debug register pairs\n", cpu);
+                return;
+        }
+        /*
+         * Have a crack at enabling monitor mode. We don't actually need
+         * it yet, but reporting an error early is useful if it fails.
+         */
+out_mdbgen:
+        if (enable_monitor_mode())
+                cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
 }
 static int __cpuinit dbg_reset_notify(struct notifier_block *self,
@@ -992,8 +1017,6 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
 static int __init arch_hw_breakpoint_init(void)
 {
-        u32 dscr;
        debug_arch = get_debug_arch();
        if (!debug_arch_supported()) {
@@ -1028,17 +1051,10 @@ static int __init arch_hw_breakpoint_init(void)
                core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
                "", core_num_wrps);
-        ARM_DBG_READ(c1, 0, dscr);
+        /* Work out the maximum supported watchpoint length. */
-        if (dscr & ARM_DSCR_HDBGEN) {
+        max_watchpoint_len = get_max_wp_len();
-                max_watchpoint_len = 4;
+        pr_info("maximum watchpoint size is %u bytes.\n",
-                pr_warning("halting debug mode enabled. Assuming maximum watchpoint size of %u bytes.\n",
+                        max_watchpoint_len);
-                           max_watchpoint_len);
-        } else {
-                /* Work out the maximum supported watchpoint length. */
-                max_watchpoint_len = get_max_wp_len();
-                pr_info("maximum watchpoint size is %u bytes.\n",
-                                max_watchpoint_len);
-        }
        /* Register debug fault handler. */
        hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
index 1862d8f2fd44..0cd63d080c7b 100644
--- a/arch/arm/kernel/kprobes-test.c
+++ b/arch/arm/kernel/kprobes-test.c
@@ -1598,7 +1598,7 @@ static int __init run_all_tests(void)
 {
        int ret = 0;
-        pr_info("Begining kprobe tests...\n");
+        pr_info("Beginning kprobe tests...\n");
 #ifndef CONFIG_THUMB2_KERNEL
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 53c0304b734a..f9e8657dd241 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -86,12 +86,10 @@ armpmu_map_event(struct perf_event *event,
        return -ENOENT;
 }
-int
+int armpmu_event_set_period(struct perf_event *event)
-armpmu_event_set_period(struct perf_event *event,
-                        struct hw_perf_event *hwc,
-                        int idx)
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        s64 left = local64_read(&hwc->period_left);
        s64 period = hwc->sample_period;
        int ret = 0;
@@ -119,24 +117,22 @@ armpmu_event_set_period(struct perf_event *event,
        local64_set(&hwc->prev_count, (u64)-left);
-        armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
+        armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
        perf_event_update_userpage(event);
        return ret;
 }
-u64
+u64 armpmu_event_update(struct perf_event *event)
-armpmu_event_update(struct perf_event *event,
-                    struct hw_perf_event *hwc,
-                    int idx)
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        u64 delta, prev_raw_count, new_raw_count;
 again:
        prev_raw_count = local64_read(&hwc->prev_count);
-        new_raw_count = armpmu->read_counter(idx);
+        new_raw_count = armpmu->read_counter(event);
        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
                             new_raw_count) != prev_raw_count)
@@ -159,7 +155,7 @@ armpmu_read(struct perf_event *event)
        if (hwc->idx < 0)
                return;
-        armpmu_event_update(event, hwc, hwc->idx);
+        armpmu_event_update(event);
 }
 static void
@@ -173,14 +169,13 @@ armpmu_stop(struct perf_event *event, int flags)
         * PERF_EF_UPDATE, see comments in armpmu_start().
         */
        if (!(hwc->state & PERF_HES_STOPPED)) {
-                armpmu->disable(hwc, hwc->idx);
+                armpmu->disable(event);
-                armpmu_event_update(event, hwc, hwc->idx);
+                armpmu_event_update(event);
                hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
        }
 }
-static void
+static void armpmu_start(struct perf_event *event, int flags)
-armpmu_start(struct perf_event *event, int flags)
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
@@ -200,8 +195,8 @@ armpmu_start(struct perf_event *event, int flags)
         * get an interrupt too soon or *way* too late if the overflow has
         * happened since disabling.
         */
-        armpmu_event_set_period(event, hwc, hwc->idx);
+        armpmu_event_set_period(event);
-        armpmu->enable(hwc, hwc->idx);
+        armpmu->enable(event);
 }
 static void
@@ -233,7 +228,7 @@ armpmu_add(struct perf_event *event, int flags)
        perf_pmu_disable(event->pmu);
        /* If we don't have a space for the counter then finish early. */
-        idx = armpmu->get_event_idx(hw_events, hwc);
+        idx = armpmu->get_event_idx(hw_events, event);
        if (idx < 0) {
                err = idx;
                goto out;
@@ -244,7 +239,7 @@ armpmu_add(struct perf_event *event, int flags)
         * sure it is disabled.
         */
        event->hw.idx = idx;
-        armpmu->disable(hwc, idx);
+        armpmu->disable(event);
        hw_events->events[idx] = event;
        hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
@@ -264,13 +259,12 @@ validate_event(struct pmu_hw_events *hw_events,
               struct perf_event *event)
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
-        struct hw_perf_event fake_event = event->hw;
        struct pmu *leader_pmu = event->group_leader->pmu;
        if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
                return 1;
-        return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
+        return armpmu->get_event_idx(hw_events, event) >= 0;
 }
 static int
@@ -316,7 +310,7 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 static void
 armpmu_release_hardware(struct arm_pmu *armpmu)
 {
-        armpmu->free_irq();
+        armpmu->free_irq(armpmu);
        pm_runtime_put_sync(&armpmu->plat_device->dev);
 }
@@ -330,7 +324,7 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
                return -ENODEV;
        pm_runtime_get_sync(&pmu_device->dev);
-        err = armpmu->request_irq(armpmu_dispatch_irq);
+        err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
        if (err) {
                armpmu_release_hardware(armpmu);
                return err;
@@ -465,13 +459,13 @@ static void armpmu_enable(struct pmu *pmu)
        int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
        if (enabled)
-                armpmu->start();
+                armpmu->start(armpmu);
 }
 static void armpmu_disable(struct pmu *pmu)
 {
        struct arm_pmu *armpmu = to_arm_pmu(pmu);
-        armpmu->stop();
+        armpmu->stop(armpmu);
 }
 #ifdef CONFIG_PM_RUNTIME
@@ -517,12 +511,13 @@ static void __init armpmu_init(struct arm_pmu *armpmu)
        };
 }
-int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, int type)
 {
        armpmu_init(armpmu);
+        pm_runtime_enable(&armpmu->plat_device->dev);
        pr_info("enabled with %s PMU driver, %d counters available\n",
                        armpmu->name, armpmu->num_events);
-        return perf_pmu_register(&armpmu->pmu, name, type);
+        return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
 }
 /*
@@ -576,6 +571,10 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
        struct frame_tail __user *tail;
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+                /* We don't support guest os callchain now */
+                return;
+        }
        tail = (struct frame_tail __user *)regs->ARM_fp - 1;
@@ -603,9 +602,41 @@ perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
        struct stackframe fr;
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+                /* We don't support guest os callchain now */
+                return;
+        }
        fr.fp = regs->ARM_fp;
        fr.sp = regs->ARM_sp;
        fr.lr = regs->ARM_lr;
        fr.pc = regs->ARM_pc;
        walk_stackframe(&fr, callchain_trace, entry);
 }
+unsigned long perf_instruction_pointer(struct pt_regs *regs)
+{
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
+                return perf_guest_cbs->get_guest_ip();
+        return instruction_pointer(regs);
+}
+unsigned long perf_misc_flags(struct pt_regs *regs)
+{
+        int misc = 0;
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+                if (perf_guest_cbs->is_user_mode())
+                        misc |= PERF_RECORD_MISC_GUEST_USER;
+                else
+                        misc |= PERF_RECORD_MISC_GUEST_KERNEL;
+        } else {
+                if (user_mode(regs))
+                        misc |= PERF_RECORD_MISC_USER;
+                else
+                        misc |= PERF_RECORD_MISC_KERNEL;
+        }
+        return misc;
+}
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 8d7d8d4de9d6..9a4f6307a016 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -23,6 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <asm/cputype.h>
@@ -45,7 +46,7 @@ const char *perf_pmu_name(void)
        if (!cpu_pmu)
                return NULL;
-        return cpu_pmu->pmu.name;
+        return cpu_pmu->name;
 }
 EXPORT_SYMBOL_GPL(perf_pmu_name);
@@ -70,7 +71,7 @@ static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
        return &__get_cpu_var(cpu_hw_events);
 }
-static void cpu_pmu_free_irq(void)
+static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
 {
        int i, irq, irqs;
        struct platform_device *pmu_device = cpu_pmu->plat_device;
@@ -86,7 +87,7 @@ static void cpu_pmu_free_irq(void)
        }
 }
-static int cpu_pmu_request_irq(irq_handler_t handler)
+static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 {
        int i, err, irq, irqs;
        struct platform_device *pmu_device = cpu_pmu->plat_device;
@@ -147,7 +148,7 @@ static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
        /* Ensure the PMU has sane values out of reset. */
        if (cpu_pmu && cpu_pmu->reset)
-                on_each_cpu(cpu_pmu->reset, NULL, 1);
+                on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
 }
 /*
@@ -163,7 +164,9 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
                return NOTIFY_DONE;
        if (cpu_pmu && cpu_pmu->reset)
-                cpu_pmu->reset(NULL);
+                cpu_pmu->reset(cpu_pmu);
+        else
+                return NOTIFY_DONE;
        return NOTIFY_OK;
 }
@@ -195,13 +198,13 @@ static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
 /*
 * CPU PMU identification and probing.
 */
-static struct arm_pmu *__devinit probe_current_pmu(void)
+static int __devinit probe_current_pmu(struct arm_pmu *pmu)
 {
-        struct arm_pmu *pmu = NULL;
        int cpu = get_cpu();
        unsigned long cpuid = read_cpuid_id();
        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
        unsigned long part_number = (cpuid & 0xFFF0);
+        int ret = -ENODEV;
        pr_info("probing PMU on CPU %d\n", cpu);
@@ -211,25 +214,25 @@ static struct arm_pmu *__devinit probe_current_pmu(void)
                case 0xB360:    /* ARM1136 */
                case 0xB560:    /* ARM1156 */
                case 0xB760:    /* ARM1176 */
-                        pmu = armv6pmu_init();
+                        ret = armv6pmu_init(pmu);
                        break;
                case 0xB020:    /* ARM11mpcore */
-                        pmu = armv6mpcore_pmu_init();
+                        ret = armv6mpcore_pmu_init(pmu);
                        break;
                case 0xC080:    /* Cortex-A8 */
-                        pmu = armv7_a8_pmu_init();
+                        ret = armv7_a8_pmu_init(pmu);
                        break;
                case 0xC090:    /* Cortex-A9 */
-                        pmu = armv7_a9_pmu_init();
+                        ret = armv7_a9_pmu_init(pmu);
                        break;
                case 0xC050:    /* Cortex-A5 */
-                        pmu = armv7_a5_pmu_init();
+                        ret = armv7_a5_pmu_init(pmu);
                        break;
                case 0xC0F0:    /* Cortex-A15 */
-                        pmu = armv7_a15_pmu_init();
+                        ret = armv7_a15_pmu_init(pmu);
                        break;
                case 0xC070:    /* Cortex-A7 */
-                        pmu = armv7_a7_pmu_init();
+                        ret = armv7_a7_pmu_init(pmu);
                        break;
                }
        /* Intel CPUs [xscale]. */
@@ -237,43 +240,54 @@ static struct arm_pmu *__devinit probe_current_pmu(void)
                part_number = (cpuid >> 13) & 0x7;
                switch (part_number) {
                case 1:
-                        pmu = xscale1pmu_init();
+                        ret = xscale1pmu_init(pmu);
                        break;
                case 2:
-                        pmu = xscale2pmu_init();
+                        ret = xscale2pmu_init(pmu);
                        break;
                }
        }
        put_cpu();
-        return pmu;
+        return ret;
 }
 static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
 {
        const struct of_device_id *of_id;
-        struct arm_pmu *(*init_fn)(void);
+        int (*init_fn)(struct arm_pmu *);
        struct device_node *node = pdev->dev.of_node;
+        struct arm_pmu *pmu;
+        int ret = -ENODEV;
        if (cpu_pmu) {
                pr_info("attempt to register multiple PMU devices!");
                return -ENOSPC;
        }
+        pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
+        if (!pmu) {
+                pr_info("failed to allocate PMU device!");
+                return -ENOMEM;
+        }
        if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
                init_fn = of_id->data;
-                cpu_pmu = init_fn();
+                ret = init_fn(pmu);
        } else {
-                cpu_pmu = probe_current_pmu();
+                ret = probe_current_pmu(pmu);
        }
-        if (!cpu_pmu)
+        if (ret) {
-                return -ENODEV;
+                pr_info("failed to register PMU devices!");
+                kfree(pmu);
+                return ret;
+        }
+        cpu_pmu = pmu;
        cpu_pmu->plat_device = pdev;
        cpu_pmu_init(cpu_pmu);
-        register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+        armpmu_register(cpu_pmu, PERF_TYPE_RAW);
-        armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
        return 0;
 }
@@ -290,6 +304,16 @@ static struct platform_driver cpu_pmu_driver = {
 static int __init register_pmu_driver(void)
 {
-        return platform_driver_register(&cpu_pmu_driver);
+        int err;
+        err = register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+        if (err)
+                return err;
+        err = platform_driver_register(&cpu_pmu_driver);
+        if (err)
+                unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);
+        return err;
 }
 device_initcall(register_pmu_driver);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 6ccc07971745..f3e22ff8b6a2 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -401,9 +401,10 @@ armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
        return ret;
 }
-static inline u32
+static inline u32 armv6pmu_read_counter(struct perf_event *event)
-armv6pmu_read_counter(int counter)
 {
+        struct hw_perf_event *hwc = &event->hw;
+        int counter = hwc->idx;
        unsigned long value = 0;
        if (ARMV6_CYCLE_COUNTER == counter)
@@ -418,10 +419,11 @@ armv6pmu_read_counter(int counter)
        return value;
 }
-static inline void
+static inline void armv6pmu_write_counter(struct perf_event *event, u32 value)
-armv6pmu_write_counter(int counter,
-                       u32 value)
 {
+        struct hw_perf_event *hwc = &event->hw;
+        int counter = hwc->idx;
        if (ARMV6_CYCLE_COUNTER == counter)
                asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
        else if (ARMV6_COUNTER0 == counter)
@@ -432,12 +434,13 @@ armv6pmu_write_counter(int counter,
                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
 }
-static void
+static void armv6pmu_enable_event(struct perf_event *event)
-armv6pmu_enable_event(struct hw_perf_event *hwc,
-                      int idx)
 {
        unsigned long val, mask, evt, flags;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
        if (ARMV6_CYCLE_COUNTER == idx) {
                mask    = 0;
@@ -473,7 +476,8 @@ armv6pmu_handle_irq(int irq_num,
 {
        unsigned long pmcr = armv6_pmcr_read();
        struct perf_sample_data data;
-        struct pmu_hw_events *cpuc;
+        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
+        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
        struct pt_regs *regs;
        int idx;
@@ -489,7 +493,6 @@ armv6pmu_handle_irq(int irq_num,
         */
        armv6_pmcr_write(pmcr);
-        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
                struct hw_perf_event *hwc;
@@ -506,13 +509,13 @@ armv6pmu_handle_irq(int irq_num,
                        continue;
                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
+                armpmu_event_update(event);
                perf_sample_data_init(&data, 0, hwc->last_period);
-                if (!armpmu_event_set_period(event, hwc, idx))
+                if (!armpmu_event_set_period(event))
                        continue;
                if (perf_event_overflow(event, &data, regs))
-                        cpu_pmu->disable(hwc, idx);
+                        cpu_pmu->disable(event);
        }
        /*
@@ -527,8 +530,7 @@ armv6pmu_handle_irq(int irq_num,
        return IRQ_HANDLED;
 }
-static void
+static void armv6pmu_start(struct arm_pmu *cpu_pmu)
-armv6pmu_start(void)
 {
        unsigned long flags, val;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -540,8 +542,7 @@ armv6pmu_start(void)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void
+static void armv6pmu_stop(struct arm_pmu *cpu_pmu)
-armv6pmu_stop(void)
 {
        unsigned long flags, val;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -555,10 +556,11 @@ armv6pmu_stop(void)
 static int
 armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
-                       struct hw_perf_event *event)
+                                struct perf_event *event)
 {
+        struct hw_perf_event *hwc = &event->hw;
        /* Always place a cycle counter into the cycle counter. */
-        if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
+        if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) {
                if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
                        return -EAGAIN;
@@ -579,12 +581,13 @@ armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
        }
 }
-static void
+static void armv6pmu_disable_event(struct perf_event *event)
-armv6pmu_disable_event(struct hw_perf_event *hwc,
-                       int idx)
 {
        unsigned long val, mask, evt, flags;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
        if (ARMV6_CYCLE_COUNTER == idx) {
                mask    = ARMV6_PMCR_CCOUNT_IEN;
@@ -613,12 +616,13 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void
+static void armv6mpcore_pmu_disable_event(struct perf_event *event)
-armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
-                              int idx)
 {
        unsigned long val, mask, flags, evt = 0;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
        if (ARMV6_CYCLE_COUNTER == idx) {
                mask    = ARMV6_PMCR_CCOUNT_IEN;
@@ -649,24 +653,22 @@ static int armv6_map_event(struct perf_event *event)
                                &armv6_perf_cache_map, 0xFF);
 }
-static struct arm_pmu armv6pmu = {
+static int __devinit armv6pmu_init(struct arm_pmu *cpu_pmu)
-        .name                   = "v6",
-        .handle_irq             = armv6pmu_handle_irq,
-        .enable                 = armv6pmu_enable_event,
-        .disable                = armv6pmu_disable_event,
-        .read_counter           = armv6pmu_read_counter,
-        .write_counter          = armv6pmu_write_counter,
-        .get_event_idx          = armv6pmu_get_event_idx,
-        .start                  = armv6pmu_start,
-        .stop                   = armv6pmu_stop,
-        .map_event              = armv6_map_event,
-        .num_events             = 3,
-        .max_period             = (1LLU << 32) - 1,
-};
-static struct arm_pmu *__devinit armv6pmu_init(void)
 {
-        return &armv6pmu;
+        cpu_pmu->name           = "v6";
+        cpu_pmu->handle_irq     = armv6pmu_handle_irq;
+        cpu_pmu->enable         = armv6pmu_enable_event;
+        cpu_pmu->disable        = armv6pmu_disable_event;
+        cpu_pmu->read_counter   = armv6pmu_read_counter;
+        cpu_pmu->write_counter  = armv6pmu_write_counter;
+        cpu_pmu->get_event_idx  = armv6pmu_get_event_idx;
+        cpu_pmu->start          = armv6pmu_start;
+        cpu_pmu->stop           = armv6pmu_stop;
+        cpu_pmu->map_event      = armv6_map_event;
+        cpu_pmu->num_events     = 3;
+        cpu_pmu->max_period     = (1LLU << 32) - 1;
+        return 0;
 }
 /*
@@ -683,33 +685,31 @@ static int armv6mpcore_map_event(struct perf_event *event)
                                &armv6mpcore_perf_cache_map, 0xFF);
 }
-static struct arm_pmu armv6mpcore_pmu = {
+static int __devinit armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
-        .name                   = "v6mpcore",
-        .handle_irq             = armv6pmu_handle_irq,
-        .enable                 = armv6pmu_enable_event,
-        .disable                = armv6mpcore_pmu_disable_event,
-        .read_counter           = armv6pmu_read_counter,
-        .write_counter          = armv6pmu_write_counter,
-        .get_event_idx          = armv6pmu_get_event_idx,
-        .start                  = armv6pmu_start,
-        .stop                   = armv6pmu_stop,
-        .map_event              = armv6mpcore_map_event,
-        .num_events             = 3,
-        .max_period             = (1LLU << 32) - 1,
-};
-static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
-        return &armv6mpcore_pmu;
+        cpu_pmu->name           = "v6mpcore";
+        cpu_pmu->handle_irq     = armv6pmu_handle_irq;
+        cpu_pmu->enable         = armv6pmu_enable_event;
+        cpu_pmu->disable        = armv6mpcore_pmu_disable_event;
+        cpu_pmu->read_counter   = armv6pmu_read_counter;
+        cpu_pmu->write_counter  = armv6pmu_write_counter;
+        cpu_pmu->get_event_idx  = armv6pmu_get_event_idx;
+        cpu_pmu->start          = armv6pmu_start;
+        cpu_pmu->stop           = armv6pmu_stop;
+        cpu_pmu->map_event      = armv6mpcore_map_event;
+        cpu_pmu->num_events     = 3;
+        cpu_pmu->max_period     = (1LLU << 32) - 1;
+        return 0;
 }
 #else
-static struct arm_pmu *__devinit armv6pmu_init(void)
+static int armv6pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
-static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
+static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
 #endif  /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index bd4b090ebcfd..7d0cce85d17e 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -18,8 +18,6 @@
 #ifdef CONFIG_CPU_V7
-static struct arm_pmu armv7pmu;
 /*
 * Common ARMv7 event types
 *
@@ -738,7 +736,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 */
 #define ARMV7_IDX_CYCLE_COUNTER 0
 #define ARMV7_IDX_COUNTER0      1
-#define ARMV7_IDX_COUNTER_LAST  (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
+#define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \
+        (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 #define ARMV7_MAX_COUNTERS      32
 #define ARMV7_COUNTER_MASK      (ARMV7_MAX_COUNTERS - 1)
@@ -804,49 +803,34 @@ static inline int armv7_pmnc_has_overflowed(u32 pmnc)
        return pmnc & ARMV7_OVERFLOWED_MASK;
 }
-static inline int armv7_pmnc_counter_valid(int idx)
+static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx)
 {
-        return idx >= ARMV7_IDX_CYCLE_COUNTER && idx <= ARMV7_IDX_COUNTER_LAST;
+        return idx >= ARMV7_IDX_CYCLE_COUNTER &&
+                idx <= ARMV7_IDX_COUNTER_LAST(cpu_pmu);
 }
 static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
 {
-        int ret = 0;
+        return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx));
-        u32 counter;
-        if (!armv7_pmnc_counter_valid(idx)) {
-                pr_err("CPU%u checking wrong counter %d overflow status\n",
-                        smp_processor_id(), idx);
-        } else {
-                counter = ARMV7_IDX_TO_COUNTER(idx);
-                ret = pmnc & BIT(counter);
-        }
-        return ret;
 }
 static inline int armv7_pmnc_select_counter(int idx)
 {
-        u32 counter;
+        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
-        if (!armv7_pmnc_counter_valid(idx)) {
-                pr_err("CPU%u selecting wrong PMNC counter %d\n",
-                        smp_processor_id(), idx);
-                return -EINVAL;
-        }
-        counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
        isb();
        return idx;
 }
-static inline u32 armv7pmu_read_counter(int idx)
+static inline u32 armv7pmu_read_counter(struct perf_event *event)
 {
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
        u32 value = 0;
-        if (!armv7_pmnc_counter_valid(idx))
+        if (!armv7_pmnc_counter_valid(cpu_pmu, idx))
                pr_err("CPU%u reading wrong counter %d\n",
                        smp_processor_id(), idx);
        else if (idx == ARMV7_IDX_CYCLE_COUNTER)
@@ -857,9 +841,13 @@ static inline u32 armv7pmu_read_counter(int idx)
        return value;
 }
-static inline void armv7pmu_write_counter(int idx, u32 value)
+static inline void armv7pmu_write_counter(struct perf_event *event, u32 value)
 {
-        if (!armv7_pmnc_counter_valid(idx))
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        if (!armv7_pmnc_counter_valid(cpu_pmu, idx))
                pr_err("CPU%u writing wrong counter %d\n",
                        smp_processor_id(), idx);
        else if (idx == ARMV7_IDX_CYCLE_COUNTER)
@@ -878,60 +866,28 @@ static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
 static inline int armv7_pmnc_enable_counter(int idx)
 {
-        u32 counter;
+        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
-        if (!armv7_pmnc_counter_valid(idx)) {
-                pr_err("CPU%u enabling wrong PMNC counter %d\n",
-                        smp_processor_id(), idx);
-                return -EINVAL;
-        }
-        counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
        return idx;
 }
 static inline int armv7_pmnc_disable_counter(int idx)
 {
-        u32 counter;
+        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
-        if (!armv7_pmnc_counter_valid(idx)) {
-                pr_err("CPU%u disabling wrong PMNC counter %d\n",
-                        smp_processor_id(), idx);
-                return -EINVAL;
-        }
-        counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
        return idx;
 }
 static inline int armv7_pmnc_enable_intens(int idx)
 {
-        u32 counter;
+        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
-        if (!armv7_pmnc_counter_valid(idx)) {
-                pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
-                        smp_processor_id(), idx);
-                return -EINVAL;
-        }
-        counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
        return idx;
 }
 static inline int armv7_pmnc_disable_intens(int idx)
 {
-        u32 counter;
+        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
-        if (!armv7_pmnc_counter_valid(idx)) {
-                pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
-                        smp_processor_id(), idx);
-                return -EINVAL;
-        }
-        counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
        isb();
        /* Clear the overflow flag in case an interrupt is pending. */
@@ -956,7 +912,7 @@ static inline u32 armv7_pmnc_getreset_flags(void)
 }
 #ifdef DEBUG
-static void armv7_pmnc_dump_regs(void)
+static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu)
 {
        u32 val;
        unsigned int cnt;
@@ -981,7 +937,8 @@ static void armv7_pmnc_dump_regs(void)
        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
        printk(KERN_INFO "CCNT  =0x%08x\n", val);
-        for (cnt = ARMV7_IDX_COUNTER0; cnt <= ARMV7_IDX_COUNTER_LAST; cnt++) {
+        for (cnt = ARMV7_IDX_COUNTER0;
+                        cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) {
                armv7_pmnc_select_counter(cnt);
                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
@@ -993,10 +950,19 @@ static void armv7_pmnc_dump_regs(void)
 }
 #endif
-static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
+static void armv7pmu_enable_event(struct perf_event *event)
 {
        unsigned long flags;
+        struct hw_perf_event *hwc = &event->hw;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
+        if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
+                pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
+                        smp_processor_id(), idx);
+                return;
+        }
        /*
         * Enable counter and interrupt, and set the counter to count
@@ -1014,7 +980,7 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
         * We only need to set the event for the cycle counter if we
         * have the ability to perform event filtering.
         */
-        if (armv7pmu.set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
+        if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
                armv7_pmnc_write_evtsel(idx, hwc->config_base);
        /*
@@ -1030,10 +996,19 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
+static void armv7pmu_disable_event(struct perf_event *event)
 {
        unsigned long flags;
+        struct hw_perf_event *hwc = &event->hw;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
+        if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
+                pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
+                        smp_processor_id(), idx);
+                return;
+        }
        /*
         * Disable counter and interrupt
@@ -1057,7 +1032,8 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
 {
        u32 pmnc;
        struct perf_sample_data data;
-        struct pmu_hw_events *cpuc;
+        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
+        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
        struct pt_regs *regs;
        int idx;
@@ -1077,7 +1053,6 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
         */
        regs = get_irq_regs();
-        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
                struct hw_perf_event *hwc;
@@ -1094,13 +1069,13 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
                        continue;
                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
+                armpmu_event_update(event);
                perf_sample_data_init(&data, 0, hwc->last_period);
-                if (!armpmu_event_set_period(event, hwc, idx))
+                if (!armpmu_event_set_period(event))
                        continue;
                if (perf_event_overflow(event, &data, regs))
-                        cpu_pmu->disable(hwc, idx);
+                        cpu_pmu->disable(event);
        }
        /*
@@ -1115,7 +1090,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
        return IRQ_HANDLED;
 }
-static void armv7pmu_start(void)
+static void armv7pmu_start(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -1126,7 +1101,7 @@ static void armv7pmu_start(void)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void armv7pmu_stop(void)
+static void armv7pmu_stop(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -1138,10 +1113,12 @@ static void armv7pmu_stop(void)
 }
 static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,
-                                  struct hw_perf_event *event)
+                                  struct perf_event *event)
 {
        int idx;
-        unsigned long evtype = event->config_base & ARMV7_EVTYPE_EVENT;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
+        unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT;
        /* Always place a cycle counter into the cycle counter. */
        if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {
@@ -1192,11 +1169,14 @@ static int armv7pmu_set_event_filter(struct hw_perf_event *event,
 static void armv7pmu_reset(void *info)
 {
+        struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
        u32 idx, nb_cnt = cpu_pmu->num_events;
        /* The counter and interrupt enable registers are unknown at reset. */
-        for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
+        for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
-                armv7pmu_disable_event(NULL, idx);
+                armv7_pmnc_disable_counter(idx);
+                armv7_pmnc_disable_intens(idx);
+        }
        /* Initialize & Reset PMNC: C and P bits */
        armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
@@ -1232,17 +1212,18 @@ static int armv7_a7_map_event(struct perf_event *event)
                                &armv7_a7_perf_cache_map, 0xFF);
 }
-static struct arm_pmu armv7pmu = {
+static void armv7pmu_init(struct arm_pmu *cpu_pmu)
-        .handle_irq             = armv7pmu_handle_irq,
+{
-        .enable                 = armv7pmu_enable_event,
+        cpu_pmu->handle_irq     = armv7pmu_handle_irq;
-        .disable                = armv7pmu_disable_event,
+        cpu_pmu->enable         = armv7pmu_enable_event;
-        .read_counter           = armv7pmu_read_counter,
+        cpu_pmu->disable        = armv7pmu_disable_event;
-        .write_counter          = armv7pmu_write_counter,
+        cpu_pmu->read_counter   = armv7pmu_read_counter;
-        .get_event_idx          = armv7pmu_get_event_idx,
+        cpu_pmu->write_counter  = armv7pmu_write_counter;
-        .start                  = armv7pmu_start,
+        cpu_pmu->get_event_idx  = armv7pmu_get_event_idx;
-        .stop                   = armv7pmu_stop,
+        cpu_pmu->start          = armv7pmu_start;
-        .reset                  = armv7pmu_reset,
+        cpu_pmu->stop           = armv7pmu_stop;
-        .max_period             = (1LLU << 32) - 1,
+        cpu_pmu->reset          = armv7pmu_reset;
+        cpu_pmu->max_period     = (1LLU << 32) - 1;
 };
 static u32 __devinit armv7_read_num_pmnc_events(void)
@@ -1256,70 +1237,75 @@ static u32 __devinit armv7_read_num_pmnc_events(void)
        return nb_cnt + 1;
 }
-static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
+static int __devinit armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        armv7pmu.name           = "ARMv7 Cortex-A8";
+        armv7pmu_init(cpu_pmu);
-        armv7pmu.map_event      = armv7_a8_map_event;
+        cpu_pmu->name           = "ARMv7 Cortex-A8";
-        armv7pmu.num_events     = armv7_read_num_pmnc_events();
+        cpu_pmu->map_event      = armv7_a8_map_event;
-        return &armv7pmu;
+        cpu_pmu->num_events     = armv7_read_num_pmnc_events();
+        return 0;
 }
-static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
+static int __devinit armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        armv7pmu.name           = "ARMv7 Cortex-A9";
+        armv7pmu_init(cpu_pmu);
-        armv7pmu.map_event      = armv7_a9_map_event;
+        cpu_pmu->name           = "ARMv7 Cortex-A9";
-        armv7pmu.num_events     = armv7_read_num_pmnc_events();
+        cpu_pmu->map_event      = armv7_a9_map_event;
-        return &armv7pmu;
+        cpu_pmu->num_events     = armv7_read_num_pmnc_events();
+        return 0;
 }
-static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
+static int __devinit armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        armv7pmu.name           = "ARMv7 Cortex-A5";
+        armv7pmu_init(cpu_pmu);
-        armv7pmu.map_event      = armv7_a5_map_event;
+        cpu_pmu->name           = "ARMv7 Cortex-A5";
-        armv7pmu.num_events     = armv7_read_num_pmnc_events();
+        cpu_pmu->map_event      = armv7_a5_map_event;
-        return &armv7pmu;
+        cpu_pmu->num_events     = armv7_read_num_pmnc_events();
+        return 0;
 }
-static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
+static int __devinit armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        armv7pmu.name           = "ARMv7 Cortex-A15";
+        armv7pmu_init(cpu_pmu);
-        armv7pmu.map_event      = armv7_a15_map_event;
+        cpu_pmu->name           = "ARMv7 Cortex-A15";
-        armv7pmu.num_events     = armv7_read_num_pmnc_events();
+        cpu_pmu->map_event      = armv7_a15_map_event;
-        armv7pmu.set_event_filter = armv7pmu_set_event_filter;
+        cpu_pmu->num_events     = armv7_read_num_pmnc_events();
-        return &armv7pmu;
+        cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
+        return 0;
 }
-static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
+static int __devinit armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        armv7pmu.name           = "ARMv7 Cortex-A7";
+        armv7pmu_init(cpu_pmu);
-        armv7pmu.map_event      = armv7_a7_map_event;
+        cpu_pmu->name           = "ARMv7 Cortex-A7";
-        armv7pmu.num_events     = armv7_read_num_pmnc_events();
+        cpu_pmu->map_event      = armv7_a7_map_event;
-        armv7pmu.set_event_filter = armv7pmu_set_event_filter;
+        cpu_pmu->num_events     = armv7_read_num_pmnc_events();
-        return &armv7pmu;
+        cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
+        return 0;
 }
 #else
-static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
+static inline int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
-static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
+static inline int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
-static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
+static inline int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
-static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
+static inline int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
-static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
+static inline int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
 #endif  /* CONFIG_CPU_V7 */
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 426e19f380a2..0c8265e53d5f 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -224,7 +224,8 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
 {
        unsigned long pmnc;
        struct perf_sample_data data;
-        struct pmu_hw_events *cpuc;
+        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
+        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
        struct pt_regs *regs;
        int idx;
@@ -248,7 +249,6 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
        regs = get_irq_regs();
-        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
                struct hw_perf_event *hwc;
@@ -260,13 +260,13 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
                        continue;
                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
+                armpmu_event_update(event);
                perf_sample_data_init(&data, 0, hwc->last_period);
-                if (!armpmu_event_set_period(event, hwc, idx))
+                if (!armpmu_event_set_period(event))
                        continue;
                if (perf_event_overflow(event, &data, regs))
-                        cpu_pmu->disable(hwc, idx);
+                        cpu_pmu->disable(event);
        }
        irq_work_run();
@@ -280,11 +280,13 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
        return IRQ_HANDLED;
 }
-static void
+static void xscale1pmu_enable_event(struct perf_event *event)
-xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
        unsigned long val, mask, evt, flags;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
        switch (idx) {
        case XSCALE_CYCLE_COUNTER:
@@ -314,11 +316,13 @@ xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void
+static void xscale1pmu_disable_event(struct perf_event *event)
-xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
 {
        unsigned long val, mask, evt, flags;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
        switch (idx) {
        case XSCALE_CYCLE_COUNTER:
@@ -348,9 +352,10 @@ xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
 static int
 xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
-                        struct hw_perf_event *event)
+                                struct perf_event *event)
 {
-        if (XSCALE_PERFCTR_CCNT == event->config_base) {
+        struct hw_perf_event *hwc = &event->hw;
+        if (XSCALE_PERFCTR_CCNT == hwc->config_base) {
                if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
                        return -EAGAIN;
@@ -366,8 +371,7 @@ xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
        }
 }
-static void
+static void xscale1pmu_start(struct arm_pmu *cpu_pmu)
-xscale1pmu_start(void)
 {
        unsigned long flags, val;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -379,8 +383,7 @@ xscale1pmu_start(void)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void
+static void xscale1pmu_stop(struct arm_pmu *cpu_pmu)
-xscale1pmu_stop(void)
 {
        unsigned long flags, val;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -392,9 +395,10 @@ xscale1pmu_stop(void)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static inline u32
+static inline u32 xscale1pmu_read_counter(struct perf_event *event)
-xscale1pmu_read_counter(int counter)
 {
+        struct hw_perf_event *hwc = &event->hw;
+        int counter = hwc->idx;
        u32 val = 0;
        switch (counter) {
@@ -412,9 +416,11 @@ xscale1pmu_read_counter(int counter)
        return val;
 }
-static inline void
+static inline void xscale1pmu_write_counter(struct perf_event *event, u32 val)
-xscale1pmu_write_counter(int counter, u32 val)
 {
+        struct hw_perf_event *hwc = &event->hw;
+        int counter = hwc->idx;
        switch (counter) {
        case XSCALE_CYCLE_COUNTER:
                asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
@@ -434,24 +440,22 @@ static int xscale_map_event(struct perf_event *event)
                                &xscale_perf_cache_map, 0xFF);
 }
-static struct arm_pmu xscale1pmu = {
+static int __devinit xscale1pmu_init(struct arm_pmu *cpu_pmu)
-        .name           = "xscale1",
-        .handle_irq     = xscale1pmu_handle_irq,
-        .enable         = xscale1pmu_enable_event,
-        .disable        = xscale1pmu_disable_event,
-        .read_counter   = xscale1pmu_read_counter,
-        .write_counter  = xscale1pmu_write_counter,
-        .get_event_idx  = xscale1pmu_get_event_idx,
-        .start          = xscale1pmu_start,
-        .stop           = xscale1pmu_stop,
-        .map_event      = xscale_map_event,
-        .num_events     = 3,
-        .max_period     = (1LLU << 32) - 1,
-};
-static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
-        return &xscale1pmu;
+        cpu_pmu->name           = "xscale1";
+        cpu_pmu->handle_irq     = xscale1pmu_handle_irq;
+        cpu_pmu->enable         = xscale1pmu_enable_event;
+        cpu_pmu->disable        = xscale1pmu_disable_event;
+        cpu_pmu->read_counter   = xscale1pmu_read_counter;
+        cpu_pmu->write_counter  = xscale1pmu_write_counter;
+        cpu_pmu->get_event_idx  = xscale1pmu_get_event_idx;
+        cpu_pmu->start          = xscale1pmu_start;
+        cpu_pmu->stop           = xscale1pmu_stop;
+        cpu_pmu->map_event      = xscale_map_event;
+        cpu_pmu->num_events     = 3;
+        cpu_pmu->max_period     = (1LLU << 32) - 1;
+        return 0;
 }
 #define XSCALE2_OVERFLOWED_MASK 0x01f
@@ -567,7 +571,8 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
 {
        unsigned long pmnc, of_flags;
        struct perf_sample_data data;
-        struct pmu_hw_events *cpuc;
+        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
+        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
        struct pt_regs *regs;
        int idx;
@@ -585,7 +590,6 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
        regs = get_irq_regs();
-        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
                struct hw_perf_event *hwc;
@@ -597,13 +601,13 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
                        continue;
                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
+                armpmu_event_update(event);
                perf_sample_data_init(&data, 0, hwc->last_period);
-                if (!armpmu_event_set_period(event, hwc, idx))
+                if (!armpmu_event_set_period(event))
                        continue;
                if (perf_event_overflow(event, &data, regs))
-                        cpu_pmu->disable(hwc, idx);
+                        cpu_pmu->disable(event);
        }
        irq_work_run();
@@ -617,11 +621,13 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
        return IRQ_HANDLED;
 }
-static void
+static void xscale2pmu_enable_event(struct perf_event *event)
-xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
        unsigned long flags, ien, evtsel;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
        ien = xscale2pmu_read_int_enable();
        evtsel = xscale2pmu_read_event_select();
@@ -661,11 +667,13 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void
+static void xscale2pmu_disable_event(struct perf_event *event)
-xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
 {
        unsigned long flags, ien, evtsel, of_flags;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        struct hw_perf_event *hwc = &event->hw;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        int idx = hwc->idx;
        ien = xscale2pmu_read_int_enable();
        evtsel = xscale2pmu_read_event_select();
@@ -713,7 +721,7 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
 static int
 xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc,
-                        struct hw_perf_event *event)
+                                struct perf_event *event)
 {
        int idx = xscale1pmu_get_event_idx(cpuc, event);
        if (idx >= 0)
@@ -727,8 +735,7 @@ out:
        return idx;
 }
-static void
+static void xscale2pmu_start(struct arm_pmu *cpu_pmu)
-xscale2pmu_start(void)
 {
        unsigned long flags, val;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -740,8 +747,7 @@ xscale2pmu_start(void)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static void
+static void xscale2pmu_stop(struct arm_pmu *cpu_pmu)
-xscale2pmu_stop(void)
 {
        unsigned long flags, val;
        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
@@ -753,9 +759,10 @@ xscale2pmu_stop(void)
        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
-static inline u32
+static inline u32 xscale2pmu_read_counter(struct perf_event *event)
-xscale2pmu_read_counter(int counter)
 {
+        struct hw_perf_event *hwc = &event->hw;
+        int counter = hwc->idx;
        u32 val = 0;
        switch (counter) {
@@ -779,9 +786,11 @@ xscale2pmu_read_counter(int counter)
        return val;
 }
-static inline void
+static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val)
-xscale2pmu_write_counter(int counter, u32 val)
 {
+        struct hw_perf_event *hwc = &event->hw;
+        int counter = hwc->idx;
        switch (counter) {
        case XSCALE_CYCLE_COUNTER:
                asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
@@ -801,33 +810,31 @@ xscale2pmu_write_counter(int counter, u32 val)
        }
 }
-static struct arm_pmu xscale2pmu = {
+static int __devinit xscale2pmu_init(struct arm_pmu *cpu_pmu)
-        .name           = "xscale2",
-        .handle_irq     = xscale2pmu_handle_irq,
-        .enable         = xscale2pmu_enable_event,
-        .disable        = xscale2pmu_disable_event,
-        .read_counter   = xscale2pmu_read_counter,
-        .write_counter  = xscale2pmu_write_counter,
-        .get_event_idx  = xscale2pmu_get_event_idx,
-        .start          = xscale2pmu_start,
-        .stop           = xscale2pmu_stop,
-        .map_event      = xscale_map_event,
-        .num_events     = 5,
-        .max_period     = (1LLU << 32) - 1,
-};
-static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
-        return &xscale2pmu;
+        cpu_pmu->name           = "xscale2";
+        cpu_pmu->handle_irq     = xscale2pmu_handle_irq;
+        cpu_pmu->enable         = xscale2pmu_enable_event;
+        cpu_pmu->disable        = xscale2pmu_disable_event;
+        cpu_pmu->read_counter   = xscale2pmu_read_counter;
+        cpu_pmu->write_counter  = xscale2pmu_write_counter;
+        cpu_pmu->get_event_idx  = xscale2pmu_get_event_idx;
+        cpu_pmu->start          = xscale2pmu_start;
+        cpu_pmu->stop           = xscale2pmu_stop;
+        cpu_pmu->map_event      = xscale_map_event;
+        cpu_pmu->num_events     = 5;
+        cpu_pmu->max_period     = (1LLU << 32) - 1;
+        return 0;
 }
 #else
-static struct arm_pmu *__devinit xscale1pmu_init(void)
+static inline int xscale1pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
-static struct arm_pmu *__devinit xscale2pmu_init(void)
+static inline int xscale2pmu_init(struct arm_pmu *cpu_pmu)
 {
-        return NULL;
+        return -ENODEV;
 }
 #endif  /* CONFIG_CPU_XSCALE */
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 90084a6de35a..c6dec5fc20aa 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -34,6 +34,7 @@
 #include <linux/leds.h>
 #include <asm/cacheflush.h>
+#include <asm/idmap.h>
 #include <asm/processor.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
@@ -56,8 +57,6 @@ static const char *isa_modes[] = {
  "ARM" , "Thumb" , "Jazelle", "ThumbEE"
 };
-extern void setup_mm_for_reboot(void);
 static volatile int hlt_counter;
 void disable_hlt(void)
@@ -70,6 +69,7 @@ EXPORT_SYMBOL(disable_hlt);
 void enable_hlt(void)
 {
        hlt_counter--;
+        BUG_ON(hlt_counter < 0);
 }
 EXPORT_SYMBOL(enable_hlt);
@@ -376,17 +376,18 @@ asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
 int
 copy_thread(unsigned long clone_flags, unsigned long stack_start,
-            unsigned long stk_sz, struct task_struct *p, struct pt_regs *regs)
+            unsigned long stk_sz, struct task_struct *p)
 {
        struct thread_info *thread = task_thread_info(p);
        struct pt_regs *childregs = task_pt_regs(p);
        memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save));
-        if (likely(regs)) {
+        if (likely(!(p->flags & PF_KTHREAD))) {
-                *childregs = *regs;
+                *childregs = *current_pt_regs();
                childregs->ARM_r0 = 0;
-                childregs->ARM_sp = stack_start;
+                if (stack_start)
+                        childregs->ARM_sp = stack_start;
        } else {
                memset(childregs, 0, sizeof(struct pt_regs));
                thread->cpu_context.r4 = stk_sz;
@@ -399,7 +400,7 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
        clear_ptrace_hw_breakpoint(p);
        if (clone_flags & CLONE_SETTLS)
-                thread->tp_value = regs->ARM_r3;
+                thread->tp_value = childregs->ARM_r3;
        thread_notify(THREAD_NOTIFY_COPY, thread);
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 739db3a1b2d2..03deeffd9f6d 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -916,16 +916,11 @@ enum ptrace_syscall_dir {
        PTRACE_SYSCALL_EXIT,
 };
-static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
+static int tracehook_report_syscall(struct pt_regs *regs,
-                                enum ptrace_syscall_dir dir)
+                                    enum ptrace_syscall_dir dir)
 {
        unsigned long ip;
-        current_thread_info()->syscall = scno;
-        if (!test_thread_flag(TIF_SYSCALL_TRACE))
-                return scno;
        /*
         * IP is used to denote syscall entry/exit:
         * IP = 0 -> entry, =1 -> exit
@@ -944,19 +939,41 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
-        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        current_thread_info()->syscall = scno;
+        /* Do the secure computing check first; failures should be fast. */
+        if (secure_computing(scno) == -1)
+                return -1;
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                scno = tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
                trace_sys_enter(regs, scno);
        audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
                            regs->ARM_r2, regs->ARM_r3);
        return scno;
 }
-asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
+asmlinkage void syscall_trace_exit(struct pt_regs *regs)
 {
-        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        /*
-        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+         * Audit the syscall before anything else, as a debugger may
-                trace_sys_exit(regs, scno);
+         * come in and change the current registers.
+         */
        audit_syscall_exit(regs);
-        return scno;
+        /*
+         * Note that we haven't updated the ->syscall field for the
+         * current thread. This isn't a problem because it will have
+         * been set on syscall entry and there hasn't been an opportunity
+         * for a PTRACE_SET_SYSCALL since then.
+         */
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_exit(regs, regs_return_value(regs));
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall(regs, PTRACE_SYSCALL_EXIT);
 }
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index da1d1aa20ad9..9a89bf4aefe1 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -383,6 +383,12 @@ void cpu_init(void)
                BUG();
        }
+        /*
+         * This only works on resume and secondary cores. For booting on the
+         * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
+         */
+        set_my_cpu_offset(per_cpu_offset(cpu));
        cpu_proc_init();
        /*
@@ -426,13 +432,14 @@ int __cpu_logical_map[NR_CPUS];
 void __init smp_setup_processor_id(void)
 {
        int i;
-        u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
+        u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
+        u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
        cpu_logical_map(0) = cpu;
-        for (i = 1; i < NR_CPUS; ++i)
+        for (i = 1; i < nr_cpu_ids; ++i)
                cpu_logical_map(i) = i == cpu ? 0 : i;
-        printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
+        printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
 }
 static void __init setup_processor(void)
@@ -758,6 +765,7 @@ void __init setup_arch(char **cmdline_p)
        unflatten_device_tree();
+        arm_dt_init_cpu_maps();
 #ifdef CONFIG_SMP
        if (is_smp()) {
                smp_set_ops(mdesc->smp);
@@ -841,12 +849,9 @@ static const char *hwcap_str[] = {
 static int c_show(struct seq_file *m, void *v)
 {
-        int i;
+        int i, j;
+        u32 cpuid;
-        seq_printf(m, "Processor\t: %s rev %d (%s)\n",
-                   cpu_name, read_cpuid_id() & 15, elf_platform);
-#if defined(CONFIG_SMP)
        for_each_online_cpu(i) {
                /*
                 * glibc reads /proc/cpuinfo to determine the number of
@@ -854,45 +859,48 @@ static int c_show(struct seq_file *m, void *v)
                 * "processor".  Give glibc what it expects.
                 */
                seq_printf(m, "processor\t: %d\n", i);
-                seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
+                cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
+                seq_printf(m, "model name\t: %s rev %d (%s)\n",
+                           cpu_name, cpuid & 15, elf_platform);
+#if defined(CONFIG_SMP)
+                seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
                           per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
                           (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
-        }
+#else
-#else /* CONFIG_SMP */
+                seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
-        seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
+                           loops_per_jiffy / (500000/HZ),
-                   loops_per_jiffy / (500000/HZ),
+                           (loops_per_jiffy / (5000/HZ)) % 100);
-                   (loops_per_jiffy / (5000/HZ)) % 100);
 #endif
+                /* dump out the processor features */
+                seq_puts(m, "Features\t: ");
-        /* dump out the processor features */
+                for (j = 0; hwcap_str[j]; j++)
-        seq_puts(m, "Features\t: ");
+                        if (elf_hwcap & (1 << j))
+                                seq_printf(m, "%s ", hwcap_str[j]);
-        for (i = 0; hwcap_str[i]; i++)
-                if (elf_hwcap & (1 << i))
-                        seq_printf(m, "%s ", hwcap_str[i]);
-        seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
+                seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
-        seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
+                seq_printf(m, "CPU architecture: %s\n",
+                           proc_arch[cpu_architecture()]);
-        if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
+                if ((cpuid & 0x0008f000) == 0x00000000) {
-                /* pre-ARM7 */
+                        /* pre-ARM7 */
-                seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
+                        seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
-        } else {
-                if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
-                        /* ARM7 */
-                        seq_printf(m, "CPU variant\t: 0x%02x\n",
-                                   (read_cpuid_id() >> 16) & 127);
                } else {
-                        /* post-ARM7 */
+                        if ((cpuid & 0x0008f000) == 0x00007000) {
-                        seq_printf(m, "CPU variant\t: 0x%x\n",
+                                /* ARM7 */
-                                   (read_cpuid_id() >> 20) & 15);
+                                seq_printf(m, "CPU variant\t: 0x%02x\n",
+                                           (cpuid >> 16) & 127);
+                        } else {
+                                /* post-ARM7 */
+                                seq_printf(m, "CPU variant\t: 0x%x\n",
+                                           (cpuid >> 20) & 15);
+                        }
+                        seq_printf(m, "CPU part\t: 0x%03x\n",
+                                   (cpuid >> 4) & 0xfff);
                }
-                seq_printf(m, "CPU part\t: 0x%03x\n",
+                seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
-                           (read_cpuid_id() >> 4) & 0xfff);
        }
-        seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
-        seq_puts(m, "\n");
        seq_printf(m, "Hardware\t: %s\n", machine_name);
        seq_printf(m, "Revision\t: %04x\n", system_rev);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index fbc8b2623d82..84f4cbf652e5 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -281,6 +281,7 @@ static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
        struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
        cpu_info->loops_per_jiffy = loops_per_jiffy;
+        cpu_info->cpuid = read_cpuid_id();
        store_cpu_topology(cpuid);
 }
@@ -313,9 +314,10 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
        current->active_mm = mm;
        cpumask_set_cpu(cpu, mm_cpumask(mm));
+        cpu_init();
        printk("CPU%u: Booted secondary processor\n", cpu);
-        cpu_init();
        preempt_disable();
        trace_hardirqs_off();
@@ -371,6 +373,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
 void __init smp_prepare_boot_cpu(void)
 {
+        set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
 }
 void __init smp_prepare_cpus(unsigned int max_cpus)
@@ -421,6 +424,11 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
        smp_cross_call(mask, IPI_CALL_FUNC);
 }
+void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
+{
+        smp_cross_call(mask, IPI_WAKEUP);
+}
 void arch_send_call_function_single_ipi(int cpu)
 {
        smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
@@ -443,7 +451,7 @@ void show_ipi_list(struct seq_file *p, int prec)
        for (i = 0; i < NR_IPI; i++) {
                seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
-                for_each_present_cpu(cpu)
+                for_each_online_cpu(cpu)
                        seq_printf(p, "%10u ",
                                   __get_irq_stat(cpu, ipi_irqs[i]));
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index b22d700fea27..49f335d301ba 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -31,6 +31,8 @@ static void __iomem *twd_base;
 static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
+static bool common_setup_called;
+static DEFINE_PER_CPU(bool, percpu_setup_called);
 static struct clock_event_device __percpu **twd_evt;
 static int twd_ppi;
@@ -248,17 +250,9 @@ static struct clk *twd_get_clock(void)
                return clk;
        }
-        err = clk_prepare(clk);
+        err = clk_prepare_enable(clk);
        if (err) {
-                pr_err("smp_twd: clock failed to prepare: %d\n", err);
+                pr_err("smp_twd: clock failed to prepare+enable: %d\n", err);
-                clk_put(clk);
-                return ERR_PTR(err);
-        }
-        err = clk_enable(clk);
-        if (err) {
-                pr_err("smp_twd: clock failed to enable: %d\n", err);
-                clk_unprepare(clk);
                clk_put(clk);
                return ERR_PTR(err);
        }
@@ -272,15 +266,45 @@ static struct clk *twd_get_clock(void)
 static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
 {
        struct clock_event_device **this_cpu_clk;
+        int cpu = smp_processor_id();
+        /*
+         * If the basic setup for this CPU has been done before don't
+         * bother with the below.
+         */
+        if (per_cpu(percpu_setup_called, cpu)) {
+                __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+                clockevents_register_device(*__this_cpu_ptr(twd_evt));
+                enable_percpu_irq(clk->irq, 0);
+                return 0;
+        }
+        per_cpu(percpu_setup_called, cpu) = true;
-        if (!twd_clk)
+        /*
+         * This stuff only need to be done once for the entire TWD cluster
+         * during the runtime of the system.
+         */
+        if (!common_setup_called) {
                twd_clk = twd_get_clock();
-        if (!IS_ERR_OR_NULL(twd_clk))
+                /*
-                twd_timer_rate = clk_get_rate(twd_clk);
+                 * We use IS_ERR_OR_NULL() here, because if the clock stubs
-        else
+                 * are active we will get a valid clk reference which is
-                twd_calibrate_rate();
+                 * however NULL and will return the rate 0. In that case we
+                 * need to calibrate the rate instead.
+                 */
+                if (!IS_ERR_OR_NULL(twd_clk))
+                        twd_timer_rate = clk_get_rate(twd_clk);
+                else
+                        twd_calibrate_rate();
+                common_setup_called = true;
+        }
+        /*
+         * The following is done once per CPU the first time .setup() is
+         * called.
+         */
        __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
        clk->name = "local_timer";
@@ -366,10 +390,8 @@ void __init twd_local_timer_of_register(void)
        int err;
        np = of_find_matching_node(NULL, twd_of_match);
-        if (!np) {
+        if (!np)
-                err = -ENODEV;
+                return;
-                goto out;
-        }
        twd_ppi = irq_of_parse_and_map(np, 0);
        if (!twd_ppi) {
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index c2a898aa57aa..3151f5623d0e 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -28,37 +28,6 @@
 #include <linux/uaccess.h>
 #include <linux/slab.h>
-/* Fork a new task - this creates a new program thread.
- * This is called indirectly via a small wrapper
- */
-asmlinkage int sys_fork(struct pt_regs *regs)
-{
-#ifdef CONFIG_MMU
-        return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
-#else
-        /* can not support in nommu mode */
-        return(-EINVAL);
-#endif
-}
-/* Clone a task - this clones the calling program thread.
- * This is called indirectly via a small wrapper
- */
-asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
-                         int __user *parent_tidptr, int tls_val,
-                         int __user *child_tidptr, struct pt_regs *regs)
-{
-        if (!newsp)
-                newsp = regs->ARM_sp;
-        return do_fork(clone_flags, newsp, regs, 0, parent_tidptr, child_tidptr);
-}
-asmlinkage int sys_vfork(struct pt_regs *regs)
-{
-        return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
-}
 /*
 * Since loff_t is a 64 bit type we avoid a lot of ABI hassle
 * with a different argument ordering.
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 26c12c6440fc..79282ebcd939 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -196,32 +196,7 @@ static inline void parse_dt_topology(void) {}
 static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
 #endif
+ /*
-/*
- * cpu topology management
- */
-#define MPIDR_SMP_BITMASK (0x3 << 30)
-#define MPIDR_SMP_VALUE (0x2 << 30)
-#define MPIDR_MT_BITMASK (0x1 << 24)
-/*
- * These masks reflect the current use of the affinity levels.
- * The affinity level can be up to 16 bits according to ARM ARM
- */
-#define MPIDR_HWID_BITMASK 0xFFFFFF
-#define MPIDR_LEVEL0_MASK 0x3
-#define MPIDR_LEVEL0_SHIFT 0
-#define MPIDR_LEVEL1_MASK 0xF
-#define MPIDR_LEVEL1_SHIFT 8
-#define MPIDR_LEVEL2_MASK 0xFF
-#define MPIDR_LEVEL2_SHIFT 16
-/*
 * cpu topology table
 */
 struct cputopo_arm cpu_topology[NR_CPUS];
@@ -282,19 +257,14 @@ void store_cpu_topology(unsigned int cpuid)
                if (mpidr & MPIDR_MT_BITMASK) {
                        /* core performance interdependency */
-                        cpuid_topo->thread_id = (mpidr >> MPIDR_LEVEL0_SHIFT)
+                        cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-                                & MPIDR_LEVEL0_MASK;
+                        cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-                        cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL1_SHIFT)
+                        cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
-                                & MPIDR_LEVEL1_MASK;
-                        cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL2_SHIFT)
-                                & MPIDR_LEVEL2_MASK;
                } else {
                        /* largely independent cores */
                        cpuid_topo->thread_id = -1;
-                        cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL0_SHIFT)
+                        cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-                                & MPIDR_LEVEL0_MASK;
+                        cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-                        cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL1_SHIFT)
-                                & MPIDR_LEVEL1_MASK;
                }
        } else {
                /*
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 36ff15bbfdd4..b9f38e388b43 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -114,6 +114,15 @@ SECTIONS
        RO_DATA(PAGE_SIZE)
+        . = ALIGN(4);
+        __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
+                __start___ex_table = .;
+#ifdef CONFIG_MMU
+                *(__ex_table)
+#endif
+                __stop___ex_table = .;
+        }
 #ifdef CONFIG_ARM_UNWIND
        /*
         * Stack unwinding tables
@@ -220,16 +229,6 @@ SECTIONS
                READ_MOSTLY_DATA(L1_CACHE_BYTES)
                /*
-                 * The exception fixup table (might need resorting at runtime)
-                 */
-                . = ALIGN(4);
-                __start___ex_table = .;
-#ifdef CONFIG_MMU
-                *(__ex_table)
-#endif
-                __stop___ex_table = .;
-                /*
                 * and the usual data section
                 */
                DATA_DATA
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 043624219b55..958358c91afd 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -39,7 +39,6 @@ config SOC_AT91RM9200
 config SOC_AT91SAM9260
        bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
        select HAVE_AT91_DBGU0
-        select HAVE_NET_MACB
        select SOC_AT91SAM9
        help
          Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
@@ -57,7 +56,6 @@ config SOC_AT91SAM9263
        bool "AT91SAM9263"
        select HAVE_AT91_DBGU1
        select HAVE_FB_ATMEL
-        select HAVE_NET_MACB
        select SOC_AT91SAM9
 config SOC_AT91SAM9RL
@@ -70,7 +68,6 @@ config SOC_AT91SAM9G45
        bool "AT91SAM9G45 or AT91SAM9M10 families"
        select HAVE_AT91_DBGU1
        select HAVE_FB_ATMEL
-        select HAVE_NET_MACB
        select SOC_AT91SAM9
        help
          Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
@@ -80,7 +77,6 @@ config SOC_AT91SAM9X5
        bool "AT91SAM9x5 family"
        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
-        select HAVE_NET_MACB
        select SOC_AT91SAM9
        help
          Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
@@ -494,8 +490,17 @@ endif
 comment "Generic Board Type"
+config MACH_AT91RM9200_DT
+        bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
+        depends on SOC_AT91RM9200
+        select USE_OF
+        help
+          Select this if you want to experiment device-tree with
+          an Atmel RM9200 Evaluation Kit.
 config MACH_AT91SAM_DT
        bool "Atmel AT91SAM Evaluation Kits with device-tree support"
+        depends on SOC_AT91SAM9
        select USE_OF
        help
          Select this if you want to experiment device-tree with
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 3bb7a51efc9d..b38a1dcb79b8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -88,6 +88,7 @@ obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
 obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 # AT91SAM board with device-tree
+obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o
 obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
 # AT91X40 board-specific support
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/at91_aic.h
index eaea66197fa1..eaea66197fa1 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/at91_aic.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/at91_rstc.h
index 875fa336800b..875fa336800b 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/at91_rstc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/at91_shdwc.h
index 60478ea8bd46..60478ea8bd46 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/at91_shdwc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/at91_tc.h
index 46a317fd7164..46a317fd7164 100644
--- a/arch/arm/mach-at91/include/mach/at91_tc.h
+++ b/arch/arm/mach-at91/at91_tc.h
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 5269825194a8..7aeb473ee539 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -17,11 +17,11 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91rm9200.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
+#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -184,9 +184,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
@@ -194,6 +197,24 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
        CLKDEV_CON_ID("pioD", &pioD_clk),
+        /* usart lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
+        /* tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
+        CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -361,10 +382,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0       /* Advanced Interrupt Controller (IRQ6) */
 };
-struct at91_init_soc __initdata at91rm9200_soc = {
+AT91_SOC_START(rm9200)
        .map_io = at91rm9200_map_io,
        .default_irq_priority = at91rm9200_default_irq_priority,
        .ioremap_registers = at91rm9200_ioremap_registers,
        .register_clocks = at91rm9200_register_clocks,
        .init = at91rm9200_initialize,
-};
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 3cee0e6ea7c3..3ebc9792560c 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -18,11 +18,11 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
-#include <mach/board.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include "board.h"
 #include "generic.h"
@@ -752,7 +752,7 @@ static struct resource ssc0_resources[] = {
 };
 static struct platform_device at91rm9200_ssc0_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 0,
        .dev    = {
                .dma_mask               = &ssc0_dmamask,
@@ -794,7 +794,7 @@ static struct resource ssc1_resources[] = {
 };
 static struct platform_device at91rm9200_ssc1_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 1,
        .dev    = {
                .dma_mask               = &ssc1_dmamask,
@@ -836,7 +836,7 @@ static struct resource ssc2_resources[] = {
 };
 static struct platform_device at91rm9200_ssc2_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 2,
        .dev    = {
                .dma_mask               = &ssc2_dmamask,
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index aaa443b48c91..cafe98836c8a 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -24,6 +24,9 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/export.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/mach/time.h>
@@ -91,7 +94,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 static struct irqaction at91rm9200_timer_irq = {
        .name           = "at91_tick",
        .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91rm9200_timer_interrupt
+        .handler        = at91rm9200_timer_interrupt,
+        .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
 };
 static cycle_t read_clk32k(struct clocksource *cs)
@@ -179,8 +183,60 @@ static struct clock_event_device clkevt = {
 void __iomem *at91_st_base;
 EXPORT_SYMBOL_GPL(at91_st_base);
+#ifdef CONFIG_OF
+static struct of_device_id at91rm9200_st_timer_ids[] = {
+        { .compatible = "atmel,at91rm9200-st" },
+        { /* sentinel */ }
+};
+static int __init of_at91rm9200_st_init(void)
+{
+        struct device_node *np;
+        int ret;
+        np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
+        if (!np)
+                goto err;
+        at91_st_base = of_iomap(np, 0);
+        if (!at91_st_base)
+                goto node_err;
+        /* Get the interrupts property */
+        ret = irq_of_parse_and_map(np, 0);
+        if (!ret)
+                goto ioremap_err;
+        at91rm9200_timer_irq.irq = ret;
+        of_node_put(np);
+        return 0;
+ioremap_err:
+        iounmap(at91_st_base);
+node_err:
+        of_node_put(np);
+err:
+        return -EINVAL;
+}
+#else
+static int __init of_at91rm9200_st_init(void)
+{
+        return -EINVAL;
+}
+#endif
 void __init at91rm9200_ioremap_st(u32 addr)
 {
+#ifdef CONFIG_OF
+        struct device_node *np;
+        np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
        at91_st_base = ioremap(addr, 256);
        if (!at91_st_base)
                panic("Impossible to ioremap ST\n");
@@ -191,13 +247,16 @@ void __init at91rm9200_ioremap_st(u32 addr)
 */
 void __init at91rm9200_timer_init(void)
 {
+        /* For device tree enabled device: initialize here */
+        of_at91rm9200_st_init();
        /* Disable all timer interrupts, and clear any pending ones */
        at91_st_write(AT91_ST_IDR,
                AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
        at91_st_read(AT91_ST_SR);
        /* Make IRQs happen for the system timer */
-        setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
+        setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
        /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
         * directly for the clocksource and all clockevents, after adjusting
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index f8202615f4a8..b67cd5374117 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -20,10 +20,10 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include "at91_aic.h"
+#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -210,7 +210,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
        /* more usart lookup table for DT entries */
@@ -230,11 +231,15 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -390,10 +395,10 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller */
 };
-struct at91_init_soc __initdata at91sam9260_soc = {
+AT91_SOC_START(sam9260)
        .map_io = at91sam9260_map_io,
        .default_irq_priority = at91sam9260_default_irq_priority,
        .ioremap_registers = at91sam9260_ioremap_registers,
        .register_clocks = at91sam9260_register_clocks,
        .init = at91sam9260_initialize,
-};
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 414bd855fb0c..eda8d1679d40 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -19,7 +19,6 @@
 #include <linux/platform_data/at91_adc.h>
-#include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9260_matrix.h>
@@ -27,6 +26,7 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_adc.h>
+#include "board.h"
 #include "generic.h"
@@ -742,7 +742,7 @@ static struct resource ssc_resources[] = {
 };
 static struct platform_device at91sam9260_ssc_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 0,
        .dev    = {
                .dma_mask               = &ssc_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 04295c04b3e0..2998a08afc2d 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -19,10 +19,10 @@
 #include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include "at91_aic.h"
+#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -174,9 +174,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
@@ -334,10 +337,10 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller */
 };
-struct at91_init_soc __initdata at91sam9261_soc = {
+AT91_SOC_START(sam9261)
        .map_io = at91sam9261_map_io,
        .default_irq_priority = at91sam9261_default_irq_priority,
        .ioremap_registers = at91sam9261_ioremap_registers,
        .register_clocks = at91sam9261_register_clocks,
        .init = at91sam9261_initialize,
-};
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index cd604aad8e96..92e0f861084a 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -21,12 +21,12 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
-#include <mach/board.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91sam9261_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include "board.h"
 #include "generic.h"
@@ -706,7 +706,7 @@ static struct resource ssc0_resources[] = {
 };
 static struct platform_device at91sam9261_ssc0_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 0,
        .dev    = {
                .dma_mask               = &ssc0_dmamask,
@@ -748,7 +748,7 @@ static struct resource ssc1_resources[] = {
 };
 static struct platform_device at91sam9261_ssc1_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 1,
        .dev    = {
                .dma_mask               = &ssc1_dmamask,
@@ -790,7 +790,7 @@ static struct resource ssc2_resources[] = {
 };
 static struct platform_device at91sam9261_ssc2_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 2,
        .dev    = {
                .dma_mask               = &ssc2_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index d6f9c23927c4..b9fc60d1b33a 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -18,10 +18,10 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include "at91_aic.h"
+#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -186,8 +186,10 @@ static struct clk *periph_clocks[] __initdata = {
 static struct clk_lookup periph_clocks_lookups[] = {
        /* One additional fake clock for macb_hclk */
        CLKDEV_CON_ID("hclk", &macb_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
@@ -211,7 +213,14 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -365,10 +374,10 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller (IRQ1) */
 };
-struct at91_init_soc __initdata at91sam9263_soc = {
+AT91_SOC_START(sam9263)
        .map_io = at91sam9263_map_io,
        .default_irq_priority = at91sam9263_default_irq_priority,
        .ioremap_registers = at91sam9263_ioremap_registers,
        .register_clocks = at91sam9263_register_clocks,
        .init = at91sam9263_initialize,
-};
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 9c61e59a2104..ed666f5cb01d 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -20,12 +20,12 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
-#include <mach/board.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91sam9263_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include "board.h"
 #include "generic.h"
@@ -1199,7 +1199,7 @@ static struct resource ssc0_resources[] = {
 };
 static struct platform_device at91sam9263_ssc0_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 0,
        .dev    = {
                .dma_mask               = &ssc0_dmamask,
@@ -1241,7 +1241,7 @@ static struct resource ssc1_resources[] = {
 };
 static struct platform_device at91sam9263_ssc1_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 1,
        .dev    = {
                .dma_mask               = &ssc1_dmamask,
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index ffc0957d7623..358412f1f5f8 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -20,8 +20,18 @@
 #include <asm/mach/time.h>
-#include <mach/at91_pit.h>
+#define AT91_PIT_MR             0x00                    /* Mode Register */
+#define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
+#define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
+#define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
+#define AT91_PIT_SR             0x04                    /* Status Register */
+#define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
+#define AT91_PIT_PIVR           0x08                    /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR           0x0c                    /* Periodic Interval Image Register */
+#define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
+#define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
 #define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 7af2e108b8a0..f039538d3bdb 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -16,7 +16,7 @@
 #include <linux/linkage.h>
 #include <mach/hardware.h>
 #include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include "at91_rstc.h"
                        .arm
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 84af1b506d92..d3addee43d8d 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -18,10 +18,10 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
+#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -239,8 +239,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
        CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
        CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
        CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
@@ -256,10 +258,18 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
        CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
        CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
        CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
@@ -343,7 +353,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
 static void __init at91sam9g45_map_io(void)
 {
        at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
-        init_consistent_dma_size(SZ_4M);
 }
 static void __init at91sam9g45_ioremap_registers(void)
@@ -409,10 +418,10 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller (IRQ0) */
 };
-struct at91_init_soc __initdata at91sam9g45_soc = {
+AT91_SOC_START(sam9g45)
        .map_io = at91sam9g45_map_io,
        .default_irq_priority = at91sam9g45_default_irq_priority,
        .ioremap_registers = at91sam9g45_ioremap_registers,
        .register_clocks = at91sam9g45_register_clocks,
        .init = at91sam9g45_initialize,
-};
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index fcd233cb33d2..827c9f2a70fb 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -26,7 +26,6 @@
 #include <video/atmel_lcdc.h>
 #include <mach/at91_adc.h>
-#include <mach/board.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
 #include <mach/at91_matrix.h>
@@ -36,6 +35,7 @@
 #include <media/atmel-isi.h>
+#include "board.h"
 #include "generic.h"
 #include "clock.h"
@@ -1459,7 +1459,7 @@ static struct resource ssc0_resources[] = {
 };
 static struct platform_device at91sam9g45_ssc0_device = {
-        .name   = "ssc",
+        .name   = "at91sam9g45_ssc",
        .id     = 0,
        .dev    = {
                .dma_mask               = &ssc0_dmamask,
@@ -1501,7 +1501,7 @@ static struct resource ssc1_resources[] = {
 };
 static struct platform_device at91sam9g45_ssc1_device = {
-        .name   = "ssc",
+        .name   = "at91sam9g45_ssc",
        .id     = 1,
        .dev    = {
                .dma_mask               = &ssc1_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 9d457182c86c..721a1a34dd1d 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -13,8 +13,7 @@
 #include <linux/linkage.h>
 #include <mach/hardware.h>
 #include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include "at91_rstc.h"
                        .arm
                        .globl  at91sam9g45_restart
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 732d3d3f4ec5..5dfc8fd87103 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -15,8 +15,8 @@
 #include <mach/at91sam9n12.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
-#include <mach/board.h>
+#include "board.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -168,13 +168,14 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
-        CLKDEV_CON_ID("pioA", &pioAB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
-        CLKDEV_CON_ID("pioB", &pioAB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
-        CLKDEV_CON_ID("pioC", &pioCD_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
-        CLKDEV_CON_ID("pioD", &pioCD_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
        /* additional fake clock for macb_hclk */
        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
        CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
@@ -223,13 +224,10 @@ static void __init at91sam9n12_map_io(void)
 void __init at91sam9n12_initialize(void)
 {
        at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
-        /* Register GPIO subsystem (using DT) */
-        at91_gpio_init(NULL, 0);
 }
-struct at91_init_soc __initdata at91sam9n12_soc = {
+AT91_SOC_START(sam9n12)
        .map_io = at91sam9n12_map_io,
        .register_clocks = at91sam9n12_register_clocks,
        .init = at91sam9n12_initialize,
-};
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72e908412222..eb98704db2d9 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -19,10 +19,10 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include "at91_aic.h"
+#include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -184,8 +184,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -338,10 +340,10 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
        0,      /* Advanced Interrupt Controller */
 };
-struct at91_init_soc __initdata at91sam9rl_soc = {
+AT91_SOC_START(sam9rl)
        .map_io = at91sam9rl_map_io,
        .default_irq_priority = at91sam9rl_default_irq_priority,
        .ioremap_registers = at91sam9rl_ioremap_registers,
        .register_clocks = at91sam9rl_register_clocks,
        .init = at91sam9rl_initialize,
-};
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 5047bdc92adf..ddf223ff35c4 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -17,13 +17,13 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
-#include <mach/board.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91sam9rl_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <linux/platform_data/dma-atmel.h>
+#include "board.h"
 #include "generic.h"
@@ -832,7 +832,7 @@ static struct resource ssc0_resources[] = {
 };
 static struct platform_device at91sam9rl_ssc0_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 0,
        .dev    = {
                .dma_mask               = &ssc0_dmamask,
@@ -874,7 +874,7 @@ static struct resource ssc1_resources[] = {
 };
 static struct platform_device at91sam9rl_ssc1_device = {
-        .name   = "ssc",
+        .name   = "at91rm9200_ssc",
        .id     = 1,
        .dev    = {
                .dma_mask               = &ssc1_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e5035380dcbc..44a9a62dcc13 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -15,8 +15,8 @@
 #include <mach/at91sam9x5.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
-#include <mach/board.h>
+#include "board.h"
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
@@ -229,15 +229,18 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
        CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
-        CLKDEV_CON_ID("pioA", &pioAB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
-        CLKDEV_CON_ID("pioB", &pioAB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
-        CLKDEV_CON_ID("pioC", &pioCD_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
-        CLKDEV_CON_ID("pioD", &pioCD_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
        /* additional fake clock for macb_hclk */
        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
        CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
@@ -313,18 +316,11 @@ static void __init at91sam9x5_map_io(void)
        at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 }
-void __init at91sam9x5_initialize(void)
-{
-        /* Register GPIO subsystem (using DT) */
-        at91_gpio_init(NULL, 0);
-}
 /* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */
-struct at91_init_soc __initdata at91sam9x5_soc = {
+AT91_SOC_START(sam9x5)
        .map_io = at91sam9x5_map_io,
        .register_clocks = at91sam9x5_register_clocks,
-        .init = at91sam9x5_initialize,
+AT91_SOC_END
-};
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index bb7f54474b92..19ca79396905 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -18,9 +18,10 @@
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <mach/at91x40.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_st.h>
 #include <mach/timex.h>
+#include "at91_aic.h"
 #include "generic.h"
 /*
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index ee06d7bcdf76..0e57e440c061 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -26,7 +26,8 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach/time.h>
-#include <mach/at91_tc.h>
+#include "at91_tc.h"
 #define at91_tc_read(field) \
        __raw_readl(AT91_IO_P2V(AT91_TC) + field)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 22d8856094f1..b99b5752cc10 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -34,10 +34,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
 #include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 93a832f70232..854b97974287 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -43,9 +43,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
+#include "at91_aic.h"
-#include <mach/at91_aic.h>
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 477e708497bc..28a18ce6d914 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -38,10 +38,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 71d8f362a1d5..c17bb533a949 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -35,9 +35,9 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index e71c473316e3..847432441ecc 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -40,12 +40,12 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2cbd1a2b6c35..2a7af7868747 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -36,12 +36,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
 static struct gpio_led cpuat91_leds[] = {
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 3e37437a7a61..48a531e05be3 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -38,9 +38,9 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
@@ -53,6 +53,8 @@ static void __init csb337_init_early(void)
 static struct macb_platform_data __initdata csb337_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC2,
        .is_rmii        = 0,
+        /* The CSB337 bootloader stores the MAC the wrong-way around */
+        .rev_eth_addr   = 1,
 };
 static struct at91_usbh_data __initdata csb337_usbh_data = {
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 872871ab1160..ec0f3abd504b 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -35,9 +35,9 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index e8f45c4e0ea8..881170ce61dd 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,23 +15,20 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <asm/setup.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
 static const struct of_device_id irq_of_match[] __initconst = {
        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-        { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
-        { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
        { /*sentinel*/ }
 };
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 01f66e99ece7..b489388a6f84 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -27,8 +27,9 @@
 #include <mach/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
 static void __init at91eb01_init_irq(void)
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 0cfac16ee9d5..9f5e71c95f05 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -35,9 +35,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
+#include "at91_aic.h"
-#include <mach/at91_aic.h>
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 3d931ffac4bf..ef69e0ebe949 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -37,10 +37,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
 #include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index d93658a2b128..50f3d3795c05 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -24,12 +24,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
 static void __init eco920_init_early(void)
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index fa98abacb1ba..5d44eba0f20f 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -33,9 +33,9 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
 static void __init flexibity_init_early(void)
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 6e47071d8206..191d37c16bab 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -41,10 +41,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index a9d5e78118c5..23a2fa17ab29 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -30,14 +30,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/gsia18s.h>
-#include <mach/stamp9g20.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gsia18s.h"
+#include "stamp9g20.h"
 static void __init gsia18s_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 86050da3ba53..9a43d1e1a037 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -34,10 +34,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/cpu.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index abe9fed7a3e0..f168bec2369f 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -35,12 +35,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
 #include <mach/cpu.h>
-#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 6960778af4c2..bc7a1c4a1f6a 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -44,10 +44,10 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 9ca3e32c54cb..0299554495dd 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -29,13 +29,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/stamp9g20.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "stamp9g20.h"
 static void __init pcontrol_g20_init_early(void)
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index f83e1de699e6..4938f1cd5e13 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -37,11 +37,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 799f214edebe..33b1628467ea 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -40,11 +40,11 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include "at91_aic.h"
+#include "at91_shdwc.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-rm9200-dt.c
new file mode 100644
index 000000000000..5f9ce3da3fde
--- /dev/null
+++ b/arch/arm/mach-at91/board-rm9200-dt.c
@@ -0,0 +1,57 @@
+/*
+ *  Setup code for AT91RM9200 Evaluation Kits with Device Tree support
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *                2012 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include "at91_aic.h"
+#include "generic.h"
+static const struct of_device_id irq_of_match[] __initconst = {
+        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
+        { /*sentinel*/ }
+};
+static void __init at91rm9200_dt_init_irq(void)
+{
+        of_irq_init(irq_of_match);
+}
+static void __init at91rm9200_dt_device_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char *at91rm9200_dt_board_compat[] __initdata = {
+        "atmel,at91rm9200",
+        NULL
+};
+DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
+        .timer          = &at91rm9200_timer,
+        .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
+        .init_early     = at91rm9200_dt_initialize,
+        .init_irq       = at91rm9200_dt_init_irq,
+        .init_machine   = at91rm9200_dt_device_init,
+        .dt_compat      = at91rm9200_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 66338e7ebfba..9e5061bef0d0 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -39,11 +39,11 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 5d1b5729dc69..58277dbc718f 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -39,11 +39,11 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index a0ecf04e9ae3..2e8b8339a206 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -25,11 +25,11 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <linux/gpio.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
 static void __init rsi_ews_init_early(void)
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index c5f01acce3c0..b75fbf6003a1 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -37,10 +37,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 8cd6e679fbe0..f0135cd1d858 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -41,12 +41,12 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
+#include "at91_aic.h"
+#include "at91_shdwc.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index a9167dd45f96..13ebaa8e4100 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -45,12 +45,12 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
+#include "at91_aic.h"
+#include "at91_shdwc.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index b87dbe2be0d6..89b9608742a7 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -44,12 +44,12 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
+#include "at91_aic.h"
+#include "at91_shdwc.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 3ab2b86a3762..1b7dd9f688d3 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -43,11 +43,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
@@ -353,6 +353,16 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
        },
 };
+static struct platform_device sam9g20ek_audio_device = {
+        .name   = "at91sam9g20ek-audio",
+        .id     = -1,
+};
+static void __init ek_add_device_audio(void)
+{
+        platform_device_register(&sam9g20ek_audio_device);
+}
 static void __init ek_board_init(void)
 {
@@ -394,6 +404,7 @@ static void __init ek_board_init(void)
        at91_set_B_periph(AT91_PIN_PC1, 0);
        /* SSC (for WM8731) */
        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
+        ek_add_device_audio();
 }
 MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 3d48ec154685..e4cc375e3a32 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -42,12 +42,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
+#include "at91_aic.h"
+#include "at91_shdwc.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index fb89ea92e3f2..377a1097afa7 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -30,11 +30,12 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include "at91_aic.h"
+#include "at91_shdwc.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index a4e031a039fd..98771500ddb9 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -32,10 +32,10 @@
 #include <asm/mach/arch.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index c3fb31d5116e..48a962b61fa3 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -25,10 +25,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 6ea069b57335..c1060f96e589 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -41,11 +41,11 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include "at91_aic.h"
+#include "at91_shdwc.h"
+#include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index f162fdfd66eb..8673aebcb85d 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -43,12 +43,12 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include "at91_aic.h"
+#include "board.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/board.h
index c55a4364ffb4..4a234fb2ab3b 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/board.h
@@ -31,71 +31,24 @@
 #ifndef __ASM_ARCH_BOARD_H
 #define __ASM_ARCH_BOARD_H
-#include <linux/mtd/partitions.h>
-#include <linux/device.h>
-#include <linux/i2c.h>
-#include <linux/leds.h>
-#include <linux/spi/spi.h>
-#include <linux/usb/atmel_usba_udc.h>
-#include <linux/atmel-mci.h>
-#include <sound/atmel-ac97c.h>
-#include <linux/serial.h>
-#include <linux/platform_data/macb.h>
 #include <linux/platform_data/atmel.h>
 /* USB Device */
-struct at91_udc_data {
-        int     vbus_pin;               /* high == host powering us */
-        u8      vbus_active_low;        /* vbus polarity */
-        u8      vbus_polled;            /* Use polling, not interrupt */
-        int     pullup_pin;             /* active == D+ pulled up */
-        u8      pullup_active_low;      /* true == pullup_pin is active low */
-};
 extern void __init at91_add_device_udc(struct at91_udc_data *data);
 /* USB High Speed Device */
 extern void __init at91_add_device_usba(struct usba_platform_data *data);
 /* Compact Flash */
-struct at91_cf_data {
-        int     irq_pin;                /* I/O IRQ */
-        int     det_pin;                /* Card detect */
-        int     vcc_pin;                /* power switching */
-        int     rst_pin;                /* card reset */
-        u8      chipselect;             /* EBI Chip Select number */
-        u8      flags;
-#define AT91_CF_TRUE_IDE        0x01
-#define AT91_IDE_SWAP_A0_A2     0x02
-};
 extern void __init at91_add_device_cf(struct at91_cf_data *data);
 /* MMC / SD */
-  /* at91_mci platform config */
-struct at91_mmc_data {
-        int             det_pin;        /* card detect IRQ */
-        unsigned        slot_b:1;       /* uses Slot B */
-        unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
-        int             wp_pin;         /* (SD) writeprotect detect */
-        int             vcc_pin;        /* power switching (high == on) */
-};
-extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
  /* atmel-mci platform config */
 extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
 extern void __init at91_add_device_eth(struct macb_platform_data *data);
 /* USB Host */
-#define AT91_MAX_USBH_PORTS     3
-struct at91_usbh_data {
-        int             vbus_pin[AT91_MAX_USBH_PORTS];  /* port power-control pin */
-        int             overcurrent_pin[AT91_MAX_USBH_PORTS];
-        u8              ports;                          /* number of ports on root hub */
-        u8              overcurrent_supported;
-        u8              vbus_pin_active_low[AT91_MAX_USBH_PORTS];
-        u8              overcurrent_status[AT91_MAX_USBH_PORTS];
-        u8              overcurrent_changed[AT91_MAX_USBH_PORTS];
-};
 extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
 extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
 extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
@@ -124,13 +77,6 @@ extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pin
 extern struct platform_device *atmel_default_console_device;
-struct atmel_uart_data {
-        int                     num;            /* port num */
-        short                   use_dma_tx;     /* use transmit DMA? */
-        short                   use_dma_rx;     /* use receive DMA? */
-        void __iomem            *regs;          /* virt. base address, if any */
-        struct serial_rs485     rs485;          /* rs485 settings */
-};
 extern void __init at91_add_device_serial(void);
 /*
@@ -173,24 +119,13 @@ extern void __init at91_add_device_isi(struct isi_platform_data *data,
                bool use_pck_as_mck);
 /* Touchscreen Controller */
-struct at91_tsadcc_data {
-        unsigned int    adc_clock;
-        u8              pendet_debounce;
-        u8              ts_sample_hold_time;
-};
 extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data);
 /* CAN */
-struct at91_can_data {
-        void (*transceiver_switch)(int on);
-};
 extern void __init at91_add_device_can(struct at91_can_data *data);
 /* LEDs */
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
-/* FIXME: this needs a better location, but gets stuff building again */
-extern int at91_suspend_entering_slow_clock(void);
 #endif
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index b62f560e6c75..fc593d615e7d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -20,6 +20,7 @@ extern void __init at91_init_sram(int bank, unsigned long base,
 extern void __init at91rm9200_set_type(int type);
 extern void __init at91_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
+extern void __init at91rm9200_dt_initialize(void);
 extern void __init at91_dt_initialize(void);
 /* Interrupts */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0e74bd..c5d7e1e9d757 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -23,8 +23,6 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_gpio.h>
 #include <asm/mach/irq.h>
@@ -33,6 +31,8 @@
 #include "generic.h"
+#define MAX_NB_GPIO_PER_BANK    32
 struct at91_gpio_chip {
        struct gpio_chip        chip;
        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
@@ -46,6 +46,7 @@ struct at91_gpio_chip {
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
@@ -55,26 +56,27 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset);
 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
-#define AT91_GPIO_CHIP(name, nr_gpio)                                   \
+#define AT91_GPIO_CHIP(name)                                            \
        {                                                               \
                .chip = {                                               \
                        .label            = name,                       \
+                        .request          = at91_gpiolib_request,       \
                        .direction_input  = at91_gpiolib_direction_input, \
                        .direction_output = at91_gpiolib_direction_output, \
                        .get              = at91_gpiolib_get,           \
                        .set              = at91_gpiolib_set,           \
                        .dbg_show         = at91_gpiolib_dbg_show,      \
                        .to_irq           = at91_gpiolib_to_irq,        \
-                        .ngpio            = nr_gpio,                    \
+                        .ngpio            = MAX_NB_GPIO_PER_BANK,       \
                },                                                      \
        }
 static struct at91_gpio_chip gpio_chip[] = {
-        AT91_GPIO_CHIP("pioA", 32),
+        AT91_GPIO_CHIP("pioA"),
-        AT91_GPIO_CHIP("pioB", 32),
+        AT91_GPIO_CHIP("pioB"),
-        AT91_GPIO_CHIP("pioC", 32),
+        AT91_GPIO_CHIP("pioC"),
-        AT91_GPIO_CHIP("pioD", 32),
+        AT91_GPIO_CHIP("pioD"),
-        AT91_GPIO_CHIP("pioE", 32),
+        AT91_GPIO_CHIP("pioE"),
 };
 static int gpio_banks;
@@ -89,7 +91,7 @@ static unsigned long at91_gpio_caps;
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
-        pin /= 32;
+        pin /= MAX_NB_GPIO_PER_BANK;
        if (likely(pin < gpio_banks))
                return gpio_chip[pin].regbase;
@@ -98,7 +100,7 @@ static inline void __iomem *pin_to_controller(unsigned pin)
 static inline unsigned pin_to_mask(unsigned pin)
 {
-        return 1 << (pin % 32);
+        return 1 << (pin % MAX_NB_GPIO_PER_BANK);
 }
@@ -713,80 +715,6 @@ postcore_initcall(at91_gpio_debugfs_init);
 */
 static struct lock_class_key gpio_lock_class;
-#if defined(CONFIG_OF)
-static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
-                                                        irq_hw_number_t hw)
-{
-        struct at91_gpio_chip   *at91_gpio = h->host_data;
-        irq_set_lockdep_class(virq, &gpio_lock_class);
-        /*
-         * Can use the "simple" and not "edge" handler since it's
-         * shorter, and the AIC handles interrupts sanely.
-         */
-        irq_set_chip_and_handler(virq, &gpio_irqchip,
-                                 handle_simple_irq);
-        set_irq_flags(virq, IRQF_VALID);
-        irq_set_chip_data(virq, at91_gpio);
-        return 0;
-}
-static struct irq_domain_ops at91_gpio_ops = {
-        .map    = at91_gpio_irq_map,
-        .xlate  = irq_domain_xlate_twocell,
-};
-int __init at91_gpio_of_irq_setup(struct device_node *node,
-                                     struct device_node *parent)
-{
-        struct at91_gpio_chip   *prev = NULL;
-        int                     alias_idx = of_alias_get_id(node, "gpio");
-        struct at91_gpio_chip   *at91_gpio = &gpio_chip[alias_idx];
-        /* Setup proper .irq_set_type function */
-        if (has_pio3())
-                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
-        else
-                gpio_irqchip.irq_set_type = gpio_irq_type;
-        /* Disable irqs of this PIO controller */
-        __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
-        /* Setup irq domain */
-        at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
-                                                &at91_gpio_ops, at91_gpio);
-        if (!at91_gpio->domain)
-                panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
-                        at91_gpio->pioc_idx);
-        /* Setup chained handler */
-        if (at91_gpio->pioc_idx)
-                prev = &gpio_chip[at91_gpio->pioc_idx - 1];
-        /* The toplevel handler handles one bank of GPIOs, except
-         * on some SoC it can handles up to three...
-         * We only set up the handler for the first of the list.
-         */
-        if (prev && prev->next == at91_gpio)
-                return 0;
-        at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
-                                                        at91_gpio->pioc_hwirq);
-        irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
-        irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
-        return 0;
-}
-#else
-int __init at91_gpio_of_irq_setup(struct device_node *node,
-                                     struct device_node *parent)
-{
-        return -EINVAL;
-}
-#endif
 /*
 * irqdomain initialization: pile up irqdomains on top of AIC range
 */
@@ -862,6 +790,16 @@ void __init at91_gpio_irq_setup(void)
 }
 /* gpiolib support */
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        void __iomem *pio = at91_gpio->regbase;
+        unsigned mask = 1 << offset;
+        __raw_writel(mask, pio + PIO_PER);
+        return 0;
+}
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset)
 {
@@ -975,81 +913,11 @@ err:
        return -EINVAL;
 }
-#ifdef CONFIG_OF_GPIO
-static void __init of_at91_gpio_init_one(struct device_node *np)
-{
-        int alias_idx;
-        struct at91_gpio_chip *at91_gpio;
-        if (!np)
-                return;
-        alias_idx = of_alias_get_id(np, "gpio");
-        if (alias_idx >= MAX_GPIO_BANKS) {
-                pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
-                                                alias_idx, MAX_GPIO_BANKS);
-                return;
-        }
-        at91_gpio = &gpio_chip[alias_idx];
-        at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
-        at91_gpio->regbase = of_iomap(np, 0);
-        if (!at91_gpio->regbase) {
-                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
-                                                                alias_idx);
-                return;
-        }
-        /* Get the interrupts property */
-        if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
-                pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
-                                                                alias_idx);
-                goto ioremap_err;
-        }
-        /* Get capabilities from compatibility property */
-        if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
-                at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
-        /* Setup clock */
-        if (at91_gpio_setup_clk(alias_idx))
-                goto ioremap_err;
-        at91_gpio->chip.of_node = np;
-        gpio_banks = max(gpio_banks, alias_idx + 1);
-        at91_gpio->pioc_idx = alias_idx;
-        return;
-ioremap_err:
-        iounmap(at91_gpio->regbase);
-}
-static int __init of_at91_gpio_init(void)
-{
-        struct device_node *np = NULL;
-        /*
-         * This isn't ideal, but it gets things hooked up until this
-         * driver is converted into a platform_device
-         */
-        for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
-                of_at91_gpio_init_one(np);
-        return gpio_banks > 0 ? 0 : -EINVAL;
-}
-#else
-static int __init of_at91_gpio_init(void)
-{
-        return -EINVAL;
-}
-#endif
 static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
 {
        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
-        at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
+        at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
        at91_gpio->pioc_hwirq = pioc_hwirq;
        at91_gpio->pioc_idx = idx;
@@ -1079,11 +947,11 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
        BUG_ON(nr_banks > MAX_GPIO_BANKS);
-        if (of_at91_gpio_init() < 0) {
+        if (of_have_populated_dt())
-                /* No GPIO controller found in device tree */
+                return;
-                for (i = 0; i < nr_banks; i++)
-                        at91_gpio_init_one(i, data[i].regbase, data[i].id);
+        for (i = 0; i < nr_banks; i++)
-        }
+                at91_gpio_init_one(i, data[i].regbase, data[i].id);
        for (i = 0; i < gpio_banks; i++) {
                at91_gpio = &gpio_chip[i];
diff --git a/arch/arm/mach-at91/include/mach/gsia18s.h b/arch/arm/mach-at91/gsia18s.h
index 307c194926f9..307c194926f9 100644
--- a/arch/arm/mach-at91/include/mach/gsia18s.h
+++ b/arch/arm/mach-at91/gsia18s.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
deleted file mode 100644
index d1f80ad7f4d4..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_pit.h
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Periodic Interval Timer (PIT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_PIT_H
-#define AT91_PIT_H
-#define AT91_PIT_MR             0x00                    /* Mode Register */
-#define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
-#define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
-#define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
-#define AT91_PIT_SR             0x04                    /* Status Register */
-#define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
-#define AT91_PIT_PIVR           0x08                    /* Periodic Interval Value Register */
-#define AT91_PIT_PIIR           0x0c                    /* Periodic Interval Image Register */
-#define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
-#define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
deleted file mode 100644
index da1945e5f714..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_rtc.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_rtc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Real Time Clock (RTC) - System peripheral registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_RTC_H
-#define AT91_RTC_H
-#define AT91_RTC_CR             0x00                    /* Control Register */
-#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
-#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
-#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
-#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
-#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
-#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
-#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
-#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
-#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
-#define AT91_RTC_MR             0x04                    /* Mode Register */
-#define                 AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
-#define AT91_RTC_TIMR           0x08                    /* Time Register */
-#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
-#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
-#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
-#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
-#define AT91_RTC_CALR           0x0c                    /* Calendar Register */
-#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
-#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
-#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
-#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
-#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
-#define AT91_RTC_TIMALR         0x10                    /* Time Alarm Register */
-#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
-#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
-#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
-#define AT91_RTC_CALALR         0x14                    /* Calendar Alarm Register */
-#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
-#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
-#define AT91_RTC_SR             0x18                    /* Status Register */
-#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
-#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
-#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
-#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
-#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
-#define AT91_RTC_SCCR           0x1c                    /* Status Clear Command Register */
-#define AT91_RTC_IER            0x20                    /* Interrupt Enable Register */
-#define AT91_RTC_IDR            0x24                    /* Interrupt Disable Register */
-#define AT91_RTC_IMR            0x28                    /* Interrupt Mask Register */
-#define AT91_RTC_VER            0x2c                    /* Valid Entry Register */
-#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
-#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
-#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
-#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
deleted file mode 100644
index b8260cd8041c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200_emac.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Ethernet MAC registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91RM9200_EMAC_H
-#define AT91RM9200_EMAC_H
-#define AT91_EMAC_CTL           0x00    /* Control Register */
-#define         AT91_EMAC_LB            (1 <<  0)       /* Loopback */
-#define         AT91_EMAC_LBL           (1 <<  1)       /* Loopback Local */
-#define         AT91_EMAC_RE            (1 <<  2)       /* Receive Enable */
-#define         AT91_EMAC_TE            (1 <<  3)       /* Transmit Enable */
-#define         AT91_EMAC_MPE           (1 <<  4)       /* Management Port Enable */
-#define         AT91_EMAC_CSR           (1 <<  5)       /* Clear Statistics Registers */
-#define         AT91_EMAC_INCSTAT       (1 <<  6)       /* Increment Statistics Registers */
-#define         AT91_EMAC_WES           (1 <<  7)       /* Write Enable for Statistics Registers */
-#define         AT91_EMAC_BP            (1 <<  8)       /* Back Pressure */
-#define AT91_EMAC_CFG           0x04    /* Configuration Register */
-#define         AT91_EMAC_SPD           (1 <<  0)       /* Speed */
-#define         AT91_EMAC_FD            (1 <<  1)       /* Full Duplex */
-#define         AT91_EMAC_BR            (1 <<  2)       /* Bit Rate */
-#define         AT91_EMAC_CAF           (1 <<  4)       /* Copy All Frames */
-#define         AT91_EMAC_NBC           (1 <<  5)       /* No Broadcast */
-#define         AT91_EMAC_MTI           (1 <<  6)       /* Multicast Hash Enable */
-#define         AT91_EMAC_UNI           (1 <<  7)       /* Unicast Hash Enable */
-#define         AT91_EMAC_BIG           (1 <<  8)       /* Receive 1522 Bytes */
-#define         AT91_EMAC_EAE           (1 <<  9)       /* External Address Match Enable */
-#define         AT91_EMAC_CLK           (3 << 10)       /* MDC Clock Divisor */
-#define         AT91_EMAC_CLK_DIV8              (0 << 10)
-#define         AT91_EMAC_CLK_DIV16             (1 << 10)
-#define         AT91_EMAC_CLK_DIV32             (2 << 10)
-#define         AT91_EMAC_CLK_DIV64             (3 << 10)
-#define         AT91_EMAC_RTY           (1 << 12)       /* Retry Test */
-#define         AT91_EMAC_RMII          (1 << 13)       /* Reduce MII (RMII) */
-#define AT91_EMAC_SR            0x08    /* Status Register */
-#define         AT91_EMAC_SR_LINK       (1 <<  0)       /* Link */
-#define         AT91_EMAC_SR_MDIO       (1 <<  1)       /* MDIO pin */
-#define         AT91_EMAC_SR_IDLE       (1 <<  2)       /* PHY idle */
-#define AT91_EMAC_TAR           0x0c    /* Transmit Address Register */
-#define AT91_EMAC_TCR           0x10    /* Transmit Control Register */
-#define         AT91_EMAC_LEN           (0x7ff << 0)    /* Transmit Frame Length */
-#define         AT91_EMAC_NCRC          (1     << 15)   /* No CRC */
-#define AT91_EMAC_TSR           0x14    /* Transmit Status Register */
-#define         AT91_EMAC_TSR_OVR       (1 <<  0)       /* Transmit Buffer Overrun */
-#define         AT91_EMAC_TSR_COL       (1 <<  1)       /* Collision Occurred */
-#define         AT91_EMAC_TSR_RLE       (1 <<  2)       /* Retry Limit Exceeded */
-#define         AT91_EMAC_TSR_IDLE      (1 <<  3)       /* Transmitter Idle */
-#define         AT91_EMAC_TSR_BNQ       (1 <<  4)       /* Transmit Buffer not Queued */
-#define         AT91_EMAC_TSR_COMP      (1 <<  5)       /* Transmit Complete */
-#define         AT91_EMAC_TSR_UND       (1 <<  6)       /* Transmit Underrun */
-#define AT91_EMAC_RBQP          0x18    /* Receive Buffer Queue Pointer */
-#define AT91_EMAC_RSR           0x20    /* Receive Status Register */
-#define         AT91_EMAC_RSR_BNA       (1 <<  0)       /* Buffer Not Available */
-#define         AT91_EMAC_RSR_REC       (1 <<  1)       /* Frame Received */
-#define         AT91_EMAC_RSR_OVR       (1 <<  2)       /* RX Overrun */
-#define AT91_EMAC_ISR           0x24    /* Interrupt Status Register */
-#define         AT91_EMAC_DONE          (1 <<  0)       /* Management Done */
-#define         AT91_EMAC_RCOM          (1 <<  1)       /* Receive Complete */
-#define         AT91_EMAC_RBNA          (1 <<  2)       /* Receive Buffer Not Available */
-#define         AT91_EMAC_TOVR          (1 <<  3)       /* Transmit Buffer Overrun */
-#define         AT91_EMAC_TUND          (1 <<  4)       /* Transmit Buffer Underrun */
-#define         AT91_EMAC_RTRY          (1 <<  5)       /* Retry Limit */
-#define         AT91_EMAC_TBRE          (1 <<  6)       /* Transmit Buffer Register Empty */
-#define         AT91_EMAC_TCOM          (1 <<  7)       /* Transmit Complete */
-#define         AT91_EMAC_TIDLE         (1 <<  8)       /* Transmit Idle */
-#define         AT91_EMAC_LINK          (1 <<  9)       /* Link */
-#define         AT91_EMAC_ROVR          (1 << 10)       /* RX Overrun */
-#define         AT91_EMAC_ABT           (1 << 11)       /* Abort */
-#define AT91_EMAC_IER           0x28    /* Interrupt Enable Register */
-#define AT91_EMAC_IDR           0x2c    /* Interrupt Disable Register */
-#define AT91_EMAC_IMR           0x30    /* Interrupt Mask Register */
-#define AT91_EMAC_MAN           0x34    /* PHY Maintenance Register */
-#define         AT91_EMAC_DATA          (0xffff << 0)   /* MDIO Data */
-#define         AT91_EMAC_REGA          (0x1f   << 18)  /* MDIO Register */
-#define         AT91_EMAC_PHYA          (0x1f   << 23)  /* MDIO PHY Address */
-#define         AT91_EMAC_RW            (3      << 28)  /* Read/Write operation */
-#define                 AT91_EMAC_RW_W          (1 << 28)
-#define                 AT91_EMAC_RW_R          (2 << 28)
-#define         AT91_EMAC_MAN_802_3     0x40020000      /* IEEE 802.3 value */
-/*
- * Statistics Registers.
- */
-#define AT91_EMAC_FRA           0x40    /* Frames Transmitted OK */
-#define AT91_EMAC_SCOL          0x44    /* Single Collision Frame */
-#define AT91_EMAC_MCOL          0x48    /* Multiple Collision Frame */
-#define AT91_EMAC_OK            0x4c    /* Frames Received OK */
-#define AT91_EMAC_SEQE          0x50    /* Frame Check Sequence Error */
-#define AT91_EMAC_ALE           0x54    /* Alignmemt Error */
-#define AT91_EMAC_DTE           0x58    /* Deffered Transmission Frame */
-#define AT91_EMAC_LCOL          0x5c    /* Late Collision */
-#define AT91_EMAC_ECOL          0x60    /* Excessive Collision */
-#define AT91_EMAC_TUE           0x64    /* Transmit Underrun Error */
-#define AT91_EMAC_CSE           0x68    /* Carrier Sense Error */
-#define AT91_EMAC_DRFC          0x6c    /* Discard RX Frame */
-#define AT91_EMAC_ROV           0x70    /* Receive Overrun */
-#define AT91_EMAC_CDE           0x74    /* Code Error */
-#define AT91_EMAC_ELR           0x78    /* Excessive Length Error */
-#define AT91_EMAC_RJB           0x7c    /* Receive Jabber */
-#define AT91_EMAC_USF           0x80    /* Undersize Frame */
-#define AT91_EMAC_SQEE          0x84    /* SQE Test Error */
-/*
- * Address Registers.
- */
-#define AT91_EMAC_HSL           0x90    /* Hash Address Low [31:0] */
-#define AT91_EMAC_HSH           0x94    /* Hash Address High [63:32] */
-#define AT91_EMAC_SA1L          0x98    /* Specific Address 1 Low, bytes 0-3 */
-#define AT91_EMAC_SA1H          0x9c    /* Specific Address 1 High, bytes 4-5 */
-#define AT91_EMAC_SA2L          0xa0    /* Specific Address 2 Low, bytes 0-3 */
-#define AT91_EMAC_SA2H          0xa4    /* Specific Address 2 High, bytes 4-5 */
-#define AT91_EMAC_SA3L          0xa8    /* Specific Address 3 Low, bytes 0-3 */
-#define AT91_EMAC_SA3H          0xac    /* Specific Address 3 High, bytes 4-5 */
-#define AT91_EMAC_SA4L          0xb0    /* Specific Address 4 Low, bytes 0-3 */
-#define AT91_EMAC_SA4H          0xb4    /* Specific Address 4 High, bytes 4-5 */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/atmel-mci.h b/arch/arm/mach-at91/include/mach/atmel-mci.h
index cd580a12e904..3069e4135573 100644
--- a/arch/arm/mach-at91/include/mach/atmel-mci.h
+++ b/arch/arm/mach-at91/include/mach/atmel-mci.h
@@ -14,11 +14,4 @@ struct mci_dma_data {
 #define slave_data_ptr(s)       (&(s)->sdata)
 #define find_slave_dev(s)       ((s)->sdata.dma_dev)
-#define setup_dma_addr(s, t, r) do {            \
-        if (s) {                                \
-                (s)->sdata.tx_reg = (t);        \
-                (s)->sdata.rx_reg = (r);        \
-        }                                       \
-} while (0)
 #endif /* __MACH_ATMEL_MCI_H */
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 711a7892d331..a832e0707611 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -90,9 +90,6 @@
 #define AT91_SRAM_MAX           SZ_1M
 #define AT91_VIRT_BASE          (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
-/* Serial ports */
-#define ATMEL_MAX_UART          7               /* 6 USART3's and one DBGU port (SAM9260) */
 /* External Memory Map */
 #define AT91_CHIPSELECT_0       0x10000000
 #define AT91_CHIPSELECT_1       0x20000000
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index febc2ee901a5..8e210262aeee 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -42,7 +42,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <mach/at91_aic.h>
+#include "at91_aic.h"
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 1b1e62b5f41b..3e22978b5547 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <mach/board.h>
+#include "board.h"
 /* ------------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5315f05896e9..adb6db888a1f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -25,10 +25,10 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
-#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
+#include "at91_aic.h"
 #include "generic.h"
 #include "pm.h"
@@ -36,8 +36,8 @@
 * Show the reason for the previous system reset.
 */
-#include <mach/at91_rstc.h>
+#include "at91_rstc.h"
-#include <mach/at91_shdwc.h>
+#include "at91_shdwc.h"
 static void __init show_reset_status(void)
 {
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 0b32c81730a5..9ee866ce0478 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -10,6 +10,7 @@
 #include <linux/mm.h>
 #include <linux/pm.h>
 #include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
@@ -18,8 +19,8 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91_pmc.h>
-#include <mach/at91_shdwc.h>
+#include "at91_shdwc.h"
 #include "soc.h"
 #include "generic.h"
@@ -338,6 +339,7 @@ static void at91_dt_rstc(void)
 }
 static struct of_device_id ramc_ids[] = {
+        { .compatible = "atmel,at91rm9200-sdramc" },
        { .compatible = "atmel,at91sam9260-sdramc" },
        { .compatible = "atmel,at91sam9g45-ddramc" },
        { /*sentinel*/ }
@@ -436,6 +438,19 @@ end:
        of_node_put(np);
 }
+void __init at91rm9200_dt_initialize(void)
+{
+        at91_dt_ramc();
+        /* Init clock subsystem */
+        at91_dt_clock_init();
+        /* Register the processor-specific clocks */
+        at91_boot_soc.register_clocks();
+        at91_boot_soc.init();
+}
 void __init at91_dt_initialize(void)
 {
        at91_dt_rstc();
@@ -448,7 +463,8 @@ void __init at91_dt_initialize(void)
        /* Register the processor-specific clocks */
        at91_boot_soc.register_clocks();
-        at91_boot_soc.init();
+        if (at91_boot_soc.init)
+                at91_boot_soc.init();
 }
 #endif
@@ -463,4 +479,6 @@ void __init at91_initialize(unsigned long main_clock)
        at91_boot_soc.register_clocks();
        at91_boot_soc.init();
+        pinctrl_provide_dummies();
 }
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index a9cfeb153719..9c6d3d4f9a23 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -5,6 +5,7 @@
 */
 struct at91_init_soc {
+        int builtin;
        unsigned int *default_irq_priority;
        void (*map_io)(void);
        void (*ioremap_registers)(void);
@@ -22,9 +23,18 @@ extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
 extern struct at91_init_soc at91sam9n12_soc;
+#define AT91_SOC_START(_name)                           \
+struct at91_init_soc __initdata at91##_name##_soc       \
+ __used                                                 \
+                                                = {     \
+        .builtin        = 1,                            \
+#define AT91_SOC_END                                    \
+};
 static inline int at91_soc_is_enabled(void)
 {
-        return at91_boot_soc.init != NULL;
+        return at91_boot_soc.builtin;
 }
 #if !defined(CONFIG_SOC_AT91RM9200)
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/stamp9g20.h
index f62c0abca4b4..f62c0abca4b4 100644
--- a/arch/arm/mach-at91/include/mach/stamp9g20.h
+++ b/arch/arm/mach-at91/stamp9g20.h
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
new file mode 100644
index 000000000000..48705c10a0fe
--- /dev/null
+++ b/arch/arm/mach-bcm/Kconfig
@@ -0,0 +1,19 @@
+config ARCH_BCM
+        bool "Broadcom SoC" if ARCH_MULTI_V7
+        depends on MMU
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_764369 if SMP
+        select ARM_GIC
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select GENERIC_TIME
+        select GPIO_BCM
+        select SPARSE_IRQ
+        select TICK_ONESHOT
+        help
+          This enables support for system based on Broadcom SoCs.
+          It currently supports the 'BCM281XX' family, which includes
+          BCM11130, BCM11140, BCM11351, BCM28145 and
+          BCM28155 variants.
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
new file mode 100644
index 000000000000..bbf412261e5e
--- /dev/null
+++ b/arch/arm/mach-bcm/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2012 Broadcom Corporation
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation version 2.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+obj-$(CONFIG_ARCH_BCM) := board_bcm.o
diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
new file mode 100644
index 000000000000..3a62f1b1cabc
--- /dev/null
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/time.h>
+static const struct of_device_id irq_match[] = {
+        {.compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {}
+};
+static void timer_init(void)
+{
+}
+static struct sys_timer timer = {
+        .init = timer_init,
+};
+static void __init init_irq(void)
+{
+        of_irq_init(irq_match);
+}
+static void __init board_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                &platform_bus);
+}
+static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
+DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
+        .init_irq = init_irq,
+        .timer = &timer,
+        .init_machine = board_init,
+        .dt_compat = bcm11351_dt_compat,
+        .handle_irq = gic_handle_irq,
+MACHINE_END
diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot
index 2d30e17f5b69..b3271754e9fd 100644
--- a/arch/arm/mach-bcm2835/Makefile.boot
+++ b/arch/arm/mach-bcm2835/Makefile.boot
@@ -1,3 +1 @@
-   zreladdr-y := 0x00008000
+zreladdr-y := 0x00008000
-params_phys-y := 0x00000100
-initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index f6fea4933571..f0d739f4b7a3 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -12,8 +12,10 @@
 * GNU General Public License for more details.
 */
+#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/irqchip/bcm2835.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/bcm2835_timer.h>
 #include <linux/clk/bcm2835.h>
@@ -23,6 +25,48 @@
 #include <mach/bcm2835_soc.h>
+#define PM_RSTC                         0x1c
+#define PM_WDOG                         0x24
+#define PM_PASSWORD                     0x5a000000
+#define PM_RSTC_WRCFG_MASK              0x00000030
+#define PM_RSTC_WRCFG_FULL_RESET        0x00000020
+static void __iomem *wdt_regs;
+/*
+ * The machine restart method can be called from an atomic context so we won't
+ * be able to ioremap the regs then.
+ */
+static void bcm2835_setup_restart(void)
+{
+        struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                                "brcm,bcm2835-pm-wdt");
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+        wdt_regs = of_iomap(np, 0);
+        WARN(!wdt_regs, "failed to remap watchdog regs");
+}
+static void bcm2835_restart(char mode, const char *cmd)
+{
+        u32 val;
+        if (!wdt_regs)
+                return;
+        /* use a timeout of 10 ticks (~150us) */
+        writel_relaxed(10 | PM_PASSWORD, wdt_regs + PM_WDOG);
+        val = readl_relaxed(wdt_regs + PM_RSTC);
+        val &= ~PM_RSTC_WRCFG_MASK;
+        val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
+        writel_relaxed(val, wdt_regs + PM_RSTC);
+        /* No sleeping, possibly atomic. */
+        mdelay(1);
+}
 static struct map_desc io_map __initdata = {
        .virtual = BCM2835_PERIPH_VIRT,
        .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
@@ -30,15 +74,16 @@ static struct map_desc io_map __initdata = {
        .type = MT_DEVICE
 };
-void __init bcm2835_map_io(void)
+static void __init bcm2835_map_io(void)
 {
        iotable_init(&io_map, 1);
 }
-void __init bcm2835_init(void)
+static void __init bcm2835_init(void)
 {
        int ret;
+        bcm2835_setup_restart();
        bcm2835_init_clocks();
        ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
@@ -60,5 +105,6 @@ DT_MACHINE_START(BCM2835, "BCM2835")
        .handle_irq = bcm2835_handle_irq,
        .init_machine = bcm2835_init,
        .timer = &bcm2835_timer,
+        .restart = bcm2835_restart,
        .dt_compat = bcm2835_compat
 MACHINE_END
diff --git a/arch/arm/mach-bcm2835/include/mach/gpio.h b/arch/arm/mach-bcm2835/include/mach/gpio.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 263242da2cb8..2d00165e85ec 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -10,7 +10,6 @@ config ARCH_AUTCPU12
 config ARCH_CDB89712
        bool "CDB89712"
-        select ISA
        help
          This is an evaluation board from Cirrus for the CS89712 processor.
          The board includes 2 serial ports, Ethernet, IRDA, and expansion
@@ -25,7 +24,6 @@ config ARCH_EDB7211
        bool "EDB7211"
        select ARCH_SELECT_MEMORY_MODEL
        select ARCH_SPARSEMEM_ENABLE
-        select ISA
        help
          Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
          evaluation board.
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 6da6940b3656..992995af666a 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -9,9 +9,9 @@ obj-m			:=
 obj-n                   :=
 obj-                    :=
-obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
+obj-$(CONFIG_ARCH_AUTCPU12)     += board-autcpu12.o
-obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
+obj-$(CONFIG_ARCH_CDB89712)     += board-cdb89712.o
-obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
+obj-$(CONFIG_ARCH_CLEP7312)     += board-clep7312.o
-obj-$(CONFIG_ARCH_EDB7211)  += edb7211-arch.o edb7211-mm.o
+obj-$(CONFIG_ARCH_EDB7211)      += board-edb7211.o
-obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
+obj-$(CONFIG_ARCH_FORTUNET)     += board-fortunet.o
-obj-$(CONFIG_ARCH_P720T)    += p720t.o
+obj-$(CONFIG_ARCH_P720T)        += board-p720t.o
diff --git a/arch/arm/mach-clps711x/Makefile.boot b/arch/arm/mach-clps711x/Makefile.boot
index 9398e859b5af..eba77d35a615 100644
--- a/arch/arm/mach-clps711x/Makefile.boot
+++ b/arch/arm/mach-clps711x/Makefile.boot
@@ -1,5 +1,4 @@
 # The standard locations for stuff on CLPS711x type processors
-   zreladdr-y                           += 0xc0028000
 params_phys-y                           := 0xc0000100
 # Should probably have some agreement on these...
 initrd_phys-$(CONFIG_ARCH_P720T)        := 0xc0400000
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
deleted file mode 100644
index 32871918bb6e..000000000000
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/autcpu12.c
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <mach/hardware.h>
-#include <asm/sizes.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <mach/autcpu12.h>
-#include "common.h"
-/*
- * The on-chip registers are given a size of 1MB so that a section can
- * be used to map them; this saves a page table.  This is the place to
- * add mappings for ROM, expansion memory, PCMCIA, etc.  (if static
- * mappings are chosen for those areas).
- *
-*/
-static struct map_desc autcpu12_io_desc[] __initdata = {
-        /* memory-mapped extra io and CS8900A Ethernet chip */
-        /* ethernet chip */
-        {
-                .virtual        = AUTCPU12_VIRT_CS8900A,
-                .pfn            = __phys_to_pfn(AUTCPU12_PHYS_CS8900A),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }
-};
-void __init autcpu12_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(autcpu12_io_desc, ARRAY_SIZE(autcpu12_io_desc));
-}
-static struct resource autcpu12_nvram_resource[] __initdata = {
-        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
-};
-static struct platform_device autcpu12_nvram_pdev __initdata = {
-        .name           = "autcpu12_nvram",
-        .id             = -1,
-        .resource       = autcpu12_nvram_resource,
-        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
-};
-static void __init autcpu12_init(void)
-{
-        platform_device_register(&autcpu12_nvram_pdev);
-}
-MACHINE_START(AUTCPU12, "autronix autcpu12")
-        /* Maintainer: Thomas Gleixner */
-        .atag_offset    = 0x20000,
-        .init_machine   = autcpu12_init,
-        .map_io         = autcpu12_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
new file mode 100644
index 000000000000..3fbf43f72589
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -0,0 +1,179 @@
+/*
+ *  linux/arch/arm/mach-clps711x/autcpu12.c
+ *
+ * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand-gpio.h>
+#include <linux/platform_device.h>
+#include <linux/basic_mmio_gpio.h>
+#include <mach/hardware.h>
+#include <asm/sizes.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <mach/autcpu12.h>
+#include "common.h"
+#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+#define AUTCPU12_SMC_BASE       (CS1_PHYS_BASE + 0x06000000)
+#define AUTCPU12_SMC_SEL_BASE   (AUTCPU12_SMC_BASE + 0x10)
+#define AUTCPU12_MMGPIO_BASE    (CLPS711X_NR_GPIO)
+#define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
+#define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
+#define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
+#define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
+static struct resource autcpu12_cs8900_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
+        DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
+};
+static struct resource autcpu12_nvram_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
+};
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+        .name           = "autcpu12_nvram",
+        .id             = -1,
+        .resource       = autcpu12_nvram_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
+};
+static struct resource autcpu12_nand_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
+};
+static struct mtd_partition autcpu12_nand_parts[] __initdata = {
+        {
+                .name   = "Flash partition 1",
+                .offset = 0,
+                .size   = SZ_8M,
+        },
+        {
+                .name   = "Flash partition 2",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
+                                         size_t sz)
+{
+        switch (sz) {
+        case SZ_16M:
+        case SZ_32M:
+                break;
+        case SZ_64M:
+        case SZ_128M:
+                pdata->parts[0].size = SZ_16M;
+                break;
+        default:
+                pr_warn("Unsupported SmartMedia device size %u\n", sz);
+                break;
+        }
+}
+static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
+        .gpio_rdy       = AUTCPU12_SMC_RDY,
+        .gpio_nce       = AUTCPU12_SMC_NCE,
+        .gpio_ale       = AUTCPU12_SMC_ALE,
+        .gpio_cle       = AUTCPU12_SMC_CLE,
+        .gpio_nwp       = -1,
+        .chip_delay     = 20,
+        .parts          = autcpu12_nand_parts,
+        .num_parts      = ARRAY_SIZE(autcpu12_nand_parts),
+        .adjust_parts   = autcpu12_adjust_parts,
+};
+static struct platform_device autcpu12_nand_pdev __initdata = {
+        .name           = "gpio-nand",
+        .id             = -1,
+        .resource       = autcpu12_nand_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nand_resource),
+        .dev            = {
+                .platform_data = &autcpu12_nand_pdata,
+        },
+};
+static struct resource autcpu12_mmgpio_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
+};
+static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
+        .base   = AUTCPU12_MMGPIO_BASE,
+        .ngpio  = 8,
+};
+static struct platform_device autcpu12_mmgpio_pdev __initdata = {
+        .name           = "basic-mmio-gpio",
+        .id             = -1,
+        .resource       = autcpu12_mmgpio_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_mmgpio_resource),
+        .dev            = {
+                .platform_data = &autcpu12_mmgpio_pdata,
+        },
+};
+static void __init autcpu12_init(void)
+{
+        platform_device_register_simple("video-clps711x", 0, NULL, 0);
+        platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
+                                        ARRAY_SIZE(autcpu12_cs8900_resource));
+        platform_device_register(&autcpu12_mmgpio_pdev);
+        platform_device_register(&autcpu12_nvram_pdev);
+}
+static void __init autcpu12_init_late(void)
+{
+        if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
+                /* We are need both drivers to handle NAND */
+                platform_device_register(&autcpu12_nand_pdev);
+        }
+}
+MACHINE_START(AUTCPU12, "autronix autcpu12")
+        /* Maintainer: Thomas Gleixner */
+        .atag_offset    = 0x20000,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .map_io         = clps711x_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = autcpu12_init,
+        .init_late      = autcpu12_init_late,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
new file mode 100644
index 000000000000..60900ddf97c9
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -0,0 +1,147 @@
+/*
+ *  linux/arch/arm/mach-clps711x/cdb89712.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/partitions.h>
+#include <mach/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include "common.h"
+#define CDB89712_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+#define CDB89712_CS8900_IRQ     (IRQ_EINT3)
+static struct resource cdb89712_cs8900_resource[] __initdata = {
+        DEFINE_RES_MEM(CDB89712_CS8900_BASE, SZ_1K),
+        DEFINE_RES_IRQ(CDB89712_CS8900_IRQ),
+};
+static struct mtd_partition cdb89712_flash_partitions[] __initdata = {
+        {
+                .name   = "Flash",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data cdb89712_flash_pdata __initdata = {
+        .width          = 4,
+        .probe_type     = "map_rom",
+        .parts          = cdb89712_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(cdb89712_flash_partitions),
+};
+static struct resource cdb89712_flash_resources[] __initdata = {
+        DEFINE_RES_MEM(CS0_PHYS_BASE, SZ_8M),
+};
+static struct platform_device cdb89712_flash_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = cdb89712_flash_resources,
+        .num_resources  = ARRAY_SIZE(cdb89712_flash_resources),
+        .dev    = {
+                .platform_data  = &cdb89712_flash_pdata,
+        },
+};
+static struct mtd_partition cdb89712_bootrom_partitions[] __initdata = {
+        {
+                .name   = "BootROM",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data cdb89712_bootrom_pdata __initdata = {
+        .width          = 4,
+        .probe_type     = "map_rom",
+        .parts          = cdb89712_bootrom_partitions,
+        .nr_parts       = ARRAY_SIZE(cdb89712_bootrom_partitions),
+};
+static struct resource cdb89712_bootrom_resources[] __initdata = {
+        DEFINE_RES_NAMED(CS7_PHYS_BASE, SZ_128, "BOOTROM", IORESOURCE_MEM |
+                         IORESOURCE_CACHEABLE | IORESOURCE_READONLY),
+};
+static struct platform_device cdb89712_bootrom_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 1,
+        .resource       = cdb89712_bootrom_resources,
+        .num_resources  = ARRAY_SIZE(cdb89712_bootrom_resources),
+        .dev    = {
+                .platform_data  = &cdb89712_bootrom_pdata,
+        },
+};
+static struct platdata_mtd_ram cdb89712_sram_pdata __initdata = {
+        .bankwidth      = 4,
+};
+static struct resource cdb89712_sram_resources[] __initdata = {
+        DEFINE_RES_MEM(CLPS711X_SRAM_BASE, CLPS711X_SRAM_SIZE),
+};
+static struct platform_device cdb89712_sram_pdev __initdata = {
+        .name           = "mtd-ram",
+        .id             = 0,
+        .resource       = cdb89712_sram_resources,
+        .num_resources  = ARRAY_SIZE(cdb89712_sram_resources),
+        .dev    = {
+                .platform_data  = &cdb89712_sram_pdata,
+        },
+};
+static void __init cdb89712_init(void)
+{
+        platform_device_register(&cdb89712_flash_pdev);
+        platform_device_register(&cdb89712_bootrom_pdev);
+        platform_device_register(&cdb89712_sram_pdev);
+        platform_device_register_simple("cs89x0", 0, cdb89712_cs8900_resource,
+                                        ARRAY_SIZE(cdb89712_cs8900_resource));
+}
+MACHINE_START(CDB89712, "Cirrus-CDB89712")
+        /* Maintainer: Ray Lehtiniemi */
+        .atag_offset    = 0x100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .map_io         = clps711x_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = cdb89712_init,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index dbc7842639dc..0b32a487183b 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -33,14 +33,14 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
        mi->bank[0].size = 0x01000000;
 }
 MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
        /* Maintainer: Nobody */
        .atag_offset    = 0x0100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fixup_clep7312,
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
new file mode 100644
index 000000000000..71aa5cf2c0d3
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -0,0 +1,180 @@
+/*
+ *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/memblock.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/backlight.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <asm/setup.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <video/platform_lcd.h>
+#include <mach/hardware.h>
+#include "common.h"
+#define VIDEORAM_SIZE           SZ_128K
+#define EDB7211_LCD_DC_DC_EN    CLPS711X_GPIO(3, 1)
+#define EDB7211_LCDEN           CLPS711X_GPIO(3, 2)
+#define EDB7211_LCDBL           CLPS711X_GPIO(3, 3)
+#define EDB7211_FLASH0_BASE     (CS0_PHYS_BASE)
+#define EDB7211_FLASH1_BASE     (CS1_PHYS_BASE)
+#define EDB7211_CS8900_BASE     (CS2_PHYS_BASE + 0x300)
+#define EDB7211_CS8900_IRQ      (IRQ_EINT3)
+static struct resource edb7211_cs8900_resource[] __initdata = {
+        DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
+        DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
+};
+static struct mtd_partition edb7211_flash_partitions[] __initdata = {
+        {
+                .name   = "Flash",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct physmap_flash_data edb7211_flash_pdata __initdata = {
+        .width          = 4,
+        .parts          = edb7211_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(edb7211_flash_partitions),
+};
+static struct resource edb7211_flash_resources[] __initdata = {
+        DEFINE_RES_MEM(EDB7211_FLASH0_BASE, SZ_8M),
+        DEFINE_RES_MEM(EDB7211_FLASH1_BASE, SZ_8M),
+};
+static struct platform_device edb7211_flash_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = edb7211_flash_resources,
+        .num_resources  = ARRAY_SIZE(edb7211_flash_resources),
+        .dev    = {
+                .platform_data  = &edb7211_flash_pdata,
+        },
+};
+static void edb7211_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
+{
+        if (power) {
+                gpio_set_value(EDB7211_LCDEN, 1);
+                udelay(100);
+                gpio_set_value(EDB7211_LCD_DC_DC_EN, 1);
+        } else {
+                gpio_set_value(EDB7211_LCD_DC_DC_EN, 0);
+                udelay(100);
+                gpio_set_value(EDB7211_LCDEN, 0);
+        }
+}
+static struct plat_lcd_data edb7211_lcd_power_pdata = {
+        .set_power      = edb7211_lcd_power_set,
+};
+static void edb7211_lcd_backlight_set_intensity(int intensity)
+{
+        gpio_set_value(EDB7211_LCDBL, intensity);
+}
+static struct generic_bl_info edb7211_lcd_backlight_pdata = {
+        .name                   = "lcd-backlight.0",
+        .default_intensity      = 0x01,
+        .max_intensity          = 0x01,
+        .set_bl_intensity       = edb7211_lcd_backlight_set_intensity,
+};
+static struct gpio edb7211_gpios[] __initconst = {
+        { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW,     "LCD DC-DC" },
+        { EDB7211_LCDEN,        GPIOF_OUT_INIT_LOW,     "LCD POWER" },
+        { EDB7211_LCDBL,        GPIOF_OUT_INIT_LOW,     "LCD BACKLIGHT" },
+};
+static struct map_desc edb7211_io_desc[] __initdata = {
+        {       /* Memory-mapped extra keyboard row */
+                .virtual        = IO_ADDRESS(EP7211_PHYS_EXTKBD),
+                .pfn            = __phys_to_pfn(EP7211_PHYS_EXTKBD),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE,
+        },
+};
+void __init edb7211_map_io(void)
+{
+        clps711x_map_io();
+        iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
+}
+/* Reserve screen memory region at the start of main system memory. */
+static void __init edb7211_reserve(void)
+{
+        memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
+}
+static void __init
+fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+        /*
+         * Bank start addresses are not present in the information
+         * passed in from the boot loader.  We could potentially
+         * detect them, but instead we hard-code them.
+         *
+         * Banks sizes _are_ present in the param block, but we're
+         * not using that information yet.
+         */
+        mi->bank[0].start = 0xc0000000;
+        mi->bank[0].size = SZ_8M;
+        mi->bank[1].start = 0xc1000000;
+        mi->bank[1].size = SZ_8M;
+        mi->nr_banks = 2;
+}
+static void __init edb7211_init(void)
+{
+        gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
+        platform_device_register(&edb7211_flash_pdev);
+        platform_device_register_data(&platform_bus, "platform-lcd", 0,
+                                      &edb7211_lcd_power_pdata,
+                                      sizeof(edb7211_lcd_power_pdata));
+        platform_device_register_data(&platform_bus, "generic-bl", 0,
+                                      &edb7211_lcd_backlight_pdata,
+                                      sizeof(edb7211_lcd_backlight_pdata));
+        platform_device_register_simple("video-clps711x", 0, NULL, 0);
+        platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
+                                        ARRAY_SIZE(edb7211_cs8900_resource));
+}
+MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
+        /* Maintainer: Jon McClintock */
+        .atag_offset    = VIDEORAM_SIZE + 0x100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .fixup          = fixup_edb7211,
+        .reserve        = edb7211_reserve,
+        .map_io         = edb7211_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = edb7211_init,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index 3a3f0b702cb4..7d0125580366 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -74,9 +74,11 @@ fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(FORTUNET, "ARM-FortuNet")
        /* Maintainer: FortuNet Inc. */
+        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fortunet_fixup,
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
new file mode 100644
index 000000000000..1518fc83babd
--- /dev/null
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -0,0 +1,232 @@
+/*
+ *  linux/arch/arm/mach-clps711x/p720t.c
+ *
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
+#include <linux/sizes.h>
+#include <linux/backlight.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand-gpio.h>
+#include <mach/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/syspld.h>
+#include <video/platform_lcd.h>
+#include "common.h"
+#define P720T_USERLED           CLPS711X_GPIO(3, 0)
+#define P720T_NAND_CLE          CLPS711X_GPIO(4, 0)
+#define P720T_NAND_ALE          CLPS711X_GPIO(4, 1)
+#define P720T_NAND_NCE          CLPS711X_GPIO(4, 2)
+#define P720T_NAND_BASE         (CLPS711X_SDRAM1_BASE)
+static struct resource p720t_nand_resource[] __initdata = {
+        DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
+};
+static struct mtd_partition p720t_nand_parts[] __initdata = {
+        {
+                .name   = "Flash partition 1",
+                .offset = 0,
+                .size   = SZ_2M,
+        },
+        {
+                .name   = "Flash partition 2",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct gpio_nand_platdata p720t_nand_pdata __initdata = {
+        .gpio_rdy       = -1,
+        .gpio_nce       = P720T_NAND_NCE,
+        .gpio_ale       = P720T_NAND_ALE,
+        .gpio_cle       = P720T_NAND_CLE,
+        .gpio_nwp       = -1,
+        .chip_delay     = 15,
+        .parts          = p720t_nand_parts,
+        .num_parts      = ARRAY_SIZE(p720t_nand_parts),
+};
+static struct platform_device p720t_nand_pdev __initdata = {
+        .name           = "gpio-nand",
+        .id             = -1,
+        .resource       = p720t_nand_resource,
+        .num_resources  = ARRAY_SIZE(p720t_nand_resource),
+        .dev            = {
+                .platform_data = &p720t_nand_pdata,
+        },
+};
+static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
+{
+        if (power) {
+                PLD_LCDEN = PLD_LCDEN_EN;
+                PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
+        } else {
+                PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
+                PLD_LCDEN = 0;
+        }
+}
+static struct plat_lcd_data p720t_lcd_power_pdata = {
+        .set_power      = p720t_lcd_power_set,
+};
+static void p720t_lcd_backlight_set_intensity(int intensity)
+{
+        if (intensity)
+                PLD_PWR |= PLD_S3_ON;
+        else
+                PLD_PWR = 0;
+}
+static struct generic_bl_info p720t_lcd_backlight_pdata = {
+        .name                   = "lcd-backlight.0",
+        .default_intensity      = 0x01,
+        .max_intensity          = 0x01,
+        .set_bl_intensity       = p720t_lcd_backlight_set_intensity,
+};
+/*
+ * Map the P720T system PLD. It occupies two address spaces:
+ * 0x10000000 and 0x10400000. We map both regions as one.
+ */
+static struct map_desc p720t_io_desc[] __initdata = {
+        {
+                .virtual        = SYSPLD_VIRT_BASE,
+                .pfn            = __phys_to_pfn(SYSPLD_PHYS_BASE),
+                .length         = SZ_8M,
+                .type           = MT_DEVICE,
+        },
+};
+static void __init
+fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
+{
+        /*
+         * Our bootloader doesn't setup any tags (yet).
+         */
+        if (tag->hdr.tag != ATAG_CORE) {
+                tag->hdr.tag = ATAG_CORE;
+                tag->hdr.size = tag_size(tag_core);
+                tag->u.core.flags = 0;
+                tag->u.core.pagesize = PAGE_SIZE;
+                tag->u.core.rootdev = 0x0100;
+                tag = tag_next(tag);
+                tag->hdr.tag = ATAG_MEM;
+                tag->hdr.size = tag_size(tag_mem32);
+                tag->u.mem.size = 4096;
+                tag->u.mem.start = PHYS_OFFSET;
+                tag = tag_next(tag);
+                tag->hdr.tag = ATAG_NONE;
+                tag->hdr.size = 0;
+        }
+}
+static void __init p720t_map_io(void)
+{
+        clps711x_map_io();
+        iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
+}
+static void __init p720t_init_early(void)
+{
+        /*
+         * Power down as much as possible in case we don't
+         * have the drivers loaded.
+         */
+        PLD_LCDEN = 0;
+        PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
+        PLD_KBD   = 0;
+        PLD_IO    = 0;
+        PLD_IRDA  = 0;
+        PLD_CODEC = 0;
+        PLD_TCH   = 0;
+        PLD_SPI   = 0;
+        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
+                PLD_COM2 = 0;
+                PLD_COM1 = 0;
+        }
+}
+static struct gpio_led p720t_gpio_leds[] = {
+        {
+                .name                   = "User LED",
+                .default_trigger        = "heartbeat",
+                .gpio                   = P720T_USERLED,
+        },
+};
+static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
+        .leds           = p720t_gpio_leds,
+        .num_leds       = ARRAY_SIZE(p720t_gpio_leds),
+};
+static void __init p720t_init(void)
+{
+        platform_device_register(&p720t_nand_pdev);
+        platform_device_register_data(&platform_bus, "platform-lcd", 0,
+                                      &p720t_lcd_power_pdata,
+                                      sizeof(p720t_lcd_power_pdata));
+        platform_device_register_data(&platform_bus, "generic-bl", 0,
+                                      &p720t_lcd_backlight_pdata,
+                                      sizeof(p720t_lcd_backlight_pdata));
+        platform_device_register_simple("video-clps711x", 0, NULL, 0);
+}
+static void __init p720t_init_late(void)
+{
+        platform_device_register_data(&platform_bus, "leds-gpio", 0,
+                                      &p720t_gpio_led_pdata,
+                                      sizeof(p720t_gpio_led_pdata));
+}
+MACHINE_START(P720T, "ARM-Prospector720T")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .atag_offset    = 0x100,
+        .nr_irqs        = CLPS711X_NR_IRQS,
+        .fixup          = fixup_p720t,
+        .map_io         = p720t_map_io,
+        .init_early     = p720t_init_early,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .init_machine   = p720t_init,
+        .init_late      = p720t_init_late,
+        .handle_irq     = clps711x_handle_irq,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
deleted file mode 100644
index c314f49d6ef6..000000000000
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/cdb89712.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "common.h"
-/*
- * Map the CS89712 Ethernet port.  That should be moved to the
- * ethernet driver, perhaps.
- */
-static struct map_desc cdb89712_io_desc[] __initdata = {
-        {
-                .virtual        = ETHER_BASE,
-                .pfn            =__phys_to_pfn(ETHER_START),
-                .length         = ETHER_SIZE,
-                .type           = MT_DEVICE
-        }
-};
-static void __init cdb89712_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(cdb89712_io_desc, ARRAY_SIZE(cdb89712_io_desc));
-}
-MACHINE_START(CDB89712, "Cirrus-CDB89712")
-        /* Maintainer: Ray Lehtiniemi */
-        .atag_offset    = 0x100,
-        .map_io         = cdb89712_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 509243d89a32..e046439573ee 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -21,13 +21,16 @@
 */
 #include <linux/io.h>
 #include <linux/init.h>
+#include <linux/sizes.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clockchips.h>
 #include <linux/clk-provider.h>
-#include <asm/sizes.h>
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
@@ -36,7 +39,6 @@
 static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
                  *clk_tint, *clk_spi;
-static unsigned long latch;
 /*
 * This maps the generic CLPS711x registers
@@ -45,7 +47,7 @@ static struct map_desc clps711x_io_desc[] __initdata = {
        {
                .virtual        = (unsigned long)CLPS711X_VIRT_BASE,
                .pfn            = __phys_to_pfn(CLPS711X_PHYS_BASE),
-                .length         = SZ_1M,
+                .length         = SZ_64K,
                .type           = MT_DEVICE
        }
 };
@@ -64,7 +66,7 @@ static void int1_mask(struct irq_data *d)
        clps_writel(intmr1, INTMR1);
 }
-static void int1_ack(struct irq_data *d)
+static void int1_eoi(struct irq_data *d)
 {
        switch (d->irq) {
        case IRQ_CSINT:  clps_writel(0, COEOI);  break;
@@ -86,7 +88,8 @@ static void int1_unmask(struct irq_data *d)
 }
 static struct irq_chip int1_chip = {
-        .irq_ack        = int1_ack,
+        .name           = "Interrupt Vector 1",
+        .irq_eoi        = int1_eoi,
        .irq_mask       = int1_mask,
        .irq_unmask     = int1_unmask,
 };
@@ -100,7 +103,7 @@ static void int2_mask(struct irq_data *d)
        clps_writel(intmr2, INTMR2);
 }
-static void int2_ack(struct irq_data *d)
+static void int2_eoi(struct irq_data *d)
 {
        switch (d->irq) {
        case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
@@ -117,73 +120,160 @@ static void int2_unmask(struct irq_data *d)
 }
 static struct irq_chip int2_chip = {
-        .irq_ack        = int2_ack,
+        .name           = "Interrupt Vector 2",
+        .irq_eoi        = int2_eoi,
        .irq_mask       = int2_mask,
        .irq_unmask     = int2_unmask,
 };
+static void int3_mask(struct irq_data *d)
+{
+        u32 intmr3;
+        intmr3 = clps_readl(INTMR3);
+        intmr3 &= ~(1 << (d->irq - 32));
+        clps_writel(intmr3, INTMR3);
+}
+static void int3_unmask(struct irq_data *d)
+{
+        u32 intmr3;
+        intmr3 = clps_readl(INTMR3);
+        intmr3 |= 1 << (d->irq - 32);
+        clps_writel(intmr3, INTMR3);
+}
+static struct irq_chip int3_chip = {
+        .name           = "Interrupt Vector 3",
+        .irq_mask       = int3_mask,
+        .irq_unmask     = int3_unmask,
+};
+static struct {
+        int                     nr;
+        struct irq_chip         *chip;
+        irq_flow_handler_t      handle;
+} clps711x_irqdescs[] __initdata = {
+        { IRQ_CSINT,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_EINT1,    &int1_chip,     handle_level_irq,       },
+        { IRQ_EINT2,    &int1_chip,     handle_level_irq,       },
+        { IRQ_EINT3,    &int1_chip,     handle_level_irq,       },
+        { IRQ_TC1OI,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_TC2OI,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_RTCMI,    &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_TINT,     &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_UTXINT1,  &int1_chip,     handle_level_irq,       },
+        { IRQ_URXINT1,  &int1_chip,     handle_level_irq,       },
+        { IRQ_UMSINT,   &int1_chip,     handle_fasteoi_irq,     },
+        { IRQ_SSEOTI,   &int1_chip,     handle_level_irq,       },
+        { IRQ_KBDINT,   &int2_chip,     handle_fasteoi_irq,     },
+        { IRQ_SS2RX,    &int2_chip,     handle_level_irq,       },
+        { IRQ_SS2TX,    &int2_chip,     handle_level_irq,       },
+        { IRQ_UTXINT2,  &int2_chip,     handle_level_irq,       },
+        { IRQ_URXINT2,  &int2_chip,     handle_level_irq,       },
+};
 void __init clps711x_init_irq(void)
 {
        unsigned int i;
-        for (i = 0; i < NR_IRQS; i++) {
+        /* Disable interrupts */
-                if (INT1_IRQS & (1 << i)) {
-                        irq_set_chip_and_handler(i, &int1_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                }
-                if (INT2_IRQS & (1 << i)) {
-                        irq_set_chip_and_handler(i, &int2_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-        /*
-         * Disable interrupts
-         */
        clps_writel(0, INTMR1);
        clps_writel(0, INTMR2);
+        clps_writel(0, INTMR3);
-        /*
+        /* Clear down any pending interrupts */
-         * Clear down any pending interrupts
+        clps_writel(0, BLEOI);
-         */
+        clps_writel(0, MCEOI);
        clps_writel(0, COEOI);
        clps_writel(0, TC1EOI);
        clps_writel(0, TC2EOI);
        clps_writel(0, RTCEOI);
        clps_writel(0, TEOI);
        clps_writel(0, UMSEOI);
-        clps_writel(0, SYNCIO);
        clps_writel(0, KBDEOI);
+        clps_writel(0, SRXEOF);
+        clps_writel(0xffffffff, DAISR);
+        for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
+                irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
+                                         clps711x_irqdescs[i].chip,
+                                         clps711x_irqdescs[i].handle);
+                set_irq_flags(clps711x_irqdescs[i].nr,
+                              IRQF_VALID | IRQF_PROBE);
+        }
+        if (IS_ENABLED(CONFIG_FIQ)) {
+                init_FIQ(0);
+                irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
+                                         handle_bad_irq);
+                set_irq_flags(IRQ_DAIINT,
+                              IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
+        }
 }
-/*
+inline u32 fls16(u32 x)
- * gettimeoffset() returns time since last timer tick, in usecs.
- *
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
- * 'tick' is usecs per jiffy.
- */
-static unsigned long clps711x_gettimeoffset(void)
 {
-        unsigned long hwticks;
+        u32 r = 15;
-        hwticks = latch - (clps_readl(TC2D) & 0xffff);
-        return (hwticks * (tick_nsec / 1000)) / latch;
+        if (!(x & 0xff00)) {
+                x <<= 8;
+                r -= 8;
+        }
+        if (!(x & 0xf000)) {
+                x <<= 4;
+                r -= 4;
+        }
+        if (!(x & 0xc000)) {
+                x <<= 2;
+                r -= 2;
+        }
+        if (!(x & 0x8000))
+                r--;
+        return r;
 }
-/*
+asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
- * IRQ handler for the timer
- */
-static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
 {
-        timer_tick();
+        u32 irqstat;
+        void __iomem *base = CLPS711X_VIRT_BASE;
+        irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
+        if (irqstat) {
+                handle_IRQ(fls16(irqstat), regs);
+                return;
+        }
+        irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
+        if (likely(irqstat))
+                handle_IRQ(fls16(irqstat) + 16, regs);
+}
+static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
+                                         struct clock_event_device *evt)
+{
+}
+static struct clock_event_device clockevent_clps711x = {
+        .name           = "CLPS711x Clockevents",
+        .rating         = 300,
+        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .set_mode       = clps711x_clockevent_set_mode,
+};
+static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
+{
+        clockevent_clps711x.event_handler(&clockevent_clps711x);
        return IRQ_HANDLED;
 }
 static struct irqaction clps711x_timer_irq = {
        .name           = "CLPS711x Timer Tick",
        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = p720t_timer_interrupt,
+        .handler        = clps711x_timer_interrupt,
 };
 static void add_fixed_clk(struct clk *clk, const char *name, int rate)
@@ -244,20 +334,19 @@ static void __init clps711x_timer_init(void)
        pr_info("CPU frequency set at %i Hz.\n", cpu);
-        latch = (timh + HZ / 2) / HZ;
+        clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
        tmp = clps_readl(SYSCON1);
        tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
        clps_writel(tmp, SYSCON1);
-        clps_writel(latch - 1, TC2D);
+        clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 struct sys_timer clps711x_timer = {
        .init           = clps711x_timer_init,
-        .offset         = clps711x_gettimeoffset,
 };
 void clps711x_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index fc0f0650dcb5..b7c0c75c90c0 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -4,9 +4,14 @@
 * Common bits.
 */
+#define CLPS711X_NR_IRQS        (33)
+#define CLPS711X_NR_GPIO        (4 * 8 + 3)
+#define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
 struct sys_timer;
 extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
-extern struct sys_timer clps711x_timer;
+extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(char mode, const char *cmd);
+extern struct sys_timer clps711x_timer;
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
deleted file mode 100644
index 5fad0b4f40ad..000000000000
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/arch-edb7211.c
- *
- *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/memblock.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-extern void edb7211_map_io(void);
-/* Reserve screen memory region at the start of main system memory. */
-static void __init edb7211_reserve(void)
-{
-        memblock_reserve(PHYS_OFFSET, 0x00020000);
-}
-static void __init
-fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
-{
-        /*
-         * Bank start addresses are not present in the information
-         * passed in from the boot loader.  We could potentially
-         * detect them, but instead we hard-code them.
-         *
-         * Banks sizes _are_ present in the param block, but we're
-         * not using that information yet.
-         */
-        mi->bank[0].start = 0xc0000000;
-        mi->bank[0].size = 8*1024*1024;
-        mi->bank[1].start = 0xc1000000;
-        mi->bank[1].size = 8*1024*1024;
-        mi->nr_banks = 2;
-}
-MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
-        /* Maintainer: Jon McClintock */
-        .atag_offset    = 0x20100,      /* 0xc0000000 - 0xc001ffff can be video RAM */
-        .fixup          = fixup_edb7211,
-        .map_io         = edb7211_map_io,
-        .reserve        = edb7211_reserve,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
deleted file mode 100644
index 4372f06c9929..000000000000
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/mm.c
- *
- *  Extra MM routines for the EDB7211 board
- *
- *  Copyright (C) 2000, 2001 Blue Mug, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/bug.h>
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
- 
-#include <asm/mach/map.h>
-extern void clps711x_map_io(void);
-/*
- * The on-chip registers are given a size of 1MB so that a section can
- * be used to map them; this saves a page table.  This is the place to
- * add mappings for ROM, expansion memory, PCMCIA, etc.  (if static
- * mappings are chosen for those areas).
- *
- * Here is a physical memory map (to be fleshed out later):
- *
- * Physical Address  Size  Description
- * ----------------- ----- ---------------------------------
- * c0000000-c001ffff 128KB reserved for video RAM [1]
- * c0020000-c0023fff  16KB parameters (see Documentation/arm/Setup)
- * c0024000-c0027fff  16KB swapper_pg_dir (task 0 page directory)
- * c0028000-...            kernel image (TEXTADDR)
- *
- * [1] Unused pages should be given back to the VM; they are not yet.
- *     The parameter block should also be released (not sure if this
- *     happens).
- */
-static struct map_desc edb7211_io_desc[] __initdata = {
-        {       /* memory-mapped extra keyboard row */
-                .virtual        = EP7211_VIRT_EXTKBD,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_EXTKBD),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        }, {    /* and CS8900A Ethernet chip */
-                .virtual        = EP7211_VIRT_CS8900A,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_CS8900A),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        }, {    /* flash banks */
-                .virtual        = EP7211_VIRT_FLASH1,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_FLASH1),
-                .length         = SZ_8M,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = EP7211_VIRT_FLASH2,
-                .pfn            = __phys_to_pfn(EP7211_PHYS_FLASH2),
-                .length         = SZ_8M,
-                .type           = MT_DEVICE,
-        }
-};
-void __init edb7211_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
-}
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index 1588a365f610..0452f5f3f034 100644
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
@@ -21,24 +21,15 @@
 #define __ASM_ARCH_AUTCPU12_H
 /*
- * The CS8900A ethernet chip has its I/O registers wired to chip select 2
- * (nCS2). This is the mapping for it.
- */
-#define AUTCPU12_PHYS_CS8900A           CS2_PHYS_BASE           /* physical */
-#define AUTCPU12_VIRT_CS8900A           (0xfe000000)            /* virtual */
-/*
 * The flash bank is wired to chip select 0
 */
 #define AUTCPU12_PHYS_FLASH             CS0_PHYS_BASE           /* physical */
 /* offset for device specific information structure */
 #define AUTCPU12_LCDINFO_OFFS           (0x00010000)    
-/*
-* Videomemory is the internal SRAM (CS 6)       
+/* Videomemory in the internal SRAM (CS 6) */
-*/
 #define AUTCPU12_PHYS_VIDEO             CS6_PHYS_BASE
-#define AUTCPU12_VIRT_VIDEO             (0xfd000000)
 /*
 * All special IO's are tied to CS1
@@ -49,8 +40,6 @@
 #define AUTCPU12_PHYS_CSAUX1            CS1_PHYS_BASE +0x04000000  /* physical */
-#define AUTCPU12_PHYS_SMC               CS1_PHYS_BASE +0x06000000  /* physical */
 #define AUTCPU12_PHYS_CAN               CS1_PHYS_BASE +0x08000000  /* physical */
 #define AUTCPU12_PHYS_TOUCH             CS1_PHYS_BASE +0x0A000000  /* physical */
@@ -59,14 +48,6 @@
 #define AUTCPU12_PHYS_LPT               CS1_PHYS_BASE +0x0E000000  /* physical */
-/* 
-* defines for smartmedia card access 
-*/
-#define AUTCPU12_SMC_RDY                (1<<2)
-#define AUTCPU12_SMC_ALE                (1<<3)
-#define AUTCPU12_SMC_CLE                (1<<4)
-#define AUTCPU12_SMC_PORT_OFFSET        PBDR
-#define AUTCPU12_SMC_SELECT_OFFSET      0x10
 /*
 * defines for lcd contrast 
 */
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index c82e21ca49c7..01d1b9559710 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -257,6 +257,9 @@
 #define MEMCFG_BUS_WIDTH_16     (0)
 #define MEMCFG_BUS_WIDTH_8      (3)
+#define MEMCFG_SQAEN            (1 << 6)
+#define MEMCFG_CLKENB           (1 << 7)
 #define MEMCFG_WAITSTATE_8_3    (0 << 2)
 #define MEMCFG_WAITSTATE_7_3    (1 << 2)
 #define MEMCFG_WAITSTATE_6_3    (2 << 2)
@@ -274,4 +277,28 @@
 #define MEMCFG_WAITSTATE_2_0    (14 << 2)
 #define MEMCFG_WAITSTATE_1_0    (15 << 2)
+/* INTSR1 Interrupts */
+#define IRQ_CSINT               (4)
+#define IRQ_EINT1               (5)
+#define IRQ_EINT2               (6)
+#define IRQ_EINT3               (7)
+#define IRQ_TC1OI               (8)
+#define IRQ_TC2OI               (9)
+#define IRQ_RTCMI               (10)
+#define IRQ_TINT                (11)
+#define IRQ_UTXINT1             (12)
+#define IRQ_URXINT1             (13)
+#define IRQ_UMSINT              (14)
+#define IRQ_SSEOTI              (15)
+/* INTSR2 Interrupts */
+#define IRQ_KBDINT              (16 + 0)
+#define IRQ_SS2RX               (16 + 1)
+#define IRQ_SS2TX               (16 + 2)
+#define IRQ_UTXINT2             (16 + 12)
+#define IRQ_URXINT2             (16 + 13)
+/* INTSR3 Interrupts */
+#define IRQ_DAIINT              (32 + 0)
 #endif /* __MACH_CLPS711X_H */
diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S
deleted file mode 100644
index 56e5c2c23504..000000000000
--- a/arch/arm/mach-clps711x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * arch/arm/mach-clps711x/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for CLPS711X-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
-#error INTSR stride != INTMR stride
-#endif
-                .macro  get_irqnr_and_base, irqnr, stat, base, mask
-                mov     \base, #CLPS711X_VIRT_BASE
-                ldr     \stat, [\base, #INTSR1]
-                ldr     \mask, [\base, #INTMR1]
-                mov     \irqnr, #4
-                mov     \mask, \mask, lsl #16
-                and     \stat, \stat, \mask, lsr #16
-                movs    \stat, \stat, lsr #4
-                bne     1001f
-                add     \base, \base, #INTSR2 - INTSR1
-                ldr     \stat, [\base, #INTSR1]
-                ldr     \mask, [\base, #INTMR1]
-                mov     \irqnr, #16
-                mov     \mask, \mask, lsl #16
-                and     \stat, \stat, \mask, lsr #16
-1001:           tst     \stat, #255
-                addeq   \irqnr, \irqnr, #8
-                moveq   \stat, \stat, lsr #8
-                tst     \stat, #15
-                addeq   \irqnr, \irqnr, #4
-                moveq   \stat, \stat, lsr #4
-                tst     \stat, #3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \stat, \stat, lsr #2
-                tst     \stat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \stat, \stat, lsr #1
-                tst     \stat, #1                       @ bit 0 should be set
-                .endm
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 8497775d6ee5..2f23dd5d73e4 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -24,7 +24,10 @@
 #include <mach/clps711x.h>
-#define CLPS711X_VIRT_BASE      IOMEM(0xff000000)
+#define IO_ADDRESS(x)           (0xdc000000 + (((x) & 0x03ffffff) | \
+                                (((x) >> 2) & 0x3c000000)))
+#define CLPS711X_VIRT_BASE      IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE))
 #ifndef __ASSEMBLY__
 #define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))
@@ -61,67 +64,17 @@
 #define CS7_PHYS_BASE           (0x00000000)
 #endif
-#define SYSPLD_VIRT_BASE        0xfe000000
+#define CLPS711X_SRAM_BASE      CS6_PHYS_BASE
-#define SYSPLD_BASE             SYSPLD_VIRT_BASE
+#define CLPS711X_SRAM_SIZE      (48 * 1024)
-#if defined (CONFIG_ARCH_CDB89712)
-#define ETHER_START      0x20000000
-#define ETHER_SIZE       0x1000
-#define ETHER_BASE       0xfe000000
-#endif
+#define CLPS711X_SDRAM0_BASE    (0xc0000000)
+#define CLPS711X_SDRAM1_BASE    (0xd0000000)
 #if defined (CONFIG_ARCH_EDB7211)
-/*
+/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
- * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 
+#define EP7211_PHYS_EXTKBD      CS3_PHYS_BASE
- * and repeat across it. This is the mapping for it.
- *
- * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This 
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_EXTKBD              CS3_PHYS_BASE   /* physical */
-#define EP7211_VIRT_EXTKBD              (0xfd000000)    /* virtual */
-/*
- * The CS8900A ethernet chip has its I/O registers wired to chip select 2 
- * (nCS2). This is the mapping for it.
- *
- * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This 
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_CS8900A             CS2_PHYS_BASE   /* physical */
-#define EP7211_VIRT_CS8900A             (0xfc000000)    /* virtual */
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define EP7211_PHYS_FLASH1              CS0_PHYS_BASE   /* physical */
-#define EP7211_PHYS_FLASH2              CS1_PHYS_BASE   /* physical */
-#define EP7211_VIRT_FLASH1              (0xfa000000)    /* virtual */
-#define EP7211_VIRT_FLASH2              (0xfb000000)    /* virtual */
 #endif /* CONFIG_ARCH_EDB7211 */
-/*
- * Relevant bits in port D, which controls power to the various parts of
- * the LCD on the EDB7211.
- */
-#define EDB_PD1_LCD_DC_DC_EN    (1<<1)
-#define EDB_PD2_LCDEN           (1<<2)
-#define EDB_PD3_LCDBL           (1<<3)
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h
deleted file mode 100644
index 14d215f8ca81..000000000000
--- a/arch/arm/mach-clps711x/include/mach/irqs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/irqs.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * Interrupts from INTSR1
- */
-#define IRQ_CSINT                       4
-#define IRQ_EINT1                       5
-#define IRQ_EINT2                       6
-#define IRQ_EINT3                       7
-#define IRQ_TC1OI                       8
-#define IRQ_TC2OI                       9
-#define IRQ_RTCMI                       10
-#define IRQ_TINT                        11
-#define IRQ_UTXINT1                     12
-#define IRQ_URXINT1                     13
-#define IRQ_UMSINT                      14
-#define IRQ_SSEOTI                      15
-#define INT1_IRQS                       (0x0000fff0)
-/*
- * Interrupts from INTSR2
- */
-#define IRQ_KBDINT                      (16+0)  /* bit 0 */
-#define IRQ_SS2RX                       (16+1)  /* bit 1 */
-#define IRQ_SS2TX                       (16+2)  /* bit 2 */
-#define IRQ_UTXINT2                     (16+12) /* bit 12 */
-#define IRQ_URXINT2                     (16+13) /* bit 13 */
-#define INT2_IRQS                       (0x30070000)
-#define NR_IRQS                         30
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
index f7f4c1201898..9a433155bf58 100644
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ b/arch/arm/mach-clps711x/include/mach/syspld.h
@@ -23,14 +23,9 @@
 #define __ASM_ARCH_SYSPLD_H
 #define SYSPLD_PHYS_BASE        (0x10000000)
+#define SYSPLD_VIRT_BASE        IO_ADDRESS(SYSPLD_PHYS_BASE)
-#ifndef __ASSEMBLY__
+#define SYSPLD_REG(type, off)   (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
-#include <asm/types.h>
-#define SYSPLD_REG(type,off)    (*(volatile type *)(SYSPLD_BASE + off))
-#else
-#define SYSPLD_REG(type,off)    (off)
-#endif
 #define PLD_INT         SYSPLD_REG(u32, 0x000000)
 #define PLD_INT_PENIRQ          (1 << 5)
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
deleted file mode 100644
index b752b586fc2f..000000000000
--- a/arch/arm/mach-clps711x/p720t.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/p720t.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <asm/sizes.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/syspld.h>
-#include <asm/hardware/clps7111.h>
-#include "common.h"
-/*
- * Map the P720T system PLD.  It occupies two address spaces:
- *  SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000
- * We map both here.
- */
-static struct map_desc p720t_io_desc[] __initdata = {
-        {
-                .virtual        = SYSPLD_VIRT_BASE,
-                .pfn            = __phys_to_pfn(SYSPLD_PHYS_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = 0xfe400000,
-                .pfn            = __phys_to_pfn(0x10400000),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }
-};
-static void __init
-fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
-{
-        /*
-         * Our bootloader doesn't setup any tags (yet).
-         */
-        if (tag->hdr.tag != ATAG_CORE) {
-                tag->hdr.tag = ATAG_CORE;
-                tag->hdr.size = tag_size(tag_core);
-                tag->u.core.flags = 0;
-                tag->u.core.pagesize = PAGE_SIZE;
-                tag->u.core.rootdev = 0x0100;
-                tag = tag_next(tag);
-                tag->hdr.tag = ATAG_MEM;
-                tag->hdr.size = tag_size(tag_mem32);
-                tag->u.mem.size = 4096;
-                tag->u.mem.start = PHYS_OFFSET;
-                tag = tag_next(tag);
-                tag->hdr.tag = ATAG_NONE;
-                tag->hdr.size = 0;
-        }
-}
-static void __init p720t_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
-}
-static void __init p720t_init_early(void)
-{
-        /*
-         * Power down as much as possible in case we don't
-         * have the drivers loaded.
-         */
-        PLD_LCDEN = 0;
-        PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-        PLD_KBD   = 0;
-        PLD_IO    = 0;
-        PLD_IRDA  = 0;
-        PLD_CODEC = 0;
-        PLD_TCH   = 0;
-        PLD_SPI   = 0;
-        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
-                PLD_COM2 = 0;
-                PLD_COM1 = 0;
-        }
-}
-/*
- * LED controled by CPLD
- */
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-static void p720t_led_set(struct led_classdev *cdev,
-                              enum led_brightness b)
-{
-        u8 reg = clps_readb(PDDR);
-        if (b != LED_OFF)
-                reg |= 0x1;
-        else
-                reg &= ~0x1;
-        clps_writeb(reg, PDDR);
-}
-static enum led_brightness p720t_led_get(struct led_classdev *cdev)
-{
-        u8 reg = clps_readb(PDDR);
-        return (reg & 0x1) ? LED_FULL : LED_OFF;
-}
-static int __init p720t_leds_init(void)
-{
-        struct led_classdev *cdev;
-        int ret;
-        if (!machine_is_p720t())
-                return -ENODEV;
-        cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
-        if (!cdev)
-                return -ENOMEM;
-        cdev->name = "p720t:0";
-        cdev->brightness_set = p720t_led_set;
-        cdev->brightness_get = p720t_led_get;
-        cdev->default_trigger = "heartbeat";
-        ret = led_classdev_register(NULL, cdev);
-        if (ret < 0) {
-                kfree(cdev);
-                return ret;
-        }
-        return 0;
-}
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(p720t_leds_init);
-#endif
-MACHINE_START(P720T, "ARM-Prospector720T")
-        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .atag_offset    = 0x100,
-        .fixup          = fixup_p720t,
-        .init_early     = p720t_init_early,
-        .map_io         = p720t_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 29b13f249aa9..9ebfcc46feb1 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -3,7 +3,6 @@ menu "CNS3XXX platform type"
 config MACH_CNS3420VB
        bool "Support for CNS3420 Validation Board"
-        select MIGHT_HAVE_PCI
        help
          Include support for the Cavium Networks CNS3420 MPCore Platform
          Baseboard.
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2c5fb4c7e509..ae305397003c 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -24,6 +24,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/gic.h>
@@ -32,6 +34,7 @@
 #include <asm/mach/time.h>
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
+#include <mach/pm.h>
 #include "core.h"
 #include "devices.h"
@@ -125,13 +128,52 @@ static struct resource cns3xxx_usb_ehci_resources[] = {
 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
+static int csn3xxx_usb_power_on(struct platform_device *pdev)
+{
+        /*
+         * EHCI and OHCI share the same clock and power,
+         * resetting twice would cause the 1st controller been reset.
+         * Therefore only do power up  at the first up device, and
+         * power down at the last down device.
+         *
+         * Set USB AHB INCR length to 16
+         */
+        if (atomic_inc_return(&usb_pwr_ref) == 1) {
+                cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
+                cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+                cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
+                __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
+                        MISC_CHIP_CONFIG_REG);
+        }
+        return 0;
+}
+static void csn3xxx_usb_power_off(struct platform_device *pdev)
+{
+        /*
+         * EHCI and OHCI share the same clock and power,
+         * resetting twice would cause the 1st controller been reset.
+         * Therefore only do power up  at the first up device, and
+         * power down at the last down device.
+         */
+        if (atomic_dec_return(&usb_pwr_ref) == 0)
+                cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+}
+static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
+        .power_on       = csn3xxx_usb_power_on,
+        .power_off      = csn3xxx_usb_power_off,
+};
 static struct platform_device cns3xxx_usb_ehci_device = {
-        .name          = "cns3xxx-ehci",
+        .name          = "ehci-platform",
        .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
        .resource      = cns3xxx_usb_ehci_resources,
        .dev           = {
                .dma_mask          = &cns3xxx_usb_ehci_dma_mask,
                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data     = &cns3xxx_usb_ehci_pdata,
        },
 };
@@ -149,13 +191,20 @@ static struct resource cns3xxx_usb_ohci_resources[] = {
 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
+static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
+        .num_ports      = 1,
+        .power_on       = csn3xxx_usb_power_on,
+        .power_off      = csn3xxx_usb_power_off,
+};
 static struct platform_device cns3xxx_usb_ohci_device = {
-        .name          = "cns3xxx-ohci",
+        .name          = "ohci-platform",
        .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
        .resource      = cns3xxx_usb_ohci_resources,
        .dev           = {
                .dma_mask          = &cns3xxx_usb_ohci_dma_mask,
                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data     = &cns3xxx_usb_ohci_pdata,
        },
 };
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index f8eecb959413..0153950f6068 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -58,6 +58,14 @@ config ARCH_DAVINCI_TNETV107X
 comment "DaVinci Board Type"
+config MACH_DA8XX_DT
+        bool "Support DA8XX platforms using device tree"
+        default y
+        depends on ARCH_DAVINCI_DA8XX
+        help
+          Say y here to include support for TI DaVinci DA850 based using
+          Flattened Device Tree. More information at Documentation/devicetree
 config MACH_DAVINCI_EVM
        bool "TI DM644x EVM"
        default ARCH_DAVINCI_DM644x
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2227effcb0e9..fb5c1aa98a63 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)                   += cp_intc.o
 # Board specific
+obj-$(CONFIG_MACH_DA8XX_DT)             += da8xx-dt.o
 obj-$(CONFIG_MACH_DAVINCI_EVM)          += board-dm644x-evm.o
 obj-$(CONFIG_MACH_SFFSDR)               += board-sffsdr.o
 obj-$(CONFIG_MACH_NEUROS_OSD2)          += board-neuros-osd2.o
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 32ee3f895967..7211772edd9d 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -11,39 +11,40 @@
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/input.h>
+#include <linux/input/tps6507x-ts.h>
 #include <linux/mfd/tps6507x.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
+#include <linux/platform_data/spi-davinci.h>
+#include <linux/platform_data/uio_pruss.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/tps6507x.h>
-#include <linux/input/tps6507x-ts.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#include <linux/delay.h>
 #include <linux/wl12xx.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/system_info.h>
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
-#include <linux/platform_data/mtd-davinci.h>
 #include <mach/mux.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/spi-davinci.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/system_info.h>
 #include <media/tvp514x.h>
 #include <media/adv7343.h>
@@ -762,16 +763,19 @@ static u8 da850_iis_serializer_direction[] = {
 };
 static struct snd_platform_data da850_evm_snd_data = {
-        .tx_dma_offset  = 0x2000,
+        .tx_dma_offset          = 0x2000,
-        .rx_dma_offset  = 0x2000,
+        .rx_dma_offset          = 0x2000,
-        .op_mode        = DAVINCI_MCASP_IIS_MODE,
+        .op_mode                = DAVINCI_MCASP_IIS_MODE,
-        .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
+        .num_serializer         = ARRAY_SIZE(da850_iis_serializer_direction),
-        .tdm_slots      = 2,
+        .tdm_slots              = 2,
-        .serial_dir     = da850_iis_serializer_direction,
+        .serial_dir             = da850_iis_serializer_direction,
-        .asp_chan_q     = EVENTQ_0,
+        .asp_chan_q             = EVENTQ_0,
-        .version        = MCASP_VERSION_2,
+        .ram_chan_q             = EVENTQ_1,
-        .txnumevt       = 1,
+        .version                = MCASP_VERSION_2,
-        .rxnumevt       = 1,
+        .txnumevt               = 1,
+        .rxnumevt               = 1,
+        .sram_size_playback     = SZ_8K,
+        .sram_size_capture      = SZ_8K,
 };
 static const short da850_evm_mcasp_pins[] __initconst = {
@@ -1509,6 +1513,7 @@ static __init void da850_evm_init(void)
                pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
                                ret);
+        da850_evm_snd_data.sram_pool = sram_get_gen_pool();
        da8xx_register_mcasp(0, &da850_evm_snd_data);
        ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
@@ -1516,6 +1521,11 @@ static __init void da850_evm_init(void)
                pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
                                ret);
+        ret = da8xx_register_uio_pruss();
+        if (ret)
+                pr_warn("da850_evm_init: pruss initialization failed: %d\n",
+                                ret);
        /* Handle board specific muxing for LCD here */
        ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
        if (ret)
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 88ebea89abdf..cdf8d0746e79 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
        if (IS_ERR(aemif))
                WARN("%s: unable to get AEMIF clock\n", __func__);
        else
-                clk_enable(aemif);
+                clk_prepare_enable(aemif);
        platform_add_devices(davinci_evm_devices,
                             ARRAY_SIZE(davinci_evm_devices));
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 2f88103c6459..d41954507fc2 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
        if (IS_ERR(aemif))
                WARN("%s: unable to get AEMIF clock\n", __func__);
        else
-                clk_enable(aemif);
+                clk_prepare_enable(aemif);
        platform_add_devices(davinci_leopard_devices,
                             ARRAY_SIZE(davinci_leopard_devices));
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 1b4a8adcfdc9..5d49c75388ca 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -478,7 +478,7 @@ static void __init evm_init_cpld(void)
        aemif_clk = clk_get(NULL, "aemif");
        if (IS_ERR(aemif_clk))
                return;
-        clk_enable(aemif_clk);
+        clk_prepare_enable(aemif_clk);
        if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
                        "cpld") == NULL)
@@ -489,7 +489,7 @@ static void __init evm_init_cpld(void)
                                SECTION_SIZE);
 fail:
                pr_err("ERROR: can't map CPLD\n");
-                clk_disable(aemif_clk);
+                clk_disable_unprepare(aemif_clk);
                return;
        }
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index f22572cee49d..f5e018de7fa5 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -519,13 +519,11 @@ static int dm6444evm_msp430_get_pins(void)
        char buf[4];
        struct i2c_msg msg[2] = {
                {
-                        .addr = dm6446evm_msp->addr,
                        .flags = 0,
                        .len = 2,
                        .buf = (void __force *)txbuf,
                },
                {
-                        .addr = dm6446evm_msp->addr,
                        .flags = I2C_M_RD,
                        .len = 4,
                        .buf = buf,
@@ -536,6 +534,9 @@ static int dm6444evm_msp430_get_pins(void)
        if (!dm6446evm_msp)
                return -ENXIO;
+        msg[0].addr = dm6446evm_msp->addr;
+        msg[1].addr = dm6446evm_msp->addr;
        /* Command 4 == get input state, returns port 2 and port3 data
         *   S Addr W [A] len=2 [A] cmd=4 [A]
         *   RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
@@ -776,7 +777,7 @@ static __init void davinci_evm_init(void)
        struct davinci_soc_info *soc_info = &davinci_soc_info;
        aemif_clk = clk_get(NULL, "aemif");
-        clk_enable(aemif_clk);
+        clk_prepare_enable(aemif_clk);
        if (HAS_ATA) {
                if (HAS_NAND || HAS_NOR)
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 1dbf85beed1b..9211e8800c79 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -194,7 +194,7 @@ static int evm_led_setup(struct i2c_client *client, int gpio,
        while (ngpio--) {
                leds->gpio = gpio++;
                leds++;
-        };
+        }
        evm_led_dev = platform_device_alloc("leds-gpio", 0);
        platform_device_add_data(evm_led_dev, &evm_led_data,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 144bf31d68dd..3e3e3afebf88 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -188,7 +188,7 @@ static __init void davinci_ntosd2_init(void)
        struct davinci_soc_info *soc_info = &davinci_soc_info;
        aemif_clk = clk_get(NULL, "aemif");
-        clk_enable(aemif_clk);
+        clk_prepare_enable(aemif_clk);
        if (HAS_ATA) {
                if (HAS_NAND)
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 64b0f65a8639..a794f6d9d444 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -87,8 +87,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
                iotable_init(davinci_soc_info.io_desc,
                                davinci_soc_info.io_desc_num);
-        init_consistent_dma_size(14 << 20);
        /*
         * Normally devicemaps_init() would flush caches and tlb after
         * mdesc->map_io(), but we must also do it here because of the CPU
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b90c172d5541..68c5fe01857c 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -212,6 +212,12 @@ static struct clk tptc2_clk = {
        .flags          = ALWAYS_ENABLED,
 };
+static struct clk pruss_clk = {
+        .name           = "pruss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_PRUSS,
+};
 static struct clk uart0_clk = {
        .name           = "uart0",
        .parent         = &pll0_sysclk2,
@@ -385,6 +391,7 @@ static struct clk_lookup da850_clks[] = {
        CLK(NULL,               "tptc1",        &tptc1_clk),
        CLK(NULL,               "tpcc1",        &tpcc1_clk),
        CLK(NULL,               "tptc2",        &tptc2_clk),
+        CLK("pruss_uio",        "pruss",        &pruss_clk),
        CLK(NULL,               "uart0",        &uart0_clk),
        CLK(NULL,               "uart1",        &uart1_clk),
        CLK(NULL,               "uart2",        &uart2_clk),
@@ -781,12 +788,6 @@ static struct map_desc da850_io_desc[] = {
                .length         = DA8XX_CP_INTC_SIZE,
                .type           = MT_DEVICE
        },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
-                .length         = SZ_8K,
-                .type           = MT_DEVICE
-        },
 };
 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
@@ -1239,8 +1240,8 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
        .gpio_irq               = IRQ_DA8XX_GPIO0,
        .serial_dev             = &da8xx_serial_device,
        .emac_pdata             = &da8xx_emac_pdata,
-        .sram_dma               = DA8XX_ARM_RAM_BASE,
+        .sram_dma               = DA8XX_SHARED_RAM_BASE,
-        .sram_len               = SZ_8K,
+        .sram_len               = SZ_128K,
 };
 void __init da850_init(void)
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
new file mode 100644
index 000000000000..37c27af18fa0
--- /dev/null
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Modified from mach-omap/omap2/board-generic.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/arch.h>
+#include <mach/common.h>
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+#define DA8XX_NUM_UARTS 3
+void __init da8xx_uart_clk_enable(void)
+{
+        int i;
+        for (i = 0; i < DA8XX_NUM_UARTS; i++)
+                davinci_serial_setup_clk(i, NULL);
+}
+static struct of_device_id da8xx_irq_match[] __initdata = {
+        { .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
+        { }
+};
+static void __init da8xx_init_irq(void)
+{
+        of_irq_init(da8xx_irq_match);
+}
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+static void __init da850_init_machine(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        da8xx_uart_clk_enable();
+}
+static const char *da850_boards_compat[] __initdata = {
+        "enbw,cmc",
+        "ti,da850-evm",
+        "ti,da850",
+        NULL,
+};
+DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
+        .map_io         = da850_init,
+        .init_irq       = da8xx_init_irq,
+        .timer          = &davinci_timer,
+        .init_machine   = da850_init_machine,
+        .dt_compat      = da850_boards_compat,
+        .init_late      = davinci_init_late,
+        .restart        = da8xx_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bd2f72b414bc..46c9a0c09ae5 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -22,6 +22,7 @@
 #include <mach/time.h>
 #include <mach/da8xx.h>
 #include <mach/cpuidle.h>
+#include <mach/sram.h>
 #include "clock.h"
 #include "asp.h"
@@ -32,6 +33,7 @@
 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
 #define DA8XX_I2C0_BASE                 0x01c22000
 #define DA8XX_RTC_BASE                  0x01c23000
+#define DA8XX_PRUSS_MEM_BASE            0x01c30000
 #define DA8XX_MMCSD0_BASE               0x01c40000
 #define DA8XX_SPI0_BASE                 0x01c41000
 #define DA830_SPI1_BASE                 0x01e12000
@@ -518,6 +520,75 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
        }
 }
+static struct resource da8xx_pruss_resources[] = {
+        {
+                .start  = DA8XX_PRUSS_MEM_BASE,
+                .end    = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT0,
+                .end    = IRQ_DA8XX_EVTOUT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT1,
+                .end    = IRQ_DA8XX_EVTOUT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT2,
+                .end    = IRQ_DA8XX_EVTOUT2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT3,
+                .end    = IRQ_DA8XX_EVTOUT3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT4,
+                .end    = IRQ_DA8XX_EVTOUT4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT5,
+                .end    = IRQ_DA8XX_EVTOUT5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT6,
+                .end    = IRQ_DA8XX_EVTOUT6,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_EVTOUT7,
+                .end    = IRQ_DA8XX_EVTOUT7,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
+        .pintc_base     = 0x4000,
+};
+static struct platform_device da8xx_uio_pruss_dev = {
+        .name           = "pruss_uio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(da8xx_pruss_resources),
+        .resource       = da8xx_pruss_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &da8xx_uio_pruss_pdata,
+        }
+};
+int __init da8xx_register_uio_pruss(void)
+{
+        da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
+        return platform_device_register(&da8xx_uio_pruss_dev);
+}
 static const struct display_panel disp_panel = {
        QVGA,
        16,
@@ -900,7 +971,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
        if (IS_ERR(da850_sata_clk))
                return PTR_ERR(da850_sata_clk);
-        ret = clk_enable(da850_sata_clk);
+        ret = clk_prepare_enable(da850_sata_clk);
        if (ret)
                goto err0;
@@ -931,7 +1002,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
        return 0;
 err1:
-        clk_disable(da850_sata_clk);
+        clk_disable_unprepare(da850_sata_clk);
 err0:
        clk_put(da850_sata_clk);
        return ret;
@@ -939,7 +1010,7 @@ err0:
 static void da850_sata_exit(struct device *dev)
 {
-        clk_disable(da850_sata_clk);
+        clk_disable_unprepare(da850_sata_clk);
        clk_put(da850_sata_clk);
 }
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 29b17f7d3a5f..773ab07a71a0 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -374,7 +374,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
         * complete sample conversion in time.
         */
        tsc_clk = clk_get(NULL, "sys_tsc_clk");
-        if (tsc_clk) {
+        if (!IS_ERR(tsc_clk)) {
                error = clk_set_rate(tsc_clk, 5000000);
                WARN_ON(error < 0);
                clk_put(tsc_clk);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a255434908db..b49c3b77d55e 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -758,12 +758,6 @@ static struct map_desc dm355_io_desc[] = {
                .length         = IO_SIZE,
                .type           = MT_DEVICE
        },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00010000),
-                .length         = SZ_32K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 /* Contents of JTAG ID register used to identify exact cpu type */
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index b680c832e0ba..6c3980540be0 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -985,12 +985,6 @@ static struct map_desc dm365_io_desc[] = {
                .length         = IO_SIZE,
                .type           = MT_DEVICE
        },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00010000),
-                .length         = SZ_32K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 static struct resource dm365_ks_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 14e9947bad6e..11c79a3362ef 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -785,12 +785,6 @@ static struct map_desc dm644x_io_desc[] = {
                .length         = IO_SIZE,
                .type           = MT_DEVICE
        },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00008000),
-                .length         = SZ_16K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 /* Contents of JTAG ID register used to identify exact cpu type */
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 97c0f8e555bd..ac7b431c4c8e 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -756,12 +756,6 @@ static struct map_desc dm646x_io_desc[] = {
                .length         = IO_SIZE,
                .type           = MT_DEVICE
        },
-        {
-                .virtual        = SRAM_VIRT,
-                .pfn            = __phys_to_pfn(0x00010000),
-                .length         = SZ_32K,
-                .type           = MT_MEMORY_NONCACHED,
-        },
 };
 /* Contents of JTAG ID register used to identify exact cpu type */
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index bdc4aa8e672a..046c7238a3d6 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -104,8 +104,6 @@ int davinci_pm_init(void);
 static inline int davinci_pm_init(void) { return 0; }
 #endif
-/* standard place to map on-chip SRAMs; they *may* support DMA */
-#define SRAM_VIRT       0xfffe0000
 #define SRAM_SIZE       SZ_128K
 #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index aaccdc4528fc..700d311c6854 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -26,6 +26,7 @@
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
 #include <linux/platform_data/spi-davinci.h>
+#include <linux/platform_data/uio_pruss.h>
 #include <media/davinci/vpif_types.h>
@@ -72,6 +73,7 @@ extern unsigned int da850_max_speed;
 #define DA8XX_AEMIF_CS2_BASE    0x60000000
 #define DA8XX_AEMIF_CS3_BASE    0x62000000
 #define DA8XX_AEMIF_CTL_BASE    0x68000000
+#define DA8XX_SHARED_RAM_BASE   0x80000000
 #define DA8XX_ARM_RAM_BASE      0xffff0000
 void __init da830_init(void);
@@ -86,6 +88,7 @@ int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
 int da8xx_register_emac(void);
+int da8xx_register_uio_pruss(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
 int da850_register_mmcsd1(struct davinci_mmc_config *config);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 46b3cd11c3c2..62ad300440f5 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -38,11 +38,12 @@
 #ifndef __ASSEMBLY__
 struct davinci_uart_config {
-        /* Bit field of UARTs present; bit 0 --> UART1 */
+        /* Bit field of UARTs present; bit 0 --> UART0 */
        unsigned int enabled_uarts;
 };
 extern int davinci_serial_init(struct davinci_uart_config *);
+extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate);
 #endif
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h
index 111f7cc71e07..4e5db56218b8 100644
--- a/arch/arm/mach-davinci/include/mach/sram.h
+++ b/arch/arm/mach-davinci/include/mach/sram.h
@@ -24,4 +24,7 @@
 extern void *sram_alloc(size_t len, dma_addr_t *dma);
 extern void sram_free(void *addr, size_t len);
+/* Get the struct gen_pool * for use in platform data */
+extern struct gen_pool *sram_get_gen_pool(void);
 #endif /* __MACH_SRAM_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 18cfd4977155..3a0ff905a69b 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -32,6 +32,9 @@ u32 *uart;
 /* PORT_16C550A, in polled non-fifo mode */
 static void putc(char c)
 {
+        if (!uart)
+                return;
        while (!(uart[UART_LSR] & UART_LSR_THRE))
                barrier();
        uart[UART_TX] = c;
@@ -39,6 +42,9 @@ static void putc(char c)
 static inline void flush(void)
 {
+        if (!uart)
+                return;
        while (!(uart[UART_LSR] & UART_LSR_THRE))
                barrier();
 }
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 1875740fe27c..f2625814c3c9 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -70,11 +70,33 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
                                 UART_DM646X_SCR_TX_WATERMARK);
 }
-int __init davinci_serial_init(struct davinci_uart_config *info)
+/* Enable UART clock and obtain its rate */
+int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
 {
-        int i;
        char name[16];
-        struct clk *uart_clk;
+        struct clk *clk;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        struct device *dev = &soc_info->serial_dev->dev;
+        sprintf(name, "uart%d", instance);
+        clk = clk_get(dev, name);
+        if (IS_ERR(clk)) {
+                pr_err("%s:%d: failed to get UART%d clock\n",
+                                        __func__, __LINE__, instance);
+                return PTR_ERR(clk);
+        }
+        clk_prepare_enable(clk);
+        if (rate)
+                *rate = clk_get_rate(clk);
+        return 0;
+}
+int __init davinci_serial_init(struct davinci_uart_config *info)
+{
+        int i, ret;
        struct davinci_soc_info *soc_info = &davinci_soc_info;
        struct device *dev = &soc_info->serial_dev->dev;
        struct plat_serial8250_port *p = dev->platform_data;
@@ -87,16 +109,9 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
                if (!(info->enabled_uarts & (1 << i)))
                        continue;
-                sprintf(name, "uart%d", i);
+                ret = davinci_serial_setup_clk(i, &p->uartclk);
-                uart_clk = clk_get(dev, name);
+                if (ret)
-                if (IS_ERR(uart_clk)) {
-                        printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
-                                        __func__, __LINE__, i);
                        continue;
-                }
-                clk_enable(uart_clk);
-                p->uartclk = clk_get_rate(uart_clk);
                if (!p->membase && p->mapbase) {
                        p->membase = ioremap(p->mapbase, SZ_4K);
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index db0f7787faf1..c5f7ee5cc80a 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -10,6 +10,7 @@
 */
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/genalloc.h>
 #include <mach/common.h>
@@ -17,6 +18,11 @@
 static struct gen_pool *sram_pool;
+struct gen_pool *sram_get_gen_pool(void)
+{
+        return sram_pool;
+}
 void *sram_alloc(size_t len, dma_addr_t *dma)
 {
        unsigned long vaddr;
@@ -32,7 +38,7 @@ void *sram_alloc(size_t len, dma_addr_t *dma)
                return NULL;
        if (dma)
-                *dma = dma_base + (vaddr - SRAM_VIRT);
+                *dma = gen_pool_virt_to_phys(sram_pool, vaddr);
        return (void *)vaddr;
 }
@@ -53,8 +59,10 @@ EXPORT_SYMBOL(sram_free);
 */
 static int __init sram_init(void)
 {
+        phys_addr_t phys = davinci_soc_info.sram_dma;
        unsigned len = davinci_soc_info.sram_len;
        int status = 0;
+        void *addr;
        if (len) {
                len = min_t(unsigned, len, SRAM_SIZE);
@@ -62,8 +70,17 @@ static int __init sram_init(void)
                if (!sram_pool)
                        status = -ENOMEM;
        }
-        if (sram_pool)
-                status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1);
+        if (sram_pool) {
+                addr = ioremap(phys, len);
+                if (!addr)
+                        return -ENOMEM;
+                status = gen_pool_add_virt(sram_pool, (unsigned)addr,
+                                           phys, len, -1);
+                if (status < 0)
+                        iounmap(addr);
+        }
        WARN_ON(status < 0);
        return status;
 }
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 75da315b6587..9847938785ca 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
        timer_clk = clk_get(NULL, "timer0");
        BUG_ON(IS_ERR(timer_clk));
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
        /* init timer hw */
        timer_init();
@@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
        wd_clk = clk_get(&pdev->dev, NULL);
        if (WARN_ON(IS_ERR(wd_clk)))
                return;
-        clk_enable(wd_clk);
+        clk_prepare_enable(wd_clk);
        /* disable, internal clock source */
        __raw_writel(0, base + TCR);
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index f77b95336e2b..34509ffba221 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -42,14 +42,8 @@ static struct musb_hdrc_config musb_config = {
 };
 static struct musb_hdrc_platform_data usb_data = {
-#if defined(CONFIG_USB_MUSB_OTG)
        /* OTG requires a Mini-AB connector */
        .mode           = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
-        .mode           = MUSB_PERIPHERAL,
-#elif defined(CONFIG_USB_MUSB_HOST)
-        .mode           = MUSB_HOST,
-#endif
        .clock          = "usb",
        .config         = &musb_config,
 };
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 7bcd0dfce4b1..b47f75038686 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -63,7 +63,7 @@ static inline int pmu_to_irq(int pin)
 static inline int irq_to_pmu(int irq)
 {
-        if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)
+        if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS)
                return irq - IRQ_DOVE_PMU_START;
        return -EINVAL;
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 087711524e8a..bc4344aa1009 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -46,8 +46,20 @@ static void pmu_irq_ack(struct irq_data *d)
        int pin = irq_to_pmu(d->irq);
        u32 u;
+        /*
+         * The PMU mask register is not RW0C: it is RW.  This means that
+         * the bits take whatever value is written to them; if you write
+         * a '1', you will set the interrupt.
+         *
+         * Unfortunately this means there is NO race free way to clear
+         * these interrupts.
+         *
+         * So, let's structure the code so that the window is as small as
+         * possible.
+         */
        u = ~(1 << (pin & 31));
-        writel(u, PMU_INTERRUPT_CAUSE);
+        u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
+        writel_relaxed(u, PMU_INTERRUPT_CAUSE);
 }
 static struct irq_chip pmu_irq_chip = {
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index da55107033dd..91d5b6f1d5af 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,10 +63,20 @@ config SOC_EXYNOS5250
        depends on ARCH_EXYNOS5
        select S5P_PM if PM
        select S5P_SLEEP if PM
+        select S5P_DEV_MFC
        select SAMSUNG_DMADEV
        help
          Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5440
+        bool "SAMSUNG EXYNOS5440"
+        default y
+        depends on ARCH_EXYNOS5
+        select ARM_ARCH_TIMER
+        select AUTO_ZRELADDR
+        help
+          Enable EXYNOS5440 SoC support
 config EXYNOS4_MCT
        bool
        default y
@@ -98,11 +108,6 @@ config EXYNOS_DEV_SYSMMU
        help
          Common setup code for SYSTEM MMU in EXYNOS platforms
-config EXYNOS4_DEV_DWMCI
-        bool
-        help
-          Compile in platform device definitions for DWMCI
 config EXYNOS4_DEV_USB_OHCI
        bool
        help
@@ -417,9 +422,9 @@ config MACH_EXYNOS4_DT
 config MACH_EXYNOS5_DT
        bool "SAMSUNG EXYNOS5 Machine using device tree"
+        default y
        depends on ARCH_EXYNOS5
        select ARM_AMBA
-        select SOC_EXYNOS5250
        select USE_OF
        help
          Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9b58024f7d43..b189881657ec 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,9 +14,9 @@ obj-				:=
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
 obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
-obj-$(CONFIG_ARCH_EXYNOS5)      += clock-exynos5.o
 obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
+obj-$(CONFIG_SOC_EXYNOS5250)    += clock-exynos5.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
@@ -50,10 +50,8 @@ obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 obj-y                                   += dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
-obj-$(CONFIG_EXYNOS4_DEV_DWMCI)         += dev-dwmci.o
 obj-$(CONFIG_EXYNOS_DEV_DMA)            += dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
-obj-$(CONFIG_EXYNOS_DEV_DRM)            += dev-drm.o
 obj-$(CONFIG_EXYNOS_DEV_SYSMMU)         += dev-sysmmu.o
 obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 6a45c9a9abe9..efead60b9436 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -576,6 +576,10 @@ static struct clk exynos4_init_clocks_off[] = {
                .enable         = exynos4_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 15),
        }, {
+                .name           = "tmu_apbif",
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
                .name           = "keypad",
                .enable         = exynos4_clk_ip_perir_ctrl,
                .ctrlbit        = (1 << 16),
@@ -613,11 +617,6 @@ static struct clk exynos4_init_clocks_off[] = {
                .ctrlbit        = (1 << 18),
        }, {
                .name           = "iis",
-                .devname        = "samsung-i2s.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "iis",
                .devname        = "samsung-i2s.1",
                .enable         = exynos4_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 20),
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index c44ca1ee1b8d..e9d7b80bae49 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -80,6 +80,8 @@ static struct sleep_save exynos5_clock_save[] = {
        SAVE_ITEM(EXYNOS5_VPLL_CON0),
        SAVE_ITEM(EXYNOS5_VPLL_CON1),
        SAVE_ITEM(EXYNOS5_VPLL_CON2),
+        SAVE_ITEM(EXYNOS5_PWR_CTRL1),
+        SAVE_ITEM(EXYNOS5_PWR_CTRL2),
 };
 #endif
@@ -196,6 +198,11 @@ static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 }
+static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
 /* Core list of CMU_CPU side */
 static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -292,7 +299,7 @@ static struct clksrc_sources exynos5_clk_src_mpll = {
        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
 };
-struct clksrc_clk exynos5_clk_mout_mpll = {
+static struct clksrc_clk exynos5_clk_mout_mpll = {
        .clk = {
                .name           = "mout_mpll",
        },
@@ -467,12 +474,12 @@ static struct clksrc_clk exynos5_clk_pclk_acp = {
 /* Core list of CMU_TOP side */
-struct clk *exynos5_clkset_aclk_top_list[] = {
+static struct clk *exynos5_clkset_aclk_top_list[] = {
        [0] = &exynos5_clk_mout_mpll_user.clk,
        [1] = &exynos5_clk_mout_bpll_user.clk,
 };
-struct clksrc_sources exynos5_clkset_aclk = {
+static struct clksrc_sources exynos5_clkset_aclk = {
        .sources        = exynos5_clkset_aclk_top_list,
        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
 };
@@ -486,12 +493,12 @@ static struct clksrc_clk exynos5_clk_aclk_400 = {
        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 };
-struct clk *exynos5_clkset_aclk_333_166_list[] = {
+static struct clk *exynos5_clkset_aclk_333_166_list[] = {
        [0] = &exynos5_clk_mout_cpll.clk,
        [1] = &exynos5_clk_mout_mpll_user.clk,
 };
-struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
        .sources        = exynos5_clkset_aclk_333_166_list,
        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
 };
@@ -616,6 +623,11 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_peric_ctrl,
                .ctrlbit        = (1 << 24),
        }, {
+                .name           = "tmu_apbif",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peris_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
                .name           = "rtc",
                .parent         = &exynos5_clk_aclk_66.clk,
                .enable         = exynos5_clk_ip_peris_ctrl,
@@ -651,33 +663,48 @@ static struct clk exynos5_init_clocks_off[] = {
                .ctrlbit        = (1 << 15),
        }, {
                .name           = "sata",
-                .devname        = "ahci",
+                .devname        = "exynos5-sata",
+                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 6),
        }, {
-                .name           = "sata_phy",
+                .name           = "sata-phy",
+                .devname        = "exynos5-sata-phy",
+                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 24),
        }, {
-                .name           = "sata_phy_i2c",
+                .name           = "i2c",
+                .devname        = "exynos5-sata-phy-i2c",
+                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 25),
        }, {
                .name           = "mfc",
-                .devname        = "s5p-mfc",
+                .devname        = "s5p-mfc-v6",
                .enable         = exynos5_clk_ip_mfc_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
+                .devname        = "exynos5-hdmi",
                .enable         = exynos5_clk_ip_disp1_ctrl,
                .ctrlbit        = (1 << 6),
        }, {
+                .name           = "hdmiphy",
+                .devname        = "exynos5-hdmi",
+                .enable         = exynos5_clk_hdmiphy_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
                .name           = "mixer",
-                .devname        = "s5p-mixer",
+                .devname        = "exynos5-mixer",
                .enable         = exynos5_clk_ip_disp1_ctrl,
                .ctrlbit        = (1 << 5),
        }, {
+                .name           = "dp",
+                .devname        = "exynos-dp",
+                .enable         = exynos5_clk_ip_disp1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
                .name           = "jpeg",
                .enable         = exynos5_clk_ip_gen_ctrl,
                .ctrlbit        = (1 << 2),
@@ -966,7 +993,7 @@ static struct clk exynos5_clk_fimd1 = {
        .ctrlbit        = (1 << 0),
 };
-struct clk *exynos5_clkset_group_list[] = {
+static struct clk *exynos5_clkset_group_list[] = {
        [0] = &clk_ext_xtal_mux,
        [1] = NULL,
        [2] = &exynos5_clk_sclk_hdmi24m,
@@ -979,7 +1006,7 @@ struct clk *exynos5_clkset_group_list[] = {
        [9] = &exynos5_clk_mout_cpll.clk,
 };
-struct clksrc_sources exynos5_clkset_group = {
+static struct clksrc_sources exynos5_clkset_group = {
        .sources        = exynos5_clkset_group_list,
        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 };
@@ -1195,7 +1222,7 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
 };
-struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
        .clk    = {
                .name           = "sclk_fimd",
                .devname        = "exynos5-fb.1",
@@ -1226,6 +1253,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
        }, {
                .clk    = {
+                        .name           = "sclk_sata",
+                        .devname        = "exynos5-sata",
+                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos5_clkset_aclk,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
                        .name           = "sclk_gscl_wrap",
                        .devname        = "s5p-mipi-csis.0",
                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
@@ -1476,7 +1513,7 @@ static void exynos5_clock_resume(void)
 #define exynos5_clock_resume NULL
 #endif
-struct syscore_ops exynos5_clock_syscore_ops = {
+static struct syscore_ops exynos5_clock_syscore_ops = {
        .suspend        = exynos5_clock_suspend,
        .resume         = exynos5_clock_resume,
 };
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 1947be8e5f5b..ddd4b72c6f9a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -18,6 +18,7 @@
 #include <linux/sched.h>
 #include <linux/serial_core.h>
 #include <linux/of.h>
+#include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
@@ -58,12 +59,14 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
+static void exynos5440_map_io(void);
 static void exynos4_init_clocks(int xtal);
 static void exynos5_init_clocks(int xtal);
-static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 static struct cpu_table cpu_ids[] __initdata = {
@@ -72,7 +75,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
-                .init_uarts     = exynos_init_uarts,
+                .init_uarts     = exynos4_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4210,
        }, {
@@ -80,7 +83,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
-                .init_uarts     = exynos_init_uarts,
+                .init_uarts     = exynos4_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4212,
        }, {
@@ -88,7 +91,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
-                .init_uarts     = exynos_init_uarts,
+                .init_uarts     = exynos4_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4412,
        }, {
@@ -96,9 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idmask         = EXYNOS5_SOC_MASK,
                .map_io         = exynos5_map_io,
                .init_clocks    = exynos5_init_clocks,
-                .init_uarts     = exynos_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos5250,
+        }, {
+                .idcode         = EXYNOS5440_SOC_ID,
+                .idmask         = EXYNOS5_SOC_MASK,
+                .map_io         = exynos5440_map_io,
+                .init           = exynos_init,
+                .name           = name_exynos5440,
        },
 };
@@ -113,6 +121,17 @@ static struct map_desc exynos_iodesc[] __initdata = {
        },
 };
+#ifdef CONFIG_ARCH_EXYNOS5
+static struct map_desc exynos5440_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CHIPID,
+                .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+#endif
 static struct map_desc exynos4_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -257,24 +276,18 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                .length         = SZ_64K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_COMBINER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S3C_VA_UART,
                .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
                .length         = SZ_512K,
                .type           = MT_DEVICE,
-        }, {
+        },
-                .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+};
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
-                .length         = SZ_8K,
+static struct map_desc exynos5440_iodesc0[] __initdata = {
-                .type           = MT_DEVICE,
+        {
-        }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
-                .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+                .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
+                .length         = SZ_512K,
-                .length         = SZ_4K,
                .type           = MT_DEVICE,
        },
 };
@@ -286,11 +299,29 @@ void exynos4_restart(char mode, const char *cmd)
 void exynos5_restart(char mode, const char *cmd)
 {
-        __raw_writel(0x1, EXYNOS_SWRESET);
+        u32 val;
+        void __iomem *addr;
+        if (of_machine_is_compatible("samsung,exynos5250")) {
+                val = 0x1;
+                addr = EXYNOS_SWRESET;
+        } else if (of_machine_is_compatible("samsung,exynos5440")) {
+                val = (0x10 << 20) | (0x1 << 16);
+                addr = EXYNOS5440_SWRESET;
+        } else {
+                pr_err("%s: cannot support non-DT\n", __func__);
+                return;
+        }
+        __raw_writel(val, addr);
 }
 void __init exynos_init_late(void)
 {
+        if (of_machine_is_compatible("samsung,exynos5440"))
+                /* to be supported later */
+                return;
        exynos_pm_late_initcall();
 }
@@ -302,8 +333,20 @@ void __init exynos_init_late(void)
 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 {
+        struct map_desc *iodesc = exynos_iodesc;
+        int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
+#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
+        unsigned long root = of_get_flat_dt_root();
        /* initialize the io descriptors we need for initialization */
-        iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+        if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
+                iodesc = exynos5440_iodesc;
+                iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
+        }
+#endif
+        iotable_init(iodesc, iodesc_sz);
        if (mach_desc)
                iotable_init(mach_desc, size);
@@ -354,23 +397,6 @@ static void __init exynos4_map_io(void)
 static void __init exynos5_map_io(void)
 {
        iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-        s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
-        s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
-        s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
-        s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
-        s3c_sdhci_setname(0, "exynos4-sdhci");
-        s3c_sdhci_setname(1, "exynos4-sdhci");
-        s3c_sdhci_setname(2, "exynos4-sdhci");
-        s3c_sdhci_setname(3, "exynos4-sdhci");
-        /* The I2C bus controllers are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_i2c2_setname("s3c2440-i2c");
-        s3c64xx_spi_setname("exynos4210-spi");
 }
 static void __init exynos4_init_clocks(int xtal)
@@ -389,6 +415,11 @@ static void __init exynos4_init_clocks(int xtal)
        exynos4_setup_clocks();
 }
+static void __init exynos5440_map_io(void)
+{
+        iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
+}
 static void __init exynos5_init_clocks(int xtal)
 {
        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -589,7 +620,8 @@ static void __init combiner_init(void __iomem *combiner_base,
 }
 #ifdef CONFIG_OF
-int __init combiner_of_init(struct device_node *np, struct device_node *parent)
+static int __init combiner_of_init(struct device_node *np,
+                                   struct device_node *parent)
 {
        void __iomem *combiner_base;
@@ -604,8 +636,9 @@ int __init combiner_of_init(struct device_node *np, struct device_node *parent)
        return 0;
 }
-static const struct of_device_id exynos4_dt_irq_match[] = {
+static const struct of_device_id exynos_dt_irq_match[] = {
        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
        { .compatible = "samsung,exynos4210-combiner",
                        .data = combiner_of_init, },
        {},
@@ -622,7 +655,7 @@ void __init exynos4_init_irq(void)
                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 #ifdef CONFIG_OF
        else
-                of_irq_init(exynos4_dt_irq_match);
+                of_irq_init(exynos_dt_irq_match);
 #endif
        if (!of_have_populated_dt())
@@ -639,7 +672,7 @@ void __init exynos4_init_irq(void)
 void __init exynos5_init_irq(void)
 {
 #ifdef CONFIG_OF
-        of_irq_init(exynos4_dt_irq_match);
+        of_irq_init(exynos_dt_irq_match);
 #endif
        /*
         * The parameters of s5p_init_irq() are for VIC init.
@@ -647,6 +680,8 @@ void __init exynos5_init_irq(void)
         * uses GIC instead of VIC.
         */
        s5p_init_irq(NULL, 0);
+        gic_arch_extn.irq_set_wake = s3c_irq_wake;
 }
 struct bus_type exynos_subsys = {
@@ -669,7 +704,7 @@ static int __init exynos4_l2x0_cache_init(void)
 {
        int ret;
-        if (soc_is_exynos5250())
+        if (soc_is_exynos5250() || soc_is_exynos5440())
                return 0;
        ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
@@ -727,7 +762,7 @@ static int __init exynos_init(void)
 /* uart registration process */
-static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        struct s3c2410_uartcfg *tcfg = cfg;
        u32 ucnt;
@@ -735,10 +770,7 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
        for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
                tcfg->has_fracval = 1;
-        if (soc_is_exynos5250())
+        s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
-                s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
-        else
-                s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 static void __iomem *exynos_eint_base;
@@ -970,14 +1002,7 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
        struct irq_chip *chip = irq_get_chip(irq);
        chained_irq_enter(chip, desc);
-        chip->irq_mask(&desc->irq_data);
-        if (chip->irq_ack)
-                chip->irq_ack(&desc->irq_data);
        generic_handle_irq(*irq_data);
-        chip->irq_unmask(&desc->irq_data);
        chained_irq_exit(chip, desc);
 }
@@ -997,11 +1022,14 @@ static int __init exynos_init_irq_eint(void)
         * platforms switch over to using the pinctrl driver, the wakeup
         * interrupt support code here can be completely removed.
         */
+        static const struct of_device_id exynos_pinctrl_ids[] = {
+                { .compatible = "samsung,pinctrl-exynos4210", },
+                { .compatible = "samsung,pinctrl-exynos4x12", },
+        };
        struct device_node *pctrl_np, *wkup_np;
-        const char *pctrl_compat = "samsung,pinctrl-exynos4210";
        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
-        for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
+        for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
                if (of_device_is_available(pctrl_np)) {
                        wkup_np = of_find_compatible_node(pctrl_np, NULL,
                                                        wkup_compat);
@@ -1010,6 +1038,8 @@ static int __init exynos_init_irq_eint(void)
                }
        }
 #endif
+        if (soc_is_exynos5440())
+                return 0;
        if (soc_is_exynos5250())
                exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index cff0595d0d35..050924152776 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -21,6 +21,7 @@
 #include <asm/suspend.h>
 #include <asm/unified.h>
 #include <asm/cpuidle.h>
+#include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pmu.h>
@@ -116,7 +117,8 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
        cpu_suspend(0, idle_finisher);
 #ifdef CONFIG_SMP
-        scu_enable(S5P_VA_SCU);
+        if (!soc_is_exynos5250())
+                scu_enable(S5P_VA_SCU);
 #endif
        cpu_pm_exit();
@@ -156,12 +158,47 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                return exynos4_enter_core0_aftr(dev, drv, new_index);
 }
+static void __init exynos5_core_down_clk(void)
+{
+        unsigned int tmp;
+        /*
+         * Enable arm clock down (in idle) and set arm divider
+         * ratios in WFI/WFE state.
+         */
+        tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
+              PWR_CTRL1_CORE1_DOWN_RATIO | \
+              PWR_CTRL1_DIV2_DOWN_EN     | \
+              PWR_CTRL1_DIV1_DOWN_EN     | \
+              PWR_CTRL1_USE_CORE1_WFE    | \
+              PWR_CTRL1_USE_CORE0_WFE    | \
+              PWR_CTRL1_USE_CORE1_WFI    | \
+              PWR_CTRL1_USE_CORE0_WFI;
+        __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+        /*
+         * Enable arm clock up (on exiting idle). Set arm divider
+         * ratios when not in idle along with the standby duration
+         * ratios.
+         */
+        tmp = PWR_CTRL2_DIV2_UP_EN       | \
+              PWR_CTRL2_DIV1_UP_EN       | \
+              PWR_CTRL2_DUR_STANDBY2_VAL | \
+              PWR_CTRL2_DUR_STANDBY1_VAL | \
+              PWR_CTRL2_CORE2_UP_RATIO   | \
+              PWR_CTRL2_CORE1_UP_RATIO;
+        __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
+}
 static int __init exynos4_init_cpuidle(void)
 {
        int i, max_cpuidle_state, cpu_id;
        struct cpuidle_device *device;
        struct cpuidle_driver *drv = &exynos4_idle_driver;
+        if (soc_is_exynos5250())
+                exynos5_core_down_clk();
        /* Setup cpuidle driver */
        drv->state_count = (sizeof(exynos4_cpuidle_set) /
                                       sizeof(struct cpuidle_state));
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index ae321c7cb15f..a1cb42c39590 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -14,9 +14,9 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/asoc-s3c.h>
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
deleted file mode 100644
index 17c9c6ecc2e0..000000000000
--- a/arch/arm/mach-exynos/dev-drm.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos/dev-drm.c
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - core DRM device
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <plat/devs.h>
-static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
-struct platform_device exynos_device_drm = {
-        .name   = "exynos-drm",
-        .dev    = {
-                .dma_mask               = &exynos_drm_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
deleted file mode 100644
index 79035018fb74..000000000000
--- a/arch/arm/mach-exynos/dev-dwmci.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/dev-dwmci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Platform device for Synopsys DesignWare Mobile Storage IP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mmc/dw_mmc.h>
-#include <plat/devs.h>
-#include <mach/map.h>
-static int exynos4_dwmci_get_bus_wd(u32 slot_id)
-{
-        return 4;
-}
-static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
-{
-        return 0;
-}
-static struct resource exynos4_dwmci_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
-        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
-};
-static struct dw_mci_board exynos4_dwci_pdata = {
-        .num_slots                      = 1,
-        .quirks                         = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
-        .bus_hz                         = 80 * 1000 * 1000,
-        .detect_delay_ms        = 200,
-        .init                           = exynos4_dwmci_init,
-        .get_bus_wd                     = exynos4_dwmci_get_bus_wd,
-};
-static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
-struct platform_device exynos4_device_dwmci = {
-        .name           = "dw_mmc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(exynos4_dwmci_resource),
-        .resource       = exynos4_dwmci_resource,
-        .dev            = {
-                .dma_mask               = &exynos4_dwmci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data  = &exynos4_dwci_pdata,
-        },
-};
-void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
-{
-        struct dw_mci_board *npd;
-        npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
-                        &exynos4_device_dwmci);
-        if (!npd->init)
-                npd->init = exynos4_dwmci_init;
-        if (!npd->get_bus_wd)
-                npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
-}
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
index 14ed7951a2c6..4244d02dafbd 100644
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -12,10 +12,10 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <mach/irqs.h>
 #include <mach/map.h>
-#include <linux/platform_data/usb-exynos.h>
 #include <plat/devs.h>
 #include <plat/usb-phy.h>
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
index 2e85c022fd16..7c42f4b7c8be 100644
--- a/arch/arm/mach-exynos/dev-uart.c
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -52,27 +52,3 @@ struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
                .nr_resources   = ARRAY_SIZE(exynos4_uart3_resource),
        },
 };
-EXYNOS_UART_RESOURCE(5, 0)
-EXYNOS_UART_RESOURCE(5, 1)
-EXYNOS_UART_RESOURCE(5, 2)
-EXYNOS_UART_RESOURCE(5, 3)
-struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
-        [0] = {
-                .resources      = exynos5_uart0_resource,
-                .nr_resources   = ARRAY_SIZE(exynos5_uart0_resource),
-        },
-        [1] = {
-                .resources      = exynos5_uart1_resource,
-                .nr_resources   = ARRAY_SIZE(exynos5_uart0_resource),
-        },
-        [2] = {
-                .resources      = exynos5_uart2_resource,
-                .nr_resources   = ARRAY_SIZE(exynos5_uart2_resource),
-        },
-        [3] = {
-                .resources      = exynos5_uart3_resource,
-                .nr_resources   = ARRAY_SIZE(exynos5_uart3_resource),
-        },
-};
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index f4d7dd20cdac..c3f825b27947 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -20,10 +20,11 @@
 #include <asm/smp_plat.h>
 #include <mach/regs-pmu.h>
+#include <plat/cpu.h>
 #include "common.h"
-static inline void cpu_enter_lowpower(void)
+static inline void cpu_enter_lowpower_a9(void)
 {
        unsigned int v;
@@ -45,6 +46,35 @@ static inline void cpu_enter_lowpower(void)
          : "cc");
 }
+static inline void cpu_enter_lowpower_a15(void)
+{
+        unsigned int v;
+        asm volatile(
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+          : "=&r" (v)
+          : "Ir" (CR_C)
+          : "cc");
+        flush_cache_louis();
+        asm volatile(
+        /*
+        * Turn off coherency
+        */
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        : "=&r" (v)
+        : "Ir" (0x40)
+        : "cc");
+        isb();
+        dsb();
+}
 static inline void cpu_leave_lowpower(void)
 {
        unsigned int v;
@@ -103,11 +133,20 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 void __ref exynos_cpu_die(unsigned int cpu)
 {
        int spurious = 0;
+        int primary_part = 0;
        /*
-         * we're ready for shutdown now, so do it
+         * we're ready for shutdown now, so do it.
+         * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
+         * number by reading the Main ID register and then perform the
+         * appropriate sequence for entering low power.
         */
-        cpu_enter_lowpower();
+        asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
+        if ((primary_part & 0xfff0) == 0xc0f0)
+                cpu_enter_lowpower_a15();
+        else
+                cpu_enter_lowpower_a9();
        platform_do_lowpower(cpu, &spurious);
        /*
diff --git a/arch/arm/mach-exynos/include/mach/dwmci.h b/arch/arm/mach-exynos/include/mach/dwmci.h
deleted file mode 100644
index 7ce657459cc0..000000000000
--- a/arch/arm/mach-exynos/include/mach/dwmci.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Synopsys DesignWare Mobile Storage for EXYNOS4210
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_ARCH_DWMCI_H
-#define __ASM_ARM_ARCH_DWMCI_H __FILE__
-#include <linux/mmc/dw_mmc.h>
-extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
-#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6f9092..1f4dc35cd4b9 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -136,6 +136,9 @@
 #define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
+#define EXYNOS4_IRQ_TMU_TRIG0           COMBINER_IRQ(2, 4)
+#define EXYNOS4_IRQ_TMU_TRIG1           COMBINER_IRQ(3, 4)
 #define EXYNOS4_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
 #define EXYNOS4_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
 #define EXYNOS4_IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
@@ -259,11 +262,6 @@
 #define EXYNOS5_IRQ_IEM_IEC             IRQ_SPI(48)
 #define EXYNOS5_IRQ_IEM_APC             IRQ_SPI(49)
 #define EXYNOS5_IRQ_GPIO_C2C            IRQ_SPI(50)
-#define EXYNOS5_IRQ_UART0               IRQ_SPI(51)
-#define EXYNOS5_IRQ_UART1               IRQ_SPI(52)
-#define EXYNOS5_IRQ_UART2               IRQ_SPI(53)
-#define EXYNOS5_IRQ_UART3               IRQ_SPI(54)
-#define EXYNOS5_IRQ_UART4               IRQ_SPI(55)
 #define EXYNOS5_IRQ_IIC                 IRQ_SPI(56)
 #define EXYNOS5_IRQ_IIC1                IRQ_SPI(57)
 #define EXYNOS5_IRQ_IIC2                IRQ_SPI(58)
@@ -333,6 +331,11 @@
 #define EXYNOS5_IRQ_FIMC_LITE1          IRQ_SPI(126)
 #define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
+/* EXYNOS5440 */
+#define EXYNOS5440_IRQ_UART0            IRQ_SPI(2)
+#define EXYNOS5440_IRQ_UART1            IRQ_SPI(3)
 #define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
 #define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index ed4da4544cd2..1df6abbf53b8 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -53,6 +53,7 @@
 #define EXYNOS4_PA_ONENAND_DMA          0x0C600000
 #define EXYNOS_PA_CHIPID                0x10000000
+#define EXYNOS5440_PA_CHIPID            0x00160000
 #define EXYNOS4_PA_SYSCON               0x10010000
 #define EXYNOS5_PA_SYSCON               0x10050100
@@ -88,6 +89,8 @@
 #define EXYNOS4_PA_TWD                  0x10500600
 #define EXYNOS4_PA_L2CC                 0x10502000
+#define EXYNOS4_PA_TMU                  0x100C0000
 #define EXYNOS4_PA_MDMA0                0x10810000
 #define EXYNOS4_PA_MDMA1                0x12850000
 #define EXYNOS4_PA_S_MDMA1              0x12840000
@@ -280,7 +283,10 @@
 #define EXYNOS5_PA_UART1                0x12C10000
 #define EXYNOS5_PA_UART2                0x12C20000
 #define EXYNOS5_PA_UART3                0x12C30000
-#define EXYNOS5_SZ_UART                 SZ_256
+#define EXYNOS5440_PA_UART0             0x000B0000
+#define EXYNOS5440_PA_UART1             0x000C0000
+#define EXYNOS5440_SZ_UART              SZ_256
 #define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 8c9b38c9c504..d36ad76ad6a4 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -267,6 +267,9 @@
 #define EXYNOS5_CLKDIV_STATCPU0                 EXYNOS_CLKREG(0x00600)
 #define EXYNOS5_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x00604)
+#define EXYNOS5_PWR_CTRL1                       EXYNOS_CLKREG(0x01020)
+#define EXYNOS5_PWR_CTRL2                       EXYNOS_CLKREG(0x01024)
 #define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
 #define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
@@ -344,6 +347,22 @@
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
+#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
+#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
 /* Compatibility defines and inclusion */
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/include/mach/regs-mem.h b/arch/arm/mach-exynos/include/mach/regs-mem.h
deleted file mode 100644
index 0368b5a27252..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-mem.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - SROMC and DMC register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_REGS_MEM_H
-#define __ASM_ARCH_REGS_MEM_H __FILE__
-#include <mach/map.h>
-#define S5P_DMC0_MEMCON_OFFSET          0x04
-#define S5P_DMC0_MEMTYPE_SHIFT          8
-#define S5P_DMC0_MEMTYPE_MASK           0xF
-#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d4e392b811a3..3f30aa1ae354 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -15,6 +15,7 @@
 #include <mach/map.h>
 #define S5P_PMUREG(x)                           (S5P_VA_PMU + (x))
+#define S5P_SYSREG(x)                           (S3C_VA_SYS + (x))
 #define S5P_CENTRAL_SEQ_CONFIGURATION           S5P_PMUREG(0x0200)
@@ -31,6 +32,7 @@
 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
 #define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
+#define EXYNOS5440_SWRESET                      S5P_PMUREG(0x00C4)
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
@@ -230,7 +232,7 @@
 /* For EXYNOS5 */
-#define EXYNOS5_USB_CFG                                         S5P_PMUREG(0x0230)
+#define EXYNOS5_SYS_I2C_CFG                                     S5P_SYSREG(0x0234)
 #define EXYNOS5_AUTO_WDTRESET_DISABLE                           S5P_PMUREG(0x0408)
 #define EXYNOS5_MASK_WDTRESET_REQUEST                           S5P_PMUREG(0x040C)
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 3f37a5e8a1f4..b938f9fc1dd1 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -147,7 +147,6 @@ static struct platform_device *armlex4210_devices[] __initdata = {
        &s3c_device_hsmmc3,
        &s3c_device_rtc,
        &s3c_device_wdt,
-        &samsung_asoc_dma,
        &armlex4210_smsc911x,
        &exynos4_device_ahci,
 };
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index eadf4b59e7d2..92757ff817ae 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -77,6 +77,9 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
                                "exynos4210-spi.2", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
+                                "exynos-tmu", NULL),
        {},
 };
@@ -94,6 +97,8 @@ static void __init exynos4_dt_machine_init(void)
 static char const *exynos4_dt_compat[] __initdata = {
        "samsung,exynos4210",
+        "samsung,exynos4212",
+        "samsung,exynos4412",
        NULL
 };
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db1cd8eacf28..f038c8cadca4 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -10,14 +10,19 @@
 */
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 #include <linux/serial_core.h>
+#include <linux/memblock.h>
+#include <linux/io.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 #include <mach/map.h>
+#include <mach/regs-pmu.h>
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/mfc.h>
 #include "common.h"
@@ -47,6 +52,20 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "s3c2440-i2c.0", NULL),
        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
                                "s3c2440-i2c.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
+                                "s3c2440-i2c.2", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
+                                "s3c2440-i2c.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
+                                "s3c2440-i2c.4", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
+                                "s3c2440-i2c.5", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
+                                "s3c2440-i2c.6", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
+                                "s3c2440-i2c.7", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
+                                "s3c2440-hdmiphy-i2c", NULL),
        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
                                "dw_mmc.0", NULL),
        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
@@ -61,6 +80,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "exynos4210-spi.1", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
                                "exynos4210-spi.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
+                                "exynos5-sata", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
+                                "exynos5-sata-phy", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
+                                "exynos5-sata-phy-i2c", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
@@ -72,35 +97,91 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "exynos-gsc.2", NULL),
        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
                                "exynos-gsc.3", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
+                                "exynos5-hdmi", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
+                                "exynos5-mixer", NULL),
+        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
+                                "exynos-tmu", NULL),
        {},
 };
-static void __init exynos5250_dt_map_io(void)
+static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
+                                "exynos4210-uart.0", NULL),
+        {},
+};
+static void __init exynos5_dt_map_io(void)
 {
+        unsigned long root = of_get_flat_dt_root();
        exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+        if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
+                s3c24xx_init_clocks(24000000);
 }
-static void __init exynos5250_dt_machine_init(void)
+static void __init exynos5_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
+        struct device_node *i2c_np;
-                                exynos5250_auxdata_lookup, NULL);
+        const char *i2c_compat = "samsung,s3c2440-i2c";
+        unsigned int tmp;
+        /*
+         * Exynos5's legacy i2c controller and new high speed i2c
+         * controller have muxed interrupt sources. By default the
+         * interrupts for 4-channel HS-I2C controller are enabled.
+         * If node for first four channels of legacy i2c controller
+         * are available then re-configure the interrupts via the
+         * system register.
+         */
+        for_each_compatible_node(i2c_np, NULL, i2c_compat) {
+                if (of_device_is_available(i2c_np)) {
+                        if (of_alias_get_id(i2c_np, "i2c") < 4) {
+                                tmp = readl(EXYNOS5_SYS_I2C_CFG);
+                                writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")),
+                                                EXYNOS5_SYS_I2C_CFG);
+                        }
+                }
+        }
+        if (of_machine_is_compatible("samsung,exynos5250"))
+                of_platform_populate(NULL, of_default_bus_match_table,
+                                     exynos5250_auxdata_lookup, NULL);
+        else if (of_machine_is_compatible("samsung,exynos5440"))
+                of_platform_populate(NULL, of_default_bus_match_table,
+                                     exynos5440_auxdata_lookup, NULL);
 }
-static char const *exynos5250_dt_compat[] __initdata = {
+static char const *exynos5_dt_compat[] __initdata = {
        "samsung,exynos5250",
+        "samsung,exynos5440",
        NULL
 };
+static void __init exynos5_reserve(void)
+{
+        struct s5p_mfc_dt_meminfo mfc_mem;
+        /* Reserve memory for MFC only if it's available */
+        mfc_mem.compatible = "samsung,mfc-v6";
+        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+                                mfc_mem.lsize);
+}
 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .init_irq       = exynos5_init_irq,
        .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos5250_dt_map_io,
+        .map_io         = exynos5_dt_map_io,
        .handle_irq     = gic_handle_irq,
-        .init_machine   = exynos5250_dt_machine_init,
+        .init_machine   = exynos5_dt_machine_init,
        .init_late      = exynos_init_late,
        .timer          = &exynos4_timer,
-        .dt_compat      = exynos5250_dt_compat,
+        .dt_compat      = exynos5_dt_compat,
        .restart        = exynos5_restart,
+        .reserve        = exynos5_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index c05d7aa84031..27d4ed8b116e 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -25,7 +25,10 @@
 #include <linux/mmc/host.h>
 #include <linux/fb.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mipi-csis.h>
 #include <linux/platform_data/s3c-hsotg.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <drm/exynos_drm.h>
 #include <video/platform_lcd.h>
@@ -45,14 +48,11 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/mfc.h>
 #include <plat/fimc-core.h>
 #include <plat/camport.h>
-#include <linux/platform_data/mipi-csis.h>
 #include <mach/map.h>
@@ -113,7 +113,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
                                MMC_CAP_ERASE),
-        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
@@ -1327,9 +1326,6 @@ static struct platform_device *nuri_devices[] __initdata = {
        &cam_vdda_fixed_rdev,
        &cam_8m_12v_fixed_rdev,
        &exynos4_bus_devfreq,
-#ifdef CONFIG_DRM_EXYNOS
-        &exynos_device_drm,
-#endif
 };
 static void __init nuri_map_io(void)
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 9adf491674ea..e6f4191cd14c 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -23,7 +23,10 @@
 #include <linux/mfd/max8997.h>
 #include <linux/lcd.h>
 #include <linux/rfkill-gpio.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/s3c-hsotg.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -36,8 +39,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
@@ -45,7 +46,6 @@
 #include <plat/mfc.h>
 #include <plat/hdmi.h>
-#include <linux/platform_data/usb-exynos.h>
 #include <mach/map.h>
 #include <drm/exynos_drm.h>
@@ -100,6 +100,7 @@ static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
+        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */
 };
 static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
@@ -110,6 +111,7 @@ static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
 static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
+        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */
 };
 static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
        REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
@@ -709,9 +711,6 @@ static struct platform_device *origen_devices[] __initdata = {
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
        &s5p_device_mixer,
-#ifdef CONFIG_DRM_EXYNOS
-        &exynos_device_drm,
-#endif
        &exynos4_device_ohci,
        &origen_device_gpiokeys,
        &origen_lcd_hv070wsa,
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 730f1ac65928..a1555a73c7af 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -21,6 +21,7 @@
 #include <linux/pwm_backlight.h>
 #include <linux/regulator/machine.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <asm/mach/arch.h>
@@ -34,7 +35,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/mfc.h>
 #include <plat/regs-serial.h>
@@ -317,9 +317,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
        &s5p_device_mfc,
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
-#ifdef CONFIG_DRM_EXYNOS
-        &exynos_device_drm,
-#endif
        &samsung_device_keypad,
 };
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index ee4fb1a9cb72..b7384241fb03 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -20,7 +20,10 @@
 #include <linux/input.h>
 #include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/s3c-hsotg.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -35,16 +38,13 @@
 #include <plat/fb.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
-#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/hdmi.h>
 #include <mach/map.h>
-#include <linux/platform_data/usb-exynos.h>
 #include <drm/exynos_drm.h>
 #include "common.h"
@@ -300,9 +300,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
        &s5p_device_fimc_md,
        &s5p_device_g2d,
        &s5p_device_jpeg,
-#ifdef CONFIG_DRM_EXYNOS
-        &exynos_device_drm,
-#endif
        &exynos4_device_ac97,
        &exynos4_device_i2s0,
        &exynos4_device_ohci,
@@ -311,7 +308,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
        &exynos4_device_spdif,
-        &samsung_asoc_dma,
        &samsung_asoc_idma,
        &s5p_device_fimd0,
        &smdkv310_device_audio,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index ebc9dd339a38..9e3340f18950 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -23,6 +23,8 @@
 #include <linux/i2c-gpio.h>
 #include <linux/i2c/mcs.h>
 #include <linux/i2c/atmel_mxt_ts.h>
+#include <linux/platform_data/i2c-s3c2410.h>
+#include <linux/platform_data/mipi-csis.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <drm/exynos_drm.h>
@@ -35,7 +37,6 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/fb.h>
 #include <plat/mfc.h>
@@ -43,7 +44,6 @@
 #include <plat/fimc-core.h>
 #include <plat/s5p-time.h>
 #include <plat/camport.h>
-#include <linux/platform_data/mipi-csis.h>
 #include <mach/map.h>
@@ -754,7 +754,6 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
        .max_width              = 8,
        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
@@ -1081,9 +1080,6 @@ static struct platform_device *universal_devices[] __initdata = {
        &s5p_device_onenand,
        &s5p_device_fimd0,
        &s5p_device_jpeg,
-#ifdef CONFIG_DRM_EXYNOS
-        &exynos_device_drm,
-#endif
        &s3c_device_usb_hsotg,
        &s5p_device_mfc,
        &s5p_device_mfc_l,
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8a408b..57668eb68e75 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -19,7 +19,9 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/percpu.h>
+#include <linux/of.h>
+#include <asm/arch_timer.h>
 #include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
@@ -476,8 +478,13 @@ static void __init exynos4_timer_resources(void)
 #endif /* CONFIG_LOCAL_TIMERS */
 }
-static void __init exynos4_timer_init(void)
+static void __init exynos_timer_init(void)
 {
+        if (soc_is_exynos5440()) {
+                arch_timer_of_register();
+                return;
+        }
        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
                mct_int_type = MCT_INT_SPI;
        else
@@ -489,5 +496,5 @@ static void __init exynos4_timer_init(void)
 }
 struct sys_timer exynos4_timer = {
-        .init           = exynos4_timer_init,
+        .init           = exynos_timer_init,
 };
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index f93d820ecab5..4ca8ff14a5bf 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -36,8 +36,22 @@
 extern void exynos4_secondary_startup(void);
-#define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+static inline void __iomem *cpu_boot_reg_base(void)
-                                S5P_INFORM5 : S5P_VA_SYSRAM)
+{
+        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+                return S5P_INFORM5;
+        return S5P_VA_SYSRAM;
+}
+static inline void __iomem *cpu_boot_reg(int cpu)
+{
+        void __iomem *boot_reg;
+        boot_reg = cpu_boot_reg_base();
+        if (soc_is_exynos4412())
+                boot_reg += 4*cpu;
+        return boot_reg;
+}
 /*
 * Write pen_release in a way that is guaranteed to be visible to all
@@ -84,6 +98,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu)
 static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
+        unsigned long phys_cpu = cpu_logical_map(cpu);
        /*
         * Set synchronisation state between this boot processor
@@ -99,7 +114,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
         * Note that "pen_release" is the hardware CPU ID, whereas
         * "cpu" is Linux's internal ID.
         */
-        write_pen_release(cpu_logical_map(cpu));
+        write_pen_release(phys_cpu);
        if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
                __raw_writel(S5P_CORE_LOCAL_PWR_EN,
@@ -133,7 +148,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
                smp_rmb();
                __raw_writel(virt_to_phys(exynos4_secondary_startup),
-                        CPU1_BOOT_REG);
+                                                        cpu_boot_reg(phys_cpu));
                gic_raise_softirq(cpumask_of(cpu), 0);
                if (pen_release == -1)
@@ -181,6 +196,8 @@ static void __init exynos_smp_init_cpus(void)
 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
+        int i;
        if (!soc_is_exynos5250())
                scu_enable(scu_base_addr());
@@ -190,8 +207,9 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-        __raw_writel(virt_to_phys(exynos4_secondary_startup),
+        for (i = 1; i < max_cpus; ++i)
-                        CPU1_BOOT_REG);
+                __raw_writel(virt_to_phys(exynos4_secondary_startup),
+                                        cpu_boot_reg(cpu_logical_map(i)));
 }
 struct smp_operations exynos_smp_ops __initdata = {
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c06c992943a1..b9b539cac81e 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -62,6 +62,10 @@ static struct sleep_save exynos4_vpll_save[] = {
        SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
+static struct sleep_save exynos5_sys_save[] = {
+        SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
+};
 static struct sleep_save exynos_core_save[] = {
        /* SROM side */
        SAVE_ITEM(S5P_SROM_BW),
@@ -81,6 +85,9 @@ static int exynos_cpu_suspend(unsigned long arg)
        outer_flush_all();
 #endif
+        if (soc_is_exynos5250())
+                flush_cache_all();
        /* issue the standby signal into the pm unit. */
        cpu_do_idle();
@@ -98,6 +105,7 @@ static void exynos_pm_prepare(void)
                s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
                s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
        } else {
+                s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
                /* Disable USE_RETENTION of JPEG_MEM_OPTION */
                tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
                tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
@@ -301,6 +309,10 @@ static void exynos_pm_resume(void)
        __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
        __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+        if (soc_is_exynos5250())
+                s3c_pm_do_restore(exynos5_sys_save,
+                        ARRAY_SIZE(exynos5_sys_save));
        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
        if (!soc_is_exynos5250()) {
@@ -312,6 +324,10 @@ static void exynos_pm_resume(void)
        }
 early_wakeup:
+        /* Clear SLEEP mode set in INFORM1 */
+        __raw_writel(0x0, S5P_INFORM1);
        return;
 }
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index c0bc83a7663e..9f1351de52f7 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -19,6 +19,8 @@
 #include <linux/pm_domain.h>
 #include <linux/delay.h>
 #include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/sched.h>
 #include <mach/regs-pmu.h>
 #include <plat/devs.h>
@@ -83,12 +85,88 @@ static struct exynos_pm_domain PD = {			\
 }
 #ifdef CONFIG_OF
+static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
+                                         struct device *dev)
+{
+        int ret;
+        dev_dbg(dev, "adding to power domain %s\n", pd->pd.name);
+        while (1) {
+                ret = pm_genpd_add_device(&pd->pd, dev);
+                if (ret != -EAGAIN)
+                        break;
+                cond_resched();
+        }
+        pm_genpd_dev_need_restore(dev, true);
+}
+static void exynos_remove_device_from_domain(struct device *dev)
+{
+        struct generic_pm_domain *genpd = dev_to_genpd(dev);
+        int ret;
+        dev_dbg(dev, "removing from power domain %s\n", genpd->name);
+        while (1) {
+                ret = pm_genpd_remove_device(genpd, dev);
+                if (ret != -EAGAIN)
+                        break;
+                cond_resched();
+        }
+}
+static void exynos_read_domain_from_dt(struct device *dev)
+{
+        struct platform_device *pd_pdev;
+        struct exynos_pm_domain *pd;
+        struct device_node *node;
+        node = of_parse_phandle(dev->of_node, "samsung,power-domain", 0);
+        if (!node)
+                return;
+        pd_pdev = of_find_device_by_node(node);
+        if (!pd_pdev)
+                return;
+        pd = platform_get_drvdata(pd_pdev);
+        exynos_add_device_to_domain(pd, dev);
+}
+static int exynos_pm_notifier_call(struct notifier_block *nb,
+                                    unsigned long event, void *data)
+{
+        struct device *dev = data;
+        switch (event) {
+        case BUS_NOTIFY_BIND_DRIVER:
+                if (dev->of_node)
+                        exynos_read_domain_from_dt(dev);
+                break;
+        case BUS_NOTIFY_UNBOUND_DRIVER:
+                exynos_remove_device_from_domain(dev);
+                break;
+        }
+        return NOTIFY_DONE;
+}
+static struct notifier_block platform_nb = {
+        .notifier_call = exynos_pm_notifier_call,
+};
 static __init int exynos_pm_dt_parse_domains(void)
 {
+        struct platform_device *pdev;
        struct device_node *np;
        for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
                struct exynos_pm_domain *pd;
+                int on;
+                pdev = of_find_device_by_node(np);
                pd = kzalloc(sizeof(*pd), GFP_KERNEL);
                if (!pd) {
@@ -97,15 +175,22 @@ static __init int exynos_pm_dt_parse_domains(void)
                        return -ENOMEM;
                }
-                if (of_get_property(np, "samsung,exynos4210-pd-off", NULL))
+                pd->pd.name = kstrdup(np->name, GFP_KERNEL);
-                        pd->is_off = true;
+                pd->name = pd->pd.name;
-                pd->name = np->name;
                pd->base = of_iomap(np, 0);
                pd->pd.power_off = exynos_pd_power_off;
                pd->pd.power_on = exynos_pd_power_on;
                pd->pd.of_node = np;
-                pm_genpd_init(&pd->pd, NULL, false);
+                platform_set_drvdata(pdev, pd);
+                on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
+                pm_genpd_init(&pd->pd, NULL, !on);
        }
+        bus_register_notifier(&platform_bus_type, &platform_nb);
        return 0;
 }
 #else
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index 5700f23629f7..e2d9dfbf102c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -20,7 +20,7 @@ struct platform_device; /* don't need the contents */
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        if (soc_is_exynos5250())
+        if (soc_is_exynos5250() || soc_is_exynos5440())
                /* will be implemented with gpio function */
                return;
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 0e1d0a42a3ea..551c97e87a78 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,5 +1,5 @@
 config ARCH_HIGHBANK
-        bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7
+        bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
        select ARM_GIC
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 3ec8bdd25d09..8a1ef576d79f 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -3,7 +3,6 @@ obj-y					:= highbank.o system.o smc.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_smc.o                            :=-Wa,-march=armv7-a$(plus_sec)
-obj-$(CONFIG_DEBUG_HIGHBANK_UART)       += lluart.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_PM_SLEEP)                  += pm.o
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 286ec82a4f63..80235b46cb58 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,12 +1,10 @@
+#ifndef __HIGHBANK_CORE_H
+#define __HIGHBANK_CORE_H
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
 extern void highbank_clocks_init(void);
 extern void highbank_restart(char, const char *);
 extern void __iomem *scu_base_addr;
-#ifdef CONFIG_DEBUG_HIGHBANK_UART
-extern void highbank_lluart_map_io(void);
-#else
-static inline void highbank_lluart_map_io(void) {}
-#endif
 #ifdef CONFIG_PM_SLEEP
 extern void highbank_pm_init(void);
@@ -18,3 +16,5 @@ extern void highbank_smc1(int fn, int arg);
 extern void highbank_cpu_die(unsigned int cpu);
 extern struct smp_operations highbank_smp_ops;
+#endif
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 40e36a50304c..dc248167d206 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -26,9 +26,9 @@
 #include <linux/smp.h>
 #include <linux/amba/bus.h>
+#include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
@@ -42,16 +42,7 @@
 #include "sysregs.h"
 void __iomem *sregs_base;
+void __iomem *scu_base_addr;
-#define HB_SCU_VIRT_BASE        0xfee00000
-void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
-static struct map_desc scu_io_desc __initdata = {
-        .virtual        = HB_SCU_VIRT_BASE,
-        .pfn            = 0, /* run-time */
-        .length         = SZ_4K,
-        .type           = MT_DEVICE,
-};
 static void __init highbank_scu_map_io(void)
 {
@@ -60,14 +51,7 @@ static void __init highbank_scu_map_io(void)
        /* Get SCU base */
        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
-        scu_io_desc.pfn = __phys_to_pfn(base);
+        scu_base_addr = ioremap(base, SZ_4K);
-        iotable_init(&scu_io_desc, 1);
-}
-static void __init highbank_map_io(void)
-{
-        highbank_scu_map_io();
-        highbank_lluart_map_io();
 }
 #define HB_JUMP_TABLE_PHYS(cpu)         (0x40 + (0x10 * (cpu)))
@@ -83,6 +67,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
 }
 const static struct of_device_id irq_match[] = {
+        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
        {}
 };
@@ -99,6 +84,9 @@ static void __init highbank_init_irq(void)
 {
        of_irq_init(irq_match);
+        if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
+                highbank_scu_map_io();
 #ifdef CONFIG_CACHE_L2X0
        /* Enable PL310 L2 Cache controller */
        highbank_smc1(0x102, 0x1);
@@ -136,6 +124,9 @@ static void __init highbank_timer_init(void)
        sp804_clockevents_init(timer_base, irq, "timer0");
        twd_local_timer_of_register();
+        arch_timer_of_register();
+        arch_timer_sched_clock_init();
 }
 static struct sys_timer highbank_timer = {
@@ -145,7 +136,6 @@ static struct sys_timer highbank_timer = {
 static void highbank_power_off(void)
 {
        hignbank_set_pwr_shutdown();
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
        while (1)
                cpu_do_idle();
@@ -211,12 +201,13 @@ static void __init highbank_init(void)
 static const char *highbank_match[] __initconst = {
        "calxeda,highbank",
+        "calxeda,ecx-2000",
        NULL,
 };
 DT_MACHINE_START(HIGHBANK, "Highbank")
        .smp            = smp_ops(highbank_smp_ops),
-        .map_io         = highbank_map_io,
+        .map_io         = debug_ll_io_init,
        .init_irq       = highbank_init_irq,
        .timer          = &highbank_timer,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
index 2c1b8c3c8e45..7b60faccd551 100644
--- a/arch/arm/mach-highbank/hotplug.c
+++ b/arch/arm/mach-highbank/hotplug.c
@@ -14,13 +14,11 @@
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 #include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 #include "core.h"
+#include "sysregs.h"
 extern void secondary_startup(void);
@@ -33,7 +31,7 @@ void __ref highbank_cpu_die(unsigned int cpu)
        flush_cache_all();
        highbank_set_cpu_jump(cpu, secondary_startup);
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        highbank_set_core_pwr();
        cpu_do_idle();
diff --git a/arch/arm/mach-highbank/lluart.c b/arch/arm/mach-highbank/lluart.c
deleted file mode 100644
index 371575019f33..000000000000
--- a/arch/arm/mach-highbank/lluart.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2011 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
-#include <asm/mach/map.h>
-#define HB_DEBUG_LL_PHYS_BASE   0xfff36000
-#define HB_DEBUG_LL_VIRT_BASE   0xfee36000
-static struct map_desc lluart_io_desc __initdata = {
-        .virtual        = HB_DEBUG_LL_VIRT_BASE,
-        .pfn            = __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
-        .length         = SZ_4K,
-        .type           = MT_DEVICE,
-};
-void __init highbank_lluart_map_io(void)
-{
-        iotable_init(&lluart_io_desc, 1);
-}
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index fa9560ec6e70..1129957f6c1d 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -42,9 +42,7 @@ static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struc
 */
 static void __init highbank_smp_init_cpus(void)
 {
-        unsigned int i, ncores;
+        unsigned int i, ncores = 4;
-        ncores = scu_get_core_count(scu_base_addr);
        /* sanity check */
        if (ncores > NR_CPUS) {
@@ -65,7 +63,8 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 {
        int i;
-        scu_enable(scu_base_addr);
+        if (scu_base_addr)
+                scu_enable(scu_base_addr);
        /*
         * Write the address of secondary startup into the jump table
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
index de866f21331f..74aa135966f0 100644
--- a/arch/arm/mach-highbank/pm.c
+++ b/arch/arm/mach-highbank/pm.c
@@ -19,7 +19,6 @@
 #include <linux/suspend.h>
 #include <asm/proc-fns.h>
-#include <asm/smp_scu.h>
 #include <asm/suspend.h>
 #include "core.h"
@@ -35,8 +34,6 @@ static int highbank_pm_enter(suspend_state_t state)
 {
        hignbank_set_pwr_suspend();
        highbank_set_cpu_jump(0, cpu_resume);
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
        cpu_suspend(0, highbank_suspend_finish);
        return 0;
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
index 0e913389f445..e13e8ea7c6cb 100644
--- a/arch/arm/mach-highbank/sysregs.h
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -17,6 +17,10 @@
 #define _MACH_HIGHBANK__SYSREGS_H_
 #include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include "core.h"
 extern void __iomem *sregs_base;
@@ -29,24 +33,39 @@ extern void __iomem *sregs_base;
 #define HB_PWR_HARD_RESET               2
 #define HB_PWR_SHUTDOWN                 3
+#define SREG_CPU_PWR_CTRL(c)            (0x200 + ((c) * 4))
+static inline void highbank_set_core_pwr(void)
+{
+        int cpu = cpu_logical_map(smp_processor_id());
+        if (scu_base_addr)
+                scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
+        else
+                writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
+}
 static inline void hignbank_set_pwr_suspend(void)
 {
        writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 static inline void hignbank_set_pwr_shutdown(void)
 {
        writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 static inline void hignbank_set_pwr_soft_reset(void)
 {
        writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 static inline void hignbank_set_pwr_hard_reset(void)
 {
        writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+        highbank_set_core_pwr();
 }
 #endif
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 86e37cd9376c..aed96ad9bd4a 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -14,7 +14,6 @@
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 #include <linux/io.h>
-#include <asm/smp_scu.h>
 #include <asm/proc-fns.h>
 #include "core.h"
@@ -27,7 +26,6 @@ void highbank_restart(char mode, const char *cmd)
        else
                hignbank_set_pwr_soft_reset();
-        scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
        while (1)
                cpu_do_idle();
 }
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c
index 5c10ad05df74..134377352966 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/mach-imx/3ds_debugboard.c
@@ -21,7 +21,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
-#include <mach/hardware.h>
+#include "hardware.h"
 /* LAN9217 ethernet base address */
 #define LAN9217_BASE_ADDR(n)    (n + 0x0)
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/mach-imx/3ds_debugboard.h
index 9fd6cb3f8fad..9fd6cb3f8fad 100644
--- a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
+++ b/arch/arm/mach-imx/3ds_debugboard.h
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8d276584650e..1ad0d76de8c7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,3 +1,70 @@
+config ARCH_MXC
+        bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_PATCH_PHYS_VIRT
+        select AUTO_ZRELADDR if !ZBOOT_ROM
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          Support for Freescale MXC/iMX-based family of processors
+menu "Freescale i.MX support"
+        depends on ARCH_MXC
+config MXC_IRQ_PRIOR
+        bool "Use IRQ priority"
+        help
+          Select this if you want to use prioritized IRQ handling.
+          This feature prevents higher priority ISR to be interrupted
+          by lower priority IRQ even IRQF_DISABLED flag is not set.
+          This may be useful in embedded applications, where are strong
+          requirements for timing.
+          Say N here, unless you have a specialized requirement.
+config MXC_TZIC
+        bool
+config MXC_AVIC
+        bool
+config MXC_DEBUG_BOARD
+        bool "Enable MXC debug board(for 3-stack)"
+        help
+          The debug board is an integral part of the MXC 3-stack(PDK)
+          platforms, it can be attached or removed from the peripheral
+          board. On debug board, several debug devices(ethernet, UART,
+          buttons, LEDs and JTAG) are implemented. Between the MCU and
+          these devices, a CPLD is added as a bridge which performs
+          data/address de-multiplexing and decode, signal level shift,
+          interrupt control and various board functions.
+config HAVE_EPIT
+        bool
+config MXC_USE_EPIT
+        bool "Use EPIT instead of GPT"
+        depends on HAVE_EPIT
+        help
+          Use EPIT as the system timer on systems that have it. Normally you
+          don't have a reason to do so as the EPIT has the same features and
+          uses the same clocks as the GPT. Anyway, on some systems the GPT
+          may be in use for other purposes.
+config MXC_ULPI
+        bool
+config ARCH_HAS_RNGA
+        bool
+config IRAM_ALLOC
+        bool
+        select GENERIC_ALLOCATOR
 config HAVE_IMX_GPC
        bool
@@ -5,6 +72,12 @@ config HAVE_IMX_MMDC
        bool
 config HAVE_IMX_SRC
+        def_bool y if SMP
+config IMX_HAVE_IOMUX_V1
+        bool
+config ARCH_MXC_IOMUX_V3
        bool
 config ARCH_MX1
@@ -104,7 +177,7 @@ config	SOC_IMX51
        select PINCTRL_IMX51
        select SOC_IMX5
-if ARCH_IMX_V4_V5
+if ARCH_MULTI_V4T
 comment "MX1 platforms:"
 config MACH_MXLADS
@@ -133,6 +206,10 @@ config MACH_APF9328
        help
          Say Yes here if you are using the Armadeus APF9328 development board
+endif
+if ARCH_MULTI_V5
 comment "MX21 platforms:"
 config MACH_MX21ADS
@@ -195,6 +272,13 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
 endchoice
+config MACH_IMX25_DT
+        bool "Support i.MX25 platforms from device tree"
+        select SOC_IMX25
+        help
+          Include support for Freescale i.MX25 based platforms
+          using the device tree for discovery
 comment "MX27 platforms:"
 config MACH_MX27ADS
@@ -317,6 +401,7 @@ config MACH_IMX27_VISSTRIM_M10
        select IMX_HAVE_PLATFORM_IMX_SSI
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_MX2_CAMERA
+        select IMX_HAVE_PLATFORM_MX2_EMMA
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_MMC
        select LEDS_GPIO_REGISTER
@@ -384,7 +469,7 @@ config MACH_IMX27_DT
 endif
-if ARCH_IMX_V6_V7
+if ARCH_MULTI_V6
 comment "MX31 platforms:"
@@ -649,6 +734,10 @@ config MACH_VPR200
          Include support for VPR200 platform. This includes specific
          configurations for the board and its peripherals.
+endif
+if ARCH_MULTI_V7
 comment "i.MX5 platforms:"
 config MACH_MX50_RDP
@@ -739,6 +828,7 @@ config	SOC_IMX53
        select ARCH_MX5
        select ARCH_MX53
        select HAVE_CAN_FLEXCAN if CAN
+        select IMX_HAVE_PLATFORM_IMX2_WDT
        select PINCTRL
        select PINCTRL_IMX53
        select SOC_IMX5
@@ -748,7 +838,14 @@ config	SOC_IMX53
 config SOC_IMX6Q
        bool "i.MX6 Quad support"
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
+        select ARM_ERRATA_743622
+        select ARM_ERRATA_751472
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_764369 if SMP
+        select ARM_ERRATA_775420
        select ARM_GIC
        select COMMON_CLK
        select CPU_V7
@@ -756,13 +853,20 @@ config SOC_IMX6Q
        select HAVE_CAN_FLEXCAN if CAN
        select HAVE_IMX_GPC
        select HAVE_IMX_MMDC
-        select HAVE_IMX_SRC
        select HAVE_SMP
        select MFD_SYSCON
        select PINCTRL
        select PINCTRL_IMX6Q
+        select PL310_ERRATA_588369 if CACHE_PL310
+        select PL310_ERRATA_727915 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+        select PM_OPP if PM
        help
          This enables support for Freescale i.MX6 Quad processor.
 endif
+source "arch/arm/mach-imx/devices/Kconfig"
+endmenu
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 895754aeb4f3..0634b3152c24 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,3 +1,5 @@
+obj-y := time.o cpu.o system.o irq-common.o
 obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
@@ -15,6 +17,24 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(i
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                            clk-pfd.o clk-busy.o clk.o
+obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
+obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
+obj-$(CONFIG_MXC_TZIC) += tzic.o
+obj-$(CONFIG_MXC_AVIC) += avic.o
+obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
+obj-$(CONFIG_MXC_ULPI) += ulpi.o
+obj-$(CONFIG_MXC_USE_EPIT) += epit.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
+obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
+obj-$(CONFIG_CPU_IDLE) += cpuidle.o
+ifdef CONFIG_SND_IMX_SOC
+obj-y += ssi-fiq.o
+obj-y += ssi-fiq-ksym.o
+endif
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -30,6 +50,7 @@ obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
 obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
+obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
 # i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
@@ -89,3 +110,5 @@ obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
+obj-y += devices/
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/mach-imx/avic.c
index cbd55c36def3..0eff23ed92b9 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -22,12 +22,11 @@
 #include <linux/irqdomain.h>
 #include <linux/io.h>
 #include <linux/of.h>
-#include <mach/common.h>
 #include <asm/mach/irq.h>
 #include <asm/exception.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include "common.h"
+#include "hardware.h"
 #include "irq-common.h"
 #define AVIC_INTCNTL            0x00    /* int control reg */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/mach-imx/board-mx31lilly.h
index 0df71bfefbb1..0df71bfefbb1 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/mach-imx/board-mx31lilly.h
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/mach-imx/board-mx31lite.h
index c1ad0ae807cc..c1ad0ae807cc 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/mach-imx/board-mx31lite.h
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/mach-imx/board-mx31moboard.h
index de14543891cf..de14543891cf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/mach-imx/board-mx31moboard.h
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/mach-imx/board-pcm038.h
index 6f371e35753d..6f371e35753d 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/mach-imx/board-pcm038.h
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 516ddee1948e..15f9d223cf0b 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -22,9 +22,9 @@
 #include <linux/clkdev.h>
 #include <linux/err.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
 #include "clk.h"
+#include "common.h"
+#include "hardware.h"
 /* CCM register addresses */
 #define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
@@ -82,7 +82,8 @@ int __init mx1_clocks_init(unsigned long fref)
                        pr_err("imx1 clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));
-        clk_register_clkdev(clk[dma_gate], "ahb", "imx-dma");
+        clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
+        clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
        clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
        clk_register_clkdev(clk[mma_gate], "mma", NULL);
        clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
@@ -94,18 +95,18 @@ int __init mx1_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
        clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
-        clk_register_clkdev(clk[hclk], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
        clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
        clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
        clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
-        clk_register_clkdev(clk[per2], "per", "imx-fb.0");
+        clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
        clk_register_clkdev(clk[hclk], "mshc", NULL);
        clk_register_clkdev(clk[per3], "ssi", NULL);
-        clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
+        clk_register_clkdev(clk[clk32], NULL, "imx1-rtc.0");
        clk_register_clkdev(clk[clko], "clko", NULL);
        mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index cf65148bc519..d7ed66091a2a 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -25,9 +25,9 @@
 #include <linux/module.h>
 #include <linux/err.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
 #include "clk.h"
+#include "common.h"
+#include "hardware.h"
 #define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
@@ -156,16 +156,16 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
        clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
-        clk_register_clkdev(clk[per3], "per", "imx-fb.0");
+        clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
        clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
        clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
-        clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
-        clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
+        clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
-        clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
+        clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
        clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
        clk_register_clkdev(clk[brom_gate], "brom", NULL);
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 01e2f843bf2e..b197aa73dc4b 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -23,11 +23,14 @@
 #include <linux/io.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/mx25.h>
 #include "clk.h"
+#include "common.h"
+#include "hardware.h"
+#include "mx25.h"
 #define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
@@ -55,6 +58,8 @@
 #define ccm(x)  (CRM_BASE + (x))
+static struct clk_onecell_data clk_data;
 static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
 static const char *per_sel_clks[] = { "ahb", "upll", };
@@ -64,24 +69,30 @@ enum mx25_clks {
        per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
        per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
        per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
-        csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per,
+        csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per,
-        lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per,
+        gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per,
-        csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb,
+        pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per,
-        usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg,
+        uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb,
-        cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg,
+        esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb,
-        kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg,
+        reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg,
-        ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg,
+        cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg,
-        uart4_ipg, uart5_ipg, wdt_ipg, clk_max
+        reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9,
+        gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12,
+        iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg,
+        pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
+        sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
+        uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
+        wdt_ipg, clk_max
 };
 static struct clk *clk[clk_max];
-int __init mx25_clocks_init(void)
+static int __init __mx25_clocks_init(unsigned long osc_rate)
 {
        int i;
        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[osc] = imx_clk_fixed("osc", 24000000);
+        clk[osc] = imx_clk_fixed("osc", osc_rate);
        clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
        clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
        clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
@@ -123,22 +134,36 @@ int __init mx25_clocks_init(void)
        clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
        clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
        clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
+        clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0),  1);
+        clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0),  2);
        clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0),  3);
        clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0),  4);
        clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0),  5);
        clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0),  6);
        clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0),  7);
        clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0),  8);
+        clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0),  9);
+        clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0),  10);
+        clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0),  11);
+        clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0),  12);
        clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
        clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
        clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
+        clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16);
+        /* CCM_CGCR0(17): reserved */
        clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
+        clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19);
+        clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20);
        clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
        clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
        clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
        clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
+        clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25);
        clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
+        clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27);
        clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
+        /* CCM_CGCR0(29-31): reserved */
+        /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */
        clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1),  2);
        clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1),  3);
        clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1),  4);
@@ -146,17 +171,41 @@ int __init mx25_clocks_init(void)
        clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1),  6);
        clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1),  7);
        clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1),  8);
+        clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1),  9);
+        clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1),  10);
+        clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1),  11);
+        /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */
        clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
        clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
        clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
+        /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */
+        /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */
+        /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */
+        clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19);
+        clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20);
+        clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21);
+        clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22);
+        /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */
+        /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */
+        /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */
        clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
+        /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */
+        /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */
        clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
        clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
+        /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */
        clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
        clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2),  0);
        clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2),  1);
        clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2),  2);
+        clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2),  3);
+        /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */
+        clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2),  5);
        clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2),  6);
+        clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2),  7);
+        clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2),  8);
+        clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2),  9);
+        clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2),  10);
        clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
        clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
        clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
@@ -165,6 +214,7 @@ int __init mx25_clocks_init(void)
        clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
        clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
        clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
+        /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
        clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
        for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -172,6 +222,18 @@ int __init mx25_clocks_init(void)
                        pr_err("i.MX25 clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));
+        clk_prepare_enable(clk[emi_ahb]);
+        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+        return 0;
+}
+int __init mx25_clocks_init(void)
+{
+        __mx25_clocks_init(24000000);
        /* i.mx25 has the i.mx21 type uart */
        clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
@@ -183,8 +245,6 @@ int __init mx25_clocks_init(void)
        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
        clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
        clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
        clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
        clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
@@ -197,7 +257,7 @@ int __init mx25_clocks_init(void)
        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
        clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
-        clk_register_clkdev(clk[nfc_ipg_per], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
        /* i.mx25 has the i.mx35 type cspi */
        clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
        clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
@@ -212,15 +272,15 @@ int __init mx25_clocks_init(void)
        clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
        clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
        clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
        clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
        clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
        clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
-        clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
        clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
        clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
        clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
@@ -230,9 +290,9 @@ int __init mx25_clocks_init(void)
        clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
        clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
        clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
-        clk_register_clkdev(clk[csi_ipg_per], "per", "mx2-camera.0");
+        clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ipg], "ipg", "mx2-camera.0");
+        clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
-        clk_register_clkdev(clk[csi_ahb], "ahb", "mx2-camera.0");
+        clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
        clk_register_clkdev(clk[dummy], "audmux", NULL);
        clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
        clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
@@ -242,5 +302,40 @@ int __init mx25_clocks_init(void)
        clk_register_clkdev(clk[iim_ipg], "iim", NULL);
        mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
+        return 0;
+}
+int __init mx25_clocks_init_dt(void)
+{
+        struct device_node *np;
+        void __iomem *base;
+        int irq;
+        unsigned long osc_rate = 24000000;
+        /* retrieve the freqency of fixed clocks from device tree */
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                u32 rate;
+                if (of_property_read_u32(np, "clock-frequency", &rate))
+                        continue;
+                if (of_device_is_compatible(np, "fsl,imx-osc"))
+                        osc_rate = rate;
+        }
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        __mx25_clocks_init(osc_rate);
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(base, irq);
        return 0;
 }
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 366e5d59d886..4c1d1e4efc74 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -6,9 +6,9 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
 #include "clk.h"
+#include "common.h"
+#include "hardware.h"
 #define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
@@ -51,8 +51,10 @@
 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
+static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
+static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
 static const char *clko_sel_clks[] = {
-        "ckil", "prem", "ckih", "ckih",
+        "ckil", "fpm", "ckih", "ckih",
        "ckih", "mpll", "spll", "cpu_div",
        "ahb", "ipg", "per1_div", "per2_div",
        "per3_div", "per4_div", "ssi1_div", "ssi2_div",
@@ -79,7 +81,8 @@ enum mx27_clks {
        vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
        csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
        uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
-        uart2_ipg_gate, uart1_ipg_gate, clk_max
+        uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
+        mpll_sel, clk_max
 };
 static struct clk *clk[clk_max];
@@ -91,7 +94,15 @@ int __init mx27_clocks_init(unsigned long fref)
        clk[dummy] = imx_clk_fixed("dummy", 0);
        clk[ckih] = imx_clk_fixed("ckih", fref);
        clk[ckil] = imx_clk_fixed("ckil", 32768);
-        clk[mpll] = imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
+        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
+        clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
+        clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
+                        mpll_osc_sel_clks,
+                        ARRAY_SIZE(mpll_osc_sel_clks));
+        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
+                        ARRAY_SIZE(mpll_sel_clks));
+        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
        clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
        clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
@@ -211,19 +222,20 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
        clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
-        clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.0");
+        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
-        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "mxc-mmc.0");
+        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
-        clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.1");
+        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.1");
+        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
-        clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.2");
+        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.2");
+        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
        clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
        clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
        clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
-        clk_register_clkdev(clk[per3_gate], "per", "imx-fb.0");
+        clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx-fb.0");
+        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[csi_ahb_gate], "ahb", "mx2-camera.0");
+        clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
+        clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
        clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
@@ -238,27 +250,27 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
        clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
-        clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
+        clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
-        clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma");
+        clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
        clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
        clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
        clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
        clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
        clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
-        clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "mx2-camera.0");
+        clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
-        clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "mx2-camera.0");
+        clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
        clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
        clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
        clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
        clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
-        clk_register_clkdev(clk[rtc_ipg_gate], NULL, "mxc_rtc");
+        clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
        clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
        clk_register_clkdev(clk[cpu_div], "cpu", NULL);
        clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 1253af2d9971..8be64e0a4ace 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -22,12 +22,11 @@
 #include <linux/err.h>
 #include <linux/of.h>
-#include <mach/hardware.h>
-#include <mach/mx31.h>
-#include <mach/common.h>
 #include "clk.h"
+#include "common.h"
 #include "crmregs-imx3.h"
+#include "hardware.h"
+#include "mx31.h"
 static const char *mcu_main_sel[] = { "spll", "mpll", };
 static const char *per_sel[] = { "per_div", "ipg", };
@@ -124,10 +123,10 @@ int __init mx31_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
        clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[rtc_gate], NULL, "mxc_rtc");
+        clk_register_clkdev(clk[rtc_gate], NULL, "imx21-rtc");
        clk_register_clkdev(clk[epit1_gate], "epit", NULL);
        clk_register_clkdev(clk[epit2_gate], "epit", NULL);
-        clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
        clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
        clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
@@ -155,12 +154,12 @@ int __init mx31_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
        clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
        clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[sdhc1_gate], NULL, "mxc-mmc.0");
+        clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
-        clk_register_clkdev(clk[sdhc2_gate], NULL, "mxc-mmc.1");
+        clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
        clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
        clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
        clk_register_clkdev(clk[firi_gate], "firi", NULL);
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 177259b523cd..66f3d65ea275 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -14,11 +14,10 @@
 #include <linux/of.h>
 #include <linux/err.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
 #include "crmregs-imx3.h"
 #include "clk.h"
+#include "common.h"
+#include "hardware.h"
 struct arm_ahb_div {
        unsigned char arm, ahb, sel;
@@ -226,9 +225,9 @@ int __init mx35_clocks_init()
        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
        clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
        clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
@@ -256,7 +255,7 @@ int __init mx35_clocks_init()
        clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
        clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
        clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
        clk_prepare_enable(clk[spba_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a0bf84803eac..e8c0473c7568 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -14,11 +14,10 @@
 #include <linux/of.h>
 #include <linux/err.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
 #include "crm-regs-imx5.h"
 #include "clk.h"
+#include "common.h"
+#include "hardware.h"
 /* Low-power Audio Playback Mode clock */
 static const char *lp_apm_sel[] = { "osc", };
@@ -88,6 +87,7 @@ enum imx5_clks {
 };
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
                unsigned long rate_osc, unsigned long rate_ckih1,
@@ -258,8 +258,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
        clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
        clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
-        clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+        clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+        clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
@@ -272,7 +272,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
        clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
        clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
-        clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
+        clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
@@ -306,6 +306,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk_prepare_enable(clk[spba]);
        clk_prepare_enable(clk[emi_fast_gate]); /* fec */
        clk_prepare_enable(clk[emi_slow_gate]); /* eim */
+        clk_prepare_enable(clk[mipi_hsc1_gate]);
+        clk_prepare_enable(clk[mipi_hsc2_gate]);
+        clk_prepare_enable(clk[mipi_esc_gate]);
+        clk_prepare_enable(clk[mipi_hsp_gate]);
        clk_prepare_enable(clk[tmax1]);
        clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
        clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
@@ -315,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                        unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
        int i;
+        struct device_node *np;
        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
@@ -343,16 +348,20 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                        pr_err("i.MX51 clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
-        clk_register_clkdev(clk[hsi2c_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
        clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
        clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
        clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -366,10 +375,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
        /* set the usboh3 parent to pll2_sw */
        clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -393,6 +398,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 {
        int i;
        unsigned long r;
+        struct device_node *np;
        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -437,15 +443,20 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                        pr_err("i.MX53 clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
        clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
-        clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+        clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
        clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+        clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
        clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
@@ -459,14 +470,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
-        clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
-        clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
-        clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
-        clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
-        clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
        /* set SDHC root clock to 200MHZ*/
        clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 3ec242f3341e..7f2c10c7413a 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -19,8 +19,9 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <mach/common.h>
 #include "clk.h"
+#include "common.h"
 #define CCGR0                           0x68
 #define CCGR1                           0x6c
@@ -104,7 +105,7 @@ static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m"
 static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
 static const char *ipu_sels[]           = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
-static const char *ldb_di_sels[]        = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *ldb_di_sels[]        = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_pfd1_540m", };
 static const char *ipu_di_pre_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
 static const char *ipu1_di0_sels[]      = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
 static const char *ipu1_di1_sels[]      = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
@@ -151,8 +152,9 @@ enum mx6q_clks {
        gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
        ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
        usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
-        pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
+        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
+        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
        clk_max
 };
@@ -163,6 +165,13 @@ static enum mx6q_clks const clks_init_on[] __initconst = {
        mmdc_ch0_axi, rom,
 };
+static struct clk_div_table clk_enet_ref_table[] = {
+        { .val = 0, .div = 20, },
+        { .val = 1, .div = 10, },
+        { .val = 2, .div = 5, },
+        { .val = 3, .div = 4, },
+};
 int __init mx6q_clocks_init(void)
 {
        struct device_node *np;
@@ -189,19 +198,29 @@ int __init mx6q_clocks_init(void)
        base = of_iomap(np, 0);
        WARN_ON(!base);
-        /*                   type                               name         parent_name  base     gate_mask div_mask */
+        /*                   type                               name         parent_name  base     div_mask */
-        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x2000,   0x7f);
+        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x7f);
-        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x2000,   0x1);
+        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x1);
-        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x2000,   0x3);
+        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x3);
-        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x2000,   0x7f);
+        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x7f);
-        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x2000,   0x7f);
+        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
-        clk[pll6_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll6_mlb",     "osc", base + 0xd0, 0x2000,   0x0);
+        clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
-        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x2000,   0x3);
+        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
-        clk[pll8_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll8_enet",    "osc", base + 0xe0, 0x182000, 0x3);
+        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
+        clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+        clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+        clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+        clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+        clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+                        base + 0xe0, 0, 2, 0, clk_enet_ref_table,
+                        &imx_ccm_lock);
        /*                                name              parent_name        reg       idx */
        clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
        clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
@@ -357,7 +376,7 @@ int __init mx6q_clocks_init(void)
        clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
        clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
        clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-        clk[mlb]          = imx_clk_gate2("mlb",           "pll6_mlb",          base + 0x74, 18);
+        clk[mlb]          = imx_clk_gate2("mlb",           "pll8_mlb",          base + 0x74, 18);
        clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
        clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
        clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
@@ -405,6 +424,7 @@ int __init mx6q_clocks_init(void)
        clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
        clk_register_clkdev(clk[ahb], "ahb", NULL);
        clk_register_clkdev(clk[cko1], "cko1", NULL);
+        clk_register_clkdev(clk[arm], NULL, "cpu0");
        /*
         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 02be73178912..abff350ba24c 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -4,10 +4,10 @@
 #include <linux/slab.h>
 #include <linux/kernel.h>
 #include <linux/err.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
 #include "clk.h"
+#include "common.h"
+#include "hardware.h"
 /**
 * pll v1
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 36aac947bce1..d09bc3df9a7a 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -31,7 +31,6 @@
 * @clk_hw:      clock source
 * @base:        base address of PLL registers
 * @powerup_set: set POWER bit to power up the PLL
- * @gate_mask:   mask of gate bits
 * @div_mask:    mask of divider bits
 *
 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
@@ -41,7 +40,6 @@ struct clk_pllv3 {
        struct clk_hw   hw;
        void __iomem    *base;
        bool            powerup_set;
-        u32             gate_mask;
        u32             div_mask;
 };
@@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw)
        u32 val;
        val = readl_relaxed(pll->base);
-        val |= pll->gate_mask;
+        val |= BM_PLL_ENABLE;
        writel_relaxed(val, pll->base);
        return 0;
@@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw)
        u32 val;
        val = readl_relaxed(pll->base);
-        val &= ~pll->gate_mask;
+        val &= ~BM_PLL_ENABLE;
        writel_relaxed(val, pll->base);
 }
@@ -287,66 +285,7 @@ static const struct clk_ops clk_pllv3_av_ops = {
 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
                                                unsigned long parent_rate)
 {
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
+        return 500000000;
-        u32 div = readl_relaxed(pll->base) & pll->div_mask;
-        switch (div) {
-        case 0:
-                return 25000000;
-        case 1:
-                return 50000000;
-        case 2:
-                return 100000000;
-        case 3:
-                return 125000000;
-        }
-        return 0;
-}
-static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
-                                      unsigned long *prate)
-{
-        if (rate >= 125000000)
-                rate = 125000000;
-        else if (rate >= 100000000)
-                rate = 100000000;
-        else if (rate >= 50000000)
-                rate = 50000000;
-        else
-                rate = 25000000;
-        return rate;
-}
-static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        u32 val, div;
-        switch (rate) {
-        case 25000000:
-                div = 0;
-                break;
-        case 50000000:
-                div = 1;
-                break;
-        case 100000000:
-                div = 2;
-                break;
-        case 125000000:
-                div = 3;
-                break;
-        default:
-                return -EINVAL;
-        }
-        val = readl_relaxed(pll->base);
-        val &= ~pll->div_mask;
-        val |= div;
-        writel_relaxed(val, pll->base);
-        return 0;
 }
 static const struct clk_ops clk_pllv3_enet_ops = {
@@ -355,8 +294,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
        .enable         = clk_pllv3_enable,
        .disable        = clk_pllv3_disable,
        .recalc_rate    = clk_pllv3_enet_recalc_rate,
-        .round_rate     = clk_pllv3_enet_round_rate,
-        .set_rate       = clk_pllv3_enet_set_rate,
 };
 static const struct clk_ops clk_pllv3_mlb_ops = {
@@ -368,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                          const char *parent_name, void __iomem *base,
-                          u32 gate_mask, u32 div_mask)
+                          u32 div_mask)
 {
        struct clk_pllv3 *pll;
        const struct clk_ops *ops;
@@ -400,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                ops = &clk_pllv3_ops;
        }
        pll->base = base;
-        pll->gate_mask = gate_mask;
        pll->div_mask = div_mask;
        init.name = name;
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 5f2d8acca25f..9d1f3b99d1d3 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -22,8 +22,7 @@ enum imx_pllv3_type {
 };
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-                const char *parent_name, void __iomem *base, u32 gate_mask,
+                const char *parent_name, void __iomem *base, u32 div_mask);
-                u32 div_mask);
 struct clk *clk_register_gate2(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/mach-imx/common.h
index ead901814c0d..7191ab4434e5 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -66,6 +66,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                        unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                        unsigned long ckih1, unsigned long ckih2);
+extern int mx25_clocks_init_dt(void);
 extern int mx27_clocks_init_dt(void);
 extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
@@ -79,6 +80,7 @@ extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
 extern void imx_set_aips(void __iomem *);
+extern int mxc_device_init(void);
 enum mxc_cpu_pwr_mode {
        WAIT_CLOCKED,           /* wfi only */
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
index 6914bcbf84e4..96ec64b5ff7d 100644
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -11,8 +11,9 @@
 */
 #include <linux/module.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/iim.h>
+#include "iim.h"
+#include "hardware.h"
 static int mx25_cpu_rev = -1;
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index ff38e1505f67..fe8d36f7e30e 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -24,7 +24,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
-#include <mach/hardware.h>
+#include "hardware.h"
 static int mx27_cpu_rev = -1;
 static int mx27_cpu_partnumber;
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index 3f2345f0cdaf..fde1860a2521 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -11,9 +11,10 @@
 #include <linux/module.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/iim.h>
+#include "common.h"
-#include <mach/common.h>
+#include "hardware.h"
+#include "iim.h"
 static int mx31_cpu_rev = -1;
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
index 846e46eb8cbf..ec3aaa098c17 100644
--- a/arch/arm/mach-imx/cpu-imx35.c
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -10,8 +10,9 @@
 */
 #include <linux/module.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/iim.h>
+#include "hardware.h"
+#include "iim.h"
 static int mx35_cpu_rev = -1;
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 8eb15a2fcaf9..d88760014ff9 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -15,9 +15,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
-#include <mach/hardware.h>
 #include <linux/io.h>
+#include "hardware.h"
 static int mx5_cpu_rev = -1;
 #define IIM_SREV 0x24
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/mach-imx/cpu.c
index 220dd6f93126..03fcbd082593 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -1,7 +1,8 @@
 #include <linux/module.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
+#include "hardware.h"
 unsigned int __mxc_cpu_type;
 EXPORT_SYMBOL(__mxc_cpu_type);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
index 7b92cd6da6d3..b9ef692b61a2 100644
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ b/arch/arm/mach-imx/cpu_op-mx51.c
@@ -13,9 +13,10 @@
 #include <linux/bug.h>
 #include <linux/types.h>
-#include <mach/hardware.h>
 #include <linux/kernel.h>
+#include "hardware.h"
 static struct cpu_op mx51_cpu_op[] = {
        {
        .cpu_rate = 160000000,},
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index b5b6f8083130..36e8b3994470 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -22,7 +22,8 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/slab.h>
-#include <mach/hardware.h>
+#include "hardware.h"
 #define CLK32_FREQ      32768
 #define NANOSECOND      (1000 * 1000 * 1000)
diff --git a/arch/arm/plat-mxc/cpuidle.c b/arch/arm/mach-imx/cpuidle.c
index d4cb511a44a8..d4cb511a44a8 100644
--- a/arch/arm/plat-mxc/cpuidle.c
+++ b/arch/arm/mach-imx/cpuidle.c
diff --git a/arch/arm/plat-mxc/include/mach/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index bc932d1af372..bc932d1af372 100644
--- a/arch/arm/plat-mxc/include/mach/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index 3aad1e70de96..f9b5afc6bcd1 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -6,8 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/mx1.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_imx_fb_data imx1_imx_fb_data;
 #define imx1_add_imx_fb(pdata) \
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 93ece55f75df..bd9393280159 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -6,8 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/mx21.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
 #define imx21_add_imx21_hcd(pdata)      \
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index f8e03dd1f116..0d2922bc575c 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -6,8 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/mx25.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_fec_data imx25_fec_data;
 #define imx25_add_fec(pdata)    \
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 04822932cdd1..130962519751 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -6,8 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/mx27.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_fec_data imx27_fec_data;
 #define imx27_add_fec(pdata)    \
@@ -54,8 +53,10 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
 extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
        imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
+extern const struct imx_mx2_emma_data imx27_mx2_emmaprp_data;
 #define imx27_add_mx2_emmaprp() \
-        imx_add_mx2_emmaprp(&imx27_mx2_camera_data)
+        imx_add_mx2_emmaprp(&imx27_mx2_emmaprp_data)
 extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
 #define imx27_add_mxc_ehci_otg(pdata)   \
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index 8b2ceb45bb83..e8d1611bbc8e 100644
--- a/arch/arm/mach-imx/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -6,8 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/mx31.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
 #define imx31_add_fsl_usb2_udc(pdata)   \
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index c3e9f206ac2b..e2675f1b141c 100644
--- a/arch/arm/mach-imx/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -6,8 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/mx35.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_fec_data imx35_fec_data;
 #define imx35_add_fec(pdata)    \
diff --git a/arch/arm/mach-imx/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h
index 7216667eaafc..2c290391f298 100644
--- a/arch/arm/mach-imx/devices-imx50.h
+++ b/arch/arm/mach-imx/devices-imx50.h
@@ -18,8 +18,7 @@
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */
-#include <mach/mx50.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
 #define imx50_add_imx_uart(id, pdata)   \
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index 9f1718725195..deee5baee88c 100644
--- a/arch/arm/mach-imx/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
@@ -6,8 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/mx51.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
 extern const struct imx_fec_data imx51_fec_data;
 #define imx51_add_fec(pdata)    \
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index a35d9841f494..9a8f1ca7bcb1 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -56,6 +56,9 @@ config IMX_HAVE_PLATFORM_MX1_CAMERA
 config IMX_HAVE_PLATFORM_MX2_CAMERA
        bool
+config IMX_HAVE_PLATFORM_MX2_EMMA
+        bool
 config IMX_HAVE_PLATFORM_MXC_EHCI
        bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 76f3195475d0..6acf37e0c119 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -1,3 +1,5 @@
+obj-y := devices.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
@@ -28,3 +30,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) +=  platform-ahci-imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index eaf79d220c9a..6277baf1b7be 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -108,6 +108,7 @@ struct platform_device *__init imx_add_imxdi_rtc(
 #include <linux/platform_data/video-imxfb.h>
 struct imx_imx_fb_data {
+        const char *devid;
        resource_size_t iobase;
        resource_size_t iosize;
        resource_size_t irq;
@@ -118,6 +119,7 @@ struct platform_device *__init imx_add_imx_fb(
 #include <linux/platform_data/i2c-imx.h>
 struct imx_imx_i2c_data {
+        const char *devid;
        int id;
        resource_size_t iobase;
        resource_size_t iosize;
@@ -219,6 +221,7 @@ struct platform_device *__init imx_add_mx1_camera(
 #include <linux/platform_data/camera-mx2.h>
 struct imx_mx2_camera_data {
+        const char *devid;
        resource_size_t iobasecsi;
        resource_size_t iosizecsi;
        resource_size_t irqcsi;
@@ -229,8 +232,15 @@ struct imx_mx2_camera_data {
 struct platform_device *__init imx_add_mx2_camera(
                const struct imx_mx2_camera_data *data,
                const struct mx2_camera_platform_data *pdata);
+struct imx_mx2_emma_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
 struct platform_device *__init imx_add_mx2_emmaprp(
-                const struct imx_mx2_camera_data *data);
+                const struct imx_mx2_emma_data *data);
 #include <linux/platform_data/usb-ehci-mxc.h>
 struct imx_mxc_ehci_data {
@@ -244,6 +254,7 @@ struct platform_device *__init imx_add_mxc_ehci(
 #include <linux/platform_data/mmc-mxcmmc.h>
 struct imx_mxc_mmc_data {
+        const char *devid;
        int id;
        resource_size_t iobase;
        resource_size_t iosize;
@@ -256,6 +267,7 @@ struct platform_device *__init imx_add_mxc_mmc(
 #include <linux/platform_data/mtd-mxc_nand.h>
 struct imx_mxc_nand_data {
+        const char *devid;
        /*
         * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
         * machines but don't change existing devices as the nand device usually
@@ -290,6 +302,7 @@ struct platform_device *__init imx_add_mxc_pwm(
 /* mxc_rtc */
 struct imx_mxc_rtc_data {
+        const char *devid;
        resource_size_t iobase;
        resource_size_t irq;
 };
@@ -326,7 +339,8 @@ struct platform_device *__init imx_add_spi_imx(
                const struct imx_spi_imx_data *data,
                const struct spi_imx_master *pdata);
-struct platform_device *imx_add_imx_dma(void);
+struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
+                                        int irq, int irq_err);
 struct platform_device *imx_add_imx_sdma(char *name,
        resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/mach-imx/devices/devices.c
index 4d55a7a26e98..1b37482407f9 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/mach-imx/devices/devices.c
@@ -21,7 +21,6 @@
 #include <linux/init.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
-#include <mach/common.h>
 struct device mxc_aips_bus = {
        .init_name      = "mxc_aips",
@@ -33,7 +32,7 @@ struct device mxc_ahb_bus = {
        .parent         = &platform_bus,
 };
-static int __init mxc_device_init(void)
+int __init mxc_device_init(void)
 {
        int ret;
@@ -46,4 +45,3 @@ static int __init mxc_device_init(void)
 done:
        return ret;
 }
-core_initcall(mxc_device_init);
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/mach-imx/devices/platform-ahci-imx.c
index ade4a1c4e2a3..3d87dd9c284a 100644
--- a/arch/arm/plat-mxc/devices/platform-ahci-imx.c
+++ b/arch/arm/mach-imx/devices/platform-ahci-imx.c
@@ -24,8 +24,9 @@
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_ahci_imx_data_entry_single(soc, _devid)             \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index 0bae44e890db..2cb188ad9a0a 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -8,8 +8,9 @@
 */
 #include <linux/dma-mapping.h>
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_fec_data_entry_single(soc, _devid)                          \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/mach-imx/devices/platform-flexcan.c
index 4e8497af2eb1..1078bf0a94ef 100644
--- a/arch/arm/plat-mxc/devices/platform-flexcan.c
+++ b/arch/arm/mach-imx/devices/platform-flexcan.c
@@ -5,8 +5,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 848038f301fd..37e44398197b 100644
--- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -7,8 +7,9 @@
 * Free Software Foundation.
 */
 #include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_fsl_usb2_udc_data_entry_single(soc)                         \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-gpio-mxc.c b/arch/arm/mach-imx/devices/platform-gpio-mxc.c
index a7919a241032..26483fa94b75 100644
--- a/arch/arm/plat-mxc/devices/platform-gpio-mxc.c
+++ b/arch/arm/mach-imx/devices/platform-gpio-mxc.c
@@ -6,7 +6,7 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/devices-common.h>
+#include "devices-common.h"
 struct platform_device *__init mxc_register_gpio(char *name, int id,
        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high)
diff --git a/arch/arm/plat-mxc/devices/platform-gpio_keys.c b/arch/arm/mach-imx/devices/platform-gpio_keys.c
index 1c53a532ea0e..486282539c76 100644
--- a/arch/arm/plat-mxc/devices/platform-gpio_keys.c
+++ b/arch/arm/mach-imx/devices/platform-gpio_keys.c
@@ -16,8 +16,9 @@
 * Boston, MA  02110-1301, USA.
 */
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 struct platform_device *__init imx_add_gpio_keys(
                const struct gpio_keys_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/mach-imx/devices/platform-imx-dma.c
index 7fa7e9c92468..ccdb5dc4ddbd 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/mach-imx/devices/platform-imx-dma.c
@@ -6,12 +6,29 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/devices-common.h>
+#include "devices-common.h"
-struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
+struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name,
+        resource_size_t iobase, int irq, int irq_err)
 {
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = irq_err,
+                        .end = irq_err,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
        return platform_device_register_resndata(&mxc_ahb_bus,
-                        "imx-dma", -1, NULL, 0, NULL, 0);
+                        name, -1, res, ARRAY_SIZE(res), NULL, 0);
 }
 struct platform_device __init __maybe_unused *imx_add_imx_sdma(char *name,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index 2b0b5e0aa998..10b0ed39f07f 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -7,11 +7,13 @@
 * Free Software Foundation.
 */
 #include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
-#define imx_imx_fb_data_entry_single(soc, _size)                        \
+#include "../hardware.h"
+#include "devices-common.h"
+#define imx_imx_fb_data_entry_single(soc, _devid, _size)                \
        {                                                               \
+                .devid = _devid,                                        \
                .iobase = soc ## _LCDC_BASE_ADDR,                       \
                .iosize = _size,                                        \
                .irq = soc ## _INT_LCDC,                                \
@@ -19,22 +21,22 @@
 #ifdef CONFIG_SOC_IMX1
 const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX1, SZ_4K);
+        imx_imx_fb_data_entry_single(MX1, "imx1-fb", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX1 */
 #ifdef CONFIG_SOC_IMX21
 const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX21, SZ_4K);
+        imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 #ifdef CONFIG_SOC_IMX25
 const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX25, SZ_16K);
+        imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K);
 #endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
-        imx_imx_fb_data_entry_single(MX27, SZ_4K);
+        imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX27 */
 struct platform_device *__init imx_add_imx_fb(
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 19ad580c0be3..8e30e5703cd2 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -6,34 +6,35 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
-#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)           \
+#define imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)   \
        {                                                               \
+                .devid = _devid,                                        \
                .id = _id,                                              \
                .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR,           \
                .iosize = _size,                                        \
                .irq = soc ## _INT_I2C ## _hwid,                        \
        }
-#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size)                  \
+#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size)          \
-        [_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)
+        [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)
 #ifdef CONFIG_SOC_IMX1
 const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
-        imx_imx_i2c_data_entry_single(MX1, 0, , SZ_4K);
+        imx_imx_i2c_data_entry_single(MX1, "imx1-i2c", 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX1 */
 #ifdef CONFIG_SOC_IMX21
 const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
-        imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
+        imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 #ifdef CONFIG_SOC_IMX25
 const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
 #define imx25_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
+        imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K)
        imx25_imx_i2c_data_entry(0, 1),
        imx25_imx_i2c_data_entry(1, 2),
        imx25_imx_i2c_data_entry(2, 3),
@@ -43,7 +44,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
 #define imx27_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx_imx_i2c_data_entry(MX27, "imx21-i2c", _id, _hwid, SZ_4K)
        imx27_imx_i2c_data_entry(0, 1),
        imx27_imx_i2c_data_entry(1, 2),
 };
@@ -52,7 +53,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX31
 const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
 #define imx31_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
+        imx_imx_i2c_data_entry(MX31, "imx21-i2c", _id, _hwid, SZ_4K)
        imx31_imx_i2c_data_entry(0, 1),
        imx31_imx_i2c_data_entry(1, 2),
        imx31_imx_i2c_data_entry(2, 3),
@@ -62,7 +63,7 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX35
 const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 #define imx35_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
+        imx_imx_i2c_data_entry(MX35, "imx21-i2c", _id, _hwid, SZ_4K)
        imx35_imx_i2c_data_entry(0, 1),
        imx35_imx_i2c_data_entry(1, 2),
        imx35_imx_i2c_data_entry(2, 3),
@@ -72,7 +73,7 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX50
 const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
 #define imx50_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX50, _id, _hwid, SZ_4K)
+        imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K)
        imx50_imx_i2c_data_entry(0, 1),
        imx50_imx_i2c_data_entry(1, 2),
        imx50_imx_i2c_data_entry(2, 3),
@@ -82,10 +83,11 @@ const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX51
 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
 #define imx51_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
+        imx_imx_i2c_data_entry(MX51, "imx21-i2c", _id, _hwid, SZ_4K)
        imx51_imx_i2c_data_entry(0, 1),
        imx51_imx_i2c_data_entry(1, 2),
        {
+                .devid = "imx21-i2c",
                .id = 2,
                .iobase = MX51_HSI2C_DMA_BASE_ADDR,
                .iosize = SZ_16K,
@@ -97,7 +99,7 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX53
 const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
 #define imx53_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K)
+        imx_imx_i2c_data_entry(MX53, "imx21-i2c", _id, _hwid, SZ_4K)
        imx53_imx_i2c_data_entry(0, 1),
        imx53_imx_i2c_data_entry(1, 2),
        imx53_imx_i2c_data_entry(2, 3),
@@ -120,7 +122,7 @@ struct platform_device *__init imx_add_imx_i2c(
                },
        };
-        return imx_add_platform_device("imx-i2c", data->id,
+        return imx_add_platform_device(data->devid, data->id,
                        res, ARRAY_SIZE(res),
                        pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index 479c3e9f771f..8f22a4c98a4c 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_imx_keypad_data_entry_single(soc, _size)                    \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index 21c6f30e1017..bfcb8f3dfa8d 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_imx_ssi_data_entry(soc, _id, _hwid, _size)                  \
        [_id] = {                                                       \
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index d390f00bd294..67bf866a2cb6 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size)            \
        [_id] = {                                                       \
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index 5e07ef2bf1c4..ec75d6413686 100644
--- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -7,8 +7,9 @@
 * Free Software Foundation.
 */
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)          \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/mach-imx/devices/platform-imx21-hcd.c
index 5770a42f33bf..30c81616a9a1 100644
--- a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c
+++ b/arch/arm/mach-imx/devices/platform-imx21-hcd.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_imx21_hcd_data_entry_single(soc)                            \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-imx27-coda.c b/arch/arm/mach-imx/devices/platform-imx27-coda.c
index 8b12aacdf396..25bebc29e546 100644
--- a/arch/arm/plat-mxc/devices/platform-imx27-coda.c
+++ b/arch/arm/mach-imx/devices/platform-imx27-coda.c
@@ -7,8 +7,8 @@
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx27_coda_data imx27_coda_data __initconst = {
diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/mach-imx/devices/platform-imx_udc.c
index 6fd675dfce14..5ced7e4e2c71 100644
--- a/arch/arm/plat-mxc/devices/platform-imx_udc.c
+++ b/arch/arm/mach-imx/devices/platform-imx_udc.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_imx_udc_data_entry_single(soc, _size)                       \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
index 805336fdc252..5bb490d556ea 100644
--- a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
+++ b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
@@ -7,8 +7,9 @@
 * Free Software Foundation.
 */
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_imxdi_rtc_data_entry_single(soc)                            \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/mach-imx/devices/platform-ipu-core.c
index d1e33cc6f12e..fc4dd7cedc11 100644
--- a/arch/arm/plat-mxc/devices/platform-ipu-core.c
+++ b/arch/arm/mach-imx/devices/platform-ipu-core.c
@@ -7,8 +7,9 @@
 * Free Software Foundation.
 */
 #include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_ipu_core_entry_single(soc)                                  \
 {                                                                       \
diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/mach-imx/devices/platform-mx1-camera.c
index edcc581a30a9..2c6788131080 100644
--- a/arch/arm/plat-mxc/devices/platform-mx1-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx1-camera.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_mx1_camera_data_entry_single(soc, _size)                    \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
index 11eace953a09..b53e1f348f51 100644
--- a/arch/arm/plat-mxc/devices/platform-mx2-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-camera.c
@@ -6,17 +6,19 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
-#define imx_mx2_camera_data_entry_single(soc)                           \
+#define imx_mx2_camera_data_entry_single(soc, _devid)                   \
        {                                                               \
+                .devid = _devid,                                        \
                .iobasecsi = soc ## _CSI_BASE_ADDR,                     \
                .iosizecsi = SZ_4K,                                     \
                .irqcsi = soc ## _INT_CSI,                              \
        }
-#define imx_mx2_camera_data_entry_single_emma(soc)                      \
+#define imx_mx2_camera_data_entry_single_emma(soc, _devid)              \
        {                                                               \
+                .devid = _devid,                                        \
                .iobasecsi = soc ## _CSI_BASE_ADDR,                     \
                .iosizecsi = SZ_32,                                     \
                .irqcsi = soc ## _INT_CSI,                              \
@@ -27,12 +29,12 @@
 #ifdef CONFIG_SOC_IMX25
 const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
-        imx_mx2_camera_data_entry_single(MX25);
+        imx_mx2_camera_data_entry_single(MX25, "imx25-camera");
 #endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
-        imx_mx2_camera_data_entry_single_emma(MX27);
+        imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");
 #endif /* ifdef CONFIG_SOC_IMX27 */
 struct platform_device *__init imx_add_mx2_camera(
@@ -58,25 +60,8 @@ struct platform_device *__init imx_add_mx2_camera(
                        .flags = IORESOURCE_IRQ,
                },
        };
-        return imx_add_platform_device_dmamask("mx2-camera", 0,
+        return imx_add_platform_device_dmamask(data->devid, 0,
                        res, data->iobaseemmaprp ? 4 : 2,
                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 }
-struct platform_device *__init imx_add_mx2_emmaprp(
-                const struct imx_mx2_camera_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobaseemmaprp,
-                        .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irqemmaprp,
-                        .end = data->irqemmaprp,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
-                        res, 2, NULL, 0, DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
index 35851d889aca..5d4bbbfde641 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
@@ -7,8 +7,9 @@
 * Free Software Foundation.
 */
 #include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_mxc_ehci_data_entry_single(soc, _id, hs)                    \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
index e7b920b58675..b8203c760c8f 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
@@ -7,24 +7,26 @@
 * Free Software Foundation.
 */
 #include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
-#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size)           \
+#include "../hardware.h"
+#include "devices-common.h"
+#define imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size)   \
        {                                                               \
+                .devid = _devid,                                        \
                .id = _id,                                              \
                .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR,          \
                .iosize = _size,                                        \
                .irq = soc ## _INT_SDHC ## _hwid,                       \
                .dmareq = soc ## _DMA_REQ_SDHC ## _hwid,                \
        }
-#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size)                  \
+#define imx_mxc_mmc_data_entry(soc, _devid, _id, _hwid, _size)          \
-        [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size)
+        [_id] = imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size)
 #ifdef CONFIG_SOC_IMX21
 const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
 #define imx21_mxc_mmc_data_entry(_id, _hwid)                            \
-        imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K)
+        imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K)
        imx21_mxc_mmc_data_entry(0, 1),
        imx21_mxc_mmc_data_entry(1, 2),
 };
@@ -33,7 +35,7 @@ const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
 #define imx27_mxc_mmc_data_entry(_id, _hwid)                            \
-        imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx_mxc_mmc_data_entry(MX27, "imx21-mmc", _id, _hwid, SZ_4K)
        imx27_mxc_mmc_data_entry(0, 1),
        imx27_mxc_mmc_data_entry(1, 2),
 };
@@ -42,7 +44,7 @@ const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX31
 const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = {
 #define imx31_mxc_mmc_data_entry(_id, _hwid)                            \
-        imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K)
+        imx_mxc_mmc_data_entry(MX31, "imx31-mmc", _id, _hwid, SZ_16K)
        imx31_mxc_mmc_data_entry(0, 1),
        imx31_mxc_mmc_data_entry(1, 2),
 };
@@ -67,7 +69,7 @@ struct platform_device *__init imx_add_mxc_mmc(
                        .flags = IORESOURCE_DMA,
                },
        };
-        return imx_add_platform_device_dmamask("mxc-mmc", data->id,
+        return imx_add_platform_device_dmamask(data->devid, data->id,
                        res, ARRAY_SIZE(res),
                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index 95b75cc70515..7af1c53e42b5 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -7,18 +7,21 @@
 * Free Software Foundation.
 */
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
-#define imx_mxc_nand_data_entry_single(soc, _size)                      \
+#include "../hardware.h"
+#include "devices-common.h"
+#define imx_mxc_nand_data_entry_single(soc, _devid, _size)              \
        {                                                               \
+                .devid = _devid,                                        \
                .iobase = soc ## _NFC_BASE_ADDR,                        \
                .iosize = _size,                                        \
                .irq = soc ## _INT_NFC                                  \
        }
-#define imx_mxc_nandv3_data_entry_single(soc, _size)                    \
+#define imx_mxc_nandv3_data_entry_single(soc, _devid, _size)            \
        {                                                               \
+                .devid = _devid,                                        \
                .id = -1,                                               \
                .iobase = soc ## _NFC_BASE_ADDR,                        \
                .iosize = _size,                                        \
@@ -28,32 +31,32 @@
 #ifdef CONFIG_SOC_IMX21
 const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX21, SZ_4K);
+        imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 #ifdef CONFIG_SOC_IMX25
 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX25, SZ_8K);
+        imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
 #endif /* ifdef CONFIG_SOC_IMX25 */
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX27, SZ_4K);
+        imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX27 */
 #ifdef CONFIG_SOC_IMX31
 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX31, SZ_4K);
+        imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K);
 #endif
 #ifdef CONFIG_SOC_IMX35
 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
-        imx_mxc_nand_data_entry_single(MX35, SZ_8K);
+        imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
 #endif
 #ifdef CONFIG_SOC_IMX51
 const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
-        imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
+        imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K);
 #endif
 struct platform_device *__init imx_add_mxc_nand(
@@ -76,7 +79,7 @@ struct platform_device *__init imx_add_mxc_nand(
                        .flags = IORESOURCE_MEM,
                },
        };
-        return imx_add_platform_device("mxc_nand", data->id,
+        return imx_add_platform_device(data->devid, data->id,
                        res, ARRAY_SIZE(res) - !data->axibase,
                        pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
index b0c4ae298111..dcd289777687 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)           \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
index b4b7612b6e17..c58404badb59 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 struct imx_mxc_rnga_data {
        resource_size_t iobase;
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/mach-imx/devices/platform-mxc_rtc.c
index a5c9ad5721c2..c7fffaadf847 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_rtc.c
@@ -6,23 +6,24 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
-#define imx_mxc_rtc_data_entry_single(soc)                              \
+#define imx_mxc_rtc_data_entry_single(soc, _devid)                      \
        {                                                               \
+                .devid = _devid,                                        \
                .iobase = soc ## _RTC_BASE_ADDR,                        \
                .irq = soc ## _INT_RTC,                                 \
        }
 #ifdef CONFIG_SOC_IMX31
 const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
-        imx_mxc_rtc_data_entry_single(MX31);
+        imx_mxc_rtc_data_entry_single(MX31, "imx21-rtc");
 #endif /* ifdef CONFIG_SOC_IMX31 */
 #ifdef CONFIG_SOC_IMX35
 const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst =
-        imx_mxc_rtc_data_entry_single(MX35);
+        imx_mxc_rtc_data_entry_single(MX35, "imx21-rtc");
 #endif /* ifdef CONFIG_SOC_IMX35 */
 struct platform_device *__init imx_add_mxc_rtc(
@@ -40,6 +41,6 @@ struct platform_device *__init imx_add_mxc_rtc(
                },
        };
-        return imx_add_platform_device("mxc_rtc", -1,
+        return imx_add_platform_device(data->devid, -1,
                        res, ARRAY_SIZE(res), NULL, 0);
 }
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/mach-imx/devices/platform-mxc_w1.c
index 96fa5ea91fe8..88c18b720d63 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_w1.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_w1.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_mxc_w1_data_entry_single(soc)                               \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c
index 70e2f2a44714..e4ec11c8ce55 100644
--- a/arch/arm/plat-mxc/devices/platform-pata_imx.c
+++ b/arch/arm/mach-imx/devices/platform-pata_imx.c
@@ -3,8 +3,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_pata_imx_data_entry_single(soc, _size)                      \
        {                                                               \
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
index 3793e475cd95..e66a4e316311 100644
--- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
@@ -6,10 +6,11 @@
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
 #include <linux/platform_data/mmc-esdhc-imx.h>
+#include "../hardware.h"
+#include "devices-common.h"
 #define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \
        {                                                               \
                .devid = _devid,                                        \
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index 9c50c14c8f92..8880bcb11e05 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -6,8 +6,8 @@
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
-#include <mach/hardware.h>
+#include "../hardware.h"
-#include <mach/devices-common.h>
+#include "devices-common.h"
 #define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
        {                                                               \
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 576af7446952..134c190e3003 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -15,10 +15,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
 #define USBCTRL_OTGBASE_OFFSET  0x600
 #define MX25_OTG_SIC_SHIFT      29
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
index cd6e1f81508d..448d9115539d 100644
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -15,10 +15,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
 #define USBCTRL_OTGBASE_OFFSET  0x600
 #define MX27_OTG_SIC_SHIFT      29
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index 9a880c78af34..05de4e1e39d7 100644
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -15,10 +15,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
 #define USBCTRL_OTGBASE_OFFSET  0x600
 #define MX31_OTG_SIC_SHIFT      29
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 293397852e4e..554e7cccff53 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -15,10 +15,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
 #define USBCTRL_OTGBASE_OFFSET  0x600
 #define MX35_OTG_SIC_SHIFT      29
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
index cf8d00e5cce1..e49710b10c68 100644
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ b/arch/arm/mach-imx/ehci-imx5.c
@@ -15,10 +15,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
 #define MXC_OTG_OFFSET                  0
 #define MXC_H1_OFFSET                   0x200
 #define MXC_H2_OFFSET                   0x400
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/mach-imx/epit.c
index 88726f4dbbfa..04a5961beeac 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/mach-imx/epit.c
@@ -51,10 +51,10 @@
 #include <linux/clockchips.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <mach/hardware.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
+#include "common.h"
+#include "hardware.h"
 static struct clock_event_device clockevent_epit;
 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h
index a21d3313f994..a21d3313f994 100644
--- a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
+++ b/arch/arm/mach-imx/eukrea-baseboards.h
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 98aef571b9f8..b4c70028d359 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -29,11 +29,10 @@
 #include <asm/mach/arch.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx27.h>
-#include <mach/hardware.h>
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
 static const int eukrea_mbimx27_pins[] __initconst = {
        /* UART2 */
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 0b84666792f0..e2b70f4c1a2c 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -26,14 +26,14 @@
 #include <linux/spi/spi.h>
 #include <video/platform_lcd.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx25.h>
-#include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/mx25.h>
+#include "common.h"
 #include "devices-imx25.h"
+#include "hardware.h"
+#include "iomux-mx25.h"
+#include "mx25.h"
 static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
        /* LCD */
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index c6532a007d46..5a2d5ef12dd5 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -36,11 +36,10 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "common.h"
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
 #include "devices-imx35.h"
+#include "hardware.h"
+#include "iomux-mx35.h"
 static const struct fb_videomode fb_modedb[] = {
        {
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
index 8b0de30d7a3f..9be6c1e69d68 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
@@ -36,11 +36,10 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "common.h"
-#include <mach/common.h>
-#include <mach/iomux-mx51.h>
 #include "devices-imx51.h"
+#include "hardware.h"
+#include "iomux-mx51.h"
 static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
        /* LED */
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/mach-imx/hardware.h
index ebf10654bb42..3ce7fa3bd43f 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -105,20 +105,20 @@
 #define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
-#include <mach/mxc.h>
+#include "mxc.h"
-#include <mach/mx6q.h>
+#include "mx6q.h"
-#include <mach/mx50.h>
+#include "mx50.h"
-#include <mach/mx51.h>
+#include "mx51.h"
-#include <mach/mx53.h>
+#include "mx53.h"
-#include <mach/mx3x.h>
+#include "mx3x.h"
-#include <mach/mx31.h>
+#include "mx31.h"
-#include <mach/mx35.h>
+#include "mx35.h"
-#include <mach/mx2x.h>
+#include "mx2x.h"
-#include <mach/mx21.h>
+#include "mx21.h"
-#include <mach/mx27.h>
+#include "mx27.h"
-#include <mach/mx1.h>
+#include "mx1.h"
-#include <mach/mx25.h>
+#include "mx25.h"
 #define imx_map_entry(soc, name, _type) {                               \
        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index b07b778dc9a8..3dec962b0770 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -13,7 +13,8 @@
 #include <linux/errno.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
-#include <mach/common.h>
+#include "common.h"
 static inline void cpu_enter_lowpower(void)
 {
diff --git a/arch/arm/plat-mxc/include/mach/iim.h b/arch/arm/mach-imx/iim.h
index 315bffadafda..315bffadafda 100644
--- a/arch/arm/plat-mxc/include/mach/iim.h
+++ b/arch/arm/mach-imx/iim.h
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
new file mode 100644
index 000000000000..e17dfbc42192
--- /dev/null
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include "common.h"
+#include "mx25.h"
+static void __init imx25_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static void __init imx25_timer_init(void)
+{
+        mx25_clocks_init_dt();
+}
+static struct sys_timer imx25_timer = {
+        .init = imx25_timer_init,
+};
+static const char * const imx25_dt_board_compat[] __initconst = {
+        "fsl,imx25",
+        NULL
+};
+DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
+        .map_io         = mx25_map_io,
+        .init_early     = imx25_init_early,
+        .init_irq       = mx25_init_irq,
+        .handle_irq     = imx25_handle_irq,
+        .timer          = &imx25_timer,
+        .init_machine   = imx25_dt_init,
+        .dt_compat      = imx25_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index e80d5235dac0..ebfae96543c4 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -14,21 +14,22 @@
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/mx27.h>
+#include "common.h"
+#include "mx27.h"
 static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
        OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
        OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "mxc_nand.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "imx27-nand.0", NULL),
        { /* sentinel */ }
 };
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index a68ba207b2b7..af476de2570e 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -14,8 +14,9 @@
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/mx31.h>
+#include "common.h"
+#include "mx31.h"
 static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index f233b4bb2342..5ffa40c673f8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -15,38 +15,13 @@
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/mx51.h>
-/*
+#include "common.h"
- * Lookup table for attaching a specific name and platform_data pointer to
+#include "mx51.h"
- * devices as they get created by of_platform_populate().  Ideally this table
- * would not exist, but the current clock implementation depends on some devices
- * having a specific name.
- */
-static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
-        OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
-        { /* sentinel */ }
-};
 static void __init imx51_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-                             imx51_auxdata_lookup, NULL);
 }
 static void __init imx51_timer_init(void)
diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
deleted file mode 100644
index df5f522da6b3..000000000000
--- a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __MACH_DMA_MX1_MX2_H__
-#define __MACH_DMA_MX1_MX2_H__
-/*
- * Don't use this header in new code, it will go away when all users are
- * converted to mach/dma-v1.h
- */
-#include <mach/dma-v1.h>
-#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 82bd4403b450..cabefbc5e7c1 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -22,8 +22,9 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
+#include "hardware.h"
+#include "iomux-mx3.h"
 /*
 * IOMUX register (base) addresses
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/mach-imx/iomux-mx1.h
index 6b1507cf378e..95f4681d85d7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1.h
+++ b/arch/arm/mach-imx/iomux-mx1.h
@@ -18,7 +18,7 @@
 #ifndef __MACH_IOMUX_MX1_H__
 #define __MACH_IOMUX_MX1_H__
-#include <mach/iomux-v1.h>
+#include "iomux-v1.h"
 #define PA0_AIN_SPI2_CLK        (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
 #define PA0_AF_ETMTRACESYNC     (GPIO_PORTA | GPIO_AF | 0)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/mach-imx/iomux-mx21.h
index 1495dfda7834..a70cffceb085 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx21.h
+++ b/arch/arm/mach-imx/iomux-mx21.h
@@ -18,8 +18,8 @@
 #ifndef __MACH_IOMUX_MX21_H__
 #define __MACH_IOMUX_MX21_H__
-#include <mach/iomux-mx2x.h>
+#include "iomux-mx2x.h"
-#include <mach/iomux-v1.h>
+#include "iomux-v1.h"
 /* Primary GPIO pin functions */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/mach-imx/iomux-mx25.h
index c61ec0fc10d4..be51e838375c 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/mach-imx/iomux-mx25.h
@@ -19,7 +19,7 @@
 #ifndef __MACH_IOMUX_MX25_H__
 #define __MACH_IOMUX_MX25_H__
-#include <mach/iomux-v3.h>
+#include "iomux-v3.h"
 /*
 * IOMUX/PAD Bit field definitions
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/mach-imx/iomux-mx27.h
index d9f9a6e32d80..218e99e89e86 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx27.h
+++ b/arch/arm/mach-imx/iomux-mx27.h
@@ -19,8 +19,8 @@
 #ifndef __MACH_IOMUX_MX27_H__
 #define __MACH_IOMUX_MX27_H__
-#include <mach/iomux-mx2x.h>
+#include "iomux-mx2x.h"
-#include <mach/iomux-v1.h>
+#include "iomux-v1.h"
 /* Primary GPIO pin functions */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/mach-imx/iomux-mx2x.h
index 7a9b20abda09..7a9b20abda09 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
+++ b/arch/arm/mach-imx/iomux-mx2x.h
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index f79f78a1c0ed..f79f78a1c0ed 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/mach-imx/iomux-mx35.h
index 3117c18bbbd9..90bfa6b5be6a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/mach-imx/iomux-mx35.h
@@ -19,7 +19,7 @@
 #ifndef __MACH_IOMUX_MX35_H__
 #define __MACH_IOMUX_MX35_H__
-#include <mach/iomux-v3.h>
+#include "iomux-v3.h"
 /*
 * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/mach-imx/iomux-mx50.h
index 98e7fd0b9083..00f56e0e8009 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx50.h
+++ b/arch/arm/mach-imx/iomux-mx50.h
@@ -19,7 +19,7 @@
 #ifndef __MACH_IOMUX_MX50_H__
 #define __MACH_IOMUX_MX50_H__
-#include <mach/iomux-v3.h>
+#include "iomux-v3.h"
 #define MX50_ELCDIF_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h
index 2623e7a2e190..75bbcc4aa2d2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/mach-imx/iomux-mx51.h
@@ -13,7 +13,7 @@
 #ifndef __MACH_IOMUX_MX51_H__
 #define __MACH_IOMUX_MX51_H__
-#include <mach/iomux-v3.h>
+#include "iomux-v3.h"
 #define __NA_   0x000
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index 1f73963bc13e..2b156d1d9e21 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -28,9 +28,10 @@
 #include <linux/string.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-v1.h>
+#include "hardware.h"
+#include "iomux-v1.h"
 static void __iomem *imx_iomuxv1_baseaddr;
 static unsigned imx_iomuxv1_numports;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/mach-imx/iomux-v1.h
index 02651a40fe23..02651a40fe23 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/mach-imx/iomux-v1.h
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 99a9cdb9d6be..9dae74bf47fc 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -25,9 +25,10 @@
 #include <linux/string.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-v3.h>
+#include "hardware.h"
+#include "iomux-v3.h"
 static void __iomem *base;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h
index 2fa3b5430102..2fa3b5430102 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/mach-imx/iomux-v3.h
diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/mach-imx/iram.h
index 022690c33702..022690c33702 100644
--- a/arch/arm/plat-mxc/include/mach/iram.h
+++ b/arch/arm/mach-imx/iram.h
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/mach-imx/iram_alloc.c
index 074c3869626a..6c80424f678e 100644
--- a/arch/arm/plat-mxc/iram_alloc.c
+++ b/arch/arm/mach-imx/iram_alloc.c
@@ -22,7 +22,8 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/genalloc.h>
-#include <mach/iram.h>
+#include "iram.h"
 static unsigned long iram_phys_base;
 static void __iomem *iram_virt_base;
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/mach-imx/irq-common.c
index b6e11458e5ae..b6e11458e5ae 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/mach-imx/irq-common.h
index 6ccb3a14c693..5b2dabba330f 100644
--- a/arch/arm/plat-mxc/irq-common.h
+++ b/arch/arm/mach-imx/irq-common.h
@@ -19,6 +19,9 @@
 #ifndef __PLAT_MXC_IRQ_COMMON_H__
 #define __PLAT_MXC_IRQ_COMMON_H__
+/* all normal IRQs can be FIQs */
+#define FIQ_START       0
 struct mxc_extra_irq
 {
        int (*set_priority)(unsigned char irq, unsigned char prio);
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index c40a34c00489..2fdc9bf2fb5e 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -14,19 +14,28 @@
 #include <asm/page.h>
 #include <asm/sizes.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "hardware.h"
+#define IMX6Q_UART1_BASE_ADDR   0x02020000
+#define IMX6Q_UART2_BASE_ADDR   0x021e8000
+#define IMX6Q_UART3_BASE_ADDR   0x021ec000
+#define IMX6Q_UART4_BASE_ADDR   0x021f0000
+#define IMX6Q_UART5_BASE_ADDR   0x021f4000
+/*
+ * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
+ * of IMX6Q_UART##n##_BASE_ADDR.
+ */
+#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
+#define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
+#define IMX6Q_DEBUG_UART_BASE   IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
 static struct map_desc imx_lluart_desc = {
-#ifdef CONFIG_DEBUG_IMX6Q_UART2
+#ifdef CONFIG_DEBUG_IMX6Q_UART
-        .virtual        = MX6Q_IO_P2V(MX6Q_UART2_BASE_ADDR),
+        .virtual        = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
-        .pfn            = __phys_to_pfn(MX6Q_UART2_BASE_ADDR),
+        .pfn            = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
-        .length         = MX6Q_UART2_SIZE,
+        .length         = 0x4000,
-        .type           = MT_DEVICE,
-#endif
-#ifdef CONFIG_DEBUG_IMX6Q_UART4
-        .virtual        = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
-        .pfn            = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
-        .length         = MX6Q_UART4_SIZE,
        .type           = MT_DEVICE,
 #endif
 };
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 7b99a79722b6..5c9bd2c66e6d 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -25,11 +25,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/hardware.h>
-#include <mach/iomux-mx1.h>
 #include "devices-imx1.h"
+#include "hardware.h"
+#include "iomux-mx1.h"
 static const int apf9328_pins[] __initconst = {
        /* UART1 */
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 5985ed1b8c98..59bd6b06a6b5 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -41,19 +41,18 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx3.h>
-#include <mach/ulpi.h>
 #include "devices-imx31.h"
 #include "crmregs-imx3.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 static int armadillo5x0_pins[] = {
        /* UART1 */
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 9a9897749dd6..3a39d5aec07a 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -19,15 +19,14 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <mach/iomux-mx3.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
 #include <asm/mach/time.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 2bb9e18d9ee1..12a370646b45 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -34,13 +34,12 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/eukrea-baseboards.h>
+#include "common.h"
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx27.h>
-#include <mach/ulpi.h>
 #include "devices-imx27.h"
+#include "eukrea-baseboards.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
+#include "ulpi.h"
 static const int eukrea_cpuimx27_pins[] __initconst = {
        /* UART1 */
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index d49b0ec6bdec..5a31bf8c8f4c 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -37,12 +37,11 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/eukrea-baseboards.h>
+#include "common.h"
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
 #include "devices-imx35.h"
+#include "eukrea-baseboards.h"
+#include "hardware.h"
+#include "iomux-mx35.h"
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index b87cc49ab1e8..b727de029c8f 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -26,18 +26,17 @@
 #include <linux/spi/spi.h>
 #include <linux/can/platform/mcp251x.h>
-#include <mach/eukrea-baseboards.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include "common.h"
 #include "devices-imx51.h"
 #include "cpu_op-mx51.h"
+#include "eukrea-baseboards.h"
+#include "hardware.h"
+#include "iomux-mx51.h"
 #define USBH1_RST               IMX_GPIO_NR(2, 28)
 #define ETH_RST                 IMX_GPIO_NR(2, 31)
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 017bbb70ea41..75027a5ad8b7 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -27,18 +27,18 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <mach/eukrea-baseboards.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/mx25.h>
-#include <mach/iomux-mx25.h>
+#include "common.h"
 #include "devices-imx25.h"
+#include "eukrea-baseboards.h"
+#include "hardware.h"
+#include "iomux-mx25.h"
+#include "mx25.h"
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 141756f00ae5..318bd8df7fcc 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -40,17 +40,21 @@
 #include <asm/mach/time.h>
 #include <asm/system_info.h>
 #include <asm/memblock.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx27.h>
+#include "common.h"
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
 #define TVP5150_RSTN (GPIO_PORTC + 18)
 #define TVP5150_PWDN (GPIO_PORTC + 19)
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25)
+#define VERSION_MASK            0x7
+#define MOTHERBOARD_SHIFT       4
+#define EXPBOARD_SHIFT          0
 #define MOTHERBOARD_BIT2        (GPIO_PORTD + 31)
 #define MOTHERBOARD_BIT1        (GPIO_PORTD + 30)
 #define MOTHERBOARD_BIT0        (GPIO_PORTD + 29)
@@ -237,7 +241,7 @@ static struct mx2_camera_platform_data visstrim_camera = {
 static phys_addr_t mx2_camera_base __initdata;
 #define MX2_CAMERA_BUF_SIZE SZ_8M
-static void __init visstrim_camera_init(void)
+static void __init visstrim_analog_camera_init(void)
 {
        struct platform_device *pdev;
        int dma;
@@ -474,6 +478,27 @@ static void __init visstrim_deinterlace_init(void)
                return;
 }
+/* Emma-PrP for format conversion */
+static void __init visstrim_emmaprp_init(void)
+{
+        struct platform_device *pdev;
+        int dma;
+        pdev = imx27_add_mx2_emmaprp();
+        if (IS_ERR(pdev))
+                return;
+        /*
+         * Use the same memory area as the analog camera since both
+         * devices are, by nature, exclusive.
+         */
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                mx2_camera_base, mx2_camera_base,
+                                MX2_CAMERA_BUF_SIZE,
+                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                pr_err("Failed to declare memory for emmaprp\n");
+}
 /* Audio */
 static const struct snd_mx27vis_platform_data snd_mx27vis_pdata __initconst = {
@@ -507,13 +532,14 @@ static void __init visstrim_m10_revision(void)
        mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
        system_rev = 0x27000;
-        system_rev |= (mo_version << 4);
+        system_rev |= (mo_version << MOTHERBOARD_SHIFT);
-        system_rev |= exp_version;
+        system_rev |= (exp_version << EXPBOARD_SHIFT);
 }
 static void __init visstrim_m10_board_init(void)
 {
        int ret;
+        int mo_version;
        imx27_soc_init();
        visstrim_m10_revision();
@@ -546,8 +572,24 @@ static void __init visstrim_m10_board_init(void)
        platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
                                      &iclink_tvp5150, sizeof(iclink_tvp5150));
        gpio_led_register_device(0, &visstrim_m10_led_data);
-        visstrim_deinterlace_init();
-        visstrim_camera_init();
+        /* Use mother board version to decide what video devices we shall use */
+        mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
+        if (mo_version & 0x1) {
+                visstrim_emmaprp_init();
+                /*
+                 * Despite not being used, tvp5150 must be
+                 * powered on to avoid I2C problems. To minimize
+                 * power consupmtion keep reset enabled.
+                 */
+                gpio_set_value(TVP5150_PWDN, 1);
+                ndelay(1);
+                gpio_set_value(TVP5150_RSTN, 0);
+        } else {
+                visstrim_deinterlace_init();
+                visstrim_analog_camera_init();
+        }
        visstrim_coda_init();
 }
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 7381387a8905..53a860112938 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -17,11 +17,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx27.h>
+#include "hardware.h"
+#include "common.h"
 #include "devices-imx27.h"
+#include "iomux-mx27.h"
 static const int mx27ipcam_pins[] __initconst = {
        /* UART1 */
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 1f45b9189229..fc8dce931378 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -20,11 +20,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx27.h>
+#include "common.h"
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
 static const int mx27lite_pins[] __initconst = {
        /* UART1 */
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 29711e95579f..860284dea0e7 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -19,36 +19,9 @@
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/mx53.h>
-/*
+#include "common.h"
- * Lookup table for attaching a specific name and platform_data pointer to
+#include "mx53.h"
- * devices as they get created by of_platform_populate().  Ideally this table
- * would not exist, but the current clock implementation depends on some devices
- * having a specific name.
- */
-static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
-        OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
-        { /* sentinel */ }
-};
 static void __init imx53_qsb_init(void)
 {
@@ -68,8 +41,7 @@ static void __init imx53_dt_init(void)
        if (of_machine_is_compatible("fsl,imx53-qsb"))
                imx53_qsb_init();
-        of_platform_populate(NULL, of_default_bus_match_table,
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-                             imx53_auxdata_lookup, NULL);
 }
 static void __init imx53_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 47c91f7185d2..4eb1b3ac794c 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -33,10 +33,44 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
-#include <mach/common.h>
-#include <mach/cpuidle.h>
-#include <mach/hardware.h>
+#include "common.h"
+#include "cpuidle.h"
+#include "hardware.h"
+#define IMX6Q_ANALOG_DIGPROG    0x260
+static int imx6q_revision(void)
+{
+        struct device_node *np;
+        void __iomem *base;
+        static u32 rev;
+        if (!rev) {
+                np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+                if (!np)
+                        return IMX_CHIP_REVISION_UNKNOWN;
+                base = of_iomap(np, 0);
+                if (!base) {
+                        of_node_put(np);
+                        return IMX_CHIP_REVISION_UNKNOWN;
+                }
+                rev =  readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
+                iounmap(base);
+                of_node_put(np);
+        }
+        switch (rev & 0xff) {
+        case 0:
+                return IMX_CHIP_REVISION_1_0;
+        case 1:
+                return IMX_CHIP_REVISION_1_1;
+        case 2:
+                return IMX_CHIP_REVISION_1_2;
+        default:
+                return IMX_CHIP_REVISION_UNKNOWN;
+        }
+}
 void imx6q_restart(char mode, const char *cmd)
 {
@@ -117,6 +151,17 @@ static void __init imx6q_sabrelite_init(void)
        imx6q_sabrelite_cko1_setup();
 }
+static void __init imx6q_1588_init(void)
+{
+        struct regmap *gpr;
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr))
+                regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
+        else
+                pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+}
 static void __init imx6q_usb_init(void)
 {
        struct regmap *anatop;
@@ -153,6 +198,7 @@ static void __init imx6q_init_machine(void)
        imx6q_pm_init();
        imx6q_usb_init();
+        imx6q_1588_init();
 }
 static struct cpuidle_driver imx6q_cpuidle_driver = {
@@ -192,6 +238,7 @@ static void __init imx6q_timer_init(void)
 {
        mx6q_clocks_init();
        twd_local_timer_of_register();
+        imx_print_silicon_rev("i.MX6Q", imx6q_revision());
 }
 static struct sys_timer imx6q_timer = {
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 0330078ff788..2e536ea53444 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,11 +36,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
 #define KZM_ARM11_IO_ADDRESS(x) (IOMEM(                                 \
        IMX_IO_P2V_MODULE(x, MX31_CS4) ?:                               \
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 667f359a2e8b..06b483783e68 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -23,11 +23,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/hardware.h>
-#include <mach/iomux-mx1.h>
 #include "devices-imx1.h"
+#include "hardware.h"
+#include "iomux-mx1.h"
 static const int mx1ads_pins[] __initconst = {
        /* UART1 */
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index ed22e3fe6ec8..6adb3136bb08 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -18,15 +18,15 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-mx21.h>
+#include "common.h"
 #include "devices-imx21.h"
+#include "hardware.h"
+#include "iomux-mx21.h"
 /*
 * Memory-mapped I/O on MX21ADS base board
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index ce247fd1269a..b1b03aa55bb8 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -31,17 +31,17 @@
 #include <linux/platform_device.h>
 #include <linux/usb/otg.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/mx25.h>
-#include <mach/iomux-mx25.h>
+#include "common.h"
 #include "devices-imx25.h"
+#include "hardware.h"
+#include "iomux-mx25.h"
+#include "mx25.h"
 #define MX25PDK_CAN_PWDN        IMX_GPIO_NR(4, 6)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 05996f39005c..d0e547fa925f 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -36,13 +36,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx27.h>
-#include <mach/ulpi.h>
-#include <mach/3ds_debugboard.h>
+#include "3ds_debugboard.h"
+#include "common.h"
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
+#include "ulpi.h"
 #define SD1_EN_GPIO             IMX_GPIO_NR(2, 25)
 #define OTG_PHY_RESET_GPIO      IMX_GPIO_NR(2, 23)
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 7dc59bac0e55..3d036f57f0e6 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -21,15 +21,15 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-mx27.h>
+#include "common.h"
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
 /*
 * Base address of PBC controller, CS4
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 8915f937b7d5..bc301befdd06 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -30,19 +30,19 @@
 #include <media/soc_camera.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/3ds_debugboard.h>
-#include <mach/ulpi.h>
+#include "3ds_debugboard.h"
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 static int mx31_3ds_pins[] = {
        /* UART1 */
@@ -393,7 +393,7 @@ static struct regulator_init_data gpo_init = {
 };
 static struct regulator_consumer_supply vmmc2_consumers[] = {
-        REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
+        REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"),
 };
 static struct regulator_init_data vmmc2_init = {
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index e774b07f48d3..8b56f8883f32 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -28,8 +28,6 @@
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
 #include <linux/mfd/wm8350/audio.h>
@@ -37,7 +35,10 @@
 #include <linux/mfd/wm8350/pmic.h>
 #endif
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
 /* Base address of PBC controller */
 #define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 34b9bf075daf..08b9965c8b36 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -42,13 +42,12 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "board-mx31lilly.h"
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31lilly.h>
-#include <mach/ulpi.h>
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 /*
 * This file contains module-specific initialization routines for LILLY-1131.
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index ef57cff5abfb..bdcd92e59518 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -39,13 +39,12 @@
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <mach/hardware.h>
+#include "board-mx31lite.h"
-#include <mach/common.h>
+#include "common.h"
-#include <mach/board-mx31lite.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ulpi.h>
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 /*
 * This file contains the module-specific initialization routines.
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 459e754ef8c9..2517cfa9f26b 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -42,14 +42,14 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <mach/board-mx31moboard.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ulpi.h>
 #include <linux/platform_data/asoc-imx-ssi.h>
+#include "board-mx31moboard.h"
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 static unsigned int moboard_pins[] = {
        /* UART0 */
@@ -175,11 +175,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = {
 static struct regulator_consumer_supply sdhc_consumers[] = {
        {
-                .dev_name = "mxc-mmc.0",
+                .dev_name = "imx31-mmc.0",
                .supply = "sdhc0_vcc",
        },
        {
-                .dev_name = "mxc-mmc.1",
+                .dev_name = "imx31-mmc.1",
                .supply = "sdhc1_vcc",
        },
 };
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 504983c68aa8..5277da45d60c 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -43,15 +43,15 @@
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
-#include <mach/3ds_debugboard.h>
 #include <video/platform_lcd.h>
 #include <media/soc_camera.h>
+#include "3ds_debugboard.h"
+#include "common.h"
 #include "devices-imx35.h"
+#include "hardware.h"
+#include "iomux-mx35.h"
 #define GPIO_MC9S08DZ60_GPS_ENABLE 0
 #define GPIO_MC9S08DZ60_HDD_ENABLE 4
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
index 42b66e8d9615..0c1f88a80bdc 100644
--- a/arch/arm/mach-imx/mach-mx50_rdp.c
+++ b/arch/arm/mach-imx/mach-mx50_rdp.c
@@ -24,17 +24,16 @@
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx50.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include "common.h"
 #include "devices-imx50.h"
+#include "hardware.h"
+#include "iomux-mx50.h"
 #define FEC_EN          IMX_GPIO_NR(6, 23)
 #define FEC_RESET_B     IMX_GPIO_NR(4, 12)
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 9ee84a4af639..abc25bd1107b 100644
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
@@ -19,12 +19,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/hardware.h>
+#include "3ds_debugboard.h"
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx51.h>
-#include <mach/3ds_debugboard.h>
 #include "devices-imx51.h"
+#include "hardware.h"
+#include "iomux-mx51.h"
 #define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 7b31cbde8775..d9a84ca2199a 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -20,17 +20,16 @@
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include "common.h"
 #include "devices-imx51.h"
 #include "cpu_op-mx51.h"
+#include "hardware.h"
+#include "iomux-mx51.h"
 #define BABBAGE_USB_HUB_RESET   IMX_GPIO_NR(1, 7)
 #define BABBAGE_USBH1_STP       IMX_GPIO_NR(1, 27)
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 0bf6d30aa32d..f4a8c7e108e1 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -21,17 +21,17 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
-#include <mach/iomux-mx27.h>
 #include <linux/i2c/pca953x.h>
+#include "common.h"
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
 static const int mxt_td60_pins[] __initconst = {
        /* UART0 */
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index de8516b7d69f..eee369fa94a2 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -32,13 +32,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
-#include <mach/ulpi.h>
+#include "common.h"
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
+#include "ulpi.h"
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index e3c45130fb3c..547fef133f65 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -42,13 +42,13 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ulpi.h>
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
 #include "pcm037.h"
+#include "ulpi.h"
 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index 11ffa81ad17d..8fd8255068ee 100644
--- a/arch/arm/mach-imx/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -11,13 +11,12 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
 #include <asm/mach-types.h>
 #include "pcm037.h"
+#include "common.h"
 #include "devices-imx31.h"
+#include "iomux-mx3.h"
 static unsigned int pcm037_eet_pins[] = {
        /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 95f49d936fd3..4aa0d0798605 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -33,13 +33,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/board-pcm038.h>
+#include "board-pcm038.h"
-#include <mach/common.h>
+#include "common.h"
-#include <mach/hardware.h>
-#include <mach/iomux-mx27.h>
-#include <mach/ulpi.h>
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
+#include "ulpi.h"
 static const int pcm038_pins[] __initconst = {
        /* UART1 */
@@ -212,7 +211,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = {
 static struct regulator_consumer_supply sdhc1_consumers[] = {
        {
-                .dev_name = "mxc-mmc.1",
+                .dev_name = "imx21-mmc.1",
                .supply = "sdhc_vcc",
        },
 };
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index e4bd4387e344..92445440221e 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -33,12 +33,11 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "common.h"
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
-#include <mach/ulpi.h>
 #include "devices-imx35.h"
+#include "hardware.h"
+#include "iomux-mx35.h"
+#include "ulpi.h"
 static const struct fb_videomode fb_modedb[] = {
        {
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index fb25fbd31226..96d9a91f8a3b 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -21,17 +21,17 @@
 #include <linux/mtd/nand.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <mach/iomux-mx3.h>
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
 /* FPGA defines */
 #define QONG_FPGA_VERSION(major, minor, rev)    \
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 67ff38e9a3ca..fc970409dbaf 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -20,11 +20,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/hardware.h>
-#include <mach/iomux-mx1.h>
 #include "devices-imx1.h"
+#include "hardware.h"
+#include "iomux-mx1.h"
 /*
 * This scb9328 has a 32MiB flash
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 39eb7960e2a4..3aecf91e4289 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -28,15 +28,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/mfd/mc13xxx.h>
+#include "common.h"
 #include "devices-imx35.h"
+#include "hardware.h"
+#include "iomux-mx35.h"
 #define GPIO_LCDPWR     IMX_GPIO_NR(1, 2)
 #define GPIO_PMIC_INT   IMX_GPIO_NR(2, 0)
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 6d60d51868bc..7a146671e65a 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -22,9 +22,10 @@
 #include <asm/mach/map.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/hardware.h>
+#include "devices/devices-common.h"
-#include <mach/iomux-v1.h>
+#include "hardware.h"
+#include "iomux-v1.h"
 static struct map_desc imx_io_desc[] __initdata = {
        imx_map_entry(MX1, IO, MT_DEVICE),
@@ -58,5 +59,7 @@ void __init imx1_soc_init(void)
                                                MX1_GPIO_INT_PORTC, 0);
        mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
                                                MX1_GPIO_INT_PORTD, 0);
+        imx_add_imx_dma("imx1-dma", MX1_DMA_BASE_ADDR,
+                        MX1_DMA_INT, MX1_DMA_ERR);
        pinctrl_provide_dummies();
 }
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d056dad0940d..d8ccd3a8ec53 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -21,12 +21,13 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/pinctrl/machine.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-v1.h>
+#include "common.h"
+#include "devices/devices-common.h"
+#include "hardware.h"
+#include "iomux-v1.h"
 /* MX21 memory map definition */
 static struct map_desc imx21_io_desc[] __initdata = {
@@ -81,6 +82,8 @@ static const struct resource imx21_audmux_res[] __initconst = {
 void __init imx21_soc_init(void)
 {
+        mxc_device_init();
        mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
        mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
        mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
@@ -89,7 +92,8 @@ void __init imx21_soc_init(void)
        mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
        pinctrl_provide_dummies();
-        imx_add_imx_dma();
+        imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR,
+                        MX21_INT_DMACH0, 0); /* No ERR irq */
        platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
                                        ARRAY_SIZE(imx21_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index f3f5c6542ab4..9357707bb7af 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -24,11 +24,11 @@
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/devices-common.h>
+#include "devices/devices-common.h"
-#include <mach/hardware.h>
+#include "hardware.h"
-#include <mach/mx25.h>
+#include "iomux-v3.h"
-#include <mach/iomux-v3.h>
+#include "mx25.h"
 /*
 * This table defines static virtual address mappings for I/O regions.
@@ -89,6 +89,8 @@ static const struct resource imx25_audmux_res[] __initconst = {
 void __init imx25_soc_init(void)
 {
+        mxc_device_init();
        /* i.mx25 has the i.mx35 type gpio */
        mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
        mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index e7e24afc45ed..4f1be65a7b5f 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -21,12 +21,13 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/pinctrl/machine.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-v1.h>
+#include "common.h"
+#include "devices/devices-common.h"
+#include "hardware.h"
+#include "iomux-v1.h"
 /* MX27 memory map definition */
 static struct map_desc imx27_io_desc[] __initdata = {
@@ -81,6 +82,8 @@ static const struct resource imx27_audmux_res[] __initconst = {
 void __init imx27_soc_init(void)
 {
+        mxc_device_init();
        /* i.mx27 has the i.mx21 type gpio */
        mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
        mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
@@ -90,7 +93,8 @@ void __init imx27_soc_init(void)
        mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
        pinctrl_provide_dummies();
-        imx_add_imx_dma();
+        imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR,
+                        MX27_INT_DMACH0, 0); /* No ERR irq */
        /* imx27 has the imx21 type audmux */
        platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
                                        ARRAY_SIZE(imx27_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index b5deb0554552..cefa047c4053 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -26,12 +26,11 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/devices-common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-v3.h>
 #include "crmregs-imx3.h"
+#include "devices/devices-common.h"
+#include "hardware.h"
+#include "iomux-v3.h"
 void __iomem *mx3_ccm_base;
@@ -175,6 +174,8 @@ void __init imx31_soc_init(void)
        imx3_init_l2x0();
+        mxc_device_init();
        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
@@ -271,6 +272,8 @@ void __init imx35_soc_init(void)
        imx3_init_l2x0();
+        mxc_device_init();
        mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
        mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
        mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index acb0aadb4255..79d71cf23a1d 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -18,10 +18,10 @@
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "common.h"
-#include <mach/common.h>
+#include "devices/devices-common.h"
-#include <mach/devices-common.h>
+#include "hardware.h"
-#include <mach/iomux-v3.h>
+#include "iomux-v3.h"
 /*
 * Define the MX50 memory map.
@@ -81,8 +81,28 @@ void __init imx50_init_early(void)
        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
 }
+/*
+ * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
+ * the Freescale marketing division. However this did not remove the
+ * hardware from the chip which still needs to be configured for proper
+ * IPU support.
+ */
+static void __init imx51_ipu_mipi_setup(void)
+{
+        void __iomem *hsc_addr;
+        hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
+        /* setup MIPI module to legacy mode */
+        __raw_writel(0xf00, hsc_addr);
+        /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
+        __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
+                hsc_addr + 0x800);
+}
 void __init imx51_init_early(void)
 {
+        imx51_ipu_mipi_setup();
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
@@ -138,6 +158,8 @@ static const struct resource imx51_audmux_res[] __initconst = {
 void __init imx50_soc_init(void)
 {
+        mxc_device_init();
        /* i.mx50 has the i.mx35 type gpio */
        mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
        mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
@@ -153,6 +175,8 @@ void __init imx50_soc_init(void)
 void __init imx51_soc_init(void)
 {
+        mxc_device_init();
        /* i.mx51 has the i.mx35 type gpio */
        mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
        mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/mach-imx/mx1.h
index 45bd31cc34d6..45bd31cc34d6 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/mach-imx/mx1.h
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/mach-imx/mx21.h
index 468738aa997f..468738aa997f 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/mach-imx/mx21.h
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/mach-imx/mx25.h
index ec466400a200..ec466400a200 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/mach-imx/mx25.h
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/mach-imx/mx27.h
index e074616d54ca..e074616d54ca 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/mach-imx/mx27.h
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/mach-imx/mx2x.h
index 11642f5b224c..11642f5b224c 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/mach-imx/mx2x.h
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/mach-imx/mx31.h
index ee9b1f9215df..ee9b1f9215df 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/mach-imx/mx31.h
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index 29e890f92055..d4361b80c5fb 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -30,12 +30,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "board-mx31lilly.h"
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31lilly.h>
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
 /*
 * This file contains board-specific initialization routines for the
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index 83d17d9e0bc8..5a160b7e4fce 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -31,12 +31,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/hardware.h>
+#include "board-mx31lite.h"
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31lite.h>
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
 /*
 * This file contains board-specific initialization routines for the
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index cc285e507286..52d5b1574721 100644
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -22,12 +22,11 @@
 #include <linux/usb/otg.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx3.h>
-#include <mach/hardware.h>
-#include <mach/ulpi.h>
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 static unsigned int devboard_pins[] = {
        /* UART1 */
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index 135c90e3a45f..a4f43e90f3c1 100644
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -24,14 +24,13 @@
 #include <linux/usb/otg.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ulpi.h>
 #include <media/soc_camera.h>
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 static unsigned int marxbot_pins[] = {
        /* SDHC2 */
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index fabb801e7994..04ae45dbfaa7 100644
--- a/arch/arm/mach-imx/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -23,15 +23,14 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31moboard.h>
-#include <mach/ulpi.h>
 #include <media/soc_camera.h>
+#include "board-mx31moboard.h"
+#include "common.h"
 #include "devices-imx31.h"
+#include "hardware.h"
+#include "iomux-mx3.h"
+#include "ulpi.h"
 static unsigned int smartbot_pins[] = {
        /* UART1 */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/mach-imx/mx35.h
index 2af5d3a699c7..2af5d3a699c7 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/mach-imx/mx35.h
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/mach-imx/mx3x.h
index 96fb4fbc8ad7..96fb4fbc8ad7 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/mach-imx/mx3x.h
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/mach-imx/mx50.h
index 09ac19c1570c..09ac19c1570c 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/mach-imx/mx50.h
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/mach-imx/mx51.h
index af844f76261a..af844f76261a 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/mach-imx/mx51.h
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/mach-imx/mx53.h
index f829d1c22501..f829d1c22501 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/mach-imx/mx53.h
diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/mach-imx/mx6q.h
index f7e7dbac8f4b..19d3f54db5af 100644
--- a/arch/arm/plat-mxc/include/mach/mx6q.h
+++ b/arch/arm/mach-imx/mx6q.h
@@ -27,9 +27,5 @@
 #define MX6Q_CCM_SIZE                   0x4000
 #define MX6Q_ANATOP_BASE_ADDR           0x020c8000
 #define MX6Q_ANATOP_SIZE                0x1000
-#define MX6Q_UART2_BASE_ADDR            0x021e8000
-#define MX6Q_UART2_SIZE                 0x4000
-#define MX6Q_UART4_BASE_ADDR            0x021f0000
-#define MX6Q_UART4_SIZE                 0x4000
 #endif  /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/mach-imx/mxc.h
index d78298366a91..d78298366a91 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index 9917e2ff51da..51c608234089 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -23,11 +23,10 @@
 #include <asm/mach/arch.h>
-#include <mach/common.h>
+#include "common.h"
-#include <mach/iomux-mx27.h>
-#include <mach/hardware.h>
 #include "devices-imx27.h"
+#include "hardware.h"
+#include "iomux-mx27.h"
 static const int pcm970_pins[] __initconst = {
        /* SDHC */
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 2ac43e1a2dfd..3777b805b76b 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -16,8 +16,9 @@
 #include <asm/smp_scu.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
+#include "common.h"
+#include "hardware.h"
 static void __iomem *scu_base;
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index 6fcffa7db978..56d02d064fbf 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -10,7 +10,8 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
+#include "hardware.h"
 static int mx27_suspend_enter(suspend_state_t state)
 {
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
index 822103bdb709..6a07006ff0f4 100644
--- a/arch/arm/mach-imx/pm-imx3.c
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -9,10 +9,11 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
 #include <linux/io.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
+#include "common.h"
-#include <mach/devices-common.h>
 #include "crmregs-imx3.h"
+#include "devices/devices-common.h"
+#include "hardware.h"
 /*
 * Set cpu low power mode before WFI instruction. This function is called
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 19621ed1ffa5..2e063c2deb9e 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -16,10 +16,11 @@
 #include <asm/cacheflush.h>
 #include <asm/system_misc.h>
 #include <asm/tlbflush.h>
-#include <mach/common.h>
-#include <mach/cpuidle.h>
+#include "common.h"
-#include <mach/hardware.h>
+#include "cpuidle.h"
 #include "crm-regs-imx5.h"
+#include "hardware.h"
 /*
 * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index f7b0c2b1b905..a17543da602d 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -18,8 +18,9 @@
 #include <asm/proc-fns.h>
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
+#include "common.h"
+#include "hardware.h"
 extern unsigned long phys_l2x0_saved_regs;
diff --git a/arch/arm/plat-mxc/ssi-fiq-ksym.c b/arch/arm/mach-imx/ssi-fiq-ksym.c
index 792090f9a032..792090f9a032 100644
--- a/arch/arm/plat-mxc/ssi-fiq-ksym.c
+++ b/arch/arm/mach-imx/ssi-fiq-ksym.c
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/mach-imx/ssi-fiq.S
index a8b93c5f29b5..a8b93c5f29b5 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/mach-imx/ssi-fiq.S
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/mach-imx/system.c
index 3da78cfc5a94..695e0d73bf85 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -22,12 +22,13 @@
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
 #include <asm/system_misc.h>
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
+#include "common.h"
+#include "hardware.h"
 static void __iomem *wdog_base;
 /*
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/mach-imx/time.c
index a17abcf98325..f017302f6d09 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -27,10 +27,11 @@
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <mach/hardware.h>
 #include <asm/sched_clock.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
+#include "common.h"
+#include "hardware.h"
 /*
 * There are 2 versions of the timer hardware on Freescale MXC hardware.
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/mach-imx/tzic.c
index 3ed1adbc09f8..9721161f208f 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -21,10 +21,8 @@
 #include <asm/mach/irq.h>
 #include <asm/exception.h>
-#include <mach/hardware.h>
+#include "common.h"
-#include <mach/common.h>
+#include "hardware.h"
-#include <mach/irqs.h>
 #include "irq-common.h"
 /*
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/mach-imx/ulpi.c
index d2963427184f..0f051957d10c 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/mach-imx/ulpi.c
@@ -24,7 +24,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
+#include "ulpi.h"
 /* ULPIVIEW register bits */
 #define ULPIVW_WU               (1 << 31)       /* Wakeup */
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/mach-imx/ulpi.h
index 42bdaca6d7d9..42bdaca6d7d9 100644
--- a/arch/arm/plat-mxc/include/mach/ulpi.h
+++ b/arch/arm/mach-imx/ulpi.h
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 350e26636a06..abeff25532ab 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -8,6 +8,7 @@ config ARCH_INTEGRATOR_AP
        select MIGHT_HAVE_PCI
        select SERIAL_AMBA_PL010
        select SERIAL_AMBA_PL010_CONSOLE
+        select SOC_BUS
        help
          Include support for the ARM(R) Integrator/AP and
          Integrator/PP2 platforms.
@@ -19,6 +20,7 @@ config ARCH_INTEGRATOR_CP
        select PLAT_VERSATILE_CLCD
        select SERIAL_AMBA_PL011
        select SERIAL_AMBA_PL011_CONSOLE
+        select SOC_BUS
        help
          Include support for the ARM(R) Integrator CP platform.
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index c3ff21b5ea24..79197d8b34aa 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,6 +1,12 @@
 #include <linux/amba/serial.h>
-extern struct amba_pl010_data integrator_uart_data;
+#ifdef CONFIG_ARCH_INTEGRATOR_AP
+extern struct amba_pl010_data ap_uart_data;
+#else
+/* Not used without Integrator/AP support anyway */
+struct amba_pl010_data ap_uart_data {};
+#endif
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
 void integrator_restart(char, const char *);
+void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index ea22a17246d7..39c060f75e47 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -18,10 +18,10 @@
 #include <linux/memblock.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
-#include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
 #include <linux/io.h>
+#include <linux/stat.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -46,10 +46,10 @@ static AMBA_APB_DEVICE(rtc, "rtc", 0,
        INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
 static AMBA_APB_DEVICE(uart0, "uart0", 0,
-        INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
+        INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL);
 static AMBA_APB_DEVICE(uart1, "uart1", 0,
-        INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
+        INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL);
 static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
 static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
@@ -77,6 +77,8 @@ int __init integrator_init(bool is_cp)
                uart1_device.periphid   = 0x00041010;
                kmi0_device.periphid    = 0x00041050;
                kmi1_device.periphid    = 0x00041050;
+                uart0_device.dev.platform_data = &ap_uart_data;
+                uart1_device.dev.platform_data = &ap_uart_data;
        }
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
@@ -89,49 +91,6 @@ int __init integrator_init(bool is_cp)
 #endif
-/*
- * On the Integrator platform, the port RTS and DTR are provided by
- * bits in the following SC_CTRLS register bits:
- *        RTS  DTR
- *  UART0  7    6
- *  UART1  5    4
- */
-#define SC_CTRLC        __io_address(INTEGRATOR_SC_CTRLC)
-#define SC_CTRLS        __io_address(INTEGRATOR_SC_CTRLS)
-static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
-{
-        unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
-        u32 phybase = dev->res.start;
-        if (phybase == INTEGRATOR_UART0_BASE) {
-                /* UART0 */
-                rts_mask = 1 << 4;
-                dtr_mask = 1 << 5;
-        } else {
-                /* UART1 */
-                rts_mask = 1 << 6;
-                dtr_mask = 1 << 7;
-        }
-        if (mctrl & TIOCM_RTS)
-                ctrlc |= rts_mask;
-        else
-                ctrls |= rts_mask;
-        if (mctrl & TIOCM_DTR)
-                ctrlc |= dtr_mask;
-        else
-                ctrls |= dtr_mask;
-        __raw_writel(ctrls, SC_CTRLS);
-        __raw_writel(ctrlc, SC_CTRLC);
-}
-struct amba_pl010_data integrator_uart_data = {
-        .set_mctrl = integrator_uart_set_mctrl,
-};
 static DEFINE_RAW_SPINLOCK(cm_lock);
 /**
@@ -169,3 +128,93 @@ void integrator_restart(char mode, const char *cmd)
 {
        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 }
+static u32 integrator_id;
+static ssize_t intcp_get_manf(struct device *dev,
+                              struct device_attribute *attr,
+                              char *buf)
+{
+        return sprintf(buf, "%02x\n", integrator_id >> 24);
+}
+static struct device_attribute intcp_manf_attr =
+        __ATTR(manufacturer,  S_IRUGO, intcp_get_manf,  NULL);
+static ssize_t intcp_get_arch(struct device *dev,
+                              struct device_attribute *attr,
+                              char *buf)
+{
+        const char *arch;
+        switch ((integrator_id >> 16) & 0xff) {
+        case 0x00:
+                arch = "ASB little-endian";
+                break;
+        case 0x01:
+                arch = "AHB little-endian";
+                break;
+        case 0x03:
+                arch = "AHB-Lite system bus, bi-endian";
+                break;
+        case 0x04:
+                arch = "AHB";
+                break;
+        default:
+                arch = "Unknown";
+                break;
+        }
+        return sprintf(buf, "%s\n", arch);
+}
+static struct device_attribute intcp_arch_attr =
+        __ATTR(architecture,  S_IRUGO, intcp_get_arch,  NULL);
+static ssize_t intcp_get_fpga(struct device *dev,
+                              struct device_attribute *attr,
+                              char *buf)
+{
+        const char *fpga;
+        switch ((integrator_id >> 12) & 0xf) {
+        case 0x01:
+                fpga = "XC4062";
+                break;
+        case 0x02:
+                fpga = "XC4085";
+                break;
+        case 0x04:
+                fpga = "EPM7256AE (Altera PLD)";
+                break;
+        default:
+                fpga = "Unknown";
+                break;
+        }
+        return sprintf(buf, "%s\n", fpga);
+}
+static struct device_attribute intcp_fpga_attr =
+        __ATTR(fpga,  S_IRUGO, intcp_get_fpga,  NULL);
+static ssize_t intcp_get_build(struct device *dev,
+                               struct device_attribute *attr,
+                               char *buf)
+{
+        return sprintf(buf, "%02x\n", (integrator_id >> 4) & 0xFF);
+}
+static struct device_attribute intcp_build_attr =
+        __ATTR(build,  S_IRUGO, intcp_get_build,  NULL);
+void integrator_init_sysfs(struct device *parent, u32 id)
+{
+        integrator_id = id;
+        device_create_file(parent, &intcp_manf_attr);
+        device_create_file(parent, &intcp_arch_attr);
+        device_create_file(parent, &intcp_fpga_attr);
+        device_create_file(parent, &intcp_build_attr);
+}
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index e428f3ab15c7..9f82f9dcbb98 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -21,10 +21,9 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-integrator.h>
 #include <linux/slab.h>
-#include <linux/clkdev.h>
-#include <asm/hardware/icst.h>
 #include <mach/lm.h>
 #include <mach/impd1.h>
 #include <asm/sizes.h>
@@ -36,45 +35,6 @@ MODULE_PARM_DESC(lmid, "logic module stack position");
 struct impd1_module {
        void __iomem    *base;
-        struct clk      vcos[2];
-        struct clk_lookup *clks[3];
-};
-static const struct icst_params impd1_vco_params = {
-        .ref            = 24000000,     /* 24 MHz */
-        .vco_max        = ICST525_VCO_MAX_3V,
-        .vco_min        = ICST525_VCO_MIN,
-        .vd_min         = 12,
-        .vd_max         = 519,
-        .rd_min         = 3,
-        .rd_max         = 120,
-        .s2div          = icst525_s2div,
-        .idx2s          = icst525_idx2s,
-};
-static void impd1_setvco(struct clk *clk, struct icst_vco vco)
-{
-        struct impd1_module *impd1 = clk->data;
-        u32 val = vco.v | (vco.r << 9) | (vco.s << 16);
-        writel(0xa05f, impd1->base + IMPD1_LOCK);
-        writel(val, clk->vcoreg);
-        writel(0, impd1->base + IMPD1_LOCK);
-#ifdef DEBUG
-        vco.v = val & 0x1ff;
-        vco.r = (val >> 9) & 0x7f;
-        vco.s = (val >> 16) & 7;
-        pr_debug("IM-PD1: VCO%d clock is %ld Hz\n",
-                 vconr, icst525_hz(&impd1_vco_params, vco));
-#endif
-}
-static const struct clk_ops impd1_clk_ops = {
-        .round  = icst_clk_round,
-        .set    = icst_clk_set,
-        .setvco = impd1_setvco,
 };
 void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
@@ -344,10 +304,6 @@ static struct impd1_device impd1_devs[] = {
        }
 };
-static struct clk fixed_14745600 = {
-        .rate = 14745600,
-};
 static int impd1_probe(struct lm_device *dev)
 {
        struct impd1_module *impd1;
@@ -376,23 +332,7 @@ static int impd1_probe(struct lm_device *dev)
        printk("IM-PD1 found at 0x%08lx\n",
                (unsigned long)dev->resource.start);
-        for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) {
+        integrator_impd1_clk_init(impd1->base, dev->id);
-                impd1->vcos[i].ops = &impd1_clk_ops,
-                impd1->vcos[i].owner = THIS_MODULE,
-                impd1->vcos[i].params = &impd1_vco_params,
-                impd1->vcos[i].data = impd1;
-        }
-        impd1->vcos[0].vcoreg = impd1->base + IMPD1_OSC1;
-        impd1->vcos[1].vcoreg = impd1->base + IMPD1_OSC2;
-        impd1->clks[0] = clkdev_alloc(&impd1->vcos[0], NULL, "lm%x:01000",
-                                        dev->id);
-        impd1->clks[1] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00100",
-                                        dev->id);
-        impd1->clks[2] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00200",
-                                        dev->id);
-        for (i = 0; i < ARRAY_SIZE(impd1->clks); i++)
-                clkdev_add(impd1->clks[i]);
        for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) {
                struct impd1_device *idev = impd1_devs + i;
@@ -402,9 +342,10 @@ static int impd1_probe(struct lm_device *dev)
                pc_base = dev->resource.start + idev->offset;
                snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
-                d = amba_ahb_device_add(&dev->dev, devname, pc_base, SZ_4K,
+                d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K,
-                                        dev->irq, dev->irq,
+                                            dev->irq, dev->irq,
-                                        idev->platform_data, idev->id);
+                                            idev->platform_data, idev->id,
+                                            &dev->resource);
                if (IS_ERR(d)) {
                        dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d));
                        continue;
@@ -431,12 +372,9 @@ static int impd1_remove_one(struct device *dev, void *data)
 static void impd1_remove(struct lm_device *dev)
 {
        struct impd1_module *impd1 = lm_get_drvdata(dev);
-        int i;
        device_for_each_child(&dev->dev, NULL, impd1_remove_one);
+        integrator_impd1_clk_exit(dev->id);
-        for (i = 0; i < ARRAY_SIZE(impd1->clks); i++)
-                clkdev_drop(impd1->clks[i]);
        lm_set_drvdata(dev, NULL);
diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h
index 7371018455d2..eff0adad9ae3 100644
--- a/arch/arm/mach-integrator/include/mach/irqs.h
+++ b/arch/arm/mach-integrator/include/mach/irqs.h
@@ -19,64 +19,63 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/* 
+/*
- *  Interrupt numbers
+ * Interrupt numbers, all of the above are just static reservations
+ * used so they can be encoded into device resources. They will finally
+ * be done away with when switching to device tree.
 */
-#define IRQ_PIC_START                   1
+#define IRQ_PIC_START                   64
-#define IRQ_SOFTINT                     1
+#define IRQ_SOFTINT                     (IRQ_PIC_START+0)
-#define IRQ_UARTINT0                    2
+#define IRQ_UARTINT0                    (IRQ_PIC_START+1)
-#define IRQ_UARTINT1                    3
+#define IRQ_UARTINT1                    (IRQ_PIC_START+2)
-#define IRQ_KMIINT0                     4
+#define IRQ_KMIINT0                     (IRQ_PIC_START+3)
-#define IRQ_KMIINT1                     5
+#define IRQ_KMIINT1                     (IRQ_PIC_START+4)
-#define IRQ_TIMERINT0                   6
+#define IRQ_TIMERINT0                   (IRQ_PIC_START+5)
-#define IRQ_TIMERINT1                   7
+#define IRQ_TIMERINT1                   (IRQ_PIC_START+6)
-#define IRQ_TIMERINT2                   8
+#define IRQ_TIMERINT2                   (IRQ_PIC_START+7)
-#define IRQ_RTCINT                      9
+#define IRQ_RTCINT                      (IRQ_PIC_START+8)
-#define IRQ_AP_EXPINT0                  10
+#define IRQ_AP_EXPINT0                  (IRQ_PIC_START+9)
-#define IRQ_AP_EXPINT1                  11
+#define IRQ_AP_EXPINT1                  (IRQ_PIC_START+10)
-#define IRQ_AP_EXPINT2                  12
+#define IRQ_AP_EXPINT2                  (IRQ_PIC_START+11)
-#define IRQ_AP_EXPINT3                  13
+#define IRQ_AP_EXPINT3                  (IRQ_PIC_START+12)
-#define IRQ_AP_PCIINT0                  14
+#define IRQ_AP_PCIINT0                  (IRQ_PIC_START+13)
-#define IRQ_AP_PCIINT1                  15
+#define IRQ_AP_PCIINT1                  (IRQ_PIC_START+14)
-#define IRQ_AP_PCIINT2                  16
+#define IRQ_AP_PCIINT2                  (IRQ_PIC_START+15)
-#define IRQ_AP_PCIINT3                  17
+#define IRQ_AP_PCIINT3                  (IRQ_PIC_START+16)
-#define IRQ_AP_V3INT                    18
+#define IRQ_AP_V3INT                    (IRQ_PIC_START+17)
-#define IRQ_AP_CPINT0                   19
+#define IRQ_AP_CPINT0                   (IRQ_PIC_START+18)
-#define IRQ_AP_CPINT1                   20
+#define IRQ_AP_CPINT1                   (IRQ_PIC_START+19)
-#define IRQ_AP_LBUSTIMEOUT              21
+#define IRQ_AP_LBUSTIMEOUT              (IRQ_PIC_START+20)
-#define IRQ_AP_APCINT                   22
+#define IRQ_AP_APCINT                   (IRQ_PIC_START+21)
-#define IRQ_CP_CLCDCINT                 23
+#define IRQ_CP_CLCDCINT                 (IRQ_PIC_START+22)
-#define IRQ_CP_MMCIINT0                 24
+#define IRQ_CP_MMCIINT0                 (IRQ_PIC_START+23)
-#define IRQ_CP_MMCIINT1                 25
+#define IRQ_CP_MMCIINT1                 (IRQ_PIC_START+24)
-#define IRQ_CP_AACIINT                  26
+#define IRQ_CP_AACIINT                  (IRQ_PIC_START+25)
-#define IRQ_CP_CPPLDINT                 27
+#define IRQ_CP_CPPLDINT                 (IRQ_PIC_START+26)
-#define IRQ_CP_ETHINT                   28
+#define IRQ_CP_ETHINT                   (IRQ_PIC_START+27)
-#define IRQ_CP_TSPENINT                 29
+#define IRQ_CP_TSPENINT                 (IRQ_PIC_START+28)
-#define IRQ_PIC_END                     29
+#define IRQ_PIC_END                     (IRQ_PIC_START+28)
-#define IRQ_CIC_START                   32
+#define IRQ_CIC_START                   (IRQ_PIC_END+1)
-#define IRQ_CM_SOFTINT                  32
+#define IRQ_CM_SOFTINT                  (IRQ_CIC_START+0)
-#define IRQ_CM_COMMRX                   33
+#define IRQ_CM_COMMRX                   (IRQ_CIC_START+1)
-#define IRQ_CM_COMMTX                   34
+#define IRQ_CM_COMMTX                   (IRQ_CIC_START+2)
-#define IRQ_CIC_END                     34
+#define IRQ_CIC_END                     (IRQ_CIC_START+2)
 /*
 * IntegratorCP only
 */
-#define IRQ_SIC_START                   35
+#define IRQ_SIC_START                   (IRQ_CIC_END+1)
-#define IRQ_SIC_CP_SOFTINT              35
+#define IRQ_SIC_CP_SOFTINT              (IRQ_SIC_START+0)
-#define IRQ_SIC_CP_RI0                  36
+#define IRQ_SIC_CP_RI0                  (IRQ_SIC_START+1)
-#define IRQ_SIC_CP_RI1                  37
+#define IRQ_SIC_CP_RI1                  (IRQ_SIC_START+2)
-#define IRQ_SIC_CP_CARDIN               38
+#define IRQ_SIC_CP_CARDIN               (IRQ_SIC_START+3)
-#define IRQ_SIC_CP_LMINT0               39
+#define IRQ_SIC_CP_LMINT0               (IRQ_SIC_START+4)
-#define IRQ_SIC_CP_LMINT1               40
+#define IRQ_SIC_CP_LMINT1               (IRQ_SIC_START+5)
-#define IRQ_SIC_CP_LMINT2               41
+#define IRQ_SIC_CP_LMINT2               (IRQ_SIC_START+6)
-#define IRQ_SIC_CP_LMINT3               42
+#define IRQ_SIC_CP_LMINT3               (IRQ_SIC_START+7)
-#define IRQ_SIC_CP_LMINT4               43
+#define IRQ_SIC_CP_LMINT4               (IRQ_SIC_START+8)
-#define IRQ_SIC_CP_LMINT5               44
+#define IRQ_SIC_CP_LMINT5               (IRQ_SIC_START+9)
-#define IRQ_SIC_CP_LMINT6               45
+#define IRQ_SIC_CP_LMINT6               (IRQ_SIC_START+10)
-#define IRQ_SIC_CP_LMINT7               46
+#define IRQ_SIC_CP_LMINT7               (IRQ_SIC_START+11)
-#define IRQ_SIC_END                     46
+#define IRQ_SIC_END                     (IRQ_SIC_START+11)
-#define NR_IRQS_INTEGRATOR_AP           34
-#define NR_IRQS_INTEGRATOR_CP           47
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index efeac5d0bc9e..be5859efe10e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -190,7 +190,6 @@
 #define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
 #define INTEGRATOR_SC_DEC_OFFSET        0x10
 #define INTEGRATOR_SC_ARB_OFFSET        0x14
-#define INTEGRATOR_SC_PCIENABLE_OFFSET  0x18
 #define INTEGRATOR_SC_LOCK_OFFSET       0x1C
 #define INTEGRATOR_SC_BASE              0x11000000
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index e6617c134faf..11e2a4145807 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,12 +31,16 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/stat.h>
+#include <linux/sys_soc.h>
+#include <linux/termios.h>
 #include <video/vga.h>
 #include <mach/hardware.h>
@@ -56,11 +60,12 @@
 #include <asm/mach/pci.h>
 #include <asm/mach/time.h>
-#include <plat/fpga-irq.h>
 #include "common.h"
-/* 
+/* Base address to the AP system controller */
+void __iomem *ap_syscon_base;
+/*
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
@@ -68,7 +73,6 @@
 * just for now).
 */
 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
-#define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
@@ -97,11 +101,6 @@ static struct map_desc ap_io_desc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
                .length         = SZ_4K,
@@ -122,11 +121,6 @@ static struct map_desc ap_io_desc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
                .length         = SZ_4K,
@@ -201,8 +195,6 @@ device_initcall(irq_syscore_init);
 /*
 * Flash handling.
 */
-#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
-#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
@@ -210,7 +202,8 @@ static int ap_flash_init(struct platform_device *dev)
 {
        u32 tmp;
-        writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
+        writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
+               ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
        tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
        writel(tmp, EBI_CSR1);
@@ -227,7 +220,8 @@ static void ap_flash_exit(struct platform_device *dev)
 {
        u32 tmp;
-        writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
+        writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
+               ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
        tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
        writel(tmp, EBI_CSR1);
@@ -241,9 +235,12 @@ static void ap_flash_exit(struct platform_device *dev)
 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 {
-        void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
+        if (on)
+                writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
-        writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
+                       ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
+        else
+                writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
+                       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 }
 static struct physmap_flash_data ap_flash_data = {
@@ -254,6 +251,45 @@ static struct physmap_flash_data ap_flash_data = {
 };
 /*
+ * For the PL010 found in the Integrator/AP some of the UART control is
+ * implemented in the system controller and accessed using a callback
+ * from the driver.
+ */
+static void integrator_uart_set_mctrl(struct amba_device *dev,
+                                void __iomem *base, unsigned int mctrl)
+{
+        unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
+        u32 phybase = dev->res.start;
+        if (phybase == INTEGRATOR_UART0_BASE) {
+                /* UART0 */
+                rts_mask = 1 << 4;
+                dtr_mask = 1 << 5;
+        } else {
+                /* UART1 */
+                rts_mask = 1 << 6;
+                dtr_mask = 1 << 7;
+        }
+        if (mctrl & TIOCM_RTS)
+                ctrlc |= rts_mask;
+        else
+                ctrls |= rts_mask;
+        if (mctrl & TIOCM_DTR)
+                ctrlc |= dtr_mask;
+        else
+                ctrls |= dtr_mask;
+        __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
+        __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
+}
+struct amba_pl010_data ap_uart_data = {
+        .set_mctrl = integrator_uart_set_mctrl,
+};
+/*
 * Where is the timer (VA)?
 */
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
@@ -450,9 +486,9 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
                "rtc", NULL),
        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
-                "uart0", &integrator_uart_data),
+                "uart0", &ap_uart_data),
        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
-                "uart1", &integrator_uart_data),
+                "uart1", &ap_uart_data),
        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
                "kmi0", NULL),
        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
@@ -465,12 +501,60 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 static void __init ap_init_of(void)
 {
        unsigned long sc_dec;
+        struct device_node *root;
+        struct device_node *syscon;
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+        u32 ap_sc_id;
+        int err;
        int i;
-        of_platform_populate(NULL, of_default_bus_match_table,
+        /* Here we create an SoC device for the root node */
-                        ap_auxdata_lookup, NULL);
+        root = of_find_node_by_path("/");
+        if (!root)
+                return;
+        syscon = of_find_node_by_path("/syscon");
+        if (!syscon)
+                return;
+        ap_syscon_base = of_iomap(syscon, 0);
+        if (!ap_syscon_base)
+                return;
+        ap_sc_id = readl(ap_syscon_base);
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+        err = of_property_read_string(root, "compatible",
+                                      &soc_dev_attr->soc_id);
+        if (err)
+                return;
+        err = of_property_read_string(root, "model", &soc_dev_attr->machine);
+        if (err)
+                return;
+        soc_dev_attr->family = "Integrator";
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
+                                           'A' + (ap_sc_id & 0x0f));
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR_OR_NULL(soc_dev)) {
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr);
+                return;
+        }
+        parent = soc_device_to_device(soc_dev);
+        if (!IS_ERR_OR_NULL(parent))
+                integrator_init_sysfs(parent, ap_sc_id);
-        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        of_platform_populate(root, of_default_bus_match_table,
+                        ap_auxdata_lookup, parent);
+        sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
        for (i = 0; i < 4; i++) {
                struct lm_device *lmdev;
@@ -499,7 +583,6 @@ static const char * ap_dt_board_compat[] = {
 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
        .reserve        = integrator_reserve,
        .map_io         = ap_map_io,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
        .init_early     = ap_init_early,
        .init_irq       = ap_init_irq_of,
        .handle_irq     = fpga_handle_irq,
@@ -514,6 +597,27 @@ MACHINE_END
 #ifdef CONFIG_ATAGS
 /*
+ * For the ATAG boot some static mappings are needed. This will
+ * go away with the ATAG support down the road.
+ */
+static struct map_desc ap_io_desc_atag[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
+                .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE
+        },
+};
+static void __init ap_map_io_atag(void)
+{
+        iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
+        ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
+        ap_map_io();
+}
+/*
 * This is where non-devicetree initialization code is collected and stashed
 * for eventual deletion.
 */
@@ -581,7 +685,7 @@ static void __init ap_init(void)
        platform_device_register(&cfi_flash_device);
-        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
        for (i = 0; i < 4; i++) {
                struct lm_device *lmdev;
@@ -608,8 +712,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
        .reserve        = integrator_reserve,
-        .map_io         = ap_map_io,
+        .map_io         = ap_map_io_atag,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
        .init_early     = ap_init_early,
        .init_irq       = ap_init_irq,
        .handle_irq     = fpga_handle_irq,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 5b08e8e4cc83..7322838c0447 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -20,12 +20,14 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/sys_soc.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -46,16 +48,17 @@
 #include <asm/hardware/timer-sp.h>
 #include <plat/clcd.h>
-#include <plat/fpga-irq.h>
 #include <plat/sched_clock.h>
 #include "common.h"
+/* Base address to the CP controller */
+static void __iomem *intcp_con_base;
 #define INTCP_PA_FLASH_BASE             0x24000000
 #define INTCP_PA_CLCD_BASE              0xc0000000
-#define INTCP_VA_CTRL_BASE              __io_address(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
@@ -82,11 +85,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
                .length         = SZ_4K,
@@ -107,11 +105,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
                .length         = SZ_4K,
@@ -126,11 +119,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
        }
 };
@@ -146,9 +134,9 @@ static int intcp_flash_init(struct platform_device *dev)
 {
        u32 val;
-        val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+        val = readl(intcp_con_base + INTCP_FLASHPROG);
        val |= CINTEGRATOR_FLASHPROG_FLWREN;
-        writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+        writel(val, intcp_con_base + INTCP_FLASHPROG);
        return 0;
 }
@@ -157,21 +145,21 @@ static void intcp_flash_exit(struct platform_device *dev)
 {
        u32 val;
-        val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+        val = readl(intcp_con_base + INTCP_FLASHPROG);
        val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
-        writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+        writel(val, intcp_con_base + INTCP_FLASHPROG);
 }
 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
 {
        u32 val;
-        val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+        val = readl(intcp_con_base + INTCP_FLASHPROG);
        if (on)
                val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
        else
                val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
-        writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
+        writel(val, intcp_con_base + INTCP_FLASHPROG);
 }
 static struct physmap_flash_data intcp_flash_data = {
@@ -190,7 +178,7 @@ static struct physmap_flash_data intcp_flash_data = {
 static unsigned int mmc_status(struct device *dev)
 {
        unsigned int status = readl(__io_address(0xca000000 + 4));
-        writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
+        writel(8, intcp_con_base + 8);
        return status & 8;
 }
@@ -318,9 +306,9 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
                "rtc", NULL),
        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
-                "uart0", &integrator_uart_data),
+                "uart0", NULL),
        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
-                "uart1", &integrator_uart_data),
+                "uart1", NULL),
        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
                "kmi0", NULL),
        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
@@ -338,8 +326,57 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 static void __init intcp_init_of(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
+        struct device_node *root;
-                        intcp_auxdata_lookup, NULL);
+        struct device_node *cpcon;
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+        u32 intcp_sc_id;
+        int err;
+        /* Here we create an SoC device for the root node */
+        root = of_find_node_by_path("/");
+        if (!root)
+                return;
+        cpcon = of_find_node_by_path("/cpcon");
+        if (!cpcon)
+                return;
+        intcp_con_base = of_iomap(cpcon, 0);
+        if (!intcp_con_base)
+                return;
+        intcp_sc_id = readl(intcp_con_base);
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+        err = of_property_read_string(root, "compatible",
+                                      &soc_dev_attr->soc_id);
+        if (err)
+                return;
+        err = of_property_read_string(root, "model", &soc_dev_attr->machine);
+        if (err)
+                return;
+        soc_dev_attr->family = "Integrator";
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
+                                           'A' + (intcp_sc_id & 0x0f));
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR_OR_NULL(soc_dev)) {
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr);
+                return;
+        }
+        parent = soc_device_to_device(soc_dev);
+        if (!IS_ERR_OR_NULL(parent))
+                integrator_init_sysfs(parent, intcp_sc_id);
+        of_platform_populate(root, of_default_bus_match_table,
+                        intcp_auxdata_lookup, parent);
 }
 static const char * intcp_dt_board_compat[] = {
@@ -350,7 +387,6 @@ static const char * intcp_dt_board_compat[] = {
 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
        .reserve        = integrator_reserve,
        .map_io         = intcp_map_io,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
        .init_early     = intcp_init_early,
        .init_irq       = intcp_init_irq_of,
        .handle_irq     = fpga_handle_irq,
@@ -365,6 +401,28 @@ MACHINE_END
 #ifdef CONFIG_ATAGS
 /*
+ * For the ATAG boot some static mappings are needed. This will
+ * go away with the ATAG support down the road.
+ */
+static struct map_desc intcp_io_desc_atag[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
+                .pfn            = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE
+        },
+};
+static void __init intcp_map_io_atag(void)
+{
+        iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
+        intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
+        intcp_map_io();
+}
+/*
 * This is where non-devicetree initialization code is collected and stashed
 * for eventual deletion.
 */
@@ -423,7 +481,7 @@ static void __init intcp_init_irq(void)
        u32 pic_mask, cic_mask, sic_mask;
        /* These masks are for the HW IRQ registers */
-        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+        pic_mask = ~((~0u) << (11 - 0));
        pic_mask |= (~((~0u) << (29 - 22))) << 22;
        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
@@ -503,8 +561,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
        .reserve        = integrator_reserve,
-        .map_io         = intcp_map_io,
+        .map_io         = intcp_map_io_atag,
-        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
        .init_early     = intcp_init_early,
        .init_irq       = intcp_init_irq,
        .handle_irq     = fpga_handle_irq,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index bbeca59df66b..be50e795536d 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -191,12 +191,9 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
        /*
         * Trap out illegal values
         */
-        if (offset > 255)
+        BUG_ON(offset > 255);
-                BUG();
+        BUG_ON(busnr > 255);
-        if (busnr > 255)
+        BUG_ON(devfn > 255);
-                BUG();
-        if (devfn > 255)
-                BUG();
        if (busnr == 0) {
                int slot = PCI_SLOT(devfn);
@@ -388,9 +385,10 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
 * means I can't get additional information on the reason for the pm2fb
 * problems.  I suppose I'll just have to mind-meld with the machine. ;)
 */
-#define SC_PCI     __io_address(INTEGRATOR_SC_PCIENABLE)
+static void __iomem *ap_syscon_base;
-#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20)
+#define INTEGRATOR_SC_PCIENABLE_OFFSET  0x18
-#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24)
+#define INTEGRATOR_SC_LBFADDR_OFFSET    0x20
+#define INTEGRATOR_SC_LBFCODE_OFFSET    0x24
 static int
 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -401,13 +399,13 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
        char buf[128];
        sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
-                addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
+                addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
                v3_readb(V3_LB_ISTAT));
        printk(KERN_DEBUG "%s", buf);
 #endif
        v3_writeb(V3_LB_ISTAT, 0);
-        __raw_writel(3, SC_PCI);
+        __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
        /*
         * If the instruction being executed was a read,
@@ -449,15 +447,15 @@ static irqreturn_t v3_irq(int dummy, void *devid)
        sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
                "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
-                __raw_readl(SC_LBFADDR),
+                __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
-                __raw_readl(SC_LBFCODE) & 255,
+                __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
                v3_readb(V3_LB_ISTAT));
        printascii(buf);
 #endif
        v3_writew(V3_PCI_STAT, 0xf000);
        v3_writeb(V3_LB_ISTAT, 0);
-        __raw_writel(3, SC_PCI);
+        __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
 #ifdef CONFIG_DEBUG_LL
        /*
@@ -480,6 +478,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
        if (nr == 0) {
                sys->mem_offset = PHYS_PCI_MEM_BASE;
                ret = pci_v3_setup_resources(sys);
+                /* Remap the Integrator system controller */
+                ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
+                if (!ap_syscon_base)
+                        return -EINVAL;
        }
        return ret;
@@ -568,7 +570,7 @@ void __init pci_v3_preinit(void)
        v3_writeb(V3_LB_ISTAT, 0);
        v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
        v3_writeb(V3_LB_IMASK, 0x28);
-        __raw_writel(3, SC_PCI);
+        __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
        /*
         * Grab the PCI error interrupt.
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 1694f01ce2b6..6d6bde3e15fa 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -410,6 +410,7 @@ void __init ixp4xx_pci_preinit(void)
                 * Enable the IO window to be way up high, at 0xfffffc00
                 */
                local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
+                local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
        } else {
                printk("PCI: IXP4xx is target - No bus scan performed\n");
        }
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fdf91a160884..8c0c0e2d0727 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -67,15 +67,12 @@ static struct map_desc ixp4xx_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
                .length         = IXP4XX_PCI_CFG_REGION_SIZE,
                .type           = MT_DEVICE
-        },
+        }, {    /* Queue Manager */
-#ifdef CONFIG_DEBUG_LL
+                .virtual        = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
-        {       /* Debug UART mapping */
+                .pfn            = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
-                .virtual        = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
+                .length         = IXP4XX_QMGR_REGION_SIZE,
-                .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
-                .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
                .type           = MT_DEVICE
-        }
+        },
-#endif
 };
 void __init ixp4xx_map_io(void)
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index b800a031207c..53b8348dfcc2 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -15,6 +15,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/pci.h>
+#include <asm/system_info.h>
 #define SLOT_ETHA               0x0B    /* IDSEL = AD21 */
 #define SLOT_ETHB               0x0C    /* IDSEL = AD20 */
@@ -329,7 +330,7 @@ static struct platform_device device_hss_tab[] = {
 };
-static struct platform_device *device_tab[6] __initdata = {
+static struct platform_device *device_tab[7] __initdata = {
        &device_flash,          /* index 0 */
 };
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
index 8c9f8d564492..ff686cbc5df4 100644
--- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -17,8 +17,8 @@
 #else
                mov     \rp, #0
 #endif
-                orr     \rv, \rp, #0xff000000   @ virtual
+                orr     \rv, \rp, #0xfe000000   @ virtual
-                orr     \rv, \rv, #0x00b00000
+                orr     \rv, \rv, #0x00f00000
                orr     \rp, \rp, #0xc8000000   @ physical
                .endm
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index eb68b61ce975..c5bae9c035d5 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -30,51 +30,43 @@
 *
 * 0x50000000   0x10000000      ioremap'd       EXP BUS
 *
- * 0x6000000    0x00004000      ioremap'd       QMgr
+ * 0xC8000000   0x00013000      0xFEF00000      On-Chip Peripherals
 *
- * 0xC0000000   0x00001000      0xffbff000      PCI CFG
+ * 0xC0000000   0x00001000      0xFEF13000      PCI CFG
 *
- * 0xC4000000   0x00001000      0xffbfe000      EXP CFG
+ * 0xC4000000   0x00001000      0xFEF14000      EXP CFG
 *
- * 0xC8000000   0x00013000      0xffbeb000      On-Chip Peripherals
+ * 0x60000000   0x00004000      0xFEF15000      QMgr
 */
 /*
 * Queue Manager
 */
-#define IXP4XX_QMGR_BASE_PHYS           (0x60000000)
+#define IXP4XX_QMGR_BASE_PHYS           0x60000000
-#define IXP4XX_QMGR_REGION_SIZE         (0x00004000)
+#define IXP4XX_QMGR_BASE_VIRT           IOMEM(0xFEF15000)
+#define IXP4XX_QMGR_REGION_SIZE         0x00004000
 /*
- * Expansion BUS Configuration registers
+ * Peripheral space, including debug UART. Must be section-aligned so that
+ * it can be used with the low-level debug code.
 */
-#define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
+#define IXP4XX_PERIPHERAL_BASE_PHYS     0xC8000000
-#define IXP4XX_EXP_CFG_BASE_VIRT        IOMEM(0xFFBFE000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     IOMEM(0xFEF00000)
-#define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
+#define IXP4XX_PERIPHERAL_REGION_SIZE   0x00013000
 /*
 * PCI Config registers
 */
-#define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
+#define IXP4XX_PCI_CFG_BASE_PHYS        0xC0000000
-#define IXP4XX_PCI_CFG_BASE_VIRT        IOMEM(0xFFBFF000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        IOMEM(0xFEF13000)
-#define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
+#define IXP4XX_PCI_CFG_REGION_SIZE      0x00001000
-/*
- * Peripheral space
- */
-#define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     IOMEM(0xFFBEB000)
-#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 /*
- * Debug UART
+ * Expansion BUS Configuration registers
- *
- * This is basically a remap of UART1 into a region that is section
- * aligned so that it * can be used with the low-level debug code.
 */
-#define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
+#define IXP4XX_EXP_CFG_BASE_PHYS        0xC4000000
-#define IXP4XX_DEBUG_UART_BASE_VIRT     IOMEM(0xffb00000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        0xFEF14000
-#define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
+#define IXP4XX_EXP_CFG_REGION_SIZE      0x00001000
 #define IXP4XX_EXP_CS0_OFFSET   0x00
 #define IXP4XX_EXP_CS1_OFFSET   0x04
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
index 9e7cad2d54cb..4de8da536dbb 100644
--- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h
+++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
@@ -86,7 +86,7 @@ void qmgr_release_queue(unsigned int queue);
 static inline void qmgr_put_entry(unsigned int queue, u32 val)
 {
-        extern struct qmgr_regs __iomem *qmgr_regs;
+        struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
 #if DEBUG_QMGR
        BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
@@ -99,7 +99,7 @@ static inline void qmgr_put_entry(unsigned int queue, u32 val)
 static inline u32 qmgr_get_entry(unsigned int queue)
 {
        u32 val;
-        extern struct qmgr_regs __iomem *qmgr_regs;
+        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
        val = __raw_readl(&qmgr_regs->acc[queue][0]);
 #if DEBUG_QMGR
        BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
@@ -112,14 +112,14 @@ static inline u32 qmgr_get_entry(unsigned int queue)
 static inline int __qmgr_get_stat1(unsigned int queue)
 {
-        extern struct qmgr_regs __iomem *qmgr_regs;
+        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
        return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
                >> ((queue & 7) << 2)) & 0xF;
 }
 static inline int __qmgr_get_stat2(unsigned int queue)
 {
-        extern struct qmgr_regs __iomem *qmgr_regs;
+        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
        BUG_ON(queue >= HALF_QUEUES);
        return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
                >> ((queue & 0xF) << 1)) & 0x3;
@@ -145,7 +145,7 @@ static inline int qmgr_stat_empty(unsigned int queue)
 */
 static inline int qmgr_stat_below_low_watermark(unsigned int queue)
 {
-        extern struct qmgr_regs __iomem *qmgr_regs;
+        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
        if (queue >= HALF_QUEUES)
                return (__raw_readl(&qmgr_regs->statne_h) >>
                        (queue - HALF_QUEUES)) & 0x01;
@@ -172,7 +172,7 @@ static inline int qmgr_stat_above_high_watermark(unsigned int queue)
 */
 static inline int qmgr_stat_full(unsigned int queue)
 {
-        extern struct qmgr_regs __iomem *qmgr_regs;
+        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
        if (queue >= HALF_QUEUES)
                return (__raw_readl(&qmgr_regs->statf_h) >>
                        (queue - HALF_QUEUES)) & 0x01;
diff --git a/arch/arm/mach-ixp4xx/include/mach/udc.h b/arch/arm/mach-ixp4xx/include/mach/udc.h
index 80d6da2eafac..7bd8b96c8843 100644
--- a/arch/arm/mach-ixp4xx/include/mach/udc.h
+++ b/arch/arm/mach-ixp4xx/include/mach/udc.h
@@ -2,7 +2,7 @@
 * arch/arm/mach-ixp4xx/include/mach/udc.h
 *
 */
-#include <asm/mach/udc_pxa2xx.h>
+#include <linux/platform_data/pxa2xx_udc.h>
 extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index a17ed79207a4..d4eb09a62863 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -116,7 +116,11 @@
 /* NPE mailbox_status value for reset */
 #define RESET_MBOX_STAT                 0x0000F0F0
-const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
+#define NPE_A_FIRMWARE "NPE-A"
+#define NPE_B_FIRMWARE "NPE-B"
+#define NPE_C_FIRMWARE "NPE-C"
+const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE };
 #define print_npe(pri, npe, fmt, ...)                                   \
        printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
@@ -724,6 +728,9 @@ module_exit(npe_cleanup_module);
 MODULE_AUTHOR("Krzysztof Halasa");
 MODULE_LICENSE("GPL v2");
+MODULE_FIRMWARE(NPE_A_FIRMWARE);
+MODULE_FIRMWARE(NPE_B_FIRMWARE);
+MODULE_FIRMWARE(NPE_C_FIRMWARE);
 EXPORT_SYMBOL(npe_names);
 EXPORT_SYMBOL(npe_running);
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index 852f7c9f87d0..9d1b6b7c394c 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -14,7 +14,7 @@
 #include <linux/module.h>
 #include <mach/qmgr.h>
-struct qmgr_regs __iomem *qmgr_regs;
+static struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
 static struct resource *mem_res;
 static spinlock_t qmgr_lock;
 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
@@ -293,12 +293,6 @@ static int qmgr_init(void)
        if (mem_res == NULL)
                return -EBUSY;
-        qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
-        if (qmgr_regs == NULL) {
-                err = -ENOMEM;
-                goto error_map;
-        }
        /* reset qmgr registers */
        for (i = 0; i < 4; i++) {
                __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
@@ -347,8 +341,6 @@ static int qmgr_init(void)
 error_irq2:
        free_irq(IRQ_IXP4XX_QM1, NULL);
 error_irq:
-        iounmap(qmgr_regs);
-error_map:
        release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
        return err;
 }
@@ -359,7 +351,6 @@ static void qmgr_remove(void)
        free_irq(IRQ_IXP4XX_QM2, NULL);
        synchronize_irq(IRQ_IXP4XX_QM1);
        synchronize_irq(IRQ_IXP4XX_QM2);
-        iounmap(qmgr_regs);
        release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
 }
@@ -369,7 +360,6 @@ module_exit(qmgr_remove);
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Krzysztof Halasa");
-EXPORT_SYMBOL(qmgr_regs);
 EXPORT_SYMBOL(qmgr_set_irq);
 EXPORT_SYMBOL(qmgr_enable_irq);
 EXPORT_SYMBOL(qmgr_disable_irq);
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 2833492eb273..f91cdff5a3e4 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -46,6 +46,11 @@ config MACH_GURUPLUG
 config ARCH_KIRKWOOD_DT
        bool "Marvell Kirkwood Flattened Device Tree"
+        select POWER_SUPPLY
+        select POWER_RESET
+        select POWER_RESET_GPIO
+        select REGULATOR
+        select REGULATOR_FIXED_VOLTAGE
        select MVEBU_CLK_CORE
        select MVEBU_CLK_GATING
        select USE_OF
@@ -132,6 +137,63 @@ config MACH_KM_KIRKWOOD_DT
          Say 'Y' here if you want your kernel to support the
          Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+config MACH_INETSPACE_V2_DT
+        bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the LaCie
+          Internet Space v2 NAS, using Flattened Device Tree.
+config MACH_MPLCEC4_DT
+        bool "MPL CEC4 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          MPL CEC4 (Flattened Device Tree).
+config MACH_NETSPACE_V2_DT
+        bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the LaCie
+          Network Space v2 NAS, using Flattened Device Tree.
+config MACH_NETSPACE_MAX_V2_DT
+        bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the LaCie
+          Network Space Max v2 NAS, using Flattened Device Tree.
+config MACH_NETSPACE_LITE_V2_DT
+        bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the LaCie
+          Network Space Lite v2 NAS, using Flattened Device Tree.
+config MACH_NETSPACE_MINI_V2_DT
+        bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the LaCie
+          Network Space Mini v2 NAS (aka SafeBox), using Flattened
+          Device Tree.
+config MACH_OPENBLOCKS_A6_DT
+        bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Plat'Home OpenBlocks A6 (Flattened Device Tree).
+config MACH_TOPKICK_DT
+        bool "USI Topkick (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          USI Topkick, using Flattened Device Tree
 config MACH_TS219
        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
        help
@@ -218,6 +280,14 @@ config MACH_T5325
          Say 'Y' here if you want your kernel to support the
          HP t5325 Thin Client.
+config MACH_NSA310_DT
+        bool "ZyXEL NSA-310 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        select ARM_ATAG_DTB_COMPAT
+        help
+          Say 'Y' here if you want your kernel to support the
+          ZyXEL NSA-310 board (Flattened Device Tree).
 endmenu
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 294779f892d9..8d2e5a96247c 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -31,3 +31,12 @@ obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
 obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
 obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)       += board-km_kirkwood.o
+obj-$(CONFIG_MACH_INETSPACE_V2_DT)      += board-ns2.o
+obj-$(CONFIG_MACH_MPLCEC4_DT)           += board-mplcec4.o
+obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)  += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)  += board-ns2.o
+obj-$(CONFIG_MACH_NSA310_DT)            += board-nsa310.o
+obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)     += board-openblocks_a6.o
+obj-$(CONFIG_MACH_TOPKICK_DT)           += board-usi_topkick.o
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 43d16d6714b8..a1aa87f09180 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -17,51 +17,11 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data dnskw_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
-static unsigned int dnskw_mpp_config[] __initdata = {
-        MPP13_UART1_TXD,        /* Custom ... */
-        MPP14_UART1_RXD,        /* ... Controller (DNS-320 only) */
-        MPP20_SATA1_ACTn,       /* LED: White Right HDD */
-        MPP21_SATA0_ACTn,       /* LED: White Left HDD */
-        MPP24_GPIO,
-        MPP25_GPIO,
-        MPP26_GPIO,     /* LED: Power */
-        MPP27_GPIO,     /* LED: Red Right HDD */
-        MPP28_GPIO,     /* LED: Red Left HDD */
-        MPP29_GPIO,     /* LED: Red USB (DNS-325 only) */
-        MPP30_GPIO,
-        MPP31_GPIO,
-        MPP32_GPIO,
-        MPP33_GPO,
-        MPP34_GPIO,     /* Button: Front power */
-        MPP35_GPIO,     /* LED: Red USB (DNS-320 only) */
-        MPP36_GPIO,     /* Power: Turn off board */
-        MPP37_GPIO,     /* Power: Turn back on after power failure */
-        MPP38_GPIO,
-        MPP39_GPIO,     /* Power: SATA0 */
-        MPP40_GPIO,     /* Power: SATA1 */
-        MPP41_GPIO,     /* SATA0 present */
-        MPP42_GPIO,     /* SATA1 present */
-        MPP43_GPIO,     /* LED: White USB */
-        MPP44_GPIO,     /* Fan: Tachometer Pin */
-        MPP45_GPIO,     /* Fan: high speed */
-        MPP46_GPIO,     /* Fan: low speed */
-        MPP47_GPIO,     /* Button: Back unmount */
-        MPP48_GPIO,     /* Button: Back reset */
-        MPP49_GPIO,     /* Temp Alarm (DNS-325) Pin of U5 (DNS-320) */
-        0
-};
-static void dnskw_power_off(void)
-{
-        gpio_set_value(36, 1);
-}
 /* Register any GPIO for output and set the value */
 static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 {
@@ -76,22 +36,8 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 void __init dnskw_init(void)
 {
-        kirkwood_mpp_conf(dnskw_mpp_config);
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&dnskw_ge00_data);
-        /* Register power-off GPIO. */
-        if (gpio_request(36, "dnskw:power:off") == 0
-            && gpio_direction_output(36, 0) == 0)
-                pm_power_off = dnskw_power_off;
-        else
-                pr_err("dnskw: failed to configure power-off GPIO\n");
-        /* Ensure power is supplied to both HDDs */
-        dnskw_gpio_register(39, "dnskw:power:sata0", 1);
-        dnskw_gpio_register(40, "dnskw:power:sata1", 1);
        /* Set NAS to turn back on after a power failure */
        dnskw_gpio_register(37, "dnskw:power:recover", 1);
 }
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
index f2fbb023e679..d7196db33984 100644
--- a/arch/arm/mach-kirkwood/board-dockstar.c
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -16,46 +16,17 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data dockstar_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
-static unsigned int dockstar_mpp_config[] __initdata = {
-        MPP29_GPIO,     /* USB Power Enable */
-        MPP46_GPIO,     /* LED green */
-        MPP47_GPIO,     /* LED orange */
-        0
-};
 void __init dockstar_dt_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(dockstar_mpp_config);
-        if (gpio_request(29, "USB Power Enable") != 0 ||
-            gpio_direction_output(29, 1) != 0)
-                pr_err("can't setup GPIO 29 (USB Power Enable)\n");
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&dockstar_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 20af53a56c0e..08248e24ffcd 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -13,26 +13,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
 #include <linux/gpio.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
 #include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
@@ -46,25 +30,11 @@ static struct mvsdio_platform_data dreamplug_mvsdio_data = {
        /* unfortunately the CD signal has not been connected */
 };
-static unsigned int dreamplug_mpp_config[] __initdata = {
-        MPP0_SPI_SCn,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP47_GPIO,     /* Bluetooth LED */
-        MPP48_GPIO,     /* Wifi LED */
-        MPP49_GPIO,     /* Wifi AP LED */
-        0
-};
 void __init dreamplug_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(dreamplug_mpp_config);
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&dreamplug_ge00_data);
        kirkwood_ge01_init(&dreamplug_ge01_data);
        kirkwood_sdio_init(&dreamplug_mvsdio_data);
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 9826904277b8..ff4150a2ad05 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -128,10 +128,29 @@ static void __init kirkwood_dt_init(void)
        if (of_machine_is_compatible("keymile,km_kirkwood"))
                km_kirkwood_init();
+        if (of_machine_is_compatible("lacie,inetspace_v2") ||
+            of_machine_is_compatible("lacie,netspace_v2") ||
+            of_machine_is_compatible("lacie,netspace_max_v2") ||
+            of_machine_is_compatible("lacie,netspace_lite_v2") ||
+            of_machine_is_compatible("lacie,netspace_mini_v2"))
+                ns2_init();
+        if (of_machine_is_compatible("mpl,cec4"))
+                mplcec4_init();
+        if (of_machine_is_compatible("plathome,openblocks-a6"))
+                openblocks_a6_init();
+        if (of_machine_is_compatible("usi,topkick"))
+                usi_topkick_init();
+        if (of_machine_is_compatible("zyxel,nsa310"))
+                nsa310_init();
        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
-static const char *kirkwood_dt_board_compat[] = {
+static const char * const kirkwood_dt_board_compat[] = {
        "globalscale,dreamplug",
        "dlink,dns-320",
        "dlink,dns-325",
@@ -143,6 +162,15 @@ static const char *kirkwood_dt_board_compat[] = {
        "buffalo,lsxl",
        "iom,ix2-200",
        "keymile,km_kirkwood",
+        "lacie,inetspace_v2",
+        "lacie,netspace_max_v2",
+        "lacie,netspace_v2",
+        "lacie,netspace_lite_v2",
+        "lacie,netspace_mini_v2",
+        "mpl,cec4",
+        "plathome,openblocks-a6",
+        "usi,topkick",
+        "zyxel,nsa310",
        NULL
 };
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 001ca8c96980..9db979aec82e 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -18,54 +18,17 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
-static unsigned int goflexnet_mpp_config[] __initdata = {
-        MPP29_GPIO,     /* USB Power Enable */
-        MPP47_GPIO,     /* LED Orange */
-        MPP46_GPIO,     /* LED Green */
-        MPP45_GPIO,     /* LED Left Capacity 3 */
-        MPP44_GPIO,     /* LED Left Capacity 2 */
-        MPP43_GPIO,     /* LED Left Capacity 1 */
-        MPP42_GPIO,     /* LED Left Capacity 0 */
-        MPP41_GPIO,     /* LED Right Capacity 3 */
-        MPP40_GPIO,     /* LED Right Capacity 2 */
-        MPP39_GPIO,     /* LED Right Capacity 1 */
-        MPP38_GPIO,     /* LED Right Capacity 0 */
-        0
-};
 void __init goflexnet_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(goflexnet_mpp_config);
-        if (gpio_request(29, "USB Power Enable") != 0 ||
-            gpio_direction_output(29, 1) != 0)
-                pr_err("can't setup GPIO 29 (USB Power Enable)\n");
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&goflexnet_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index cfc47f80e734..9f6f496380d8 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -13,59 +13,18 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
 #include <linux/input.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
 #include "common.h"
-#include "mpp.h"
-#define IB62X0_GPIO_POWER_OFF   24
 static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
-static unsigned int ib62x0_mpp_config[] __initdata = {
-        MPP0_NF_IO2,
-        MPP1_NF_IO3,
-        MPP2_NF_IO4,
-        MPP3_NF_IO5,
-        MPP4_NF_IO6,
-        MPP5_NF_IO7,
-        MPP18_NF_IO0,
-        MPP19_NF_IO1,
-        MPP22_GPIO,     /* OS LED red */
-        MPP24_GPIO,     /* Power off device */
-        MPP25_GPIO,     /* OS LED green */
-        MPP27_GPIO,     /* USB transfer LED */
-        MPP28_GPIO,     /* Reset button */
-        MPP29_GPIO,     /* USB Copy button */
-        0
-};
-static void ib62x0_power_off(void)
-{
-        gpio_set_value(IB62X0_GPIO_POWER_OFF, 1);
-}
 void __init ib62x0_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(ib62x0_mpp_config);
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&ib62x0_ge00_data);
-        if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
-            gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
-                pm_power_off = ib62x0_power_off;
-        else
-                pr_err("board-ib62x0: failed to configure power-off GPIO\n");
 }
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d084b1e2943a..c8ebde4919e2 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -10,42 +10,16 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
 #include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data iconnect_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
 };
-static unsigned int iconnect_mpp_config[] __initdata = {
-        MPP12_GPIO,
-        MPP35_GPIO,
-        MPP41_GPIO,
-        MPP42_GPIO,
-        MPP43_GPIO,
-        MPP44_GPIO,
-        MPP45_GPIO,
-        MPP46_GPIO,
-        MPP47_GPIO,
-        MPP48_GPIO,
-        0
-};
 void __init iconnect_init(void)
 {
-        kirkwood_mpp_conf(iconnect_mpp_config);
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&iconnect_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
index 158fb97d0397..f655b2637b0e 100644
--- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -10,12 +10,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
-#include <mach/kirkwood.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_NONE,
@@ -23,35 +20,10 @@ static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
        .duplex         = DUPLEX_FULL,
 };
-static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
-        MPP12_GPIO,                     /* Reset Button */
-        MPP14_GPIO,                     /* Power Button */
-        MPP15_GPIO,                     /* Backup LED (blue) */
-        MPP16_GPIO,                     /* Power LED (white) */
-        MPP35_GPIO,                     /* OTB Button */
-        MPP36_GPIO,                     /* Rebuild LED (white) */
-        MPP37_GPIO,                     /* Health LED (red) */
-        MPP38_GPIO,                     /* SATA LED brightness control 1 */
-        MPP39_GPIO,                     /* SATA LED brightness control 2 */
-        MPP40_GPIO,                     /* Backup LED brightness control 1 */
-        MPP41_GPIO,                     /* Backup LED brightness control 2 */
-        MPP42_GPIO,                     /* Power LED brightness control 1 */
-        MPP43_GPIO,                     /* Power LED brightness control 2 */
-        MPP44_GPIO,                     /* Health LED brightness control 1 */
-        MPP45_GPIO,                     /* Health LED brightness control 2 */
-        MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
-        MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
-        0
-};
 void __init iomega_ix2_200_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
-        kirkwood_ehci_init();
        kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
index f7d32834b757..44e4605ba0bf 100644
--- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -18,27 +18,15 @@
 #include <linux/clk.h>
 #include <linux/clk-private.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
-static unsigned int km_kirkwood_mpp_config[] __initdata = {
-        MPP8_GPIO,      /* I2C SDA */
-        MPP9_GPIO,      /* I2C SCL */
-        0
-};
 void __init km_kirkwood_init(void)
 {
        struct clk *sata_clk;
        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_mpp_conf(km_kirkwood_mpp_config);
-        /*
         * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
         * SATA bits (14-15) of the Clock Gating Control Register. Since these
         * devices are also not present in this variant, their clocks get
@@ -52,6 +40,5 @@ void __init km_kirkwood_init(void)
        if (!IS_ERR(sata_clk))
                sata_clk->flags |= CLK_IGNORE_UNUSED;
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&km_kirkwood_ge00_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 83d8975592f8..4ec8b7ae784a 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -14,19 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/gpio.h>
-#include <linux/gpio-fan.h>
-#include <linux/input.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
 #include "common.h"
-#include "mpp.h"
 static struct mv643xx_eth_platform_data lsxl_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
@@ -36,68 +25,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
-static unsigned int lsxl_mpp_config[] __initdata = {
-        MPP10_GPO,      /* HDD Power Enable */
-        MPP11_GPIO,     /* USB Vbus Enable */
-        MPP18_GPO,      /* FAN High Enable# */
-        MPP19_GPO,      /* FAN Low Enable# */
-        MPP36_GPIO,     /* Function Blue LED */
-        MPP37_GPIO,     /* Alarm LED */
-        MPP38_GPIO,     /* Info LED */
-        MPP39_GPIO,     /* Power LED */
-        MPP40_GPIO,     /* Fan Lock */
-        MPP41_GPIO,     /* Function Button */
-        MPP42_GPIO,     /* Power Switch */
-        MPP43_GPIO,     /* Power Auto Switch */
-        MPP48_GPIO,     /* Function Red LED */
-        0
-};
-#define LSXL_GPIO_FAN_HIGH      18
-#define LSXL_GPIO_FAN_LOW       19
-#define LSXL_GPIO_FAN_LOCK      40
-static struct gpio_fan_alarm lsxl_alarm = {
-        .gpio = LSXL_GPIO_FAN_LOCK,
-};
-static struct gpio_fan_speed lsxl_speeds[] = {
-        {
-                .rpm = 0,
-                .ctrl_val = 3,
-        }, {
-                .rpm = 1500,
-                .ctrl_val = 1,
-        }, {
-                .rpm = 3250,
-                .ctrl_val = 2,
-        }, {
-                .rpm = 5000,
-                .ctrl_val = 0,
-        }
-};
-static int lsxl_gpio_list[] = {
-        LSXL_GPIO_FAN_HIGH, LSXL_GPIO_FAN_LOW,
-};
-static struct gpio_fan_platform_data lsxl_fan_data = {
-        .num_ctrl = ARRAY_SIZE(lsxl_gpio_list),
-        .ctrl = lsxl_gpio_list,
-        .alarm = &lsxl_alarm,
-        .num_speed = ARRAY_SIZE(lsxl_speeds),
-        .speed = lsxl_speeds,
-};
-static struct platform_device lsxl_fan_device = {
-        .name = "gpio-fan",
-        .id = -1,
-        .num_resources = 0,
-        .dev = {
-                .platform_data = &lsxl_fan_data,
-        },
-};
 /*
 * On the LS-XHL/LS-CHLv2, the shutdown process is following:
 * - Userland monitors key events until the power switch goes to off position
@@ -111,24 +38,14 @@ static void lsxl_power_off(void)
        kirkwood_restart('h', NULL);
 }
-#define LSXL_GPIO_HDD_POWER 10
-#define LSXL_GPIO_USB_POWER 11
 void __init lsxl_init(void)
 {
        /*
         * Basic setup. Needs to be called early.
         */
-        kirkwood_mpp_conf(lsxl_mpp_config);
-        /* usb and sata power on */
-        gpio_set_value(LSXL_GPIO_USB_POWER, 1);
-        gpio_set_value(LSXL_GPIO_HDD_POWER, 1);
-        kirkwood_ehci_init();
        kirkwood_ge00_init(&lsxl_ge00_data);
        kirkwood_ge01_init(&lsxl_ge01_data);
-        platform_device_register(&lsxl_fan_device);
        /* register power-off method */
        pm_power_off = lsxl_power_off;
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
new file mode 100644
index 000000000000..56bfe5a1605a
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012 MPL AG, Switzerland
+ * Stefan Peter <s.peter@mpl.ch>
+ *
+ * arch/arm/mach-kirkwood/board-mplcec4.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data mplcec4_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
+};
+static struct mv643xx_eth_platform_data mplcec4_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(2),
+};
+static struct mvsdio_platform_data mplcec4_mvsdio_data = {
+        .gpio_card_detect = 47, /* MPP47 used as SD card detect */
+};
+void __init mplcec4_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_ge00_init(&mplcec4_ge00_data);
+        kirkwood_ge01_init(&mplcec4_ge01_data);
+        kirkwood_sdio_init(&mplcec4_mvsdio_data);
+        kirkwood_pcie_init(KW_PCIE0);
+}
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
new file mode 100644
index 000000000000..8821720ab5a4
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-ns2.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2012 (C), Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * arch/arm/mach-kirkwood/board-ns2.c
+ *
+ * LaCie Network Space v2 board (and parents) initialization for drivers
+ * not converted to flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/of.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data ns2_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+static unsigned int ns2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP6_SYSRST_OUTn,
+        MPP7_GPO,               /* Fan speed (bit 1) */
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_GPO,              /* Red led */
+        MPP14_GPIO,             /* USB fuse */
+        MPP16_GPIO,             /* SATA 0 power */
+        MPP17_GPIO,             /* SATA 1 power */
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
+        MPP20_SATA1_ACTn,
+        MPP21_SATA0_ACTn,
+        MPP22_GPIO,             /* Fan speed (bit 0) */
+        MPP23_GPIO,             /* Fan power */
+        MPP24_GPIO,             /* USB mode select */
+        MPP25_GPIO,             /* Fan rotation fail */
+        MPP26_GPIO,             /* USB device vbus */
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* Blue led (slow register) */
+        MPP30_GPIO,             /* Blue led (command register) */
+        MPP31_GPIO,             /* Board power off */
+        MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
+        MPP33_GPO,              /* Fan speed (bit 2) */
+        0
+};
+#define NS2_GPIO_POWER_OFF      31
+static void ns2_power_off(void)
+{
+        gpio_set_value(NS2_GPIO_POWER_OFF, 1);
+}
+void __init ns2_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(ns2_mpp_config);
+        if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
+            of_machine_is_compatible("lacie,netspace_mini_v2"))
+                ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+        kirkwood_ge00_init(&ns2_ge00_data);
+        if (gpio_request(NS2_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(NS2_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = ns2_power_off;
+        else
+                pr_err("ns2: failed to configure power-off GPIO\n");
+}
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
new file mode 100644
index 000000000000..f58d2e1a4042
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-nsa310.c
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mach-kirkwood/nsa-310-setup.c
+ *
+ * ZyXEL NSA-310 Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+#define NSA310_GPIO_USB_POWER_OFF       21
+#define NSA310_GPIO_POWER_OFF           48
+static unsigned int nsa310_mpp_config[] __initdata = {
+        MPP12_GPIO, /* led esata green */
+        MPP13_GPIO, /* led esata red */
+        MPP15_GPIO, /* led usb green */
+        MPP16_GPIO, /* led usb red */
+        MPP21_GPIO, /* control usb power off */
+        MPP28_GPIO, /* led sys green */
+        MPP29_GPIO, /* led sys red */
+        MPP36_GPIO, /* key reset */
+        MPP37_GPIO, /* key copy */
+        MPP39_GPIO, /* led copy green */
+        MPP40_GPIO, /* led copy red */
+        MPP41_GPIO, /* led hdd green */
+        MPP42_GPIO, /* led hdd red */
+        MPP44_GPIO, /* ?? */
+        MPP46_GPIO, /* key power */
+        MPP48_GPIO, /* control power off */
+        0
+};
+static struct i2c_board_info __initdata nsa310_i2c_info[] = {
+        { I2C_BOARD_INFO("adt7476", 0x2e) },
+};
+static void nsa310_power_off(void)
+{
+        gpio_set_value(NSA310_GPIO_POWER_OFF, 1);
+}
+static int __init nsa310_gpio_request(unsigned int gpio, unsigned long flags,
+                                       const char *label)
+{
+        int err;
+        err = gpio_request_one(gpio, flags, label);
+        if (err)
+                pr_err("NSA-310: can't setup GPIO%u (%s), err=%d\n",
+                        gpio, label, err);
+        return err;
+}
+static void __init nsa310_gpio_init(void)
+{
+        int err;
+        err = nsa310_gpio_request(NSA310_GPIO_POWER_OFF, GPIOF_OUT_INIT_LOW,
+                                  "Power Off");
+        if (!err)
+                pm_power_off = nsa310_power_off;
+        nsa310_gpio_request(NSA310_GPIO_USB_POWER_OFF, GPIOF_OUT_INIT_LOW,
+                            "USB Power Off");
+}
+void __init nsa310_init(void)
+{
+        u32 dev, rev;
+        kirkwood_mpp_conf(nsa310_mpp_config);
+        nsa310_gpio_init();
+        kirkwood_pcie_id(&dev, &rev);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(nsa310_i2c_info));
+}
+static int __init nsa310_pci_init(void)
+{
+        if (of_machine_is_compatible("zyxel,nsa310"))
+                kirkwood_pcie_init(KW_PCIE0);
+        return 0;
+}
+subsys_initcall(nsa310_pci_init);
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
new file mode 100644
index 000000000000..815fc6451d52
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-openblocks_a6.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2012 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * arch/arm/mach-kirkwood/board-openblocks_a6.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data openblocks_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+static unsigned int openblocks_a6_mpp_config[] __initdata = {
+        MPP0_NF_IO2,
+        MPP1_NF_IO3,
+        MPP2_NF_IO4,
+        MPP3_NF_IO5,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP6_SYSRST_OUTn,
+        MPP8_UART1_RTS,
+        MPP9_UART1_CTS,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP13_UART1_TXD,
+        MPP14_UART1_RXD,
+        MPP15_UART0_RTS,
+        MPP16_UART0_CTS,
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
+        MPP20_GPIO, /* DIP SW0 */
+        MPP21_GPIO, /* DIP SW1 */
+        MPP22_GPIO, /* DIP SW2 */
+        MPP23_GPIO, /* DIP SW3 */
+        MPP24_GPIO, /* GPIO 0 */
+        MPP25_GPIO, /* GPIO 1 */
+        MPP26_GPIO, /* GPIO 2 */
+        MPP27_GPIO, /* GPIO 3 */
+        MPP28_GPIO, /* GPIO 4 */
+        MPP29_GPIO, /* GPIO 5 */
+        MPP30_GPIO, /* GPIO 6 */
+        MPP31_GPIO, /* GPIO 7 */
+        MPP36_TW1_SDA,
+        MPP37_TW1_SCK,
+        MPP38_GPIO, /* INIT */
+        MPP39_GPIO, /* USB OC */
+        MPP41_GPIO, /* LED: Red */
+        MPP42_GPIO, /* LED: Green */
+        MPP43_GPIO, /* LED: Yellow */
+        0,
+};
+void __init openblocks_a6_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(openblocks_a6_mpp_config);
+        kirkwood_ge00_init(&openblocks_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index 1750e68506c1..acb0187c7ee1 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -19,54 +19,25 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
-#include "mpp.h"
 #include "tsx1x-common.h"
 static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
-static unsigned int qnap_ts219_mpp_config[] __initdata = {
-        MPP0_SPI_SCn,
-        MPP1_SPI_MOSI,
-        MPP2_SPI_SCK,
-        MPP3_SPI_MISO,
-        MPP4_SATA1_ACTn,
-        MPP5_SATA0_ACTn,
-        MPP8_TW0_SDA,
-        MPP9_TW0_SCK,
-        MPP10_UART0_TXD,
-        MPP11_UART0_RXD,
-        MPP13_UART1_TXD,        /* PIC controller */
-        MPP14_UART1_RXD,        /* PIC controller */
-        MPP15_GPIO,             /* USB Copy button (on devices with 88F6281) */
-        MPP16_GPIO,             /* Reset button (on devices with 88F6281) */
-        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
-        MPP37_GPIO,             /* Reset button (on devices with 88F6282) */
-        MPP43_GPIO,             /* USB Copy button (on devices with 88F6282) */
-        MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
-        0
-};
 void __init qnap_dt_ts219_init(void)
 {
        u32 dev, rev;
-        kirkwood_mpp_conf(qnap_ts219_mpp_config);
        kirkwood_pcie_id(&dev, &rev);
        if (dev == MV88F6282_DEV_ID)
                qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
        kirkwood_ge00_init(&qnap_ts219_ge00_data);
-        kirkwood_ehci_init();
        pm_power_off = qnap_tsx1x_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
new file mode 100644
index 000000000000..15e69fcde9f4
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-usi_topkick.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-usi_topkick.c
+ *
+ * USI Topkick Init for drivers not converted to flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data topkick_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+static struct mvsdio_platform_data topkick_mvsdio_data = {
+        /* unfortunately the CD signal has not been connected */
+};
+/*
+ * GPIO LED layout
+ *
+ *       /-SYS_LED(2)
+ *       |
+ *       |   /-DISK_LED
+ *       |   |
+ *       |   |   /-WLAN_LED(2)
+ *       |   |   |
+ * [SW] [*] [*] [*]
+ */
+/*
+ * Switch positions
+ *
+ *     /-SW_LEFT
+ *     |
+ *     |   /-SW_IDLE
+ *     |   |
+ *     |   |   /-SW_RIGHT
+ *     |   |   |
+ * PS [L] [I] [R] LEDS
+ */
+static unsigned int topkick_mpp_config[] __initdata = {
+        MPP21_GPIO,     /* DISK_LED           (low active) - yellow */
+        MPP36_GPIO,     /* SATA0 power enable (high active) */
+        MPP37_GPIO,     /* SYS_LED2           (low active) - red */
+        MPP38_GPIO,     /* SYS_LED            (low active) - blue */
+        MPP39_GPIO,     /* WLAN_LED           (low active) - green */
+        MPP43_GPIO,     /* SW_LEFT            (low active) */
+        MPP44_GPIO,     /* SW_RIGHT           (low active) */
+        MPP45_GPIO,     /* SW_IDLE            (low active) */
+        MPP46_GPIO,     /* SW_LEFT            (low active) */
+        MPP48_GPIO,     /* WLAN_LED2          (low active) - yellow */
+        0
+};
+#define TOPKICK_SATA0_PWR_ENABLE 36
+void __init usi_topkick_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(topkick_mpp_config);
+        /* SATA0 power enable */
+        gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1);
+        kirkwood_ge00_init(&topkick_ge00_data);
+        kirkwood_sdio_init(&topkick_mvsdio_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 401dac1a8d80..bac21a554c91 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -18,10 +18,10 @@
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/timex.h>
+#include <linux/kexec.h>
 #include <net/dsa.h>
 #include <asm/page.h>
-#include <asm/timex.h>
-#include <asm/kexec.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
@@ -266,6 +266,7 @@ void __init kirkwood_clk_init(void)
        orion_clkdev_add("1", "pcie", pex1);
        orion_clkdev_add(NULL, "kirkwood-i2s", audio);
        orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit);
+        orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".1", runit);
        /* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
         * so should never be gated.
@@ -425,7 +426,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 /*****************************************************************************
 * SPI
 ****************************************************************************/
-void __init kirkwood_spi_init()
+void __init kirkwood_spi_init(void)
 {
        orion_spi_init(SPI_PHYS_BASE);
 }
@@ -646,8 +647,7 @@ void __init kirkwood_l2_init(void)
 void __init kirkwood_init(void)
 {
-        printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
+        pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
-                kirkwood_id(), kirkwood_tclk);
        /*
         * Disable propagation of mbus errors to the CPU local bus,
@@ -671,7 +671,7 @@ void __init kirkwood_init(void)
        kirkwood_xor1_init();
        kirkwood_crypto_init();
-#ifdef CONFIG_KEXEC 
+#ifdef CONFIG_KEXEC
        kexec_reinit = kirkwood_enable_pcie;
 #endif
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index bcffd7ca1ca2..5ffa57f08c80 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -47,7 +47,8 @@ void kirkwood_i2c_init(void);
 void kirkwood_uart0_init(void);
 void kirkwood_uart1_init(void);
 void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
-void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *));
+void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
+                            int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 void kirkwood_clk_init(void);
@@ -112,6 +113,40 @@ void km_kirkwood_init(void);
 static inline void km_kirkwood_init(void) {};
 #endif
+#ifdef CONFIG_MACH_MPLCEC4_DT
+void mplcec4_init(void);
+#else
+static inline void mplcec4_init(void) {};
+#endif
+#if defined(CONFIG_MACH_INETSPACE_V2_DT) || \
+        defined(CONFIG_MACH_NETSPACE_V2_DT) || \
+        defined(CONFIG_MACH_NETSPACE_MAX_V2_DT) || \
+        defined(CONFIG_MACH_NETSPACE_LITE_V2_DT) || \
+        defined(CONFIG_MACH_NETSPACE_MINI_V2_DT)
+void ns2_init(void);
+#else
+static inline void ns2_init(void) {};
+#endif
+#ifdef CONFIG_MACH_NSA310_DT
+void nsa310_init(void);
+#else
+static inline void nsa310_init(void) {};
+#endif
+#ifdef CONFIG_MACH_OPENBLOCKS_A6_DT
+void openblocks_a6_init(void);
+#else
+static inline void openblocks_a6_init(void) {};
+#endif
+#ifdef CONFIG_MACH_TOPKICK_DT
+void usi_topkick_init(void);
+#else
+static inline void usi_topkick_init(void) {};
+#endif
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/cpuidle.c b/arch/arm/mach-kirkwood/cpuidle.c
index 0f1710941878..f7304670f2f8 100644
--- a/arch/arm/mach-kirkwood/cpuidle.c
+++ b/arch/arm/mach-kirkwood/cpuidle.c
@@ -64,7 +64,7 @@ static int kirkwood_init_cpuidle(void)
        cpuidle_register_driver(&kirkwood_idle_driver);
        if (cpuidle_register_device(device)) {
-                printk(KERN_ERR "kirkwood_init_cpuidle: Failed registering\n");
+                pr_err("kirkwood_init_cpuidle: Failed registering\n");
                return -EIO;
        }
        return 0;
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 23dcb19cc2a7..791a98fafa29 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -93,7 +93,7 @@ static void __init dockstar_init(void)
        if (gpio_request(29, "USB Power Enable") != 0 ||
            gpio_direction_output(29, 1) != 0)
-                printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
+                pr_err("can't set up GPIO 29 (USB Power Enable)\n");
        kirkwood_ehci_init();
        kirkwood_ge00_init(&dockstar_ge00_data);
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 884703535a0a..2a97a2e4163c 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -14,6 +14,7 @@
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
+#include "common.h"
 static int __initdata gpio0_irqs[4] = {
        IRQ_KIRKWOOD_GPIO_LOW_0_7,
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c
index 285edab776e9..489495976fcd 100644
--- a/arch/arm/mach-kirkwood/lacie_v2-common.c
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.c
@@ -19,6 +19,7 @@
 #include <mach/irqs.h>
 #include <plat/time.h>
 #include "common.h"
+#include "lacie_v2-common.h"
 /*****************************************************************************
 * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 0c6ad63f10c7..827cde42414f 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -30,8 +30,8 @@ static unsigned int __init kirkwood_variant(void)
        if (dev == MV88F6180_DEV_ID)
                return MPP_F6180_MASK;
-        printk(KERN_ERR "MPP setup: unknown kirkwood variant "
+        pr_err("MPP setup: unknown kirkwood variant (dev %#x rev %#x)\n",
-                        "(dev %#x rev %#x)\n", dev, rev);
+               dev, rev);
        return 0;
 }
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 88b0788bacae..728e86d33f0c 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -79,7 +79,7 @@ static struct platform_device netspace_v2_gpio_buttons = {
        .name           = "gpio-keys",
        .id             = -1,
        .dev            = {
-                .platform_data  = &netspace_v2_button_data,
+                .platform_data  = &netspace_v2_button_data,
        },
 };
@@ -211,7 +211,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
        MPP29_GPIO,             /* Blue led (slow register) */
        MPP30_GPIO,             /* Blue led (command register) */
        MPP31_GPIO,             /* Board power off */
-        MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
+        MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
        MPP33_GPO,              /* Fan speed (bit 2) */
        0
 };
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 134ef50d58fc..7e81e9b586bf 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -121,14 +121,12 @@ static int __init uart1_mpp_config(void)
        kirkwood_mpp_conf(openrd_uart1_mpp_config);
        if (gpio_request(34, "SD_UART1_SEL")) {
-                printk(KERN_ERR "GPIO request failed for SD/UART1 selection"
+                pr_err("GPIO request 34 failed for SD/UART1 selection\n");
-                                ", gpio: 34\n");
                return -EIO;
        }
        if (gpio_request(28, "RS232_RS485_SEL")) {
-                printk(KERN_ERR "GPIO request failed for RS232/RS485 selection"
+                pr_err("GPIO request 28 failed for RS232/RS485 selection\n");
-                                ", gpio# 28\n");
                gpio_free(34);
                return -EIO;
        }
@@ -185,15 +183,13 @@ static void __init openrd_init(void)
        if (uart1 <= 0) {
                if (uart1 < 0)
-                        printk(KERN_ERR "Invalid kernel parameter to select "
+                        pr_err("Invalid kernel parameter to select UART1. Defaulting to SD. ERROR CODE: %d\n",
-                                "UART1. Defaulting to SD. ERROR CODE: %d\n",
+                               uart1);
-                                uart1);
                /* Select SD
                 * Pin # 34: 0 => UART1, 1 => SD */
                if (gpio_request(34, "SD_UART1_SEL")) {
-                        printk(KERN_ERR "GPIO request failed for SD/UART1 "
+                        pr_err("GPIO request 34 failed for SD/UART1 selection\n");
-                                        "selection, gpio: 34\n");
                } else {
                        gpio_direction_output(34, 1);
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index ec544918b12c..ef102646ba9a 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -26,7 +26,7 @@ static void kirkwood_enable_pcie_clk(const char *port)
        clk = clk_get_sys("pcie", port);
        if (IS_ERR(clk)) {
-                printk(KERN_ERR "PCIE clock %s missing\n", port);
+                pr_err("PCIE clock %s missing\n", port);
                return;
        }
        clk_prepare_enable(clk);
@@ -168,7 +168,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
                return 0;
        index = pcie_port_map[nr];
-        printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+        pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
        pp = kzalloc(sizeof(*pp), GFP_KERNEL);
        if (!pp)
@@ -186,7 +186,8 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
        case 1:
                kirkwood_enable_pcie_clk("1");
                pcie1_ioresources_init(pp);
-                pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
+                pci_ioremap_io(SZ_64K * sys->busnr,
+                               KIRKWOOD_PCIE1_IO_PHYS_BASE);
                break;
        default:
                panic("PCIe setup: invalid controller %d", index);
@@ -207,14 +208,19 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
        return 1;
 }
+/*
+ * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
+ * is operating as a root complex this needs to be switched to
+ * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
+ * the device. Decoding setup is handled by the orion code.
+ */
 static void __devinit rc_pci_fixup(struct pci_dev *dev)
 {
-        /*
-         * Prevent enumeration of root complex.
-         */
        if (dev->bus->parent == NULL && dev->devfn == 0) {
                int i;
+                dev->class &= 0xff;
+                dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
                        dev->resource[i].start = 0;
                        dev->resource[i].end   = 0;
@@ -224,22 +230,6 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
-static struct pci_bus __init *
-kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        struct pci_bus *bus;
-        if (nr < num_pcie_ports) {
-                bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
-                                        &sys->resources);
-        } else {
-                bus = NULL;
-                BUG();
-        }
-        return bus;
-}
 static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
        u8 pin)
 {
@@ -251,19 +241,19 @@ static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci kirkwood_pci __initdata = {
        .setup          = kirkwood_pcie_setup,
-        .scan           = kirkwood_pcie_scan_bus,
        .map_irq        = kirkwood_pcie_map_irq,
+        .ops            = &pcie_ops,
 };
 static void __init add_pcie_port(int index, void __iomem *base)
 {
-        printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+        pr_info("Kirkwood PCIe port %d: ", index);
        if (orion_pcie_link_up(base)) {
-                printk(KERN_INFO "link up\n");
+                pr_info("link up\n");
                pcie_port_map[num_pcie_ports++] = index;
        } else
-                printk(KERN_INFO "link down, ignoring\n");
+                pr_info("link down, ignoring\n");
 }
 void __init kirkwood_pcie_init(unsigned int portmask)
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 28d0abaf4bd9..8a175948b28d 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -117,7 +117,7 @@ static void __init sheevaplug_init(void)
        if (gpio_request(29, "USB Power Enable") != 0 ||
            gpio_direction_output(29, 1) != 0)
-                printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
+                pr_err("can't set up GPIO 29 (USB Power Enable)\n");
        kirkwood_ehci_init();
        kirkwood_ge00_init(&sheevaplug_ge00_data);
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index bad738e44044..f2daf711e72e 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -29,7 +29,7 @@
 #include "common.h"
 #include "mpp.h"
-struct mtd_partition hp_t5325_partitions[] = {
+static struct mtd_partition hp_t5325_partitions[] = {
        {
                .name           = "u-boot env",
                .size           = SZ_64K,
@@ -59,14 +59,14 @@ struct mtd_partition hp_t5325_partitions[] = {
        },
 };
-const struct flash_platform_data hp_t5325_flash = {
+static const struct flash_platform_data hp_t5325_flash = {
        .type           = "mx25l8005",
        .name           = "spi_flash",
        .parts          = hp_t5325_partitions,
        .nr_parts       = ARRAY_SIZE(hp_t5325_partitions),
 };
-struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
+static struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
        {
                .modalias       = "m25p80",
                .platform_data  = &hp_t5325_flash,
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 367a9400f532..e4c61279ea86 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -170,8 +170,7 @@ static int __init ts41x_pci_init(void)
                else
                        kirkwood_pcie_init(KW_PCIE0);
        }
+        return 0;
-   return 0;
 }
 subsys_initcall(ts41x_pci_init);
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
index 8943ede29b44..cec87cef76ca 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.c
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -7,6 +7,7 @@
 #include <linux/serial_reg.h>
 #include <mach/kirkwood.h>
 #include "common.h"
+#include "tsx1x-common.h"
 /*
 * QNAP TS-x1x Boards flash
@@ -29,7 +30,7 @@
 *
 ***************************************************************************/
-struct mtd_partition qnap_tsx1x_partitions[] = {
+static struct mtd_partition qnap_tsx1x_partitions[] = {
        {
                .name           = "U-Boot",
                .size           = 0x00080000,
@@ -58,14 +59,14 @@ struct mtd_partition qnap_tsx1x_partitions[] = {
        },
 };
-const struct flash_platform_data qnap_tsx1x_flash = {
+static const struct flash_platform_data qnap_tsx1x_flash = {
        .type           = "m25p128",
        .name           = "spi_flash",
        .parts          = qnap_tsx1x_partitions,
        .nr_parts       = ARRAY_SIZE(qnap_tsx1x_partitions),
 };
-struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
+static struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
        {
                .modalias       = "m25p80",
                .platform_data  = &qnap_tsx1x_flash,
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index f48c2e961b84..dd5d6f532e8c 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
        .get_rate       = local_return_parent_rate,
 };
+static struct clk clk_mpwm = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
+        .get_rate       = local_return_parent_rate,
+};
 static struct clk clk_wdt = {
        .parent         = &clk_pclk,
        .enable         = local_onoff_enable,
@@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
        CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
        CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
+        CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
        CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
        CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
        CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index acc4aabf1c7b..b5612a1d1839 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -515,6 +515,7 @@
 /*
 * clkpwr_timers_pwms_clk_ctrl_1 register definitions
 */
+#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN        0x40
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN      0x20
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN      0x10
 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN      0x08
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 3c6332753358..9ecb8f9c4ef5 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -412,7 +412,6 @@ static const struct of_device_id mic_of_match[] __initconst = {
 void __init lpc32xx_init_irq(void)
 {
        unsigned int i;
-        int irq_base;
        /* Setup MIC */
        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
@@ -443,15 +442,6 @@ void __init lpc32xx_init_irq(void)
        lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
        lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
-        /* mask all interrupts except SUBIRQ */
-        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
-        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
-        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
-        /* MIC SUBIRQx interrupts will route handling to the chain handlers */
-        irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
-        irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
        /* Initially disable all wake events */
        __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
        __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
@@ -475,16 +465,13 @@ void __init lpc32xx_init_irq(void)
        of_irq_init(mic_of_match);
-        irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0);
-        if (irq_base < 0) {
-                pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n");
-                irq_base = 0;
-        }
        lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS,
-                                                   irq_base, 0,
+                                                   0, 0, &irq_domain_simple_ops,
-                                                   &irq_domain_simple_ops,
                                                   NULL);
        if (!lpc32xx_mic_domain)
                panic("Unable to add MIC irq domain\n");
+        /* MIC SUBIRQx interrupts will route handling to the chain handlers */
+        irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
+        irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
 }
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 178d4daa5e1d..ebdda8346a26 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -89,6 +89,8 @@ config MACH_MMP_DT
        select CPU_PXA168
        select CPU_PXA910
        select USE_OF
+        select PINCTRL
+        select PINCTRL_SINGLE
        help
          Include support for Marvell MMP2 based platforms using
          the device tree. Needn't select any other machine while
@@ -99,6 +101,8 @@ config MACH_MMP2_DT
        depends on !CPU_MOHAWK
        select CPU_MMP2
        select USE_OF
+        select PINCTRL
+        select PINCTRL_SINGLE
        help
          Include support for Marvell MMP2 based platforms using
          the device tree.
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 4748ec551a68..98070370d602 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -100,6 +100,25 @@ static struct fb_videomode apx4devkit_video_modes[] = {
        },
 };
+static struct fb_videomode apf28dev_video_modes[] = {
+        {
+                .name = "LW700",
+                .refresh = 60,
+                .xres = 800,
+                .yres = 480,
+                .pixclock = 30303, /* picosecond */
+                .left_margin = 96,
+                .right_margin = 96, /* at least 3 & 1 */
+                .upper_margin = 0x14,
+                .lower_margin = 0x15,
+                .hsync_len = 64,
+                .vsync_len = 4,
+                .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+                                FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
 static struct mxsfb_platform_data mxsfb_pdata __initdata;
 /*
@@ -160,6 +179,7 @@ static struct sys_timer imx28_timer = {
 enum mac_oui {
        OUI_FSL,
        OUI_DENX,
+        OUI_CRYSTALFONTZ,
 };
 static void __init update_fec_mac_prop(enum mac_oui oui)
@@ -175,8 +195,12 @@ static void __init update_fec_mac_prop(enum mac_oui oui)
                np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
                if (!np)
                        return;
                from = np;
+                if (of_get_property(np, "local-mac-address", NULL))
+                        continue;
                newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
                if (!newmac)
                        return;
@@ -205,6 +229,11 @@ static void __init update_fec_mac_prop(enum mac_oui oui)
                        macaddr[1] = 0xe5;
                        macaddr[2] = 0x4e;
                        break;
+                case OUI_CRYSTALFONTZ:
+                        macaddr[0] = 0x58;
+                        macaddr[1] = 0xb9;
+                        macaddr[2] = 0xe1;
+                        break;
                }
                val = ocotp[i];
                macaddr[3] = (val >> 16) & 0xff;
@@ -261,6 +290,11 @@ static void __init m28evk_init(void)
        mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
 }
+static void __init sc_sps1_init(void)
+{
+        enable_clk_enet_out();
+}
 static int apx4devkit_phy_fixup(struct phy_device *phy)
 {
        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
@@ -355,6 +389,22 @@ static void __init tx28_post_init(void)
        pinctrl_put(pctl);
 }
+static void __init cfa10049_init(void)
+{
+        enable_clk_enet_out();
+        update_fec_mac_prop(OUI_CRYSTALFONTZ);
+}
+static void __init apf28_init(void)
+{
+        enable_clk_enet_out();
+        mxsfb_pdata.mode_list = apf28dev_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
+        mxsfb_pdata.default_bpp = 16;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
+}
 static void __init mxs_machine_init(void)
 {
        if (of_machine_is_compatible("fsl,imx28-evk"))
@@ -365,6 +415,12 @@ static void __init mxs_machine_init(void)
                m28evk_init();
        else if (of_machine_is_compatible("bluegiga,apx4devkit"))
                apx4devkit_init();
+        else if (of_machine_is_compatible("crystalfontz,cfa10049"))
+                cfa10049_init();
+        else if (of_machine_is_compatible("armadeus,imx28-apf28"))
+                apf28_init();
+        else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
+                sc_sps1_init();
        of_platform_populate(NULL, of_default_bus_match_table,
                             mxs_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 7c3792613392..856f4c796061 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -29,6 +29,7 @@
 #include <linux/of_irq.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <mach/mxs.h>
 #include <mach/common.h>
@@ -233,15 +234,22 @@ static struct clocksource clocksource_mxs = {
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
+static u32 notrace mxs_read_sched_clock_v2(void)
+{
+        return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
+}
 static int __init mxs_clocksource_init(struct clk *timer_clk)
 {
        unsigned int c = clk_get_rate(timer_clk);
        if (timrot_is_v1())
                clocksource_register_hz(&clocksource_mxs, c);
-        else
+        else {
                clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
                        "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
+                setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
+        }
        return 0;
 }
diff --git a/arch/arm/mach-netx/xc.c b/arch/arm/mach-netx/xc.c
index e4cfb7e5361d..f1c972d87bac 100644
--- a/arch/arm/mach-netx/xc.c
+++ b/arch/arm/mach-netx/xc.c
@@ -136,7 +136,7 @@ int xc_request_firmware(struct xc *x)
        if (head->magic != 0x4e657458) {
                if (head->magic == 0x5874654e) {
                        dev_err(x->dev,
-                            "firmware magic is 'XteN'. Endianess problems?\n");
+                            "firmware magic is 'XteN'. Endianness problems?\n");
                        ret = -ENODEV;
                        goto exit_release_firmware;
                }
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index c744946ef022..706dc5727bbe 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -4,7 +4,7 @@ menu "Nomadik boards"
 config MACH_NOMADIK_8815NHK
        bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
-        select HAS_MTU
+        select CLKSRC_NOMADIK_MTU
        select NOMADIK_8815
 endmenu
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index bfa1eab91f41..5ccdf53c5a9d 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -24,20 +24,17 @@
 #include <linux/i2c.h>
 #include <linux/io.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
+#include <linux/platform_data/clocksource-nomadik-mtu.h>
+#include <linux/platform_data/mtd-nomadik-nand.h>
 #include <asm/hardware/vic.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/time.h>
-#include <plat/gpio-nomadik.h>
-#include <plat/mtu.h>
-#include <plat/pincfg.h>
-#include <linux/platform_data/mtd-nomadik-nand.h>
 #include <mach/fsmc.h>
+#include <mach/irqs.h>
 #include "cpu-8815.h"
@@ -261,7 +258,7 @@ static void __init nomadik_timer_init(void)
        src_cr |= SRC_CR_INIT_VAL;
        writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
-        nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE));
+        nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE), IRQ_MTU0);
 }
 static struct sys_timer nomadik_timer = {
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index b617eaed0ce5..1273931303fb 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -26,8 +26,8 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-nomadik.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
-#include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-nomadik/i2c-8815nhk.c b/arch/arm/mach-nomadik/i2c-8815nhk.c
index 6d14454d4609..0c2f6628299a 100644
--- a/arch/arm/mach-nomadik/i2c-8815nhk.c
+++ b/arch/arm/mach-nomadik/i2c-8815nhk.c
@@ -4,8 +4,7 @@
 #include <linux/i2c-algo-bit.h>
 #include <linux/i2c-gpio.h>
 #include <linux/platform_device.h>
-#include <plat/gpio-nomadik.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
-#include <plat/pincfg.h>
 /*
 * There are two busses in the 8815NHK.
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
index a118e615f865..b549d0571548 100644
--- a/arch/arm/mach-nomadik/include/mach/irqs.h
+++ b/arch/arm/mach-nomadik/include/mach/irqs.h
@@ -72,7 +72,7 @@
 #define NOMADIK_NR_GPIO                 128 /* last 4 not wired to pins */
 #define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_GPIO_OFFSET)
 #define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_GPIO_OFFSET)
-#define NR_IRQS                         NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define NOMADIK_NR_IRQS                 NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
 /* Following two are used by entry_macro.S, to access our dual-vic */
 #define VIC_REG_IRQSR0          0
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index cd169c386161..f0e69cbc5baa 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,8 @@
 #
 # Common support
-obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
+obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \
+         serial.o devices.o dma.o
 obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index e255164ff087..a8fce3ccc707 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -625,7 +625,6 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
        .atag_offset    = 0x100,
        .map_io         = ams_delta_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = ams_delta_init,
        .init_late      = ams_delta_init_late,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 4b6de70c47a6..560a7dcf0a56 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -27,16 +27,16 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/mux.h>
 #include <mach/flash.h>
-#include <plat/fpga.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/hardware.h>
 #include "iomap.h"
 #include "common.h"
+#include "fpga.h"
 /* fsample is pretty close to p2-sample */
@@ -123,9 +123,9 @@ static struct resource smc91x_resources[] = {
 static void __init fsample_init_smc91x(void)
 {
-        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+        __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
        mdelay(50);
-        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+        __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
                   H2P2_DBG_FPGA_LAN_RESET);
        mdelay(50);
 }
@@ -307,8 +307,7 @@ static void __init omap_fsample_init(void)
        fsample_init_smc91x();
-        if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
+        BUG_ON(gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0);
-                BUG();
        gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
        omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
@@ -362,7 +361,6 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
        .atag_offset    = 0x100,
        .map_io         = omap_fsample_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_fsample_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 4ec579fdd366..608e7d2a2778 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -81,7 +81,6 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
        .atag_offset    = 0x100,
        .map_io         = omap16xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_generic_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index e1362ce48497..7119ef28e0ad 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -13,12 +13,11 @@
 */
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/i2c/tps65010.h>
-#include <plat/mmc.h>
 #include "board-h2.h"
+#include "mmc.h"
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 376f7f29ef77..2274bd677efc 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -39,8 +39,8 @@
 #include <asm/mach/map.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/flash.h>
@@ -50,6 +50,7 @@
 #include "common.h"
 #include "board-h2.h"
+#include "dma.h"
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
@@ -411,8 +412,7 @@ static void __init h2_init(void)
        h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS;
        h2_nand_resource.end += SZ_4K - 1;
-        if (gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
+        BUG_ON(gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0);
-                BUG();
        gpio_direction_input(H2_NAND_RB_GPIO_PIN);
        omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
@@ -458,7 +458,6 @@ MACHINE_START(OMAP_H2, "TI-H2")
        .atag_offset    = 0x100,
        .map_io         = omap16xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = h2_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index c74daace8cd6..17d77914d769 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -16,9 +16,8 @@
 #include <linux/i2c/tps65010.h>
-#include <plat/mmc.h>
 #include "board-h3.h"
+#include "mmc.h"
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index ededdb7ef28c..1051935f0aac 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -41,9 +41,9 @@
 #include <asm/mach/map.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <linux/platform_data/keypad-omap.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include <mach/flash.h>
 #include <mach/hardware.h>
@@ -406,8 +406,7 @@ static void __init h3_init(void)
        nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS;
        nand_resource.end += SZ_4K - 1;
-        if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
+        BUG_ON(gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0);
-                BUG();
        gpio_direction_input(H3_NAND_RB_GPIO_PIN);
        /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
@@ -452,7 +451,6 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
        .atag_offset    = 0x100,
        .map_io         = omap16xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = h3_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 87ab2086ef96..356f816c84a6 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -43,7 +43,7 @@
 #include <asm/mach/arch.h>
 #include <mach/omap7xx.h>
-#include <plat/mmc.h>
+#include "mmc.h"
 #include <mach/irqs.h>
 #include <mach/usb.h>
@@ -600,7 +600,6 @@ MACHINE_START(HERALD, "HTC Herald")
        .atag_offset    = 0x100,
        .map_io         = htcherald_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = htcherald_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index db5f7d2976e7..f8033fab0f82 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -33,16 +33,15 @@
 #include <mach/mux.h>
 #include <mach/flash.h>
-#include <plat/fpga.h>
+#include <mach/tc.h>
-#include <plat/tc.h>
 #include <linux/platform_data/keypad-omap.h>
-#include <plat/mmc.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
 #include "iomap.h"
 #include "common.h"
+#include "mmc.h"
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define INNOVATOR1610_ETHR_START        0x04000300
@@ -215,7 +214,7 @@ static struct platform_device *innovator1510_devices[] __initdata = {
 static int innovator_get_pendown_state(void)
 {
-        return !(fpga_read(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
+        return !(__raw_readb(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
 }
 static const struct ads7846_platform_data innovator1510_ts_info = {
@@ -279,7 +278,7 @@ static struct platform_device *innovator1610_devices[] __initdata = {
 static void __init innovator_init_smc91x(void)
 {
        if (cpu_is_omap1510()) {
-                fpga_write(fpga_read(OMAP1510_FPGA_RST) & ~1,
+                __raw_writeb(__raw_readb(OMAP1510_FPGA_RST) & ~1,
                           OMAP1510_FPGA_RST);
                udelay(750);
        } else {
@@ -335,10 +334,10 @@ static int mmc_set_power(struct device *dev, int slot, int power_on,
                                int vdd)
 {
        if (power_on)
-                fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
+                __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) | (1 << 3),
                                OMAP1510_FPGA_POWER);
        else
-                fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
+                __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) & ~(1 << 3),
                                OMAP1510_FPGA_POWER);
        return 0;
@@ -390,14 +389,14 @@ static void __init innovator_init(void)
                omap_cfg_reg(UART3_TX);
                omap_cfg_reg(UART3_RX);
-                reg = fpga_read(OMAP1510_FPGA_POWER);
+                reg = __raw_readb(OMAP1510_FPGA_POWER);
                reg |= OMAP1510_FPGA_PCR_COM1_EN;
-                fpga_write(reg, OMAP1510_FPGA_POWER);
+                __raw_writeb(reg, OMAP1510_FPGA_POWER);
                udelay(10);
-                reg = fpga_read(OMAP1510_FPGA_POWER);
+                reg = __raw_readb(OMAP1510_FPGA_POWER);
                reg |= OMAP1510_FPGA_PCR_COM2_EN;
-                fpga_write(reg, OMAP1510_FPGA_POWER);
+                __raw_writeb(reg, OMAP1510_FPGA_POWER);
                udelay(10);
                platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
@@ -437,6 +436,7 @@ static void __init innovator_init(void)
 */
 static void __init innovator_map_io(void)
 {
+#ifdef CONFIG_ARCH_OMAP15XX
        omap15xx_map_io();
        iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
@@ -444,9 +444,10 @@ static void __init innovator_map_io(void)
        /* Dump the Innovator FPGA rev early - useful info for support. */
        pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n",
-                        fpga_read(OMAP1510_FPGA_REV_HIGH),
+                        __raw_readb(OMAP1510_FPGA_REV_HIGH),
-                        fpga_read(OMAP1510_FPGA_REV_LOW),
+                        __raw_readb(OMAP1510_FPGA_REV_LOW),
-                        fpga_read(OMAP1510_FPGA_BOARD_REV));
+                        __raw_readb(OMAP1510_FPGA_BOARD_REV));
+#endif
 }
 MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
@@ -454,7 +455,6 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
        .atag_offset    = 0x100,
        .map_io         = innovator_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = innovator_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 7d5c06d6a52a..3e8ead67e459 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -29,13 +29,13 @@
 #include <asm/mach/map.h>
 #include <mach/mux.h>
-#include <plat/mmc.h>
-#include <plat/clock.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
 #include "common.h"
+#include "clock.h"
+#include "mmc.h"
 #define ADS7846_PENDOWN_GPIO    15
@@ -251,7 +251,6 @@ MACHINE_START(NOKIA770, "Nokia 770")
        .atag_offset    = 0x100,
        .map_io         = omap16xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_nokia770_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 5973945a8741..872ea47cd28a 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -48,7 +48,7 @@
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -606,7 +606,6 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
        .atag_offset    = 0x100,
        .map_io         = omap16xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = osk_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 1c578d58923a..c33dceb46607 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -36,8 +36,8 @@
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
@@ -45,6 +45,7 @@
 #include <mach/usb.h>
 #include "common.h"
+#include "dma.h"
 #define PALMTE_USBDETECT_GPIO   0
 #define PALMTE_USB_OR_DC_GPIO   1
@@ -264,7 +265,6 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
        .atag_offset    = 0x100,
        .map_io         = omap15xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmte_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 97158095083c..2948b0ee4be8 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -28,16 +28,16 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/platform_data/omap1_bl.h>
+#include <linux/platform_data/leds-omap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/led.h>
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
@@ -45,6 +45,7 @@
 #include <mach/usb.h>
 #include "common.h"
+#include "dma.h"
 #define PALMTT_USBDETECT_GPIO   0
 #define PALMTT_CABLE_GPIO       1
@@ -310,7 +311,6 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
        .atag_offset    = 0x100,
        .map_io         = omap15xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmtt_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e311032e7eeb..7a05895c0be3 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -38,8 +38,8 @@
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
@@ -47,6 +47,7 @@
 #include <mach/usb.h>
 #include "common.h"
+#include "dma.h"
 #define PALMZ71_USBDETECT_GPIO  0
 #define PALMZ71_PENIRQ_GPIO     6
@@ -326,7 +327,6 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
        .atag_offset    = 0x100,
        .map_io         = omap15xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmz71_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 198b05417bfc..27f8d12ec222 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -28,15 +28,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/mux.h>
-#include <plat/fpga.h>
 #include <mach/flash.h>
 #include <mach/hardware.h>
 #include "iomap.h"
 #include "common.h"
+#include "fpga.h"
 static const unsigned int p2_keymap[] = {
        KEY(0, 0, KEY_UP),
@@ -231,9 +231,9 @@ static struct omap_lcd_config perseus2_lcd_config __initdata = {
 static void __init perseus2_init_smc91x(void)
 {
-        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+        __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
        mdelay(50);
-        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+        __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
                   H2P2_DBG_FPGA_LAN_RESET);
        mdelay(50);
 }
@@ -275,8 +275,7 @@ static void __init omap_perseus2_init(void)
        perseus2_init_smc91x();
-        if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
+        BUG_ON(gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0);
-                BUG();
        gpio_direction_input(P2_NAND_RB_GPIO_PIN);
        omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
@@ -324,7 +323,6 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
        .atag_offset    = 0x100,
        .map_io         = omap_perseus2_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_perseus2_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index 5932d56e17bf..4fcf19c78a08 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -16,9 +16,10 @@
 #include <linux/platform_device.h>
 #include <mach/hardware.h>
-#include <plat/mmc.h>
 #include <mach/board-sx1.h>
+#include "mmc.h"
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 static int mmc_set_power(struct device *dev, int slot, int power_on,
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 13bf2cc56814..20ed52ae1714 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -36,15 +36,16 @@
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include <mach/irda.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/board-sx1.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
 #include "common.h"
+#include "dma.h"
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
@@ -403,7 +404,6 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
        .atag_offset    = 0x100,
        .map_io         = omap15xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_sx1_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index ad75e3411d46..abf705f49b19 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -34,7 +34,7 @@
 #include <mach/board-voiceblue.h>
 #include <mach/flash.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -286,7 +286,6 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
        .atag_offset    = 0x100,
        .map_io         = omap15xx_map_io,
        .init_early     = omap1_init_early,
-        .reserve        = omap_reserve,
        .init_irq       = omap1_init_irq,
        .init_machine   = voiceblue_init,
        .init_late      = omap1_init_late,
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 638f4070fc70..4f5fd4a084c0 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -12,6 +12,7 @@
 * published by the Free Software Foundation.
 */
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
@@ -21,21 +22,21 @@
 #include <asm/mach-types.h>
-#include <plat/cpu.h>
-#include <plat/usb.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/clkdev_omap.h>
 #include <mach/hardware.h>
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "opp.h"
+#include "sram.h"
 __u32 arm_idlect1_mask;
 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+static DEFINE_SPINLOCK(clockfw_lock);
 /*
 * Omap1 specific clock functions
 */
@@ -607,3 +608,497 @@ void omap1_clk_disable_unused(struct clk *clk)
 }
 #endif
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        int ret;
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap1_clk_enable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+        if (clk == NULL || IS_ERR(clk))
+                return;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (clk->usecount == 0) {
+                pr_err("Trying disable clock %s with 0 usecount\n",
+                       clk->name);
+                WARN_ON(1);
+                goto out;
+        }
+        omap1_clk_disable(clk);
+out:
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long flags;
+        unsigned long ret;
+        if (clk == NULL || IS_ERR(clk))
+                return 0;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = clk->rate;
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return ret;
+}
+EXPORT_SYMBOL(clk_get_rate);
+/*
+ * Optional clock functions defined in include/linux/clk.h
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        long ret;
+        if (clk == NULL || IS_ERR(clk))
+                return 0;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap1_clk_round_rate(clk, rate);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return ret;
+}
+EXPORT_SYMBOL(clk_round_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        int ret = -EINVAL;
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        ret = omap1_clk_set_rate(clk, rate);
+        if (ret == 0)
+                propagate_rate(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n");
+        return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_parent);
+struct clk *clk_get_parent(struct clk *clk)
+{
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+/*
+ * OMAP specific clock functions shared between omap1 and omap2
+ */
+int __initdata mpurate;
+/*
+ * By default we use the rate set by the bootloader.
+ * You can override this with mpurate= cmdline option.
+ */
+static int __init omap_clk_setup(char *str)
+{
+        get_option(&str, &mpurate);
+        if (!mpurate)
+                return 1;
+        if (mpurate < 1000)
+                mpurate *= 1000000;
+        return 1;
+}
+__setup("mpurate=", omap_clk_setup);
+/* Used for clocks that always have same value as the parent clock */
+unsigned long followparent_recalc(struct clk *clk)
+{
+        return clk->parent->rate;
+}
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+{
+        WARN_ON(!clk->fixed_div);
+        return clk->parent->rate / clk->fixed_div;
+}
+void clk_reparent(struct clk *child, struct clk *parent)
+{
+        list_del_init(&child->sibling);
+        if (parent)
+                list_add(&child->sibling, &parent->children);
+        child->parent = parent;
+        /* now do the debugfs renaming to reattach the child
+           to the proper parent */
+}
+/* Propagate rate to children */
+void propagate_rate(struct clk *tclk)
+{
+        struct clk *clkp;
+        list_for_each_entry(clkp, &tclk->children, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
+        }
+}
+static LIST_HEAD(root_clks);
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+        struct clk *clkp;
+        list_for_each_entry(clkp, &root_clks, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
+        }
+}
+/**
+ * clk_preinit - initialize any fields in the struct clk before clk init
+ * @clk: struct clk * to initialize
+ *
+ * Initialize any struct clk fields needed before normal clk initialization
+ * can run.  No return value.
+ */
+void clk_preinit(struct clk *clk)
+{
+        INIT_LIST_HEAD(&clk->children);
+}
+int clk_register(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+        /*
+         * trap out already registered clocks
+         */
+        if (clk->node.next || clk->node.prev)
+                return 0;
+        mutex_lock(&clocks_mutex);
+        if (clk->parent)
+                list_add(&clk->sibling, &clk->parent->children);
+        else
+                list_add(&clk->sibling, &root_clks);
+        list_add(&clk->node, &clocks);
+        if (clk->init)
+                clk->init(clk);
+        mutex_unlock(&clocks_mutex);
+        return 0;
+}
+EXPORT_SYMBOL(clk_register);
+void clk_unregister(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+        mutex_lock(&clocks_mutex);
+        list_del(&clk->sibling);
+        list_del(&clk->node);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_unregister);
+void clk_enable_init_clocks(void)
+{
+        struct clk *clkp;
+        list_for_each_entry(clkp, &clocks, node)
+                if (clkp->flags & ENABLE_ON_INIT)
+                        clk_enable(clkp);
+}
+/**
+ * omap_clk_get_by_name - locate OMAP struct clk by its name
+ * @name: name of the struct clk to locate
+ *
+ * Locate an OMAP struct clk by its name.  Assumes that struct clk
+ * names are unique.  Returns NULL if not found or a pointer to the
+ * struct clk if found.
+ */
+struct clk *omap_clk_get_by_name(const char *name)
+{
+        struct clk *c;
+        struct clk *ret = NULL;
+        mutex_lock(&clocks_mutex);
+        list_for_each_entry(c, &clocks, node) {
+                if (!strcmp(c->name, name)) {
+                        ret = c;
+                        break;
+                }
+        }
+        mutex_unlock(&clocks_mutex);
+        return ret;
+}
+int omap_clk_enable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->allow_idle)
+                        c->ops->allow_idle(c);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return 0;
+}
+int omap_clk_disable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->deny_idle)
+                        c->ops->deny_idle(c);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return 0;
+}
+/*
+ * Low level helpers
+ */
+static int clkll_enable_null(struct clk *clk)
+{
+        return 0;
+}
+static void clkll_disable_null(struct clk *clk)
+{
+}
+const struct clkops clkops_null = {
+        .enable         = clkll_enable_null,
+        .disable        = clkll_disable_null,
+};
+/*
+ * Dummy clock
+ *
+ * Used for clock aliases that are needed on some OMAPs, but not others
+ */
+struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_null,
+};
+/*
+ *
+ */
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+/*
+ * Disable any unused clocks left on by the bootloader
+ */
+static int __init clk_disable_unused(void)
+{
+        struct clk *ck;
+        unsigned long flags;
+        pr_info("clock: disabling unused clocks to save power\n");
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(ck, &clocks, node) {
+                if (ck->ops == &clkops_null)
+                        continue;
+                if (ck->usecount > 0 || !ck->enable_reg)
+                        continue;
+                omap1_clk_disable_unused(ck);
+        }
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return 0;
+}
+late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
+#endif
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes
+ */
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+static struct dentry *clk_debugfs_root;
+static int clk_dbg_show_summary(struct seq_file *s, void *unused)
+{
+        struct clk *c;
+        struct clk *pa;
+        mutex_lock(&clocks_mutex);
+        seq_printf(s, "%-30s %-30s %-10s %s\n",
+                   "clock-name", "parent-name", "rate", "use-count");
+        list_for_each_entry(c, &clocks, node) {
+                pa = c->parent;
+                seq_printf(s, "%-30s %-30s %-10lu %d\n",
+                           c->name, pa ? pa->name : "none", c->rate,
+                           c->usecount);
+        }
+        mutex_unlock(&clocks_mutex);
+        return 0;
+}
+static int clk_dbg_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, clk_dbg_show_summary, inode->i_private);
+}
+static const struct file_operations debug_clock_fops = {
+        .open           = clk_dbg_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+static int clk_debugfs_register_one(struct clk *c)
+{
+        int err;
+        struct dentry *d;
+        struct clk *pa = c->parent;
+        d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
+        if (!d)
+                return -ENOMEM;
+        c->dent = d;
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        return 0;
+err_out:
+        debugfs_remove_recursive(c->dent);
+        return err;
+}
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent;
+        if (pa && !pa->dent) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+        if (!c->dent) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+        d = debugfs_create_dir("clock", NULL);
+        if (!d)
+                return -ENOMEM;
+        clk_debugfs_root = d;
+        list_for_each_entry(c, &clocks, node) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+        d = debugfs_create_file("summary", S_IRUGO,
+                d, NULL, &debug_clock_fops);
+        if (!d)
+                return -ENOMEM;
+        return 0;
+err_out:
+        debugfs_remove_recursive(clk_debugfs_root);
+        return err;
+}
+late_initcall(clk_debugfs_init);
+#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 3d04f4f67676..1e4918a3a5ee 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -14,8 +14,184 @@
 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
 #include <linux/clk.h>
+#include <linux/list.h>
-#include <plat/clock.h>
+#include <linux/clkdev.h>
+struct module;
+struct clk;
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+/* Platform flags for the clkdev-OMAP integration code */
+#define CK_310          (1 << 0)
+#define CK_7XX          (1 << 1)        /* 7xx, 850 */
+#define CK_1510         (1 << 2)
+#define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
+#define CK_1710         (1 << 4)        /* 1710 extra for rate selection */
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk)     (clk->name)
+#define __clk_get_parent(clk)   (clk->parent)
+#define __clk_get_rate(clk)     (clk->rate)
+/**
+ * struct clkops - some clock function pointers
+ * @enable: fn ptr that enables the current clock in hardware
+ * @disable: fn ptr that enables the current clock in hardware
+ * @find_idlest: function returning the IDLEST register for the clock's IP blk
+ * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
+ *
+ * A "companion" clk is an accompanying clock to the one being queried
+ * that must be enabled for the IP module connected to the clock to
+ * become accessible by the hardware.  Neither @find_idlest nor
+ * @find_companion should be needed; that information is IP
+ * block-specific; the hwmod code has been created to handle this, but
+ * until hwmod data is ready and drivers have been converted to use PM
+ * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
+ * @find_companion must, unfortunately, remain.
+ */
+struct clkops {
+        int                     (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+        void                    (*find_idlest)(struct clk *, void __iomem **,
+                                               u8 *, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **,
+                                                  u8 *);
+        void                    (*allow_idle)(struct clk *);
+        void                    (*deny_idle)(struct clk *);
+};
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
+#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL      (1 << 1)
+#define CLOCK_NO_IDLE_PARENT    (1 << 2)
+#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2          (1 << 5)
+/**
+ * struct clk - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @ops: struct clkops * for this clock
+ * @name: the name of the clock in the hardware (used in hwmod data and debug)
+ * @parent: pointer to this clock's parent struct clk
+ * @children: list_head connecting to the child clks' @sibling list_heads
+ * @sibling: list_head connecting this clk to its parent clk's @children
+ * @rate: current clock rate
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @recalc: fn ptr that returns the clock's current rate
+ * @set_rate: fn ptr that can change the clock's current rate
+ * @round_rate: fn ptr that can round the clock's current rate
+ * @init: fn ptr to do clock-specific initialization
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @usecount: number of users that have requested this clock to be enabled
+ * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
+ * @flags: see "struct clk.flags possibilities" above
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ * XXX @usecount is poorly named.  It should be "enable_count" or
+ * something similar.  "users" in the description refers to kernel
+ * code (core code or drivers) that have called clk_enable() and not
+ * yet called clk_disable(); the usecount of parent clocks is also
+ * incremented by the clock code when clk_enable() is called on child
+ * clocks and decremented by the clock code when clk_disable() is
+ * called on child clocks.
+ *
+ * XXX @clkdm, @usecount, @children, @sibling should be marked for
+ * internal use only.
+ *
+ * @children and @sibling are used to optimize parent-to-child clock
+ * tree traversals.  (child-to-parent traversals use @parent.)
+ *
+ * XXX The notion of the clock's current rate probably needs to be
+ * separated from the clock's target rate.
+ */
+struct clk {
+        struct list_head        node;
+        const struct clkops     *ops;
+        const char              *name;
+        struct clk              *parent;
+        struct list_head        children;
+        struct list_head        sibling;        /* node for children */
+        unsigned long           rate;
+        void __iomem            *enable_reg;
+        unsigned long           (*recalc)(struct clk *);
+        int                     (*set_rate)(struct clk *, unsigned long);
+        long                    (*round_rate)(struct clk *, unsigned long);
+        void                    (*init)(struct clk *);
+        u8                      enable_bit;
+        s8                      usecount;
+        u8                      fixed_div;
+        u8                      flags;
+        u8                      rate_offset;
+        u8                      src_offset;
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
+};
+struct clk_functions {
+        int             (*clk_enable)(struct clk *clk);
+        void            (*clk_disable)(struct clk *clk);
+        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
+        void            (*clk_allow_idle)(struct clk *clk);
+        void            (*clk_deny_idle)(struct clk *clk);
+        void            (*clk_disable_unused)(struct clk *clk);
+};
+extern int mpurate;
+extern int clk_init(struct clk_functions *custom_clocks);
+extern void clk_preinit(struct clk *clk);
+extern int clk_register(struct clk *clk);
+extern void clk_reparent(struct clk *child, struct clk *parent);
+extern void clk_unregister(struct clk *clk);
+extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
+extern unsigned long followparent_recalc(struct clk *clk);
+extern void clk_enable_init_clocks(void);
+unsigned long omap_fixed_divisor_recalc(struct clk *clk);
+extern struct clk *omap_clk_get_by_name(const char *name);
+extern int omap_clk_enable_autoidle_all(void);
+extern int omap_clk_disable_autoidle_all(void);
+extern const struct clkops clkops_null;
+extern struct clk dummy_ck;
 int omap1_clk_init(void);
 void omap1_clk_late_init(void);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 9b45f4b0ee22..cb7c6ae2e3fc 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -22,16 +22,14 @@
 #include <asm/mach-types.h>  /* for machine_is_* */
-#include <plat/clock.h>
+#include "soc.h"
-#include <plat/cpu.h>
-#include <plat/clkdev_omap.h>
-#include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
 #include <mach/hardware.h>
 #include <mach/usb.h>   /* for OTG_BASE */
 #include "iomap.h"
 #include "clock.h"
+#include "sram.h"
 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
 #define IDL_CLKOUT_ARM_SHIFT                    12
@@ -765,14 +763,6 @@ static struct omap_clk omap_clks[] = {
 * init
 */
-static struct clk_functions omap1_clk_functions = {
-        .clk_enable             = omap1_clk_enable,
-        .clk_disable            = omap1_clk_disable,
-        .clk_round_rate         = omap1_clk_round_rate,
-        .clk_set_rate           = omap1_clk_set_rate,
-        .clk_disable_unused     = omap1_clk_disable_unused,
-};
 static void __init omap1_show_rates(void)
 {
        pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
@@ -803,8 +793,6 @@ int __init omap1_clk_init(void)
        if (!cpu_is_omap15xx())
                omap_writew(0, SOFT_REQ_REG2);
-        clk_init(&omap1_clk_functions);
        /* By default all idlect1 clocks are allowed to idle */
        arm_idlect1_mask = ~0;
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index c2552b24f9f2..b53e0854422f 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -26,8 +26,10 @@
 #ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
 #define __ARCH_ARM_MACH_OMAP1_COMMON_H
-#include <plat/common.h>
 #include <linux/mtd/mtd.h>
+#include <linux/i2c-omap.h>
+#include <plat/i2c.h>
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 void omap7xx_map_io(void);
@@ -38,6 +40,7 @@ static inline void omap7xx_map_io(void)
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
+void omap1510_fpga_init_irq(void);
 void omap15xx_map_io(void);
 #else
 static inline void omap15xx_map_io(void)
@@ -90,4 +93,6 @@ extern int ocpi_enable(void);
 static inline int ocpi_enable(void) { return 0; }
 #endif
+extern u32 omap1_get_reset_sources(void);
 #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index d3fec92c54cb..0af635205e8a 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -17,12 +17,12 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/omap-wd-timer.h>
 #include <asm/mach/map.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
-#include <plat/mmc.h>
 #include <mach/omap7xx.h>
 #include <mach/camera.h>
@@ -30,6 +30,9 @@
 #include "common.h"
 #include "clock.h"
+#include "dma.h"
+#include "mmc.h"
+#include "sram.h"
 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
@@ -175,6 +178,13 @@ static int __init omap_mmc_add(const char *name, int id, unsigned long base,
        res[3].name = "tx";
        res[3].flags = IORESOURCE_DMA;
+        if (cpu_is_omap7xx())
+                data->slots[0].features = MMC_OMAP7XX;
+        if (cpu_is_omap15xx())
+                data->slots[0].features = MMC_OMAP15XX;
+        if (cpu_is_omap16xx())
+                data->slots[0].features = MMC_OMAP16XX;
        ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
        if (ret == 0)
                ret = platform_device_add_data(pdev, data, sizeof(*data));
@@ -439,18 +449,31 @@ static struct resource wdt_resources[] = {
 };
 static struct platform_device omap_wdt_device = {
-        .name      = "omap_wdt",
+        .name           = "omap_wdt",
-        .id          = -1,
+        .id             = -1,
        .num_resources  = ARRAY_SIZE(wdt_resources),
        .resource       = wdt_resources,
 };
 static int __init omap_init_wdt(void)
 {
+        struct omap_wd_timer_platform_data pdata;
+        int ret;
        if (!cpu_is_omap16xx())
                return -ENODEV;
-        return platform_device_register(&omap_wdt_device);
+        pdata.read_reset_sources = omap1_get_reset_sources;
+        ret = platform_device_register(&omap_wdt_device);
+        if (!ret) {
+                ret = platform_device_add_data(&omap_wdt_device, &pdata,
+                                               sizeof(pdata));
+                if (ret)
+                        platform_device_del(&omap_wdt_device);
+        }
+        return ret;
 }
 subsys_initcall(omap_init_wdt);
 #endif
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 29007fef84cd..e190611e4b46 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -25,11 +25,13 @@
 #include <linux/device.h>
 #include <linux/io.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/irqs.h>
+#include "dma.h"
 #define OMAP1_DMA_BASE                  (0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
 #define OMAP1_DMA_STRIDE                0x40
@@ -319,6 +321,9 @@ static int __init omap1_system_dma_init(void)
                d->dev_caps = ENABLE_1510_MODE;
        enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
+        if (cpu_is_omap16xx())
+                d->dev_caps = ENABLE_16XX_MODE;
        d->dev_caps             |= SRC_PORT;
        d->dev_caps             |= DST_PORT;
        d->dev_caps             |= SRC_INDEX;
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h
new file mode 100644
index 000000000000..da6345dab03f
--- /dev/null
+++ b/arch/arm/mach-omap1/dma.h
@@ -0,0 +1,83 @@
+/*
+ *  OMAP1 DMA channel definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __OMAP1_DMA_CHANNEL_H
+#define __OMAP1_DMA_CHANNEL_H
+/* DMA channels for omap1 */
+#define OMAP_DMA_NO_DEVICE              0
+#define OMAP_DMA_MCSI1_TX               1
+#define OMAP_DMA_MCSI1_RX               2
+#define OMAP_DMA_I2C_RX                 3
+#define OMAP_DMA_I2C_TX                 4
+#define OMAP_DMA_EXT_NDMA_REQ           5
+#define OMAP_DMA_EXT_NDMA_REQ2          6
+#define OMAP_DMA_UWIRE_TX               7
+#define OMAP_DMA_MCBSP1_TX              8
+#define OMAP_DMA_MCBSP1_RX              9
+#define OMAP_DMA_MCBSP3_TX              10
+#define OMAP_DMA_MCBSP3_RX              11
+#define OMAP_DMA_UART1_TX               12
+#define OMAP_DMA_UART1_RX               13
+#define OMAP_DMA_UART2_TX               14
+#define OMAP_DMA_UART2_RX               15
+#define OMAP_DMA_MCBSP2_TX              16
+#define OMAP_DMA_MCBSP2_RX              17
+#define OMAP_DMA_UART3_TX               18
+#define OMAP_DMA_UART3_RX               19
+#define OMAP_DMA_CAMERA_IF_RX           20
+#define OMAP_DMA_MMC_TX                 21
+#define OMAP_DMA_MMC_RX                 22
+#define OMAP_DMA_NAND                   23
+#define OMAP_DMA_IRQ_LCD_LINE           24
+#define OMAP_DMA_MEMORY_STICK           25
+#define OMAP_DMA_USB_W2FC_RX0           26
+#define OMAP_DMA_USB_W2FC_RX1           27
+#define OMAP_DMA_USB_W2FC_RX2           28
+#define OMAP_DMA_USB_W2FC_TX0           29
+#define OMAP_DMA_USB_W2FC_TX1           30
+#define OMAP_DMA_USB_W2FC_TX2           31
+/* These are only for 1610 */
+#define OMAP_DMA_CRYPTO_DES_IN          32
+#define OMAP_DMA_SPI_TX                 33
+#define OMAP_DMA_SPI_RX                 34
+#define OMAP_DMA_CRYPTO_HASH            35
+#define OMAP_DMA_CCP_ATTN               36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
+#define OMAP_DMA_MMC2_TX                54
+#define OMAP_DMA_MMC2_RX                55
+#define OMAP_DMA_CRYPTO_DES_OUT         56
+#endif /* __OMAP1_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 73ae6169aa4a..b3fb531af94e 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -10,7 +10,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
 #include <mach/flash.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 29ec50fc688d..8bd71b2d0967 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -27,11 +27,11 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <plat/fpga.h>
 #include <mach/hardware.h>
 #include "iomap.h"
+#include "common.h"
+#include "fpga.h"
 static void fpga_mask_irq(struct irq_data *d)
 {
diff --git a/arch/arm/mach-omap1/fpga.h b/arch/arm/mach-omap1/fpga.h
new file mode 100644
index 000000000000..4b4307a80e48
--- /dev/null
+++ b/arch/arm/mach-omap1/fpga.h
@@ -0,0 +1,52 @@
+/*
+ * Interrupt handler for OMAP-1510 FPGA
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP_FPGA_H
+#define __ASM_ARCH_OMAP_FPGA_H
+/*
+ * ---------------------------------------------------------------------------
+ *  H2/P2 Debug board FPGA
+ * ---------------------------------------------------------------------------
+ */
+/* maps in the FPGA registers and the ETHR registers */
+#define H2P2_DBG_FPGA_BASE              0xE8000000              /* VA */
+#define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
+#define H2P2_DBG_FPGA_START             0x04000000              /* PA */
+#define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
+#define H2P2_DBG_FPGA_FPGA_REV          IOMEM(H2P2_DBG_FPGA_BASE + 0x10)        /* FPGA Revision */
+#define H2P2_DBG_FPGA_BOARD_REV         IOMEM(H2P2_DBG_FPGA_BASE + 0x12)        /* Board Revision */
+#define H2P2_DBG_FPGA_GPIO              IOMEM(H2P2_DBG_FPGA_BASE + 0x14)        /* GPIO outputs */
+#define H2P2_DBG_FPGA_LEDS              IOMEM(H2P2_DBG_FPGA_BASE + 0x16)        /* LEDs outputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS       IOMEM(H2P2_DBG_FPGA_BASE + 0x18)        /* Misc inputs */
+#define H2P2_DBG_FPGA_LAN_STATUS        IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)        /* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_RESET         IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)        /* LAN Reset line */
+/* LEDs definition on debug board (16 LEDs, all physically green) */
+#define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
+#define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
+#define H2P2_DBG_FPGA_LED_RED           (1 << 13)
+#define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
+/*  cpu0 load-meter LEDs */
+#define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
+#define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
+#define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
+#define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
+#define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
+#endif
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 98e6f39224a4..02b3eb2e201c 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -19,6 +19,8 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <mach/irqs.h>
 #define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
 #define OMAP1510_GPIO_BASE              0xFFFCE000
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 33f419236b17..b9952a258d82 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -19,6 +19,8 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <mach/irqs.h>
 #define OMAP1610_GPIO1_BASE             0xfffbe400
 #define OMAP1610_GPIO2_BASE             0xfffbec00
 #define OMAP1610_GPIO3_BASE             0xfffbb400
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 958ce9acee95..f5819b2b7cbe 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -19,6 +19,8 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <mach/irqs.h>
 #define OMAP7XX_GPIO1_BASE              0xfffbc000
 #define OMAP7XX_GPIO2_BASE              0xfffbc800
 #define OMAP7XX_GPIO3_BASE              0xfffbd000
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index a0551a6d7451..faca808cb3d9 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -19,11 +19,25 @@
 *
 */
-#include <plat/i2c.h>
+#include <linux/i2c-omap.h>
 #include <mach/mux.h>
-#include <plat/cpu.h>
+#include "soc.h"
+#include <plat/i2c.h>
+#define OMAP_I2C_SIZE           0x3f
+#define OMAP1_I2C_BASE          0xfffb3800
+#define OMAP1_INT_I2C           (32 + 4)
+static const char name[] = "omap_i2c";
-void __init omap1_i2c_mux_pins(int bus_id)
+static struct resource i2c_resources[2] = {
+};
+static struct platform_device omap_i2c_devices[1] = {
+};
+static void __init omap1_i2c_mux_pins(int bus_id)
 {
        if (cpu_is_omap7xx()) {
                omap_cfg_reg(I2C_7XX_SDA);
@@ -33,3 +47,47 @@ void __init omap1_i2c_mux_pins(int bus_id)
                omap_cfg_reg(I2C_SCL);
        }
 }
+int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
+                                int bus_id)
+{
+        struct platform_device *pdev;
+        struct resource *res;
+        if (bus_id > 1)
+                return -EINVAL;
+        omap1_i2c_mux_pins(bus_id);
+        pdev = &omap_i2c_devices[bus_id - 1];
+        pdev->id = bus_id;
+        pdev->name = name;
+        pdev->num_resources = ARRAY_SIZE(i2c_resources);
+        res = i2c_resources;
+        res[0].start = OMAP1_I2C_BASE;
+        res[0].end = res[0].start + OMAP_I2C_SIZE;
+        res[0].flags = IORESOURCE_MEM;
+        res[1].start = OMAP1_INT_I2C;
+        res[1].flags = IORESOURCE_IRQ;
+        pdev->resource = res;
+        /* all OMAP1 have IP version 1 register set */
+        pdata->rev = OMAP_I2C_IP_VERSION_1;
+        /* all OMAP1 I2C are implemented like this */
+        pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
+                       OMAP_I2C_FLAG_SIMPLE_CLOCK |
+                       OMAP_I2C_FLAG_16BIT_DATA_REG |
+                       OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
+        /* how the cpu bus is wired up differs for 7xx only */
+        if (cpu_is_omap7xx())
+                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
+        else
+                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
+        pdev->dev.platform_data = pdata;
+        return platform_device_register(pdev);
+}
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index a1b846aacdaf..52de382fc804 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <asm/system_info.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index 2b36a281dc84..5c1a26c9f490 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
 #include <linux/serial_reg.h>
-#include <plat/serial.h>
+#include "serial.h"
                .pushsection .data
 omap_uart_phys: .word   0x0
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index 88f08cab1717..78a8c6c24764 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -13,8 +13,6 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include "../../iomap.h"
                .macro  get_irqnr_preamble, base, tmp
                .endm
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h
deleted file mode 100644
index ebf86c0f4f46..000000000000
--- a/arch/arm/mach-omap1/include/mach/gpio.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/gpio.h
- */
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index 84248d250adb..5875a5098d35 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -39,7 +39,7 @@
 #include <asm/sizes.h>
 #ifndef __ASSEMBLER__
 #include <asm/types.h>
-#include <plat/cpu.h>
+#include <mach/soc.h>
 /*
 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
@@ -51,7 +51,7 @@ extern void omap_writeb(u8 v, u32 pa);
 extern void omap_writew(u16 v, u32 pa);
 extern void omap_writel(u32 v, u32 pa);
-#include <plat/tc.h>
+#include <mach/tc.h>
 /* Almost all documentation for chip and board memory maps assumes
 * BM is clear.  Most devel boards have a switch to control booting
@@ -72,7 +72,10 @@ static inline u32 omap_cs3_phys(void)
 #endif  /* ifndef __ASSEMBLER__ */
-#include <plat/serial.h>
+#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
+#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
+#include <mach/serial.h>
 /*
 * ---------------------------------------------------------------------------
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
index 901082def9bd..3c2530523111 100644
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ b/arch/arm/mach-omap1/include/mach/memory.h
@@ -19,7 +19,7 @@
 * because of the strncmp().
 */
 #if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__)
-#include <plat/cpu.h>
+#include <mach/soc.h>
 /*
 * OMAP-1510 Local Bus address offset
diff --git a/arch/arm/mach-omap1/include/mach/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h
index 8fe05d6137c0..3d235244bf5c 100644
--- a/arch/arm/mach-omap1/include/mach/omap1510.h
+++ b/arch/arm/mach-omap1/include/mach/omap1510.h
@@ -45,5 +45,118 @@
 #define OMAP1510_DSP_MMU_BASE   (0xfffed200)
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
+#define OMAP1510_FPGA_SIZE              SZ_4K
+#define OMAP1510_FPGA_START             0x08000000              /* PA */
+/* Revision */
+#define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
+/* Interrupt status */
+#define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
+/* Interrupt mask */
+#define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
+/* Reset registers */
+#define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
+#define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
+#define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
+#define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
+#define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
+#define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
+/*
+ * Power up Giga UART driver, turn on HID clock.
+ * Turn off BT power, since we're not using it and it
+ * draws power.
+ */
+#define OMAP1510_FPGA_RESET_VALUE               0x42
+#define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
+#define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
+#define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
+#define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
+#define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
+#define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
+#define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
+#define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
+/*
+ * Innovator/OMAP1510 FPGA HID register bit definitions
+ */
+#define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
+#define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
+#define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
+#define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
+#define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
+#define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
+#define OMAP1510_FPGA_HID_rsrvd (1<<6)
+#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
+/* The FPGA IRQ is cascaded through GPIO_13 */
+#define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
+/* IRQ Numbers for interrupts muxed through the FPGA */
+#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
+#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
+#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
+#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
+#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
+#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
+#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
+#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
+#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
+#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
+#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
+#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
+#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
+#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
+#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
+#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
+#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
+#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
+#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
+#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
 #endif /*  __ASM_ARCH_OMAP15XX_H */
diff --git a/arch/arm/mach-omap1/include/mach/serial.h b/arch/arm/mach-omap1/include/mach/serial.h
new file mode 100644
index 000000000000..2ce6a2db470b
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/serial.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+#include <linux/init.h>
+/*
+ * Memory entry used for the DEBUG_LL UART configuration, relative to
+ * start of RAM. See also uncompress.h and debug-macro.S.
+ *
+ * Note that using a memory location for storing the UART configuration
+ * has at least two limitations:
+ *
+ * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
+ *    uncompress code could then partially overwrite itself
+ * 2. We assume printascii is called at least once before paging_init,
+ *    and addruart has a chance to read OMAP_UART_INFO
+ */
+#define OMAP_UART_INFO_OFS      0x3ffc
+/* OMAP1 serial ports */
+#define OMAP1_UART1_BASE        0xfffb0000
+#define OMAP1_UART2_BASE        0xfffb0800
+#define OMAP1_UART3_BASE        0xfffb9800
+#define OMAP_PORT_SHIFT         2
+#define OMAP7XX_PORT_SHIFT      0
+#define OMAP1510_BASE_BAUD      (12000000/16)
+#define OMAP16XX_BASE_BAUD      (48000000/16)
+/*
+ * DEBUG_LL port encoding stored into the UART1 scratchpad register by
+ * decomp_setup in uncompress.h
+ */
+#define OMAP1UART1              11
+#define OMAP1UART2              12
+#define OMAP1UART3              13
+#ifndef __ASSEMBLER__
+extern void omap_serial_init(void);
+#endif
+#endif
diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h
new file mode 100644
index 000000000000..6cf9c1cc2bef
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/soc.h
@@ -0,0 +1,229 @@
+/*
+ * OMAP cpu type detection
+ *
+ * Copyright (C) 2004, 2008 Nokia Corporation
+ *
+ * Copyright (C) 2009-11 Texas Instruments.
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_OMAP_CPU_H
+#define __ASM_ARCH_OMAP_CPU_H
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP1
+#undef OMAP_NAME
+#ifdef CONFIG_ARCH_OMAP730
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap730
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP850
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap850
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap1510
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap16xx
+# endif
+#endif
+/*
+ * omap_rev bits:
+ * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
+ * CPU revision (See _REV_ defined in cpu.h)    [15:08]
+ * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
+ */
+unsigned int omap_rev(void);
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
+/*
+ * Macros to group OMAP into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap7xx():    True for OMAP730, OMAP850
+ * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
+ * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
+ */
+#define GET_OMAP_CLASS  (omap_rev() & 0xff)
+#define IS_OMAP_CLASS(class, id)                        \
+static inline int is_omap ##class (void)                \
+{                                                       \
+        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
+}
+#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
+#define IS_OMAP_SUBCLASS(subclass, id)                  \
+static inline int is_omap ##subclass (void)             \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+IS_OMAP_CLASS(7xx, 0x07)
+IS_OMAP_CLASS(15xx, 0x15)
+IS_OMAP_CLASS(16xx, 0x16)
+#define cpu_is_omap7xx()                0
+#define cpu_is_omap15xx()               0
+#define cpu_is_omap16xx()               0
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             is_omap15xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             is_omap16xx()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             1
+# endif
+#endif
+/*
+ * Macros to detect individual cpu types.
+ * These are only rarely needed.
+ * cpu_is_omap310():    True for OMAP310
+ * cpu_is_omap1510():   True for OMAP1510
+ * cpu_is_omap1610():   True for OMAP1610
+ * cpu_is_omap1611():   True for OMAP1611
+ * cpu_is_omap5912():   True for OMAP5912
+ * cpu_is_omap1621():   True for OMAP1621
+ * cpu_is_omap1710():   True for OMAP1710
+ */
+#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+IS_OMAP_TYPE(310, 0x0310)
+IS_OMAP_TYPE(1510, 0x1510)
+IS_OMAP_TYPE(1610, 0x1610)
+IS_OMAP_TYPE(1611, 0x1611)
+IS_OMAP_TYPE(5912, 0x1611)
+IS_OMAP_TYPE(1621, 0x1621)
+IS_OMAP_TYPE(1710, 0x1710)
+#define cpu_is_omap310()                0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap5912()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+/* These are needed to compile common code */
+#ifdef CONFIG_ARCH_OMAP1
+#define cpu_is_omap242x()               0
+#define cpu_is_omap2430()               0
+#define cpu_is_omap243x()               0
+#define cpu_is_omap24xx()               0
+#define cpu_is_omap34xx()               0
+#define cpu_is_omap44xx()               0
+#define soc_is_omap54xx()               0
+#define soc_is_am33xx()                 0
+#define cpu_class_is_omap1()            1
+#define cpu_class_is_omap2()            0
+#endif
+/*
+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
+ * between 310 vs. 1510 and 1611B/5912 vs. 1710.
+ */
+#if defined(CONFIG_ARCH_OMAP15XX)
+# undef  cpu_is_omap310
+# undef  cpu_is_omap1510
+# define cpu_is_omap310()               is_omap310()
+# define cpu_is_omap1510()              is_omap1510()
+#endif
+#if defined(CONFIG_ARCH_OMAP16XX)
+# undef  cpu_is_omap1610
+# undef  cpu_is_omap1611
+# undef  cpu_is_omap5912
+# undef  cpu_is_omap1621
+# undef  cpu_is_omap1710
+# define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap1611()              is_omap1611()
+# define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1621()              is_omap1621()
+# define cpu_is_omap1710()              is_omap1710()
+#endif
+#endif  /* __ASSEMBLY__ */
+#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/mach-omap1/include/mach/tc.h
index 1b4b2da86203..1b4b2da86203 100644
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ b/arch/arm/mach-omap1/include/mach/tc.h
diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h
index 0ff22dc075c7..ad6fbe7d83f2 100644
--- a/arch/arm/mach-omap1/include/mach/uncompress.h
+++ b/arch/arm/mach-omap1/include/mach/uncompress.h
@@ -1,5 +1,122 @@
 /*
- * arch/arm/mach-omap1/include/mach/uncompress.h
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
 */
-#include <plat/uncompress.h>
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include "serial.h"
+#define MDR1_MODE_MASK                  0x07
+volatile u8 *uart_base;
+int uart_shift;
+/*
+ * Store the DEBUG_LL uart number into memory.
+ * See also debug-macro.S, and serial.c for related code.
+ */
+static void set_omap_uart_info(unsigned char port)
+{
+        /*
+         * Get address of some.bss variable and round it down
+         * a la CONFIG_AUTO_ZRELADDR.
+         */
+        u32 ram_start = (u32)&uart_shift & 0xf8000000;
+        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
+        *uart_info = port;
+}
+static void putc(int c)
+{
+        if (!uart_base)
+                return;
+        /* Check for UART 16x mode */
+        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
+                return;
+        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
+                barrier();
+        uart_base[UART_TX << uart_shift] = c;
+}
+static inline void flush(void)
+{
+}
+/*
+ * Macros to configure UART1 and debug UART
+ */
+#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
+        if (machine_is_##mach()) {                                      \
+                uart_base = (volatile u8 *)(dbg_uart);                  \
+                uart_shift = (dbg_shft);                                \
+                port = (dbg_id);                                        \
+                set_omap_uart_info(port);                               \
+                break;                                                  \
+        }
+#define DEBUG_LL_OMAP7XX(p, mach)                                       \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
+                OMAP1UART##p)
+#define DEBUG_LL_OMAP1(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP1UART##p)
+static inline void arch_decomp_setup(void)
+{
+        int port = 0;
+        /*
+         * Initialize the port based on the machine ID from the bootloader.
+         * Note that we're using macros here instead of switch statement
+         * as machine_is functions are optimized out for the boards that
+         * are not selected.
+         */
+        do {
+                /* omap7xx/8xx based boards using UART1 with shift 0 */
+                DEBUG_LL_OMAP7XX(1, herald);
+                DEBUG_LL_OMAP7XX(1, omap_perseus2);
+                /* omap15xx/16xx based boards using UART1 */
+                DEBUG_LL_OMAP1(1, ams_delta);
+                DEBUG_LL_OMAP1(1, nokia770);
+                DEBUG_LL_OMAP1(1, omap_h2);
+                DEBUG_LL_OMAP1(1, omap_h3);
+                DEBUG_LL_OMAP1(1, omap_innovator);
+                DEBUG_LL_OMAP1(1, omap_osk);
+                DEBUG_LL_OMAP1(1, omap_palmte);
+                DEBUG_LL_OMAP1(1, omap_palmz71);
+                /* omap15xx/16xx based boards using UART2 */
+                DEBUG_LL_OMAP1(2, omap_palmtt);
+                /* omap15xx/16xx based boards using UART3 */
+                DEBUG_LL_OMAP1(3, sx1);
+        } while (0);
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 6a5baab1f4cb..499b8accb83d 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -17,8 +17,8 @@
 #include <asm/mach/map.h>
 #include <mach/mux.h>
-#include <plat/tc.h>
+#include <mach/tc.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include "iomap.h"
 #include "common.h"
@@ -134,7 +134,6 @@ void __init omap1_init_early(void)
         */
        omap1_clk_init();
        omap1_mux_init();
-        omap_init_consistent_dma_size();
 }
 void __init omap1_init_late(void)
diff --git a/arch/arm/mach-omap1/iomap.h b/arch/arm/mach-omap1/iomap.h
index 330c4716b028..f4e2d7a21365 100644
--- a/arch/arm/mach-omap1/iomap.h
+++ b/arch/arm/mach-omap1/iomap.h
@@ -22,9 +22,6 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
-#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
 /*
 * ----------------------------------------------------------------------------
 * Omap1 specific IO mapping
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 6995fb6a3345..122ef67939a2 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -45,7 +45,7 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index ed42628611bc..77924be37d41 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -27,11 +27,13 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include <mach/hardware.h>
 #include <mach/lcdc.h>
+#include "dma.h"
 int omap_lcd_dma_running(void)
 {
        /*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index bdc2e7541adb..b0d4723c9a90 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -19,14 +19,15 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include <mach/mux.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <mach/irqs.h>
 #include "iomap.h"
+#include "dma.h"
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
diff --git a/arch/arm/mach-omap1/mmc.h b/arch/arm/mach-omap1/mmc.h
new file mode 100644
index 000000000000..39c2b13de884
--- /dev/null
+++ b/arch/arm/mach-omap1/mmc.h
@@ -0,0 +1,18 @@
+#include <linux/mmc/host.h>
+#include <linux/platform_data/mmc-omap.h>
+#define OMAP15XX_NR_MMC         1
+#define OMAP16XX_NR_MMC         2
+#define OMAP1_MMC_SIZE          0x080
+#define OMAP1_MMC1_BASE         0xfffb7800
+#define OMAP1_MMC2_BASE         0xfffb7c00      /* omap16xx only */
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+                                int nr_controllers);
+#else
+static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+                                int nr_controllers)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
index 9cd4ddb51397..8dcebe6d8882 100644
--- a/arch/arm/mach-omap1/opp_data.c
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -10,7 +10,7 @@
 * published by the Free Software Foundation.
 */
-#include <plat/clkdev_omap.h>
+#include "clock.h"
 #include "opp.h"
 /*-------------------------------------------------------------------------
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 47ec16155483..7a7690ab6cb8 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -44,23 +44,23 @@
 #include <linux/io.h>
 #include <linux/atomic.h>
+#include <asm/fncpy.h>
 #include <asm/system_misc.h>
 #include <asm/irq.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
-#include <plat/cpu.h>
+#include <mach/tc.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/tc.h>
 #include <mach/mux.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include <plat/dmtimer.h>
 #include <mach/irqs.h>
 #include "iomap.h"
+#include "clock.h"
 #include "pm.h"
+#include "sram.h"
 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
index 7868e75ad077..3f2d39672393 100644
--- a/arch/arm/mach-omap1/pm_bus.c
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -19,8 +19,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <plat/omap_device.h>
+#include "soc.h"
-#include <plat/omap-pm.h>
 #ifdef CONFIG_PM_RUNTIME
 static int omap1_pm_runtime_suspend(struct device *dev)
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index b17709103866..5eebd7e889d0 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -4,12 +4,24 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <plat/prcm.h>
 #include <mach/hardware.h>
+#include "iomap.h"
 #include "common.h"
+/* ARM_SYSST bit shifts related to SoC reset sources */
+#define ARM_SYSST_POR_SHIFT                             5
+#define ARM_SYSST_EXT_RST_SHIFT                         4
+#define ARM_SYSST_ARM_WDRST_SHIFT                       2
+#define ARM_SYSST_GLOB_SWRST_SHIFT                      1
+/* Standardized reset source bits (across all OMAP SoCs) */
+#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT               0
+#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT               1
+#define OMAP_MPU_WD_RST_SRC_ID_SHIFT                    3
+#define OMAP_EXTWARM_RST_SRC_ID_SHIFT                   5
 void omap1_restart(char mode, const char *cmd)
 {
        /*
@@ -23,3 +35,28 @@ void omap1_restart(char mode, const char *cmd)
        omap_writew(1, ARM_RSTCT1);
 }
+/**
+ * omap1_get_reset_sources - return the source of the SoC's last reset
+ *
+ * Returns bits that represent the last reset source for the SoC.  The
+ * format is standardized across OMAPs for use by the OMAP watchdog.
+ */
+u32 omap1_get_reset_sources(void)
+{
+        u32 ret = 0;
+        u16 rs;
+        rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST));
+        if (rs & (1 << ARM_SYSST_POR_SHIFT))
+                ret |= 1 << OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT;
+        if (rs & (1 << ARM_SYSST_EXT_RST_SHIFT))
+                ret |= 1 << OMAP_EXTWARM_RST_SRC_ID_SHIFT;
+        if (rs & (1 << ARM_SYSST_ARM_WDRST_SHIFT))
+                ret |= 1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT;
+        if (rs & (1 << ARM_SYSST_GLOB_SWRST_SHIFT))
+                ret |= 1 << OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT;
+        return ret;
+}
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index b9d6834af835..d1ac08016f0b 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -23,7 +23,6 @@
 #include <asm/mach-types.h>
 #include <mach/mux.h>
-#include <plat/fpga.h>
 #include "pm.h"
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index 0e628743bd03..a908c51839a4 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -36,6 +36,8 @@
 #include <asm/assembler.h>
+#include <mach/hardware.h>
 #include "iomap.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap1/soc.h b/arch/arm/mach-omap1/soc.h
new file mode 100644
index 000000000000..69daf0187b1d
--- /dev/null
+++ b/arch/arm/mach-omap1/soc.h
@@ -0,0 +1,4 @@
+/*
+ * We can move mach/soc.h here once the drivers are fixed
+ */
+#include <mach/soc.h>
diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c
new file mode 100644
index 000000000000..6431b0f862ce
--- /dev/null
+++ b/arch/arm/mach-omap1/sram-init.c
@@ -0,0 +1,76 @@
+/*
+ * OMAP SRAM detection and management
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/fncpy.h>
+#include <asm/tlb.h>
+#include <asm/cacheflush.h>
+#include <asm/mach/map.h>
+#include "soc.h"
+#include "sram.h"
+#define OMAP1_SRAM_PA           0x20000000
+#define SRAM_BOOTLOADER_SZ      0x80
+/*
+ * The amount of SRAM depends on the core type.
+ * Note that we cannot try to test for SRAM here because writes
+ * to secure SRAM will hang the system. Also the SRAM is not
+ * yet mapped at this point.
+ */
+static void __init omap_detect_and_map_sram(void)
+{
+        unsigned long omap_sram_skip = SRAM_BOOTLOADER_SZ;
+        unsigned long omap_sram_start = OMAP1_SRAM_PA;
+        unsigned long omap_sram_size;
+        if (cpu_is_omap7xx())
+                omap_sram_size = 0x32000;       /* 200K */
+        else if (cpu_is_omap15xx())
+                omap_sram_size = 0x30000;       /* 192K */
+        else if (cpu_is_omap1610() || cpu_is_omap1611() ||
+                        cpu_is_omap1621() || cpu_is_omap1710())
+                omap_sram_size = 0x4000;        /* 16K */
+        else {
+                pr_err("Could not detect SRAM size\n");
+                omap_sram_size = 0x4000;
+        }
+        omap_map_sram(omap_sram_start, omap_sram_size,
+                omap_sram_skip, 1);
+}
+static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
+void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
+{
+        BUG_ON(!_omap_sram_reprogram_clock);
+        /* On 730, bit 13 must always be 1 */
+        if (cpu_is_omap7xx())
+                ckctl |= 0x2000;
+        _omap_sram_reprogram_clock(dpllctl, ckctl);
+}
+int __init omap_sram_init(void)
+{
+        omap_detect_and_map_sram();
+        _omap_sram_reprogram_clock =
+                        omap_sram_push(omap1_sram_reprogram_clock,
+                                        omap1_sram_reprogram_clock_sz);
+        return 0;
+}
diff --git a/arch/arm/mach-omap1/sram.h b/arch/arm/mach-omap1/sram.h
new file mode 100644
index 000000000000..d5a6c8362301
--- /dev/null
+++ b/arch/arm/mach-omap1/sram.h
@@ -0,0 +1,7 @@
+#include <plat/sram.h>
+extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
+/* Do not use these */
+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap1_sram_reprogram_clock_sz;
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index cdeb9d3ef640..bde7a35e5000 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -25,6 +25,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/dmtimer-omap.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 74529549130c..41152fadd4c0 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -50,7 +50,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <plat/dmtimer.h>
+#include <plat/counter-32k.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 84267edd9421..104fed366b8f 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -301,7 +301,7 @@ static inline void otg_device_init(struct omap_usb_config *pdata)
 #endif
-u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
+static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
 {
        u32     syscon1 = 0;
@@ -409,7 +409,7 @@ u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
        return syscon1 << 16;
 }
-u32 __init omap1_usb1_init(unsigned nwires)
+static u32 __init omap1_usb1_init(unsigned nwires)
 {
        u32     syscon1 = 0;
@@ -475,7 +475,7 @@ bad:
        return syscon1 << 20;
 }
-u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
+static u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
 {
        u32     syscon1 = 0;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d669e227e00c..be0f62bf9037 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -34,6 +34,7 @@ config ARCH_OMAP2
        select CPU_V6
        select MULTI_IRQ_HANDLER
        select SOC_HAS_OMAP2_SDRC
+        select COMMON_CLK
 config ARCH_OMAP3
        bool "TI OMAP3"
@@ -47,6 +48,7 @@ config ARCH_OMAP3
        select PM_OPP if PM
        select PM_RUNTIME if CPU_IDLE
        select SOC_HAS_OMAP2_SDRC
+        select COMMON_CLK
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
 config ARCH_OMAP4
@@ -68,6 +70,7 @@ config ARCH_OMAP4
        select PM_OPP if PM
        select PM_RUNTIME if CPU_IDLE
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
+        select COMMON_CLK
 config SOC_OMAP5
        bool "TI OMAP5"
@@ -77,6 +80,7 @@ config SOC_OMAP5
        select CPU_V7
        select HAVE_SMP
        select SOC_HAS_REALTIME_COUNTER
+        select COMMON_CLK
 comment "OMAP Core Type"
        depends on ARCH_OMAP2
@@ -111,6 +115,7 @@ config SOC_AM33XX
        select ARM_CPU_SUSPEND if PM
        select CPU_V7
        select MULTI_IRQ_HANDLER
+        select COMMON_CLK
 config OMAP_PACKAGE_ZAF
       bool
@@ -270,14 +275,14 @@ config MACH_NOKIA_N8X0
        select OMAP_PACKAGE_ZAC
 config MACH_NOKIA_RM680
-        bool "Nokia RM-680/696 board"
+        bool "Nokia N950 (RM-680) / N9 (RM-696) phones"
        depends on ARCH_OMAP3
        default y
        select MACH_NOKIA_RM696
        select OMAP_PACKAGE_CBB
 config MACH_NOKIA_RX51
-        bool "Nokia RX-51 board"
+        bool "Nokia N900 (RX-51) phone"
        depends on ARCH_OMAP3
        default y
        select OMAP_PACKAGE_CBB
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fe40d9e488c9..a8004f33b7e2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,30 +4,37 @@
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
+         omap_device.o sram.o
-# INTCPS IP block support - XXX should be moved to drivers/
-obj-$(CONFIG_ARCH_OMAP2)                += irq.o
+omap-2-3-common                         = irq.o
-obj-$(CONFIG_ARCH_OMAP3)                += irq.o
+hwmod-common                            = omap_hwmod.o \
-obj-$(CONFIG_SOC_AM33XX)                += irq.o
+                                          omap_hwmod_common_data.o
+clock-common                            = clock.o clock_common_data.o \
-# Secure monitor API support
+                                          clkt_dpll.o clkt_clksel.o
-obj-$(CONFIG_ARCH_OMAP3)                += omap-smc.o omap-secure.o
+secure-common                           = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap-smc.o omap-secure.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-smc.o omap-secure.o
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
+obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
 endif
-obj-$(CONFIG_TWL4030_CORE)              += omap_twl.o
+obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 # SMP support ONLY available for OMAP4
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
+omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
-obj-$(CONFIG_SOC_OMAP5)                 += omap4-common.o omap-wakeupgen.o
+                                           sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common)
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common)
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -43,6 +50,11 @@ AFLAGS_sram242x.o			:=-Wa,-march=armv6
 AFLAGS_sram243x.o                       :=-Wa,-march=armv6
 AFLAGS_sram34xx.o                       :=-Wa,-march=armv7-a
+# Restart code (OMAP4/5 currently in omap4-common.c)
+obj-$(CONFIG_SOC_OMAP2420)              += omap2-restart.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap2-restart.o
+obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
 # Pin multiplexing
 obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
 obj-$(CONFIG_SOC_OMAP2430)              += mux2430.o
@@ -52,7 +64,6 @@ obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
-obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 # OPP table initialization
 ifeq ($(CONFIG_PM_OPP),y)
@@ -62,16 +73,18 @@ obj-$(CONFIG_ARCH_OMAP4)		+= opp4xxx_data.o
 endif
 # Power Management
+obj-$(CONFIG_OMAP_PM_NOOP)              += omap-pm-noop.o
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o sleep44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)     += smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
@@ -83,76 +96,82 @@ endif
 endif
 ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 endif
 # PRCM
-obj-y                                   += prcm.o prm_common.o
+obj-y                                   += prm_common.o cm_common.o
-obj-$(CONFIG_ARCH_OMAP2)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
-obj-$(CONFIG_ARCH_OMAP3)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
 omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
                                           prcm_mpu44xx.o prminst44xx.o \
-                                           vc44xx_data.o vp44xx_data.o \
+                                           vc44xx_data.o vp44xx_data.o
-                                           prm44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 # OMAP voltage domains
-obj-y                                   += voltage.o vc.o vp.o
+voltagedomain-common                    := voltage.o vc.o vp.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += voltagedomains2xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
 # OMAP powerdomain framework
-obj-y                                   += powerdomain.o powerdomain-common.o
+powerdomain-common                      += powerdomain.o powerdomain-common.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP2)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += powerdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += powerdomain44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 # PRCM clockdomain control
-obj-y                                   += clockdomain.o
+clockdomain-common                      += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clockdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += clockdomain44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 # Clock framework
-obj-y                                   += clock.o clock_common_data.o \
+obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
-                                           clkt_dpll.o clkt_clksel.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_sys.o
-obj-$(CONFIG_ARCH_OMAP2)                += clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o clkt2xxx_sys.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_virt_prcm_set.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_apll.o clkt2xxx_osc.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpll.o clkt_iclk.o
-obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += cclock2420_data.o
-obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o cclock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clkt34xx_dpll3m2.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o clkt_iclk.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o clock3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o cclock3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += clock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) cclock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
-obj-$(CONFIG_SOC_AM33XX)                += dpll3xxx.o clock33xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
+obj-$(CONFIG_SOC_AM33XX)                += cclock33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
 # OMAP2 clock rate set data (old "OPP" data)
@@ -160,7 +179,6 @@ obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 # hwmod data
-obj-y                                   += omap_hwmod_common_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_interconnect_data.o
@@ -184,8 +202,6 @@ obj-$(CONFIG_HW_PERF_EVENTS)		+= pmu.o
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
-obj-$(CONFIG_OMAP_IOMMU)                += iommu2.o
 iommu-$(CONFIG_OMAP_IOMMU)              := omap-iommu.o
 obj-y                                   += $(iommu-m) $(iommu-y)
@@ -206,10 +222,10 @@ obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o
 obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
 obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
@@ -279,4 +295,4 @@ endif
 emac-$(CONFIG_TI_DAVINCI_EMAC)          := am35xx-emac.o
 obj-y                                   += $(emac-m) $(emac-y)
-obj-y                                   += common-board-devices.o twl-common.o
+obj-y                                   += common-board-devices.o twl-common.o dss-common.o
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 06c19bb7bca6..43296c1af9ee 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -21,5 +21,6 @@
 #define AM33XX_SCM_BASE         0x44E10000
 #define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
 #define AM33XX_PRCM_BASE        0x44E00000
+#define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + 0x3FC)
 #endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index d0c54c573d34..af11dcdb7e2c 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/davinci_emac.h>
 #include <asm/system.h>
-#include <plat/omap_device.h>
+#include "omap_device.h"
 #include "am35xx.h"
 #include "control.h"
 #include "am35xx-emac.h"
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 95b384d54f8a..4815ea6f8f5d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -28,14 +28,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
-#include <plat/usb.h>
 #include "gpmc-smc91x.h"
 #include <video/omapdss.h>
@@ -287,5 +285,5 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
        .init_machine   = omap_2430sdp_init,
        .init_late      = omap2430_init_late,
        .timer          = &omap2_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 96cd3693e1ae..7b201546834d 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -30,15 +30,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/usb.h>
 #include "common.h"
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
-#include <plat/gpmc.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
+#include "gpmc.h"
 #include "gpmc-smc91x.h"
+#include "soc.h"
 #include "board-flash.h"
 #include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
@@ -597,5 +597,5 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
        .init_machine   = omap_3430sdp_init,
        .init_late      = omap3430_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index fc224ad86747..050aaa771254 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -18,9 +18,8 @@
 #include "common.h"
 #include "gpmc-smc91x.h"
-#include <plat/usb.h>
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 #include "board-flash.h"
 #include "mux.h"
@@ -213,5 +212,5 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
        .init_machine   = omap_sdp_init,
        .init_late      = omap3630_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 3669c120c7e8..1cc6696594fd 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -27,6 +27,7 @@
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
 #include <linux/platform_data/omap4-keypad.h>
+#include <linux/usb/musb.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -34,31 +35,23 @@
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/usb.h>
-#include <plat/mmc.h>
 #include "omap4-keypad.h"
-#include <video/omapdss.h>
-#include <video/omap-panel-nokia-dsi.h>
-#include <video/omap-panel-picodlp.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 #include "soc.h"
 #include "mux.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
+#include "dss-common.h"
 #define ETH_KS8851_IRQ                  34
 #define ETH_KS8851_POWER_ON             48
 #define ETH_KS8851_QUART                138
 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
 #define OMAP4_SFH7741_ENABLE_GPIO               188
-#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
-#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
-#define HDMI_GPIO_HPD  63 /* Hotplug detect */
-#define DISPLAY_SEL_GPIO        59      /* LCD2/PicoDLP switch */
-#define DLP_POWER_ON_GPIO       40
 #define GPIO_WIFI_PMENA         54
 #define GPIO_WIFI_IRQ           53
@@ -607,154 +600,6 @@ static void __init omap_sfh7741prox_init(void)
                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
 }
-static struct nokia_dsi_panel_data dsi1_panel = {
-                .name           = "taal",
-                .reset_gpio     = 102,
-                .use_ext_te     = false,
-                .ext_te_gpio    = 101,
-                .esd_interval   = 0,
-                .pin_config = {
-                        .num_pins       = 6,
-                        .pins           = { 0, 1, 2, 3, 4, 5 },
-                },
-};
-static struct omap_dss_device sdp4430_lcd_device = {
-        .name                   = "lcd",
-        .driver_name            = "taal",
-        .type                   = OMAP_DISPLAY_TYPE_DSI,
-        .data                   = &dsi1_panel,
-        .phy.dsi                = {
-                .module         = 0,
-        },
-        .channel                = OMAP_DSS_CHANNEL_LCD,
-};
-static struct nokia_dsi_panel_data dsi2_panel = {
-                .name           = "taal",
-                .reset_gpio     = 104,
-                .use_ext_te     = false,
-                .ext_te_gpio    = 103,
-                .esd_interval   = 0,
-                .pin_config = {
-                        .num_pins       = 6,
-                        .pins           = { 0, 1, 2, 3, 4, 5 },
-                },
-};
-static struct omap_dss_device sdp4430_lcd2_device = {
-        .name                   = "lcd2",
-        .driver_name            = "taal",
-        .type                   = OMAP_DISPLAY_TYPE_DSI,
-        .data                   = &dsi2_panel,
-        .phy.dsi                = {
-                .module         = 1,
-        },
-        .channel                = OMAP_DSS_CHANNEL_LCD2,
-};
-static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
-        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
-        .ls_oe_gpio = HDMI_GPIO_LS_OE,
-        .hpd_gpio = HDMI_GPIO_HPD,
-};
-static struct omap_dss_device sdp4430_hdmi_device = {
-        .name = "hdmi",
-        .driver_name = "hdmi_panel",
-        .type = OMAP_DISPLAY_TYPE_HDMI,
-        .channel = OMAP_DSS_CHANNEL_DIGIT,
-        .data = &sdp4430_hdmi_data,
-};
-static struct picodlp_panel_data sdp4430_picodlp_pdata = {
-        .picodlp_adapter_id     = 2,
-        .emu_done_gpio          = 44,
-        .pwrgood_gpio           = 45,
-};
-static void sdp4430_picodlp_init(void)
-{
-        int r;
-        const struct gpio picodlp_gpios[] = {
-                {DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
-                        "DLP POWER ON"},
-                {sdp4430_picodlp_pdata.emu_done_gpio, GPIOF_IN,
-                        "DLP EMU DONE"},
-                {sdp4430_picodlp_pdata.pwrgood_gpio, GPIOF_OUT_INIT_LOW,
-                        "DLP PWRGOOD"},
-        };
-        r = gpio_request_array(picodlp_gpios, ARRAY_SIZE(picodlp_gpios));
-        if (r)
-                pr_err("Cannot request PicoDLP GPIOs, error %d\n", r);
-}
-static int sdp4430_panel_enable_picodlp(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(DISPLAY_SEL_GPIO, 0);
-        gpio_set_value(DLP_POWER_ON_GPIO, 1);
-        return 0;
-}
-static void sdp4430_panel_disable_picodlp(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(DLP_POWER_ON_GPIO, 0);
-        gpio_set_value(DISPLAY_SEL_GPIO, 1);
-}
-static struct omap_dss_device sdp4430_picodlp_device = {
-        .name                   = "picodlp",
-        .driver_name            = "picodlp_panel",
-        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .phy.dpi.data_lines     = 24,
-        .channel                = OMAP_DSS_CHANNEL_LCD2,
-        .platform_enable        = sdp4430_panel_enable_picodlp,
-        .platform_disable       = sdp4430_panel_disable_picodlp,
-        .data                   = &sdp4430_picodlp_pdata,
-};
-static struct omap_dss_device *sdp4430_dss_devices[] = {
-        &sdp4430_lcd_device,
-        &sdp4430_lcd2_device,
-        &sdp4430_hdmi_device,
-        &sdp4430_picodlp_device,
-};
-static struct omap_dss_board_info sdp4430_dss_data = {
-        .num_devices    = ARRAY_SIZE(sdp4430_dss_devices),
-        .devices        = sdp4430_dss_devices,
-        .default_device = &sdp4430_lcd_device,
-};
-static void __init omap_4430sdp_display_init(void)
-{
-        int r;
-        /* Enable LCD2 by default (instead of Pico DLP) */
-        r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
-                        "display_sel");
-        if (r)
-                pr_err("%s: Could not get display_sel GPIO\n", __func__);
-        sdp4430_picodlp_init();
-        omap_display_init(&sdp4430_dss_data);
-        /*
-         * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
-         * later have external pull up on the HDMI I2C lines
-         */
-        if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
-                omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
-        else
-                omap_hdmi_init(0);
-        omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
-}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
@@ -881,5 +726,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        .init_machine   = omap_4430sdp_init,
        .init_late      = omap4430_init_late,
        .timer          = &omap4_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap44xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 318feadb1d6e..51b96a1206d1 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/usb.h>
 #include "am35xx-emac.h"
 #include "mux.h"
@@ -94,5 +93,5 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
        .init_machine   = am3517_crane_init,
        .init_late      = am35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index e16289755f2e..4be58fd071f6 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -25,6 +25,7 @@
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
+#include <linux/usb/musb.h>
 #include <linux/platform_data/gpio-omap.h>
 #include "am35xx.h"
@@ -33,7 +34,6 @@
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
@@ -393,5 +393,5 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
        .init_machine   = am3517_evm_init,
        .init_late      = am35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index cea3abace815..5d0a61f54165 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -28,14 +28,14 @@
 #include <linux/clk.h>
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/leds-omap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
-#include <plat/led.h>
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -338,5 +338,5 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
        .init_machine   = omap_apollon_init,
        .init_late      = omap2420_init_late,
        .timer          = &omap2_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 376d26eb601c..c8e37dc00892 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -38,21 +38,19 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "common.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/gpmc.h>
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
-#include <mach/hardware.h>
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "gpmc.h"
+#include "gpmc-nand.h"
 #define CM_T35_GPIO_PENDOWN             57
 #define SB_T35_USB_HUB_RESET_GPIO       167
@@ -181,7 +179,7 @@ static struct omap_nand_platform_data cm_t35_nand_data = {
 static void __init cm_t35_init_nand(void)
 {
-        if (gpmc_nand_init(&cm_t35_nand_data) < 0)
+        if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
                pr_err("CM-T35: Unable to register NAND device\n");
 }
 #else
@@ -753,18 +751,18 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
        .init_machine   = cm_t35_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
 MACHINE_START(CM_T3730, "Compulab CM-T3730")
-        .atag_offset    = 0x100,
+        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
+        .reserve        = omap_reserve,
-        .map_io         = omap3_map_io,
+        .map_io         = omap3_map_io,
-        .init_early     = omap3630_init_early,
+        .init_early     = omap3630_init_early,
-        .init_irq       = omap3_init_irq,
+        .init_irq       = omap3_init_irq,
        .handle_irq     = omap3_intc_handle_irq,
-        .init_machine   = cm_t3730_init,
+        .init_machine   = cm_t3730_init,
        .init_late     = omap3630_init_late,
-        .timer          = &omap3_timer,
+        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 59c0a45f75b0..ebbc2adb499e 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -39,9 +39,8 @@
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/usb.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "am35xx.h"
@@ -49,6 +48,7 @@
 #include "control.h"
 #include "common-board-devices.h"
 #include "am35xx-emac.h"
+#include "gpmc-nand.h"
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 static struct gpio_led cm_t3517_leds[] = {
@@ -240,7 +240,7 @@ static struct omap_nand_platform_data cm_t3517_nand_data = {
 static void __init cm_t3517_init_nand(void)
 {
-        if (gpmc_nand_init(&cm_t3517_nand_data) < 0)
+        if (gpmc_nand_init(&cm_t3517_nand_data, NULL) < 0)
                pr_err("CM-T3517: NAND initialization failed\n");
 }
 #else
@@ -297,6 +297,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3517_init,
        .init_late      = am35xx_init_late,
-        .timer          = &omap3_timer,
+        .timer          = &omap3_gp_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 1fd161e934c7..7667eb749522 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -39,9 +39,8 @@
 #include <asm/mach/flash.h>
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
@@ -55,8 +54,11 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
+#define NAND_CS                 0
 #define OMAP_DM9000_GPIO_IRQ    25
 #define OMAP3_DEVKIT_TS_GPIO    27
@@ -621,8 +623,9 @@ static void __init devkit8000_init(void)
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
+        board_nand_init(devkit8000_nand_partitions,
-                             ARRAY_SIZE(devkit8000_nand_partitions));
+                        ARRAY_SIZE(devkit8000_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
        omap_twl4030_audio_init("omap3beagle");
        /* Ensure SDRC pins are mux'd for self-refresh */
@@ -640,5 +643,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
        .init_machine   = devkit8000_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_secure_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index e642acf9cad0..c33adea0247c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -17,14 +17,14 @@
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
-#include <plat/cpu.h>
-#include <plat/gpmc.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
-#include <plat/tc.h>
+#include "soc.h"
 #include "common.h"
 #include "board-flash.h"
+#include "gpmc-onenand.h"
+#include "gpmc-nand.h"
 #define REG_FPGA_REV                    0x10
 #define REG_FPGA_DIP_SWITCH_INPUT2      0x60
@@ -104,36 +104,35 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
                defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 /* Note that all values in this struct are in nanoseconds */
-static struct gpmc_timings nand_timings = {
+struct gpmc_timings nand_default_timings[1] = {
+        {
+                .sync_clk = 0,
-        .sync_clk = 0,
+                .cs_on = 0,
+                .cs_rd_off = 36,
+                .cs_wr_off = 36,
-        .cs_on = 0,
+                .adv_on = 6,
-        .cs_rd_off = 36,
+                .adv_rd_off = 24,
-        .cs_wr_off = 36,
+                .adv_wr_off = 36,
-        .adv_on = 6,
+                .we_off = 30,
-        .adv_rd_off = 24,
+                .oe_off = 48,
-        .adv_wr_off = 36,
-        .we_off = 30,
+                .access = 54,
-        .oe_off = 48,
+                .rd_cycle = 72,
+                .wr_cycle = 72,
-        .access = 54,
+                .wr_access = 30,
-        .rd_cycle = 72,
+                .wr_data_mux_bus = 0,
-        .wr_cycle = 72,
+        },
-        .wr_access = 30,
-        .wr_data_mux_bus = 0,
 };
-static struct omap_nand_platform_data board_nand_data = {
+static struct omap_nand_platform_data board_nand_data;
-        .gpmc_t         = &nand_timings,
-};
 void
-__init board_nand_init(struct mtd_partition *nand_parts,
+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
-                        u8 nr_parts, u8 cs, int nand_type)
+                                int nand_type, struct gpmc_timings *gpmc_t)
 {
        board_nand_data.cs              = cs;
        board_nand_data.parts           = nand_parts;
@@ -141,7 +140,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
        board_nand_data.devsize         = nand_type;
        board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-        gpmc_nand_init(&board_nand_data);
+        gpmc_nand_init(&board_nand_data, gpmc_t);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -238,5 +237,6 @@ void __init board_flash_init(struct flash_partitions partition_info[],
                pr_err("NAND: Unable to find configuration in GPMC\n");
        else
                board_nand_init(partition_info[2].parts,
-                        partition_info[2].nr_parts, nandcs, nand_type);
+                        partition_info[2].nr_parts, nandcs,
+                        nand_type, nand_default_timings);
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index c44b70d52021..2fb5d41a9fae 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -12,7 +12,7 @@
 */
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #define PDC_NOR         1
 #define PDC_NAND        2
@@ -40,12 +40,14 @@ static inline void board_flash_init(struct flash_partitions part[],
 #if defined(CONFIG_MTD_NAND_OMAP2) || \
                defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 extern void board_nand_init(struct mtd_partition *nand_parts,
-                                        u8 nr_parts, u8 cs, int nand_type);
+                u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
+extern struct gpmc_timings nand_default_timings[];
 #else
 static inline void board_nand_init(struct mtd_partition *nand_parts,
-                                        u8 nr_parts, u8 cs, int nand_type)
+                u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
 {
 }
+#define nand_default_timings    NULL
 #endif
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 601ecdfb1cf9..53cb380b7877 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -21,6 +21,7 @@
 #include "common.h"
 #include "common-board-devices.h"
+#include "dss-common.h"
 #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
 #define intc_of_init    NULL
@@ -40,6 +41,15 @@ static void __init omap_generic_init(void)
        omap_sdrc_init(NULL, NULL);
        of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
+        /*
+         * HACK: call display setup code for selected boards to enable omapdss.
+         * This will be removed when omapdss supports DT.
+         */
+        if (of_machine_is_compatible("ti,omap4-panda"))
+                omap4_panda_display_init_of();
+        else if (of_machine_is_compatible("ti,omap4-sdp"))
+                omap_4430sdp_display_init_of();
 }
 #ifdef CONFIG_SOC_OMAP2420
@@ -57,7 +67,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
        .init_machine   = omap_generic_init,
        .timer          = &omap2_timer,
        .dt_compat      = omap242x_boards_compat,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
 #endif
@@ -76,7 +86,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
        .init_machine   = omap_generic_init,
        .timer          = &omap2_timer,
        .dt_compat      = omap243x_boards_compat,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
 #endif
@@ -95,7 +105,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
        .init_machine   = omap_generic_init,
        .timer          = &omap3_timer,
        .dt_compat      = omap3_boards_compat,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
+MACHINE_END
+static const char *omap3_gp_boards_compat[] __initdata = {
+        "ti,omap3-beagle",
+        NULL,
+};
+DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3430_init_early,
+        .init_irq       = omap_intc_of_init,
+        .handle_irq     = omap3_intc_handle_irq,
+        .init_machine   = omap_generic_init,
+        .timer          = &omap3_secure_timer,
+        .dt_compat      = omap3_gp_boards_compat,
+        .restart        = omap3xxx_restart,
 MACHINE_END
 #endif
@@ -134,7 +161,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
        .init_late      = omap4430_init_late,
        .timer          = &omap4_timer,
        .dt_compat      = omap4_boards_compat,
-        .restart        = omap_prcm_restart,
+        .restart        = omap44xx_restart,
 MACHINE_END
 #endif
@@ -154,6 +181,6 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
        .init_machine   = omap_generic_init,
        .timer          = &omap5_timer,
        .dt_compat      = omap5_boards_compat,
-        .restart        = omap_prcm_restart,
+        .restart        = omap44xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8d04bf851af4..9a3878ec2256 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -26,15 +26,14 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/mfd/menelaus.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/menelaus.h>
+#include <linux/omap-dma.h>
-#include <plat/dma.h>
+#include <plat/debug-devices.h>
-#include <plat/gpmc.h>
-#include "debug-devices.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -42,6 +41,7 @@
 #include "common.h"
 #include "mux.h"
 #include "control.h"
+#include "gpmc.h"
 #define H4_FLASH_CS     0
 #define H4_SMC91X_CS    1
@@ -386,5 +386,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
        .init_machine   = omap_h4_init,
        .init_late      = omap2420_init_late,
        .timer          = &omap2_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 378590694447..0f24cb84ba5a 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -29,20 +29,19 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include "common.h"
-#include <plat/gpmc.h>
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+#include "common.h"
+#include "gpmc.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
 #include "common-board-devices.h"
 #include "board-flash.h"
 #include "control.h"
+#include "gpmc-onenand.h"
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -175,7 +174,7 @@ static void __init igep_flash_init(void)
                pr_info("IGEP: initializing NAND memory device\n");
                board_nand_init(igep_flash_partitions,
                                ARRAY_SIZE(igep_flash_partitions),
-                                0, NAND_BUSWIDTH_16);
+                                0, NAND_BUSWIDTH_16, nand_default_timings);
        } else if (mux == IGEP_SYSBOOT_ONENAND) {
                pr_info("IGEP: initializing OneNAND memory device\n");
                board_onenand_init(igep_flash_partitions,
@@ -657,7 +656,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
        .init_machine   = igep_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
 MACHINE_START(IGEP0030, "IGEP OMAP3 module")
@@ -670,5 +669,5 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
        .init_machine   = igep_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ee8c3cfb95b3..0869f4f3d3e1 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -35,9 +35,8 @@
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/gpmc.h>
+#include "board-zoom.h"
-#include <mach/board-zoom.h>
+#include "gpmc.h"
-#include <plat/usb.h>
 #include "gpmc-smsc911x.h"
 #include <video/omapdss.h>
@@ -420,8 +419,8 @@ static void __init omap_ldp_init(void)
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
        usb_musb_init(NULL);
-        board_nand_init(ldp_nand_partitions,
+        board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
-                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+                        ZOOM_NAND_CS, 0, nand_default_timings);
        omap_hsmmc_init(mmc);
        ldp_display_init();
@@ -437,5 +436,5 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
        .init_machine   = omap_ldp_init,
        .init_late      = omap3430_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index d95f727ca39a..a4e167c55c1d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -22,16 +22,17 @@
 #include <linux/usb/musb.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+#include <linux/mfd/menelaus.h>
 #include <sound/tlv320aic3x.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include "common.h"
-#include <plat/menelaus.h>
+#include "mmc.h"
-#include <plat/mmc.h>
 #include "mux.h"
+#include "gpmc-onenand.h"
 #define TUSB6010_ASYNC_CS       1
 #define TUSB6010_SYNC_CS        4
@@ -689,7 +690,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
        .init_machine   = n8x0_init_machine,
        .init_late      = omap2420_init_late,
        .timer          = &omap2_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
 MACHINE_START(NOKIA_N810, "Nokia N810")
@@ -702,7 +703,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
        .init_machine   = n8x0_init_machine,
        .init_late      = omap2420_init_late,
        .timer          = &omap2_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
@@ -715,5 +716,5 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .init_machine   = n8x0_init_machine,
        .init_late      = omap2420_init_late,
        .timer          = &omap2_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap2xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index d41ab98890ff..22c483d5dfa8 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -39,19 +39,22 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/gpmc.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
-#include <plat/omap_device.h>
+#include "common.h"
+#include "omap_device.h"
+#include "gpmc.h"
+#include "soc.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
+#define NAND_CS 0
 /*
 * OMAP3 Beagle revision
 * Run time detection of Beagle revision is done by reading GPIO.
@@ -518,8 +521,9 @@ static void __init omap3_beagle_init(void)
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
+        board_nand_init(omap3beagle_nand_partitions,
-                             ARRAY_SIZE(omap3beagle_nand_partitions));
+                        ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
        omap_twl4030_audio_init("omap3beagle");
        /* Ensure msecure is mux'd to be able to set the RTC. */
@@ -541,5 +545,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
        .init_machine   = omap3_beagle_init,
        .init_late      = omap3_init_late,
        .timer          = &omap3_secure_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b9b776b6c954..54647d6286b4 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -32,6 +32,7 @@
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/musb.h>
 #include <linux/usb/nop-usb-xceiv.h>
 #include <linux/smsc911x.h>
@@ -45,17 +46,20 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/usb.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include "common.h"
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
+#include "soc.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+#define NAND_CS                 0
 #define OMAP3_EVM_TS_GPIO       175
 #define OMAP3_EVM_EHCI_VBUS     22
@@ -731,8 +735,9 @@ static void __init omap3_evm_init(void)
        }
        usb_musb_init(&musb_board_data);
        usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
+        board_nand_init(omap3evm_nand_partitions,
-                             ARRAY_SIZE(omap3evm_nand_partitions));
+                        ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
        omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
        omap3evm_init_smsc911x();
@@ -752,5 +757,5 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
        .init_machine   = omap3_evm_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 7bd8253b5d1d..2a065ba6eb58 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -34,16 +34,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "gpmc-smsc911x.h"
-#include <plat/gpmc.h>
-#include <plat/sdrc.h>
-#include <plat/usb.h>
 #include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
+#include "gpmc.h"
+#include "gpmc-smsc911x.h"
 #define OMAP3LOGIC_SMSC911X_CS                  1
@@ -235,7 +232,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
        .init_machine   = omap3logic_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
@@ -248,5 +245,5 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
        .init_machine   = omap3logic_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 00a1f4ae6e44..a53a6683c1b8 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -42,7 +42,6 @@
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
@@ -50,6 +49,7 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "gpmc-nand.h"
 #define PANDORA_WIFI_IRQ_GPIO           21
 #define PANDORA_WIFI_NRESET_GPIO        23
@@ -602,7 +602,7 @@ static void __init omap3pandora_init(void)
        omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
        usbhs_init(&usbhs_bdata);
        usb_musb_init(NULL);
-        gpmc_nand_init(&pandora_nand_data);
+        gpmc_nand_init(&pandora_nand_data, NULL);
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -619,5 +619,5 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
        .init_machine   = omap3pandora_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 731235eb319e..d8638b3b4f94 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -40,9 +40,8 @@
 #include <asm/mach/flash.h>
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
@@ -428,5 +427,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
        .init_machine           = omap3_stalker_init,
        .init_late              = omap35xx_init_late,
        .timer                  = &omap3_secure_timer,
-        .restart                = omap_prcm_restart,
+        .restart                = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 944ffc436577..263cb9cfbf37 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -44,12 +44,12 @@
 #include <asm/system_info.h>
 #include "common.h"
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/usb.h>
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 #include <asm/setup.h>
@@ -59,6 +59,8 @@
 #define TB_BL_PWM_TIMER         9
 #define TB_KILL_POWER_GPIO      168
+#define NAND_CS                 0
 static unsigned long touchbook_revision;
 static struct mtd_partition omap3touchbook_nand_partitions[] = {
@@ -365,8 +367,9 @@ static void __init omap3_touchbook_init(void)
        omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
-        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
+        board_nand_init(omap3touchbook_nand_partitions,
-                             ARRAY_SIZE(omap3touchbook_nand_partitions));
+                        ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
+                        NAND_BUSWIDTH_16, NULL);
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -384,5 +387,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
        .init_machine   = omap3_touchbook_init,
        .init_late      = omap3430_init_late,
        .timer          = &omap3_secure_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index bfcd397e233c..5c8e9cee2c2e 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -29,6 +29,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/ti_wilink_st.h>
+#include <linux/usb/musb.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
@@ -36,26 +37,20 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <video/omapdss.h>
 #include "common.h"
-#include <plat/usb.h>
-#include <plat/mmc.h>
-#include <video/omap-panel-tfp410.h>
 #include "soc.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "mux.h"
 #include "common-board-devices.h"
+#include "dss-common.h"
 #define GPIO_HUB_POWER          1
 #define GPIO_HUB_NRESET         62
 #define GPIO_WIFI_PMENA         43
 #define GPIO_WIFI_IRQ           53
-#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
-#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
-#define HDMI_GPIO_HPD  63 /* Hotplug detect */
 /* wl127x BT, FM, GPS connectivity chip */
 static struct ti_st_plat_data wilink_platform_data = {
@@ -409,68 +404,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 #define board_mux       NULL
 #endif
-/* Display DVI */
-#define PANDA_DVI_TFP410_POWER_DOWN_GPIO        0
-/* Using generic display panel */
-static struct tfp410_platform_data omap4_dvi_panel = {
-        .i2c_bus_num            = 3,
-        .power_down_gpio        = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
-};
-static struct omap_dss_device omap4_panda_dvi_device = {
-        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .name                   = "dvi",
-        .driver_name            = "tfp410",
-        .data                   = &omap4_dvi_panel,
-        .phy.dpi.data_lines     = 24,
-        .reset_gpio             = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
-        .channel                = OMAP_DSS_CHANNEL_LCD2,
-};
-static struct omap_dss_hdmi_data omap4_panda_hdmi_data = {
-        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
-        .ls_oe_gpio = HDMI_GPIO_LS_OE,
-        .hpd_gpio = HDMI_GPIO_HPD,
-};
-static struct omap_dss_device  omap4_panda_hdmi_device = {
-        .name = "hdmi",
-        .driver_name = "hdmi_panel",
-        .type = OMAP_DISPLAY_TYPE_HDMI,
-        .channel = OMAP_DSS_CHANNEL_DIGIT,
-        .data = &omap4_panda_hdmi_data,
-};
-static struct omap_dss_device *omap4_panda_dss_devices[] = {
-        &omap4_panda_dvi_device,
-        &omap4_panda_hdmi_device,
-};
-static struct omap_dss_board_info omap4_panda_dss_data = {
-        .num_devices    = ARRAY_SIZE(omap4_panda_dss_devices),
-        .devices        = omap4_panda_dss_devices,
-        .default_device = &omap4_panda_dvi_device,
-};
-static void __init omap4_panda_display_init(void)
-{
-        omap_display_init(&omap4_panda_dss_data);
-        /*
-         * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
-         * later have external pull up on the HDMI I2C lines
-         */
-        if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
-                omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
-        else
-                omap_hdmi_init(0);
-        omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
-}
 static void omap4_panda_init_rev(void)
 {
@@ -524,5 +457,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
        .init_machine   = omap4_panda_init,
        .init_late      = omap4430_init_late,
        .timer          = &omap4_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap44xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index b700685762b5..c8fde3e56441 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -45,18 +45,20 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/gpmc.h>
-#include <plat/usb.h>
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
+#include "gpmc.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
+#define NAND_CS                 0
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
 #define OVERO_GPIO_PENDOWN      114
@@ -495,8 +497,8 @@ static void __init overo_init(void)
        omap_serial_init();
        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
                                  mt46h32m32lf6_sdrc_params);
-        omap_nand_flash_init(0, overo_nand_partitions,
+        board_nand_init(overo_nand_partitions,
-                             ARRAY_SIZE(overo_nand_partitions));
+                        ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
        usb_musb_init(NULL);
        usbhs_init(&usbhs_bdata);
        overo_spi_init();
@@ -550,5 +552,5 @@ MACHINE_START(OVERO, "Gumstix Overo")
        .init_machine   = overo_init,
        .init_late      = omap35xx_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 45997bfbcbd2..0c777b75e484 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -1,5 +1,5 @@
 /*
- * Board support file for Nokia RM-680/696.
+ * Board support file for Nokia N950 (RM-680) / N9 (RM-696).
 *
 * Copyright (C) 2010 Nokia
 *
@@ -22,17 +22,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-#include <plat/i2c.h>
-#include <plat/mmc.h>
-#include <plat/usb.h>
-#include <plat/gpmc.h>
 #include "common.h"
-#include <plat/serial.h>
 #include "mux.h"
+#include "gpmc.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "sdram-nokia.h"
 #include "common-board-devices.h"
+#include "gpmc-onenand.h"
 static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
@@ -151,7 +148,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
        .init_machine   = rm680_init,
        .init_late      = omap3630_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
 MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
@@ -164,5 +161,5 @@ MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
        .init_machine   = rm680_init,
        .init_late      = omap3630_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 020e03c95bfe..60529e0b3d67 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -31,9 +31,7 @@
 #include <asm/system_info.h>
 #include "common.h"
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
-#include <plat/gpmc.h>
-#include <plat/omap-pm.h>
 #include "gpmc-smc91x.h"
 #include "board-rx51.h"
@@ -52,8 +50,11 @@
 #endif
 #include "mux.h"
+#include "omap-pm.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "gpmc.h"
+#include "gpmc-onenand.h"
 #define SYSTEM_REV_B_USES_VAUX3 0x1699
 #define SYSTEM_REV_S_USES_VAUX3 0x8
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 7bbb05d9689b..f1d6efe079ca 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-omap2/board-rx51.c
+ * Board support file for Nokia N900 (aka RX-51).
 *
 * Copyright (C) 2007, 2008 Nokia
 *
@@ -17,18 +17,18 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/usb/musb.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "common.h"
+#include <linux/omap-dma.h>
-#include <plat/dma.h>
-#include <plat/gpmc.h>
-#include <plat/usb.h>
+#include "common.h"
 #include "mux.h"
+#include "gpmc.h"
 #include "pm.h"
 #include "sdram-nokia.h"
@@ -127,5 +127,5 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
        .init_machine   = rx51_init,
        .init_late      = omap3430_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index c4f8833b4c3c..1a3e056d63a7 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -14,13 +14,14 @@
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/usb/musb.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/usb.h>
 static struct omap_musb_board_data musb_board_data = {
        .set_phy_power  = ti81xx_musb_phy_power,
@@ -45,7 +46,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
        .timer          = &omap3_timer,
        .init_machine   = ti81xx_evm_init,
        .init_late      = ti81xx_init_late,
-        .restart        = omap_prcm_restart,
+        .restart        = omap44xx_restart,
 MACHINE_END
 MACHINE_START(TI8148EVM, "ti8148evm")
@@ -57,5 +58,5 @@ MACHINE_START(TI8148EVM, "ti8148evm")
        .timer          = &omap3_timer,
        .init_machine   = ti81xx_evm_init,
        .init_late      = ti81xx_init_late,
-        .restart        = omap_prcm_restart,
+        .restart        = omap44xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index afb2278a29f6..42e5f231a799 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -17,10 +17,10 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "gpmc-smsc911x.h"
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 #include "soc.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index b940ab2259fb..1c7c834a5b5f 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,8 +16,9 @@
 #include <linux/spi/spi.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
+#include "soc.h"
 #include "common.h"
 #define LCD_PANEL_RESET_GPIO_PROD       96
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c166fe1fdff9..26e07addc9d7 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -26,9 +26,8 @@
 #include <asm/mach/map.h>
 #include "common.h"
-#include <plat/usb.h>
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 #include "mux.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4994438e1f46..d7fa31e67238 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -22,9 +22,8 @@
 #include <asm/mach/arch.h>
 #include "common.h"
-#include <plat/usb.h>
-#include <mach/board-zoom.h>
+#include "board-zoom.h"
 #include "board-flash.h"
 #include "mux.h"
@@ -113,8 +112,9 @@ static void __init omap_zoom_init(void)
                usbhs_init(&usbhs_bdata);
        }
-        board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
+        board_nand_init(zoom_nand_partitions,
-                                                ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
+                        NAND_BUSWIDTH_16, nand_default_timings);
        zoom_debugboard_init();
        zoom_peripherals_init();
@@ -138,7 +138,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
        .init_machine   = omap_zoom_init,
        .init_late      = omap3430_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
 MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
@@ -151,5 +151,5 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .init_machine   = omap_zoom_init,
        .init_late      = omap3630_init_late,
        .timer          = &omap3_timer,
-        .restart        = omap_prcm_restart,
+        .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/board-zoom.h
index 2e9486940ead..2e9486940ead 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/board-zoom.h
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
new file mode 100644
index 000000000000..7e5febe456d9
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -0,0 +1,1950 @@
+/*
+ * OMAP2420 clock data
+ *
+ * Copyright (C) 2005-2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+/*
+ * 2420 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
+ *
+ *      Several sources are given initial rates which may be wrong, this will
+ *      be fixed up in the init func.
+ *
+ *      Things are broadly separated below by clock domains. It is
+ *      noteworthy that most peripherals have dependencies on multiple clock
+ *      domains. Many get their interface clocks from the L4 domain, but get
+ *      functional clocks from fixed sources or other core domain derived
+ *      clocks.
+ */
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+static struct clk osc_ck;
+static const struct clk_ops osc_ck_ops = {
+        .recalc_rate    = &omap2_osc_clk_recalc,
+};
+static struct clk_hw_omap osc_ck_hw = {
+        .hw = {
+                .clk = &osc_ck,
+        },
+};
+static struct clk osc_ck = {
+        .name   = "osc_ck",
+        .ops    = &osc_ck_ops,
+        .hw     = &osc_ck_hw.hw,
+        .flags  = CLK_IS_ROOT,
+};
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+static struct clk sys_ck;
+static const char *sys_ck_parent_names[] = {
+        "osc_ck",
+};
+static const struct clk_ops sys_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .recalc_rate    = &omap2xxx_sys_clk_recalc,
+};
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+static struct dpll_data dpll_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP24XX_DPLL_MULT_MASK,
+        .div1_mask      = OMAP24XX_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP24XX_EN_DPLL_MASK,
+        .max_multiplier = 1023,
+        .min_divider    = 1,
+        .max_divider    = 16,
+};
+static struct clk dpll_ck;
+static const char *dpll_ck_parent_names[] = {
+        "sys_ck",
+};
+static const struct clk_ops dpll_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap2_dpllcore_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap2_reprogram_dpllcore,
+};
+static struct clk_hw_omap dpll_ck_hw = {
+        .hw = {
+                .clk = &dpll_ck,
+        },
+        .ops            = &clkhwops_omap2xxx_dpll,
+        .dpll_data      = &dpll_dd,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+static struct clk core_ck;
+static const char *core_ck_parent_names[] = {
+        "dpll_ck",
+};
+static const struct clk_ops core_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+};
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+                   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                   OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+                   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                   OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk aes_ick;
+static const char *aes_ick_parent_names[] = {
+        "l4_ck",
+};
+static const struct clk_ops aes_ick_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+};
+static struct clk_hw_omap aes_ick_hw = {
+        .hw = {
+                .clk = &aes_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk apll54_ck;
+static const struct clk_ops apll54_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_clk_apll54_enable,
+        .disable        = &omap2_clk_apll54_disable,
+        .recalc_rate    = &omap2_clk_apll54_recalc,
+};
+static struct clk_hw_omap apll54_ck_hw = {
+        .hw = {
+                .clk = &apll54_ck,
+        },
+        .ops            = &clkhwops_apll54,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+static struct clk apll96_ck;
+static const struct clk_ops apll96_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_clk_apll96_enable,
+        .disable        = &omap2_clk_apll96_disable,
+        .recalc_rate    = &omap2_clk_apll96_recalc,
+};
+static struct clk_hw_omap apll96_ck_hw = {
+        .hw = {
+                .clk = &apll96_ck,
+        },
+        .ops            = &clkhwops_apll96,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+static struct clk func_96m_ck;
+static const char *func_96m_ck_parent_names[] = {
+        "apll96_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
+static struct clk cam_fck;
+static const char *cam_fck_parent_names[] = {
+        "func_96m_ck",
+};
+static struct clk_hw_omap cam_fck_hw = {
+        .hw = {
+                .clk = &cam_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk cam_ick;
+static struct clk_hw_omap cam_ick_hw = {
+        .hw = {
+                .clk = &cam_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk des_ick;
+static struct clk_hw_omap des_ick_hw = {
+        .hw = {
+                .clk = &des_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate dsp_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel dsp_fck_clksel[] = {
+        { .parent = &core_ck, .rates = dsp_fck_core_rates },
+        { .parent = NULL },
+};
+static const char *dsp_fck_parent_names[] = {
+        "core_ck",
+};
+static const struct clk_ops dsp_fck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                         OMAP24XX_CLKSEL_DSP_MASK,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                         OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+                         dsp_fck_parent_names, dsp_fck_ops);
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
+        { .parent = NULL },
+};
+static const char *dsp_ick_parent_names[] = {
+        "dsp_fck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                         OMAP24XX_CLKSEL_DSP_IF_MASK,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+                         OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
+                         dsp_ick_parent_names, dsp_fck_ops);
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss1_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel dss1_fck_clksel[] = {
+        { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+        { .parent = &core_ck, .rates = dss1_fck_core_rates },
+        { .parent = NULL },
+};
+static const char *dss1_fck_parent_names[] = {
+        "sys_ck", "core_ck",
+};
+static struct clk dss1_fck;
+static const struct clk_ops dss1_fck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_DSS1_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_DSS1_SHIFT, NULL,
+                         dss1_fck_parent_names, dss1_fck_ops);
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate func_48m_apll96_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate func_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel func_48m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+        { .parent = &alt_ck, .rates = func_48m_alt_rates },
+        { .parent = NULL },
+};
+static const char *func_48m_ck_parent_names[] = {
+        "apll96_ck", "alt_ck",
+};
+static struct clk func_48m_ck;
+static const struct clk_ops func_48m_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+static struct clk_hw_omap func_48m_ck_hw = {
+        .hw = {
+                .clk = &func_48m_ck,
+        },
+        .clksel         = func_48m_clksel,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+static const struct clksel dss2_fck_clksel[] = {
+        { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+        { .parent = NULL },
+};
+static const char *dss2_fck_parent_names[] = {
+        "sys_ck", "func_48m_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_DSS2_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_DSS2_SHIFT, NULL,
+                         dss2_fck_parent_names, dss1_fck_ops);
+static const char *func_54m_ck_parent_names[] = {
+        "apll54_ck", "alt_ck",
+};
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+               OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+               OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
+               0x0, NULL);
+static struct clk dss_54m_fck;
+static const char *dss_54m_fck_parent_names[] = {
+        "func_54m_ck",
+};
+static struct clk_hw_omap dss_54m_fck_hw = {
+        .hw = {
+                .clk = &dss_54m_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+static struct clk dss_ick;
+static struct clk_hw_omap dss_ick_hw = {
+        .hw = {
+                .clk = &dss_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk eac_fck;
+static struct clk_hw_omap eac_fck_hw = {
+        .hw = {
+                .clk = &eac_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk eac_ick;
+static struct clk_hw_omap eac_ick_hw = {
+        .hw = {
+                .clk = &eac_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk emul_ck;
+static struct clk_hw_omap emul_ck_hw = {
+        .hw = {
+                .clk = &emul_ck,
+        },
+        .enable_reg     = OMAP2420_PRCM_CLKEMUL_CTRL,
+        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+static struct clk fac_fck;
+static const char *fac_fck_parent_names[] = {
+        "func_12m_ck",
+};
+static struct clk_hw_omap fac_fck_hw = {
+        .hw = {
+                .clk = &fac_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+static struct clk fac_ick;
+static struct clk_hw_omap fac_ick_hw = {
+        .hw = {
+                .clk = &fac_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel gfx_fck_clksel[] = {
+        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+        { .parent = NULL },
+};
+static const char *gfx_2d_fck_parent_names[] = {
+        "core_l3_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                         OMAP_CLKSEL_GFX_MASK,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                         OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+                         gfx_2d_fck_parent_names, dsp_fck_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                         OMAP_CLKSEL_GFX_MASK,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                         OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+                         gfx_2d_fck_parent_names, dsp_fck_ops);
+static struct clk gfx_ick;
+static const char *gfx_ick_parent_names[] = {
+        "core_l3_ck",
+};
+static struct clk_hw_omap gfx_ick_hw = {
+        .hw = {
+                .clk = &gfx_ick,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .clkdm_name     = "gfx_clkdm",
+};
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+static struct clk gpios_fck;
+static const char *gpios_fck_parent_names[] = {
+        "func_32k_ck",
+};
+static struct clk_hw_omap gpios_fck_hw = {
+        .hw = {
+                .clk = &gpios_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
+static struct clk wu_l4_ick;
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+static struct clk gpios_ick;
+static const char *gpios_ick_parent_names[] = {
+        "wu_l4_ick",
+};
+static struct clk_hw_omap gpios_ick_hw = {
+        .hw = {
+                .clk = &gpios_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk gpmc_fck;
+static struct clk_hw_omap gpmc_fck_hw = {
+        .hw = {
+                .clk = &gpmc_fck,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+static const struct clksel_rate gpt_alt_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel omap24xx_gpt_clksel[] = {
+        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck, .rates = gpt_sys_rates },
+        { .parent = &alt_ck, .rates = gpt_alt_rates },
+        { .parent = NULL },
+};
+static const char *gpt10_fck_parent_names[] = {
+        "func_32k_ck", "sys_ck", "alt_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT10_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt10_ick;
+static struct clk_hw_omap gpt10_ick_hw = {
+        .hw = {
+                .clk = &gpt10_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT11_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt11_ick;
+static struct clk_hw_omap gpt11_ick_hw = {
+        .hw = {
+                .clk = &gpt11_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT12_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt12_ick;
+static struct clk_hw_omap gpt12_ick_hw = {
+        .hw = {
+                .clk = &gpt12_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clk_ops gpt1_fck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_GPT1_MASK,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+                         OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, gpt1_fck_ops);
+static struct clk gpt1_ick;
+static struct clk_hw_omap gpt1_ick_hw = {
+        .hw = {
+                .clk = &gpt1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT2_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt2_ick;
+static struct clk_hw_omap gpt2_ick_hw = {
+        .hw = {
+                .clk = &gpt2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT3_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt3_ick;
+static struct clk_hw_omap gpt3_ick_hw = {
+        .hw = {
+                .clk = &gpt3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT4_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt4_ick;
+static struct clk_hw_omap gpt4_ick_hw = {
+        .hw = {
+                .clk = &gpt4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT5_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt5_ick;
+static struct clk_hw_omap gpt5_ick_hw = {
+        .hw = {
+                .clk = &gpt5_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT6_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt6_ick;
+static struct clk_hw_omap gpt6_ick_hw = {
+        .hw = {
+                .clk = &gpt6_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT7_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt7_ick;
+static struct clk_hw_omap gpt7_ick_hw = {
+        .hw = {
+                .clk = &gpt7_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT8_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt8_ick;
+static struct clk_hw_omap gpt8_ick_hw = {
+        .hw = {
+                .clk = &gpt8_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT9_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt9_ick;
+static struct clk_hw_omap gpt9_ick_hw = {
+        .hw = {
+                .clk = &gpt9_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk hdq_fck;
+static struct clk_hw_omap hdq_fck_hw = {
+        .hw = {
+                .clk = &hdq_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+static struct clk hdq_ick;
+static struct clk_hw_omap hdq_ick_hw = {
+        .hw = {
+                .clk = &hdq_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk i2c1_fck;
+static struct clk_hw_omap i2c1_fck_hw = {
+        .hw = {
+                .clk = &i2c1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
+static struct clk i2c1_ick;
+static struct clk_hw_omap i2c1_ick_hw = {
+        .hw = {
+                .clk = &i2c1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk i2c2_fck;
+static struct clk_hw_omap i2c2_fck_hw = {
+        .hw = {
+                .clk = &i2c2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
+static struct clk i2c2_ick;
+static struct clk_hw_omap i2c2_ick_hw = {
+        .hw = {
+                .clk = &i2c2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                         OMAP2420_CLKSEL_IVA_MASK,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                         OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
+                         dsp_fck_parent_names, dsp_fck_ops);
+static struct clk iva1_mpu_int_ifck;
+static const char *iva1_mpu_int_ifck_parent_names[] = {
+        "iva1_ifck",
+};
+static const struct clk_ops iva1_mpu_int_ifck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap_fixed_divisor_recalc,
+};
+static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
+        .hw = {
+                .clk = &iva1_mpu_int_ifck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
+        .clkdm_name     = "iva1_clkdm",
+        .fixed_div      = 2,
+};
+DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
+                  iva1_mpu_int_ifck_ops);
+static struct clk mailboxes_ick;
+static struct clk_hw_omap mailboxes_ick_hw = {
+        .hw = {
+                .clk = &mailboxes_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp1_fck_parent_names[] = {
+        "func_96m_ck", "mcbsp_clks",
+};
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                         OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                         OMAP2_MCBSP1_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, dss1_fck_ops);
+static struct clk mcbsp1_ick;
+static struct clk_hw_omap mcbsp1_ick_hw = {
+        .hw = {
+                .clk = &mcbsp1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                         OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                         OMAP2_MCBSP2_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, dss1_fck_ops);
+static struct clk mcbsp2_ick;
+static struct clk_hw_omap mcbsp2_ick_hw = {
+        .hw = {
+                .clk = &mcbsp2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mcspi1_fck;
+static const char *mcspi1_fck_parent_names[] = {
+        "func_48m_ck",
+};
+static struct clk_hw_omap mcspi1_fck_hw = {
+        .hw = {
+                .clk = &mcspi1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk mcspi1_ick;
+static struct clk_hw_omap mcspi1_ick_hw = {
+        .hw = {
+                .clk = &mcspi1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mcspi2_fck;
+static struct clk_hw_omap mcspi2_fck_hw = {
+        .hw = {
+                .clk = &mcspi2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk mcspi2_ick;
+static struct clk_hw_omap mcspi2_ick_hw = {
+        .hw = {
+                .clk = &mcspi2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mmc_fck;
+static struct clk_hw_omap mmc_fck_hw = {
+        .hw = {
+                .clk = &mmc_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk mmc_ick;
+static struct clk_hw_omap mmc_ick_hw = {
+        .hw = {
+                .clk = &mmc_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
+                   OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+                   OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk mpu_wdt_fck;
+static struct clk_hw_omap mpu_wdt_fck_hw = {
+        .hw = {
+                .clk = &mpu_wdt_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
+static struct clk mpu_wdt_ick;
+static struct clk_hw_omap mpu_wdt_ick_hw = {
+        .hw = {
+                .clk = &mpu_wdt_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk mspro_fck;
+static struct clk_hw_omap mspro_fck_hw = {
+        .hw = {
+                .clk = &mspro_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk mspro_ick;
+static struct clk_hw_omap mspro_ick_hw = {
+        .hw = {
+                .clk = &mspro_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk omapctrl_ick;
+static struct clk_hw_omap omapctrl_ick_hw = {
+        .hw = {
+                .clk = &omapctrl_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk pka_ick;
+static struct clk_hw_omap pka_ick_hw = {
+        .hw = {
+                .clk = &pka_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk rng_ick;
+static struct clk_hw_omap rng_ick_hw = {
+        .hw = {
+                .clk = &rng_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk sdma_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
+static struct clk sdma_ick;
+static struct clk_hw_omap sdma_ick_hw = {
+        .hw = {
+                .clk = &sdma_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
+static struct clk sdrc_ick;
+static struct clk_hw_omap sdrc_ick_hw = {
+        .hw = {
+                .clk = &sdrc_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDRC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
+static struct clk sha_ick;
+static struct clk_hw_omap sha_ick_hw = {
+        .hw = {
+                .clk = &sha_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk ssi_l4_ick;
+static struct clk_hw_omap ssi_l4_ick_hw = {
+        .hw = {
+                .clk = &ssi_l4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+        { .parent = NULL },
+};
+static const char *ssi_ssr_sst_fck_parent_names[] = {
+        "core_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
+                         ssi_ssr_sst_fck_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_SSI_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+                         OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
+                         ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
+static struct clk sync_32k_ick;
+static struct clk_hw_omap sync_32k_ick_hw = {
+        .hw = {
+                .clk = &sync_32k_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel common_clkout_src_clksel[] = {
+        { .parent = &core_ck, .rates = common_clkout_src_core_rates },
+        { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+        { .parent = NULL },
+};
+static const char *sys_clkout_src_parent_names[] = {
+        "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
+                         OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
+                         OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
+                         NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
+                   OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
+                   OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
+                         common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
+                         OMAP2420_CLKOUT2_SOURCE_MASK,
+                         OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
+                         NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
+                   OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
+                   OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+static struct clk uart1_fck;
+static struct clk_hw_omap uart1_fck_hw = {
+        .hw = {
+                .clk = &uart1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk uart1_ick;
+static struct clk_hw_omap uart1_ick_hw = {
+        .hw = {
+                .clk = &uart1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk uart2_fck;
+static struct clk_hw_omap uart2_fck_hw = {
+        .hw = {
+                .clk = &uart2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk uart2_ick;
+static struct clk_hw_omap uart2_ick_hw = {
+        .hw = {
+                .clk = &uart2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk uart3_fck;
+static struct clk_hw_omap uart3_fck_hw = {
+        .hw = {
+                .clk = &uart3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk uart3_ick;
+static struct clk_hw_omap uart3_ick_hw = {
+        .hw = {
+                .clk = &uart3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk usb_fck;
+static struct clk_hw_omap usb_fck_hw = {
+        .hw = {
+                .clk = &usb_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel usb_l4_ick_clksel[] = {
+        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+        { .parent = NULL },
+};
+static const char *usb_l4_ick_parent_names[] = {
+        "core_l3_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_USB_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+                         OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
+                         usb_l4_ick_parent_names, dsp_fck_ops);
+static struct clk virt_prcm_set;
+static const char *virt_prcm_set_parent_names[] = {
+        "mpu_ck",
+};
+static const struct clk_ops virt_prcm_set_ops = {
+        .recalc_rate    = &omap2_table_mpu_recalc,
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
+DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_242X },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 3, .val = 3, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 9, .val = 9, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X },
+        { .div = 18, .val = 18, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+static const struct clksel vlynq_fck_clksel[] = {
+        { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+        { .parent = &core_ck, .rates = vlynq_fck_core_rates },
+        { .parent = NULL },
+};
+static const char *vlynq_fck_parent_names[] = {
+        "func_96m_ck", "core_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP2420_CLKSEL_VLYNQ_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
+                         vlynq_fck_parent_names, dss1_fck_ops);
+static struct clk vlynq_ick;
+static struct clk_hw_omap vlynq_ick_hw = {
+        .hw = {
+                .clk = &vlynq_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
+static struct clk wdt1_ick;
+static struct clk_hw_omap wdt1_ick_hw = {
+        .hw = {
+                .clk = &wdt1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk wdt1_osc_ck;
+static const struct clk_ops wdt1_osc_ck_ops = {};
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
+DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
+static struct clk wdt3_fck;
+static struct clk_hw_omap wdt3_fck_hw = {
+        .hw = {
+                .clk = &wdt3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
+static struct clk wdt3_ick;
+static struct clk_hw_omap wdt3_ick_hw = {
+        .hw = {
+                .clk = &wdt3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk wdt4_fck;
+static struct clk_hw_omap wdt4_fck_hw = {
+        .hw = {
+                .clk = &wdt4_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
+static struct clk wdt4_ick;
+static struct clk_hw_omap wdt4_ick_hw = {
+        .hw = {
+                .clk = &wdt4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
+/*
+ * clkdev integration
+ */
+static struct omap_clk omap2420_clks[] = {
+        /* external root sources */
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
+        CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
+        CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
+        /* internal analog sources */
+        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
+        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
+        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
+        /* internal prcm root sources */
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
+        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
+        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
+        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
+        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+        /* mpu domain clocks */
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
+        /* dsp domain clocks */
+        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
+        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
+        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
+        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+        /* GFX domain clocks */
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
+        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
+        /* DSS domain clocks */
+        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
+        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
+        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
+        /* L3 domain clocks */
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
+        /* L4 domain clocks */
+        CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
+        /* virtual meta-group clock */
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
+        /* general l4 interface ck, multi-parent functional clk */
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
+        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
+        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
+        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
+        CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
+        CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
+        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
+        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
+        CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
+        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
+        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
+        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
+        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
+        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
+        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
+        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
+        CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
+        CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
+        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
+        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
+        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
+};
+static const char *enable_init_clks[] = {
+        "apll96_ck",
+        "apll54_ck",
+        "sync_32k_ick",
+        "omapctrl_ick",
+        "gpmc_fck",
+        "sdrc_ick",
+};
+/*
+ * init code
+ */
+int __init omap2420_clk_init(void)
+{
+        struct omap_clk *c;
+        prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+        cpu_mask = RATE_IN_242X;
+        rate_table = omap2420_rate_table;
+        omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
+        omap2xxx_clkt_vps_check_bootloader_rates();
+        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+             c++) {
+                clkdev_add(&c->lk);
+                if (!__clk_init(NULL, c->lk.clk))
+                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
+        }
+        omap2_clk_disable_autoidle_all();
+        omap2_clk_enable_init_clocks(enable_init_clks,
+                                     ARRAY_SIZE(enable_init_clks));
+        pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (clk_get_rate(&sys_ck) / 1000000),
+                (clk_get_rate(&sys_ck) / 100000) % 10,
+                (clk_get_rate(&dpll_ck) / 1000000),
+                (clk_get_rate(&mpu_ck) / 1000000));
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
new file mode 100644
index 000000000000..eda079b96c6a
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -0,0 +1,2065 @@
+/*
+ * OMAP2430 clock data
+ *
+ * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm2xxx.h"
+#include "prm2xxx.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "control.h"
+#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
+/*
+ * 2430 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
+ *
+ *      Several sources are given initial rates which may be wrong, this will
+ *      be fixed up in the init func.
+ *
+ *      Things are broadly separated below by clock domains. It is
+ *      noteworthy that most peripherals have dependencies on multiple clock
+ *      domains. Many get their interface clocks from the L4 domain, but get
+ *      functional clocks from fixed sources or other core domain derived
+ *      clocks.
+ */
+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+static struct clk osc_ck;
+static const struct clk_ops osc_ck_ops = {
+        .enable         = &omap2_enable_osc_ck,
+        .disable        = omap2_disable_osc_ck,
+        .recalc_rate    = &omap2_osc_clk_recalc,
+};
+static struct clk_hw_omap osc_ck_hw = {
+        .hw = {
+                .clk = &osc_ck,
+        },
+};
+static struct clk osc_ck = {
+        .name   = "osc_ck",
+        .ops    = &osc_ck_ops,
+        .hw     = &osc_ck_hw.hw,
+        .flags  = CLK_IS_ROOT,
+};
+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+static struct clk sys_ck;
+static const char *sys_ck_parent_names[] = {
+        "osc_ck",
+};
+static const struct clk_ops sys_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .recalc_rate    = &omap2xxx_sys_clk_recalc,
+};
+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
+static struct dpll_data dpll_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP24XX_DPLL_MULT_MASK,
+        .div1_mask      = OMAP24XX_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP24XX_EN_DPLL_MASK,
+        .max_multiplier = 1023,
+        .min_divider    = 1,
+        .max_divider    = 16,
+};
+static struct clk dpll_ck;
+static const char *dpll_ck_parent_names[] = {
+        "sys_ck",
+};
+static const struct clk_ops dpll_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap2_dpllcore_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap2_reprogram_dpllcore,
+};
+static struct clk_hw_omap dpll_ck_hw = {
+        .hw = {
+                .clk = &dpll_ck,
+        },
+        .ops            = &clkhwops_omap2xxx_dpll,
+        .dpll_data      = &dpll_dd,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
+static struct clk core_ck;
+static const char *core_ck_parent_names[] = {
+        "dpll_ck",
+};
+static const struct clk_ops core_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+};
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
+                   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                   OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
+                   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                   OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk aes_ick;
+static const char *aes_ick_parent_names[] = {
+        "l4_ck",
+};
+static const struct clk_ops aes_ick_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+};
+static struct clk_hw_omap aes_ick_hw = {
+        .hw = {
+                .clk = &aes_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk apll54_ck;
+static const struct clk_ops apll54_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_clk_apll54_enable,
+        .disable        = &omap2_clk_apll54_disable,
+        .recalc_rate    = &omap2_clk_apll54_recalc,
+};
+static struct clk_hw_omap apll54_ck_hw = {
+        .hw = {
+                .clk = &apll54_ck,
+        },
+        .ops            = &clkhwops_apll54,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
+static struct clk apll96_ck;
+static const struct clk_ops apll96_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_clk_apll96_enable,
+        .disable        = &omap2_clk_apll96_disable,
+        .recalc_rate    = &omap2_clk_apll96_recalc,
+};
+static struct clk_hw_omap apll96_ck_hw = {
+        .hw = {
+                .clk = &apll96_ck,
+        },
+        .ops            = &clkhwops_apll96,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
+static const char *func_96m_ck_parent_names[] = {
+        "apll96_ck", "alt_ck",
+};
+DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
+               OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
+               OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
+static struct clk cam_fck;
+static const char *cam_fck_parent_names[] = {
+        "func_96m_ck",
+};
+static struct clk_hw_omap cam_fck_hw = {
+        .hw = {
+                .clk = &cam_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk cam_ick;
+static struct clk_hw_omap cam_ick_hw = {
+        .hw = {
+                .clk = &cam_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk des_ick;
+static struct clk_hw_omap des_ick_hw = {
+        .hw = {
+                .clk = &des_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate dsp_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel dsp_fck_clksel[] = {
+        { .parent = &core_ck, .rates = dsp_fck_core_rates },
+        { .parent = NULL },
+};
+static const char *dsp_fck_parent_names[] = {
+        "core_ck",
+};
+static struct clk dsp_fck;
+static const struct clk_ops dsp_fck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                         OMAP24XX_CLKSEL_DSP_MASK,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                         OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+                         dsp_fck_parent_names, dsp_fck_ops);
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss1_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel dss1_fck_clksel[] = {
+        { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+        { .parent = &core_ck, .rates = dss1_fck_core_rates },
+        { .parent = NULL },
+};
+static const char *dss1_fck_parent_names[] = {
+        "sys_ck", "core_ck",
+};
+static const struct clk_ops dss1_fck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_DSS1_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_DSS1_SHIFT, NULL,
+                         dss1_fck_parent_names, dss1_fck_ops);
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate func_48m_apll96_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate func_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel func_48m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+        { .parent = &alt_ck, .rates = func_48m_alt_rates },
+        { .parent = NULL },
+};
+static const char *func_48m_ck_parent_names[] = {
+        "apll96_ck", "alt_ck",
+};
+static struct clk func_48m_ck;
+static const struct clk_ops func_48m_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+static struct clk_hw_omap func_48m_ck_hw = {
+        .hw = {
+                .clk = &func_48m_ck,
+        },
+        .clksel         = func_48m_clksel,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
+static const struct clksel dss2_fck_clksel[] = {
+        { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+        { .parent = NULL },
+};
+static const char *dss2_fck_parent_names[] = {
+        "sys_ck", "func_48m_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_DSS2_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_DSS2_SHIFT, NULL,
+                         dss2_fck_parent_names, dss1_fck_ops);
+static const char *func_54m_ck_parent_names[] = {
+        "apll54_ck", "alt_ck",
+};
+DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
+               OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+               OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
+static struct clk dss_54m_fck;
+static const char *dss_54m_fck_parent_names[] = {
+        "func_54m_ck",
+};
+static struct clk_hw_omap dss_54m_fck_hw = {
+        .hw = {
+                .clk = &dss_54m_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
+static struct clk dss_ick;
+static struct clk_hw_omap dss_ick_hw = {
+        .hw = {
+                .clk = &dss_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk emul_ck;
+static struct clk_hw_omap emul_ck_hw = {
+        .hw = {
+                .clk = &emul_ck,
+        },
+        .enable_reg     = OMAP2430_PRCM_CLKEMUL_CTRL,
+        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
+DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
+static struct clk fac_fck;
+static const char *fac_fck_parent_names[] = {
+        "func_12m_ck",
+};
+static struct clk_hw_omap fac_fck_hw = {
+        .hw = {
+                .clk = &fac_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
+static struct clk fac_ick;
+static struct clk_hw_omap fac_ick_hw = {
+        .hw = {
+                .clk = &fac_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel gfx_fck_clksel[] = {
+        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+        { .parent = NULL },
+};
+static const char *gfx_2d_fck_parent_names[] = {
+        "core_l3_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                         OMAP_CLKSEL_GFX_MASK,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                         OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
+                         gfx_2d_fck_parent_names, dsp_fck_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                         OMAP_CLKSEL_GFX_MASK,
+                         OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+                         OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
+                         gfx_2d_fck_parent_names, dsp_fck_ops);
+static struct clk gfx_ick;
+static const char *gfx_ick_parent_names[] = {
+        "core_l3_ck",
+};
+static struct clk_hw_omap gfx_ick_hw = {
+        .hw = {
+                .clk = &gfx_ick,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .clkdm_name     = "gfx_clkdm",
+};
+DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
+static struct clk gpio5_fck;
+static const char *gpio5_fck_parent_names[] = {
+        "func_32k_ck",
+};
+static struct clk_hw_omap gpio5_fck_hw = {
+        .hw = {
+                .clk = &gpio5_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
+static struct clk gpio5_ick;
+static struct clk_hw_omap gpio5_ick_hw = {
+        .hw = {
+                .clk = &gpio5_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk gpios_fck;
+static struct clk_hw_omap gpios_fck_hw = {
+        .hw = {
+                .clk = &gpios_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
+static struct clk wu_l4_ick;
+DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
+static struct clk gpios_ick;
+static const char *gpios_ick_parent_names[] = {
+        "wu_l4_ick",
+};
+static struct clk_hw_omap gpios_ick_hw = {
+        .hw = {
+                .clk = &gpios_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk gpmc_fck;
+static struct clk_hw_omap gpmc_fck_hw = {
+        .hw = {
+                .clk = &gpmc_fck,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
+static const struct clksel_rate gpt_alt_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel omap24xx_gpt_clksel[] = {
+        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck, .rates = gpt_sys_rates },
+        { .parent = &alt_ck, .rates = gpt_alt_rates },
+        { .parent = NULL },
+};
+static const char *gpt10_fck_parent_names[] = {
+        "func_32k_ck", "sys_ck", "alt_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT10_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt10_ick;
+static struct clk_hw_omap gpt10_ick_hw = {
+        .hw = {
+                .clk = &gpt10_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT11_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt11_ick;
+static struct clk_hw_omap gpt11_ick_hw = {
+        .hw = {
+                .clk = &gpt11_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT12_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt12_ick;
+static struct clk_hw_omap gpt12_ick_hw = {
+        .hw = {
+                .clk = &gpt12_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clk_ops gpt1_fck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_GPT1_MASK,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+                         OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, gpt1_fck_ops);
+static struct clk gpt1_ick;
+static struct clk_hw_omap gpt1_ick_hw = {
+        .hw = {
+                .clk = &gpt1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT2_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt2_ick;
+static struct clk_hw_omap gpt2_ick_hw = {
+        .hw = {
+                .clk = &gpt2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT3_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt3_ick;
+static struct clk_hw_omap gpt3_ick_hw = {
+        .hw = {
+                .clk = &gpt3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT4_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt4_ick;
+static struct clk_hw_omap gpt4_ick_hw = {
+        .hw = {
+                .clk = &gpt4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT5_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt5_ick;
+static struct clk_hw_omap gpt5_ick_hw = {
+        .hw = {
+                .clk = &gpt5_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT6_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt6_ick;
+static struct clk_hw_omap gpt6_ick_hw = {
+        .hw = {
+                .clk = &gpt6_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT7_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt7_ick;
+static struct clk_hw_omap gpt7_ick_hw = {
+        .hw = {
+                .clk = &gpt7_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk gpt8_fck;
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT8_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt8_ick;
+static struct clk_hw_omap gpt8_ick_hw = {
+        .hw = {
+                .clk = &gpt8_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+                         OMAP24XX_CLKSEL_GPT9_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, dss1_fck_ops);
+static struct clk gpt9_ick;
+static struct clk_hw_omap gpt9_ick_hw = {
+        .hw = {
+                .clk = &gpt9_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk hdq_fck;
+static struct clk_hw_omap hdq_fck_hw = {
+        .hw = {
+                .clk = &hdq_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
+static struct clk hdq_ick;
+static struct clk_hw_omap hdq_ick_hw = {
+        .hw = {
+                .clk = &hdq_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk i2c1_ick;
+static struct clk_hw_omap i2c1_ick_hw = {
+        .hw = {
+                .clk = &i2c1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk i2c2_ick;
+static struct clk_hw_omap i2c2_ick_hw = {
+        .hw = {
+                .clk = &i2c2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk i2chs1_fck;
+static struct clk_hw_omap i2chs1_fck_hw = {
+        .hw = {
+                .clk = &i2chs1_fck,
+        },
+        .ops            = &clkhwops_omap2430_i2chs_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk i2chs2_fck;
+static struct clk_hw_omap i2chs2_fck_hw = {
+        .hw = {
+                .clk = &i2chs2_fck,
+        },
+        .ops            = &clkhwops_omap2430_i2chs_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk icr_ick;
+static struct clk_hw_omap icr_ick_hw = {
+        .hw = {
+                .clk = &icr_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
+        { .parent = NULL },
+};
+static const char *iva2_1_ick_parent_names[] = {
+        "dsp_fck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+                         OMAP24XX_CLKSEL_DSP_IF_MASK,
+                         OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+                         OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
+                         iva2_1_ick_parent_names, dsp_fck_ops);
+static struct clk mailboxes_ick;
+static struct clk_hw_omap mailboxes_ick_hw = {
+        .hw = {
+                .clk = &mailboxes_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp1_fck_parent_names[] = {
+        "func_96m_ck", "mcbsp_clks",
+};
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                         OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                         OMAP2_MCBSP1_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, dss1_fck_ops);
+static struct clk mcbsp1_ick;
+static struct clk_hw_omap mcbsp1_ick_hw = {
+        .hw = {
+                .clk = &mcbsp1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                         OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                         OMAP2_MCBSP2_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, dss1_fck_ops);
+static struct clk mcbsp2_ick;
+static struct clk_hw_omap mcbsp2_ick_hw = {
+        .hw = {
+                .clk = &mcbsp2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                         OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+                         OMAP2_MCBSP3_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+                         OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, dss1_fck_ops);
+static struct clk mcbsp3_ick;
+static struct clk_hw_omap mcbsp3_ick_hw = {
+        .hw = {
+                .clk = &mcbsp3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                         OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+                         OMAP2_MCBSP4_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+                         OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, dss1_fck_ops);
+static struct clk mcbsp4_ick;
+static struct clk_hw_omap mcbsp4_ick_hw = {
+        .hw = {
+                .clk = &mcbsp4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel,
+                         OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+                         OMAP2_MCBSP5_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+                         OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, dss1_fck_ops);
+static struct clk mcbsp5_ick;
+static struct clk_hw_omap mcbsp5_ick_hw = {
+        .hw = {
+                .clk = &mcbsp5_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mcspi1_fck;
+static const char *mcspi1_fck_parent_names[] = {
+        "func_48m_ck",
+};
+static struct clk_hw_omap mcspi1_fck_hw = {
+        .hw = {
+                .clk = &mcspi1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk mcspi1_ick;
+static struct clk_hw_omap mcspi1_ick_hw = {
+        .hw = {
+                .clk = &mcspi1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mcspi2_fck;
+static struct clk_hw_omap mcspi2_fck_hw = {
+        .hw = {
+                .clk = &mcspi2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk mcspi2_ick;
+static struct clk_hw_omap mcspi2_ick_hw = {
+        .hw = {
+                .clk = &mcspi2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mcspi3_fck;
+static struct clk_hw_omap mcspi3_fck_hw = {
+        .hw = {
+                .clk = &mcspi3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk mcspi3_ick;
+static struct clk_hw_omap mcspi3_ick_hw = {
+        .hw = {
+                .clk = &mcspi3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate mdm_ick_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X },
+        { .div = 6, .val = 6, .flags = RATE_IN_243X },
+        { .div = 9, .val = 9, .flags = RATE_IN_243X },
+        { .div = 0 }
+};
+static const struct clksel mdm_ick_clksel[] = {
+        { .parent = &core_ck, .rates = mdm_ick_core_rates },
+        { .parent = NULL },
+};
+static const char *mdm_ick_parent_names[] = {
+        "core_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel,
+                         OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
+                         OMAP2430_CLKSEL_MDM_MASK,
+                         OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+                         OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
+                         &clkhwops_iclk_wait, mdm_ick_parent_names,
+                         dsp_fck_ops);
+static struct clk mdm_intc_ick;
+static struct clk_hw_omap mdm_intc_ick_hw = {
+        .hw = {
+                .clk = &mdm_intc_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mdm_osc_ck;
+static struct clk_hw_omap mdm_osc_ck_hw = {
+        .hw = {
+                .clk = &mdm_osc_ck,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
+        .clkdm_name     = "mdm_clkdm",
+};
+DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
+static struct clk mmchs1_fck;
+static struct clk_hw_omap mmchs1_fck_hw = {
+        .hw = {
+                .clk = &mmchs1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk mmchs1_ick;
+static struct clk_hw_omap mmchs1_ick_hw = {
+        .hw = {
+                .clk = &mmchs1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mmchs2_fck;
+static struct clk_hw_omap mmchs2_fck_hw = {
+        .hw = {
+                .clk = &mmchs2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk mmchs2_ick;
+static struct clk_hw_omap mmchs2_ick_hw = {
+        .hw = {
+                .clk = &mmchs2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk mmchsdb1_fck;
+static struct clk_hw_omap mmchsdb1_fck_hw = {
+        .hw = {
+                .clk = &mmchsdb1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops);
+static struct clk mmchsdb2_fck;
+static struct clk_hw_omap mmchsdb2_fck_hw = {
+        .hw = {
+                .clk = &mmchsdb2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
+DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
+                   OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+                   OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk mpu_wdt_fck;
+static struct clk_hw_omap mpu_wdt_fck_hw = {
+        .hw = {
+                .clk = &mpu_wdt_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops);
+static struct clk mpu_wdt_ick;
+static struct clk_hw_omap mpu_wdt_ick_hw = {
+        .hw = {
+                .clk = &mpu_wdt_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk mspro_fck;
+static struct clk_hw_omap mspro_fck_hw = {
+        .hw = {
+                .clk = &mspro_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
+static struct clk mspro_ick;
+static struct clk_hw_omap mspro_ick_hw = {
+        .hw = {
+                .clk = &mspro_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk omapctrl_ick;
+static struct clk_hw_omap omapctrl_ick_hw = {
+        .hw = {
+                .clk = &omapctrl_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk pka_ick;
+static struct clk_hw_omap pka_ick_hw = {
+        .hw = {
+                .clk = &pka_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk rng_ick;
+static struct clk_hw_omap rng_ick_hw = {
+        .hw = {
+                .clk = &rng_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk sdma_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
+static struct clk sdma_ick;
+static struct clk_hw_omap sdma_ick_hw = {
+        .hw = {
+                .clk = &sdma_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
+static struct clk sdrc_ick;
+static struct clk_hw_omap sdrc_ick_hw = {
+        .hw = {
+                .clk = &sdrc_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
+static struct clk sha_ick;
+static struct clk_hw_omap sha_ick_hw = {
+        .hw = {
+                .clk = &sha_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk ssi_l4_ick;
+static struct clk_hw_omap ssi_l4_ick_hw = {
+        .hw = {
+                .clk = &ssi_l4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_243X },
+        { .div = 0 }
+};
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+        { .parent = NULL },
+};
+static const char *ssi_ssr_sst_fck_parent_names[] = {
+        "core_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
+                         ssi_ssr_sst_fck_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_SSI_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+                         OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
+                         ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
+static struct clk sync_32k_ick;
+static struct clk_hw_omap sync_32k_ick_hw = {
+        .hw = {
+                .clk = &sync_32k_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel common_clkout_src_clksel[] = {
+        { .parent = &core_ck, .rates = common_clkout_src_core_rates },
+        { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+        { .parent = NULL },
+};
+static const char *sys_clkout_src_parent_names[] = {
+        "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
+                         OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
+                         OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
+                         NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
+DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
+                   OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
+                   OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+static struct clk uart1_fck;
+static struct clk_hw_omap uart1_fck_hw = {
+        .hw = {
+                .clk = &uart1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk uart1_ick;
+static struct clk_hw_omap uart1_ick_hw = {
+        .hw = {
+                .clk = &uart1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk uart2_fck;
+static struct clk_hw_omap uart2_fck_hw = {
+        .hw = {
+                .clk = &uart2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk uart2_ick;
+static struct clk_hw_omap uart2_ick_hw = {
+        .hw = {
+                .clk = &uart2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk uart3_fck;
+static struct clk_hw_omap uart3_fck_hw = {
+        .hw = {
+                .clk = &uart3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static struct clk uart3_ick;
+static struct clk_hw_omap uart3_ick_hw = {
+        .hw = {
+                .clk = &uart3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
+static struct clk usb_fck;
+static struct clk_hw_omap usb_fck_hw = {
+        .hw = {
+                .clk = &usb_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+static const struct clksel usb_l4_ick_clksel[] = {
+        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+        { .parent = NULL },
+};
+static const char *usb_l4_ick_parent_names[] = {
+        "core_l3_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+                         OMAP24XX_CLKSEL_USB_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+                         OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
+                         usb_l4_ick_parent_names, dsp_fck_ops);
+static struct clk usbhs_ick;
+static struct clk_hw_omap usbhs_ick_hw = {
+        .hw = {
+                .clk = &usbhs_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops);
+static struct clk virt_prcm_set;
+static const char *virt_prcm_set_parent_names[] = {
+        "mpu_ck",
+};
+static const struct clk_ops virt_prcm_set_ops = {
+        .recalc_rate    = &omap2_table_mpu_recalc,
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
+DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
+static struct clk wdt1_ick;
+static struct clk_hw_omap wdt1_ick_hw = {
+        .hw = {
+                .clk = &wdt1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
+static struct clk wdt1_osc_ck;
+static const struct clk_ops wdt1_osc_ck_ops = {};
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
+DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
+static struct clk wdt4_fck;
+static struct clk_hw_omap wdt4_fck_hw = {
+        .hw = {
+                .clk = &wdt4_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops);
+static struct clk wdt4_ick;
+static struct clk_hw_omap wdt4_ick_hw = {
+        .hw = {
+                .clk = &wdt4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
+/*
+ * clkdev integration
+ */
+static struct omap_clk omap2430_clks[] = {
+        /* external root sources */
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
+        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
+        CLK("twl",      "fck",          &osc_ck,        CK_243X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
+        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
+        /* internal analog sources */
+        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
+        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
+        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X),
+        /* internal prcm root sources */
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
+        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
+        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
+        CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
+        /* mpu domain clocks */
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
+        /* dsp domain clocks */
+        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
+        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
+        /* GFX domain clocks */
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X),
+        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X),
+        /* Modem domain clocks */
+        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
+        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+        /* DSS domain clocks */
+        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
+        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
+        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
+        /* L3 domain clocks */
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X),
+        /* L4 domain clocks */
+        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_243X),
+        /* virtual meta-group clock */
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
+        /* general l4 interface ck, multi-parent functional clk */
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X),
+        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
+        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
+        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
+        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
+        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
+        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
+        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
+        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
+        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
+        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
+        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
+        CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
+        CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
+        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
+        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
+        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
+        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
+        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
+        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
+        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
+        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK(NULL,        "mmchsdb1_fck",        &mmchsdb1_fck,  CK_243X),
+        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+        CLK(NULL,        "mmchsdb2_fck",        &mmchsdb2_fck,  CK_243X),
+        CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
+};
+static const char *enable_init_clks[] = {
+        "apll96_ck",
+        "apll54_ck",
+        "sync_32k_ick",
+        "omapctrl_ick",
+        "gpmc_fck",
+        "sdrc_ick",
+};
+/*
+ * init code
+ */
+int __init omap2430_clk_init(void)
+{
+        struct omap_clk *c;
+        prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
+        cpu_mask = RATE_IN_243X;
+        rate_table = omap2430_rate_table;
+        omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
+        omap2xxx_clkt_vps_check_bootloader_rates();
+        for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
+             c++) {
+                clkdev_add(&c->lk);
+                if (!__clk_init(NULL, c->lk.clk))
+                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
+        }
+        omap2_clk_disable_autoidle_all();
+        omap2_clk_enable_init_clocks(enable_init_clks,
+                                     ARRAY_SIZE(enable_init_clks));
+        pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (clk_get_rate(&sys_ck) / 1000000),
+                (clk_get_rate(&sys_ck) / 100000) % 10,
+                (clk_get_rate(&dpll_ck) / 1000000),
+                (clk_get_rate(&mpu_ck) / 1000000));
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
new file mode 100644
index 000000000000..ea64ad606759
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -0,0 +1,961 @@
+/*
+ * AM33XX Clock data
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include "am33xx.h"
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "control.h"
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-33xx.h"
+#include "prm.h"
+/* Modulemode control */
+#define AM33XX_MODULEMODE_HWCTRL_SHIFT          0
+#define AM33XX_MODULEMODE_SWCTRL_SHIFT          1
+/*LIST_HEAD(clocks);*/
+/* Root clocks */
+/* RTC 32k */
+DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
+/* On-Chip 32KHz RC OSC */
+DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
+/* Crystal input clks */
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
+/* Oscillator clock */
+/* 19.2, 24, 25 or 26 MHz */
+static const char *sys_clkin_ck_parents[] = {
+        "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
+        "virt_26000000_ck",
+};
+/*
+ * sys_clk in: input to the dpll and also used as funtional clock for,
+ *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
+ *
+ */
+DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
+               AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
+               AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
+               AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
+               0, NULL);
+/* External clock - 12 MHz */
+DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
+/* Module clocks and DPLL outputs */
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+/* CLKDCOLDO output */
+static const char *dpll_core_ck_parents[] = {
+        "sys_clkin_ck",
+};
+static struct clk dpll_core_ck;
+static const struct clk_ops dpll_core_ck_ops = {
+        .recalc_rate    = &omap3_dpll_recalc,
+        .get_parent     = &omap2_init_dpll_parent,
+};
+static struct clk_hw_omap dpll_core_ck_hw = {
+        .hw     = {
+                .clk    = &dpll_core_ck,
+        },
+        .dpll_data      = &dpll_core_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
+static const char *dpll_core_x2_ck_parents[] = {
+        "dpll_core_ck",
+};
+static struct clk dpll_core_x2_ck;
+static const struct clk_ops dpll_x2_ck_ops = {
+        .recalc_rate    = &omap3_clkoutx2_recalc,
+};
+static struct clk_hw_omap dpll_core_x2_ck_hw = {
+        .hw     = {
+                .clk    = &dpll_core_x2_ck,
+        },
+        .flags          = CLOCK_CLKOUTX2,
+};
+DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
+DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
+                   0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
+                   AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
+                   AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
+                   NULL);
+DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
+                   0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
+                   AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
+                   AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
+                   0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
+                   AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
+                   AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_mpu_ck;
+static const struct clk_ops dpll_mpu_ck_ops = {
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .recalc_rate    = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .get_parent     = &omap2_init_dpll_parent,
+};
+static struct clk_hw_omap dpll_mpu_ck_hw = {
+        .hw = {
+                .clk    = &dpll_mpu_ck,
+        },
+        .dpll_data      = &dpll_mpu_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
+                   0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
+                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+/* DPLL_DDR */
+static struct dpll_data dpll_ddr_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_ddr_ck;
+static const struct clk_ops dpll_ddr_ck_ops = {
+        .recalc_rate    = &omap3_dpll_recalc,
+        .get_parent     = &omap2_init_dpll_parent,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+static struct clk_hw_omap dpll_ddr_ck_hw = {
+        .hw = {
+                .clk    = &dpll_ddr_ck,
+        },
+        .dpll_data      = &dpll_ddr_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
+                   0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
+                   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+/* emif_fck functional clock */
+DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
+                        0x0, 1, 2);
+/* DPLL_DISP */
+static struct dpll_data dpll_disp_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_disp_ck;
+static struct clk_hw_omap dpll_disp_ck_hw = {
+        .hw = {
+                .clk    = &dpll_disp_ck,
+        },
+        .dpll_data      = &dpll_disp_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
+                   AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
+                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
+        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
+        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+        .flags          = DPLL_J_TYPE,
+};
+/* CLKDCOLDO */
+static struct clk dpll_per_ck;
+static struct clk_hw_omap dpll_per_ck_hw = {
+        .hw     = {
+                .clk    = &dpll_per_ck,
+        },
+        .dpll_data      = &dpll_per_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
+/* CLKOUT: fdpll/M2 */
+DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
+                   AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
+                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
+                   NULL);
+DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
+                        &dpll_per_m2_ck, 0x0, 1, 4);
+DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
+                        &dpll_per_m2_ck, 0x0, 1, 4);
+DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
+                        &dpll_core_m4_ck, 0x0, 1, 2);
+DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
+                        1, 2);
+DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
+                        8);
+/*
+ * Below clock nodes describes clockdomains derived out
+ * of core clock.
+ */
+static const struct clk_ops clk_ops_null = {
+};
+static const char *l3_gclk_parents[] = {
+        "dpll_core_m4_ck"
+};
+static struct clk l3_gclk;
+DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
+DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
+static struct clk l4hs_gclk;
+DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
+DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
+static const char *l3s_gclk_parents[] = {
+        "dpll_core_m4_div2_ck"
+};
+static struct clk l3s_gclk;
+DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
+DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
+static struct clk l4fw_gclk;
+DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
+DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
+static struct clk l4ls_gclk;
+DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
+DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
+static struct clk sysclk_div_ck;
+DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
+DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
+/*
+ * In order to match the clock domain with hwmod clockdomain entry,
+ * separate clock nodes is required for the modules which are
+ * directly getting their funtioncal clock from sys_clkin.
+ */
+static struct clk adc_tsc_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
+DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
+static struct clk dcan0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
+DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
+static struct clk dcan1_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
+DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
+static struct clk mcasp0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
+DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
+static struct clk mcasp1_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
+DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
+static struct clk smartreflex0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
+DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
+static struct clk smartreflex1_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
+DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
+/*
+ * Modules clock nodes
+ *
+ * The following clock leaf nodes are added for the moment because:
+ *
+ *  - hwmod data is not present for these modules, either hwmod
+ *    control is not required or its not populated.
+ *  - Driver code is not yet migrated to use hwmod/runtime pm
+ *  - Modules outside kernel access (to disable them by default)
+ *
+ *     - debugss
+ *     - mmu (gfx domain)
+ *     - cefuse
+ *     - usbotg_fck (its additional clock and not really a modulemode)
+ *     - ieee5000
+ */
+DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
+                AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
+                AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
+                AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+/*
+ * clkdiv32 is generated from fixed division of 732.4219
+ */
+DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
+DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0,
+                AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+/* "usbotg_fck" is an additional clock and not really a modulemode */
+DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
+                AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
+                0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
+                AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+/* Timers */
+static const struct clksel timer1_clkmux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
+        { .parent = &tclkin_ck, .rates = div_1_2_rates },
+        { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
+        { .parent = &clk_32768_ck, .rates = div_1_4_rates },
+        { .parent = NULL },
+};
+static const char *timer1_ck_parents[] = {
+        "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
+        "clk_32768_ck",
+};
+static struct clk timer1_fck;
+static const struct clk_ops timer1_fck_ops = {
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+        .init           = &omap2_init_clk_clkdm,
+};
+static struct clk_hw_omap timer1_fck_hw = {
+        .hw     = {
+                .clk    = &timer1_fck,
+        },
+        .clkdm_name     = "l4ls_clkdm",
+        .clksel         = timer1_clkmux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
+};
+DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
+static const struct clksel timer2_to_7_clk_sel[] = {
+        { .parent = &tclkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const char *timer2_to_7_ck_parents[] = {
+        "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
+};
+static struct clk timer2_fck;
+static struct clk_hw_omap timer2_fck_hw = {
+        .hw     = {
+                .clk    = &timer2_fck,
+        },
+        .clkdm_name     = "l4ls_clkdm",
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
+static struct clk timer3_fck;
+static struct clk_hw_omap timer3_fck_hw = {
+        .hw     = {
+                .clk    = &timer3_fck,
+        },
+        .clkdm_name     = "l4ls_clkdm",
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
+static struct clk timer4_fck;
+static struct clk_hw_omap timer4_fck_hw = {
+        .hw     = {
+                .clk    = &timer4_fck,
+        },
+        .clkdm_name     = "l4ls_clkdm",
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
+static struct clk timer5_fck;
+static struct clk_hw_omap timer5_fck_hw = {
+        .hw     = {
+                .clk    = &timer5_fck,
+        },
+        .clkdm_name     = "l4ls_clkdm",
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
+static struct clk timer6_fck;
+static struct clk_hw_omap timer6_fck_hw = {
+        .hw     = {
+                .clk    = &timer6_fck,
+        },
+        .clkdm_name     = "l4ls_clkdm",
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
+static struct clk timer7_fck;
+static struct clk_hw_omap timer7_fck_hw = {
+        .hw     = {
+                .clk    = &timer7_fck,
+        },
+        .clkdm_name     = "l4ls_clkdm",
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
+DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
+                        "dpll_core_m5_ck",
+                        &dpll_core_m5_ck,
+                        0x0,
+                        1, 2);
+static const struct clk_ops cpsw_fck_ops = {
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
+        { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static const char *cpsw_cpts_rft_ck_parents[] = {
+        "dpll_core_m5_ck", "dpll_core_m4_ck",
+};
+static struct clk cpsw_cpts_rft_clk;
+static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
+        .hw     = {
+                .clk    = &cpsw_cpts_rft_clk,
+        },
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .clksel         = cpsw_cpts_rft_clkmux_sel,
+        .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
+        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
+};
+DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
+/* gpio */
+static const char *gpio0_ck_parents[] = {
+        "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
+};
+static const struct clksel gpio0_dbclk_mux_sel[] = {
+        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+        { .parent = &clk_32768_ck, .rates = div_1_1_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const struct clk_ops gpio_fck_ops = {
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+        .init           = &omap2_init_clk_clkdm,
+};
+static struct clk gpio0_dbclk_mux_ck;
+static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
+        .hw     = {
+                .clk    = &gpio0_dbclk_mux_ck,
+        },
+        .clkdm_name     = "l4_wkup_clkdm",
+        .clksel         = gpio0_dbclk_mux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
+DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
+                AM33XX_CM_WKUP_GPIO0_CLKCTRL,
+                AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
+                AM33XX_CM_PER_GPIO1_CLKCTRL,
+                AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
+                AM33XX_CM_PER_GPIO2_CLKCTRL,
+                AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
+                AM33XX_CM_PER_GPIO3_CLKCTRL,
+                AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
+static const char *pruss_ck_parents[] = {
+        "l3_gclk", "dpll_disp_m2_ck",
+};
+static const struct clksel pruss_ocp_clk_mux_sel[] = {
+        { .parent = &l3_gclk, .rates = div_1_0_rates },
+        { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk pruss_ocp_gclk;
+static struct clk_hw_omap pruss_ocp_gclk_hw = {
+        .hw     = {
+                .clk    = &pruss_ocp_gclk,
+        },
+        .clkdm_name     = "pruss_ocp_clkdm",
+        .clksel         = pruss_ocp_clk_mux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_PRUSS_OCP_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
+};
+DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
+static const char *lcd_ck_parents[] = {
+        "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
+};
+static const struct clksel lcd_clk_mux_sel[] = {
+        { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static struct clk lcd_gclk;
+static struct clk_hw_omap lcd_gclk_hw = {
+        .hw     = {
+                .clk    = &lcd_gclk,
+        },
+        .clkdm_name     = "lcdc_clkdm",
+        .clksel         = lcd_clk_mux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
+DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
+static const char *gfx_ck_parents[] = {
+        "dpll_core_m4_ck", "dpll_per_m2_ck",
+};
+static const struct clksel gfx_clksel_sel[] = {
+        { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk gfx_fclk_clksel_ck;
+static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
+        .hw     = {
+                .clk    = &gfx_fclk_clksel_ck,
+        },
+        .clksel         = gfx_clksel_sel,
+        .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
+        .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
+};
+DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
+static const struct clk_div_table div_1_0_2_1_rates[] = {
+        { .div = 1, .val = 0, },
+        { .div = 2, .val = 1, },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
+                         &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
+                         AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
+                         0x0, div_1_0_2_1_rates, NULL);
+static const char *sysclkout_ck_parents[] = {
+        "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
+        "lcd_gclk",
+};
+static const struct clksel sysclkout_pre_sel[] = {
+        { .parent = &clk_32768_ck, .rates = div_1_0_rates },
+        { .parent = &l3_gclk, .rates = div_1_1_rates },
+        { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
+        { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
+        { .parent = &lcd_gclk, .rates = div_1_4_rates },
+        { .parent = NULL },
+};
+static struct clk sysclkout_pre_ck;
+static struct clk_hw_omap sysclkout_pre_ck_hw = {
+        .hw     = {
+                .clk    = &sysclkout_pre_ck,
+        },
+        .clksel         = sysclkout_pre_sel,
+        .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
+        .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
+};
+DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
+/* Divide by 8 clock rates with default clock is 1/1*/
+static const struct clk_div_table div8_rates[] = {
+        { .div = 1, .val = 0, },
+        { .div = 2, .val = 1, },
+        { .div = 3, .val = 2, },
+        { .div = 4, .val = 3, },
+        { .div = 5, .val = 4, },
+        { .div = 6, .val = 5, },
+        { .div = 7, .val = 6, },
+        { .div = 8, .val = 7, },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
+                         0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
+                         AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
+DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
+                AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
+static const char *wdt_ck_parents[] = {
+        "clk_rc32k_ck", "clkdiv32k_ick",
+};
+static const struct clksel wdt_clkmux_sel[] = {
+        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static struct clk wdt1_fck;
+static struct clk_hw_omap wdt1_fck_hw = {
+        .hw     = {
+                .clk    = &wdt1_fck,
+        },
+        .clkdm_name     = "l4_wkup_clkdm",
+        .clksel         = wdt_clkmux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+};
+DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
+/*
+ * clkdev
+ */
+static struct omap_clk am33xx_clks[] = {
+        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
+        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
+        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck,      CK_AM33XX),
+        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck,      CK_AM33XX),
+        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck,      CK_AM33XX),
+        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_AM33XX),
+        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
+        CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
+        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,  CK_AM33XX),
+        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
+        CLK("cpu0",     NULL,                   &dpll_mpu_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
+        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
+        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,  CK_AM33XX),
+        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
+        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck,    CK_AM33XX),
+        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck,   CK_AM33XX),
+        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
+        CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
+        CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck,  CK_AM33XX),
+        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
+        CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
+        CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
+        CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
+        CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),
+        CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
+        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
+        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck,    CK_AM33XX),
+        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck,    CK_AM33XX),
+        CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
+        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
+        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
+        CLK(NULL,       "timer1_fck",           &timer1_fck,    CK_AM33XX),
+        CLK(NULL,       "timer2_fck",           &timer2_fck,    CK_AM33XX),
+        CLK(NULL,       "timer3_fck",           &timer3_fck,    CK_AM33XX),
+        CLK(NULL,       "timer4_fck",           &timer4_fck,    CK_AM33XX),
+        CLK(NULL,       "timer5_fck",           &timer5_fck,    CK_AM33XX),
+        CLK(NULL,       "timer6_fck",           &timer6_fck,    CK_AM33XX),
+        CLK(NULL,       "timer7_fck",           &timer7_fck,    CK_AM33XX),
+        CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
+        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
+        CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
+        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk,   CK_AM33XX),
+        CLK(NULL,       "l3_gclk",              &l3_gclk,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,  CK_AM33XX),
+        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk,     CK_AM33XX),
+        CLK(NULL,       "l3s_gclk",             &l3s_gclk,      CK_AM33XX),
+        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk,     CK_AM33XX),
+        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk,     CK_AM33XX),
+        CLK(NULL,       "clk_24mhz",            &clk_24mhz,     CK_AM33XX),
+        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck, CK_AM33XX),
+        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk,      CK_AM33XX),
+        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk,     CK_AM33XX),
+        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck,    CK_AM33XX),
+        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,   CK_AM33XX),
+        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,   CK_AM33XX),
+        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,   CK_AM33XX),
+        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,   CK_AM33XX),
+        CLK(NULL,       "lcd_gclk",             &lcd_gclk,      CK_AM33XX),
+        CLK(NULL,       "mmc_clk",              &mmc_clk,       CK_AM33XX),
+        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck,    CK_AM33XX),
+        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck,        CK_AM33XX),
+        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
+        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck,        CK_AM33XX),
+        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick, CK_AM33XX),
+        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck,  CK_AM33XX),
+};
+static const char *enable_init_clks[] = {
+        "dpll_ddr_m2_ck",
+        "dpll_mpu_m2_ck",
+        "l3_gclk",
+        "l4hs_gclk",
+        "l4fw_gclk",
+        "l4ls_gclk",
+};
+int __init am33xx_clk_init(void)
+{
+        struct omap_clk *c;
+        u32 cpu_clkflg;
+        if (soc_is_am33xx()) {
+                cpu_mask = RATE_IN_AM33XX;
+                cpu_clkflg = CK_AM33XX;
+        }
+        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        if (!__clk_init(NULL, c->lk.clk))
+                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
+                }
+        }
+        omap2_clk_disable_autoidle_all();
+        omap2_clk_enable_init_clocks(enable_init_clks,
+                                     ARRAY_SIZE(enable_init_clks));
+        /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+         *    physically present, in such a case HWMOD enabling of
+         *    clock would be failure with default parent. And timer
+         *    probe thinks clock is already enabled, this leads to
+         *    crash upon accessing timer 3 & 6 registers in probe.
+         *    Fix by setting parent of both these timers to master
+         *    oscillator clock.
+         */
+        clk_set_parent(&timer3_fck, &sys_clkin_ck);
+        clk_set_parent(&timer6_fck, &sys_clkin_ck);
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
new file mode 100644
index 000000000000..bdf39481fbd6
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -0,0 +1,3595 @@
+/*
+ * OMAP3 clock data
+ *
+ * Copyright (C) 2007-2012 Texas Instruments, Inc.
+ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+ * DPLL bypass clock support added by Roman Tereshonkov
+ *
+ */
+/*
+ * Virtual clocks are introduced as convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock3xxx.h"
+#include "clock34xx.h"
+#include "clock36xx.h"
+#include "clock3517.h"
+#include "cm3xxx.h"
+#include "cm-regbits-34xx.h"
+#include "prm3xxx.h"
+#include "prm-regbits-34xx.h"
+#include "control.h"
+/*
+ * clocks
+ */
+#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
+/* Maximum DPLL multiplier, divider values for OMAP3 */
+#define OMAP3_MAX_DPLL_MULT             2047
+#define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
+#define OMAP3_MAX_DPLL_DIV              128
+DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
+DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
+DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
+DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
+DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
+DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
+static const char *osc_sys_ck_parent_names[] = {
+        "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
+        "virt_38_4m_ck", "virt_16_8m_ck",
+};
+DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
+               OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
+               OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
+DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
+                   OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
+                   OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+static struct dpll_data dpll3_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll3_ck;
+static const char *dpll3_ck_parent_names[] = {
+        "sys_ck",
+};
+static const struct clk_ops dpll3_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+};
+static struct clk_hw_omap dpll3_ck_hw = {
+        .hw = {
+                .clk = &dpll3_ck,
+        },
+        .ops            = &clkhwops_omap3_dpll,
+        .dpll_data      = &dpll3_dd,
+        .clkdm_name     = "dpll3_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
+DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
+                   OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+                   OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
+                   OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk core_ck;
+static const char *core_ck_parent_names[] = {
+        "dpll3_m2_ck",
+};
+static const struct clk_ops core_ck_ops = {};
+DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
+DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
+DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
+                   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+                   OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
+                   OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+                   OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk security_l4_ick2;
+static const char *security_l4_ick2_parent_names[] = {
+        "l4_ick",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
+DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
+static struct clk aes1_ick;
+static const char *aes1_ick_parent_names[] = {
+        "security_l4_ick2",
+};
+static const struct clk_ops aes1_ick_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+};
+static struct clk_hw_omap aes1_ick_hw = {
+        .hw = {
+                .clk = &aes1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
+};
+DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
+static struct clk core_l4_ick;
+static const struct clk_ops core_l4_ick_ops = {
+        .init           = &omap2_init_clk_clkdm,
+};
+DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
+DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
+static struct clk aes2_ick;
+static const char *aes2_ick_parent_names[] = {
+        "core_l4_ick",
+};
+static const struct clk_ops aes2_ick_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+};
+static struct clk_hw_omap aes2_ick_hw = {
+        .hw = {
+                .clk = &aes2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk dpll1_fck;
+static struct dpll_data dpll1_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll1_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll1_ck;
+static const struct clk_ops dpll1_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap3_dpll_recalc,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .round_rate     = &omap2_dpll_round_rate,
+};
+static struct clk_hw_omap dpll1_ck_hw = {
+        .hw = {
+                .clk = &dpll1_ck,
+        },
+        .ops            = &clkhwops_omap3_dpll,
+        .dpll_data      = &dpll1_dd,
+        .clkdm_name     = "dpll1_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
+DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
+DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
+                   OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+                   OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
+                   OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk mpu_ck;
+static const char *mpu_ck_parent_names[] = {
+        "dpll1_x2m2_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
+DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
+DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
+                   OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+                   OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
+                   0x0, NULL);
+static struct clk cam_ick;
+static struct clk_hw_omap cam_ick_hw = {
+        .hw = {
+                .clk = &cam_ick,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+};
+DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static struct dpll_data dpll4_dd;
+static struct dpll_data dpll4_dd_34xx __initdata = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct dpll_data dpll4_dd_3630 __initdata = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
+        .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
+        .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .flags          = DPLL_J_TYPE
+};
+static struct clk dpll4_ck;
+static const struct clk_ops dpll4_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap3_dpll_recalc,
+        .set_rate       = &omap3_dpll4_set_rate,
+        .round_rate     = &omap2_dpll_round_rate,
+};
+static struct clk_hw_omap dpll4_ck_hw = {
+        .hw = {
+                .clk = &dpll4_ck,
+        },
+        .dpll_data      = &dpll4_dd,
+        .ops            = &clkhwops_omap3_dpll,
+        .clkdm_name     = "dpll4_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
+DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+                   OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dpll4_m5x2_ck;
+static const char *dpll4_m5x2_ck_parent_names[] = {
+        "dpll4_m5_ck",
+};
+static const struct clk_ops dpll4_m5x2_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap3_clkoutx2_recalc,
+};
+static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
+        .disable        = &omap2_dflt_clk_disable,
+        .recalc_rate    = &omap3_clkoutx2_recalc,
+};
+static struct clk_hw_omap dpll4_m5x2_ck_hw = {
+        .hw = {
+                .clk = &dpll4_m5x2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
+static struct clk dpll4_m5x2_ck_3630 = {
+        .name           = "dpll4_m5x2_ck",
+        .hw             = &dpll4_m5x2_ck_hw.hw,
+        .parent_names   = dpll4_m5x2_ck_parent_names,
+        .num_parents    = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
+        .ops            = &dpll4_m5x2_ck_3630_ops,
+};
+static struct clk cam_mclk;
+static const char *cam_mclk_parent_names[] = {
+        "dpll4_m5x2_ck",
+};
+static struct clk_hw_omap cam_mclk_hw = {
+        .hw = {
+                .clk = &cam_mclk,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+};
+DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);
+static const struct clksel_rate clkout2_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
+                   OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+                   OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dpll4_m2x2_ck;
+static const char *dpll4_m2x2_ck_parent_names[] = {
+        "dpll4_m2_ck",
+};
+static struct clk_hw_omap dpll4_m2x2_ck_hw = {
+        .hw = {
+                .clk = &dpll4_m2x2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
+static struct clk dpll4_m2x2_ck_3630 = {
+        .name           = "dpll4_m2x2_ck",
+        .hw             = &dpll4_m2x2_ck_hw.hw,
+        .parent_names   = dpll4_m2x2_ck_parent_names,
+        .num_parents    = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
+        .ops            = &dpll4_m5x2_ck_3630_ops,
+};
+static struct clk omap_96m_alwon_fck;
+static const char *omap_96m_alwon_fck_parent_names[] = {
+        "dpll4_m2x2_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
+DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
+                  core_ck_ops);
+static struct clk cm_96m_fck;
+static const char *cm_96m_fck_parent_names[] = {
+        "omap_96m_alwon_fck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
+DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+                   OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dpll4_m3x2_ck;
+static const char *dpll4_m3x2_ck_parent_names[] = {
+        "dpll4_m3_ck",
+};
+static struct clk_hw_omap dpll4_m3x2_ck_hw = {
+        .hw = {
+                .clk = &dpll4_m3x2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
+static struct clk dpll4_m3x2_ck_3630 = {
+        .name           = "dpll4_m3x2_ck",
+        .hw             = &dpll4_m3x2_ck_hw.hw,
+        .parent_names   = dpll4_m3x2_ck_parent_names,
+        .num_parents    = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
+        .ops            = &dpll4_m5x2_ck_3630_ops,
+};
+static const char *omap_54m_fck_parent_names[] = {
+        "dpll4_m3x2_ck", "sys_altclk",
+};
+DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
+               OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
+               OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
+static const struct clksel clkout2_src_clksel[] = {
+        { .parent = &core_ck, .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
+        { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
+        { .parent = NULL },
+};
+static const char *clkout2_src_ck_parent_names[] = {
+        "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
+};
+static const struct clk_ops clkout2_src_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
+                         clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
+                         OMAP3430_CLKOUT2SOURCE_MASK,
+                         OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
+                         NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate omap_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel omap_48m_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
+        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+        { .parent = NULL },
+};
+static const char *omap_48m_fck_parent_names[] = {
+        "cm_96m_fck", "sys_altclk",
+};
+static struct clk omap_48m_fck;
+static const struct clk_ops omap_48m_fck_ops = {
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+static struct clk_hw_omap omap_48m_fck_hw = {
+        .hw = {
+                .clk = &omap_48m_fck,
+        },
+        .clksel         = omap_48m_clksel,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
+};
+DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
+DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
+static struct clk core_12m_fck;
+static const char *core_12m_fck_parent_names[] = {
+        "omap_12m_fck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
+DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
+static struct clk core_48m_fck;
+static const char *core_48m_fck_parent_names[] = {
+        "omap_48m_fck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
+DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
+static const char *omap_96m_fck_parent_names[] = {
+        "cm_96m_fck", "sys_ck",
+};
+DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
+               OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+               OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
+static struct clk core_96m_fck;
+static const char *core_96m_fck_parent_names[] = {
+        "omap_96m_fck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
+DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
+static struct clk core_l3_ick;
+static const char *core_l3_ick_parent_names[] = {
+        "l3_ick",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
+DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
+DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
+static struct clk corex2_fck;
+static const char *corex2_fck_parent_names[] = {
+        "dpll3_m2x2_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
+DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
+static struct clk cpefuse_fck;
+static struct clk_hw_omap cpefuse_fck_hw = {
+        .hw = {
+                .clk = &cpefuse_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk csi2_96m_fck;
+static const char *csi2_96m_fck_parent_names[] = {
+        "core_96m_fck",
+};
+static struct clk_hw_omap csi2_96m_fck_hw = {
+        .hw = {
+                .clk = &csi2_96m_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+};
+DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk d2d_26m_fck;
+static struct clk_hw_omap d2d_26m_fck_hw = {
+        .hw = {
+                .clk = &d2d_26m_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+};
+DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk des1_ick;
+static struct clk_hw_omap des1_ick_hw = {
+        .hw = {
+                .clk = &des1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
+};
+DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
+static struct clk des2_ick;
+static struct clk_hw_omap des2_ick_hw = {
+        .hw = {
+                .clk = &des2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
+                   OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+                   OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dpll2_fck;
+static struct dpll_data dpll2_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll2_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .modes          = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
+                           (1 << DPLL_LOW_POWER_BYPASS)),
+        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll2_ck;
+static struct clk_hw_omap dpll2_ck_hw = {
+        .hw = {
+                .clk = &dpll2_ck,
+        },
+        .ops            = &clkhwops_omap3_dpll,
+        .dpll_data      = &dpll2_dd,
+        .clkdm_name     = "dpll2_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
+DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+                   OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
+                   OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
+                   OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+                   OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dpll3_m3x2_ck;
+static const char *dpll3_m3x2_ck_parent_names[] = {
+        "dpll3_m3_ck",
+};
+static struct clk_hw_omap dpll3_m3x2_ck_hw = {
+        .hw = {
+                .clk = &dpll3_m3x2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll3_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
+static struct clk dpll3_m3x2_ck_3630 = {
+        .name           = "dpll3_m3x2_ck",
+        .hw             = &dpll3_m3x2_ck_hw.hw,
+        .parent_names   = dpll3_m3x2_ck_parent_names,
+        .num_parents    = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
+        .ops            = &dpll4_m5x2_ck_3630_ops,
+};
+DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
+DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+                   OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dpll4_m4x2_ck;
+static const char *dpll4_m4x2_ck_parent_names[] = {
+        "dpll4_m4_ck",
+};
+static struct clk_hw_omap dpll4_m4x2_ck_hw = {
+        .hw = {
+                .clk = &dpll4_m4x2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
+static struct clk dpll4_m4x2_ck_3630 = {
+        .name           = "dpll4_m4x2_ck",
+        .hw             = &dpll4_m4x2_ck_hw.hw,
+        .parent_names   = dpll4_m4x2_ck_parent_names,
+        .num_parents    = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
+        .ops            = &dpll4_m5x2_ck_3630_ops,
+};
+DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+                   OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dpll4_m6x2_ck;
+static const char *dpll4_m6x2_ck_parent_names[] = {
+        "dpll4_m6_ck",
+};
+static struct clk_hw_omap dpll4_m6x2_ck_hw = {
+        .hw = {
+                .clk = &dpll4_m6x2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
+static struct clk dpll4_m6x2_ck_3630 = {
+        .name           = "dpll4_m6x2_ck",
+        .hw             = &dpll4_m6x2_ck_hw.hw,
+        .parent_names   = dpll4_m6x2_ck_parent_names,
+        .num_parents    = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
+        .ops            = &dpll4_m5x2_ck_3630_ops,
+};
+DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
+static struct dpll_data dpll5_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+};
+static struct clk dpll5_ck;
+static struct clk_hw_omap dpll5_ck_hw = {
+        .hw = {
+                .clk = &dpll5_ck,
+        },
+        .ops            = &clkhwops_omap3_dpll,
+        .dpll_data      = &dpll5_dd,
+        .clkdm_name     = "dpll5_clkdm",
+};
+DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
+DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
+                   OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+                   OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk dss1_alwon_fck_3430es1;
+static const char *dss1_alwon_fck_3430es1_parent_names[] = {
+        "dpll4_m4x2_ck",
+};
+static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
+        .hw = {
+                .clk = &dss1_alwon_fck_3430es1,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
+                  aes2_ick_ops);
+static struct clk dss1_alwon_fck_3430es2;
+static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
+        .hw = {
+                .clk = &dss1_alwon_fck_3430es2,
+        },
+        .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
+                  aes2_ick_ops);
+static struct clk dss2_alwon_fck;
+static struct clk_hw_omap dss2_alwon_fck_hw = {
+        .hw = {
+                .clk = &dss2_alwon_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk dss_96m_fck;
+static struct clk_hw_omap dss_96m_fck_hw = {
+        .hw = {
+                .clk = &dss_96m_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
+static struct clk dss_ick_3430es1;
+static struct clk_hw_omap dss_ick_3430es1_hw = {
+        .hw = {
+                .clk = &dss_ick_3430es1,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
+static struct clk dss_ick_3430es2;
+static struct clk_hw_omap dss_ick_3430es2_hw = {
+        .hw = {
+                .clk = &dss_ick_3430es2,
+        },
+        .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
+static struct clk dss_tv_fck;
+static const char *dss_tv_fck_parent_names[] = {
+        "omap_54m_fck",
+};
+static struct clk_hw_omap dss_tv_fck_hw = {
+        .hw = {
+                .clk = &dss_tv_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+};
+DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
+static struct clk emac_fck;
+static const char *emac_fck_parent_names[] = {
+        "rmii_ck",
+};
+static struct clk_hw_omap emac_fck_hw = {
+        .hw = {
+                .clk = &emac_fck,
+        },
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
+};
+DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
+static struct clk ipss_ick;
+static const char *ipss_ick_parent_names[] = {
+        "core_l3_ick",
+};
+static struct clk_hw_omap ipss_ick_hw = {
+        .hw = {
+                .clk = &ipss_ick,
+        },
+        .ops            = &clkhwops_am35xx_ipss_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = AM35XX_EN_IPSS_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
+static struct clk emac_ick;
+static const char *emac_ick_parent_names[] = {
+        "ipss_ick",
+};
+static struct clk_hw_omap emac_ick_hw = {
+        .hw = {
+                .clk = &emac_ick,
+        },
+        .ops            = &clkhwops_am35xx_ipss_module_wait,
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
+static struct clk emu_core_alwon_ck;
+static const char *emu_core_alwon_ck_parent_names[] = {
+        "dpll3_m3x2_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
+DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
+                  core_l4_ick_ops);
+static struct clk emu_mpu_alwon_ck;
+static const char *emu_mpu_alwon_ck_parent_names[] = {
+        "mpu_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
+DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
+static struct clk emu_per_alwon_ck;
+static const char *emu_per_alwon_ck_parent_names[] = {
+        "dpll4_m6x2_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
+DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
+                  core_l4_ick_ops);
+static const char *emu_src_ck_parent_names[] = {
+        "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
+};
+static const struct clksel_rate emu_src_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate emu_src_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate emu_src_per_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel_rate emu_src_mpu_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 },
+};
+static const struct clksel emu_src_clksel[] = {
+        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
+        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
+        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
+        { .parent = NULL },
+};
+static const struct clk_ops emu_src_ck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+static struct clk emu_src_ck;
+static struct clk_hw_omap emu_src_ck_hw = {
+        .hw = {
+                .clk = &emu_src_ck,
+        },
+        .clksel         = emu_src_clksel,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
+        .clkdm_name     = "emu_clkdm",
+};
+DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
+DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+                   OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk fac_ick;
+static struct clk_hw_omap fac_ick_hw = {
+        .hw = {
+                .clk = &fac_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk fshostusb_fck;
+static const char *fshostusb_fck_parent_names[] = {
+        "core_48m_fck",
+};
+static struct clk_hw_omap fshostusb_fck_hw = {
+        .hw = {
+                .clk = &fshostusb_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk gfx_l3_ck;
+static struct clk_hw_omap gfx_l3_ck_hw = {
+        .hw = {
+                .clk = &gfx_l3_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+};
+DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
+DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
+                   OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+                   OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk gfx_cg1_ck;
+static const char *gfx_cg1_ck_parent_names[] = {
+        "gfx_l3_fck",
+};
+static struct clk_hw_omap gfx_cg1_ck_hw = {
+        .hw = {
+                .clk = &gfx_cg1_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+};
+DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
+static struct clk gfx_cg2_ck;
+static struct clk_hw_omap gfx_cg2_ck_hw = {
+        .hw = {
+                .clk = &gfx_cg2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+};
+DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
+static struct clk gfx_l3_ick;
+static const char *gfx_l3_ick_parent_names[] = {
+        "gfx_l3_ck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
+DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
+static struct clk wkup_32k_fck;
+static const char *wkup_32k_fck_parent_names[] = {
+        "omap_32k_fck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
+static struct clk gpio1_dbck;
+static const char *gpio1_dbck_parent_names[] = {
+        "wkup_32k_fck",
+};
+static struct clk_hw_omap gpio1_dbck_hw = {
+        .hw = {
+                .clk = &gpio1_dbck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
+static struct clk wkup_l4_ick;
+DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
+static struct clk gpio1_ick;
+static const char *gpio1_ick_parent_names[] = {
+        "wkup_l4_ick",
+};
+static struct clk_hw_omap gpio1_ick_hw = {
+        .hw = {
+                .clk = &gpio1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
+static struct clk per_32k_alwon_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
+DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
+                  core_l4_ick_ops);
+static struct clk gpio2_dbck;
+static const char *gpio2_dbck_parent_names[] = {
+        "per_32k_alwon_fck",
+};
+static struct clk_hw_omap gpio2_dbck_hw = {
+        .hw = {
+                .clk = &gpio2_dbck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
+static struct clk per_l4_ick;
+DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
+DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
+static struct clk gpio2_ick;
+static const char *gpio2_ick_parent_names[] = {
+        "per_l4_ick",
+};
+static struct clk_hw_omap gpio2_ick_hw = {
+        .hw = {
+                .clk = &gpio2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk gpio3_dbck;
+static struct clk_hw_omap gpio3_dbck_hw = {
+        .hw = {
+                .clk = &gpio3_dbck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
+static struct clk gpio3_ick;
+static struct clk_hw_omap gpio3_ick_hw = {
+        .hw = {
+                .clk = &gpio3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk gpio4_dbck;
+static struct clk_hw_omap gpio4_dbck_hw = {
+        .hw = {
+                .clk = &gpio4_dbck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
+static struct clk gpio4_ick;
+static struct clk_hw_omap gpio4_ick_hw = {
+        .hw = {
+                .clk = &gpio4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk gpio5_dbck;
+static struct clk_hw_omap gpio5_dbck_hw = {
+        .hw = {
+                .clk = &gpio5_dbck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
+static struct clk gpio5_ick;
+static struct clk_hw_omap gpio5_ick_hw = {
+        .hw = {
+                .clk = &gpio5_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk gpio6_dbck;
+static struct clk_hw_omap gpio6_dbck_hw = {
+        .hw = {
+                .clk = &gpio6_dbck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
+static struct clk gpio6_ick;
+static struct clk_hw_omap gpio6_ick_hw = {
+        .hw = {
+                .clk = &gpio6_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk gpmc_fck;
+static struct clk_hw_omap gpmc_fck_hw = {
+        .hw = {
+                .clk = &gpmc_fck,
+        },
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
+static const struct clksel omap343x_gpt_clksel[] = {
+        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck, .rates = gpt_sys_rates },
+        { .parent = NULL },
+};
+static const char *gpt10_fck_parent_names[] = {
+        "omap_32k_fck", "sys_ck",
+};
+DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT10_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt10_ick;
+static struct clk_hw_omap gpt10_ick_hw = {
+        .hw = {
+                .clk = &gpt10_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT11_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt11_ick;
+static struct clk_hw_omap gpt11_ick_hw = {
+        .hw = {
+                .clk = &gpt11_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk gpt12_fck;
+static const char *gpt12_fck_parent_names[] = {
+        "secure_32k_fck",
+};
+DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
+static struct clk gpt12_ick;
+static struct clk_hw_omap gpt12_ick_hw = {
+        .hw = {
+                .clk = &gpt12_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT1_MASK,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt1_ick;
+static struct clk_hw_omap gpt1_ick_hw = {
+        .hw = {
+                .clk = &gpt1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT2_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt2_ick;
+static struct clk_hw_omap gpt2_ick_hw = {
+        .hw = {
+                .clk = &gpt2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT3_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt3_ick;
+static struct clk_hw_omap gpt3_ick_hw = {
+        .hw = {
+                .clk = &gpt3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT4_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt4_ick;
+static struct clk_hw_omap gpt4_ick_hw = {
+        .hw = {
+                .clk = &gpt4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT5_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt5_ick;
+static struct clk_hw_omap gpt5_ick_hw = {
+        .hw = {
+                .clk = &gpt5_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT6_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt6_ick;
+static struct clk_hw_omap gpt6_ick_hw = {
+        .hw = {
+                .clk = &gpt6_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT7_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt7_ick;
+static struct clk_hw_omap gpt7_ick_hw = {
+        .hw = {
+                .clk = &gpt7_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT8_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt8_ick;
+static struct clk_hw_omap gpt8_ick_hw = {
+        .hw = {
+                .clk = &gpt8_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_GPT9_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
+                         gpt10_fck_parent_names, clkout2_src_ck_ops);
+static struct clk gpt9_ick;
+static struct clk_hw_omap gpt9_ick_hw = {
+        .hw = {
+                .clk = &gpt9_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk hdq_fck;
+static const char *hdq_fck_parent_names[] = {
+        "core_12m_fck",
+};
+static struct clk_hw_omap hdq_fck_hw = {
+        .hw = {
+                .clk = &hdq_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
+static struct clk hdq_ick;
+static struct clk_hw_omap hdq_ick_hw = {
+        .hw = {
+                .clk = &hdq_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk hecc_ck;
+static struct clk_hw_omap hecc_ck_hw = {
+        .hw = {
+                .clk = &hecc_ck,
+        },
+        .ops            = &clkhwops_am35xx_ipss_module_wait,
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk hsotgusb_fck_am35xx;
+static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
+        .hw = {
+                .clk = &hsotgusb_fck_am35xx,
+        },
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk hsotgusb_ick_3430es1;
+static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
+        .hw = {
+                .clk = &hsotgusb_ick_3430es1,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
+static struct clk hsotgusb_ick_3430es2;
+static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
+        .hw = {
+                .clk = &hsotgusb_ick_3430es2,
+        },
+        .ops            = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
+static struct clk hsotgusb_ick_am35xx;
+static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
+        .hw = {
+                .clk = &hsotgusb_ick_am35xx,
+        },
+        .ops            = &clkhwops_am35xx_ipss_module_wait,
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
+static struct clk i2c1_fck;
+static struct clk_hw_omap i2c1_fck_hw = {
+        .hw = {
+                .clk = &i2c1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk i2c1_ick;
+static struct clk_hw_omap i2c1_ick_hw = {
+        .hw = {
+                .clk = &i2c1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk i2c2_fck;
+static struct clk_hw_omap i2c2_fck_hw = {
+        .hw = {
+                .clk = &i2c2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk i2c2_ick;
+static struct clk_hw_omap i2c2_ick_hw = {
+        .hw = {
+                .clk = &i2c2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk i2c3_fck;
+static struct clk_hw_omap i2c3_fck_hw = {
+        .hw = {
+                .clk = &i2c3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk i2c3_ick;
+static struct clk_hw_omap i2c3_ick_hw = {
+        .hw = {
+                .clk = &i2c3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk icr_ick;
+static struct clk_hw_omap icr_ick_hw = {
+        .hw = {
+                .clk = &icr_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk iva2_ck;
+static const char *iva2_ck_parent_names[] = {
+        "dpll2_m2_ck",
+};
+static struct clk_hw_omap iva2_ck_hw = {
+        .hw = {
+                .clk = &iva2_ck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+        .clkdm_name     = "iva2_clkdm",
+};
+DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
+static struct clk mad2d_ick;
+static struct clk_hw_omap mad2d_ick_hw = {
+        .hw = {
+                .clk = &mad2d_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+};
+DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
+static struct clk mailboxes_ick;
+static struct clk_hw_omap mailboxes_ick_hw = {
+        .hw = {
+                .clk = &mailboxes_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel mcbsp_15_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp1_fck_parent_names[] = {
+        "core_96m_fck", "mcbsp_clks",
+};
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
+                         OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                         OMAP2_MCBSP1_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, clkout2_src_ck_ops);
+static struct clk mcbsp1_ick;
+static struct clk_hw_omap mcbsp1_ick_hw = {
+        .hw = {
+                .clk = &mcbsp1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk per_96m_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
+DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
+static const struct clksel mcbsp_234_clksel[] = {
+        { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp2_fck_parent_names[] = {
+        "per_96m_fck", "mcbsp_clks",
+};
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
+                         OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+                         OMAP2_MCBSP2_CLKS_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
+                         mcbsp2_fck_parent_names, clkout2_src_ck_ops);
+static struct clk mcbsp2_ick;
+static struct clk_hw_omap mcbsp2_ick_hw = {
+        .hw = {
+                .clk = &mcbsp2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
+                         OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+                         OMAP2_MCBSP3_CLKS_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
+                         mcbsp2_fck_parent_names, clkout2_src_ck_ops);
+static struct clk mcbsp3_ick;
+static struct clk_hw_omap mcbsp3_ick_hw = {
+        .hw = {
+                .clk = &mcbsp3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
+                         OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+                         OMAP2_MCBSP4_CLKS_MASK,
+                         OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+                         OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
+                         mcbsp2_fck_parent_names, clkout2_src_ck_ops);
+static struct clk mcbsp4_ick;
+static struct clk_hw_omap mcbsp4_ick_hw = {
+        .hw = {
+                .clk = &mcbsp4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
+                         OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+                         OMAP2_MCBSP5_CLKS_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
+                         mcbsp1_fck_parent_names, clkout2_src_ck_ops);
+static struct clk mcbsp5_ick;
+static struct clk_hw_omap mcbsp5_ick_hw = {
+        .hw = {
+                .clk = &mcbsp5_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk mcspi1_fck;
+static struct clk_hw_omap mcspi1_fck_hw = {
+        .hw = {
+                .clk = &mcspi1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk mcspi1_ick;
+static struct clk_hw_omap mcspi1_ick_hw = {
+        .hw = {
+                .clk = &mcspi1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk mcspi2_fck;
+static struct clk_hw_omap mcspi2_fck_hw = {
+        .hw = {
+                .clk = &mcspi2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk mcspi2_ick;
+static struct clk_hw_omap mcspi2_ick_hw = {
+        .hw = {
+                .clk = &mcspi2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk mcspi3_fck;
+static struct clk_hw_omap mcspi3_fck_hw = {
+        .hw = {
+                .clk = &mcspi3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk mcspi3_ick;
+static struct clk_hw_omap mcspi3_ick_hw = {
+        .hw = {
+                .clk = &mcspi3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk mcspi4_fck;
+static struct clk_hw_omap mcspi4_fck_hw = {
+        .hw = {
+                .clk = &mcspi4_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk mcspi4_ick;
+static struct clk_hw_omap mcspi4_ick_hw = {
+        .hw = {
+                .clk = &mcspi4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk mmchs1_fck;
+static struct clk_hw_omap mmchs1_fck_hw = {
+        .hw = {
+                .clk = &mmchs1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk mmchs1_ick;
+static struct clk_hw_omap mmchs1_ick_hw = {
+        .hw = {
+                .clk = &mmchs1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk mmchs2_fck;
+static struct clk_hw_omap mmchs2_fck_hw = {
+        .hw = {
+                .clk = &mmchs2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk mmchs2_ick;
+static struct clk_hw_omap mmchs2_ick_hw = {
+        .hw = {
+                .clk = &mmchs2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk mmchs3_fck;
+static struct clk_hw_omap mmchs3_fck_hw = {
+        .hw = {
+                .clk = &mmchs3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk mmchs3_ick;
+static struct clk_hw_omap mmchs3_ick_hw = {
+        .hw = {
+                .clk = &mmchs3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk modem_fck;
+static struct clk_hw_omap modem_fck_hw = {
+        .hw = {
+                .clk = &modem_fck,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+};
+DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk mspro_fck;
+static struct clk_hw_omap mspro_fck_hw = {
+        .hw = {
+                .clk = &mspro_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
+static struct clk mspro_ick;
+static struct clk_hw_omap mspro_ick_hw = {
+        .hw = {
+                .clk = &mspro_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk omap_192m_alwon_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
+DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
+                  core_ck_ops);
+static struct clk omap_32ksync_ick;
+static struct clk_hw_omap omap_32ksync_ick_hw = {
+        .hw = {
+                .clk = &omap_32ksync_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
+static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_36XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_36XX },
+        { .div = 0 }
+};
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+        { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
+        { .parent = NULL }
+};
+static struct clk omap_96m_alwon_fck_3630;
+static const char *omap_96m_alwon_fck_3630_parent_names[] = {
+        "omap_192m_alwon_fck",
+};
+static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
+        .set_rate       = &omap2_clksel_set_rate,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
+        .hw = {
+                .clk = &omap_96m_alwon_fck_3630,
+        },
+        .clksel         = omap_96m_alwon_fck_clksel,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
+};
+static struct clk omap_96m_alwon_fck_3630 = {
+        .name   = "omap_96m_alwon_fck",
+        .hw     = &omap_96m_alwon_fck_3630_hw.hw,
+        .parent_names   = omap_96m_alwon_fck_3630_parent_names,
+        .num_parents    = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
+        .ops    = &omap_96m_alwon_fck_3630_ops,
+};
+static struct clk omapctrl_ick;
+static struct clk_hw_omap omapctrl_ick_hw = {
+        .hw = {
+                .clk = &omapctrl_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
+DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+                   OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+                   OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk per_48m_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
+DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
+static struct clk security_l3_ick;
+DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
+DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
+static struct clk pka_ick;
+static const char *pka_ick_parent_names[] = {
+        "security_l3_ick",
+};
+static struct clk_hw_omap pka_ick_hw = {
+        .hw = {
+                .clk = &pka_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
+};
+DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
+DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
+                   OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+                   OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
+                   CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk rng_ick;
+static struct clk_hw_omap rng_ick_hw = {
+        .hw = {
+                .clk = &rng_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
+};
+DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
+static struct clk sad2d_ick;
+static struct clk_hw_omap sad2d_ick_hw = {
+        .hw = {
+                .clk = &sad2d_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+};
+DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
+static struct clk sdrc_ick;
+static struct clk_hw_omap sdrc_ick_hw = {
+        .hw = {
+                .clk = &sdrc_ick,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
+static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 2, .val = 5, .flags = RATE_IN_36XX },
+        { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate sgx_96m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate sgx_192m_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_36XX },
+        { .div = 0 }
+};
+static const struct clksel_rate sgx_corex2_rates[] = {
+        { .div = 3, .val = 6, .flags = RATE_IN_36XX },
+        { .div = 5, .val = 7, .flags = RATE_IN_36XX },
+        { .div = 0 }
+};
+static const struct clksel sgx_clksel[] = {
+        { .parent = &core_ck, .rates = sgx_core_rates },
+        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+        { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
+        { .parent = &corex2_fck, .rates = sgx_corex2_rates },
+        { .parent = NULL },
+};
+static const char *sgx_fck_parent_names[] = {
+        "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
+};
+static struct clk sgx_fck;
+static const struct clk_ops sgx_fck_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
+                         OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+                         OMAP3430ES2_CLKSEL_SGX_MASK,
+                         OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+                         OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
+                         &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
+static struct clk sgx_ick;
+static struct clk_hw_omap sgx_ick_hw = {
+        .hw = {
+                .clk = &sgx_ick,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
+        .clkdm_name     = "sgx_clkdm",
+};
+DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
+static struct clk sha11_ick;
+static struct clk_hw_omap sha11_ick_hw = {
+        .hw = {
+                .clk = &sha11_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
+};
+DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
+static struct clk sha12_ick;
+static struct clk_hw_omap sha12_ick_hw = {
+        .hw = {
+                .clk = &sha12_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk sr1_fck;
+static struct clk_hw_omap sr1_fck_hw = {
+        .hw = {
+                .clk = &sr1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk sr2_fck;
+static struct clk_hw_omap sr2_fck_hw = {
+        .hw = {
+                .clk = &sr2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
+static struct clk sr_l4_ick;
+DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
+DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
+static struct clk ssi_l4_ick;
+DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
+DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
+static struct clk ssi_ick_3430es1;
+static const char *ssi_ick_3430es1_parent_names[] = {
+        "ssi_l4_ick",
+};
+static struct clk_hw_omap ssi_ick_3430es1_hw = {
+        .hw = {
+                .clk = &ssi_ick_3430es1,
+        },
+        .ops            = &clkhwops_iclk,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
+static struct clk ssi_ick_3430es2;
+static struct clk_hw_omap ssi_ick_3430es2_hw = {
+        .hw = {
+                .clk = &ssi_ick_3430es2,
+        },
+        .ops            = &clkhwops_omap3430es2_iclk_ssi_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel ssi_ssr_clksel[] = {
+        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+        { .parent = NULL },
+};
+static const char *ssi_ssr_fck_3430es1_parent_names[] = {
+        "corex2_fck",
+};
+static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
+                         ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_SSI_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP3430_EN_SSI_SHIFT,
+                         NULL, ssi_ssr_fck_3430es1_parent_names,
+                         ssi_ssr_fck_3430es1_ops);
+DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
+                         ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+                         OMAP3430_CLKSEL_SSI_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+                         OMAP3430_EN_SSI_SHIFT,
+                         NULL, ssi_ssr_fck_3430es1_parent_names,
+                         ssi_ssr_fck_3430es1_ops);
+DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
+                        &ssi_ssr_fck_3430es1, 0x0, 1, 2);
+DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
+                        &ssi_ssr_fck_3430es2, 0x0, 1, 2);
+static struct clk sys_clkout1;
+static const char *sys_clkout1_parent_names[] = {
+        "osc_sys_ck",
+};
+static struct clk_hw_omap sys_clkout1_hw = {
+        .hw = {
+                .clk = &sys_clkout1,
+        },
+        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
+};
+DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
+DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
+                   OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
+                   OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
+               OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+               OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
+                   OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+                   OMAP3430_CLKSEL_TRACECLK_SHIFT,
+                   OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+static struct clk ts_fck;
+static struct clk_hw_omap ts_fck_hw = {
+        .hw = {
+                .clk = &ts_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
+static struct clk uart1_fck;
+static struct clk_hw_omap uart1_fck_hw = {
+        .hw = {
+                .clk = &uart1_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk uart1_ick;
+static struct clk_hw_omap uart1_ick_hw = {
+        .hw = {
+                .clk = &uart1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk uart2_fck;
+static struct clk_hw_omap uart2_fck_hw = {
+        .hw = {
+                .clk = &uart2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk uart2_ick;
+static struct clk_hw_omap uart2_ick_hw = {
+        .hw = {
+                .clk = &uart2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
+static struct clk uart3_fck;
+static const char *uart3_fck_parent_names[] = {
+        "per_48m_fck",
+};
+static struct clk_hw_omap uart3_fck_hw = {
+        .hw = {
+                .clk = &uart3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
+static struct clk uart3_ick;
+static struct clk_hw_omap uart3_ick_hw = {
+        .hw = {
+                .clk = &uart3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk uart4_fck;
+static struct clk_hw_omap uart4_fck_hw = {
+        .hw = {
+                .clk = &uart4_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
+static struct clk uart4_fck_am35xx;
+static struct clk_hw_omap uart4_fck_am35xx_hw = {
+        .hw = {
+                .clk = &uart4_fck_am35xx,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = AM35XX_EN_UART4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
+static struct clk uart4_ick;
+static struct clk_hw_omap uart4_ick_hw = {
+        .hw = {
+                .clk = &uart4_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
+static struct clk uart4_ick_am35xx;
+static struct clk_hw_omap uart4_ick_am35xx_hw = {
+        .hw = {
+                .clk = &uart4_ick_am35xx,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = AM35XX_EN_UART4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
+static const struct clksel_rate div2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
+        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel usb_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL },
+};
+static const char *usb_l4_ick_parent_names[] = {
+        "l4_ick",
+};
+DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+                         OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+                         OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+                         OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+                         &clkhwops_iclk_wait, usb_l4_ick_parent_names,
+                         ssi_ssr_fck_3430es1_ops);
+static struct clk usbhost_120m_fck;
+static const char *usbhost_120m_fck_parent_names[] = {
+        "dpll5_m2_ck",
+};
+static struct clk_hw_omap usbhost_120m_fck_hw = {
+        .hw = {
+                .clk = &usbhost_120m_fck,
+        },
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+};
+DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
+                  aes2_ick_ops);
+static struct clk usbhost_48m_fck;
+static struct clk_hw_omap usbhost_48m_fck_hw = {
+        .hw = {
+                .clk = &usbhost_48m_fck,
+        },
+        .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+};
+DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
+static struct clk usbhost_ick;
+static struct clk_hw_omap usbhost_ick_hw = {
+        .hw = {
+                .clk = &usbhost_ick,
+        },
+        .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+};
+DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
+static struct clk usbtll_fck;
+static struct clk_hw_omap usbtll_fck_hw = {
+        .hw = {
+                .clk = &usbtll_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
+static struct clk usbtll_ick;
+static struct clk_hw_omap usbtll_ick_hw = {
+        .hw = {
+                .clk = &usbtll_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+};
+DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
+static const struct clksel_rate usim_96m_rates[] = {
+        { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
+        { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel_rate usim_120m_rates[] = {
+        { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+        { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
+        { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
+        { .div = 0 }
+};
+static const struct clksel usim_clksel[] = {
+        { .parent = &omap_96m_fck, .rates = usim_96m_rates },
+        { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
+        { .parent = &sys_ck, .rates = div2_rates },
+        { .parent = NULL },
+};
+static const char *usim_fck_parent_names[] = {
+        "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
+};
+static struct clk usim_fck;
+static const struct clk_ops usim_fck_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+};
+DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+                         OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+                         OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+                         OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
+                         usim_fck_parent_names, usim_fck_ops);
+static struct clk usim_ick;
+static struct clk_hw_omap usim_ick_hw = {
+        .hw = {
+                .clk = &usim_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
+static struct clk vpfe_fck;
+static const char *vpfe_fck_parent_names[] = {
+        "pclk_ck",
+};
+static struct clk_hw_omap vpfe_fck_hw = {
+        .hw = {
+                .clk = &vpfe_fck,
+        },
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
+};
+DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
+static struct clk vpfe_ick;
+static struct clk_hw_omap vpfe_ick_hw = {
+        .hw = {
+                .clk = &vpfe_ick,
+        },
+        .ops            = &clkhwops_am35xx_ipss_module_wait,
+        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+        .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+};
+DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
+static struct clk wdt1_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
+DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
+static struct clk wdt1_ick;
+static struct clk_hw_omap wdt1_ick_hw = {
+        .hw = {
+                .clk = &wdt1_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
+static struct clk wdt2_fck;
+static struct clk_hw_omap wdt2_fck_hw = {
+        .hw = {
+                .clk = &wdt2_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
+static struct clk wdt2_ick;
+static struct clk_hw_omap wdt2_ick_hw = {
+        .hw = {
+                .clk = &wdt2_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
+static struct clk wdt3_fck;
+static struct clk_hw_omap wdt3_fck_hw = {
+        .hw = {
+                .clk = &wdt3_fck,
+        },
+        .ops            = &clkhwops_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
+static struct clk wdt3_ick;
+static struct clk_hw_omap wdt3_ick_hw = {
+        .hw = {
+                .clk = &wdt3_ick,
+        },
+        .ops            = &clkhwops_iclk_wait,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+};
+DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
+/*
+ * clkdev
+ */
+static struct omap_clk omap3xxx_clks[] = {
+        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
+        CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
+        CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
+        CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
+        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
+        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
+        CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
+        CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
+        CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
+        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
+        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
+        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
+        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
+        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
+        CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
+        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
+        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
+        CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
+        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
+        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
+        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
+        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
+        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
+        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
+        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
+        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
+        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
+        CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
+        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
+        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
+        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
+        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
+        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
+        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
+        CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
+        CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
+        CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
+        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
+        CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
+        CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
+        CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
+        CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
+        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
+        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
+        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
+        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
+        CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
+        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
+};
+static const char *enable_init_clks[] = {
+        "sdrc_ick",
+        "gpmc_fck",
+        "omapctrl_ick",
+};
+int __init omap3xxx_clk_init(void)
+{
+        struct omap_clk *c;
+        u32 cpu_clkflg = 0;
+        /*
+         * 3505 must be tested before 3517, since 3517 returns true
+         * for both AM3517 chips and AM3517 family chips, which
+         * includes 3505.  Unfortunately there's no obvious family
+         * test for 3517/3505 :-(
+         */
+        if (soc_is_am35xx()) {
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_AM35XX;
+        } else if (cpu_is_omap3630()) {
+                cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
+                cpu_clkflg = CK_36XX;
+        } else if (cpu_is_ti816x()) {
+                cpu_mask = RATE_IN_TI816X;
+                cpu_clkflg = CK_TI816X;
+        } else if (soc_is_am33xx()) {
+                cpu_mask = RATE_IN_AM33XX;
+        } else if (cpu_is_ti814x()) {
+                cpu_mask = RATE_IN_TI814X;
+        } else if (cpu_is_omap34xx()) {
+                if (omap_rev() == OMAP3430_REV_ES1_0) {
+                        cpu_mask = RATE_IN_3430ES1;
+                        cpu_clkflg = CK_3430ES1;
+                } else {
+                        /*
+                         * Assume that anything that we haven't matched yet
+                         * has 3430ES2-type clocks.
+                         */
+                        cpu_mask = RATE_IN_3430ES2PLUS;
+                        cpu_clkflg = CK_3430ES2PLUS;
+                }
+        } else {
+                WARN(1, "clock: could not identify OMAP3 variant\n");
+        }
+        if (omap3_has_192mhz_clk())
+                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
+        if (cpu_is_omap3630()) {
+                dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
+                dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
+                dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
+                dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
+                dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
+                dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
+        }
+        /*
+         * XXX This type of dynamic rewriting of the clock tree is
+         * deprecated and should be revised soon.
+         */
+        if (cpu_is_omap3630())
+                dpll4_dd = dpll4_dd_3630;
+        else
+                dpll4_dd = dpll4_dd_34xx;
+        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
+             c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        if (!__clk_init(NULL, c->lk.clk))
+                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
+                }
+        omap2_clk_disable_autoidle_all();
+        omap2_clk_enable_init_clocks(enable_init_clks,
+                                     ARRAY_SIZE(enable_init_clks));
+        pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (clk_get_rate(&osc_sys_ck) / 1000000),
+                (clk_get_rate(&osc_sys_ck) / 100000) % 10,
+                (clk_get_rate(&core_ck) / 1000000),
+                (clk_get_rate(&arm_fck) / 1000000));
+        /*
+         * Lock DPLL5 -- here only until other device init code can
+         * handle this
+         */
+        if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
+                omap3_clk_lock_dpll5();
+        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
+        sdrc_ick_p = clk_get(NULL, "sdrc_ick");
+        arm_fck_p = clk_get(NULL, "arm_fck");
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
new file mode 100644
index 000000000000..aa56c3e5bb34
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -0,0 +1,1987 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Mike Turquette (mturquette@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ */
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock44xx.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "cm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+#include "control.h"
+#include "scrm44xx.h"
+/* OMAP4 modulemode control */
+#define OMAP4430_MODULEMODE_HWCTRL_SHIFT                0
+#define OMAP4430_MODULEMODE_SWCTRL_SHIFT                1
+/* Root clocks */
+DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
+DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
+DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
+                OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
+DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
+DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
+DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
+                OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
+DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
+static const char *sys_clkin_ck_parents[] = {
+        "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
+        "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
+        "virt_38400000_ck",
+};
+DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
+               OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
+               OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
+DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
+DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
+DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
+DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
+DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
+/* Module clocks and DPLL outputs */
+static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
+        "sys_clkin_ck", "sys_32k_ck",
+};
+DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
+               NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
+               OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
+DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
+               0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
+               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
+        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
+        .clk_ref        = &abe_dpll_refclk_mux_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static const char *dpll_abe_ck_parents[] = {
+        "abe_dpll_refclk_mux_ck",
+};
+static struct clk dpll_abe_ck;
+static const struct clk_ops dpll_abe_ck_ops = {
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+        .recalc_rate    = &omap4_dpll_regm4xen_recalc,
+        .round_rate     = &omap4_dpll_regm4xen_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .get_parent     = &omap2_init_dpll_parent,
+};
+static struct clk_hw_omap dpll_abe_ck_hw = {
+        .hw = {
+                .clk = &dpll_abe_ck,
+        },
+        .dpll_data      = &dpll_abe_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
+static const char *dpll_abe_x2_ck_parents[] = {
+        "dpll_abe_ck",
+};
+static struct clk dpll_abe_x2_ck;
+static const struct clk_ops dpll_abe_x2_ck_ops = {
+        .recalc_rate    = &omap3_clkoutx2_recalc,
+};
+static struct clk_hw_omap dpll_abe_x2_ck_hw = {
+        .hw = {
+                .clk = &dpll_abe_x2_ck,
+        },
+        .flags          = CLOCK_CLKOUTX2,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .ops            = &clkhwops_omap4_dpllmx,
+};
+DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
+static const struct clk_ops omap_hsdivider_ops = {
+        .set_rate       = &omap2_clksel_set_rate,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
+                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
+DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+                        0x0, 1, 8);
+DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
+                   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
+                   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
+                   OMAP4430_CM1_ABE_AESS_CLKCTRL,
+                   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
+                   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
+                   0x0, NULL);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
+                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
+static const char *core_hsd_byp_clk_mux_ck_parents[] = {
+        "sys_clkin_ck", "dpll_abe_m3x2_ck",
+};
+DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
+               0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
+               OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
+               0x0, NULL);
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
+        .clk_bypass     = &core_hsd_byp_clk_mux_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static const char *dpll_core_ck_parents[] = {
+        "sys_clkin_ck",
+};
+static struct clk dpll_core_ck;
+static const struct clk_ops dpll_core_ck_ops = {
+        .recalc_rate    = &omap3_dpll_recalc,
+        .get_parent     = &omap2_init_dpll_parent,
+};
+static struct clk_hw_omap dpll_core_ck_hw = {
+        .hw = {
+                .clk = &dpll_core_ck,
+        },
+        .dpll_data      = &dpll_core_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
+static const char *dpll_core_x2_ck_parents[] = {
+        "dpll_core_ck",
+};
+static struct clk dpll_core_x2_ck;
+static struct clk_hw_omap dpll_core_x2_ck_hw = {
+        .hw = {
+                .clk = &dpll_core_x2_ck,
+        },
+};
+DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
+                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
+                          OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
+                          OMAP4430_CM_DIV_M2_DPLL_CORE,
+                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
+DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
+                        2);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
+                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
+                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
+DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
+                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
+                   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
+DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck",
+                          &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA,
+                          OMAP4430_CLKSEL_0_1_MASK);
+DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
+                   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
+                   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
+                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
+                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
+DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
+                        0x0, 1, 2);
+DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
+                   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
+                   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+static const struct clk_ops dmic_fck_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+        .set_parent     = &omap2_clksel_set_parent,
+        .init           = &omap2_init_clk_clkdm,
+};
+static const char *dpll_core_m3x2_ck_parents[] = {
+        "dpll_core_x2_ck",
+};
+static const struct clksel dpll_core_m3x2_div[] = {
+        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+/* XXX Missing round_rate, set_rate in ops */
+DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
+                         OMAP4430_CM_DIV_M3_DPLL_CORE,
+                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+                         OMAP4430_CM_DIV_M3_DPLL_CORE,
+                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
+                         dpll_core_m3x2_ck_parents, dmic_fck_ops);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
+                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
+                          OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
+static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
+        "sys_clkin_ck", "div_iva_hs_clk",
+};
+DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
+               0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
+               OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
+        .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_iva_ck;
+static struct clk_hw_omap dpll_iva_ck_hw = {
+        .hw = {
+                .clk = &dpll_iva_ck,
+        },
+        .dpll_data      = &dpll_iva_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+static const char *dpll_iva_x2_ck_parents[] = {
+        "dpll_iva_ck",
+};
+static struct clk dpll_iva_x2_ck;
+static struct clk_hw_omap dpll_iva_x2_ck_hw = {
+        .hw = {
+                .clk = &dpll_iva_x2_ck,
+        },
+};
+DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
+                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
+                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
+        .clk_bypass     = &div_mpu_hs_clk,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_mpu_ck;
+static struct clk_hw_omap dpll_mpu_ck_hw = {
+        .hw = {
+                .clk = &dpll_mpu_ck,
+        },
+        .dpll_data      = &dpll_mpu_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
+                          OMAP4430_CM_DIV_M2_DPLL_MPU,
+                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
+DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
+                        &dpll_abe_m3x2_ck, 0x0, 1, 2);
+static const char *per_hsd_byp_clk_mux_ck_parents[] = {
+        "sys_clkin_ck", "per_hs_clk_div_ck",
+};
+DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
+               0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
+               OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
+        .clk_bypass     = &per_hsd_byp_clk_mux_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = 2047,
+        .max_divider    = 128,
+        .min_divider    = 1,
+};
+static struct clk dpll_per_ck;
+static struct clk_hw_omap dpll_per_ck_hw = {
+        .hw = {
+                .clk = &dpll_per_ck,
+        },
+        .dpll_data      = &dpll_per_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
+                   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
+                   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+static const char *dpll_per_x2_ck_parents[] = {
+        "dpll_per_ck",
+};
+static struct clk dpll_per_x2_ck;
+static struct clk_hw_omap dpll_per_x2_ck_hw = {
+        .hw = {
+                .clk = &dpll_per_x2_ck,
+        },
+        .flags          = CLOCK_CLKOUTX2,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .ops            = &clkhwops_omap4_dpllmx,
+};
+DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
+                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
+static const char *dpll_per_m3x2_ck_parents[] = {
+        "dpll_per_x2_ck",
+};
+static const struct clksel dpll_per_m3x2_div[] = {
+        { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+/* XXX Missing round_rate, set_rate in ops */
+DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
+                         OMAP4430_CM_DIV_M3_DPLL_PER,
+                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+                         OMAP4430_CM_DIV_M3_DPLL_PER,
+                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
+                         dpll_per_m3x2_ck_parents, dmic_fck_ops);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
+                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
+                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
+                          OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+                          0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
+                          OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
+DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
+                        &dpll_abe_m3x2_ck, 0x0, 1, 3);
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
+        .clk_bypass     = &usb_hs_clk_div_ck,
+        .flags          = DPLL_J_TYPE,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
+        .mult_mask      = OMAP4430_DPLL_MULT_USB_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_0_7_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
+        .max_multiplier = 4095,
+        .max_divider    = 256,
+        .min_divider    = 1,
+};
+static struct clk dpll_usb_ck;
+static struct clk_hw_omap dpll_usb_ck_hw = {
+        .hw = {
+                .clk = &dpll_usb_ck,
+        },
+        .dpll_data      = &dpll_usb_dd,
+        .ops            = &clkhwops_omap3_dpll,
+};
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+static const char *dpll_usb_clkdcoldo_ck_parents[] = {
+        "dpll_usb_ck",
+};
+static struct clk dpll_usb_clkdcoldo_ck;
+static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
+};
+static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
+        .hw = {
+                .clk = &dpll_usb_clkdcoldo_ck,
+        },
+        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
+        .ops            = &clkhwops_omap4_dpllmx,
+};
+DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
+                  dpll_usb_clkdcoldo_ck_ops);
+DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
+                          OMAP4430_CM_DIV_M2_DPLL_USB,
+                          OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
+static const char *ducati_clk_mux_ck_parents[] = {
+        "div_core_ck", "dpll_per_m6x2_ck",
+};
+DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
+               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
+DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+                        0x0, 1, 16);
+DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
+                        1, 4);
+DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+                        0x0, 1, 8);
+static const struct clk_div_table func_48m_fclk_rates[] = {
+        { .div = 4, .val = 0 },
+        { .div = 8, .val = 1 },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
+                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
+                         NULL);
+DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+                        0x0, 1, 4);
+static const struct clk_div_table func_64m_fclk_rates[] = {
+        { .div = 2, .val = 0 },
+        { .div = 4, .val = 1 },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
+                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
+                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
+                         NULL);
+static const struct clk_div_table func_96m_fclk_rates[] = {
+        { .div = 2, .val = 0 },
+        { .div = 4, .val = 1 },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
+                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
+                         NULL);
+static const struct clk_div_table init_60m_fclk_rates[] = {
+        { .div = 1, .val = 0 },
+        { .div = 8, .val = 1 },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
+                         0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
+                         OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
+                         0x0, init_60m_fclk_rates, NULL);
+DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
+                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
+                   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
+DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
+                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
+                   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
+DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+                        0x0, 1, 16);
+static const char *l4_wkup_clk_mux_ck_parents[] = {
+        "sys_clkin_ck", "lp_clk_div_ck",
+};
+DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
+               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
+static const struct clk_div_table ocp_abe_iclk_rates[] = {
+        { .div = 2, .val = 0 },
+        { .div = 1, .val = 1 },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
+                         OMAP4430_CM1_ABE_AESS_CLKCTRL,
+                         OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
+                         OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
+                         0x0, ocp_abe_iclk_rates, NULL);
+DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
+                        0x0, 1, 4);
+DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
+                   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
+                   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
+DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
+                   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
+                   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
+static struct clk dbgclk_mux_ck;
+DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
+DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents,
+                  dpll_usb_clkdcoldo_ck_ops);
+/* Leaf clocks controlled by modules */
+DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
+                OMAP4430_CM_L4SEC_AES1_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
+                OMAP4430_CM_L4SEC_AES2_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
+                OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+                OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
+static const struct clk_div_table div_ts_ck_rates[] = {
+        { .div = 8, .val = 0 },
+        { .div = 16, .val = 1 },
+        { .div = 32, .val = 2 },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
+                         0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+                         OMAP4430_CLKSEL_24_25_SHIFT,
+                         OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
+                         NULL);
+DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
+                OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+                OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+static const char *dmic_sync_mux_ck_parents[] = {
+        "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
+};
+DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
+               0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+static const struct clksel func_dmic_abe_gfclk_sel[] = {
+        { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const char *dmic_fck_parents[] = {
+        "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
+};
+/* Merged func_dmic_abe_gfclk into dmic */
+static struct clk dmic_fck;
+DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
+                         OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+                         OMAP4430_CLKSEL_SOURCE_MASK,
+                         OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         dmic_fck_parents, dmic_fck_ops);
+DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
+                OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
+                OMAP4430_CM_DSS_DSS_CLKCTRL,
+                OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
+                OMAP4430_CM_DSS_DSS_CLKCTRL,
+                OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
+                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
+                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
+                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
+                OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
+                OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
+                OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
+                   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
+                   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
+                OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
+                OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
+                0x0, NULL);
+static const struct clksel sgx_clk_mux_sel[] = {
+        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static const char *gpu_fck_parents[] = {
+        "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
+};
+/* Merged sgx_clk_mux into gpu */
+DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
+                         OMAP4430_CM_GFX_GFX_CLKCTRL,
+                         OMAP4430_CLKSEL_SGX_FCLK_MASK,
+                         OMAP4430_CM_GFX_GFX_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         gpu_fck_parents, dmic_fck_ops);
+DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
+                OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
+                   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
+                   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
+DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
+                OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
+                OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
+                OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
+                OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
+                OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
+                OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
+                OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
+                OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+static struct clk l3_instr_ick;
+static const char *l3_instr_ick_parent_names[] = {
+        "l3_div_ck",
+};
+static const struct clk_ops l3_instr_ick_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .init           = &omap2_init_clk_clkdm,
+};
+static struct clk_hw_omap l3_instr_ick_hw = {
+        .hw = {
+                .clk = &l3_instr_ick,
+        },
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
+        .clkdm_name     = "l3_instr_clkdm",
+};
+DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
+static struct clk l3_main_3_ick;
+static struct clk_hw_omap l3_main_3_ick_hw = {
+        .hw = {
+                .clk = &l3_main_3_ick,
+        },
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
+        .clkdm_name     = "l3_instr_clkdm",
+};
+DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
+DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+static const struct clksel func_mcasp_abe_gfclk_sel[] = {
+        { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const char *mcasp_fck_parents[] = {
+        "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
+};
+/* Merged func_mcasp_abe_gfclk into mcasp */
+DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel,
+                         OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+                         OMAP4430_CLKSEL_SOURCE_MASK,
+                         OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         mcasp_fck_parents, dmic_fck_ops);
+DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+static const struct clksel func_mcbsp1_gfclk_sel[] = {
+        { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp1_fck_parents[] = {
+        "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
+};
+/* Merged func_mcbsp1_gfclk into mcbsp1 */
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel,
+                         OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+                         OMAP4430_CLKSEL_SOURCE_MASK,
+                         OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         mcbsp1_fck_parents, dmic_fck_ops);
+DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+static const struct clksel func_mcbsp2_gfclk_sel[] = {
+        { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp2_fck_parents[] = {
+        "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
+};
+/* Merged func_mcbsp2_gfclk into mcbsp2 */
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel,
+                         OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+                         OMAP4430_CLKSEL_SOURCE_MASK,
+                         OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         mcbsp2_fck_parents, dmic_fck_ops);
+DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+static const struct clksel func_mcbsp3_gfclk_sel[] = {
+        { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp3_fck_parents[] = {
+        "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
+};
+/* Merged func_mcbsp3_gfclk into mcbsp3 */
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel,
+                         OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+                         OMAP4430_CLKSEL_SOURCE_MASK,
+                         OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         mcbsp3_fck_parents, dmic_fck_ops);
+static const char *mcbsp4_sync_mux_ck_parents[] = {
+        "func_96m_fclk", "per_abe_nc_fclk",
+};
+DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
+               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
+static const struct clksel per_mcbsp4_gfclk_sel[] = {
+        { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static const char *mcbsp4_fck_parents[] = {
+        "mcbsp4_sync_mux_ck", "pad_clks_ck",
+};
+/* Merged per_mcbsp4_gfclk into mcbsp4 */
+DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
+                         OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+                         OMAP4430_CLKSEL_SOURCE_24_24_MASK,
+                         OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         mcbsp4_fck_parents, dmic_fck_ops);
+DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
+                OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+static const struct clksel hsmmc1_fclk_sel[] = {
+        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static const char *mmc1_fck_parents[] = {
+        "func_64m_fclk", "func_96m_fclk",
+};
+/* Merged hsmmc1_fclk into mmc1 */
+DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
+                         OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         mmc1_fck_parents, dmic_fck_ops);
+/* Merged hsmmc2_fclk into mmc2 */
+DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
+                         OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         mmc1_fck_parents, dmic_fck_ops);
+DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+static struct clk ocp_wp_noc_ick;
+static struct clk_hw_omap ocp_wp_noc_ick_hw = {
+        .hw = {
+                .clk = &ocp_wp_noc_ick,
+        },
+        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
+        .clkdm_name     = "l3_instr_clkdm",
+};
+DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
+DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
+                OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
+                OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
+                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+                OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
+                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+                OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
+                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+                OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
+                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
+                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
+                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+                OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
+                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+                OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
+                &pad_slimbus_core_clks_ck, 0x0,
+                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
+                0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
+                0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
+                0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+static const struct clksel dmt1_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+/* Merged dmt1_clk_mux into timer1 */
+DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel,
+                         OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+/* Merged cm2_dm10_mux into timer10 */
+DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                         OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+                         OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+/* Merged cm2_dm11_mux into timer11 */
+DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                         OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+                         OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+/* Merged cm2_dm2_mux into timer2 */
+DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                         OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+                         OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+/* Merged cm2_dm3_mux into timer3 */
+DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                         OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+                         OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+/* Merged cm2_dm4_mux into timer4 */
+DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                         OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+                         OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+static const struct clksel timer5_sync_mux_sel[] = {
+        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+static const char *timer5_fck_parents[] = {
+        "syc_clk_div_ck", "sys_32k_ck",
+};
+/* Merged timer5_sync_mux into timer5 */
+DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel,
+                         OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         timer5_fck_parents, dmic_fck_ops);
+/* Merged timer6_sync_mux into timer6 */
+DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
+                         OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         timer5_fck_parents, dmic_fck_ops);
+/* Merged timer7_sync_mux into timer7 */
+DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
+                         OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         timer5_fck_parents, dmic_fck_ops);
+/* Merged timer8_sync_mux into timer8 */
+DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
+                         OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         timer5_fck_parents, dmic_fck_ops);
+/* Merged cm2_dm9_mux into timer9 */
+DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
+                         OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+                         OMAP4430_CLKSEL_MASK,
+                         OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+                         OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
+                         abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
+DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_UART1_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_UART2_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_UART3_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L4PER_UART4_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+static struct clk usb_host_fs_fck;
+static const char *usb_host_fs_fck_parent_names[] = {
+        "func_48mc_fclk",
+};
+static const struct clk_ops usb_host_fs_fck_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+};
+static struct clk_hw_omap usb_host_fs_fck_hw = {
+        .hw = {
+                .clk = &usb_host_fs_fck,
+        },
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+};
+DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
+                  usb_host_fs_fck_ops);
+static const char *utmi_p1_gfclk_parents[] = {
+        "init_60m_fclk", "xclk60mhsp1_ck",
+};
+DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
+               OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+               OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
+static const char *utmi_p2_gfclk_parents[] = {
+        "init_60m_fclk", "xclk60mhsp2_ck",
+};
+DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
+               OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+               OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
+                &dpll_usb_m2_ck, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
+                &init_60m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
+                &init_60m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
+                &dpll_usb_m2_ck, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
+static const char *otg_60m_gfclk_parents[] = {
+        "utmi_phy_clkout_ck", "xclk60motg_ck",
+};
+DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
+               OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
+               OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
+DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+                OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
+                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
+                OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+                OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+                OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+                OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
+DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
+                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
+static const struct clk_div_table usim_ck_rates[] = {
+        { .div = 14, .val = 0 },
+        { .div = 18, .val = 1 },
+        { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
+                         OMAP4430_CM_WKUP_USIM_CLKCTRL,
+                         OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
+                         0x0, usim_ck_rates, NULL);
+DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
+                OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
+                OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
+                0x0, NULL);
+/* Remaining optional clocks */
+static const char *pmd_stm_clock_mux_ck_parents[] = {
+        "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
+};
+DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
+               OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
+DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
+               OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+               OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
+               OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
+DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
+                   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+                   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
+                   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
+static const char *trace_clk_div_ck_parents[] = {
+        "pmd_trace_clk_mux_ck",
+};
+static const struct clksel trace_clk_div_div[] = {
+        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+static struct clk trace_clk_div_ck;
+static const struct clk_ops trace_clk_div_ck_ops = {
+        .recalc_rate    = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+        .init           = &omap2_init_clk_clkdm,
+        .enable         = &omap2_clkops_enable_clkdm,
+        .disable        = &omap2_clkops_disable_clkdm,
+};
+static struct clk_hw_omap trace_clk_div_ck_hw = {
+        .hw = {
+                .clk = &trace_clk_div_ck,
+        },
+        .clkdm_name     = "emu_sys_clkdm",
+        .clksel         = trace_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
+};
+DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
+                  trace_clk_div_ck_ops);
+/* SCRM aux clk nodes */
+static const struct clksel auxclk_src_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+static const char *auxclk_src_ck_parents[] = {
+        "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
+};
+static const struct clk_ops auxclk_src_ck_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+        .is_enabled     = &omap2_dflt_clk_is_enabled,
+        .recalc_rate    = &omap2_clksel_recalc,
+        .get_parent     = &omap2_clksel_find_parent_index,
+};
+DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
+                         OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
+                         OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
+                         auxclk_src_ck_parents, auxclk_src_ck_ops);
+DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
+                   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
+                   0x0, NULL);
+DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
+                         OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
+                         OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
+                         auxclk_src_ck_parents, auxclk_src_ck_ops);
+DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
+                   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
+                   0x0, NULL);
+DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
+                         OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
+                         OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
+                         auxclk_src_ck_parents, auxclk_src_ck_ops);
+DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
+                   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
+                   0x0, NULL);
+DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
+                         OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
+                         OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
+                         auxclk_src_ck_parents, auxclk_src_ck_ops);
+DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
+                   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
+                   0x0, NULL);
+DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
+                         OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
+                         OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
+                         auxclk_src_ck_parents, auxclk_src_ck_ops);
+DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
+                   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
+                   0x0, NULL);
+DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
+                         OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
+                         OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
+                         auxclk_src_ck_parents, auxclk_src_ck_ops);
+DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
+                   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
+                   0x0, NULL);
+static const char *auxclkreq_ck_parents[] = {
+        "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
+        "auxclk5_ck",
+};
+DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
+               OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
+               OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
+               OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
+               OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
+               OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
+               0x0, NULL);
+DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
+               OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
+               0x0, NULL);
+/*
+ * clkdev
+ */
+static struct omap_clk omap44xx_clks[] = {
+        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
+        CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck,       CK_443X),
+        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
+        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
+        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
+        CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk,       CK_443X),
+        CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
+        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
+        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
+        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
+        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
+        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
+        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
+        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
+        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
+        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
+        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
+        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
+        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
+        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
+        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
+        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
+        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
+        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
+        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
+        CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
+        CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
+        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
+        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
+        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
+        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
+        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
+        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
+        CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
+        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
+        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
+        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
+        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
+        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
+        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
+        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
+        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
+        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
+        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
+        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
+        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
+        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
+        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
+        CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
+        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
+        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
+        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
+        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
+        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
+        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
+        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
+        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
+        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
+        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
+        CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
+        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
+        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
+        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
+        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
+        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
+        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
+        CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
+        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
+        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
+        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
+        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
+        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
+        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
+        CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
+        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
+        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
+        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
+        CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
+        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
+        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
+        CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
+        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
+        CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
+        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
+        CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
+        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
+        CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
+        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
+        CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
+        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
+        CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
+        CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
+        CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
+        CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
+        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
+        CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
+        CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
+        CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
+        CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
+        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
+        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
+        CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
+        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
+        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
+        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
+        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
+        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
+        CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
+        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
+        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
+        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
+        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
+        CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
+        CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
+        CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
+        CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
+        CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
+        CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
+        CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
+        CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
+        CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
+        CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
+        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
+        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
+        CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
+        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
+        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
+        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
+        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
+        CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
+        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
+        CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
+        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
+        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
+        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
+        CLK(NULL,       "timer1_fck",                   &timer1_fck,    CK_443X),
+        CLK(NULL,       "timer10_fck",                  &timer10_fck,   CK_443X),
+        CLK(NULL,       "timer11_fck",                  &timer11_fck,   CK_443X),
+        CLK(NULL,       "timer2_fck",                   &timer2_fck,    CK_443X),
+        CLK(NULL,       "timer3_fck",                   &timer3_fck,    CK_443X),
+        CLK(NULL,       "timer4_fck",                   &timer4_fck,    CK_443X),
+        CLK(NULL,       "timer5_fck",                   &timer5_fck,    CK_443X),
+        CLK(NULL,       "timer6_fck",                   &timer6_fck,    CK_443X),
+        CLK(NULL,       "timer7_fck",                   &timer7_fck,    CK_443X),
+        CLK(NULL,       "timer8_fck",                   &timer8_fck,    CK_443X),
+        CLK(NULL,       "timer9_fck",                   &timer9_fck,    CK_443X),
+        CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
+        CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
+        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
+        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
+        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
+        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
+        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
+        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
+        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
+        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
+        CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick,        CK_443X),
+        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
+        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
+        CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
+        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
+        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
+        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
+        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
+        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
+        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
+        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
+        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
+        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
+        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
+        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
+        CLK("omap-gpmc",        "fck",                  &dummy_ck,      CK_443X),
+        CLK("omap_i2c.1",       "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap_i2c.2",       "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap_i2c.3",       "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap_i2c.4",       "ick",                  &dummy_ck,      CK_443X),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.0",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.1",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.2",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.3",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.4",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.1",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.2",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.3",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap-mcbsp.4",     "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
+        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
+        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
+        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
+        CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
+        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("49038000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
+};
+static const char *enable_init_clks[] = {
+        "emif1_fck",
+        "emif2_fck",
+        "gpmc_ick",
+        "l3_instr_ick",
+        "l3_main_3_ick",
+        "ocp_wp_noc_ick",
+};
+int __init omap4xxx_clk_init(void)
+{
+        u32 cpu_clkflg;
+        struct omap_clk *c;
+        if (cpu_is_omap443x()) {
+                cpu_mask = RATE_IN_4430;
+                cpu_clkflg = CK_443X;
+        } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
+                cpu_mask = RATE_IN_4460 | RATE_IN_4430;
+                cpu_clkflg = CK_446X | CK_443X;
+                if (cpu_is_omap447x())
+                        pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
+        } else {
+                return 0;
+        }
+        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+                                                                        c++) {
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        if (!__clk_init(NULL, c->lk.clk))
+                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
+                }
+        }
+        omap2_clk_disable_autoidle_all();
+        omap2_clk_enable_init_clocks(enable_init_clks,
+                                     ARRAY_SIZE(enable_init_clks));
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index c2d15212d64d..25b1feed480d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -21,12 +21,10 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
-#include <plat/prcm.h>
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
@@ -38,92 +36,90 @@
 #define APLLS_CLKIN_13MHZ               2
 #define APLLS_CLKIN_12MHZ               3
-void __iomem *cm_idlest_pll;
 /* Private functions */
-/* Enable an APLL if off */
+/**
-static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
+ * omap2xxx_clk_apll_locked - is the APLL locked?
+ * @hw: struct clk_hw * of the APLL to check
+ *
+ * If the APLL IP block referred to by @hw indicates that it's locked,
+ * return true; otherwise, return false.
+ */
+static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
 {
-        u32 cval, apll_mask;
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+        u32 r, apll_mask;
        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
-        cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-        if ((cval & apll_mask) == apll_mask)
-                return 0;   /* apll already enabled */
-        cval &= ~apll_mask;
-        cval |= apll_mask;
-        omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-        omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
-                             OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
-        /*
+        return ((r & apll_mask) == apll_mask) ? true : false;
-         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
-         * fails?
-         */
-        return 0;
 }
-static int omap2_clk_apll96_enable(struct clk *clk)
+int omap2_clk_apll96_enable(struct clk_hw *hw)
 {
-        return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
+        return omap2xxx_cm_apll96_enable();
 }
-static int omap2_clk_apll54_enable(struct clk *clk)
+int omap2_clk_apll54_enable(struct clk_hw *hw)
 {
-        return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
+        return omap2xxx_cm_apll54_enable();
 }
-static void _apll96_allow_idle(struct clk *clk)
+static void _apll96_allow_idle(struct clk_hw_omap *clk)
 {
        omap2xxx_cm_set_apll96_auto_low_power_stop();
 }
-static void _apll96_deny_idle(struct clk *clk)
+static void _apll96_deny_idle(struct clk_hw_omap *clk)
 {
        omap2xxx_cm_set_apll96_disable_autoidle();
 }
-static void _apll54_allow_idle(struct clk *clk)
+static void _apll54_allow_idle(struct clk_hw_omap *clk)
 {
        omap2xxx_cm_set_apll54_auto_low_power_stop();
 }
-static void _apll54_deny_idle(struct clk *clk)
+static void _apll54_deny_idle(struct clk_hw_omap *clk)
 {
        omap2xxx_cm_set_apll54_disable_autoidle();
 }
-/* Stop APLL */
+void omap2_clk_apll96_disable(struct clk_hw *hw)
-static void omap2_clk_apll_disable(struct clk *clk)
 {
-        u32 cval;
+        omap2xxx_cm_apll96_disable();
+}
-        cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+void omap2_clk_apll54_disable(struct clk_hw *hw)
-        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+{
-        omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+        omap2xxx_cm_apll54_disable();
 }
-/* Public data */
+unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
+                                      unsigned long parent_rate)
+{
+        return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
+}
-const struct clkops clkops_apll96 = {
+unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
-        .enable         = omap2_clk_apll96_enable,
+                                      unsigned long parent_rate)
-        .disable        = omap2_clk_apll_disable,
+{
-        .allow_idle     = _apll96_allow_idle,
+        return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
-        .deny_idle      = _apll96_deny_idle,
+}
-};
-const struct clkops clkops_apll54 = {
+/* Public data */
-        .enable         = omap2_clk_apll54_enable,
+const struct clk_hw_omap_ops clkhwops_apll54 = {
-        .disable        = omap2_clk_apll_disable,
        .allow_idle     = _apll54_allow_idle,
        .deny_idle      = _apll54_deny_idle,
 };
+const struct clk_hw_omap_ops clkhwops_apll96 = {
+        .allow_idle     = _apll96_allow_idle,
+        .deny_idle      = _apll96_deny_idle,
+};
 /* Public functions */
 u32 omap2xxx_get_apll_clkin(void)
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
index 1502a7bc20bb..82572e277b97 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
@@ -14,10 +14,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "clock.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 /* Private functions */
@@ -31,7 +29,7 @@
 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
 * instead.  Add some mechanism to optionally enter this mode.
 */
-static void _allow_idle(struct clk *clk)
+static void _allow_idle(struct clk_hw_omap *clk)
 {
        if (!clk || !clk->dpll_data)
                return;
@@ -45,7 +43,7 @@ static void _allow_idle(struct clk *clk)
 *
 * Disable DPLL automatic idle control.  No return value.
 */
-static void _deny_idle(struct clk *clk)
+static void _deny_idle(struct clk_hw_omap *clk)
 {
        if (!clk || !clk->dpll_data)
                return;
@@ -55,9 +53,7 @@ static void _deny_idle(struct clk *clk)
 /* Public data */
+const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
-const struct clkops clkops_omap2xxx_dpll_ops = {
        .allow_idle     = _allow_idle,
        .deny_idle      = _deny_idle,
 };
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 4ae439222085..d8620105c42a 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -25,21 +25,25 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "sram.h"
 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
+/*
+ * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
+ * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set
+ * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
+ */
+static struct clk_hw_omap *dpll_core_ck;
 /**
 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
 *
 * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
@@ -47,12 +51,14 @@
 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
 * core_ck.
 */
-unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
+unsigned long omap2xxx_clk_get_core_rate(void)
 {
        long long core_clk;
        u32 v;
-        core_clk = omap2_get_dpll_rate(clk);
+        WARN_ON(!dpll_core_ck);
+        core_clk = omap2_get_dpll_rate(dpll_core_ck);
        v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
        v &= OMAP24XX_CORE_CLK_SRC_MASK;
@@ -98,19 +104,22 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 }
-unsigned long omap2_dpllcore_recalc(struct clk *clk)
+unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
+                                    unsigned long parent_rate)
 {
-        return omap2xxx_clk_get_core_rate(clk);
+        return omap2xxx_clk_get_core_rate();
 }
-int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
+int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
+                             unsigned long parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 cur_rate, low, mult, div, valid_rate, done_rate;
        u32 bypass = 0;
        struct prcm_config tmpset;
        const struct dpll_data *dd;
-        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+        cur_rate = omap2xxx_clk_get_core_rate();
        mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
@@ -171,3 +180,19 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
        return 0;
 }
+/**
+ * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
+ * @clk: struct clk *dpll_ck
+ *
+ * Store a local copy of @clk in dpll_core_ck so other code can query
+ * the core rate without having to clk_get(), which can sleep.  Must
+ * only be called once.  No return value.  XXX If the clock
+ * registration process is ever changed such that dpll_ck is no longer
+ * statically defined, this code may need to change to increment some
+ * kind of use count on dpll_ck.
+ */
+void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
+{
+        WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
+        dpll_core_ck = to_clk_hw_omap(hw);
+}
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index c3460928b5e0..19f54d433490 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -23,8 +23,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "clock.h"
 #include "clock2xxx.h"
 #include "prm2xxx_3xxx.h"
@@ -37,7 +35,7 @@
 * clk_enable/clk_disable()-based usecounting for osc_ck should be
 * replaced with autoidle-based usecounting.
 */
-static int omap2_enable_osc_ck(struct clk *clk)
+int omap2_enable_osc_ck(struct clk_hw *clk)
 {
        u32 pcc;
@@ -55,7 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk)
 * clk_enable/clk_disable()-based usecounting for osc_ck should be
 * replaced with autoidle-based usecounting.
 */
-static void omap2_disable_osc_ck(struct clk *clk)
+void omap2_disable_osc_ck(struct clk_hw *clk)
 {
        u32 pcc;
@@ -64,13 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk)
        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
 }
-const struct clkops clkops_oscck = {
+unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
-        .enable         = omap2_enable_osc_ck,
+                                   unsigned long parent_rate)
-        .disable        = omap2_disable_osc_ck,
-};
-unsigned long omap2_osc_clk_recalc(struct clk *clk)
 {
        return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
 }
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index 8693cfdac49a..f467d072cd02 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -22,8 +22,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "clock.h"
 #include "clock2xxx.h"
 #include "prm2xxx_3xxx.h"
@@ -42,9 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void)
        return div;
 }
-unsigned long omap2xxx_sys_clk_recalc(struct clk *clk)
+unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
+                                      unsigned long parent_rate)
 {
-        return clk->parent->rate / omap2xxx_get_sysclkdiv();
+        return parent_rate / omap2xxx_get_sysclkdiv();
 }
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3524f0e7b6d5..ae2b35e76dc8 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2xxx DVFS virtual clock functions
 *
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2005-2008, 2012 Texas Instruments, Inc.
 * Copyright (C) 2004-2010 Nokia Corporation
 *
 * Contacts:
@@ -33,27 +33,33 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
 #include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "sram.h"
 const struct prcm_config *curr_prcm_set;
 const struct prcm_config *rate_table;
+/*
+ * sys_ck_rate: the rate of the external high-frequency clock
+ * oscillator on the board.  Set by the SoC-specific clock init code.
+ * Once set during a boot, will not change.
+ */
+static unsigned long sys_ck_rate;
 /**
 * omap2_table_mpu_recalc - just return the MPU speed
 * @clk: virt_prcm_set struct clk
 *
 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 */
-unsigned long omap2_table_mpu_recalc(struct clk *clk)
+unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
+                                     unsigned long parent_rate)
 {
        return curr_prcm_set->mpu_speed;
 }
@@ -65,18 +71,18 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 * just uses the ARM rates.
 */
-long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *parent_rate)
 {
        const struct prcm_config *ptr;
-        long highest_rate, sys_clk_rate;
+        long highest_rate;
        highest_rate = -EINVAL;
-        sys_clk_rate = __clk_get_rate(sclk);
        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
                if (!(ptr->flags & cpu_mask))
                        continue;
-                if (ptr->xtal_speed != sys_clk_rate)
+                if (ptr->xtal_speed != sys_ck_rate)
                        continue;
                highest_rate = ptr->mpu_speed;
@@ -89,21 +95,19 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 }
 /* Sets basic clocks based on the specified rate */
-int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
+                            unsigned long parent_rate)
 {
        u32 cur_rate, done_rate, bypass = 0, tmp;
        const struct prcm_config *prcm;
        unsigned long found_speed = 0;
        unsigned long flags;
-        long sys_clk_rate;
-        sys_clk_rate = __clk_get_rate(sclk);
        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                if (!(prcm->flags & cpu_mask))
                        continue;
-                if (prcm->xtal_speed != sys_clk_rate)
+                if (prcm->xtal_speed != sys_ck_rate)
                        continue;
                if (prcm->mpu_speed <= rate) {
@@ -119,7 +123,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
        }
        curr_prcm_set = prcm;
-        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+        cur_rate = omap2xxx_clk_get_core_rate();
        if (prcm->dpll_speed == cur_rate / 2) {
                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -169,3 +173,50 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
        return 0;
 }
+/**
+ * omap2xxx_clkt_vps_check_bootloader_rate - determine which of the rate
+ * table sets matches the current CORE DPLL hardware rate
+ *
+ * Check the MPU rate set by bootloader.  Sets the 'curr_prcm_set'
+ * global to point to the active rate set when found; otherwise, sets
+ * it to NULL.  No return value;
+ */
+void omap2xxx_clkt_vps_check_bootloader_rates(void)
+{
+        const struct prcm_config *prcm = NULL;
+        unsigned long rate;
+        rate = omap2xxx_clk_get_core_rate();
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck_rate)
+                        continue;
+                if (prcm->dpll_speed <= rate)
+                        break;
+        }
+        curr_prcm_set = prcm;
+}
+/**
+ * omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate
+ *
+ * Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS
+ * code.  (The sys_ck rate does not -- or rather, must not -- change
+ * during kernel runtime.)  Must be called after we have a valid
+ * sys_ck rate, but before the virt_prcm_set clock rate is
+ * recalculated.  No return value.
+ */
+void omap2xxx_clkt_vps_late_init(void)
+{
+        struct clk *c;
+        c = clk_get(NULL, "sys_ck");
+        if (IS_ERR(c)) {
+                WARN(1, "could not locate sys_ck\n");
+        } else {
+                sys_ck_rate = clk_get_rate(c);
+                clk_put(c);
+        }
+}
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 7c6da2f731dc..eb69acf21014 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -21,14 +21,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
 #include "clock.h"
 #include "clock3xxx.h"
 #include "clock34xx.h"
 #include "sdrc.h"
+#include "sram.h"
 #define CYCLES_PER_MHZ                  1000000
@@ -47,8 +44,10 @@
 * Program the DPLL M2 divider with the rounded target rate.  Returns
 * -EINVAL upon error, or 0 upon success.
 */
-int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 new_div = 0;
        u32 unlock_dll = 0;
        u32 c;
@@ -66,7 +65,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
                return -EINVAL;
        sdrcrate = __clk_get_rate(sdrc_ick_p);
-        clkrate = __clk_get_rate(clk);
+        clkrate = __clk_get_rate(hw->clk);
        if (rate > clkrate)
                sdrcrate <<= ((rate / clkrate) >> 1);
        else
@@ -115,8 +114,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                  0, 0, 0, 0);
-        clk->rate = rate;
        return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 3ff22114d702..0ec9f6fdf046 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -41,12 +41,10 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bug.h>
-#include <plat/clock.h>
 #include "clock.h"
 /* Private functions */
@@ -60,11 +58,14 @@
 * the element associated with the supplied parent clock address.
 * Returns a pointer to the struct clksel on success or NULL on error.
 */
-static const struct clksel *_get_clksel_by_parent(struct clk *clk,
+static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk,
                                                  struct clk *src_clk)
 {
        const struct clksel *clks;
+        if (!src_clk)
+                return NULL;
        for (clks = clk->clksel; clks->parent; clks++)
                if (clks->parent == src_clk)
                        break; /* Found the requested parent */
@@ -72,7 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
        if (!clks->parent) {
                /* This indicates a data problem */
                WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
-                     __clk_get_name(clk), __clk_get_name(src_clk));
+                     __clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
                return NULL;
        }
@@ -80,64 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 }
 /**
- * _get_div_and_fieldval() - find the new clksel divisor and field value to use
- * @src_clk: planned new parent struct clk *
- * @clk: struct clk * that is being reparented
- * @field_val: pointer to a u32 to contain the register data for the divisor
- *
- * Given an intended new parent struct clk * @src_clk, and the struct
- * clk * @clk to the clock that is being reparented, find the
- * appropriate rate divisor for the new clock (returned as the return
- * value), and the corresponding register bitfield data to program to
- * reach that divisor (returned in the u32 pointed to by @field_val).
- * Returns 0 on error, or returns the newly-selected divisor upon
- * success (in this latter case, the corresponding register bitfield
- * value is passed back in the variable pointed to by @field_val)
- */
-static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
-                                u32 *field_val)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr, *max_clkr = NULL;
-        u8 max_div = 0;
-        clks = _get_clksel_by_parent(clk, src_clk);
-        if (!clks)
-                return 0;
-        /*
-         * Find the highest divisor (e.g., the one resulting in the
-         * lowest rate) to use as the default.  This should avoid
-         * clock rates that are too high for the device.  XXX A better
-         * solution here would be to try to determine if there is a
-         * divisor matching the original clock rate before the parent
-         * switch, and if it cannot be found, to fall back to the
-         * highest divisor.
-         */
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if (!(clkr->flags & cpu_mask))
-                        continue;
-                if (clkr->div > max_div) {
-                        max_div = clkr->div;
-                        max_clkr = clkr;
-                }
-        }
-        if (max_div == 0) {
-                /* This indicates an error in the clksel data */
-                WARN(1, "clock: %s: could not find divisor for parent %s\n",
-                     __clk_get_name(clk),
-                     __clk_get_name(__clk_get_parent(src_clk)));
-                return 0;
-        }
-        *field_val = max_clkr->val;
-        return max_div;
-}
-/**
 * _write_clksel_reg() - program a clock's clksel register in hardware
 * @clk: struct clk * to program
 * @v: clksel bitfield value to program (with LSB at bit 0)
@@ -150,7 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
 * take into account any time the hardware might take to switch the
 * clock source.
 */
-static void _write_clksel_reg(struct clk *clk, u32 field_val)
+static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
 {
        u32 v;
@@ -173,13 +116,14 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val)
 * before calling.  Returns 0 on error or returns the actual integer divisor
 * upon success.
 */
-static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
+static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val)
 {
        const struct clksel *clks;
        const struct clksel_rate *clkr;
        struct clk *parent;
-        parent = __clk_get_parent(clk);
+        parent = __clk_get_parent(clk->hw.clk);
        clks = _get_clksel_by_parent(clk, parent);
        if (!clks)
                return 0;
@@ -195,7 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
        if (!clkr->div) {
                /* This indicates a data error */
                WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
-                     __clk_get_name(clk), field_val, __clk_get_name(parent));
+                     __clk_get_name(clk->hw.clk), field_val,
+                     __clk_get_name(parent));
                return 0;
        }
@@ -212,7 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 * register field value _before_ left-shifting (i.e., LSB is at bit
 * 0); or returns 0xFFFFFFFF (~0) upon error.
 */
-static u32 _divisor_to_clksel(struct clk *clk, u32 div)
+static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
 {
        const struct clksel *clks;
        const struct clksel_rate *clkr;
@@ -221,7 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
        /* should never happen */
        WARN_ON(div == 0);
-        parent = __clk_get_parent(clk);
+        parent = __clk_get_parent(clk->hw.clk);
        clks = _get_clksel_by_parent(clk, parent);
        if (!clks)
                return ~0;
@@ -236,7 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
        if (!clkr->div) {
                pr_err("clock: %s: could not find divisor %d for parent %s\n",
-                       __clk_get_name(clk), div, __clk_get_name(parent));
+                       __clk_get_name(clk->hw.clk), div,
+                       __clk_get_name(parent));
                return ~0;
        }
@@ -251,7 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 * into the hardware, convert it into the actual divisor value, and
 * return it; or return 0 on error.
 */
-static u32 _read_divisor(struct clk *clk)
+static u32 _read_divisor(struct clk_hw_omap *clk)
 {
        u32 v;
@@ -279,7 +225,8 @@ static u32 _read_divisor(struct clk *clk)
 *
 * Returns the rounded clock rate or returns 0xffffffff on error.
 */
-u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
+                                                 unsigned long target_rate,
                                u32 *new_div)
 {
        unsigned long test_rate;
@@ -290,9 +237,9 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        unsigned long parent_rate;
        const char *clk_name;
-        parent = __clk_get_parent(clk);
+        parent = __clk_get_parent(clk->hw.clk);
+        clk_name = __clk_get_name(clk->hw.clk);
        parent_rate = __clk_get_rate(parent);
-        clk_name = __clk_get_name(clk);
        if (!clk->clksel || !clk->clksel_mask)
                return ~0;
@@ -343,27 +290,35 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 */
 /**
- * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
+ * omap2_clksel_find_parent_index() - return the array index of the current
- * @clk: OMAP clock struct ptr to use
+ * hardware parent of @hw
+ * @hw: struct clk_hw * to find the current hardware parent of
 *
- * Given a pointer @clk to a source-selectable struct clk, read the
+ * Given a struct clk_hw pointer @hw to the 'hw' member of a struct
- * hardware register and determine what its parent is currently set
+ * clk_hw_omap record representing a source-selectable hardware clock,
- * to.  Update @clk's .parent field with the appropriate clk ptr.  No
+ * read the hardware register and determine what its parent is
- * return value.
+ * currently set to.  Intended to be called only by the common clock
+ * framework struct clk_hw_ops.get_parent function pointer.  Return
+ * the array index of this parent clock upon success -- there is no
+ * way to return an error, so if we encounter an error, just WARN()
+ * and pretend that we know that we're doing.
 */
-void omap2_init_clksel_parent(struct clk *clk)
+u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        const struct clksel *clks;
        const struct clksel_rate *clkr;
        u32 r, found = 0;
        struct clk *parent;
        const char *clk_name;
+        int ret = 0, f = 0;
-        if (!clk->clksel || !clk->clksel_mask)
+        parent = __clk_get_parent(hw->clk);
-                return;
+        clk_name = __clk_get_name(hw->clk);
-        parent = __clk_get_parent(clk);
+        /* XXX should be able to return an error */
-        clk_name = __clk_get_name(clk);
+        WARN((!clk->clksel || !clk->clksel_mask),
+             "clock: %s: attempt to call on a non-clksel clock", clk_name);
        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
        r >>= __ffs(clk->clksel_mask);
@@ -374,27 +329,21 @@ void omap2_init_clksel_parent(struct clk *clk)
                                continue;
                        if (clkr->val == r) {
-                                if (parent != clks->parent) {
-                                        pr_debug("clock: %s: inited parent to %s (was %s)\n",
-                                                 clk_name,
-                                                 __clk_get_name(clks->parent),
-                                                 ((parent) ?
-                                                  __clk_get_name(parent) :
-                                                 "NULL"));
-                                        clk_reparent(clk, clks->parent);
-                                }
                                found = 1;
+                                ret = f;
                        }
                }
+                f++;
        }
        /* This indicates a data error */
        WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
             clk_name, r);
-        return;
+        return ret;
 }
 /**
 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
 * @clk: struct clk *
@@ -404,21 +353,23 @@ void omap2_init_clksel_parent(struct clk *clk)
 * function.  Returns the clock's current rate, based on its parent's rate
 * and its current divisor setting in the hardware.
 */
-unsigned long omap2_clksel_recalc(struct clk *clk)
+unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
 {
        unsigned long rate;
        u32 div = 0;
-        struct clk *parent;
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-        div = _read_divisor(clk);
+        if (!parent_rate)
-        if (div == 0)
+                return 0;
-                return __clk_get_rate(clk);
-        parent = __clk_get_parent(clk);
+        div = _read_divisor(clk);
-        rate = __clk_get_rate(parent) / div;
+        if (!div)
+                rate = parent_rate;
+        else
+                rate = parent_rate / div;
-        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+        pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__,
-                 __clk_get_name(clk), rate, div);
+                 __clk_get_name(hw->clk), rate, div);
        return rate;
 }
@@ -434,8 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
 *
 * Returns the rounded clock rate or returns 0xffffffff on error.
 */
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
+long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
+                        unsigned long *parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 new_div;
        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
@@ -456,8 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
 * is changed, they will all be affected without any notification.
 * Returns -EINVAL upon error, or 0 upon success.
 */
-int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
+int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 field_val, validrate, new_div = 0;
        if (!clk->clksel || !clk->clksel_mask)
@@ -473,10 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
        _write_clksel_reg(clk, field_val);
-        clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
+        pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk),
+                 __clk_get_rate(hw->clk));
-        pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
-                 __clk_get_rate(clk));
        return 0;
 }
@@ -501,32 +454,13 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 * affected without any notification.  Returns -EINVAL upon error, or
 * 0 upon success.
 */
-int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
+int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
 {
-        u32 field_val = 0;
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-        u32 parent_div;
        if (!clk->clksel || !clk->clksel_mask)
                return -EINVAL;
-        parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
-        if (!parent_div)
-                return -EINVAL;
        _write_clksel_reg(clk, field_val);
-        clk_reparent(clk, new_parent);
-        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
-        clk->rate = __clk_get_rate(new_parent);
-        if (parent_div > 0)
-                __clk_get_rate(clk) /= parent_div;
-        pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-                 __clk_get_name(clk),
-                 __clk_get_name(__clk_get_parent(clk)),
-                 __clk_get_rate(clk));
        return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 80411142f482..924c230f8948 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -16,13 +16,11 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <asm/div64.h>
-#include <plat/clock.h>
 #include "soc.h"
 #include "clock.h"
 #include "cm-regbits-24xx.h"
@@ -78,7 +76,7 @@
 * (assuming that it is counting N upwards), or -2 if the enclosing loop
 * should skip to the next iteration (again assuming N is increasing).
 */
-static int _dpll_test_fint(struct clk *clk, u8 n)
+static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
 {
        struct dpll_data *dd;
        long fint, fint_min, fint_max;
@@ -87,7 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        dd = clk->dpll_data;
        /* DPLL divider must result in a valid jitter correction val */
-        fint = __clk_get_rate(__clk_get_parent(clk)) / n;
+        fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
        if (cpu_is_omap24xx()) {
                /* Should not be called for OMAP2, so warn if it is called */
@@ -188,15 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
 }
 /* Public functions */
+u8 omap2_init_dpll_parent(struct clk_hw *hw)
-void omap2_init_dpll_parent(struct clk *clk)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 v;
        struct dpll_data *dd;
        dd = clk->dpll_data;
        if (!dd)
-                return;
+                return -EINVAL;
        v = __raw_readl(dd->control_reg);
        v &= dd->enable_mask;
@@ -206,18 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk)
        if (cpu_is_omap24xx()) {
                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        clk_reparent(clk, dd->clk_bypass);
+                        return 1;
        } else if (cpu_is_omap34xx()) {
                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        clk_reparent(clk, dd->clk_bypass);
+                        return 1;
        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        clk_reparent(clk, dd->clk_bypass);
+                        return 1;
        }
-        return;
+        return 0;
 }
 /**
@@ -234,7 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk)
 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
 * if the clock @clk is not a DPLL.
 */
-u32 omap2_get_dpll_rate(struct clk *clk)
+unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
 {
        long long dpll_clk;
        u32 dpll_mult, dpll_div, v;
@@ -290,8 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 * (expensive) function again.  Returns ~0 if the target rate cannot
 * be rounded, or the rounded rate upon success.
 */
-long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+                unsigned long *parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        int m, n, r, scaled_max_m;
        unsigned long scaled_rt_rp;
        unsigned long new_rate = 0;
@@ -305,7 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
        dd = clk->dpll_data;
        ref_rate = __clk_get_rate(dd->clk_ref);
-        clk_name = __clk_get_name(clk);
+        clk_name = __clk_get_name(hw->clk);
        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
                 clk_name, target_rate);
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index 3d43fba2542f..f10eb03ce3e2 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -11,11 +11,9 @@
 #undef DEBUG
 #include <linux/kernel.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
-#include <plat/clock.h>
-#include <plat/prcm.h>
 #include "clock.h"
 #include "clock2xxx.h"
@@ -25,7 +23,7 @@
 /* Private functions */
 /* XXX */
-void omap2_clkt_iclk_allow_idle(struct clk *clk)
+void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
 {
        u32 v, r;
@@ -37,7 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk)
 }
 /* XXX */
-void omap2_clkt_iclk_deny_idle(struct clk *clk)
+void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
 {
        u32 v, r;
@@ -50,33 +48,17 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk)
 /* Public data */
-const struct clkops clkops_omap2_iclk_dflt_wait = {
+const struct clk_hw_omap_ops clkhwops_iclk = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_companion = omap2_clk_dflt_find_companion,
-        .find_idlest    = omap2_clk_dflt_find_idlest,
        .allow_idle     = omap2_clkt_iclk_allow_idle,
        .deny_idle      = omap2_clkt_iclk_deny_idle,
 };
-const struct clkops clkops_omap2_iclk_dflt = {
+const struct clk_hw_omap_ops clkhwops_iclk_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
        .allow_idle     = omap2_clkt_iclk_allow_idle,
        .deny_idle      = omap2_clkt_iclk_deny_idle,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
-const struct clkops clkops_omap2_iclk_idle_only = {
-        .allow_idle     = omap2_clkt_iclk_allow_idle,
-        .deny_idle      = omap2_clkt_iclk_deny_idle,
-};
-const struct clkops clkops_omap2_mdmclk_dflt_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_companion = omap2_clk_dflt_find_companion,
-        .find_idlest    = omap2_clk_dflt_find_idlest,
-        .allow_idle     = omap2_clkt_iclk_allow_idle,
-        .deny_idle      = omap2_clkt_iclk_deny_idle,
-};
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 961ac8f7e13d..e4ec3a69ee2e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -15,27 +15,35 @@
 #undef DEBUG
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
 #include <asm/cpu.h>
-#include <plat/clock.h>
-#include <plat/prcm.h>
 #include <trace/events/power.h>
 #include "soc.h"
 #include "clockdomain.h"
 #include "clock.h"
-#include "cm2xxx_3xxx.h"
+#include "cm.h"
+#include "cm2xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
+#include "common.h"
+/*
+ * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
+ * for a module to indicate that it is no longer in idle
+ */
+#define MAX_MODULE_ENABLE_WAIT          100000
 u16 cpu_mask;
@@ -47,12 +55,69 @@ u16 cpu_mask;
 */
 static bool clkdm_control = true;
+static LIST_HEAD(clk_hw_omap_clocks);
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_hw_omap *oclk;
+        if (!hw) {
+                pr_warn("%s: hw is NULL\n", __func__);
+                return -EINVAL;
+        }
+        oclk = to_clk_hw_omap(hw);
+        WARN_ON(!oclk->fixed_div);
+        return parent_rate / oclk->fixed_div;
+}
 /*
 * OMAP2+ specific clock functions
 */
 /* Private functions */
+/**
+ * _wait_idlest_generic - wait for a module to leave the idle state
+ * @reg: virtual address of module IDLEST register
+ * @mask: value to mask against to determine if the module is active
+ * @idlest: idle state indicator (0 or 1) for the clock
+ * @name: name of the clock (for printk)
+ *
+ * Wait for a module to leave idle, where its idle-status register is
+ * not inside the CM module.  Returns 1 if the module left idle
+ * promptly, or 0 if the module did not leave idle before the timeout
+ * elapsed.  XXX Deprecated - should be moved into drivers for the
+ * individual IP block that the IDLEST register exists in.
+ */
+static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
+                                const char *name)
+{
+        int i = 0, ena = 0;
+        ena = (idlest) ? 0 : mask;
+        omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+                          MAX_MODULE_ENABLE_WAIT, i);
+        if (i < MAX_MODULE_ENABLE_WAIT)
+                pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
+                         name, i);
+        else
+                pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
+                       name, MAX_MODULE_ENABLE_WAIT);
+        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
+};
 /**
 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
 * @clk: struct clk * belonging to the module
@@ -63,10 +128,12 @@ static bool clkdm_control = true;
 * belong in the clock code and will be moved in the medium term to
 * module-dependent code.  No return value.
 */
-static void _omap2_module_wait_ready(struct clk *clk)
+static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
 {
        void __iomem *companion_reg, *idlest_reg;
-        u8 other_bit, idlest_bit, idlest_val;
+        u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
+        s16 prcm_mod;
+        int r;
        /* Not all modules have multiple clocks that their IDLEST depends on */
        if (clk->ops->find_companion) {
@@ -76,9 +143,14 @@ static void _omap2_module_wait_ready(struct clk *clk)
        }
        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
+        r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
-        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
+        if (r) {
-                             __clk_get_name(clk));
+                /* IDLEST register not in the CM module */
+                _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
+                                     __clk_get_name(clk->hw.clk));
+        } else {
+                cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
+        };
 }
 /* Public functions */
@@ -91,15 +163,16 @@ static void _omap2_module_wait_ready(struct clk *clk)
 * clockdomain pointer, and save it into the struct clk.  Intended to be
 * called during clk_register().  No return value.
 */
-void omap2_init_clk_clkdm(struct clk *clk)
+void omap2_init_clk_clkdm(struct clk_hw *hw)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        struct clockdomain *clkdm;
        const char *clk_name;
        if (!clk->clkdm_name)
                return;
-        clk_name = __clk_get_name(clk);
+        clk_name = __clk_get_name(hw->clk);
        clkdm = clkdm_lookup(clk->clkdm_name);
        if (clkdm) {
@@ -146,8 +219,8 @@ void __init omap2_clk_disable_clkdm_control(void)
 * associate this type of code with per-module data structures to
 * avoid this issue, and remove the casts.  No return value.
 */
-void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
-                                   u8 *other_bit)
+                        void __iomem **other_reg, u8 *other_bit)
 {
        u32 r;
@@ -175,8 +248,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
 * register address ID (e.g., that CM_FCLKEN2 corresponds to
 * CM_IDLEST2).  This is not true for all modules.  No return value.
 */
-void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
-                                u8 *idlest_bit, u8 *idlest_val)
+                void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
 {
        u32 r;
@@ -198,16 +271,44 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
 }
-int omap2_dflt_clk_enable(struct clk *clk)
+/**
+ * omap2_dflt_clk_enable - enable a clock in the hardware
+ * @hw: struct clk_hw * of the clock to enable
+ *
+ * Enable the clock @hw in the hardware.  We first call into the OMAP
+ * clockdomain code to "enable" the corresponding clockdomain if this
+ * is the first enabled user of the clockdomain.  Then program the
+ * hardware to enable the clock.  Then wait for the IP block that uses
+ * this clock to leave idle (if applicable).  Returns the error value
+ * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
+ * if @hw has a null clock enable_reg, or zero upon success.
+ */
+int omap2_dflt_clk_enable(struct clk_hw *hw)
 {
+        struct clk_hw_omap *clk;
        u32 v;
+        int ret = 0;
+        clk = to_clk_hw_omap(hw);
+        if (clkdm_control && clk->clkdm) {
+                ret = clkdm_clk_enable(clk->clkdm, hw->clk);
+                if (ret) {
+                        WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
+                             __func__, __clk_get_name(hw->clk),
+                             clk->clkdm->name, ret);
+                        return ret;
+                }
+        }
        if (unlikely(clk->enable_reg == NULL)) {
-                pr_err("clock.c: Enable for %s without enable code\n",
+                pr_err("%s: %s missing enable_reg\n", __func__,
-                       clk->name);
+                       __clk_get_name(hw->clk));
-                return 0; /* REVISIT: -EINVAL */
+                ret = -EINVAL;
+                goto err;
        }
+        /* FIXME should not have INVERT_ENABLE bit here */
        v = __raw_readl(clk->enable_reg);
        if (clk->flags & INVERT_ENABLE)
                v &= ~(1 << clk->enable_bit);
@@ -216,22 +317,39 @@ int omap2_dflt_clk_enable(struct clk *clk)
        __raw_writel(v, clk->enable_reg);
        v = __raw_readl(clk->enable_reg); /* OCP barrier */
-        if (clk->ops->find_idlest)
+        if (clk->ops && clk->ops->find_idlest)
                _omap2_module_wait_ready(clk);
        return 0;
+err:
+        if (clkdm_control && clk->clkdm)
+                clkdm_clk_disable(clk->clkdm, hw->clk);
+        return ret;
 }
-void omap2_dflt_clk_disable(struct clk *clk)
+/**
+ * omap2_dflt_clk_disable - disable a clock in the hardware
+ * @hw: struct clk_hw * of the clock to disable
+ *
+ * Disable the clock @hw in the hardware, and call into the OMAP
+ * clockdomain code to "disable" the corresponding clockdomain if all
+ * clocks/hwmods in that clockdomain are now disabled.  No return
+ * value.
+ */
+void omap2_dflt_clk_disable(struct clk_hw *hw)
 {
+        struct clk_hw_omap *clk;
        u32 v;
+        clk = to_clk_hw_omap(hw);
        if (!clk->enable_reg) {
                /*
-                 * 'Independent' here refers to a clock which is not
+                 * 'independent' here refers to a clock which is not
                 * controlled by its parent.
                 */
-                pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
+                pr_err("%s: independent clock %s has no enable_reg\n",
+                       __func__, __clk_get_name(hw->clk));
                return;
        }
@@ -242,191 +360,213 @@ void omap2_dflt_clk_disable(struct clk *clk)
                v &= ~(1 << clk->enable_bit);
        __raw_writel(v, clk->enable_reg);
        /* No OCP barrier needed here since it is a disable operation */
-}
-const struct clkops clkops_omap2_dflt_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_companion = omap2_clk_dflt_find_companion,
-        .find_idlest    = omap2_clk_dflt_find_idlest,
-};
-const struct clkops clkops_omap2_dflt = {
+        if (clkdm_control && clk->clkdm)
-        .enable         = omap2_dflt_clk_enable,
+                clkdm_clk_disable(clk->clkdm, hw->clk);
-        .disable        = omap2_dflt_clk_disable,
+}
-};
 /**
- * omap2_clk_disable - disable a clock, if the system is not using it
+ * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
- * @clk: struct clk * to disable
+ * @hw: struct clk_hw * of the clock being enabled
 *
- * Decrements the usecount on struct clk @clk.  If there are no users
+ * Increment the usecount of the clockdomain of the clock pointed to
- * left, call the clkops-specific clock disable function to disable it
+ * by @hw; if the usecount is 1, the clockdomain will be "enabled."
- * in hardware.  If the clock is part of a clockdomain (which they all
+ * Only needed for clocks that don't use omap2_dflt_clk_enable() as
- * should be), request that the clockdomain be disabled.  (It too has
+ * their enable function pointer.  Passes along the return value of
- * a usecount, and so will not be disabled in the hardware until it no
+ * clkdm_clk_enable(), -EINVAL if @hw is not associated with a
- * longer has any users.)  If the clock has a parent clock (most of
+ * clockdomain, or 0 if clock framework-based clockdomain control is
- * them do), then call ourselves, recursing on the parent clock.  This
+ * not implemented.
- * can cause an entire branch of the clock tree to be powered off by
- * simply disabling one clock.  Intended to be called with the clockfw_lock
- * spinlock held.  No return value.
 */
-void omap2_clk_disable(struct clk *clk)
+int omap2_clkops_enable_clkdm(struct clk_hw *hw)
 {
-        if (clk->usecount == 0) {
+        struct clk_hw_omap *clk;
-                WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
+        int ret = 0;
-                return;
-        }
-        pr_debug("clock: %s: decrementing usecount\n", clk->name);
+        clk = to_clk_hw_omap(hw);
-        clk->usecount--;
+        if (unlikely(!clk->clkdm)) {
+                pr_err("%s: %s: no clkdm set ?!\n", __func__,
-        if (clk->usecount > 0)
+                       __clk_get_name(hw->clk));
-                return;
+                return -EINVAL;
+        }
-        pr_debug("clock: %s: disabling in hardware\n", clk->name);
+        if (unlikely(clk->enable_reg))
+                pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
+                       __clk_get_name(hw->clk));
-        if (clk->ops && clk->ops->disable) {
+        if (!clkdm_control) {
-                trace_clock_disable(clk->name, 0, smp_processor_id());
+                pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
-                clk->ops->disable(clk);
+                       __func__, __clk_get_name(hw->clk));
+                return 0;
        }
-        if (clkdm_control && clk->clkdm)
+        ret = clkdm_clk_enable(clk->clkdm, hw->clk);
-                clkdm_clk_disable(clk->clkdm, clk);
+        WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
+             __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
-        if (clk->parent)
+        return ret;
-                omap2_clk_disable(clk->parent);
 }
 /**
- * omap2_clk_enable - request that the system enable a clock
+ * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
- * @clk: struct clk * to enable
+ * @hw: struct clk_hw * of the clock being disabled
 *
- * Increments the usecount on struct clk @clk.  If there were no users
+ * Decrement the usecount of the clockdomain of the clock pointed to
- * previously, then recurse up the clock tree, enabling all of the
+ * by @hw; if the usecount is 0, the clockdomain will be "disabled."
- * clock's parents and all of the parent clockdomains, and finally,
+ * Only needed for clocks that don't use omap2_dflt_clk_disable() as their
- * enabling @clk's clockdomain, and @clk itself.  Intended to be
+ * disable function pointer.  No return value.
- * called with the clockfw_lock spinlock held.  Returns 0 upon success
- * or a negative error code upon failure.
 */
-int omap2_clk_enable(struct clk *clk)
+void omap2_clkops_disable_clkdm(struct clk_hw *hw)
 {
-        int ret;
+        struct clk_hw_omap *clk;
-        pr_debug("clock: %s: incrementing usecount\n", clk->name);
-        clk->usecount++;
-        if (clk->usecount > 1)
-                return 0;
-        pr_debug("clock: %s: enabling in hardware\n", clk->name);
+        clk = to_clk_hw_omap(hw);
-        if (clk->parent) {
+        if (unlikely(!clk->clkdm)) {
-                ret = omap2_clk_enable(clk->parent);
+                pr_err("%s: %s: no clkdm set ?!\n", __func__,
-                if (ret) {
+                       __clk_get_name(hw->clk));
-                        WARN(1, "clock: %s: could not enable parent %s: %d\n",
+                return;
-                             clk->name, clk->parent->name, ret);
-                        goto oce_err1;
-                }
        }
-        if (clkdm_control && clk->clkdm) {
+        if (unlikely(clk->enable_reg))
-                ret = clkdm_clk_enable(clk->clkdm, clk);
+                pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
-                if (ret) {
+                       __clk_get_name(hw->clk));
-                        WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
-                             clk->name, clk->clkdm->name, ret);
-                        goto oce_err2;
-                }
-        }
-        if (clk->ops && clk->ops->enable) {
+        if (!clkdm_control) {
-                trace_clock_enable(clk->name, 1, smp_processor_id());
+                pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
-                ret = clk->ops->enable(clk);
+                       __func__, __clk_get_name(hw->clk));
-                if (ret) {
+                return;
-                        WARN(1, "clock: %s: could not enable: %d\n",
-                             clk->name, ret);
-                        goto oce_err3;
-                }
        }
-        return 0;
+        clkdm_clk_disable(clk->clkdm, hw->clk);
-oce_err3:
-        if (clkdm_control && clk->clkdm)
-                clkdm_clk_disable(clk->clkdm, clk);
-oce_err2:
-        if (clk->parent)
-                omap2_clk_disable(clk->parent);
-oce_err1:
-        clk->usecount--;
-        return ret;
 }
-/* Given a clock and a rate apply a clock specific rounding function */
+/**
-long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+ * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
+ * @hw: struct clk_hw * to check
+ *
+ * Return 1 if the clock represented by @hw is enabled in the
+ * hardware, or 0 otherwise.  Intended for use in the struct
+ * clk_ops.is_enabled function pointer.
+ */
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
 {
-        if (clk->round_rate)
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-                return clk->round_rate(clk, rate);
+        u32 v;
+        v = __raw_readl(clk->enable_reg);
+        if (clk->flags & INVERT_ENABLE)
+                v ^= BIT(clk->enable_bit);
+        v &= BIT(clk->enable_bit);
-        return clk->rate;
+        return v ? 1 : 0;
 }
-/* Set the clock rate for a clock source */
+static int __initdata mpurate;
-int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
+/*
+ * By default we use the rate set by the bootloader.
+ * You can override this with mpurate= cmdline option.
+ */
+static int __init omap_clk_setup(char *str)
 {
-        int ret = -EINVAL;
+        get_option(&str, &mpurate);
-        pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
+        if (!mpurate)
+                return 1;
-        /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
+        if (mpurate < 1000)
-        if (clk->set_rate) {
+                mpurate *= 1000000;
-                trace_clock_set_rate(clk->name, rate, smp_processor_id());
-                ret = clk->set_rate(clk, rate);
-        }
-        return ret;
+        return 1;
 }
+__setup("mpurate=", omap_clk_setup);
-int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
+/**
+ * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock
+ * @clk: struct clk * to initialize
+ *
+ * Add an OMAP clock @clk to the internal list of OMAP clocks.  Used
+ * temporarily for autoidle handling, until this support can be
+ * integrated into the common clock framework code in some way.  No
+ * return value.
+ */
+void omap2_init_clk_hw_omap_clocks(struct clk *clk)
 {
-        if (!clk->clksel)
+        struct clk_hw_omap *c;
-                return -EINVAL;
-        if (clk->parent == new_parent)
+        if (__clk_get_flags(clk) & CLK_IS_BASIC)
-                return 0;
+                return;
-        return omap2_clksel_set_parent(clk, new_parent);
+        c = to_clk_hw_omap(__clk_get_hw(clk));
+        list_add(&c->node, &clk_hw_omap_clocks);
 }
-/*
+/**
- * OMAP2+ clock reset and init functions
+ * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that
+ * support it
+ *
+ * Enable clock autoidle on all OMAP clocks that have allow_idle
+ * function pointers associated with them.  This function is intended
+ * to be temporary until support for this is added to the common clock
+ * code.  Returns 0.
 */
+int omap2_clk_enable_autoidle_all(void)
+{
+        struct clk_hw_omap *c;
+        list_for_each_entry(c, &clk_hw_omap_clocks, node)
+                if (c->ops && c->ops->allow_idle)
+                        c->ops->allow_idle(c);
+        return 0;
+}
-#ifdef CONFIG_OMAP_RESET_CLOCKS
+/**
-void omap2_clk_disable_unused(struct clk *clk)
+ * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that
+ * support it
+ *
+ * Disable clock autoidle on all OMAP clocks that have allow_idle
+ * function pointers associated with them.  This function is intended
+ * to be temporary until support for this is added to the common clock
+ * code.  Returns 0.
+ */
+int omap2_clk_disable_autoidle_all(void)
 {
-        u32 regval32, v;
+        struct clk_hw_omap *c;
-        v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
+        list_for_each_entry(c, &clk_hw_omap_clocks, node)
+                if (c->ops && c->ops->deny_idle)
+                        c->ops->deny_idle(c);
+        return 0;
+}
-        regval32 = __raw_readl(clk->enable_reg);
+/**
-        if ((regval32 & (1 << clk->enable_bit)) == v)
+ * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
-                return;
+ * @clk_names: ptr to an array of strings of clock names to enable
+ * @num_clocks: number of clock names in @clk_names
+ *
+ * Prepare and enable a list of clocks, named by @clk_names.  No
+ * return value. XXX Deprecated; only needed until these clocks are
+ * properly claimed and enabled by the drivers or core code that uses
+ * them.  XXX What code disables & calls clk_put on these clocks?
+ */
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
+{
+        struct clk *init_clk;
+        int i;
-        pr_debug("Disabling unused clock \"%s\"\n", clk->name);
+        for (i = 0; i < num_clocks; i++) {
-        if (cpu_is_omap34xx()) {
+                init_clk = clk_get(NULL, clk_names[i]);
-                omap2_clk_enable(clk);
+                clk_prepare_enable(init_clk);
-                omap2_clk_disable(clk);
-        } else {
-                clk->ops->disable(clk);
        }
-        if (clk->clkdm != NULL)
-                pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
 }
-#endif
+const struct clk_hw_omap_ops clkhwops_wait = {
+        .find_idlest    = omap2_clk_dflt_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
 /**
 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
@@ -458,14 +598,12 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
        r = clk_set_rate(mpurate_ck, mpurate);
        if (IS_ERR_VALUE(r)) {
                WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
-                     mpurate_ck->name, mpurate, r);
+                     mpurate_ck_name, mpurate, r);
                clk_put(mpurate_ck);
                return -EINVAL;
        }
        calibrate_delay();
-        recalculate_root_clocks();
        clk_put(mpurate_ck);
        return 0;
@@ -509,15 +647,3 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                (clk_get_rate(core_ck) / 1000000),
                (clk_get_rate(mpu_ck) / 1000000));
 }
-/* Common data */
-struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-};
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 35ec5f3d9a73..9917f793c3b6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -17,8 +17,311 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 #include <linux/kernel.h>
+#include <linux/list.h>
-#include <plat/clock.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+/* Platform flags for the clkdev-OMAP integration code */
+#define CK_242X         (1 << 0)
+#define CK_243X         (1 << 1)        /* 243x, 253x */
+#define CK_3430ES1      (1 << 2)        /* 34xxES1 only */
+#define CK_3430ES2PLUS  (1 << 3)        /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_AM35XX       (1 << 4)        /* Sitara AM35xx */
+#define CK_36XX         (1 << 5)        /* 36xx/37xx-specific clocks */
+#define CK_443X         (1 << 6)
+#define CK_TI816X       (1 << 7)
+#define CK_446X         (1 << 8)
+#define CK_AM33XX       (1 << 9)        /* AM33xx specific clocks */
+#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
+#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
+struct clockdomain;
+#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
+#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)      \
+        static struct clk _name = {                             \
+                .name = #_name,                                 \
+                .hw = &_name##_hw.hw,                           \
+                .parent_names = _parent_array_name,             \
+                .num_parents = ARRAY_SIZE(_parent_array_name),  \
+                .ops = &_clkops_name,                           \
+        };
+#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name)           \
+        static struct clk_hw_omap _name##_hw = {                \
+                .hw = {                                         \
+                        .clk = &_name,                          \
+                },                                              \
+                .clkdm_name = _clkdm_name,                      \
+        };
+#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel,        \
+                            _clksel_reg, _clksel_mask,          \
+                            _parent_names, _ops)                \
+        static struct clk _name;                                \
+        static struct clk_hw_omap _name##_hw = {                \
+                .hw = {                                         \
+                        .clk = &_name,                          \
+                },                                              \
+                .clksel         = _clksel,                      \
+                .clksel_reg     = _clksel_reg,                  \
+                .clksel_mask    = _clksel_mask,                 \
+                .clkdm_name     = _clkdm_name,                  \
+        };                                                      \
+        DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
+#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel,   \
+                                 _clksel_reg, _clksel_mask,     \
+                                 _enable_reg, _enable_bit,      \
+                                 _hwops, _parent_names, _ops)   \
+        static struct clk _name;                                \
+        static struct clk_hw_omap _name##_hw = {                \
+                .hw = {                                         \
+                        .clk = &_name,                          \
+                },                                              \
+                .ops            = _hwops,                       \
+                .enable_reg     = _enable_reg,                  \
+                .enable_bit     = _enable_bit,                  \
+                .clksel         = _clksel,                      \
+                .clksel_reg     = _clksel_reg,                  \
+                .clksel_mask    = _clksel_mask,                 \
+                .clkdm_name     = _clkdm_name,                  \
+        };                                                      \
+        DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
+#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name,          \
+                                _parent_ptr, _flags,            \
+                                _clksel_reg, _clksel_mask)      \
+        static const struct clksel _name##_div[] = {            \
+                {                                               \
+                        .parent = _parent_ptr,                  \
+                        .rates = div31_1to31_rates              \
+                },                                              \
+                { .parent = NULL },                             \
+        };                                                      \
+        static struct clk _name;                                \
+        static const char *_name##_parent_names[] = {           \
+                _parent_name,                                   \
+        };                                                      \
+        static struct clk_hw_omap _name##_hw = {                \
+                .hw = {                                         \
+                        .clk = &_name,                          \
+                },                                              \
+                .clksel         = _name##_div,                  \
+                .clksel_reg     = _clksel_reg,                  \
+                .clksel_mask    = _clksel_mask,                 \
+                .ops            = &clkhwops_omap4_dpllmx,       \
+        };                                                      \
+        DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
+/* struct clksel_rate.flags possibilities */
+#define RATE_IN_242X            (1 << 0)
+#define RATE_IN_243X            (1 << 1)
+#define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
+#define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
+#define RATE_IN_36XX            (1 << 4)
+#define RATE_IN_4430            (1 << 5)
+#define RATE_IN_TI816X          (1 << 6)
+#define RATE_IN_4460            (1 << 7)
+#define RATE_IN_AM33XX          (1 << 8)
+#define RATE_IN_TI814X          (1 << 9)
+#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
+#define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
+#define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
+#define RATE_IN_44XX            (RATE_IN_4430 | RATE_IN_4460)
+/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
+#define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
+/**
+ * struct clksel_rate - register bitfield values corresponding to clk divisors
+ * @val: register bitfield value (shifted to bit 0)
+ * @div: clock divisor corresponding to @val
+ * @flags: (see "struct clksel_rate.flags possibilities" above)
+ *
+ * @val should match the value of a read from struct clk.clksel_reg
+ * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
+ *
+ * @div is the divisor that should be applied to the parent clock's rate
+ * to produce the current clock's rate.
+ */
+struct clksel_rate {
+        u32                     val;
+        u8                      div;
+        u16                     flags;
+};
+/**
+ * struct clksel - available parent clocks, and a pointer to their divisors
+ * @parent: struct clk * to a possible parent clock
+ * @rates: available divisors for this parent clock
+ *
+ * A struct clksel is always associated with one or more struct clks
+ * and one or more struct clksel_rates.
+ */
+struct clksel {
+        struct clk               *parent;
+        const struct clksel_rate *rates;
+};
+/**
+ * struct dpll_data - DPLL registers and integration data
+ * @mult_div1_reg: register containing the DPLL M and N bitfields
+ * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
+ * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
+ * @clk_bypass: struct clk pointer to the clock's bypass clock input
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+ * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
+ * @min_divider: minimum valid non-bypass divider value (actual)
+ * @max_divider: maximum valid non-bypass divider value (actual)
+ * @modes: possible values of @enable_mask
+ * @autoidle_reg: register containing the DPLL autoidle mode bitfield
+ * @idlest_reg: register containing the DPLL idle status bitfield
+ * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
+ * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
+ * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
+ * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
+ * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @flags: DPLL type/features (see below)
+ *
+ * Possible values for @flags:
+ * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
+ *
+ * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
+ *
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+struct dpll_data {
+        void __iomem            *mult_div1_reg;
+        u32                     mult_mask;
+        u32                     div1_mask;
+        struct clk              *clk_bypass;
+        struct clk              *clk_ref;
+        void __iomem            *control_reg;
+        u32                     enable_mask;
+        unsigned long           last_rounded_rate;
+        u16                     last_rounded_m;
+        u16                     max_multiplier;
+        u8                      last_rounded_n;
+        u8                      min_divider;
+        u16                     max_divider;
+        u8                      modes;
+        void __iomem            *autoidle_reg;
+        void __iomem            *idlest_reg;
+        u32                     autoidle_mask;
+        u32                     freqsel_mask;
+        u32                     idlest_mask;
+        u32                     dco_mask;
+        u32                     sddiv_mask;
+        u8                      auto_recal_bit;
+        u8                      recal_en_bit;
+        u8                      recal_st_bit;
+        u8                      flags;
+};
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
+#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL      (1 << 1)
+#define CLOCK_NO_IDLE_PARENT    (1 << 2)
+#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2          (1 << 5)
+/**
+ * struct clk_hw_omap - OMAP struct clk
+ * @node: list_head connecting this clock into the full clock list
+ * @enable_reg: register to write to enable the clock (see @enable_bit)
+ * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
+ * @flags: see "struct clk.flags possibilities" above
+ * @clksel_reg: for clksel clks, register va containing src/divisor select
+ * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
+ * @clksel: for clksel clks, pointer to struct clksel for this clock
+ * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
+ * @clkdm_name: clockdomain name that this clock is contained in
+ * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
+ * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
+ * @src_offset: bitshift for source selection bitfield (OMAP1 only)
+ *
+ * XXX @rate_offset, @src_offset should probably be removed and OMAP1
+ * clock code converted to use clksel.
+ *
+ */
+struct clk_hw_omap_ops;
+struct clk_hw_omap {
+        struct clk_hw           hw;
+        struct list_head        node;
+        unsigned long           fixed_rate;
+        u8                      fixed_div;
+        void __iomem            *enable_reg;
+        u8                      enable_bit;
+        u8                      flags;
+        void __iomem            *clksel_reg;
+        u32                     clksel_mask;
+        const struct clksel     *clksel;
+        struct dpll_data        *dpll_data;
+        const char              *clkdm_name;
+        struct clockdomain      *clkdm;
+        const struct clk_hw_omap_ops    *ops;
+};
+struct clk_hw_omap_ops {
+        void                    (*find_idlest)(struct clk_hw_omap *oclk,
+                                        void __iomem **idlest_reg,
+                                        u8 *idlest_bit, u8 *idlest_val);
+        void                    (*find_companion)(struct clk_hw_omap *oclk,
+                                        void __iomem **other_reg,
+                                        u8 *other_bit);
+        void                    (*allow_idle)(struct clk_hw_omap *oclk);
+        void                    (*deny_idle)(struct clk_hw_omap *oclk);
+};
+unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
+                                        unsigned long parent_rate);
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
 #define CORE_CLK_SRC_32K                0x0
@@ -49,84 +352,62 @@
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE             0x1
-int omap2_clk_enable(struct clk *clk);
+long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-void omap2_clk_disable(struct clk *clk);
+                        unsigned long *parent_rate);
-long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
+int omap3_noncore_dpll_enable(struct clk_hw *hw);
-int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
+void omap3_noncore_dpll_disable(struct clk_hw *hw);
-long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-unsigned long omap3_dpll_recalc(struct clk *clk);
+                                unsigned long parent_rate);
-unsigned long omap3_clkoutx2_recalc(struct clk *clk);
+u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
-void omap3_dpll_allow_idle(struct clk *clk);
+void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
-void omap3_dpll_deny_idle(struct clk *clk);
+void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-u32 omap3_dpll_autoidle_read(struct clk *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+                                    unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
-void omap3_noncore_dpll_disable(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
-int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-void omap4_dpllmx_deny_gatectrl(struct clk *clk);
+                                unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
+                                    unsigned long target_rate,
+                                    unsigned long *parent_rate);
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-void omap2_clk_disable_unused(struct clk *clk);
-#else
-#define omap2_clk_disable_unused        NULL
-#endif
-void omap2_init_clk_clkdm(struct clk *clk);
+void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 /* clkt_clksel.c public functions */
-u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
+                                unsigned long target_rate,
                                u32 *new_div);
-void omap2_init_clksel_parent(struct clk *clk);
+u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
-unsigned long omap2_clksel_recalc(struct clk *clk);
+unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
+long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
-int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+                                unsigned long *parent_rate);
-int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
+int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate);
+int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 /* clkt_iclk.c public functions */
-extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
+extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
-extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
+extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
-u32 omap2_get_dpll_rate(struct clk *clk);
-void omap2_init_dpll_parent(struct clk *clk);
-int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
+u8 omap2_init_dpll_parent(struct clk_hw *hw);
+unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
-#ifdef CONFIG_ARCH_OMAP2
-void omap2xxx_clk_prepare_for_reboot(void);
-#else
-static inline void omap2xxx_clk_prepare_for_reboot(void)
-{
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP3
+int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap3_clk_prepare_for_reboot(void);
+void omap2_dflt_clk_disable(struct clk_hw *hw);
-#else
+int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
-static inline void omap3_clk_prepare_for_reboot(void)
+void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
-{
+                                   void __iomem **other_reg,
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-void omap4_clk_prepare_for_reboot(void);
-#else
-static inline void omap4_clk_prepare_for_reboot(void)
-{
-}
-#endif
-int omap2_dflt_clk_enable(struct clk *clk);
-void omap2_dflt_clk_disable(struct clk *clk);
-void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
                                   u8 *other_bit);
-void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
+                                void __iomem **idlest_reg,
                                u8 *idlest_bit, u8 *idlest_val);
+void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+int omap2_clk_enable_autoidle_all(void);
+int omap2_clk_disable_autoidle_all(void);
+void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                               const char *core_ck_name,
@@ -139,34 +420,43 @@ extern const struct clkops clkops_dummy;
 extern const struct clkops clkops_omap2_dflt;
 extern struct clk_functions omap2_clk_functions;
-extern struct clk *vclk, *sclk;
 extern const struct clksel_rate gpt_32k_rates[];
 extern const struct clksel_rate gpt_sys_rates[];
 extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
+extern struct clk dummy_ck;
-extern const struct clkops clkops_omap2_iclk_dflt_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
-extern const struct clkops clkops_omap2_iclk_dflt;
+extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
-extern const struct clkops clkops_omap2_iclk_idle_only;
+extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
-extern const struct clkops clkops_omap2xxx_dpll_ops;
+extern const struct clk_hw_omap_ops clkhwops_iclk;
-extern const struct clkops clkops_omap3_noncore_dpll_ops;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clkops clkops_omap3_core_dpll_ops;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
-extern const struct clkops clkops_omap4_dpllmx_ops;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
+extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
+extern const struct clk_hw_omap_ops clkhwops_apll54;
+extern const struct clk_hw_omap_ops clkhwops_apll96;
+extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
+extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
 /* clksel_rate blocks shared between OMAP44xx and AM33xx */
 extern const struct clksel_rate div_1_0_rates[];
+extern const struct clksel_rate div3_1to4_rates[];
 extern const struct clksel_rate div_1_1_rates[];
 extern const struct clksel_rate div_1_2_rates[];
 extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
-/* clocks shared between various OMAP SoCs */
-extern struct clk virt_19200000_ck;
-extern struct clk virt_26000000_ck;
 extern int am33xx_clk_init(void);
+extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 #endif
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
deleted file mode 100644
index c3cde1a2b6de..000000000000
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ /dev/null
@@ -1,1990 +0,0 @@
-/*
- * OMAP2420 clock data
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2011 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/list.h>
-#include <plat/clkdev_omap.h>
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-#include "cm-regbits-24xx.h"
-#include "sdrc.h"
-#include "control.h"
-#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
-/*
- * 2420 clock tree.
- *
- * NOTE:In many cases here we are assigning a 'default' parent. In
- *      many cases the parent is selectable. The set parent calls will
- *      also switch sources.
- *
- *      Several sources are given initial rates which may be wrong, this will
- *      be fixed up in the init func.
- *
- *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most peripherals have dependencies on multiple clock
- *      domains. Many get their interface clocks from the L4 domain, but get
- *      functional clocks from fixed sources or other core domain derived
- *      clocks.
- */
-/* Base external input clocks */
-static struct clk func_32k_ck = {
-        .name           = "func_32k_ck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .clkdm_name     = "wkup_clkdm",
-};
-static struct clk secure_32k_ck = {
-        .name           = "secure_32k_ck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .clkdm_name     = "wkup_clkdm",
-};
-/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
-static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
-        .name           = "osc_ck",
-        .ops            = &clkops_oscck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_osc_clk_recalc,
-};
-/* Without modem likely 12MHz, with modem likely 13MHz */
-static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
-        .name           = "sys_ck",             /* ~ ref_clk also */
-        .ops            = &clkops_null,
-        .parent         = &osc_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2xxx_sys_clk_recalc,
-};
-static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
-        .name           = "alt_ck",
-        .ops            = &clkops_null,
-        .rate           = 54000000,
-        .clkdm_name     = "wkup_clkdm",
-};
-/* Optional external clock input for McBSP CLKS */
-static struct clk mcbsp_clks = {
-        .name           = "mcbsp_clks",
-        .ops            = &clkops_null,
-};
-/*
- * Analog domain root source clocks
- */
-/* dpll_ck, is broken out in to special cases through clksel */
-/* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
- * deal with this
- */
-static struct dpll_data dpll_dd = {
-        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
-        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
-        .clk_bypass             = &sys_ck,
-        .clk_ref                = &sys_ck,
-        .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask            = OMAP24XX_EN_DPLL_MASK,
-        .max_multiplier         = 1023,
-        .min_divider            = 1,
-        .max_divider            = 16,
-};
-/*
- * XXX Cannot add round_rate here yet, as this is still a composite clock,
- * not just a DPLL
- */
-static struct clk dpll_ck = {
-        .name           = "dpll_ck",
-        .ops            = &clkops_omap2xxx_dpll_ops,
-        .parent         = &sys_ck,              /* Can be func_32k also */
-        .dpll_data      = &dpll_dd,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_dpllcore_recalc,
-        .set_rate       = &omap2_reprogram_dpllcore,
-};
-static struct clk apll96_ck = {
-        .name           = "apll96_ck",
-        .ops            = &clkops_apll96,
-        .parent         = &sys_ck,
-        .rate           = 96000000,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
-};
-static struct clk apll54_ck = {
-        .name           = "apll54_ck",
-        .ops            = &clkops_apll54,
-        .parent         = &sys_ck,
-        .rate           = 54000000,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
-};
-/*
- * PRCM digital base sources
- */
-/* func_54m_ck */
-static const struct clksel_rate func_54m_apll54_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel_rate func_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel func_54m_clksel[] = {
-        { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
-        { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
-        { .parent = NULL },
-};
-static struct clk func_54m_ck = {
-        .name           = "func_54m_ck",
-        .ops            = &clkops_null,
-        .parent         = &apll54_ck,   /* can also be alt_clk */
-        .clkdm_name     = "wkup_clkdm",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
-        .clksel         = func_54m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll_ck,             /* can also be 32k */
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk func_96m_ck = {
-        .name           = "func_96m_ck",
-        .ops            = &clkops_null,
-        .parent         = &apll96_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* func_48m_ck */
-static const struct clksel_rate func_48m_apll96_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel_rate func_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel func_48m_clksel[] = {
-        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
-        { .parent = &alt_ck, .rates = func_48m_alt_rates },
-        { .parent = NULL }
-};
-static struct clk func_48m_ck = {
-        .name           = "func_48m_ck",
-        .ops            = &clkops_null,
-        .parent         = &apll96_ck,    /* 96M or Alt */
-        .clkdm_name     = "wkup_clkdm",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
-        .clksel         = func_48m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk func_12m_ck = {
-        .name           = "func_12m_ck",
-        .ops            = &clkops_null,
-        .parent         = &func_48m_ck,
-        .fixed_div      = 4,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/* Secure timer, only available in secure mode */
-static struct clk wdt1_osc_ck = {
-        .name           = "ck_wdt1_osc",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &osc_ck,
-        .recalc         = &followparent_recalc,
-};
-/*
- * The common_clkout* clksel_rate structs are common to
- * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
- * sys_clkout2_* are 2420-only, so the
- * clksel_rate flags fields are inaccurate for those clocks. This is
- * harmless since access to those clocks are gated by the struct clk
- * flags fields, which mark them as 2420-only.
- */
-static const struct clksel_rate common_clkout_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_clkout_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_clkout_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_clkout_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel common_clkout_src_clksel[] = {
-        { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
-        { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
-        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
-        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
-        { .parent = NULL }
-};
-static struct clk sys_clkout_src = {
-        .name           = "sys_clkout_src",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &func_54m_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
-        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
-        .clksel         = common_clkout_src_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static const struct clksel_rate common_clkout_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 16, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel sys_clkout_clksel[] = {
-        { .parent = &sys_clkout_src, .rates = common_clkout_rates },
-        { .parent = NULL }
-};
-static struct clk sys_clkout = {
-        .name           = "sys_clkout",
-        .ops            = &clkops_null,
-        .parent         = &sys_clkout_src,
-        .clkdm_name     = "wkup_clkdm",
-        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
-        .clksel         = sys_clkout_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2_src = {
-        .name           = "sys_clkout2_src",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &func_54m_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
-        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
-        .clksel         = common_clkout_src_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static const struct clksel sys_clkout2_clksel[] = {
-        { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
-        { .parent = NULL }
-};
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2 = {
-        .name           = "sys_clkout2",
-        .ops            = &clkops_null,
-        .parent         = &sys_clkout2_src,
-        .clkdm_name     = "wkup_clkdm",
-        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
-        .clksel         = sys_clkout2_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk emul_ck = {
-        .name           = "emul_ck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &func_54m_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP2420_PRCM_CLKEMUL_CTRL,
-        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * MPU clock domain
- *      Clocks:
- *              MPU_FCLK, MPU_ICLK
- *              INT_M_FCLK, INT_M_I_CLK
- *
- * - Individual clocks are hardware managed.
- * - Base divider comes from: CM_CLKSEL_MPU
- *
- */
-static const struct clksel_rate mpu_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_242X },
-        { .div = 6, .val = 6, .flags = RATE_IN_242X },
-        { .div = 8, .val = 8, .flags = RATE_IN_242X },
-        { .div = 0 },
-};
-static const struct clksel mpu_clksel[] = {
-        { .parent = &core_ck, .rates = mpu_core_rates },
-        { .parent = NULL }
-};
-static struct clk mpu_ck = {    /* Control cpu */
-        .name           = "mpu_ck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .clkdm_name     = "mpu_clkdm",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
-        .clksel         = mpu_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * DSP (2420-UMA+IVA1) clock domain
- * Clocks:
- *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
- *
- * Won't be too specific here. The core clock comes into this block
- * it is divided then tee'ed. One branch goes directly to xyz enable
- * controls. The other branch gets further divided by 2 then possibly
- * routed into a synchronizer and out of clocks abc.
- */
-static const struct clksel_rate dsp_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_242X },
-        { .div = 8, .val = 8, .flags = RATE_IN_242X },
-        { .div = 12, .val = 12, .flags = RATE_IN_242X },
-        { .div = 0 },
-};
-static const struct clksel dsp_fck_clksel[] = {
-        { .parent = &core_ck, .rates = dsp_fck_core_rates },
-        { .parent = NULL }
-};
-static struct clk dsp_fck = {
-        .name           = "dsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_ck,
-        .clkdm_name     = "dsp_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
-        .clksel         = dsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel dsp_ick_clksel[] = {
-        { .parent = &dsp_fck, .rates = dsp_ick_rates },
-        { .parent = NULL }
-};
-static struct clk dsp_ick = {
-        .name           = "dsp_ick",     /* apparently ipi and isp */
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &dsp_fck,
-        .clkdm_name     = "dsp_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
-        .clksel         = dsp_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
- * the C54x, but which is contained in the DSP powerdomain.  Does not
- * exist on later OMAPs.
- */
-static struct clk iva1_ifck = {
-        .name           = "iva1_ifck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_ck,
-        .clkdm_name     = "iva1_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
-        .clksel         = dsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* IVA1 mpu/int/i/f clocks are /2 of parent */
-static struct clk iva1_mpu_int_ifck = {
-        .name           = "iva1_mpu_int_ifck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &iva1_ifck,
-        .clkdm_name     = "iva1_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/*
- * L3 clock domain
- * L3 clocks are used for both interface and functional clocks to
- * multiple entities. Some of these clocks are completely managed
- * by hardware, and some others allow software control. Hardware
- * managed ones general are based on directly CLK_REQ signals and
- * various auto idle settings. The functional spec sets many of these
- * as 'tie-high' for their enables.
- *
- * I-CLOCKS:
- *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
- *      CAM, HS-USB.
- * F-CLOCK
- *      SSI.
- *
- * GPMC memories and SDRC have timing and clock sensitive registers which
- * may very well need notification when the clock changes. Currently for low
- * operating points, these are taken care of in sleep.S.
- */
-static const struct clksel_rate core_l3_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_242X },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
-        { .div = 8, .val = 8, .flags = RATE_IN_242X },
-        { .div = 12, .val = 12, .flags = RATE_IN_242X },
-        { .div = 16, .val = 16, .flags = RATE_IN_242X },
-        { .div = 0 }
-};
-static const struct clksel core_l3_clksel[] = {
-        { .parent = &core_ck, .rates = core_l3_core_rates },
-        { .parent = NULL }
-};
-static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
-        .name           = "core_l3_ck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
-        .clksel         = core_l3_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* usb_l4_ick */
-static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel usb_l4_ick_clksel[] = {
-        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
-        { .parent = NULL },
-};
-/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
-static struct clk usb_l4_ick = {        /* FS-USB interface clock */
-        .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
-        .clksel         = usb_l4_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * L4 clock management domain
- *
- * This domain contains lots of interface clocks from the L4 interface, some
- * functional clocks.   Fixed APLL functional source clocks are managed in
- * this domain.
- */
-static const struct clksel_rate l4_core_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel l4_clksel[] = {
-        { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
-        { .parent = NULL }
-};
-static struct clk l4_ck = {             /* used both as an ick and fck */
-        .name           = "l4_ck",
-        .ops            = &clkops_null,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
-        .clksel         = l4_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * SSI is in L3 management domain, its direct parent is core not l3,
- * many core power domain entities are grouped into the L3 clock
- * domain.
- * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
- *
- * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
- */
-static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_242X },
-        { .div = 8, .val = 8, .flags = RATE_IN_242X },
-        { .div = 0 }
-};
-static const struct clksel ssi_ssr_sst_fck_clksel[] = {
-        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
-        { .parent = NULL }
-};
-static struct clk ssi_ssr_sst_fck = {
-        .name           = "ssi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_sst_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * Presumably this is the same as SSI_ICLK.
- * TRM contradicts itself on what clockdomain SSI_ICLK is in
- */
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * GFX clock domain
- *      Clocks:
- * GFX_FCLK, GFX_ICLK
- * GFX_CG1(2d), GFX_CG2(3d)
- *
- * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
- * The 2d and 3d clocks run at a hardware determined
- * divided value of fclk.
- *
- */
-/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
-static const struct clksel gfx_fck_clksel[] = {
-        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
-        { .parent = NULL },
-};
-static struct clk gfx_3d_fck = {
-        .name           = "gfx_3d_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "gfx_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
-        .clksel         = gfx_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk gfx_2d_fck = {
-        .name           = "gfx_2d_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "gfx_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
-        .clksel         = gfx_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* This interface clock does not have a CM_AUTOIDLE bit */
-static struct clk gfx_ick = {
-        .name           = "gfx_ick",            /* From l3 */
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "gfx_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP_EN_GFX_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * DSS clock domain
- * CLOCKs:
- * DSS_L4_ICLK, DSS_L3_ICLK,
- * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
- *
- * DSS is both initiator and target.
- */
-/* XXX Add RATE_NOT_VALIDATED */
-static const struct clksel_rate dss1_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate dss1_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
-        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
-        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
-        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
-        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel dss1_fck_clksel[] = {
-        { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
-        { .parent = &core_ck, .rates = dss1_fck_core_rates },
-        { .parent = NULL },
-};
-static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &l4_ck,       /* really both l3 and l4 */
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss1_fck = {
-        .name           = "dss1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &core_ck,             /* Core or sys */
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
-        .clksel         = dss1_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate dss2_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate dss2_fck_48m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel dss2_fck_clksel[] = {
-        { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
-        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
-        { .parent = NULL }
-};
-static struct clk dss2_fck = {          /* Alt clk used in power management */
-        .name           = "dss2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
-        .clksel         = dss2_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk dss_54m_fck = {       /* Alt clk used in power management */
-        .name           = "dss_54m_fck",        /* 54m tv clk */
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_54m_ck,
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wu_l4_ick = {
-        .name           = "wu_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/*
- * CORE power domain ICLK & FCLK defines.
- * Many of the these can have more than one possible parent. Entries
- * here will likely have an L4 interface parent, and may have multiple
- * functional clock parents.
- */
-static const struct clksel_rate gpt_alt_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel omap24xx_gpt_clksel[] = {
-        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
-        { .parent = &sys_ck,      .rates = gpt_sys_rates },
-        { .parent = &alt_ck,      .rates = gpt_alt_rates },
-        { .parent = NULL },
-};
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &secure_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel_rate common_mcbsp_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel mcbsp_fck_clksel[] = {
-        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
-        .clksel         = mcbsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
-        .clksel         = mcbsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcspi1_ick = {
-        .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi1_fck = {
-        .name           = "mcspi1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi2_ick = {
-        .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi2_fck = {
-        .name           = "mcspi2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpios_ick = {
-        .name           = "gpios_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpios_fck = {
-        .name           = "gpios_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mpu_wdt_ick = {
-        .name           = "mpu_wdt_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mpu_wdt_fck = {
-        .name           = "mpu_wdt_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sync_32k_ick = {
-        .name           = "sync_32k_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .flags          = ENABLE_ON_INIT,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .flags          = ENABLE_ON_INIT,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk cam_ick = {
-        .name           = "cam_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
- * split into two separate clocks, since the parent clocks are different
- * and the clockdomains are also different.
- */
-static struct clk cam_fck = {
-        .name           = "cam_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt4_ick = {
-        .name           = "wdt4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt4_fck = {
-        .name           = "wdt4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt3_ick = {
-        .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmc_ick = {
-        .name           = "mmc_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmc_fck = {
-        .name           = "mmc_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk fac_fck = {
-        .name           = "fac_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_12m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk eac_ick = {
-        .name           = "eac_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk eac_fck = {
-        .name           = "eac_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_12m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c2_ick = {
-        .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c2_fck = {
-        .name           = "i2c2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_12m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c1_ick = {
-        .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c1_fck = {
-        .name           = "i2c1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_12m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
- * accesses derived from this data.
- */
-static struct clk gpmc_fck = {
-        .name           = "gpmc_fck",
-        .ops            = &clkops_omap2_iclk_idle_only,
-        .parent         = &core_l3_ck,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sdma_fck = {
-        .name           = "sdma_fck",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/*
- * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
- * accesses derived from this data.
- */
-static struct clk sdma_ick = {
-        .name           = "sdma_ick",
-        .ops            = &clkops_omap2_iclk_idle_only,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
- * accesses derived from this data.
- */
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .ops            = &clkops_omap2_iclk_idle_only,
-        .parent         = &core_l3_ck,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP24XX_AUTO_SDRC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk vlynq_ick = {
-        .name           = "vlynq_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel_rate vlynq_fck_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_242X },
-        { .div = 0 }
-};
-static const struct clksel_rate vlynq_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_242X },
-        { .div = 2, .val = 2, .flags = RATE_IN_242X },
-        { .div = 3, .val = 3, .flags = RATE_IN_242X },
-        { .div = 4, .val = 4, .flags = RATE_IN_242X },
-        { .div = 6, .val = 6, .flags = RATE_IN_242X },
-        { .div = 8, .val = 8, .flags = RATE_IN_242X },
-        { .div = 9, .val = 9, .flags = RATE_IN_242X },
-        { .div = 12, .val = 12, .flags = RATE_IN_242X },
-        { .div = 16, .val = 16, .flags = RATE_IN_242X },
-        { .div = 18, .val = 18, .flags = RATE_IN_242X },
-        { .div = 0 }
-};
-static const struct clksel vlynq_fck_clksel[] = {
-        { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
-        { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
-        { .parent = NULL }
-};
-static struct clk vlynq_fck = {
-        .name           = "vlynq_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
-        .clksel         = vlynq_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk des_ick = {
-        .name           = "des_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sha_ick = {
-        .name           = "sha_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk aes_ick = {
-        .name           = "aes_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_fck = {
-        .name           = "usb_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * This clock is a composite clock which does entire set changes then
- * forces a rebalance. It keys on the MPU speed, but it really could
- * be any key speed part of a set in the rate table.
- *
- * to really change a set, you need memory table sets which get changed
- * in sram, pre-notifiers & post notifiers, changing the top set, without
- * having low level display recalc's won't work... this is why dpm notifiers
- * work, isr's off, walk a list of clocks already _off_ and not messing with
- * the bus.
- *
- * This clock should have no parent. It embodies the entire upper level
- * active set. A parent will mess up some of the init also.
- */
-static struct clk virt_prcm_set = {
-        .name           = "virt_prcm_set",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
-        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
-        .set_rate       = &omap2_select_table_rate,
-        .round_rate     = &omap2_round_to_table_rate,
-};
-/*
- * clkdev integration
- */
-static struct omap_clk omap2420_clks[] = {
-        /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
-        /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
-        /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
-        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
-        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
-        /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
-        /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
-        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
-        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
-        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
-        /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
-        /* DSS domain clocks */
-        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
-        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
-        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
-        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
-        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
-        /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
-        /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
-        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
-        /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
-        /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
-        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
-        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
-        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
-        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
-        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
-        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
-        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
-        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
-        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
-        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
-        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
-        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
-        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
-        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
-        CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
-        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
-        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
-        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
-        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
-        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
-};
-/*
- * init code
- */
-int __init omap2420_clk_init(void)
-{
-        const struct prcm_config *prcm;
-        struct omap_clk *c;
-        u32 clkrate;
-        prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
-        cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
-        cpu_mask = RATE_IN_242X;
-        rate_table = omap2420_rate_table;
-        clk_init(&omap2_clk_functions);
-        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
-             c++)
-                clk_preinit(c->lk.clk);
-        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
-        propagate_rate(&osc_ck);
-        sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
-        propagate_rate(&sys_ck);
-        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
-             c++) {
-                clkdev_add(&c->lk);
-                clk_register(c->lk.clk);
-                omap2_init_clk_clkdm(c->lk.clk);
-        }
-        /* Disable autoidle on all clocks; let the PM code enable it later */
-        omap_clk_disable_autoidle_all();
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                        break;
-        }
-        curr_prcm_set = prcm;
-        recalculate_root_clocks();
-        pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
-                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-        dclk = clk_get(NULL, "dpll_ck");
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index a8e326177466..cef0c8d1de52 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -21,13 +21,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 /**
@@ -42,7 +40,7 @@
 * passes back the correct CM_IDLEST register address for I2CHS
 * modules.  No return value.
 */
-static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk,
                                           void __iomem **idlest_reg,
                                           u8 *idlest_bit,
                                           u8 *idlest_val)
@@ -53,9 +51,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
 }
 /* 2430 I2CHS has non-standard IDLEST register */
-const struct clkops clkops_omap2430_i2chs_wait = {
+const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
        .find_idlest    = omap2430_clk_i2chs_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
deleted file mode 100644
index 22404fe435e7..000000000000
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ /dev/null
@@ -1,2089 +0,0 @@
-/*
- * OMAP2430 clock data
- *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2011 Nokia Corporation
- *
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/list.h>
-#include <plat/clkdev_omap.h>
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-24xx.h"
-#include "cm-regbits-24xx.h"
-#include "sdrc.h"
-#include "control.h"
-#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
-/*
- * 2430 clock tree.
- *
- * NOTE:In many cases here we are assigning a 'default' parent. In
- *      many cases the parent is selectable. The set parent calls will
- *      also switch sources.
- *
- *      Several sources are given initial rates which may be wrong, this will
- *      be fixed up in the init func.
- *
- *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most peripherals have dependencies on multiple clock
- *      domains. Many get their interface clocks from the L4 domain, but get
- *      functional clocks from fixed sources or other core domain derived
- *      clocks.
- */
-/* Base external input clocks */
-static struct clk func_32k_ck = {
-        .name           = "func_32k_ck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .clkdm_name     = "wkup_clkdm",
-};
-static struct clk secure_32k_ck = {
-        .name           = "secure_32k_ck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .clkdm_name     = "wkup_clkdm",
-};
-/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
-static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
-        .name           = "osc_ck",
-        .ops            = &clkops_oscck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_osc_clk_recalc,
-};
-/* Without modem likely 12MHz, with modem likely 13MHz */
-static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
-        .name           = "sys_ck",             /* ~ ref_clk also */
-        .ops            = &clkops_null,
-        .parent         = &osc_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2xxx_sys_clk_recalc,
-};
-static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
-        .name           = "alt_ck",
-        .ops            = &clkops_null,
-        .rate           = 54000000,
-        .clkdm_name     = "wkup_clkdm",
-};
-/* Optional external clock input for McBSP CLKS */
-static struct clk mcbsp_clks = {
-        .name           = "mcbsp_clks",
-        .ops            = &clkops_null,
-};
-/*
- * Analog domain root source clocks
- */
-/* dpll_ck, is broken out in to special cases through clksel */
-/* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
- * deal with this
- */
-static struct dpll_data dpll_dd = {
-        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
-        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
-        .clk_bypass             = &sys_ck,
-        .clk_ref                = &sys_ck,
-        .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask            = OMAP24XX_EN_DPLL_MASK,
-        .max_multiplier         = 1023,
-        .min_divider            = 1,
-        .max_divider            = 16,
-};
-/*
- * XXX Cannot add round_rate here yet, as this is still a composite clock,
- * not just a DPLL
- */
-static struct clk dpll_ck = {
-        .name           = "dpll_ck",
-        .ops            = &clkops_omap2xxx_dpll_ops,
-        .parent         = &sys_ck,              /* Can be func_32k also */
-        .dpll_data      = &dpll_dd,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_dpllcore_recalc,
-        .set_rate       = &omap2_reprogram_dpllcore,
-};
-static struct clk apll96_ck = {
-        .name           = "apll96_ck",
-        .ops            = &clkops_apll96,
-        .parent         = &sys_ck,
-        .rate           = 96000000,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
-};
-static struct clk apll54_ck = {
-        .name           = "apll54_ck",
-        .ops            = &clkops_apll54,
-        .parent         = &sys_ck,
-        .rate           = 54000000,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
-};
-/*
- * PRCM digital base sources
- */
-/* func_54m_ck */
-static const struct clksel_rate func_54m_apll54_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel_rate func_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel func_54m_clksel[] = {
-        { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
-        { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
-        { .parent = NULL },
-};
-static struct clk func_54m_ck = {
-        .name           = "func_54m_ck",
-        .ops            = &clkops_null,
-        .parent         = &apll54_ck,   /* can also be alt_clk */
-        .clkdm_name     = "wkup_clkdm",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
-        .clksel         = func_54m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll_ck,             /* can also be 32k */
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* func_96m_ck */
-static const struct clksel_rate func_96m_apll96_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel_rate func_96m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_243X },
-        { .div = 0 },
-};
-static const struct clksel func_96m_clksel[] = {
-        { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
-        { .parent = &alt_ck,    .rates = func_96m_alt_rates },
-        { .parent = NULL }
-};
-static struct clk func_96m_ck = {
-        .name           = "func_96m_ck",
-        .ops            = &clkops_null,
-        .parent         = &apll96_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP2430_96M_SOURCE_MASK,
-        .clksel         = func_96m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* func_48m_ck */
-static const struct clksel_rate func_48m_apll96_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel_rate func_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel func_48m_clksel[] = {
-        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
-        { .parent = &alt_ck, .rates = func_48m_alt_rates },
-        { .parent = NULL }
-};
-static struct clk func_48m_ck = {
-        .name           = "func_48m_ck",
-        .ops            = &clkops_null,
-        .parent         = &apll96_ck,    /* 96M or Alt */
-        .clkdm_name     = "wkup_clkdm",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
-        .clksel         = func_48m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk func_12m_ck = {
-        .name           = "func_12m_ck",
-        .ops            = &clkops_null,
-        .parent         = &func_48m_ck,
-        .fixed_div      = 4,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/* Secure timer, only available in secure mode */
-static struct clk wdt1_osc_ck = {
-        .name           = "ck_wdt1_osc",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &osc_ck,
-        .recalc         = &followparent_recalc,
-};
-/*
- * The common_clkout* clksel_rate structs are common to
- * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
- * sys_clkout2_* are 2420-only, so the
- * clksel_rate flags fields are inaccurate for those clocks. This is
- * harmless since access to those clocks are gated by the struct clk
- * flags fields, which mark them as 2420-only.
- */
-static const struct clksel_rate common_clkout_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_clkout_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_clkout_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_clkout_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel common_clkout_src_clksel[] = {
-        { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
-        { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
-        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
-        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
-        { .parent = NULL }
-};
-static struct clk sys_clkout_src = {
-        .name           = "sys_clkout_src",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &func_54m_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
-        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
-        .clksel         = common_clkout_src_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static const struct clksel_rate common_clkout_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 16, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel sys_clkout_clksel[] = {
-        { .parent = &sys_clkout_src, .rates = common_clkout_rates },
-        { .parent = NULL }
-};
-static struct clk sys_clkout = {
-        .name           = "sys_clkout",
-        .ops            = &clkops_null,
-        .parent         = &sys_clkout_src,
-        .clkdm_name     = "wkup_clkdm",
-        .clksel_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
-        .clksel         = sys_clkout_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk emul_ck = {
-        .name           = "emul_ck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &func_54m_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP2430_PRCM_CLKEMUL_CTRL,
-        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * MPU clock domain
- *      Clocks:
- *              MPU_FCLK, MPU_ICLK
- *              INT_M_FCLK, INT_M_I_CLK
- *
- * - Individual clocks are hardware managed.
- * - Base divider comes from: CM_CLKSEL_MPU
- *
- */
-static const struct clksel_rate mpu_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel mpu_clksel[] = {
-        { .parent = &core_ck, .rates = mpu_core_rates },
-        { .parent = NULL }
-};
-static struct clk mpu_ck = {    /* Control cpu */
-        .name           = "mpu_ck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .clkdm_name     = "mpu_clkdm",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
-        .clksel         = mpu_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * DSP (2430-IVA2.1) clock domain
- * Clocks:
- *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
- *
- * Won't be too specific here. The core clock comes into this block
- * it is divided then tee'ed. One branch goes directly to xyz enable
- * controls. The other branch gets further divided by 2 then possibly
- * routed into a synchronizer and out of clocks abc.
- */
-static const struct clksel_rate dsp_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-static const struct clksel dsp_fck_clksel[] = {
-        { .parent = &core_ck, .rates = dsp_fck_core_rates },
-        { .parent = NULL }
-};
-static struct clk dsp_fck = {
-        .name           = "dsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_ck,
-        .clkdm_name     = "dsp_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
-        .clksel         = dsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel dsp_ick_clksel[] = {
-        { .parent = &dsp_fck, .rates = dsp_ick_rates },
-        { .parent = NULL }
-};
-/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
-static struct clk iva2_1_ick = {
-        .name           = "iva2_1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dsp_fck,
-        .clkdm_name     = "dsp_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
-        .clksel         = dsp_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * L3 clock domain
- * L3 clocks are used for both interface and functional clocks to
- * multiple entities. Some of these clocks are completely managed
- * by hardware, and some others allow software control. Hardware
- * managed ones general are based on directly CLK_REQ signals and
- * various auto idle settings. The functional spec sets many of these
- * as 'tie-high' for their enables.
- *
- * I-CLOCKS:
- *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
- *      CAM, HS-USB.
- * F-CLOCK
- *      SSI.
- *
- * GPMC memories and SDRC have timing and clock sensitive registers which
- * may very well need notification when the clock changes. Currently for low
- * operating points, these are taken care of in sleep.S.
- */
-static const struct clksel_rate core_l3_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel core_l3_clksel[] = {
-        { .parent = &core_ck, .rates = core_l3_core_rates },
-        { .parent = NULL }
-};
-static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
-        .name           = "core_l3_ck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
-        .clksel         = core_l3_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* usb_l4_ick */
-static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel usb_l4_ick_clksel[] = {
-        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
-        { .parent = NULL },
-};
-/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
-static struct clk usb_l4_ick = {        /* FS-USB interface clock */
-        .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
-        .clksel         = usb_l4_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * L4 clock management domain
- *
- * This domain contains lots of interface clocks from the L4 interface, some
- * functional clocks.   Fixed APLL functional source clocks are managed in
- * this domain.
- */
-static const struct clksel_rate l4_core_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel l4_clksel[] = {
-        { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
-        { .parent = NULL }
-};
-static struct clk l4_ck = {             /* used both as an ick and fck */
-        .name           = "l4_ck",
-        .ops            = &clkops_null,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
-        .clksel         = l4_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * SSI is in L3 management domain, its direct parent is core not l3,
- * many core power domain entities are grouped into the L3 clock
- * domain.
- * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
- *
- * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
- */
-static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 5, .val = 5, .flags = RATE_IN_243X },
-        { .div = 0 }
-};
-static const struct clksel ssi_ssr_sst_fck_clksel[] = {
-        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
-        { .parent = NULL }
-};
-static struct clk ssi_ssr_sst_fck = {
-        .name           = "ssi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_sst_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * Presumably this is the same as SSI_ICLK.
- * TRM contradicts itself on what clockdomain SSI_ICLK is in
- */
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * GFX clock domain
- *      Clocks:
- * GFX_FCLK, GFX_ICLK
- * GFX_CG1(2d), GFX_CG2(3d)
- *
- * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
- * The 2d and 3d clocks run at a hardware determined
- * divided value of fclk.
- *
- */
-/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
-static const struct clksel gfx_fck_clksel[] = {
-        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
-        { .parent = NULL },
-};
-static struct clk gfx_3d_fck = {
-        .name           = "gfx_3d_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "gfx_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
-        .clksel         = gfx_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk gfx_2d_fck = {
-        .name           = "gfx_2d_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "gfx_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
-        .clksel         = gfx_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* This interface clock does not have a CM_AUTOIDLE bit */
-static struct clk gfx_ick = {
-        .name           = "gfx_ick",            /* From l3 */
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "gfx_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP_EN_GFX_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * Modem clock domain (2430)
- *      CLOCKS:
- *              MDM_OSC_CLK
- *              MDM_ICLK
- * These clocks are usable in chassis mode only.
- */
-static const struct clksel_rate mdm_ick_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_243X },
-        { .div = 4, .val = 4, .flags = RATE_IN_243X },
-        { .div = 6, .val = 6, .flags = RATE_IN_243X },
-        { .div = 9, .val = 9, .flags = RATE_IN_243X },
-        { .div = 0 }
-};
-static const struct clksel mdm_ick_clksel[] = {
-        { .parent = &core_ck, .rates = mdm_ick_core_rates },
-        { .parent = NULL }
-};
-static struct clk mdm_ick = {           /* used both as a ick and fck */
-        .name           = "mdm_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_ck,
-        .clkdm_name     = "mdm_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
-        .clksel         = mdm_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mdm_osc_ck = {
-        .name           = "mdm_osc_ck",
-        .ops            = &clkops_omap2_mdmclk_dflt_wait,
-        .parent         = &osc_ck,
-        .clkdm_name     = "mdm_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * DSS clock domain
- * CLOCKs:
- * DSS_L4_ICLK, DSS_L3_ICLK,
- * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
- *
- * DSS is both initiator and target.
- */
-/* XXX Add RATE_NOT_VALIDATED */
-static const struct clksel_rate dss1_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate dss1_fck_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
-        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
-        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
-        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
-        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
-        { .div = 16, .val = 16, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel dss1_fck_clksel[] = {
-        { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
-        { .parent = &core_ck, .rates = dss1_fck_core_rates },
-        { .parent = NULL },
-};
-static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &l4_ck,       /* really both l3 and l4 */
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss1_fck = {
-        .name           = "dss1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &core_ck,             /* Core or sys */
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
-        .clksel         = dss1_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate dss2_fck_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate dss2_fck_48m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel dss2_fck_clksel[] = {
-        { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
-        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
-        { .parent = NULL }
-};
-static struct clk dss2_fck = {          /* Alt clk used in power management */
-        .name           = "dss2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
-        .clksel         = dss2_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk dss_54m_fck = {       /* Alt clk used in power management */
-        .name           = "dss_54m_fck",        /* 54m tv clk */
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_54m_ck,
-        .clkdm_name     = "dss_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wu_l4_ick = {
-        .name           = "wu_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/*
- * CORE power domain ICLK & FCLK defines.
- * Many of the these can have more than one possible parent. Entries
- * here will likely have an L4 interface parent, and may have multiple
- * functional clock parents.
- */
-static const struct clksel_rate gpt_alt_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel omap24xx_gpt_clksel[] = {
-        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
-        { .parent = &sys_ck,      .rates = gpt_sys_rates },
-        { .parent = &alt_ck,      .rates = gpt_alt_rates },
-        { .parent = NULL },
-};
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &secure_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
-        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
-        .clksel         = omap24xx_gpt_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel_rate common_mcbsp_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 0 }
-};
-static const struct clksel mcbsp_fck_clksel[] = {
-        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
-        .clksel         = mcbsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
-        .clksel         = mcbsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
-        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
-        .clksel         = mcbsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
-        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
-        .clksel         = mcbsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
-        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
-        .clksel         = mcbsp_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcspi1_ick = {
-        .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi1_fck = {
-        .name           = "mcspi1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi2_ick = {
-        .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi2_fck = {
-        .name           = "mcspi2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi3_ick = {
-        .name           = "mcspi3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi3_fck = {
-        .name           = "mcspi3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpios_ick = {
-        .name           = "gpios_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpios_fck = {
-        .name           = "gpios_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mpu_wdt_ick = {
-        .name           = "mpu_wdt_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mpu_wdt_fck = {
-        .name           = "mpu_wdt_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sync_32k_ick = {
-        .name           = "sync_32k_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .flags          = ENABLE_ON_INIT,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .flags          = ENABLE_ON_INIT,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk icr_ick = {
-        .name           = "icr_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wu_l4_ick,
-        .clkdm_name     = "wkup_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk cam_ick = {
-        .name           = "cam_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
- * split into two separate clocks, since the parent clocks are different
- * and the clockdomains are also different.
- */
-static struct clk cam_fck = {
-        .name           = "cam_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt4_ick = {
-        .name           = "wdt4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt4_fck = {
-        .name           = "wdt4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk fac_fck = {
-        .name           = "fac_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_12m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_12m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * XXX This is marked as a 2420-only define, but it claims to be present
- * on 2430 also.  Double-check.
- */
-static struct clk i2c2_ick = {
-        .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2chs2_fck = {
-        .name           = "i2chs2_fck",
-        .ops            = &clkops_omap2430_i2chs_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * XXX This is marked as a 2420-only define, but it claims to be present
- * on 2430 also.  Double-check.
- */
-static struct clk i2c1_ick = {
-        .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2chs1_fck = {
-        .name           = "i2chs1_fck",
-        .ops            = &clkops_omap2430_i2chs_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
- * accesses derived from this data.
- */
-static struct clk gpmc_fck = {
-        .name           = "gpmc_fck",
-        .ops            = &clkops_omap2_iclk_idle_only,
-        .parent         = &core_l3_ck,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sdma_fck = {
-        .name           = "sdma_fck",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/*
- * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
- * accesses derived from this data.
- */
-static struct clk sdma_ick = {
-        .name           = "sdma_ick",
-        .ops            = &clkops_omap2_iclk_idle_only,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .ops            = &clkops_omap2_iclk_idle_only,
-        .parent         = &core_l3_ck,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk des_ick = {
-        .name           = "des_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sha_ick = {
-        .name           = "sha_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk aes_ick = {
-        .name           = "aes_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
-        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_fck = {
-        .name           = "usb_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_48m_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usbhs_ick = {
-        .name           = "usbhs_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l3_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs1_ick = {
-        .name           = "mmchs1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs1_fck = {
-        .name           = "mmchs1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs2_ick = {
-        .name           = "mmchs2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs2_fck = {
-        .name           = "mmchs2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio5_fck = {
-        .name           = "gpio5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mdm_intc_ick = {
-        .name           = "mdm_intc_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchsdb1_fck = {
-        .name           = "mmchsdb1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchsdb2_fck = {
-        .name           = "mmchsdb2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &func_32k_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
-        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * This clock is a composite clock which does entire set changes then
- * forces a rebalance. It keys on the MPU speed, but it really could
- * be any key speed part of a set in the rate table.
- *
- * to really change a set, you need memory table sets which get changed
- * in sram, pre-notifiers & post notifiers, changing the top set, without
- * having low level display recalc's won't work... this is why dpm notifiers
- * work, isr's off, walk a list of clocks already _off_ and not messing with
- * the bus.
- *
- * This clock should have no parent. It embodies the entire upper level
- * active set. A parent will mess up some of the init also.
- */
-static struct clk virt_prcm_set = {
-        .name           = "virt_prcm_set",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
-        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
-        .set_rate       = &omap2_select_table_rate,
-        .round_rate     = &omap2_round_to_table_rate,
-};
-/*
- * clkdev integration
- */
-static struct omap_clk omap2430_clks[] = {
-        /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
-        CLK("twl",      "fck",          &osc_ck,        CK_243X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
-        /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X),
-        /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
-        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
-        /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
-        /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
-        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
-        /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X),
-        /* Modem domain clocks */
-        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
-        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
-        /* DSS domain clocks */
-        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
-        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
-        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
-        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
-        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
-        /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X),
-        /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
-        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_243X),
-        /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
-        /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
-        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
-        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
-        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
-        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
-        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
-        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
-        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
-        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
-        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
-        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
-        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
-        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
-        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
-        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
-        CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
-        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
-        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
-        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
-        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
-        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
-        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
-        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
-        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
-        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
-        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
-        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
-        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
-        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
-        CLK(NULL,       "mmchsdb1_fck",         &mmchsdb1_fck,  CK_243X),
-        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
-        CLK(NULL,       "mmchsdb2_fck",         &mmchsdb2_fck,  CK_243X),
-        CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
-        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
-};
-/*
- * init code
- */
-int __init omap2430_clk_init(void)
-{
-        const struct prcm_config *prcm;
-        struct omap_clk *c;
-        u32 clkrate;
-        prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
-        cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
-        cpu_mask = RATE_IN_243X;
-        rate_table = omap2430_rate_table;
-        clk_init(&omap2_clk_functions);
-        for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
-             c++)
-                clk_preinit(c->lk.clk);
-        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
-        propagate_rate(&osc_ck);
-        sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
-        propagate_rate(&sys_ck);
-        for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
-             c++) {
-                clkdev_add(&c->lk);
-                clk_register(c->lk.clk);
-                omap2_init_clk_clkdm(c->lk.clk);
-        }
-        /* Disable autoidle on all clocks; let the PM code enable it later */
-        omap_clk_disable_autoidle_all();
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                        break;
-        }
-        curr_prcm_set = prcm;
-        recalculate_root_clocks();
-        pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
-                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-        dclk = clk_get(NULL, "dpll_ck");
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index e92be1fc1a00..1ff646908627 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -22,35 +22,18 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm.h"
 #include "cm-regbits-24xx.h"
-struct clk *vclk, *sclk, *dclk;
+struct clk_hw *dclk_hw;
 /*
 * Omap24xx specific clock functions
 */
 /*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2xxx_clk_prepare_for_reboot(void)
-{
-        u32 rate;
-        if (vclk == NULL || sclk == NULL)
-                return;
-        rate = clk_get_rate(sclk);
-        clk_set_rate(vclk, rate);
-}
-/*
 * Switch the MPU rate if specified on cmdline.  We cannot do this
 * early until cmdline is parsed.  XXX This should be removed from the
 * clock code and handled by the OPP layer code in the near future.
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index cb6df8ca9e4a..539dc08afbba 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -8,17 +8,34 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
-unsigned long omap2_table_mpu_recalc(struct clk *clk);
+#include <linux/clk-provider.h>
-int omap2_select_table_rate(struct clk *clk, unsigned long rate);
+#include "clock.h"
-long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-unsigned long omap2xxx_sys_clk_recalc(struct clk *clk);
+unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
-unsigned long omap2_osc_clk_recalc(struct clk *clk);
+                                     unsigned long parent_rate);
-unsigned long omap2_dpllcore_recalc(struct clk *clk);
+int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
-int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
+                            unsigned long parent_rate);
-unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
+long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *parent_rate);
+unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
+                                      unsigned long parent_rate);
+unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
+                                   unsigned long parent_rate);
+unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
+                                    unsigned long parent_rate);
+int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
+                             unsigned long parent_rate);
+void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
+unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
+                                      unsigned long parent_rate);
+unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
+                                      unsigned long parent_rate);
+unsigned long omap2xxx_clk_get_core_rate(void);
 u32 omap2xxx_get_apll_clkin(void);
 u32 omap2xxx_get_sysclkdiv(void);
 void omap2xxx_clk_prepare_for_reboot(void);
+void omap2xxx_clkt_vps_check_bootloader_rates(void);
+void omap2xxx_clkt_vps_late_init(void);
 #ifdef CONFIG_SOC_OMAP2420
 int omap2420_clk_init(void);
@@ -32,13 +49,14 @@ int omap2430_clk_init(void);
 #define omap2430_clk_init()     do { } while(0)
 #endif
-extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;
+extern void __iomem *prcm_clksrc_ctrl;
-extern struct clk *dclk;
+extern struct clk_hw *dclk_hw;
+int omap2_enable_osc_ck(struct clk_hw *hw);
-extern const struct clkops clkops_omap2430_i2chs_wait;
+void omap2_disable_osc_ck(struct clk_hw *hw);
-extern const struct clkops clkops_oscck;
+int omap2_clk_apll96_enable(struct clk_hw *hw);
-extern const struct clkops clkops_apll96;
+int omap2_clk_apll54_enable(struct clk_hw *hw);
-extern const struct clkops clkops_apll54;
+void omap2_clk_apll96_disable(struct clk_hw *hw);
+void omap2_clk_apll54_disable(struct clk_hw *hw);
 #endif
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
deleted file mode 100644
index 1a45d6bd2539..000000000000
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ /dev/null
@@ -1,1112 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <plat/clkdev_omap.h>
-#include "am33xx.h"
-#include "iomap.h"
-#include "control.h"
-#include "clock.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-/* Maximum DPLL multiplier, divider values for AM33XX */
-#define AM33XX_MAX_DPLL_MULT            2047
-#define AM33XX_MAX_DPLL_DIV             128
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL        0
-#define AM33XX_MODULEMODE_SWCTRL        1
-/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
- *    physically present, in such a case HWMOD enabling of
- *    clock would be failure with default parent. And timer
- *    probe thinks clock is already enabled, this leads to
- *    crash upon accessing timer 3 & 6 registers in probe.
- *    Fix by setting parent of both these timers to master
- *    oscillator clock.
- */
-static inline void am33xx_init_timer_parent(struct clk *clk)
-{
-        omap2_clksel_set_parent(clk, clk->parent);
-}
-/* Root clocks */
-/* RTC 32k */
-static struct clk clk_32768_ck = {
-        .name           = "clk_32768_ck",
-        .clkdm_name     = "l4_rtc_clkdm",
-        .rate           = 32768,
-        .ops            = &clkops_null,
-};
-/* On-Chip 32KHz RC OSC */
-static struct clk clk_rc32k_ck = {
-        .name           = "clk_rc32k_ck",
-        .rate           = 32000,
-        .ops            = &clkops_null,
-};
-/* Crystal input clks */
-static struct clk virt_24000000_ck = {
-        .name           = "virt_24000000_ck",
-        .rate           = 24000000,
-        .ops            = &clkops_null,
-};
-static struct clk virt_25000000_ck = {
-        .name           = "virt_25000000_ck",
-        .rate           = 25000000,
-        .ops            = &clkops_null,
-};
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const struct clksel sys_clkin_sel[] = {
-        { .parent = &virt_19200000_ck, .rates = div_1_0_rates },
-        { .parent = &virt_24000000_ck, .rates = div_1_1_rates },
-        { .parent = &virt_25000000_ck, .rates = div_1_2_rates },
-        { .parent = &virt_26000000_ck, .rates = div_1_3_rates },
-        { .parent = NULL },
-};
-/* External clock - 12 MHz */
-static struct clk tclkin_ck = {
-        .name           = "tclkin_ck",
-        .rate           = 12000000,
-        .ops            = &clkops_null,
-};
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-static struct clk sys_clkin_ck = {
-        .name           = "sys_clkin_ck",
-        .parent         = &virt_24000000_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-        .clksel_mask    = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK,
-        .clksel         = sys_clkin_sel,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = AM33XX_MAX_DPLL_MULT,
-        .max_divider    = AM33XX_MAX_DPLL_DIV,
-        .min_divider    = 1,
-};
-/* CLKDCOLDO output */
-static struct clk dpll_core_ck = {
-        .name           = "dpll_core_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_core_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_core_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-};
-static struct clk dpll_core_x2_ck = {
-        .name           = "dpll_core_x2_ck",
-        .parent         = &dpll_core_ck,
-        .flags          = CLOCK_CLKOUTX2,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel dpll_core_m4_div[] = {
-        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_core_m4_ck = {
-        .name           = "dpll_core_m4_ck",
-        .parent         = &dpll_core_x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = dpll_core_m4_div,
-        .clksel_reg     = AM33XX_CM_DIV_M4_DPLL_CORE,
-        .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel dpll_core_m5_div[] = {
-        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_core_m5_ck = {
-        .name           = "dpll_core_m5_ck",
-        .parent         = &dpll_core_x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = dpll_core_m5_div,
-        .clksel_reg     = AM33XX_CM_DIV_M5_DPLL_CORE,
-        .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel dpll_core_m6_div[] = {
-        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_core_m6_ck = {
-        .name           = "dpll_core_m6_ck",
-        .parent         = &dpll_core_x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = dpll_core_m6_div,
-        .clksel_reg     = AM33XX_CM_DIV_M6_DPLL_CORE,
-        .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = AM33XX_MAX_DPLL_MULT,
-        .max_divider    = AM33XX_MAX_DPLL_DIV,
-        .min_divider    = 1,
-};
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck = {
-        .name           = "dpll_mpu_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_mpu_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-static const struct clksel dpll_mpu_m2_div[] = {
-        { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_mpu_m2_ck = {
-        .name           = "dpll_mpu_m2_ck",
-        .clkdm_name     = "mpu_clkdm",
-        .parent         = &dpll_mpu_ck,
-        .clksel         = dpll_mpu_m2_div,
-        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_MPU,
-        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = AM33XX_MAX_DPLL_MULT,
-        .max_divider    = AM33XX_MAX_DPLL_DIV,
-        .min_divider    = 1,
-};
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck = {
-        .name           = "dpll_ddr_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_ddr_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_dpll_recalc,
-};
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-static const struct clksel dpll_ddr_m2_div[] = {
-        { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_ddr_m2_ck = {
-        .name           = "dpll_ddr_m2_ck",
-        .parent         = &dpll_ddr_ck,
-        .clksel         = dpll_ddr_m2_div,
-        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DDR,
-        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-/* emif_fck functional clock */
-static struct clk dpll_ddr_m2_div2_ck = {
-        .name           = "dpll_ddr_m2_div2_ck",
-        .clkdm_name     = "l3_clkdm",
-        .parent         = &dpll_ddr_m2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = AM33XX_MAX_DPLL_MULT,
-        .max_divider    = AM33XX_MAX_DPLL_DIV,
-        .min_divider    = 1,
-};
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck = {
-        .name           = "dpll_disp_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_disp_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-static const struct clksel dpll_disp_m2_div[] = {
-        { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_disp_m2_ck = {
-        .name           = "dpll_disp_m2_ck",
-        .parent         = &dpll_disp_ck,
-        .clksel         = dpll_disp_m2_div,
-        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DISP,
-        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
-        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
-        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = AM33XX_MAX_DPLL_MULT,
-        .max_divider    = AM33XX_MAX_DPLL_DIV,
-        .min_divider    = 1,
-        .flags          = DPLL_J_TYPE,
-};
-/* CLKDCOLDO */
-static struct clk dpll_per_ck = {
-        .name           = "dpll_per_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_per_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-/* CLKOUT: fdpll/M2 */
-static const struct clksel dpll_per_m2_div[] = {
-        { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_per_m2_ck = {
-        .name           = "dpll_per_m2_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
-        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
-        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_per_m2_div4_wkupdm_ck = {
-        .name           = "dpll_per_m2_div4_wkupdm_ck",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &dpll_per_m2_ck,
-        .fixed_div      = 4,
-        .ops            = &clkops_null,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk dpll_per_m2_div4_ck = {
-        .name           = "dpll_per_m2_div4_ck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &dpll_per_m2_ck,
-        .fixed_div      = 4,
-        .ops            = &clkops_null,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk l3_gclk = {
-        .name           = "l3_gclk",
-        .clkdm_name     = "l3_clkdm",
-        .parent         = &dpll_core_m4_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dpll_core_m4_div2_ck = {
-        .name           = "dpll_core_m4_div2_ck",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &dpll_core_m4_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk l4_rtc_gclk = {
-        .name           = "l4_rtc_gclk",
-        .parent         = &dpll_core_m4_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk clk_24mhz = {
-        .name           = "clk_24mhz",
-        .parent         = &dpll_per_m2_ck,
-        .fixed_div      = 8,
-        .ops            = &clkops_null,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static struct clk l4hs_gclk = {
-        .name           = "l4hs_gclk",
-        .clkdm_name     = "l4hs_clkdm",
-        .parent         = &dpll_core_m4_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk l3s_gclk = {
-        .name           = "l3s_gclk",
-        .clkdm_name     = "l3s_clkdm",
-        .parent         = &dpll_core_m4_div2_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk l4fw_gclk = {
-        .name           = "l4fw_gclk",
-        .clkdm_name     = "l4fw_clkdm",
-        .parent         = &dpll_core_m4_div2_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk l4ls_gclk = {
-        .name           = "l4ls_gclk",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &dpll_core_m4_div2_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sysclk_div_ck = {
-        .name           = "sysclk_div_ck",
-        .parent         = &dpll_core_m4_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck = {
-        .name           = "adc_tsc_fck",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dcan0_fck = {
-        .name           = "dcan0_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dcan1_fck = {
-        .name           = "dcan1_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcasp0_fck = {
-        .name           = "mcasp0_fck",
-        .clkdm_name     = "l3s_clkdm",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcasp1_fck = {
-        .name           = "mcasp1_fck",
-        .clkdm_name     = "l3s_clkdm",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk smartreflex0_fck = {
-        .name           = "smartreflex0_fck",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk smartreflex1_fck = {
-        .name           = "smartreflex1_fck",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- *  - hwmod data is not present for these modules, either hwmod
- *    control is not required or its not populated.
- *  - Driver code is not yet migrated to use hwmod/runtime pm
- *  - Modules outside kernel access (to disable them by default)
- *
- *     - debugss
- *     - mmu (gfx domain)
- *     - cefuse
- *     - usbotg_fck (its additional clock and not really a modulemode)
- *     - ieee5000
- */
-static struct clk debugss_ick = {
-        .name           = "debugss_ick",
-        .clkdm_name     = "l3_aon_clkdm",
-        .parent         = &dpll_core_m4_ck,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmu_fck = {
-        .name           = "mmu_fck",
-        .clkdm_name     = "gfx_l3_clkdm",
-        .parent         = &dpll_core_m4_ck,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
-        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
-        .recalc         = &followparent_recalc,
-};
-static struct clk cefuse_fck = {
-        .name           = "cefuse_fck",
-        .clkdm_name     = "l4_cefuse_clkdm",
-        .parent         = &sys_clkin_ck,
-        .enable_reg     = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
-        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &followparent_recalc,
-};
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-static struct clk clkdiv32k_ick = {
-        .name           = "clkdiv32k_ick",
-        .clkdm_name     = "clk_24mhz_clkdm",
-        .rate           = 32768,
-        .parent         = &clk_24mhz,
-        .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
-        .ops            = &clkops_omap2_dflt,
-};
-static struct clk usbotg_fck = {
-        .name           = "usbotg_fck",
-        .clkdm_name     = "l3s_clkdm",
-        .parent         = &dpll_per_ck,
-        .enable_reg     = AM33XX_CM_CLKDCOLDO_DPLL_PER,
-        .enable_bit     = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &followparent_recalc,
-};
-static struct clk ieee5000_fck = {
-        .name           = "ieee5000_fck",
-        .clkdm_name     = "l3s_clkdm",
-        .parent         = &dpll_core_m4_div2_ck,
-        .enable_reg     = AM33XX_CM_PER_IEEE5000_CLKCTRL,
-        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &followparent_recalc,
-};
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-        { .parent = &tclkin_ck, .rates = div_1_2_rates },
-        { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-        { .parent = &clk_32768_ck, .rates = div_1_4_rates },
-        { .parent = NULL },
-};
-static struct clk timer1_fck = {
-        .name           = "timer1_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = timer1_clkmux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel timer2_to_7_clk_sel[] = {
-        { .parent = &tclkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-static struct clk timer2_fck = {
-        .name           = "timer2_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk timer3_fck = {
-        .name           = "timer3_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .init           = &am33xx_init_timer_parent,
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk timer4_fck = {
-        .name           = "timer4_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk timer5_fck = {
-        .name           = "timer5_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk timer6_fck = {
-        .name           = "timer6_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .init           = &am33xx_init_timer_parent,
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk timer7_fck = {
-        .name           = "timer7_fck",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk cpsw_125mhz_gclk = {
-        .name           = "cpsw_125mhz_gclk",
-        .clkdm_name     = "cpsw_125mhz_clkdm",
-        .parent         = &dpll_core_m5_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-        { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk cpsw_cpts_rft_clk = {
-        .name           = "cpsw_cpts_rft_clk",
-        .clkdm_name     = "cpsw_125mhz_clkdm",
-        .parent         = &dpll_core_m5_ck,
-        .clksel         = cpsw_cpts_rft_clkmux_sel,
-        .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
-        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-/* gpio */
-static const struct clksel gpio0_dbclk_mux_sel[] = {
-        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-        { .parent = &clk_32768_ck, .rates = div_1_1_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-static struct clk gpio0_dbclk_mux_ck = {
-        .name           = "gpio0_dbclk_mux_ck",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &clk_rc32k_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = gpio0_dbclk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpio0_dbclk = {
-        .name           = "gpio0_dbclk",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &gpio0_dbclk_mux_ck,
-        .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-        .enable_bit     = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio1_dbclk = {
-        .name           = "gpio1_dbclk",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &clkdiv32k_ick,
-        .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
-        .enable_bit     = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio2_dbclk = {
-        .name           = "gpio2_dbclk",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &clkdiv32k_ick,
-        .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
-        .enable_bit     = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio3_dbclk = {
-        .name           = "gpio3_dbclk",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &clkdiv32k_ick,
-        .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
-        .enable_bit     = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
-        { .parent = &l3_gclk, .rates = div_1_0_rates },
-        { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk pruss_ocp_gclk = {
-        .name           = "pruss_ocp_gclk",
-        .clkdm_name     = "pruss_ocp_clkdm",
-        .parent         = &l3_gclk,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = pruss_ocp_clk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_PRUSS_OCP_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel lcd_clk_mux_sel[] = {
-        { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-static struct clk lcd_gclk = {
-        .name           = "lcd_gclk",
-        .clkdm_name     = "lcdc_clkdm",
-        .parent         = &dpll_disp_m2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = lcd_clk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmc_clk = {
-        .name           = "mmc_clk",
-        .clkdm_name     = "l4ls_clkdm",
-        .parent         = &dpll_per_m2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk mmc2_fck = {
-        .name           = "mmc2_fck",
-        .clkdm_name     = "l3s_clkdm",
-        .parent         = &mmc_clk,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel gfx_clksel_sel[] = {
-        { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk gfx_fclk_clksel_ck = {
-        .name           = "gfx_fclk_clksel_ck",
-        .parent         = &dpll_core_m4_ck,
-        .clksel         = gfx_clksel_sel,
-        .ops            = &clkops_null,
-        .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
-        .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate div_1_0_2_1_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
-        { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
-        { .div = 0 },
-};
-static const struct clksel gfx_div_sel[] = {
-        { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
-        { .parent = NULL },
-};
-static struct clk gfx_fck_div_ck = {
-        .name           = "gfx_fck_div_ck",
-        .clkdm_name     = "gfx_l3_clkdm",
-        .parent         = &gfx_fclk_clksel_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = gfx_div_sel,
-        .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-        .ops            = &clkops_null,
-};
-static const struct clksel sysclkout_pre_sel[] = {
-        { .parent = &clk_32768_ck, .rates = div_1_0_rates },
-        { .parent = &l3_gclk, .rates = div_1_1_rates },
-        { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
-        { .parent = &lcd_gclk, .rates = div_1_4_rates },
-        { .parent = NULL },
-};
-static struct clk sysclkout_pre_ck = {
-        .name           = "sysclkout_pre_ck",
-        .parent         = &clk_32768_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = sysclkout_pre_sel,
-        .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
-        .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clksel_rate div8_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
-        { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
-        { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
-        { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
-        { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
-        { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
-        { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
-        { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
-        { .div = 0 },
-};
-static const struct clksel clkout2_div[] = {
-        { .parent = &sysclkout_pre_ck, .rates = div8_rates },
-        { .parent = NULL },
-};
-static struct clk clkout2_ck = {
-        .name           = "clkout2_ck",
-        .parent         = &sysclkout_pre_ck,
-        .ops            = &clkops_omap2_dflt,
-        .clksel         = clkout2_div,
-        .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
-        .clksel_mask    = AM33XX_CLKOUT2DIV_MASK,
-        .enable_reg     = AM33XX_CM_CLKOUT_CTRL,
-        .enable_bit     = AM33XX_CLKOUT2EN_SHIFT,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel wdt_clkmux_sel[] = {
-        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk wdt1_fck = {
-        .name           = "wdt1_fck",
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &clk_rc32k_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel         = wdt_clkmux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
-        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
-        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
-        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_AM33XX),
-        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
-        CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
-        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,  CK_AM33XX),
-        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
-        CLK("cpu0",     NULL,                   &dpll_mpu_ck,           CK_AM33XX),
-        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,  CK_AM33XX),
-        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck,    CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck,   CK_AM33XX),
-        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
-        CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
-        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
-        CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
-        CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
-        CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
-        CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),
-        CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
-        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
-        CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
-        CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
-        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck,    CK_AM33XX),
-        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck,    CK_AM33XX),
-        CLK("NULL",     "mmc2_fck",             &mmc2_fck,      CK_AM33XX),
-        CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
-        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
-        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
-        CLK(NULL,       "timer1_fck",           &timer1_fck,    CK_AM33XX),
-        CLK(NULL,       "timer2_fck",           &timer2_fck,    CK_AM33XX),
-        CLK(NULL,       "timer3_fck",           &timer3_fck,    CK_AM33XX),
-        CLK(NULL,       "timer4_fck",           &timer4_fck,    CK_AM33XX),
-        CLK(NULL,       "timer5_fck",           &timer5_fck,    CK_AM33XX),
-        CLK(NULL,       "timer6_fck",           &timer6_fck,    CK_AM33XX),
-        CLK(NULL,       "timer7_fck",           &timer7_fck,    CK_AM33XX),
-        CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
-        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
-        CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
-        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk,   CK_AM33XX),
-        CLK(NULL,       "l3_gclk",              &l3_gclk,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,  CK_AM33XX),
-        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk,     CK_AM33XX),
-        CLK(NULL,       "l3s_gclk",             &l3s_gclk,      CK_AM33XX),
-        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk,     CK_AM33XX),
-        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk,     CK_AM33XX),
-        CLK(NULL,       "clk_24mhz",            &clk_24mhz,     CK_AM33XX),
-        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck, CK_AM33XX),
-        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk,      CK_AM33XX),
-        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk,     CK_AM33XX),
-        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck,    CK_AM33XX),
-        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,   CK_AM33XX),
-        CLK(NULL,       "lcd_gclk",             &lcd_gclk,      CK_AM33XX),
-        CLK(NULL,       "mmc_clk",              &mmc_clk,       CK_AM33XX),
-        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck,    CK_AM33XX),
-        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck,        CK_AM33XX),
-        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
-        CLK(NULL,       "clkout2_ck",           &clkout2_ck,    CK_AM33XX),
-        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick, CK_AM33XX),
-        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck,  CK_AM33XX),
-};
-int __init am33xx_clk_init(void)
-{
-        struct omap_clk *c;
-        u32 cpu_clkflg;
-        if (soc_is_am33xx()) {
-                cpu_mask = RATE_IN_AM33XX;
-                cpu_clkflg = CK_AM33XX;
-        }
-        clk_init(&omap2_clk_functions);
-        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
-                clk_preinit(c->lk.clk);
-        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                        omap2_init_clk_clkdm(c->lk.clk);
-                }
-        }
-        recalculate_root_clocks();
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 1fc96b9ee330..4596468e50ab 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -21,11 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "clock.h"
 #include "clock34xx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 /**
@@ -39,7 +37,7 @@
 * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 * @idlest_reg and @idlest_bit.  No return value.
 */
-static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk,
                                            void __iomem **idlest_reg,
                                            u8 *idlest_bit,
                                            u8 *idlest_val)
@@ -51,21 +49,16 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
        *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
        *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }
+const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = {
-const struct clkops clkops_omap3430es2_ssi_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
-const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
+const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
        .allow_idle     = omap2_clkt_iclk_allow_idle,
        .deny_idle      = omap2_clkt_iclk_deny_idle,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
 /**
@@ -82,7 +75,7 @@ const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
 * default find_idlest code assumes that they are at the same
 * position.)  No return value.
 */
-static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk,
                                                    void __iomem **idlest_reg,
                                                    u8 *idlest_bit,
                                                    u8 *idlest_val)
@@ -96,20 +89,16 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
        *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }
-const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
-const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
+const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
        .allow_idle     = omap2_clkt_iclk_allow_idle,
        .deny_idle      = omap2_clkt_iclk_deny_idle,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
 /**
@@ -123,7 +112,7 @@ const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
 * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 * @idlest_reg and @idlest_bit.  No return value.
 */
-static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk,
                                                 void __iomem **idlest_reg,
                                                 u8 *idlest_bit,
                                                 u8 *idlest_val)
@@ -136,18 +125,14 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
        *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }
-const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = {
-        .enable         = omap2_dflt_clk_enable,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
-        .disable        = omap2_dflt_clk_disable,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
-const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
+const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
+        .find_companion = omap2_clk_dflt_find_companion,
-        .allow_idle     = omap2_clkt_iclk_allow_idle,
-        .deny_idle      = omap2_clkt_iclk_deny_idle,
 };
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index 2e97d08f0e56..4d79ae2c0241 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -21,11 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "clock.h"
 #include "clock3517.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 /*
@@ -49,7 +47,7 @@
 * in the enable register itsel at a bit offset of 4 from the enable
 * bit. A value of 1 indicates that clock is enabled.
 */
-static void am35xx_clk_find_idlest(struct clk *clk,
+static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
                                            void __iomem **idlest_reg,
                                            u8 *idlest_bit,
                                            u8 *idlest_val)
@@ -73,8 +71,9 @@ static void am35xx_clk_find_idlest(struct clk *clk,
 * associate this type of code with per-module data structures to
 * avoid this issue, and remove the casts.  No return value.
 */
-static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,
+static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
-                                            u8 *other_bit)
+                                      void __iomem **other_reg,
+                                      u8 *other_bit)
 {
        *other_reg = (__force void __iomem *)(clk->enable_reg);
        if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
@@ -82,10 +81,7 @@ static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,
        else
                *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
 }
+const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
-const struct clkops clkops_am35xx_ipss_module_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
        .find_idlest    = am35xx_clk_find_idlest,
        .find_companion = am35xx_clk_find_companion,
 };
@@ -101,7 +97,7 @@ const struct clkops clkops_am35xx_ipss_module_wait = {
 * CM_{I,F}CLKEN bit.  Pass back the correct info via @idlest_reg
 * and @idlest_bit.  No return value.
 */
-static void am35xx_clk_ipss_find_idlest(struct clk *clk,
+static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
                                            void __iomem **idlest_reg,
                                            u8 *idlest_bit,
                                            u8 *idlest_val)
@@ -114,13 +110,9 @@ static void am35xx_clk_ipss_find_idlest(struct clk *clk,
        *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }
-const struct clkops clkops_am35xx_ipss_wait = {
+const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = am35xx_clk_ipss_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
        .allow_idle     = omap2_clkt_iclk_allow_idle,
        .deny_idle      = omap2_clkt_iclk_deny_idle,
+        .find_idlest    = am35xx_clk_ipss_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
 };
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 0c5e25ed8879..8f3bf4e50908 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -22,8 +22,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "clock.h"
 #include "clock36xx.h"
@@ -39,34 +37,32 @@
 * (Any other value different from the Read value) to the
 * corresponding CM_CLKSEL register will refresh the dividers.
 */
-static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)
+int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
+        struct clk_hw_omap *parent;
+        struct clk_hw *parent_hw;
        u32 dummy_v, orig_v, clksel_shift;
        int ret;
        /* Clear PWRDN bit of HSDIVIDER */
        ret = omap2_dflt_clk_enable(clk);
+        parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
+        parent = to_clk_hw_omap(parent_hw);
        /* Restore the dividers */
        if (!ret) {
-                clksel_shift = __ffs(clk->parent->clksel_mask);
+                clksel_shift = __ffs(parent->clksel_mask);
-                orig_v = __raw_readl(clk->parent->clksel_reg);
+                orig_v = __raw_readl(parent->clksel_reg);
                dummy_v = orig_v;
                /* Write any other value different from the Read value */
                dummy_v ^= (1 << clksel_shift);
-                __raw_writel(dummy_v, clk->parent->clksel_reg);
+                __raw_writel(dummy_v, parent->clksel_reg);
                /* Write the original divider */
-                __raw_writel(orig_v, clk->parent->clksel_reg);
+                __raw_writel(orig_v, parent->clksel_reg);
        }
        return ret;
 }
-const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
-        .enable         = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
-        .disable        = omap2_dflt_clk_disable,
-        .find_companion = omap2_clk_dflt_find_companion,
-        .find_idlest    = omap2_clk_dflt_find_idlest,
-};
diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h
index a7dee5bc6364..945bb7f083e9 100644
--- a/arch/arm/mach-omap2/clock36xx.h
+++ b/arch/arm/mach-omap2/clock36xx.h
@@ -8,6 +8,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
-extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw);
 #endif
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 83bb01427d40..4eacab8f1176 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -21,8 +21,6 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
 #include "soc.h"
 #include "clock.h"
 #include "clock3xxx.h"
@@ -40,8 +38,8 @@
 /* needed by omap3_core_dpll_m2_set_rate() */
 struct clk *sdrc_ick_p, *arm_fck_p;
+int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
-int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
+                                unsigned long parent_rate)
 {
        /*
         * According to the 12-5 CDP code from TI, "Limitation 2.5"
@@ -53,7 +51,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
                return -EINVAL;
        }
-        return omap3_noncore_dpll_set_rate(clk, rate);
+        return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
 }
 void __init omap3_clk_lock_dpll5(void)
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8bbeeaf399e2..8cd4b0a882ae 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,8 +9,10 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
 int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
+int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
-int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
+                                        unsigned long parent_rate);
+int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
+                                        unsigned long parent_rate);
 void omap3_clk_lock_dpll5(void);
 extern struct clk *sdrc_ick_p;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
deleted file mode 100644
index 1f42c9d5ecf3..000000000000
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ /dev/null
@@ -1,3617 +0,0 @@
-/*
- * OMAP3 clock data
- *
- * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
- * Copyright (C) 2007-2011 Nokia Corporation
- *
- * Written by Paul Walmsley
- * With many device clock fixes by Kevin Hilman and Jouni Högander
- * DPLL bypass clock support added by Roman Tereshonkov
- *
- */
-/*
- * Virtual clocks are introduced as convenient tools.
- * They are sources for other clocks and not supposed
- * to be requested from drivers directly.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <plat/clkdev_omap.h>
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock3xxx.h"
-#include "clock34xx.h"
-#include "clock36xx.h"
-#include "clock3517.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-34xx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm-regbits-34xx.h"
-#include "control.h"
-/*
- * clocks
- */
-#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
-/* Maximum DPLL multiplier, divider values for OMAP3 */
-#define OMAP3_MAX_DPLL_MULT             2047
-#define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
-#define OMAP3_MAX_DPLL_DIV              128
-/*
- * DPLL1 supplies clock to the MPU.
- * DPLL2 supplies clock to the IVA2.
- * DPLL3 supplies CORE domain clocks.
- * DPLL4 supplies peripheral clocks.
- * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
- */
-/* Forward declarations for DPLL bypass clocks */
-static struct clk dpll1_fck;
-static struct clk dpll2_fck;
-/* PRM CLOCKS */
-/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
-static struct clk omap_32k_fck = {
-        .name           = "omap_32k_fck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-};
-static struct clk secure_32k_fck = {
-        .name           = "secure_32k_fck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-};
-/* Virtual source clocks for osc_sys_ck */
-static struct clk virt_12m_ck = {
-        .name           = "virt_12m_ck",
-        .ops            = &clkops_null,
-        .rate           = 12000000,
-};
-static struct clk virt_13m_ck = {
-        .name           = "virt_13m_ck",
-        .ops            = &clkops_null,
-        .rate           = 13000000,
-};
-static struct clk virt_16_8m_ck = {
-        .name           = "virt_16_8m_ck",
-        .ops            = &clkops_null,
-        .rate           = 16800000,
-};
-static struct clk virt_38_4m_ck = {
-        .name           = "virt_38_4m_ck",
-        .ops            = &clkops_null,
-        .rate           = 38400000,
-};
-static const struct clksel_rate osc_sys_12m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate osc_sys_13m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate osc_sys_16_8m_rates[] = {
-        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 0 }
-};
-static const struct clksel_rate osc_sys_19_2m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate osc_sys_26m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate osc_sys_38_4m_rates[] = {
-        { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel osc_sys_clksel[] = {
-        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
-        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
-        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
-        { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
-        { .parent = &virt_26000000_ck,   .rates = osc_sys_26m_rates },
-        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
-        { .parent = NULL },
-};
-/* Oscillator clock */
-/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
-static struct clk osc_sys_ck = {
-        .name           = "osc_sys_ck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_PRM_CLKSEL,
-        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
-        .clksel         = osc_sys_clksel,
-        /* REVISIT: deal with autoextclkmode? */
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate div2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel sys_clksel[] = {
-        { .parent = &osc_sys_ck, .rates = div2_rates },
-        { .parent = NULL }
-};
-/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
-/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
-static struct clk sys_ck = {
-        .name           = "sys_ck",
-        .ops            = &clkops_null,
-        .parent         = &osc_sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
-        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
-        .clksel         = sys_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk sys_altclk = {
-        .name           = "sys_altclk",
-        .ops            = &clkops_null,
-};
-/* Optional external clock input for some McBSPs */
-static struct clk mcbsp_clks = {
-        .name           = "mcbsp_clks",
-        .ops            = &clkops_null,
-};
-/* PRM EXTERNAL CLOCK OUTPUT */
-static struct clk sys_clkout1 = {
-        .name           = "sys_clkout1",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &osc_sys_ck,
-        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
-        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/* DPLLS */
-/* CM CLOCKS */
-static const struct clksel_rate div16_dpll_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
-        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
-        { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
-        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
-        { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
-        { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
-        { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
-        { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
-        { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
-        { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
-        { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
-        { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate dpll4_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
-        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
-        { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
-        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
-        { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
-        { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
-        { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
-        { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
-        { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
-        { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
-        { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
-        { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
-        { .div = 17, .val = 17, .flags = RATE_IN_36XX },
-        { .div = 18, .val = 18, .flags = RATE_IN_36XX },
-        { .div = 19, .val = 19, .flags = RATE_IN_36XX },
-        { .div = 20, .val = 20, .flags = RATE_IN_36XX },
-        { .div = 21, .val = 21, .flags = RATE_IN_36XX },
-        { .div = 22, .val = 22, .flags = RATE_IN_36XX },
-        { .div = 23, .val = 23, .flags = RATE_IN_36XX },
-        { .div = 24, .val = 24, .flags = RATE_IN_36XX },
-        { .div = 25, .val = 25, .flags = RATE_IN_36XX },
-        { .div = 26, .val = 26, .flags = RATE_IN_36XX },
-        { .div = 27, .val = 27, .flags = RATE_IN_36XX },
-        { .div = 28, .val = 28, .flags = RATE_IN_36XX },
-        { .div = 29, .val = 29, .flags = RATE_IN_36XX },
-        { .div = 30, .val = 30, .flags = RATE_IN_36XX },
-        { .div = 31, .val = 31, .flags = RATE_IN_36XX },
-        { .div = 32, .val = 32, .flags = RATE_IN_36XX },
-        { .div = 0 }
-};
-/* DPLL1 */
-/* MPU clock source */
-/* Type: DPLL */
-static struct dpll_data dpll1_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
-        .clk_bypass     = &dpll1_fck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
-        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
-        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-};
-static struct clk dpll1_ck = {
-        .name           = "dpll1_ck",
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll1_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed.
- */
-static struct clk dpll1_x2_ck = {
-        .name           = "dpll1_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_ck,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
-static const struct clksel div16_dpll1_x2m2_clksel[] = {
-        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-/*
- * Does not exist in the TRM - needed to separate the M2 divider from
- * bypass selection in mpu_ck
- */
-static struct clk dpll1_x2m2_ck = {
-        .name           = "dpll1_x2m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
-        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div16_dpll1_x2m2_clksel,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* DPLL2 */
-/* IVA2 clock source */
-/* Type: DPLL */
-static struct dpll_data dpll2_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
-        .clk_bypass     = &dpll2_fck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
-        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
-                                (1 << DPLL_LOW_POWER_BYPASS),
-        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
-        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-};
-static struct clk dpll2_ck = {
-        .name           = "dpll2_ck",
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll2_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll2_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-static const struct clksel div16_dpll2_m2x2_clksel[] = {
-        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-/*
- * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
- * or CLKOUTX2. CLKOUT seems most plausible.
- */
-static struct clk dpll2_m2_ck = {
-        .name           = "dpll2_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                          OMAP3430_CM_CLKSEL2_PLL),
-        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div16_dpll2_m2x2_clksel,
-        .clkdm_name     = "dpll2_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * DPLL3
- * Source clock for all interfaces and for some device fclks
- * REVISIT: Also supports fast relock bypass - not included below
- */
-static struct dpll_data dpll3_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
-        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
-        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-};
-static struct clk dpll3_ck = {
-        .name           = "dpll3_ck",
-        .ops            = &clkops_omap3_core_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll3_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed
- */
-static struct clk dpll3_x2_ck = {
-        .name           = "dpll3_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel_rate div31_dpll3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
-        { .div = 0 },
-};
-static const struct clksel div31_dpll3m2_clksel[] = {
-        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
-        { .parent = NULL }
-};
-/* DPLL3 output M2 - primary control point for CORE speed */
-static struct clk dpll3_m2_ck = {
-        .name           = "dpll3_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div31_dpll3m2_clksel,
-        .clkdm_name     = "dpll3_clkdm",
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap3_core_dpll_m2_set_rate,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dpll3_m2x2_ck = {
-        .name           = "dpll3_m2x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static const struct clksel div16_dpll3_clksel[] = {
-        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-/* This virtual clock is the source for dpll3_m3x2_ck */
-static struct clk dpll3_m3_ck = {
-        .name           = "dpll3_m3_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
-        .clksel         = div16_dpll3_clksel,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll3_m3x2_ck = {
-        .name           = "dpll3_m3x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll3_m3_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static struct clk emu_core_alwon_ck = {
-        .name           = "emu_core_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m3x2_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* DPLL4 */
-/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
-/* Type: DPLL */
-static struct dpll_data dpll4_dd;
-static struct dpll_data dpll4_dd_34xx __initdata = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
-        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
-        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-};
-static struct dpll_data dpll4_dd_3630 __initdata = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
-        .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
-        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
-        .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
-        .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .flags          = DPLL_J_TYPE
-};
-static struct clk dpll4_ck = {
-        .name           = "dpll4_ck",
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll4_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_dpll4_set_rate,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed --
- * XXX does this serve any downstream clocks?
- */
-static struct clk dpll4_x2_ck = {
-        .name           = "dpll4_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel dpll4_clksel[] = {
-        { .parent = &dpll4_ck, .rates = dpll4_rates },
-        { .parent = NULL }
-};
-/* This virtual clock is the source for dpll4_m2x2_ck */
-static struct clk dpll4_m2_ck = {
-        .name           = "dpll4_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
-        .clksel_mask    = OMAP3630_DIV_96M_MASK,
-        .clksel         = dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m2x2_ck = {
-        .name           = "dpll4_m2x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-/*
- * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
- * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
- * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
- * CM_96K_(F)CLK.
- */
-/* Adding 192MHz Clock node needed by SGX */
-static struct clk omap_192m_alwon_fck = {
-        .name           = "omap_192m_alwon_fck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_m2x2_ck,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_36XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_36XX },
-        { .div = 0 }
-};
-static const struct clksel omap_96m_alwon_fck_clksel[] = {
-        { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
-        { .parent = NULL }
-};
-static const struct clksel_rate omap_96m_dpll_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate omap_96m_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static struct clk omap_96m_alwon_fck = {
-        .name           = "omap_96m_alwon_fck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_m2x2_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk omap_96m_alwon_fck_3630 = {
-        .name           = "omap_96m_alwon_fck",
-        .parent         = &omap_192m_alwon_fck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
-        .clksel         = omap_96m_alwon_fck_clksel
-};
-static struct clk cm_96m_fck = {
-        .name           = "cm_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_alwon_fck,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel omap_96m_fck_clksel[] = {
-        { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
-        { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
-        { .parent = NULL }
-};
-static struct clk omap_96m_fck = {
-        .name           = "omap_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
-        .clksel         = omap_96m_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* This virtual clock is the source for dpll4_m3x2_ck */
-static struct clk dpll4_m3_ck = {
-        .name           = "dpll4_m3_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
-        .clksel         = dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m3x2_ck = {
-        .name           = "dpll4_m3x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m3_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate omap_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel omap_54m_clksel[] = {
-        { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
-        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
-        { .parent = NULL }
-};
-static struct clk omap_54m_fck = {
-        .name           = "omap_54m_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
-        .clksel         = omap_54m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate omap_48m_cm96m_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate omap_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel omap_48m_clksel[] = {
-        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
-        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
-        { .parent = NULL }
-};
-static struct clk omap_48m_fck = {
-        .name           = "omap_48m_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
-        .clksel         = omap_48m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk omap_12m_fck = {
-        .name           = "omap_12m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .fixed_div      = 4,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/* This virtual clock is the source for dpll4_m4x2_ck */
-static struct clk dpll4_m4_ck = {
-        .name           = "dpll4_m4_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
-        .clksel         = dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-};
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m4x2_ck = {
-        .name           = "dpll4_m4x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m4_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-/* This virtual clock is the source for dpll4_m5x2_ck */
-static struct clk dpll4_m5_ck = {
-        .name           = "dpll4_m5_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
-        .clksel         = dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m5x2_ck = {
-        .name           = "dpll4_m5x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m5_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-/* This virtual clock is the source for dpll4_m6x2_ck */
-static struct clk dpll4_m6_ck = {
-        .name           = "dpll4_m6_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
-        .clksel         = dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m6x2_ck = {
-        .name           = "dpll4_m6x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m6_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static struct clk emu_per_alwon_ck = {
-        .name           = "emu_per_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_m6x2_ck,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* DPLL5 */
-/* Supplies 120MHz clock, USIM source clock */
-/* Type: DPLL */
-/* 3430ES2 only */
-static struct dpll_data dpll5_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
-        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
-        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
-        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
-        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-};
-static struct clk dpll5_ck = {
-        .name           = "dpll5_ck",
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll5_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll5_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-static const struct clksel div16_dpll5_clksel[] = {
-        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-static struct clk dpll5_m2_ck = {
-        .name           = "dpll5_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll5_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
-        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
-        .clksel         = div16_dpll5_clksel,
-        .clkdm_name     = "dpll5_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* CM EXTERNAL CLOCK OUTPUTS */
-static const struct clksel_rate clkout2_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate clkout2_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate clkout2_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate clkout2_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel clkout2_src_clksel[] = {
-        { .parent = &core_ck,           .rates = clkout2_src_core_rates },
-        { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
-        { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
-        { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
-        { .parent = NULL }
-};
-static struct clk clkout2_src_ck = {
-        .name           = "clkout2_src_ck",
-        .ops            = &clkops_omap2_dflt,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
-        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
-        .clksel         = clkout2_src_clksel,
-        .clkdm_name     = "core_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate sys_clkout2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel sys_clkout2_clksel[] = {
-        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
-        { .parent = NULL },
-};
-static struct clk sys_clkout2 = {
-        .name           = "sys_clkout2",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
-        .clksel         = sys_clkout2_clksel,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate
-};
-/* CM OUTPUT CLOCKS */
-static struct clk corex2_fck = {
-        .name           = "corex2_fck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2x2_ck,
-        .recalc         = &followparent_recalc,
-};
-/* DPLL power domain clock controls */
-static const struct clksel_rate div4_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel div4_core_clksel[] = {
-        { .parent = &core_ck, .rates = div4_rates },
-        { .parent = NULL }
-};
-/*
- * REVISIT: Are these in DPLL power domain or CM power domain? docs
- * may be inconsistent here?
- */
-static struct clk dpll1_fck = {
-        .name           = "dpll1_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
-        .clksel         = div4_core_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mpu_ck = {
-        .name           = "mpu_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_x2m2_ck,
-        .clkdm_name     = "mpu_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
-static const struct clksel_rate arm_fck_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel arm_fck_clksel[] = {
-        { .parent = &mpu_ck, .rates = arm_fck_rates },
-        { .parent = NULL }
-};
-static struct clk arm_fck = {
-        .name           = "arm_fck",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
-        .clksel         = arm_fck_clksel,
-        .clkdm_name     = "mpu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* XXX What about neon_clkdm ? */
-/*
- * REVISIT: This clock is never specifically defined in the 3430 TRM,
- * although it is referenced - so this is a guess
- */
-static struct clk emu_mpu_alwon_ck = {
-        .name           = "emu_mpu_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dpll2_fck = {
-        .name           = "dpll2_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
-        .clksel         = div4_core_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk iva2_ck = {
-        .name           = "iva2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll2_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
-        .clkdm_name     = "iva2_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* Common interface clocks */
-static const struct clksel div2_core_clksel[] = {
-        { .parent = &core_ck, .rates = div2_rates },
-        { .parent = NULL }
-};
-static struct clk l3_ick = {
-        .name           = "l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
-        .clksel         = div2_core_clksel,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel div2_l3_clksel[] = {
-        { .parent = &l3_ick, .rates = div2_rates },
-        { .parent = NULL }
-};
-static struct clk l4_ick = {
-        .name           = "l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
-        .clksel         = div2_l3_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel div2_l4_clksel[] = {
-        { .parent = &l4_ick, .rates = div2_rates },
-        { .parent = NULL }
-};
-static struct clk rm_ick = {
-        .name           = "rm_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
-        .clksel         = div2_l4_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* GFX power domain */
-/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
-static const struct clksel gfx_l3_clksel[] = {
-        { .parent = &l3_ick, .rates = gfx_l3_rates },
-        { .parent = NULL }
-};
-/*
- * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
- * This interface clock does not have a CM_AUTOIDLE bit
- */
-static struct clk gfx_l3_ck = {
-        .name           = "gfx_l3_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP_EN_GFX_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gfx_l3_fck = {
-        .name           = "gfx_l3_fck",
-        .ops            = &clkops_null,
-        .parent         = &gfx_l3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
-        .clksel         = gfx_l3_clksel,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gfx_l3_ick = {
-        .name           = "gfx_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &gfx_l3_ck,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gfx_cg1_ck = {
-        .name           = "gfx_cg1_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gfx_cg2_ck = {
-        .name           = "gfx_cg2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* SGX power domain - 3430ES2 only */
-static const struct clksel_rate sgx_core_rates[] = {
-        { .div = 2, .val = 5, .flags = RATE_IN_36XX },
-        { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel_rate sgx_192m_rates[] = {
-        { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
-        { .div = 0 },
-};
-static const struct clksel_rate sgx_corex2_rates[] = {
-        { .div = 3, .val = 6, .flags = RATE_IN_36XX },
-        { .div = 5, .val = 7, .flags = RATE_IN_36XX },
-        { .div = 0 },
-};
-static const struct clksel_rate sgx_96m_rates[] = {
-        { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel sgx_clksel[] = {
-        { .parent = &core_ck,    .rates = sgx_core_rates },
-        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
-        { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
-        { .parent = &corex2_fck, .rates = sgx_corex2_rates },
-        { .parent = NULL }
-};
-static struct clk sgx_fck = {
-        .name           = "sgx_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
-        .clksel         = sgx_clksel,
-        .clkdm_name     = "sgx_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate
-};
-/* This interface clock does not have a CM_AUTOIDLE bit */
-static struct clk sgx_ick = {
-        .name           = "sgx_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
-        .clkdm_name     = "sgx_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* CORE power domain */
-static struct clk d2d_26m_fck = {
-        .name           = "d2d_26m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk modem_fck = {
-        .name           = "modem_fck",
-        .ops            = &clkops_omap2_mdmclk_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk sad2d_ick = {
-        .name           = "sad2d_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mad2d_ick = {
-        .name           = "mad2d_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel omap343x_gpt_clksel[] = {
-        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
-        { .parent = &sys_ck,       .rates = gpt_sys_rates },
-        { .parent = NULL}
-};
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk cpefuse_fck = {
-        .name           = "cpefuse_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk ts_fck = {
-        .name           = "ts_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_32k_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usbtll_fck = {
-        .name           = "usbtll_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll5_m2_ck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/* CORE 96M FCLK-derived clocks */
-static struct clk core_96m_fck = {
-        .name           = "core_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs3_fck = {
-        .name           = "mmchs3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs2_fck = {
-        .name           = "mmchs2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs1_fck = {
-        .name           = "mmchs1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c3_fck = {
-        .name           = "i2c3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c2_fck = {
-        .name           = "i2c2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c1_fck = {
-        .name           = "i2c1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/*
- * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
- * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
- */
-static const struct clksel_rate common_mcbsp_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel mcbsp_15_clksel[] = {
-        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
-        .clksel         = mcbsp_15_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
-        .clksel         = mcbsp_15_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* CORE_48M_FCK-derived clocks */
-static struct clk core_48m_fck = {
-        .name           = "core_48m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi4_fck = {
-        .name           = "mcspi4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .recalc         = &followparent_recalc,
-        .clkdm_name     = "core_l4_clkdm",
-};
-static struct clk mcspi3_fck = {
-        .name           = "mcspi3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .recalc         = &followparent_recalc,
-        .clkdm_name     = "core_l4_clkdm",
-};
-static struct clk mcspi2_fck = {
-        .name           = "mcspi2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .recalc         = &followparent_recalc,
-        .clkdm_name     = "core_l4_clkdm",
-};
-static struct clk mcspi1_fck = {
-        .name           = "mcspi1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .recalc         = &followparent_recalc,
-        .clkdm_name     = "core_l4_clkdm",
-};
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk fshostusb_fck = {
-        .name           = "fshostusb_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/* CORE_12M_FCK based clocks */
-static struct clk core_12m_fck = {
-        .name           = "core_12m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_12m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_12m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/* DPLL3-derived clock */
-static const struct clksel_rate ssi_ssr_corex2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
-        { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
-        { .div = 0 }
-};
-static const struct clksel ssi_ssr_clksel[] = {
-        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
-        { .parent = NULL }
-};
-static struct clk ssi_ssr_fck_3430es1 = {
-        .name           = "ssi_ssr_fck",
-        .ops            = &clkops_omap2_dflt,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk ssi_ssr_fck_3430es2 = {
-        .name           = "ssi_ssr_fck",
-        .ops            = &clkops_omap3430es2_ssi_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk ssi_sst_fck_3430es1 = {
-        .name           = "ssi_sst_fck",
-        .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck_3430es1,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk ssi_sst_fck_3430es2 = {
-        .name           = "ssi_sst_fck",
-        .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck_3430es2,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/* CORE_L3_ICK based clocks */
-/*
- * XXX must add clk_enable/clk_disable for these if standard code won't
- * handle it
- */
-static struct clk core_l3_ick = {
-        .name           = "core_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk hsotgusb_ick_3430es1 = {
-        .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk hsotgusb_ick_3430es2 = {
-        .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* This interface clock does not have a CM_AUTOIDLE bit */
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpmc_fck = {
-        .name           = "gpmc_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_l3_ick,
-        .flags          = ENABLE_ON_INIT, /* huh? */
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* SECURITY_L3_ICK based clocks */
-static struct clk security_l3_ick = {
-        .name           = "security_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .recalc         = &followparent_recalc,
-};
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &security_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/* CORE_L4_ICK based clocks */
-static struct clk core_l4_ick = {
-        .name           = "core_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk usbtll_ick = {
-        .name           = "usbtll_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs3_ick = {
-        .name           = "mmchs3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* Intersystem Communication Registers - chassis mode only */
-static struct clk icr_ick = {
-        .name           = "icr_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk aes2_ick = {
-        .name           = "aes2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk sha12_ick = {
-        .name           = "sha12_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk des2_ick = {
-        .name           = "des2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs2_ick = {
-        .name           = "mmchs2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmchs1_ick = {
-        .name           = "mmchs1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi4_ick = {
-        .name           = "mcspi4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi3_ick = {
-        .name           = "mcspi3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi2_ick = {
-        .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi1_ick = {
-        .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c3_ick = {
-        .name           = "i2c3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c2_ick = {
-        .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c1_ick = {
-        .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* SSI_L4_ICK based clocks */
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk ssi_ick_3430es1 = {
-        .name           = "ssi_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &ssi_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk ssi_ick_3430es2 = {
-        .name           = "ssi_ick",
-        .ops            = &clkops_omap3430es2_iclk_ssi_wait,
-        .parent         = &ssi_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
- * but l4_ick makes more sense to me */
-static const struct clksel usb_l4_clksel[] = {
-        { .parent = &l4_ick, .rates = div2_rates },
-        { .parent = NULL },
-};
-static struct clk usb_l4_ick = {
-        .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &l4_ick,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
-        .clksel         = usb_l4_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* SECURITY_L4_ICK2 based clocks */
-static struct clk security_l4_ick2 = {
-        .name           = "security_l4_ick2",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .recalc         = &followparent_recalc,
-};
-static struct clk aes1_ick = {
-        .name           = "aes1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sha11_ick = {
-        .name           = "sha11_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk des1_ick = {
-        .name           = "des1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/* DSS */
-static struct clk dss1_alwon_fck_3430es1 = {
-        .name           = "dss1_alwon_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll4_m4x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss1_alwon_fck_3430es2 = {
-        .name           = "dss1_alwon_fck",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &dpll4_m4x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_tv_fck = {
-        .name           = "dss_tv_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_54m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_96m_fck = {
-        .name           = "dss_96m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss2_alwon_fck = {
-        .name           = "dss2_alwon_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_ick_3430es1 = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_ick_3430es2 = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* CAM */
-static struct clk cam_mclk = {
-        .name           = "cam_mclk",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll4_m5x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk cam_ick = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "cam_ick",
-        .ops            = &clkops_omap2_iclk_dflt,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk csi2_96m_fck = {
-        .name           = "csi2_96m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* USBHOST - 3430ES2 only */
-static struct clk usbhost_120m_fck = {
-        .name           = "usbhost_120m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll5_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk usbhost_48m_fck = {
-        .name           = "usbhost_48m_fck",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &omap_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk usbhost_ick = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "usbhost_ick",
-        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* WKUP */
-static const struct clksel_rate usim_96m_rates[] = {
-        { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
-        { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel_rate usim_120m_rates[] = {
-        { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
-        { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
-        { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
-        { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel usim_clksel[] = {
-        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
-        { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
-        { .parent = &sys_ck,            .rates = div2_rates },
-        { .parent = NULL },
-};
-/* 3430ES2 only */
-static struct clk usim_fck = {
-        .name           = "usim_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
-        .clksel         = usim_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk wkup_32k_fck = {
-        .name           = "wkup_32k_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_32k_fck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio1_dbck = {
-        .name           = "gpio1_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &wkup_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt2_fck = {
-        .name           = "wdt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk wkup_l4_ick = {
-        .name           = "wkup_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* 3430ES2 only */
-/* Never specifically named in the TRM, so we have to infer a likely name */
-static struct clk usim_ick = {
-        .name           = "usim_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt2_ick = {
-        .name           = "wdt2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio1_ick = {
-        .name           = "gpio1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk omap_32ksync_ick = {
-        .name           = "omap_32ksync_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* XXX This clock no longer exists in 3430 TRM rev F */
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* PER clock domain */
-static struct clk per_96m_fck = {
-        .name           = "per_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_alwon_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk per_48m_fck = {
-        .name           = "per_48m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart4_fck = {
-        .name           = "uart4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart4_fck_am35xx = {
-        .name           = "uart4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = AM35XX_EN_UART4_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk per_32k_alwon_fck = {
-        .name           = "per_32k_alwon_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_32k_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio6_dbck = {
-        .name           = "gpio6_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio5_dbck = {
-        .name           = "gpio5_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio4_dbck = {
-        .name           = "gpio4_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio3_dbck = {
-        .name           = "gpio3_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio2_dbck = {
-        .name           = "gpio2_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk per_l4_ick = {
-        .name           = "per_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio6_ick = {
-        .name           = "gpio6_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio4_ick = {
-        .name           = "gpio4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio3_ick = {
-        .name           = "gpio3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio2_ick = {
-        .name           = "gpio2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt3_ick = {
-        .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart4_ick = {
-        .name           = "uart4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel mcbsp_234_clksel[] = {
-        { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* EMU clocks */
-/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
-static const struct clksel_rate emu_src_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel_rate emu_src_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel_rate emu_src_per_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel_rate emu_src_mpu_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel emu_src_clksel[] = {
-        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
-        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
-        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
-        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
-        { .parent = NULL },
-};
-/*
- * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
- * to switch the source of some of the EMU clocks.
- * XXX Are there CLKEN bits for these EMU clks?
- */
-static struct clk emu_src_ck = {
-        .name           = "emu_src_ck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
-        .clksel         = emu_src_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate pclk_emu_rates[] = {
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel pclk_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
-        { .parent = NULL },
-};
-static struct clk pclk_fck = {
-        .name           = "pclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
-        .clksel         = pclk_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate pclkx2_emu_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel pclkx2_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
-        { .parent = NULL },
-};
-static struct clk pclkx2_fck = {
-        .name           = "pclkx2_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
-        .clksel         = pclkx2_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel atclk_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = div2_rates },
-        { .parent = NULL },
-};
-static struct clk atclk_fck = {
-        .name           = "atclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
-        .clksel         = atclk_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk traceclk_src_fck = {
-        .name           = "traceclk_src_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
-        .clksel         = emu_src_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate traceclk_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
-        { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
-        { .div = 0 },
-};
-static const struct clksel traceclk_clksel[] = {
-        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
-        { .parent = NULL },
-};
-static struct clk traceclk_fck = {
-        .name           = "traceclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
-        .clksel         = traceclk_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-/* SR clocks */
-/* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
-        .name           = "sr1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
-        .name           = "sr2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk sr_l4_ick = {
-        .name           = "sr_l4_ick",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* SECURE_32K_FCK clocks */
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .ops            = &clkops_null,
-        .parent         = &secure_32k_fck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk wdt1_fck = {
-        .name           = "wdt1_fck",
-        .ops            = &clkops_null,
-        .parent         = &secure_32k_fck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-/* Clocks for AM35XX */
-static struct clk ipss_ick = {
-        .name           = "ipss_ick",
-        .ops            = &clkops_am35xx_ipss_wait,
-        .parent         = &core_l3_ick,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = AM35XX_EN_IPSS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk emac_ick = {
-        .name           = "emac_ick",
-        .ops            = &clkops_am35xx_ipss_module_wait,
-        .parent         = &ipss_ick,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
-        .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk rmii_ck = {
-        .name           = "rmii_ck",
-        .ops            = &clkops_null,
-        .rate           = 50000000,
-};
-static struct clk emac_fck = {
-        .name           = "emac_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &rmii_ck,
-        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
-        .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk hsotgusb_ick_am35xx = {
-        .name           = "hsotgusb_ick",
-        .ops            = &clkops_am35xx_ipss_module_wait,
-        .parent         = &ipss_ick,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
-        .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk hsotgusb_fck_am35xx = {
-        .name           = "hsotgusb_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
-        .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk hecc_ck = {
-        .name           = "hecc_ck",
-        .ops            = &clkops_am35xx_ipss_module_wait,
-        .parent         = &sys_ck,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
-        .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk vpfe_ick = {
-        .name           = "vpfe_ick",
-        .ops            = &clkops_am35xx_ipss_module_wait,
-        .parent         = &ipss_ick,
-        .clkdm_name     = "core_l3_clkdm",
-        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
-        .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-static struct clk pclk_ck = {
-        .name           = "pclk_ck",
-        .ops            = &clkops_null,
-        .rate           = 27000000,
-};
-static struct clk vpfe_fck = {
-        .name           = "vpfe_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &pclk_ck,
-        .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
-        .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-/*
- * The UART1/2 functional clock acts as the functional clock for
- * UART4. No separate fclk control available.  XXX Well now we have a
- * uart4_fck that is apparently used as the UART4 functional clock,
- * but it also seems that uart1_fck or uart2_fck are still needed, at
- * least for UART4 softresets to complete.  This really needs
- * clarification.
- */
-static struct clk uart4_ick_am35xx = {
-        .name           = "uart4_ick",
-        .ops            = &clkops_omap2_iclk_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = AM35XX_EN_UART4_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .ops            = &clkops_null,
-};
-/*
- * clkdev
- */
-static struct omap_clk omap3xxx_clks[] = {
-        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
-        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
-        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
-        CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
-        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_3XXX),
-        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
-        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
-        CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
-        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
-        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
-        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
-        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
-        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
-        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
-        CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
-        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
-        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
-        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
-        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
-        CLK(NULL,       "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
-        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
-        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
-        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
-        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
-        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
-        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
-        CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
-        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
-        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
-        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
-        CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
-        CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
-        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
-        CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
-        CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
-        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
-        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
-        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
-        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
-        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
-        CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
-        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
-        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
-        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
-        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
-        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
-        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
-        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
-        CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
-        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
-        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
-        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
-        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
-        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
-        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
-        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
-        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
-        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
-        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
-        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
-        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
-        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
-        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
-        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
-        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
-        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
-        CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
-        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
-        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
-        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
-        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
-        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
-        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
-        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
-        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
-        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
-        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
-        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
-        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
-        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
-        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
-        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
-        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
-        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
-        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
-        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
-        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
-        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
-        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
-        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
-        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
-        CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
-        CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
-        CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
-        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
-        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
-        CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
-        CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
-        CLK(NULL,       "vpfe_ick",     &emac_ick,      CK_AM35XX),
-        CLK(NULL,       "vpfe_fck",     &emac_fck,      CK_AM35XX),
-        CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
-        CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
-        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
-        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
-        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
-        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
-        CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
-        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
-};
-int __init omap3xxx_clk_init(void)
-{
-        struct omap_clk *c;
-        u32 cpu_clkflg = 0;
-        if (soc_is_am35xx()) {
-                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_AM35XX;
-        } else if (cpu_is_omap3630()) {
-                cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
-                cpu_clkflg = CK_36XX;
-        } else if (cpu_is_ti816x()) {
-                cpu_mask = RATE_IN_TI816X;
-                cpu_clkflg = CK_TI816X;
-        } else if (soc_is_am33xx()) {
-                cpu_mask = RATE_IN_AM33XX;
-        } else if (cpu_is_ti814x()) {
-                cpu_mask = RATE_IN_TI814X;
-        } else if (cpu_is_omap34xx()) {
-                if (omap_rev() == OMAP3430_REV_ES1_0) {
-                        cpu_mask = RATE_IN_3430ES1;
-                        cpu_clkflg = CK_3430ES1;
-                } else {
-                        /*
-                         * Assume that anything that we haven't matched yet
-                         * has 3430ES2-type clocks.
-                         */
-                        cpu_mask = RATE_IN_3430ES2PLUS;
-                        cpu_clkflg = CK_3430ES2PLUS;
-                }
-        } else {
-                WARN(1, "clock: could not identify OMAP3 variant\n");
-        }
-        if (omap3_has_192mhz_clk())
-                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
-        if (cpu_is_omap3630()) {
-                /*
-                 * XXX This type of dynamic rewriting of the clock tree is
-                 * deprecated and should be revised soon.
-                 *
-                 * For 3630: override clkops_omap2_dflt_wait for the
-                 * clocks affected from PWRDN reset Limitation
-                 */
-                dpll3_m3x2_ck.ops =
-                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
-                dpll4_m2x2_ck.ops =
-                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
-                dpll4_m3x2_ck.ops =
-                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
-                dpll4_m4x2_ck.ops =
-                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
-                dpll4_m5x2_ck.ops =
-                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
-                dpll4_m6x2_ck.ops =
-                                &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
-        }
-        /*
-         * XXX This type of dynamic rewriting of the clock tree is
-         * deprecated and should be revised soon.
-         */
-        if (cpu_is_omap3630())
-                dpll4_dd = dpll4_dd_3630;
-        else
-                dpll4_dd = dpll4_dd_34xx;
-        clk_init(&omap2_clk_functions);
-        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
-             c++)
-                clk_preinit(c->lk.clk);
-        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
-             c++)
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                        omap2_init_clk_clkdm(c->lk.clk);
-                }
-        /* Disable autoidle on all clocks; let the PM code enable it later */
-        omap_clk_disable_autoidle_all();
-        recalculate_root_clocks();
-        pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
-                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
-                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-        /*
-         * Lock DPLL5 -- here only until other device init code can
-         * handle this
-         */
-        if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
-                omap3_clk_lock_dpll5();
-        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
-        sdrc_ick_p = clk_get(NULL, "sdrc_ick");
-        arm_fck_p = clk_get(NULL, "arm_fck");
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
deleted file mode 100644
index 6efc30c961a5..000000000000
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ /dev/null
@@ -1,3402 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- */
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <plat/clkdev_omap.h>
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL                      0
-#define OMAP4430_MODULEMODE_SWCTRL                      1
-/* Root clocks */
-static struct clk extalt_clkin_ck = {
-        .name           = "extalt_clkin_ck",
-        .rate           = 59000000,
-        .ops            = &clkops_null,
-};
-static struct clk pad_clks_ck = {
-        .name           = "pad_clks_ck",
-        .rate           = 12000000,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
-};
-static struct clk pad_slimbus_core_clks_ck = {
-        .name           = "pad_slimbus_core_clks_ck",
-        .rate           = 12000000,
-        .ops            = &clkops_null,
-};
-static struct clk secure_32k_clk_src_ck = {
-        .name           = "secure_32k_clk_src_ck",
-        .rate           = 32768,
-        .ops            = &clkops_null,
-};
-static struct clk slimbus_clk = {
-        .name           = "slimbus_clk",
-        .rate           = 12000000,
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-};
-static struct clk sys_32k_ck = {
-        .name           = "sys_32k_ck",
-        .clkdm_name     = "prm_clkdm",
-        .rate           = 32768,
-        .ops            = &clkops_null,
-};
-static struct clk virt_12000000_ck = {
-        .name           = "virt_12000000_ck",
-        .ops            = &clkops_null,
-        .rate           = 12000000,
-};
-static struct clk virt_13000000_ck = {
-        .name           = "virt_13000000_ck",
-        .ops            = &clkops_null,
-        .rate           = 13000000,
-};
-static struct clk virt_16800000_ck = {
-        .name           = "virt_16800000_ck",
-        .ops            = &clkops_null,
-        .rate           = 16800000,
-};
-static struct clk virt_27000000_ck = {
-        .name           = "virt_27000000_ck",
-        .ops            = &clkops_null,
-        .rate           = 27000000,
-};
-static struct clk virt_38400000_ck = {
-        .name           = "virt_38400000_ck",
-        .ops            = &clkops_null,
-        .rate           = 38400000,
-};
-static const struct clksel_rate div_1_5_rates[] = {
-        { .div = 1, .val = 5, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel_rate div_1_6_rates[] = {
-        { .div = 1, .val = 6, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel_rate div_1_7_rates[] = {
-        { .div = 1, .val = 7, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel sys_clkin_sel[] = {
-        { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
-        { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
-        { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
-        { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
-        { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
-        { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
-        { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
-        { .parent = NULL },
-};
-static struct clk sys_clkin_ck = {
-        .name           = "sys_clkin_ck",
-        .rate           = 38400000,
-        .clksel         = sys_clkin_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
-        .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk tie_low_clock_ck = {
-        .name           = "tie_low_clock_ck",
-        .rate           = 0,
-        .ops            = &clkops_null,
-};
-static struct clk utmi_phy_clkout_ck = {
-        .name           = "utmi_phy_clkout_ck",
-        .rate           = 60000000,
-        .ops            = &clkops_null,
-};
-static struct clk xclk60mhsp1_ck = {
-        .name           = "xclk60mhsp1_ck",
-        .rate           = 60000000,
-        .ops            = &clkops_null,
-};
-static struct clk xclk60mhsp2_ck = {
-        .name           = "xclk60mhsp2_ck",
-        .rate           = 60000000,
-        .ops            = &clkops_null,
-};
-static struct clk xclk60motg_ck = {
-        .name           = "xclk60motg_ck",
-        .rate           = 60000000,
-        .ops            = &clkops_null,
-};
-/* Module clocks and DPLL outputs */
-static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk abe_dpll_bypass_clk_mux_ck = {
-        .name           = "abe_dpll_bypass_clk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk abe_dpll_refclk_mux_ck = {
-        .name           = "abe_dpll_refclk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
-        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
-        .clk_ref        = &abe_dpll_refclk_mux_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-static struct clk dpll_abe_ck = {
-        .name           = "dpll_abe_ck",
-        .parent         = &abe_dpll_refclk_mux_ck,
-        .dpll_data      = &dpll_abe_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap4_dpll_regm4xen_recalc,
-        .round_rate     = &omap4_dpll_regm4xen_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-static struct clk dpll_abe_x2_ck = {
-        .name           = "dpll_abe_x2_ck",
-        .parent         = &dpll_abe_ck,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
-        .flags          = CLOCK_CLKOUTX2,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel dpll_abe_m2x2_div[] = {
-        { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_abe_m2x2_ck = {
-        .name           = "dpll_abe_m2x2_ck",
-        .parent         = &dpll_abe_x2_ck,
-        .clksel         = dpll_abe_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk abe_24m_fclk = {
-        .name           = "abe_24m_fclk",
-        .parent         = &dpll_abe_m2x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 8,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel_rate div3_1to4_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel abe_clk_div[] = {
-        { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-static struct clk abe_clk = {
-        .name           = "abe_clk",
-        .parent         = &dpll_abe_m2x2_ck,
-        .clksel         = abe_clk_div,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
-        .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel_rate div2_1to2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel aess_fclk_div[] = {
-        { .parent = &abe_clk, .rates = div2_1to2_rates },
-        { .parent = NULL },
-};
-static struct clk aess_fclk = {
-        .name           = "aess_fclk",
-        .parent         = &abe_clk,
-        .clksel         = aess_fclk_div,
-        .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_abe_m3x2_ck = {
-        .name           = "dpll_abe_m3x2_ck",
-        .parent         = &dpll_abe_x2_ck,
-        .clksel         = dpll_abe_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel core_hsd_byp_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk core_hsd_byp_clk_mux_ck = {
-        .name           = "core_hsd_byp_clk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = core_hsd_byp_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
-        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
-        .clk_bypass     = &core_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-static struct clk dpll_core_ck = {
-        .name           = "dpll_core_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_core_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_core_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-};
-static struct clk dpll_core_x2_ck = {
-        .name           = "dpll_core_x2_ck",
-        .parent         = &dpll_core_ck,
-        .flags          = CLOCK_CLKOUTX2,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel dpll_core_m6x2_div[] = {
-        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_core_m6x2_ck = {
-        .name           = "dpll_core_m6x2_ck",
-        .parent         = &dpll_core_x2_ck,
-        .clksel         = dpll_core_m6x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel dbgclk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk dbgclk_mux_ck = {
-        .name           = "dbgclk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel dpll_core_m2_div[] = {
-        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_core_m2_ck = {
-        .name           = "dpll_core_m2_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk ddrphy_ck = {
-        .name           = "ddrphy_ck",
-        .parent         = &dpll_core_m2_ck,
-        .ops            = &clkops_null,
-        .clkdm_name     = "l3_emif_clkdm",
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk dpll_core_m5x2_ck = {
-        .name           = "dpll_core_m5x2_ck",
-        .parent         = &dpll_core_x2_ck,
-        .clksel         = dpll_core_m6x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel div_core_div[] = {
-        { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
-        { .parent = NULL },
-};
-static struct clk div_core_ck = {
-        .name           = "div_core_ck",
-        .parent         = &dpll_core_m5x2_ck,
-        .clksel         = div_core_div,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
-        .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel_rate div4_1to8_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 3, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel div_iva_hs_clk_div[] = {
-        { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
-        { .parent = NULL },
-};
-static struct clk div_iva_hs_clk = {
-        .name           = "div_iva_hs_clk",
-        .parent         = &dpll_core_m5x2_ck,
-        .clksel         = div_iva_hs_clk_div,
-        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
-        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk div_mpu_hs_clk = {
-        .name           = "div_mpu_hs_clk",
-        .parent         = &dpll_core_m5x2_ck,
-        .clksel         = div_iva_hs_clk_div,
-        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
-        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_core_m4x2_ck = {
-        .name           = "dpll_core_m4x2_ck",
-        .parent         = &dpll_core_x2_ck,
-        .clksel         = dpll_core_m6x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dll_clk_div_ck = {
-        .name           = "dll_clk_div_ck",
-        .parent         = &dpll_core_m4x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel dpll_abe_m2_div[] = {
-        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_abe_m2_ck = {
-        .name           = "dpll_abe_m2_ck",
-        .parent         = &dpll_abe_ck,
-        .clksel         = dpll_abe_m2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_core_m3x2_ck = {
-        .name           = "dpll_core_m3x2_ck",
-        .parent         = &dpll_core_x2_ck,
-        .clksel         = dpll_core_m6x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
-        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
-};
-static struct clk dpll_core_m7x2_ck = {
-        .name           = "dpll_core_m7x2_ck",
-        .parent         = &dpll_core_x2_ck,
-        .clksel         = dpll_core_m6x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk iva_hsd_byp_clk_mux_ck = {
-        .name           = "iva_hsd_byp_clk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = iva_hsd_byp_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
-        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
-        .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-static struct clk dpll_iva_ck = {
-        .name           = "dpll_iva_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_iva_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-static struct clk dpll_iva_x2_ck = {
-        .name           = "dpll_iva_x2_ck",
-        .parent         = &dpll_iva_ck,
-        .flags          = CLOCK_CLKOUTX2,
-        .ops            = &clkops_null,
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel dpll_iva_m4x2_div[] = {
-        { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_iva_m4x2_ck = {
-        .name           = "dpll_iva_m4x2_ck",
-        .parent         = &dpll_iva_x2_ck,
-        .clksel         = dpll_iva_m4x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_iva_m5x2_ck = {
-        .name           = "dpll_iva_m5x2_ck",
-        .parent         = &dpll_iva_x2_ck,
-        .clksel         = dpll_iva_m4x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
-        .clk_bypass     = &div_mpu_hs_clk,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-static struct clk dpll_mpu_ck = {
-        .name           = "dpll_mpu_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_mpu_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-static const struct clksel dpll_mpu_m2_div[] = {
-        { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_mpu_m2_ck = {
-        .name           = "dpll_mpu_m2_ck",
-        .parent         = &dpll_mpu_ck,
-        .clkdm_name     = "cm_clkdm",
-        .clksel         = dpll_mpu_m2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk per_hs_clk_div_ck = {
-        .name           = "per_hs_clk_div_ck",
-        .parent         = &dpll_abe_m3x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel per_hsd_byp_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk per_hsd_byp_clk_mux_ck = {
-        .name           = "per_hsd_byp_clk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = per_hsd_byp_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
-        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
-        .clk_bypass     = &per_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-static struct clk dpll_per_ck = {
-        .name           = "dpll_per_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_per_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-static const struct clksel dpll_per_m2_div[] = {
-        { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_per_m2_ck = {
-        .name           = "dpll_per_m2_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_per_x2_ck = {
-        .name           = "dpll_per_x2_ck",
-        .parent         = &dpll_per_ck,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
-        .flags          = CLOCK_CLKOUTX2,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-static const struct clksel dpll_per_m2x2_div[] = {
-        { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_per_m2x2_ck = {
-        .name           = "dpll_per_m2x2_ck",
-        .parent         = &dpll_per_x2_ck,
-        .clksel         = dpll_per_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_per_m3x2_ck = {
-        .name           = "dpll_per_m3x2_ck",
-        .parent         = &dpll_per_x2_ck,
-        .clksel         = dpll_per_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
-        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
-};
-static struct clk dpll_per_m4x2_ck = {
-        .name           = "dpll_per_m4x2_ck",
-        .parent         = &dpll_per_x2_ck,
-        .clksel         = dpll_per_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_per_m5x2_ck = {
-        .name           = "dpll_per_m5x2_ck",
-        .parent         = &dpll_per_x2_ck,
-        .clksel         = dpll_per_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_per_m6x2_ck = {
-        .name           = "dpll_per_m6x2_ck",
-        .parent         = &dpll_per_x2_ck,
-        .clksel         = dpll_per_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk dpll_per_m7x2_ck = {
-        .name           = "dpll_per_m7x2_ck",
-        .parent         = &dpll_per_x2_ck,
-        .clksel         = dpll_per_m2x2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
-        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk usb_hs_clk_div_ck = {
-        .name           = "usb_hs_clk_div_ck",
-        .parent         = &dpll_abe_m3x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 3,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
-        .clk_bypass     = &usb_hs_clk_div_ck,
-        .flags          = DPLL_J_TYPE,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
-        .mult_mask      = OMAP4430_DPLL_MULT_USB_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_0_7_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
-        .max_multiplier = 4095,
-        .max_divider    = 256,
-        .min_divider    = 1,
-};
-static struct clk dpll_usb_ck = {
-        .name           = "dpll_usb_ck",
-        .parent         = &sys_clkin_ck,
-        .dpll_data      = &dpll_usb_dd,
-        .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_omap3_noncore_dpll_ops,
-        .recalc         = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "l3_init_clkdm",
-};
-static struct clk dpll_usb_clkdcoldo_ck = {
-        .name           = "dpll_usb_clkdcoldo_ck",
-        .parent         = &dpll_usb_ck,
-        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel dpll_usb_m2_div[] = {
-        { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-static struct clk dpll_usb_m2_ck = {
-        .name           = "dpll_usb_m2_ck",
-        .parent         = &dpll_usb_ck,
-        .clksel         = dpll_usb_m2_div,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
-        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
-        .ops            = &clkops_omap4_dpllmx_ops,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel ducati_clk_mux_sel[] = {
-        { .parent = &div_core_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk ducati_clk_mux_ck = {
-        .name           = "ducati_clk_mux_ck",
-        .parent         = &div_core_ck,
-        .clksel         = ducati_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk func_12m_fclk = {
-        .name           = "func_12m_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 16,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk func_24m_clk = {
-        .name           = "func_24m_clk",
-        .parent         = &dpll_per_m2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 4,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk func_24mc_fclk = {
-        .name           = "func_24mc_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 8,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel_rate div2_4to8_rates[] = {
-        { .div = 4, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel func_48m_fclk_div[] = {
-        { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
-        { .parent = NULL },
-};
-static struct clk func_48m_fclk = {
-        .name           = "func_48m_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .clksel         = func_48m_fclk_div,
-        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
-        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk func_48mc_fclk = {
-        .name           = "func_48mc_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 4,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel_rate div2_2to4_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel func_64m_fclk_div[] = {
-        { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
-        { .parent = NULL },
-};
-static struct clk func_64m_fclk = {
-        .name           = "func_64m_fclk",
-        .parent         = &dpll_per_m4x2_ck,
-        .clksel         = func_64m_fclk_div,
-        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
-        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel func_96m_fclk_div[] = {
-        { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
-        { .parent = NULL },
-};
-static struct clk func_96m_fclk = {
-        .name           = "func_96m_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .clksel         = func_96m_fclk_div,
-        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
-        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel_rate div2_1to8_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel init_60m_fclk_div[] = {
-        { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
-        { .parent = NULL },
-};
-static struct clk init_60m_fclk = {
-        .name           = "init_60m_fclk",
-        .parent         = &dpll_usb_m2_ck,
-        .clksel         = init_60m_fclk_div,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel l3_div_div[] = {
-        { .parent = &div_core_ck, .rates = div2_1to2_rates },
-        { .parent = NULL },
-};
-static struct clk l3_div_ck = {
-        .name           = "l3_div_ck",
-        .parent         = &div_core_ck,
-        .clkdm_name     = "cm_clkdm",
-        .clksel         = l3_div_div,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
-        .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel l4_div_div[] = {
-        { .parent = &l3_div_ck, .rates = div2_1to2_rates },
-        { .parent = NULL },
-};
-static struct clk l4_div_ck = {
-        .name           = "l4_div_ck",
-        .parent         = &l3_div_ck,
-        .clksel         = l4_div_div,
-        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
-        .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk lp_clk_div_ck = {
-        .name           = "lp_clk_div_ck",
-        .parent         = &dpll_abe_m2x2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 16,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel l4_wkup_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk l4_wkup_clk_mux_ck = {
-        .name           = "l4_wkup_clk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = l4_wkup_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel_rate div2_2to1_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel ocp_abe_iclk_div[] = {
-        { .parent = &aess_fclk, .rates = div2_2to1_rates },
-        { .parent = NULL },
-};
-static struct clk mpu_periphclk = {
-        .name           = "mpu_periphclk",
-        .parent         = &dpll_mpu_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 2,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static struct clk ocp_abe_iclk = {
-        .name           = "ocp_abe_iclk",
-        .parent         = &aess_fclk,
-        .clksel         = ocp_abe_iclk_div,
-        .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk per_abe_24m_fclk = {
-        .name           = "per_abe_24m_fclk",
-        .parent         = &dpll_abe_m2_ck,
-        .ops            = &clkops_null,
-        .fixed_div      = 4,
-        .recalc         = &omap_fixed_divisor_recalc,
-};
-static const struct clksel per_abe_nc_fclk_div[] = {
-        { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
-        { .parent = NULL },
-};
-static struct clk per_abe_nc_fclk = {
-        .name           = "per_abe_nc_fclk",
-        .parent         = &dpll_abe_m2_ck,
-        .clksel         = per_abe_nc_fclk_div,
-        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
-        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel pmd_stm_clock_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
-        { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-static struct clk pmd_stm_clock_mux_ck = {
-        .name           = "pmd_stm_clock_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static struct clk pmd_trace_clk_mux_ck = {
-        .name           = "pmd_trace_clk_mux_ck",
-        .parent         = &sys_clkin_ck,
-        .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel syc_clk_div_div[] = {
-        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
-        { .parent = NULL },
-};
-static struct clk syc_clk_div_ck = {
-        .name           = "syc_clk_div_ck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = syc_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-/* Leaf clocks controlled by modules */
-static struct clk aes1_fck = {
-        .name           = "aes1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk aes2_fck = {
-        .name           = "aes2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk aess_fck = {
-        .name           = "aess_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &aess_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk bandgap_fclk = {
-        .name           = "bandgap_fclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk des3des_fck = {
-        .name           = "des3des_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel dmic_sync_mux_sel[] = {
-        { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
-        { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
-        { .parent = &func_24m_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-static struct clk dmic_sync_mux_ck = {
-        .name           = "dmic_sync_mux_ck",
-        .parent         = &abe_24m_fclk,
-        .clksel         = dmic_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-        { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-/* Merged func_dmic_abe_gfclk into dmic */
-static struct clk dmic_fck = {
-        .name           = "dmic_fck",
-        .parent         = &dmic_sync_mux_ck,
-        .clksel         = func_dmic_abe_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-static struct clk dsp_fck = {
-        .name           = "dsp_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "tesla_clkdm",
-        .parent         = &dpll_iva_m4x2_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_sys_clk = {
-        .name           = "dss_sys_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
-        .clkdm_name     = "l3_dss_clkdm",
-        .parent         = &syc_clk_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_tv_clk = {
-        .name           = "dss_tv_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
-        .clkdm_name     = "l3_dss_clkdm",
-        .parent         = &extalt_clkin_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_dss_clk = {
-        .name           = "dss_dss_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-        .clkdm_name     = "l3_dss_clkdm",
-        .parent         = &dpll_per_m5x2_ck,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel_rate div3_8to32_rates[] = {
-        { .div = 8, .val = 0, .flags = RATE_IN_4460 },
-        { .div = 16, .val = 1, .flags = RATE_IN_4460 },
-        { .div = 32, .val = 2, .flags = RATE_IN_4460 },
-        { .div = 0 },
-};
-static const struct clksel div_ts_div[] = {
-        { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
-        { .parent = NULL },
-};
-static struct clk div_ts_ck = {
-        .name           = "div_ts_ck",
-        .parent         = &l4_wkup_clk_mux_ck,
-        .clksel         = div_ts_div,
-        .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk bandgap_ts_fclk = {
-        .name           = "bandgap_ts_fclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-        .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &div_ts_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_48mhz_clk = {
-        .name           = "dss_48mhz_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-        .clkdm_name     = "l3_dss_clkdm",
-        .parent         = &func_48mc_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk dss_fck = {
-        .name           = "dss_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_dss_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk efuse_ctrl_cust_fck = {
-        .name           = "efuse_ctrl_cust_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_cefuse_clkdm",
-        .parent         = &sys_clkin_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk emif1_fck = {
-        .name           = "emif1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "l3_emif_clkdm",
-        .parent         = &ddrphy_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk emif2_fck = {
-        .name           = "emif2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "l3_emif_clkdm",
-        .parent         = &ddrphy_ck,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel fdif_fclk_div[] = {
-        { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-/* Merged fdif_fclk into fdif */
-static struct clk fdif_fck = {
-        .name           = "fdif_fck",
-        .parent         = &dpll_per_m4x2_ck,
-        .clksel         = fdif_fclk_div,
-        .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-        .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "iss_clkdm",
-};
-static struct clk fpka_fck = {
-        .name           = "fpka_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio1_dbclk = {
-        .name           = "gpio1_dbclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio1_ick = {
-        .name           = "gpio1_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &l4_wkup_clk_mux_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio2_dbclk = {
-        .name           = "gpio2_dbclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio2_ick = {
-        .name           = "gpio2_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio3_dbclk = {
-        .name           = "gpio3_dbclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio3_ick = {
-        .name           = "gpio3_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio4_dbclk = {
-        .name           = "gpio4_dbclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio4_ick = {
-        .name           = "gpio4_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio5_dbclk = {
-        .name           = "gpio5_dbclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio6_dbclk = {
-        .name           = "gpio6_dbclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpio6_ick = {
-        .name           = "gpio6_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk gpmc_ick = {
-        .name           = "gpmc_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "l3_2_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel sgx_clk_mux_sel[] = {
-        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-/* Merged sgx_clk_mux into gpu */
-static struct clk gpu_fck = {
-        .name           = "gpu_fck",
-        .parent         = &dpll_core_m7x2_ck,
-        .clksel         = sgx_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_gfx_clkdm",
-};
-static struct clk hdq1w_fck = {
-        .name           = "hdq1w_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_12m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel hsi_fclk_div[] = {
-        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-/* Merged hsi_fclk into hsi */
-static struct clk hsi_fck = {
-        .name           = "hsi_fck",
-        .parent         = &dpll_per_m2x2_ck,
-        .clksel         = hsi_fclk_div,
-        .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-        .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-};
-static struct clk i2c1_fck = {
-        .name           = "i2c1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_96m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c2_fck = {
-        .name           = "i2c2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_96m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c3_fck = {
-        .name           = "i2c3_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_96m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk i2c4_fck = {
-        .name           = "i2c4_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_96m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk ipu_fck = {
-        .name           = "ipu_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "ducati_clkdm",
-        .parent         = &ducati_clk_mux_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk iss_ctrlclk = {
-        .name           = "iss_ctrlclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-        .clkdm_name     = "iss_clkdm",
-        .parent         = &func_96m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk iss_fck = {
-        .name           = "iss_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "iss_clkdm",
-        .parent         = &ducati_clk_mux_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk iva_fck = {
-        .name           = "iva_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "ivahd_clkdm",
-        .parent         = &dpll_iva_m5x2_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk kbd_fck = {
-        .name           = "kbd_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk l3_instr_ick = {
-        .name           = "l3_instr_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "l3_instr_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk l3_main_3_ick = {
-        .name           = "l3_main_3_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "l3_instr_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcasp_sync_mux_ck = {
-        .name           = "mcasp_sync_mux_ck",
-        .parent         = &abe_24m_fclk,
-        .clksel         = dmic_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-        { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-/* Merged func_mcasp_abe_gfclk into mcasp */
-static struct clk mcasp_fck = {
-        .name           = "mcasp_fck",
-        .parent         = &mcasp_sync_mux_ck,
-        .clksel         = func_mcasp_abe_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-static struct clk mcbsp1_sync_mux_ck = {
-        .name           = "mcbsp1_sync_mux_ck",
-        .parent         = &abe_24m_fclk,
-        .clksel         = dmic_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-        { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-/* Merged func_mcbsp1_gfclk into mcbsp1 */
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
-        .parent         = &mcbsp1_sync_mux_ck,
-        .clksel         = func_mcbsp1_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-static struct clk mcbsp2_sync_mux_ck = {
-        .name           = "mcbsp2_sync_mux_ck",
-        .parent         = &abe_24m_fclk,
-        .clksel         = dmic_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-        { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-/* Merged func_mcbsp2_gfclk into mcbsp2 */
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
-        .parent         = &mcbsp2_sync_mux_ck,
-        .clksel         = func_mcbsp2_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-static struct clk mcbsp3_sync_mux_ck = {
-        .name           = "mcbsp3_sync_mux_ck",
-        .parent         = &abe_24m_fclk,
-        .clksel         = dmic_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-        { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-/* Merged func_mcbsp3_gfclk into mcbsp3 */
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
-        .parent         = &mcbsp3_sync_mux_ck,
-        .clksel         = func_mcbsp3_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-static const struct clksel mcbsp4_sync_mux_sel[] = {
-        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
-        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk mcbsp4_sync_mux_ck = {
-        .name           = "mcbsp4_sync_mux_ck",
-        .parent         = &func_96m_fclk,
-        .clksel         = mcbsp4_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-        { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-/* Merged per_mcbsp4_gfclk into mcbsp4 */
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
-        .parent         = &mcbsp4_sync_mux_ck,
-        .clksel         = per_mcbsp4_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-static struct clk mcpdm_fck = {
-        .name           = "mcpdm_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &pad_clks_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi1_fck = {
-        .name           = "mcspi1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi2_fck = {
-        .name           = "mcspi2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi3_fck = {
-        .name           = "mcspi3_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mcspi4_fck = {
-        .name           = "mcspi4_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel hsmmc1_fclk_sel[] = {
-        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
-        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-/* Merged hsmmc1_fclk into mmc1 */
-static struct clk mmc1_fck = {
-        .name           = "mmc1_fck",
-        .parent         = &func_64m_fclk,
-        .clksel         = hsmmc1_fclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-};
-/* Merged hsmmc2_fclk into mmc2 */
-static struct clk mmc2_fck = {
-        .name           = "mmc2_fck",
-        .parent         = &func_64m_fclk,
-        .clksel         = hsmmc1_fclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-};
-static struct clk mmc3_fck = {
-        .name           = "mmc3_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmc4_fck = {
-        .name           = "mmc4_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk mmc5_fck = {
-        .name           = "mmc5_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk ocp2scp_usb_phy_phy_48m = {
-        .name           = "ocp2scp_usb_phy_phy_48m",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk ocp2scp_usb_phy_ick = {
-        .name           = "ocp2scp_usb_phy_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk ocp_wp_noc_ick = {
-        .name           = "ocp_wp_noc_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "l3_instr_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sha2md5_fck = {
-        .name           = "sha2md5_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk sl2if_ick = {
-        .name           = "sl2if_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "ivahd_clkdm",
-        .parent         = &dpll_iva_m5x2_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus1_fclk_1 = {
-        .name           = "slimbus1_fclk_1",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &func_24m_clk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus1_fclk_0 = {
-        .name           = "slimbus1_fclk_0",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &abe_24m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus1_fclk_2 = {
-        .name           = "slimbus1_fclk_2",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &pad_clks_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus1_slimbus_clk = {
-        .name           = "slimbus1_slimbus_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &slimbus_clk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus1_fck = {
-        .name           = "slimbus1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &ocp_abe_iclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus2_fclk_1 = {
-        .name           = "slimbus2_fclk_1",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &per_abe_24m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus2_fclk_0 = {
-        .name           = "slimbus2_fclk_0",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_24mc_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus2_slimbus_clk = {
-        .name           = "slimbus2_slimbus_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &pad_slimbus_core_clks_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk slimbus2_fck = {
-        .name           = "slimbus2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk smartreflex_core_fck = {
-        .name           = "smartreflex_core_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_ao_clkdm",
-        .parent         = &l4_wkup_clk_mux_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk smartreflex_iva_fck = {
-        .name           = "smartreflex_iva_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_ao_clkdm",
-        .parent         = &l4_wkup_clk_mux_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk smartreflex_mpu_fck = {
-        .name           = "smartreflex_mpu_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_ao_clkdm",
-        .parent         = &l4_wkup_clk_mux_ck,
-        .recalc         = &followparent_recalc,
-};
-/* Merged dmt1_clk_mux into timer1 */
-static struct clk timer1_fck = {
-        .name           = "timer1_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-};
-/* Merged cm2_dm10_mux into timer10 */
-static struct clk timer10_fck = {
-        .name           = "timer10_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-/* Merged cm2_dm11_mux into timer11 */
-static struct clk timer11_fck = {
-        .name           = "timer11_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-/* Merged cm2_dm2_mux into timer2 */
-static struct clk timer2_fck = {
-        .name           = "timer2_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-/* Merged cm2_dm3_mux into timer3 */
-static struct clk timer3_fck = {
-        .name           = "timer3_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-/* Merged cm2_dm4_mux into timer4 */
-static struct clk timer4_fck = {
-        .name           = "timer4_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-static const struct clksel timer5_sync_mux_sel[] = {
-        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-/* Merged timer5_sync_mux into timer5 */
-static struct clk timer5_fck = {
-        .name           = "timer5_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-/* Merged timer6_sync_mux into timer6 */
-static struct clk timer6_fck = {
-        .name           = "timer6_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-/* Merged timer7_sync_mux into timer7 */
-static struct clk timer7_fck = {
-        .name           = "timer7_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-/* Merged timer8_sync_mux into timer8 */
-static struct clk timer8_fck = {
-        .name           = "timer8_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-/* Merged cm2_dm9_mux into timer9 */
-static struct clk timer9_fck = {
-        .name           = "timer9_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = abe_dpll_bypass_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk uart4_fck = {
-        .name           = "uart4_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-        .parent         = &func_48m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_fs_fck = {
-        .name           = "usb_host_fs_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_48mc_fclk,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel utmi_p1_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk utmi_p1_gfclk = {
-        .name           = "utmi_p1_gfclk",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p1_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk usb_host_hs_utmi_p1_clk = {
-        .name           = "usb_host_hs_utmi_p1_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &utmi_p1_gfclk,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel utmi_p2_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk utmi_p2_gfclk = {
-        .name           = "utmi_p2_gfclk",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p2_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk usb_host_hs_utmi_p2_clk = {
-        .name           = "usb_host_hs_utmi_p2_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &utmi_p2_gfclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_hs_utmi_p3_clk = {
-        .name           = "usb_host_hs_utmi_p3_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_hs_hsic480m_p1_clk = {
-        .name           = "usb_host_hs_hsic480m_p1_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &dpll_usb_m2_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_hs_hsic60m_p1_clk = {
-        .name           = "usb_host_hs_hsic60m_p1_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_hs_hsic60m_p2_clk = {
-        .name           = "usb_host_hs_hsic60m_p2_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_hs_hsic480m_p2_clk = {
-        .name           = "usb_host_hs_hsic480m_p2_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &dpll_usb_m2_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_hs_func48mclk = {
-        .name           = "usb_host_hs_func48mclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_48mc_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_host_hs_fck = {
-        .name           = "usb_host_hs_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel otg_60m_gfclk_sel[] = {
-        { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
-        { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-static struct clk otg_60m_gfclk = {
-        .name           = "otg_60m_gfclk",
-        .parent         = &utmi_phy_clkout_ck,
-        .clksel         = otg_60m_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk usb_otg_hs_xclk = {
-        .name           = "usb_otg_hs_xclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &otg_60m_gfclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_otg_hs_ick = {
-        .name           = "usb_otg_hs_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l3_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_phy_cm_clk32k = {
-        .name           = "usb_phy_cm_clk32k",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
-        .clkdm_name     = "l4_ao_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_tll_hs_usb_ch2_clk = {
-        .name           = "usb_tll_hs_usb_ch2_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_tll_hs_usb_ch0_clk = {
-        .name           = "usb_tll_hs_usb_ch0_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_tll_hs_usb_ch1_clk = {
-        .name           = "usb_tll_hs_usb_ch1_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usb_tll_hs_ick = {
-        .name           = "usb_tll_hs_ick",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l4_div_ck,
-        .recalc         = &followparent_recalc,
-};
-static const struct clksel_rate div2_14to18_rates[] = {
-        { .div = 14, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 18, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static const struct clksel usim_fclk_div[] = {
-        { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
-        { .parent = NULL },
-};
-static struct clk usim_ck = {
-        .name           = "usim_ck",
-        .parent         = &dpll_per_m4x2_ck,
-        .clksel         = usim_fclk_div,
-        .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk usim_fclk = {
-        .name           = "usim_fclk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &usim_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk usim_fck = {
-        .name           = "usim_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wd_timer2_fck = {
-        .name           = "wd_timer2_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-static struct clk wd_timer3_fck = {
-        .name           = "wd_timer3_fck",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &sys_32k_ck,
-        .recalc         = &followparent_recalc,
-};
-/* Remaining optional clocks */
-static const struct clksel stm_clk_div_div[] = {
-        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-static struct clk stm_clk_div_ck = {
-        .name           = "stm_clk_div_ck",
-        .parent         = &pmd_stm_clock_mux_ck,
-        .clksel         = stm_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel trace_clk_div_div[] = {
-        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-static struct clk trace_clk_div_ck = {
-        .name           = "trace_clk_div_ck",
-        .parent         = &pmd_trace_clk_mux_ck,
-        .clkdm_name     = "emu_sys_clkdm",
-        .clksel         = trace_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-/* SCRM aux clk nodes */
-static const struct clksel auxclk_src_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-static const struct clksel_rate div16_1to16_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 3, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 3, .flags = RATE_IN_4430 },
-        { .div = 5, .val = 4, .flags = RATE_IN_4430 },
-        { .div = 6, .val = 5, .flags = RATE_IN_4430 },
-        { .div = 7, .val = 6, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 7, .flags = RATE_IN_4430 },
-        { .div = 9, .val = 8, .flags = RATE_IN_4430 },
-        { .div = 10, .val = 9, .flags = RATE_IN_4430 },
-        { .div = 11, .val = 10, .flags = RATE_IN_4430 },
-        { .div = 12, .val = 11, .flags = RATE_IN_4430 },
-        { .div = 13, .val = 12, .flags = RATE_IN_4430 },
-        { .div = 14, .val = 13, .flags = RATE_IN_4430 },
-        { .div = 15, .val = 14, .flags = RATE_IN_4430 },
-        { .div = 16, .val = 15, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-static struct clk auxclk0_src_ck = {
-        .name           = "auxclk0_src_ck",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_src_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
-        .clksel_mask    = OMAP4_SRCSELECT_MASK,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4_SCRM_AUXCLK0,
-        .enable_bit     = OMAP4_ENABLE_SHIFT,
-};
-static const struct clksel auxclk0_sel[] = {
-        { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
-        { .parent = NULL },
-};
-static struct clk auxclk0_ck = {
-        .name           = "auxclk0_ck",
-        .parent         = &auxclk0_src_ck,
-        .clksel         = auxclk0_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
-        .clksel_mask    = OMAP4_CLKDIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk auxclk1_src_ck = {
-        .name           = "auxclk1_src_ck",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_src_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
-        .clksel_mask    = OMAP4_SRCSELECT_MASK,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4_SCRM_AUXCLK1,
-        .enable_bit     = OMAP4_ENABLE_SHIFT,
-};
-static const struct clksel auxclk1_sel[] = {
-        { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
-        { .parent = NULL },
-};
-static struct clk auxclk1_ck = {
-        .name           = "auxclk1_ck",
-        .parent         = &auxclk1_src_ck,
-        .clksel         = auxclk1_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
-        .clksel_mask    = OMAP4_CLKDIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk auxclk2_src_ck = {
-        .name           = "auxclk2_src_ck",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_src_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
-        .clksel_mask    = OMAP4_SRCSELECT_MASK,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4_SCRM_AUXCLK2,
-        .enable_bit     = OMAP4_ENABLE_SHIFT,
-};
-static const struct clksel auxclk2_sel[] = {
-        { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
-        { .parent = NULL },
-};
-static struct clk auxclk2_ck = {
-        .name           = "auxclk2_ck",
-        .parent         = &auxclk2_src_ck,
-        .clksel         = auxclk2_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
-        .clksel_mask    = OMAP4_CLKDIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk auxclk3_src_ck = {
-        .name           = "auxclk3_src_ck",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_src_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
-        .clksel_mask    = OMAP4_SRCSELECT_MASK,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4_SCRM_AUXCLK3,
-        .enable_bit     = OMAP4_ENABLE_SHIFT,
-};
-static const struct clksel auxclk3_sel[] = {
-        { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
-        { .parent = NULL },
-};
-static struct clk auxclk3_ck = {
-        .name           = "auxclk3_ck",
-        .parent         = &auxclk3_src_ck,
-        .clksel         = auxclk3_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
-        .clksel_mask    = OMAP4_CLKDIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk auxclk4_src_ck = {
-        .name           = "auxclk4_src_ck",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_src_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
-        .clksel_mask    = OMAP4_SRCSELECT_MASK,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4_SCRM_AUXCLK4,
-        .enable_bit     = OMAP4_ENABLE_SHIFT,
-};
-static const struct clksel auxclk4_sel[] = {
-        { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
-        { .parent = NULL },
-};
-static struct clk auxclk4_ck = {
-        .name           = "auxclk4_ck",
-        .parent         = &auxclk4_src_ck,
-        .clksel         = auxclk4_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
-        .clksel_mask    = OMAP4_CLKDIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static struct clk auxclk5_src_ck = {
-        .name           = "auxclk5_src_ck",
-        .parent         = &sys_clkin_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_omap2_dflt,
-        .clksel         = auxclk_src_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
-        .clksel_mask    = OMAP4_SRCSELECT_MASK,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4_SCRM_AUXCLK5,
-        .enable_bit     = OMAP4_ENABLE_SHIFT,
-};
-static const struct clksel auxclk5_sel[] = {
-        { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
-        { .parent = NULL },
-};
-static struct clk auxclk5_ck = {
-        .name           = "auxclk5_ck",
-        .parent         = &auxclk5_src_ck,
-        .clksel         = auxclk5_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
-        .clksel_mask    = OMAP4_CLKDIV_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-static const struct clksel auxclkreq_sel[] = {
-        { .parent = &auxclk0_ck, .rates = div_1_0_rates },
-        { .parent = &auxclk1_ck, .rates = div_1_1_rates },
-        { .parent = &auxclk2_ck, .rates = div_1_2_rates },
-        { .parent = &auxclk3_ck, .rates = div_1_3_rates },
-        { .parent = &auxclk4_ck, .rates = div_1_4_rates },
-        { .parent = &auxclk5_ck, .rates = div_1_5_rates },
-        { .parent = NULL },
-};
-static struct clk auxclkreq0_ck = {
-        .name           = "auxclkreq0_ck",
-        .parent         = &auxclk0_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_null,
-        .clksel         = auxclkreq_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
-        .clksel_mask    = OMAP4_MAPPING_MASK,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk auxclkreq1_ck = {
-        .name           = "auxclkreq1_ck",
-        .parent         = &auxclk1_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_null,
-        .clksel         = auxclkreq_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
-        .clksel_mask    = OMAP4_MAPPING_MASK,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk auxclkreq2_ck = {
-        .name           = "auxclkreq2_ck",
-        .parent         = &auxclk2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_null,
-        .clksel         = auxclkreq_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
-        .clksel_mask    = OMAP4_MAPPING_MASK,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk auxclkreq3_ck = {
-        .name           = "auxclkreq3_ck",
-        .parent         = &auxclk3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_null,
-        .clksel         = auxclkreq_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
-        .clksel_mask    = OMAP4_MAPPING_MASK,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk auxclkreq4_ck = {
-        .name           = "auxclkreq4_ck",
-        .parent         = &auxclk4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_null,
-        .clksel         = auxclkreq_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
-        .clksel_mask    = OMAP4_MAPPING_MASK,
-        .recalc         = &omap2_clksel_recalc,
-};
-static struct clk auxclkreq5_ck = {
-        .name           = "auxclkreq5_ck",
-        .parent         = &auxclk5_ck,
-        .init           = &omap2_init_clksel_parent,
-        .ops            = &clkops_null,
-        .clksel         = auxclkreq_sel,
-        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
-        .clksel_mask    = OMAP4_MAPPING_MASK,
-        .recalc         = &omap2_clksel_recalc,
-};
-/*
- * clkdev
- */
-static struct omap_clk omap44xx_clks[] = {
-        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
-        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
-        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
-        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
-        CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
-        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
-        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
-        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
-        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
-        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
-        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
-        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
-        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
-        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
-        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
-        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
-        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
-        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
-        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
-        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
-        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
-        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
-        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
-        CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
-        CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
-        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
-        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
-        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
-        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
-        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
-        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
-        CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
-        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
-        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
-        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
-        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
-        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
-        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
-        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
-        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
-        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
-        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
-        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
-        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
-        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
-        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
-        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
-        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
-        CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
-        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
-        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
-        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
-        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
-        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
-        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
-        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
-        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
-        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
-        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
-        CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
-        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
-        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
-        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
-        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
-        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
-        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
-        CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
-        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
-        CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
-        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
-        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
-        CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
-        CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
-        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
-        CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
-        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
-        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
-        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
-        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
-        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
-        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
-        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
-        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
-        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
-        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
-        CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
-        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
-        CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
-        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
-        CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
-        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
-        CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
-        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
-        CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
-        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
-        CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
-        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
-        CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
-        CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
-        CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
-        CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
-        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
-        CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
-        CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
-        CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
-        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
-        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
-        CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
-        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
-        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
-        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
-        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
-        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
-        CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
-        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
-        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
-        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
-        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
-        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
-        CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
-        CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
-        CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
-        CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
-        CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
-        CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
-        CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
-        CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
-        CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
-        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
-        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
-        CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
-        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
-        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
-        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
-        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
-        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
-        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
-        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
-        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
-        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
-        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
-        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
-        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
-        CLK(NULL,       "timer1_fck",                   &timer1_fck,    CK_443X),
-        CLK(NULL,       "timer10_fck",                  &timer10_fck,   CK_443X),
-        CLK(NULL,       "timer11_fck",                  &timer11_fck,   CK_443X),
-        CLK(NULL,       "timer2_fck",                   &timer2_fck,    CK_443X),
-        CLK(NULL,       "timer3_fck",                   &timer3_fck,    CK_443X),
-        CLK(NULL,       "timer4_fck",                   &timer4_fck,    CK_443X),
-        CLK(NULL,       "timer5_fck",                   &timer5_fck,    CK_443X),
-        CLK(NULL,       "timer6_fck",                   &timer6_fck,    CK_443X),
-        CLK(NULL,       "timer7_fck",                   &timer7_fck,    CK_443X),
-        CLK(NULL,       "timer8_fck",                   &timer8_fck,    CK_443X),
-        CLK(NULL,       "timer9_fck",                   &timer9_fck,    CK_443X),
-        CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
-        CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
-        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
-        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
-        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
-        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
-        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
-        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
-        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
-        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
-        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
-        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
-        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
-        CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
-        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
-        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
-        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
-        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
-        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
-        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
-        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
-        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
-        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
-        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
-        CLK("omap-gpmc",        "fck",                          &dummy_ck,      CK_443X),
-        CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
-        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
-        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
-        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
-        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
-        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-        CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
-        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("49038000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4903a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4903c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4903e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
-};
-int __init omap4xxx_clk_init(void)
-{
-        struct omap_clk *c;
-        u32 cpu_clkflg;
-        if (cpu_is_omap443x()) {
-                cpu_mask = RATE_IN_4430;
-                cpu_clkflg = CK_443X;
-        } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-                cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-                cpu_clkflg = CK_446X | CK_443X;
-                if (cpu_is_omap447x())
-                        pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-        } else {
-                return 0;
-        }
-        clk_init(&omap2_clk_functions);
-        /*
-         * Must stay commented until all OMAP SoC drivers are
-         * converted to runtime PM, or drivers may start crashing
-         *
-         * omap2_clk_disable_clkdm_control();
-         */
-        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
-                                                                          c++)
-                clk_preinit(c->lk.clk);
-        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
-                                                                          c++)
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                        omap2_init_clk_clkdm(c->lk.clk);
-                }
-        /* Disable autoidle on all clocks; let the PM code enable it later */
-        omap_clk_disable_autoidle_all();
-        recalculate_root_clocks();
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index b9f3ba68148c..ef4d21bfb964 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -16,6 +16,7 @@
 * OMAP3xxx clock definition files.
 */
+#include <linux/clk-private.h>
 #include "clock.h"
 /* clksel_rate data common to 24xx/343x */
@@ -52,6 +53,13 @@ const struct clksel_rate div_1_0_rates[] = {
        { .div = 0 },
 };
+const struct clksel_rate div3_1to4_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
 const struct clksel_rate div_1_1_rates[] = {
        { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
        { .div = 0 },
@@ -109,14 +117,10 @@ const struct clksel_rate div31_1to31_rates[] = {
 /* Clocks shared between various OMAP SoCs */
-struct clk virt_19200000_ck = {
+static struct clk_ops dummy_ck_ops = {};
-        .name           = "virt_19200000_ck",
-        .ops            = &clkops_null,
-        .rate           = 19200000,
-};
-struct clk virt_26000000_ck = {
+struct clk dummy_ck = {
-        .name           = "virt_26000000_ck",
+        .name = "dummy_clk",
-        .ops            = &clkops_null,
+        .ops = &dummy_ck_ops,
-        .rate           = 26000000,
+        .flags = CLK_IS_BASIC,
 };
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 512e79a842cb..384873580b23 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -22,12 +22,14 @@
 #include <linux/clk.h>
 #include <linux/limits.h>
 #include <linux/err.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <plat/clock.h>
+#include "soc.h"
+#include "clock.h"
 #include "clockdomain.h"
 /* clkdm_list contains all registered struct clockdomains */
@@ -946,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
        return 0;
 }
-static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
-{
-        unsigned long flags;
-        if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
-                return -EINVAL;
-        spin_lock_irqsave(&clkdm->lock, flags);
-        if (atomic_read(&clkdm->usecount) == 0) {
-                spin_unlock_irqrestore(&clkdm->lock, flags);
-                WARN_ON(1); /* underflow */
-                return -ERANGE;
-        }
-        if (atomic_dec_return(&clkdm->usecount) > 0) {
-                spin_unlock_irqrestore(&clkdm->lock, flags);
-                return 0;
-        }
-        arch_clkdm->clkdm_clk_disable(clkdm);
-        pwrdm_state_switch(clkdm->pwrdm.ptr);
-        spin_unlock_irqrestore(&clkdm->lock, flags);
-        pr_debug("clockdomain: %s: disabled\n", clkdm->name);
-        return 0;
-}
 /**
 * clkdm_clk_enable - add an enabled downstream clock to this clkdm
 * @clkdm: struct clockdomain *
@@ -1017,15 +990,37 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
 */
 int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
-        /*
+        unsigned long flags;
-         * XXX Rewrite this code to maintain a list of enabled
-         * downstream clocks for debugging purposes?
-         */
-        if (!clk)
+        if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
                return -EINVAL;
-        return _clkdm_clk_hwmod_disable(clkdm);
+        spin_lock_irqsave(&clkdm->lock, flags);
+        /* corner case: disabling unused clocks */
+        if (__clk_get_enable_count(clk) == 0)
+                goto ccd_exit;
+        if (atomic_read(&clkdm->usecount) == 0) {
+                spin_unlock_irqrestore(&clkdm->lock, flags);
+                WARN_ON(1); /* underflow */
+                return -ERANGE;
+        }
+        if (atomic_dec_return(&clkdm->usecount) > 0) {
+                spin_unlock_irqrestore(&clkdm->lock, flags);
+                return 0;
+        }
+        arch_clkdm->clkdm_clk_disable(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
+        pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+ccd_exit:
+        spin_unlock_irqrestore(&clkdm->lock, flags);
+        return 0;
 }
 /**
@@ -1076,6 +1071,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 */
 int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
 {
+        unsigned long flags;
        /* The clkdm attribute does not exist yet prior OMAP4 */
        if (cpu_is_omap24xx() || cpu_is_omap34xx())
                return 0;
@@ -1085,9 +1082,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
         * downstream hwmods for debugging purposes?
         */
-        if (!oh)
+        if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
                return -EINVAL;
-        return _clkdm_clk_hwmod_disable(clkdm);
+        spin_lock_irqsave(&clkdm->lock, flags);
+        if (atomic_read(&clkdm->usecount) == 0) {
+                spin_unlock_irqrestore(&clkdm->lock, flags);
+                WARN_ON(1); /* underflow */
+                return -ERANGE;
+        }
+        if (atomic_dec_return(&clkdm->usecount) > 0) {
+                spin_unlock_irqrestore(&clkdm->lock, flags);
+                return 0;
+        }
+        arch_clkdm->clkdm_clk_disable(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
+        spin_unlock_irqrestore(&clkdm->lock, flags);
+        pr_debug("clockdomain: %s: disabled\n", clkdm->name);
+        return 0;
 }
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 629576be7444..bc42446e23ab 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -18,9 +18,8 @@
 #include <linux/spinlock.h>
 #include "powerdomain.h"
-#include <plat/clock.h>
+#include "clock.h"
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/cpu.h>
 /*
 * Clockdomain flags
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
deleted file mode 100644
index 70294f54e35a..000000000000
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * OMAP2 and OMAP3 clockdomain control
- *
- * Copyright (C) 2008-2010 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/types.h>
-#include <plat/prcm.h>
-#include "prm.h"
-#include "prm2xxx_3xxx.h"
-#include "cm.h"
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-24xx.h"
-#include "cm-regbits-34xx.h"
-#include "prm-regbits-24xx.h"
-#include "clockdomain.h"
-static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
-                                                struct clockdomain *clkdm2)
-{
-        omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
-        return 0;
-}
-static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
-        return 0;
-}
-static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
-                                PM_WKDEP, (1 << clkdm2->dep_bit));
-}
-static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
-{
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!cd->clkdm)
-                        continue; /* only happens if data is erroneous */
-                /* PRM accesses are slow, so minimize them */
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->wkdep_usecount, 0);
-        }
-        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
-                                 PM_WKDEP);
-        return 0;
-}
-static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP);
-        return 0;
-}
-static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
-                                clkdm1->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP);
-        return 0;
-}
-static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
-                                                 struct clockdomain *clkdm2)
-{
-        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
-}
-static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
-{
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!cd->clkdm)
-                        continue; /* only happens if data is erroneous */
-                /* PRM accesses are slow, so minimize them */
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->sleepdep_usecount, 0);
-        }
-        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
-                                OMAP3430_CM_SLEEPDEP);
-        return 0;
-}
-static int omap2_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
-                                clkdm->pwrdm.ptr->prcm_offs,
-                                OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
-                                clkdm->pwrdm.ptr->prcm_offs,
-                                OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_add_autodeps(clkdm);
-        omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-}
-static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_del_autodeps(clkdm);
-}
-static void _enable_hwsup(struct clockdomain *clkdm)
-{
-        if (cpu_is_omap24xx())
-                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                               clkdm->clktrctrl_mask);
-        else if (cpu_is_omap34xx())
-                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                               clkdm->clktrctrl_mask);
-}
-static void _disable_hwsup(struct clockdomain *clkdm)
-{
-        if (cpu_is_omap24xx())
-                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                                clkdm->clktrctrl_mask);
-        else if (cpu_is_omap34xx())
-                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                                clkdm->clktrctrl_mask);
-}
-static int omap3_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_add_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                        omap2_clkdm_wakeup(clkdm);
-        }
-        return 0;
-}
-static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_del_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
-                        omap2_clkdm_sleep(clkdm);
-        }
-        return 0;
-}
-static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_add_autodeps(clkdm);
-        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-}
-static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        if (atomic_read(&clkdm->usecount) > 0)
-                _clkdm_del_autodeps(clkdm);
-}
-static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-        /*
-         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
-         * more details on the unpleasant problem this is working
-         * around
-         */
-        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
-            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
-                omap3_clkdm_wakeup(clkdm);
-                return 0;
-        }
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_add_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                        omap3_clkdm_wakeup(clkdm);
-        }
-        return 0;
-}
-static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-        if (!clkdm->clktrctrl_mask)
-                return 0;
-        /*
-         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
-         * more details on the unpleasant problem this is working
-         * around
-         */
-        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
-            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-                _enable_hwsup(clkdm);
-                return 0;
-        }
-        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        if (hwsup) {
-                /* Disable HW transitions when we are changing deps */
-                _disable_hwsup(clkdm);
-                _clkdm_del_autodeps(clkdm);
-                _enable_hwsup(clkdm);
-        } else {
-                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
-                        omap3_clkdm_sleep(clkdm);
-        }
-        return 0;
-}
-struct clkdm_ops omap2_clkdm_operations = {
-        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
-        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
-        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
-        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
-        .clkdm_sleep            = omap2_clkdm_sleep,
-        .clkdm_wakeup           = omap2_clkdm_wakeup,
-        .clkdm_allow_idle       = omap2_clkdm_allow_idle,
-        .clkdm_deny_idle        = omap2_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
-};
-struct clkdm_ops omap3_clkdm_operations = {
-        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
-        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
-        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
-        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
-        .clkdm_add_sleepdep     = omap3_clkdm_add_sleepdep,
-        .clkdm_del_sleepdep     = omap3_clkdm_del_sleepdep,
-        .clkdm_read_sleepdep    = omap3_clkdm_read_sleepdep,
-        .clkdm_clear_all_sleepdeps      = omap3_clkdm_clear_all_sleepdeps,
-        .clkdm_sleep            = omap3_clkdm_sleep,
-        .clkdm_wakeup           = omap3_clkdm_wakeup,
-        .clkdm_allow_idle       = omap3_clkdm_allow_idle,
-        .clkdm_deny_idle        = omap3_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
-};
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c
deleted file mode 100644
index aca6388fad76..000000000000
--- a/arch/arm/mach-omap2/clockdomain33xx.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * AM33XX clockdomain control
- *
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include "clockdomain.h"
-#include "cm33xx.h"
-static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
-}
-static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
-}
-static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                return am33xx_clkdm_wakeup(clkdm);
-        return 0;
-}
-static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-        hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
-        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
-                am33xx_clkdm_sleep(clkdm);
-        return 0;
-}
-struct clkdm_ops am33xx_clkdm_operations = {
-        .clkdm_sleep            = am33xx_clkdm_sleep,
-        .clkdm_wakeup           = am33xx_clkdm_wakeup,
-        .clkdm_allow_idle       = am33xx_clkdm_allow_idle,
-        .clkdm_deny_idle        = am33xx_clkdm_deny_idle,
-        .clkdm_clk_enable       = am33xx_clkdm_clk_enable,
-        .clkdm_clk_disable      = am33xx_clkdm_clk_disable,
-};
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
deleted file mode 100644
index 6fc6155625bc..000000000000
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * OMAP4 clockdomain control
- *
- * Copyright (C) 2008-2010 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include "clockdomain.h"
-#include "cminst44xx.h"
-#include "cm44xx.h"
-static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
-                                        struct clockdomain *clkdm2)
-{
-        omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
-                                        clkdm1->prcm_partition,
-                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
-                                        OMAP4_CM_STATICDEP);
-        return 0;
-}
-static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
-                                        struct clockdomain *clkdm2)
-{
-        omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
-                                        clkdm1->prcm_partition,
-                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
-                                        OMAP4_CM_STATICDEP);
-        return 0;
-}
-static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
-                                        struct clockdomain *clkdm2)
-{
-        return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
-                                        clkdm1->cm_inst, clkdm1->clkdm_offs +
-                                        OMAP4_CM_STATICDEP,
-                                        (1 << clkdm2->dep_bit));
-}
-static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
-{
-        struct clkdm_dep *cd;
-        u32 mask = 0;
-        if (!clkdm->prcm_partition)
-                return 0;
-        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                if (!cd->clkdm)
-                        continue; /* only happens if data is erroneous */
-                mask |= 1 << cd->clkdm->dep_bit;
-                atomic_set(&cd->wkdep_usecount, 0);
-        }
-        omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs +
-                                        OMAP4_CM_STATICDEP);
-        return 0;
-}
-static int omap4_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-        return 0;
-}
-static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
-{
-        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-}
-static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
-{
-        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                omap4_clkdm_wakeup(clkdm);
-        else
-                omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
-                                                 clkdm->cm_inst,
-                                                 clkdm->clkdm_offs);
-}
-static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
-{
-        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
-                return omap4_clkdm_wakeup(clkdm);
-        return 0;
-}
-static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
-{
-        bool hwsup = false;
-        if (!clkdm->prcm_partition)
-                return 0;
-        /*
-         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
-         * more details on the unpleasant problem this is working
-         * around
-         */
-        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
-            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-                omap4_clkdm_allow_idle(clkdm);
-                return 0;
-        }
-        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
-        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
-                omap4_clkdm_sleep(clkdm);
-        return 0;
-}
-struct clkdm_ops omap4_clkdm_operations = {
-        .clkdm_add_wkdep        = omap4_clkdm_add_wkup_sleep_dep,
-        .clkdm_del_wkdep        = omap4_clkdm_del_wkup_sleep_dep,
-        .clkdm_read_wkdep       = omap4_clkdm_read_wkup_sleep_dep,
-        .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
-        .clkdm_add_sleepdep     = omap4_clkdm_add_wkup_sleep_dep,
-        .clkdm_del_sleepdep     = omap4_clkdm_del_wkup_sleep_dep,
-        .clkdm_read_sleepdep    = omap4_clkdm_read_wkup_sleep_dep,
-        .clkdm_clear_all_sleepdeps      = omap4_clkdm_clear_all_wkup_sleep_deps,
-        .clkdm_sleep            = omap4_clkdm_sleep,
-        .clkdm_wakeup           = omap4_clkdm_wakeup,
-        .clkdm_allow_idle       = omap4_clkdm_allow_idle,
-        .clkdm_deny_idle        = omap4_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
-};
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 5c741852fac0..7e76becf3a4a 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -35,6 +35,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index f09617555e15..b923007e45d0 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -35,6 +35,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 933a35cd124a..e6b91e552d3d 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -33,6 +33,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include "soc.h"
 #include "clockdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 686290437568..669ef51b17a8 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -59,6 +59,7 @@
 /* CM_CLKSEL_MPU */
 #define OMAP24XX_CLKSEL_MPU_SHIFT                       0
 #define OMAP24XX_CLKSEL_MPU_MASK                        (0x1f << 0)
+#define OMAP24XX_CLKSEL_MPU_WIDTH                       5
 /* CM_CLKSTCTRL_MPU */
 #define OMAP24XX_AUTOSTATE_MPU_SHIFT                    0
@@ -237,8 +238,10 @@
 #define OMAP24XX_CLKSEL_DSS1_MASK                       (0x1f << 8)
 #define OMAP24XX_CLKSEL_L4_SHIFT                        5
 #define OMAP24XX_CLKSEL_L4_MASK                         (0x3 << 5)
+#define OMAP24XX_CLKSEL_L4_WIDTH                        2
 #define OMAP24XX_CLKSEL_L3_SHIFT                        0
 #define OMAP24XX_CLKSEL_L3_MASK                         (0x1f << 0)
+#define OMAP24XX_CLKSEL_L3_WIDTH                        5
 /* CM_CLKSEL2_CORE */
 #define OMAP24XX_CLKSEL_GPT12_SHIFT                     22
@@ -333,7 +336,9 @@
 #define OMAP24XX_EN_DPLL_MASK                           (0x3 << 0)
 /* CM_IDLEST_CKGEN */
+#define OMAP24XX_ST_54M_APLL_SHIFT                      9
 #define OMAP24XX_ST_54M_APLL_MASK                       (1 << 9)
+#define OMAP24XX_ST_96M_APLL_SHIFT                      8
 #define OMAP24XX_ST_96M_APLL_MASK                       (1 << 8)
 #define OMAP24XX_ST_54M_CLK_MASK                        (1 << 6)
 #define OMAP24XX_ST_12M_CLK_MASK                        (1 << 5)
@@ -361,8 +366,10 @@
 #define OMAP24XX_DPLL_DIV_MASK                          (0xf << 8)
 #define OMAP24XX_54M_SOURCE_SHIFT                       5
 #define OMAP24XX_54M_SOURCE_MASK                        (1 << 5)
+#define OMAP24XX_54M_SOURCE_WIDTH                       1
 #define OMAP2430_96M_SOURCE_SHIFT                       4
 #define OMAP2430_96M_SOURCE_MASK                        (1 << 4)
+#define OMAP2430_96M_SOURCE_WIDTH                       1
 #define OMAP24XX_48M_SOURCE_SHIFT                       3
 #define OMAP24XX_48M_SOURCE_MASK                        (1 << 3)
 #define OMAP2430_ALTCLK_SOURCE_SHIFT                    0
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 59598ffd8783..adf78d325804 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -81,6 +81,7 @@
 /* CM_CLKSEL1_PLL_IVA2 */
 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
 #define OMAP3430_IVA2_CLK_SRC_MASK                      (0x7 << 19)
+#define OMAP3430_IVA2_CLK_SRC_WIDTH                     3
 #define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
 #define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
 #define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
@@ -89,6 +90,7 @@
 /* CM_CLKSEL2_PLL_IVA2 */
 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT             0
 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK              (0x1f << 0)
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH             5
 /* CM_CLKSTCTRL_IVA2 */
 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT                   0
@@ -118,6 +120,7 @@
 /* CM_IDLEST_PLL_MPU */
 #define OMAP3430_ST_MPU_CLK_SHIFT                       0
 #define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
+#define OMAP3430_ST_MPU_CLK_WIDTH                       1
 /* CM_AUTOIDLE_PLL_MPU */
 #define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0
@@ -126,6 +129,7 @@
 /* CM_CLKSEL1_PLL_MPU */
 #define OMAP3430_MPU_CLK_SRC_SHIFT                      19
 #define OMAP3430_MPU_CLK_SRC_MASK                       (0x7 << 19)
+#define OMAP3430_MPU_CLK_SRC_WIDTH                      3
 #define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
 #define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
 #define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
@@ -134,6 +138,7 @@
 /* CM_CLKSEL2_PLL_MPU */
 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT              0
 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK               (0x1f << 0)
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH              5
 /* CM_CLKSTCTRL_MPU */
 #define OMAP3430_CLKTRCTRL_MPU_SHIFT                    0
@@ -345,10 +350,13 @@
 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK               (0x3 << 4)
 #define OMAP3430_CLKSEL_L4_SHIFT                        2
 #define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
+#define OMAP3430_CLKSEL_L4_WIDTH                        2
 #define OMAP3430_CLKSEL_L3_SHIFT                        0
 #define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
+#define OMAP3430_CLKSEL_L3_WIDTH                        2
 #define OMAP3630_CLKSEL_96M_SHIFT                       12
 #define OMAP3630_CLKSEL_96M_MASK                        (0x3 << 12)
+#define OMAP3630_CLKSEL_96M_WIDTH                       2
 /* CM_CLKSTCTRL_CORE */
 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
@@ -452,6 +460,7 @@
 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK                 (0xf << 3)
 #define OMAP3430_CLKSEL_RM_SHIFT                        1
 #define OMAP3430_CLKSEL_RM_MASK                         (0x3 << 1)
+#define OMAP3430_CLKSEL_RM_WIDTH                        2
 #define OMAP3430_CLKSEL_GPT1_SHIFT                      0
 #define OMAP3430_CLKSEL_GPT1_MASK                       (1 << 0)
@@ -520,14 +529,17 @@
 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK              (0x1f << 27)
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH             5
 #define OMAP3430_CORE_DPLL_MULT_SHIFT                   16
 #define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
 #define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
 #define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
 #define OMAP3430_SOURCE_96M_SHIFT                       6
 #define OMAP3430_SOURCE_96M_MASK                        (1 << 6)
+#define OMAP3430_SOURCE_96M_WIDTH                       1
 #define OMAP3430_SOURCE_54M_SHIFT                       5
 #define OMAP3430_SOURCE_54M_MASK                        (1 << 5)
+#define OMAP3430_SOURCE_54M_WIDTH                       1
 #define OMAP3430_SOURCE_48M_SHIFT                       3
 #define OMAP3430_SOURCE_48M_MASK                        (1 << 3)
@@ -545,7 +557,9 @@
 /* CM_CLKSEL3_PLL */
 #define OMAP3430_DIV_96M_SHIFT                          0
 #define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
+#define OMAP3430_DIV_96M_WIDTH                          5
 #define OMAP3630_DIV_96M_MASK                           (0x3f << 0)
+#define OMAP3630_DIV_96M_WIDTH                          6
 /* CM_CLKSEL4_PLL */
 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT             8
@@ -556,12 +570,14 @@
 /* CM_CLKSEL5_PLL */
 #define OMAP3430ES2_DIV_120M_SHIFT                      0
 #define OMAP3430ES2_DIV_120M_MASK                       (0x1f << 0)
+#define OMAP3430ES2_DIV_120M_WIDTH                      5
 /* CM_CLKOUT_CTRL */
 #define OMAP3430_CLKOUT2_EN_SHIFT                       7
 #define OMAP3430_CLKOUT2_EN_MASK                        (1 << 7)
 #define OMAP3430_CLKOUT2_DIV_SHIFT                      3
 #define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
+#define OMAP3430_CLKOUT2_DIV_WIDTH                      3
 #define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
 #define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
@@ -592,10 +608,14 @@
 /* CM_CLKSEL_DSS */
 #define OMAP3430_CLKSEL_TV_SHIFT                        8
 #define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
+#define OMAP3430_CLKSEL_TV_WIDTH                        5
 #define OMAP3630_CLKSEL_TV_MASK                         (0x3f << 8)
+#define OMAP3630_CLKSEL_TV_WIDTH                        6
 #define OMAP3430_CLKSEL_DSS1_SHIFT                      0
 #define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
+#define OMAP3430_CLKSEL_DSS1_WIDTH                      5
 #define OMAP3630_CLKSEL_DSS1_MASK                       (0x3f << 0)
+#define OMAP3630_CLKSEL_DSS1_WIDTH                      6
 /* CM_SLEEPDEP_DSS specific bits */
@@ -623,7 +643,9 @@
 /* CM_CLKSEL_CAM */
 #define OMAP3430_CLKSEL_CAM_SHIFT                       0
 #define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
+#define OMAP3430_CLKSEL_CAM_WIDTH                       5
 #define OMAP3630_CLKSEL_CAM_MASK                        (0x3f << 0)
+#define OMAP3630_CLKSEL_CAM_WIDTH                       6
 /* CM_SLEEPDEP_CAM specific bits */
@@ -721,21 +743,30 @@
 /* CM_CLKSEL1_EMU */
 #define OMAP3430_DIV_DPLL4_SHIFT                        24
 #define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
+#define OMAP3430_DIV_DPLL4_WIDTH                        5
 #define OMAP3630_DIV_DPLL4_MASK                         (0x3f << 24)
+#define OMAP3630_DIV_DPLL4_WIDTH                        6
 #define OMAP3430_DIV_DPLL3_SHIFT                        16
 #define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
+#define OMAP3430_DIV_DPLL3_WIDTH                        5
 #define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11
 #define OMAP3430_CLKSEL_TRACECLK_MASK                   (0x7 << 11)
+#define OMAP3430_CLKSEL_TRACECLK_WIDTH                  3
 #define OMAP3430_CLKSEL_PCLK_SHIFT                      8
 #define OMAP3430_CLKSEL_PCLK_MASK                       (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLK_WIDTH                      3
 #define OMAP3430_CLKSEL_PCLKX2_SHIFT                    6
 #define OMAP3430_CLKSEL_PCLKX2_MASK                     (0x3 << 6)
+#define OMAP3430_CLKSEL_PCLKX2_WIDTH                    2
 #define OMAP3430_CLKSEL_ATCLK_SHIFT                     4
 #define OMAP3430_CLKSEL_ATCLK_MASK                      (0x3 << 4)
+#define OMAP3430_CLKSEL_ATCLK_WIDTH                     2
 #define OMAP3430_TRACE_MUX_CTRL_SHIFT                   2
 #define OMAP3430_TRACE_MUX_CTRL_MASK                    (0x3 << 2)
+#define OMAP3430_TRACE_MUX_CTRL_WIDTH                   2
 #define OMAP3430_MUX_CTRL_SHIFT                         0
 #define OMAP3430_MUX_CTRL_MASK                          (0x3 << 0)
+#define OMAP3430_MUX_CTRL_WIDTH                         2
 /* CM_CLKSTCTRL_EMU */
 #define OMAP3430_CLKTRCTRL_EMU_SHIFT                    0
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index f24e3f7a2bbc..93473f9a551c 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -1,7 +1,7 @@
 /*
 * OMAP2+ Clock Management prototypes
 *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -22,6 +22,12 @@
 */
 #define MAX_MODULE_READY_TIME           2000
+# ifndef __ASSEMBLER__
+extern void __iomem *cm_base;
+extern void __iomem *cm2_base;
+extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
+# endif
 /*
 * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
 * the PRCM to request that a module enter the inactive state in the
@@ -33,4 +39,26 @@
 */
 #define MAX_MODULE_DISABLE_TIME         5000
+# ifndef __ASSEMBLER__
+/**
+ * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
+ * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
+ * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
+ */
+struct cm_ll_data {
+        int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
+                                u8 *idlest_reg_id);
+        int (*wait_module_ready)(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
+};
+extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
+                               u8 *idlest_reg_id);
+extern int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
+extern int cm_register(struct cm_ll_data *cld);
+extern int cm_unregister(struct cm_ll_data *cld);
+# endif
 #endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
new file mode 100644
index 000000000000..db650690e9d0
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -0,0 +1,381 @@
+/*
+ * OMAP2xxx CM module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include "soc.h"
+#include "iomap.h"
+#include "common.h"
+#include "prm2xxx.h"
+#include "cm.h"
+#include "cm2xxx.h"
+#include "cm-regbits-24xx.h"
+#include "clockdomain.h"
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
+#define DPLL_AUTOIDLE_DISABLE                           0x0
+#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
+#define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
+#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
+/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
+#define EN_APLL_LOCKED                                  3
+static const u8 omap2xxx_cm_idlest_offs[] = {
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
+};
+/*
+ *
+ */
+static void _write_clktrctrl(u8 c, s16 module, u32 mask)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= ~mask;
+        v |= c << __ffs(mask);
+        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
+}
+bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= mask;
+        v >>= __ffs(mask);
+        return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+}
+void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+/*
+ * DPLL autoidle control
+ */
+static void _omap2xxx_set_dpll_autoidle(u8 m)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~OMAP24XX_AUTO_DPLL_MASK;
+        v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+void omap2xxx_cm_set_dpll_disable_autoidle(void)
+{
+        _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+}
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+{
+        _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+}
+/*
+ * APLL control
+ */
+static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~mask;
+        v |= m << __ffs(mask);
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+void omap2xxx_cm_set_apll54_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+void omap2xxx_cm_set_apll96_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+/* Enable an APLL if off */
+static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
+{
+        u32 v, m;
+        m = EN_APLL_LOCKED << enable_bit;
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        if (v & m)
+                return 0;   /* apll already enabled */
+        v |= m;
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
+        omap2xxx_cm_wait_module_ready(PLL_MOD, 1, status_bit);
+        /*
+         * REVISIT: Should we return an error code if
+         * omap2xxx_cm_wait_module_ready() fails?
+         */
+        return 0;
+}
+/* Stop APLL */
+static void _omap2xxx_apll_disable(u8 enable_bit)
+{
+        u32 v;
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        v &= ~(EN_APLL_LOCKED << enable_bit);
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
+}
+/* Enable an APLL if off */
+int omap2xxx_cm_apll54_enable(void)
+{
+        return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT,
+                                     OMAP24XX_ST_54M_APLL_SHIFT);
+}
+/* Enable an APLL if off */
+int omap2xxx_cm_apll96_enable(void)
+{
+        return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT,
+                                     OMAP24XX_ST_96M_APLL_SHIFT);
+}
+/* Stop APLL */
+void omap2xxx_cm_apll54_disable(void)
+{
+        _omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT);
+}
+/* Stop APLL */
+void omap2xxx_cm_apll96_disable(void)
+{
+        _omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT);
+}
+/**
+ * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
+ * @idlest_reg: CM_IDLEST* virtual address
+ * @prcm_inst: pointer to an s16 to return the PRCM instance offset
+ * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
+ *
+ * XXX This function is only needed until absolute register addresses are
+ * removed from the OMAP struct clk records.
+ */
+int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
+                                 u8 *idlest_reg_id)
+{
+        unsigned long offs;
+        u8 idlest_offs;
+        int i;
+        if (idlest_reg < cm_base || idlest_reg > (cm_base + 0x0fff))
+                return -EINVAL;
+        idlest_offs = (unsigned long)idlest_reg & 0xff;
+        for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
+                if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
+                        *idlest_reg_id = i + 1;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
+                return -EINVAL;
+        offs = idlest_reg - cm_base;
+        offs &= 0xff00;
+        *prcm_inst = offs;
+        return 0;
+}
+/*
+ *
+ */
+/**
+ * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * Wait for the PRCM to indicate that the module identified by
+ * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
+ * success or -EBUSY if the module doesn't enable in time.
+ */
+int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+{
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
+                return -EINVAL;
+        cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
+        mask = 1 << idlest_shift;
+        ena = mask;
+        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
+                            mask) == ena), MAX_MODULE_READY_TIME, i);
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+/* Clockdomain low-level functions */
+static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
+        omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                       clkdm->clktrctrl_mask);
+}
+static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                        clkdm->clktrctrl_mask);
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_del_autodeps(clkdm);
+}
+static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+        hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_add_autodeps(clkdm);
+                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap2xxx_clkdm_wakeup(clkdm);
+        }
+        return 0;
+}
+static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+        hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_del_autodeps(clkdm);
+                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap2xxx_clkdm_sleep(clkdm);
+        }
+        return 0;
+}
+struct clkdm_ops omap2_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_sleep            = omap2xxx_clkdm_sleep,
+        .clkdm_wakeup           = omap2xxx_clkdm_wakeup,
+        .clkdm_allow_idle       = omap2xxx_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap2xxx_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap2xxx_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap2xxx_clkdm_clk_disable,
+};
+/*
+ *
+ */
+static struct cm_ll_data omap2xxx_cm_ll_data = {
+        .split_idlest_reg       = &omap2xxx_cm_split_idlest_reg,
+        .wait_module_ready      = &omap2xxx_cm_wait_module_ready,
+};
+int __init omap2xxx_cm_init(void)
+{
+        if (!cpu_is_omap24xx())
+                return 0;
+        return cm_register(&omap2xxx_cm_ll_data);
+}
+static void __exit omap2xxx_cm_exit(void)
+{
+        if (!cpu_is_omap24xx())
+                return;
+        /* Should never happen */
+        WARN(cm_unregister(&omap2xxx_cm_ll_data),
+             "%s: cm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap2xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
new file mode 100644
index 000000000000..4cbb39b051d2
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -0,0 +1,70 @@
+/*
+ * OMAP2xxx Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
+#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
+#include "prcm-common.h"
+#include "cm2xxx_3xxx.h"
+#define OMAP2420_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+/* OMAP2-specific register offsets */
+#define OMAP24XX_CM_FCLKEN2                             0x0004
+#define OMAP24XX_CM_ICLKEN4                             0x001c
+#define OMAP24XX_CM_AUTOIDLE4                           0x003c
+#define OMAP24XX_CM_IDLEST4                             0x002c
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+#define OMAP24XX_CM_IDLEST_VAL                          0
+/* Clock management domain register get/set */
+#ifndef __ASSEMBLER__
+extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                         u8 idlest_shift);
+extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
+                                        s16 *prcm_inst, u8 *idlest_reg_id);
+extern int __init omap2xxx_cm_init(void);
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 57b2f3c2fbf3..bfbd16fe9151 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -16,28 +16,7 @@
 #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
 #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
-#include "prcm-common.h"
+#include "cm.h"
-#define OMAP2420_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
-#define OMAP2430_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
-#define OMAP34XX_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
-/*
- * OMAP3-specific global CM registers
- * Use cm_{read,write}_reg() with these registers.
- * These registers appear once per CM module.
- */
-#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
-#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
-#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 /*
 * Module specific CM register offsets from CM_BASE + domain offset
@@ -57,6 +36,7 @@
 #define CM_IDLEST                                       0x0020
 #define CM_IDLEST1                                      CM_IDLEST
 #define CM_IDLEST2                                      0x0024
+#define OMAP2430_CM_IDLEST3                             0x0028
 #define CM_AUTOIDLE                                     0x0030
 #define CM_AUTOIDLE1                                    CM_AUTOIDLE
 #define CM_AUTOIDLE2                                    0x0034
@@ -66,70 +46,60 @@
 #define CM_CLKSEL2                                      0x0044
 #define OMAP2_CM_CLKSTCTRL                              0x0048
-/* OMAP2-specific register offsets */
+#ifndef __ASSEMBLER__
-#define OMAP24XX_CM_FCLKEN2                             0x0004
-#define OMAP24XX_CM_ICLKEN4                             0x001c
-#define OMAP24XX_CM_AUTOIDLE4                           0x003c
-#define OMAP24XX_CM_IDLEST4                             0x002c
-#define OMAP2430_CM_IDLEST3                             0x0028
-/* OMAP3-specific register offsets */
-#define OMAP3430_CM_CLKEN_PLL                           0x0004
-#define OMAP3430ES2_CM_CLKEN2                           0x0004
-#define OMAP3430ES2_CM_FCLKEN3                          0x0008
-#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
-#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
-#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
-#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
-#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
-#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
-#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
-#define OMAP3430_CM_CLKSTST                             0x004c
-#define OMAP3430ES2_CM_CLKSEL4                          0x004c
-#define OMAP3430ES2_CM_CLKSEL5                          0x0050
-#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
-#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+#include <linux/io.h>
-/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(cm_base + module + idx);
+}
-#define OMAP24XX_CM_IDLEST_VAL                          0
+static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
-#define OMAP34XX_CM_IDLEST_VAL                          1
+{
+        __raw_writel(val, cm_base + module + idx);
+}
+/* Read-modify-write a register in a CM module. Caller must lock */
+static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
+                                            s16 idx)
+{
+        u32 v;
-/* Clock management domain register get/set */
+        v = omap2_cm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_cm_write_mod_reg(v, module, idx);
-#ifndef __ASSEMBLER__
+        return v;
+}
-extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
+/* Read a CM register, AND it, and shift the result down to bit 0 */
-extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
+static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+{
+        u32 v;
-extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+        v = omap2_cm_read_mod_reg(domain, idx);
-                                      u8 idlest_shift);
+        v &= mask;
-extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+        v >>= __ffs(mask);
-extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
-extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+        return v;
-extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+}
-extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+{
-extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+        return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
-extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+}
-extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
-extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
+extern int omap2xxx_cm_apll54_enable(void);
-extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+extern void omap2xxx_cm_apll54_disable(void);
-extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
+extern int omap2xxx_cm_apll96_enable(void);
-extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+extern void omap2xxx_cm_apll96_disable(void);
 #endif
@@ -138,6 +108,7 @@ extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
 /* CM_CLKSEL_GFX */
 #define OMAP_CLKSEL_GFX_SHIFT                           0
 #define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
+#define OMAP_CLKSEL_GFX_WIDTH                           3
 /* CM_ICLKEN_GFX */
 #define OMAP_EN_GFX_SHIFT                               0
@@ -146,11 +117,4 @@ extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
 /* CM_IDLEST_GFX */
 #define OMAP_ST_GFX_MASK                                (1 << 0)
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern void omap3_cm_save_context(void);
-extern void omap3_cm_restore_context(void);
-# endif
 #endif
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 13f56eafef03..058ce3c0873e 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -22,8 +22,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "clockdomain.h"
 #include "cm.h"
 #include "cm33xx.h"
 #include "cm-regbits-34xx.h"
@@ -311,3 +310,58 @@ void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
        v &= ~AM33XX_MODULEMODE_MASK;
        am33xx_cm_write_reg(v, inst, clkctrl_offs);
 }
+/*
+ * Clockdomain low-level functions
+ */
+static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return am33xx_clkdm_wakeup(clkdm);
+        return 0;
+}
+static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+        hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                am33xx_clkdm_sleep(clkdm);
+        return 0;
+}
+struct clkdm_ops am33xx_clkdm_operations = {
+        .clkdm_sleep            = am33xx_clkdm_sleep,
+        .clkdm_wakeup           = am33xx_clkdm_wakeup,
+        .clkdm_allow_idle       = am33xx_clkdm_allow_idle,
+        .clkdm_deny_idle        = am33xx_clkdm_deny_idle,
+        .clkdm_clk_enable       = am33xx_clkdm_clk_enable,
+        .clkdm_clk_disable      = am33xx_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 7f07ab02a5b3..c2086f2e86b6 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -1,8 +1,10 @@
 /*
- * OMAP2/3 CM module functions
+ * OMAP3xxx CM module functions
 *
 * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
 * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -12,8 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/io.h>
@@ -21,56 +21,16 @@
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
+#include "prm2xxx_3xxx.h"
 #include "cm.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
-#include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
+#include "clockdomain.h"
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
+static const u8 omap3xxx_cm_idlest_offs[] = {
-#define DPLL_AUTOIDLE_DISABLE                           0x0
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
-#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
-/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
-#define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
-#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
-static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
 };
-u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
-{
-        return __raw_readl(cm_base + module + idx);
-}
-void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __raw_writel(val, cm_base + module + idx);
-}
-/* Read-modify-write a register in a CM module. Caller must lock */
-u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-        v = omap2_cm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        omap2_cm_write_mod_reg(v, module, idx);
-        return v;
-}
-u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
 /*
 *
 */
@@ -85,33 +45,15 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
 }
-bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
 {
        u32 v;
-        bool ret = 0;
-        BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
        v &= mask;
        v >>= __ffs(mask);
-        if (cpu_is_omap24xx())
+        return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
-                ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
-        else
-                ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
-        return ret;
-}
-void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
-{
-        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
-}
-void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
-{
-        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
 }
 void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
@@ -135,109 +77,247 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
 }
 /*
- * DPLL autoidle control
+ *
 */
-static void _omap2xxx_set_dpll_autoidle(u8 m)
+/**
+ * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * Wait for the PRCM to indicate that the module identified by
+ * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
+ * success or -EBUSY if the module doesn't enable in time.
+ */
+int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 {
-        u32 v;
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
-        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
-        v &= ~OMAP24XX_AUTO_DPLL_MASK;
+                return -EINVAL;
-        v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
-        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
-}
-void omap2xxx_cm_set_dpll_disable_autoidle(void)
+        cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
-{
-        _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+        mask = 1 << idlest_shift;
+        ena = 0;
+        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
+                            mask) == ena), MAX_MODULE_READY_TIME, i);
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
-void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+/**
+ * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
+ * @idlest_reg: CM_IDLEST* virtual address
+ * @prcm_inst: pointer to an s16 to return the PRCM instance offset
+ * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
+ *
+ * XXX This function is only needed until absolute register addresses are
+ * removed from the OMAP struct clk records.
+ */
+int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
+                                 u8 *idlest_reg_id)
 {
-        _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+        unsigned long offs;
+        u8 idlest_offs;
+        int i;
+        if (idlest_reg < (cm_base + OMAP3430_IVA2_MOD) ||
+            idlest_reg > (cm_base + 0x1ffff))
+                return -EINVAL;
+        idlest_offs = (unsigned long)idlest_reg & 0xff;
+        for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
+                if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
+                        *idlest_reg_id = i + 1;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
+                return -EINVAL;
+        offs = idlest_reg - cm_base;
+        offs &= 0xff00;
+        *prcm_inst = offs;
+        return 0;
 }
-/*
+/* Clockdomain low-level operations */
- * APLL autoidle control
- */
-static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
+                                       struct clockdomain *clkdm2)
 {
-        u32 v;
+        omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                  clkdm1->pwrdm.ptr->prcm_offs,
+                                  OMAP3430_CM_SLEEPDEP);
+        return 0;
+}
-        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
-        v &= ~mask;
+                                       struct clockdomain *clkdm2)
-        v |= m << __ffs(mask);
+{
-        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+        omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                    clkdm1->pwrdm.ptr->prcm_offs,
+                                    OMAP3430_CM_SLEEPDEP);
+        return 0;
 }
-void omap2xxx_cm_set_apll54_disable_autoidle(void)
+static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+        return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
-                                    OMAP24XX_AUTO_54M_MASK);
+                                            OMAP3430_CM_SLEEPDEP,
+                                            (1 << clkdm2->dep_bit));
 }
-void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+        struct clkdm_dep *cd;
-                                    OMAP24XX_AUTO_54M_MASK);
+        u32 mask = 0;
+        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->sleepdep_usecount, 0);
+        }
+        omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                    OMAP3430_CM_SLEEPDEP);
+        return 0;
 }
-void omap2xxx_cm_set_apll96_disable_autoidle(void)
+static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
-                                    OMAP24XX_AUTO_96M_MASK);
+                                      clkdm->clktrctrl_mask);
+        return 0;
 }
-void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
 {
-        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
-                                    OMAP24XX_AUTO_96M_MASK);
+                                       clkdm->clktrctrl_mask);
+        return 0;
 }
-/*
+static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
- *
+{
- */
+        if (atomic_read(&clkdm->usecount) > 0)
+                _clkdm_add_autodeps(clkdm);
-/**
+        omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
- * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
+                                       clkdm->clktrctrl_mask);
- * @prcm_mod: PRCM module offset
+}
- * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
- * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
- *
- * XXX document
- */
-int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 {
-        int ena = 0, i = 0;
+        omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
-        u8 cm_idlest_reg;
+                                        clkdm->clktrctrl_mask);
-        u32 mask;
-        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
+        if (atomic_read(&clkdm->usecount) > 0)
-                return -EINVAL;
+                _clkdm_del_autodeps(clkdm);
+}
-        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
+static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
-        mask = 1 << idlest_shift;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
-        if (cpu_is_omap24xx())
+        /*
-                ena = mask;
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
-        else if (cpu_is_omap34xx())
+         * more details on the unpleasant problem this is working
-                ena = 0;
+         * around
-        else
+         */
-                BUG();
+        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
+            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+                omap3xxx_clkdm_wakeup(clkdm);
+                return 0;
+        }
+        hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_add_autodeps(clkdm);
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap3xxx_clkdm_wakeup(clkdm);
+        }
+        return 0;
+}
-        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
+static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
-                          MAX_MODULE_READY_TIME, i);
+{
+        bool hwsup = false;
-        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+                return 0;
+        }
+        hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+                _clkdm_del_autodeps(clkdm);
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap3xxx_clkdm_sleep(clkdm);
+        }
+        return 0;
 }
+struct clkdm_ops omap3_clkdm_operations = {
+        .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
+        .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
+        .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
+        .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+        .clkdm_add_sleepdep     = omap3xxx_clkdm_add_sleepdep,
+        .clkdm_del_sleepdep     = omap3xxx_clkdm_del_sleepdep,
+        .clkdm_read_sleepdep    = omap3xxx_clkdm_read_sleepdep,
+        .clkdm_clear_all_sleepdeps      = omap3xxx_clkdm_clear_all_sleepdeps,
+        .clkdm_sleep            = omap3xxx_clkdm_sleep,
+        .clkdm_wakeup           = omap3xxx_clkdm_wakeup,
+        .clkdm_allow_idle       = omap3xxx_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap3xxx_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
+};
 /*
 * Context save/restore code - OMAP3 only
 */
-#ifdef CONFIG_ARCH_OMAP3
 struct omap3_cm_regs {
        u32 iva2_cm_clksel1;
        u32 iva2_cm_clksel2;
@@ -555,4 +635,31 @@ void omap3_cm_restore_context(void)
        omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
                               OMAP3_CM_CLKOUT_CTRL_OFFSET);
 }
-#endif
+/*
+ *
+ */
+static struct cm_ll_data omap3xxx_cm_ll_data = {
+        .split_idlest_reg       = &omap3xxx_cm_split_idlest_reg,
+        .wait_module_ready      = &omap3xxx_cm_wait_module_ready,
+};
+int __init omap3xxx_cm_init(void)
+{
+        if (!cpu_is_omap34xx())
+                return 0;
+        return cm_register(&omap3xxx_cm_ll_data);
+}
+static void __exit omap3xxx_cm_exit(void)
+{
+        if (!cpu_is_omap34xx())
+                return;
+        /* Should never happen */
+        WARN(cm_unregister(&omap3xxx_cm_ll_data),
+             "%s: cm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap3xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
new file mode 100644
index 000000000000..e8e146f4a43f
--- /dev/null
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -0,0 +1,91 @@
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
+#define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
+#include "prcm-common.h"
+#include "cm2xxx_3xxx.h"
+#define OMAP34XX_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+/*
+ * OMAP3-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
+#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+/* OMAP3-specific register offsets */
+#define OMAP3430_CM_CLKEN_PLL                           0x0004
+#define OMAP3430ES2_CM_CLKEN2                           0x0004
+#define OMAP3430ES2_CM_FCLKEN3                          0x0008
+#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST                             0x004c
+#define OMAP3430ES2_CM_CLKSEL4                          0x004c
+#define OMAP3430ES2_CM_CLKSEL5                          0x0050
+#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
+#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+#define OMAP34XX_CM_IDLEST_VAL                          1
+#ifndef __ASSEMBLER__
+extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                         u8 idlest_shift);
+extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
+                                        s16 *prcm_inst, u8 *idlest_reg_id);
+extern void omap3_cm_save_context(void);
+extern void omap3_cm_restore_context(void);
+extern int __init omap3xxx_cm_init(void);
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
new file mode 100644
index 000000000000..40b3b5a84458
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -0,0 +1,140 @@
+/*
+ * OMAP2+ common Clock Management (CM) IP block functions
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This code should eventually be moved to a CM driver.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include "cm2xxx.h"
+#include "cm3xxx.h"
+#include "cm44xx.h"
+#include "common.h"
+/*
+ * cm_ll_data: function pointers to SoC-specific implementations of
+ * common CM functions
+ */
+static struct cm_ll_data null_cm_ll_data;
+static struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
+/* cm_base: base virtual address of the CM IP block */
+void __iomem *cm_base;
+/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
+void __iomem *cm2_base;
+/**
+ * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
+ * @cm: CM base virtual address
+ * @cm2: CM2 base virtual address (if present on the booted SoC)
+ *
+ * XXX Will be replaced when the PRM/CM drivers are completed.
+ */
+void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
+{
+        cm_base = cm;
+        cm2_base = cm2;
+}
+/**
+ * cm_split_idlest_reg - split CM_IDLEST reg addr into its components
+ * @idlest_reg: CM_IDLEST* virtual address
+ * @prcm_inst: pointer to an s16 to return the PRCM instance offset
+ * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
+ *
+ * Given an absolute CM_IDLEST register address @idlest_reg, passes
+ * the PRCM instance offset and IDLEST register ID back to the caller
+ * via the @prcm_inst and @idlest_reg_id.  Returns -EINVAL upon error,
+ * or 0 upon success.  XXX This function is only needed until absolute
+ * register addresses are removed from the OMAP struct clk records.
+ */
+int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
+                        u8 *idlest_reg_id)
+{
+        if (!cm_ll_data->split_idlest_reg) {
+                WARN_ONCE(1, "cm: %s: no low-level function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst,
+                                           idlest_reg_id);
+}
+/**
+ * cm_wait_module_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * Wait for the PRCM to indicate that the module identified by
+ * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
+ * success, -EBUSY if the module doesn't enable in time, or -EINVAL if
+ * no per-SoC wait_module_ready() function pointer has been registered
+ * or if the idlest register is unknown on the SoC.
+ */
+int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+{
+        if (!cm_ll_data->wait_module_ready) {
+                WARN_ONCE(1, "cm: %s: no low-level function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return cm_ll_data->wait_module_ready(prcm_mod, idlest_id, idlest_shift);
+}
+/**
+ * cm_register - register per-SoC low-level data with the CM
+ * @cld: low-level per-SoC OMAP CM data & function pointers to register
+ *
+ * Register per-SoC low-level OMAP CM data and function pointers with
+ * the OMAP CM common interface.  The caller must keep the data
+ * pointed to by @cld valid until it calls cm_unregister() and
+ * it returns successfully.  Returns 0 upon success, -EINVAL if @cld
+ * is NULL, or -EEXIST if cm_register() has already been called
+ * without an intervening cm_unregister().
+ */
+int cm_register(struct cm_ll_data *cld)
+{
+        if (!cld)
+                return -EINVAL;
+        if (cm_ll_data != &null_cm_ll_data)
+                return -EEXIST;
+        cm_ll_data = cld;
+        return 0;
+}
+/**
+ * cm_unregister - unregister per-SoC low-level data & function pointers
+ * @cld: low-level per-SoC OMAP CM data & function pointers to unregister
+ *
+ * Unregister per-SoC low-level OMAP CM data and function pointers
+ * that were previously registered with cm_register().  The
+ * caller may not destroy any of the data pointed to by @cld until
+ * this function returns successfully.  Returns 0 upon success, or
+ * -EINVAL if @cld is NULL or if @cld does not match the struct
+ * cm_ll_data * previously registered by cm_register().
+ */
+int cm_unregister(struct cm_ll_data *cld)
+{
+        if (!cld || cm_ll_data != cld)
+                return -EINVAL;
+        cm_ll_data = &null_cm_ll_data;
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 1894015ff04b..7f9a464f01e9 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -2,8 +2,9 @@
 * OMAP4 CM instance functions
 *
 * Copyright (C) 2009 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
 * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -22,6 +23,7 @@
 #include "iomap.h"
 #include "common.h"
+#include "clockdomain.h"
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
@@ -343,3 +345,141 @@ void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
        v &= ~OMAP4430_MODULEMODE_MASK;
        omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
 }
+/*
+ * Clockdomain low-level functions
+ */
+static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
+                                       clkdm1->prcm_partition,
+                                       clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                       OMAP4_CM_STATICDEP);
+        return 0;
+}
+static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
+                                         clkdm1->prcm_partition,
+                                         clkdm1->cm_inst, clkdm1->clkdm_offs +
+                                         OMAP4_CM_STATICDEP);
+        return 0;
+}
+static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
+                                        struct clockdomain *clkdm2)
+{
+        return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
+                                               clkdm1->cm_inst,
+                                               clkdm1->clkdm_offs +
+                                               OMAP4_CM_STATICDEP,
+                                               (1 << clkdm2->dep_bit));
+}
+static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+        if (!clkdm->prcm_partition)
+                return 0;
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!cd->clkdm)
+                        continue; /* only happens if data is erroneous */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
+        }
+        omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
+                                         clkdm->cm_inst, clkdm->clkdm_offs +
+                                         OMAP4_CM_STATICDEP);
+        return 0;
+}
+static int omap4_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+}
+static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                omap4_clkdm_wakeup(clkdm);
+        else
+                omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
+                                                 clkdm->cm_inst,
+                                                 clkdm->clkdm_offs);
+}
+static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return omap4_clkdm_wakeup(clkdm);
+        return 0;
+}
+static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+        if (!clkdm->prcm_partition)
+                return 0;
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap4_clkdm_allow_idle(clkdm);
+                return 0;
+        }
+        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                omap4_clkdm_sleep(clkdm);
+        return 0;
+}
+struct clkdm_ops omap4_clkdm_operations = {
+        .clkdm_add_wkdep        = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_wkdep        = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_wkdep       = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_add_sleepdep     = omap4_clkdm_add_wkup_sleep_dep,
+        .clkdm_del_sleepdep     = omap4_clkdm_del_wkup_sleep_dep,
+        .clkdm_read_sleepdep    = omap4_clkdm_read_wkup_sleep_dep,
+        .clkdm_clear_all_sleepdeps      = omap4_clkdm_clear_all_wkup_sleep_deps,
+        .clkdm_sleep            = omap4_clkdm_sleep,
+        .clkdm_wakeup           = omap4_clkdm_wakeup,
+        .clkdm_allow_idle       = omap4_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap4_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index d69fdefef985..bd7bab889745 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -38,4 +38,6 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
 extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
                                           u32 mask);
+extern void omap_cm_base_init(void);
 #endif
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 84551f205e46..d246efd9f734 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -25,7 +25,6 @@
 #include <linux/spi/ads7846.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include "common.h"
 #include "common-board-devices.h"
@@ -102,48 +101,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 {
 }
 #endif
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data;
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-                                 int nr_parts)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-        if (nandcs > GPMC_CS_NUM) {
-                pr_info("NAND: Unable to find configuration in GPMC\n");
-                return;
-        }
-        if (nandcs < GPMC_CS_NUM) {
-                nand_data.cs = nandcs;
-                nand_data.parts = parts;
-                nand_data.nr_parts = nr_parts;
-                nand_data.devsize = options;
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-#else
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-                                 int nr_parts)
-{
-}
-#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index a0b4a42836ab..72bb41b3fd25 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,6 +10,5 @@ struct ads7846_platform_data;
 void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
                       struct ads7846_platform_data *board_pdata);
-void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
 #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 17950c6e130b..5c2fd4863b2b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -14,189 +14,26 @@
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/clk.h>
+#include <linux/platform_data/dsp-omap.h>
-#include <linux/io.h>
-#include <plat/clock.h>
+#include <plat/vram.h>
-#include "soc.h"
-#include "iomap.h"
 #include "common.h"
-#include "sdrc.h"
+#include "omap-secure.h"
-#include "control.h"
-/* Global address base setup code */
-static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
-{
-        omap2_set_globals_tap(omap2_globals);
-        omap2_set_globals_sdrc(omap2_globals);
-        omap2_set_globals_control(omap2_globals);
-        omap2_set_globals_prcm(omap2_globals);
-}
-#if defined(CONFIG_SOC_OMAP2420)
-static struct omap_globals omap242x_globals = {
-        .class  = OMAP242X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
-        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
-        .sms    = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
-};
-void __init omap2_set_globals_242x(void)
-{
-        __omap2_set_globals(&omap242x_globals);
-}
-void __init omap242x_map_io(void)
-{
-        omap242x_map_common_io();
-}
-#endif
-#if defined(CONFIG_SOC_OMAP2430)
-static struct omap_globals omap243x_globals = {
-        .class  = OMAP243X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
-        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
-        .sms    = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
-};
-void __init omap2_set_globals_243x(void)
-{
-        __omap2_set_globals(&omap243x_globals);
-}
-void __init omap243x_map_io(void)
-{
-        omap243x_map_common_io();
-}
-#endif
-#if defined(CONFIG_ARCH_OMAP3)
-static struct omap_globals omap3_globals = {
-        .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
-        .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
-        .sms    = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
-};
-void __init omap2_set_globals_3xxx(void)
-{
-        __omap2_set_globals(&omap3_globals);
-}
-void __init omap3_map_io(void)
-{
-        omap34xx_map_common_io();
-}
 /*
- * Adjust TAP register base such that omap3_check_revision accesses the correct
+ * Stub function for OMAP2 so that common files
- * TI81XX register for checking device ID (it adds 0x204 to tap base while
+ * continue to build when custom builds are used
- * TI81XX DEVICE ID register is at offset 0x600 from control base).
 */
-#define TI81XX_TAP_BASE         (TI81XX_CTRL_BASE + \
+int __weak omap_secure_ram_reserve_memblock(void)
-                                TI81XX_CONTROL_DEVICE_ID - 0x204)
-static struct omap_globals ti81xx_globals = {
-        .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
-};
-void __init omap2_set_globals_ti81xx(void)
-{
-        __omap2_set_globals(&ti81xx_globals);
-}
-void __init ti81xx_map_io(void)
-{
-        omapti81xx_map_common_io();
-}
-#endif
-#if defined(CONFIG_SOC_AM33XX)
-#define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + \
-                                TI81XX_CONTROL_DEVICE_ID - 0x204)
-static struct omap_globals am33xx_globals = {
-        .class  = AM335X_CLASS,
-        .tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
-        .ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
-        .prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
-        .cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
-};
-void __init omap2_set_globals_am33xx(void)
-{
-        __omap2_set_globals(&am33xx_globals);
-}
-void __init am33xx_map_io(void)
-{
-        omapam33xx_map_common_io();
-}
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-static struct omap_globals omap4_globals = {
-        .class  = OMAP443X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-        .ctrl_pad       = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
-        .prcm_mpu       = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
-};
-void __init omap2_set_globals_443x(void)
-{
-        __omap2_set_globals(&omap4_globals);
-}
-void __init omap4_map_io(void)
-{
-        omap44xx_map_common_io();
-}
-#endif
-#if defined(CONFIG_SOC_OMAP5)
-static struct omap_globals omap5_globals = {
-        .class  = OMAP54XX_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-        .ctrl_pad       = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
-        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
-        .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
-};
-void __init omap2_set_globals_5xxx(void)
 {
-        omap2_set_globals_tap(&omap5_globals);
+        return 0;
-        omap2_set_globals_control(&omap5_globals);
-        omap2_set_globals_prcm(&omap5_globals);
 }
-void __init omap5_map_io(void)
+void __init omap_reserve(void)
 {
-        omap5_map_common_io();
+        omap_vram_reserve_sdram_memblock();
+        omap_dsp_reserve_sdram_memblock();
+        omap_secure_ram_reserve_memblock();
+        omap_barrier_reserve_memblock();
 }
-#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7045e4d61ac3..948bcaa82eb6 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -28,63 +28,18 @@
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/i2c.h>
 #include <linux/i2c/twl.h>
+#include <linux/i2c-omap.h>
 #include <asm/proc-fns.h>
-#include <plat/cpu.h>
+#include "i2c.h"
-#include <plat/serial.h>
+#include "serial.h"
-#include <plat/common.h>
-#define OMAP_INTC_START         NR_IRQS
+#include "usb.h"
-#ifdef CONFIG_SOC_OMAP2420
-extern void omap242x_map_common_io(void);
-#else
-static inline void omap242x_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_SOC_OMAP2430
-extern void omap243x_map_common_io(void);
-#else
-static inline void omap243x_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-extern void omap34xx_map_common_io(void);
-#else
-static inline void omap34xx_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_SOC_TI81XX
-extern void omapti81xx_map_common_io(void);
-#else
-static inline void omapti81xx_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_SOC_AM33XX
+#define OMAP_INTC_START         NR_IRQS
-extern void omapam33xx_map_common_io(void);
-#else
-static inline void omapam33xx_map_common_io(void)
-{
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-extern void omap44xx_map_common_io(void);
-#else
-static inline void omap44xx_map_common_io(void)
-{
-}
-#endif
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
 int omap2_pm_init(void);
@@ -122,19 +77,12 @@ static inline int omap_mux_late_init(void)
 }
 #endif
-#ifdef CONFIG_SOC_OMAP5
-extern void omap5_map_common_io(void);
-#else
-static inline void omap5_map_common_io(void)
-{
-}
-#endif
 extern void omap2_init_common_infrastructure(void);
 extern struct sys_timer omap2_timer;
 extern struct sys_timer omap3_timer;
 extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap3_gp_timer;
 extern struct sys_timer omap3_am33xx_timer;
 extern struct sys_timer omap4_timer;
 extern struct sys_timer omap5_timer;
@@ -162,52 +110,43 @@ void am35xx_init_late(void);
 void ti81xx_init_late(void);
 void omap4430_init_late(void);
 int omap2_common_pm_late_init(void);
-void omap_prcm_restart(char, const char *);
-/*
+#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
- * IO bases for various OMAP processors
+void omap2xxx_restart(char mode, const char *cmd);
- * Except the tap base, rest all the io bases
+#else
- * listed are physical addresses.
+static inline void omap2xxx_restart(char mode, const char *cmd)
- */
+{
-struct omap_globals {
+}
-        u32             class;          /* OMAP class to detect */
+#endif
-        void __iomem    *tap;           /* Control module ID code */
-        void __iomem    *sdrc;           /* SDRAM Controller */
+#ifdef CONFIG_ARCH_OMAP3
-        void __iomem    *sms;            /* SDRAM Memory Scheduler */
+void omap3xxx_restart(char mode, const char *cmd);
-        void __iomem    *ctrl;           /* System Control Module */
+#else
-        void __iomem    *ctrl_pad;      /* PAD Control Module */
+static inline void omap3xxx_restart(char mode, const char *cmd)
-        void __iomem    *prm;            /* Power and Reset Management */
+{
-        void __iomem    *cm;             /* Clock Management */
+}
-        void __iomem    *cm2;
+#endif
-        void __iomem    *prcm_mpu;
-};
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+void omap44xx_restart(char mode, const char *cmd);
-void omap2_set_globals_242x(void);
-void omap2_set_globals_243x(void);
-void omap2_set_globals_3xxx(void);
-void omap2_set_globals_443x(void);
-void omap2_set_globals_5xxx(void);
-void omap2_set_globals_ti81xx(void);
-void omap2_set_globals_am33xx(void);
-/* These get called from omap2_set_globals_xxxx(), do not call these */
-void omap2_set_globals_tap(struct omap_globals *);
-#if defined(CONFIG_SOC_HAS_OMAP2_SDRC)
-void omap2_set_globals_sdrc(struct omap_globals *);
 #else
-static inline void omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
+static inline void omap44xx_restart(char mode, const char *cmd)
-{ }
+{
+}
 #endif
-void omap2_set_globals_control(struct omap_globals *);
-void omap2_set_globals_prcm(struct omap_globals *);
+/* This gets called from mach-omap2/io.c, do not call this */
+void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
-void omap242x_map_io(void);
-void omap243x_map_io(void);
+void __init omap242x_map_io(void);
-void omap3_map_io(void);
+void __init omap243x_map_io(void);
-void am33xx_map_io(void);
+void __init omap3_map_io(void);
-void omap4_map_io(void);
+void __init am33xx_map_io(void);
-void omap5_map_io(void);
+void __init omap4_map_io(void);
-void ti81xx_map_io(void);
+void __init omap5_map_io(void);
+void __init ti81xx_map_io(void);
+/* omap_barriers_init() is OMAP4 only */
 void omap_barriers_init(void);
 /**
@@ -275,6 +214,9 @@ static inline void __iomem *omap4_get_scu_base(void)
 #endif
 extern void __init gic_init_irq(void);
+extern void gic_dist_disable(void);
+extern bool gic_dist_disabled(void);
+extern void gic_timer_retrigger(void);
 extern void omap_smc1(u32 fn, u32 arg);
 extern void __iomem *omap4_get_sar_ram_base(void);
 extern void omap_do_wfi(void);
@@ -282,6 +224,7 @@ extern void omap_do_wfi(void);
 #ifdef CONFIG_SMP
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
+extern void omap_secondary_startup_4460(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
@@ -338,6 +281,10 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                      struct omap_sdrc_params *sdrc_cs1);
 struct omap2_hsmmc_info;
 extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
+extern void omap_reserve(void);
+struct omap_hwmod;
+extern int omap_dss_reset(struct omap_hwmod *);
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index d1ff8399a222..2adb2683f074 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3 System Control Module register access
 *
- * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007, 2012 Texas Instruments, Inc.
 * Copyright (C) 2007 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -15,15 +15,13 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <plat/sdrc.h>
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
-#include "prm2xxx_3xxx.h"
+#include "prm3xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
@@ -149,13 +147,11 @@ static struct omap3_control_regs control_context;
 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 #define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
-void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
+void __init omap2_set_globals_control(void __iomem *ctrl,
+                                      void __iomem *ctrl_pad)
 {
-        if (omap2_globals->ctrl)
+        omap2_ctrl_base = ctrl;
-                omap2_ctrl_base = omap2_globals->ctrl;
+        omap4_ctrl_pad_base = ctrl_pad;
-        if (omap2_globals->ctrl_pad)
-                omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
 }
 void __iomem *omap_ctrl_base_get(void)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a89e8256fd0e..3d944d3263d2 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -201,6 +201,7 @@
 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO      0x249
 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50        0x254
 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100       0x257
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV     0x25A
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
@@ -414,6 +415,8 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
+extern void omap2_set_globals_control(void __iomem *ctrl,
+                                      void __iomem *ctrl_pad);
 #else
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index bc2756959be5..bca7a8885703 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -27,7 +27,6 @@
 #include <linux/export.h>
 #include <linux/cpu_pm.h>
-#include <plat/prcm.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c72b5a727720..4abb8b5e9bc0 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -24,10 +24,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
+#include <linux/omap-dma.h>
 #include "iomap.h"
-#include <plat/dma.h>
+#include "omap_hwmod.h"
-#include <plat/omap_hwmod.h>
+#include "omap_device.h"
-#include <plat/omap_device.h>
 #include "omap4-keypad.h"
 #include "soc.h"
@@ -35,6 +36,7 @@
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
+#include "dma.h"
 #define L3_MODULES_MAX_LEN 12
 #define L3_MODULES 3
@@ -127,7 +129,7 @@ static struct platform_device omap2cam_device = {
 #if defined(CONFIG_IOMMU_API)
-#include <plat/iommu.h>
+#include <linux/platform_data/iommu-omap.h>
 static struct resource omap3isp_resources[] = {
        {
@@ -201,6 +203,16 @@ static struct resource omap3isp_resources[] = {
                .flags          = IORESOURCE_MEM,
        },
        {
+                .start          = OMAP343X_CTRL_BASE + OMAP343X_CONTROL_CSIRXFE,
+                .end            = OMAP343X_CTRL_BASE + OMAP343X_CONTROL_CSIRXFE + 3,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP343X_CTRL_BASE + OMAP3630_CONTROL_CAMERA_PHY_CTRL,
+                .end            = OMAP343X_CTRL_BASE + OMAP3630_CONTROL_CAMERA_PHY_CTRL + 3,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
                .start          = 24 + OMAP_INTC_START,
                .flags          = IORESOURCE_IRQ,
        }
@@ -723,29 +735,3 @@ static int __init omap2_init_devices(void)
        return 0;
 }
 arch_initcall(omap2_init_devices);
-#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
-static int __init omap_init_wdt(void)
-{
-        int id = -1;
-        struct platform_device *pdev;
-        struct omap_hwmod *oh;
-        char *oh_name = "wd_timer2";
-        char *dev_name = "omap_wdt";
-        if (!cpu_class_is_omap2() || of_have_populated_dt())
-                return 0;
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                pr_err("Could not look up wd_timer%d hwmod\n", id);
-                return -EINVAL;
-        }
-        pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
-        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
-                                dev_name, oh->name);
-        return 0;
-}
-subsys_initcall(omap_init_wdt);
-#endif
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 1011995f150a..38ba58c97628 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -25,15 +25,17 @@
 #include <linux/delay.h>
 #include <video/omapdss.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/omap_device.h>
+#include "omap_device.h"
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
 #include "common.h"
+#include "soc.h"
 #include "iomap.h"
 #include "mux.h"
 #include "control.h"
 #include "display.h"
+#include "prm.h"
 #define DISPC_CONTROL           0x0040
 #define DISPC_CONTROL2          0x0238
@@ -284,6 +286,35 @@ err:
        return ERR_PTR(r);
 }
+static enum omapdss_version __init omap_display_get_version(void)
+{
+        if (cpu_is_omap24xx())
+                return OMAPDSS_VER_OMAP24xx;
+        else if (cpu_is_omap3630())
+                return OMAPDSS_VER_OMAP3630;
+        else if (cpu_is_omap34xx()) {
+                if (soc_is_am35xx()) {
+                        return OMAPDSS_VER_AM35xx;
+                } else {
+                        if (omap_rev() < OMAP3430_REV_ES3_0)
+                                return OMAPDSS_VER_OMAP34xx_ES1;
+                        else
+                                return OMAPDSS_VER_OMAP34xx_ES3;
+                }
+        } else if (omap_rev() == OMAP4430_REV_ES1_0)
+                return OMAPDSS_VER_OMAP4430_ES1;
+        else if (omap_rev() == OMAP4430_REV_ES2_0 ||
+                        omap_rev() == OMAP4430_REV_ES2_1 ||
+                        omap_rev() == OMAP4430_REV_ES2_2)
+                return OMAPDSS_VER_OMAP4430_ES2;
+        else if (cpu_is_omap44xx())
+                return OMAPDSS_VER_OMAP4;
+        else if (soc_is_omap54xx())
+                return OMAPDSS_VER_OMAP5;
+        else
+                return OMAPDSS_VER_UNKNOWN;
+}
 int __init omap_display_init(struct omap_dss_board_info *board_data)
 {
        int r = 0;
@@ -291,9 +322,18 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
        int i, oh_count;
        const struct omap_dss_hwmod_data *curr_dss_hwmod;
        struct platform_device *dss_pdev;
+        enum omapdss_version ver;
        /* create omapdss device */
+        ver = omap_display_get_version();
+        if (ver == OMAPDSS_VER_UNKNOWN) {
+                pr_err("DSS not supported on this SoC\n");
+                return -ENODEV;
+        }
+        board_data->version = ver;
        board_data->dsi_enable_pads = omap_dsi_enable_pads;
        board_data->dsi_disable_pads = omap_dsi_disable_pads;
        board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
@@ -473,7 +513,6 @@ static void dispc_disable_outputs(void)
        }
 }
-#define MAX_MODULE_SOFTRESET_WAIT       10000
 int omap_dss_reset(struct omap_hwmod *oh)
 {
        struct omap_hwmod_opt_clk *oc;
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index ff75abe60af2..612b98249873 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -28,9 +28,11 @@
 #include <linux/init.h>
 #include <linux/device.h>
-#include <plat/omap_hwmod.h>
+#include <linux/omap-dma.h>
-#include <plat/omap_device.h>
-#include <plat/dma.h>
+#include "soc.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
 #define OMAP2_DMA_STRIDE        0x60
@@ -274,6 +276,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
                return -ENOMEM;
        }
+        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                d->dev_caps |= HS_CHANNELS_RESERVED;
        /* Check the capabilities register for descriptor loading feature */
        if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
                dma_common_ch_end = CCDN;
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
new file mode 100644
index 000000000000..eba80dbc5218
--- /dev/null
+++ b/arch/arm/mach-omap2/dma.h
@@ -0,0 +1,131 @@
+/*
+ *  OMAP2PLUS DMA channel definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __OMAP2PLUS_DMA_CHANNEL_H
+#define __OMAP2PLUS_DMA_CHANNEL_H
+/* DMA channels for 24xx */
+#define OMAP24XX_DMA_NO_DEVICE          0
+#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
+#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
+#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
+#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
+#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
+#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
+#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
+#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
+#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
+#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
+#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
+#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
+#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
+#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
+#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
+#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
+#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
+#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
+#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
+#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
+#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
+#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
+#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
+#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
+#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
+#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
+#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
+#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
+#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
+#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
+#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
+#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
+#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
+#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
+#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
+#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
+#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
+#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
+#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
+#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
+#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
+#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
+#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
+#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
+#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
+#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
+#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
+#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
+#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
+#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
+#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
+#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
+#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
+/* Only for AM35xx */
+#define AM35XX_DMA_UART4_TX             54
+#define AM35XX_DMA_UART4_RX             55
+#endif /* __OMAP2PLUS_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 814e1808e158..fafb28c0dcbc 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -28,9 +28,8 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
-#include <plat/clock.h>
 #include "soc.h"
+#include "clockdomain.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
@@ -44,7 +43,7 @@
 /* Private functions */
 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
-static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
+static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
 {
        const struct dpll_data *dd;
        u32 v;
@@ -58,7 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 }
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
-static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
+static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
 {
        const struct dpll_data *dd;
        int i = 0;
@@ -66,7 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
        const char *clk_name;
        dd = clk->dpll_data;
-        clk_name = __clk_get_name(clk);
+        clk_name = __clk_get_name(clk->hw.clk);
        state <<= __ffs(dd->idlest_mask);
@@ -90,7 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 }
 /* From 3430 TRM ES2 4.7.6.2 */
-static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
+static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
 {
        unsigned long fint;
        u16 f = 0;
@@ -135,14 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
 * locked successfully, return 0; if the DPLL did not lock in the time
 * allotted, or DPLL3 was passed in, return -EINVAL.
 */
-static int _omap3_noncore_dpll_lock(struct clk *clk)
+static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
 {
        const struct dpll_data *dd;
        u8 ai;
        u8 state = 1;
        int r = 0;
-        pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
+        pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
        dd = clk->dpll_data;
        state <<= __ffs(dd->idlest_mask);
@@ -180,7 +179,7 @@ done:
 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
 * return -EINVAL.
 */
-static int _omap3_noncore_dpll_bypass(struct clk *clk)
+static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
 {
        int r;
        u8 ai;
@@ -189,7 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
                return -EINVAL;
        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-                 __clk_get_name(clk));
+                 __clk_get_name(clk->hw.clk));
        ai = omap3_dpll_autoidle_read(clk);
@@ -212,14 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
 * code.  If DPLL3 was passed in, or the DPLL does not support
 * low-power stop, return -EINVAL; otherwise, return 0.
 */
-static int _omap3_noncore_dpll_stop(struct clk *clk)
+static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
 {
        u8 ai;
        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
                return -EINVAL;
-        pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
+        pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
        ai = omap3_dpll_autoidle_read(clk);
@@ -243,11 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
 * XXX This code is not needed for 3430/AM35xx; can it be optimized
 * out in non-multi-OMAP builds for those chips?
 */
-static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
+static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
 {
        unsigned long fint, clkinp; /* watch out for overflow */
-        clkinp = __clk_get_rate(__clk_get_parent(clk));
+        clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
        fint = (clkinp / n) * m;
        if (fint < 1000000000)
@@ -268,12 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 * XXX This code is not needed for 3430/AM35xx; can it be optimized
 * out in non-multi-OMAP builds for those chips?
 */
-static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
+static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
 {
        unsigned long clkinp, sd; /* watch out for overflow */
        int mod1, mod2;
-        clkinp = __clk_get_rate(__clk_get_parent(clk));
+        clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
        /*
         * target sigma-delta to near 250MHz
@@ -300,7 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 * lock..  Returns -EINVAL upon error, or 0 upon success.
 */
-static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
+                                      u16 freqsel)
 {
        struct dpll_data *dd = clk->dpll_data;
        u8 dco, sd_div;
@@ -357,8 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 *
 * Recalculate and propagate the DPLL rate.
 */
-unsigned long omap3_dpll_recalc(struct clk *clk)
+unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        return omap2_get_dpll_rate(clk);
 }
@@ -378,8 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk)
 * support low-power stop, or if the DPLL took too long to enter
 * bypass or lock, return -EINVAL; otherwise, return 0.
 */
-int omap3_noncore_dpll_enable(struct clk *clk)
+int omap3_noncore_dpll_enable(struct clk_hw *hw)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        int r;
        struct dpll_data *dd;
        struct clk *parent;
@@ -388,22 +391,26 @@ int omap3_noncore_dpll_enable(struct clk *clk)
        if (!dd)
                return -EINVAL;
-        parent = __clk_get_parent(clk);
+        if (clk->clkdm) {
+                r = clkdm_clk_enable(clk->clkdm, hw->clk);
+                if (r) {
+                        WARN(1,
+                             "%s: could not enable %s's clockdomain %s: %d\n",
+                             __func__, __clk_get_name(hw->clk),
+                             clk->clkdm->name, r);
+                        return r;
+                }
+        }
-        if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+        parent = __clk_get_parent(hw->clk);
+        if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
                WARN_ON(parent != dd->clk_bypass);
                r = _omap3_noncore_dpll_bypass(clk);
        } else {
                WARN_ON(parent != dd->clk_ref);
                r = _omap3_noncore_dpll_lock(clk);
        }
-        /*
-         *FIXME: this is dubious - if clk->rate has changed, what about
-         * propagating?
-         */
-        if (!r)
-                clk->rate = (clk->recalc) ? clk->recalc(clk) :
-                        omap2_get_dpll_rate(clk);
        return r;
 }
@@ -415,9 +422,13 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 * Instructs a non-CORE DPLL to enter low-power stop.  This function is
 * intended for use in struct clkops.  No return value.
 */
-void omap3_noncore_dpll_disable(struct clk *clk)
+void omap3_noncore_dpll_disable(struct clk_hw *hw)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        _omap3_noncore_dpll_stop(clk);
+        if (clk->clkdm)
+                clkdm_clk_disable(clk->clkdm, hw->clk);
 }
@@ -434,80 +445,72 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 * target rate if it hasn't been done already, then program and lock
 * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
 */
-int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        struct clk *new_parent = NULL;
-        unsigned long hw_rate, bypass_rate;
        u16 freqsel = 0;
        struct dpll_data *dd;
        int ret;
-        if (!clk || !rate)
+        if (!hw || !rate)
                return -EINVAL;
        dd = clk->dpll_data;
        if (!dd)
                return -EINVAL;
-        hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
+        __clk_prepare(dd->clk_bypass);
-        if (rate == hw_rate)
+        clk_enable(dd->clk_bypass);
-                return 0;
+        __clk_prepare(dd->clk_ref);
+        clk_enable(dd->clk_ref);
-        /*
+        if (__clk_get_rate(dd->clk_bypass) == rate &&
-         * Ensure both the bypass and ref clocks are enabled prior to
+            (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-         * doing anything; we need the bypass clock running to reprogram
+                pr_debug("%s: %s: set rate: entering bypass.\n",
-         * the DPLL.
+                         __func__, __clk_get_name(hw->clk));
-         */
-        omap2_clk_enable(dd->clk_bypass);
-        omap2_clk_enable(dd->clk_ref);
-        bypass_rate = __clk_get_rate(dd->clk_bypass);
-        if (bypass_rate == rate &&
-            (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
                ret = _omap3_noncore_dpll_bypass(clk);
                if (!ret)
                        new_parent = dd->clk_bypass;
        } else {
                if (dd->last_rounded_rate != rate)
-                        rate = clk->round_rate(clk, rate);
+                        rate = __clk_round_rate(hw->clk, rate);
                if (dd->last_rounded_rate == 0)
                        return -EINVAL;
                /* No freqsel on OMAP4 and OMAP3630 */
-                if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
+                if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
                        freqsel = _omap3_dpll_compute_freqsel(clk,
                                                dd->last_rounded_n);
                        if (!freqsel)
                                WARN_ON(1);
                }
-                pr_debug("clock: %s: set rate: locking rate to %lu.\n",
+                pr_debug("%s: %s: set rate: locking rate to %lu.\n",
-                         __clk_get_name(clk), rate);
+                         __func__, __clk_get_name(hw->clk), rate);
                ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
-                                                 dd->last_rounded_n, freqsel);
+                                                dd->last_rounded_n, freqsel);
                if (!ret)
                        new_parent = dd->clk_ref;
        }
-        if (!ret) {
+        /*
-                /*
+        * FIXME - this is all wrong.  common code handles reparenting and
-                 * Switch the parent clock in the hierarchy, and make sure
+        * migrating prepare/enable counts.  dplls should be a multiplexer
-                 * that the new parent's usecount is correct.  Note: we
+        * clock and this should be a set_parent operation so that all of that
-                 * enable the new parent before disabling the old to avoid
+        * stuff is inherited for free
-                 * any unnecessary hardware disable->enable transitions.
+        */
-                 */
-                if (clk->usecount) {
+        if (!ret)
-                        omap2_clk_enable(new_parent);
+                __clk_reparent(hw->clk, new_parent);
-                        omap2_clk_disable(clk->parent);
-                }
+        clk_disable(dd->clk_ref);
-                clk_reparent(clk, new_parent);
+        __clk_unprepare(dd->clk_ref);
-                clk->rate = rate;
+        clk_disable(dd->clk_bypass);
-        }
+        __clk_unprepare(dd->clk_bypass);
-        omap2_clk_disable(dd->clk_ref);
-        omap2_clk_disable(dd->clk_bypass);
        return 0;
 }
@@ -522,7 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 * -EINVAL if passed a null pointer or if the struct clk does not
 * appear to refer to a DPLL.
 */
-u32 omap3_dpll_autoidle_read(struct clk *clk)
+u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
 {
        const struct dpll_data *dd;
        u32 v;
@@ -551,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
 * OMAP3430.  The DPLL will enter low-power stop when its downstream
 * clocks are gated.  No return value.
 */
-void omap3_dpll_allow_idle(struct clk *clk)
+void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
 {
        const struct dpll_data *dd;
        u32 v;
@@ -561,11 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk)
        dd = clk->dpll_data;
-        if (!dd->autoidle_reg) {
+        if (!dd->autoidle_reg)
-                pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        __clk_get_name(clk));
                return;
-        }
        /*
         * REVISIT: CORE DPLL can optionally enter low-power bypass
@@ -585,7 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
 *
 * Disable DPLL automatic idle control.  No return value.
 */
-void omap3_dpll_deny_idle(struct clk *clk)
+void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
 {
        const struct dpll_data *dd;
        u32 v;
@@ -595,11 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk)
        dd = clk->dpll_data;
-        if (!dd->autoidle_reg) {
+        if (!dd->autoidle_reg)
-                pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        __clk_get_name(clk));
                return;
-        }
        v = __raw_readl(dd->autoidle_reg);
        v &= ~dd->autoidle_mask;
@@ -617,18 +614,25 @@ void omap3_dpll_deny_idle(struct clk *clk)
 * Using parent clock DPLL data, look up DPLL state.  If locked, set our
 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
 */
-unsigned long omap3_clkoutx2_recalc(struct clk *clk)
+unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+                                    unsigned long parent_rate)
 {
        const struct dpll_data *dd;
        unsigned long rate;
        u32 v;
-        struct clk *pclk;
+        struct clk_hw_omap *pclk = NULL;
-        unsigned long parent_rate;
+        struct clk *parent;
        /* Walk up the parents of clk, looking for a DPLL */
-        pclk = __clk_get_parent(clk);
+        do {
-        while (pclk && !pclk->dpll_data)
+                do {
-                pclk = __clk_get_parent(pclk);
+                        parent = __clk_get_parent(hw->clk);
+                        hw = __clk_get_hw(parent);
+                } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
+                if (!hw)
+                        break;
+                pclk = to_clk_hw_omap(hw);
+        } while (pclk && !pclk->dpll_data);
        /* clk does not have a DPLL as a parent?  error in the clock data */
        if (!pclk) {
@@ -640,7 +644,6 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
        WARN_ON(!dd->enable_mask);
-        parent_rate = __clk_get_rate(__clk_get_parent(clk));
        v = __raw_readl(dd->control_reg) & dd->enable_mask;
        v >>= __ffs(dd->enable_mask);
        if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
@@ -651,15 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 }
 /* OMAP3/4 non-CORE DPLL clkops */
+const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
-const struct clkops clkops_omap3_noncore_dpll_ops = {
-        .enable         = omap3_noncore_dpll_enable,
-        .disable        = omap3_noncore_dpll_disable,
-        .allow_idle     = omap3_dpll_allow_idle,
-        .deny_idle      = omap3_dpll_deny_idle,
-};
-const struct clkops clkops_omap3_core_dpll_ops = {
        .allow_idle     = omap3_dpll_allow_idle,
        .deny_idle      = omap3_dpll_deny_idle,
 };
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 09d0ccccb861..d3326c474fdc 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -15,15 +15,13 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <plat/clock.h>
 #include "soc.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm-regbits-44xx.h"
 /* Supported only on OMAP4 */
-int omap4_dpllmx_gatectrl_read(struct clk *clk)
+int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
 {
        u32 v;
        u32 mask;
@@ -42,7 +40,7 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk)
        return v;
 }
-void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
 {
        u32 v;
        u32 mask;
@@ -60,7 +58,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk)
        __raw_writel(v, clk->clksel_reg);
 }
-void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
 {
        u32 v;
        u32 mask;
@@ -78,9 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk)
        __raw_writel(v, clk->clksel_reg);
 }
-const struct clkops clkops_omap4_dpllmx_ops = {
+const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
        .allow_idle     = omap4_dpllmx_allow_gatectrl,
-        .deny_idle      = omap4_dpllmx_deny_gatectrl,
+        .deny_idle      = omap4_dpllmx_deny_gatectrl,
 };
 /**
@@ -92,8 +90,10 @@ const struct clkops clkops_omap4_dpllmx_ops = {
 * OMAP4 ABE DPLL.  Returns the DPLL's output rate (before M-dividers)
 * upon success, or 0 upon error.
 */
-unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
+unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+                        unsigned long parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 v;
        unsigned long rate;
        struct dpll_data *dd;
@@ -125,8 +125,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
 * ~0 if an error occurred in omap2_dpll_round_rate().
 */
-long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
+long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+                                    unsigned long target_rate,
+                                    unsigned long *parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
        u32 v;
        struct dpll_data *dd;
        long r;
@@ -142,7 +145,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
        if (v)
                target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
-        r = omap2_dpll_round_rate(clk, target_rate);
+        r = omap2_dpll_round_rate(hw, target_rate, NULL);
        if (r == ~0)
                return r;
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
index 72e0f01b715c..fce5aa3fff49 100644
--- a/arch/arm/mach-omap2/drm.c
+++ b/arch/arm/mach-omap2/drm.c
@@ -23,15 +23,20 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/platform_data/omap_drm.h>
-#include <plat/omap_device.h>
+#include "omap_device.h"
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
+#include <plat/cpu.h>
 #if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE)
+static struct omap_drm_platform_data platform_data;
 static struct platform_device omap_drm_device = {
        .dev = {
                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &platform_data,
        },
        .name = "omapdrm",
        .id = 0,
@@ -52,6 +57,8 @@ static int __init omap_init_drm(void)
                        oh->name);
        }
+        platform_data.omaprev = GET_OMAP_REVISION();
        return platform_device_register(&omap_drm_device);
 }
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 98388109f22a..b155500e84a8 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -27,7 +27,7 @@
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #ifdef CONFIG_BRIDGE_DVFS
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
 #endif
 #include <linux/platform_data/dsp-omap.h>
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
new file mode 100644
index 000000000000..679a0478644f
--- /dev/null
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2012 Texas Instruments, Inc..
+ * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+/*
+ * NOTE: this is a transitional file to help with DT adaptation.
+ * This file will be removed when DSS supports DT.
+ */
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-nokia-dsi.h>
+#include <video/omap-panel-picodlp.h>
+#include <plat/cpu.h>
+#include "dss-common.h"
+#include "mux.h"
+#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
+#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
+#define HDMI_GPIO_HPD  63 /* Hotplug detect */
+/* Display DVI */
+#define PANDA_DVI_TFP410_POWER_DOWN_GPIO        0
+/* Using generic display panel */
+static struct tfp410_platform_data omap4_dvi_panel = {
+        .i2c_bus_num            = 3,
+        .power_down_gpio        = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
+};
+static struct omap_dss_device omap4_panda_dvi_device = {
+        .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .name                   = "dvi",
+        .driver_name            = "tfp410",
+        .data                   = &omap4_dvi_panel,
+        .phy.dpi.data_lines     = 24,
+        .reset_gpio             = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
+        .channel                = OMAP_DSS_CHANNEL_LCD2,
+};
+static struct omap_dss_hdmi_data omap4_panda_hdmi_data = {
+        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
+        .ls_oe_gpio = HDMI_GPIO_LS_OE,
+        .hpd_gpio = HDMI_GPIO_HPD,
+};
+static struct omap_dss_device  omap4_panda_hdmi_device = {
+        .name = "hdmi",
+        .driver_name = "hdmi_panel",
+        .type = OMAP_DISPLAY_TYPE_HDMI,
+        .channel = OMAP_DSS_CHANNEL_DIGIT,
+        .data = &omap4_panda_hdmi_data,
+};
+static struct omap_dss_device *omap4_panda_dss_devices[] = {
+        &omap4_panda_dvi_device,
+        &omap4_panda_hdmi_device,
+};
+static struct omap_dss_board_info omap4_panda_dss_data = {
+        .num_devices    = ARRAY_SIZE(omap4_panda_dss_devices),
+        .devices        = omap4_panda_dss_devices,
+        .default_device = &omap4_panda_dvi_device,
+};
+void __init omap4_panda_display_init(void)
+{
+        omap_display_init(&omap4_panda_dss_data);
+        /*
+         * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
+         * later have external pull up on the HDMI I2C lines
+         */
+        if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
+                omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
+        else
+                omap_hdmi_init(0);
+        omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
+}
+void __init omap4_panda_display_init_of(void)
+{
+        omap_display_init(&omap4_panda_dss_data);
+}
+/* OMAP4 Blaze display data */
+#define DISPLAY_SEL_GPIO        59      /* LCD2/PicoDLP switch */
+#define DLP_POWER_ON_GPIO       40
+static struct nokia_dsi_panel_data dsi1_panel = {
+                .name           = "taal",
+                .reset_gpio     = 102,
+                .use_ext_te     = false,
+                .ext_te_gpio    = 101,
+                .esd_interval   = 0,
+                .pin_config = {
+                        .num_pins       = 6,
+                        .pins           = { 0, 1, 2, 3, 4, 5 },
+                },
+};
+static struct omap_dss_device sdp4430_lcd_device = {
+        .name                   = "lcd",
+        .driver_name            = "taal",
+        .type                   = OMAP_DISPLAY_TYPE_DSI,
+        .data                   = &dsi1_panel,
+        .phy.dsi                = {
+                .module         = 0,
+        },
+        .channel                = OMAP_DSS_CHANNEL_LCD,
+};
+static struct nokia_dsi_panel_data dsi2_panel = {
+                .name           = "taal",
+                .reset_gpio     = 104,
+                .use_ext_te     = false,
+                .ext_te_gpio    = 103,
+                .esd_interval   = 0,
+                .pin_config = {
+                        .num_pins       = 6,
+                        .pins           = { 0, 1, 2, 3, 4, 5 },
+                },
+};
+static struct omap_dss_device sdp4430_lcd2_device = {
+        .name                   = "lcd2",
+        .driver_name            = "taal",
+        .type                   = OMAP_DISPLAY_TYPE_DSI,
+        .data                   = &dsi2_panel,
+        .phy.dsi                = {
+                .module         = 1,
+        },
+        .channel                = OMAP_DSS_CHANNEL_LCD2,
+};
+static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
+        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
+        .ls_oe_gpio = HDMI_GPIO_LS_OE,
+        .hpd_gpio = HDMI_GPIO_HPD,
+};
+static struct omap_dss_device sdp4430_hdmi_device = {
+        .name = "hdmi",
+        .driver_name = "hdmi_panel",
+        .type = OMAP_DISPLAY_TYPE_HDMI,
+        .channel = OMAP_DSS_CHANNEL_DIGIT,
+        .data = &sdp4430_hdmi_data,
+};
+static struct picodlp_panel_data sdp4430_picodlp_pdata = {
+        .picodlp_adapter_id     = 2,
+        .emu_done_gpio          = 44,
+        .pwrgood_gpio           = 45,
+};
+static void sdp4430_picodlp_init(void)
+{
+        int r;
+        const struct gpio picodlp_gpios[] = {
+                {DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
+                        "DLP POWER ON"},
+                {sdp4430_picodlp_pdata.emu_done_gpio, GPIOF_IN,
+                        "DLP EMU DONE"},
+                {sdp4430_picodlp_pdata.pwrgood_gpio, GPIOF_OUT_INIT_LOW,
+                        "DLP PWRGOOD"},
+        };
+        r = gpio_request_array(picodlp_gpios, ARRAY_SIZE(picodlp_gpios));
+        if (r)
+                pr_err("Cannot request PicoDLP GPIOs, error %d\n", r);
+}
+static int sdp4430_panel_enable_picodlp(struct omap_dss_device *dssdev)
+{
+        gpio_set_value(DISPLAY_SEL_GPIO, 0);
+        gpio_set_value(DLP_POWER_ON_GPIO, 1);
+        return 0;
+}
+static void sdp4430_panel_disable_picodlp(struct omap_dss_device *dssdev)
+{
+        gpio_set_value(DLP_POWER_ON_GPIO, 0);
+        gpio_set_value(DISPLAY_SEL_GPIO, 1);
+}
+static struct omap_dss_device sdp4430_picodlp_device = {
+        .name                   = "picodlp",
+        .driver_name            = "picodlp_panel",
+        .type                   = OMAP_DISPLAY_TYPE_DPI,
+        .phy.dpi.data_lines     = 24,
+        .channel                = OMAP_DSS_CHANNEL_LCD2,
+        .platform_enable        = sdp4430_panel_enable_picodlp,
+        .platform_disable       = sdp4430_panel_disable_picodlp,
+        .data                   = &sdp4430_picodlp_pdata,
+};
+static struct omap_dss_device *sdp4430_dss_devices[] = {
+        &sdp4430_lcd_device,
+        &sdp4430_lcd2_device,
+        &sdp4430_hdmi_device,
+        &sdp4430_picodlp_device,
+};
+static struct omap_dss_board_info sdp4430_dss_data = {
+        .num_devices    = ARRAY_SIZE(sdp4430_dss_devices),
+        .devices        = sdp4430_dss_devices,
+        .default_device = &sdp4430_lcd_device,
+};
+void __init omap_4430sdp_display_init(void)
+{
+        int r;
+        /* Enable LCD2 by default (instead of Pico DLP) */
+        r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
+                        "display_sel");
+        if (r)
+                pr_err("%s: Could not get display_sel GPIO\n", __func__);
+        sdp4430_picodlp_init();
+        omap_display_init(&sdp4430_dss_data);
+        /*
+         * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
+         * later have external pull up on the HDMI I2C lines
+         */
+        if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
+                omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
+        else
+                omap_hdmi_init(0);
+        omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
+}
+void __init omap_4430sdp_display_init_of(void)
+{
+        int r;
+        /* Enable LCD2 by default (instead of Pico DLP) */
+        r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
+                        "display_sel");
+        if (r)
+                pr_err("%s: Could not get display_sel GPIO\n", __func__);
+        sdp4430_picodlp_init();
+        omap_display_init(&sdp4430_dss_data);
+}
diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h
new file mode 100644
index 000000000000..915f6fff5106
--- /dev/null
+++ b/arch/arm/mach-omap2/dss-common.h
@@ -0,0 +1,14 @@
+#ifndef __OMAP_DSS_COMMON__
+#define __OMAP_DSS_COMMON__
+/*
+ * NOTE: this is a transitional file to help with DT adaptation.
+ * This file will be removed when DSS supports DT.
+ */
+void __init omap4_panda_display_init(void);
+void __init omap4_panda_display_init_of(void);
+void __init omap_4430sdp_display_init(void);
+void __init omap_4430sdp_display_init_of(void);
+#endif
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index d1058f16fb40..399acabc3d0b 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,9 +23,9 @@
 #include <linux/of.h>
 #include <linux/platform_data/gpio-omap.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/omap_device.h>
+#include "omap_device.h"
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4acf497faeb3..db969a5c4998 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -17,9 +17,12 @@
 #include <asm/mach/flash.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "soc.h"
+#include "gpmc-nand.h"
+/* minimum size for IO mapping */
+#define NAND_IO_SIZE    4
 static struct resource gpmc_nand_resource[] = {
        {
@@ -40,41 +43,36 @@ static struct platform_device gpmc_nand_device = {
        .resource       = gpmc_nand_resource,
 };
-static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
+static int omap2_nand_gpmc_retime(
+                                struct omap_nand_platform_data *gpmc_nand_data,
+                                struct gpmc_timings *gpmc_t)
 {
        struct gpmc_timings t;
        int err;
-        if (!gpmc_nand_data->gpmc_t)
-                return 0;
        memset(&t, 0, sizeof(t));
-        t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
+        t.sync_clk = gpmc_t->sync_clk;
-        t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
+        t.cs_on = gpmc_t->cs_on;
-        t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);
+        t.adv_on = gpmc_t->adv_on;
        /* Read */
-        t.adv_rd_off = gpmc_round_ns_to_ticks(
+        t.adv_rd_off = gpmc_t->adv_rd_off;
-                                gpmc_nand_data->gpmc_t->adv_rd_off);
        t.oe_on  = t.adv_on;
-        t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access);
+        t.access = gpmc_t->access;
-        t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off);
+        t.oe_off = gpmc_t->oe_off;
-        t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off);
+        t.cs_rd_off = gpmc_t->cs_rd_off;
-        t.rd_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle);
+        t.rd_cycle = gpmc_t->rd_cycle;
        /* Write */
-        t.adv_wr_off = gpmc_round_ns_to_ticks(
+        t.adv_wr_off = gpmc_t->adv_wr_off;
-                                gpmc_nand_data->gpmc_t->adv_wr_off);
        t.we_on  = t.oe_on;
        if (cpu_is_omap34xx()) {
-            t.wr_data_mux_bus = gpmc_round_ns_to_ticks(
+                t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
-                                gpmc_nand_data->gpmc_t->wr_data_mux_bus);
+                t.wr_access = gpmc_t->wr_access;
-            t.wr_access = gpmc_round_ns_to_ticks(
-                                gpmc_nand_data->gpmc_t->wr_access);
        }
-        t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off);
+        t.we_off = gpmc_t->we_off;
-        t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off);
+        t.cs_wr_off = gpmc_t->cs_wr_off;
-        t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
+        t.wr_cycle = gpmc_t->wr_cycle;
        /* Configure GPMC */
        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
@@ -91,7 +89,29 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
        return 0;
 }
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
+static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+{
+        /* support only OMAP3 class */
+        if (!cpu_is_omap34xx()) {
+                pr_err("BCH ecc is not supported on this CPU\n");
+                return 0;
+        }
+        /*
+         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
+         * Other chips may be added if confirmed to work.
+         */
+        if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
+            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
+                pr_err("BCH 4-bit mode is not supported on this CPU\n");
+                return 0;
+        }
+        return 1;
+}
+int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
+                          struct gpmc_timings *gpmc_t)
 {
        int err = 0;
        struct device *dev = &gpmc_nand_device.dev;
@@ -112,11 +132,13 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
                                gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
        gpmc_nand_resource[2].start =
                                gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
-         /* Set timings in GPMC */
-        err = omap2_nand_gpmc_retime(gpmc_nand_data);
+        if (gpmc_t) {
-        if (err < 0) {
+                err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
-                dev_err(dev, "Unable to set gpmc timings: %d\n", err);
+                if (err < 0) {
-                return err;
+                        dev_err(dev, "Unable to set gpmc timings: %d\n", err);
+                        return err;
+                }
        }
        /* Enable RD PIN Monitoring Reg */
@@ -126,6 +148,9 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
        gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
+        if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
+                return -EINVAL;
        err = platform_device_register(&gpmc_nand_device);
        if (err < 0) {
                dev_err(dev, "Unable to register NAND device\n");
diff --git a/arch/arm/mach-omap2/gpmc-nand.h b/arch/arm/mach-omap2/gpmc-nand.h
new file mode 100644
index 000000000000..d59e1281e851
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-nand.h
@@ -0,0 +1,27 @@
+/*
+ *  arch/arm/mach-omap2/gpmc-nand.h
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef __OMAP2_GPMC_NAND_H
+#define __OMAP2_GPMC_NAND_H
+#include "gpmc.h"
+#include <linux/platform_data/mtd-nand-omap2.h>
+#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
+extern int gpmc_nand_init(struct omap_nand_platform_data *d,
+                          struct gpmc_timings *gpmc_t);
+#else
+static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
+                                 struct gpmc_timings *gpmc_t)
+{
+        return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 916716e1da3b..94a349e4dc96 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -16,15 +16,24 @@
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+#include <linux/err.h>
 #include <asm/mach/flash.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "soc.h"
+#include "gpmc-onenand.h"
 #define ONENAND_IO_SIZE SZ_128K
+#define ONENAND_FLAG_SYNCREAD   (1 << 0)
+#define ONENAND_FLAG_SYNCWRITE  (1 << 1)
+#define ONENAND_FLAG_HF         (1 << 2)
+#define ONENAND_FLAG_VHF        (1 << 3)
+static unsigned onenand_flags;
+static unsigned latency;
 static struct omap_onenand_platform_data *gpmc_onenand_data;
 static struct resource gpmc_onenand_resource = {
@@ -38,11 +47,10 @@ static struct platform_device gpmc_onenand_device = {
        .resource       = &gpmc_onenand_resource,
 };
-static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
+static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 {
+        struct gpmc_device_timings dev_t;
        struct gpmc_timings t;
-        u32 reg;
-        int err;
        const int t_cer = 15;
        const int t_avdp = 12;
@@ -51,60 +59,49 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
        const int t_aa = 76;
        const int t_oe = 20;
        const int t_cez = 20; /* max of t_cez, t_oez */
-        const int t_ds = 30;
        const int t_wpl = 40;
        const int t_wph = 30;
-        /* Ensure sync read and sync write are disabled */
+        memset(&dev_t, 0, sizeof(dev_t));
-        reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
-        reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
-        writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-        memset(&t, 0, sizeof(t));
+        dev_t.mux = true;
-        t.sync_clk = 0;
+        dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
-        t.cs_on = 0;
+        dev_t.t_avdp_w = dev_t.t_avdp_r;
-        t.adv_on = 0;
+        dev_t.t_aavdh = t_aavdh * 1000;
+        dev_t.t_aa = t_aa * 1000;
-        /* Read */
+        dev_t.t_ce = t_ce * 1000;
-        t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
+        dev_t.t_oe = t_oe * 1000;
-        t.oe_on  = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
+        dev_t.t_cez_r = t_cez * 1000;
-        t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
+        dev_t.t_cez_w = dev_t.t_cez_r;
-        t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
+        dev_t.t_wpl = t_wpl * 1000;
-        t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
+        dev_t.t_wph = t_wph * 1000;
-        t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
-        t.cs_rd_off = t.oe_off;
+        gpmc_calc_timings(&t, &dev_t);
-        t.rd_cycle  = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
+        return t;
-        /* Write */
+}
-        t.adv_wr_off = t.adv_rd_off;
-        t.we_on  = t.oe_on;
-        if (cpu_is_omap34xx()) {
-                t.wr_data_mux_bus = t.we_on;
-                t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
-        }
-        t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
-        t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
-        t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
+static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
+{
        /* Configure GPMC for asynchronous read */
        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
                          GPMC_CONFIG1_DEVICESIZE_16 |
                          GPMC_CONFIG1_MUXADDDATA);
-        err = gpmc_cs_set_timings(cs, &t);
+        return gpmc_cs_set_timings(cs, t);
-        if (err)
+}
-                return err;
+static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
+{
+        u32 reg;
        /* Ensure sync read and sync write are disabled */
        reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
        reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
        writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-        return 0;
 }
-static void set_onenand_cfg(void __iomem *onenand_base, int latency,
+static void set_onenand_cfg(void __iomem *onenand_base)
-                                int sync_read, int sync_write, int hf, int vhf)
 {
        u32 reg;
@@ -112,19 +109,19 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
        reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
        reg |=  (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
                ONENAND_SYS_CFG1_BL_16;
-        if (sync_read)
+        if (onenand_flags & ONENAND_FLAG_SYNCREAD)
                reg |= ONENAND_SYS_CFG1_SYNC_READ;
        else
                reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
-        if (sync_write)
+        if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
                reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
        else
                reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
-        if (hf)
+        if (onenand_flags & ONENAND_FLAG_HF)
                reg |= ONENAND_SYS_CFG1_HF;
        else
                reg &= ~ONENAND_SYS_CFG1_HF;
-        if (vhf)
+        if (onenand_flags & ONENAND_FLAG_VHF)
                reg |= ONENAND_SYS_CFG1_VHF;
        else
                reg &= ~ONENAND_SYS_CFG1_VHF;
@@ -132,21 +129,10 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
 }
 static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
-                                  void __iomem *onenand_base, bool *clk_dep)
+                                  void __iomem *onenand_base)
 {
        u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
-        int freq = 0;
+        int freq;
-        if (cfg->get_freq) {
-                struct onenand_freq_info fi;
-                fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
-                fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
-                fi.ver_id = ver;
-                freq = cfg->get_freq(&fi, clk_dep);
-                if (freq)
-                        return freq;
-        }
        switch ((ver >> 4) & 0xf) {
        case 0:
@@ -172,41 +158,24 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
        return freq;
 }
-static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+static struct gpmc_timings
-                                        void __iomem *onenand_base,
+omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
-                                        int *freq_ptr)
+                                int freq)
 {
+        struct gpmc_device_timings dev_t;
        struct gpmc_timings t;
        const int t_cer  = 15;
        const int t_avdp = 12;
        const int t_cez  = 20; /* max of t_cez, t_oez */
-        const int t_ds   = 30;
        const int t_wpl  = 40;
        const int t_wph  = 30;
        int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-        int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+        int div, gpmc_clk_ns;
-        int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
-        int err, ticks_cez;
-        int cs = cfg->cs, freq = *freq_ptr;
-        u32 reg;
-        bool clk_dep = false;
-        if (cfg->flags & ONENAND_SYNC_READ) {
+        if (cfg->flags & ONENAND_SYNC_READ)
-                sync_read = 1;
+                onenand_flags = ONENAND_FLAG_SYNCREAD;
-        } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
+        else if (cfg->flags & ONENAND_SYNC_READWRITE)
-                sync_read = 1;
+                onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
-                sync_write = 1;
-        } else
-                return omap2_onenand_set_async_mode(cs, onenand_base);
-        if (!freq) {
-                /* Very first call freq is not known */
-                err = omap2_onenand_set_async_mode(cs, onenand_base);
-                if (err)
-                        return err;
-                freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
-                first_time = 1;
-        }
        switch (freq) {
        case 104:
@@ -244,116 +213,67 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                t_ach   = 9;
                t_aavdh = 7;
                t_rdyo  = 15;
-                sync_write = 0;
+                onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
                break;
        }
-        div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
+        div = gpmc_calc_divider(min_gpmc_clk_period);
        gpmc_clk_ns = gpmc_ticks_to_ns(div);
        if (gpmc_clk_ns < 15) /* >66Mhz */
-                hf = 1;
+                onenand_flags |= ONENAND_FLAG_HF;
+        else
+                onenand_flags &= ~ONENAND_FLAG_HF;
        if (gpmc_clk_ns < 12) /* >83Mhz */
-                vhf = 1;
+                onenand_flags |= ONENAND_FLAG_VHF;
-        if (vhf)
+        else
+                onenand_flags &= ~ONENAND_FLAG_VHF;
+        if (onenand_flags & ONENAND_FLAG_VHF)
                latency = 8;
-        else if (hf)
+        else if (onenand_flags & ONENAND_FLAG_HF)
                latency = 6;
        else if (gpmc_clk_ns >= 25) /* 40 MHz*/
                latency = 3;
        else
                latency = 4;
-        if (clk_dep) {
+        /* Set synchronous read timings */
-                if (gpmc_clk_ns < 12) { /* >83Mhz */
+        memset(&dev_t, 0, sizeof(dev_t));
-                        t_ces   = 3;
-                        t_avds  = 4;
-                } else if (gpmc_clk_ns < 15) { /* >66Mhz */
-                        t_ces   = 5;
-                        t_avds  = 4;
-                } else if (gpmc_clk_ns < 25) { /* >40Mhz */
-                        t_ces   = 6;
-                        t_avds  = 5;
-                } else {
-                        t_ces   = 7;
-                        t_avds  = 7;
-                }
-        }
-        if (first_time)
+        dev_t.mux = true;
-                set_onenand_cfg(onenand_base, latency,
+        dev_t.sync_read = true;
-                                        sync_read, sync_write, hf, vhf);
+        if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
+                dev_t.sync_write = true;
-        if (div == 1) {
-                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
-                reg |= (1 << 7);
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
-                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
-                reg |= (1 << 7);
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
-                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
-                reg |= (1 << 7);
-                reg |= (1 << 23);
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
        } else {
-                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
+                dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
-                reg &= ~(1 << 7);
+                dev_t.t_wpl = t_wpl * 1000;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
+                dev_t.t_wph = t_wph * 1000;
-                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
+                dev_t.t_aavdh = t_aavdh * 1000;
-                reg &= ~(1 << 7);
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
-                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
-                reg &= ~(1 << 7);
-                reg &= ~(1 << 23);
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
        }
+        dev_t.ce_xdelay = true;
+        dev_t.avd_xdelay = true;
+        dev_t.oe_xdelay = true;
+        dev_t.we_xdelay = true;
+        dev_t.clk = min_gpmc_clk_period;
+        dev_t.t_bacc = dev_t.clk;
+        dev_t.t_ces = t_ces * 1000;
+        dev_t.t_avds = t_avds * 1000;
+        dev_t.t_avdh = t_avdh * 1000;
+        dev_t.t_ach = t_ach * 1000;
+        dev_t.cyc_iaa = (latency + 1);
+        dev_t.t_cez_r = t_cez * 1000;
+        dev_t.t_cez_w = dev_t.t_cez_r;
+        dev_t.cyc_aavdh_oe = 1;
+        dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
+        gpmc_calc_timings(&t, &dev_t);
+        return t;
+}
-        /* Set synchronous read timings */
+static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
-        memset(&t, 0, sizeof(t));
+{
-        t.sync_clk = min_gpmc_clk_period;
+        unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
-        t.cs_on = 0;
+        unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
-        t.adv_on = 0;
-        fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
-        fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
-        t.page_burst_access = gpmc_clk_ns;
-        /* Read */
-        t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
-        t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
-        /* Force at least 1 clk between AVD High to OE Low */
-        if (t.oe_on <= t.adv_rd_off)
-                t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
-        t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
-        t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
-        t.cs_rd_off = t.oe_off;
-        ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
-        t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
-                     ticks_cez);
-        /* Write */
-        if (sync_write) {
-                t.adv_wr_off = t.adv_rd_off;
-                t.we_on  = 0;
-                t.we_off = t.cs_rd_off;
-                t.cs_wr_off = t.cs_rd_off;
-                t.wr_cycle  = t.rd_cycle;
-                if (cpu_is_omap34xx()) {
-                        t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
-                                        gpmc_ps_to_ticks(min_gpmc_clk_period +
-                                        t_rdyo * 1000));
-                        t.wr_access = t.access;
-                }
-        } else {
-                t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
-                                                        t_avdp, t_cer));
-                t.we_on  = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
-                t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
-                t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
-                t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
-                if (cpu_is_omap34xx()) {
-                        t.wr_data_mux_bus = t.we_on;
-                        t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
-                }
-        }
        /* Configure GPMC for synchronous read */
        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
@@ -362,7 +282,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                          (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
                          (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
                          (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
-                          GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
                          GPMC_CONFIG1_PAGE_LEN(2) |
                          (cpu_is_omap34xx() ? 0 :
                                (GPMC_CONFIG1_WAIT_READ_MON |
@@ -371,11 +290,45 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                          GPMC_CONFIG1_DEVICETYPE_NOR |
                          GPMC_CONFIG1_MUXADDDATA);
-        err = gpmc_cs_set_timings(cs, &t);
+        return gpmc_cs_set_timings(cs, t);
-        if (err)
+}
-                return err;
+static int omap2_onenand_setup_async(void __iomem *onenand_base)
+{
+        struct gpmc_timings t;
+        int ret;
+        omap2_onenand_set_async_mode(onenand_base);
+        t = omap2_onenand_calc_async_timings();
+        ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
+        if (IS_ERR_VALUE(ret))
+                return ret;
+        omap2_onenand_set_async_mode(onenand_base);
+        return 0;
+}
+static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
+{
+        int ret, freq = *freq_ptr;
+        struct gpmc_timings t;
-        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+        if (!freq) {
+                /* Very first call freq is not known */
+                freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
+                set_onenand_cfg(onenand_base);
+        }
+        t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
+        ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
+        if (IS_ERR_VALUE(ret))
+                return ret;
+        set_onenand_cfg(onenand_base);
        *freq_ptr = freq;
@@ -385,15 +338,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
        struct device *dev = &gpmc_onenand_device.dev;
+        unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
+        int ret;
-        /* Set sync timings in GPMC */
+        ret = omap2_onenand_setup_async(onenand_base);
-        if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
+        if (ret) {
-                        freq_ptr) < 0) {
+                dev_err(dev, "unable to set to async mode\n");
-                dev_err(dev, "Unable to set synchronous mode\n");
+                return ret;
-                return -EINVAL;
        }
-        return 0;
+        if (!(gpmc_onenand_data->flags & l))
+                return 0;
+        ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
+        if (ret)
+                dev_err(dev, "unable to set to sync mode\n");
+        return ret;
 }
 void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
@@ -411,6 +371,11 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
        }
+        if (cpu_is_omap34xx())
+                gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
+        else
+                gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
        err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
                                (unsigned long *)&gpmc_onenand_resource.start);
        if (err < 0) {
diff --git a/arch/arm/mach-omap2/gpmc-onenand.h b/arch/arm/mach-omap2/gpmc-onenand.h
new file mode 100644
index 000000000000..216f23a8b45c
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-onenand.h
@@ -0,0 +1,24 @@
+/*
+ *  arch/arm/mach-omap2/gpmc-onenand.h
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef __OMAP2_GPMC_ONENAND_H
+#define __OMAP2_GPMC_ONENAND_H
+#include <linux/platform_data/mtd-onenand-omap2.h>
+#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
+extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
+#else
+#define board_onenand_data      NULL
+static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
+{
+}
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 565475310374..11d0b756f098 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "gpmc-smc91x.h"
 #include "soc.h"
@@ -58,6 +58,7 @@ static struct platform_device gpmc_smc91x_device = {
 static int smc91c96_gpmc_retime(void)
 {
        struct gpmc_timings t;
+        struct gpmc_device_timings dev_t;
        const int t3 = 10;      /* Figure 12.2 read and 12.4 write */
        const int t4_r = 20;    /* Figure 12.2 read */
        const int t4_w = 5;     /* Figure 12.4 write */
@@ -68,32 +69,6 @@ static int smc91c96_gpmc_retime(void)
        const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
        u32 l;
-        memset(&t, 0, sizeof(t));
-        /* Read timings */
-        t.cs_on = 0;
-        t.adv_on = t.cs_on;
-        t.oe_on = t.adv_on + t3;
-        t.access = t.oe_on + t5;
-        t.oe_off = t.access;
-        t.adv_rd_off = t.oe_off + max(t4_r, t6);
-        t.cs_rd_off = t.oe_off;
-        t.rd_cycle = t20 - t.oe_on;
-        /* Write timings */
-        t.we_on = t.adv_on + t3;
-        if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) {
-                t.wr_data_mux_bus = t.we_on;
-                t.we_off = t.wr_data_mux_bus + t7;
-        } else
-                t.we_off = t.we_on + t7;
-        if (cpu_is_omap34xx())
-                t.wr_access = t.we_off;
-        t.adv_wr_off = t.we_off + max(t4_w, t8);
-        t.cs_wr_off = t.we_off + t4_w;
-        t.wr_cycle = t20 - t.we_on;
        l = GPMC_CONFIG1_DEVICESIZE_16;
        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
                l |= GPMC_CONFIG1_MUXADDDATA;
@@ -115,6 +90,22 @@ static int smc91c96_gpmc_retime(void)
        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
                return 0;
+        memset(&dev_t, 0, sizeof(dev_t));
+        dev_t.t_oeasu = t3 * 1000;
+        dev_t.t_oe = t5 * 1000;
+        dev_t.t_cez_r = t4_r * 1000;
+        dev_t.t_oez = t6 * 1000;
+        dev_t.t_rd_cycle = (t20 - t3) * 1000;
+        dev_t.t_weasu = t3 * 1000;
+        dev_t.t_wpl = t7 * 1000;
+        dev_t.t_wph = t8 * 1000;
+        dev_t.t_cez_w = t4_w * 1000;
+        dev_t.t_wr_cycle = (t20 - t3) * 1000;
+        gpmc_calc_timings(&t, &dev_t);
        return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
 }
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index 249a0b440cd6..ef990118d32b 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -20,7 +20,7 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "gpmc-smsc911x.h"
 static struct resource gpmc_smsc911x_resources[] = {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 92b5718fa722..65468f6d7f0e 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,16 +26,14 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <asm/mach-types.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/gpmc.h>
-#include <plat/cpu.h>
+#include <asm/mach-types.h>
-#include <plat/gpmc.h>
-#include <plat/sdrc.h>
-#include <plat/omap_device.h>
 #include "soc.h"
 #include "common.h"
+#include "omap_device.h"
+#include "gpmc.h"
 #define DEVICE_NAME             "omap-gpmc"
@@ -59,6 +57,9 @@
 #define GPMC_ECC_SIZE_CONFIG    0x1fc
 #define GPMC_ECC1_RESULT        0x200
 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
+#define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
+#define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
+#define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
 /* GPMC ECC control settings */
 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
@@ -73,8 +74,16 @@
 #define GPMC_ECC_CTRL_ECCREG8           0x008
 #define GPMC_ECC_CTRL_ECCREG9           0x009
+#define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
+#define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
+#define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
+#define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
+#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
+#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
 #define GPMC_CS0_OFFSET         0x60
 #define GPMC_CS_SIZE            0x30
+#define GPMC_BCH_SIZE           0x10
 #define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
@@ -137,7 +146,6 @@ static struct resource	gpmc_mem_root;
 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
-static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -158,22 +166,6 @@ static u32 gpmc_read_reg(int idx)
        return __raw_readl(gpmc_base + idx);
 }
-static void gpmc_cs_write_byte(int cs, int idx, u8 val)
-{
-        void __iomem *reg_addr;
-        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        __raw_writeb(val, reg_addr);
-}
-static u8 gpmc_cs_read_byte(int cs, int idx)
-{
-        void __iomem *reg_addr;
-        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        return __raw_readb(reg_addr);
-}
 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 {
        void __iomem *reg_addr;
@@ -238,6 +230,51 @@ unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
        return ticks * gpmc_get_fclk_period() / 1000;
 }
+static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
+{
+        return ticks * gpmc_get_fclk_period();
+}
+static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
+{
+        unsigned long ticks = gpmc_ps_to_ticks(time_ps);
+        return ticks * gpmc_get_fclk_period();
+}
+static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
+{
+        u32 l;
+        l = gpmc_cs_read_reg(cs, reg);
+        if (value)
+                l |= mask;
+        else
+                l &= ~mask;
+        gpmc_cs_write_reg(cs, reg, l);
+}
+static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
+{
+        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
+                           GPMC_CONFIG1_TIME_PARA_GRAN,
+                           p->time_para_granularity);
+        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
+                           GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
+        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
+                           GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
+        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
+                           GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
+        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
+                           GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
+        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
+                           GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
+                           p->cycle2cyclesamecsen);
+        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
+                           GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
+                           p->cycle2cyclediffcsen);
+}
 #ifdef DEBUG
 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
                               int time, const char *name)
@@ -288,7 +325,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
                return -1
 #endif
-int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
+int gpmc_calc_divider(unsigned int sync_clk)
 {
        int div;
        u32 l;
@@ -308,7 +345,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
        int div;
        u32 l;
-        div = gpmc_cs_calc_divider(cs, t->sync_clk);
+        div = gpmc_calc_divider(t->sync_clk);
        if (div < 0)
                return div;
@@ -331,6 +368,12 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
        GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
+        GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
+        GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
+        GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
+        GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
                GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
        if (gpmc_capability & GPMC_HAS_WR_ACCESS)
@@ -350,6 +393,8 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
        }
+        gpmc_cs_bool_timings(cs, &t->bool_timings);
        return 0;
 }
@@ -509,44 +554,6 @@ void gpmc_cs_free(int cs)
 EXPORT_SYMBOL(gpmc_cs_free);
 /**
- * gpmc_read_status - read access request to get the different gpmc status
- * @cmd: command type
- * @return status
- */
-int gpmc_read_status(int cmd)
-{
-        int     status = -EINVAL;
-        u32     regval = 0;
-        switch (cmd) {
-        case GPMC_GET_IRQ_STATUS:
-                status = gpmc_read_reg(GPMC_IRQSTATUS);
-                break;
-        case GPMC_PREFETCH_FIFO_CNT:
-                regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
-                status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
-                break;
-        case GPMC_PREFETCH_COUNT:
-                regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
-                status = GPMC_PREFETCH_STATUS_COUNT(regval);
-                break;
-        case GPMC_STATUS_BUFFER:
-                regval = gpmc_read_reg(GPMC_STATUS);
-                /* 1 : buffer is available to write */
-                status = regval & GPMC_STATUS_BUFF_EMPTY;
-                break;
-        default:
-                printk(KERN_ERR "gpmc_read_status: Not supported\n");
-        }
-        return status;
-}
-EXPORT_SYMBOL(gpmc_read_status);
-/**
 * gpmc_cs_configure - write request to configure gpmc
 * @cs: chip select number
 * @cmd: command type
@@ -614,121 +621,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
 }
 EXPORT_SYMBOL(gpmc_cs_configure);
-/**
- * gpmc_nand_read - nand specific read access request
- * @cs: chip select number
- * @cmd: command type
- */
-int gpmc_nand_read(int cs, int cmd)
-{
-        int rval = -EINVAL;
-        switch (cmd) {
-        case GPMC_NAND_DATA:
-                rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
-                break;
-        default:
-                printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
-        }
-        return rval;
-}
-EXPORT_SYMBOL(gpmc_nand_read);
-/**
- * gpmc_nand_write - nand specific write request
- * @cs: chip select number
- * @cmd: command type
- * @wval: value to write
- */
-int gpmc_nand_write(int cs, int cmd, int wval)
-{
-        int err = 0;
-        switch (cmd) {
-        case GPMC_NAND_COMMAND:
-                gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
-                break;
-        case GPMC_NAND_ADDRESS:
-                gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
-                break;
-        case GPMC_NAND_DATA:
-                gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
-        default:
-                printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
-                err = -EINVAL;
-        }
-        return err;
-}
-EXPORT_SYMBOL(gpmc_nand_write);
-/**
- * gpmc_prefetch_enable - configures and starts prefetch transfer
- * @cs: cs (chip select) number
- * @fifo_th: fifo threshold to be used for read/ write
- * @dma_mode: dma mode enable (1) or disable (0)
- * @u32_count: number of bytes to be transferred
- * @is_write: prefetch read(0) or write post(1) mode
- */
-int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
-                                unsigned int u32_count, int is_write)
-{
-        if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
-                pr_err("gpmc: fifo threshold is not supported\n");
-                return -1;
-        } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
-                /* Set the amount of bytes to be prefetched */
-                gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
-                /* Set dma/mpu mode, the prefetch read / post write and
-                 * enable the engine. Set which cs is has requested for.
-                 */
-                gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
-                                        PREFETCH_FIFOTHRESHOLD(fifo_th) |
-                                        ENABLE_PREFETCH |
-                                        (dma_mode << DMA_MPU_MODE) |
-                                        (0x1 & is_write)));
-                /*  Start the prefetch engine */
-                gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
-        } else {
-                return -EBUSY;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(gpmc_prefetch_enable);
-/**
- * gpmc_prefetch_reset - disables and stops the prefetch engine
- */
-int gpmc_prefetch_reset(int cs)
-{
-        u32 config1;
-        /* check if the same module/cs is trying to reset */
-        config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
-        if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
-                return -EINVAL;
-        /* Stop the PFPW engine */
-        gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
-        /* Reset/disable the PFPW engine */
-        gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
-        return 0;
-}
-EXPORT_SYMBOL(gpmc_prefetch_reset);
 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 {
+        int i;
        reg->gpmc_status = gpmc_base + GPMC_STATUS;
        reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
                                GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
@@ -744,7 +640,17 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
        reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
        reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
        reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
-        reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
+        for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
+                reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
+                                           GPMC_BCH_SIZE * i;
+                reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
+                                           GPMC_BCH_SIZE * i;
+                reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
+                                           GPMC_BCH_SIZE * i;
+                reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
+                                           GPMC_BCH_SIZE * i;
+        }
 }
 int gpmc_get_client_irq(unsigned irq_config)
@@ -902,6 +808,319 @@ static int __devinit gpmc_mem_init(void)
        return 0;
 }
+static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
+{
+        u32 temp;
+        int div;
+        div = gpmc_calc_divider(sync_clk);
+        temp = gpmc_ps_to_ticks(time_ps);
+        temp = (temp + div - 1) / div;
+        return gpmc_ticks_to_ps(temp * div);
+}
+/* XXX: can the cycles be avoided ? */
+static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
+                                struct gpmc_device_timings *dev_t)
+{
+        bool mux = dev_t->mux;
+        u32 temp;
+        /* adv_rd_off */
+        temp = dev_t->t_avdp_r;
+        /* XXX: mux check required ? */
+        if (mux) {
+                /* XXX: t_avdp not to be required for sync, only added for tusb
+                 * this indirectly necessitates requirement of t_avdp_r and
+                 * t_avdp_w instead of having a single t_avdp
+                 */
+                temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
+                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
+        }
+        gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
+        /* oe_on */
+        temp = dev_t->t_oeasu; /* XXX: remove this ? */
+        if (mux) {
+                temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
+                temp = max_t(u32, temp, gpmc_t->adv_rd_off +
+                                gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
+        }
+        gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
+        /* access */
+        /* XXX: any scope for improvement ?, by combining oe_on
+         * and clk_activation, need to check whether
+         * access = clk_activation + round to sync clk ?
+         */
+        temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
+        temp += gpmc_t->clk_activation;
+        if (dev_t->cyc_oe)
+                temp = max_t(u32, temp, gpmc_t->oe_on +
+                                gpmc_ticks_to_ps(dev_t->cyc_oe));
+        gpmc_t->access = gpmc_round_ps_to_ticks(temp);
+        gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
+        gpmc_t->cs_rd_off = gpmc_t->oe_off;
+        /* rd_cycle */
+        temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
+        temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
+                                                        gpmc_t->access;
+        /* XXX: barter t_ce_rdyz with t_cez_r ? */
+        if (dev_t->t_ce_rdyz)
+                temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
+        gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
+        return 0;
+}
+static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
+                                struct gpmc_device_timings *dev_t)
+{
+        bool mux = dev_t->mux;
+        u32 temp;
+        /* adv_wr_off */
+        temp = dev_t->t_avdp_w;
+        if (mux) {
+                temp = max_t(u32, temp,
+                        gpmc_t->clk_activation + dev_t->t_avdh);
+                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
+        }
+        gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
+        /* wr_data_mux_bus */
+        temp = max_t(u32, dev_t->t_weasu,
+                        gpmc_t->clk_activation + dev_t->t_rdyo);
+        /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
+         * and in that case remember to handle we_on properly
+         */
+        if (mux) {
+                temp = max_t(u32, temp,
+                        gpmc_t->adv_wr_off + dev_t->t_aavdh);
+                temp = max_t(u32, temp, gpmc_t->adv_wr_off +
+                                gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
+        }
+        gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
+        /* we_on */
+        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
+                gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
+        else
+                gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
+        /* wr_access */
+        /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
+        gpmc_t->wr_access = gpmc_t->access;
+        /* we_off */
+        temp = gpmc_t->we_on + dev_t->t_wpl;
+        temp = max_t(u32, temp,
+                        gpmc_t->wr_access + gpmc_ticks_to_ps(1));
+        temp = max_t(u32, temp,
+                gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
+        gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
+        gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
+                                                        dev_t->t_wph);
+        /* wr_cycle */
+        temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
+        temp += gpmc_t->wr_access;
+        /* XXX: barter t_ce_rdyz with t_cez_w ? */
+        if (dev_t->t_ce_rdyz)
+                temp = max_t(u32, temp,
+                                 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
+        gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
+        return 0;
+}
+static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
+                                struct gpmc_device_timings *dev_t)
+{
+        bool mux = dev_t->mux;
+        u32 temp;
+        /* adv_rd_off */
+        temp = dev_t->t_avdp_r;
+        if (mux)
+                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
+        gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
+        /* oe_on */
+        temp = dev_t->t_oeasu;
+        if (mux)
+                temp = max_t(u32, temp,
+                        gpmc_t->adv_rd_off + dev_t->t_aavdh);
+        gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
+        /* access */
+        temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
+                                gpmc_t->oe_on + dev_t->t_oe);
+        temp = max_t(u32, temp,
+                                gpmc_t->cs_on + dev_t->t_ce);
+        temp = max_t(u32, temp,
+                                gpmc_t->adv_on + dev_t->t_aa);
+        gpmc_t->access = gpmc_round_ps_to_ticks(temp);
+        gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
+        gpmc_t->cs_rd_off = gpmc_t->oe_off;
+        /* rd_cycle */
+        temp = max_t(u32, dev_t->t_rd_cycle,
+                        gpmc_t->cs_rd_off + dev_t->t_cez_r);
+        temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
+        gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
+        return 0;
+}
+static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
+                                struct gpmc_device_timings *dev_t)
+{
+        bool mux = dev_t->mux;
+        u32 temp;
+        /* adv_wr_off */
+        temp = dev_t->t_avdp_w;
+        if (mux)
+                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
+        gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
+        /* wr_data_mux_bus */
+        temp = dev_t->t_weasu;
+        if (mux) {
+                temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
+                temp = max_t(u32, temp, gpmc_t->adv_wr_off +
+                                gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
+        }
+        gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
+        /* we_on */
+        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
+                gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
+        else
+                gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
+        /* we_off */
+        temp = gpmc_t->we_on + dev_t->t_wpl;
+        gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
+        gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
+                                                        dev_t->t_wph);
+        /* wr_cycle */
+        temp = max_t(u32, dev_t->t_wr_cycle,
+                                gpmc_t->cs_wr_off + dev_t->t_cez_w);
+        gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
+        return 0;
+}
+static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
+                        struct gpmc_device_timings *dev_t)
+{
+        u32 temp;
+        gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
+                                                gpmc_get_fclk_period();
+        gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
+                                        dev_t->t_bacc,
+                                        gpmc_t->sync_clk);
+        temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
+        gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
+        if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
+                return 0;
+        if (dev_t->ce_xdelay)
+                gpmc_t->bool_timings.cs_extra_delay = true;
+        if (dev_t->avd_xdelay)
+                gpmc_t->bool_timings.adv_extra_delay = true;
+        if (dev_t->oe_xdelay)
+                gpmc_t->bool_timings.oe_extra_delay = true;
+        if (dev_t->we_xdelay)
+                gpmc_t->bool_timings.we_extra_delay = true;
+        return 0;
+}
+static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
+                        struct gpmc_device_timings *dev_t)
+{
+        u32 temp;
+        /* cs_on */
+        gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
+        /* adv_on */
+        temp = dev_t->t_avdasu;
+        if (dev_t->t_ce_avd)
+                temp = max_t(u32, temp,
+                                gpmc_t->cs_on + dev_t->t_ce_avd);
+        gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
+        if (dev_t->sync_write || dev_t->sync_read)
+                gpmc_calc_sync_common_timings(gpmc_t, dev_t);
+        return 0;
+}
+/* TODO: remove this function once all peripherals are confirmed to
+ * work with generic timing. Simultaneously gpmc_cs_set_timings()
+ * has to be modified to handle timings in ps instead of ns
+*/
+static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
+{
+        t->cs_on /= 1000;
+        t->cs_rd_off /= 1000;
+        t->cs_wr_off /= 1000;
+        t->adv_on /= 1000;
+        t->adv_rd_off /= 1000;
+        t->adv_wr_off /= 1000;
+        t->we_on /= 1000;
+        t->we_off /= 1000;
+        t->oe_on /= 1000;
+        t->oe_off /= 1000;
+        t->page_burst_access /= 1000;
+        t->access /= 1000;
+        t->rd_cycle /= 1000;
+        t->wr_cycle /= 1000;
+        t->bus_turnaround /= 1000;
+        t->cycle2cycle_delay /= 1000;
+        t->wait_monitoring /= 1000;
+        t->clk_activation /= 1000;
+        t->wr_access /= 1000;
+        t->wr_data_mux_bus /= 1000;
+}
+int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
+                        struct gpmc_device_timings *dev_t)
+{
+        memset(gpmc_t, 0, sizeof(*gpmc_t));
+        gpmc_calc_common_timings(gpmc_t, dev_t);
+        if (dev_t->sync_read)
+                gpmc_calc_sync_read_timings(gpmc_t, dev_t);
+        else
+                gpmc_calc_async_read_timings(gpmc_t, dev_t);
+        if (dev_t->sync_write)
+                gpmc_calc_sync_write_timings(gpmc_t, dev_t);
+        else
+                gpmc_calc_async_write_timings(gpmc_t, dev_t);
+        /* TODO: remove, see function definition */
+        gpmc_convert_ps_to_ns(gpmc_t);
+        return 0;
+}
 static __devinit int gpmc_probe(struct platform_device *pdev)
 {
        int rc;
@@ -1093,267 +1312,3 @@ void omap3_gpmc_restore_context(void)
        }
 }
 #endif /* CONFIG_ARCH_OMAP3 */
-/**
- * gpmc_enable_hwecc - enable hardware ecc functionality
- * @cs: chip select number
- * @mode: read/write mode
- * @dev_width: device bus width(1 for x16, 0 for x8)
- * @ecc_size: bytes for which ECC will be generated
- */
-int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
-{
-        unsigned int val;
-        /* check if ecc module is in used */
-        if (gpmc_ecc_used != -EINVAL)
-                return -EINVAL;
-        gpmc_ecc_used = cs;
-        /* clear ecc and enable bits */
-        gpmc_write_reg(GPMC_ECC_CONTROL,
-                        GPMC_ECC_CTRL_ECCCLEAR |
-                        GPMC_ECC_CTRL_ECCREG1);
-        /* program ecc and result sizes */
-        val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
-        gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
-        switch (mode) {
-        case GPMC_ECC_READ:
-        case GPMC_ECC_WRITE:
-                gpmc_write_reg(GPMC_ECC_CONTROL,
-                                GPMC_ECC_CTRL_ECCCLEAR |
-                                GPMC_ECC_CTRL_ECCREG1);
-                break;
-        case GPMC_ECC_READSYN:
-                gpmc_write_reg(GPMC_ECC_CONTROL,
-                                GPMC_ECC_CTRL_ECCCLEAR |
-                                GPMC_ECC_CTRL_ECCDISABLE);
-                break;
-        default:
-                printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
-                break;
-        }
-        /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
-        val = (dev_width << 7) | (cs << 1) | (0x1);
-        gpmc_write_reg(GPMC_ECC_CONFIG, val);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
-/**
- * gpmc_calculate_ecc - generate non-inverted ecc bytes
- * @cs: chip select number
- * @dat: data pointer over which ecc is computed
- * @ecc_code: ecc code buffer
- *
- * Using non-inverted ECC is considered ugly since writing a blank
- * page (padding) will clear the ECC bytes. This is not a problem as long
- * no one is trying to write data on the seemingly unused page. Reading
- * an erased page will produce an ECC mismatch between generated and read
- * ECC bytes that has to be dealt with separately.
- */
-int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
-{
-        unsigned int val = 0x0;
-        if (gpmc_ecc_used != cs)
-                return -EINVAL;
-        /* read ecc result */
-        val = gpmc_read_reg(GPMC_ECC1_RESULT);
-        *ecc_code++ = val;          /* P128e, ..., P1e */
-        *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
-        /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
-        *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
-        gpmc_ecc_used = -EINVAL;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
-#ifdef CONFIG_ARCH_OMAP3
-/**
- * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
- * @cs: chip select number
- * @nsectors: how many 512-byte sectors to process
- * @nerrors: how many errors to correct per sector (4 or 8)
- *
- * This function must be executed before any call to gpmc_enable_hwecc_bch.
- */
-int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
-{
-        /* check if ecc module is in use */
-        if (gpmc_ecc_used != -EINVAL)
-                return -EINVAL;
-        /* support only OMAP3 class */
-        if (!cpu_is_omap34xx()) {
-                printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
-                return -EINVAL;
-        }
-        /*
-         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
-         * Other chips may be added if confirmed to work.
-         */
-        if ((nerrors == 4) &&
-            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
-                printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
-                return -EINVAL;
-        }
-        /* sanity check */
-        if (nsectors > 8) {
-                printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
-                       nsectors);
-                return -EINVAL;
-        }
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
-/**
- * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
- * @cs: chip select number
- * @mode: read/write mode
- * @dev_width: device bus width(1 for x16, 0 for x8)
- * @nsectors: how many 512-byte sectors to process
- * @nerrors: how many errors to correct per sector (4 or 8)
- */
-int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
-                          int nerrors)
-{
-        unsigned int val;
-        /* check if ecc module is in use */
-        if (gpmc_ecc_used != -EINVAL)
-                return -EINVAL;
-        gpmc_ecc_used = cs;
-        /* clear ecc and enable bits */
-        gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
-        /*
-         * When using BCH, sector size is hardcoded to 512 bytes.
-         * Here we are using wrapping mode 6 both for reading and writing, with:
-         *  size0 = 0  (no additional protected byte in spare area)
-         *  size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
-         */
-        gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
-        /* BCH configuration */
-        val = ((1                        << 16) | /* enable BCH */
-               (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
-               (0x06                     <<  8) | /* wrap mode = 6 */
-               (dev_width                <<  7) | /* bus width */
-               (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
-               (cs                       <<  1) | /* ECC CS */
-               (0x1));                            /* enable ECC */
-        gpmc_write_reg(GPMC_ECC_CONFIG, val);
-        gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
-/**
- * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
- * @cs:  chip select number
- * @dat: The pointer to data on which ecc is computed
- * @ecc: The ecc output buffer
- */
-int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
-{
-        int i;
-        unsigned long nsectors, reg, val1, val2;
-        if (gpmc_ecc_used != cs)
-                return -EINVAL;
-        nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
-        for (i = 0; i < nsectors; i++) {
-                reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
-                /* Read hw-computed remainder */
-                val1 = gpmc_read_reg(reg + 0);
-                val2 = gpmc_read_reg(reg + 4);
-                /*
-                 * Add constant polynomial to remainder, in order to get an ecc
-                 * sequence of 0xFFs for a buffer filled with 0xFFs; and
-                 * left-justify the resulting polynomial.
-                 */
-                *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
-                *ecc++ = 0x13 ^ ((val2 >>  4) & 0xFF);
-                *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
-                *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
-                *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
-                *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
-                *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
-        }
-        gpmc_ecc_used = -EINVAL;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
-/**
- * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
- * @cs:  chip select number
- * @dat: The pointer to data on which ecc is computed
- * @ecc: The ecc output buffer
- */
-int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
-{
-        int i;
-        unsigned long nsectors, reg, val1, val2, val3, val4;
-        if (gpmc_ecc_used != cs)
-                return -EINVAL;
-        nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
-        for (i = 0; i < nsectors; i++) {
-                reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
-                /* Read hw-computed remainder */
-                val1 = gpmc_read_reg(reg + 0);
-                val2 = gpmc_read_reg(reg + 4);
-                val3 = gpmc_read_reg(reg + 8);
-                val4 = gpmc_read_reg(reg + 12);
-                /*
-                 * Add constant polynomial to remainder, in order to get an ecc
-                 * sequence of 0xFFs for a buffer filled with 0xFFs.
-                 */
-                *ecc++ = 0xef ^ (val4 & 0xFF);
-                *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
-                *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
-                *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
-                *ecc++ = 0xed ^ (val3 & 0xFF);
-                *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
-                *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
-                *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
-                *ecc++ = 0x97 ^ (val2 & 0xFF);
-                *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
-                *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
-                *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
-                *ecc++ = 0xb5 ^ (val1 & 0xFF);
-        }
-        gpmc_ecc_used = -EINVAL;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
-#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index 2e6e2597178c..fe0a844d5007 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -11,6 +11,8 @@
 #ifndef __OMAP2_GPMC_H
 #define __OMAP2_GPMC_H
+#include <linux/platform_data/mtd-nand-omap2.h>
 /* Maximum Number of Chip Selects */
 #define GPMC_CS_NUM             8
@@ -32,15 +34,6 @@
 #define GPMC_SET_IRQ_STATUS     0x00000004
 #define GPMC_CONFIG_WP          0x00000005
-#define GPMC_GET_IRQ_STATUS     0x00000006
-#define GPMC_PREFETCH_FIFO_CNT  0x00000007 /* bytes available in FIFO for r/w */
-#define GPMC_PREFETCH_COUNT     0x00000008 /* remaining bytes to be read/write*/
-#define GPMC_STATUS_BUFFER      0x00000009 /* 1: buffer is available to write */
-#define GPMC_NAND_COMMAND       0x0000000a
-#define GPMC_NAND_ADDRESS       0x0000000b
-#define GPMC_NAND_DATA          0x0000000c
 #define GPMC_ENABLE_IRQ         0x0000000d
 /* ECC commands */
@@ -76,24 +69,20 @@
 #define GPMC_DEVICETYPE_NOR             0
 #define GPMC_DEVICETYPE_NAND            2
 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
-#define GPMC_STATUS_BUFF_EMPTY          0x00000001
 #define WR_RD_PIN_MONITORING            0x00600000
-#define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      ((val >> 24) & 0x7F)
-#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
 #define GPMC_IRQ_COUNT_EVENT            0x02
-#define PREFETCH_FIFOTHRESHOLD_MAX      0x40
-#define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
+/* bool type time settings */
+struct gpmc_bool_timings {
-enum omap_ecc {
+        bool cycle2cyclediffcsen;
-                /* 1-bit ecc: stored at end of spare area */
+        bool cycle2cyclesamecsen;
-        OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
+        bool we_extra_delay;
-        OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
+        bool oe_extra_delay;
-                /* 1-bit ecc: stored at beginning of spare area as romcode */
+        bool adv_extra_delay;
-        OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
+        bool cs_extra_delay;
-        OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
+        bool time_para_granularity;
-        OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
 };
 /*
@@ -105,50 +94,104 @@ struct gpmc_timings {
        u32 sync_clk;
        /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
-        u16 cs_on;              /* Assertion time */
+        u32 cs_on;              /* Assertion time */
-        u16 cs_rd_off;          /* Read deassertion time */
+        u32 cs_rd_off;          /* Read deassertion time */
-        u16 cs_wr_off;          /* Write deassertion time */
+        u32 cs_wr_off;          /* Write deassertion time */
        /* ADV signal timings corresponding to GPMC_CONFIG3 */
-        u16 adv_on;             /* Assertion time */
+        u32 adv_on;             /* Assertion time */
-        u16 adv_rd_off;         /* Read deassertion time */
+        u32 adv_rd_off;         /* Read deassertion time */
-        u16 adv_wr_off;         /* Write deassertion time */
+        u32 adv_wr_off;         /* Write deassertion time */
        /* WE signals timings corresponding to GPMC_CONFIG4 */
-        u16 we_on;              /* WE assertion time */
+        u32 we_on;              /* WE assertion time */
-        u16 we_off;             /* WE deassertion time */
+        u32 we_off;             /* WE deassertion time */
        /* OE signals timings corresponding to GPMC_CONFIG4 */
-        u16 oe_on;              /* OE assertion time */
+        u32 oe_on;              /* OE assertion time */
-        u16 oe_off;             /* OE deassertion time */
+        u32 oe_off;             /* OE deassertion time */
        /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
-        u16 page_burst_access;  /* Multiple access word delay */
+        u32 page_burst_access;  /* Multiple access word delay */
-        u16 access;             /* Start-cycle to first data valid delay */
+        u32 access;             /* Start-cycle to first data valid delay */
-        u16 rd_cycle;           /* Total read cycle time */
+        u32 rd_cycle;           /* Total read cycle time */
-        u16 wr_cycle;           /* Total write cycle time */
+        u32 wr_cycle;           /* Total write cycle time */
+        u32 bus_turnaround;
+        u32 cycle2cycle_delay;
+        u32 wait_monitoring;
+        u32 clk_activation;
        /* The following are only on OMAP3430 */
-        u16 wr_access;          /* WRACCESSTIME */
+        u32 wr_access;          /* WRACCESSTIME */
-        u16 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
+        u32 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
+        struct gpmc_bool_timings bool_timings;
 };
-struct gpmc_nand_regs {
+/* Device timings in picoseconds */
-        void __iomem    *gpmc_status;
+struct gpmc_device_timings {
-        void __iomem    *gpmc_nand_command;
+        u32 t_ceasu;    /* address setup to CS valid */
-        void __iomem    *gpmc_nand_address;
+        u32 t_avdasu;   /* address setup to ADV valid */
-        void __iomem    *gpmc_nand_data;
+        /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
-        void __iomem    *gpmc_prefetch_config1;
+         * of tusb using these timings even for sync whilst
-        void __iomem    *gpmc_prefetch_config2;
+         * ideally for adv_rd/(wr)_off it should have considered
-        void __iomem    *gpmc_prefetch_control;
+         * t_avdh instead. This indirectly necessitates r/w
-        void __iomem    *gpmc_prefetch_status;
+         * variations of t_avdp as it is possible to have one
-        void __iomem    *gpmc_ecc_config;
+         * sync & other async
-        void __iomem    *gpmc_ecc_control;
+         */
-        void __iomem    *gpmc_ecc_size_config;
+        u32 t_avdp_r;   /* ADV low time (what about t_cer ?) */
-        void __iomem    *gpmc_ecc1_result;
+        u32 t_avdp_w;
-        void __iomem    *gpmc_bch_result0;
+        u32 t_aavdh;    /* address hold time */
+        u32 t_oeasu;    /* address setup to OE valid */
+        u32 t_aa;       /* access time from ADV assertion */
+        u32 t_iaa;      /* initial access time */
+        u32 t_oe;       /* access time from OE assertion */
+        u32 t_ce;       /* access time from CS asertion */
+        u32 t_rd_cycle; /* read cycle time */
+        u32 t_cez_r;    /* read CS deassertion to high Z */
+        u32 t_cez_w;    /* write CS deassertion to high Z */
+        u32 t_oez;      /* OE deassertion to high Z */
+        u32 t_weasu;    /* address setup to WE valid */
+        u32 t_wpl;      /* write assertion time */
+        u32 t_wph;      /* write deassertion time */
+        u32 t_wr_cycle; /* write cycle time */
+        u32 clk;
+        u32 t_bacc;     /* burst access valid clock to output delay */
+        u32 t_ces;      /* CS setup time to clk */
+        u32 t_avds;     /* ADV setup time to clk */
+        u32 t_avdh;     /* ADV hold time from clk */
+        u32 t_ach;      /* address hold time from clk */
+        u32 t_rdyo;     /* clk to ready valid */
+        u32 t_ce_rdyz;  /* XXX: description ?, or use t_cez instead */
+        u32 t_ce_avd;   /* CS on to ADV on delay */
+        /* XXX: check the possibility of combining
+         * cyc_aavhd_oe & cyc_aavdh_we
+         */
+        u8 cyc_aavdh_oe;/* read address hold time in cycles */
+        u8 cyc_aavdh_we;/* write address hold time in cycles */
+        u8 cyc_oe;      /* access time from OE assertion in cycles */
+        u8 cyc_wpl;     /* write deassertion time in cycles */
+        u32 cyc_iaa;    /* initial access time in cycles */
+        bool mux;       /* address & data muxed */
+        bool sync_write;/* synchronous write */
+        bool sync_read; /* synchronous read */
+        /* extra delays */
+        bool ce_xdelay;
+        bool avd_xdelay;
+        bool oe_xdelay;
+        bool we_xdelay;
 };
+extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
+                                struct gpmc_device_timings *dev_t);
 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
@@ -160,31 +203,14 @@ extern unsigned long gpmc_get_fclk_period(void);
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
 extern u32 gpmc_cs_read_reg(int cs, int idx);
-extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
+extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
-extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
-                                        unsigned int u32_count, int is_write);
-extern int gpmc_prefetch_reset(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern int gpmc_read_status(int cmd);
 extern int gpmc_cs_configure(int cs, int cmd, int wval);
-extern int gpmc_nand_read(int cs, int cmd);
-extern int gpmc_nand_write(int cs, int cmd, int wval);
-int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
-int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
-#ifdef CONFIG_ARCH_OMAP3
-int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors);
-int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
-                          int nerrors);
-int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc);
-int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc);
-#endif /* CONFIG_ARCH_OMAP3 */
 #endif
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index e003f2bba30c..ab7bf181a105 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -27,15 +27,13 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/omap_device.h>
+#include "omap_device.h"
 #include "hdq1w.h"
+#include "prm.h"
 #include "common.h"
-/* Maximum microseconds to wait for OMAP module to softreset */
-#define MAX_MODULE_SOFTRESET_WAIT       10000
 /**
 * omap_hdq1w_reset - reset the OMAP HDQ1W module
 * @oh: struct omap_hwmod *
diff --git a/arch/arm/mach-omap2/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h
index 0c1efc846d8d..c7e08d2a7a46 100644
--- a/arch/arm/mach-omap2/hdq1w.h
+++ b/arch/arm/mach-omap2/hdq1w.h
@@ -21,7 +21,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
 #define ARCH_ARM_MACH_OMAP2_HDQ1W_H
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 /*
 * XXX A future cleanup patch should modify
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 4d3a6324155f..4a964338992a 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,14 +14,14 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <linux/platform_data/gpio-omap.h>
-#include <plat/mmc.h>
+#include "soc.h"
-#include <plat/omap-pm.h>
+#include "omap_device.h"
-#include <plat/omap_device.h>
+#include "omap-pm.h"
 #include "mux.h"
+#include "mmc.h"
 #include "hsmmc.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 8763c8520dc2..1df9b5feda16 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -21,8 +21,8 @@
 #include <linux/err.h>
 #include <linux/hwspinlock.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/omap_device.h>
+#include "omap_device.h"
 static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
        .base_id = 0,
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index fc57e67b321f..fbb9b152cd5e 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -19,21 +19,23 @@
 *
 */
-#include <plat/i2c.h>
+#include "soc.h"
-#include "common.h"
+#include "omap_hwmod.h"
-#include <plat/omap_hwmod.h>
+#include "omap_device.h"
+#include "prm.h"
+#include "common.h"
 #include "mux.h"
+#include "i2c.h"
 /* In register I2C_CON, Bit 15 is the I2C enable bit */
 #define I2C_EN                                  BIT(15)
 #define OMAP2_I2C_CON_OFFSET                    0x24
 #define OMAP4_I2C_CON_OFFSET                    0xA4
-/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_OMAP_I2C_HWMOD_NAME_LEN     16
-#define MAX_MODULE_SOFTRESET_WAIT       10000
-void __init omap2_i2c_mux_pins(int bus_id)
+static void __init omap2_i2c_mux_pins(int bus_id)
 {
        char mux_name[sizeof("i2c2_scl.i2c2_scl")];
@@ -104,3 +106,62 @@ int omap_i2c_reset(struct omap_hwmod *oh)
        return 0;
 }
+static int __init omap_i2c_nr_ports(void)
+{
+        int ports = 0;
+        if (cpu_is_omap24xx())
+                ports = 2;
+        else if (cpu_is_omap34xx())
+                ports = 3;
+        else if (cpu_is_omap44xx())
+                ports = 4;
+        return ports;
+}
+static const char name[] = "omap_i2c";
+int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
+                                int bus_id)
+{
+        int l;
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+        struct omap_i2c_bus_platform_data *pdata;
+        struct omap_i2c_dev_attr *dev_attr;
+        if (bus_id > omap_i2c_nr_ports())
+                return -EINVAL;
+        omap2_i2c_mux_pins(bus_id);
+        l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
+        WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
+                "String buffer overflow in I2C%d device setup\n", bus_id);
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                        pr_err("Could not look up %s\n", oh_name);
+                        return -EEXIST;
+        }
+        pdata = i2c_pdata;
+        /*
+         * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
+         * use, and functionality implementation flags, up to the OMAP I2C
+         * driver via platform data
+         */
+        pdata->rev = oh->class->rev;
+        dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
+        pdata->flags = dev_attr->flags;
+        pdev = omap_device_build(name, bus_id, oh, pdata,
+                        sizeof(struct omap_i2c_bus_platform_data),
+                        NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
+        return PTR_RET(pdev);
+}
diff --git a/arch/arm/mach-omap2/i2c.h b/arch/arm/mach-omap2/i2c.h
new file mode 100644
index 000000000000..42b6f2e7d190
--- /dev/null
+++ b/arch/arm/mach-omap2/i2c.h
@@ -0,0 +1,42 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#include <plat/i2c.h>
+#ifndef __MACH_OMAP2_I2C_H
+#define __MACH_OMAP2_I2C_H
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+        u8      fifo_depth;
+        u32     flags;
+};
+int omap_i2c_reset(struct omap_hwmod *oh);
+#endif  /* __MACH_OMAP2_I2C_H */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index cf2362ccb234..45cc7ed4dd58 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -28,6 +28,9 @@
 #include "soc.h"
 #include "control.h"
+#define OMAP4_SILICON_TYPE_STANDARD             0x01
+#define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
 static unsigned int omap_revision;
 static const char *cpu_rev;
 u32 omap_features;
@@ -273,25 +276,11 @@ void __init omap4xxx_check_features(void)
 {
        u32 si_type;
-        if (cpu_is_omap443x())
+        si_type =
-                omap_features |= OMAP4_HAS_MPU_1GHZ;
+        (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
-        if (cpu_is_omap446x()) {
+        if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
-                si_type =
+                omap_features = OMAP4_HAS_PERF_SILICON;
-                        read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
-                switch ((si_type & (3 << 16)) >> 16) {
-                case 2:
-                        /* High performance device */
-                        omap_features |= OMAP4_HAS_MPU_1_5GHZ;
-                        break;
-                case 1:
-                default:
-                        /* Standard device */
-                        omap_features |= OMAP4_HAS_MPU_1_2GHZ;
-                        break;
-                }
-        }
 }
 void __init ti81xx_check_features(void)
@@ -559,11 +548,12 @@ void __init omap5xxx_check_revision(void)
 * detect the exact revision later on in omap2_detect_revision() once map_io
 * is done.
 */
-void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
+void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
 {
-        omap_revision = omap2_globals->class;
+        omap_revision = class;
-        tap_base = omap2_globals->tap;
+        tap_base = tap;
+        /* XXX What is this intended to do? */
        if (cpu_is_omap34xx())
                tap_prod_id = 0x0210;
        else
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 93d10de7129f..cfaed13d0040 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
 #include <linux/serial_reg.h>
-#include <plat/serial.h>
+#include <mach/serial.h>
 #define UART_OFFSET(addr)       ((addr) & 0x00ffffff)
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
deleted file mode 100644
index 5621cc59c9f4..000000000000
--- a/arch/arm/mach-omap2/include/mach/gpio.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/gpio.h
- */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
index 65fce44dce34..70eda00db7a4 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/mach-omap2/include/mach/serial.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/serial.h
- *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
@@ -10,11 +8,6 @@
 * GNU General Public License for more details.
 */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-#include <linux/init.h>
 /*
 * Memory entry used for the DEBUG_LL UART configuration, relative to
 * start of RAM. See also uncompress.h and debug-macro.S.
@@ -29,11 +22,6 @@
 */
 #define OMAP_UART_INFO_OFS      0x3ffc
-/* OMAP1 serial ports */
-#define OMAP1_UART1_BASE        0xfffb0000
-#define OMAP1_UART2_BASE        0xfffb0800
-#define OMAP1_UART3_BASE        0xfffb9800
 /* OMAP2 serial ports */
 #define OMAP2_UART1_BASE        0x4806a000
 #define OMAP2_UART2_BASE        0x4806c000
@@ -76,20 +64,14 @@
 #define ZOOM_UART_VIRT          0xfa400000
 #define OMAP_PORT_SHIFT         2
-#define OMAP7XX_PORT_SHIFT      0
 #define ZOOM_PORT_SHIFT         1
-#define OMAP1510_BASE_BAUD      (12000000/16)
-#define OMAP16XX_BASE_BAUD      (48000000/16)
 #define OMAP24XX_BASE_BAUD      (48000000/16)
 /*
 * DEBUG_LL port encoding stored into the UART1 scratchpad register by
 * decomp_setup in uncompress.h
 */
-#define OMAP1UART1              11
-#define OMAP1UART2              12
-#define OMAP1UART3              13
 #define OMAP2UART1              21
 #define OMAP2UART2              22
 #define OMAP2UART3              23
@@ -109,15 +91,6 @@
 #define OMAP5UART4              OMAP4UART4
 #define ZOOM_UART               95              /* Only on zoom2/3 */
-/* This is only used by 8250.c for omap1510 */
-#define is_omap_port(pt)        ({int __ret = 0;                        \
-                        if ((pt)->port.mapbase == OMAP1_UART1_BASE ||   \
-                            (pt)->port.mapbase == OMAP1_UART2_BASE ||   \
-                            (pt)->port.mapbase == OMAP1_UART3_BASE)     \
-                                __ret = 1;                              \
-                        __ret;                                          \
-                        })
 #ifndef __ASSEMBLER__
 struct omap_board_data;
@@ -128,5 +101,3 @@ extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
 extern void omap_serial_init_port(struct omap_board_data *bdata,
                struct omap_uart_port_info *platform_data);
 #endif
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
index 78e0557bfd4e..8e3546d3e041 100644
--- a/arch/arm/mach-omap2/include/mach/uncompress.h
+++ b/arch/arm/mach-omap2/include/mach/uncompress.h
@@ -1,5 +1,176 @@
 /*
- * arch/arm/mach-omap2/include/mach/uncompress.h
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
 */
-#include <plat/uncompress.h>
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <mach/serial.h>
+#define MDR1_MODE_MASK                  0x07
+volatile u8 *uart_base;
+int uart_shift;
+/*
+ * Store the DEBUG_LL uart number into memory.
+ * See also debug-macro.S, and serial.c for related code.
+ */
+static void set_omap_uart_info(unsigned char port)
+{
+        /*
+         * Get address of some.bss variable and round it down
+         * a la CONFIG_AUTO_ZRELADDR.
+         */
+        u32 ram_start = (u32)&uart_shift & 0xf8000000;
+        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
+        *uart_info = port;
+}
+static void putc(int c)
+{
+        if (!uart_base)
+                return;
+        /* Check for UART 16x mode */
+        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
+                return;
+        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
+                barrier();
+        uart_base[UART_TX << uart_shift] = c;
+}
+static inline void flush(void)
+{
+}
+/*
+ * Macros to configure UART1 and debug UART
+ */
+#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
+        if (machine_is_##mach()) {                                      \
+                uart_base = (volatile u8 *)(dbg_uart);                  \
+                uart_shift = (dbg_shft);                                \
+                port = (dbg_id);                                        \
+                set_omap_uart_info(port);                               \
+                break;                                                  \
+        }
+#define DEBUG_LL_OMAP2(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP2UART##p)
+#define DEBUG_LL_OMAP3(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP3UART##p)
+#define DEBUG_LL_OMAP4(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP4UART##p)
+#define DEBUG_LL_OMAP5(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP5UART##p)
+/* Zoom2/3 shift is different for UART1 and external port */
+#define DEBUG_LL_ZOOM(mach)                                             \
+        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+#define DEBUG_LL_TI81XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                TI81XXUART##p)
+#define DEBUG_LL_AM33XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                AM33XXUART##p)
+static inline void arch_decomp_setup(void)
+{
+        int port = 0;
+        /*
+         * Initialize the port based on the machine ID from the bootloader.
+         * Note that we're using macros here instead of switch statement
+         * as machine_is functions are optimized out for the boards that
+         * are not selected.
+         */
+        do {
+                /* omap2 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap_2430sdp);
+                DEBUG_LL_OMAP2(1, omap_apollon);
+                DEBUG_LL_OMAP2(1, omap_h4);
+                /* omap2 based boards using UART3 */
+                DEBUG_LL_OMAP2(3, nokia_n800);
+                DEBUG_LL_OMAP2(3, nokia_n810);
+                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
+                /* omap3 based boards using UART1 */
+                DEBUG_LL_OMAP2(1, omap3evm);
+                DEBUG_LL_OMAP3(1, omap_3430sdp);
+                DEBUG_LL_OMAP3(1, omap_3630sdp);
+                DEBUG_LL_OMAP3(1, omap3530_lv_som);
+                DEBUG_LL_OMAP3(1, omap3_torpedo);
+                /* omap3 based boards using UART3 */
+                DEBUG_LL_OMAP3(3, cm_t35);
+                DEBUG_LL_OMAP3(3, cm_t3517);
+                DEBUG_LL_OMAP3(3, cm_t3730);
+                DEBUG_LL_OMAP3(3, craneboard);
+                DEBUG_LL_OMAP3(3, devkit8000);
+                DEBUG_LL_OMAP3(3, igep0020);
+                DEBUG_LL_OMAP3(3, igep0030);
+                DEBUG_LL_OMAP3(3, nokia_rm680);
+                DEBUG_LL_OMAP3(3, nokia_rm696);
+                DEBUG_LL_OMAP3(3, nokia_rx51);
+                DEBUG_LL_OMAP3(3, omap3517evm);
+                DEBUG_LL_OMAP3(3, omap3_beagle);
+                DEBUG_LL_OMAP3(3, omap3_pandora);
+                DEBUG_LL_OMAP3(3, omap_ldp);
+                DEBUG_LL_OMAP3(3, overo);
+                DEBUG_LL_OMAP3(3, touchbook);
+                /* omap4 based boards using UART3 */
+                DEBUG_LL_OMAP4(3, omap_4430sdp);
+                DEBUG_LL_OMAP4(3, omap4_panda);
+                /* omap5 based boards using UART3 */
+                DEBUG_LL_OMAP5(3, omap5_sevm);
+                /* zoom2/3 external uart */
+                DEBUG_LL_ZOOM(omap_zoom2);
+                DEBUG_LL_ZOOM(omap_zoom3);
+                /* TI8168 base boards using UART3 */
+                DEBUG_LL_TI81XX(3, ti8168evm);
+                /* TI8148 base boards using UART1 */
+                DEBUG_LL_TI81XX(1, ti8148evm);
+                /* AM33XX base boards using UART1 */
+                DEBUG_LL_AM33XX(1, am335xevm);
+        } while (0);
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4234d28dc171..2c3fdd65387b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -25,14 +25,9 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
-#include <plat/sram.h>
+#include <linux/omap-dma.h>
-#include <plat/sdrc.h>
-#include <plat/serial.h>
-#include <plat/omap-pm.h>
-#include <plat/omap_hwmod.h>
-#include <plat/multi.h>
-#include <plat/dma.h>
+#include "omap_hwmod.h"
 #include "soc.h"
 #include "iomap.h"
 #include "voltage.h"
@@ -43,6 +38,21 @@
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
+#include "omap-pm.h"
+#include "sdrc.h"
+#include "control.h"
+#include "serial.h"
+#include "sram.h"
+#include "cm2xxx.h"
+#include "cm3xxx.h"
+#include "prm.h"
+#include "cm.h"
+#include "prcm_mpu44xx.h"
+#include "prminst44xx.h"
+#include "cminst44xx.h"
+#include "prm2xxx.h"
+#include "prm3xxx.h"
+#include "prm44xx.h"
 /*
 * The machine specific code may provide the extra mapping besides the
@@ -265,7 +275,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
 #endif
 #ifdef CONFIG_SOC_OMAP2420
-void __init omap242x_map_common_io(void)
+void __init omap242x_map_io(void)
 {
        iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
        iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
@@ -273,7 +283,7 @@ void __init omap242x_map_common_io(void)
 #endif
 #ifdef CONFIG_SOC_OMAP2430
-void __init omap243x_map_common_io(void)
+void __init omap243x_map_io(void)
 {
        iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
        iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
@@ -281,28 +291,28 @@ void __init omap243x_map_common_io(void)
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-void __init omap34xx_map_common_io(void)
+void __init omap3_map_io(void)
 {
        iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 }
 #endif
 #ifdef CONFIG_SOC_TI81XX
-void __init omapti81xx_map_common_io(void)
+void __init ti81xx_map_io(void)
 {
        iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
 }
 #endif
 #ifdef CONFIG_SOC_AM33XX
-void __init omapam33xx_map_common_io(void)
+void __init am33xx_map_io(void)
 {
        iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 }
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-void __init omap44xx_map_common_io(void)
+void __init omap4_map_io(void)
 {
        iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
        omap_barriers_init();
@@ -310,7 +320,7 @@ void __init omap44xx_map_common_io(void)
 #endif
 #ifdef CONFIG_SOC_OMAP5
-void __init omap5_map_common_io(void)
+void __init omap5_map_io(void)
 {
        iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
 }
@@ -354,11 +364,6 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
        return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 }
-static void __init omap_common_init_early(void)
-{
-        omap_init_consistent_dma_size();
-}
 static void __init omap_hwmod_init_postsetup(void)
 {
        u8 postsetup_state;
@@ -377,9 +382,16 @@ static void __init omap_hwmod_init_postsetup(void)
 #ifdef CONFIG_SOC_OMAP2420
 void __init omap2420_init_early(void)
 {
-        omap2_set_globals_242x();
+        omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
+        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
+                               OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
+        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
+        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
        omap2xxx_check_revision();
-        omap_common_init_early();
+        omap2xxx_prm_init();
+        omap2xxx_cm_init();
        omap2xxx_voltagedomains_init();
        omap242x_powerdomains_init();
        omap242x_clockdomains_init();
@@ -393,15 +405,23 @@ void __init omap2420_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap2_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 #endif
 #ifdef CONFIG_SOC_OMAP2430
 void __init omap2430_init_early(void)
 {
-        omap2_set_globals_243x();
+        omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
+        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
+                               OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
+        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
+        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
        omap2xxx_check_revision();
-        omap_common_init_early();
+        omap2xxx_prm_init();
+        omap2xxx_cm_init();
        omap2xxx_voltagedomains_init();
        omap243x_powerdomains_init();
        omap243x_clockdomains_init();
@@ -415,6 +435,7 @@ void __init omap2430_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap2_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 #endif
@@ -425,10 +446,17 @@ void __init omap2430_init_late(void)
 #ifdef CONFIG_ARCH_OMAP3
 void __init omap3_init_early(void)
 {
-        omap2_set_globals_3xxx();
+        omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
+        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
+                               OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
+        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
+        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
        omap3xxx_check_revision();
        omap3xxx_check_features();
-        omap_common_init_early();
+        omap3xxx_prm_init();
+        omap3xxx_cm_init();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        omap3xxx_clockdomains_init();
@@ -459,10 +487,14 @@ void __init am35xx_init_early(void)
 void __init ti81xx_init_early(void)
 {
-        omap2_set_globals_ti81xx();
+        omap2_set_globals_tap(OMAP343X_CLASS,
+                              OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
+        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
+        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        ti81xx_check_features();
-        omap_common_init_early();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        omap3xxx_clockdomains_init();
@@ -476,6 +508,7 @@ void __init omap3_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap3_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 void __init omap3430_init_late(void)
@@ -483,6 +516,7 @@ void __init omap3430_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap3_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 void __init omap35xx_init_late(void)
@@ -490,6 +524,7 @@ void __init omap35xx_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap3_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 void __init omap3630_init_late(void)
@@ -497,6 +532,7 @@ void __init omap3630_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap3_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 void __init am35xx_init_late(void)
@@ -504,6 +540,7 @@ void __init am35xx_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap3_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 void __init ti81xx_init_late(void)
@@ -511,16 +548,21 @@ void __init ti81xx_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap3_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 #endif
 #ifdef CONFIG_SOC_AM33XX
 void __init am33xx_init_early(void)
 {
-        omap2_set_globals_am33xx();
+        omap2_set_globals_tap(AM335X_CLASS,
+                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
+        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
+        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        ti81xx_check_features();
-        omap_common_init_early();
        am33xx_voltagedomains_init();
        am33xx_powerdomains_init();
        am33xx_clockdomains_init();
@@ -533,10 +575,19 @@ void __init am33xx_init_early(void)
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap4430_init_early(void)
 {
-        omap2_set_globals_443x();
+        omap2_set_globals_tap(OMAP443X_CLASS,
+                              OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
+        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
+                                  OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
+        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
+        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
+                             OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
+        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
+        omap_prm_base_init();
+        omap_cm_base_init();
        omap4xxx_check_revision();
        omap4xxx_check_features();
-        omap_common_init_early();
+        omap44xx_prm_init();
        omap44xx_voltagedomains_init();
        omap44xx_powerdomains_init();
        omap44xx_clockdomains_init();
@@ -550,15 +601,24 @@ void __init omap4430_init_late(void)
        omap_mux_late_init();
        omap2_common_pm_late_init();
        omap4_pm_init();
+        omap2_clk_enable_autoidle_all();
 }
 #endif
 #ifdef CONFIG_SOC_OMAP5
 void __init omap5_init_early(void)
 {
-        omap2_set_globals_5xxx();
+        omap2_set_globals_tap(OMAP54XX_CLASS,
+                              OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
+        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+                                  OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
+        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
+        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
+                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
+        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap_prm_base_init();
+        omap_cm_base_init();
        omap5xxx_check_revision();
-        omap_common_init_early();
 }
 #endif
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
deleted file mode 100644
index eefc37912ef3..000000000000
--- a/arch/arm/mach-omap2/iommu2.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * omap iommu: omap2/3 architecture specific functions
- *
- * Copyright (C) 2008-2009 Nokia Corporation
- *
- * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
- *              Paul Mundt and Toshihiro Kobayashi
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/stringify.h>
-#include <plat/iommu.h>
-/*
- * omap2 architecture specific register bit definitions
- */
-#define IOMMU_ARCH_VERSION      0x00000011
-/* SYSCONF */
-#define MMU_SYS_IDLE_SHIFT      3
-#define MMU_SYS_IDLE_FORCE      (0 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_IDLE_NONE       (1 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_IDLE_SMART      (2 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_IDLE_MASK       (3 << MMU_SYS_IDLE_SHIFT)
-#define MMU_SYS_SOFTRESET       (1 << 1)
-#define MMU_SYS_AUTOIDLE        1
-/* SYSSTATUS */
-#define MMU_SYS_RESETDONE       1
-/* IRQSTATUS & IRQENABLE */
-#define MMU_IRQ_MULTIHITFAULT   (1 << 4)
-#define MMU_IRQ_TABLEWALKFAULT  (1 << 3)
-#define MMU_IRQ_EMUMISS         (1 << 2)
-#define MMU_IRQ_TRANSLATIONFAULT        (1 << 1)
-#define MMU_IRQ_TLBMISS         (1 << 0)
-#define __MMU_IRQ_FAULT         \
-        (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
-#define MMU_IRQ_MASK            \
-        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
-#define MMU_IRQ_TWL_MASK        (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
-#define MMU_IRQ_TLB_MISS_MASK   (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
-/* MMU_CNTL */
-#define MMU_CNTL_SHIFT          1
-#define MMU_CNTL_MASK           (7 << MMU_CNTL_SHIFT)
-#define MMU_CNTL_EML_TLB        (1 << 3)
-#define MMU_CNTL_TWL_EN         (1 << 2)
-#define MMU_CNTL_MMU_EN         (1 << 1)
-#define get_cam_va_mask(pgsz)                           \
-        (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
-         ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
-         ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
-         ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
-static void __iommu_set_twl(struct omap_iommu *obj, bool on)
-{
-        u32 l = iommu_read_reg(obj, MMU_CNTL);
-        if (on)
-                iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
-        else
-                iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
-        l &= ~MMU_CNTL_MASK;
-        if (on)
-                l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
-        else
-                l |= (MMU_CNTL_MMU_EN);
-        iommu_write_reg(obj, l, MMU_CNTL);
-}
-static int omap2_iommu_enable(struct omap_iommu *obj)
-{
-        u32 l, pa;
-        unsigned long timeout;
-        if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
-                return -EINVAL;
-        pa = virt_to_phys(obj->iopgd);
-        if (!IS_ALIGNED(pa, SZ_16K))
-                return -EINVAL;
-        iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
-        timeout = jiffies + msecs_to_jiffies(20);
-        do {
-                l = iommu_read_reg(obj, MMU_SYSSTATUS);
-                if (l & MMU_SYS_RESETDONE)
-                        break;
-        } while (!time_after(jiffies, timeout));
-        if (!(l & MMU_SYS_RESETDONE)) {
-                dev_err(obj->dev, "can't take mmu out of reset\n");
-                return -ENODEV;
-        }
-        l = iommu_read_reg(obj, MMU_REVISION);
-        dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
-                 (l >> 4) & 0xf, l & 0xf);
-        l = iommu_read_reg(obj, MMU_SYSCONFIG);
-        l &= ~MMU_SYS_IDLE_MASK;
-        l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
-        iommu_write_reg(obj, l, MMU_SYSCONFIG);
-        iommu_write_reg(obj, pa, MMU_TTB);
-        __iommu_set_twl(obj, true);
-        return 0;
-}
-static void omap2_iommu_disable(struct omap_iommu *obj)
-{
-        u32 l = iommu_read_reg(obj, MMU_CNTL);
-        l &= ~MMU_CNTL_MASK;
-        iommu_write_reg(obj, l, MMU_CNTL);
-        iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
-        dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
-}
-static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
-{
-        __iommu_set_twl(obj, false);
-}
-static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
-{
-        u32 stat, da;
-        u32 errs = 0;
-        stat = iommu_read_reg(obj, MMU_IRQSTATUS);
-        stat &= MMU_IRQ_MASK;
-        if (!stat) {
-                *ra = 0;
-                return 0;
-        }
-        da = iommu_read_reg(obj, MMU_FAULT_AD);
-        *ra = da;
-        if (stat & MMU_IRQ_TLBMISS)
-                errs |= OMAP_IOMMU_ERR_TLB_MISS;
-        if (stat & MMU_IRQ_TRANSLATIONFAULT)
-                errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
-        if (stat & MMU_IRQ_EMUMISS)
-                errs |= OMAP_IOMMU_ERR_EMU_MISS;
-        if (stat & MMU_IRQ_TABLEWALKFAULT)
-                errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
-        if (stat & MMU_IRQ_MULTIHITFAULT)
-                errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
-        iommu_write_reg(obj, stat, MMU_IRQSTATUS);
-        return errs;
-}
-static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
-{
-        cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
-        cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
-}
-static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
-{
-        iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
-        iommu_write_reg(obj, cr->ram, MMU_RAM);
-}
-static u32 omap2_cr_to_virt(struct cr_regs *cr)
-{
-        u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
-        u32 mask = get_cam_va_mask(cr->cam & page_size);
-        return cr->cam & mask;
-}
-static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
-                                                struct iotlb_entry *e)
-{
-        struct cr_regs *cr;
-        if (e->da & ~(get_cam_va_mask(e->pgsz))) {
-                dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
-                        e->da);
-                return ERR_PTR(-EINVAL);
-        }
-        cr = kmalloc(sizeof(*cr), GFP_KERNEL);
-        if (!cr)
-                return ERR_PTR(-ENOMEM);
-        cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
-        cr->ram = e->pa | e->endian | e->elsz | e->mixed;
-        return cr;
-}
-static inline int omap2_cr_valid(struct cr_regs *cr)
-{
-        return cr->cam & MMU_CAM_V;
-}
-static u32 omap2_get_pte_attr(struct iotlb_entry *e)
-{
-        u32 attr;
-        attr = e->mixed << 5;
-        attr |= e->endian;
-        attr |= e->elsz >> 3;
-        attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
-                        (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
-        return attr;
-}
-static ssize_t
-omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
-{
-        char *p = buf;
-        /* FIXME: Need more detail analysis of cam/ram */
-        p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
-                                        (cr->cam & MMU_CAM_P) ? 1 : 0);
-        return p - buf;
-}
-#define pr_reg(name)                                                    \
-        do {                                                            \
-                ssize_t bytes;                                          \
-                const char *str = "%20s: %08x\n";                       \
-                const int maxcol = 32;                                  \
-                bytes = snprintf(p, maxcol, str, __stringify(name),     \
-                                 iommu_read_reg(obj, MMU_##name));      \
-                p += bytes;                                             \
-                len -= bytes;                                           \
-                if (len < maxcol)                                       \
-                        goto out;                                       \
-        } while (0)
-static ssize_t
-omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
-{
-        char *p = buf;
-        pr_reg(REVISION);
-        pr_reg(SYSCONFIG);
-        pr_reg(SYSSTATUS);
-        pr_reg(IRQSTATUS);
-        pr_reg(IRQENABLE);
-        pr_reg(WALKING_ST);
-        pr_reg(CNTL);
-        pr_reg(FAULT_AD);
-        pr_reg(TTB);
-        pr_reg(LOCK);
-        pr_reg(LD_TLB);
-        pr_reg(CAM);
-        pr_reg(RAM);
-        pr_reg(GFLUSH);
-        pr_reg(FLUSH_ENTRY);
-        pr_reg(READ_CAM);
-        pr_reg(READ_RAM);
-        pr_reg(EMU_FAULT_AD);
-out:
-        return p - buf;
-}
-static void omap2_iommu_save_ctx(struct omap_iommu *obj)
-{
-        int i;
-        u32 *p = obj->ctx;
-        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
-                p[i] = iommu_read_reg(obj, i * sizeof(u32));
-                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
-        }
-        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
-}
-static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
-{
-        int i;
-        u32 *p = obj->ctx;
-        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
-                iommu_write_reg(obj, p[i], i * sizeof(u32));
-                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
-        }
-        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
-}
-static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
-{
-        e->da           = cr->cam & MMU_CAM_VATAG_MASK;
-        e->pa           = cr->ram & MMU_RAM_PADDR_MASK;
-        e->valid        = cr->cam & MMU_CAM_V;
-        e->pgsz         = cr->cam & MMU_CAM_PGSZ_MASK;
-        e->endian       = cr->ram & MMU_RAM_ENDIAN_MASK;
-        e->elsz         = cr->ram & MMU_RAM_ELSZ_MASK;
-        e->mixed        = cr->ram & MMU_RAM_MIXED;
-}
-static const struct iommu_functions omap2_iommu_ops = {
-        .version        = IOMMU_ARCH_VERSION,
-        .enable         = omap2_iommu_enable,
-        .disable        = omap2_iommu_disable,
-        .set_twl        = omap2_iommu_set_twl,
-        .fault_isr      = omap2_iommu_fault_isr,
-        .tlb_read_cr    = omap2_tlb_read_cr,
-        .tlb_load_cr    = omap2_tlb_load_cr,
-        .cr_to_e        = omap2_cr_to_e,
-        .cr_to_virt     = omap2_cr_to_virt,
-        .alloc_cr       = omap2_alloc_cr,
-        .cr_valid       = omap2_cr_valid,
-        .dump_cr        = omap2_dump_cr,
-        .get_pte_attr   = omap2_get_pte_attr,
-        .save_ctx       = omap2_iommu_save_ctx,
-        .restore_ctx    = omap2_iommu_restore_ctx,
-        .dump_ctx       = omap2_iommu_dump_ctx,
-};
-static int __init omap2_iommu_init(void)
-{
-        return omap_install_iommu_arch(&omap2_iommu_ops);
-}
-module_init(omap2_iommu_init);
-static void __exit omap2_iommu_exit(void)
-{
-        omap_uninstall_iommu_arch(&omap2_iommu_ops);
-}
-module_exit(omap2_iommu_exit);
-MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
-MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
-MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 37f8f948047b..df49f2a49461 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -19,16 +19,17 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dma.h>
-#include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/omap-dma.h>
+#include "omap_device.h"
 /*
 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
 */
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
 static int omap3_enable_st_clock(unsigned int id, bool enable)
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
new file mode 100644
index 000000000000..0cd4b089da9c
--- /dev/null
+++ b/arch/arm/mach-omap2/mmc.h
@@ -0,0 +1,23 @@
+#include <linux/mmc/host.h>
+#include <linux/platform_data/mmc-omap.h>
+#define OMAP24XX_NR_MMC         2
+#define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
+#define OMAP2_MMC1_BASE         0x4809c000
+#define OMAP4_MMC_REG_OFFSET    0x100
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
+#else
+static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
+{
+}
+#endif
+struct omap_hwmod;
+int omap_msdi_reset(struct omap_hwmod *oh);
+/* called from board-specific card detection service routine */
+extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
+                                        int is_closed);
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 9e57b4aadb06..aafdd4ca9f4f 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -25,13 +25,13 @@
 #include <linux/err.h>
 #include <linux/platform_data/gpio-omap.h>
-#include <plat/omap_hwmod.h>
+#include "prm.h"
-#include <plat/omap_device.h>
-#include <plat/mmc.h>
 #include "common.h"
 #include "control.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
 #include "mux.h"
+#include "mmc.h"
 /*
 * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
@@ -44,9 +44,6 @@
 #define MSDI_CON_CLKD_MASK                      (0x3f << 0)
 #define MSDI_CON_CLKD_SHIFT                     0
-/* Maximum microseconds to wait for OMAP module to softreset */
-#define MAX_MODULE_SOFTRESET_WAIT       10000
 /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
 #define MSDI_TARGET_RESET_CLKD          0x3ff
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 701e17cba468..26126343d6ac 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -36,8 +36,9 @@
 #include <linux/interrupt.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
+#include "soc.h"
 #include "control.h"
 #include "mux.h"
 #include "prm.h"
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 502e3135aad3..0ea09faf327b 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,6 +18,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include "omap44xx.h"
        __CPUINIT
 /* Physical address needed since MMU not enabled yet on secondary core */
@@ -64,3 +66,39 @@ hold:	ldr	r12,=0x103
        b       secondary_startup
 ENDPROC(omap_secondary_startup)
+ENTRY(omap_secondary_startup_4460)
+hold_2: ldr     r12,=0x103
+        dsb
+        smc     #0                      @ read from AuxCoreBoot0
+        mov     r0, r0, lsr #9
+        mrc     p15, 0, r4, c0, c0, 5
+        and     r4, r4, #0x0f
+        cmp     r0, r4
+        bne     hold_2
+        /*
+         * GIC distributor control register has changed between
+         * CortexA9 r1pX and r2pX. The Control Register secure
+         * banked version is now composed of 2 bits:
+         * bit 0 == Secure Enable
+         * bit 1 == Non-Secure Enable
+         * The Non-Secure banked register has not changed
+         * Because the ROM Code is based on the r1pX GIC, the CPU1
+         * GIC restoration will cause a problem to CPU0 Non-Secure SW.
+         * The workaround must be:
+         * 1) Before doing the CPU1 wakeup, CPU0 must disable
+         * the GIC distributor
+         * 2) CPU1 must re-enable the GIC distributor on
+         * it's wakeup path.
+         */
+        ldr     r1, =OMAP44XX_GIC_DIST_BASE
+        ldr     r0, [r1]
+        orr     r0, #1
+        str     r0, [r1]
+        /*
+         * we've been released from the wait loop,secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+ENDPROC(omap_secondary_startup_4460)
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index df298d46707c..a6a4ff8744b7 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -13,7 +13,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <plat/iommu.h>
+#include <linux/platform_data/iommu-omap.h>
 #include "soc.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index ff4e6a0e9c7c..aac46bfdbeb2 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -50,6 +50,7 @@
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "soc.h"
 #include "common.h"
 #include "omap44xx.h"
 #include "omap4-sar-layout.h"
@@ -67,6 +68,7 @@ struct omap4_cpu_pm_info {
        void __iomem *scu_sar_addr;
        void __iomem *wkup_sar_addr;
        void __iomem *l2x0_sar_addr;
+        void (*secondary_startup)(void);
 };
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
@@ -299,6 +301,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 {
        unsigned int cpu_state = 0;
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
        if (omap_rev() == OMAP4430_REV_ES1_0)
                return -ENXIO;
@@ -308,7 +311,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
        clear_cpu_prev_pwrst(cpu);
        set_cpu_next_pwrst(cpu, power_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
+        set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
        scu_pwrst_prepare(cpu, power_state);
        /*
@@ -359,6 +362,11 @@ int __init omap4_mpuss_init(void)
        pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
        pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+        if (cpu_is_omap446x())
+                pm_info->secondary_startup = omap_secondary_startup_4460;
+        else
+                pm_info->secondary_startup = omap_secondary_startup;
        pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
        if (!pm_info->pwrdm) {
                pr_err("Lookup failed for CPU1 pwrdm\n");
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/mach-omap2/omap-pm-noop.c
index 9722f418ae1f..6a3be2bebddb 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/mach-omap2/omap-pm-noop.c
@@ -22,9 +22,8 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
-/* Interface documentation is in mach/omap-pm.h */
+#include "omap_device.h"
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
-#include <plat/omap_device.h>
 static bool off_mode_enabled;
 static int dummy_context_loss_counter;
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/mach-omap2/omap-pm.h
index 67faa7b8fe92..67faa7b8fe92 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/mach-omap2/omap-pm.h
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index e089e4d1ae38..b970440cffca 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -18,7 +18,6 @@
 #include <asm/cacheflush.h>
 #include <asm/memblock.h>
-#include <plat/omap-secure.h>
 #include "omap-secure.h"
 static phys_addr_t omap_secure_memblock_base;
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index c90a43589abe..0e729170c46b 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -52,6 +52,13 @@ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
                                u32 arg1, u32 arg2, u32 arg3, u32 arg4);
 extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
 extern phys_addr_t omap_secure_ram_mempool_base(void);
+extern int omap_secure_ram_reserve_memblock(void);
+#ifdef CONFIG_OMAP4_ERRATA_I688
+extern int omap_barrier_reserve_memblock(void);
+#else
+static inline void omap_barrier_reserve_memblock(void)
+{ }
+#endif
 #endif /* __ASSEMBLER__ */
 #endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 4d05fa8a4e48..cd42d921940d 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -32,6 +32,7 @@
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
+#include "pm.h"
 #define CPU_MASK                0xff0ffff0
 #define CPU_CORTEX_A9           0x410FC090
@@ -39,6 +40,8 @@
 #define OMAP5_CORE_COUNT        0x2
+u16 pm44xx_errata;
 /* SCU base address */
 static void __iomem *scu_base;
@@ -118,8 +121,37 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         *      4.3.4.2 Power States of CPU0 and CPU1
         */
        if (booted) {
+                /*
+                 * GIC distributor control register has changed between
+                 * CortexA9 r1pX and r2pX. The Control Register secure
+                 * banked version is now composed of 2 bits:
+                 * bit 0 == Secure Enable
+                 * bit 1 == Non-Secure Enable
+                 * The Non-Secure banked register has not changed
+                 * Because the ROM Code is based on the r1pX GIC, the CPU1
+                 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
+                 * The workaround must be:
+                 * 1) Before doing the CPU1 wakeup, CPU0 must disable
+                 * the GIC distributor
+                 * 2) CPU1 must re-enable the GIC distributor on
+                 * it's wakeup path.
+                 */
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
+                        local_irq_disable();
+                        gic_dist_disable();
+                }
                clkdm_wakeup(cpu1_clkdm);
                clkdm_allow_idle(cpu1_clkdm);
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
+                        while (gic_dist_disabled()) {
+                                udelay(1);
+                                cpu_relax();
+                        }
+                        gic_timer_retrigger();
+                        local_irq_enable();
+                }
        } else {
                dsb_sev();
                booted = true;
@@ -138,7 +170,14 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
 static void __init wakeup_secondary(void)
 {
+        void *startup_addr = omap_secondary_startup;
        void __iomem *base = omap_get_wakeupgen_base();
+        if (cpu_is_omap446x()) {
+                startup_addr = omap_secondary_startup_4460;
+                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
+        }
        /*
         * Write the address of secondary startup routine into the
         * AuxCoreBoot1 where ROM code will jump and start executing
@@ -146,7 +185,7 @@ static void __init wakeup_secondary(void)
         * A barrier is added to ensure that write buffer is drained
         */
        if (omap_secure_apis_support())
-                omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
        else
                __raw_writel(virt_to_phys(omap5_secondary_startup),
                                                base + OMAP_AUX_CORE_BOOT_1);
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
new file mode 100644
index 000000000000..be6bc89ab1e8
--- /dev/null
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -0,0 +1,65 @@
+/*
+ * omap2-restart.c - code common to all OMAP2xxx machines.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include "common.h"
+#include "prm2xxx.h"
+/*
+ * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set
+ * clock and the sys_ck.  Used during the reset process
+ */
+static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck;
+/* Reboot handling */
+/**
+ * omap2xxx_restart - Set DPLL to bypass mode for reboot to work
+ *
+ * Set the DPLL to bypass so that reboot completes successfully.  No
+ * return value.
+ */
+void omap2xxx_restart(char mode, const char *cmd)
+{
+        u32 rate;
+        rate = clk_get_rate(reset_sys_ck);
+        clk_set_rate(reset_virt_prcm_set_ck, rate);
+        /* XXX Should save the cmd argument for use after the reboot */
+        omap2xxx_prm_dpll_reset(); /* never returns */
+        while (1);
+}
+/**
+ * omap2xxx_common_look_up_clks_for_reset - look up clocks needed for restart
+ *
+ * Some clocks need to be looked up in advance for the SoC restart
+ * operation to work - see omap2xxx_restart().  Returns -EINVAL upon
+ * error or 0 upon success.
+ */
+static int __init omap2xxx_common_look_up_clks_for_reset(void)
+{
+        reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set");
+        if (IS_ERR(reset_virt_prcm_set_ck))
+                return -EINVAL;
+        reset_sys_ck = clk_get(NULL, "sys_ck");
+        if (IS_ERR(reset_sys_ck))
+                return -EINVAL;
+        return 0;
+}
+core_initcall(omap2xxx_common_look_up_clks_for_reset);
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
new file mode 100644
index 000000000000..923c582189e5
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -0,0 +1,36 @@
+/*
+ * omap3-restart.c - Code common to all OMAP3xxx machines.
+ *
+ * Copyright (C) 2009, 2012 Texas Instruments
+ * Copyright (C) 2010 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include "iomap.h"
+#include "common.h"
+#include "control.h"
+#include "prm3xxx.h"
+/* Global address base setup code */
+/**
+ * omap3xxx_restart - trigger a software restart of the SoC
+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
+ * @cmd: passed from the userspace program rebooting the system (if provided)
+ *
+ * Resets the SoC.  For @cmd, see the 'reboot' syscall in
+ * kernel/sys.c.  No return value.
+ */
+void omap3xxx_restart(char mode, const char *cmd)
+{
+        omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
+        omap3xxx_prm_dpll3_reset(); /* never returns */
+        while (1);
+}
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index e1f289748c5d..6897ae21bb82 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
 #include <linux/of_irq.h>
@@ -24,23 +25,29 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
+#include <asm/smp_twd.h>
-#include <plat/sram.h>
-#include <plat/omap-secure.h>
-#include <plat/mmc.h>
 #include "omap-wakeupgen.h"
 #include "soc.h"
+#include "iomap.h"
 #include "common.h"
+#include "mmc.h"
 #include "hsmmc.h"
+#include "prminst44xx.h"
+#include "prcm_mpu44xx.h"
 #include "omap4-sar-layout.h"
+#include "omap-secure.h"
+#include "sram.h"
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
 #endif
 static void __iomem *sar_ram_base;
+static void __iomem *gic_dist_base_addr;
+static void __iomem *twd_base;
+#define IRQ_LOCALTIMER          29
 #ifdef CONFIG_OMAP4_ERRATA_I688
 /* Used to implement memory barrier on DRAM path */
@@ -95,12 +102,14 @@ void __init omap_barriers_init(void)
 void __init gic_init_irq(void)
 {
        void __iomem *omap_irq_base;
-        void __iomem *gic_dist_base_addr;
        /* Static mapping, never released */
        gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
        BUG_ON(!gic_dist_base_addr);
+        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
+        BUG_ON(!twd_base);
        /* Static mapping, never released */
        omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
        BUG_ON(!omap_irq_base);
@@ -110,6 +119,38 @@ void __init gic_init_irq(void)
        gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 }
+void gic_dist_disable(void)
+{
+        if (gic_dist_base_addr)
+                __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
+}
+bool gic_dist_disabled(void)
+{
+        return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
+}
+void gic_timer_retrigger(void)
+{
+        u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
+        u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
+        u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+        if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
+                /*
+                 * The local timer interrupt got lost while the distributor was
+                 * disabled.  Ack the pending interrupt, and retrigger it.
+                 */
+                pr_warn("%s: lost localtimer interrupt\n", __func__);
+                __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+                if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
+                        __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
+                        twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
+                        __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
+                }
+        }
+}
 #ifdef CONFIG_CACHE_L2X0
 void __iomem *omap4_get_l2cache_base(void)
@@ -281,3 +322,19 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
        return 0;
 }
 #endif
+/**
+ * omap44xx_restart - trigger a software restart of the SoC
+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
+ * @cmd: passed from the userspace program rebooting the system (if provided)
+ *
+ * Resets the SoC.  For @cmd, see the 'reboot' syscall in
+ * kernel/sys.c.  No return value.
+ */
+void omap44xx_restart(char mode, const char *cmd)
+{
+        /* XXX Should save 'cmd' into scratchpad for use after reboot */
+        omap4_prminst_global_warm_sw_reset(); /* never returns */
+        while (1);
+}
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 7a7d1f2a65e9..e065daa537c0 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -89,9 +89,8 @@
 #include <linux/of.h>
 #include <linux/notifier.h>
-#include <plat/omap_device.h>
+#include "omap_device.h"
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/clock.h>
 /* These parameters are passed to _omap_device_{de,}activate() */
 #define USE_WAKEUP_LAT                  0
@@ -442,19 +441,21 @@ int omap_device_get_context_loss_count(struct platform_device *pdev)
 /**
 * omap_device_count_resources - count number of struct resource entries needed
 * @od: struct omap_device *
+ * @flags: Type of resources to include when counting (IRQ/DMA/MEM)
 *
 * Count the number of struct resource entries needed for this
 * omap_device @od.  Used by omap_device_build_ss() to determine how
 * much memory to allocate before calling
 * omap_device_fill_resources().  Returns the count.
 */
-static int omap_device_count_resources(struct omap_device *od)
+static int omap_device_count_resources(struct omap_device *od,
+                                       unsigned long flags)
 {
        int c = 0;
        int i;
        for (i = 0; i < od->hwmods_cnt; i++)
-                c += omap_hwmod_count_resources(od->hwmods[i]);
+                c += omap_hwmod_count_resources(od->hwmods[i], flags);
        pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
                 od->pdev->name, c, od->hwmods_cnt);
@@ -558,52 +559,73 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
        od->hwmods = hwmods;
        od->pdev = pdev;
-        res_count = omap_device_count_resources(od);
        /*
+         * Non-DT Boot:
+         *   Here, pdev->num_resources = 0, and we should get all the
+         *   resources from hwmod.
+         *
         * DT Boot:
         *   OF framework will construct the resource structure (currently
         *   does for MEM & IRQ resource) and we should respect/use these
         *   resources, killing hwmod dependency.
         *   If pdev->num_resources > 0, we assume that MEM & IRQ resources
         *   have been allocated by OF layer already (through DTB).
-         *
+         *   As preparation for the future we examine the OF provided resources
-         * Non-DT Boot:
+         *   to see if we have DMA resources provided already. In this case
-         *   Here, pdev->num_resources = 0, and we should get all the
+         *   there is no need to update the resources for the device, we use the
-         *   resources from hwmod.
+         *   OF provided ones.
         *
         * TODO: Once DMA resource is available from OF layer, we should
         *   kill filling any resources from hwmod.
         */
-        if (res_count > pdev->num_resources) {
+        if (!pdev->num_resources) {
-                /* Allocate resources memory to account for new resources */
+                /* Count all resources for the device */
-                res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
+                res_count = omap_device_count_resources(od, IORESOURCE_IRQ |
-                if (!res)
+                                                            IORESOURCE_DMA |
-                        goto oda_exit3;
+                                                            IORESOURCE_MEM);
+        } else {
-                /*
+                /* Take a look if we already have DMA resource via DT */
-                 * If pdev->num_resources > 0, then assume that,
+                for (i = 0; i < pdev->num_resources; i++) {
-                 * MEM and IRQ resources will only come from DT and only
+                        struct resource *r = &pdev->resource[i];
-                 * fill DMA resource from hwmod layer.
-                 */
+                        /* We have it, no need to touch the resources */
-                if (pdev->num_resources && pdev->resource) {
+                        if (r->flags == IORESOURCE_DMA)
-                        dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
+                                goto have_everything;
-                                __func__, res_count);
-                        memcpy(res, pdev->resource,
-                               sizeof(struct resource) * pdev->num_resources);
-                        _od_fill_dma_resources(od, &res[pdev->num_resources]);
-                } else {
-                        dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
-                                __func__, res_count);
-                        omap_device_fill_resources(od, res);
                }
+                /* Count only DMA resources for the device */
+                res_count = omap_device_count_resources(od, IORESOURCE_DMA);
+                /* The device has no DMA resource, no need for update */
+                if (!res_count)
+                        goto have_everything;
-                ret = platform_device_add_resources(pdev, res, res_count);
+                res_count += pdev->num_resources;
-                kfree(res);
+        }
-                if (ret)
+        /* Allocate resources memory to account for new resources */
-                        goto oda_exit3;
+        res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
+        if (!res)
+                goto oda_exit3;
+        if (!pdev->num_resources) {
+                dev_dbg(&pdev->dev, "%s: using %d resources from hwmod\n",
+                        __func__, res_count);
+                omap_device_fill_resources(od, res);
+        } else {
+                dev_dbg(&pdev->dev,
+                        "%s: appending %d DMA resources from hwmod\n",
+                        __func__, res_count - pdev->num_resources);
+                memcpy(res, pdev->resource,
+                       sizeof(struct resource) * pdev->num_resources);
+                _od_fill_dma_resources(od, &res[pdev->num_resources]);
        }
+        ret = platform_device_add_resources(pdev, res, res_count);
+        kfree(res);
+        if (ret)
+                goto oda_exit3;
+have_everything:
        if (!pm_lats) {
                pm_lats = omap_default_latency;
                pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index 106f50665804..0933c599bf89 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -34,7 +34,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 extern struct dev_pm_domain omap_device_pm_domain;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 87cc6d058de2..4653efb87a27 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -130,7 +130,7 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/io.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/list.h>
@@ -139,27 +139,25 @@
 #include <linux/slab.h>
 #include <linux/bootmem.h>
-#include <plat/clock.h>
+#include "clock.h"
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/prcm.h>
 #include "soc.h"
 #include "common.h"
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
+#include "cm3xxx.h"
 #include "cminst44xx.h"
 #include "cm33xx.h"
-#include "prm2xxx_3xxx.h"
+#include "prm.h"
+#include "prm3xxx.h"
 #include "prm44xx.h"
 #include "prm33xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
 #include "pm.h"
-/* Maximum microseconds to wait for OMAP module to softreset */
-#define MAX_MODULE_SOFTRESET_WAIT       10000
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME              "mpu"
@@ -189,6 +187,8 @@ struct omap_hwmod_soc_ops {
        int (*is_hardreset_asserted)(struct omap_hwmod *oh,
                                     struct omap_hwmod_rst_info *ohri);
        int (*init_clkdm)(struct omap_hwmod *oh);
+        void (*update_context_lost)(struct omap_hwmod *oh);
+        int (*get_context_lost)(struct omap_hwmod *oh);
 };
 /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
@@ -648,6 +648,19 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
        return 0;
 }
+static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
+{
+        struct clk_hw_omap *clk;
+        if (oh->clkdm) {
+                return oh->clkdm;
+        } else if (oh->_clk) {
+                clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
+                return  clk->clkdm;
+        }
+        return NULL;
+}
 /**
 * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
 * @oh: struct omap_hwmod *
@@ -663,13 +676,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
 */
 static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
-        if (!oh->_clk)
+        struct clockdomain *clkdm, *init_clkdm;
+        clkdm = _get_clkdm(oh);
+        init_clkdm = _get_clkdm(init_oh);
+        if (!clkdm || !init_clkdm)
                return -EINVAL;
-        if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+        if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
                return 0;
-        return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
+        return clkdm_add_sleepdep(clkdm, init_clkdm);
 }
 /**
@@ -687,13 +705,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 */
 static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
-        if (!oh->_clk)
+        struct clockdomain *clkdm, *init_clkdm;
+        clkdm = _get_clkdm(oh);
+        init_clkdm = _get_clkdm(init_oh);
+        if (!clkdm || !init_clkdm)
                return -EINVAL;
-        if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+        if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
                return 0;
-        return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
+        return clkdm_del_sleepdep(clkdm, init_clkdm);
 }
 /**
@@ -727,7 +750,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
         */
        clk_prepare(oh->_clk);
-        if (!oh->_clk->clkdm)
+        if (!_get_clkdm(oh))
                pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
                           oh->name, oh->main_clk);
@@ -1310,6 +1333,7 @@ static void _enable_sysc(struct omap_hwmod *oh)
        u8 idlemode, sf;
        u32 v;
        bool clkdm_act;
+        struct clockdomain *clkdm;
        if (!oh->class->sysc)
                return;
@@ -1329,11 +1353,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
        v = oh->_sysc_cache;
        sf = oh->class->sysc->sysc_flags;
+        clkdm = _get_clkdm(oh);
        if (sf & SYSC_HAS_SIDLEMODE) {
-                clkdm_act = ((oh->clkdm &&
+                clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU);
-                              oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) ||
-                             (oh->_clk && oh->_clk->clkdm &&
-                              oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU));
                if (clkdm_act && !(oh->class->sysc->idlemodes &
                                   (SIDLE_SMART | SIDLE_SMART_WKUP)))
                        idlemode = HWMOD_IDLEMODE_FORCE;
@@ -1535,11 +1557,12 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
        pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
+        if (soc_ops.init_clkdm)
+                ret |= soc_ops.init_clkdm(oh);
        ret |= _init_main_clk(oh);
        ret |= _init_interface_clks(oh);
        ret |= _init_opt_clks(oh);
-        if (soc_ops.init_clkdm)
-                ret |= soc_ops.init_clkdm(oh);
        if (!ret)
                oh->_state = _HWMOD_STATE_CLKS_INITED;
@@ -1994,6 +2017,42 @@ static void _reconfigure_io_chain(void)
 }
 /**
+ * _omap4_update_context_lost - increment hwmod context loss counter if
+ * hwmod context was lost, and clear hardware context loss reg
+ * @oh: hwmod to check for context loss
+ *
+ * If the PRCM indicates that the hwmod @oh lost context, increment
+ * our in-memory context loss counter, and clear the RM_*_CONTEXT
+ * bits. No return value.
+ */
+static void _omap4_update_context_lost(struct omap_hwmod *oh)
+{
+        if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT)
+                return;
+        if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition,
+                                          oh->clkdm->pwrdm.ptr->prcm_offs,
+                                          oh->prcm.omap4.context_offs))
+                return;
+        oh->prcm.omap4.context_lost_counter++;
+        prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition,
+                                         oh->clkdm->pwrdm.ptr->prcm_offs,
+                                         oh->prcm.omap4.context_offs);
+}
+/**
+ * _omap4_get_context_lost - get context loss counter for a hwmod
+ * @oh: hwmod to get context loss counter for
+ *
+ * Returns the in-memory context loss counter for a hwmod.
+ */
+static int _omap4_get_context_lost(struct omap_hwmod *oh)
+{
+        return oh->prcm.omap4.context_lost_counter;
+}
+/**
 * _enable - enable an omap_hwmod
 * @oh: struct omap_hwmod *
 *
@@ -2076,6 +2135,9 @@ static int _enable(struct omap_hwmod *oh)
        if (soc_ops.enable_module)
                soc_ops.enable_module(oh);
+        if (soc_ops.update_context_lost)
+                soc_ops.update_context_lost(oh);
        r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
                -EINVAL;
        if (!r) {
@@ -2095,7 +2157,8 @@ static int _enable(struct omap_hwmod *oh)
                        _enable_sysc(oh);
                }
        } else {
-                _omap4_disable_module(oh);
+                if (soc_ops.disable_module)
+                        soc_ops.disable_module(oh);
                _disable_clocks(oh);
                pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
                         oh->name, r);
@@ -2703,7 +2766,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
 /* Static functions intended only for use in soc_ops field function pointers */
 /**
- * _omap2_wait_target_ready - wait for a module to leave slave idle
+ * _omap2xxx_wait_target_ready - wait for a module to leave slave idle
 * @oh: struct omap_hwmod *
 *
 * Wait for a module @oh to leave slave idle.  Returns 0 if the module
@@ -2711,7 +2774,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
 * slave idle; otherwise, pass along the return value of the
 * appropriate *_cm*_wait_module_ready() function.
 */
-static int _omap2_wait_target_ready(struct omap_hwmod *oh)
+static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh)
 {
        if (!oh)
                return -EINVAL;
@@ -2724,9 +2787,36 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
        /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
-        return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+        return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
-                                          oh->prcm.omap2.idlest_reg_id,
+                                             oh->prcm.omap2.idlest_reg_id,
-                                          oh->prcm.omap2.idlest_idle_bit);
+                                             oh->prcm.omap2.idlest_idle_bit);
+}
+/**
+ * _omap3xxx_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+        /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
+        return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+                                             oh->prcm.omap2.idlest_reg_id,
+                                             oh->prcm.omap2.idlest_idle_bit);
 }
 /**
@@ -3372,7 +3462,7 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 /**
 * omap_hwmod_count_resources - count number of struct resources needed by hwmod
 * @oh: struct omap_hwmod *
- * @res: pointer to the first element of an array of struct resource to fill
+ * @flags: Type of resources to include when counting (IRQ/DMA/MEM)
 *
 * Count the number of struct resource array elements necessary to
 * contain omap_hwmod @oh resources.  Intended to be called by code
@@ -3385,20 +3475,25 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 * resource IDs.
 *
 */
-int omap_hwmod_count_resources(struct omap_hwmod *oh)
+int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags)
 {
-        struct omap_hwmod_ocp_if *os;
+        int ret = 0;
-        struct list_head *p;
-        int ret;
-        int i = 0;
-        ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
+        if (flags & IORESOURCE_IRQ)
+                ret += _count_mpu_irqs(oh);
-        p = oh->slave_ports.next;
+        if (flags & IORESOURCE_DMA)
+                ret += _count_sdma_reqs(oh);
-        while (i < oh->slaves_cnt) {
+        if (flags & IORESOURCE_MEM) {
-                os = _fetch_next_ocp_if(&p, &i);
+                int i = 0;
-                ret += _count_ocp_if_addr_spaces(os);
+                struct omap_hwmod_ocp_if *os;
+                struct list_head *p = oh->slave_ports.next;
+                while (i < oh->slaves_cnt) {
+                        os = _fetch_next_ocp_if(&p, &i);
+                        ret += _count_ocp_if_addr_spaces(os);
+                }
        }
        return ret;
@@ -3565,10 +3660,15 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
 {
        struct clk *c;
        struct omap_hwmod_ocp_if *oi;
+        struct clockdomain *clkdm;
+        struct clk_hw_omap *clk;
        if (!oh)
                return NULL;
+        if (oh->clkdm)
+                return oh->clkdm->pwrdm.ptr;
        if (oh->_clk) {
                c = oh->_clk;
        } else {
@@ -3578,11 +3678,12 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
                c = oi->_clk;
        }
-        if (!c->clkdm)
+        clk = to_clk_hw_omap(__clk_get_hw(c));
+        clkdm = clk->clkdm;
+        if (!clkdm)
                return NULL;
-        return c->clkdm->pwrdm.ptr;
+        return clkdm->pwrdm.ptr;
 }
 /**
@@ -3887,17 +3988,21 @@ ohsps_unlock:
 * omap_hwmod_get_context_loss_count - get lost context count
 * @oh: struct omap_hwmod *
 *
- * Query the powerdomain of of @oh to get the context loss
+ * Returns the context loss count of associated @oh
- * count for this device.
+ * upon success, or zero if no context loss data is available.
 *
- * Returns the context loss count of the powerdomain assocated with @oh
+ * On OMAP4, this queries the per-hwmod context loss register,
- * upon success, or zero if no powerdomain exists for @oh.
+ * assuming one exists.  If not, or on OMAP2/3, this queries the
+ * enclosing powerdomain context loss count.
 */
 int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
 {
        struct powerdomain *pwrdm;
        int ret = 0;
+        if (soc_ops.get_context_lost)
+                return soc_ops.get_context_lost(oh);
        pwrdm = omap_hwmod_get_pwrdm(oh);
        if (pwrdm)
                ret = pwrdm_get_context_loss_count(pwrdm);
@@ -3994,8 +4099,13 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
 */
 void __init omap_hwmod_init(void)
 {
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+        if (cpu_is_omap24xx()) {
-                soc_ops.wait_target_ready = _omap2_wait_target_ready;
+                soc_ops.wait_target_ready = _omap2xxx_wait_target_ready;
+                soc_ops.assert_hardreset = _omap2_assert_hardreset;
+                soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+        } else if (cpu_is_omap34xx()) {
+                soc_ops.wait_target_ready = _omap3xxx_wait_target_ready;
                soc_ops.assert_hardreset = _omap2_assert_hardreset;
                soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
@@ -4007,6 +4117,8 @@ void __init omap_hwmod_init(void)
                soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
                soc_ops.init_clkdm = _init_clkdm;
+                soc_ops.update_context_lost = _omap4_update_context_lost;
+                soc_ops.get_context_lost = _omap4_get_context_lost;
        } else if (soc_is_am33xx()) {
                soc_ops.enable_module = _am33xx_enable_module;
                soc_ops.disable_module = _am33xx_disable_module;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 1db029438022..3ae852a522f9 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -2,7 +2,7 @@
 * omap_hwmod macros, structures
 *
 * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2012 Texas Instruments, Inc.
+ * Copyright (C) 2011-2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -35,7 +35,6 @@
 #include <linux/list.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
-#include <plat/cpu.h>
 struct omap_device;
@@ -395,12 +394,15 @@ struct omap_hwmod_omap2_prcm {
 /**
 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
- * @clkctrl_reg: PRCM address of the clock control register
+ * @clkctrl_offs: offset of the PRCM clock control register
- * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM
+ * @context_offs: offset of the RM_*_CONTEXT register
 * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
 * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
 * @submodule_wkdep_bit: bit shift of the WKDEP range
 * @flags: PRCM register capabilities for this IP block
+ * @modulemode: allowable modulemodes
+ * @context_lost_counter: Count of module level context lost
 *
 * If @lostcontext_mask is not defined, context loss check code uses
 * whole register without masking. @lostcontext_mask should only be
@@ -416,6 +418,7 @@ struct omap_hwmod_omap4_prcm {
        u8              submodule_wkdep_bit;
        u8              modulemode;
        u8              flags;
+        int             context_lost_counter;
 };
@@ -634,7 +637,7 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
 int omap_hwmod_softreset(struct omap_hwmod *oh);
-int omap_hwmod_count_resources(struct omap_hwmod *oh);
+int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
 int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b5db6007c523..b5efe58c0be0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -12,21 +12,23 @@
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/omap_hwmod.h>
+#include <linux/i2c-omap.h>
-#include <plat/dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/serial.h>
+#include <linux/omap-dma.h>
-#include <plat/i2c.h>
 #include <plat/dmtimer.h>
+#include "omap_hwmod.h"
 #include "l3_2xxx.h"
 #include "l4_2xxx.h"
-#include <plat/mmc.h>
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "serial.h"
 #include "wd_timer.h"
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c455e41b0237..6c8fa70ddadd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,21 +12,22 @@
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */
+#include <linux/i2c-omap.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/omap-dma.h>
-#include <plat/omap_hwmod.h>
-#include <plat/dma.h>
-#include <plat/serial.h>
-#include <plat/i2c.h>
 #include <plat/dmtimer.h>
-#include <plat/mmc.h>
+#include "omap_hwmod.h"
+#include "mmc.h"
 #include "l3_2xxx.h"
 #include "soc.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
+#include "i2c.h"
 #include "wd_timer.h"
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index cbb4ef6544ad..0413daba2dba 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -13,8 +13,7 @@
 */
 #include <asm/sizes.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/serial.h>
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 8851bbb6bb24..534974e08add 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -9,13 +9,15 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <plat/omap_hwmod.h>
-#include <plat/serial.h>
+#include <linux/dmaengine.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
-#include <plat/common.h>
+#include "omap_hwmod.h"
 #include "hdq1w.h"
 #include "omap_hwmod_common_data.h"
+#include "dma.h"
 /* UART */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 1a1287d62648..47901a5e76de 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -13,10 +13,10 @@
 */
 #include <asm/sizes.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/serial.h>
 #include "l3_2xxx.h"
 #include "l4_2xxx.h"
+#include "serial.h"
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index bd9220ed5ab9..e596117004d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -8,13 +8,13 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <plat/omap_hwmod.h>
-#include <plat/serial.h>
 #include <linux/platform_data/gpio-omap.h>
-#include <plat/dma.h>
+#include <linux/omap-dma.h>
 #include <plat/dmtimer.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
@@ -58,8 +58,9 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
        .syss_offs      = 0x0014,
        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -268,6 +269,7 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
        },
        .dev_attr       = &capability_alwon_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer2 */
@@ -286,6 +288,7 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
                },
        },
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer3 */
@@ -304,6 +307,7 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
                },
        },
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer4 */
@@ -322,6 +326,7 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
                },
        },
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer5 */
@@ -341,6 +346,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer6 */
@@ -360,6 +366,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer7 */
@@ -379,6 +386,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer8 */
@@ -398,6 +406,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer9 */
@@ -417,6 +426,7 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer10 */
@@ -436,6 +446,7 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer11 */
@@ -455,6 +466,7 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer12 */
@@ -474,6 +486,7 @@ struct omap_hwmod omap2xxx_timer12_hwmod = {
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* wd_timer2 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 59d5c1cd316d..32820d89f5b4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -14,13 +14,11 @@
 * GNU General Public License for more details.
 */
-#include <plat/omap_hwmod.h>
+#include <linux/i2c-omap.h>
-#include <plat/cpu.h>
+#include "omap_hwmod.h"
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dma.h>
-#include <plat/mmc.h>
-#include <plat/i2c.h>
 #include "omap_hwmod_common_data.h"
@@ -28,6 +26,8 @@
 #include "cm33xx.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
+#include "i2c.h"
+#include "mmc.h"
 /*
 * IP blocks
@@ -674,6 +674,7 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
        .name           = "cpgmac0",
        .class          = &am33xx_cpgmac0_hwmod_class,
        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
        .mpu_irqs       = am33xx_cpgmac0_irqs,
        .main_clk       = "cpsw_125mhz_gclk",
        .prcm           = {
@@ -685,6 +686,20 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 };
 /*
+ * mdio class
+ */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+        .name           = "davinci_mdio",
+};
+static struct omap_hwmod am33xx_mdio_hwmod = {
+        .name           = "davinci_mdio",
+        .class          = &am33xx_mdio_hwmod_class,
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .main_clk       = "cpsw_125mhz_gclk",
+};
+/*
 * dcan class
 */
 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
@@ -2501,6 +2516,21 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
        .user           = OCP_USER_MPU,
 };
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+        {
+                .pa_start       = 0x4A101000,
+                .pa_end         = 0x4A101000 + SZ_256 - 1,
+        },
+        { }
+};
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+        .master         = &am33xx_cpgmac0_hwmod,
+        .slave          = &am33xx_mdio_hwmod,
+        .addr           = am33xx_mdio_addr_space,
+        .user           = OCP_USER_MPU,
+};
 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
        {
                .pa_start       = 0x48080000,
@@ -3371,6 +3401,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l3_main__tptc2,
        &am33xx_l3_s__usbss,
        &am33xx_l4_hs__cpgmac0,
+        &am33xx_cpgmac0__mdio,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f67b7ee07dd4..ec4499e5a4c9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -14,28 +14,32 @@
 *
 * XXX these should be marked initdata for multi-OMAP kernels
 */
+#include <linux/i2c-omap.h>
 #include <linux/power/smartreflex.h>
 #include <linux/platform_data/gpio-omap.h>
-#include <plat/omap_hwmod.h>
+#include <linux/omap-dma.h>
-#include <plat/dma.h>
-#include <plat/serial.h>
 #include "l3_3xxx.h"
 #include "l4_3xxx.h"
-#include <plat/i2c.h>
-#include <plat/mmc.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/iommu-omap.h>
 #include <plat/dmtimer.h>
-#include <plat/iommu.h>
 #include "am35xx.h"
 #include "soc.h"
+#include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
+#include "dma.h"
+#include "i2c.h"
+#include "mmc.h"
 #include "wd_timer.h"
+#include "serial.h"
 /*
 * OMAP3xxx hardware module integration data
@@ -149,29 +153,16 @@ static struct omap_hwmod omap3xxx_debugss_hwmod = {
 };
 /* timer class */
-static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
-                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                                SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
-        .name = "timer",
-        .sysc = &omap3xxx_timer_1ms_sysc,
-};
 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
        .rev_offs       = 0x0000,
        .sysc_offs      = 0x0010,
        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -220,7 +211,8 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer2 */
@@ -237,7 +229,8 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
                },
        },
-        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer3 */
@@ -255,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
                },
        },
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer4 */
@@ -272,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
                },
        },
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer5 */
@@ -290,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer6 */
@@ -308,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer7 */
@@ -326,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer8 */
@@ -344,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
        },
        .dev_attr       = &capability_dsp_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer9 */
@@ -362,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer10 */
@@ -379,7 +379,8 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer11 */
@@ -398,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /* timer12 */
@@ -421,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
        },
        .dev_attr       = &capability_secure_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0b1249e00398..eb61cfd9452b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,22 +22,24 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
 #include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/i2c-omap.h>
-#include <plat/omap_hwmod.h>
+#include <linux/omap-dma.h>
-#include <plat/i2c.h>
-#include <plat/dma.h>
+#include <linux/platform_data/omap_ocp2scp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/mmc.h>
+#include <linux/platform_data/iommu-omap.h>
 #include <plat/dmtimer.h>
-#include <plat/common.h>
-#include <plat/iommu.h>
+#include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
+#include "i2c.h"
+#include "mmc.h"
 #include "wd_timer.h"
 /* Base offset for all OMAP4 interrupts external to MPUSS */
@@ -3102,6 +3104,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
                           SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -3155,6 +3158,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
        .name           = "timer1",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer1_irqs,
        .main_clk       = "timer1_fck",
        .prcm = {
@@ -3177,6 +3181,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
        .name           = "timer2",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer2_irqs,
        .main_clk       = "timer2_fck",
        .prcm = {
@@ -3351,6 +3356,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
        .name           = "timer10",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer10_irqs,
        .main_clk       = "timer10_fck",
        .prcm = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 9f1ccdc8cc8c..79d623b83e49 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -16,7 +16,7 @@
 * data and their integration with other OMAP modules and Linux.
 */
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 2bc8f1705d4a..cfcce299177c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -13,7 +13,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
 #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 #include "common.h"
 #include "display.h"
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index c784c12f98a1..336fdfcf88bb 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -19,7 +19,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
 #define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 #include "voltage.h"
@@ -89,8 +89,11 @@ extern struct omap_volt_data omap34xx_vddcore_volt_data[];
 extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
 extern struct omap_volt_data omap36xx_vddcore_volt_data[];
-extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
+extern struct omap_volt_data omap443x_vdd_mpu_volt_data[];
-extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
+extern struct omap_volt_data omap443x_vdd_iva_volt_data[];
-extern struct omap_volt_data omap44xx_vdd_core_volt_data[];
+extern struct omap_volt_data omap443x_vdd_core_volt_data[];
+extern struct omap_volt_data omap446x_vdd_mpu_volt_data[];
+extern struct omap_volt_data omap446x_vdd_iva_volt_data[];
+extern struct omap_volt_data omap446x_vdd_core_volt_data[];
 #endif          /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d992db8ff0b0..e237602e10ea 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -27,11 +27,43 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/usb.h>
+#include <linux/usb/musb.h>
-#include <plat/usb.h>
 #include "soc.h"
 #include "control.h"
+#include "usb.h"
+#define CONTROL_DEV_CONF                0x300
+#define PHY_PD                          0x1
+/**
+ * omap4430_phy_power_down: disable MUSB PHY during early init
+ *
+ * OMAP4 MUSB PHY module is enabled by default on reset, but this will
+ * prevent core retention if not disabled by SW. USB driver will
+ * later on enable this, once and if the driver needs it.
+ */
+static int __init omap4430_phy_power_down(void)
+{
+        void __iomem *ctrl_base;
+        if (!cpu_is_omap44xx())
+                return 0;
+        ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
+        if (!ctrl_base) {
+                pr_err("control module ioremap failed\n");
+                return -ENOMEM;
+        }
+        /* Power down the phy */
+        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+        iounmap(ctrl_base);
+        return 0;
+}
+early_initcall(omap4430_phy_power_down);
 void am35x_musb_reset(void)
 {
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index f515a1a056d5..fefd40166624 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -18,6 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/i2c/twl.h>
+#include "soc.h"
 #include "voltage.h"
 #include "pm.h"
@@ -30,16 +31,6 @@
 #define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
 #define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
-#define OMAP3430_VP1_VLIMITTO_VDDMIN    0x14
-#define OMAP3430_VP1_VLIMITTO_VDDMAX    0x42
-#define OMAP3430_VP2_VLIMITTO_VDDMIN    0x18
-#define OMAP3430_VP2_VLIMITTO_VDDMAX    0x2c
-#define OMAP3630_VP1_VLIMITTO_VDDMIN    0x18
-#define OMAP3630_VP1_VLIMITTO_VDDMAX    0x3c
-#define OMAP3630_VP2_VLIMITTO_VDDMIN    0x18
-#define OMAP3630_VP2_VLIMITTO_VDDMAX    0x30
 #define OMAP4_SRI2C_SLAVE_ADDR          0x12
 #define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
 #define OMAP4_VDD_MPU_SR_CMD_REG        0x56
@@ -53,13 +44,6 @@
 #define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
 #define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
-#define OMAP4_VP_MPU_VLIMITTO_VDDMIN    0xA
-#define OMAP4_VP_MPU_VLIMITTO_VDDMAX    0x39
-#define OMAP4_VP_IVA_VLIMITTO_VDDMIN    0xA
-#define OMAP4_VP_IVA_VLIMITTO_VDDMAX    0x2D
-#define OMAP4_VP_CORE_VLIMITTO_VDDMIN   0xA
-#define OMAP4_VP_CORE_VLIMITTO_VDDMAX   0x28
 static bool is_offset_valid;
 static u8 smps_offset;
 /*
@@ -158,16 +142,11 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
 static struct omap_voltdm_pmic omap3_mpu_pmic = {
        .slew_rate              = 4000,
        .step_size              = 12500,
-        .on_volt                = 1200000,
-        .onlp_volt              = 1000000,
-        .ret_volt               = 975000,
-        .off_volt               = 600000,
-        .volt_setup_time        = 0xfff,
        .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
        .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
-        .vp_vddmin              = OMAP3430_VP1_VLIMITTO_VDDMIN,
+        .vddmin                 = 600000,
-        .vp_vddmax              = OMAP3430_VP1_VLIMITTO_VDDMAX,
+        .vddmax                 = 1450000,
        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
        .volt_reg_addr          = OMAP3_VDD_MPU_SR_CONTROL_REG,
@@ -179,16 +158,11 @@ static struct omap_voltdm_pmic omap3_mpu_pmic = {
 static struct omap_voltdm_pmic omap3_core_pmic = {
        .slew_rate              = 4000,
        .step_size              = 12500,
-        .on_volt                = 1200000,
-        .onlp_volt              = 1000000,
-        .ret_volt               = 975000,
-        .off_volt               = 600000,
-        .volt_setup_time        = 0xfff,
        .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
        .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
-        .vp_vddmin              = OMAP3430_VP2_VLIMITTO_VDDMIN,
+        .vddmin                 = 600000,
-        .vp_vddmax              = OMAP3430_VP2_VLIMITTO_VDDMAX,
+        .vddmax                 = 1450000,
        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
        .volt_reg_addr          = OMAP3_VDD_CORE_SR_CONTROL_REG,
@@ -200,21 +174,17 @@ static struct omap_voltdm_pmic omap3_core_pmic = {
 static struct omap_voltdm_pmic omap4_mpu_pmic = {
        .slew_rate              = 4000,
        .step_size              = 12660,
-        .on_volt                = 1375000,
-        .onlp_volt              = 1375000,
-        .ret_volt               = 830000,
-        .off_volt               = 0,
-        .volt_setup_time        = 0,
        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
-        .vp_vddmin              = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
+        .vddmin                 = 0,
-        .vp_vddmax              = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
+        .vddmax                 = 2100000,
        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
        .volt_reg_addr          = OMAP4_VDD_MPU_SR_VOLT_REG,
        .cmd_reg_addr           = OMAP4_VDD_MPU_SR_CMD_REG,
        .i2c_high_speed         = true,
+        .i2c_pad_load           = 3,
        .vsel_to_uv             = twl6030_vsel_to_uv,
        .uv_to_vsel             = twl6030_uv_to_vsel,
 };
@@ -222,21 +192,17 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = {
 static struct omap_voltdm_pmic omap4_iva_pmic = {
        .slew_rate              = 4000,
        .step_size              = 12660,
-        .on_volt                = 1188000,
-        .onlp_volt              = 1188000,
-        .ret_volt               = 830000,
-        .off_volt               = 0,
-        .volt_setup_time        = 0,
        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
-        .vp_vddmin              = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
+        .vddmin                 = 0,
-        .vp_vddmax              = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
+        .vddmax                 = 2100000,
        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
        .volt_reg_addr          = OMAP4_VDD_IVA_SR_VOLT_REG,
        .cmd_reg_addr           = OMAP4_VDD_IVA_SR_CMD_REG,
        .i2c_high_speed         = true,
+        .i2c_pad_load           = 3,
        .vsel_to_uv             = twl6030_vsel_to_uv,
        .uv_to_vsel             = twl6030_uv_to_vsel,
 };
@@ -244,20 +210,17 @@ static struct omap_voltdm_pmic omap4_iva_pmic = {
 static struct omap_voltdm_pmic omap4_core_pmic = {
        .slew_rate              = 4000,
        .step_size              = 12660,
-        .on_volt                = 1200000,
-        .onlp_volt              = 1200000,
-        .ret_volt               = 830000,
-        .off_volt               = 0,
-        .volt_setup_time        = 0,
        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
-        .vp_vddmin              = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
+        .vddmin                 = 0,
-        .vp_vddmax              = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
+        .vddmax                 = 2100000,
        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
        .volt_reg_addr          = OMAP4_VDD_CORE_SR_VOLT_REG,
        .cmd_reg_addr           = OMAP4_VDD_CORE_SR_CMD_REG,
+        .i2c_high_speed         = true,
+        .i2c_pad_load           = 3,
        .vsel_to_uv             = twl6030_vsel_to_uv,
        .uv_to_vsel             = twl6030_uv_to_vsel,
 };
@@ -288,13 +251,6 @@ int __init omap3_twl_init(void)
        if (!cpu_is_omap34xx())
                return -ENODEV;
-        if (cpu_is_omap3630()) {
-                omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
-                omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
-                omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
-                omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
-        }
        /*
         * The smartreflex bit on twl4030 specifies if the setting of voltage
         * is done over the I2C_SR path. Since this setting is independent of
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index 58e16aef40bb..bd41d59a7cab 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -20,7 +20,7 @@
 #include <linux/opp.h>
 #include <linux/cpu.h>
-#include <plat/omap_device.h>
+#include "omap_device.h"
 #include "omap_opp_data.h"
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 75cef5f67a8a..62772e0e0d69 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -19,6 +19,7 @@
 */
 #include <linux/module.h>
+#include "soc.h"
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index a9fd6d5fe79e..d470b728e720 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP4 OPP table definitions.
 *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
 *      Nishanth Menon
 *      Kevin Hilman
 *      Thara Gopinath
@@ -35,7 +35,7 @@
 #define OMAP4430_VDD_MPU_OPPTURBO_UV            1313000
 #define OMAP4430_VDD_MPU_OPPNITRO_UV            1375000
-struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
@@ -47,7 +47,7 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
 #define OMAP4430_VDD_IVA_OPP100_UV              1188000
 #define OMAP4430_VDD_IVA_OPPTURBO_UV            1300000
-struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
@@ -57,14 +57,14 @@ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
 #define OMAP4430_VDD_CORE_OPP50_UV              1025000
 #define OMAP4430_VDD_CORE_OPP100_UV             1200000
-struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+struct omap_volt_data omap443x_vdd_core_volt_data[] = {
        VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
        VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
        VOLT_DATA_DEFINE(0, 0, 0, 0),
 };
-static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
        /* MPU OPP1 - OPP50 */
        OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
        /* MPU OPP2 - OPP100 */
@@ -86,6 +86,82 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
        /* TODO: add DSP, aess, fdif, gpu */
 };
+#define OMAP4460_VDD_MPU_OPP50_UV               1025000
+#define OMAP4460_VDD_MPU_OPP100_UV              1200000
+#define OMAP4460_VDD_MPU_OPPTURBO_UV            1313000
+#define OMAP4460_VDD_MPU_OPPNITRO_UV            1375000
+struct omap_volt_data omap446x_vdd_mpu_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+#define OMAP4460_VDD_IVA_OPP50_UV               1025000
+#define OMAP4460_VDD_IVA_OPP100_UV              1200000
+#define OMAP4460_VDD_IVA_OPPTURBO_UV            1313000
+#define OMAP4460_VDD_IVA_OPPNITRO_UV            1375000
+struct omap_volt_data omap446x_vdd_iva_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+#define OMAP4460_VDD_CORE_OPP50_UV              1025000
+#define OMAP4460_VDD_CORE_OPP100_UV             1200000
+#define OMAP4460_VDD_CORE_OPP100_OV_UV          1250000
+struct omap_volt_data omap446x_vdd_core_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_OV_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100OV, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
+        /* MPU OPP1 - OPP50 */
+        OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV),
+        /* MPU OPP2 - OPP100 */
+        OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV),
+        /* MPU OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("mpu", true, 920000000, OMAP4460_VDD_MPU_OPPTURBO_UV),
+        /*
+         * MPU OPP4 - OPP-Nitro + Disabled as the reference schematics
+         * recommends TPS623631 - confirm and enable the opp in board file
+         * XXX: May be we should enable these based on mpu capability and
+         * Exception board files disable it...
+         */
+        OPP_INITIALIZER("mpu", false, 1200000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
+        /* MPU OPP4 - OPP-Nitro SpeedBin */
+        OPP_INITIALIZER("mpu", false, 1500000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
+        /* L3 OPP1 - OPP50 */
+        OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4460_VDD_CORE_OPP50_UV),
+        /* L3 OPP2 - OPP100 */
+        OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV),
+        /* IVA OPP1 - OPP50 */
+        OPP_INITIALIZER("iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV),
+        /* IVA OPP2 - OPP100 */
+        OPP_INITIALIZER("iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV),
+        /*
+         * IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
+         * recommends Phoenix VCORE2 which can supply only 600mA - so the ones
+         * above this OPP frequency, even though OMAP is capable, should be
+         * enabled by board file which is sure of the chip power capability
+         */
+        OPP_INITIALIZER("iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
+        /* IVA OPP4 - OPP-Nitro */
+        OPP_INITIALIZER("iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
+        /* IVA OPP5 - OPP-Nitro SpeedBin*/
+        OPP_INITIALIZER("iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
+        /* TODO: add DSP, aess, fdif, gpu */
+};
 /**
 * omap4_opp_init() - initialize omap4 opp table
 */
@@ -93,12 +169,12 @@ int __init omap4_opp_init(void)
 {
        int r = -ENODEV;
-        if (!cpu_is_omap443x())
+        if (cpu_is_omap443x())
-                return r;
+                r = omap_init_opp_table(omap443x_opp_def_list,
+                        ARRAY_SIZE(omap443x_opp_def_list));
-        r = omap_init_opp_table(omap44xx_opp_def_list,
+        else if (cpu_is_omap446x())
-                        ARRAY_SIZE(omap44xx_opp_def_list));
+                r = omap_init_opp_table(omap446x_opp_def_list,
+                        ARRAY_SIZE(omap446x_opp_def_list));
        return r;
 }
 device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 46092cd806fa..e2c291f52f92 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -27,12 +27,12 @@
 #include <linux/module.h>
 #include <linux/slab.h>
-#include <plat/clock.h>
+#include "clock.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/dmtimer.h>
+#include "omap-pm.h"
-#include <plat/omap-pm.h>
+#include "soc.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index ea61c32957bd..f4b3143a8b1d 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -20,10 +20,11 @@
 #include <asm/system_misc.h>
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
-#include <plat/omap_device.h>
+#include "omap_device.h"
 #include "common.h"
+#include "soc.h"
 #include "prcm-common.h"
 #include "voltage.h"
 #include "powerdomain.h"
@@ -39,6 +40,38 @@ static struct omap_device_pm_latency *pm_lats;
 */
 int (*omap_pm_suspend)(void);
+#ifdef CONFIG_PM
+/**
+ * struct omap2_oscillator - Describe the board main oscillator latencies
+ * @startup_time: oscillator startup latency
+ * @shutdown_time: oscillator shutdown latency
+ */
+struct omap2_oscillator {
+        u32 startup_time;
+        u32 shutdown_time;
+};
+static struct omap2_oscillator oscillator = {
+        .startup_time = ULONG_MAX,
+        .shutdown_time = ULONG_MAX,
+};
+void omap_pm_setup_oscillator(u32 tstart, u32 tshut)
+{
+        oscillator.startup_time = tstart;
+        oscillator.shutdown_time = tshut;
+}
+void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
+{
+        if (!tstart || !tshut)
+                return;
+        *tstart = oscillator.startup_time;
+        *tshut = oscillator.shutdown_time;
+}
+#endif
 static int __init _init_omap_device(char *name)
 {
        struct omap_hwmod *oh;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 67d66131cfa7..c22503b17abd 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -102,6 +102,15 @@ extern void enable_omap3630_toggle_l2_on_restore(void);
 static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
+#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD      (1 << 0)
+#if defined(CONFIG_ARCH_OMAP4)
+extern u16 pm44xx_errata;
+#define IS_PM44XX_ERRATUM(id)           (pm44xx_errata & (id))
+#else
+#define IS_PM44XX_ERRATUM(id)           0
+#endif
 #ifdef CONFIG_POWER_AVS_OMAP
 extern int omap_devinit_smartreflex(void);
 extern void omap_enable_smartreflex_on_init(void);
@@ -129,4 +138,14 @@ static inline int omap4_twl_init(void)
 }
 #endif
+#ifdef CONFIG_PM
+extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
+extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
+extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
+#else
+static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
+static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; }
+static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
+#endif
 #endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 8af6cd6ac331..c333fa6dffa8 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -25,27 +25,30 @@
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/delay.h>
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <asm/fncpy.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
 #include <asm/system_misc.h>
-#include <plat/clock.h>
+#include <linux/omap-dma.h>
-#include <plat/sram.h>
-#include <plat/dma.h>
+#include "soc.h"
 #include "common.h"
-#include "prm2xxx_3xxx.h"
+#include "clock.h"
+#include "prm2xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "sram.h"
 #include "pm.h"
 #include "control.h"
 #include "powerdomain.h"
@@ -200,7 +203,7 @@ static int omap2_can_sleep(void)
 {
        if (omap2_fclks_active())
                return 0;
-        if (osc_ck->usecount > 1)
+        if (__clk_is_enabled(osc_ck))
                return 0;
        if (omap_dma_running())
                return 0;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3a904de4313e..7be3622cfc85 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,29 +28,27 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/omap-dma.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <trace/events/power.h>
+#include <asm/fncpy.h>
 #include <asm/suspend.h>
 #include <asm/system_misc.h>
-#include <plat/sram.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include <plat/sdrc.h>
+#include "soc.h"
-#include <plat/prcm.h>
-#include <plat/gpmc.h>
-#include <plat/dma.h>
 #include "common.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "gpmc.h"
 #include "prm-regbits-34xx.h"
+#include "prm3xxx.h"
-#include "prm2xxx_3xxx.h"
 #include "pm.h"
 #include "sdrc.h"
+#include "sram.h"
 #include "control.h"
 /* pm34xx errata defined in pm.h */
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 04922d149068..aa6fd98f606e 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -18,6 +18,7 @@
 #include <linux/slab.h>
 #include <asm/system_misc.h>
+#include "soc.h"
 #include "common.h"
 #include "clockdomain.h"
 #include "powerdomain.h"
@@ -100,13 +101,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
        if (!strncmp(pwrdm->name, "cpu", 3))
                return 0;
-        /*
-         * FIXME: Remove this check when core retention is supported
-         * Only MPUSS power domain is added in the list.
-         */
-        if (strcmp(pwrdm->name, "mpu_pwrdm"))
-                return 0;
        pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
        if (!pwrst)
                return -ENOMEM;
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index 2a791766283d..250d909e38bd 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -15,8 +15,9 @@
 #include <asm/pmu.h>
-#include <plat/omap_hwmod.h>
+#include "soc.h"
-#include <plat/omap_device.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
 static char *omap2_pmu_oh_names[] = {"mpu"};
 static char *omap3_pmu_oh_names[] = {"mpu", "debugss"};
@@ -57,8 +58,6 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
        if (IS_ERR(omap_pmu_dev))
                return PTR_ERR(omap_pmu_dev);
-        pm_runtime_enable(&omap_pmu_dev->dev);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 1678a3284233..dea62a9aad07 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -29,8 +29,6 @@
 #include <asm/cpu.h>
-#include <plat/prcm.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index baee90608d11..5277d56eb37f 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -22,8 +22,6 @@
 #include <linux/atomic.h>
-#include <plat/cpu.h>
 #include "voltage.h"
 /* Powerdomain basic power states */
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
deleted file mode 100644
index 3950ccfe5f4a..000000000000
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * OMAP2 and OMAP3 powerdomain control
- *
- * Copyright (C) 2009-2011 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/bug.h>
-#include <plat/prcm.h>
-#include "powerdomain.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
-#include "prm-regbits-34xx.h"
-/* Common functions across OMAP2 and OMAP3 */
-static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
-                                (pwrst << OMAP_POWERSTATE_SHIFT),
-                                pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTCTRL,
-                                             OMAP_POWERSTATE_MASK);
-}
-static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTST,
-                                             OMAP_POWERSTATEST_MASK);
-}
-static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-                                                                u8 pwrst)
-{
-        u32 m;
-        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
-        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-                                   OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
-                                                                u8 pwrst)
-{
-        u32 m;
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-                                   OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m;
-        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
-                                             m);
-}
-static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m;
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTCTRL, m);
-}
-static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        u32 v;
-        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
-        omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
-                                   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
-        return 0;
-}
-static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
-{
-        u32 c = 0;
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-        /* XXX Is this udelay() value meaningful? */
-        while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
-                OMAP_INTRANSITION_MASK) &&
-                (c++ < PWRDM_TRANSITION_BAILOUT))
-                        udelay(1);
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                       pwrdm->name);
-                return -EAGAIN;
-        }
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
-        return 0;
-}
-/* Applicable only for OMAP3. Not supported on OMAP2 */
-static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP3430_PM_PREPWSTST,
-                                             OMAP3430_LASTPOWERSTATEENTERED_MASK);
-}
-static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTST,
-                                             OMAP3430_LOGICSTATEST_MASK);
-}
-static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP2_PM_PWSTCTRL,
-                                             OMAP3430_LOGICSTATEST_MASK);
-}
-static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
-{
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                             OMAP3430_PM_PREPWSTST,
-                                             OMAP3430_LASTLOGICSTATEENTERED_MASK);
-}
-static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
-{
-        switch (bank) {
-        case 0:
-                return OMAP3430_LASTMEM1STATEENTERED_MASK;
-        case 1:
-                return OMAP3430_LASTMEM2STATEENTERED_MASK;
-        case 2:
-                return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
-        case 3:
-                return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
-        return 0;
-}
-static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m;
-        m = omap3_get_mem_bank_lastmemst_mask(bank);
-        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                OMAP3430_PM_PREPWSTST, m);
-}
-static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
-{
-        omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
-        return 0;
-}
-static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
-{
-        return omap2_prm_rmw_mod_reg_bits(0,
-                                          1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-                                          pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
-}
-static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
-{
-        return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-                                          0, pwrdm->prcm_offs,
-                                          OMAP2_PM_PWSTCTRL);
-}
-struct pwrdm_ops omap2_pwrdm_operations = {
-        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
-        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
-        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
-        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
-        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
-};
-struct pwrdm_ops omap3_pwrdm_operations = {
-        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
-        .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
-        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
-        .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
-        .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
-        .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
-        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
-        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
-        .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
-        .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
-        .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
-        .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
-        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
-};
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
deleted file mode 100644
index 67c5663899b6..000000000000
--- a/arch/arm/mach-omap2/powerdomain33xx.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * AM33XX Powerdomain control
- *
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
- * <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <plat/prcm.h>
-#include "powerdomain.h"
-#include "prm33xx.h"
-#include "prm-regbits-33xx.h"
-static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
-                                (pwrst << OMAP_POWERSTATE_SHIFT),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        return 0;
-}
-static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
-        v &= OMAP_POWERSTATE_MASK;
-        v >>= OMAP_POWERSTATE_SHIFT;
-        return v;
-}
-static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= OMAP_POWERSTATEST_MASK;
-        v >>= OMAP_POWERSTATEST_SHIFT;
-        return v;
-}
-static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
-        v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
-        return v;
-}
-static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
-{
-        am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
-                                (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        return 0;
-}
-static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
-{
-        am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
-                                AM33XX_LASTPOWERSTATEENTERED_MASK,
-                                pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        return 0;
-}
-static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        u32 m;
-        m = pwrdm->logicretstate_mask;
-        if (!m)
-                return -EINVAL;
-        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        return 0;
-}
-static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= AM33XX_LOGICSTATEST_MASK;
-        v >>= AM33XX_LOGICSTATEST_SHIFT;
-        return v;
-}
-static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
-{
-        u32 v, m;
-        m = pwrdm->logicretstate_mask;
-        if (!m)
-                return -EINVAL;
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        v &= m;
-        v >>= __ffs(m);
-        return v;
-}
-static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-                u8 pwrst)
-{
-        u32 m;
-        m = pwrdm->mem_on_mask[bank];
-        if (!m)
-                return -EINVAL;
-        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        return 0;
-}
-static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
-                                        u8 pwrst)
-{
-        u32 m;
-        m = pwrdm->mem_ret_mask[bank];
-        if (!m)
-                return -EINVAL;
-        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
-                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        return 0;
-}
-static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-        m = pwrdm->mem_pwrst_mask[bank];
-        if (!m)
-                return -EINVAL;
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
-        v &= m;
-        v >>= __ffs(m);
-        return v;
-}
-static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-        m = pwrdm->mem_retst_mask[bank];
-        if (!m)
-                return -EINVAL;
-        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
-        v &= m;
-        v >>= __ffs(m);
-        return v;
-}
-static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
-{
-        u32 c = 0;
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-        /* XXX Is this udelay() value meaningful? */
-        while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
-                        & OMAP_INTRANSITION_MASK) &&
-                        (c++ < PWRDM_TRANSITION_BAILOUT))
-                udelay(1);
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                       pwrdm->name);
-                return -EAGAIN;
-        }
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
-        return 0;
-}
-struct pwrdm_ops am33xx_pwrdm_operations = {
-        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst               = am33xx_pwrdm_read_pwrst,
-        .pwrdm_read_prev_pwrst          = am33xx_pwrdm_read_prev_pwrst,
-        .pwrdm_set_logic_retst          = am33xx_pwrdm_set_logic_retst,
-        .pwrdm_read_logic_pwrst         = am33xx_pwrdm_read_logic_pwrst,
-        .pwrdm_read_logic_retst         = am33xx_pwrdm_read_logic_retst,
-        .pwrdm_clear_all_prev_pwrst     = am33xx_pwrdm_clear_all_prev_pwrst,
-        .pwrdm_set_lowpwrstchange       = am33xx_pwrdm_set_lowpwrstchange,
-        .pwrdm_read_mem_pwrst           = am33xx_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst           = am33xx_pwrdm_read_mem_retst,
-        .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
-        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
-};
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
deleted file mode 100644
index aceb4f464c9b..000000000000
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * OMAP4 powerdomain control
- *
- * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/bug.h>
-#include "powerdomain.h"
-#include <plat/prcm.h>
-#include "prm2xxx_3xxx.h"
-#include "prm44xx.h"
-#include "prminst44xx.h"
-#include "prm-regbits-44xx.h"
-static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
-                                        (pwrst << OMAP_POWERSTATE_SHIFT),
-                                        pwrdm->prcm_partition,
-                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
-        return 0;
-}
-static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        v &= OMAP_POWERSTATE_MASK;
-        v >>= OMAP_POWERSTATE_SHIFT;
-        return v;
-}
-static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= OMAP_POWERSTATEST_MASK;
-        v >>= OMAP_POWERSTATEST_SHIFT;
-        return v;
-}
-static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
-        v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
-        return v;
-}
-static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
-{
-        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
-                                        (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
-                                        pwrdm->prcm_partition,
-                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
-        return 0;
-}
-static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
-{
-        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
-                                        OMAP4430_LASTPOWERSTATEENTERED_MASK,
-                                        pwrdm->prcm_partition,
-                                        pwrdm->prcm_offs, OMAP4_PM_PWSTST);
-        return 0;
-}
-static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
-{
-        u32 v;
-        v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
-        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
-                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        return 0;
-}
-static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-                                    u8 pwrst)
-{
-        u32 m;
-        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
-        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
-                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        return 0;
-}
-static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
-                                     u8 pwrst)
-{
-        u32 m;
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
-                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        return 0;
-}
-static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= OMAP4430_LOGICSTATEST_MASK;
-        v >>= OMAP4430_LOGICSTATEST_SHIFT;
-        return v;
-}
-static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
-{
-        u32 v;
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        v &= OMAP4430_LOGICRETSTATE_MASK;
-        v >>= OMAP4430_LOGICRETSTATE_SHIFT;
-        return v;
-}
-/**
- * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
- * @pwrdm: struct powerdomain * to read the state for
- *
- * Reads the previous logic powerstate for a powerdomain. This
- * function must determine the previous logic powerstate by first
- * checking the previous powerstate for the domain. If that was OFF,
- * then logic has been lost. If previous state was RETENTION, the
- * function reads the setting for the next retention logic state to
- * see the actual value.  In every other case, the logic is
- * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
- * depending whether the logic was retained or not.
- */
-static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
-{
-        int state;
-        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
-        if (state == PWRDM_POWER_OFF)
-                return PWRDM_POWER_OFF;
-        if (state != PWRDM_POWER_RET)
-                return PWRDM_POWER_RET;
-        return omap4_pwrdm_read_logic_retst(pwrdm);
-}
-static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTST);
-        v &= m;
-        v >>= __ffs(m);
-        return v;
-}
-static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
-{
-        u32 m, v;
-        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
-                                        OMAP4_PM_PWSTCTRL);
-        v &= m;
-        v >>= __ffs(m);
-        return v;
-}
-/**
- * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
- * @pwrdm: struct powerdomain * to read mem powerstate for
- * @bank: memory bank index
- *
- * Reads the previous memory powerstate for a powerdomain. This
- * function must determine the previous memory powerstate by first
- * checking the previous powerstate for the domain. If that was OFF,
- * then logic has been lost. If previous state was RETENTION, the
- * function reads the setting for the next memory retention state to
- * see the actual value.  In every other case, the logic is
- * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
- * depending whether logic was retained or not.
- */
-static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
-{
-        int state;
-        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
-        if (state == PWRDM_POWER_OFF)
-                return PWRDM_POWER_OFF;
-        if (state != PWRDM_POWER_RET)
-                return PWRDM_POWER_RET;
-        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
-}
-static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
-{
-        u32 c = 0;
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-        /* XXX Is this udelay() value meaningful? */
-        while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
-                                            pwrdm->prcm_offs,
-                                            OMAP4_PM_PWSTST) &
-                OMAP_INTRANSITION_MASK) &&
-               (c++ < PWRDM_TRANSITION_BAILOUT))
-                udelay(1);
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                       pwrdm->name);
-                return -EAGAIN;
-        }
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
-        return 0;
-}
-struct pwrdm_ops omap4_pwrdm_operations = {
-        .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
-        .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
-        .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
-        .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
-        .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
-        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
-        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
-        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
-        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
-        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
-        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
-        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
-        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
-        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
-        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
-        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
-};
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 2385c1f009ee..ba520d4f7c7b 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include "soc.h"
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 72df97482cc0..c7d355fafd24 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -406,11 +406,6 @@
 #define OMAP3430_EN_CORE_MASK                           (1 << 0)
-/*
- * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
- * submodule to exit hardreset
- */
-#define MAX_MODULE_HARDRESET_WAIT               10000
 /*
 * Maximum time(us) it takes to output the signal WUCLKOUT of the last
@@ -419,24 +414,7 @@
 * microseconds on OMAP4, so this timeout may be too high.
 */
 #define MAX_IOPAD_LATCH_TIME                    100
 # ifndef __ASSEMBLER__
-extern void __iomem *prm_base;
-extern void __iomem *cm_base;
-extern void __iomem *cm2_base;
-extern void __iomem *prcm_mpu_base;
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-extern void omap_prm_base_init(void);
-extern void omap_cm_base_init(void);
-#else
-static inline void omap_prm_base_init(void)
-{
-}
-static inline void omap_cm_base_init(void)
-{
-}
-#endif
 /**
 * struct omap_prcm_irq - describes a PRCM interrupt bit
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
deleted file mode 100644
index 0f51e034e0aa..000000000000
--- a/arch/arm/mach-omap2/prcm.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/prcm.c
- *
- * OMAP 24xx Power Reset and Clock Management (PRCM) functions
- *
- * Copyright (C) 2005 Nokia Corporation
- *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Rajendra Nayak <rnayak@ti.com>
- *
- * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
- * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include "common.h"
-#include <plat/prcm.h>
-#include "clock.h"
-#include "clock2xxx.h"
-#include "cm2xxx_3xxx.h"
-#include "prm2xxx_3xxx.h"
-#include "prm44xx.h"
-#include "prminst44xx.h"
-#include "cminst44xx.h"
-#include "prm-regbits-24xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-void __iomem *prm_base;
-void __iomem *cm_base;
-void __iomem *cm2_base;
-void __iomem *prcm_mpu_base;
-#define MAX_MODULE_ENABLE_WAIT          100000
-u32 omap_prcm_get_reset_sources(void)
-{
-        /* XXX This presumably needs modification for 34XX */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
-        if (cpu_is_omap44xx())
-                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
-        return 0;
-}
-EXPORT_SYMBOL(omap_prcm_get_reset_sources);
-/* Resets clock rates and reboots the system. Only called from system.h */
-void omap_prcm_restart(char mode, const char *cmd)
-{
-        s16 prcm_offs = 0;
-        if (cpu_is_omap24xx()) {
-                omap2xxx_clk_prepare_for_reboot();
-                prcm_offs = WKUP_MOD;
-        } else if (cpu_is_omap34xx()) {
-                prcm_offs = OMAP3430_GR_MOD;
-                omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
-        } else if (cpu_is_omap44xx()) {
-                omap4_prminst_global_warm_sw_reset(); /* never returns */
-        } else {
-                WARN_ON(1);
-        }
-        /*
-         * As per Errata i520, in some cases, user will not be able to
-         * access DDR memory after warm-reset.
-         * This situation occurs while the warm-reset happens during a read
-         * access to DDR memory. In that particular condition, DDR memory
-         * does not respond to a corrupted read command due to the warm
-         * reset occurrence but SDRC is waiting for read completion.
-         * SDRC is not sensitive to the warm reset, but the interconnect is
-         * reset on the fly, thus causing a misalignment between SDRC logic,
-         * interconnect logic and DDR memory state.
-         * WORKAROUND:
-         * Steps to perform before a Warm reset is trigged:
-         * 1. enable self-refresh on idle request
-         * 2. put SDRC in idle
-         * 3. wait until SDRC goes to idle
-         * 4. generate SW reset (Global SW reset)
-         *
-         * Steps to be performed after warm reset occurs (in bootloader):
-         * if HW warm reset is the source, apply below steps before any
-         * accesses to SDRAM:
-         * 1. Reset SMS and SDRC and wait till reset is complete
-         * 2. Re-initialize SMS, SDRC and memory
-         *
-         * NOTE: Above work around is required only if arch reset is implemented
-         * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
-         * the WA since it resets SDRC as well as part of cold reset.
-         */
-        /* XXX should be moved to some OMAP2/3 specific code */
-        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
-                                   OMAP2_RM_RSTCTRL);
-        omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
-}
-/**
- * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
- * @reg: physical address of module IDLEST register
- * @mask: value to mask against to determine if the module is active
- * @idlest: idle state indicator (0 or 1) for the clock
- * @name: name of the clock (for printk)
- *
- * Returns 1 if the module indicated readiness in time, or 0 if it
- * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
- *
- * XXX This function is deprecated.  It should be removed once the
- * hwmod conversion is complete.
- */
-int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
-                                const char *name)
-{
-        int i = 0;
-        int ena = 0;
-        if (idlest)
-                ena = 0;
-        else
-                ena = mask;
-        /* Wait for lock */
-        omap_test_timeout(((__raw_readl(reg) & mask) == ena),
-                          MAX_MODULE_ENABLE_WAIT, i);
-        if (i < MAX_MODULE_ENABLE_WAIT)
-                pr_debug("cm: Module associated with clock %s ready after %d loops\n",
-                         name, i);
-        else
-                pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
-                       name, MAX_MODULE_ENABLE_WAIT);
-        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
-};
-void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
-{
-        if (omap2_globals->prm)
-                prm_base = omap2_globals->prm;
-        if (omap2_globals->cm)
-                cm_base = omap2_globals->cm;
-        if (omap2_globals->cm2)
-                cm2_base = omap2_globals->cm2;
-        if (omap2_globals->prcm_mpu)
-                prcm_mpu_base = omap2_globals->prcm_mpu;
-        if (cpu_is_omap44xx() || soc_is_omap54xx()) {
-                omap_prm_base_init();
-                omap_cm_base_init();
-        }
-}
-/*
- * Stubbed functions so that common files continue to build when
- * custom builds are used
- * XXX These are temporary and should be removed at the earliest possible
- * opportunity
- */
-int __weak omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs)
-{
-        return 0;
-}
-void __weak omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
-                                s16 cdoffs, u16 clkctrl_offs)
-{
-}
-void __weak omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
-                                 u16 clkctrl_offs)
-{
-}
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index 928dbd4f20ed..c30e44a7fab0 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -20,6 +20,12 @@
 #include "prcm_mpu44xx.h"
 #include "cm-regbits-44xx.h"
+/*
+ * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP
+ *   block registers
+ */
+void __iomem *prcm_mpu_base;
 /* PRCM_MPU low-level functions */
 u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
@@ -43,3 +49,14 @@ u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
        return v;
 }
+/**
+ * omap2_set_globals_prcm_mpu - set the MPU PRCM base address (for early use)
+ * @prcm_mpu: PRCM_MPU base virtual address
+ *
+ * XXX Will be replaced when the PRM/CM drivers are completed.
+ */
+void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu)
+{
+        prcm_mpu_base = prcm_mpu;
+}
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 8a6e250f04b5..884af7bb4afd 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -1,7 +1,7 @@
 /*
 * OMAP44xx PRCM MPU instance offset macros
 *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010, 2012 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
@@ -25,6 +25,12 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
+#include "common.h"
+# ifndef __ASSEMBLER__
+extern void __iomem *prcm_mpu_base;
+# endif
 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
@@ -98,6 +104,7 @@ extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
 extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
 extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
                                            s16 idx);
+extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
 # endif
 #endif
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 6ac966103f34..91aa5106d637 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -14,7 +14,7 @@
 * published by the Free Software Foundation.
 */
-#include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
 /* Bits shared between registers */
@@ -107,12 +107,14 @@
 #define OMAP2420_CLKOUT2_EN_MASK                        (1 << 15)
 #define OMAP2420_CLKOUT2_DIV_SHIFT                      11
 #define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
+#define OMAP2420_CLKOUT2_DIV_WIDTH                      3
 #define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
 #define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
 #define OMAP24XX_CLKOUT_EN_SHIFT                        7
 #define OMAP24XX_CLKOUT_EN_MASK                         (1 << 7)
 #define OMAP24XX_CLKOUT_DIV_SHIFT                       3
 #define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
+#define OMAP24XX_CLKOUT_DIV_WIDTH                       3
 #define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
 #define OMAP24XX_CLKOUT_SOURCE_MASK                     (0x3 << 0)
@@ -209,9 +211,13 @@
 /* RM_RSTST_WKUP specific bits */
 /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST_SHIFT                      6
 #define OMAP24XX_EXTWMPU_RST_MASK                       (1 << 6)
+#define OMAP24XX_SECU_WD_RST_SHIFT                      5
 #define OMAP24XX_SECU_WD_RST_MASK                       (1 << 5)
+#define OMAP24XX_MPU_WD_RST_SHIFT                       4
 #define OMAP24XX_MPU_WD_RST_MASK                        (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST_SHIFT                    3
 #define OMAP24XX_SECU_VIOL_RST_MASK                     (1 << 3)
 /* PM_WKEN_WKUP specific bits */
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 64c087af6a8b..b0a2142eeb91 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -14,7 +14,7 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
-#include "prm2xxx_3xxx.h"
+#include "prm3xxx.h"
 /* Shared register bits */
@@ -384,6 +384,7 @@
 /* PRM_CLKSEL */
 #define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
 #define OMAP3430_SYS_CLKIN_SEL_MASK                     (0x7 << 0)
+#define OMAP3430_SYS_CLKIN_SEL_WIDTH                    3
 /* PRM_CLKOUT_CTRL */
 #define OMAP3430_CLKOUT_EN_MASK                         (1 << 7)
@@ -509,15 +510,25 @@
 #define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
 /* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST_SHIFT                   10
 #define OMAP3430_ICECRUSHER_RST_MASK                    (1 << 10)
+#define OMAP3430_ICEPICK_RST_SHIFT                      9
 #define OMAP3430_ICEPICK_RST_MASK                       (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT         8
 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK          (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT         7
 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK          (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST_SHIFT                6
 #define OMAP3430_EXTERNAL_WARM_RST_MASK                 (1 << 6)
+#define OMAP3430_SECURE_WD_RST_SHIFT                    5
 #define OMAP3430_SECURE_WD_RST_MASK                     (1 << 5)
+#define OMAP3430_MPU_WD_RST_SHIFT                       4
 #define OMAP3430_MPU_WD_RST_MASK                        (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST_SHIFT                3
 #define OMAP3430_SECURITY_VIOL_RST_MASK                 (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST_SHIFT                    1
 #define OMAP3430_GLOBAL_SW_RST_MASK                     (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST_SHIFT                  0
 #define OMAP3430_GLOBAL_COLD_RST_MASK                   (1 << 0)
 /* PRM_VOLTCTRL */
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 39d562169d18..ac25ae6667cf 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
 *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 *
 * Paul Walmsley
@@ -15,6 +15,28 @@
 #include "prcm-common.h"
+# ifndef __ASSEMBLER__
+extern void __iomem *prm_base;
+extern void omap2_set_globals_prm(void __iomem *prm);
+# endif
+/*
+ * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
+ * module to softreset
+ */
+#define MAX_MODULE_SOFTRESET_WAIT               10000
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT               10000
+/*
+ * Register bitfields
+ */
 /*
 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
 *
@@ -52,5 +74,67 @@
 #define OMAP_POWERSTATE_SHIFT                           0
 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
+/*
+ * Standardized OMAP reset source bits
+ *
+ * To the extent these happen to match the hardware register bit
+ * shifts, it's purely coincidental.  Used by omap-wdt.c.
+ * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
+ * there are any bits remaining in the global PRM_RSTST register that
+ * haven't been identified, or when the PRM code for the current SoC
+ * doesn't know how to interpret the register.
+ */
+#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT                       0
+#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT                       1
+#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT                         2
+#define OMAP_MPU_WD_RST_SRC_ID_SHIFT                            3
+#define OMAP_SECU_WD_RST_SRC_ID_SHIFT                           4
+#define OMAP_EXTWARM_RST_SRC_ID_SHIFT                           5
+#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT                        6
+#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT                        7
+#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT                       8
+#define OMAP_ICEPICK_RST_SRC_ID_SHIFT                           9
+#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT                        10
+#define OMAP_C2C_RST_SRC_ID_SHIFT                               11
+#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT                           12
+#ifndef __ASSEMBLER__
+/**
+ * struct prm_reset_src_map - map register bitshifts to standard bitshifts
+ * @reg_shift: bitshift in the PRM reset source register
+ * @std_shift: bitshift equivalent in the standard reset source list
+ *
+ * The fields are signed because -1 is used as a terminator.
+ */
+struct prm_reset_src_map {
+        s8 reg_shift;
+        s8 std_shift;
+};
+/**
+ * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
+ * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
+ * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
+ * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
+ *
+ * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
+ * deprecated.
+ */
+struct prm_ll_data {
+        u32 (*read_reset_sources)(void);
+        bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
+        void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
+};
+extern int prm_register(struct prm_ll_data *pld);
+extern int prm_unregister(struct prm_ll_data *pld);
+extern u32 prm_read_reset_sources(void);
+extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
+extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
+#endif
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
new file mode 100644
index 000000000000..faeab18696df
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -0,0 +1,138 @@
+/*
+ * OMAP2xxx PRM module functions
+ *
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include "common.h"
+#include <plat/cpu.h>
+#include "vp.h"
+#include "powerdomain.h"
+#include "clockdomain.h"
+#include "prm2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm-regbits-24xx.h"
+/*
+ * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
+ *   hardware register (which are specific to the OMAP2xxx SoCs) to
+ *   reset source ID bit shifts (which is an OMAP SoC-independent
+ *   enumeration)
+ */
+static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
+        { OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
+        { OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
+        { OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
+        { OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
+        { OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
+        { -1, -1 },
+};
+/**
+ * omap2xxx_prm_read_reset_sources - return the last SoC reset source
+ *
+ * Return a u32 representing the last reset sources of the SoC.  The
+ * returned reset source bits are standardized across OMAP SoCs.
+ */
+static u32 omap2xxx_prm_read_reset_sources(void)
+{
+        struct prm_reset_src_map *p;
+        u32 r = 0;
+        u32 v;
+        v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
+        p = omap2xxx_prm_reset_src_map;
+        while (p->reg_shift >= 0 && p->std_shift >= 0) {
+                if (v & (1 << p->reg_shift))
+                        r |= 1 << p->std_shift;
+                p++;
+        }
+        return r;
+}
+/**
+ * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
+ *
+ * Set the DPLL reset bit, which should reboot the SoC.  This is the
+ * recommended way to restart the SoC.  No return value.
+ */
+void omap2xxx_prm_dpll_reset(void)
+{
+        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
+                                   OMAP2_RM_RSTCTRL);
+        /* OCP barrier */
+        omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
+}
+int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                   clkdm->pwrdm.ptr->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                                     clkdm->pwrdm.ptr->prcm_offs,
+                                     OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+struct pwrdm_ops omap2_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
+/*
+ *
+ */
+static struct prm_ll_data omap2xxx_prm_ll_data = {
+        .read_reset_sources = &omap2xxx_prm_read_reset_sources,
+};
+int __init omap2xxx_prm_init(void)
+{
+        if (!cpu_is_omap24xx())
+                return 0;
+        return prm_register(&omap2xxx_prm_ll_data);
+}
+static void __exit omap2xxx_prm_exit(void)
+{
+        if (!cpu_is_omap24xx())
+                return;
+        /* Should never happen */
+        WARN(prm_unregister(&omap2xxx_prm_ll_data),
+             "%s: prm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
new file mode 100644
index 000000000000..3194dd87e0e4
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -0,0 +1,133 @@
+/*
+ * OMAP2xxx Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
+#include "prcm-common.h"
+#include "prm.h"
+#include "prm2xxx_3xxx.h"
+#define OMAP2420_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+/*
+ * OMAP2-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ *
+ */
+#define OMAP2_PRCM_REVISION_OFFSET      0x0000
+#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
+#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
+#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
+#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
+#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
+#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
+#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
+#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
+#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
+#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
+#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
+#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
+#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
+#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
+#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
+#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
+#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
+/*
+ * Module specific PRM register offsets from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ */
+/* Register offsets appearing on both OMAP2 and OMAP3 */
+#define OMAP2_RM_RSTCTRL                                0x0050
+#define OMAP2_RM_RSTTIME                                0x0054
+#define OMAP2_RM_RSTST                                  0x0058
+#define OMAP2_PM_PWSTCTRL                               0x00e0
+#define OMAP2_PM_PWSTST                                 0x00e4
+#define PM_WKEN                                         0x00a0
+#define PM_WKEN1                                        PM_WKEN
+#define PM_WKST                                         0x00b0
+#define PM_WKST1                                        PM_WKST
+#define PM_WKDEP                                        0x00c8
+#define PM_EVGENCTRL                                    0x00d4
+#define PM_EVGENONTIM                                   0x00d8
+#define PM_EVGENOFFTIM                                  0x00dc
+/* OMAP2xxx specific register offsets */
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+#ifndef __ASSEMBLER__
+/* Function prototypes */
+extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
+extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
+extern void omap2xxx_prm_dpll_reset(void);
+extern int __init omap2xxx_prm_init(void);
+#endif
+#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9529984d8d2b..30517f5af707 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -15,82 +15,12 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/io.h>
-#include <linux/irq.h>
-#include <plat/prcm.h>
-#include "soc.h"
 #include "common.h"
-#include "vp.h"
+#include "powerdomain.h"
 #include "prm2xxx_3xxx.h"
-#include "cm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "prm-regbits-34xx.h"
+#include "clockdomain.h"
-static const struct omap_prcm_irq omap3_prcm_irqs[] = {
-        OMAP_PRCM_IRQ("wkup",   0,      0),
-        OMAP_PRCM_IRQ("io",     9,      1),
-};
-static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
-        .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
-        .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
-        .nr_regs                = 1,
-        .irqs                   = omap3_prcm_irqs,
-        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
-        .irq                    = 11 + OMAP_INTC_START,
-        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
-        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
-        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
-        .restore_irqen          = &omap3xxx_prm_restore_irqen,
-};
-u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
-{
-        return __raw_readl(prm_base + module + idx);
-}
-void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __raw_writel(val, prm_base + module + idx);
-}
-/* Read-modify-write a register in a PRM module. Caller must lock */
-u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-        v = omap2_prm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        omap2_prm_write_mod_reg(v, module, idx);
-        return v;
-}
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-        u32 v;
-        v = omap2_prm_read_mod_reg(domain, idx);
-        v &= mask;
-        v >>= __ffs(mask);
-        return v;
-}
-u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
 /**
 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
@@ -104,9 +34,6 @@ u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 */
 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
 {
-        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
-                return -EINVAL;
        return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
                                       (1 << shift));
 }
@@ -127,9 +54,6 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
 {
        u32 mask;
-        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
-                return -EINVAL;
        mask = 1 << shift;
        omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
@@ -156,9 +80,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
        u32 rst, st;
        int c;
-        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
-                return -EINVAL;
        rst = 1 << rst_shift;
        st = 1 << st_shift;
@@ -178,188 +99,155 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
-/* PRM VP */
-/*
- * struct omap3_vp - OMAP3 VP register access description.
- * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
- */
-struct omap3_vp {
-        u32 tranxdone_status;
-};
-static struct omap3_vp omap3_vp[] = {
-        [OMAP3_VP_VDD_MPU_ID] = {
-                .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
-        },
-        [OMAP3_VP_VDD_CORE_ID] = {
-                .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
-        },
-};
-#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
-u32 omap3_prm_vp_check_txdone(u8 vp_id)
-{
-        struct omap3_vp *vp = &omap3_vp[vp_id];
-        u32 irqstatus;
-        irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
+/* Powerdomain low-level functions */
-                                           OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        return irqstatus & vp->tranxdone_status;
-}
-void omap3_prm_vp_clear_txdone(u8 vp_id)
+/* Common functions across OMAP2 and OMAP3 */
+int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 {
-        struct omap3_vp *vp = &omap3_vp[vp_id];
+        omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
+                                   (pwrst << OMAP_POWERSTATE_SHIFT),
-        omap2_prm_write_mod_reg(vp->tranxdone_status,
+                                   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
-                                OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        return 0;
 }
-u32 omap3_prm_vcvp_read(u8 offset)
+int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 {
-        return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP_POWERSTATE_MASK);
 }
-void omap3_prm_vcvp_write(u32 val, u8 offset)
+int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
 {
-        omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP_POWERSTATEST_MASK);
 }
-u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
 {
-        return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+        return 0;
 }
-/**
+int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
- * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+                                                                u8 pwrst)
- * @events: ptr to a u32, preallocated by caller
- *
- * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
- * MPU IRQs, and store the result into the u32 pointed to by @events.
- * No return value.
- */
-void omap3xxx_prm_read_pending_irqs(unsigned long *events)
 {
-        u32 mask, st;
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-        /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-        mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+                                   OMAP2_PM_PWSTCTRL);
-        st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        events[0] = mask & st;
+        return 0;
 }
-/**
+int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
- * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
- *
- * Force any buffered writes to the PRM IP block to complete.  Needed
- * by the PRM IRQ handler, which reads and writes directly to the IP
- * block, to avoid race conditions after acknowledging or clearing IRQ
- * bits.  No return value.
- */
-void omap3xxx_prm_ocp_barrier(void)
 {
-        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
+                                             m);
 }
-/**
+int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
- * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
- * @saved_mask: ptr to a u32 array to save IRQENABLE bits
- *
- * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
- * must be allocated by the caller.  Intended to be used in the PRM
- * interrupt handler suspend callback.  The OCP barrier is needed to
- * ensure the write to disable PRM interrupts reaches the PRM before
- * returning; otherwise, spurious interrupts might occur.  No return
- * value.
- */
-void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
 {
-        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
+        u32 m;
-                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
-        /* OCP barrier */
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
-        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+                                             OMAP2_PM_PWSTCTRL, m);
 }
-/**
+int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
- * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
- * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
- *
- * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
- * to be used in the PRM interrupt handler resume callback to restore
- * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
- * barrier should be needed here; any pending PRM interrupts will fire
- * once the writes reach the PRM.  No return value.
- */
-void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 {
-        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
+        u32 v;
-                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
+        omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+        return 0;
 }
-/**
+int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
- * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
- *
- * Clear any previously-latched I/O wakeup events and ensure that the
- * I/O wakeup gates are aligned with the current mux settings.  Works
- * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
- * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
- * return value.
- */
-void omap3xxx_prm_reconfigure_io_chain(void)
 {
-        int i = 0;
+        u32 c = 0;
-        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+        /*
-                                   PM_WKEN);
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
-        omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+        /* XXX Is this udelay() value meaningful? */
-                          OMAP3430_ST_IO_CHAIN_MASK,
+        while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
-                          MAX_IOPAD_LATCH_TIME, i);
+                OMAP_INTRANSITION_MASK) &&
-        if (i == MAX_IOPAD_LATCH_TIME)
+                (c++ < PWRDM_TRANSITION_BAILOUT))
-                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+                        udelay(1);
-        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+        if (c > PWRDM_TRANSITION_BAILOUT) {
-                                     PM_WKEN);
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
+        }
-        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
-                                   PM_WKST);
-        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+        return 0;
 }
-/**
+int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
- * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+                          struct clockdomain *clkdm2)
- *
+{
- * Activates the I/O wakeup event latches and allows events logged by
+        omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
- * those latches to signal a wakeup event to the PRCM.  For I/O
+                                   clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
- * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
+        return 0;
- * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
+}
- * No return value.
- */
+int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
-static void __init omap3xxx_prm_enable_io_wakeup(void)
+                          struct clockdomain *clkdm2)
+{
+        omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                     clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        return 0;
+}
+int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
+                           struct clockdomain *clkdm2)
 {
-        if (omap3_has_io_wakeup())
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
-                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                             PM_WKDEP, (1 << clkdm2->dep_bit));
-                                           PM_WKEN);
 }
-static int __init omap3xxx_prcm_init(void)
+int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
 {
-        int ret = 0;
+        struct clkdm_dep *cd;
+        u32 mask = 0;
-        if (cpu_is_omap34xx()) {
-                omap3xxx_prm_enable_io_wakeup();
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
-                ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+                if (!cd->clkdm)
-                if (!ret)
+                        continue; /* only happens if data is erroneous */
-                        irq_set_status_flags(omap_prcm_event_to_irq("io"),
-                                             IRQ_NOAUTOEN);
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
        }
-        return ret;
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                                     PM_WKDEP);
+        return 0;
 }
-subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index c19d249b4816..9624b40836d4 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -1,7 +1,7 @@
 /*
- * OMAP2/3 Power/Reset Management (PRM) register definitions
+ * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
 *
- * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
 * Copyright (C) 2008-2010 Nokia Corporation
 * Paul Walmsley
 *
@@ -19,160 +19,6 @@
 #include "prcm-common.h"
 #include "prm.h"
-#define OMAP2420_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
-#define OMAP2430_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
-#define OMAP34XX_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
-/*
- * OMAP2-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
- * bits.)
- *
- */
-#define OMAP2_PRCM_REVISION_OFFSET      0x0000
-#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
-#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
-#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
-#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
-#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
-#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
-#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
-#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
-#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
-#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
-#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
-#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
-#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
-#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
-#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
-#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
-/*
- * OMAP3-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
- * bits.)
- */
-#define OMAP3_PRM_REVISION_OFFSET       0x0004
-#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
-#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
-#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
-#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
-#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
-#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
-#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
-#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
-#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
-#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
-#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
-#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
-#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
-#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
-#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
-#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
-#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
-#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
-#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
-#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
-#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
-#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
-#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
-#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
-#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
-#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
-#define OMAP3_PRM_RSTST_OFFSET  0x0058
-#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
-#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
-#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
-#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
-#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
-#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
-#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
-#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
-#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
-#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
-#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
-#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
-#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
-#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
-#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
-#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
-#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
-#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
-#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
-#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
-#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
-#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
-#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
-#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
-#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
-#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
-#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
-#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
-#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
-#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
-#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
-#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
-#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
-#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
-#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
-#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
-#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
-#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
-#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
-#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
-#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
-#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
-#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 /*
 * Module specific PRM register offsets from PRM_BASE + domain offset
 *
@@ -200,66 +46,83 @@
 #define PM_EVGENONTIM                                   0x00d8
 #define PM_EVGENOFFTIM                                  0x00dc
-/* OMAP2xxx specific register offsets */
-#define OMAP24XX_PM_WKEN2                               0x00a4
-#define OMAP24XX_PM_WKST2                               0x00b4
-#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
-/* OMAP3 specific register offsets */
+#ifndef __ASSEMBLER__
-#define OMAP3430ES2_PM_WKEN3                            0x00f0
-#define OMAP3430ES2_PM_WKST3                            0x00b8
-#define OMAP3430_PM_MPUGRPSEL                           0x00a4
-#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
-#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
-#define OMAP3430_PM_IVAGRPSEL                           0x00a8
-#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
-#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
-#define OMAP3430_PM_PREPWSTST                           0x00e8
-#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
-#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+#include <linux/io.h>
+#include "powerdomain.h"
-#ifndef __ASSEMBLER__
 /* Power/reset management domain register get/set */
-extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
+static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
-extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
+{
-extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+        return __raw_readl(prm_base + module + idx);
-extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+}
-extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
-extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, prm_base + module + idx);
+}
+/* Read-modify-write a register in a PRM module. Caller must lock */
+static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
+                                             s16 idx)
+{
+        u32 v;
+        v = omap2_prm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_prm_write_mod_reg(v, module, idx);
+        return v;
+}
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        u32 v;
+        v = omap2_prm_read_mod_reg(domain, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+        return v;
+}
+static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
 /* These omap2_ PRM functions apply to both OMAP2 and 3 */
 extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
-/* OMAP3-specific VP functions */
+extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
-u32 omap3_prm_vp_check_txdone(u8 vp_id);
+extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
-void omap3_prm_vp_clear_txdone(u8 vp_id);
+extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
+extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
-/*
+                                    u8 pwrst);
- * OMAP3 access functions for voltage controller (VC) and
+extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
- * voltage proccessor (VP) in the PRM.
+                                     u8 pwrst);
- */
+extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-extern u32 omap3_prm_vcvp_read(u8 offset);
+extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
-extern void omap3_prm_vcvp_write(u32 val, u8 offset);
+extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
-extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
-extern void omap3xxx_prm_reconfigure_io_chain(void);
+extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
+                                 struct clockdomain *clkdm2);
-/* PRM interrupt-related functions */
+extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
-extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+                                 struct clockdomain *clkdm2);
-extern void omap3xxx_prm_ocp_barrier(void);
+extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
-extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+                                  struct clockdomain *clkdm2);
-extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
 #endif /* __ASSEMBLER */
@@ -289,6 +152,7 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 /* Named PRCM_CLKSRC_CTRL on the 24XX */
 #define OMAP_SYSCLKDIV_SHIFT                            6
 #define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
+#define OMAP_SYSCLKDIV_WIDTH                            2
 #define OMAP_AUTOEXTCLKMODE_SHIFT                       3
 #define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
 #define OMAP_SYSCLKSEL_SHIFT                            0
@@ -348,7 +212,9 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 *
 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 */
+#define OMAP_GLOBALWARM_RST_SHIFT                       1
 #define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
+#define OMAP_GLOBALCOLD_RST_SHIFT                       0
 #define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
 /*
@@ -376,11 +242,4 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 #define OMAP_LOGICRETSTATE_MASK                         (1 << 2)
-/*
- * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
- * submodule to exit hardreset
- */
-#define MAX_MODULE_HARDRESET_WAIT               10000
 #endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index e7dbb6cf1255..1ac73883f891 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -19,9 +19,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
 #include "common.h"
+#include "powerdomain.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
@@ -133,3 +132,204 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
+static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
+                                (pwrst << OMAP_POWERSTATE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+        return v;
+}
+static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+        return v;
+}
+static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
+        v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
+        return v;
+}
+static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
+                                (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        return 0;
+}
+static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 m;
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LOGICSTATEST_MASK;
+        v >>= AM33XX_LOGICSTATEST_SHIFT;
+        return v;
+}
+static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v, m;
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+        return v;
+}
+static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                u8 pwrst)
+{
+        u32 m;
+        m = pwrdm->mem_on_mask[bank];
+        if (!m)
+                return -EINVAL;
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                        u8 pwrst)
+{
+        u32 m;
+        m = pwrdm->mem_ret_mask[bank];
+        if (!m)
+                return -EINVAL;
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+        m = pwrdm->mem_pwrst_mask[bank];
+        if (!m)
+                return -EINVAL;
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= m;
+        v >>= __ffs(m);
+        return v;
+}
+static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+        m = pwrdm->mem_retst_mask[bank];
+        if (!m)
+                return -EINVAL;
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+        return v;
+}
+static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+        /* XXX Is this udelay() value meaningful? */
+        while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
+                        & OMAP_INTRANSITION_MASK) &&
+                        (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
+        }
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+        return 0;
+}
+struct pwrdm_ops am33xx_pwrdm_operations = {
+        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst               = am33xx_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst          = am33xx_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst          = am33xx_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst         = am33xx_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst         = am33xx_pwrdm_read_logic_retst,
+        .pwrdm_clear_all_prev_pwrst     = am33xx_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = am33xx_pwrdm_set_lowpwrstchange,
+        .pwrdm_read_mem_pwrst           = am33xx_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst           = am33xx_pwrdm_read_mem_retst,
+        .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
new file mode 100644
index 000000000000..db198d058584
--- /dev/null
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -0,0 +1,420 @@
+/*
+ * OMAP3xxx PRM module functions
+ *
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include "common.h"
+#include <plat/cpu.h>
+#include "vp.h"
+#include "powerdomain.h"
+#include "prm3xxx.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "prm-regbits-34xx.h"
+static const struct omap_prcm_irq omap3_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
+        .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 1,
+        .irqs                   = omap3_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
+        .irq                    = 11 + OMAP_INTC_START,
+        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap3xxx_prm_restore_irqen,
+};
+/*
+ * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware
+ *   register (which are specific to OMAP3xxx SoCs) to reset source ID
+ *   bit shifts (which is an OMAP SoC-independent enumeration)
+ */
+static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = {
+        { OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
+        { OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
+        { OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
+        { OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
+        { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT,
+          OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
+        { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT,
+          OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
+        { OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
+        { OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT },
+        { -1, -1 },
+};
+/* PRM VP */
+/*
+ * struct omap3_vp - OMAP3 VP register access description.
+ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
+ */
+struct omap3_vp {
+        u32 tranxdone_status;
+};
+static struct omap3_vp omap3_vp[] = {
+        [OMAP3_VP_VDD_MPU_ID] = {
+                .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
+        },
+        [OMAP3_VP_VDD_CORE_ID] = {
+                .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
+        },
+};
+#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
+u32 omap3_prm_vp_check_txdone(u8 vp_id)
+{
+        struct omap3_vp *vp = &omap3_vp[vp_id];
+        u32 irqstatus;
+        irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
+                                           OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        return irqstatus & vp->tranxdone_status;
+}
+void omap3_prm_vp_clear_txdone(u8 vp_id)
+{
+        struct omap3_vp *vp = &omap3_vp[vp_id];
+        omap2_prm_write_mod_reg(vp->tranxdone_status,
+                                OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+}
+u32 omap3_prm_vcvp_read(u8 offset)
+{
+        return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
+}
+void omap3_prm_vcvp_write(u32 val, u8 offset)
+{
+        omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
+}
+u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
+{
+        return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
+}
+/**
+ * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC
+ *
+ * Set the DPLL3 reset bit, which should reboot the SoC.  This is the
+ * recommended way to restart the SoC, considering Errata i520.  No
+ * return value.
+ */
+void omap3xxx_prm_dpll3_reset(void)
+{
+        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD,
+                                   OMAP2_RM_RSTCTRL);
+        /* OCP barrier */
+        omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL);
+}
+/**
+ * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to a u32, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the u32 pointed to by @events.
+ * No return value.
+ */
+void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+{
+        u32 mask, st;
+        /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
+        mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        events[0] = mask & st;
+}
+/**
+ * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap3xxx_prm_ocp_barrier(void)
+{
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+/**
+ * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
+ * must be allocated by the caller.  Intended to be used in the PRM
+ * interrupt handler suspend callback.  The OCP barrier is needed to
+ * ensure the write to disable PRM interrupts reaches the PRM before
+ * returning; otherwise, spurious interrupts might occur.  No return
+ * value.
+ */
+void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
+                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        /* OCP barrier */
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+/**
+ * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
+ * to be used in the PRM interrupt handler resume callback to restore
+ * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
+ * barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
+                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+}
+/**
+ * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
+ * return value.
+ */
+void omap3xxx_prm_reconfigure_io_chain(void)
+{
+        int i = 0;
+        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKEN);
+        omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+                          OMAP3430_ST_IO_CHAIN_MASK,
+                          MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                     PM_WKEN);
+        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKST);
+        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+}
+/**
+ * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O
+ * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
+ * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
+ * No return value.
+ */
+static void __init omap3xxx_prm_enable_io_wakeup(void)
+{
+        if (omap3_has_io_wakeup())
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                           PM_WKEN);
+}
+/**
+ * omap3xxx_prm_read_reset_sources - return the last SoC reset source
+ *
+ * Return a u32 representing the last reset sources of the SoC.  The
+ * returned reset source bits are standardized across OMAP SoCs.
+ */
+static u32 omap3xxx_prm_read_reset_sources(void)
+{
+        struct prm_reset_src_map *p;
+        u32 r = 0;
+        u32 v;
+        v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
+        p = omap3xxx_prm_reset_src_map;
+        while (p->reg_shift >= 0 && p->std_shift >= 0) {
+                if (v & (1 << p->reg_shift))
+                        r |= 1 << p->std_shift;
+                p++;
+        }
+        return r;
+}
+/* Powerdomain low-level functions */
+/* Applicable only for OMAP3. Not supported on OMAP2 */
+static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTPOWERSTATEENTERED_MASK);
+}
+static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTLOGICSTATEENTERED_MASK);
+}
+static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP3430_LASTMEM1STATEENTERED_MASK;
+        case 1:
+                return OMAP3430_LASTMEM2STATEENTERED_MASK;
+        case 2:
+                return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
+        case 3:
+                return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+        m = omap3_get_mem_bank_lastmemst_mask(bank);
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                OMAP3430_PM_PREPWSTST, m);
+}
+static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
+        return 0;
+}
+static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(0,
+                                          1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+}
+static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          0, pwrdm->prcm_offs,
+                                          OMAP2_PM_PWSTCTRL);
+}
+struct pwrdm_ops omap3_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
+        .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
+        .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
+        .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
+/*
+ *
+ */
+static struct prm_ll_data omap3xxx_prm_ll_data = {
+        .read_reset_sources = &omap3xxx_prm_read_reset_sources,
+};
+int __init omap3xxx_prm_init(void)
+{
+        if (!cpu_is_omap34xx())
+                return 0;
+        return prm_register(&omap3xxx_prm_ll_data);
+}
+static int __init omap3xxx_prm_late_init(void)
+{
+        int ret;
+        if (!cpu_is_omap34xx())
+                return 0;
+        omap3xxx_prm_enable_io_wakeup();
+        ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+        if (!ret)
+                irq_set_status_flags(omap_prcm_event_to_irq("io"),
+                                     IRQ_NOAUTOEN);
+        return ret;
+}
+subsys_initcall(omap3xxx_prm_late_init);
+static void __exit omap3xxx_prm_exit(void)
+{
+        if (!cpu_is_omap34xx())
+                return;
+        /* Should never happen */
+        WARN(prm_unregister(&omap3xxx_prm_ll_data),
+             "%s: prm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap3xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
new file mode 100644
index 000000000000..277f71794e61
--- /dev/null
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -0,0 +1,163 @@
+/*
+ * OMAP3xxx Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
+#include "prcm-common.h"
+#include "prm.h"
+#include "prm2xxx_3xxx.h"
+#define OMAP34XX_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+/*
+ * OMAP3-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ */
+#define OMAP3_PRM_REVISION_OFFSET       0x0004
+#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
+#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
+#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
+#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
+#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
+#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
+#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3_PRM_RSTST_OFFSET  0x0058
+#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
+#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
+#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
+#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
+#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
+#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
+#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
+#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
+#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
+#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
+#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
+#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+/* OMAP3 specific register offsets */
+#define OMAP3430ES2_PM_WKEN3                            0x00f0
+#define OMAP3430ES2_PM_WKST3                            0x00b8
+#define OMAP3430_PM_MPUGRPSEL                           0x00a4
+#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
+#define OMAP3430_PM_IVAGRPSEL                           0x00a8
+#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
+#define OMAP3430_PM_PREPWSTST                           0x00e8
+#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+#ifndef __ASSEMBLER__
+/* OMAP3-specific VP functions */
+u32 omap3_prm_vp_check_txdone(u8 vp_id);
+void omap3_prm_vp_clear_txdone(u8 vp_id);
+/*
+ * OMAP3 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap3_prm_vcvp_read(u8 offset);
+extern void omap3_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+extern void omap3xxx_prm_reconfigure_io_chain(void);
+/* PRM interrupt-related functions */
+extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+extern void omap3xxx_prm_ocp_barrier(void);
+extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+extern void omap3xxx_prm_dpll3_reset(void);
+extern int __init omap3xxx_prm_init(void);
+extern u32 omap3xxx_prm_get_reset_sources(void);
+#endif /* __ASSEMBLER */
+#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index f0c4d5f4a174..7498bc77fe8b 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -1,10 +1,11 @@
 /*
 * OMAP4 PRM module functions
 *
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2012 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 * Benoît Cousson
 * Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -17,7 +18,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/prcm.h>
 #include "soc.h"
 #include "iomap.h"
@@ -27,6 +27,9 @@
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prminst44xx.h"
+#include "powerdomain.h"
+/* Static data */
 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
        OMAP_PRCM_IRQ("wkup",   0,      0),
@@ -46,6 +49,33 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
        .restore_irqen          = &omap44xx_prm_restore_irqen,
 };
+/*
+ * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
+ *   hardware register (which are specific to OMAP44xx SoCs) to reset
+ *   source ID bit shifts (which is an OMAP SoC-independent
+ *   enumeration)
+ */
+static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
+        { OMAP4430_RST_GLOBAL_WARM_SW_SHIFT,
+          OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
+        { OMAP4430_RST_GLOBAL_COLD_SW_SHIFT,
+          OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
+        { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
+          OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
+        { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
+        { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
+        { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
+        { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
+          OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
+        { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
+          OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
+        { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
+          OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
+        { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
+        { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
+        { -1, -1 },
+};
 /* PRM low-level functions */
 /* Read a register in a CM/PRM instance in the PRM module */
@@ -291,12 +321,359 @@ static void __init omap44xx_prm_enable_io_wakeup(void)
                                    OMAP4_PRM_IO_PMCTRL_OFFSET);
 }
-static int __init omap4xxx_prcm_init(void)
+/**
+ * omap44xx_prm_read_reset_sources - return the last SoC reset source
+ *
+ * Return a u32 representing the last reset sources of the SoC.  The
+ * returned reset source bits are standardized across OMAP SoCs.
+ */
+static u32 omap44xx_prm_read_reset_sources(void)
+{
+        struct prm_reset_src_map *p;
+        u32 r = 0;
+        u32 v;
+        v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
+                                    OMAP4_RM_RSTST);
+        p = omap44xx_prm_reset_src_map;
+        while (p->reg_shift >= 0 && p->std_shift >= 0) {
+                if (v & (1 << p->reg_shift))
+                        r |= 1 << p->std_shift;
+                p++;
+        }
+        return r;
+}
+/**
+ * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
+ * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
+ * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
+ * @idx: CONTEXT register offset
+ *
+ * Return 1 if any bits were set in the *_CONTEXT_* register
+ * identified by (@part, @inst, @idx), which means that some context
+ * was lost for that module; otherwise, return 0.
+ */
+static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
+{
+        return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
+}
+/**
+ * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
+ * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
+ * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
+ * @idx: CONTEXT register offset
+ *
+ * Clear hardware context loss bits for the module identified by
+ * (@part, @inst, @idx).  No return value.  XXX Writes to reserved bits;
+ * is there a way to avoid this?
+ */
+static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
+                                                      u16 idx)
+{
+        omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
+}
+/* Powerdomain low-level functions */
+static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
+                                        (pwrst << OMAP_POWERSTATE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
+        v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
+                                        (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTST);
+        return 0;
+}
+static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+        v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                    u8 pwrst)
+{
+        u32 m;
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                     u8 pwrst)
 {
-        if (cpu_is_omap44xx()) {
+        u32 m;
-                omap44xx_prm_enable_io_wakeup();
-                return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LOGICSTATEST_MASK;
+        v >>= OMAP4430_LOGICSTATEST_SHIFT;
+        return v;
+}
+static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v;
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP4430_LOGICRETSTATE_MASK;
+        v >>= OMAP4430_LOGICRETSTATE_SHIFT;
+        return v;
+}
+/**
+ * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
+ * @pwrdm: struct powerdomain * to read the state for
+ *
+ * Reads the previous logic powerstate for a powerdomain. This
+ * function must determine the previous logic powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next retention logic state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether the logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        int state;
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+        return omap4_pwrdm_read_logic_retst(pwrdm);
+}
+static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= m;
+        v >>= __ffs(m);
+        return v;
+}
+static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= m;
+        v >>= __ffs(m);
+        return v;
+}
+/**
+ * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
+ * @pwrdm: struct powerdomain * to read mem powerstate for
+ * @bank: memory bank index
+ *
+ * Reads the previous memory powerstate for a powerdomain. This
+ * function must determine the previous memory powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next memory retention state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        int state;
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
+}
+static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
+                                            pwrdm->prcm_offs,
+                                            OMAP4_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+               (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
        }
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
        return 0;
 }
-subsys_initcall(omap4xxx_prcm_init);
+struct pwrdm_ops omap4_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
+        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
+        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
+        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
+        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
+};
+/*
+ * XXX document
+ */
+static struct prm_ll_data omap44xx_prm_ll_data = {
+        .read_reset_sources = &omap44xx_prm_read_reset_sources,
+        .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
+        .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
+};
+int __init omap44xx_prm_init(void)
+{
+        if (!cpu_is_omap44xx())
+                return 0;
+        return prm_register(&omap44xx_prm_ll_data);
+}
+static int __init omap44xx_prm_late_init(void)
+{
+        if (!cpu_is_omap44xx())
+                return 0;
+        omap44xx_prm_enable_io_wakeup();
+        return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+}
+subsys_initcall(omap44xx_prm_late_init);
+static void __exit omap44xx_prm_exit(void)
+{
+        if (!cpu_is_omap44xx())
+                return;
+        /* Should never happen */
+        WARN(prm_unregister(&omap44xx_prm_ll_data),
+             "%s: prm_ll_data function pointer mismatch\n", __func__);
+}
+__exitcall(omap44xx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index ee72ae6bd8c9..22b0979206ca 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -771,6 +771,9 @@ extern void omap44xx_prm_ocp_barrier(void);
 extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
 extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+extern int __init omap44xx_prm_init(void);
+extern u32 omap44xx_prm_get_reset_sources(void);
 # endif
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 6b4d332be2f6..228b850e632f 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -24,11 +24,11 @@
 #include <linux/interrupt.h>
 #include <linux/slab.h>
-#include <plat/common.h>
-#include <plat/prcm.h>
 #include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
+#include "prm3xxx.h"
 #include "prm44xx.h"
+#include "common.h"
 /*
 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -53,6 +53,16 @@ static struct irq_chip_generic **prcm_irq_chips;
 */
 static struct omap_prcm_irq_setup *prcm_irq_setup;
+/* prm_base: base virtual address of the PRM IP block */
+void __iomem *prm_base;
+/*
+ * prm_ll_data: function pointers to SoC-specific implementations of
+ * common PRM functions
+ */
+static struct prm_ll_data null_prm_ll_data;
+static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
 /* Private functions */
 /*
@@ -319,64 +329,127 @@ err:
        return -ENOMEM;
 }
-/*
+/**
- * Stubbed functions so that common files continue to build when
+ * omap2_set_globals_prm - set the PRM base address (for early use)
- * custom builds are used
+ * @prm: PRM base virtual address
- * XXX These are temporary and should be removed at the earliest possible
+ *
- * opportunity
+ * XXX Will be replaced when the PRM/CM drivers are completed.
 */
-u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx)
+void __init omap2_set_globals_prm(void __iomem *prm)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        prm_base = prm;
-        return 0;
 }
-void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+/**
+ * prm_read_reset_sources - return the sources of the SoC's last reset
+ *
+ * Return a u32 bitmask representing the reset sources that caused the
+ * SoC to reset.  The low-level per-SoC functions called by this
+ * function remap the SoC-specific reset source bits into an
+ * OMAP-common set of reset source bits, defined in
+ * arch/arm/mach-omap2/prm.h.  Returns the standardized reset source
+ * u32 bitmask from the hardware upon success, or returns (1 <<
+ * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
+ * function was registered.
+ */
+u32 prm_read_reset_sources(void)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
-}
-u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
+        if (prm_ll_data->read_reset_sources)
-                s16 module, s16 idx)
+                ret = prm_ll_data->read_reset_sources();
-{
+        else
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+                WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
-        return 0;
-}
-u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+        return ret;
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
-        return 0;
 }
-u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+/**
+ * prm_was_any_context_lost_old - was device context lost? (old API)
+ * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
+ * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
+ * @idx: CONTEXT register offset
+ *
+ * Return 1 if any bits were set in the *_CONTEXT_* register
+ * identified by (@part, @inst, @idx), which means that some context
+ * was lost for that module; otherwise, return 0.  XXX Deprecated;
+ * callers need to use a less-SoC-dependent way to identify hardware
+ * IP blocks.
+ */
+bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        bool ret = true;
-        return 0;
-}
-u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+        if (prm_ll_data->was_any_context_lost_old)
-{
+                ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        else
-        return 0;
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+        return ret;
 }
-int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+/**
+ * prm_clear_context_lost_flags_old - clear context loss flags (old API)
+ * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
+ * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
+ * @idx: CONTEXT register offset
+ *
+ * Clear hardware context loss bits for the module identified by
+ * (@part, @inst, @idx).  No return value.  XXX Deprecated; callers
+ * need to use a less-SoC-dependent way to identify hardware IP
+ * blocks.
+ */
+void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        if (prm_ll_data->clear_context_loss_flags_old)
-        return 0;
+                prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
+        else
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
 }
-int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+/**
+ * prm_register - register per-SoC low-level data with the PRM
+ * @pld: low-level per-SoC OMAP PRM data & function pointers to register
+ *
+ * Register per-SoC low-level OMAP PRM data and function pointers with
+ * the OMAP PRM common interface.  The caller must keep the data
+ * pointed to by @pld valid until it calls prm_unregister() and
+ * it returns successfully.  Returns 0 upon success, -EINVAL if @pld
+ * is NULL, or -EEXIST if prm_register() has already been called
+ * without an intervening prm_unregister().
+ */
+int prm_register(struct prm_ll_data *pld)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        if (!pld)
+                return -EINVAL;
+        if (prm_ll_data != &null_prm_ll_data)
+                return -EEXIST;
+        prm_ll_data = pld;
        return 0;
 }
-int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
+/**
-                                                u8 st_shift)
+ * prm_unregister - unregister per-SoC low-level data & function pointers
+ * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
+ *
+ * Unregister per-SoC low-level OMAP PRM data and function pointers
+ * that were previously registered with prm_register().  The
+ * caller may not destroy any of the data pointed to by @pld until
+ * this function returns successfully.  Returns 0 upon success, or
+ * -EINVAL if @pld is NULL or if @pld does not match the struct
+ * prm_ll_data * previously registered by prm_register().
+ */
+int prm_unregister(struct prm_ll_data *pld)
 {
-        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        if (!pld || prm_ll_data != pld)
+                return -EINVAL;
+        prm_ll_data = &null_prm_ll_data;
        return 0;
 }
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index 46f2efb36596..a2ede2d65481 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -30,4 +30,6 @@ extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
 extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
                                            u16 rstctrl_offs);
+extern void omap_prm_base_init(void);
 #endif
diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h
index 701bf2d32949..e897ac89a3fd 100644
--- a/arch/arm/mach-omap2/scrm44xx.h
+++ b/arch/arm/mach-omap2/scrm44xx.h
@@ -127,12 +127,14 @@
 /* AUXCLKREQ0 */
 #define OMAP4_MAPPING_SHIFT                     2
 #define OMAP4_MAPPING_MASK                      (0x7 << 2)
+#define OMAP4_MAPPING_WIDTH                     3
 #define OMAP4_ACCURACY_SHIFT                    1
 #define OMAP4_ACCURACY_MASK                     (1 << 1)
 /* AUXCLK0 */
 #define OMAP4_CLKDIV_SHIFT                      16
 #define OMAP4_CLKDIV_MASK                       (0xf << 16)
+#define OMAP4_CLKDIV_WIDTH                      4
 #define OMAP4_DISABLECLK_SHIFT                  9
 #define OMAP4_DISABLECLK_MASK                   (1 << 9)
 #define OMAP4_ENABLE_SHIFT                      8
diff --git a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
index 8bfaf342a028..1ee58c281a31 100644
--- a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
+++ b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
@@ -11,7 +11,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
 #define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
-#include <plat/sdrc.h>
+#include "sdrc.h"
 /* Hynix H8MBX00U0MER-0EM */
 static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
index a391b4939f74..85cccc004c06 100644
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -14,7 +14,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
 #define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
-#include <plat/sdrc.h>
+#include "sdrc.h"
 /* Micron MT46H32M32LF-6 */
 /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index 845c4fd2b125..0fa7ffa9b5ed 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -18,10 +18,8 @@
 #include <linux/io.h>
 #include "common.h"
-#include <plat/clock.h>
-#include <plat/sdrc.h>
 #include "sdram-nokia.h"
+#include "sdrc.h"
 /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
 struct sdram_timings {
diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
index cd4352917022..003f7bf4e2e3 100644
--- a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
+++ b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
@@ -11,7 +11,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
 #define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
-#include <plat/sdrc.h>
+#include "sdrc.h"
 /* Numonyx  M65KXXXXAM */
 static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 0e518a72831f..8dc3de5ebb5b 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -14,7 +14,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
 #define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
-#include <plat/sdrc.h>
+#include "sdrc.h"
 /* Qimonda HYB18M512160AF-6 */
 static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index e3d345f46409..dae7e4804a48 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -24,10 +24,7 @@
 #include <linux/io.h>
 #include "common.h"
-#include <plat/clock.h>
+#include "clock.h"
-#include <plat/sram.h>
-#include <plat/sdrc.h>
 #include "sdrc.h"
 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
@@ -115,12 +112,10 @@ int omap2_sdrc_get_params(unsigned long r,
 }
-void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
+void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
 {
-        if (omap2_globals->sdrc)
+        omap2_sdrc_base = sdrc;
-                omap2_sdrc_base = omap2_globals->sdrc;
+        omap2_sms_base = sms;
-        if (omap2_globals->sms)
-                omap2_sms_base = omap2_globals->sms;
 }
 /**
@@ -160,19 +155,3 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
        sdrc_write_reg(l, SDRC_POWER);
        omap2_sms_save_context();
 }
-void omap2_sms_write_rot_control(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_CONTROL(ctx));
-}
-void omap2_sms_write_rot_size(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_SIZE(ctx));
-}
-void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
-}
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index b3f83799e6cf..446aa13511fd 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -2,12 +2,14 @@
 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
 /*
- * OMAP2 SDRC register definitions
+ * OMAP2/3 SDRC/SMS macros and prototypes
 *
- * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Nokia Corporation
 *
- * Written by Paul Walmsley
+ * Paul Walmsley
+ * Tony Lindgren
+ * Richard Woodruff
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -15,8 +17,6 @@
 */
 #undef DEBUG
-#include <plat/sdrc.h>
 #ifndef __ASSEMBLER__
 #include <linux/io.h>
@@ -50,6 +50,60 @@ static inline u32 sms_read_reg(u16 reg)
 {
        return __raw_readl(OMAP_SMS_REGADDR(reg));
 }
+extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
+/**
+ * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
+ * @rate: SDRC clock rate (in Hz)
+ * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
+ * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
+ * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
+ * @mr: Value to program to SDRC_MR for this rate
+ *
+ * This structure holds a pre-computed set of register values for the
+ * SDRC for a given SDRC clock rate and SDRAM chip.  These are
+ * intended to be pre-computed and specified in an array in the board-*.c
+ * files.  The structure is keyed off the 'rate' field.
+ */
+struct omap_sdrc_params {
+        unsigned long rate;
+        u32 actim_ctrla;
+        u32 actim_ctrlb;
+        u32 rfr_ctrl;
+        u32 mr;
+};
+#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1);
+#else
+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                          struct omap_sdrc_params *sdrc_cs1) {};
+#endif
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1);
+void omap2_sms_save_context(void);
+void omap2_sms_restore_context(void);
+struct memory_timings {
+        u32 m_type;             /* ddr = 1, sdr = 0 */
+        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
+        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
+        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
+        u32 base_cs;            /* base chip select to use for calculations */
+};
+extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
+struct omap_sdrc_params *rx51_get_sdram_timings(void);
+u32 omap2xxx_sdrc_dll_is_unlocked(void);
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
 #else
 #define OMAP242X_SDRC_REGADDR(reg)                                      \
                        OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
@@ -57,6 +111,7 @@ static inline u32 sms_read_reg(u16 reg)
                        OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
 #define OMAP34XX_SDRC_REGADDR(reg)                                      \
                        OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
 #endif  /* __ASSEMBLER__ */
 /* Minimum frequency that the SDRC DLL can lock at */
@@ -74,4 +129,85 @@ static inline u32 sms_read_reg(u16 reg)
 */
 #define SDRC_MPURATE_LOOPS              96
+/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
+#define SDRC_SYSCONFIG          0x010
+#define SDRC_CS_CFG             0x040
+#define SDRC_SHARING            0x044
+#define SDRC_ERR_TYPE           0x04C
+#define SDRC_DLLA_CTRL          0x060
+#define SDRC_DLLA_STATUS        0x064
+#define SDRC_DLLB_CTRL          0x068
+#define SDRC_DLLB_STATUS        0x06C
+#define SDRC_POWER              0x070
+#define SDRC_MCFG_0             0x080
+#define SDRC_MR_0               0x084
+#define SDRC_EMR2_0             0x08c
+#define SDRC_ACTIM_CTRL_A_0     0x09c
+#define SDRC_ACTIM_CTRL_B_0     0x0a0
+#define SDRC_RFR_CTRL_0         0x0a4
+#define SDRC_MANUAL_0           0x0a8
+#define SDRC_MCFG_1             0x0B0
+#define SDRC_MR_1               0x0B4
+#define SDRC_EMR2_1             0x0BC
+#define SDRC_ACTIM_CTRL_A_1     0x0C4
+#define SDRC_ACTIM_CTRL_B_1     0x0C8
+#define SDRC_RFR_CTRL_1         0x0D4
+#define SDRC_MANUAL_1           0x0D8
+#define SDRC_POWER_AUTOCOUNT_SHIFT      8
+#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT        4
+#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
+/*
+ * These values represent the number of memory clock cycles between
+ * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
+ * rows per device, and include a subtraction of a 50 cycle window in the
+ * event that the autorefresh command is delayed due to other SDRC activity.
+ * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
+ * counter reaches 0.
+ *
+ * These represent optimal values for common parts, it won't work for all.
+ * As long as you scale down, most parameters are still work, they just
+ * become sub-optimal. The RFR value goes in the opposite direction. If you
+ * don't adjust it down as your clock period increases the refresh interval
+ * will not be met. Setting all parameters for complete worst case may work,
+ * but may cut memory performance by 2x. Due to errata the DLLs need to be
+ * unlocked and their value needs run time calibration. A dynamic call is
+ * need for that as no single right value exists acorss production samples.
+ *
+ * Only the FULL speed values are given. Current code is such that rate
+ * changes must be made at DPLLoutx2. The actual value adjustment for low
+ * frequency operation will be handled by omap_set_performance()
+ *
+ * By having the boot loader boot up in the fastest L4 speed available likely
+ * will result in something which you can switch between.
+ */
+#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
+#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
+#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
+#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
+#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
+/*
+ * SMS register access
+ */
+#define OMAP242X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+/* SMS register offsets - read/write with sms_{read,write}_reg() */
+#define SMS_SYSCONFIG                   0x010
+/* REVISIT: fill in other SMS registers here */
 #endif
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 73e55e485329..907291714643 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,16 +24,13 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
-#include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
 #include "clock.h"
 #include "sdrc.h"
+#include "sram.h"
 /* Memory timing, DLL mode flags */
 #define M_DDR           1
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index a507cd6cf4f1..93d102535c85 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -26,21 +26,22 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 #include <linux/console.h>
+#include <linux/omap-dma.h>
 #include <plat/omap-serial.h>
-#include "common.h"
-#include <plat/dma.h>
-#include <plat/omap_hwmod.h>
-#include <plat/omap_device.h>
-#include <plat/omap-pm.h>
-#include <plat/serial.h>
+#include "common.h"
+#include "omap_hwmod.h"
+#include "omap_device.h"
+#include "omap-pm.h"
+#include "soc.h"
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
 #include "cm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
 #include "control.h"
 #include "mux.h"
+#include "serial.h"
 /*
 * NOTE: By default the serial auto_suspend timeout is disabled as it causes
diff --git a/arch/arm/mach-omap2/serial.h b/arch/arm/mach-omap2/serial.h
new file mode 100644
index 000000000000..c4014f013df0
--- /dev/null
+++ b/arch/arm/mach-omap2/serial.h
@@ -0,0 +1 @@
+#include <mach/serial.h>
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 506987979c1c..d1dedc8195ed 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,13 +26,12 @@
 #include <asm/assembler.h>
-#include <plat/sram.h>
 #include "omap34xx.h"
 #include "iomap.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
-#include "prm2xxx_3xxx.h"
+#include "prm3xxx.h"
 #include "sdrc.h"
+#include "sram.h"
 #include "control.h"
 /*
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index fc9b96daf851..f31d90774de0 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -1,7 +1,469 @@
-#include <plat/cpu.h>
+/*
+ * OMAP cpu type detection
+ *
+ * Copyright (C) 2004, 2008 Nokia Corporation
+ *
+ * Copyright (C) 2009-11 Texas Instruments.
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
 #include "omap24xx.h"
 #include "omap34xx.h"
 #include "omap44xx.h"
 #include "ti81xx.h"
 #include "am33xx.h"
 #include "omap54xx.h"
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP2
+#undef OMAP_NAME
+#ifdef CONFIG_SOC_OMAP2420
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2420
+# endif
+#endif
+#ifdef CONFIG_SOC_OMAP2430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2430
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap3
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap4
+# endif
+#endif
+#ifdef CONFIG_SOC_OMAP5
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap5
+# endif
+#endif
+#ifdef CONFIG_SOC_AM33XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am33xx
+# endif
+#endif
+/*
+ * Omap device type i.e. EMU/HS/TST/GP/BAD
+ */
+#define OMAP2_DEVICE_TYPE_TEST          0
+#define OMAP2_DEVICE_TYPE_EMU           1
+#define OMAP2_DEVICE_TYPE_SEC           2
+#define OMAP2_DEVICE_TYPE_GP            3
+#define OMAP2_DEVICE_TYPE_BAD           4
+int omap_type(void);
+/*
+ * omap_rev bits:
+ * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
+ * CPU revision (See _REV_ defined in cpu.h)    [15:08]
+ * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
+ */
+unsigned int omap_rev(void);
+/*
+ * Get the CPU revision for OMAP devices
+ */
+#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
+/*
+ * Macros to group OMAP into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
+ * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
+ * cpu_is_omap243x():   True for OMAP2430
+ * cpu_is_omap343x():   True for OMAP3430
+ * cpu_is_omap443x():   True for OMAP4430
+ * cpu_is_omap446x():   True for OMAP4460
+ * cpu_is_omap447x():   True for OMAP4470
+ * soc_is_omap543x():   True for OMAP5430, OMAP5432
+ */
+#define GET_OMAP_CLASS  (omap_rev() & 0xff)
+#define IS_OMAP_CLASS(class, id)                        \
+static inline int is_omap ##class (void)                \
+{                                                       \
+        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
+}
+#define GET_AM_CLASS    ((omap_rev() >> 24) & 0xff)
+#define IS_AM_CLASS(class, id)                          \
+static inline int is_am ##class (void)                  \
+{                                                       \
+        return (GET_AM_CLASS == (id)) ? 1 : 0;          \
+}
+#define GET_TI_CLASS    ((omap_rev() >> 24) & 0xff)
+#define IS_TI_CLASS(class, id)                  \
+static inline int is_ti ##class (void)          \
+{                                                       \
+        return (GET_TI_CLASS == (id)) ? 1 : 0;  \
+}
+#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
+#define IS_OMAP_SUBCLASS(subclass, id)                  \
+static inline int is_omap ##subclass (void)             \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+#define IS_TI_SUBCLASS(subclass, id)                    \
+static inline int is_ti ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+#define IS_AM_SUBCLASS(subclass, id)                    \
+static inline int is_am ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+IS_OMAP_CLASS(24xx, 0x24)
+IS_OMAP_CLASS(34xx, 0x34)
+IS_OMAP_CLASS(44xx, 0x44)
+IS_AM_CLASS(35xx, 0x35)
+IS_OMAP_CLASS(54xx, 0x54)
+IS_AM_CLASS(33xx, 0x33)
+IS_TI_CLASS(81xx, 0x81)
+IS_OMAP_SUBCLASS(242x, 0x242)
+IS_OMAP_SUBCLASS(243x, 0x243)
+IS_OMAP_SUBCLASS(343x, 0x343)
+IS_OMAP_SUBCLASS(363x, 0x363)
+IS_OMAP_SUBCLASS(443x, 0x443)
+IS_OMAP_SUBCLASS(446x, 0x446)
+IS_OMAP_SUBCLASS(447x, 0x447)
+IS_OMAP_SUBCLASS(543x, 0x543)
+IS_TI_SUBCLASS(816x, 0x816)
+IS_TI_SUBCLASS(814x, 0x814)
+IS_AM_SUBCLASS(335x, 0x335)
+#define cpu_is_omap24xx()               0
+#define cpu_is_omap242x()               0
+#define cpu_is_omap243x()               0
+#define cpu_is_omap34xx()               0
+#define cpu_is_omap343x()               0
+#define cpu_is_ti81xx()                 0
+#define cpu_is_ti816x()                 0
+#define cpu_is_ti814x()                 0
+#define soc_is_am35xx()                 0
+#define soc_is_am33xx()                 0
+#define soc_is_am335x()                 0
+#define cpu_is_omap44xx()               0
+#define cpu_is_omap443x()               0
+#define cpu_is_omap446x()               0
+#define cpu_is_omap447x()               0
+#define soc_is_omap54xx()               0
+#define soc_is_omap543x()               0
+#if defined(MULTI_OMAP2)
+# if defined(CONFIG_ARCH_OMAP2)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             is_omap24xx()
+# endif
+# if defined (CONFIG_SOC_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             is_omap242x()
+# endif
+# if defined (CONFIG_SOC_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             is_omap243x()
+# endif
+# if defined(CONFIG_ARCH_OMAP3)
+#  undef  cpu_is_omap34xx
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap34xx()             is_omap34xx()
+#  define cpu_is_omap343x()             is_omap343x()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP2)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             1
+# endif
+# if defined(CONFIG_SOC_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             1
+# endif
+# if defined(CONFIG_SOC_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP3)
+#  undef  cpu_is_omap34xx
+#  define cpu_is_omap34xx()             1
+# endif
+# if defined(CONFIG_SOC_OMAP3430)
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap343x()             1
+# endif
+#endif
+/*
+ * Macros to detect individual cpu types.
+ * These are only rarely needed.
+ * cpu_is_omap2420():   True for OMAP2420
+ * cpu_is_omap2422():   True for OMAP2422
+ * cpu_is_omap2423():   True for OMAP2423
+ * cpu_is_omap2430():   True for OMAP2430
+ * cpu_is_omap3430():   True for OMAP3430
+ */
+#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+IS_OMAP_TYPE(2420, 0x2420)
+IS_OMAP_TYPE(2422, 0x2422)
+IS_OMAP_TYPE(2423, 0x2423)
+IS_OMAP_TYPE(2430, 0x2430)
+IS_OMAP_TYPE(3430, 0x3430)
+#define cpu_is_omap2420()               0
+#define cpu_is_omap2422()               0
+#define cpu_is_omap2423()               0
+#define cpu_is_omap2430()               0
+#define cpu_is_omap3430()               0
+#define cpu_is_omap3630()               0
+#define soc_is_omap5430()               0
+/* These are needed for the common code */
+#ifdef CONFIG_ARCH_OMAP2PLUS
+#define cpu_is_omap7xx()                0
+#define cpu_is_omap15xx()               0
+#define cpu_is_omap16xx()               0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+#define cpu_class_is_omap1()            0
+#define cpu_class_is_omap2()            1
+#endif
+#if defined(CONFIG_ARCH_OMAP2)
+# undef  cpu_is_omap2420
+# undef  cpu_is_omap2422
+# undef  cpu_is_omap2423
+# undef  cpu_is_omap2430
+# define cpu_is_omap2420()              is_omap2420()
+# define cpu_is_omap2422()              is_omap2422()
+# define cpu_is_omap2423()              is_omap2423()
+# define cpu_is_omap2430()              is_omap2430()
+#endif
+#if defined(CONFIG_ARCH_OMAP3)
+# undef cpu_is_omap3430
+# undef cpu_is_ti81xx
+# undef cpu_is_ti816x
+# undef cpu_is_ti814x
+# undef soc_is_am35xx
+# define cpu_is_omap3430()              is_omap3430()
+# undef cpu_is_omap3630
+# define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti81xx()                is_ti81xx()
+# define cpu_is_ti816x()                is_ti816x()
+# define cpu_is_ti814x()                is_ti814x()
+# define soc_is_am35xx()                is_am35xx()
+#endif
+# if defined(CONFIG_SOC_AM33XX)
+# undef soc_is_am33xx
+# undef soc_is_am335x
+# define soc_is_am33xx()                is_am33xx()
+# define soc_is_am335x()                is_am335x()
+#endif
+# if defined(CONFIG_ARCH_OMAP4)
+# undef cpu_is_omap44xx
+# undef cpu_is_omap443x
+# undef cpu_is_omap446x
+# undef cpu_is_omap447x
+# define cpu_is_omap44xx()              is_omap44xx()
+# define cpu_is_omap443x()              is_omap443x()
+# define cpu_is_omap446x()              is_omap446x()
+# define cpu_is_omap447x()              is_omap447x()
+# endif
+# if defined(CONFIG_SOC_OMAP5)
+# undef soc_is_omap54xx
+# undef soc_is_omap543x
+# define soc_is_omap54xx()              is_omap54xx()
+# define soc_is_omap543x()              is_omap543x()
+#endif
+/* Various silicon revisions for omap2 */
+#define OMAP242X_CLASS          0x24200024
+#define OMAP2420_REV_ES1_0      OMAP242X_CLASS
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
+#define OMAP243X_CLASS          0x24300024
+#define OMAP2430_REV_ES1_0      OMAP243X_CLASS
+#define OMAP343X_CLASS          0x34300034
+#define OMAP3430_REV_ES1_0      OMAP343X_CLASS
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
+#define OMAP363X_CLASS          0x36300034
+#define OMAP3630_REV_ES1_0      OMAP363X_CLASS
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
+#define TI816X_CLASS            0x81600034
+#define TI8168_REV_ES1_0        TI816X_CLASS
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
+#define TI814X_CLASS            0x81400034
+#define TI8148_REV_ES1_0        TI814X_CLASS
+#define TI8148_REV_ES2_0        (TI814X_CLASS | (0x1 << 8))
+#define TI8148_REV_ES2_1        (TI814X_CLASS | (0x2 << 8))
+#define AM35XX_CLASS            0x35170034
+#define AM35XX_REV_ES1_0        AM35XX_CLASS
+#define AM35XX_REV_ES1_1        (AM35XX_CLASS | (0x1 << 8))
+#define AM335X_CLASS            0x33500033
+#define AM335X_REV_ES1_0        AM335X_CLASS
+#define OMAP443X_CLASS          0x44300044
+#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
+#define OMAP4430_REV_ES2_3      (OMAP443X_CLASS | (0x23 << 8))
+#define OMAP446X_CLASS          0x44600044
+#define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
+#define OMAP4460_REV_ES1_1      (OMAP446X_CLASS | (0x11 << 8))
+#define OMAP447X_CLASS          0x44700044
+#define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
+#define OMAP54XX_CLASS          0x54000054
+#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+void omap2xxx_check_revision(void);
+void omap3xxx_check_revision(void);
+void omap4xxx_check_revision(void);
+void omap5xxx_check_revision(void);
+void omap3xxx_check_features(void);
+void ti81xx_check_features(void);
+void omap4xxx_check_features(void);
+/*
+ * Runtime detection of OMAP3 features
+ *
+ * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
+ *    family have OS-level control over the I/O chain clock.  This is
+ *    to avoid a window during which wakeups could potentially be lost
+ *    during powerdomain transitions.  If this bit is set, it
+ *    indicates that the chip does support OS-level control of this
+ *    feature.
+ */
+extern u32 omap_features;
+#define OMAP3_HAS_L2CACHE               BIT(0)
+#define OMAP3_HAS_IVA                   BIT(1)
+#define OMAP3_HAS_SGX                   BIT(2)
+#define OMAP3_HAS_NEON                  BIT(3)
+#define OMAP3_HAS_ISP                   BIT(4)
+#define OMAP3_HAS_192MHZ_CLK            BIT(5)
+#define OMAP3_HAS_IO_WAKEUP             BIT(6)
+#define OMAP3_HAS_SDRC                  BIT(7)
+#define OMAP3_HAS_IO_CHAIN_CTRL         BIT(8)
+#define OMAP4_HAS_PERF_SILICON          BIT(9)
+#define OMAP3_HAS_FEATURE(feat,flag)                    \
+static inline unsigned int omap3_has_ ##feat(void)      \
+{                                                       \
+        return omap_features & OMAP3_HAS_ ##flag;       \
+}                                                       \
+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
+OMAP3_HAS_FEATURE(sgx, SGX)
+OMAP3_HAS_FEATURE(iva, IVA)
+OMAP3_HAS_FEATURE(neon, NEON)
+OMAP3_HAS_FEATURE(isp, ISP)
+OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+OMAP3_HAS_FEATURE(sdrc, SDRC)
+OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
+/*
+ * Runtime detection of OMAP4 features
+ */
+#define OMAP4_HAS_FEATURE(feat, flag)                   \
+static inline unsigned int omap4_has_ ##feat(void)      \
+{                                                       \
+        return omap_features & OMAP4_HAS_ ##flag;       \
+}                                                       \
+OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
+#endif  /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index f8217a5a4a26..b9753fe27232 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -23,8 +23,8 @@
 #include <linux/slab.h>
 #include <linux/io.h>
-#include <plat/omap_device.h>
+#include "soc.h"
+#include "omap_device.h"
 #include "voltage.h"
 #include "control.h"
 #include "pm.h"
@@ -121,6 +121,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
        sr_data->senn_mod = 0x1;
        sr_data->senp_mod = 0x1;
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                sr_data->err_weight = OMAP3430_SR_ERRWEIGHT;
+                sr_data->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+                sr_data->accum_data = OMAP3430_SR_ACCUMDATA;
+                if (!(strcmp(sr_data->name, "smartreflex_mpu"))) {
+                        sr_data->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+                        sr_data->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+                } else {
+                        sr_data->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+                        sr_data->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+                }
+        }
        sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
        if (!sr_data->voltdm) {
                pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
new file mode 100644
index 000000000000..0ff0f068bea8
--- /dev/null
+++ b/arch/arm/mach-omap2/sram.c
@@ -0,0 +1,305 @@
+/*
+ *
+ * OMAP SRAM detection and management
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/fncpy.h>
+#include <asm/tlb.h>
+#include <asm/cacheflush.h>
+#include <asm/mach/map.h>
+#include "soc.h"
+#include "iomap.h"
+#include "prm2xxx_3xxx.h"
+#include "sdrc.h"
+#include "sram.h"
+#define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
+#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
+#else
+#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
+#endif
+#define OMAP5_SRAM_PA           0x40300000
+#define SRAM_BOOTLOADER_SZ      0x00
+#define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
+#define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
+#define GP_DEVICE               0x300
+#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
+static unsigned long omap_sram_start;
+static unsigned long omap_sram_skip;
+static unsigned long omap_sram_size;
+/*
+ * Depending on the target RAMFS firewall setup, the public usable amount of
+ * SRAM varies.  The default accessible size for all device types is 2k. A GP
+ * device allows ARM11 but not other initiators for full size. This
+ * functionality seems ok until some nice security API happens.
+ */
+static int is_sram_locked(void)
+{
+        if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
+                /* RAMFW: R/W access to all initiators for all qualifier sets */
+                if (cpu_is_omap242x()) {
+                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
+                }
+                if (cpu_is_omap34xx()) {
+                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
+                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
+                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
+                }
+                return 0;
+        } else
+                return 1; /* assume locked with no PPA or security driver */
+}
+/*
+ * The amount of SRAM depends on the core type.
+ * Note that we cannot try to test for SRAM here because writes
+ * to secure SRAM will hang the system. Also the SRAM is not
+ * yet mapped at this point.
+ */
+static void __init omap_detect_sram(void)
+{
+        omap_sram_skip = SRAM_BOOTLOADER_SZ;
+        if (is_sram_locked()) {
+                if (cpu_is_omap34xx()) {
+                        omap_sram_start = OMAP3_SRAM_PUB_PA;
+                        if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
+                            (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
+                                omap_sram_size = 0x7000; /* 28K */
+                                omap_sram_skip += SZ_16K;
+                        } else {
+                                omap_sram_size = 0x8000; /* 32K */
+                        }
+                } else if (cpu_is_omap44xx()) {
+                        omap_sram_start = OMAP4_SRAM_PUB_PA;
+                        omap_sram_size = 0xa000; /* 40K */
+                } else if (soc_is_omap54xx()) {
+                        omap_sram_start = OMAP5_SRAM_PA;
+                        omap_sram_size = SZ_128K; /* 128KB */
+                } else {
+                        omap_sram_start = OMAP2_SRAM_PUB_PA;
+                        omap_sram_size = 0x800; /* 2K */
+                }
+        } else {
+                if (soc_is_am33xx()) {
+                        omap_sram_start = AM33XX_SRAM_PA;
+                        omap_sram_size = 0x10000; /* 64K */
+                } else if (cpu_is_omap34xx()) {
+                        omap_sram_start = OMAP3_SRAM_PA;
+                        omap_sram_size = 0x10000; /* 64K */
+                } else if (cpu_is_omap44xx()) {
+                        omap_sram_start = OMAP4_SRAM_PA;
+                        omap_sram_size = 0xe000; /* 56K */
+                } else if (soc_is_omap54xx()) {
+                        omap_sram_start = OMAP5_SRAM_PA;
+                        omap_sram_size = SZ_128K; /* 128KB */
+                } else {
+                        omap_sram_start = OMAP2_SRAM_PA;
+                        if (cpu_is_omap242x())
+                                omap_sram_size = 0xa0000; /* 640K */
+                        else if (cpu_is_omap243x())
+                                omap_sram_size = 0x10000; /* 64K */
+                }
+        }
+}
+/*
+ * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
+ */
+static void __init omap2_map_sram(void)
+{
+        int cached = 1;
+#ifdef CONFIG_OMAP4_ERRATA_I688
+        if (cpu_is_omap44xx()) {
+                omap_sram_start += PAGE_SIZE;
+                omap_sram_size -= SZ_16K;
+        }
+#endif
+        if (cpu_is_omap34xx()) {
+                /*
+                 * SRAM must be marked as non-cached on OMAP3 since the
+                 * CORE DPLL M2 divider change code (in SRAM) runs with the
+                 * SDRAM controller disabled, and if it is marked cached,
+                 * the ARM may attempt to write cache lines back to SDRAM
+                 * which will cause the system to hang.
+                 */
+                cached = 0;
+        }
+        omap_map_sram(omap_sram_start, omap_sram_size,
+                        omap_sram_skip, cached);
+}
+static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                              u32 base_cs, u32 force_unlock);
+void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                   u32 base_cs, u32 force_unlock)
+{
+        BUG_ON(!_omap2_sram_ddr_init);
+        _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
+                             base_cs, force_unlock);
+}
+static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
+                                          u32 mem_type);
+void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
+{
+        BUG_ON(!_omap2_sram_reprogram_sdrc);
+        _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
+}
+static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
+{
+        BUG_ON(!_omap2_set_prcm);
+        return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
+}
+#ifdef CONFIG_SOC_OMAP2420
+static int __init omap242x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
+                                        omap242x_sram_ddr_init_sz);
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
+                                            omap242x_sram_reprogram_sdrc_sz);
+        _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
+                                         omap242x_sram_set_prcm_sz);
+        return 0;
+}
+#else
+static inline int omap242x_sram_init(void)
+{
+        return 0;
+}
+#endif
+#ifdef CONFIG_SOC_OMAP2430
+static int __init omap243x_sram_init(void)
+{
+        _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
+                                        omap243x_sram_ddr_init_sz);
+        _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
+                                            omap243x_sram_reprogram_sdrc_sz);
+        _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
+                                         omap243x_sram_set_prcm_sz);
+        return 0;
+}
+#else
+static inline int omap243x_sram_init(void)
+{
+        return 0;
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+static u32 (*_omap3_sram_configure_core_dpll)(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
+{
+        BUG_ON(!_omap3_sram_configure_core_dpll);
+        return _omap3_sram_configure_core_dpll(
+                        m2, unlock_dll, f, inc,
+                        sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+                        sdrc_actim_ctrl_b_0, sdrc_mr_0,
+                        sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
+}
+void omap3_sram_restore_context(void)
+{
+        omap_sram_reset();
+        _omap3_sram_configure_core_dpll =
+                omap_sram_push(omap3_sram_configure_core_dpll,
+                               omap3_sram_configure_core_dpll_sz);
+        omap_push_sram_idle();
+}
+static inline int omap34xx_sram_init(void)
+{
+        omap3_sram_restore_context();
+        return 0;
+}
+#else
+static inline int omap34xx_sram_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_ARCH_OMAP3 */
+static inline int am33xx_sram_init(void)
+{
+        return 0;
+}
+int __init omap_sram_init(void)
+{
+        omap_detect_sram();
+        omap2_map_sram();
+        if (cpu_is_omap242x())
+                omap242x_sram_init();
+        else if (cpu_is_omap2430())
+                omap243x_sram_init();
+        else if (soc_is_am33xx())
+                am33xx_sram_init();
+        else if (cpu_is_omap34xx())
+                omap34xx_sram_init();
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
new file mode 100644
index 000000000000..ca7277c2a9ee
--- /dev/null
+++ b/arch/arm/mach-omap2/sram.h
@@ -0,0 +1,83 @@
+/*
+ * Interface for functions that need to be run in internal SRAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASSEMBLY__
+#include <plat/sram.h>
+extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                u32 base_cs, u32 force_unlock);
+extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                      u32 mem_type);
+extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+extern u32 omap3_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern void omap3_sram_restore_context(void);
+/* Do not use these */
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap242x_sram_ddr_init_sz;
+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap242x_sram_set_prcm_sz;
+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap243x_sram_ddr_init_sz;
+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap243x_sram_set_prcm_sz;
+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
+extern u32 omap3_sram_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+extern unsigned long omap3_sram_configure_core_dpll_sz;
+#ifdef CONFIG_PM
+extern void omap_push_sram_idle(void);
+#else
+static inline void omap_push_sram_idle(void) {}
+#endif /* CONFIG_PM */
+#endif /* __ASSEMBLY__ */
+/*
+ * OMAP2+: define the SRAM PA addresses.
+ * Used by the SRAM management code and the idle sleep code.
+ */
+#define OMAP2_SRAM_PA           0x40200000
+#define OMAP3_SRAM_PA           0x40200000
+#ifdef CONFIG_OMAP4_ERRATA_I688
+#define OMAP4_SRAM_PA           0x40304000
+#define OMAP4_SRAM_VA           0xfe404000
+#else
+#define OMAP4_SRAM_PA           0x40300000
+#endif
+#define AM33XX_SRAM_PA          0x40300000
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 8f7326cd435b..680a7c56cc3e 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -34,8 +34,8 @@
 #include "soc.h"
 #include "iomap.h"
-#include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "sdrc.h"
        .text
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index b140d6578529..a1e9edd673f4 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -34,8 +34,8 @@
 #include "soc.h"
 #include "iomap.h"
-#include "prm2xxx_3xxx.h"
+#include "prm2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "sdrc.h"
        .text
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 2d0ceaa23fb8..1446331b576a 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -32,7 +32,7 @@
 #include "soc.h"
 #include "iomap.h"
 #include "sdrc.h"
-#include "cm2xxx_3xxx.h"
+#include "cm3xxx.h"
 /*
 * This file needs be built unconditionally as ARM to interoperate correctly
diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
index 8f9843f78422..a1e6caf0dba6 100644
--- a/arch/arm/mach-omap2/ti81xx.h
+++ b/arch/arm/mach-omap2/ti81xx.h
@@ -22,6 +22,15 @@
 #define TI81XX_CTRL_BASE        TI81XX_SCM_BASE
 #define TI81XX_PRCM_BASE        0x48180000
+/*
+ * Adjust TAP register base such that omap3_check_revision accesses the correct
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
+ */
+#define TI81XX_TAP_BASE         (TI81XX_CTRL_BASE + \
+                                 TI81XX_CONTROL_DEVICE_ID - 0x204)
 #define TI81XX_ARM_INTC_BASE    0x48200000
 #endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 69e46631a7cd..7016637b531c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -37,16 +37,21 @@
 #include <linux/clockchips.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/dmtimer-omap.h>
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 #include <asm/arch_timer.h>
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
-#include <plat/omap_device.h>
+#include "omap_device.h"
+#include <plat/counter-32k.h>
 #include <plat/dmtimer.h>
-#include <plat/omap-pm.h>
+#include "omap-pm.h"
 #include "soc.h"
 #include "common.h"
@@ -61,18 +66,6 @@
 #define OMAP3_32K_SOURCE        "omap_32k_fck"
 #define OMAP4_32K_SOURCE        "sys_32k_ck"
-#ifdef CONFIG_OMAP_32K_TIMER
-#define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
-#define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
-#define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
-#define OMAP3_SECURE_TIMER      12
-#else
-#define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
-#define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
-#define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
-#define OMAP3_SECURE_TIMER      1
-#endif
 #define REALTIME_COUNTER_BASE                           0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
@@ -103,7 +96,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)
 {
        __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
-                                                0xffffffff - cycles, 1);
+                                   0xffffffff - cycles, OMAP_TIMER_POSTED);
        return 0;
 }
@@ -113,7 +106,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 {
        u32 period;
-        __omap_dm_timer_stop(&clkev, 1, clkev.rate);
+        __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
@@ -121,10 +114,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
                period -= 1;
                /* Looks like we need to first set the load value separately */
                __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
-                                        0xffffffff - period, 1);
+                                      0xffffffff - period, OMAP_TIMER_POSTED);
                __omap_dm_timer_load_start(&clkev,
                                        OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
-                                                0xffffffff - period, 1);
+                                        0xffffffff - period, OMAP_TIMER_POSTED);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                break;
@@ -144,36 +137,144 @@ static struct clock_event_device clockevent_gpt = {
        .set_mode       = omap2_gp_timer_set_mode,
 };
+static struct property device_disabled = {
+        .name = "status",
+        .length = sizeof("disabled"),
+        .value = "disabled",
+};
+static struct of_device_id omap_timer_match[] __initdata = {
+        { .compatible = "ti,omap2-timer", },
+        { }
+};
+/**
+ * omap_get_timer_dt - get a timer using device-tree
+ * @match       - device-tree match structure for matching a device type
+ * @property    - optional timer property to match
+ *
+ * Helper function to get a timer during early boot using device-tree for use
+ * as kernel system timer. Optionally, the property argument can be used to
+ * select a timer with a specific property. Once a timer is found then mark
+ * the timer node in device-tree as disabled, to prevent the kernel from
+ * registering this timer as a platform device and so no one else can use it.
+ */
+static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
+                                                     const char *property)
+{
+        struct device_node *np;
+        for_each_matching_node(np, match) {
+                if (!of_device_is_available(np)) {
+                        of_node_put(np);
+                        continue;
+                }
+                if (property && !of_get_property(np, property, NULL)) {
+                        of_node_put(np);
+                        continue;
+                }
+                prom_add_property(np, &device_disabled);
+                return np;
+        }
+        return NULL;
+}
+/**
+ * omap_dmtimer_init - initialisation function when device tree is used
+ *
+ * For secure OMAP3 devices, timers with device type "timer-secure" cannot
+ * be used by the kernel as they are reserved. Therefore, to prevent the
+ * kernel registering these devices remove them dynamically from the device
+ * tree on boot.
+ */
+void __init omap_dmtimer_init(void)
+{
+        struct device_node *np;
+        if (!cpu_is_omap34xx())
+                return;
+        /* If we are a secure device, remove any secure timer nodes */
+        if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+                np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
+                if (np)
+                        of_node_put(np);
+        }
+}
+/**
+ * omap_dm_timer_get_errata - get errata flags for a timer
+ *
+ * Get the timer errata flags that are specific to the OMAP device being used.
+ */
+u32 __init omap_dm_timer_get_errata(void)
+{
+        if (cpu_is_omap24xx())
+                return 0;
+        return OMAP_TIMER_ERRATA_I103_I767;
+}
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
                                                int gptimer_id,
-                                                const char *fck_source)
+                                                const char *fck_source,
+                                                const char *property,
+                                                int posted)
 {
        char name[10]; /* 10 = sizeof("gptXX_Xck0") */
+        const char *oh_name;
+        struct device_node *np;
        struct omap_hwmod *oh;
-        struct resource irq_rsrc, mem_rsrc;
+        struct resource irq, mem;
-        size_t size;
+        int r = 0;
-        int res = 0;
-        int r;
+        if (of_have_populated_dt()) {
+                np = omap_get_timer_dt(omap_timer_match, NULL);
-        sprintf(name, "timer%d", gptimer_id);
+                if (!np)
-        omap_hwmod_setup_one(name);
+                        return -ENODEV;
-        oh = omap_hwmod_lookup(name);
+                of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
+                if (!oh_name)
+                        return -ENODEV;
+                timer->irq = irq_of_parse_and_map(np, 0);
+                if (!timer->irq)
+                        return -ENXIO;
+                timer->io_base = of_iomap(np, 0);
+                of_node_put(np);
+        } else {
+                if (omap_dm_timer_reserve_systimer(gptimer_id))
+                        return -ENODEV;
+                sprintf(name, "timer%d", gptimer_id);
+                oh_name = name;
+        }
+        oh = omap_hwmod_lookup(oh_name);
        if (!oh)
                return -ENODEV;
-        r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
+        if (!of_have_populated_dt()) {
-        if (r)
+                r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
-                return -ENXIO;
+                                                   &irq);
-        timer->irq = irq_rsrc.start;
+                if (r)
+                        return -ENXIO;
+                timer->irq = irq.start;
-        r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
+                r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
-        if (r)
+                                                   &mem);
-                return -ENXIO;
+                if (r)
-        timer->phys_base = mem_rsrc.start;
+                        return -ENXIO;
-        size = mem_rsrc.end - mem_rsrc.start;
+                /* Static mapping, never released */
+                timer->io_base = ioremap(mem.start, mem.end - mem.start);
+        }
-        /* Static mapping, never released */
-        timer->io_base = ioremap(timer->phys_base, size);
        if (!timer->io_base)
                return -ENXIO;
@@ -182,42 +283,56 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
        if (IS_ERR(timer->fclk))
                return -ENODEV;
-        omap_hwmod_enable(oh);
+        /* FIXME: Need to remove hard-coded test on timer ID */
-        if (omap_dm_timer_reserve_systimer(gptimer_id))
-                return -ENODEV;
        if (gptimer_id != 12) {
                struct clk *src;
                src = clk_get(NULL, fck_source);
                if (IS_ERR(src)) {
-                        res = -EINVAL;
+                        r = -EINVAL;
                } else {
-                        res = __omap_dm_timer_set_source(timer->fclk, src);
+                        r = clk_set_parent(timer->fclk, src);
-                        if (IS_ERR_VALUE(res))
+                        if (IS_ERR_VALUE(r))
-                                pr_warning("%s: timer%i cannot set source\n",
+                                pr_warn("%s: %s cannot set source\n",
-                                                __func__, gptimer_id);
+                                        __func__, oh->name);
                        clk_put(src);
                }
        }
+        omap_hwmod_setup_one(oh_name);
+        omap_hwmod_enable(oh);
        __omap_dm_timer_init_regs(timer);
-        __omap_dm_timer_reset(timer, 1, 1);
-        timer->posted = 1;
-        timer->rate = clk_get_rate(timer->fclk);
+        if (posted)
+                __omap_dm_timer_enable_posted(timer);
+        /* Check that the intended posted configuration matches the actual */
+        if (posted != timer->posted)
+                return -EINVAL;
+        timer->rate = clk_get_rate(timer->fclk);
        timer->reserved = 1;
-        return res;
+        return r;
 }
 static void __init omap2_gp_clockevent_init(int gptimer_id,
-                                                const char *fck_source)
+                                                const char *fck_source,
+                                                const char *property)
 {
        int res;
-        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+        clkev.errata = omap_dm_timer_get_errata();
+        /*
+         * For clock-event timers we never read the timer counter and
+         * so we are not impacted by errata i103 and i767. Therefore,
+         * we can safely ignore this errata for clock-event timers.
+         */
+        __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
+        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
+                                     OMAP_TIMER_POSTED);
        BUG_ON(res);
        omap2_gp_timer_irq.dev_id = &clkev;
@@ -250,7 +365,8 @@ static bool use_gptimer_clksrc;
 */
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
-        return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
+        return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
+                                                     OMAP_TIMER_NONPOSTED);
 }
 static struct clocksource clocksource_gpt = {
@@ -264,21 +380,41 @@ static struct clocksource clocksource_gpt = {
 static u32 notrace dmtimer_read_sched_clock(void)
 {
        if (clksrc.reserved)
-                return __omap_dm_timer_read_counter(&clksrc, 1);
+                return __omap_dm_timer_read_counter(&clksrc,
+                                                    OMAP_TIMER_NONPOSTED);
        return 0;
 }
-#ifdef CONFIG_OMAP_32K_TIMER
+static struct of_device_id omap_counter_match[] __initdata = {
+        { .compatible = "ti,omap-counter32k", },
+        { }
+};
 /* Setup free-running counter for clocksource */
 static int __init omap2_sync32k_clocksource_init(void)
 {
        int ret;
+        struct device_node *np = NULL;
        struct omap_hwmod *oh;
        void __iomem *vbase;
        const char *oh_name = "counter_32k";
        /*
+         * If device-tree is present, then search the DT blob
+         * to see if the 32kHz counter is supported.
+         */
+        if (of_have_populated_dt()) {
+                np = omap_get_timer_dt(omap_counter_match, NULL);
+                if (!np)
+                        return -ENODEV;
+                of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
+                if (!oh_name)
+                        return -ENODEV;
+        }
+        /*
         * First check hwmod data is available for sync32k counter
         */
        oh = omap_hwmod_lookup(oh_name);
@@ -287,7 +423,13 @@ static int __init omap2_sync32k_clocksource_init(void)
        omap_hwmod_setup_one(oh_name);
-        vbase = omap_hwmod_get_mpu_rt_va(oh);
+        if (np) {
+                vbase = of_iomap(np, 0);
+                of_node_put(np);
+        } else {
+                vbase = omap_hwmod_get_mpu_rt_va(oh);
+        }
        if (!vbase) {
                pr_warn("%s: failed to get counter_32k resource\n", __func__);
                return -ENXIO;
@@ -309,23 +451,21 @@ static int __init omap2_sync32k_clocksource_init(void)
        return ret;
 }
-#else
-static inline int omap2_sync32k_clocksource_init(void)
-{
-        return -ENODEV;
-}
-#endif
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                                                const char *fck_source)
 {
        int res;
-        res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
+        clksrc.errata = omap_dm_timer_get_errata();
+        res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
+                                     OMAP_TIMER_NONPOSTED);
        BUG_ON(res);
        __omap_dm_timer_load_start(&clksrc,
-                        OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
+                                   OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
+                                   OMAP_TIMER_NONPOSTED);
        setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
        if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
@@ -336,25 +476,6 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                        gptimer_id, clksrc.rate);
 }
-static void __init omap2_clocksource_init(int gptimer_id,
-                                                const char *fck_source)
-{
-        /*
-         * First give preference to kernel parameter configuration
-         * by user (clocksource="gp_timer").
-         *
-         * In case of missing kernel parameter for clocksource,
-         * first check for availability for 32k-sync timer, in case
-         * of failure in finding 32k_counter module or registering
-         * it as clocksource, execution will fallback to gp-timer.
-         */
-        if (use_gptimer_clksrc == true)
-                omap2_gptimer_clocksource_init(gptimer_id, fck_source);
-        else if (omap2_sync32k_clocksource_init())
-                /* Fall back to gp-timer code */
-                omap2_gptimer_clocksource_init(gptimer_id, fck_source);
-}
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 /*
 * The realtime counter also called master counter, is a free-running
@@ -433,48 +554,65 @@ static inline void __init realtime_counter_init(void)
 {}
 #endif
-#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
+#define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
+                               clksrc_nr, clksrc_src)                   \
+static void __init omap##name##_gptimer_timer_init(void)                \
+{                                                                       \
+        omap_dmtimer_init();                                            \
+        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
+        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
+}
+#define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
                                clksrc_nr, clksrc_src)                  \
-static void __init omap##name##_timer_init(void)                        \
+static void __init omap##name##_sync32k_timer_init(void)                \
 {                                                                       \
-        omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
+        omap_dmtimer_init();                                            \
-        omap2_clocksource_init((clksrc_nr), clksrc_src);                \
+        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
+        /* Enable the use of clocksource="gp_timer" kernel parameter */ \
+        if (use_gptimer_clksrc)                                         \
+                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
+        else                                                            \
+                omap2_sync32k_clocksource_init();                       \
 }
-#define OMAP_SYS_TIMER(name)                                            \
+#define OMAP_SYS_TIMER(name, clksrc)                                    \
 struct sys_timer omap##name##_timer = {                                 \
-        .init   = omap##name##_timer_init,                              \
+        .init   = omap##name##_##clksrc##_timer_init,                   \
 };
 #ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
-OMAP_SYS_TIMER(2)
+                        2, OMAP2_MPU_SOURCE);
-#endif
+OMAP_SYS_TIMER(2, sync32k);
+#endif /* CONFIG_ARCH_OMAP2 */
 #ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
-OMAP_SYS_TIMER(3)
+                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
+OMAP_SYS_TIMER(3, sync32k);
-                        2, OMAP3_MPU_SOURCE)
+OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
-OMAP_SYS_TIMER(3_secure)
+                        2, OMAP3_MPU_SOURCE);
-#endif
+OMAP_SYS_TIMER(3_secure, sync32k);
+OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
+                       2, OMAP3_MPU_SOURCE);
+OMAP_SYS_TIMER(3_gp, gptimer);
+#endif /* CONFIG_ARCH_OMAP3 */
 #ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
-OMAP_SYS_TIMER(3_am33xx)
+                       2, OMAP4_MPU_SOURCE);
-#endif
+OMAP_SYS_TIMER(3_am33xx, gptimer);
+#endif /* CONFIG_SOC_AM33XX */
 #ifdef CONFIG_ARCH_OMAP4
+OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
+                        2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
-                              OMAP44XX_LOCAL_TWD_BASE, 29);
+static void __init omap4_local_timer_init(void)
-#endif
-static void __init omap4_timer_init(void)
 {
-        omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+        omap4_sync32k_timer_init();
-        omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
-#ifdef CONFIG_LOCAL_TIMERS
        /* Local timers are not supprted on OMAP4430 ES1.0 */
        if (omap_rev() != OMAP4430_REV_ES1_0) {
                int err;
@@ -488,26 +626,32 @@ static void __init omap4_timer_init(void)
                if (err)
                        pr_err("twd_local_timer_register failed %d\n", err);
        }
-#endif
 }
-OMAP_SYS_TIMER(4)
+#else /* CONFIG_LOCAL_TIMERS */
-#endif
+static void __init omap4_local_timer_init(void)
+{
+        omap4_sync32k_timer_init();
+}
+#endif /* CONFIG_LOCAL_TIMERS */
+OMAP_SYS_TIMER(4, local);
+#endif /* CONFIG_ARCH_OMAP4 */
 #ifdef CONFIG_SOC_OMAP5
-static void __init omap5_timer_init(void)
+OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
+                        2, OMAP4_MPU_SOURCE);
+static void __init omap5_realtime_timer_init(void)
 {
        int err;
-        omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+        omap5_sync32k_timer_init();
-        omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
        realtime_counter_init();
        err = arch_timer_of_register();
        if (err)
                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 }
-OMAP_SYS_TIMER(5)
+OMAP_SYS_TIMER(5, realtime);
-#endif
+#endif /* CONFIG_SOC_OMAP5 */
 /**
 * omap_timer_init - build and register timer device with an
@@ -559,6 +703,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
        if (timer_dev_attr)
                pdata->timer_capability = timer_dev_attr->timer_capability;
+        pdata->timer_errata = omap_dm_timer_get_errata();
+        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
        pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
                                 NULL, 0, 0);
@@ -583,6 +730,10 @@ static int __init omap2_dm_timer_init(void)
 {
        int ret;
+        /* If dtb is there, the devices will be created dynamically */
+        if (of_have_populated_dt())
+                return -ENODEV;
        ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
        if (unlikely(ret)) {
                pr_err("%s: device registration failed.\n", __func__);
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index a256135d8e48..e49b40b4c90a 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -26,9 +26,6 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
-#include <plat/i2c.h>
-#include <plat/usb.h>
 #include "soc.h"
 #include "twl-common.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 3c434498e12e..d1dbe125b34f 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -25,10 +25,10 @@
 #include <asm/io.h>
-#include <plat/usb.h>
+#include "soc.h"
-#include <plat/omap_device.h>
+#include "omap_device.h"
 #include "mux.h"
+#include "usb.h"
 #ifdef CONFIG_MFD_OMAP_USB_HOST
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 51da21cb78f1..7b33b375fe77 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -25,12 +25,10 @@
 #include <linux/io.h>
 #include <linux/usb/musb.h>
-#include <plat/usb.h>
+#include "omap_device.h"
-#include <plat/omap_device.h>
+#include "soc.h"
-#include "am35xx.h"
 #include "mux.h"
+#include "usb.h"
 static struct musb_hdrc_config musb_config = {
        .multipoint     = 1,
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 805bea6edf17..c5a3c6f9504e 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -15,10 +15,11 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/export.h>
+#include <linux/platform_data/usb-omap.h>
 #include <linux/usb/musb.h>
-#include <plat/gpmc.h>
+#include "gpmc.h"
 #include "mux.h"
@@ -26,180 +27,88 @@ static u8		async_cs, sync_cs;
 static unsigned         refclk_psec;
-/* t2_ps, when quantized to fclk units, must happen no earlier than
- * the clock after after t1_NS.
- *
- * Return a possibly updated value of t2_ps, converted to nsec.
- */
-static unsigned
-next_clk(unsigned t1_NS, unsigned t2_ps, unsigned fclk_ps)
-{
-        unsigned        t1_ps = t1_NS * 1000;
-        unsigned        t1_f, t2_f;
-        if ((t1_ps + fclk_ps) < t2_ps)
-                return t2_ps / 1000;
-        t1_f = (t1_ps + fclk_ps - 1) / fclk_ps;
-        t2_f = (t2_ps + fclk_ps - 1) / fclk_ps;
-        if (t1_f >= t2_f)
-                t2_f = t1_f + 1;
-        return (t2_f * fclk_ps) / 1000;
-}
 /* NOTE:  timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
-static int tusb_set_async_mode(unsigned sysclk_ps, unsigned fclk_ps)
+static int tusb_set_async_mode(unsigned sysclk_ps)
 {
+        struct gpmc_device_timings dev_t;
        struct gpmc_timings     t;
        unsigned                t_acsnh_advnh = sysclk_ps + 3000;
-        unsigned                tmp;
-        memset(&t, 0, sizeof(t));
-        /* CS_ON = t_acsnh_acsnl */
-        t.cs_on = 8;
-        /* ADV_ON = t_acsnh_advnh - t_advn */
-        t.adv_on = next_clk(t.cs_on, t_acsnh_advnh - 7000, fclk_ps);
-        /*
-         * READ ... from omap2420 TRM fig 12-13
-         */
-        /* ADV_RD_OFF = t_acsnh_advnh */
-        t.adv_rd_off = next_clk(t.adv_on, t_acsnh_advnh, fclk_ps);
-        /* OE_ON = t_acsnh_advnh + t_advn_oen (then wait for nRDY) */
-        t.oe_on = next_clk(t.adv_on, t_acsnh_advnh + 1000, fclk_ps);
-        /* ACCESS = counters continue only after nRDY */
-        tmp = t.oe_on * 1000 + 300;
-        t.access = next_clk(t.oe_on, tmp, fclk_ps);
-        /* OE_OFF = after data gets sampled */
-        tmp = t.access * 1000;
-        t.oe_off = next_clk(t.access, tmp, fclk_ps);
-        t.cs_rd_off = t.oe_off;
-        tmp = t.cs_rd_off * 1000 + 7000 /* t_acsn_rdy_z */;
-        t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps);
-        /*
-         * WRITE ... from omap2420 TRM fig 12-15
-         */
-        /* ADV_WR_OFF = t_acsnh_advnh */
-        t.adv_wr_off = t.adv_rd_off;
-        /* WE_ON = t_acsnh_advnh + t_advn_wen (then wait for nRDY) */
+        memset(&dev_t, 0, sizeof(dev_t));
-        t.we_on = next_clk(t.adv_wr_off, t_acsnh_advnh + 1000, fclk_ps);
-        /* WE_OFF = after data gets sampled */
+        dev_t.mux = true;
-        tmp = t.we_on * 1000 + 300;
-        t.we_off = next_clk(t.we_on, tmp, fclk_ps);
-        t.cs_wr_off = t.we_off;
+        dev_t.t_ceasu = 8 * 1000;
+        dev_t.t_avdasu = t_acsnh_advnh - 7000;
+        dev_t.t_ce_avd = 1000;
+        dev_t.t_avdp_r = t_acsnh_advnh;
+        dev_t.t_oeasu = t_acsnh_advnh + 1000;
+        dev_t.t_oe = 300;
+        dev_t.t_cez_r = 7000;
+        dev_t.t_cez_w = dev_t.t_cez_r;
+        dev_t.t_avdp_w = t_acsnh_advnh;
+        dev_t.t_weasu = t_acsnh_advnh + 1000;
+        dev_t.t_wpl = 300;
+        dev_t.cyc_aavdh_we = 1;
-        tmp = t.cs_wr_off * 1000 + 7000 /* t_acsn_rdy_z */;
+        gpmc_calc_timings(&t, &dev_t);
-        t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps);
        return gpmc_cs_set_timings(async_cs, &t);
 }
-static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
+static int tusb_set_sync_mode(unsigned sysclk_ps)
 {
+        struct gpmc_device_timings dev_t;
        struct gpmc_timings     t;
        unsigned                t_scsnh_advnh = sysclk_ps + 3000;
-        unsigned                tmp;
-        memset(&t, 0, sizeof(t));
-        t.cs_on = 8;
-        /* ADV_ON = t_acsnh_advnh - t_advn */
-        t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps);
-        /* GPMC_CLK rate = fclk rate / div */
-        t.sync_clk = 11100 /* 11.1 nsec */;
-        tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
-        if (tmp > 4)
-                return -ERANGE;
-        if (tmp == 0)
-                tmp = 1;
-        t.page_burst_access = (fclk_ps * tmp) / 1000;
-        /*
-         * READ ... based on omap2420 TRM fig 12-19, 12-20
-         */
-        /* ADV_RD_OFF = t_scsnh_advnh */
-        t.adv_rd_off = next_clk(t.adv_on, t_scsnh_advnh, fclk_ps);
-        /* OE_ON = t_scsnh_advnh + t_advn_oen * fclk_ps (then wait for nRDY) */
-        tmp = (t.adv_rd_off * 1000) + (3 * fclk_ps);
-        t.oe_on = next_clk(t.adv_on, tmp, fclk_ps);
-        /* ACCESS = number of clock cycles after t_adv_eon */
-        tmp = (t.oe_on * 1000) + (5 * fclk_ps);
-        t.access = next_clk(t.oe_on, tmp, fclk_ps);
-        /* OE_OFF = after data gets sampled */
+        memset(&dev_t, 0, sizeof(dev_t));
-        tmp = (t.access * 1000) + (1 * fclk_ps);
-        t.oe_off = next_clk(t.access, tmp, fclk_ps);
+        dev_t.mux = true;
+        dev_t.sync_read = true;
-        t.cs_rd_off = t.oe_off;
+        dev_t.sync_write = true;
-        tmp = t.cs_rd_off * 1000 + 7000 /* t_scsn_rdy_z */;
+        dev_t.clk = 11100;
-        t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps);
+        dev_t.t_bacc = 1000;
+        dev_t.t_ces = 1000;
-        /*
+        dev_t.t_ceasu = 8 * 1000;
-         * WRITE ... based on omap2420 TRM fig 12-21
+        dev_t.t_avdasu = t_scsnh_advnh - 7000;
-         */
+        dev_t.t_ce_avd = 1000;
+        dev_t.t_avdp_r = t_scsnh_advnh;
-        /* ADV_WR_OFF = t_scsnh_advnh */
+        dev_t.cyc_aavdh_oe = 3;
-        t.adv_wr_off = t.adv_rd_off;
+        dev_t.cyc_oe = 5;
+        dev_t.t_ce_rdyz = 7000;
-        /* WE_ON = t_scsnh_advnh + t_advn_wen * fclk_ps (then wait for nRDY) */
+        dev_t.t_avdp_w = t_scsnh_advnh;
-        tmp = (t.adv_wr_off * 1000) + (3 * fclk_ps);
+        dev_t.cyc_aavdh_we = 3;
-        t.we_on = next_clk(t.adv_wr_off, tmp, fclk_ps);
+        dev_t.cyc_wpl = 6;
+        dev_t.t_ce_rdyz = 7000;
-        /* WE_OFF = number of clock cycles after t_adv_wen */
-        tmp = (t.we_on * 1000) + (6 * fclk_ps);
+        gpmc_calc_timings(&t, &dev_t);
-        t.we_off = next_clk(t.we_on, tmp, fclk_ps);
-        t.cs_wr_off = t.we_off;
-        tmp = t.cs_wr_off * 1000 + 7000 /* t_scsn_rdy_z */;
-        t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps);
        return gpmc_cs_set_timings(sync_cs, &t);
 }
-extern unsigned long gpmc_get_fclk_period(void);
 /* tusb driver calls this when it changes the chip's clocking */
 int tusb6010_platform_retime(unsigned is_refclk)
 {
        static const char       error[] =
                KERN_ERR "tusb6010 %s retime error %d\n";
-        unsigned        fclk_ps = gpmc_get_fclk_period();
        unsigned        sysclk_ps;
        int             status;
-        if (!refclk_psec || fclk_ps == 0)
+        if (!refclk_psec)
                return -ENODEV;
        sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
-        status = tusb_set_async_mode(sysclk_ps, fclk_ps);
+        status = tusb_set_async_mode(sysclk_ps);
        if (status < 0) {
                printk(error, "async", status);
                goto done;
        }
-        status = tusb_set_sync_mode(sysclk_ps, fclk_ps);
+        status = tusb_set_sync_mode(sysclk_ps);
        if (status < 0)
                printk(error, "sync", status);
 done:
@@ -283,7 +192,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                        | GPMC_CONFIG1_READTYPE_SYNC
                        | GPMC_CONFIG1_WRITEMULTIPLE_SUPP
                        | GPMC_CONFIG1_WRITETYPE_SYNC
-                        | GPMC_CONFIG1_CLKACTIVATIONTIME(1)
                        | GPMC_CONFIG1_PAGE_LEN(2)
                        | GPMC_CONFIG1_WAIT_READ_MON
                        | GPMC_CONFIG1_WAIT_WRITE_MON
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
new file mode 100644
index 000000000000..9b986ead7c45
--- /dev/null
+++ b/arch/arm/mach-omap2/usb.h
@@ -0,0 +1,82 @@
+#include <linux/platform_data/usb-omap.h>
+/* AM35x */
+/* USB 2.0 PHY Control */
+#define CONF2_PHY_GPIOMODE      (1 << 23)
+#define CONF2_OTGMODE           (3 << 14)
+#define CONF2_NO_OVERRIDE       (0 << 14)
+#define CONF2_FORCE_HOST        (1 << 14)
+#define CONF2_FORCE_DEVICE      (2 << 14)
+#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+#define CONF2_SESENDEN          (1 << 13)
+#define CONF2_VBDTCTEN          (1 << 12)
+#define CONF2_REFFREQ_24MHZ     (2 << 8)
+#define CONF2_REFFREQ_26MHZ     (7 << 8)
+#define CONF2_REFFREQ_13MHZ     (6 << 8)
+#define CONF2_REFFREQ           (0xf << 8)
+#define CONF2_PHYCLKGD          (1 << 7)
+#define CONF2_VBUSSENSE         (1 << 6)
+#define CONF2_PHY_PLLON         (1 << 5)
+#define CONF2_RESET             (1 << 4)
+#define CONF2_PHYPWRDN          (1 << 3)
+#define CONF2_OTGPWRDN          (1 << 2)
+#define CONF2_DATPOL            (1 << 1)
+/* TI81XX specific definitions */
+#define USBCTRL0        0x620
+#define USBSTAT0        0x624
+/* TI816X PHY controls bits */
+#define TI816X_USBPHY0_NORMAL_MODE      (1 << 0)
+#define TI816X_USBPHY_REFCLK_OSC        (1 << 8)
+/* TI814X PHY controls bits */
+#define USBPHY_CM_PWRDN         (1 << 0)
+#define USBPHY_OTG_PWRDN        (1 << 1)
+#define USBPHY_CHGDET_DIS       (1 << 2)
+#define USBPHY_CHGDET_RSTRT     (1 << 3)
+#define USBPHY_SRCONDM          (1 << 4)
+#define USBPHY_SINKONDP         (1 << 5)
+#define USBPHY_CHGISINK_EN      (1 << 6)
+#define USBPHY_CHGVSRC_EN       (1 << 7)
+#define USBPHY_DMPULLUP         (1 << 8)
+#define USBPHY_DPPULLUP         (1 << 9)
+#define USBPHY_CDET_EXTCTL      (1 << 10)
+#define USBPHY_GPIO_MODE        (1 << 12)
+#define USBPHY_DPOPBUFCTL       (1 << 13)
+#define USBPHY_DMOPBUFCTL       (1 << 14)
+#define USBPHY_DPINPUT          (1 << 15)
+#define USBPHY_DMINPUT          (1 << 16)
+#define USBPHY_DPGPIO_PD        (1 << 17)
+#define USBPHY_DMGPIO_PD        (1 << 18)
+#define USBPHY_OTGVDET_EN       (1 << 19)
+#define USBPHY_OTGSESSEND_EN    (1 << 20)
+#define USBPHY_DATA_POLARITY    (1 << 23)
+struct usbhs_omap_board_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+        /* have to be valid if phy_reset is true and portx is in phy mode */
+        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+        /* Set this to true for ES2.x silicon */
+        unsigned                        es2_compatibility:1;
+        unsigned                        phy_reset:1;
+        /*
+         * Regulators for USB PHYs.
+         * Each PHY can have a separate regulator.
+         */
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
+};
+extern void usb_musb_init(struct omap_musb_board_data *board_data);
+extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
+extern void am35x_musb_reset(void);
+extern void am35x_musb_phy_power(u8 on);
+extern void am35x_musb_clear_irq(void);
+extern void am35x_set_mode(u8 musb_mode);
+extern void ti81xx_musb_phy_power(u8 on);
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 75878c37959b..49ac7977e03e 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -11,13 +11,20 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/bug.h>
+#include <linux/io.h>
+#include <asm/div64.h>
+#include "iomap.h"
 #include "soc.h"
 #include "voltage.h"
 #include "vc.h"
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
+#include "pm.h"
+#include "scrm44xx.h"
+#include "control.h"
 /**
 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
@@ -63,6 +70,9 @@ static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
 };
 static struct omap_vc_channel_cfg *vc_cfg_bits;
+/* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
+static u32 sr_i2c_pcb_length = 63;
 #define CFG_CHANNEL_MASK 0x1f
 /**
@@ -135,6 +145,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
        vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
        voltdm->write(vc_cmdval, vc->cmdval_reg);
+        voltdm->vc_param->on = target_volt;
        omap_vp_update_errorgain(voltdm, target_volt);
        return 0;
@@ -202,46 +214,389 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
        return 0;
 }
-static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
+/* Convert microsecond value to number of 32kHz clock cycles */
+static inline u32 omap_usec_to_32k(u32 usec)
+{
+        return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
+}
+/* Set oscillator setup time for omap3 */
+static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm)
+{
+        voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET);
+}
+/**
+ * omap3_set_i2c_timings - sets i2c sleep timings for a channel
+ * @voltdm: channel to configure
+ * @off_mode: select whether retention or off mode values used
+ *
+ * Calculates and sets up voltage controller to use I2C based
+ * voltage scaling for sleep modes. This can be used for either off mode
+ * or retention. Off mode has additionally an option to use sys_off_mode
+ * pad, which uses a global signal to program the whole power IC to
+ * off-mode.
+ */
+static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode)
 {
+        unsigned long voltsetup1;
+        u32 tgt_volt;
+        /*
+         * Oscillator is shut down only if we are using sys_off_mode pad,
+         * thus we set a minimal setup time here
+         */
+        omap3_set_clksetup(1, voltdm);
+        if (off_mode)
+                tgt_volt = voltdm->vc_param->off;
+        else
+                tgt_volt = voltdm->vc_param->ret;
+        voltsetup1 = (voltdm->vc_param->on - tgt_volt) /
+                        voltdm->pmic->slew_rate;
+        voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1;
+        voltdm->rmw(voltdm->vfsm->voltsetup_mask,
+                voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask),
+                voltdm->vfsm->voltsetup_reg);
        /*
-         * Voltage Manager FSM parameters init
+         * pmic is not controlling the voltage scaling during retention,
-         * XXX This data should be passed in from the board file
+         * thus set voltsetup2 to 0
         */
-        voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
+        voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET);
-        voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
-        voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
 }
-static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+/**
+ * omap3_set_off_timings - sets off-mode timings for a channel
+ * @voltdm: channel to configure
+ *
+ * Calculates and sets up off-mode timings for a channel. Off-mode
+ * can use either I2C based voltage scaling, or alternatively
+ * sys_off_mode pad can be used to send a global command to power IC.
+ * This function first checks which mode is being used, and calls
+ * omap3_set_i2c_timings() if the system is using I2C control mode.
+ * sys_off_mode has the additional benefit that voltages can be
+ * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
+ * scale to 600mV.
+ */
+static void omap3_set_off_timings(struct voltagedomain *voltdm)
 {
-        static bool is_initialized;
+        unsigned long clksetup;
+        unsigned long voltsetup2;
+        unsigned long voltsetup2_old;
+        u32 val;
+        u32 tstart, tshut;
-        if (is_initialized)
+        /* check if sys_off_mode is used to control off-mode voltages */
+        val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
+        if (!(val & OMAP3430_SEL_OFF_MASK)) {
+                /* No, omap is controlling them over I2C */
+                omap3_set_i2c_timings(voltdm, true);
                return;
+        }
+        omap_pm_get_oscillator(&tstart, &tshut);
+        omap3_set_clksetup(tstart, voltdm);
+        clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET);
+        /* voltsetup 2 in us */
+        voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate;
+        /* convert to 32k clk cycles */
+        voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000);
+        voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET);
+        /*
+         * Update voltsetup2 if higher than current value (needed because
+         * we have multiple channels with different ramp times), also
+         * update voltoffset always to value recommended by TRM
+         */
+        if (voltsetup2 > voltsetup2_old) {
+                voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET);
+                voltdm->write(clksetup - voltsetup2,
+                        OMAP3_PRM_VOLTOFFSET_OFFSET);
+        } else
+                voltdm->write(clksetup - voltsetup2_old,
+                        OMAP3_PRM_VOLTOFFSET_OFFSET);
+        /*
+         * omap is not controlling voltage scaling during off-mode,
+         * thus set voltsetup1 to 0
+         */
+        voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0,
+                voltdm->vfsm->voltsetup_reg);
+        /* voltoffset must be clksetup minus voltsetup2 according to TRM */
+        voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET);
+}
+static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
+{
+        omap3_set_off_timings(voltdm);
+}
+/**
+ * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
+ * @voltdm: channel to calculate values for
+ * @voltage_diff: voltage difference in microvolts
+ *
+ * Calculates voltage ramp prescaler + counter values for a voltage
+ * difference on omap4. Returns a field value suitable for writing to
+ * VOLTSETUP register for a channel in following format:
+ * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
+ */
+static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
+{
+        u32 prescaler;
+        u32 cycles;
+        u32 time;
+        time = voltage_diff / voltdm->pmic->slew_rate;
+        cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
+        cycles /= 64;
+        prescaler = 0;
+        /* shift to next prescaler until no overflow */
+        /* scale for div 256 = 64 * 4 */
+        if (cycles > 63) {
+                cycles /= 4;
+                prescaler++;
+        }
+        /* scale for div 512 = 256 * 2 */
+        if (cycles > 63) {
+                cycles /= 2;
+                prescaler++;
+        }
+        /* scale for div 2048 = 512 * 4 */
+        if (cycles > 63) {
+                cycles /= 4;
+                prescaler++;
+        }
+        /* check for overflow => invalid ramp time */
+        if (cycles > 63) {
+                pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
+                        voltdm->name);
+                return 0;
+        }
+        cycles++;
-        omap3_vfsm_init(voltdm);
+        return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
+                (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
+}
+/**
+ * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
+ * @usec: microseconds
+ * @shift: number of bits to shift left
+ * @mask: bitfield mask
+ *
+ * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
+ * shifted to requested position, and checked agains the mask value.
+ * If larger, forced to the max value of the field (i.e. the mask itself.)
+ * Returns the SCRM bitfield value.
+ */
+static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
+{
+        u32 val;
+        val = omap_usec_to_32k(usec) << shift;
-        is_initialized = true;
+        /* Check for overflow, if yes, force to max value */
+        if (val > mask)
+                val = mask;
+        return val;
 }
+/**
+ * omap4_set_timings - set voltage ramp timings for a channel
+ * @voltdm: channel to configure
+ * @off_mode: whether off-mode values are used
+ *
+ * Calculates and sets the voltage ramp up / down values for a channel.
+ */
+static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
+{
+        u32 val;
+        u32 ramp;
+        int offset;
+        u32 tstart, tshut;
+        if (off_mode) {
+                ramp = omap4_calc_volt_ramp(voltdm,
+                        voltdm->vc_param->on - voltdm->vc_param->off);
+                offset = voltdm->vfsm->voltsetup_off_reg;
+        } else {
+                ramp = omap4_calc_volt_ramp(voltdm,
+                        voltdm->vc_param->on - voltdm->vc_param->ret);
+                offset = voltdm->vfsm->voltsetup_reg;
+        }
+        if (!ramp)
+                return;
+        val = voltdm->read(offset);
+        val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
+        val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
+        voltdm->write(val, offset);
+        omap_pm_get_oscillator(&tstart, &tshut);
+        val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
+                OMAP4_SETUPTIME_MASK);
+        val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
+                OMAP4_DOWNTIME_MASK);
+        __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
+}
 /* OMAP4 specific voltage init functions */
 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
 {
-        static bool is_initialized;
+        omap4_set_timings(voltdm, true);
-        u32 vc_val;
+        omap4_set_timings(voltdm, false);
+}
+struct i2c_init_data {
+        u8 loadbits;
+        u8 load;
+        u8 hsscll_38_4;
+        u8 hsscll_26;
+        u8 hsscll_19_2;
+        u8 hsscll_16_8;
+        u8 hsscll_12;
+};
-        if (is_initialized)
+static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = {
+        {
+                .load = 50,
+                .loadbits = 0x3,
+                .hsscll_38_4 = 13,
+                .hsscll_26 = 11,
+                .hsscll_19_2 = 9,
+                .hsscll_16_8 = 9,
+                .hsscll_12 = 8,
+        },
+        {
+                .load = 25,
+                .loadbits = 0x2,
+                .hsscll_38_4 = 13,
+                .hsscll_26 = 11,
+                .hsscll_19_2 = 9,
+                .hsscll_16_8 = 9,
+                .hsscll_12 = 8,
+        },
+        {
+                .load = 12,
+                .loadbits = 0x1,
+                .hsscll_38_4 = 11,
+                .hsscll_26 = 10,
+                .hsscll_19_2 = 9,
+                .hsscll_16_8 = 9,
+                .hsscll_12 = 8,
+        },
+        {
+                .load = 0,
+                .loadbits = 0x0,
+                .hsscll_38_4 = 12,
+                .hsscll_26 = 10,
+                .hsscll_19_2 = 9,
+                .hsscll_16_8 = 8,
+                .hsscll_12 = 8,
+        },
+};
+/**
+ * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
+ * @voltdm: voltagedomain pointer to get data from
+ *
+ * Use PMIC + board supplied settings for calculating the total I2C
+ * channel capacitance and set the timing parameters based on this.
+ * Pre-calculated values are provided in data tables, as it is not
+ * too straightforward to calculate these runtime.
+ */
+static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
+{
+        u32 capacitance;
+        u32 val;
+        u16 hsscll;
+        const struct i2c_init_data *i2c_data;
+        if (!voltdm->pmic->i2c_high_speed) {
+                pr_warn("%s: only high speed supported!\n", __func__);
                return;
+        }
+        /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
+        capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
+        /* OMAP pad capacitance */
+        capacitance += 4;
+        /* PMIC pad capacitance */
+        capacitance += voltdm->pmic->i2c_pad_load;
+        /* Search for capacitance match in the table */
+        i2c_data = omap4_i2c_timing_data;
+        while (i2c_data->load > capacitance)
+                i2c_data++;
+        /* Select proper values based on sysclk frequency */
+        switch (voltdm->sys_clk.rate) {
+        case 38400000:
+                hsscll = i2c_data->hsscll_38_4;
+                break;
+        case 26000000:
+                hsscll = i2c_data->hsscll_26;
+                break;
+        case 19200000:
+                hsscll = i2c_data->hsscll_19_2;
+                break;
+        case 16800000:
+                hsscll = i2c_data->hsscll_16_8;
+                break;
+        case 12000000:
+                hsscll = i2c_data->hsscll_12;
+                break;
+        default:
+                pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
+                        voltdm->sys_clk.rate);
+                return;
+        }
-        /* XXX These are magic numbers and do not belong! */
+        /* Loadbits define pull setup for the I2C channels */
-        vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+        val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
-        voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
-        is_initialized = true;
+        /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
+        __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
+                                OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
+        /* HSSCLH can always be zero */
+        val = hsscll << OMAP4430_HSSCLL_SHIFT;
+        val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
+        /* Write setup times to I2C config register */
+        voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
 }
 /**
 * omap_vc_i2c_init - initialize I2C interface to PMIC
 * @voltdm: voltage domain containing VC data
@@ -281,9 +636,51 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
                            mcode << __ffs(vc->common->i2c_mcode_mask),
                            vc->common->i2c_cfg_reg);
+        if (cpu_is_omap44xx())
+                omap4_vc_i2c_timing_init(voltdm);
        initialized = true;
 }
+/**
+ * omap_vc_calc_vsel - calculate vsel value for a channel
+ * @voltdm: channel to calculate value for
+ * @uvolt: microvolt value to convert to vsel
+ *
+ * Converts a microvolt value to vsel value for the used PMIC.
+ * This checks whether the microvolt value is out of bounds, and
+ * adjusts the value accordingly. If unsupported value detected,
+ * warning is thrown.
+ */
+static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
+{
+        if (voltdm->pmic->vddmin > uvolt)
+                uvolt = voltdm->pmic->vddmin;
+        if (voltdm->pmic->vddmax < uvolt) {
+                WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
+                        __func__, uvolt, voltdm->pmic->vddmax);
+                /* Lets try maximum value anyway */
+                uvolt = voltdm->pmic->vddmax;
+        }
+        return voltdm->pmic->uv_to_vsel(uvolt);
+}
+#ifdef CONFIG_PM
+/**
+ * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
+ * @mm: length of the PCB trace in millimetres
+ *
+ * Sets the PCB trace length for the I2C channel. By default uses 63mm.
+ * This is needed for properly calculating the capacitance value for
+ * the PCB trace, and for setting the SR I2C channel timing parameters.
+ */
+void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
+{
+        sr_i2c_pcb_length = mm;
+}
+#endif
 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
 {
        struct omap_vc_channel *vc = voltdm->vc;
@@ -311,7 +708,6 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
        vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
        vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
        vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
-        vc->setup_time = voltdm->pmic->volt_setup_time;
        /* Configure the i2c slave address for this VC */
        voltdm->rmw(vc->smps_sa_mask,
@@ -331,14 +727,18 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
                voltdm->rmw(vc->smps_cmdra_mask,
                            vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
                            vc->smps_cmdra_reg);
-                vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
+                vc->cfg_channel |= vc_cfg_bits->rac;
        }
+        if (vc->cmd_reg_addr == vc->volt_reg_addr)
+                vc->cfg_channel |= vc_cfg_bits->racen;
        /* Set up the on, inactive, retention and off voltage */
-        on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
+        on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
-        onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
+        onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
-        ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
+        ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
-        off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
+        off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
        val = ((on_vsel << vc->common->cmd_on_shift) |
               (onlp_vsel << vc->common->cmd_onlp_shift) |
               (ret_vsel << vc->common->cmd_ret_shift) |
@@ -349,11 +749,6 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
        /* Channel configuration */
        omap_vc_config_channel(voltdm);
-        /* Configure the setup times */
-        voltdm->rmw(voltdm->vfsm->voltsetup_mask,
-                    vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
-                    voltdm->vfsm->voltsetup_reg);
        omap_vc_i2c_init(voltdm);
        if (cpu_is_omap34xx())
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index 478bf6b432c4..91c8d75bf2ea 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -86,7 +86,6 @@ struct omap_vc_channel {
        u16 i2c_slave_addr;
        u16 volt_reg_addr;
        u16 cmd_reg_addr;
-        u16 setup_time;
        u8 cfg_channel;
        bool i2c_high_speed;
@@ -111,6 +110,13 @@ extern struct omap_vc_channel omap4_vc_mpu;
 extern struct omap_vc_channel omap4_vc_iva;
 extern struct omap_vc_channel omap4_vc_core;
+extern struct omap_vc_param omap3_mpu_vc_data;
+extern struct omap_vc_param omap3_core_vc_data;
+extern struct omap_vc_param omap4_mpu_vc_data;
+extern struct omap_vc_param omap4_iva_vc_data;
+extern struct omap_vc_param omap4_core_vc_data;
 void omap_vc_init_channel(struct voltagedomain *voltdm);
 int omap_vc_pre_scale(struct voltagedomain *voltdm,
                      unsigned long target_volt,
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index 5d8eaf31569c..75bc4aa22b3a 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -71,3 +71,25 @@ struct omap_vc_channel omap3_vc_core = {
        .smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
        .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
 };
+/*
+ * Voltage levels for different operating modes: on, sleep, retention and off
+ */
+#define OMAP3_ON_VOLTAGE_UV             1200000
+#define OMAP3_ONLP_VOLTAGE_UV           1000000
+#define OMAP3_RET_VOLTAGE_UV            975000
+#define OMAP3_OFF_VOLTAGE_UV            600000
+struct omap_vc_param omap3_mpu_vc_data = {
+        .on             = OMAP3_ON_VOLTAGE_UV,
+        .onlp           = OMAP3_ONLP_VOLTAGE_UV,
+        .ret            = OMAP3_RET_VOLTAGE_UV,
+        .off            = OMAP3_OFF_VOLTAGE_UV,
+};
+struct omap_vc_param omap3_core_vc_data = {
+        .on             = OMAP3_ON_VOLTAGE_UV,
+        .onlp           = OMAP3_ONLP_VOLTAGE_UV,
+        .ret            = OMAP3_RET_VOLTAGE_UV,
+        .off            = OMAP3_OFF_VOLTAGE_UV,
+};
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
index d70b930f2739..085e5d6a04fd 100644
--- a/arch/arm/mach-omap2/vc44xx_data.c
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -87,3 +87,31 @@ struct omap_vc_channel omap4_vc_core = {
        .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
 };
+/*
+ * Voltage levels for different operating modes: on, sleep, retention and off
+ */
+#define OMAP4_ON_VOLTAGE_UV                     1375000
+#define OMAP4_ONLP_VOLTAGE_UV                   1375000
+#define OMAP4_RET_VOLTAGE_UV                    837500
+#define OMAP4_OFF_VOLTAGE_UV                    0
+struct omap_vc_param omap4_mpu_vc_data = {
+        .on                     = OMAP4_ON_VOLTAGE_UV,
+        .onlp                   = OMAP4_ONLP_VOLTAGE_UV,
+        .ret                    = OMAP4_RET_VOLTAGE_UV,
+        .off                    = OMAP4_OFF_VOLTAGE_UV,
+};
+struct omap_vc_param omap4_iva_vc_data = {
+        .on                     = OMAP4_ON_VOLTAGE_UV,
+        .onlp                   = OMAP4_ONLP_VOLTAGE_UV,
+        .ret                    = OMAP4_RET_VOLTAGE_UV,
+        .off                    = OMAP4_OFF_VOLTAGE_UV,
+};
+struct omap_vc_param omap4_core_vc_data = {
+        .on                     = OMAP4_ON_VOLTAGE_UV,
+        .onlp                   = OMAP4_ONLP_VOLTAGE_UV,
+        .ret                    = OMAP4_RET_VOLTAGE_UV,
+        .off                    = OMAP4_OFF_VOLTAGE_UV,
+};
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 7283b7ed7de8..a0ce4f10ff13 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -40,12 +40,14 @@ struct powerdomain;
 * data
 * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
 * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
+ * @voltsetup_off_reg: register offset of PRM_VOLTSETUP_OFF from PRM base
 *
 * XXX What about VOLTOFFSET/VOLTCTRL?
 */
 struct omap_vfsm_instance {
        u32 voltsetup_mask;
        u8 voltsetup_reg;
+        u8 voltsetup_off_reg;
 };
 /**
@@ -74,6 +76,8 @@ struct voltagedomain {
        const struct omap_vfsm_instance *vfsm;
        struct omap_vp_instance *vp;
        struct omap_voltdm_pmic *pmic;
+        struct omap_vp_param *vp_param;
+        struct omap_vc_param *vc_param;
        /* VC/VP register access functions: SoC specific */
        u32 (*read) (u8 offset);
@@ -92,6 +96,24 @@ struct voltagedomain {
        struct omap_volt_data *volt_data;
 };
+/* Min and max voltages from OMAP perspective */
+#define OMAP3430_VP1_VLIMITTO_VDDMIN    850000
+#define OMAP3430_VP1_VLIMITTO_VDDMAX    1425000
+#define OMAP3430_VP2_VLIMITTO_VDDMIN    900000
+#define OMAP3430_VP2_VLIMITTO_VDDMAX    1150000
+#define OMAP3630_VP1_VLIMITTO_VDDMIN    900000
+#define OMAP3630_VP1_VLIMITTO_VDDMAX    1350000
+#define OMAP3630_VP2_VLIMITTO_VDDMIN    900000
+#define OMAP3630_VP2_VLIMITTO_VDDMAX    1200000
+#define OMAP4_VP_MPU_VLIMITTO_VDDMIN    830000
+#define OMAP4_VP_MPU_VLIMITTO_VDDMAX    1410000
+#define OMAP4_VP_IVA_VLIMITTO_VDDMIN    830000
+#define OMAP4_VP_IVA_VLIMITTO_VDDMAX    1260000
+#define OMAP4_VP_CORE_VLIMITTO_VDDMIN   830000
+#define OMAP4_VP_CORE_VLIMITTO_VDDMAX   1200000
 /**
 * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
 * @slew_rate:  PMIC slew rate (in uv/us)
@@ -107,26 +129,34 @@ struct voltagedomain {
 struct omap_voltdm_pmic {
        int slew_rate;
        int step_size;
-        u32 on_volt;
-        u32 onlp_volt;
-        u32 ret_volt;
-        u32 off_volt;
-        u16 volt_setup_time;
        u16 i2c_slave_addr;
        u16 volt_reg_addr;
        u16 cmd_reg_addr;
        u8 vp_erroroffset;
        u8 vp_vstepmin;
        u8 vp_vstepmax;
-        u8 vp_vddmin;
+        u32 vddmin;
-        u8 vp_vddmax;
+        u32 vddmax;
        u8 vp_timeout_us;
        bool i2c_high_speed;
+        u32 i2c_pad_load;
        u8 i2c_mcode;
        unsigned long (*vsel_to_uv) (const u8 vsel);
        u8 (*uv_to_vsel) (unsigned long uV);
 };
+struct omap_vp_param {
+        u32 vddmax;
+        u32 vddmin;
+};
+struct omap_vc_param {
+        u32 on;
+        u32 onlp;
+        u32 ret;
+        u32 off;
+};
 void omap_voltage_get_volttable(struct voltagedomain *voltdm,
                struct omap_volt_data **volt_data);
 struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index 63afbfed3cbc..261bb7cb4e60 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -117,6 +117,11 @@ void __init omap3xxx_voltagedomains_init(void)
        }
 #endif
+        omap3_voltdm_mpu.vp_param = &omap3_mpu_vp_data;
+        omap3_voltdm_core.vp_param = &omap3_core_vp_data;
+        omap3_voltdm_mpu.vc_param = &omap3_mpu_vc_data;
+        omap3_voltdm_core.vc_param = &omap3_core_vc_data;
        if (soc_is_am35xx())
                voltdms = voltagedomains_am35xx;
        else
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index c3115f6853d4..48b22a0a0c88 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -22,7 +22,7 @@
 #include <linux/init.h>
 #include "common.h"
+#include "soc.h"
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
 #include "prcm44xx.h"
@@ -34,14 +34,17 @@
 static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+        .voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET,
 };
 static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = {
        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
+        .voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET,
 };
 static const struct omap_vfsm_instance omap4_vdd_core_vfsm = {
        .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+        .voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET,
 };
 static struct voltagedomain omap4_voltdm_mpu = {
@@ -101,11 +104,25 @@ void __init omap44xx_voltagedomains_init(void)
         * for the currently-running IC
         */
 #ifdef CONFIG_PM_OPP
-        omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
+        if (cpu_is_omap443x()) {
-        omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
+                omap4_voltdm_mpu.volt_data = omap443x_vdd_mpu_volt_data;
-        omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
+                omap4_voltdm_iva.volt_data = omap443x_vdd_iva_volt_data;
+                omap4_voltdm_core.volt_data = omap443x_vdd_core_volt_data;
+        } else if (cpu_is_omap446x()) {
+                omap4_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
+                omap4_voltdm_iva.volt_data = omap446x_vdd_iva_volt_data;
+                omap4_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
+        }
 #endif
+        omap4_voltdm_mpu.vp_param = &omap4_mpu_vp_data;
+        omap4_voltdm_iva.vp_param = &omap4_iva_vp_data;
+        omap4_voltdm_core.vp_param = &omap4_core_vp_data;
+        omap4_voltdm_mpu.vc_param = &omap4_mpu_vc_data;
+        omap4_voltdm_iva.vc_param = &omap4_iva_vc_data;
+        omap4_voltdm_core.vc_param = &omap4_core_vc_data;
        for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
                voltdm->sys_clk.name = sys_clk_name;
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 85241b828c02..a3c30655aa30 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -58,8 +58,10 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
        sys_clk_rate = voltdm->sys_clk.rate / 1000;
        timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
-        vddmin = voltdm->pmic->vp_vddmin;
+        vddmin = max(voltdm->vp_param->vddmin, voltdm->pmic->vddmin);
-        vddmax = voltdm->pmic->vp_vddmax;
+        vddmax = min(voltdm->vp_param->vddmax, voltdm->pmic->vddmax);
+        vddmin = voltdm->pmic->uv_to_vsel(vddmin);
+        vddmax = voltdm->pmic->uv_to_vsel(vddmax);
        waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
                                1000 * voltdm->pmic->slew_rate);
@@ -138,7 +140,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
                udelay(1);
        }
        if (timeout >= VP_TRANXDONE_TIMEOUT) {
-                pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
+                pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted\n",
                        __func__, voltdm->name);
                return -ETIMEDOUT;
        }
@@ -197,7 +199,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
        u32 vpconfig, volt;
        if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                return;
        }
@@ -214,8 +216,8 @@ void omap_vp_enable(struct voltagedomain *voltdm)
        volt = voltdm_get_voltage(voltdm);
        if (!volt) {
-                pr_warning("%s: unable to find current voltage for %s\n",
+                pr_warn("%s: unable to find current voltage for %s\n",
-                           __func__, voltdm->name);
+                        __func__, voltdm->name);
                return;
        }
@@ -242,7 +244,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
        int timeout;
        if (!voltdm || IS_ERR(voltdm)) {
-                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                pr_warn("%s: VDD specified does not exist!\n", __func__);
                return;
        }
@@ -272,8 +274,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
                          VP_IDLE_TIMEOUT, timeout);
        if (timeout >= VP_IDLE_TIMEOUT)
-                pr_warning("%s: vdd_%s idle timedout\n",
+                pr_warn("%s: vdd_%s idle timedout\n", __func__, voltdm->name);
-                        __func__, voltdm->name);
        vp->enabled = false;
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 7c155d248aa3..0fdf7080e4a6 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -117,6 +117,13 @@ extern struct omap_vp_instance omap4_vp_mpu;
 extern struct omap_vp_instance omap4_vp_iva;
 extern struct omap_vp_instance omap4_vp_core;
+extern struct omap_vp_param omap3_mpu_vp_data;
+extern struct omap_vp_param omap3_core_vp_data;
+extern struct omap_vp_param omap4_mpu_vp_data;
+extern struct omap_vp_param omap4_iva_vp_data;
+extern struct omap_vp_param omap4_core_vp_data;
 void omap_vp_init(struct voltagedomain *voltdm);
 void omap_vp_enable(struct voltagedomain *voltdm);
 void omap_vp_disable(struct voltagedomain *voltdm);
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index bd89f80089f5..1914e026245e 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -77,3 +77,13 @@ struct omap_vp_instance omap3_vp_core = {
        .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
        .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
 };
+struct omap_vp_param omap3_mpu_vp_data = {
+        .vddmin                 = OMAP3430_VP1_VLIMITTO_VDDMIN,
+        .vddmax                 = OMAP3430_VP1_VLIMITTO_VDDMAX,
+};
+struct omap_vp_param omap3_core_vp_data = {
+        .vddmin                 = OMAP3430_VP2_VLIMITTO_VDDMIN,
+        .vddmax                 = OMAP3430_VP2_VLIMITTO_VDDMAX,
+};
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index 8c031d16879e..e62f6b018beb 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -87,3 +87,18 @@ struct omap_vp_instance omap4_vp_core = {
        .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
        .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
 };
+struct omap_vp_param omap4_mpu_vp_data = {
+        .vddmin                 = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
+        .vddmax                 = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
+};
+struct omap_vp_param omap4_iva_vp_data = {
+        .vddmin                 = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
+        .vddmax                 = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
+};
+struct omap_vp_param omap4_core_vp_data = {
+        .vddmin                 = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
+        .vddmax                 = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
+};
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index b2f1c67043a2..7c2b4ed38f02 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -1,6 +1,8 @@
 /*
 * OMAP2+ MPU WD_TIMER-specific code
 *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
@@ -11,10 +13,14 @@
 #include <linux/io.h>
 #include <linux/err.h>
-#include <plat/omap_hwmod.h>
+#include <linux/platform_data/omap-wd-timer.h>
+#include "omap_hwmod.h"
+#include "omap_device.h"
 #include "wd_timer.h"
 #include "common.h"
+#include "prm.h"
+#include "soc.h"
 /*
 * In order to avoid any assumptions from bootloader regarding WDT
@@ -26,9 +32,6 @@
 #define OMAP_WDT_WPS            0x34
 #define OMAP_WDT_SPR            0x48
-/* Maximum microseconds to wait for OMAP module to softreset */
-#define MAX_MODULE_SOFTRESET_WAIT       10000
 int omap2_wd_timer_disable(struct omap_hwmod *oh)
 {
        void __iomem *base;
@@ -99,3 +102,32 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh)
        return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
                omap2_wd_timer_disable(oh);
 }
+static int __init omap_init_wdt(void)
+{
+        int id = -1;
+        struct platform_device *pdev;
+        struct omap_hwmod *oh;
+        char *oh_name = "wd_timer2";
+        char *dev_name = "omap_wdt";
+        struct omap_wd_timer_platform_data pdata;
+        if (!cpu_class_is_omap2() || of_have_populated_dt())
+                return 0;
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up wd_timer%d hwmod\n", id);
+                return -EINVAL;
+        }
+        pdata.read_reset_sources = prm_read_reset_sources;
+        pdev = omap_device_build(dev_name, id, oh, &pdata,
+                                 sizeof(struct omap_wd_timer_platform_data),
+                                 NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+             dev_name, oh->name);
+        return 0;
+}
+subsys_initcall(omap_init_wdt);
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
index f6bbba73b535..a78f81034a9f 100644
--- a/arch/arm/mach-omap2/wd_timer.h
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -10,7 +10,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
 #define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
-#include <plat/omap_hwmod.h>
+#include "omap_hwmod.h"
 extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
 extern int omap2_wd_timer_reset(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 0673f0c10432..2cb2f06c20f5 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -2,6 +2,13 @@ if ARCH_ORION5X
 menu "Orion Implementations"
+config ARCH_ORION5X_DT
+        bool "Marvell Orion5x Flattened Device Tree"
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Orion5x using flattened device tree.
 config MACH_DB88F5281
        bool "Marvell Orion-2 Development Board"
        select I2C_BOARDINFO
@@ -96,12 +103,13 @@ config MACH_MV2120
          Say 'Y' here if you want your kernel to support the
          HP Media Vault mv2120 or mv5100.
-config MACH_EDMINI_V2
+config MACH_EDMINI_V2_DT
-        bool "LaCie Ethernet Disk mini V2"
+        bool "LaCie Ethernet Disk mini V2 (Flattened Device Tree)"
        select I2C_BOARDINFO
+        select ARCH_ORION5X_DT
        help
          Say 'Y' here if you want your kernel to support the
-          LaCie Ethernet Disk mini V2.
+          LaCie Ethernet Disk mini V2 (Flattened Device Tree).
 config MACH_D2NET
        bool "LaCie d2 Network"
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 7f18cdacd487..9e809a7c05c0 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_MACH_TS409)	+= ts409-setup.o tsx09-common.o
 obj-$(CONFIG_MACH_WRT350N_V2)   += wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
-obj-$(CONFIG_MACH_EDMINI_V2)    += edmini_v2-setup.o
 obj-$(CONFIG_MACH_D2NET)        += d2net-setup.o
 obj-$(CONFIG_MACH_BIGDISK)      += d2net-setup.o
 obj-$(CONFIG_MACH_NET2BIG)      += net2big-setup.o
@@ -22,3 +21,6 @@ obj-$(CONFIG_MACH_RD88F5181L_GE)	+= rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)       += rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)       += rd88f6183ap-ge-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_LSCHL)    += ls-chl-setup.o
+obj-$(CONFIG_ARCH_ORION5X_DT)           += board-dt.o
+obj-$(CONFIG_MACH_EDMINI_V2_DT) += edmini_v2-setup.o
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
new file mode 100644
index 000000000000..32e5c211a89b
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2012 (C), Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * arch/arm/mach-orion5x/board-dt.c
+ *
+ * Flattened Device Tree board initialization
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <asm/system_misc.h>
+#include <asm/mach/arch.h>
+#include <mach/orion5x.h>
+#include <plat/irq.h>
+#include "common.h"
+struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+        OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+                       NULL),
+        OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+        OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
+        OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1090000, "mv_crypto", NULL),
+        {},
+};
+static void __init orion5x_dt_init(void)
+{
+        char *dev_name;
+        u32 dev, rev;
+        orion5x_id(&dev, &rev, &dev_name);
+        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
+        /*
+         * Setup Orion address map
+         */
+        orion5x_setup_cpu_mbus_bridge();
+        /* Setup root of clk tree */
+        clk_init();
+        /*
+         * Don't issue "Wait for Interrupt" instruction if we are
+         * running on D0 5281 silicon.
+         */
+        if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
+                printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
+                disable_hlt();
+        }
+        if (of_machine_is_compatible("lacie,ethernet-disk-mini-v2"))
+                edmini_v2_init();
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             orion5x_auxdata_lookup, NULL);
+}
+static const char *orion5x_dt_compat[] = {
+        "marvell,orion5x",
+        NULL,
+};
+DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
+        /* Maintainer: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */
+        .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
+        .init_irq       = orion_dt_init_irq,
+        .timer          = &orion5x_timer,
+        .init_machine   = orion5x_dt_init,
+        .restart        = orion5x_restart,
+        .dt_compat      = orion5x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b3eb3da01160..550f92320afb 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -65,7 +65,7 @@ void __init orion5x_map_io(void)
 ****************************************************************************/
 static struct clk *tclk;
-static void __init clk_init(void)
+void __init clk_init(void)
 {
        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
                                       orion5x_tclk);
@@ -236,7 +236,7 @@ struct sys_timer orion5x_timer = {
 /*
 * Identify device ID and rev from PCIe configuration header space '0'.
 */
-static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
+void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 {
        orion5x_pcie_id(dev, rev);
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 31bab92ce038..7db5cdd9c4b7 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -12,6 +12,8 @@ void orion5x_map_io(void);
 void orion5x_init_early(void);
 void orion5x_init_irq(void);
 void orion5x_init(void);
+void orion5x_id(u32 *dev, u32 *rev, char **dev_name);
+void clk_init(void);
 extern int orion5x_tclk;
 extern struct sys_timer orion5x_timer;
@@ -54,6 +56,13 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
 struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
 int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+/* board init functions for boards not fully converted to fdt */
+#ifdef CONFIG_MACH_EDMINI_V2_DT
+void edmini_v2_init(void);
+#else
+static inline void edmini_v2_init(void) {};
+#endif
 struct meminfo;
 struct tag;
 extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *);
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 355e962137c7..d675e727803d 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -115,69 +115,6 @@ static struct i2c_board_info __initdata edmini_v2_i2c_rtc = {
 };
 /*****************************************************************************
- * Sata
- ****************************************************************************/
-static struct mv_sata_platform_data edmini_v2_sata_data = {
-        .n_ports        = 2,
-};
-/*****************************************************************************
- * GPIO LED (simple - doesn't use hardware blinking support)
- ****************************************************************************/
-#define EDMINI_V2_GPIO_LED_POWER        16
-static struct gpio_led edmini_v2_leds[] = {
-        {
-                .name = "power:blue",
-                .gpio = EDMINI_V2_GPIO_LED_POWER,
-                .active_low = 1,
-        },
-};
-static struct gpio_led_platform_data edmini_v2_led_data = {
-        .num_leds = ARRAY_SIZE(edmini_v2_leds),
-        .leds = edmini_v2_leds,
-};
-static struct platform_device edmini_v2_gpio_leds = {
-        .name           = "leds-gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &edmini_v2_led_data,
-        },
-};
-/****************************************************************************
- * GPIO key
- ****************************************************************************/
-#define EDMINI_V2_GPIO_KEY_POWER        18
-static struct gpio_keys_button edmini_v2_buttons[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = EDMINI_V2_GPIO_KEY_POWER,
-                .desc           = "Power Button",
-                .active_low     = 0,
-        },
-};
-static struct gpio_keys_platform_data edmini_v2_button_data = {
-        .buttons        = edmini_v2_buttons,
-        .nbuttons       = ARRAY_SIZE(edmini_v2_buttons),
-};
-static struct platform_device edmini_v2_gpio_buttons = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &edmini_v2_button_data,
-        },
-};
-/*****************************************************************************
 * General Setup
 ****************************************************************************/
 static unsigned int edminiv2_mpp_modes[] __initdata = {
@@ -207,13 +144,8 @@ static unsigned int edminiv2_mpp_modes[] __initdata = {
        0,
 };
-static void __init edmini_v2_init(void)
+void __init edmini_v2_init(void)
 {
-        /*
-         * Setup basic Orion functions. Need to be called early.
-         */
-        orion5x_init();
        orion5x_mpp_conf(edminiv2_mpp_modes);
        /*
@@ -221,15 +153,10 @@ static void __init edmini_v2_init(void)
         */
        orion5x_ehci0_init();
        orion5x_eth_init(&edmini_v2_eth_data);
-        orion5x_i2c_init();
-        orion5x_sata_init(&edmini_v2_sata_data);
-        orion5x_uart0_init();
        orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE,
                                EDMINI_V2_NOR_BOOT_SIZE);
        platform_device_register(&edmini_v2_nor_flash);
-        platform_device_register(&edmini_v2_gpio_leds);
-        platform_device_register(&edmini_v2_gpio_buttons);
        pr_notice("edmini_v2: USB device port, flash write and power-off "
                  "are not yet supported.\n");
@@ -247,16 +174,3 @@ static void __init edmini_v2_init(void)
        i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1);
 }
-/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
-MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
-        /* Maintainer: Christopher Moore <moore@free.fr> */
-        .atag_offset    = 0x100,
-        .init_machine   = edmini_v2_init,
-        .map_io         = orion5x_map_io,
-        .init_early     = orion5x_init_early,
-        .init_irq       = orion5x_init_irq,
-        .timer          = &orion5x_timer,
-        .fixup          = tag_fixup_mem32,
-        .restart        = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 11aa7399dc09..86eec4159cbc 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -2,27 +2,6 @@ if ARCH_PXA
 menu "Intel PXA2xx/PXA3xx Implementations"
-config ARCH_PXA_V7
-        bool "ARMv7 (PXA95x) based systems"
-if ARCH_PXA_V7
-comment "Marvell Dev Platforms (sorted by hardware release time)"
-config MACH_TAVOREVB3
-        bool "PXA95x Development Platform (aka TavorEVB III)"
-        select CPU_PXA955
-config MACH_SAARB
-        bool "PXA955 Handheld Platform (aka SAARB)"
-        select CPU_PXA955
-endif
-config PXA_V7_MACH_AUTO
-        def_bool y
-        depends on ARCH_PXA_V7
-        depends on !MACH_SAARB
-        select MACH_TAVOREVB3
-if !ARCH_PXA_V7
 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
 config MACH_PXA3XX_DT
@@ -630,7 +609,6 @@ config MACH_ZIPIT2
        bool "Zipit Z2 Handheld"
        select HAVE_PWM
        select PXA27x
-endif
 endmenu
 config PXA25x
@@ -688,18 +666,6 @@ config CPU_PXA935
        help
          PXA935 (codename Tavor-P65)
-config PXA95x
-        bool
-        select CPU_PJ4
-        help
-          Select code specific to PXA95x variants
-config CPU_PXA955
-        bool
-        select PXA95x
-        help
-          PXA950 (codename MG1)
 config PXA_SHARP_C7xx
        bool
        select SHARPSL_PM
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index ee88d6eae648..12c500558387 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -19,7 +19,6 @@ endif
 obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
 obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
 obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
-obj-$(CONFIG_PXA95x)            += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o pxa95x.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
@@ -36,9 +35,7 @@ obj-$(CONFIG_MACH_ZYLONITE300)	+= zylonite.o zylonite_pxa300.o
 obj-$(CONFIG_MACH_ZYLONITE320)  += zylonite.o zylonite_pxa320.o
 obj-$(CONFIG_MACH_LITTLETON)    += littleton.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
-obj-$(CONFIG_MACH_TAVOREVB3)    += tavorevb3.o
 obj-$(CONFIG_MACH_SAAR)         += saar.o
-obj-$(CONFIG_MACH_SAARB)        += saarb.o
 # 3rd Party Dev Platforms
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 3a258b1bf1aa..1f65d32c8d5e 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -57,7 +57,7 @@ void clk_pxa2xx_cken_disable(struct clk *clk);
 extern struct syscore_ops pxa2xx_clock_syscore_ops;
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#if defined(CONFIG_PXA3xx)
 #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay)   \
 struct clk clk_##_name = {                              \
                .ops    = &clk_pxa3xx_cken_ops,         \
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index ddaa04de8e22..daa86d39ed9e 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -703,7 +703,7 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
 }
 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 static struct resource pxa27x_resource_keypad[] = {
        [0] = {
                .start  = 0x41500000,
@@ -872,7 +872,7 @@ struct platform_device pxa27x_device_pwm1 = {
        .resource       = pxa27x_resource_pwm1,
        .num_resources  = ARRAY_SIZE(pxa27x_resource_pwm1),
 };
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
 #ifdef CONFIG_PXA3xx
 static struct resource pxa3xx_resources_mci2[] = {
@@ -981,7 +981,7 @@ struct platform_device pxa3xx_device_gcu = {
 #endif /* CONFIG_PXA3xx */
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#if defined(CONFIG_PXA3xx)
 static struct resource pxa3xx_resources_i2c_power[] = {
        {
                .start  = 0x40f500c0,
@@ -1082,7 +1082,7 @@ struct platform_device pxa3xx_device_ssp4 = {
        .resource       = pxa3xx_resource_ssp4,
        .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
 };
-#endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
+#endif /* CONFIG_PXA3xx */
 struct resource pxa_resource_gpio[] = {
        {
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 56d92e5cad85..ccb06e485520 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -194,17 +194,6 @@
 #define __cpu_is_pxa935(id)     (0)
 #endif
-#ifdef CONFIG_CPU_PXA955
-#define __cpu_is_pxa955(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x581 || _id == 0xc08            \
-                        || _id == 0xb76;                \
-        })
-#else
-#define __cpu_is_pxa955(id)     (0)
-#endif
 #define cpu_is_pxa210()                                 \
        ({                                              \
                __cpu_is_pxa210(read_cpuid_id());       \
@@ -255,10 +244,6 @@
                __cpu_is_pxa935(read_cpuid_id());       \
         })
-#define cpu_is_pxa955()                                 \
-        ({                                              \
-                __cpu_is_pxa955(read_cpuid_id());       \
-        })
 /*
@@ -297,15 +282,6 @@
 #define __cpu_is_pxa93x(id)     (0)
 #endif
-#ifdef CONFIG_PXA95x
-#define __cpu_is_pxa95x(id)                             \
-        ({                                              \
-                __cpu_is_pxa955(id);                    \
-        })
-#else
-#define __cpu_is_pxa95x(id)     (0)
-#endif
 #define cpu_is_pxa2xx()                                 \
        ({                                              \
                __cpu_is_pxa2xx(read_cpuid_id());       \
@@ -321,10 +297,6 @@
                __cpu_is_pxa93x(read_cpuid_id());       \
         })
-#define cpu_is_pxa95x()                                 \
-        ({                                              \
-                __cpu_is_pxa95x(read_cpuid_id());       \
-        })
 /*
 * return current memory and LCD clock frequency in units of 10kHz
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 8765782dd955..48c2fd851686 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -84,7 +84,6 @@
 #define IRQ_PXA935_MMC0 PXA_IRQ(72)     /* MMC0 Controller (PXA935) */
 #define IRQ_PXA935_MMC1 PXA_IRQ(73)     /* MMC1 Controller (PXA935) */
 #define IRQ_PXA935_MMC2 PXA_IRQ(74)     /* MMC2 Controller (PXA935) */
-#define IRQ_PXA955_MMC3 PXA_IRQ(75)     /* MMC3 Controller (PXA955) */
 #define IRQ_U2P         PXA_IRQ(93)     /* USB PHY D+/D- Lines (PXA935) */
 #define PXA_GPIO_IRQ_BASE       PXA_IRQ(96)
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h
index cd3e57f42688..6dd7fa163e29 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx.h
@@ -7,7 +7,6 @@
 extern void __init pxa3xx_map_io(void);
 extern void __init pxa3xx_init_irq(void);
-extern void __init pxa95x_init_irq(void);
 #define pxa3xx_handle_irq       ichp_handle_irq
diff --git a/arch/arm/mach-pxa/include/mach/pxa95x.h b/arch/arm/mach-pxa/include/mach/pxa95x.h
deleted file mode 100644
index cbb097c4cb1f..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa95x.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_PXA95X_H
-#define __MACH_PXA95X_H
-#include <mach/pxa3xx.h>
-#include <mach/mfp-pxa930.h>
-#endif /* __MACH_PXA95X_H */
diff --git a/arch/arm/mach-pxa/include/mach/udc.h b/arch/arm/mach-pxa/include/mach/udc.h
index 2f82332e81a0..9a827e32db98 100644
--- a/arch/arm/mach-pxa/include/mach/udc.h
+++ b/arch/arm/mach-pxa/include/mach/udc.h
@@ -2,7 +2,7 @@
 * arch/arm/mach-pxa/include/mach/udc.h
 *
 */
-#include <asm/mach/udc_pxa2xx.h>
+#include <linux/platform_data/pxa2xx_udc.h>
 extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 113c57a03565..fb7f1d1627dc 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -26,6 +26,7 @@
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/pwm_backlight.h>
+#include <media/mt9v022.h>
 #include <media/soc_camera.h>
 #include <linux/platform_data/camera-pxa.h>
@@ -468,6 +469,10 @@ static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
        },
 };
+static struct mt9v022_platform_data mt9v022_pdata = {
+        .y_skip_top = 1,
+};
 static struct i2c_board_info pcm990_camera_i2c[] = {
        {
                I2C_BOARD_INFO("mt9v022", 0x48),
@@ -480,6 +485,7 @@ static struct soc_camera_link iclink[] = {
        {
                .bus_id                 = 0, /* Must match with the camera ID */
                .board_info             = &pcm990_camera_i2c[0],
+                .priv                   = &mt9v022_pdata,
                .i2c_adapter_id         = 0,
                .query_bus_param        = pcm990_camera_query_bus_param,
                .set_bus_param          = pcm990_camera_set_bus_param,
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 3352b37b60cf..3f5171eaf67b 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -209,6 +209,7 @@ static struct clk_lookup pxa25x_clkregs[] = {
        INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
        INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 static struct clk_lookup pxa25x_hwuart_clkreg =
@@ -338,6 +339,10 @@ void __init pxa25x_map_io(void)
        pxa25x_get_clk_frequency_khz(1);
 }
+static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = {
+        .gpio_set_wake = gpio_set_wake,
+};
 static struct platform_device *pxa25x_devices[] __initdata = {
        &pxa25x_device_udc,
        &pxa_device_pmu,
@@ -370,6 +375,7 @@ static int __init pxa25x_init(void)
                register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                register_syscore_ops(&pxa2xx_clock_syscore_ops);
+                pxa_register_device(&pxa_device_gpio, &pxa25x_gpio_info);
                ret = platform_add_devices(pxa25x_devices,
                                           ARRAY_SIZE(pxa25x_devices));
                if (ret)
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
index 7dbe3ccf1993..e329ccefd364 100644
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -384,18 +384,7 @@ static struct platform_driver pxa3xx_u2d_ulpi_driver = {
        .probe          = pxa3xx_u2d_probe,
        .remove         = pxa3xx_u2d_remove,
 };
+module_platform_driver(pxa3xx_u2d_ulpi_driver);
-static int pxa3xx_u2d_ulpi_init(void)
-{
-        return platform_driver_register(&pxa3xx_u2d_ulpi_driver);
-}
-module_init(pxa3xx_u2d_ulpi_init);
-static void __exit pxa3xx_u2d_ulpi_exit(void)
-{
-        platform_driver_unregister(&pxa3xx_u2d_ulpi_driver);
-}
-module_exit(pxa3xx_u2d_ulpi_exit);
 MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
 MODULE_AUTHOR("Igor Grinberg");
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
deleted file mode 100644
index 47601f80e6e7..000000000000
--- a/arch/arm/mach-pxa/pxa95x.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/pxa95x.c
- *
- * code specific to PXA95x aka MGx
- *
- * Copyright (C) 2009-2010 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/platform_device.h>
-#include <linux/i2c/pxa-i2c.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/pxa930.h>
-#include <mach/reset.h>
-#include <mach/pm.h>
-#include <mach/dma.h>
-#include "generic.h"
-#include "devices.h"
-#include "clock.h"
-static struct mfp_addr_map pxa95x_mfp_addr_map[] __initdata = {
-        MFP_ADDR(GPIO0, 0x02e0),
-        MFP_ADDR(GPIO1, 0x02dc),
-        MFP_ADDR(GPIO2, 0x02e8),
-        MFP_ADDR(GPIO3, 0x02d8),
-        MFP_ADDR(GPIO4, 0x02e4),
-        MFP_ADDR(GPIO5, 0x02ec),
-        MFP_ADDR(GPIO6, 0x02f8),
-        MFP_ADDR(GPIO7, 0x02fc),
-        MFP_ADDR(GPIO8, 0x0300),
-        MFP_ADDR(GPIO9, 0x02d4),
-        MFP_ADDR(GPIO10, 0x02f4),
-        MFP_ADDR(GPIO11, 0x02f0),
-        MFP_ADDR(GPIO12, 0x0304),
-        MFP_ADDR(GPIO13, 0x0310),
-        MFP_ADDR(GPIO14, 0x0308),
-        MFP_ADDR(GPIO15, 0x030c),
-        MFP_ADDR(GPIO16, 0x04e8),
-        MFP_ADDR(GPIO17, 0x04f4),
-        MFP_ADDR(GPIO18, 0x04f8),
-        MFP_ADDR(GPIO19, 0x04fc),
-        MFP_ADDR(GPIO20, 0x0518),
-        MFP_ADDR(GPIO21, 0x051c),
-        MFP_ADDR(GPIO22, 0x04ec),
-        MFP_ADDR(GPIO23, 0x0500),
-        MFP_ADDR(GPIO24, 0x04f0),
-        MFP_ADDR(GPIO25, 0x0504),
-        MFP_ADDR(GPIO26, 0x0510),
-        MFP_ADDR(GPIO27, 0x0514),
-        MFP_ADDR(GPIO28, 0x0520),
-        MFP_ADDR(GPIO29, 0x0600),
-        MFP_ADDR(GPIO30, 0x0618),
-        MFP_ADDR(GPIO31, 0x0610),
-        MFP_ADDR(GPIO32, 0x060c),
-        MFP_ADDR(GPIO33, 0x061c),
-        MFP_ADDR(GPIO34, 0x0620),
-        MFP_ADDR(GPIO35, 0x0628),
-        MFP_ADDR(GPIO36, 0x062c),
-        MFP_ADDR(GPIO37, 0x0630),
-        MFP_ADDR(GPIO38, 0x0634),
-        MFP_ADDR(GPIO39, 0x0638),
-        MFP_ADDR(GPIO40, 0x063c),
-        MFP_ADDR(GPIO41, 0x0614),
-        MFP_ADDR(GPIO42, 0x0624),
-        MFP_ADDR(GPIO43, 0x0608),
-        MFP_ADDR(GPIO44, 0x0604),
-        MFP_ADDR(GPIO45, 0x050c),
-        MFP_ADDR(GPIO46, 0x0508),
-        MFP_ADDR(GPIO47, 0x02bc),
-        MFP_ADDR(GPIO48, 0x02b4),
-        MFP_ADDR(GPIO49, 0x02b8),
-        MFP_ADDR(GPIO50, 0x02c8),
-        MFP_ADDR(GPIO51, 0x02c0),
-        MFP_ADDR(GPIO52, 0x02c4),
-        MFP_ADDR(GPIO53, 0x02d0),
-        MFP_ADDR(GPIO54, 0x02cc),
-        MFP_ADDR(GPIO55, 0x029c),
-        MFP_ADDR(GPIO56, 0x02a0),
-        MFP_ADDR(GPIO57, 0x0294),
-        MFP_ADDR(GPIO58, 0x0298),
-        MFP_ADDR(GPIO59, 0x02a4),
-        MFP_ADDR(GPIO60, 0x02a8),
-        MFP_ADDR(GPIO61, 0x02b0),
-        MFP_ADDR(GPIO62, 0x02ac),
-        MFP_ADDR(GPIO63, 0x0640),
-        MFP_ADDR(GPIO64, 0x065c),
-        MFP_ADDR(GPIO65, 0x0648),
-        MFP_ADDR(GPIO66, 0x0644),
-        MFP_ADDR(GPIO67, 0x0674),
-        MFP_ADDR(GPIO68, 0x0658),
-        MFP_ADDR(GPIO69, 0x0654),
-        MFP_ADDR(GPIO70, 0x0660),
-        MFP_ADDR(GPIO71, 0x0668),
-        MFP_ADDR(GPIO72, 0x0664),
-        MFP_ADDR(GPIO73, 0x0650),
-        MFP_ADDR(GPIO74, 0x066c),
-        MFP_ADDR(GPIO75, 0x064c),
-        MFP_ADDR(GPIO76, 0x0670),
-        MFP_ADDR(GPIO77, 0x0678),
-        MFP_ADDR(GPIO78, 0x067c),
-        MFP_ADDR(GPIO79, 0x0694),
-        MFP_ADDR(GPIO80, 0x069c),
-        MFP_ADDR(GPIO81, 0x06a0),
-        MFP_ADDR(GPIO82, 0x06a4),
-        MFP_ADDR(GPIO83, 0x0698),
-        MFP_ADDR(GPIO84, 0x06bc),
-        MFP_ADDR(GPIO85, 0x06b4),
-        MFP_ADDR(GPIO86, 0x06b0),
-        MFP_ADDR(GPIO87, 0x06c0),
-        MFP_ADDR(GPIO88, 0x06c4),
-        MFP_ADDR(GPIO89, 0x06ac),
-        MFP_ADDR(GPIO90, 0x0680),
-        MFP_ADDR(GPIO91, 0x0684),
-        MFP_ADDR(GPIO92, 0x0688),
-        MFP_ADDR(GPIO93, 0x0690),
-        MFP_ADDR(GPIO94, 0x068c),
-        MFP_ADDR(GPIO95, 0x06a8),
-        MFP_ADDR(GPIO96, 0x06b8),
-        MFP_ADDR(GPIO97, 0x0410),
-        MFP_ADDR(GPIO98, 0x0418),
-        MFP_ADDR(GPIO99, 0x041c),
-        MFP_ADDR(GPIO100, 0x0414),
-        MFP_ADDR(GPIO101, 0x0408),
-        MFP_ADDR(GPIO102, 0x0324),
-        MFP_ADDR(GPIO103, 0x040c),
-        MFP_ADDR(GPIO104, 0x0400),
-        MFP_ADDR(GPIO105, 0x0328),
-        MFP_ADDR(GPIO106, 0x0404),
-        MFP_ADDR(GPIO159, 0x0524),
-        MFP_ADDR(GPIO163, 0x0534),
-        MFP_ADDR(GPIO167, 0x0544),
-        MFP_ADDR(GPIO168, 0x0548),
-        MFP_ADDR(GPIO169, 0x054c),
-        MFP_ADDR(GPIO170, 0x0550),
-        MFP_ADDR(GPIO171, 0x0554),
-        MFP_ADDR(GPIO172, 0x0558),
-        MFP_ADDR(GPIO173, 0x055c),
-        MFP_ADDR(nXCVREN, 0x0204),
-        MFP_ADDR(DF_CLE_nOE, 0x020c),
-        MFP_ADDR(DF_nADV1_ALE, 0x0218),
-        MFP_ADDR(DF_SCLK_E, 0x0214),
-        MFP_ADDR(DF_SCLK_S, 0x0210),
-        MFP_ADDR(nBE0, 0x021c),
-        MFP_ADDR(nBE1, 0x0220),
-        MFP_ADDR(DF_nADV2_ALE, 0x0224),
-        MFP_ADDR(DF_INT_RnB, 0x0228),
-        MFP_ADDR(DF_nCS0, 0x022c),
-        MFP_ADDR(DF_nCS1, 0x0230),
-        MFP_ADDR(nLUA, 0x0254),
-        MFP_ADDR(nLLA, 0x0258),
-        MFP_ADDR(DF_nWE, 0x0234),
-        MFP_ADDR(DF_nRE_nOE, 0x0238),
-        MFP_ADDR(DF_ADDR0, 0x024c),
-        MFP_ADDR(DF_ADDR1, 0x0250),
-        MFP_ADDR(DF_ADDR2, 0x025c),
-        MFP_ADDR(DF_ADDR3, 0x0260),
-        MFP_ADDR(DF_IO0, 0x023c),
-        MFP_ADDR(DF_IO1, 0x0240),
-        MFP_ADDR(DF_IO2, 0x0244),
-        MFP_ADDR(DF_IO3, 0x0248),
-        MFP_ADDR(DF_IO4, 0x0264),
-        MFP_ADDR(DF_IO5, 0x0268),
-        MFP_ADDR(DF_IO6, 0x026c),
-        MFP_ADDR(DF_IO7, 0x0270),
-        MFP_ADDR(DF_IO8, 0x0274),
-        MFP_ADDR(DF_IO9, 0x0278),
-        MFP_ADDR(DF_IO10, 0x027c),
-        MFP_ADDR(DF_IO11, 0x0280),
-        MFP_ADDR(DF_IO12, 0x0284),
-        MFP_ADDR(DF_IO13, 0x0288),
-        MFP_ADDR(DF_IO14, 0x028c),
-        MFP_ADDR(DF_IO15, 0x0290),
-        MFP_ADDR(GSIM_UIO, 0x0314),
-        MFP_ADDR(GSIM_UCLK, 0x0318),
-        MFP_ADDR(GSIM_UDET, 0x031c),
-        MFP_ADDR(GSIM_nURST, 0x0320),
-        MFP_ADDR(PMIC_INT, 0x06c8),
-        MFP_ADDR(RDY, 0x0200),
-        MFP_ADDR_END,
-};
-static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops);
-static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
-static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1);
-static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1);
-static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1);
-static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
-static DEFINE_PXA3_CKEN(pxa95x_gpio, GPIO, 13000000, 0);
-static struct clk_lookup pxa95x_clkregs[] = {
-        INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
-        /* Power I2C clock is always on */
-        INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
-        INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
-        INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
-        INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
-        INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL),
-        INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"),
-        INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL),
-        INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL),
-        INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL),
-        INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL),
-        INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL),
-        INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
-        INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
-        INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
-        INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
-};
-void __init pxa95x_init_irq(void)
-{
-        pxa_init_irq(96, NULL);
-}
-/*
- * device registration specific to PXA93x.
- */
-void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
-{
-        pxa_register_device(&pxa3xx_device_i2c_power, info);
-}
-static struct platform_device *devices[] __initdata = {
-        &pxa_device_gpio,
-        &sa1100_device_rtc,
-        &pxa_device_rtc,
-        &pxa27x_device_ssp1,
-        &pxa27x_device_ssp2,
-        &pxa27x_device_ssp3,
-        &pxa3xx_device_ssp4,
-        &pxa27x_device_pwm0,
-        &pxa27x_device_pwm1,
-};
-static int __init pxa95x_init(void)
-{
-        int ret = 0, i;
-        if (cpu_is_pxa95x()) {
-                mfp_init_base(io_p2v(MFPR_BASE));
-                mfp_init_addr(pxa95x_mfp_addr_map);
-                reset_status = ARSR;
-                /*
-                 * clear RDH bit every time after reset
-                 *
-                 * Note: the last 3 bits DxS are write-1-to-clear so carefully
-                 * preserve them here in case they will be referenced later
-                 */
-                ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
-                clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs));
-                if ((ret = pxa_init_dma(IRQ_DMA, 32)))
-                        return ret;
-                register_syscore_ops(&pxa_irq_syscore_ops);
-                register_syscore_ops(&pxa3xx_clock_syscore_ops);
-                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
-        }
-        return ret;
-}
-postcore_initcall(pxa95x_init);
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
deleted file mode 100644
index 5aded5e6148f..000000000000
--- a/arch/arm/mach-pxa/saarb.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  linux/arch/arm/mach-pxa/saarb.c
- *
- *  Support for the Marvell Handheld Platform (aka SAARB)
- *
- *  Copyright (C) 2007-2010 Marvell International Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  publishhed by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/i2c/pxa-i2c.h>
-#include <linux/mfd/88pm860x.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/mfp.h>
-#include <mach/mfp-pxa930.h>
-#include <mach/pxa95x.h>
-#include "generic.h"
-#define SAARB_NR_IRQS   (IRQ_BOARD_START + 40)
-static struct pm860x_touch_pdata saarb_touch = {
-        .gpadc_prebias  = 1,
-        .slot_cycle     = 1,
-        .tsi_prebias    = 6,
-        .pen_prebias    = 16,
-        .pen_prechg     = 2,
-        .res_x          = 300,
-};
-static struct pm860x_backlight_pdata saarb_backlight[] = {
-        {
-                .id     = PM8606_ID_BACKLIGHT,
-                .iset   = PM8606_WLED_CURRENT(24),
-                .flags  = PM8606_BACKLIGHT1,
-        },
-        {},
-};
-static struct pm860x_led_pdata saarb_led[] = {
-        {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED1_RED,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED1_GREEN,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED1_BLUE,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED2_RED,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED2_GREEN,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED2_BLUE,
-        },
-};
-static struct pm860x_platform_data saarb_pm8607_info = {
-        .touch          = &saarb_touch,
-        .backlight      = &saarb_backlight[0],
-        .led            = &saarb_led[0],
-        .companion_addr = 0x10,
-        .irq_mode       = 0,
-        .irq_base       = IRQ_BOARD_START,
-        .i2c_port       = GI2C_PORT,
-};
-static struct i2c_board_info saarb_i2c_info[] = {
-        {
-                .type           = "88PM860x",
-                .addr           = 0x34,
-                .platform_data  = &saarb_pm8607_info,
-                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
-        },
-};
-static void __init saarb_init(void)
-{
-        pxa_set_ffuart_info(NULL);
-        pxa_set_i2c_info(NULL);
-        i2c_register_board_info(0, ARRAY_AND_SIZE(saarb_i2c_info));
-}
-MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
-        .atag_offset    = 0x100,
-        .map_io         = pxa3xx_map_io,
-        .nr_irqs        = SAARB_NR_IRQS,
-        .init_irq       = pxa95x_init_irq,
-        .handle_irq     = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
-        .init_machine   = saarb_init,
-        .restart        = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
deleted file mode 100644
index f7d9305cfd77..000000000000
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- *  linux/arch/arm/mach-pxa/tavorevb3.c
- *
- *  Support for the Marvell EVB3 Development Platform.
- *
- *  Copyright:  (C) Copyright 2008-2010 Marvell International Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  publishhed by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/i2c/pxa-i2c.h>
-#include <linux/gpio.h>
-#include <linux/mfd/88pm860x.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/pxa930.h>
-#include "devices.h"
-#include "generic.h"
-#define TAVOREVB3_NR_IRQS       (IRQ_BOARD_START + 24)
-static mfp_cfg_t evb3_mfp_cfg[] __initdata = {
-        /* UART */
-        GPIO53_UART1_TXD,
-        GPIO54_UART1_RXD,
-        /* PMIC */
-        PMIC_INT_GPIO83,
-};
-#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
-static struct pm860x_touch_pdata evb3_touch = {
-        .gpadc_prebias  = 1,
-        .slot_cycle     = 1,
-        .tsi_prebias    = 6,
-        .pen_prebias    = 16,
-        .pen_prechg     = 2,
-        .res_x          = 300,
-};
-static struct pm860x_backlight_pdata evb3_backlight[] = {
-        {
-                .id     = PM8606_ID_BACKLIGHT,
-                .iset   = PM8606_WLED_CURRENT(24),
-                .flags  = PM8606_BACKLIGHT1,
-        },
-        {},
-};
-static struct pm860x_led_pdata evb3_led[] = {
-        {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED1_RED,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED1_GREEN,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED1_BLUE,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED2_RED,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED2_GREEN,
-        }, {
-                .id     = PM8606_ID_LED,
-                .iset   = PM8606_LED_CURRENT(12),
-                .flags  = PM8606_LED2_BLUE,
-        },
-};
-static struct pm860x_platform_data evb3_pm8607_info = {
-        .touch                          = &evb3_touch,
-        .backlight                      = &evb3_backlight[0],
-        .led                            = &evb3_led[0],
-        .companion_addr                 = 0x10,
-        .irq_mode                       = 0,
-        .irq_base                       = IRQ_BOARD_START,
-        .i2c_port                       = GI2C_PORT,
-};
-static struct i2c_board_info evb3_i2c_info[] = {
-        {
-                .type           = "88PM860x",
-                .addr           = 0x34,
-                .platform_data  = &evb3_pm8607_info,
-                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
-        },
-};
-static void __init evb3_init_i2c(void)
-{
-        pxa_set_i2c_info(NULL);
-        i2c_register_board_info(0, ARRAY_AND_SIZE(evb3_i2c_info));
-}
-#else
-static inline void evb3_init_i2c(void) {}
-#endif
-static void __init evb3_init(void)
-{
-        /* initialize MFP configurations */
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(evb3_mfp_cfg));
-        pxa_set_ffuart_info(NULL);
-        evb3_init_i2c();
-}
-MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
-        .atag_offset    = 0x100,
-        .map_io         = pxa3xx_map_io,
-        .nr_irqs        = TAVOREVB3_NR_IRQS,
-        .init_irq       = pxa3xx_init_irq,
-        .handle_irq       = pxa3xx_handle_irq,
-        .timer          = &pxa_timer,
-        .init_machine   = evb3_init,
-        .restart        = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index d3b3cd216d64..28511d43637a 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -467,6 +467,7 @@ static void __init realview_eb_init(void)
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(realview_smp_ops),
        .fixup          = realview_fixup,
        .map_io         = realview_eb_map_io,
        .init_early     = realview_init_early,
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 2b6cb5f29c2d..25df14a9e268 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -400,11 +400,12 @@ config MACH_MINI2440
        bool "MINI2440 development board"
        select EEPROM_AT24
        select LEDS_CLASS
-        select LEDS_TRIGGER
+        select LEDS_TRIGGERS
        select LEDS_TRIGGER_BACKLIGHT
        select NEW_LEDS
        select S3C_DEV_NAND
        select S3C_DEV_USB_HOST
+        select S3C_SETUP_CAMIF
        help
          Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
          available via various sources. It can come with a 3.5" or 7" touch LCD.
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 4407b1730539..04b87ec92537 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -161,6 +161,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
        CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
+        CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
 };
 static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 7f689ce1be61..bdaba59b42dc 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -158,12 +158,6 @@ static struct clk init_clocks_off[] = {
                .devname        = "s3c2410-spi.0",
                .parent         = &clk_p,
                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_SPI0,
-        }, {
-                .name           = "spi",
-                .devname        = "s3c2410-spi.1",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
                .ctrlbit        = S3C2443_PCLKCON_SPI1,
        }
 };
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
index 6e7dc9d0cf0e..eecea2a50f8f 100644
--- a/arch/arm/mach-s3c24xx/include/mach/bast-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
@@ -74,7 +74,7 @@
 /* 0xE0000000 contains the IO space that is split by speed and
- * wether the access is for 8 or 16bit IO... this ensures that
+ * whether the access is for 8 or 16bit IO... this ensures that
 * the correct access is made
 *
 * 0x10000000 of space, partitioned as so:
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index ee99fd56c043..6b72d5a4b377 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -88,7 +88,7 @@ enum s3c2410_dma_state {
 *
 * This represents the state of the DMA engine, wrt to the loaded / running
 * transfers. Since we don't have any way of knowing exactly the state of
- * the DMA transfers, we need to know the state to make decisions on wether
+ * the DMA transfers, we need to know the state to make decisions on whether
 * we can
 *
 * S3C2410_DMA_NONE
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
index 99612fcc4eb2..28376e56dd3b 100644
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
@@ -51,7 +51,7 @@
 #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
 /* 0xE0000000 contains the IO space that is split by speed and
- * wether the access is for 8 or 16bit IO... this ensures that
+ * whether the access is for 8 or 16bit IO... this ensures that
 * the correct access is made
 *
 * 0x10000000 of space, partitioned as so:
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 4a963467b7ee..973b87ca87f4 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -521,7 +521,6 @@ static struct platform_device *gta02_devices[] __initdata = {
        &gta02_nor_flash,
        &s3c24xx_pwm_device,
        &s3c_device_iis,
-        &samsung_asoc_dma,
        &s3c_device_i2c0,
        &gta02_dfbmcs320_device,
        &gta02_buttons_device,
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 63aaf076f611..b23dd1b106e8 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -632,7 +632,6 @@ static struct platform_device *h1940_devices[] __initdata = {
        &s3c_device_wdt,
        &s3c_device_i2c0,
        &s3c_device_iis,
-        &samsung_asoc_dma,
        &s3c_device_usbgadget,
        &h1940_device_leds,
        &h1940_device_bluetooth,
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 393c0f1ac11a..a31d5b83e5f7 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -519,7 +519,6 @@ static struct platform_device *mini2440_devices[] __initdata = {
        &s3c_device_iis,
        &uda1340_codec,
        &mini2440_audio,
-        &samsung_asoc_dma,
 };
 static void __init mini2440_map_io(void)
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 379fde521d37..0606f2faaa5c 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -712,7 +712,6 @@ static struct platform_device *rx1950_devices[] __initdata = {
        &s3c_device_wdt,
        &s3c_device_i2c0,
        &s3c_device_iis,
-        &samsung_asoc_dma,
        &s3c_device_usbgadget,
        &s3c_device_rtc,
        &s3c_device_nand,
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 60627e63a254..724755f0b0f5 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -121,7 +121,7 @@ void s3c_pm_configure_extint(void)
        int pin;
        /* for each of the external interrupts (EINT0..EINT15) we
-         * need to check wether it is an external interrupt source,
+         * need to check whether it is an external interrupt source,
         * and then configure it as an input if it is not
        */
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 63e7ae3ee9e6..131c86284711 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -294,6 +294,7 @@ config MACH_WLF_CRAGG_6410
        select S3C64XX_SETUP_SDHCI
        select S3C64XX_SETUP_SPI
        select S3C64XX_SETUP_USB_PHY
+        select S3C_DEV_FB
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC1
        select S3C_DEV_HSMMC2
@@ -304,6 +305,7 @@ config MACH_WLF_CRAGG_6410
        select S3C_DEV_WDT
        select SAMSUNG_DEV_ADC
        select SAMSUNG_DEV_KEYPAD
+        select SAMSUNG_DEV_PWM
        select SAMSUNG_GPIO_EXTRA128
        help
          Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 28041e83dc82..1a6f85777449 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -138,11 +138,7 @@ static struct clk init_clocks_off[] = {
                .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
        }, {
                .name           = "i2c",
-#ifdef CONFIG_S3C_DEV_I2C1
                .devname        = "s3c2440-i2c.0",
-#else
-                .devname        = "s3c2440-i2c",
-#endif
                .parent         = &clk_p,
                .enable         = s3c64xx_pclk_ctrl,
                .ctrlbit        = S3C_CLKCON_PCLK_IIC,
@@ -319,10 +315,6 @@ static struct clk init_clocks_off[] = {
                .enable         = s3c64xx_sclk_ctrl,
                .ctrlbit        = S3C_CLKCON_SCLK_MFC,
        }, {
-                .name           = "cam",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_CAM,
-        }, {
                .name           = "sclk_jpeg",
                .enable         = s3c64xx_sclk_ctrl,
                .ctrlbit        = S3C_CLKCON_SCLK_JPEG,
@@ -681,15 +673,6 @@ static struct clksrc_sources clkset_audio2 = {
        .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
 };
-static struct clk *clkset_camif_list[] = {
-        &clk_h2,
-};
-static struct clksrc_sources clkset_camif = {
-        .sources        = clkset_camif_list,
-        .nr_sources     = ARRAY_SIZE(clkset_camif_list),
-};
 static struct clksrc_clk clksrcs[] = {
        {
                .clk    = {
@@ -744,10 +727,9 @@ static struct clksrc_clk clksrcs[] = {
                        .name           = "camera",
                        .ctrlbit        = S3C_CLKCON_SCLK_CAM,
                        .enable         = s3c64xx_sclk_ctrl,
+                        .parent         = &clk_h2,
                },
                .reg_div        = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
-                .reg_src        = { .reg = NULL, .shift = 0, .size = 0  },
-                .sources        = &clkset_camif,
        },
 };
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index be746e33e86c..aef303b8997e 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -155,7 +155,6 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
        /* initialise the io descriptors we need for initialisation */
        iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
        iotable_init(mach_desc, size);
-        init_consistent_dma_size(SZ_8M);
        /* detect cpu id */
        s3c64xx_init_cpu();
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 4e3fe57674c8..c6d8dba90623 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -20,6 +20,8 @@
 #include <linux/regulator/machine.h>
+#include <sound/wm0010.h>
+#include <sound/wm2200.h>
 #include <sound/wm5100.h>
 #include <sound/wm8996.h>
 #include <sound/wm8962.h>
@@ -33,14 +35,34 @@ static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
        .line = S3C64XX_GPC(3),
 };
+static struct wm0010_pdata wm0010_pdata = {
+        .gpio_reset = S3C64XX_GPN(6),
+        .reset_active_high = 1, /* Active high for Glenfarclas Rev 2 */
+};
 static struct spi_board_info wm1253_devs[] = {
        [0] = {
                .modalias       = "wm0010",
+                .max_speed_hz   = 26 * 1000 * 1000,
                .bus_num        = 0,
                .chip_select    = 0,
                .mode           = SPI_MODE_0,
                .irq            = S3C_EINT(5),
                .controller_data = &wm0010_spi_csinfo,
+                .platform_data = &wm0010_pdata,
+        },
+};
+static struct spi_board_info balblair_devs[] = {
+        [0] = {
+                .modalias       = "wm0010",
+                .max_speed_hz   = 26 * 1000 * 1000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+                .irq            = S3C_EINT(4),
+                .controller_data = &wm0010_spi_csinfo,
+                .platform_data = &wm0010_pdata,
        },
 };
@@ -166,12 +188,13 @@ static struct regulator_init_data wm8994_ldo2 = {
 static struct wm8994_pdata wm8994_pdata = {
        .gpio_base = CODEC_GPIO_BASE,
+        .micb2_delay = 150,
        .gpio_defaults = {
                0x3,          /* IRQ out, active high, CMOS */
        },
        .ldo = {
-                 { .init_data = &wm8994_ldo1, },
+                 { .enable = S3C64XX_GPN(6), .init_data = &wm8994_ldo1, },
-                 { .init_data = &wm8994_ldo2, },
+                 { .enable = S3C64XX_GPN(4), .init_data = &wm8994_ldo2, },
        },
 };
@@ -182,7 +205,7 @@ static const struct i2c_board_info wm1277_devs[] = {
        },
 };
-static struct arizona_pdata wm5102_pdata = {
+static struct arizona_pdata wm5102_reva_pdata = {
        .ldoena = S3C64XX_GPN(7),
        .gpio_base = CODEC_GPIO_BASE,
        .irq_active_high = true,
@@ -193,64 +216,131 @@ static struct arizona_pdata wm5102_pdata = {
        },
 };
-static struct s3c64xx_spi_csinfo wm5102_spi_csinfo = {
+static struct s3c64xx_spi_csinfo codec_spi_csinfo = {
        .line = S3C64XX_GPN(5),
 };
+static struct spi_board_info wm5102_reva_spi_devs[] = {
+        [0] = {
+                .modalias       = "wm5102",
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+                .chip_select    = 1,
+                .mode           = SPI_MODE_0,
+                .irq            = GLENFARCLAS_PMIC_IRQ_BASE +
+                                  WM831X_IRQ_GPIO_2,
+                .controller_data = &codec_spi_csinfo,
+                .platform_data = &wm5102_reva_pdata,
+        },
+};
+static struct arizona_pdata wm5102_pdata = {
+        .ldoena = S3C64XX_GPN(7),
+        .gpio_base = CODEC_GPIO_BASE,
+        .irq_active_high = true,
+        .micd_pol_gpio = CODEC_GPIO_BASE + 2,
+        .gpio_defaults = {
+                [2] = 0x10000, /* AIF3TXLRCLK */
+                [3] = 0x4,     /* OPCLK */
+        },
+};
 static struct spi_board_info wm5102_spi_devs[] = {
        [0] = {
                .modalias       = "wm5102",
                .max_speed_hz   = 10 * 1000 * 1000,
                .bus_num        = 0,
-                .chip_select    = 0,
+                .chip_select    = 1,
                .mode           = SPI_MODE_0,
                .irq            = GLENFARCLAS_PMIC_IRQ_BASE +
                                  WM831X_IRQ_GPIO_2,
-                .controller_data = &wm5102_spi_csinfo,
+                .controller_data = &codec_spi_csinfo,
                .platform_data = &wm5102_pdata,
        },
 };
+static struct spi_board_info wm5110_spi_devs[] = {
+        [0] = {
+                .modalias       = "wm5110",
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+                .chip_select    = 1,
+                .mode           = SPI_MODE_0,
+                .irq            = GLENFARCLAS_PMIC_IRQ_BASE +
+                                  WM831X_IRQ_GPIO_2,
+                .controller_data = &codec_spi_csinfo,
+                .platform_data = &wm5102_reva_pdata,
+        },
+};
 static const struct i2c_board_info wm6230_i2c_devs[] = {
        { I2C_BOARD_INFO("wm9081", 0x6c),
          .platform_data = &wm9081_pdata, },
 };
+static struct wm2200_pdata wm2200_pdata = {
+        .ldo_ena = S3C64XX_GPN(7),
+        .gpio_defaults = {
+                [2] = 0x0005,  /* GPIO3 24.576MHz output clock */
+        },
+};
+static const struct i2c_board_info wm2200_i2c[] = {
+        { I2C_BOARD_INFO("wm2200", 0x3a),
+          .platform_data = &wm2200_pdata, },
+};
 static __devinitdata const struct {
        u8 id;
+        u8 rev;
        const char *name;
        const struct i2c_board_info *i2c_devs;
        int num_i2c_devs;
        const struct spi_board_info *spi_devs;
        int num_spi_devs;
 } gf_mods[] = {
-        { .id = 0x01, .name = "1250-EV1 Springbank" },
+        { .id = 0x01, .rev = 0xff, .name = "1250-EV1 Springbank" },
-        { .id = 0x02, .name = "1251-EV1 Jura" },
+        { .id = 0x02, .rev = 0xff, .name = "1251-EV1 Jura" },
-        { .id = 0x03, .name = "1252-EV1 Glenlivet" },
+        { .id = 0x03, .rev = 0xff, .name = "1252-EV1 Glenlivet" },
-        { .id = 0x11, .name = "6249-EV2 Glenfarclas", },
+        { .id = 0x06, .rev = 0xff, .name = "WM8997-6721-CS96-EV1 Lapraoig" },
-        { .id = 0x14, .name = "6271-EV1 Lochnagar" },
+        { .id = 0x07, .rev = 0xff, .name = "WM5110-6271 Deanston",
-        { .id = 0x15, .name = "6320-EV1 Bells",
+          .spi_devs = wm5110_spi_devs,
+          .num_spi_devs = ARRAY_SIZE(wm5110_spi_devs) },
+        { .id = 0x08, .rev = 0xff, .name = "WM8903-6102 Tamdhu" },
+        { .id = 0x09, .rev = 0xff, .name = "WM1811A-6305 Adelphi" },
+        { .id = 0x0a, .rev = 0xff, .name = "WM8996-6272 Blackadder" },
+        { .id = 0x0b, .rev = 0xff, .name = "WM8994-6235 Benromach" },
+        { .id = 0x11, .rev = 0xff, .name = "6249-EV2 Glenfarclas", },
+        { .id = 0x14, .rev = 0xff, .name = "6271-EV1 Lochnagar" },
+        { .id = 0x15, .rev = 0xff, .name = "6320-EV1 Bells",
          .i2c_devs = wm6230_i2c_devs,
          .num_i2c_devs = ARRAY_SIZE(wm6230_i2c_devs) },
-        { .id = 0x21, .name = "1275-EV1 Mortlach" },
+        { .id = 0x21, .rev = 0xff, .name = "1275-EV1 Mortlach" },
-        { .id = 0x25, .name = "1274-EV1 Glencadam" },
+        { .id = 0x25, .rev = 0xff, .name = "1274-EV1 Glencadam" },
-        { .id = 0x31, .name = "1253-EV1 Tomatin",
+        { .id = 0x31, .rev = 0xff, .name = "1253-EV1 Tomatin",
          .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
-        { .id = 0x32, .name = "XXXX-EV1 Caol Illa" },
+        { .id = 0x32, .rev = 0xff, .name = "XXXX-EV1 Caol Illa" },
-        { .id = 0x33, .name = "XXXX-EV1 Oban" },
+        { .id = 0x33, .rev = 0xff, .name = "XXXX-EV1 Oban" },
-        { .id = 0x34, .name = "WM0010-6320-CS42 Balblair" },
+        { .id = 0x34, .rev = 0xff, .name = "WM0010-6320-CS42 Balblair",
-        { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
+          .spi_devs = balblair_devs,
+          .num_spi_devs = ARRAY_SIZE(balblair_devs) },
+        { .id = 0x39, .rev = 0xff, .name = "1254-EV1 Dallas Dhu",
          .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
-        { .id = 0x3a, .name = "1259-EV1 Tobermory",
+        { .id = 0x3a, .rev = 0xff, .name = "1259-EV1 Tobermory",
          .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
-        { .id = 0x3b, .name = "1255-EV1 Kilchoman",
+        { .id = 0x3b, .rev = 0xff, .name = "1255-EV1 Kilchoman",
          .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
-        { .id = 0x3c, .name = "1273-EV1 Longmorn" },
+        { .id = 0x3c, .rev = 0xff, .name = "1273-EV1 Longmorn" },
-        { .id = 0x3d, .name = "1277-EV1 Littlemill",
+        { .id = 0x3d, .rev = 0xff, .name = "1277-EV1 Littlemill",
          .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
-        { .id = 0x3e, .name = "WM5102-6271-EV1-CS127 Amrut",
+        { .id = 0x3e, .rev = 0, .name = "WM5102-6271-EV1-CS127 Amrut",
+          .spi_devs = wm5102_reva_spi_devs,
+          .num_spi_devs = ARRAY_SIZE(wm5102_reva_spi_devs) },
+        { .id = 0x3e, .rev = -1, .name = "WM5102-6271-EV1-CS127 Amrut",
          .spi_devs = wm5102_spi_devs,
          .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs) },
+        { .id = 0x3f, .rev = -1, .name = "WM2200-6271-CS90-M-REV1",
+          .i2c_devs = wm2200_i2c, .num_i2c_devs = ARRAY_SIZE(wm2200_i2c) },
 };
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
@@ -267,7 +357,8 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
        id = (ret & 0xfe) >> 2;
        rev = ret & 0x3;
        for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
-                if (id == gf_mods[i].id)
+                if (id == gf_mods[i].id && (gf_mods[i].rev == 0xff ||
+                                            rev == gf_mods[i].rev))
                        break;
        if (i < ARRAY_SIZE(gf_mods)) {
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 13b7eaa45fd0..cdde249166b5 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -287,16 +287,21 @@ static struct platform_device littlemill_device = {
        .id             = -1,
 };
-static struct platform_device bells_wm5102_device = {
+static struct platform_device bells_wm2200_device = {
        .name           = "bells",
        .id             = 0,
 };
-static struct platform_device bells_wm5110_device = {
+static struct platform_device bells_wm5102_device = {
        .name           = "bells",
        .id             = 1,
 };
+static struct platform_device bells_wm5110_device = {
+        .name           = "bells",
+        .id             = 2,
+};
 static struct regulator_consumer_supply wallvdd_consumers[] = {
        REGULATOR_SUPPLY("SPKVDD", "1-001a"),
        REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
@@ -304,6 +309,13 @@ static struct regulator_consumer_supply wallvdd_consumers[] = {
        REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
        REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
+        REGULATOR_SUPPLY("SPKVDDL", "spi0.1"),
+        REGULATOR_SUPPLY("SPKVDDR", "spi0.1"),
+        REGULATOR_SUPPLY("SPKVDDL", "wm5102-codec"),
+        REGULATOR_SUPPLY("SPKVDDR", "wm5102-codec"),
+        REGULATOR_SUPPLY("SPKVDDL", "wm5110-codec"),
+        REGULATOR_SUPPLY("SPKVDDR", "wm5110-codec"),
        REGULATOR_SUPPLY("DC1VDD", "0-0034"),
        REGULATOR_SUPPLY("DC2VDD", "0-0034"),
        REGULATOR_SUPPLY("DC3VDD", "0-0034"),
@@ -321,6 +333,16 @@ static struct regulator_consumer_supply wallvdd_consumers[] = {
        REGULATOR_SUPPLY("DC1VDD", "1-0034"),
        REGULATOR_SUPPLY("DC2VDD", "1-0034"),
        REGULATOR_SUPPLY("DC3VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO1VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO2VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO4VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO5VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO6VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO7VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO8VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO9VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO10VDD", "1-0034"),
+        REGULATOR_SUPPLY("LDO11VDD", "1-0034"),
 };
 static struct regulator_init_data wallvdd_data = {
@@ -357,7 +379,6 @@ static struct platform_device *crag6410_devices[] __initdata = {
        &s3c_device_timer[0],
        &s3c64xx_device_iis0,
        &s3c64xx_device_iis1,
-        &samsung_asoc_dma,
        &samsung_device_keypad,
        &crag6410_gpio_keydev,
        &crag6410_dm9k_device,
@@ -369,6 +390,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
        &tobermory_device,
        &littlemill_device,
        &lowland_device,
+        &bells_wm2200_device,
        &bells_wm5102_device,
        &bells_wm5110_device,
        &wallvdd_device,
@@ -597,6 +619,7 @@ static struct s3c2410_platform_i2c i2c0_pdata = {
 static struct regulator_consumer_supply pvdd_1v2_consumers[] __devinitdata = {
        REGULATOR_SUPPLY("DCVDD", "spi0.0"),
        REGULATOR_SUPPLY("AVDD", "spi0.0"),
+        REGULATOR_SUPPLY("AVDD", "spi0.1"),
 };
 static struct regulator_init_data pvdd_1v2 __devinitdata = {
@@ -621,6 +644,24 @@ static struct regulator_consumer_supply pvdd_1v8_consumers[] __devinitdata = {
        REGULATOR_SUPPLY("DCVDD", "1-001a"),
        REGULATOR_SUPPLY("AVDD", "1-001a"),
        REGULATOR_SUPPLY("DBVDD", "spi0.0"),
+        REGULATOR_SUPPLY("DBVDD", "1-003a"),
+        REGULATOR_SUPPLY("LDOVDD", "1-003a"),
+        REGULATOR_SUPPLY("CPVDD", "1-003a"),
+        REGULATOR_SUPPLY("AVDD", "1-003a"),
+        REGULATOR_SUPPLY("DBVDD1", "spi0.1"),
+        REGULATOR_SUPPLY("DBVDD2", "spi0.1"),
+        REGULATOR_SUPPLY("DBVDD3", "spi0.1"),
+        REGULATOR_SUPPLY("LDOVDD", "spi0.1"),
+        REGULATOR_SUPPLY("CPVDD", "spi0.1"),
+        REGULATOR_SUPPLY("DBVDD2", "wm5102-codec"),
+        REGULATOR_SUPPLY("DBVDD3", "wm5102-codec"),
+        REGULATOR_SUPPLY("CPVDD", "wm5102-codec"),
+        REGULATOR_SUPPLY("DBVDD2", "wm5110-codec"),
+        REGULATOR_SUPPLY("DBVDD3", "wm5110-codec"),
+        REGULATOR_SUPPLY("CPVDD", "wm5110-codec"),
 };
 static struct regulator_init_data pvdd_1v8 __devinitdata = {
@@ -685,6 +726,7 @@ static struct i2c_board_info i2c_devs1[] __devinitdata = {
          .irq = S3C_EINT(0),
          .platform_data = &glenfarclas_pmic_pdata },
+        { I2C_BOARD_INFO("wlf-gf-module", 0x20) },
        { I2C_BOARD_INFO("wlf-gf-module", 0x22) },
        { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
        { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
@@ -810,7 +852,7 @@ static void __init crag6410_machine_init(void)
        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
        samsung_keypad_set_platdata(&crag6410_keypad_data);
-        s3c64xx_spi0_set_platdata(NULL, 0, 1);
+        s3c64xx_spi0_set_platdata(NULL, 0, 2);
        platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index da1a771a29e9..574a9eef588d 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -275,7 +275,6 @@ static struct platform_device *smdk6410_devices[] __initdata = {
        &s3c_device_fb,
        &s3c_device_ohci,
        &s3c_device_usb_hsotg,
-        &samsung_asoc_dma,
        &s3c64xx_device_iisv4,
        &samsung_device_keypad,
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 111e404a81fd..8ae5800e807f 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -187,7 +187,6 @@ void __init s5p6440_map_io(void)
        s5p6440_default_sdhci2();
        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
-        init_consistent_dma_size(SZ_8M);
 }
 void __init s5p6450_map_io(void)
@@ -202,7 +201,6 @@ void __init s5p6450_map_io(void)
        s5p6450_default_sdhci2();
        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
-        init_consistent_dma_size(SZ_8M);
 }
 /*
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 96ea1fe0ec94..1af823558c60 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -165,7 +165,6 @@ static struct platform_device *smdk6440_devices[] __initdata = {
        &s3c_device_i2c1,
        &s3c_device_ts,
        &s3c_device_wdt,
-        &samsung_asoc_dma,
        &s5p6440_device_iis,
        &s3c_device_fb,
        &smdk6440_lcd_lte480wv,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 12748b6eaa7b..62526ccf6b70 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -183,7 +183,6 @@ static struct platform_device *smdk6450_devices[] __initdata = {
        &s3c_device_i2c1,
        &s3c_device_ts,
        &s3c_device_wdt,
-        &samsung_asoc_dma,
        &s5p6450_device_iis0,
        &s3c_device_fb,
        &smdk6450_lcd_lte480wv,
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index dba7384a87bd..9abe95e806ab 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -197,7 +197,6 @@ static struct platform_device *smdkc100_devices[] __initdata = {
        &s3c_device_ts,
        &s3c_device_wdt,
        &smdkc100_lcd_powerdev,
-        &samsung_asoc_dma,
        &s5pc100_device_iis0,
        &samsung_device_keypad,
        &s5pc100_device_ac97,
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index a0c50efe8145..9dfe93e2624d 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -169,8 +169,6 @@ void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
 void __init s5pv210_map_io(void)
 {
-        init_consistent_dma_size(14 << 20);
        /* initialise device information early */
        s5pv210_default_sdhci0();
        s5pv210_default_sdhci1();
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 55e1dba4ffde..c72b31078c99 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -774,7 +774,6 @@ static void __init goni_pmic_init(void)
 /* MoviNAND */
 static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
        .max_width              = 4,
-        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index d9c99fcc1aa7..f1f3bd37ecda 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -85,7 +85,6 @@ static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = {
 };
 static struct platform_device *smdkc110_devices[] __initdata = {
-        &samsung_asoc_dma,
        &s5pv210_device_iis0,
        &s5pv210_device_ac97,
        &s5pv210_device_spdif,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 4cdb5bb7bbcf..6bc8404bf678 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -234,7 +234,6 @@ static struct platform_device *smdkv210_devices[] __initdata = {
        &s5pv210_device_ac97,
        &s5pv210_device_iis0,
        &s5pv210_device_spdif,
-        &samsung_asoc_dma,
        &samsung_asoc_idma,
        &samsung_device_keypad,
        &smdkv210_dm9000,
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 6a7ad3c2a3fc..9a23739f7026 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -14,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/serial_core.h>
 #include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
@@ -37,7 +38,6 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/irda.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/assabet.h>
 #include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index 038df4894b0f..b2dadf3ea3df 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/tty.h>
@@ -34,7 +35,6 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/sa1111.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/badge4.h>
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index ad0eb08ea077..304bca4a07c0 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/mtd/mtd.h>
@@ -27,7 +28,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/cerf.h>
 #include <linux/platform_data/mfd-mcp-sa11x0.h>
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 170cb6107f68..45f424f5fca6 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/tty.h>
 #include <linux/delay.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
@@ -40,7 +41,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <asm/hardware/scoop.h>
 #include <asm/mach/sharpsl_param.h>
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index 63150e1ffe9e..f17e7382242a 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -17,12 +17,12 @@
 #include <linux/mfd/htc-egpio.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/h3xxx.h>
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index fc106aab7c7e..d005939c41fc 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -18,6 +18,7 @@
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/cpufreq.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/serial_core.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -35,7 +36,6 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index e3084f47027d..35cfc428b4d4 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -17,6 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/tty.h>
 #include <linux/delay.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/ioport.h>
 #include <linux/mtd/mtd.h>
@@ -30,7 +31,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 3048b17e84c5..f69f78fc3ddd 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -4,6 +4,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/tty.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
@@ -18,7 +19,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 41f69d97066f..102e08f7b109 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/root_dev.h>
@@ -24,7 +25,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/hardware.h>
 #include <mach/nanoengine.h>
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 266db873a4e4..88be0474f3d7 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -7,6 +7,7 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/serial_core.h>
@@ -14,7 +15,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 37fe0a0a5369..c51bb63f90fb 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -6,6 +6,7 @@
 #include <linux/kernel.h>
 #include <linux/tty.h>
 #include <linux/ioport.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/io.h>
@@ -18,7 +19,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <asm/mach/serial_sa1100.h>
 #include <mach/irqs.h>
 #include "generic.h"
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index ff6b7b35bca9..6460d25fbb88 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -5,6 +5,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/kernel.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/tty.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -18,7 +19,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/shannon.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 71790e581d93..6d65f65fcb23 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -9,6 +9,7 @@
 #include <linux/proc_fs.h>
 #include <linux/string.h>
 #include <linux/pm.h>
+#include <linux/platform_data/sa11x0-serial.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
@@ -23,7 +24,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <asm/mach/serial_sa1100.h>
 #include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/simpad.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8ae100cc655c..9255546e7bf6 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -2,18 +2,6 @@ if ARCH_SHMOBILE
 comment "SH-Mobile System Type"
-config ARCH_SH7367
-        bool "SH-Mobile G3 (SH7367)"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select CPU_V6
-        select SH_CLK_CPG
-config ARCH_SH7377
-        bool "SH-Mobile G4 (SH7377)"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select CPU_V7
-        select SH_CLK_CPG
 config ARCH_SH7372
        bool "SH-Mobile AP4 (SH7372)"
        select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -41,6 +29,8 @@ config ARCH_R8A7779
        select ARM_GIC
        select CPU_V7
        select SH_CLK_CPG
+        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_OHCI
 config ARCH_EMEV2
        bool "Emma Mobile EV2"
@@ -50,17 +40,6 @@ config ARCH_EMEV2
 comment "SH-Mobile Board Type"
-config MACH_G3EVM
-        bool "G3EVM board"
-        depends on ARCH_SH7367
-        select ARCH_REQUIRE_GPIOLIB
-config MACH_G4EVM
-        bool "G4EVM board"
-        depends on ARCH_SH7377
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 config MACH_AP4EVB
        bool "AP4EVB board"
        depends on ARCH_SH7372
@@ -95,6 +74,7 @@ config MACH_MACKEREL
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select USE_OF
 config MACH_KOTA2
        bool "KOTA2 board"
@@ -146,8 +126,7 @@ menu "Memory configuration"
 config MEMORY_START
        hex "Physical memory start address"
-        default "0x50000000" if MACH_G3EVM
+        default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
-        default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
                                MACH_MACKEREL || MACH_BONITO || \
                                MACH_ARMADILLO800EVA
        default "0x41000000" if MACH_KOTA2
@@ -159,8 +138,6 @@ config MEMORY_START
 config MEMORY_SIZE
        hex "Physical memory size"
-        default "0x08000000" if MACH_G3EVM
-        default "0x08000000" if MACH_G4EVM
        default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
                                MACH_ARMADILLO800EVA
        default "0x1e000000" if MACH_KOTA2
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe2c97c179d1..0b7147928aa3 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,8 +6,6 @@
 obj-y                           := timer.o console.o clock.o
 # CPU objects
-obj-$(CONFIG_ARCH_SH7367)       += setup-sh7367.o clock-sh7367.o intc-sh7367.o
-obj-$(CONFIG_ARCH_SH7377)       += setup-sh7377.o clock-sh7377.o intc-sh7377.o
 obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o clock-sh7372.o intc-sh7372.o
 obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
 obj-$(CONFIG_ARCH_R8A7740)      += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
@@ -23,16 +21,12 @@ smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o
 # Pinmux setup
 pfc-y                           :=
-pfc-$(CONFIG_ARCH_SH7367)       += pfc-sh7367.o
-pfc-$(CONFIG_ARCH_SH7377)       += pfc-sh7377.o
 pfc-$(CONFIG_ARCH_SH7372)       += pfc-sh7372.o
 pfc-$(CONFIG_ARCH_SH73A0)       += pfc-sh73a0.o
 pfc-$(CONFIG_ARCH_R8A7740)      += pfc-r8a7740.o
 pfc-$(CONFIG_ARCH_R8A7779)      += pfc-r8a7779.o
 # IRQ objects
-obj-$(CONFIG_ARCH_SH7367)       += entry-intc.o
-obj-$(CONFIG_ARCH_SH7377)       += entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
 obj-$(CONFIG_ARCH_R8A7740)      += entry-intc.o
@@ -45,8 +39,6 @@ obj-$(CONFIG_ARCH_R8A7740)	+= pm-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o
 # Board objects
-obj-$(CONFIG_MACH_G3EVM)        += board-g3evm.o
-obj-$(CONFIG_MACH_G4EVM)        += board-g4evm.o
 obj-$(CONFIG_MACH_AP4EVB)       += board-ap4evb.o
 obj-$(CONFIG_MACH_AG5EVM)       += board-ag5evm.o
 obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 790dc68c4312..40657854e3ad 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -658,133 +658,16 @@ static struct platform_device lcdc_device = {
 /* FSI */
 #define IRQ_FSI         evt2irq(0x1840)
-static int __fsi_set_rate(struct clk *clk, long rate, int enable)
-{
-        int ret = 0;
-        if (rate <= 0)
-                return ret;
-        if (enable) {
-                ret = clk_set_rate(clk, rate);
-                if (0 == ret)
-                        ret = clk_enable(clk);
-        } else {
-                clk_disable(clk);
-        }
-        return ret;
-}
-static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
-{
-        return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable);
-}
-static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
-{
-        struct clk *fsia_ick;
-        struct clk *fsiack;
-        int ret = -EIO;
-        fsia_ick = clk_get(dev, "icka");
-        if (IS_ERR(fsia_ick))
-                return PTR_ERR(fsia_ick);
-        /*
-         * FSIACK is connected to AK4642,
-         * and use external clock pin from it.
-         * it is parent of fsia_ick now.
-         */
-        fsiack = clk_get_parent(fsia_ick);
-        if (!fsiack)
-                goto fsia_ick_out;
-        /*
-         * we get 1/1 divided clock by setting same rate to fsiack and fsia_ick
-         *
-         ** FIXME **
-         * Because the freq_table of external clk (fsiack) are all 0,
-         * the return value of clk_round_rate became 0.
-         * So, it use __fsi_set_rate here.
-         */
-        ret = __fsi_set_rate(fsiack, rate, enable);
-        if (ret < 0)
-                goto fsiack_out;
-        ret = __fsi_set_round_rate(fsia_ick, rate, enable);
-        if ((ret < 0) && enable)
-                __fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */
-fsiack_out:
-        clk_put(fsiack);
-fsia_ick_out:
-        clk_put(fsia_ick);
-        return 0;
-}
-static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
-{
-        struct clk *fsib_clk;
-        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
-        long fsib_rate = 0;
-        long fdiv_rate = 0;
-        int ackmd_bpfmd;
-        int ret;
-        switch (rate) {
-        case 44100:
-                fsib_rate       = rate * 256;
-                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
-                break;
-        case 48000:
-                fsib_rate       = 85428000; /* around 48kHz x 256 x 7 */
-                fdiv_rate       = rate * 256;
-                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
-                break;
-        default:
-                pr_err("unsupported rate in FSI2 port B\n");
-                return -EINVAL;
-        }
-        /* FSI B setting */
-        fsib_clk = clk_get(dev, "ickb");
-        if (IS_ERR(fsib_clk))
-                return -EIO;
-        ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
-        if (ret < 0)
-                goto fsi_set_rate_end;
-        /* FSI DIV setting */
-        ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
-        if (ret < 0) {
-                /* disable FSI B */
-                if (enable)
-                        __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
-                goto fsi_set_rate_end;
-        }
-        ret = ackmd_bpfmd;
-fsi_set_rate_end:
-        clk_put(fsib_clk);
-        return ret;
-}
 static struct sh_fsi_platform_info fsi_info = {
        .port_a = {
                .flags          = SH_FSI_BRS_INV,
-                .set_rate       = fsi_ak4642_set_rate,
        },
        .port_b = {
                .flags          = SH_FSI_BRS_INV |
                                  SH_FSI_BRM_INV |
                                  SH_FSI_LRS_INV |
+                                  SH_FSI_CLK_CPG |
                                  SH_FSI_FMT_SPDIF,
-                .set_rate       = fsi_hdmi_set_rate,
        },
 };
@@ -1144,25 +1027,6 @@ out:
                clk_put(hdmi_ick);
 }
-static void __init fsi_init_pm_clock(void)
-{
-        struct clk *fsia_ick;
-        int ret;
-        fsia_ick = clk_get(&fsi_device.dev, "icka");
-        if (IS_ERR(fsia_ick)) {
-                ret = PTR_ERR(fsia_ick);
-                pr_err("Cannot get FSI ICK: %d\n", ret);
-                return;
-        }
-        ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
-        if (ret < 0)
-                pr_err("Cannot set FSI-A parent: %d\n", ret);
-        clk_put(fsia_ick);
-}
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
 # define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
@@ -1476,7 +1340,6 @@ static void __init ap4evb_init(void)
                                       ARRAY_SIZE(domain_devices));
        hdmi_init_pm_clock();
-        fsi_init_pm_clock();
        sh7372_pm_init();
        pm_clk_add(&fsi_device.dev, "spu2");
        pm_clk_add(&lcdc1_device.dev, "hdmi");
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 3cc8b1c21da9..5353adf6b828 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -768,32 +768,6 @@ static struct platform_device ceu0_device = {
 };
 /* FSI */
-static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
-{
-        struct clk *fsib;
-        int ret;
-        /* it support 48KHz only */
-        if (48000 != rate)
-                return -EINVAL;
-        fsib = clk_get(dev, "ickb");
-        if (IS_ERR(fsib))
-                return -EINVAL;
-        if (enable) {
-                ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
-                clk_enable(fsib);
-        } else {
-                ret = 0;
-                clk_disable(fsib);
-        }
-        clk_put(fsib);
-        return ret;
-}
 static struct sh_fsi_platform_info fsi_info = {
        /* FSI-WM8978 */
        .port_a = {
@@ -802,8 +776,8 @@ static struct sh_fsi_platform_info fsi_info = {
        /* FSI-HDMI */
        .port_b = {
                .flags          = SH_FSI_FMT_SPDIF |
-                                  SH_FSI_ENABLE_STREAM_MODE,
+                                  SH_FSI_ENABLE_STREAM_MODE |
-                .set_rate       = fsi_hdmi_set_rate,
+                                  SH_FSI_CLK_CPG,
                .tx_id          = SHDMA_SLAVE_FSIB_TX,
        }
 };
@@ -938,13 +912,11 @@ static void __init eva_clock_init(void)
        struct clk *xtal1       = clk_get(NULL, "extal1");
        struct clk *usb24s      = clk_get(NULL, "usb24s");
        struct clk *fsibck      = clk_get(NULL, "fsibck");
-        struct clk *fsib        = clk_get(&fsi_device.dev, "ickb");
        if (IS_ERR(system)      ||
            IS_ERR(xtal1)       ||
            IS_ERR(usb24s)      ||
-            IS_ERR(fsibck)      ||
+            IS_ERR(fsibck)) {
-            IS_ERR(fsib)) {
                pr_err("armadillo800eva board clock init failed\n");
                goto clock_error;
        }
@@ -956,9 +928,7 @@ static void __init eva_clock_init(void)
        clk_set_parent(usb24s, system);
        /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
-        clk_set_parent(fsib, fsibck);
        clk_set_rate(fsibck, 12288000);
-        clk_set_rate(fsib,   12288000);
 clock_error:
        if (!IS_ERR(system))
@@ -969,8 +939,6 @@ clock_error:
                clk_put(usb24s);
        if (!IS_ERR(fsibck))
                clk_put(fsibck);
-        if (!IS_ERR(fsib))
-                clk_put(fsib);
 }
 /*
@@ -1229,6 +1197,13 @@ static void __init eva_add_early_devices(void)
        shmobile_timer.init = eva_earlytimer_init;
 }
+#define RESCNT2 IOMEM(0xe6188020)
+static void eva_restart(char mode, const char *cmd)
+{
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
 static const char *eva_boards_compat_dt[] __initdata = {
        "renesas,armadillo800eva",
        NULL,
@@ -1243,4 +1218,5 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
        .init_late      = shmobile_init_late,
        .timer          = &shmobile_timer,
        .dt_compat      = eva_boards_compat_dt,
+        .restart        = eva_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
deleted file mode 100644
index b179d4c213bb..000000000000
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * G3EVM board support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/sh_flctl.h>
-#include <linux/usb/r8a66597.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/input/sh_keysc.h>
-#include <linux/dma-mapping.h>
-#include <mach/irqs.h>
-#include <mach/sh7367.h>
-#include <mach/common.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-/*
- * IrDA
- *
- * S67: 5bit : ON  power
- *    : 6bit : ON  remote control
- *             OFF IrDA
- */
-static struct mtd_partition nor_flash_partitions[] = {
-        {
-                .name           = "loader",
-                .offset         = 0x00000000,
-                .size           = 512 * 1024,
-        },
-        {
-                .name           = "bootenv",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 512 * 1024,
-        },
-        {
-                .name           = "kernel_ro",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-        },
-        {
-                .name           = "data",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static struct physmap_flash_data nor_flash_data = {
-        .width          = 2,
-        .parts          = nor_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
-};
-static struct resource nor_flash_resources[] = {
-        [0]     = {
-                .start  = 0x00000000,
-                .end    = 0x08000000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device nor_flash_device = {
-        .name           = "physmap-flash",
-        .dev            = {
-                .platform_data  = &nor_flash_data,
-        },
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-        .resource       = nor_flash_resources,
-};
-/* USBHS */
-static void usb_host_port_power(int port, int power)
-{
-        if (!power) /* only power-on supported for now */
-                return;
-        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
-}
-static struct r8a66597_platdata usb_host_data = {
-        .on_chip = 1,
-        .port_power = usb_host_port_power,
-};
-static struct resource usb_host_resources[] = {
-        [0] = {
-                .name   = "USBHS",
-                .start  = 0xe6890000,
-                .end    = 0xe68900e5,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0xa20), /* USBHS_USHI0 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device usb_host_device = {
-        .name           = "r8a66597_hcd",
-        .id             = 0,
-        .dev = {
-                .platform_data          = &usb_host_data,
-                .dma_mask               = NULL,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(usb_host_resources),
-        .resource       = usb_host_resources,
-};
-/* KEYSC */
-static struct sh_keysc_info keysc_info = {
-        .mode           = SH_KEYSC_MODE_5,
-        .scan_timing    = 3,
-        .delay          = 100,
-        .keycodes = {
-                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
-                KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
-                KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
-                KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
-                KEY_WAKEUP, KEY_COFFEE, KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
-                KEY_5, KEY_6, KEY_7, KEY_8, KEY_9, KEY_STOP, KEY_COMPUTER,
-        },
-};
-static struct resource keysc_resources[] = {
-        [0] = {
-                .name   = "KEYSC",
-                .start  = 0xe61b0000,
-                .end    = 0xe61b000f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0xbe0), /* KEYSC_KEY */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device keysc_device = {
-        .name           = "sh_keysc",
-        .num_resources  = ARRAY_SIZE(keysc_resources),
-        .resource       = keysc_resources,
-        .dev    = {
-                .platform_data  = &keysc_info,
-        },
-};
-static struct mtd_partition nand_partition_info[] = {
-        {
-                .name   = "system",
-                .offset = 0,
-                .size   = 64 * 1024 * 1024,
-        },
-        {
-                .name   = "userdata",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 128 * 1024 * 1024,
-        },
-        {
-                .name   = "cache",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = 64 * 1024 * 1024,
-        },
-};
-static struct resource nand_flash_resources[] = {
-        [0] = {
-                .start  = 0xe6a30000,
-                .end    = 0xe6a3009b,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct sh_flctl_platform_data nand_flash_data = {
-        .parts          = nand_partition_info,
-        .nr_parts       = ARRAY_SIZE(nand_partition_info),
-        .flcmncr_val    = QTSEL_E | FCKSEL_E | TYPESEL_SET | NANWF_E
-                        | SHBUSSEL | SEL_16BIT,
-};
-static struct platform_device nand_flash_device = {
-        .name           = "sh_flctl",
-        .resource       = nand_flash_resources,
-        .num_resources  = ARRAY_SIZE(nand_flash_resources),
-        .dev            = {
-                .platform_data = &nand_flash_data,
-        },
-};
-static struct resource irda_resources[] = {
-        [0] = {
-                .start  = 0xE6D00000,
-                .end    = 0xE6D01FD4 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x480), /* IRDA */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device irda_device = {
-        .name           = "sh_irda",
-        .id             = -1,
-        .resource       = irda_resources,
-        .num_resources  = ARRAY_SIZE(irda_resources),
-};
-static struct platform_device *g3evm_devices[] __initdata = {
-        &nor_flash_device,
-        &usb_host_device,
-        &keysc_device,
-        &nand_flash_device,
-        &irda_device,
-};
-static void __init g3evm_init(void)
-{
-        sh7367_pinmux_init();
-        /* Lit DS4 LED */
-        gpio_request(GPIO_PORT22, NULL);
-        gpio_direction_output(GPIO_PORT22, 1);
-        gpio_export(GPIO_PORT22, 0);
-        /* Lit DS8 LED */
-        gpio_request(GPIO_PORT23, NULL);
-        gpio_direction_output(GPIO_PORT23, 1);
-        gpio_export(GPIO_PORT23, 0);
-        /* Lit DS3 LED */
-        gpio_request(GPIO_PORT24, NULL);
-        gpio_direction_output(GPIO_PORT24, 1);
-        gpio_export(GPIO_PORT24, 0);
-        /* SCIFA1 */
-        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA1_CTS, NULL);
-        gpio_request(GPIO_FN_SCIFA1_RTS, NULL);
-        /* USBHS */
-        gpio_request(GPIO_FN_VBUS0, NULL);
-        gpio_request(GPIO_FN_PWEN, NULL);
-        gpio_request(GPIO_FN_OVCN, NULL);
-        gpio_request(GPIO_FN_OVCN2, NULL);
-        gpio_request(GPIO_FN_EXTLP, NULL);
-        gpio_request(GPIO_FN_IDIN, NULL);
-        /* setup USB phy */
-        __raw_writew(0x0300, IOMEM(0xe605810a));        /* USBCR1 */
-        __raw_writew(0x00e0, IOMEM(0xe60581c0));        /* CPFCH */
-        __raw_writew(0x6010, IOMEM(0xe60581c6));        /* CGPOSR */
-        __raw_writew(0x8a0a, IOMEM(0xe605810c));        /* USBCR2 */
-        /* KEYSC @ CN7 */
-        gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_PORT43_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_PORT44_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_PORT45_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_PORT46_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_PORT47_KEYOUT5, NULL);
-        gpio_request(GPIO_FN_PORT48_KEYIN0_PU, NULL);
-        gpio_request(GPIO_FN_PORT49_KEYIN1_PU, NULL);
-        gpio_request(GPIO_FN_PORT50_KEYIN2_PU, NULL);
-        gpio_request(GPIO_FN_PORT55_KEYIN3_PU, NULL);
-        gpio_request(GPIO_FN_PORT56_KEYIN4_PU, NULL);
-        gpio_request(GPIO_FN_PORT57_KEYIN5_PU, NULL);
-        gpio_request(GPIO_FN_PORT58_KEYIN6_PU, NULL);
-        /* FLCTL */
-        gpio_request(GPIO_FN_FCE0, NULL);
-        gpio_request(GPIO_FN_D0_ED0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_ED1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_ED2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_ED3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_ED4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_ED5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_ED6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_ED7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_ED8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_ED9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_ED10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_ED11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_ED12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_ED13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_ED14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_ED15_NAF15, NULL);
-        gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
-        gpio_request(GPIO_FN_FRB, NULL);
-        /* FOE, FCDE, FSC on dedicated pins */
-        __raw_writel(__raw_readl(IOMEM(0xe6158048)) & ~(1 << 15), IOMEM(0xe6158048));
-        /* IrDA */
-        gpio_request(GPIO_FN_IRDA_OUT, NULL);
-        gpio_request(GPIO_FN_IRDA_IN, NULL);
-        gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
-        sh7367_add_standard_devices();
-        platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
-}
-MACHINE_START(G3EVM, "g3evm")
-        .map_io         = sh7367_map_io,
-        .init_early     = sh7367_add_early_devices,
-        .init_irq       = sh7367_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = g3evm_init,
-        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
deleted file mode 100644
index 35c126caa4d8..000000000000
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * G4EVM board support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/usb/r8a66597.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/input/sh_keysc.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sh_mobile_sdhi.h>
-#include <linux/gpio.h>
-#include <linux/dma-mapping.h>
-#include <mach/irqs.h>
-#include <mach/sh7377.h>
-#include <mach/common.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "sh-gpio.h"
-/*
- * SDHI
- *
- * SDHI0 : card detection is possible
- * SDHI1 : card detection is impossible
- *
- * [G4-MAIN-BOARD]
- * JP74 : short         # DBG_2V8A    for SDHI0
- * JP75 : NC            # DBG_3V3A    for SDHI0
- * JP76 : NC            # DBG_3V3A_SD for SDHI0
- * JP77 : NC            # 3V3A_SDIO   for SDHI1
- * JP78 : short         # DBG_2V8A    for SDHI1
- * JP79 : NC            # DBG_3V3A    for SDHI1
- * JP80 : NC            # DBG_3V3A_SD for SDHI1
- *
- * [G4-CORE-BOARD]
- * S32 : all off        # to dissever from G3-CORE_DBG board
- * S33 : all off        # to dissever from G3-CORE_DBG board
- *
- * [G3-CORE_DBG-BOARD]
- * S1  : all off        # to dissever from G3-CORE_DBG board
- * S3  : all off        # to dissever from G3-CORE_DBG board
- * S4  : all off        # to dissever from G3-CORE_DBG board
- */
-static struct mtd_partition nor_flash_partitions[] = {
-        {
-                .name           = "loader",
-                .offset         = 0x00000000,
-                .size           = 512 * 1024,
-        },
-        {
-                .name           = "bootenv",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 512 * 1024,
-        },
-        {
-                .name           = "kernel_ro",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-        },
-        {
-                .name           = "data",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static struct physmap_flash_data nor_flash_data = {
-        .width          = 2,
-        .parts          = nor_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
-};
-static struct resource nor_flash_resources[] = {
-        [0]     = {
-                .start  = 0x00000000,
-                .end    = 0x08000000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device nor_flash_device = {
-        .name           = "physmap-flash",
-        .dev            = {
-                .platform_data  = &nor_flash_data,
-        },
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-        .resource       = nor_flash_resources,
-};
-/* USBHS */
-static void usb_host_port_power(int port, int power)
-{
-        if (!power) /* only power-on supported for now */
-                return;
-        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
-}
-static struct r8a66597_platdata usb_host_data = {
-        .on_chip = 1,
-        .port_power = usb_host_port_power,
-};
-static struct resource usb_host_resources[] = {
-        [0] = {
-                .name   = "USBHS",
-                .start  = 0xe6890000,
-                .end    = 0xe68900e5,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0a20), /* USBHS_USHI0 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device usb_host_device = {
-        .name           = "r8a66597_hcd",
-        .id             = 0,
-        .dev = {
-                .platform_data          = &usb_host_data,
-                .dma_mask               = NULL,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(usb_host_resources),
-        .resource       = usb_host_resources,
-};
-/* KEYSC */
-static struct sh_keysc_info keysc_info = {
-        .mode           = SH_KEYSC_MODE_5,
-        .scan_timing    = 3,
-        .delay          = 100,
-        .keycodes = {
-                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
-                KEY_G, KEY_H, KEY_I, KEY_J, KEY_K, KEY_L,
-                KEY_M, KEY_N, KEY_U, KEY_P, KEY_Q, KEY_R,
-                KEY_S, KEY_T, KEY_U, KEY_V, KEY_W, KEY_X,
-                KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE,
-                KEY_0, KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
-                KEY_6, KEY_7, KEY_8, KEY_9, KEY_STOP, KEY_COMPUTER,
-        },
-};
-static struct resource keysc_resources[] = {
-        [0] = {
-                .name   = "KEYSC",
-                .start  = 0xe61b0000,
-                .end    = 0xe61b000f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0be0), /* KEYSC_KEY */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device keysc_device = {
-        .name           = "sh_keysc",
-        .id             = 0, /* keysc0 clock */
-        .num_resources  = ARRAY_SIZE(keysc_resources),
-        .resource       = keysc_resources,
-        .dev    = {
-                .platform_data  = &keysc_info,
-        },
-};
-/* Fixed 3.3V regulator to be used by SDHI0 and SDHI1 */
-static struct regulator_consumer_supply fixed3v3_power_consumers[] =
-{
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
-};
-/* SDHI */
-static struct sh_mobile_sdhi_info sdhi0_info = {
-        .tmio_caps      = MMC_CAP_SDIO_IRQ,
-};
-static struct resource sdhi0_resources[] = {
-        [0] = {
-                .name   = "SDHI0",
-                .start  = 0xe6d50000,
-                .end    = 0xe6d500ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0e00), /* SDHI0 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device sdhi0_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi0_resources),
-        .resource       = sdhi0_resources,
-        .id             = 0,
-        .dev    = {
-                .platform_data  = &sdhi0_info,
-        },
-};
-static struct sh_mobile_sdhi_info sdhi1_info = {
-        .tmio_caps      = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
-};
-static struct resource sdhi1_resources[] = {
-        [0] = {
-                .name   = "SDHI1",
-                .start  = 0xe6d60000,
-                .end    = 0xe6d600ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0e80), /* SDHI1 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device sdhi1_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi1_resources),
-        .resource       = sdhi1_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &sdhi1_info,
-        },
-};
-static struct platform_device *g4evm_devices[] __initdata = {
-        &nor_flash_device,
-        &usb_host_device,
-        &keysc_device,
-        &sdhi0_device,
-        &sdhi1_device,
-};
-#define GPIO_SDHID0_D0  IOMEM(0xe60520fc)
-#define GPIO_SDHID0_D1  IOMEM(0xe60520fd)
-#define GPIO_SDHID0_D2  IOMEM(0xe60520fe)
-#define GPIO_SDHID0_D3  IOMEM(0xe60520ff)
-#define GPIO_SDHICMD0   IOMEM(0xe6052100)
-#define GPIO_SDHID1_D0  IOMEM(0xe6052103)
-#define GPIO_SDHID1_D1  IOMEM(0xe6052104)
-#define GPIO_SDHID1_D2  IOMEM(0xe6052105)
-#define GPIO_SDHID1_D3  IOMEM(0xe6052106)
-#define GPIO_SDHICMD1   IOMEM(0xe6052107)
-static void __init g4evm_init(void)
-{
-        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
-                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
-        sh7377_pinmux_init();
-        /* Lit DS14 LED */
-        gpio_request(GPIO_PORT109, NULL);
-        gpio_direction_output(GPIO_PORT109, 1);
-        gpio_export(GPIO_PORT109, 1);
-        /* Lit DS15 LED */
-        gpio_request(GPIO_PORT110, NULL);
-        gpio_direction_output(GPIO_PORT110, 1);
-        gpio_export(GPIO_PORT110, 1);
-        /* Lit DS16 LED */
-        gpio_request(GPIO_PORT112, NULL);
-        gpio_direction_output(GPIO_PORT112, 1);
-        gpio_export(GPIO_PORT112, 1);
-        /* Lit DS17 LED */
-        gpio_request(GPIO_PORT113, NULL);
-        gpio_direction_output(GPIO_PORT113, 1);
-        gpio_export(GPIO_PORT113, 1);
-        /* USBHS */
-        gpio_request(GPIO_FN_VBUS_0, NULL);
-        gpio_request(GPIO_FN_PWEN, NULL);
-        gpio_request(GPIO_FN_OVCN, NULL);
-        gpio_request(GPIO_FN_OVCN2, NULL);
-        gpio_request(GPIO_FN_EXTLP, NULL);
-        gpio_request(GPIO_FN_IDIN, NULL);
-        /* setup USB phy */
-        __raw_writew(0x0200, IOMEM(0xe605810a));       /* USBCR1 */
-        __raw_writew(0x00e0, IOMEM(0xe60581c0));       /* CPFCH */
-        __raw_writew(0x6010, IOMEM(0xe60581c6));       /* CGPOSR */
-        __raw_writew(0x8a0a, IOMEM(0xe605810c));       /* USBCR2 */
-        /* KEYSC @ CN31 */
-        gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);
-        gpio_request(GPIO_FN_PORT61_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_PORT62_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_PORT63_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_PORT64_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_PORT65_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_PORT66_KEYIN0_PU, NULL);
-        gpio_request(GPIO_FN_PORT67_KEYIN1_PU, NULL);
-        gpio_request(GPIO_FN_PORT68_KEYIN2_PU, NULL);
-        gpio_request(GPIO_FN_PORT69_KEYIN3_PU, NULL);
-        gpio_request(GPIO_FN_PORT70_KEYIN4_PU, NULL);
-        gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL);
-        gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL);
-        /* SDHI0 */
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHICD0, NULL);
-        gpio_request(GPIO_FN_SDHID0_0, NULL);
-        gpio_request(GPIO_FN_SDHID0_1, NULL);
-        gpio_request(GPIO_FN_SDHID0_2, NULL);
-        gpio_request(GPIO_FN_SDHID0_3, NULL);
-        gpio_request(GPIO_FN_SDHICMD0, NULL);
-        gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_request_pullup(GPIO_SDHID0_D0);
-        gpio_request_pullup(GPIO_SDHID0_D1);
-        gpio_request_pullup(GPIO_SDHID0_D2);
-        gpio_request_pullup(GPIO_SDHID0_D3);
-        gpio_request_pullup(GPIO_SDHICMD0);
-        /* SDHI1 */
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHID1_0, NULL);
-        gpio_request(GPIO_FN_SDHID1_1, NULL);
-        gpio_request(GPIO_FN_SDHID1_2, NULL);
-        gpio_request(GPIO_FN_SDHID1_3, NULL);
-        gpio_request(GPIO_FN_SDHICMD1, NULL);
-        gpio_request_pullup(GPIO_SDHID1_D0);
-        gpio_request_pullup(GPIO_SDHID1_D1);
-        gpio_request_pullup(GPIO_SDHID1_D2);
-        gpio_request_pullup(GPIO_SDHID1_D3);
-        gpio_request_pullup(GPIO_SDHICMD1);
-        sh7377_add_standard_devices();
-        platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
-}
-MACHINE_START(G4EVM, "g4evm")
-        .map_io         = sh7377_map_io,
-        .init_early     = sh7377_add_early_devices,
-        .init_irq       = sh7377_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = g4evm_init,
-        .init_late      = shmobile_init_late,
-        .timer          = &shmobile_timer,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 0a43f3189c21..c02448d6847f 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -384,6 +384,8 @@ static struct regulator_consumer_supply fixed2v8_power_consumers[] =
 /* SDHI */
 static struct sh_mobile_sdhi_info sdhi0_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
@@ -424,6 +426,8 @@ static struct platform_device sdhi0_device = {
 /* Micro SD */
 static struct sh_mobile_sdhi_info sdhi2_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI2_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI2_RX,
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
                          TMIO_MMC_USE_GPIO_CD |
                          TMIO_MMC_WRPROTECT_DISABLE,
@@ -548,7 +552,6 @@ static struct platform_device fsi_ak4648_device = {
 /* I2C */
 static struct pcf857x_platform_data pcf8575_pdata = {
        .gpio_base      = GPIO_PCF8575_BASE,
-        .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
 };
 static struct i2c_board_info i2c0_devices[] = {
@@ -557,7 +560,15 @@ static struct i2c_board_info i2c0_devices[] = {
        },
        {
                I2C_BOARD_INFO("r2025sd", 0x32),
-        }
+        },
+        {
+                I2C_BOARD_INFO("ak8975", 0x0c),
+                .irq = intcs_evt2irq(0x3380), /* IRQ28 */
+        },
+        {
+                I2C_BOARD_INFO("adxl34x", 0x1d),
+                .irq = intcs_evt2irq(0x3340), /* IRQ26 */
+        },
 };
 static struct i2c_board_info i2c1_devices[] = {
@@ -570,6 +581,7 @@ static struct i2c_board_info i2c1_devices[] = {
 static struct i2c_board_info i2c3_devices[] = {
        {
                I2C_BOARD_INFO("pcf8575", 0x20),
+                .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
                .platform_data = &pcf8575_pdata,
        },
 };
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 0c27c810cf99..3f56e70795b7 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -816,6 +816,8 @@ static struct platform_device usbhs1_device = {
        .id     = 1,
        .dev = {
                .platform_data          = &usbhs1_private.info,
+                .dma_mask               = &usbhs1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
        },
        .num_resources  = ARRAY_SIZE(usbhs1_resources),
        .resource       = usbhs1_resources,
@@ -860,76 +862,6 @@ static struct platform_device leds_device = {
 /* FSI */
 #define IRQ_FSI evt2irq(0x1840)
-static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
-{
-        int ret;
-        if (rate <= 0)
-                return 0;
-        if (!enable) {
-                clk_disable(clk);
-                return 0;
-        }
-        ret = clk_set_rate(clk, clk_round_rate(clk, rate));
-        if (ret < 0)
-                return ret;
-        return clk_enable(clk);
-}
-static int fsi_b_set_rate(struct device *dev, int rate, int enable)
-{
-        struct clk *fsib_clk;
-        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
-        long fsib_rate = 0;
-        long fdiv_rate = 0;
-        int ackmd_bpfmd;
-        int ret;
-        /* clock start */
-        switch (rate) {
-        case 44100:
-                fsib_rate       = rate * 256;
-                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
-                break;
-        case 48000:
-                fsib_rate       = 85428000; /* around 48kHz x 256 x 7 */
-                fdiv_rate       = rate * 256;
-                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
-                break;
-        default:
-                pr_err("unsupported rate in FSI2 port B\n");
-                return -EINVAL;
-        }
-        /* FSI B setting */
-        fsib_clk = clk_get(dev, "ickb");
-        if (IS_ERR(fsib_clk))
-                return -EIO;
-        /* fsib */
-        ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
-        if (ret < 0)
-                goto fsi_set_rate_end;
-        /* FSI DIV */
-        ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
-        if (ret < 0) {
-                /* disable FSI B */
-                if (enable)
-                        __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
-                goto fsi_set_rate_end;
-        }
-        ret = ackmd_bpfmd;
-fsi_set_rate_end:
-        clk_put(fsib_clk);
-        return ret;
-}
 static struct sh_fsi_platform_info fsi_info = {
        .port_a = {
                .flags = SH_FSI_BRS_INV,
@@ -940,8 +872,8 @@ static struct sh_fsi_platform_info fsi_info = {
                .flags = SH_FSI_BRS_INV |
                        SH_FSI_BRM_INV  |
                        SH_FSI_LRS_INV  |
+                        SH_FSI_CLK_CPG  |
                        SH_FSI_FMT_SPDIF,
-                .set_rate = fsi_b_set_rate,
        }
 };
@@ -1018,7 +950,11 @@ static struct resource nand_flash_resources[] = {
                .start  = 0xe6a30000,
                .end    = 0xe6a3009b,
                .flags  = IORESOURCE_MEM,
-        }
+        },
+        [1] = {
+                .start  = evt2irq(0x0d80), /* flstei: status error irq */
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 static struct sh_flctl_platform_data nand_flash_data = {
@@ -1651,7 +1587,12 @@ static void __init mackerel_init(void)
        pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
 }
-MACHINE_START(MACKEREL, "mackerel")
+static const char *mackerel_boards_compat_dt[] __initdata = {
+        "renesas,mackerel",
+        NULL,
+};
+DT_MACHINE_START(MACKEREL_DT, "mackerel")
        .map_io         = sh7372_map_io,
        .init_early     = sh7372_add_early_devices,
        .init_irq       = sh7372_init_irq,
@@ -1659,4 +1600,5 @@ MACHINE_START(MACKEREL, "mackerel")
        .init_machine   = mackerel_init,
        .init_late      = sh7372_pm_init_late,
        .timer          = &shmobile_timer,
+        .dt_compat  = mackerel_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index b8a7525a4e2f..449f9289567d 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -30,8 +30,14 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/sh_hspi.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -126,12 +132,201 @@ static struct platform_device thermal_device = {
        .num_resources  = ARRAY_SIZE(thermal_resources),
 };
+/* HSPI */
+static struct resource hspi_resources[] = {
+        [0] = {
+                .start          = 0xFFFC7000,
+                .end            = 0xFFFC7018 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device hspi_device = {
+        .name   = "sh-hspi",
+        .id     = 0,
+        .resource       = hspi_resources,
+        .num_resources  = ARRAY_SIZE(hspi_resources),
+};
+/* USB PHY */
+static struct resource usb_phy_resources[] = {
+        [0] = {
+                .start          = 0xffe70000,
+                .end            = 0xffe70900 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = 0xfff70000,
+                .end            = 0xfff70900 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device usb_phy_device = {
+        .name           = "rcar_usb_phy",
+        .resource       = usb_phy_resources,
+        .num_resources  = ARRAY_SIZE(usb_phy_resources),
+};
 static struct platform_device *marzen_devices[] __initdata = {
        &eth_device,
        &sdhi0_device,
        &thermal_device,
+        &hspi_device,
+        &usb_phy_device,
 };
+/* USB */
+static struct usb_phy *phy;
+static int usb_power_on(struct platform_device *pdev)
+{
+        if (!phy)
+                return -EIO;
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
+        usb_phy_init(phy);
+        return 0;
+}
+static void usb_power_off(struct platform_device *pdev)
+{
+        if (!phy)
+                return;
+        usb_phy_shutdown(phy);
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+}
+static struct usb_ehci_pdata ehcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+static struct resource ehci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70000,
+                .end    = 0xffe70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(44),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ehci0_device = {
+        .name   = "ehci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci0_resources),
+        .resource       = ehci0_resources,
+};
+static struct resource ehci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70000,
+                .end    = 0xfff70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(45),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ehci1_device = {
+        .name   = "ehci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci1_resources),
+        .resource       = ehci1_resources,
+};
+static struct usb_ohci_pdata ohcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+static struct resource ohci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70400,
+                .end    = 0xffe70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(44),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ohci0_device = {
+        .name   = "ohci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci0_resources),
+        .resource       = ohci0_resources,
+};
+static struct resource ohci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70400,
+                .end    = 0xfff70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(45),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device ohci1_device = {
+        .name   = "ohci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci1_resources),
+        .resource       = ohci1_resources,
+};
+static struct platform_device *marzen_late_devices[] __initdata = {
+        &ehci0_device,
+        &ehci1_device,
+        &ohci0_device,
+        &ohci1_device,
+};
+void __init marzen_init_late(void)
+{
+        /* get usb phy */
+        phy = usb_get_phy(USB_PHY_TYPE_USB2);
+        shmobile_init_late();
+        platform_add_devices(marzen_late_devices,
+                             ARRAY_SIZE(marzen_late_devices));
+}
 static void __init marzen_init(void)
 {
        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -163,6 +358,20 @@ static void __init marzen_init(void)
        gpio_request(GPIO_FN_SD0_CD, NULL);
        gpio_request(GPIO_FN_SD0_WP, NULL);
+        /* HSPI 0 */
+        gpio_request(GPIO_FN_HSPI_CLK0, NULL);
+        gpio_request(GPIO_FN_HSPI_CS0,  NULL);
+        gpio_request(GPIO_FN_HSPI_TX0,  NULL);
+        gpio_request(GPIO_FN_HSPI_RX0,  NULL);
+        /* USB (CN21) */
+        gpio_request(GPIO_FN_USB_OVC0, NULL);
+        gpio_request(GPIO_FN_USB_OVC1, NULL);
+        gpio_request(GPIO_FN_USB_OVC2, NULL);
+        /* USB (CN22) */
+        gpio_request(GPIO_FN_USB_PENC2, NULL);
        r8a7779_add_standard_devices();
        platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
@@ -175,6 +384,6 @@ MACHINE_START(MARZEN, "marzen")
        .init_irq       = r8a7779_init_irq,
        .handle_irq     = gic_handle_irq,
        .init_machine   = marzen_init,
-        .init_late      = shmobile_init_late,
+        .init_late      = marzen_init_late,
        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 6729e0032180..eac49d59782f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -65,6 +65,9 @@
 #define SMSTPCR3        IOMEM(0xe615013c)
 #define SMSTPCR4        IOMEM(0xe6150140)
+#define FSIDIVA         IOMEM(0xFE1F8000)
+#define FSIDIVB         IOMEM(0xFE1F8008)
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk extalr_clk = {
        .rate   = 32768,
@@ -188,6 +191,22 @@ static struct clk pllc1_div2_clk = {
 };
 /* USB clock */
+/*
+ * USBCKCR is controlling usb24 clock
+ * bit[7] : parent clock
+ * bit[6] : clock divide rate
+ * And this bit[7] is used as a "usb24s" from other devices.
+ * (Video clock / Sub clock / SPU clock)
+ * You can controll this clock as a below.
+ *
+ * struct clk *usb24    = clk_get(dev,  "usb24");
+ * struct clk *usb24s   = clk_get(NULL, "usb24s");
+ * struct clk *system   = clk_get(NULL, "system_clk");
+ * int rate = clk_get_rate(system);
+ *
+ * clk_set_parent(usb24s, system);  // for bit[7]
+ * clk_set_rate(usb24, rate / 2);   // for bit[6]
+ */
 static struct clk *usb24s_parents[] = {
        [0] = &system_clk,
        [1] = &extal2_clk
@@ -427,6 +446,14 @@ static struct clk *late_main_clks[] = {
        &hdmi2_clk,
 };
+/* FSI DIV */
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
+static struct clk fsidivs[] = {
+        [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
+        [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
+};
 /* MSTP */
 enum {
        DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
@@ -596,6 +623,10 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("icka", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIA]),
        CLKDEV_ICK_ID("ickb", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIB]),
+        CLKDEV_ICK_ID("diva", "sh_fsi2",        &fsidivs[FSIDIV_A]),
+        CLKDEV_ICK_ID("divb", "sh_fsi2",        &fsidivs[FSIDIV_B]),
+        CLKDEV_ICK_ID("xcka", "sh_fsi2",        &fsiack_clk),
+        CLKDEV_ICK_ID("xckb", "sh_fsi2",        &fsibck_clk),
 };
 void __init r8a7740_clock_init(u8 md_ck)
@@ -641,6 +672,9 @@ void __init r8a7740_clock_init(u8 md_ck)
        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
                ret = clk_register(late_main_clks[k]);
+        if (!ret)
+                ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
        if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 37b2a3133b3b..c019609da660 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,8 +87,11 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+        MSTP101, MSTP100,
+        MSTP030,
+        MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
        MSTP016, MSTP015, MSTP014,
+        MSTP007,
        MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
@@ -96,6 +99,12 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
        [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
        [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
+        [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
+        [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
+        [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */
+        [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
+        [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */
        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -105,6 +114,7 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
        [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
        [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
+        [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0,  7, 0), /* HSPI */
 };
 static unsigned long mul4_recalc(struct clk *clk)
@@ -146,14 +156,25 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
+        CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
+        CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+        CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
+        CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
+        CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
+        CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
+        CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+        CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
+        CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
+        CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
deleted file mode 100644
index ef0a95e592c4..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * SH7367 clock framework support
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include <mach/common.h>
-/* SH7367 registers */
-#define RTFRQCR    IOMEM(0xe6150000)
-#define SYFRQCR    IOMEM(0xe6150004)
-#define CMFRQCR    IOMEM(0xe61500E0)
-#define VCLKCR1    IOMEM(0xe6150008)
-#define VCLKCR2    IOMEM(0xe615000C)
-#define VCLKCR3    IOMEM(0xe615001C)
-#define SCLKACR    IOMEM(0xe6150010)
-#define SCLKBCR    IOMEM(0xe6150014)
-#define SUBUSBCKCR IOMEM(0xe6158080)
-#define SPUCKCR    IOMEM(0xe6150084)
-#define MSUCKCR    IOMEM(0xe6150088)
-#define MVI3CKCR   IOMEM(0xe6150090)
-#define VOUCKCR    IOMEM(0xe6150094)
-#define MFCK1CR    IOMEM(0xe6150098)
-#define MFCK2CR    IOMEM(0xe615009C)
-#define PLLC1CR    IOMEM(0xe6150028)
-#define PLLC2CR    IOMEM(0xe615002C)
-#define RTMSTPCR0  IOMEM(0xe6158030)
-#define RTMSTPCR2  IOMEM(0xe6158038)
-#define SYMSTPCR0  IOMEM(0xe6158040)
-#define SYMSTPCR2  IOMEM(0xe6158048)
-#define CMMSTPCR0  IOMEM(0xe615804c)
-/* Fixed 32 KHz root clock from EXTALR pin */
-static struct clk r_clk = {
-        .rate           = 32768,
-};
-/*
- * 26MHz default rate for the EXTALB1 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7367_extalb1_clk = {
-        .rate           = 26666666,
-};
-/*
- * 48MHz default rate for the EXTAL2 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7367_extal2_clk = {
-        .rate           = 48000000,
-};
-/* A fixed divide-by-2 block */
-static unsigned long div2_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 2;
-}
-static struct sh_clk_ops div2_clk_ops = {
-        .recalc         = div2_recalc,
-};
-/* Divide extalb1 by two */
-static struct clk extalb1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7367_extalb1_clk,
-};
-/* Divide extal2 by two */
-static struct clk extal2_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7367_extal2_clk,
-};
-/* PLLC1 */
-static unsigned long pllc1_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-        if (__raw_readl(PLLC1CR) & (1 << 14))
-                mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
-        return clk->parent->rate * mult;
-}
-static struct sh_clk_ops pllc1_clk_ops = {
-        .recalc         = pllc1_recalc,
-};
-static struct clk pllc1_clk = {
-        .ops            = &pllc1_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalb1_div2_clk,
-};
-/* Divide PLLC1 by two */
-static struct clk pllc1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &pllc1_clk,
-};
-/* PLLC2 */
-static unsigned long pllc2_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-        if (__raw_readl(PLLC2CR) & (1 << 31))
-                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
-        return clk->parent->rate * mult;
-}
-static struct sh_clk_ops pllc2_clk_ops = {
-        .recalc         = pllc2_recalc,
-};
-static struct clk pllc2_clk = {
-        .ops            = &pllc2_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalb1_div2_clk,
-};
-static struct clk *main_clks[] = {
-        &r_clk,
-        &sh7367_extalb1_clk,
-        &sh7367_extal2_clk,
-        &extalb1_div2_clk,
-        &extal2_div2_clk,
-        &pllc1_clk,
-        &pllc1_div2_clk,
-        &pllc2_clk,
-};
-static void div4_kick(struct clk *clk)
-{
-        unsigned long value;
-        /* set KICK bit in SYFRQCR to update hardware setting */
-        value = __raw_readl(SYFRQCR);
-        value |= (1 << 31);
-        __raw_writel(value, SYFRQCR);
-}
-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
-                          24, 32, 36, 48, 0, 72, 0, 0 };
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors = divisors,
-        .nr_divisors = ARRAY_SIZE(divisors),
-};
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-        .kick = div4_kick,
-};
-enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
-       DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
-       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
-#define DIV4(_reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
-static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
-        [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
-        [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
-        [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
-        [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
-        [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
-        [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
-        [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
-        [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
-};
-enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
-       DIV6_MVI3, DIV6_MF1, DIV6_MF2,
-       DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
-       DIV6_NR };
-static struct clk div6_clks[DIV6_NR] = {
-        [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
-        [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
-        [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
-        [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
-        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
-        [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
-        [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
-        [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
-        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
-        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
-        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
-        [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
-};
-enum { RTMSTP001,
-       RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
-       RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
-       SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
-       SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
-       SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
-       SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
-       CMMSTP003,
-       MSTP_NR };
-#define MSTP(_parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
-static struct clk mstp_clks[MSTP_NR] = {
-        [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
-        [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
-        [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
-        [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
-        [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
-        [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
-        [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
-        [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
-        [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
-        [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
-        [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
-        [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
-        [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
-        [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
-        [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
-        [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
-        [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
-        [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
-        [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
-        [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
-        [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
-        [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
-        [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
-        [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
-        [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
-        [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
-        [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
-        [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
-};
-static struct clk_lookup lookups[] = {
-        /* main clocks */
-        CLKDEV_CON_ID("r_clk", &r_clk),
-        CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
-        CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
-        CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
-        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
-        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
-        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
-        CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
-        /* DIV4 clocks */
-        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
-        CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
-        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
-        CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
-        CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
-        CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
-        CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
-        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
-        CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
-        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
-        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
-        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
-        /* DIV6 clocks */
-        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
-        CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
-        CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
-        CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
-        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
-        CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
-        CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
-        CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
-        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
-        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
-        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
-        CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
-        /* MSTP32 clocks */
-        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
-        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
-        CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
-        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
-        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
-        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
-        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
-        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
-        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
-        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
-        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
-        CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
-        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
-        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
-        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
-        CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
-        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
-};
-void __init sh7367_clock_init(void)
-{
-        int k, ret = 0;
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-        if (!ret)
-                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup sh7367 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 430a90ffa120..3ca6757b129a 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -295,10 +295,10 @@ struct clk sh7372_pllc2_clk = {
 };
 /* External input clock (pin name: FSIACK/FSIBCK ) */
-struct clk sh7372_fsiack_clk = {
+static struct clk fsiack_clk = {
 };
-struct clk sh7372_fsibck_clk = {
+static struct clk fsibck_clk = {
 };
 static struct clk *main_clks[] = {
@@ -314,8 +314,8 @@ static struct clk *main_clks[] = {
        &pllc1_clk,
        &pllc1_div2_clk,
        &sh7372_pllc2_clk,
-        &sh7372_fsiack_clk,
+        &fsiack_clk,
-        &sh7372_fsibck_clk,
+        &fsibck_clk,
 };
 static void div4_kick(struct clk *clk)
@@ -399,14 +399,14 @@ static struct clk *hdmi_parent[] = {
 static struct clk *fsiackcr_parent[] = {
        [0] = &pllc1_div2_clk,
        [1] = &sh7372_pllc2_clk,
-        [2] = &sh7372_fsiack_clk, /* external input for FSI A */
+        [2] = &fsiack_clk, /* external input for FSI A */
        [3] = NULL,     /* setting prohibited */
 };
 static struct clk *fsibckcr_parent[] = {
        [0] = &pllc1_div2_clk,
        [1] = &sh7372_pllc2_clk,
-        [2] = &sh7372_fsibck_clk, /* external input for FSI B */
+        [2] = &fsibck_clk, /* external input for FSI B */
        [3] = NULL,     /* setting prohibited */
 };
@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 };
 /* FSI DIV */
-static unsigned long fsidiv_recalc(struct clk *clk)
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
-{
-        unsigned long value;
-        value = __raw_readl(clk->mapping->base);
-        value >>= 16;
-        if (value < 2)
-                return 0;
-        return clk->parent->rate / value;
-}
-static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk_rate_div_range_round(clk, 2, 0xffff, rate);
-}
-static void fsidiv_disable(struct clk *clk)
-{
-        __raw_writel(0, clk->mapping->base);
-}
-static int fsidiv_enable(struct clk *clk)
-{
-        unsigned long value;
-        value  = __raw_readl(clk->mapping->base) >> 16;
-        if (value < 2)
-                return -EIO;
-        __raw_writel((value << 16) | 0x3, clk->mapping->base);
-        return 0;
-}
-static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
+static struct clk fsidivs[] = {
-{
+        [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
-        int idx;
+        [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
-        idx = (clk->parent->rate / rate) & 0xffff;
-        if (idx < 2)
-                return -EINVAL;
-        __raw_writel(idx << 16, clk->mapping->base);
-        return 0;
-}
-static struct sh_clk_ops fsidiv_clk_ops = {
-        .recalc         = fsidiv_recalc,
-        .round_rate     = fsidiv_round_rate,
-        .set_rate       = fsidiv_set_rate,
-        .enable         = fsidiv_enable,
-        .disable        = fsidiv_disable,
-};
-static struct clk_mapping fsidiva_clk_mapping = {
-        .phys   = FSIDIVA,
-        .len    = 8,
-};
-struct clk sh7372_fsidiva_clk = {
-        .ops            = &fsidiv_clk_ops,
-        .parent         = &div6_reparent_clks[DIV6_FSIA], /* late install */
-        .mapping        = &fsidiva_clk_mapping,
-};
-static struct clk_mapping fsidivb_clk_mapping = {
-        .phys   = FSIDIVB,
-        .len    = 8,
-};
-struct clk sh7372_fsidivb_clk = {
-        .ops            = &fsidiv_clk_ops,
-        .parent         = &div6_reparent_clks[DIV6_FSIB],  /* late install */
-        .mapping        = &fsidivb_clk_mapping,
-};
-static struct clk *late_main_clks[] = {
-        &sh7372_fsidiva_clk,
-        &sh7372_fsidivb_clk,
 };
 enum { MSTP001, MSTP000,
@@ -583,6 +507,8 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
        CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
+        CLKDEV_CON_ID("fsiack", &fsiack_clk),
+        CLKDEV_CON_ID("fsibck", &fsibck_clk),
        /* DIV4 clocks */
        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -678,6 +604,10 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
        CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
        CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
+        CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
+        CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
+        CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
+        CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
 };
 void __init sh7372_clock_init(void)
@@ -706,8 +636,8 @@ void __init sh7372_clock_init(void)
        if (!ret)
                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
+        if (!ret)
-                ret = clk_register(late_main_clks[k]);
+                ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
deleted file mode 100644
index b8480d19e1c8..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * SH7377 clock framework support
- *
- * Copyright (C) 2010 Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include <mach/common.h>
-/* SH7377 registers */
-#define RTFRQCR    IOMEM(0xe6150000)
-#define SYFRQCR    IOMEM(0xe6150004)
-#define CMFRQCR    IOMEM(0xe61500E0)
-#define VCLKCR1    IOMEM(0xe6150008)
-#define VCLKCR2    IOMEM(0xe615000C)
-#define VCLKCR3    IOMEM(0xe615001C)
-#define FMSICKCR   IOMEM(0xe6150010)
-#define FMSOCKCR   IOMEM(0xe6150014)
-#define FSICKCR    IOMEM(0xe6150018)
-#define PLLC1CR    IOMEM(0xe6150028)
-#define PLLC2CR    IOMEM(0xe615002C)
-#define SUBUSBCKCR IOMEM(0xe6150080)
-#define SPUCKCR    IOMEM(0xe6150084)
-#define MSUCKCR    IOMEM(0xe6150088)
-#define MVI3CKCR   IOMEM(0xe6150090)
-#define HDMICKCR   IOMEM(0xe6150094)
-#define MFCK1CR    IOMEM(0xe6150098)
-#define MFCK2CR    IOMEM(0xe615009C)
-#define DSITCKCR   IOMEM(0xe6150060)
-#define DSIPCKCR   IOMEM(0xe6150064)
-#define SMSTPCR0   IOMEM(0xe6150130)
-#define SMSTPCR1   IOMEM(0xe6150134)
-#define SMSTPCR2   IOMEM(0xe6150138)
-#define SMSTPCR3   IOMEM(0xe615013C)
-#define SMSTPCR4   IOMEM(0xe6150140)
-/* Fixed 32 KHz root clock from EXTALR pin */
-static struct clk r_clk = {
-        .rate           = 32768,
-};
-/*
- * 26MHz default rate for the EXTALC1 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7377_extalc1_clk = {
-        .rate           = 26666666,
-};
-/*
- * 48MHz default rate for the EXTAL2 root input clock.
- * If needed, reset this with clk_set_rate() from the platform code.
- */
-struct clk sh7377_extal2_clk = {
-        .rate           = 48000000,
-};
-/* A fixed divide-by-2 block */
-static unsigned long div2_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 2;
-}
-static struct sh_clk_ops div2_clk_ops = {
-        .recalc         = div2_recalc,
-};
-/* Divide extalc1 by two */
-static struct clk extalc1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7377_extalc1_clk,
-};
-/* Divide extal2 by two */
-static struct clk extal2_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &sh7377_extal2_clk,
-};
-/* Divide extal2 by four */
-static struct clk extal2_div4_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &extal2_div2_clk,
-};
-/* PLLC1 */
-static unsigned long pllc1_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-        if (__raw_readl(PLLC1CR) & (1 << 14))
-                mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
-        return clk->parent->rate * mult;
-}
-static struct sh_clk_ops pllc1_clk_ops = {
-        .recalc         = pllc1_recalc,
-};
-static struct clk pllc1_clk = {
-        .ops            = &pllc1_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalc1_div2_clk,
-};
-/* Divide PLLC1 by two */
-static struct clk pllc1_div2_clk = {
-        .ops            = &div2_clk_ops,
-        .parent         = &pllc1_clk,
-};
-/* PLLC2 */
-static unsigned long pllc2_recalc(struct clk *clk)
-{
-        unsigned long mult = 1;
-        if (__raw_readl(PLLC2CR) & (1 << 31))
-                mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
-        return clk->parent->rate * mult;
-}
-static struct sh_clk_ops pllc2_clk_ops = {
-        .recalc         = pllc2_recalc,
-};
-static struct clk pllc2_clk = {
-        .ops            = &pllc2_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
-        .parent         = &extalc1_div2_clk,
-};
-static struct clk *main_clks[] = {
-        &r_clk,
-        &sh7377_extalc1_clk,
-        &sh7377_extal2_clk,
-        &extalc1_div2_clk,
-        &extal2_div2_clk,
-        &extal2_div4_clk,
-        &pllc1_clk,
-        &pllc1_div2_clk,
-        &pllc2_clk,
-};
-static void div4_kick(struct clk *clk)
-{
-        unsigned long value;
-        /* set KICK bit in SYFRQCR to update hardware setting */
-        value = __raw_readl(SYFRQCR);
-        value |= (1 << 31);
-        __raw_writel(value, SYFRQCR);
-}
-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
-                          24, 32, 36, 48, 0, 72, 96, 0 };
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors = divisors,
-        .nr_divisors = ARRAY_SIZE(divisors),
-};
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-        .kick = div4_kick,
-};
-enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
-       DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
-       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
-#define DIV4(_reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
-static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
-        [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
-        [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
-        [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
-        [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
-        [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
-        [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
-        [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
-        [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
-        [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
-};
-enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
-       DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
-       DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
-       DIV6_NR };
-static struct clk div6_clks[] = {
-        [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
-        [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
-        [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
-        [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
-        [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
-        [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
-        [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
-        [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
-        [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
-        [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
-        [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
-        [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
-        [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
-        [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
-        [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
-};
-enum { MSTP001,
-       MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
-       MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-       MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
-       MSTP315, MSTP314, MSTP313,
-       MSTP403,
-       MSTP_NR };
-#define MSTP(_parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
-static struct clk mstp_clks[] = {
-        [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
-        [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
-        [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
-        [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
-        [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
-        [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
-        [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
-        [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
-        [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
-        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
-        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
-        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
-        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
-        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
-        [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
-        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
-        [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
-        [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
-        [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
-        [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
-        [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
-        [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
-        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
-};
-static struct clk_lookup lookups[] = {
-        /* main clocks */
-        CLKDEV_CON_ID("r_clk", &r_clk),
-        CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
-        CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
-        CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
-        CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
-        CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
-        CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
-        CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
-        CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
-        /* DIV4 clocks */
-        CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
-        CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
-        CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
-        CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
-        CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
-        CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
-        CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
-        CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
-        CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
-        CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
-        CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
-        CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
-        CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
-        /* DIV6 clocks */
-        CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
-        CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
-        CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
-        CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
-        CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
-        CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
-        CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
-        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
-        CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
-        CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
-        CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
-        CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
-        CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
-        CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
-        CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
-        /* MSTP32 clocks */
-        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
-        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
-        CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
-        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
-        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
-        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
-        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
-        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
-        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
-        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
-        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
-        CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
-        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
-        CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
-        CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
-        CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
-        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
-};
-void __init sh7377_clock_init(void)
-{
-        int k, ret = 0;
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-        if (!ret)
-                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup sh7377 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index d47e215aca87..dfeca79e9e96 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -18,24 +18,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
                              struct cpuidle_driver *drv, int index);
 extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
-extern void sh7367_init_irq(void);
-extern void sh7367_map_io(void);
-extern void sh7367_add_early_devices(void);
-extern void sh7367_add_standard_devices(void);
-extern void sh7367_clock_init(void);
-extern void sh7367_pinmux_init(void);
-extern struct clk sh7367_extalb1_clk;
-extern struct clk sh7367_extal2_clk;
-extern void sh7377_init_irq(void);
-extern void sh7377_map_io(void);
-extern void sh7377_add_early_devices(void);
-extern void sh7377_add_standard_devices(void);
-extern void sh7377_clock_init(void);
-extern void sh7377_pinmux_init(void);
-extern struct clk sh7377_extalc1_clk;
-extern struct clk sh7377_extal2_clk;
 extern void sh7372_init_irq(void);
 extern void sh7372_map_io(void);
 extern void sh7372_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 499f52d2a4a1..8ab0cd6ad6b0 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,7 +71,7 @@ enum {
        GPIO_FN_A19,
        /* IPSR0 */
-        GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+        GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
        GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
        GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
        GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h
deleted file mode 100644
index 52d0de686f68..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sh7367.h
+++ /dev/null
@@ -1,332 +0,0 @@
-#ifndef __ASM_SH7367_H__
-#define __ASM_SH7367_H__
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* 49-1 -> 49-6 (GPIO) */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
-        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
-        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
-        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
-        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
-        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
-        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
-        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
-        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
-        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
-        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
-        GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
-        GPIO_PORT270, GPIO_PORT271, GPIO_PORT272,
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU,
-        GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU,
-        GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU,
-        GPIO_FN_PORT58_KEYIN6_PU,
-        /* 49-1 (FN) */
-        GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2,
-        GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6,
-        GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10,
-        GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2,
-        GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
-        GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2,
-        GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20,
-        GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22,
-        GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
-        GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2,
-        GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK,
-        GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD,
-        GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
-        GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
-        GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
-        /* 49-2 (FN) */
-        GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0,
-        GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK,
-        GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0,
-        GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1,
-        GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2,
-        GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3,
-        GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4,
-        GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5,
-        GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0,
-        GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1,
-        GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2,
-        GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC,
-        GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK,
-        GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD,
-        GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD,
-        GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3,
-        GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4,
-        GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5,
-        GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6,
-        GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1,
-        GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2,
-        GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A,
-        GPIO_FN_XTALB1L,
-        GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK,
-        GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD,
-        GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS,
-        GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0,
-        GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1,
-        GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2,
-        GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3,
-        GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0,
-        GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1,
-        GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2,
-        GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3,
-        GPIO_FN_NMI, GPIO_FN_TPU4TO0,
-        GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3,
-        GPIO_FN_IRQ_TMPB,
-        GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1,
-        GPIO_FN_OVCN, GPIO_FN_MFG1_IN1,
-        GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2,
-        /* 49-3 (FN) */
-        GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2,
-        GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN,
-        GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1,
-        GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2,
-        GPIO_FN_SCIFA5_RXD,
-        GPIO_FN_SCIFA5_TXD,
-        GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1,
-        GPIO_FN_A0_EA0, GPIO_FN_BS,
-        GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0,
-        GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL,
-        GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2,
-        GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3,
-        GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC,
-        GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4,
-        GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5,
-        GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0,
-        GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1,
-        GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC,
-        GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2,
-        GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3,
-        GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4,
-        GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD,
-        GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5,
-        GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL,
-        GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2,
-        GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5,
-        GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8,
-        GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11,
-        GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13,
-        GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15,
-        GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1,
-        GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A,
-        GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD,
-        GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE,
-        GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO,
-        GPIO_FN_NBRSTOUT, GPIO_FN_NBRST,
-        /* 49-4 (FN) */
-        GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD,
-        GPIO_FN_VIO_VD, GPIO_FN_VIO_HD,
-        GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
-        GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
-        GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
-        GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
-        GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
-        GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
-        GPIO_FN_VIO_CKO,
-        GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2,
-        GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0,
-        GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1,
-        GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2,
-        GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3,
-        GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0,
-        GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2,
-        GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1,
-        GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2,
-        GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1,
-        GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3,
-        GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1,
-        GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4,
-        GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2,
-        GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5,
-        GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2,
-        GPIO_FN_LCDD6, GPIO_FN_DV_D6,
-        GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2,
-        GPIO_FN_LCDD7, GPIO_FN_DV_D7,
-        GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
-        GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16,
-        GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17,
-        GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18,
-        GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19,
-        GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20,
-        GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21,
-        GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22,
-        GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23,
-        GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24,
-        GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25,
-        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK,
-        GPIO_FN_D26, GPIO_FN_ED26,
-        GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC,
-        GPIO_FN_D27, GPIO_FN_ED27,
-        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0,
-        GPIO_FN_D28, GPIO_FN_ED28,
-        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1,
-        GPIO_FN_D29, GPIO_FN_ED29,
-        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1,
-        GPIO_FN_D30, GPIO_FN_ED30,
-        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2,
-        GPIO_FN_D31, GPIO_FN_ED31,
-        GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD,
-        GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC,
-        /* 49-5 (FN) */
-        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
-        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK,
-        GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI,
-        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD,
-        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD,
-        GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3,
-        GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7,
-        GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR,
-        GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR,
-        GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0,
-        GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1,
-        GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON,
-        GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS,
-        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD,
-        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2,
-        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2,
-        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD,
-        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2,
-        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2,
-        GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
-        GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
-        GPIO_FN_MSIOF1_SS2,
-        GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT,
-        GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
-        GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3,
-        GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3,
-        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1,
-        GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK,
-        GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC,
-        GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD,
-        GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW,
-        GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1,
-        GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1,
-        GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2,
-        GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD,
-        GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
-        GPIO_FN_SDHICLK0, GPIO_FN_TCK2,
-        GPIO_FN_SDHICD0,
-        GPIO_FN_SDHID0_0, GPIO_FN_TMS2,
-        GPIO_FN_SDHID0_1, GPIO_FN_TDO2,
-        GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
-        GPIO_FN_SDHID0_3, GPIO_FN_RTCK2,
-        /* 49-6 (FN) */
-        GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
-        GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
-        GPIO_FN_SDHICLK1, GPIO_FN_TCK3,
-        GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2,
-        GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3,
-        GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2,
-        GPIO_FN_TS_SDAT2, GPIO_FN_TDO3,
-        GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2,
-        GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
-        GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2,
-        GPIO_FN_TS_SCK2, GPIO_FN_RTCK3,
-        GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
-        GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK,
-        GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD,
-        GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS,
-        GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD,
-        GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS,
-        GPIO_FN_SDHICMD2,
-        GPIO_FN_RESETOUTS,
-        GPIO_FN_DIVLOCK,
-};
-#endif /* __ASM_SH7367_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index eb98b45c5089..b582facc1cf6 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -452,6 +452,10 @@ enum {
        SHDMA_SLAVE_SCIF5_RX,
        SHDMA_SLAVE_SCIF6_TX,
        SHDMA_SLAVE_SCIF6_RX,
+        SHDMA_SLAVE_FLCTL0_TX,
+        SHDMA_SLAVE_FLCTL0_RX,
+        SHDMA_SLAVE_FLCTL1_TX,
+        SHDMA_SLAVE_FLCTL1_RX,
        SHDMA_SLAVE_SDHI0_RX,
        SHDMA_SLAVE_SDHI0_TX,
        SHDMA_SLAVE_SDHI1_RX,
@@ -473,10 +477,6 @@ extern struct clk sh7372_extal2_clk;
 extern struct clk sh7372_dv_clki_clk;
 extern struct clk sh7372_dv_clki_div2_clk;
 extern struct clk sh7372_pllc2_clk;
-extern struct clk sh7372_fsiack_clk;
-extern struct clk sh7372_fsibck_clk;
-extern struct clk sh7372_fsidiva_clk;
-extern struct clk sh7372_fsidivb_clk;
 extern void sh7372_intcs_suspend(void);
 extern void sh7372_intcs_resume(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h
deleted file mode 100644
index f580e227dd1c..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sh7377.h
+++ /dev/null
@@ -1,360 +0,0 @@
-#ifndef __ASM_SH7377_H__
-#define __ASM_SH7377_H__
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* 55-1 -> 55-5 (GPIO) */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
-        GPIO_PORT128, GPIO_PORT129,
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
-        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
-        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
-        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
-        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
-        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
-        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
-        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
-        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
-        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
-        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU,
-        GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU,
-        GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU,
-        GPIO_FN_PORT72_KEYIN6_PU,
-        /* 55-1 (FN) */
-        GPIO_FN_VBUS_0,
-        GPIO_FN_CPORT0,
-        GPIO_FN_CPORT1,
-        GPIO_FN_CPORT2,
-        GPIO_FN_CPORT3,
-        GPIO_FN_CPORT4,
-        GPIO_FN_CPORT5,
-        GPIO_FN_CPORT6,
-        GPIO_FN_CPORT7,
-        GPIO_FN_CPORT8,
-        GPIO_FN_CPORT9,
-        GPIO_FN_CPORT10,
-        GPIO_FN_CPORT11, GPIO_FN_SIN2,
-        GPIO_FN_CPORT12, GPIO_FN_XCTS2,
-        GPIO_FN_CPORT13, GPIO_FN_RFSPO4,
-        GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
-        GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2,
-        GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3,
-        GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2,
-        GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2,
-        GPIO_FN_CPORT19_MPORT1,
-        GPIO_FN_CPORT20, GPIO_FN_RFSPO6,
-        GPIO_FN_CPORT21, GPIO_FN_STATUS0,
-        GPIO_FN_CPORT22, GPIO_FN_STATUS1,
-        GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
-        GPIO_FN_B_SYNLD1,
-        GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK,
-        GPIO_FN_XMAINPS,
-        GPIO_FN_XDIVPS,
-        GPIO_FN_XIDRST,
-        GPIO_FN_IDCLK, GPIO_FN_IC_DP,
-        GPIO_FN_IDIO, GPIO_FN_IC_DM,
-        GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT,
-        GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
-        GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
-        GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
-        GPIO_FN_PCMCLKO,
-        GPIO_FN_SYNC8KO,
-        /* 55-2 (FN) */
-        GPIO_FN_DNPCM_A,
-        GPIO_FN_UPPCM_A,
-        GPIO_FN_VACK,
-        GPIO_FN_XTALB1L,
-        GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_GPS_IM,
-        GPIO_FN_GPS_IS,
-        GPIO_FN_GPS_QM,
-        GPIO_FN_GPS_QS,
-        GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
-        GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3,
-        GPIO_FN_FMSIOLR,
-        GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1,
-        GPIO_FN_FMSIOBT,
-        GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2,
-        GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
-        GPIO_FN_OPORT3, GPIO_FN_FMSIILR,
-        GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
-        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0,
-        GPIO_FN_A0_EA0, GPIO_FN_BS,
-        GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2,
-        GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2,
-        GPIO_FN_TPU0TO1,
-        GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5,
-        GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4,
-        GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
-        GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
-        GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD,
-        GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6,
-        GPIO_FN_D0_ED0_NAF0,
-        GPIO_FN_D1_ED1_NAF1,
-        GPIO_FN_D2_ED2_NAF2,
-        GPIO_FN_D3_ED3_NAF3,
-        GPIO_FN_D4_ED4_NAF4,
-        GPIO_FN_D5_ED5_NAF5,
-        GPIO_FN_D6_ED6_NAF6,
-        GPIO_FN_D7_ED7_NAF7,
-        GPIO_FN_D8_ED8_NAF8,
-        GPIO_FN_D9_ED9_NAF9,
-        GPIO_FN_D10_ED10_NAF10,
-        GPIO_FN_D11_ED11_NAF11,
-        GPIO_FN_D12_ED12_NAF12,
-        GPIO_FN_D13_ED13_NAF13,
-        GPIO_FN_D14_ED14_NAF14,
-        GPIO_FN_D15_ED15_NAF15,
-        GPIO_FN_CS4,
-        GPIO_FN_CS5A, GPIO_FN_FMSICK,
-        GPIO_FN_CS5B, GPIO_FN_FCE1,
-        /* 55-3 (FN) */
-        GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0,
-        GPIO_FN_FCE0,
-        GPIO_FN_WAIT, GPIO_FN_DREQ0,
-        GPIO_FN_RD_XRD,
-        GPIO_FN_WE0_XWR0_FWE,
-        GPIO_FN_WE1_XWR1,
-        GPIO_FN_FRB,
-        GPIO_FN_CKO,
-        GPIO_FN_NBRSTOUT,
-        GPIO_FN_NBRST,
-        GPIO_FN_GPS_EPPSIN,
-        GPIO_FN_LATCHPULSE,
-        GPIO_FN_LTESIGNAL,
-        GPIO_FN_LEGACYSTATE,
-        GPIO_FN_TCKON,
-        GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0,
-        GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1,
-        GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD,
-        GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1,
-        GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2,
-        GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC,
-        GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD,
-        GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK,
-        GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2,
-        GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3,
-        GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC,
-        GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR,
-        GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2,
-        GPIO_FN_PORT140_FSIAOBT,
-        GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3,
-        GPIO_FN_PORT141_FSIAOSLD,
-        GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK,
-        GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR,
-        GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT,
-        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD,
-        GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2,
-        GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5,
-        GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6,
-        GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1,
-        GPIO_FN_MFG0_IN2,
-        GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
-        GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
-        GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
-        GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2,
-        GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD,
-        /* 55-4 (FN) */
-        GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
-        GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
-        GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0,
-        GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0,
-        GPIO_FN_MFG3_IN2,
-        GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0,
-        GPIO_FN_MFG3_IN1,
-        GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0,
-        GPIO_FN_MFG3_OUT1,
-        GPIO_FN_TPU3TO0,
-        GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI,
-        GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS,
-        GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS,
-        GPIO_FN_BBIF2_TSCK1,
-        GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD,
-        GPIO_FN_BBIF2_TXD1,
-        GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD,
-        GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK,
-        GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1,
-        GPIO_FN_LCDD6, GPIO_FN_XWR2,
-        GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
-        GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16,
-        GPIO_FN_ED16,
-        GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17,
-        GPIO_FN_ED17,
-        GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18,
-        GPIO_FN_ED18,
-        GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19,
-        GPIO_FN_ED19,
-        GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20,
-        GPIO_FN_ED20,
-        GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21,
-        GPIO_FN_ED21,
-        GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22,
-        GPIO_FN_ED22,
-        GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0,
-        GPIO_FN_VIO_DR7,
-        GPIO_FN_D23, GPIO_FN_ED23,
-        GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1,
-        GPIO_FN_VIO_VDR,
-        GPIO_FN_D24, GPIO_FN_ED24,
-        GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25,
-        GPIO_FN_ED25,
-        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
-        GPIO_FN_ED26,
-        GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27,
-        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
-        GPIO_FN_ED28,
-        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
-        GPIO_FN_ED29,
-        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
-        GPIO_FN_ED30,
-        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
-        GPIO_FN_ED31,
-        GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3,
-        GPIO_FN_VIO_CLKR,
-        GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC,
-        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
-        GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4,
-        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK,
-        GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5,
-        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD,
-        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN,
-        GPIO_FN_MSIOF0L_TXD,
-        GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
-        GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM,
-        GPIO_FN_PORT226_VIO_CKO2,
-        GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN,
-        GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1,
-        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC,
-        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR,
-        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT,
-        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG,
-        GPIO_FN_PORT233_FSIACK,
-        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD,
-        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2,
-        GPIO_FN_PORT235_FSIAILR,
-        GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT,
-        GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD,
-        GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
-        /* 55-5 (FN) */
-        GPIO_FN_MSIOF1_SS2,
-        GPIO_FN_SCIFA6_TXD,
-        GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1,
-        GPIO_FN_TPU4TO0,
-        GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
-        GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
-        GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS,
-        GPIO_FN_PORT244_MSIOF2_RXD,
-        GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS,
-        GPIO_FN_PORT245_MSIOF2_TXD,
-        GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1,
-        GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
-        GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2,
-        GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
-        GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1,
-        GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0,
-        GPIO_FN_PORT248_MSIOF2_TSCK,
-        GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC,
-        GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0,
-        GPIO_FN_SDHICD0,
-        GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0,
-        GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0,
-        GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
-        GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0,
-        GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
-        GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
-        GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1,
-        GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2,
-        GPIO_FN_TMS3_SWDIO_MC1,
-        GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2,
-        GPIO_FN_TDO3_SWO0_MC1,
-        GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
-        GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2,
-        GPIO_FN_RTCK3_SWO1_MC1,
-        GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
-        GPIO_FN_RESETOUTS,
-};
-#endif /* __ASM_SH7377_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
deleted file mode 100644
index 5bf776495b75..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * sh7367 processor support - INTC hardware block
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/sh_intc.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-enum {
-        UNUSED_INTCA = 0,
-        ENABLED,
-        DISABLED,
-        /* interrupt sources INTCA */
-        DIRC,
-        CRYPT1_ERR, CRYPT2_STD,
-        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
-        ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
-        ETM11_ACQCMP, ETM11_FULL,
-        MFI_MFIM, MFI_MFIS,
-        BBIF1, BBIF2,
-        USBDMAC_USHDMI,
-        USBHS_USHI0, USBHS_USHI1,
-        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
-        KEYSC_KEY,
-        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
-        MSIOF2, MSIOF1,
-        SCIFA4, SCIFA5, SCIFB,
-        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
-        SDHI0,
-        SDHI1,
-        MSU_MSU, MSU_MSU2,
-        IREM,
-        SIU,
-        SPU,
-        IRDA,
-        TPU0, TPU1, TPU2, TPU3, TPU4,
-        LCRC,
-        PINT1, PINT2,
-        TTI20,
-        MISTY,
-        DDM,
-        SDHI2,
-        RWDT0, RWDT1,
-        DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
-        DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
-        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
-        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
-        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
-        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
-        /* interrupt groups INTCA */
-        DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
-        ETM11, ARM11, USBHS, FLCTL, IIC1
-};
-static struct intc_vect intca_vectors[] __initdata = {
-        INTC_VECT(DIRC, 0x0560),
-        INTC_VECT(CRYPT1_ERR, 0x05e0),
-        INTC_VECT(CRYPT2_STD, 0x0700),
-        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
-        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
-        INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
-        INTC_VECT(ARM11_COMMRX, 0x0860),
-        INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
-        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
-        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
-        INTC_VECT(USBDMAC_USHDMI, 0x0a00),
-        INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
-        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
-        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
-        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
-        INTC_VECT(KEYSC_KEY, 0x0be0),
-        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
-        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
-        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
-        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
-        INTC_VECT(SCIFB, 0x0d60),
-        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
-        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
-        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
-        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
-        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
-        INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
-        INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
-        INTC_VECT(IREM, 0x0f60),
-        INTC_VECT(SIU, 0x0fa0),
-        INTC_VECT(SPU, 0x0fc0),
-        INTC_VECT(IRDA, 0x0480),
-        INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
-        INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
-        INTC_VECT(TPU4, 0x0520),
-        INTC_VECT(LCRC, 0x0540),
-        INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
-        INTC_VECT(TTI20, 0x1100),
-        INTC_VECT(MISTY, 0x1120),
-        INTC_VECT(DDM, 0x1140),
-        INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
-        INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
-        INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
-        INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
-        INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
-        INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
-        INTC_VECT(DMAC_2_DADERR, 0x20c0),
-        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
-        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
-        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
-        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
-        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
-        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
-        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
-        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
-};
-static struct intc_group intca_groups[] __initdata = {
-        INTC_GROUP(DMAC_1, DMAC_1_DEI0,
-                   DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
-        INTC_GROUP(DMAC_2, DMAC_2_DEI4,
-                   DMAC_2_DEI5, DMAC_2_DADERR),
-        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
-                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
-        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
-                   DMAC2_2_DEI5, DMAC2_2_DADERR),
-        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
-                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
-        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
-                   DMAC3_2_DEI5, DMAC3_2_DADERR),
-        INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
-        INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
-        INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
-        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
-                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
-        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
-};
-static struct intc_mask_reg intca_mask_registers[] __initdata = {
-        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
-          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
-            ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
-        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
-          { CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
-            DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
-        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
-          { PINT1, PINT2, 0, 0,
-            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
-        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
-          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
-            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
-        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
-          { DDM, 0, 0, 0,
-            0, 0, ETM11_FULL, ETM11_ACQCMP } },
-        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
-          { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
-            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
-        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
-          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
-            0, 0, MSIOF2, 0 } },
-        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
-        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            TTI20, USBDMAC_USHDMI, SPU, SIU } },
-        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
-          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
-            CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
-        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
-          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
-            0, 0, 0, 0 } },
-        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
-          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
-            LCRC, MSU_MSU2, IREM, MSU_MSU } },
-        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
-          { 0, 0, TPU0, TPU1,
-            TPU2, TPU3, TPU4, 0 } },
-        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            MISTY, CMT3, RWDT1, RWDT0 } },
-};
-static struct intc_prio_reg intca_prio_registers[] __initdata = {
-        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
-        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
-        { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
-                                              CMT1_CMT11, ARM11 } },
-        { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
-                                              CMT1_CMT12, TPU4 } },
-        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
-                                              MFI_MFIM, USBHS } },
-        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
-                                              0, CMT1_CMT10 } },
-        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
-                                              SCIFA2, SCIFA3 } },
-        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
-                                              FLCTL, SDHI0 } },
-        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
-        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
-        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
-        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
-        { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
-        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
-        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
-};
-static struct intc_desc intca_desc __initdata = {
-        .name = "sh7367-intca",
-        .force_enable = ENABLED,
-        .force_disable = DISABLED,
-        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
-                           intca_mask_registers, intca_prio_registers,
-                           NULL, NULL),
-};
-INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
-                 INTC_VECT, "sh7367-intca-irq-pins");
-enum {
-        UNUSED_INTCS = 0,
-        INTCS,
-        /* interrupt sources INTCS */
-        VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
-        VIO3_VOU,
-        RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
-        VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
-        VPU,
-        SGX530,
-        _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
-        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
-        IPMMU_IPMMUB, IPMMU_IPMMUS,
-        RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
-        MSIOF,
-        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
-        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
-        CMT,
-        TSIF,
-        IPMMUI,
-        MVI3,
-        ICB,
-        PEP,
-        ASA,
-        BEM,
-        VE2HO,
-        HQE,
-        JPEG,
-        LCDC,
-        /* interrupt groups INTCS */
-        _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
-};
-static struct intc_vect intcs_vectors[] = {
-        INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
-        INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
-        INTCS_VECT(VIO3_VOU, 0x780),
-        INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
-        INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
-        INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
-        INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
-        INTCS_VECT(VPU, 0x980),
-        INTCS_VECT(SGX530, 0x9e0),
-        INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
-        INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
-        INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
-        INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
-        INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
-        INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
-        INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
-        INTCS_VECT(MSIOF, 0xd20),
-        INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
-        INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
-        INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
-        INTCS_VECT(TMU_TUNI2, 0xec0),
-        INTCS_VECT(CMT, 0xf00),
-        INTCS_VECT(TSIF, 0xf20),
-        INTCS_VECT(IPMMUI, 0xf60),
-        INTCS_VECT(MVI3, 0x420),
-        INTCS_VECT(ICB, 0x480),
-        INTCS_VECT(PEP, 0x4a0),
-        INTCS_VECT(ASA, 0x4c0),
-        INTCS_VECT(BEM, 0x4e0),
-        INTCS_VECT(VE2HO, 0x520),
-        INTCS_VECT(HQE, 0x540),
-        INTCS_VECT(JPEG, 0x560),
-        INTCS_VECT(LCDC, 0x580),
-        INTC_VECT(INTCS, 0xf80),
-};
-static struct intc_group intcs_groups[] __initdata = {
-        INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
-                   _2DDMAC_2DDM2, _2DDMAC_2DDM3),
-        INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
-                   RTDMAC_1_DEI2, RTDMAC_1_DEI3),
-        INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
-        INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
-        INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
-        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
-        INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
-        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
-};
-static struct intc_mask_reg intcs_mask_registers[] = {
-        { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
-          { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
-            VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
-        { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
-          { VIO3_VOU, 0, VE2HO, VPU,
-            0, 0, 0, 0 } },
-        { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
-          { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
-            BEM, ASA, PEP, ICB } },
-        { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
-          { 0, 0, MVI3, 0,
-            JPEG, HQE, 0, LCDC } },
-        { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
-          { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
-            RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
-        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
-          { 0, 0, MSIOF, 0,
-            SGX530, 0, 0, 0 } },
-        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
-          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
-            0, 0, 0, 0 } },
-        { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
-          { 0, 0, 0, CMT,
-            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
-        { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
-          { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
-            0, 0, 0, 0 } },
-        { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
-          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
-            0, 0, IPMMUI, TSIF } },
-        { 0xffd20104, 0, 16, /* INTAMASK */
-          { 0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, INTCS } },
-};
-/* Priority is needed for INTCA to receive the INTCS interrupt */
-static struct intc_prio_reg intcs_prio_registers[] = {
-        { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
-        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
-        { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
-        { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
-        { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
-        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
-                                              TMU_TUNI2, 0 } },
-        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
-        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
-        { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
-        { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
-        { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
-        { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
-};
-static struct resource intcs_resources[] __initdata = {
-        [0] = {
-                .start  = 0xffd20000,
-                .end    = 0xffd2ffff,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct intc_desc intcs_desc __initdata = {
-        .name = "sh7367-intcs",
-        .resource = intcs_resources,
-        .num_resources = ARRAY_SIZE(intcs_resources),
-        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
-                           intcs_prio_registers, NULL, NULL),
-};
-static void intcs_demux(unsigned int irq, struct irq_desc *desc)
-{
-        void __iomem *reg = (void *)irq_get_handler_data(irq);
-        unsigned int evtcodeas = ioread32(reg);
-        generic_handle_irq(intcs_evt2irq(evtcodeas));
-}
-void __init sh7367_init_irq(void)
-{
-        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
-        register_intc_controller(&intca_desc);
-        register_intc_controller(&intca_irq_pins_desc);
-        register_intc_controller(&intcs_desc);
-        /* demux using INTEVTSA */
-        irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
-        irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
-}
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
deleted file mode 100644
index b84a460a3405..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * sh7377 processor support - INTC hardware block
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/sh_intc.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-enum {
-        UNUSED_INTCA = 0,
-        ENABLED,
-        DISABLED,
-        /* interrupt sources INTCA */
-        DIRC,
-        _2DG,
-        CRYPT_STD,
-        IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
-        AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
-        MFI_MFIM, MFI_MFIS,
-        BBIF1, BBIF2,
-        USBDMAC_USHDMI,
-        USBHS_USHI0, USBHS_USHI1,
-        _3DG_SGX540,
-        CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
-        KEYSC_KEY,
-        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
-        MSIOF2, MSIOF1,
-        SCIFA4, SCIFA5, SCIFB,
-        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
-        SDHI0,
-        SDHI1,
-        MSU_MSU, MSU_MSU2,
-        IRREM,
-        MSUG,
-        IRDA,
-        TPU0, TPU1, TPU2, TPU3, TPU4,
-        LCRC,
-        PINTCA_PINT1, PINTCA_PINT2,
-        TTI20,
-        MISTY,
-        DDM,
-        RWDT0, RWDT1,
-        DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
-        DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
-        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
-        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
-        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
-        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
-        SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
-        ICUSB_ICUSB0, ICUSB_ICUSB1,
-        ICUDMC_ICUDMC1, ICUDMC_ICUDMC2,
-        SPU2_SPU0, SPU2_SPU1,
-        FSI,
-        FMSI,
-        SCUV,
-        IPMMU_IPMMUB,
-        AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
-        MFIS2,
-        CPORTR2S,
-        CMT14, CMT15,
-        SCIFA6,
-        /* interrupt groups INTCA */
-        DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
-        AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
-        ICUSB, ICUDMC
-};
-static struct intc_vect intca_vectors[] __initdata = {
-        INTC_VECT(DIRC, 0x0560),
-        INTC_VECT(_2DG, 0x05e0),
-        INTC_VECT(CRYPT_STD, 0x0700),
-        INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
-        INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
-        INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
-        INTC_VECT(AP_ARM_COMMRX, 0x0860),
-        INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
-        INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
-        INTC_VECT(USBDMAC_USHDMI, 0x0a00),
-        INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
-        INTC_VECT(_3DG_SGX540, 0x0a60),
-        INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
-        INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
-        INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
-        INTC_VECT(KEYSC_KEY, 0x0be0),
-        INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
-        INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
-        INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
-        INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
-        INTC_VECT(SCIFB, 0x0d60),
-        INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
-        INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
-        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
-        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
-        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
-        INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
-        INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
-        INTC_VECT(IRREM, 0x0f60),
-        INTC_VECT(MSUG, 0x0fa0),
-        INTC_VECT(IRDA, 0x0480),
-        INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
-        INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
-        INTC_VECT(TPU4, 0x0520),
-        INTC_VECT(LCRC, 0x0540),
-        INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020),
-        INTC_VECT(TTI20, 0x1100),
-        INTC_VECT(MISTY, 0x1120),
-        INTC_VECT(DDM, 0x1140),
-        INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
-        INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
-        INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
-        INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
-        INTC_VECT(DMAC_2_DADERR, 0x20c0),
-        INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
-        INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
-        INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
-        INTC_VECT(DMAC2_2_DADERR, 0x21c0),
-        INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
-        INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
-        INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
-        INTC_VECT(DMAC3_2_DADERR, 0x22c0),
-        INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
-        INTC_VECT(SHWYSTAT_COM, 0x1340),
-        INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720),
-        INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0),
-        INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
-        INTC_VECT(FSI, 0x1840),
-        INTC_VECT(FMSI, 0x1860),
-        INTC_VECT(SCUV, 0x1880),
-        INTC_VECT(IPMMU_IPMMUB, 0x1900),
-        INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
-        INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
-        INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
-        INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
-        INTC_VECT(MFIS2, 0x1a00),
-        INTC_VECT(CPORTR2S, 0x1a20),
-        INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
-        INTC_VECT(SCIFA6, 0x1a80),
-};
-static struct intc_group intca_groups[] __initdata = {
-        INTC_GROUP(DMAC_1, DMAC_1_DEI0,
-                   DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
-        INTC_GROUP(DMAC_2, DMAC_2_DEI4,
-                   DMAC_2_DEI5, DMAC_2_DADERR),
-        INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
-                   DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
-        INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
-                   DMAC2_2_DEI5, DMAC2_2_DADERR),
-        INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
-                   DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
-        INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
-                   DMAC3_2_DEI5, DMAC3_2_DADERR),
-        INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
-        INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
-        INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
-        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
-                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
-        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
-        INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
-        INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
-        INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
-};
-static struct intc_mask_reg intca_mask_registers[] __initdata = {
-        { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
-          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
-            AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
-        { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
-          { _2DG, CRYPT_STD, DIRC, 0,
-            DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
-        { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
-          { PINTCA_PINT1, PINTCA_PINT2, 0, 0,
-            BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
-        { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
-          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
-            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
-        { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
-          { DDM, 0, 0, 0,
-            0, 0, 0, 0 } },
-        { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
-          { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
-            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
-        { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
-          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
-            0, 0, MSIOF2, 0 } },
-        { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
-        { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
-            TTI20, USBDMAC_USHDMI, 0, MSUG } },
-        { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
-          { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
-            CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } },
-        { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
-          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
-            0, 0, 0, 0 } },
-        { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
-          { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
-            LCRC, MSU_MSU2, IRREM, MSU_MSU } },
-        { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
-          { 0, 0, TPU0, TPU1,
-            TPU2, TPU3, TPU4, 0 } },
-        { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
-          { 0, 0, 0, 0,
-            MISTY, CMT3, RWDT1, RWDT0 } },
-        { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
-          { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
-            0, 0, 0, 0 } },
-        { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
-          { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0,
-            ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } },
-        { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
-          { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
-            SCUV, 0, 0, 0 } },
-        { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
-          { IPMMU_IPMMUB, 0, 0, 0,
-            AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
-            AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
-        { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
-          { MFIS2, CPORTR2S, CMT14, CMT15,
-            SCIFA6, 0, 0, 0 } },
-};
-static struct intc_prio_reg intca_prio_registers[] __initdata = {
-        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
-        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
-        { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
-                                              CMT1_CMT11, AP_ARM1 } },
-        { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2,
-                                              CMT1_CMT12, TPU4 } },
-        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
-                                              MFI_MFIM, USBHS } },
-        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
-                                              _3DG_SGX540, CMT1_CMT10 } },
-        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
-                                              SCIFA2, SCIFA3 } },
-        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
-                                              FLCTL, SDHI0 } },
-        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
-        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } },
-        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
-        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
-        { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
-        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
-        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } },
-        { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
-        { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } },
-        { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } },
-        { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
-        { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } },
-        { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } },
-        { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
-        { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
-                                               CMT14, CMT15 } },
-        { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
-};
-static struct intc_desc intca_desc __initdata = {
-        .name = "sh7377-intca",
-        .force_enable = ENABLED,
-        .force_disable = DISABLED,
-        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
-                           intca_mask_registers, intca_prio_registers,
-                           NULL, NULL),
-};
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
-                 INTC_VECT, "sh7377-intca-irq-pins");
-/* this macro ignore entry which is also in INTCA */
-#define __IGNORE(a...)
-#define __IGNORE0(a...) 0
-enum {
-        UNUSED_INTCS = 0,
-        INTCS,
-        /* interrupt sources INTCS */
-        VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
-        RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
-        CEU,
-        BEU_BEU0, BEU_BEU1, BEU_BEU2,
-        __IGNORE(MFI)
-        __IGNORE(BBIF2)
-        VPU,
-        TSIF1,
-        __IGNORE(SGX540)
-        _2DDMAC,
-        IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
-        IPMMU_IPMMUR, IPMMU_IPMMUR2,
-        RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
-        __IGNORE(KEYSC)
-        __IGNORE(TTI20)
-        __IGNORE(MSIOF)
-        IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
-        TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
-        CMT0,
-        TSIF0,
-        __IGNORE(CMT2)
-        LMB,
-        __IGNORE(MSUG)
-        __IGNORE(MSU_MSU, MSU_MSU2)
-        __IGNORE(CTI)
-        MVI3,
-        __IGNORE(RWDT0)
-        __IGNORE(RWDT1)
-        ICB,
-        PEP,
-        ASA,
-        __IGNORE(_2DG)
-        HQE,
-        JPU,
-        LCDC0,
-        __IGNORE(LCRC)
-        RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
-        RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
-        FRC,
-        LCDC1,
-        CSIRX,
-        DSITX_DSITX0, DSITX_DSITX1,
-        __IGNORE(SPU2_SPU0, SPU2_SPU1)
-        __IGNORE(FSI)
-        __IGNORE(FMSI)
-        __IGNORE(SCUV)
-        TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
-        TSIF2,
-        CMT4,
-        __IGNORE(MFIS2)
-        CPORTS2R,
-        /* interrupt groups INTCS */
-        RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
-        IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
-};
-#define INTCS_INTVECT 0x0F80
-static struct intc_vect intcs_vectors[] __initdata = {
-        INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
-        INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
-        INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
-        INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
-        INTCS_VECT(CEU, 0x0880),
-        INTCS_VECT(BEU_BEU0, 0x08A0),
-        INTCS_VECT(BEU_BEU1, 0x08C0),
-        INTCS_VECT(BEU_BEU2, 0x08E0),
-        __IGNORE(INTCS_VECT(MFI, 0x0900))
-        __IGNORE(INTCS_VECT(BBIF2, 0x0960))
-        INTCS_VECT(VPU, 0x0980),
-        INTCS_VECT(TSIF1, 0x09A0),
-        __IGNORE(INTCS_VECT(SGX540, 0x09E0))
-        INTCS_VECT(_2DDMAC, 0x0A00),
-        INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
-        INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
-        INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
-        INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
-        INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
-        INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
-        __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
-        __IGNORE(INTCS_VECT(TTI20, 0x0C80))
-        __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
-        INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
-        INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
-        INTCS_VECT(TMU_TUNI0, 0x0E80),
-        INTCS_VECT(TMU_TUNI1, 0x0EA0),
-        INTCS_VECT(TMU_TUNI2, 0x0EC0),
-        INTCS_VECT(CMT0, 0x0F00),
-        INTCS_VECT(TSIF0, 0x0F20),
-        __IGNORE(INTCS_VECT(CMT2, 0x0F40))
-        INTCS_VECT(LMB, 0x0F60),
-        __IGNORE(INTCS_VECT(MSUG, 0x0F80))
-        __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
-        __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
-        __IGNORE(INTCS_VECT(CTI, 0x0400))
-        INTCS_VECT(MVI3, 0x0420),
-        __IGNORE(INTCS_VECT(RWDT0, 0x0440))
-        __IGNORE(INTCS_VECT(RWDT1, 0x0460))
-        INTCS_VECT(ICB, 0x0480),
-        INTCS_VECT(PEP, 0x04A0),
-        INTCS_VECT(ASA, 0x04C0),
-        __IGNORE(INTCS_VECT(_2DG, 0x04E0))
-        INTCS_VECT(HQE, 0x0540),
-        INTCS_VECT(JPU, 0x0560),
-        INTCS_VECT(LCDC0, 0x0580),
-        __IGNORE(INTCS_VECT(LCRC, 0x05A0))
-        INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
-        INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
-        INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
-        INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
-        INTCS_VECT(FRC, 0x1700),
-        INTCS_VECT(LCDC1, 0x1780),
-        INTCS_VECT(CSIRX, 0x17A0),
-        INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
-        __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
-        __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
-        __IGNORE(INTCS_VECT(FSI, 0x1840))
-        __IGNORE(INTCS_VECT(FMSI, 0x1860))
-        __IGNORE(INTCS_VECT(SCUV, 0x1880))
-        INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
-        INTCS_VECT(TMU1_TUNI12, 0x1940),
-        INTCS_VECT(TSIF2, 0x1960),
-        INTCS_VECT(CMT4, 0x1980),
-        __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
-        INTCS_VECT(CPORTS2R, 0x1A20),
-        INTC_VECT(INTCS, INTCS_INTVECT),
-};
-static struct intc_group intcs_groups[] __initdata = {
-        INTC_GROUP(RTDMAC1_1,
-                   RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
-                   RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
-        INTC_GROUP(RTDMAC1_2,
-                   RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
-        INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
-        INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
-        INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
-        __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
-        INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
-        INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
-        INTC_GROUP(RTDMAC2_1,
-                   RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
-                   RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
-        INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
-        INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
-        __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
-        INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
-};
-static struct intc_mask_reg intcs_mask_registers[] __initdata = {
-        { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS  */
-          { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
-            VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
-        { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
-          { 0, 0, 0, VPU,
-            __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
-        { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
-          { 0, 0, 0, _2DDMAC,
-            __IGNORE0(_2DG), ASA, PEP, ICB } },
-        { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
-          { 0, 0, MVI3, __IGNORE0(CTI),
-            JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
-        { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
-          { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
-            RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
-        __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
-          { 0, 0, MSIOF, 0,
-            SGX540, 0, TTI20, 0 } })
-        { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
-          { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
-            0, 0, 0, 0 } },
-        __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
-          { 0, 0, 0, 0,
-            0, MSU_MSU, MSU_MSU2, MSUG } })
-        { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
-          { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
-            IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
-        { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
-          { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
-            0, 0, 0, 0 } },
-        { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
-          { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
-            0, TSIF1, LMB, TSIF0 } },
-        { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
-          { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
-            RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
-        { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
-          { FRC, 0, 0, 0,
-            LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
-        __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
-          {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
-           SCUV, 0, 0, 0 } })
-        { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
-          { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
-            CMT4, 0, 0, 0 } },
-        { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
-          { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
-            0, 0, 0, 0 } },
-        { 0xFFD20104, 0, 16, /* INTAMASK */
-          { 0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, INTCS } }
-};
-static struct intc_prio_reg intcs_prio_registers[] __initdata = {
-        /* IPRAS */
-        { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
-        /* IPRBS */
-        { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
-        /* IPRCS */
-        __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
-        /* IPRES */
-        { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
-        /* IPRFS */
-        { 0xFFD20014, 0, 16, 4,
-          { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
-        /* IPRGS */
-        { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
-        /* IPRHS */
-        { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
-        /* IPRIS */
-        { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
-        /* IPRJS */
-        __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
-        /* IPRKS */
-        { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
-        /* IPRLS */
-        { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
-        /* IPRMS */
-        { 0xFFD20030, 0, 16, 4,
-          { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
-        /* IPRAS3 */
-        { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
-        /* IPRBS3 */
-        { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
-        /* IPRIS3 */
-        { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
-        /* IPRJS3 */
-        { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
-        /* IPRKS3 */
-        __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
-        /* IPRLS3 */
-        __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
-        /* IPRMS3 */
-        { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
-        /* IPRNS3 */
-        { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
-        /* IPROS3 */
-        { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
-};
-static struct resource intcs_resources[] __initdata = {
-        [0] = {
-                .start  = 0xffd20000,
-                .end    = 0xffd500ff,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct intc_desc intcs_desc __initdata = {
-        .name = "sh7377-intcs",
-        .resource = intcs_resources,
-        .num_resources = ARRAY_SIZE(intcs_resources),
-        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
-                           intcs_mask_registers, intcs_prio_registers,
-                           NULL, NULL),
-};
-static void intcs_demux(unsigned int irq, struct irq_desc *desc)
-{
-        void __iomem *reg = (void *)irq_get_handler_data(irq);
-        unsigned int evtcodeas = ioread32(reg);
-        generic_handle_irq(intcs_evt2irq(evtcodeas));
-}
-#define INTEVTSA 0xFFD20100
-void __init sh7377_init_irq(void)
-{
-        void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
-        register_intc_controller(&intca_desc);
-        register_intc_controller(&intca_irq_pins_desc);
-        register_intc_controller(&intcs_desc);
-        /* demux using INTEVTSA */
-        irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
-        irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
-}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index cbc26ba2a0a2..9513234d322b 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -140,7 +140,7 @@ enum {
        FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
        FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
        FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-        FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
+        FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
        FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
        /* GPSR5 */
@@ -176,7 +176,7 @@ enum {
        FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
        FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
        FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-        FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+        FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
        FN_SCIF_CLK, FN_TCLK0_C,
        /* IPSR1 */
@@ -447,7 +447,7 @@ enum {
        A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
        BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
        ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-        PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+        USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
        SCIF_CLK_MARK, TCLK0_C_MARK,
        EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
        PINMUX_DATA(A18_MARK, FN_A18),
        PINMUX_DATA(A19_MARK, FN_A19),
-        PINMUX_IPSR_DATA(IP0_2_0, PENC2),
+        PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
        PINMUX_IPSR_DATA(IP0_2_0, PWM1),
        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
@@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(A19),
        /* IPSR0 */
-        GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+        GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
        GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
        GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
        GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
@@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_4_30_FN, FN_IP8_18,
                GP_4_29_FN, FN_IP8_17_16,
                GP_4_28_FN, FN_IP0_2_0,
-                GP_4_27_FN, FN_PENC1,
+                GP_4_27_FN, FN_USB_PENC1,
-                GP_4_26_FN, FN_PENC0,
+                GP_4_26_FN, FN_USB_PENC0,
                GP_4_25_FN, FN_IP8_15_12,
                GP_4_24_FN, FN_IP8_11_8,
                GP_4_23_FN, FN_IP8_7_4,
@@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
                FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
                /* IP0_2_0 [3] */
-                FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+                FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
                FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
        },
        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
deleted file mode 100644
index c0c137f39052..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ /dev/null
@@ -1,1727 +0,0 @@
-/*
- * sh7367 processor support - PFC hardware block
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/sh7367.h>
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx),           \
-        PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx),    \
-        PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),   \
-        PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),   \
-        PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),   \
-        PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx),   \
-        PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
-        PINMUX_DATA_END,
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
-        PINMUX_INPUT_END,
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
-        PINMUX_INPUT_PULLUP_END,
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
-        PINMUX_INPUT_PULLDOWN_END,
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
-        PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
-        PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
-        PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
-        PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
-        PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
-        PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
-        PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
-        PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
-        PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
-        MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* Special Pull-up / Pull-down Functions */
-        PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
-        PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
-        PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
-        PORT58_KEYIN6_PU_MARK,
-        /* 49-1 */
-        VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
-        CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
-        CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
-        CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
-        CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
-        CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
-        CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
-        RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
-        STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
-        MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
-        XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
-        IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
-        M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
-        XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
-        XCTS1_MARK, SCIFA4_CTS_MARK,
-        /* 49-2 */
-        HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
-        HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
-        HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
-        HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
-        HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
-        HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
-        HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
-        HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
-        HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
-        HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
-        HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
-        HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
-        HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
-        HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
-        HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
-        HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
-        B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
-        HSU_SDI_MARK, PORT55_KEYIN3_MARK,
-        HSU_SCO_MARK, PORT56_KEYIN4_MARK,
-        HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
-        HSU_DACK_MARK, PORT58_KEYIN6_MARK,
-        HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
-        HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
-        PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
-        XTALB1L_MARK,
-        GPS_AGC1_MARK, SCIFA0_RTS_MARK,
-        GPS_AGC2_MARK, SCIFA0_SCK_MARK,
-        GPS_AGC3_MARK, SCIFA0_TXD_MARK,
-        GPS_AGC4_MARK, SCIFA0_RXD_MARK,
-        GPS_PWRD_MARK, SCIFA0_CTS_MARK,
-        GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
-        SIUBOMC_MARK, TPU2TO0_MARK,
-        SIUCKB_MARK, TPU2TO1_MARK,
-        SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
-        SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
-        SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
-        SIUBILR_MARK, TPU3TO1_MARK,
-        SIUBIBT_MARK, TPU3TO2_MARK,
-        SIUBISLD_MARK, TPU3TO3_MARK,
-        NMI_MARK, TPU4TO0_MARK,
-        DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
-        IRQ_TMPB_MARK,
-        PWEN_MARK, MFG1_OUT1_MARK,
-        OVCN_MARK, MFG1_IN1_MARK,
-        OVCN2_MARK, MFG1_IN2_MARK,
-        /* 49-3 */
-        RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
-        USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
-        SCIFA5_CTS_MARK, MFG0_IN1_MARK,
-        SCIFA5_RTS_MARK, MFG0_IN2_MARK,
-        SCIFA5_RXD_MARK,
-        SCIFA5_TXD_MARK,
-        SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
-        A0_EA0_MARK, BS_MARK,
-        A14_EA14_MARK, PORT102_KEYOUT0_MARK,
-        A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
-        A16_EA16_MARK, PORT104_KEYOUT2_MARK,
-        DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
-        A17_EA17_MARK, PORT105_KEYOUT3_MARK,
-        DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
-        A18_EA18_MARK, PORT106_KEYOUT4_MARK,
-        DV_DL0_MARK, MSIOF0_TSCK_MARK,
-        A19_EA19_MARK, PORT107_KEYOUT5_MARK,
-        DV_DL1_MARK, MSIOF0_TXD_MARK,
-        A20_EA20_MARK, PORT108_KEYIN0_MARK,
-        DV_DL2_MARK, MSIOF0_RSCK_MARK,
-        A21_EA21_MARK, PORT109_KEYIN1_MARK,
-        DV_DL3_MARK, MSIOF0_RSYNC_MARK,
-        A22_EA22_MARK, PORT110_KEYIN2_MARK,
-        DV_DL4_MARK, MSIOF0_MCK0_MARK,
-        A23_EA23_MARK, PORT111_KEYIN3_MARK,
-        DV_DL5_MARK, MSIOF0_MCK1_MARK,
-        A24_EA24_MARK, PORT112_KEYIN4_MARK,
-        DV_DL6_MARK, MSIOF0_RXD_MARK,
-        A25_EA25_MARK, PORT113_KEYIN5_MARK,
-        DV_DL7_MARK, MSIOF0_SS2_MARK,
-        A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
-        D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
-        D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
-        D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
-        D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
-        D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
-        D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
-        CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
-        CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
-        DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
-        A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
-        WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
-        NBRSTOUT_MARK, NBRST_MARK,
-        /* 49-4 */
-        RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
-        VIO_VD_MARK, VIO_HD_MARK,
-        VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
-        VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
-        VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
-        VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
-        VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
-        VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
-        VIO_CKO_MARK,
-        MFG3_IN1_MARK, MFG3_IN2_MARK,
-        M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
-        M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
-        M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
-        M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
-        LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
-        SIUCKA_MARK, MFG0_OUT2_MARK,
-        LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
-        SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
-        LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
-        SIUAOBT_MARK, BBIF2_TSCK1_MARK,
-        LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
-        SIUAOSLD_MARK, BBIF2_TXD1_MARK,
-        LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
-        SIUAISPD_MARK, MFG1_OUT2_MARK,
-        LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
-        SIUAILR_MARK, MFG2_OUT2_MARK,
-        LCDD6_MARK, DV_D6_MARK,
-        SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
-        LCDD7_MARK, DV_D7_MARK,
-        SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
-        LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
-        LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
-        LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
-        LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
-        LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
-        LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
-        LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
-        LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
-        LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
-        LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
-        LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
-        D26_MARK, ED26_MARK,
-        LCDD19_MARK, MSIOF0L_TSYNC_MARK,
-        D27_MARK, ED27_MARK,
-        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
-        D28_MARK, ED28_MARK,
-        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
-        D29_MARK, ED29_MARK,
-        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
-        D30_MARK, ED30_MARK,
-        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
-        D31_MARK, ED31_MARK,
-        LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
-        LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
-        /* 49-5 */
-        LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
-        LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
-        LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
-        LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
-        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
-        VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
-        VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
-        VIO_VDR_MARK, VIO_HDR_MARK,
-        VIO_CLKR_MARK, VIO_CKOR_MARK,
-        SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
-        SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
-        SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
-        SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
-        MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
-        MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
-        MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
-        MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
-        MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
-        MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
-        MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
-        MSIOF1_SS1_MARK, EDBGREQ3_MARK,
-        MSIOF1_SS2_MARK,
-        PORT236_IROUT_MARK, IRDA_OUT_MARK,
-        IRDA_IN_MARK, IRDA_FIRSEL_MARK,
-        TPU1TO0_MARK, TS_SPSYNC3_MARK,
-        TPU1TO1_MARK, TS_SDAT3_MARK,
-        TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
-        TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
-        M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
-        M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
-        PORT245_IROUT_MARK, M15_RSW_MARK,
-        SOUT3_MARK, SCIFA2_TXD1_MARK,
-        SIN3_MARK, SCIFA2_RXD1_MARK,
-        XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
-        XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
-        DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
-        SDHICLK0_MARK, TCK2_MARK,
-        SDHICD0_MARK,
-        SDHID0_0_MARK, TMS2_MARK,
-        SDHID0_1_MARK, TDO2_MARK,
-        SDHID0_2_MARK, TDI2_MARK,
-        SDHID0_3_MARK, RTCK2_MARK,
-        /* 49-6 */
-        SDHICMD0_MARK, TRST2_MARK,
-        SDHIWP0_MARK, EDBGREQ2_MARK,
-        SDHICLK1_MARK, TCK3_MARK,
-        SDHID1_0_MARK, M11_SLCD_SO2_MARK,
-        TS_SPSYNC2_MARK, TMS3_MARK,
-        SDHID1_1_MARK, M9_SLCD_AO2_MARK,
-        TS_SDAT2_MARK, TDO3_MARK,
-        SDHID1_2_MARK, M10_SLCD_CK2_MARK,
-        TS_SDEN2_MARK, TDI3_MARK,
-        SDHID1_3_MARK, M12_SLCD_CE2_MARK,
-        TS_SCK2_MARK, RTCK3_MARK,
-        SDHICMD1_MARK, TRST3_MARK,
-        SDHICLK2_MARK, SCIFB_SCK_MARK,
-        SDHID2_0_MARK, SCIFB_TXD_MARK,
-        SDHID2_1_MARK, SCIFB_CTS_MARK,
-        SDHID2_2_MARK, SCIFB_RXD_MARK,
-        SDHID2_3_MARK, SCIFB_RTS_MARK,
-        SDHICMD2_MARK,
-        RESETOUTS_MARK,
-        DIVLOCK_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        /* 49-1 (GPIO) */
-        PORT_DATA_I_PD(0),
-        PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
-        PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
-        PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
-        PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
-        PORT_DATA_I_PU(13),
-        PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
-        PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
-        PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
-        PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
-        PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
-        PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
-        PORT_DATA_IO_PU(33),
-        PORT_DATA_O(34),
-        PORT_DATA_I_PU(35),
-        PORT_DATA_O(36),
-        PORT_DATA_I_PU_PD(37),
-        /* 49-2 (GPIO) */
-        PORT_DATA_IO_PU_PD(38),
-        PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
-        PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
-        PORT_DATA_O(46), PORT_DATA_O(47),
-        PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
-        PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
-        PORT_DATA_O(53),
-        PORT_DATA_IO_PD(54),
-        PORT_DATA_I_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),
-        PORT_DATA_I_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),
-        PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
-        PORT_DATA_O(63),
-        PORT_DATA_I_PU(64),
-        PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
-        PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
-        PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
-        PORT_DATA_I_PD(74),
-        PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
-        PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
-        PORT_DATA_O(79),
-        PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
-        PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
-        PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
-        PORT_DATA_I_PD(87),
-        PORT_DATA_IO_PU_PD(88),
-        PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
-        /* 49-3 (GPIO) */
-        PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
-        PORT_DATA_I_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
-        PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
-        PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
-        PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
-        PORT_DATA_IO_PD(107),
-        PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
-        PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
-        PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
-        PORT_DATA_IO_PU_PD(114),
-        PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
-        PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
-        PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
-        PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
-        PORT_DATA_IO_PU(130),
-        PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
-        PORT_DATA_IO_PU(134),
-        PORT_DATA_O(135), PORT_DATA_O(136),
-        PORT_DATA_I_PU_PD(137),
-        PORT_DATA_IO(138),
-        PORT_DATA_IO_PU_PD(139),
-        PORT_DATA_IO(140), PORT_DATA_IO(141),
-        PORT_DATA_I_PU(142),
-        PORT_DATA_O(143), PORT_DATA_O(144),
-        PORT_DATA_I_PU(145),
-        /* 49-4 (GPIO) */
-        PORT_DATA_O(146),
-        PORT_DATA_I_PU_PD(147),
-        PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
-        PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
-        PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
-        PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
-        PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
-        PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
-        PORT_DATA_IO_PU_PD(167),
-        PORT_DATA_O(168),
-        PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
-        PORT_DATA_O(171),
-        PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
-        PORT_DATA_O(174),
-        PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
-        PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
-        PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
-        PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
-        PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
-        PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
-        PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
-        PORT_DATA_O(199),
-        PORT_DATA_IO_PD(200),
-        /* 49-5 (GPIO) */
-        PORT_DATA_O(201),
-        PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
-        PORT_DATA_I(204),
-        PORT_DATA_O(205),
-        PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
-        PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
-        PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
-        PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
-        PORT_DATA_O(217),
-        PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
-        PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
-        PORT_DATA_I_PD(223),
-        PORT_DATA_I_PU_PD(224),
-        PORT_DATA_O(225),
-        PORT_DATA_IO_PD(226),
-        PORT_DATA_IO_PU_PD(227),
-        PORT_DATA_I_PD(228),
-        PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
-        PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
-        PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
-        PORT_DATA_I_PU_PD(235),
-        PORT_DATA_O(236),
-        PORT_DATA_I_PD(237),
-        PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
-        PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
-        PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
-        PORT_DATA_O(244),
-        PORT_DATA_IO_PU_PD(245),
-        PORT_DATA_O(246),
-        PORT_DATA_I_PD(247),
-        PORT_DATA_IO_PU_PD(248),
-        PORT_DATA_I_PU_PD(249),
-        PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
-        PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
-        PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
-        PORT_DATA_IO_PU_PD(256),
-        /* 49-6 (GPIO) */
-        PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
-        PORT_DATA_IO_PD(259),
-        PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
-        PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
-        PORT_DATA_O(265),
-        PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
-        PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
-        PORT_DATA_O(271),
-        PORT_DATA_I_PD(272),
-        /* Special Pull-up / Pull-down Functions */
-        PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT48_FN2, PORT48_IN_PU),
-        PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT49_FN2, PORT49_IN_PU),
-        PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT50_FN2, PORT50_IN_PU),
-        PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT55_FN2, PORT55_IN_PU),
-        PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT56_FN2, PORT56_IN_PU),
-        PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT57_FN2, PORT57_IN_PU),
-        PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
-                    PORT58_FN2, PORT58_IN_PU),
-        /* 49-1 (FN) */
-        PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
-        PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
-        PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
-        PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
-        PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
-        PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
-        PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
-        PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
-        PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
-        PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
-        PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
-        PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
-        PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
-        PINMUX_DATA(SIN2_MARK, PORT12_FN2),
-        PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
-        PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
-        PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
-        PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
-        PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
-        PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
-        PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
-        PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
-        PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
-        PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
-        PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
-        PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
-        PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
-        PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
-        PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
-        PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
-        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
-        PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
-        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
-        PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
-        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
-        PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
-        PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
-        PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
-        PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
-        PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
-        PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
-        PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
-        PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
-        PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
-        PINMUX_DATA(IDIO_MARK, PORT33_FN1),
-        PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
-        PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
-        PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
-        PINMUX_DATA(SIN1_MARK, PORT35_FN1),
-        PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
-        PINMUX_DATA(XWUP_MARK, PORT35_FN3),
-        PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
-        PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
-        PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
-        PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
-        PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
-        /* 49-2 (FN) */
-        PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
-        PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
-        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
-        PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
-        PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
-        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
-        PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
-        PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
-        PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
-        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
-        PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
-        PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
-        PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
-        PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
-        PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
-        PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
-        PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
-        PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
-        PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
-        PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
-        PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
-        PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
-        PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
-        PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
-        PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
-        PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
-        PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
-        PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
-        PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
-        PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
-        PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
-        PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
-        PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
-        PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
-        PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
-        PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
-        PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
-        PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
-        PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
-        PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
-        PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
-        PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
-        PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
-        PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
-        PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
-        PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
-        PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
-        PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
-        PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
-        PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
-        PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
-        PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
-        PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
-        PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
-        PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
-        PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
-        PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
-        PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
-        PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
-        PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
-        PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
-        PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
-        PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
-        PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
-        PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
-        PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
-        PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
-        PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
-        PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
-        PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
-        PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
-        PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
-        PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
-        PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
-        PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
-        PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
-        PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
-        PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
-        PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
-        PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
-        PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
-        PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
-        PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
-        PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
-        PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
-        PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
-        PINMUX_DATA(NMI_MARK, PORT83_FN1),
-        PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
-        PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
-        PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
-        PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
-        PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
-        PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
-        PINMUX_DATA(PWEN_MARK, PORT88_FN1),
-        PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
-        PINMUX_DATA(OVCN_MARK, PORT89_FN1),
-        PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
-        PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
-        PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
-        /* 49-3 (FN) */
-        PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
-        PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
-        PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
-        PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
-        PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
-        PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
-        PINMUX_DATA(IDIN_MARK, PORT95_FN1),
-        PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
-        PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
-        PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
-        PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
-        PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
-        PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
-        PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
-        PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
-        PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
-        PINMUX_DATA(BS_MARK, PORT101_FN2),
-        PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
-        PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
-        PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
-        PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
-        PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
-        PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
-        PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
-        PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
-        PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
-        PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
-        PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
-        PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
-        PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
-        PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
-        PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
-        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
-        PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
-        PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
-        PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
-        PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
-        PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
-        PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
-        PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
-        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
-        PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
-        PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
-        PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
-        PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
-        PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
-        PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
-        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
-        PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
-        PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
-        PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
-        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
-        PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
-        PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
-        PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
-        PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
-        PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
-        PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
-        PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
-        PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
-        PINMUX_DATA(A26_MARK, PORT114_FN1),
-        PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
-        PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
-        PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
-        PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
-        PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
-        PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
-        PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
-        PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
-        PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
-        PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
-        PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
-        PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
-        PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
-        PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
-        PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
-        PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
-        PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
-        PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
-        PINMUX_DATA(CS4_MARK, PORT131_FN1),
-        PINMUX_DATA(CS5A_MARK, PORT132_FN1),
-        PINMUX_DATA(CS5B_MARK, PORT133_FN1),
-        PINMUX_DATA(FCE1_MARK, PORT133_FN2),
-        PINMUX_DATA(CS6B_MARK, PORT134_FN1),
-        PINMUX_DATA(XCS2_MARK, PORT134_FN2),
-        PINMUX_DATA(FCE0_MARK, PORT135_FN1),
-        PINMUX_DATA(CS6A_MARK, PORT136_FN1),
-        PINMUX_DATA(DACK0_MARK, PORT136_FN2),
-        PINMUX_DATA(WAIT_MARK, PORT137_FN1),
-        PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
-        PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
-        PINMUX_DATA(A27_MARK, PORT139_FN1),
-        PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
-        PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
-        PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
-        PINMUX_DATA(FRB_MARK, PORT142_FN1),
-        PINMUX_DATA(CKO_MARK, PORT143_FN1),
-        PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
-        PINMUX_DATA(NBRST_MARK, PORT145_FN1),
-        /* 49-4 (FN) */
-        PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
-        PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
-        PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
-        PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
-        PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
-        PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
-        PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
-        PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
-        PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
-        PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
-        PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
-        PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
-        PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
-        PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
-        PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
-        PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
-        PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
-        PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
-        PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
-        PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
-        PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
-        PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
-        PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
-        PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
-        PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
-        PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
-        PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
-        PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
-        PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
-        PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
-        PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
-        PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
-        PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
-        PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
-        PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
-        PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
-        PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
-        PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
-        PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
-        PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
-        PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
-        PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
-        PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
-        PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
-        PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
-        PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
-        PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
-        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
-        PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
-        PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
-        PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
-        PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
-        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
-        PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
-        PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
-        PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
-        PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
-        PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
-        PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
-        PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
-        PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
-        PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
-        PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
-        PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
-        PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
-        PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
-        PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
-        PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
-        PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
-        PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
-        PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
-        PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
-        PINMUX_DATA(XWR2_MARK, PORT181_FN7),
-        PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
-        PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
-        PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
-        PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
-        PINMUX_DATA(XWR3_MARK, PORT182_FN7),
-        PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
-        PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
-        PINMUX_DATA(D16_MARK, PORT183_FN6),
-        PINMUX_DATA(ED16_MARK, PORT183_FN7),
-        PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
-        PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
-        PINMUX_DATA(D17_MARK, PORT184_FN6),
-        PINMUX_DATA(ED17_MARK, PORT184_FN7),
-        PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
-        PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
-        PINMUX_DATA(D18_MARK, PORT185_FN6),
-        PINMUX_DATA(ED18_MARK, PORT185_FN7),
-        PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
-        PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
-        PINMUX_DATA(D19_MARK, PORT186_FN6),
-        PINMUX_DATA(ED19_MARK, PORT186_FN7),
-        PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
-        PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
-        PINMUX_DATA(D20_MARK, PORT187_FN6),
-        PINMUX_DATA(ED20_MARK, PORT187_FN7),
-        PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
-        PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
-        PINMUX_DATA(D21_MARK, PORT188_FN6),
-        PINMUX_DATA(ED21_MARK, PORT188_FN7),
-        PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
-        PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
-        PINMUX_DATA(D22_MARK, PORT189_FN6),
-        PINMUX_DATA(ED22_MARK, PORT189_FN7),
-        PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
-        PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
-        PINMUX_DATA(D23_MARK, PORT190_FN6),
-        PINMUX_DATA(ED23_MARK, PORT190_FN7),
-        PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
-        PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
-        PINMUX_DATA(D24_MARK, PORT191_FN6),
-        PINMUX_DATA(ED24_MARK, PORT191_FN7),
-        PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
-        PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
-        PINMUX_DATA(D25_MARK, PORT192_FN6),
-        PINMUX_DATA(ED25_MARK, PORT192_FN7),
-        PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
-        PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
-        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
-        PINMUX_DATA(D26_MARK, PORT193_FN6),
-        PINMUX_DATA(ED26_MARK, PORT193_FN7),
-        PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
-        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
-        PINMUX_DATA(D27_MARK, PORT194_FN6),
-        PINMUX_DATA(ED27_MARK, PORT194_FN7),
-        PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
-        PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
-        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
-        PINMUX_DATA(D28_MARK, PORT195_FN6),
-        PINMUX_DATA(ED28_MARK, PORT195_FN7),
-        PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
-        PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
-        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
-        PINMUX_DATA(D29_MARK, PORT196_FN6),
-        PINMUX_DATA(ED29_MARK, PORT196_FN7),
-        PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
-        PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
-        PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
-        PINMUX_DATA(D30_MARK, PORT197_FN6),
-        PINMUX_DATA(ED30_MARK, PORT197_FN7),
-        PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
-        PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
-        PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
-        PINMUX_DATA(D31_MARK, PORT198_FN6),
-        PINMUX_DATA(ED31_MARK, PORT198_FN7),
-        PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
-        PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
-        PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
-        PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
-        PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
-        PINMUX_DATA(DACK2_MARK, PORT200_FN2),
-        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
-        /* 49-5 (FN) */
-        PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
-        PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
-        PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
-        PINMUX_DATA(DACK3_MARK, PORT201_FN4),
-        PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
-        PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
-        PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
-        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
-        PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
-        PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
-        PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
-        PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
-        PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
-        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
-        PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
-        PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
-        PINMUX_DATA(DACK1_MARK, PORT205_FN3),
-        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
-        PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
-        PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
-        PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
-        PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
-        PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
-        PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
-        PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
-        PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
-        PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
-        PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
-        PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
-        PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
-        PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
-        PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
-        PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
-        PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
-        PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
-        PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
-        PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
-        PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
-        PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
-        PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
-        PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
-        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
-        PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
-        PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
-        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
-        PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
-        PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
-        PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
-        PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
-        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
-        PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
-        PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
-        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
-        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
-        PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
-        PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
-        PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
-        PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
-        PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
-        PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
-        PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
-        PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
-        PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
-        PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
-        PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
-        PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
-        PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
-        PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
-        PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
-        PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
-        PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
-        PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
-        PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
-        PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
-        PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
-        PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
-        PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
-        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
-        PINMUX_DATA(SIN3_MARK, PORT247_FN1),
-        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
-        PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
-        PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
-        PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
-        PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
-        PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
-        PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
-        PINMUX_DATA(DINT_MARK, PORT250_FN1),
-        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
-        PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
-        PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
-        PINMUX_DATA(TCK2_MARK, PORT251_FN2),
-        PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
-        PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
-        PINMUX_DATA(TMS2_MARK, PORT253_FN2),
-        PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
-        PINMUX_DATA(TDO2_MARK, PORT254_FN2),
-        PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
-        PINMUX_DATA(TDI2_MARK, PORT255_FN2),
-        PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
-        PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
-        /* 49-6 (FN) */
-        PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
-        PINMUX_DATA(TRST2_MARK, PORT257_FN2),
-        PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
-        PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
-        PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
-        PINMUX_DATA(TCK3_MARK, PORT259_FN4),
-        PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
-        PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
-        PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
-        PINMUX_DATA(TMS3_MARK, PORT260_FN4),
-        PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
-        PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
-        PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
-        PINMUX_DATA(TDO3_MARK, PORT261_FN4),
-        PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
-        PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
-        PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
-        PINMUX_DATA(TDI3_MARK, PORT262_FN4),
-        PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
-        PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
-        PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
-        PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
-        PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
-        PINMUX_DATA(TRST3_MARK, PORT264_FN4),
-        PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
-        PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
-        PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
-        PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
-        PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
-        PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
-        PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
-        PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
-        PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
-        PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
-        PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
-        PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
-        PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* 49-1 -> 49-6 (GPIO) */
-        GPIO_PORT_ALL(),
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
-        GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
-        GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
-        GPIO_FN(PORT58_KEYIN6_PU),
-        /* 49-1 (FN) */
-        GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
-        GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
-        GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
-        GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
-        GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
-        GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
-        GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
-        GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
-        GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
-        GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
-        GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
-        GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
-        GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
-        GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
-        GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
-        /* 49-2 (FN) */
-        GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
-        GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
-        GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
-        GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
-        GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
-        GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
-        GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
-        GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
-        GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
-        GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
-        GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
-        GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
-        GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
-        GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
-        GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
-        GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
-        GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
-        GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
-        GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
-        GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
-        GPIO_FN(XTALB1L),
-        GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
-        GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
-        GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
-        GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
-        GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
-        GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
-        GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
-        GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
-        GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
-        GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
-        GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
-        GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
-        GPIO_FN(NMI), GPIO_FN(TPU4TO0),
-        GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
-        GPIO_FN(IRQ_TMPB),
-        GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
-        GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
-        GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
-        /* 49-3 (FN) */
-        GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
-        GPIO_FN(PORT93_VIO_CKO2),
-        GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
-        GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
-        GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
-        GPIO_FN(SCIFA5_RXD),
-        GPIO_FN(SCIFA5_TXD),
-        GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
-        GPIO_FN(A0_EA0), GPIO_FN(BS),
-        GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
-        GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
-        GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
-        GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
-        GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
-        GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
-        GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
-        GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
-        GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
-        GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
-        GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
-        GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
-        GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
-        GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
-        GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
-        GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
-        GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
-        GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
-        GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
-        GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
-        GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
-        GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
-        GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
-        GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
-        /* 49-4 (FN) */
-        GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
-        GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
-        GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
-        GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
-        GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
-        GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
-        GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
-        GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
-        GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
-        GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
-        GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
-        GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
-        GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
-        GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
-        GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
-        GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
-        GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
-        GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
-        GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
-        GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
-        GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
-        GPIO_FN(LCDD6), GPIO_FN(DV_D6),
-        GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
-        GPIO_FN(LCDD7), GPIO_FN(DV_D7),
-        GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
-        GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
-        GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
-        GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
-        GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
-        GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
-        GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
-        GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
-        GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
-        GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
-        GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
-        GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
-        GPIO_FN(D26), GPIO_FN(ED26),
-        GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
-        GPIO_FN(D27), GPIO_FN(ED27),
-        GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
-        GPIO_FN(D28), GPIO_FN(ED28),
-        GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
-        GPIO_FN(D29), GPIO_FN(ED29),
-        GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
-        GPIO_FN(D30), GPIO_FN(ED30),
-        GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
-        GPIO_FN(D31), GPIO_FN(ED31),
-        GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
-        GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
-        /* 49-5 (FN) */
-        GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
-        GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
-        GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
-        GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
-        GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
-        GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
-        GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
-        GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
-        GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
-        GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
-        GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
-        GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
-        GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
-        GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
-        GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
-        GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
-        GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
-        GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
-        GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
-        GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
-        GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
-        GPIO_FN(MSIOF1_SS2),
-        GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
-        GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
-        GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
-        GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
-        GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
-        GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
-        GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
-        GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
-        GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
-        GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
-        GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
-        GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
-        GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
-        GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
-        GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
-        GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
-        /* 49-6 (FN) */
-        GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
-        GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
-        GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
-        GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
-        GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
-        GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
-        GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
-        GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
-        GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
-        GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
-        GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
-        GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
-        GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
-        GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
-        GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
-        GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(RESETOUTS),
-        GPIO_FN(DIVLOCK),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0, 0xe6050000), /* PORT0CR */
-        PORTCR(1, 0xe6050001), /* PORT1CR */
-        PORTCR(2, 0xe6050002), /* PORT2CR */
-        PORTCR(3, 0xe6050003), /* PORT3CR */
-        PORTCR(4, 0xe6050004), /* PORT4CR */
-        PORTCR(5, 0xe6050005), /* PORT5CR */
-        PORTCR(6, 0xe6050006), /* PORT6CR */
-        PORTCR(7, 0xe6050007), /* PORT7CR */
-        PORTCR(8, 0xe6050008), /* PORT8CR */
-        PORTCR(9, 0xe6050009), /* PORT9CR */
-        PORTCR(10, 0xe605000a), /* PORT10CR */
-        PORTCR(11, 0xe605000b), /* PORT11CR */
-        PORTCR(12, 0xe605000c), /* PORT12CR */
-        PORTCR(13, 0xe605000d), /* PORT13CR */
-        PORTCR(14, 0xe605000e), /* PORT14CR */
-        PORTCR(15, 0xe605000f), /* PORT15CR */
-        PORTCR(16, 0xe6050010), /* PORT16CR */
-        PORTCR(17, 0xe6050011), /* PORT17CR */
-        PORTCR(18, 0xe6050012), /* PORT18CR */
-        PORTCR(19, 0xe6050013), /* PORT19CR */
-        PORTCR(20, 0xe6050014), /* PORT20CR */
-        PORTCR(21, 0xe6050015), /* PORT21CR */
-        PORTCR(22, 0xe6050016), /* PORT22CR */
-        PORTCR(23, 0xe6050017), /* PORT23CR */
-        PORTCR(24, 0xe6050018), /* PORT24CR */
-        PORTCR(25, 0xe6050019), /* PORT25CR */
-        PORTCR(26, 0xe605001a), /* PORT26CR */
-        PORTCR(27, 0xe605001b), /* PORT27CR */
-        PORTCR(28, 0xe605001c), /* PORT28CR */
-        PORTCR(29, 0xe605001d), /* PORT29CR */
-        PORTCR(30, 0xe605001e), /* PORT30CR */
-        PORTCR(31, 0xe605001f), /* PORT31CR */
-        PORTCR(32, 0xe6050020), /* PORT32CR */
-        PORTCR(33, 0xe6050021), /* PORT33CR */
-        PORTCR(34, 0xe6050022), /* PORT34CR */
-        PORTCR(35, 0xe6050023), /* PORT35CR */
-        PORTCR(36, 0xe6050024), /* PORT36CR */
-        PORTCR(37, 0xe6050025), /* PORT37CR */
-        PORTCR(38, 0xe6050026), /* PORT38CR */
-        PORTCR(39, 0xe6050027), /* PORT39CR */
-        PORTCR(40, 0xe6050028), /* PORT40CR */
-        PORTCR(41, 0xe6050029), /* PORT41CR */
-        PORTCR(42, 0xe605002a), /* PORT42CR */
-        PORTCR(43, 0xe605002b), /* PORT43CR */
-        PORTCR(44, 0xe605002c), /* PORT44CR */
-        PORTCR(45, 0xe605002d), /* PORT45CR */
-        PORTCR(46, 0xe605002e), /* PORT46CR */
-        PORTCR(47, 0xe605002f), /* PORT47CR */
-        PORTCR(48, 0xe6050030), /* PORT48CR */
-        PORTCR(49, 0xe6050031), /* PORT49CR */
-        PORTCR(50, 0xe6050032), /* PORT50CR */
-        PORTCR(51, 0xe6050033), /* PORT51CR */
-        PORTCR(52, 0xe6050034), /* PORT52CR */
-        PORTCR(53, 0xe6050035), /* PORT53CR */
-        PORTCR(54, 0xe6050036), /* PORT54CR */
-        PORTCR(55, 0xe6050037), /* PORT55CR */
-        PORTCR(56, 0xe6050038), /* PORT56CR */
-        PORTCR(57, 0xe6050039), /* PORT57CR */
-        PORTCR(58, 0xe605003a), /* PORT58CR */
-        PORTCR(59, 0xe605003b), /* PORT59CR */
-        PORTCR(60, 0xe605003c), /* PORT60CR */
-        PORTCR(61, 0xe605003d), /* PORT61CR */
-        PORTCR(62, 0xe605003e), /* PORT62CR */
-        PORTCR(63, 0xe605003f), /* PORT63CR */
-        PORTCR(64, 0xe6050040), /* PORT64CR */
-        PORTCR(65, 0xe6050041), /* PORT65CR */
-        PORTCR(66, 0xe6050042), /* PORT66CR */
-        PORTCR(67, 0xe6050043), /* PORT67CR */
-        PORTCR(68, 0xe6050044), /* PORT68CR */
-        PORTCR(69, 0xe6050045), /* PORT69CR */
-        PORTCR(70, 0xe6050046), /* PORT70CR */
-        PORTCR(71, 0xe6050047), /* PORT71CR */
-        PORTCR(72, 0xe6050048), /* PORT72CR */
-        PORTCR(73, 0xe6050049), /* PORT73CR */
-        PORTCR(74, 0xe605004a), /* PORT74CR */
-        PORTCR(75, 0xe605004b), /* PORT75CR */
-        PORTCR(76, 0xe605004c), /* PORT76CR */
-        PORTCR(77, 0xe605004d), /* PORT77CR */
-        PORTCR(78, 0xe605004e), /* PORT78CR */
-        PORTCR(79, 0xe605004f), /* PORT79CR */
-        PORTCR(80, 0xe6050050), /* PORT80CR */
-        PORTCR(81, 0xe6050051), /* PORT81CR */
-        PORTCR(82, 0xe6050052), /* PORT82CR */
-        PORTCR(83, 0xe6050053), /* PORT83CR */
-        PORTCR(84, 0xe6050054), /* PORT84CR */
-        PORTCR(85, 0xe6050055), /* PORT85CR */
-        PORTCR(86, 0xe6050056), /* PORT86CR */
-        PORTCR(87, 0xe6050057), /* PORT87CR */
-        PORTCR(88, 0xe6051058), /* PORT88CR */
-        PORTCR(89, 0xe6051059), /* PORT89CR */
-        PORTCR(90, 0xe605105a), /* PORT90CR */
-        PORTCR(91, 0xe605105b), /* PORT91CR */
-        PORTCR(92, 0xe605105c), /* PORT92CR */
-        PORTCR(93, 0xe605105d), /* PORT93CR */
-        PORTCR(94, 0xe605105e), /* PORT94CR */
-        PORTCR(95, 0xe605105f), /* PORT95CR */
-        PORTCR(96, 0xe6051060), /* PORT96CR */
-        PORTCR(97, 0xe6051061), /* PORT97CR */
-        PORTCR(98, 0xe6051062), /* PORT98CR */
-        PORTCR(99, 0xe6051063), /* PORT99CR */
-        PORTCR(100, 0xe6051064), /* PORT100CR */
-        PORTCR(101, 0xe6051065), /* PORT101CR */
-        PORTCR(102, 0xe6051066), /* PORT102CR */
-        PORTCR(103, 0xe6051067), /* PORT103CR */
-        PORTCR(104, 0xe6051068), /* PORT104CR */
-        PORTCR(105, 0xe6051069), /* PORT105CR */
-        PORTCR(106, 0xe605106a), /* PORT106CR */
-        PORTCR(107, 0xe605106b), /* PORT107CR */
-        PORTCR(108, 0xe605106c), /* PORT108CR */
-        PORTCR(109, 0xe605106d), /* PORT109CR */
-        PORTCR(110, 0xe605106e), /* PORT110CR */
-        PORTCR(111, 0xe605106f), /* PORT111CR */
-        PORTCR(112, 0xe6051070), /* PORT112CR */
-        PORTCR(113, 0xe6051071), /* PORT113CR */
-        PORTCR(114, 0xe6051072), /* PORT114CR */
-        PORTCR(115, 0xe6051073), /* PORT115CR */
-        PORTCR(116, 0xe6051074), /* PORT116CR */
-        PORTCR(117, 0xe6051075), /* PORT117CR */
-        PORTCR(118, 0xe6051076), /* PORT118CR */
-        PORTCR(119, 0xe6051077), /* PORT119CR */
-        PORTCR(120, 0xe6051078), /* PORT120CR */
-        PORTCR(121, 0xe6051079), /* PORT121CR */
-        PORTCR(122, 0xe605107a), /* PORT122CR */
-        PORTCR(123, 0xe605107b), /* PORT123CR */
-        PORTCR(124, 0xe605107c), /* PORT124CR */
-        PORTCR(125, 0xe605107d), /* PORT125CR */
-        PORTCR(126, 0xe605107e), /* PORT126CR */
-        PORTCR(127, 0xe605107f), /* PORT127CR */
-        PORTCR(128, 0xe6051080), /* PORT128CR */
-        PORTCR(129, 0xe6051081), /* PORT129CR */
-        PORTCR(130, 0xe6051082), /* PORT130CR */
-        PORTCR(131, 0xe6051083), /* PORT131CR */
-        PORTCR(132, 0xe6051084), /* PORT132CR */
-        PORTCR(133, 0xe6051085), /* PORT133CR */
-        PORTCR(134, 0xe6051086), /* PORT134CR */
-        PORTCR(135, 0xe6051087), /* PORT135CR */
-        PORTCR(136, 0xe6051088), /* PORT136CR */
-        PORTCR(137, 0xe6051089), /* PORT137CR */
-        PORTCR(138, 0xe605108a), /* PORT138CR */
-        PORTCR(139, 0xe605108b), /* PORT139CR */
-        PORTCR(140, 0xe605108c), /* PORT140CR */
-        PORTCR(141, 0xe605108d), /* PORT141CR */
-        PORTCR(142, 0xe605108e), /* PORT142CR */
-        PORTCR(143, 0xe605108f), /* PORT143CR */
-        PORTCR(144, 0xe6051090), /* PORT144CR */
-        PORTCR(145, 0xe6051091), /* PORT145CR */
-        PORTCR(146, 0xe6051092), /* PORT146CR */
-        PORTCR(147, 0xe6051093), /* PORT147CR */
-        PORTCR(148, 0xe6051094), /* PORT148CR */
-        PORTCR(149, 0xe6051095), /* PORT149CR */
-        PORTCR(150, 0xe6051096), /* PORT150CR */
-        PORTCR(151, 0xe6051097), /* PORT151CR */
-        PORTCR(152, 0xe6051098), /* PORT152CR */
-        PORTCR(153, 0xe6051099), /* PORT153CR */
-        PORTCR(154, 0xe605109a), /* PORT154CR */
-        PORTCR(155, 0xe605109b), /* PORT155CR */
-        PORTCR(156, 0xe605109c), /* PORT156CR */
-        PORTCR(157, 0xe605109d), /* PORT157CR */
-        PORTCR(158, 0xe605109e), /* PORT158CR */
-        PORTCR(159, 0xe605109f), /* PORT159CR */
-        PORTCR(160, 0xe60510a0), /* PORT160CR */
-        PORTCR(161, 0xe60510a1), /* PORT161CR */
-        PORTCR(162, 0xe60510a2), /* PORT162CR */
-        PORTCR(163, 0xe60510a3), /* PORT163CR */
-        PORTCR(164, 0xe60510a4), /* PORT164CR */
-        PORTCR(165, 0xe60510a5), /* PORT165CR */
-        PORTCR(166, 0xe60510a6), /* PORT166CR */
-        PORTCR(167, 0xe60510a7), /* PORT167CR */
-        PORTCR(168, 0xe60510a8), /* PORT168CR */
-        PORTCR(169, 0xe60510a9), /* PORT169CR */
-        PORTCR(170, 0xe60510aa), /* PORT170CR */
-        PORTCR(171, 0xe60510ab), /* PORT171CR */
-        PORTCR(172, 0xe60510ac), /* PORT172CR */
-        PORTCR(173, 0xe60510ad), /* PORT173CR */
-        PORTCR(174, 0xe60510ae), /* PORT174CR */
-        PORTCR(175, 0xe60520af), /* PORT175CR */
-        PORTCR(176, 0xe60520b0), /* PORT176CR */
-        PORTCR(177, 0xe60520b1), /* PORT177CR */
-        PORTCR(178, 0xe60520b2), /* PORT178CR */
-        PORTCR(179, 0xe60520b3), /* PORT179CR */
-        PORTCR(180, 0xe60520b4), /* PORT180CR */
-        PORTCR(181, 0xe60520b5), /* PORT181CR */
-        PORTCR(182, 0xe60520b6), /* PORT182CR */
-        PORTCR(183, 0xe60520b7), /* PORT183CR */
-        PORTCR(184, 0xe60520b8), /* PORT184CR */
-        PORTCR(185, 0xe60520b9), /* PORT185CR */
-        PORTCR(186, 0xe60520ba), /* PORT186CR */
-        PORTCR(187, 0xe60520bb), /* PORT187CR */
-        PORTCR(188, 0xe60520bc), /* PORT188CR */
-        PORTCR(189, 0xe60520bd), /* PORT189CR */
-        PORTCR(190, 0xe60520be), /* PORT190CR */
-        PORTCR(191, 0xe60520bf), /* PORT191CR */
-        PORTCR(192, 0xe60520c0), /* PORT192CR */
-        PORTCR(193, 0xe60520c1), /* PORT193CR */
-        PORTCR(194, 0xe60520c2), /* PORT194CR */
-        PORTCR(195, 0xe60520c3), /* PORT195CR */
-        PORTCR(196, 0xe60520c4), /* PORT196CR */
-        PORTCR(197, 0xe60520c5), /* PORT197CR */
-        PORTCR(198, 0xe60520c6), /* PORT198CR */
-        PORTCR(199, 0xe60520c7), /* PORT199CR */
-        PORTCR(200, 0xe60520c8), /* PORT200CR */
-        PORTCR(201, 0xe60520c9), /* PORT201CR */
-        PORTCR(202, 0xe60520ca), /* PORT202CR */
-        PORTCR(203, 0xe60520cb), /* PORT203CR */
-        PORTCR(204, 0xe60520cc), /* PORT204CR */
-        PORTCR(205, 0xe60520cd), /* PORT205CR */
-        PORTCR(206, 0xe60520ce), /* PORT206CR */
-        PORTCR(207, 0xe60520cf), /* PORT207CR */
-        PORTCR(208, 0xe60520d0), /* PORT208CR */
-        PORTCR(209, 0xe60520d1), /* PORT209CR */
-        PORTCR(210, 0xe60520d2), /* PORT210CR */
-        PORTCR(211, 0xe60520d3), /* PORT211CR */
-        PORTCR(212, 0xe60520d4), /* PORT212CR */
-        PORTCR(213, 0xe60520d5), /* PORT213CR */
-        PORTCR(214, 0xe60520d6), /* PORT214CR */
-        PORTCR(215, 0xe60520d7), /* PORT215CR */
-        PORTCR(216, 0xe60520d8), /* PORT216CR */
-        PORTCR(217, 0xe60520d9), /* PORT217CR */
-        PORTCR(218, 0xe60520da), /* PORT218CR */
-        PORTCR(219, 0xe60520db), /* PORT219CR */
-        PORTCR(220, 0xe60520dc), /* PORT220CR */
-        PORTCR(221, 0xe60520dd), /* PORT221CR */
-        PORTCR(222, 0xe60520de), /* PORT222CR */
-        PORTCR(223, 0xe60520df), /* PORT223CR */
-        PORTCR(224, 0xe60520e0), /* PORT224CR */
-        PORTCR(225, 0xe60520e1), /* PORT225CR */
-        PORTCR(226, 0xe60520e2), /* PORT226CR */
-        PORTCR(227, 0xe60520e3), /* PORT227CR */
-        PORTCR(228, 0xe60520e4), /* PORT228CR */
-        PORTCR(229, 0xe60520e5), /* PORT229CR */
-        PORTCR(230, 0xe60520e6), /* PORT230CR */
-        PORTCR(231, 0xe60520e7), /* PORT231CR */
-        PORTCR(232, 0xe60520e8), /* PORT232CR */
-        PORTCR(233, 0xe60520e9), /* PORT233CR */
-        PORTCR(234, 0xe60520ea), /* PORT234CR */
-        PORTCR(235, 0xe60520eb), /* PORT235CR */
-        PORTCR(236, 0xe60530ec), /* PORT236CR */
-        PORTCR(237, 0xe60530ed), /* PORT237CR */
-        PORTCR(238, 0xe60530ee), /* PORT238CR */
-        PORTCR(239, 0xe60530ef), /* PORT239CR */
-        PORTCR(240, 0xe60530f0), /* PORT240CR */
-        PORTCR(241, 0xe60530f1), /* PORT241CR */
-        PORTCR(242, 0xe60530f2), /* PORT242CR */
-        PORTCR(243, 0xe60530f3), /* PORT243CR */
-        PORTCR(244, 0xe60530f4), /* PORT244CR */
-        PORTCR(245, 0xe60530f5), /* PORT245CR */
-        PORTCR(246, 0xe60530f6), /* PORT246CR */
-        PORTCR(247, 0xe60530f7), /* PORT247CR */
-        PORTCR(248, 0xe60530f8), /* PORT248CR */
-        PORTCR(249, 0xe60530f9), /* PORT249CR */
-        PORTCR(250, 0xe60530fa), /* PORT250CR */
-        PORTCR(251, 0xe60530fb), /* PORT251CR */
-        PORTCR(252, 0xe60530fc), /* PORT252CR */
-        PORTCR(253, 0xe60530fd), /* PORT253CR */
-        PORTCR(254, 0xe60530fe), /* PORT254CR */
-        PORTCR(255, 0xe60530ff), /* PORT255CR */
-        PORTCR(256, 0xe6053100), /* PORT256CR */
-        PORTCR(257, 0xe6053101), /* PORT257CR */
-        PORTCR(258, 0xe6053102), /* PORT258CR */
-        PORTCR(259, 0xe6053103), /* PORT259CR */
-        PORTCR(260, 0xe6053104), /* PORT260CR */
-        PORTCR(261, 0xe6053105), /* PORT261CR */
-        PORTCR(262, 0xe6053106), /* PORT262CR */
-        PORTCR(263, 0xe6053107), /* PORT263CR */
-        PORTCR(264, 0xe6053108), /* PORT264CR */
-        PORTCR(265, 0xe6053109), /* PORT265CR */
-        PORTCR(266, 0xe605310a), /* PORT266CR */
-        PORTCR(267, 0xe605310b), /* PORT267CR */
-        PORTCR(268, 0xe605310c), /* PORT268CR */
-        PORTCR(269, 0xe605310d), /* PORT269CR */
-        PORTCR(270, 0xe605310e), /* PORT270CR */
-        PORTCR(271, 0xe605310f), /* PORT271CR */
-        PORTCR(272, 0xe6053110), /* PORT272CR */
-        { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                0, 0,
-                MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
-                0, 0,
-                0, 0 }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
-                PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-                PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-                PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
-                PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
-                PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
-                PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
-                PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
-                PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
-                PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
-                PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
-                PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
-                PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
-                PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
-                PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
-                PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
-                PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
-                PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
-                PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
-                PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-                PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-                PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-                PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-                PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-                PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-                PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-                PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
-                PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
-                PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-                PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-                PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-                PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-                PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-                PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-                PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, 0,
-                0, 0, 0, PORT272_DATA,
-                PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
-                PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
-                PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-                PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
-        },
-        { },
-};
-static struct pinmux_info sh7367_pinmux_info = {
-        .name = "sh7367_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_DIVLOCK,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-void sh7367_pinmux_init(void)
-{
-        register_pinmux(&sh7367_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
deleted file mode 100644
index f3117f67fa25..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7377.c
+++ /dev/null
@@ -1,1688 +0,0 @@
-/*
- * sh7377 processor support - PFC hardware block
- *
- * Copyright (C) 2010  NISHIMOTO Hiroki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sh_pfc.h>
-#include <mach/sh7377.h>
-#define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx),           \
-        PORT_10(fn, pfx##10, sfx),                              \
-        PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx),   \
-        PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx),   \
-        PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx),   \
-        PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx),   \
-        PORT_1(fn, pfx##118, sfx),                              \
-        PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx),   \
-        PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx),   \
-        PORT_10(fn, pfx##15, sfx),                              \
-        PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx),   \
-        PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx),   \
-        PORT_1(fn, pfx##164, sfx),                              \
-        PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx),   \
-        PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx),   \
-        PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx),   \
-        PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx),   \
-        PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),   \
-        PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),   \
-        PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),   \
-        PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx),   \
-        PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx),   \
-        PORT_1(fn, pfx##264, sfx)
-enum {
-        PINMUX_RESERVED = 0,
-        PINMUX_DATA_BEGIN,
-        PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */
-        PINMUX_DATA_END,
-        PINMUX_INPUT_BEGIN,
-        PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */
-        PINMUX_INPUT_END,
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
-        PINMUX_INPUT_PULLUP_END,
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
-        PINMUX_INPUT_PULLDOWN_END,
-        PINMUX_OUTPUT_BEGIN,
-        PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */
-        PINMUX_OUTPUT_END,
-        PINMUX_FUNCTION_BEGIN,
-        PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
-        PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
-        PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */
-        PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */
-        PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */
-        PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */
-        PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */
-        PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */
-        PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */
-        PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */
-        MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
-        MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
-        PINMUX_FUNCTION_END,
-        PINMUX_MARK_BEGIN,
-        /* Special Pull-up / Pull-down Functions */
-        PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK,
-        PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK,
-        PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK,
-        PORT72_KEYIN6_PU_MARK,
-        /* 55-1 */
-        VBUS_0_MARK,
-        CPORT0_MARK,
-        CPORT1_MARK,
-        CPORT2_MARK,
-        CPORT3_MARK,
-        CPORT4_MARK,
-        CPORT5_MARK,
-        CPORT6_MARK,
-        CPORT7_MARK,
-        CPORT8_MARK,
-        CPORT9_MARK,
-        CPORT10_MARK,
-        CPORT11_MARK, SIN2_MARK,
-        CPORT12_MARK, XCTS2_MARK,
-        CPORT13_MARK, RFSPO4_MARK,
-        CPORT14_MARK, RFSPO5_MARK,
-        CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK,
-        CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK,
-        CPORT17_IC_OE_MARK, SOUT2_MARK,
-        CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK,
-        CPORT19_MPORT1_MARK,
-        CPORT20_MARK, RFSPO6_MARK,
-        CPORT21_MARK, STATUS0_MARK,
-        CPORT22_MARK, STATUS1_MARK,
-        CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
-        B_SYNLD1_MARK,
-        B_SYNLD2_MARK, SYSENMSK_MARK,
-        XMAINPS_MARK,
-        XDIVPS_MARK,
-        XIDRST_MARK,
-        IDCLK_MARK, IC_DP_MARK,
-        IDIO_MARK, IC_DM_MARK,
-        SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK,
-        SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
-        XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
-        XCTS1_MARK, SCIFA4_CTS_MARK,
-        PCMCLKO_MARK,
-        SYNC8KO_MARK,
-        /* 55-2 */
-        DNPCM_A_MARK,
-        UPPCM_A_MARK,
-        VACK_MARK,
-        XTALB1L_MARK,
-        GPS_AGC1_MARK, SCIFA0_RTS_MARK,
-        GPS_AGC4_MARK, SCIFA0_RXD_MARK,
-        GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK,
-        GPS_IM_MARK,
-        GPS_IS_MARK,
-        GPS_QM_MARK,
-        GPS_QS_MARK,
-        FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK,
-        FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK,
-        FMSIOLR_MARK,
-        FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK,
-        FMSIOBT_MARK,
-        FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK,
-        FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK,
-        FMSIILR_MARK,
-        FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK,
-        FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK,
-        A0_EA0_MARK, BS_MARK,
-        A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK,
-        A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK,
-        A14_EA14_MARK, PORT60_KEYOUT5_MARK,
-        A15_EA15_MARK, PORT61_KEYOUT4_MARK,
-        A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK,
-        A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
-        A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK,
-        A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK,
-        A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK,
-        A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK,
-        A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK,
-        A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK,
-        A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK,
-        A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK,
-        A26_MARK, PORT72_KEYIN6_MARK,
-        D0_ED0_NAF0_MARK,
-        D1_ED1_NAF1_MARK,
-        D2_ED2_NAF2_MARK,
-        D3_ED3_NAF3_MARK,
-        D4_ED4_NAF4_MARK,
-        D5_ED5_NAF5_MARK,
-        D6_ED6_NAF6_MARK,
-        D7_ED7_NAF7_MARK,
-        D8_ED8_NAF8_MARK,
-        D9_ED9_NAF9_MARK,
-        D10_ED10_NAF10_MARK,
-        D11_ED11_NAF11_MARK,
-        D12_ED12_NAF12_MARK,
-        D13_ED13_NAF13_MARK,
-        D14_ED14_NAF14_MARK,
-        D15_ED15_NAF15_MARK,
-        CS4_MARK,
-        CS5A_MARK, FMSICK_MARK,
-        CS5B_MARK, FCE1_MARK,
-        /* 55-3 */
-        CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK,
-        FCE0_MARK,
-        WAIT_MARK, DREQ0_MARK,
-        RD_XRD_MARK,
-        WE0_XWR0_FWE_MARK,
-        WE1_XWR1_MARK,
-        FRB_MARK,
-        CKO_MARK,
-        NBRSTOUT_MARK,
-        NBRST_MARK,
-        GPS_EPPSIN_MARK,
-        LATCHPULSE_MARK,
-        LTESIGNAL_MARK,
-        LEGACYSTATE_MARK,
-        TCKON_MARK,
-        VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK,
-        VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK,
-        VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK,
-        VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK,
-        VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK,
-        VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK,
-        VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK,
-        VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK,
-        VIO_D6_MARK, PORT136_KEYIN2_MARK,
-        VIO_D7_MARK, PORT137_KEYIN3_MARK,
-        VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK,
-        VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK,
-        VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK,
-        VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK,
-        VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK,
-        VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK,
-        VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK,
-        VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK,
-        VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK,
-        VIO_FIELD_MARK, PORT147_KEYIN5_MARK,
-        VIO_CKO_MARK, PORT148_KEYIN6_MARK,
-        A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK,
-        MFG0_IN2_MARK,
-        TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
-        TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
-        TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
-        SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
-        SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
-        XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK,
-        XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK,
-        /* 55-4 */
-        DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
-        PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
-        PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK,
-        PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK,
-        MFG3_IN2_MARK,
-        PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK,
-        MFG3_IN1_MARK,
-        PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK,
-        MFG3_OUT1_MARK, TPU3TO0_MARK,
-        LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK,
-        LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK,
-        BBIF2_TSYNC1_MARK,
-        LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK,
-        BBIF2_TSCK1_MARK,
-        LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK,
-        BBIF2_TXD1_MARK,
-        LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK,
-        LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK,
-        MFG2_OUT2_MARK,
-        TPU2TO1_MARK,
-        LCDD6_MARK, XWR2_MARK,
-        LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK,
-        LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK,
-        LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK,
-        LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK,
-        LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK,
-        LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK,
-        LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK,
-        LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK,
-        LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK,
-        VIO_DR7_MARK, D23_MARK, ED23_MARK,
-        LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK,
-        VIO_VDR_MARK, D24_MARK, ED24_MARK,
-        LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK,
-        LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK,
-        LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK,
-        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK,
-        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK,
-        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK,
-        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK,
-        LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK,
-        LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK,
-        LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
-        PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK,
-        LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK,
-        LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK,
-        LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK,
-        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK,
-        SCIFA1_TXD_MARK, OVCN2_MARK,
-        EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK,
-        SCIFA1_RTS_MARK, IDIN_MARK,
-        SCIFA1_RXD_MARK,
-        SCIFA1_CTS_MARK, MFG1_IN1_MARK,
-        MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK,
-        MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK,
-        MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK,
-        MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK,
-        PORT233_FSIACK_MARK,
-        MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK,
-        MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK,
-        MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK,
-        MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK,
-        MSIOF1_SS1_MARK, EDBGREQ3_MARK,
-        /* 55-5 */
-        MSIOF1_SS2_MARK,
-        SCIFA6_TXD_MARK,
-        PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK,
-        TPU4TO0_MARK,
-        PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
-        PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
-        PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK,
-        PORT244_MSIOF2_RXD_MARK,
-        PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK,
-        PORT245_MSIOF2_TXD_MARK,
-        PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK,
-        TPU1TO0_MARK,
-        PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK,
-        TPU3TO1_MARK,
-        PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK,
-        TPU2TO0_MARK,
-        PORT248_MSIOF2_TSCK_MARK,
-        PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK,
-        SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK,
-        SDHICD0_MARK,
-        SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK,
-        SDHID0_1_MARK, TDO2_SWO0_MC0_MARK,
-        SDHID0_2_MARK, TDI2_MARK,
-        SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK,
-        SDHICMD0_MARK, TRST2_MARK,
-        SDHIWP0_MARK, EDBGREQ2_MARK,
-        SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK,
-        SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK,
-        TMS3_SWDIO_MC1_MARK,
-        SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK,
-        SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK,
-        SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK,
-        SDHICMD1_MARK, TRST3_MARK,
-        RESETOUTS_MARK,
-        PINMUX_MARK_END,
-};
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-        /* 55-1 (GPIO) */
-        PORT_DATA_I_PD(0), PORT_DATA_I_PU(1),
-        PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
-        PORT_DATA_I_PU(4), PORT_DATA_I_PU(5),
-        PORT_DATA_I_PU(6), PORT_DATA_I_PU(7),
-        PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
-        PORT_DATA_I_PU(10), PORT_DATA_I_PU(11),
-        PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13),
-        PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
-        PORT_DATA_O(16), PORT_DATA_IO(17),
-        PORT_DATA_O(18), PORT_DATA_O(19),
-        PORT_DATA_O(20), PORT_DATA_O(21),
-        PORT_DATA_O(22), PORT_DATA_O(23),
-        PORT_DATA_O(24), PORT_DATA_I_PD(25),
-        PORT_DATA_I_PD(26), PORT_DATA_O(27),
-        PORT_DATA_O(28), PORT_DATA_O(29),
-        PORT_DATA_IO(30), PORT_DATA_IO_PU(31),
-        PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33),
-        PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35),
-        PORT_DATA_O(36), PORT_DATA_IO(37),
-        /* 55-2 (GPIO) */
-        PORT_DATA_O(38), PORT_DATA_I_PU(39),
-        PORT_DATA_I_PU_PD(40), PORT_DATA_O(41),
-        PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43),
-        PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45),
-        PORT_DATA_I_PD(46), PORT_DATA_I_PD(47),
-        PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49),
-        PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51),
-        PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53),
-        PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55),
-        PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57),
-        PORT_DATA_IO(58), PORT_DATA_IO(59),
-        PORT_DATA_IO(60), PORT_DATA_IO(61),
-        PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
-        PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73),
-        PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75),
-        PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77),
-        PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79),
-        PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81),
-        PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83),
-        PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85),
-        PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87),
-        PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89),
-        PORT_DATA_O(90), PORT_DATA_IO_PU(91),
-        PORT_DATA_O(92),
-        /* 55-3 (GPIO) */
-        PORT_DATA_IO_PU(93),
-        PORT_DATA_O(94),
-        PORT_DATA_I_PU_PD(95),
-        PORT_DATA_IO(96), PORT_DATA_IO(97),
-        PORT_DATA_IO(98), PORT_DATA_I_PU(99),
-        PORT_DATA_O(100), PORT_DATA_O(101),
-        PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103),
-        PORT_DATA_I_PD(104), PORT_DATA_I_PD(105),
-        PORT_DATA_I_PD(106), PORT_DATA_I_PD(107),
-        PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109),
-        PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111),
-        PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115),
-        PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117),
-        PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128),
-        PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130),
-        PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132),
-        PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134),
-        PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136),
-        PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138),
-        PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140),
-        PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142),
-        PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144),
-        PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146),
-        PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148),
-        PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150),
-        PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152),
-        PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154),
-        PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156),
-        PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158),
-        /* 55-4 (GPIO) */
-        PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160),
-        PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162),
-        PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164),
-        PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193),
-        PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199),
-        PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
-        PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
-        PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207),
-        PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209),
-        PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
-        PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213),
-        PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215),
-        PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217),
-        PORT_DATA_O(218), PORT_DATA_IO_PD(219),
-        PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221),
-        PORT_DATA_IO_PU_PD(222),
-        PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224),
-        PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226),
-        PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228),
-        PORT_DATA_I_PD(229), PORT_DATA_IO(230),
-        PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232),
-        PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234),
-        PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236),
-        PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238),
-        /* 55-5 (GPIO) */
-        PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240),
-        PORT_DATA_O(241), PORT_DATA_I_PD(242),
-        PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244),
-        PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246),
-        PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248),
-        PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250),
-        PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252),
-        PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254),
-        PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256),
-        PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258),
-        PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260),
-        PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262),
-        PORT_DATA_IO_PU_PD(263),
-        /* Special Pull-up / Pull-down Functions */
-        PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT66_FN2, PORT66_IN_PU),
-        PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT67_FN2, PORT67_IN_PU),
-        PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT68_FN2, PORT68_IN_PU),
-        PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT69_FN2, PORT69_IN_PU),
-        PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT70_FN2, PORT70_IN_PU),
-        PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT71_FN2, PORT71_IN_PU),
-        PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
-                                PORT72_FN2, PORT72_IN_PU),
-        /* 55-1 (FN) */
-        PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
-        PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
-        PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
-        PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
-        PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
-        PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
-        PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
-        PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
-        PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
-        PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
-        PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
-        PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
-        PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
-        PINMUX_DATA(SIN2_MARK, PORT12_FN2),
-        PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
-        PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
-        PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
-        PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
-        PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
-        PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
-        PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
-        PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2),
-        PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3),
-        PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
-        PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
-        PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3),
-        PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1),
-        PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
-        PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
-        PINMUX_DATA(XRTS2_MARK, PORT19_FN2),
-        PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
-        PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1),
-        PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
-        PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
-        PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
-        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
-        PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
-        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
-        PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
-        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
-        PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
-        PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1),
-        PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1),
-        PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2),
-        PINMUX_DATA(XMAINPS_MARK, PORT27_FN1),
-        PINMUX_DATA(XDIVPS_MARK, PORT28_FN1),
-        PINMUX_DATA(XIDRST_MARK, PORT29_FN1),
-        PINMUX_DATA(IDCLK_MARK, PORT30_FN1),
-        PINMUX_DATA(IC_DP_MARK, PORT30_FN2),
-        PINMUX_DATA(IDIO_MARK, PORT31_FN1),
-        PINMUX_DATA(IC_DM_MARK, PORT31_FN2),
-        PINMUX_DATA(SOUT1_MARK, PORT32_FN1),
-        PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
-        PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3),
-        PINMUX_DATA(SIN1_MARK, PORT33_FN1),
-        PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2),
-        PINMUX_DATA(XWUP_MARK, PORT33_FN3),
-        PINMUX_DATA(XRTS1_MARK, PORT34_FN1),
-        PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2),
-        PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3),
-        PINMUX_DATA(XCTS1_MARK, PORT35_FN1),
-        PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2),
-        PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1),
-        PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1),
-        /* 55-2 (FN) */
-        PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1),
-        PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1),
-        PINMUX_DATA(VACK_MARK, PORT40_FN1),
-        PINMUX_DATA(XTALB1L_MARK, PORT41_FN1),
-        PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1),
-        PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2),
-        PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1),
-        PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
-        PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1),
-        PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2),
-        PINMUX_DATA(GPS_IM_MARK, PORT45_FN1),
-        PINMUX_DATA(GPS_IS_MARK, PORT46_FN1),
-        PINMUX_DATA(GPS_QM_MARK, PORT47_FN1),
-        PINMUX_DATA(GPS_QS_MARK, PORT48_FN1),
-        PINMUX_DATA(FMSOCK_MARK, PORT49_FN1),
-        PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2),
-        PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3),
-        PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1),
-        PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2),
-        PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3),
-        PINMUX_DATA(IPORT3_MARK, PORT50_FN4),
-        PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5),
-        PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1),
-        PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2),
-        PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3),
-        PINMUX_DATA(OPORT1_MARK, PORT51_FN4),
-        PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5),
-        PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1),
-        PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
-        PINMUX_DATA(OPORT2_MARK, PORT52_FN3),
-        PINMUX_DATA(FMSOILR_MARK, PORT53_FN1),
-        PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2),
-        PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3),
-        PINMUX_DATA(OPORT3_MARK, PORT53_FN4),
-        PINMUX_DATA(FMSIILR_MARK, PORT53_FN5),
-        PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1),
-        PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2),
-        PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3),
-        PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4),
-        PINMUX_DATA(FMSISLD_MARK, PORT55_FN1),
-        PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2),
-        PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
-        PINMUX_DATA(A0_EA0_MARK, PORT57_FN1),
-        PINMUX_DATA(BS_MARK, PORT57_FN2),
-        PINMUX_DATA(A12_EA12_MARK, PORT58_FN1),
-        PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2),
-        PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3),
-        PINMUX_DATA(A13_EA13_MARK, PORT59_FN1),
-        PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2),
-        PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3),
-        PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
-        PINMUX_DATA(A14_EA14_MARK, PORT60_FN1),
-        PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2),
-        PINMUX_DATA(A15_EA15_MARK, PORT61_FN1),
-        PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2),
-        PINMUX_DATA(A16_EA16_MARK, PORT62_FN1),
-        PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2),
-        PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3),
-        PINMUX_DATA(A17_EA17_MARK, PORT63_FN1),
-        PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2),
-        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3),
-        PINMUX_DATA(A18_EA18_MARK, PORT64_FN1),
-        PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2),
-        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3),
-        PINMUX_DATA(A19_EA19_MARK, PORT65_FN1),
-        PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2),
-        PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3),
-        PINMUX_DATA(A20_EA20_MARK, PORT66_FN1),
-        PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2),
-        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3),
-        PINMUX_DATA(A21_EA21_MARK, PORT67_FN1),
-        PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2),
-        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3),
-        PINMUX_DATA(A22_EA22_MARK, PORT68_FN1),
-        PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2),
-        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3),
-        PINMUX_DATA(A23_EA23_MARK, PORT69_FN1),
-        PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2),
-        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3),
-        PINMUX_DATA(A24_EA24_MARK, PORT70_FN1),
-        PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2),
-        PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3),
-        PINMUX_DATA(A25_EA25_MARK, PORT71_FN1),
-        PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2),
-        PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3),
-        PINMUX_DATA(A26_MARK, PORT72_FN1),
-        PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2),
-        PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1),
-        PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1),
-        PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1),
-        PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1),
-        PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1),
-        PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1),
-        PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1),
-        PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1),
-        PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1),
-        PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1),
-        PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1),
-        PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1),
-        PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1),
-        PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1),
-        PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1),
-        PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1),
-        PINMUX_DATA(CS4_MARK, PORT90_FN1),
-        PINMUX_DATA(CS5A_MARK, PORT91_FN1),
-        PINMUX_DATA(FMSICK_MARK, PORT91_FN2),
-        PINMUX_DATA(CS5B_MARK, PORT92_FN1),
-        PINMUX_DATA(FCE1_MARK, PORT92_FN2),
-        /* 55-3 (FN) */
-        PINMUX_DATA(CS6B_MARK, PORT93_FN1),
-        PINMUX_DATA(XCS2_MARK, PORT93_FN2),
-        PINMUX_DATA(CS6A_MARK, PORT93_FN3),
-        PINMUX_DATA(DACK0_MARK, PORT93_FN4),
-        PINMUX_DATA(FCE0_MARK, PORT94_FN1),
-        PINMUX_DATA(WAIT_MARK, PORT95_FN1),
-        PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
-        PINMUX_DATA(RD_XRD_MARK, PORT96_FN1),
-        PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1),
-        PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1),
-        PINMUX_DATA(FRB_MARK, PORT99_FN1),
-        PINMUX_DATA(CKO_MARK, PORT100_FN1),
-        PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1),
-        PINMUX_DATA(NBRST_MARK, PORT102_FN1),
-        PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1),
-        PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1),
-        PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1),
-        PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1),
-        PINMUX_DATA(TCKON_MARK, PORT118_FN1),
-        PINMUX_DATA(VIO_VD_MARK, PORT128_FN1),
-        PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2),
-        PINMUX_DATA(IPORT0_MARK, PORT128_FN3),
-        PINMUX_DATA(VIO_HD_MARK, PORT129_FN1),
-        PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2),
-        PINMUX_DATA(IPORT1_MARK, PORT129_FN3),
-        PINMUX_DATA(VIO_D0_MARK, PORT130_FN1),
-        PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2),
-        PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3),
-        PINMUX_DATA(VIO_D1_MARK, PORT131_FN1),
-        PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2),
-        PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3),
-        PINMUX_DATA(VIO_D2_MARK, PORT132_FN1),
-        PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2),
-        PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3),
-        PINMUX_DATA(VIO_D3_MARK, PORT133_FN1),
-        PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2),
-        PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3),
-        PINMUX_DATA(VIO_D4_MARK, PORT134_FN1),
-        PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2),
-        PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3),
-        PINMUX_DATA(VIO_D5_MARK, PORT135_FN1),
-        PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2),
-        PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3),
-        PINMUX_DATA(VIO_D6_MARK, PORT136_FN1),
-        PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2),
-        PINMUX_DATA(VIO_D7_MARK, PORT137_FN1),
-        PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2),
-        PINMUX_DATA(VIO_D8_MARK, PORT138_FN1),
-        PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2),
-        PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3),
-        PINMUX_DATA(VIO_D9_MARK, PORT139_FN1),
-        PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2),
-        PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3),
-        PINMUX_DATA(VIO_D10_MARK, PORT140_FN1),
-        PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2),
-        PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3),
-        PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4),
-        PINMUX_DATA(VIO_D11_MARK, PORT141_FN1),
-        PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2),
-        PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3),
-        PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4),
-        PINMUX_DATA(VIO_D12_MARK, PORT142_FN1),
-        PINMUX_DATA(M13_BSW_MARK, PORT142_FN2),
-        PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3),
-        PINMUX_DATA(VIO_D13_MARK, PORT143_FN1),
-        PINMUX_DATA(M14_GSW_MARK, PORT143_FN2),
-        PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3),
-        PINMUX_DATA(VIO_D14_MARK, PORT144_FN1),
-        PINMUX_DATA(M15_RSW_MARK, PORT144_FN2),
-        PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3),
-        PINMUX_DATA(VIO_D15_MARK, PORT145_FN1),
-        PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2),
-        PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3),
-        PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1),
-        PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2),
-        PINMUX_DATA(IPORT2_MARK, PORT146_FN3),
-        PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1),
-        PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2),
-        PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
-        PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2),
-        PINMUX_DATA(A27_MARK, PORT149_FN1),
-        PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2),
-        PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3),
-        PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1),
-        PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1),
-        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2),
-        PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1),
-        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2),
-        PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1),
-        PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2),
-        PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3),
-        PINMUX_DATA(SOUT3_MARK, PORT154_FN1),
-        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2),
-        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3),
-        PINMUX_DATA(SIN3_MARK, PORT155_FN1),
-        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2),
-        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3),
-        PINMUX_DATA(XRTS3_MARK, PORT156_FN1),
-        PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2),
-        PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3),
-        PINMUX_DATA(XCTS3_MARK, PORT157_FN1),
-        PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2),
-        PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3),
-        /* 55-4 (FN) */
-        PINMUX_DATA(DINT_MARK, PORT158_FN1),
-        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2),
-        PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3),
-        PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1),
-        PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2),
-        PINMUX_DATA(NMI_MARK, PORT159_FN3),
-        PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1),
-        PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2),
-        PINMUX_DATA(SOUT0_MARK, PORT160_FN3),
-        PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1),
-        PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2),
-        PINMUX_DATA(XCTS0_MARK, PORT161_FN3),
-        PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4),
-        PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1),
-        PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2),
-        PINMUX_DATA(SIN0_MARK, PORT162_FN3),
-        PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4),
-        PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1),
-        PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2),
-        PINMUX_DATA(XRTS0_MARK, PORT163_FN3),
-        PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4),
-        PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
-        PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
-        PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2),
-        PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3),
-        PINMUX_DATA(LCDD1_MARK, PORT193_FN1),
-        PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2),
-        PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3),
-        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4),
-        PINMUX_DATA(LCDD2_MARK, PORT194_FN1),
-        PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2),
-        PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3),
-        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4),
-        PINMUX_DATA(LCDD3_MARK, PORT195_FN1),
-        PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2),
-        PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3),
-        PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4),
-        PINMUX_DATA(LCDD4_MARK, PORT196_FN1),
-        PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2),
-        PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3),
-        PINMUX_DATA(LCDD5_MARK, PORT197_FN1),
-        PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2),
-        PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3),
-        PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4),
-        PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
-        PINMUX_DATA(LCDD7_MARK, PORT199_FN1),
-        PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2),
-        PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3),
-        PINMUX_DATA(LCDD8_MARK, PORT200_FN1),
-        PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2),
-        PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3),
-        PINMUX_DATA(D16_MARK, PORT200_FN4),
-        PINMUX_DATA(LCDD9_MARK, PORT201_FN1),
-        PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2),
-        PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3),
-        PINMUX_DATA(D17_MARK, PORT201_FN4),
-        PINMUX_DATA(LCDD10_MARK, PORT202_FN1),
-        PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2),
-        PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3),
-        PINMUX_DATA(D18_MARK, PORT202_FN4),
-        PINMUX_DATA(LCDD11_MARK, PORT203_FN1),
-        PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2),
-        PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3),
-        PINMUX_DATA(D19_MARK, PORT203_FN4),
-        PINMUX_DATA(LCDD12_MARK, PORT204_FN1),
-        PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2),
-        PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3),
-        PINMUX_DATA(D20_MARK, PORT204_FN4),
-        PINMUX_DATA(LCDD13_MARK, PORT205_FN1),
-        PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2),
-        PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3),
-        PINMUX_DATA(D21_MARK, PORT205_FN4),
-        PINMUX_DATA(LCDD14_MARK, PORT206_FN1),
-        PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2),
-        PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3),
-        PINMUX_DATA(D22_MARK, PORT206_FN4),
-        PINMUX_DATA(LCDD15_MARK, PORT207_FN1),
-        PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2),
-        PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3),
-        PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4),
-        PINMUX_DATA(D23_MARK, PORT207_FN5),
-        PINMUX_DATA(LCDD16_MARK, PORT208_FN1),
-        PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2),
-        PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3),
-        PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4),
-        PINMUX_DATA(D24_MARK, PORT208_FN5),
-        PINMUX_DATA(LCDD17_MARK, PORT209_FN1),
-        PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2),
-        PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3),
-        PINMUX_DATA(D25_MARK, PORT209_FN4),
-        PINMUX_DATA(LCDD18_MARK, PORT210_FN1),
-        PINMUX_DATA(DREQ2_MARK, PORT210_FN2),
-        PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3),
-        PINMUX_DATA(D26_MARK, PORT210_FN4),
-        PINMUX_DATA(LCDD19_MARK, PORT211_FN1),
-        PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2),
-        PINMUX_DATA(D27_MARK, PORT211_FN3),
-        PINMUX_DATA(LCDD20_MARK, PORT212_FN1),
-        PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2),
-        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3),
-        PINMUX_DATA(D28_MARK, PORT212_FN4),
-        PINMUX_DATA(LCDD21_MARK, PORT213_FN1),
-        PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2),
-        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3),
-        PINMUX_DATA(D29_MARK, PORT213_FN4),
-        PINMUX_DATA(LCDD22_MARK, PORT214_FN1),
-        PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2),
-        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3),
-        PINMUX_DATA(D30_MARK, PORT214_FN4),
-        PINMUX_DATA(LCDD23_MARK, PORT215_FN1),
-        PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2),
-        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3),
-        PINMUX_DATA(D31_MARK, PORT215_FN4),
-        PINMUX_DATA(LCDDCK_MARK, PORT216_FN1),
-        PINMUX_DATA(LCDWR_MARK, PORT216_FN2),
-        PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3),
-        PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4),
-        PINMUX_DATA(LCDRD_MARK, PORT217_FN1),
-        PINMUX_DATA(DACK2_MARK, PORT217_FN2),
-        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3),
-        PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1),
-        PINMUX_DATA(LCDCS_MARK, PORT218_FN2),
-        PINMUX_DATA(LCDCS2_MARK, PORT218_FN3),
-        PINMUX_DATA(DACK3_MARK, PORT218_FN4),
-        PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
-        PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6),
-        PINMUX_DATA(LCDDISP_MARK, PORT219_FN1),
-        PINMUX_DATA(LCDRS_MARK, PORT219_FN2),
-        PINMUX_DATA(DREQ3_MARK, PORT219_FN3),
-        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4),
-        PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1),
-        PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
-        PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3),
-        PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1),
-        PINMUX_DATA(DREQ1_MARK, PORT221_FN2),
-        PINMUX_DATA(PWEN_MARK, PORT221_FN3),
-        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4),
-        PINMUX_DATA(LCDDON_MARK, PORT222_FN1),
-        PINMUX_DATA(LCDDON2_MARK, PORT222_FN2),
-        PINMUX_DATA(DACK1_MARK, PORT222_FN3),
-        PINMUX_DATA(OVCN_MARK, PORT222_FN4),
-        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5),
-        PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1),
-        PINMUX_DATA(OVCN2_MARK, PORT225_FN2),
-        PINMUX_DATA(EXTLP_MARK, PORT226_FN1),
-        PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2),
-        PINMUX_DATA(USBTERM_MARK, PORT226_FN3),
-        PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4),
-        PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1),
-        PINMUX_DATA(IDIN_MARK, PORT227_FN2),
-        PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1),
-        PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1),
-        PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2),
-        PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1),
-        PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2),
-        PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3),
-        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1),
-        PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2),
-        PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3),
-        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1),
-        PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2),
-        PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3),
-        PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1),
-        PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2),
-        PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3),
-        PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4),
-        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1),
-        PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2),
-        PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3),
-        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1),
-        PINMUX_DATA(OPORT0_MARK, PORT235_FN2),
-        PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3),
-        PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4),
-        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1),
-        PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2),
-        PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3),
-        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1),
-        PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2),
-        PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3),
-        PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1),
-        PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2),
-        /* 55-5 (FN) */
-        PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1),
-        PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
-        PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1),
-        PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2),
-        PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3),
-        PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
-        PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1),
-        PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2),
-        PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1),
-        PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
-        PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1),
-        PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2),
-        PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3),
-        PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1),
-        PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2),
-        PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3),
-        PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1),
-        PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2),
-        PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3),
-        PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
-        PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1),
-        PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2),
-        PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3),
-        PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
-        PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1),
-        PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2),
-        PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3),
-        PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4),
-        PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1),
-        PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2),
-        PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
-        PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2),
-        PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
-        PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
-        PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2),
-        PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
-        PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2),
-        PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
-        PINMUX_DATA(TDI2_MARK, PORT254_FN2),
-        PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
-        PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2),
-        PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
-        PINMUX_DATA(TRST2_MARK, PORT256_FN2),
-        PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
-        PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2),
-        PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
-        PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2),
-        PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1),
-        PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2),
-        PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
-        PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4),
-        PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1),
-        PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2),
-        PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
-        PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4),
-        PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1),
-        PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2),
-        PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
-        PINMUX_DATA(TDI3_MARK, PORT261_FN4),
-        PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1),
-        PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2),
-        PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
-        PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4),
-        PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
-        PINMUX_DATA(TRST3_MARK, PORT263_FN2),
-        PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
-};
-static struct pinmux_gpio pinmux_gpios[] = {
-        /* 55-1 -> 55-5 (GPIO) */
-        GPIO_PORT_ALL(),
-        /* Special Pull-up / Pull-down Functions */
-        GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
-        GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU),
-        GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU),
-        GPIO_FN(PORT72_KEYIN6_PU),
-        /* 55-1 (FN) */
-        GPIO_FN(VBUS_0),
-        GPIO_FN(CPORT0),
-        GPIO_FN(CPORT1),
-        GPIO_FN(CPORT2),
-        GPIO_FN(CPORT3),
-        GPIO_FN(CPORT4),
-        GPIO_FN(CPORT5),
-        GPIO_FN(CPORT6),
-        GPIO_FN(CPORT7),
-        GPIO_FN(CPORT8),
-        GPIO_FN(CPORT9),
-        GPIO_FN(CPORT10),
-        GPIO_FN(CPORT11), GPIO_FN(SIN2),
-        GPIO_FN(CPORT12), GPIO_FN(XCTS2),
-        GPIO_FN(CPORT13), GPIO_FN(RFSPO4),
-        GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
-        GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2),
-        GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3),
-        GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2),
-        GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(CPORT19_MPORT1),
-        GPIO_FN(CPORT20), GPIO_FN(RFSPO6),
-        GPIO_FN(CPORT21), GPIO_FN(STATUS0),
-        GPIO_FN(CPORT22), GPIO_FN(STATUS1),
-        GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
-        GPIO_FN(B_SYNLD1),
-        GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK),
-        GPIO_FN(XMAINPS),
-        GPIO_FN(XDIVPS),
-        GPIO_FN(XIDRST),
-        GPIO_FN(IDCLK), GPIO_FN(IC_DP),
-        GPIO_FN(IDIO), GPIO_FN(IC_DM),
-        GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT),
-        GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
-        GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
-        GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
-        GPIO_FN(PCMCLKO),
-        GPIO_FN(SYNC8KO),
-        /* 55-2 (FN) */
-        GPIO_FN(DNPCM_A),
-        GPIO_FN(UPPCM_A),
-        GPIO_FN(VACK),
-        GPIO_FN(XTALB1L),
-        GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
-        GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS),
-        GPIO_FN(GPS_IM),
-        GPIO_FN(GPS_IS),
-        GPIO_FN(GPS_QM),
-        GPIO_FN(GPS_QS),
-        GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT),
-        GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2),
-        GPIO_FN(IPORT3), GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3),
-        GPIO_FN(OPORT1), GPIO_FN(FMSIOBT),
-        GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2),
-        GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3),
-        GPIO_FN(OPORT3), GPIO_FN(FMSIILR),
-        GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2),
-        GPIO_FN(FMSIIBT),
-        GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0),
-        GPIO_FN(A0_EA0), GPIO_FN(BS),
-        GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2),
-        GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2),
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5),
-        GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4),
-        GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6),
-        GPIO_FN(D0_ED0_NAF0),
-        GPIO_FN(D1_ED1_NAF1),
-        GPIO_FN(D2_ED2_NAF2),
-        GPIO_FN(D3_ED3_NAF3),
-        GPIO_FN(D4_ED4_NAF4),
-        GPIO_FN(D5_ED5_NAF5),
-        GPIO_FN(D6_ED6_NAF6),
-        GPIO_FN(D7_ED7_NAF7),
-        GPIO_FN(D8_ED8_NAF8),
-        GPIO_FN(D9_ED9_NAF9),
-        GPIO_FN(D10_ED10_NAF10),
-        GPIO_FN(D11_ED11_NAF11),
-        GPIO_FN(D12_ED12_NAF12),
-        GPIO_FN(D13_ED13_NAF13),
-        GPIO_FN(D14_ED14_NAF14),
-        GPIO_FN(D15_ED15_NAF15),
-        GPIO_FN(CS4),
-        GPIO_FN(CS5A), GPIO_FN(FMSICK),
-        /* 55-3 (FN) */
-        GPIO_FN(CS5B), GPIO_FN(FCE1),
-        GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0),
-        GPIO_FN(FCE0),
-        GPIO_FN(WAIT), GPIO_FN(DREQ0),
-        GPIO_FN(RD_XRD),
-        GPIO_FN(WE0_XWR0_FWE),
-        GPIO_FN(WE1_XWR1),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT),
-        GPIO_FN(NBRST),
-        GPIO_FN(GPS_EPPSIN),
-        GPIO_FN(LATCHPULSE),
-        GPIO_FN(LTESIGNAL),
-        GPIO_FN(LEGACYSTATE),
-        GPIO_FN(TCKON),
-        GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0),
-        GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1),
-        GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD),
-        GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1),
-        GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2),
-        GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5),
-        GPIO_FN(PORT133_MSIOF2_TSYNC),
-        GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD),
-        GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK),
-        GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2),
-        GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3),
-        GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC),
-        GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR),
-        GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2),
-        GPIO_FN(PORT140_FSIAOBT),
-        GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3),
-        GPIO_FN(PORT141_FSIAOSLD),
-        GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK),
-        GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR),
-        GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT),
-        GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD),
-        GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2),
-        GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5),
-        GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6),
-        GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1),
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD),
-        /* 55-4 (FN) */
-        GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
-        GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI),
-        GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0),
-        GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0),
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0),
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0),
-        GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0),
-        GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI),
-        GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS),
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS),
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD),
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD),
-        GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK),
-        GPIO_FN(MFG2_OUT2),
-        GPIO_FN(LCDD6),
-        GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2),
-        GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0),
-        GPIO_FN(D16),
-        GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1),
-        GPIO_FN(D17),
-        GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2),
-        GPIO_FN(D18),
-        GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3),
-        GPIO_FN(D19),
-        GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4),
-        GPIO_FN(D20),
-        GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5),
-        GPIO_FN(D21),
-        GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6),
-        GPIO_FN(D22),
-        GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0),
-        GPIO_FN(VIO_DR7), GPIO_FN(D23),
-        GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1),
-        GPIO_FN(VIO_VDR), GPIO_FN(D24),
-        GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR),
-        GPIO_FN(D25),
-        GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1),
-        GPIO_FN(D26),
-        GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27),
-        GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
-        GPIO_FN(D28),
-        GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
-        GPIO_FN(D29),
-        GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK),
-        GPIO_FN(D30),
-        GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC),
-        GPIO_FN(D31),
-        GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3),
-        GPIO_FN(VIO_CLKR),
-        GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC),
-        GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
-        GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4),
-        GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK),
-        GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5),
-        GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD),
-        GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN),
-        GPIO_FN(MSIOF0L_TXD),
-        GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM),
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN),
-        GPIO_FN(SCIFA1_RXD),
-        GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC),
-        GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR),
-        GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT),
-        GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG),
-        GPIO_FN(PORT233_FSIACK),
-        GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD),
-        GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2),
-        GPIO_FN(PORT235_FSIAILR),
-        GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT),
-        GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD),
-        GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
-        /* 55-5 (FN) */
-        GPIO_FN(MSIOF1_SS2),
-        GPIO_FN(SCIFA6_TXD),
-        GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1),
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1),
-        GPIO_FN(PORT244_SCIFB_CTS),
-        GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2),
-        GPIO_FN(PORT245_SCIFB_RTS),
-        GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1),
-        GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0),
-        GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2),
-        GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1),
-        GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1),
-        GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0),
-        GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1),
-        GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0),
-        GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0),
-        GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
-        GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0),
-        GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
-        GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
-        GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1),
-        GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(TMS3_SWDIO_MC1),
-        GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2),
-        GPIO_FN(TDO3_SWO0_MC1),
-        GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2),
-        GPIO_FN(TDI3),
-        GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2),
-        GPIO_FN(RTCK3_SWO1_MC1),
-        GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
-        GPIO_FN(RESETOUTS),
-};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
-        PORTCR(0, 0xe6050000), /* PORT0CR */
-        PORTCR(1, 0xe6050001), /* PORT1CR */
-        PORTCR(2, 0xe6050002), /* PORT2CR */
-        PORTCR(3, 0xe6050003), /* PORT3CR */
-        PORTCR(4, 0xe6050004), /* PORT4CR */
-        PORTCR(5, 0xe6050005), /* PORT5CR */
-        PORTCR(6, 0xe6050006), /* PORT6CR */
-        PORTCR(7, 0xe6050007), /* PORT7CR */
-        PORTCR(8, 0xe6050008), /* PORT8CR */
-        PORTCR(9, 0xe6050009), /* PORT9CR */
-        PORTCR(10, 0xe605000a), /* PORT10CR */
-        PORTCR(11, 0xe605000b), /* PORT11CR */
-        PORTCR(12, 0xe605000c), /* PORT12CR */
-        PORTCR(13, 0xe605000d), /* PORT13CR */
-        PORTCR(14, 0xe605000e), /* PORT14CR */
-        PORTCR(15, 0xe605000f), /* PORT15CR */
-        PORTCR(16, 0xe6050010), /* PORT16CR */
-        PORTCR(17, 0xe6050011), /* PORT17CR */
-        PORTCR(18, 0xe6050012), /* PORT18CR */
-        PORTCR(19, 0xe6050013), /* PORT19CR */
-        PORTCR(20, 0xe6050014), /* PORT20CR */
-        PORTCR(21, 0xe6050015), /* PORT21CR */
-        PORTCR(22, 0xe6050016), /* PORT22CR */
-        PORTCR(23, 0xe6050017), /* PORT23CR */
-        PORTCR(24, 0xe6050018), /* PORT24CR */
-        PORTCR(25, 0xe6050019), /* PORT25CR */
-        PORTCR(26, 0xe605001a), /* PORT26CR */
-        PORTCR(27, 0xe605001b), /* PORT27CR */
-        PORTCR(28, 0xe605001c), /* PORT28CR */
-        PORTCR(29, 0xe605001d), /* PORT29CR */
-        PORTCR(30, 0xe605001e), /* PORT30CR */
-        PORTCR(31, 0xe605001f), /* PORT31CR */
-        PORTCR(32, 0xe6050020), /* PORT32CR */
-        PORTCR(33, 0xe6050021), /* PORT33CR */
-        PORTCR(34, 0xe6050022), /* PORT34CR */
-        PORTCR(35, 0xe6050023), /* PORT35CR */
-        PORTCR(36, 0xe6050024), /* PORT36CR */
-        PORTCR(37, 0xe6050025), /* PORT37CR */
-        PORTCR(38, 0xe6050026), /* PORT38CR */
-        PORTCR(39, 0xe6050027), /* PORT39CR */
-        PORTCR(40, 0xe6050028), /* PORT40CR */
-        PORTCR(41, 0xe6050029), /* PORT41CR */
-        PORTCR(42, 0xe605002a), /* PORT42CR */
-        PORTCR(43, 0xe605002b), /* PORT43CR */
-        PORTCR(44, 0xe605002c), /* PORT44CR */
-        PORTCR(45, 0xe605002d), /* PORT45CR */
-        PORTCR(46, 0xe605002e), /* PORT46CR */
-        PORTCR(47, 0xe605002f), /* PORT47CR */
-        PORTCR(48, 0xe6050030), /* PORT48CR */
-        PORTCR(49, 0xe6050031), /* PORT49CR */
-        PORTCR(50, 0xe6050032), /* PORT50CR */
-        PORTCR(51, 0xe6050033), /* PORT51CR */
-        PORTCR(52, 0xe6050034), /* PORT52CR */
-        PORTCR(53, 0xe6050035), /* PORT53CR */
-        PORTCR(54, 0xe6050036), /* PORT54CR */
-        PORTCR(55, 0xe6050037), /* PORT55CR */
-        PORTCR(56, 0xe6050038), /* PORT56CR */
-        PORTCR(57, 0xe6050039), /* PORT57CR */
-        PORTCR(58, 0xe605003a), /* PORT58CR */
-        PORTCR(59, 0xe605003b), /* PORT59CR */
-        PORTCR(60, 0xe605003c), /* PORT60CR */
-        PORTCR(61, 0xe605003d), /* PORT61CR */
-        PORTCR(62, 0xe605003e), /* PORT62CR */
-        PORTCR(63, 0xe605003f), /* PORT63CR */
-        PORTCR(64, 0xe6050040), /* PORT64CR */
-        PORTCR(65, 0xe6050041), /* PORT65CR */
-        PORTCR(66, 0xe6050042), /* PORT66CR */
-        PORTCR(67, 0xe6050043), /* PORT67CR */
-        PORTCR(68, 0xe6050044), /* PORT68CR */
-        PORTCR(69, 0xe6050045), /* PORT69CR */
-        PORTCR(70, 0xe6050046), /* PORT70CR */
-        PORTCR(71, 0xe6050047), /* PORT71CR */
-        PORTCR(72, 0xe6050048), /* PORT72CR */
-        PORTCR(73, 0xe6050049), /* PORT73CR */
-        PORTCR(74, 0xe605004a), /* PORT74CR */
-        PORTCR(75, 0xe605004b), /* PORT75CR */
-        PORTCR(76, 0xe605004c), /* PORT76CR */
-        PORTCR(77, 0xe605004d), /* PORT77CR */
-        PORTCR(78, 0xe605004e), /* PORT78CR */
-        PORTCR(79, 0xe605004f), /* PORT79CR */
-        PORTCR(80, 0xe6050050), /* PORT80CR */
-        PORTCR(81, 0xe6050051), /* PORT81CR */
-        PORTCR(82, 0xe6050052), /* PORT82CR */
-        PORTCR(83, 0xe6050053), /* PORT83CR */
-        PORTCR(84, 0xe6050054), /* PORT84CR */
-        PORTCR(85, 0xe6050055), /* PORT85CR */
-        PORTCR(86, 0xe6050056), /* PORT86CR */
-        PORTCR(87, 0xe6050057), /* PORT87CR */
-        PORTCR(88, 0xe6050058), /* PORT88CR */
-        PORTCR(89, 0xe6050059), /* PORT89CR */
-        PORTCR(90, 0xe605005a), /* PORT90CR */
-        PORTCR(91, 0xe605005b), /* PORT91CR */
-        PORTCR(92, 0xe605005c), /* PORT92CR */
-        PORTCR(93, 0xe605005d), /* PORT93CR */
-        PORTCR(94, 0xe605005e), /* PORT94CR */
-        PORTCR(95, 0xe605005f), /* PORT95CR */
-        PORTCR(96, 0xe6050060), /* PORT96CR */
-        PORTCR(97, 0xe6050061), /* PORT97CR */
-        PORTCR(98, 0xe6050062), /* PORT98CR */
-        PORTCR(99, 0xe6050063), /* PORT99CR */
-        PORTCR(100, 0xe6050064), /* PORT100CR */
-        PORTCR(101, 0xe6050065), /* PORT101CR */
-        PORTCR(102, 0xe6050066), /* PORT102CR */
-        PORTCR(103, 0xe6050067), /* PORT103CR */
-        PORTCR(104, 0xe6050068), /* PORT104CR */
-        PORTCR(105, 0xe6050069), /* PORT105CR */
-        PORTCR(106, 0xe605006a), /* PORT106CR */
-        PORTCR(107, 0xe605006b), /* PORT107CR */
-        PORTCR(108, 0xe605006c), /* PORT108CR */
-        PORTCR(109, 0xe605006d), /* PORT109CR */
-        PORTCR(110, 0xe605006e), /* PORT110CR */
-        PORTCR(111, 0xe605006f), /* PORT111CR */
-        PORTCR(112, 0xe6050070), /* PORT112CR */
-        PORTCR(113, 0xe6050071), /* PORT113CR */
-        PORTCR(114, 0xe6050072), /* PORT114CR */
-        PORTCR(115, 0xe6050073), /* PORT115CR */
-        PORTCR(116, 0xe6050074), /* PORT116CR */
-        PORTCR(117, 0xe6050075), /* PORT117CR */
-        PORTCR(118, 0xe6050076), /* PORT118CR */
-        PORTCR(128, 0xe6051080), /* PORT128CR */
-        PORTCR(129, 0xe6051081), /* PORT129CR */
-        PORTCR(130, 0xe6051082), /* PORT130CR */
-        PORTCR(131, 0xe6051083), /* PORT131CR */
-        PORTCR(132, 0xe6051084), /* PORT132CR */
-        PORTCR(133, 0xe6051085), /* PORT133CR */
-        PORTCR(134, 0xe6051086), /* PORT134CR */
-        PORTCR(135, 0xe6051087), /* PORT135CR */
-        PORTCR(136, 0xe6051088), /* PORT136CR */
-        PORTCR(137, 0xe6051089), /* PORT137CR */
-        PORTCR(138, 0xe605108a), /* PORT138CR */
-        PORTCR(139, 0xe605108b), /* PORT139CR */
-        PORTCR(140, 0xe605108c), /* PORT140CR */
-        PORTCR(141, 0xe605108d), /* PORT141CR */
-        PORTCR(142, 0xe605108e), /* PORT142CR */
-        PORTCR(143, 0xe605108f), /* PORT143CR */
-        PORTCR(144, 0xe6051090), /* PORT144CR */
-        PORTCR(145, 0xe6051091), /* PORT145CR */
-        PORTCR(146, 0xe6051092), /* PORT146CR */
-        PORTCR(147, 0xe6051093), /* PORT147CR */
-        PORTCR(148, 0xe6051094), /* PORT148CR */
-        PORTCR(149, 0xe6051095), /* PORT149CR */
-        PORTCR(150, 0xe6051096), /* PORT150CR */
-        PORTCR(151, 0xe6051097), /* PORT151CR */
-        PORTCR(152, 0xe6051098), /* PORT152CR */
-        PORTCR(153, 0xe6051099), /* PORT153CR */
-        PORTCR(154, 0xe605109a), /* PORT154CR */
-        PORTCR(155, 0xe605109b), /* PORT155CR */
-        PORTCR(156, 0xe605109c), /* PORT156CR */
-        PORTCR(157, 0xe605109d), /* PORT157CR */
-        PORTCR(158, 0xe605109e), /* PORT158CR */
-        PORTCR(159, 0xe605109f), /* PORT159CR */
-        PORTCR(160, 0xe60510a0), /* PORT160CR */
-        PORTCR(161, 0xe60510a1), /* PORT161CR */
-        PORTCR(162, 0xe60510a2), /* PORT162CR */
-        PORTCR(163, 0xe60510a3), /* PORT163CR */
-        PORTCR(164, 0xe60510a4), /* PORT164CR */
-        PORTCR(192, 0xe60520c0), /* PORT192CR */
-        PORTCR(193, 0xe60520c1), /* PORT193CR */
-        PORTCR(194, 0xe60520c2), /* PORT194CR */
-        PORTCR(195, 0xe60520c3), /* PORT195CR */
-        PORTCR(196, 0xe60520c4), /* PORT196CR */
-        PORTCR(197, 0xe60520c5), /* PORT197CR */
-        PORTCR(198, 0xe60520c6), /* PORT198CR */
-        PORTCR(199, 0xe60520c7), /* PORT199CR */
-        PORTCR(200, 0xe60520c8), /* PORT200CR */
-        PORTCR(201, 0xe60520c9), /* PORT201CR */
-        PORTCR(202, 0xe60520ca), /* PORT202CR */
-        PORTCR(203, 0xe60520cb), /* PORT203CR */
-        PORTCR(204, 0xe60520cc), /* PORT204CR */
-        PORTCR(205, 0xe60520cd), /* PORT205CR */
-        PORTCR(206, 0xe60520ce), /* PORT206CR */
-        PORTCR(207, 0xe60520cf), /* PORT207CR */
-        PORTCR(208, 0xe60520d0), /* PORT208CR */
-        PORTCR(209, 0xe60520d1), /* PORT209CR */
-        PORTCR(210, 0xe60520d2), /* PORT210CR */
-        PORTCR(211, 0xe60520d3), /* PORT211CR */
-        PORTCR(212, 0xe60520d4), /* PORT212CR */
-        PORTCR(213, 0xe60520d5), /* PORT213CR */
-        PORTCR(214, 0xe60520d6), /* PORT214CR */
-        PORTCR(215, 0xe60520d7), /* PORT215CR */
-        PORTCR(216, 0xe60520d8), /* PORT216CR */
-        PORTCR(217, 0xe60520d9), /* PORT217CR */
-        PORTCR(218, 0xe60520da), /* PORT218CR */
-        PORTCR(219, 0xe60520db), /* PORT219CR */
-        PORTCR(220, 0xe60520dc), /* PORT220CR */
-        PORTCR(221, 0xe60520dd), /* PORT221CR */
-        PORTCR(222, 0xe60520de), /* PORT222CR */
-        PORTCR(223, 0xe60520df), /* PORT223CR */
-        PORTCR(224, 0xe60520e0), /* PORT224CR */
-        PORTCR(225, 0xe60520e1), /* PORT225CR */
-        PORTCR(226, 0xe60520e2), /* PORT226CR */
-        PORTCR(227, 0xe60520e3), /* PORT227CR */
-        PORTCR(228, 0xe60520e4), /* PORT228CR */
-        PORTCR(229, 0xe60520e5), /* PORT229CR */
-        PORTCR(230, 0xe60520e6), /* PORT230CR */
-        PORTCR(231, 0xe60520e7), /* PORT231CR */
-        PORTCR(232, 0xe60520e8), /* PORT232CR */
-        PORTCR(233, 0xe60520e9), /* PORT233CR */
-        PORTCR(234, 0xe60520ea), /* PORT234CR */
-        PORTCR(235, 0xe60520eb), /* PORT235CR */
-        PORTCR(236, 0xe60520ec), /* PORT236CR */
-        PORTCR(237, 0xe60520ed), /* PORT237CR */
-        PORTCR(238, 0xe60520ee), /* PORT238CR */
-        PORTCR(239, 0xe60520ef), /* PORT239CR */
-        PORTCR(240, 0xe60520f0), /* PORT240CR */
-        PORTCR(241, 0xe60520f1), /* PORT241CR */
-        PORTCR(242, 0xe60520f2), /* PORT242CR */
-        PORTCR(243, 0xe60520f3), /* PORT243CR */
-        PORTCR(244, 0xe60520f4), /* PORT244CR */
-        PORTCR(245, 0xe60520f5), /* PORT245CR */
-        PORTCR(246, 0xe60520f6), /* PORT246CR */
-        PORTCR(247, 0xe60520f7), /* PORT247CR */
-        PORTCR(248, 0xe60520f8), /* PORT248CR */
-        PORTCR(249, 0xe60520f9), /* PORT249CR */
-        PORTCR(250, 0xe60520fa), /* PORT250CR */
-        PORTCR(251, 0xe60520fb), /* PORT251CR */
-        PORTCR(252, 0xe60520fc), /* PORT252CR */
-        PORTCR(253, 0xe60520fd), /* PORT253CR */
-        PORTCR(254, 0xe60520fe), /* PORT254CR */
-        PORTCR(255, 0xe60520ff), /* PORT255CR */
-        PORTCR(256, 0xe6052100), /* PORT256CR */
-        PORTCR(257, 0xe6052101), /* PORT257CR */
-        PORTCR(258, 0xe6052102), /* PORT258CR */
-        PORTCR(259, 0xe6052103), /* PORT259CR */
-        PORTCR(260, 0xe6052104), /* PORT260CR */
-        PORTCR(261, 0xe6052105), /* PORT261CR */
-        PORTCR(262, 0xe6052106), /* PORT262CR */
-        PORTCR(263, 0xe6052107), /* PORT263CR */
-        PORTCR(264, 0xe6052108), /* PORT264CR */
-        { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        MSELBCR_MSEL17_0, MSELBCR_MSEL17_1,
-                        MSELBCR_MSEL16_0, MSELBCR_MSEL16_1,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
-        },
-        { },
-};
-static struct pinmux_data_reg pinmux_data_regs[] = {
-        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
-                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
-                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
-                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
-                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
-                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
-                        PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
-                        PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
-                        PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
-                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
-                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
-                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
-                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
-                        PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
-                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
-                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
-                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
-        },
-        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
-                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
-                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
-                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
-                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
-                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
-                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
-                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
-                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
-                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
-                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
-                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
-                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
-                        PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
-        },
-        { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) {
-                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
-                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
-                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
-                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
-                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
-                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
-                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
-                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT164_DATA,
-                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
-        },
-        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) {
-                        PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
-                        PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
-                        PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
-                        PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
-                        PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
-                        PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
-                        PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
-                        PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) {
-                        PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
-                        PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
-                        PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
-                        PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
-                        PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
-                        PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
-                        PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
-                        PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
-        },
-        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) {
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, 0,
-                        0, 0, 0, PORT264_DATA,
-                        PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
-                        PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
-        },
-        { },
-};
-static struct pinmux_info sh7377_pinmux_info = {
-        .name = "sh7377_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
-        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
-        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
-        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_RESETOUTS,
-        .gpios = pinmux_gpios,
-        .cfg_regs = pinmux_config_regs,
-        .data_regs = pinmux_data_regs,
-        .gpio_data = pinmux_data,
-        .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-void sh7377_pinmux_init(void)
-{
-        register_pinmux(&sh7377_pinmux_info);
-}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 11bb1d984197..095222469d03 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -66,12 +66,6 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
 void __init r8a7740_map_io(void)
 {
        iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
-        /*
-         * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
-         * enough to allocate the frame buffer memory.
-         */
-        init_consistent_dma_size(12 << 20);
 }
 /* SCIFA0 */
@@ -590,6 +584,21 @@ static struct platform_device i2c1_device = {
        .num_resources  = ARRAY_SIZE(i2c1_resources),
 };
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = evt2irq(0x19a0),
+                .end    = evt2irq(0x19a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device pmu_device = {
+        .name   = "arm-pmu",
+        .id     = -1,
+        .num_resources = ARRAY_SIZE(pmu_resources),
+        .resource = pmu_resources,
+};
 static struct platform_device *r8a7740_late_devices[] __initdata = {
        &i2c0_device,
        &i2c1_device,
@@ -597,6 +606,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
        &dma1_device,
        &dma2_device,
        &usb_dma_device,
+        &pmu_device,
 };
 /*
@@ -747,7 +757,7 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
        NULL,
 };
-DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
+DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
        .map_io         = r8a7740_map_io,
        .init_early     = r8a7740_add_early_devices_dt,
        .init_irq       = r8a7740_init_irq,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index ebbffc25f24f..7a1ad4f38539 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -229,6 +229,79 @@ static struct platform_device tmu01_device = {
        .num_resources  = ARRAY_SIZE(tmu01_resources),
 };
+/* I2C */
+static struct resource rcar_i2c0_res[] = {
+        {
+                .start  = 0xffc70000,
+                .end    = 0xffc70fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(79),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c0_device = {
+        .name           = "i2c-rcar",
+        .id             = 0,
+        .resource       = rcar_i2c0_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
+};
+static struct resource rcar_i2c1_res[] = {
+        {
+                .start  = 0xffc71000,
+                .end    = 0xffc71fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(82),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c1_device = {
+        .name           = "i2c-rcar",
+        .id             = 1,
+        .resource       = rcar_i2c1_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
+};
+static struct resource rcar_i2c2_res[] = {
+        {
+                .start  = 0xffc72000,
+                .end    = 0xffc72fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(80),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c2_device = {
+        .name           = "i2c-rcar",
+        .id             = 2,
+        .resource       = rcar_i2c2_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
+};
+static struct resource rcar_i2c3_res[] = {
+        {
+                .start  = 0xffc73000,
+                .end    = 0xffc73fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = gic_spi(81),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c3_device = {
+        .name           = "i2c-rcar",
+        .id             = 3,
+        .resource       = rcar_i2c3_res,
+        .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
+};
 static struct platform_device *r8a7779_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -238,6 +311,10 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
        &scif5_device,
        &tmu00_device,
        &tmu01_device,
+        &i2c0_device,
+        &i2c1_device,
+        &i2c2_device,
+        &i2c3_device,
 };
 static struct platform_device *r8a7779_late_devices[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
deleted file mode 100644
index e647f5410879..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- * sh7367 processor support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/uio_driver.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_timer.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-static struct map_desc sh7367_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-void __init sh7367_map_io(void)
-{
-        iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
-}
-/* SCIFA0 */
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe6c40000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
-                            evt2irq(0xc00), evt2irq(0xc00) },
-};
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-/* SCIFA1 */
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe6c50000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
-                            evt2irq(0xc20), evt2irq(0xc20) },
-};
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-/* SCIFA2 */
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe6c60000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
-                            evt2irq(0xc40), evt2irq(0xc40) },
-};
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-/* SCIFA3 */
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe6c70000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
-                            evt2irq(0xc60), evt2irq(0xc60) },
-};
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-/* SCIFA4 */
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe6c80000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
-                            evt2irq(0xd20), evt2irq(0xd20) },
-};
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-/* SCIFA5 */
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe6cb0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
-                            evt2irq(0xd40), evt2irq(0xd40) },
-};
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
-/* SCIFB */
-static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe6c30000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFB,
-        .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
-                            evt2irq(0xd60), evt2irq(0xd60) },
-};
-static struct platform_device scif6_device = {
-        .name           = "sh-sci",
-        .id             = 6,
-        .dev            = {
-                .platform_data  = &scif6_platform_data,
-        },
-};
-static struct sh_timer_config cmt10_platform_data = {
-        .name = "CMT10",
-        .channel_offset = 0x10,
-        .timer_bit = 0,
-        .clockevent_rating = 125,
-        .clocksource_rating = 125,
-};
-static struct resource cmt10_resources[] = {
-        [0] = {
-                .name   = "CMT10",
-                .start  = 0xe6138010,
-                .end    = 0xe613801b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0xb00), /* CMT1_CMT10 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device cmt10_device = {
-        .name           = "sh_cmt",
-        .id             = 10,
-        .dev = {
-                .platform_data  = &cmt10_platform_data,
-        },
-        .resource       = cmt10_resources,
-        .num_resources  = ARRAY_SIZE(cmt10_resources),
-};
-/* VPU */
-static struct uio_info vpu_platform_data = {
-        .name = "VPU5",
-        .version = "0",
-        .irq = intcs_evt2irq(0x980),
-};
-static struct resource vpu_resources[] = {
-        [0] = {
-                .name   = "VPU",
-                .start  = 0xfe900000,
-                .end    = 0xfe902807,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device vpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 0,
-        .dev = {
-                .platform_data  = &vpu_platform_data,
-        },
-        .resource       = vpu_resources,
-        .num_resources  = ARRAY_SIZE(vpu_resources),
-};
-/* VEU0 */
-static struct uio_info veu0_platform_data = {
-        .name = "VEU0",
-        .version = "0",
-        .irq = intcs_evt2irq(0x700),
-};
-static struct resource veu0_resources[] = {
-        [0] = {
-                .name   = "VEU0",
-                .start  = 0xfe920000,
-                .end    = 0xfe9200b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &veu0_platform_data,
-        },
-        .resource       = veu0_resources,
-        .num_resources  = ARRAY_SIZE(veu0_resources),
-};
-/* VEU1 */
-static struct uio_info veu1_platform_data = {
-        .name = "VEU1",
-        .version = "0",
-        .irq = intcs_evt2irq(0x720),
-};
-static struct resource veu1_resources[] = {
-        [0] = {
-                .name   = "VEU1",
-                .start  = 0xfe924000,
-                .end    = 0xfe9240b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 2,
-        .dev = {
-                .platform_data  = &veu1_platform_data,
-        },
-        .resource       = veu1_resources,
-        .num_resources  = ARRAY_SIZE(veu1_resources),
-};
-/* VEU2 */
-static struct uio_info veu2_platform_data = {
-        .name = "VEU2",
-        .version = "0",
-        .irq = intcs_evt2irq(0x740),
-};
-static struct resource veu2_resources[] = {
-        [0] = {
-                .name   = "VEU2",
-                .start  = 0xfe928000,
-                .end    = 0xfe9280b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu2_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 3,
-        .dev = {
-                .platform_data  = &veu2_platform_data,
-        },
-        .resource       = veu2_resources,
-        .num_resources  = ARRAY_SIZE(veu2_resources),
-};
-/* VEU3 */
-static struct uio_info veu3_platform_data = {
-        .name = "VEU3",
-        .version = "0",
-        .irq = intcs_evt2irq(0x760),
-};
-static struct resource veu3_resources[] = {
-        [0] = {
-                .name   = "VEU3",
-                .start  = 0xfe92c000,
-                .end    = 0xfe92c0b7,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu3_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 4,
-        .dev = {
-                .platform_data  = &veu3_platform_data,
-        },
-        .resource       = veu3_resources,
-        .num_resources  = ARRAY_SIZE(veu3_resources),
-};
-/* VEU2H */
-static struct uio_info veu2h_platform_data = {
-        .name = "VEU2H",
-        .version = "0",
-        .irq = intcs_evt2irq(0x520),
-};
-static struct resource veu2h_resources[] = {
-        [0] = {
-                .name   = "VEU2H",
-                .start  = 0xfe93c000,
-                .end    = 0xfe93c27b,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu2h_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 5,
-        .dev = {
-                .platform_data  = &veu2h_platform_data,
-        },
-        .resource       = veu2h_resources,
-        .num_resources  = ARRAY_SIZE(veu2h_resources),
-};
-/* JPU */
-static struct uio_info jpu_platform_data = {
-        .name = "JPU",
-        .version = "0",
-        .irq = intcs_evt2irq(0x560),
-};
-static struct resource jpu_resources[] = {
-        [0] = {
-                .name   = "JPU",
-                .start  = 0xfe980000,
-                .end    = 0xfe9902d3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device jpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 6,
-        .dev = {
-                .platform_data  = &jpu_platform_data,
-        },
-        .resource       = jpu_resources,
-        .num_resources  = ARRAY_SIZE(jpu_resources),
-};
-/* SPU1 */
-static struct uio_info spu1_platform_data = {
-        .name = "SPU1",
-        .version = "0",
-        .irq = evt2irq(0xfc0),
-};
-static struct resource spu1_resources[] = {
-        [0] = {
-                .name   = "SPU1",
-                .start  = 0xfe300000,
-                .end    = 0xfe3fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device spu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 7,
-        .dev = {
-                .platform_data  = &spu1_platform_data,
-        },
-        .resource       = spu1_resources,
-        .num_resources  = ARRAY_SIZE(spu1_resources),
-};
-static struct platform_device *sh7367_early_devices[] __initdata = {
-        &scif0_device,
-        &scif1_device,
-        &scif2_device,
-        &scif3_device,
-        &scif4_device,
-        &scif5_device,
-        &scif6_device,
-        &cmt10_device,
-};
-static struct platform_device *sh7367_devices[] __initdata = {
-        &vpu_device,
-        &veu0_device,
-        &veu1_device,
-        &veu2_device,
-        &veu3_device,
-        &veu2h_device,
-        &jpu_device,
-        &spu1_device,
-};
-void __init sh7367_add_standard_devices(void)
-{
-        platform_add_devices(sh7367_early_devices,
-                             ARRAY_SIZE(sh7367_early_devices));
-        platform_add_devices(sh7367_devices,
-                            ARRAY_SIZE(sh7367_devices));
-}
-static void __init sh7367_earlytimer_init(void)
-{
-        sh7367_clock_init();
-        shmobile_earlytimer_init();
-}
-#define SYMSTPCR2 IOMEM(0xe6158048)
-#define SYMSTPCR2_CMT1 (1 << 29)
-void __init sh7367_add_early_devices(void)
-{
-        /* enable clock to CMT1 */
-        __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
-        early_platform_add_devices(sh7367_early_devices,
-                                   ARRAY_SIZE(sh7367_early_devices));
-        /* setup early console here as well */
-        shmobile_setup_console();
-        /* override timer setup with soc-specific code */
-        shmobile_timer.init = sh7367_earlytimer_init;
-}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index a07954fbcd22..c917882424a7 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -58,12 +58,6 @@ static struct map_desc sh7372_io_desc[] __initdata = {
 void __init sh7372_map_io(void)
 {
        iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
-        /*
-         * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
-         * enough to allocate the frame buffer memory.
-         */
-        init_consistent_dma_size(12 << 20);
 }
 /* SCIFA0 */
@@ -408,6 +402,26 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                .mid_rid        = 0x3e,
        }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
+                .addr           = 0xe6a30050,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x83,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
+                .addr           = 0xe6a30050,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x83,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
+                .addr           = 0xe6a30060,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x87,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
+                .addr           = 0xe6a30060,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x87,
+        }, {
                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
                .addr           = 0xe6850030,
                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
deleted file mode 100644
index edcf98bb7012..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/*
- * sh7377 processor support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/of_platform.h>
-#include <linux/uio_driver.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_intc.h>
-#include <linux/sh_timer.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/mach/map.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-static struct map_desc sh7377_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-void __init sh7377_map_io(void)
-{
-        iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
-}
-/* SCIFA0 */
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe6c40000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
-                            evt2irq(0xc00), evt2irq(0xc00) },
-};
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-/* SCIFA1 */
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe6c50000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
-                            evt2irq(0xc20), evt2irq(0xc20) },
-};
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-/* SCIFA2 */
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe6c60000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
-                            evt2irq(0xc40), evt2irq(0xc40) },
-};
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-/* SCIFA3 */
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe6c70000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
-                            evt2irq(0xc60), evt2irq(0xc60) },
-};
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-/* SCIFA4 */
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe6c80000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
-                            evt2irq(0xd20), evt2irq(0xd20) },
-};
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-/* SCIFA5 */
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe6cb0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
-                            evt2irq(0xd40), evt2irq(0xd40) },
-};
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
-/* SCIFA6 */
-static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe6cc0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
-                            intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
-};
-static struct platform_device scif6_device = {
-        .name           = "sh-sci",
-        .id             = 6,
-        .dev            = {
-                .platform_data  = &scif6_platform_data,
-        },
-};
-/* SCIFB */
-static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xe6c30000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFB,
-        .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
-                            evt2irq(0xd60), evt2irq(0xd60) },
-};
-static struct platform_device scif7_device = {
-        .name           = "sh-sci",
-        .id             = 7,
-        .dev            = {
-                .platform_data  = &scif7_platform_data,
-        },
-};
-static struct sh_timer_config cmt10_platform_data = {
-        .name = "CMT10",
-        .channel_offset = 0x10,
-        .timer_bit = 0,
-        .clockevent_rating = 125,
-        .clocksource_rating = 125,
-};
-static struct resource cmt10_resources[] = {
-        [0] = {
-                .name   = "CMT10",
-                .start  = 0xe6138010,
-                .end    = 0xe613801b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0xb00), /* CMT1_CMT10 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device cmt10_device = {
-        .name           = "sh_cmt",
-        .id             = 10,
-        .dev = {
-                .platform_data  = &cmt10_platform_data,
-        },
-        .resource       = cmt10_resources,
-        .num_resources  = ARRAY_SIZE(cmt10_resources),
-};
-/* VPU */
-static struct uio_info vpu_platform_data = {
-        .name = "VPU5HG",
-        .version = "0",
-        .irq = intcs_evt2irq(0x980),
-};
-static struct resource vpu_resources[] = {
-        [0] = {
-                .name   = "VPU",
-                .start  = 0xfe900000,
-                .end    = 0xfe900157,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device vpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 0,
-        .dev = {
-                .platform_data  = &vpu_platform_data,
-        },
-        .resource       = vpu_resources,
-        .num_resources  = ARRAY_SIZE(vpu_resources),
-};
-/* VEU0 */
-static struct uio_info veu0_platform_data = {
-        .name = "VEU0",
-        .version = "0",
-        .irq = intcs_evt2irq(0x700),
-};
-static struct resource veu0_resources[] = {
-        [0] = {
-                .name   = "VEU0",
-                .start  = 0xfe920000,
-                .end    = 0xfe9200cb,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &veu0_platform_data,
-        },
-        .resource       = veu0_resources,
-        .num_resources  = ARRAY_SIZE(veu0_resources),
-};
-/* VEU1 */
-static struct uio_info veu1_platform_data = {
-        .name = "VEU1",
-        .version = "0",
-        .irq = intcs_evt2irq(0x720),
-};
-static struct resource veu1_resources[] = {
-        [0] = {
-                .name   = "VEU1",
-                .start  = 0xfe924000,
-                .end    = 0xfe9240cb,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 2,
-        .dev = {
-                .platform_data  = &veu1_platform_data,
-        },
-        .resource       = veu1_resources,
-        .num_resources  = ARRAY_SIZE(veu1_resources),
-};
-/* VEU2 */
-static struct uio_info veu2_platform_data = {
-        .name = "VEU2",
-        .version = "0",
-        .irq = intcs_evt2irq(0x740),
-};
-static struct resource veu2_resources[] = {
-        [0] = {
-                .name   = "VEU2",
-                .start  = 0xfe928000,
-                .end    = 0xfe928307,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu2_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 3,
-        .dev = {
-                .platform_data  = &veu2_platform_data,
-        },
-        .resource       = veu2_resources,
-        .num_resources  = ARRAY_SIZE(veu2_resources),
-};
-/* VEU3 */
-static struct uio_info veu3_platform_data = {
-        .name = "VEU3",
-        .version = "0",
-        .irq = intcs_evt2irq(0x760),
-};
-static struct resource veu3_resources[] = {
-        [0] = {
-                .name   = "VEU3",
-                .start  = 0xfe92c000,
-                .end    = 0xfe92c307,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device veu3_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 4,
-        .dev = {
-                .platform_data  = &veu3_platform_data,
-        },
-        .resource       = veu3_resources,
-        .num_resources  = ARRAY_SIZE(veu3_resources),
-};
-/* JPU */
-static struct uio_info jpu_platform_data = {
-        .name = "JPU",
-        .version = "0",
-        .irq = intcs_evt2irq(0x560),
-};
-static struct resource jpu_resources[] = {
-        [0] = {
-                .name   = "JPU",
-                .start  = 0xfe980000,
-                .end    = 0xfe9902d3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device jpu_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 5,
-        .dev = {
-                .platform_data  = &jpu_platform_data,
-        },
-        .resource       = jpu_resources,
-        .num_resources  = ARRAY_SIZE(jpu_resources),
-};
-/* SPU2DSP0 */
-static struct uio_info spu0_platform_data = {
-        .name = "SPU2DSP0",
-        .version = "0",
-        .irq = evt2irq(0x1800),
-};
-static struct resource spu0_resources[] = {
-        [0] = {
-                .name   = "SPU2DSP0",
-                .start  = 0xfe200000,
-                .end    = 0xfe2fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device spu0_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 6,
-        .dev = {
-                .platform_data  = &spu0_platform_data,
-        },
-        .resource       = spu0_resources,
-        .num_resources  = ARRAY_SIZE(spu0_resources),
-};
-/* SPU2DSP1 */
-static struct uio_info spu1_platform_data = {
-        .name = "SPU2DSP1",
-        .version = "0",
-        .irq = evt2irq(0x1820),
-};
-static struct resource spu1_resources[] = {
-        [0] = {
-                .name   = "SPU2DSP1",
-                .start  = 0xfe300000,
-                .end    = 0xfe3fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device spu1_device = {
-        .name           = "uio_pdrv_genirq",
-        .id             = 7,
-        .dev = {
-                .platform_data  = &spu1_platform_data,
-        },
-        .resource       = spu1_resources,
-        .num_resources  = ARRAY_SIZE(spu1_resources),
-};
-static struct platform_device *sh7377_early_devices[] __initdata = {
-        &scif0_device,
-        &scif1_device,
-        &scif2_device,
-        &scif3_device,
-        &scif4_device,
-        &scif5_device,
-        &scif6_device,
-        &scif7_device,
-        &cmt10_device,
-};
-static struct platform_device *sh7377_devices[] __initdata = {
-        &vpu_device,
-        &veu0_device,
-        &veu1_device,
-        &veu2_device,
-        &veu3_device,
-        &jpu_device,
-        &spu0_device,
-        &spu1_device,
-};
-void __init sh7377_add_standard_devices(void)
-{
-        platform_add_devices(sh7377_early_devices,
-                            ARRAY_SIZE(sh7377_early_devices));
-        platform_add_devices(sh7377_devices,
-                            ARRAY_SIZE(sh7377_devices));
-}
-static void __init sh7377_earlytimer_init(void)
-{
-        sh7377_clock_init();
-        shmobile_earlytimer_init();
-}
-#define SMSTPCR3 IOMEM(0xe615013c)
-#define SMSTPCR3_CMT1 (1 << 29)
-void __init sh7377_add_early_devices(void)
-{
-        /* enable clock to CMT1 */
-        __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
-        early_platform_add_devices(sh7377_early_devices,
-                                   ARRAY_SIZE(sh7377_early_devices));
-        /* setup early console here as well */
-        shmobile_setup_console();
-        /* override timer setup with soc-specific code */
-        shmobile_timer.init = sh7377_earlytimer_init;
-}
-#ifdef CONFIG_USE_OF
-void __init sh7377_add_early_devices_dt(void)
-{
-        shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */
-        early_platform_add_devices(sh7377_early_devices,
-                                   ARRAY_SIZE(sh7377_early_devices));
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = {
-        { }
-};
-void __init sh7377_add_standard_devices_dt(void)
-{
-        /* clocks are setup late during boot in the case of DT */
-        sh7377_clock_init();
-        platform_add_devices(sh7377_early_devices,
-                            ARRAY_SIZE(sh7377_early_devices));
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             sh7377_auxdata_lookup, NULL);
-}
-static const char *sh7377_boards_compat_dt[] __initdata = {
-        "renesas,sh7377",
-        NULL,
-};
-DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)")
-        .map_io         = sh7377_map_io,
-        .init_early     = sh7377_add_early_devices_dt,
-        .init_irq       = sh7377_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = sh7377_add_standard_devices_dt,
-        .timer          = &shmobile_timer,
-        .dt_compat      = sh7377_boards_compat_dt,
-MACHINE_END
-#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 803a3281feb5..566e804d4036 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -12,5 +12,6 @@ config ARCH_SOCFPGA
        select GENERIC_CLOCKEVENTS
        select GPIO_PL061 if GPIOLIB
        select HAVE_ARM_SCU
+        select HAVE_SMP
        select SPARSE_IRQ
        select USE_OF
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4fb93240971d..6dd7a93a90fe 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -3,3 +3,4 @@
 #
 obj-y                                   := socfpga.o
+obj-$(CONFIG_SMP)       += headsmp.o platsmp.o
diff --git a/arch/arm/mach-vt8500/include/mach/irqs.h b/arch/arm/mach-socfpga/core.h
index a129fd1222fb..9941caa94931 100644
--- a/arch/arm/mach-vt8500/include/mach/irqs.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -1,7 +1,6 @@
 /*
- *  arch/arm/mach-vt8500/include/mach/irqs.h
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
- *
+ * Copyright (C) 2012 Altera Corporation
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -18,5 +17,18 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/* This value is just to make the core happy, never used otherwise */
+#ifndef __MACH_CORE_H
-#define NR_IRQS 128
+#define __MACH_CORE_H
+extern void secondary_startup(void);
+extern void __iomem *socfpga_scu_base_addr;
+extern void socfpga_init_clocks(void);
+extern void socfpga_sysmgr_init(void);
+extern struct smp_operations socfpga_smp_ops;
+extern char secondary_trampoline, secondary_trampoline_end;
+#define SOCFPGA_SCU_VIRT_BASE   0xfffec000
+#endif
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
new file mode 100644
index 000000000000..f09b1283ffca
--- /dev/null
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -0,0 +1,25 @@
+/*
+ *  Copyright (c) 2003 ARM Limited
+ *  Copyright (c) u-boot contributors
+ *  Copyright (c) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+        __CPUINIT
+        .arch   armv7-a
+#define CPU1_START_ADDR                 0xffd08010
+ENTRY(secondary_trampoline)
+        movw    r0, #:lower16:CPU1_START_ADDR
+        movt  r0, #:upper16:CPU1_START_ADDR
+        ldr     r1, [r0]
+        bx      r1
+ENTRY(secondary_trampoline_end)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
new file mode 100644
index 000000000000..68dd1b69512a
--- /dev/null
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+#include "core.h"
+extern void __iomem *sys_manager_base_addr;
+extern void __iomem *rst_manager_base_addr;
+static void __cpuinit socfpga_secondary_init(unsigned int cpu)
+{
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_secondary_init(0);
+}
+static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+        memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+        __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+        flush_cache_all();
+        smp_wmb();
+        outer_clean_range(0, trampoline_size);
+        /* This will release CPU #1 out of reset.*/
+        __raw_writel(0, rst_manager_base_addr + 0x10);
+        return 0;
+}
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init socfpga_smp_init_cpus(void)
+{
+        unsigned int i, ncores;
+        ncores = scu_get_core_count(socfpga_scu_base_addr);
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+        /* sanity check */
+        if (ncores > num_possible_cpus()) {
+                pr_warn("socfpga: no. of cores (%d) greater than configured"
+                        "maximum of %d - clipping\n", ncores, num_possible_cpus());
+                ncores = num_possible_cpus();
+        }
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+        set_smp_cross_call(gic_raise_softirq);
+}
+static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
+{
+        scu_enable(socfpga_scu_base_addr);
+}
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+static void socfpga_cpu_die(unsigned int cpu)
+{
+        cpu_do_idle();
+        /* We should have never returned from idle */
+        panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+}
+struct smp_operations socfpga_smp_ops __initdata = {
+        .smp_init_cpus          = socfpga_smp_init_cpus,
+        .smp_prepare_cpus       = socfpga_smp_prepare_cpus,
+        .smp_secondary_init     = socfpga_secondary_init,
+        .smp_boot_secondary     = socfpga_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = socfpga_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index f01e1ebf5396..6732924a5fee 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -15,23 +15,73 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 #include <linux/dw_apb_timer.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
-extern void socfpga_init_clocks(void);
+#include "core.h"
+void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
+void __iomem *sys_manager_base_addr;
+void __iomem *rst_manager_base_addr;
+static struct map_desc scu_io_desc __initdata = {
+        .virtual        = SOCFPGA_SCU_VIRT_BASE,
+        .pfn            = 0, /* run-time */
+        .length         = SZ_8K,
+        .type           = MT_DEVICE,
+};
+static struct map_desc uart_io_desc __initdata = {
+        .virtual        = 0xfec02000,
+        .pfn            = __phys_to_pfn(0xffc02000),
+        .length         = SZ_8K,
+        .type           = MT_DEVICE,
+};
+static void __init socfpga_scu_map_io(void)
+{
+        unsigned long base;
+        /* Get SCU base */
+        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+        scu_io_desc.pfn = __phys_to_pfn(base);
+        iotable_init(&scu_io_desc, 1);
+}
+static void __init socfpga_map_io(void)
+{
+        socfpga_scu_map_io();
+        iotable_init(&uart_io_desc, 1);
+        early_printk("Early printk initialized\n");
+}
 const static struct of_device_id irq_match[] = {
        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
        {}
 };
+void __init socfpga_sysmgr_init(void)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+        sys_manager_base_addr = of_iomap(np, 0);
+        np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
+        rst_manager_base_addr = of_iomap(np, 0);
+}
 static void __init gic_init_irq(void)
 {
        of_irq_init(irq_match);
+        socfpga_sysmgr_init();
 }
 static void socfpga_cyclone5_restart(char mode, const char *cmd)
@@ -53,6 +103,8 @@ static const char *altera_dt_match[] = {
 };
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+        .smp            = smp_ops(socfpga_smp_ops),
+        .map_io         = socfpga_map_io,
        .init_irq       = gic_init_irq,
        .handle_irq     = gic_handle_irq,
        .timer          = &dw_apb_timer,
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 07d90acc92c8..7cfa6818865a 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -47,14 +47,6 @@
 #define DMAC1_BASE                              UL(0xEB000000)
 #define MCIF_CF_BASE                            UL(0xB2800000)
-/* Devices present in SPEAr1310 */
-#ifdef CONFIG_MACH_SPEAR1310
-#define SPEAR1310_RAS_GRP1_BASE                 UL(0xD8000000)
-#define VA_SPEAR1310_RAS_GRP1_BASE              UL(0xFA000000)
-#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
-#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
-#endif /* CONFIG_MACH_SPEAR1310 */
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE                     UART_BASE
 #define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 9fbbfc5650aa..02f4724bb0d4 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -15,6 +15,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/of_platform.h>
+#include <linux/pata_arasan_cf_data.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -27,16 +28,25 @@
 #define SPEAR1310_SATA1_BASE                    UL(0xB1800000)
 #define SPEAR1310_SATA2_BASE                    UL(0xB4000000)
+#define SPEAR1310_RAS_GRP1_BASE                 UL(0xD8000000)
+#define VA_SPEAR1310_RAS_GRP1_BASE              UL(0xFA000000)
+#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
+static struct arasan_cf_pdata cf_pdata = {
+        .cf_if_clk = CF_IF_CLK_166M,
+        .quirk = CF_BROKEN_UDMA,
+        .dma_priv = &cf_dma_priv,
+};
 /* ssp device registration */
 static struct pl022_ssp_controller ssp1_plat_data = {
-        .bus_id = 0,
        .enable_dma = 0,
-        .num_chipselect = 3,
 };
 /* Add SPEAr1310 auxdata to pass platform data */
 static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
        OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 5633d698f1e1..c4af775a8451 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -57,12 +57,10 @@ static struct dw_dma_slave ssp_dma_param[] = {
 };
 struct pl022_ssp_controller pl022_plat_data = {
-        .bus_id = 0,
        .enable_dma = 1,
        .dma_filter = dw_dma_filter,
        .dma_rx_param = &ssp_dma_param[1],
        .dma_tx_param = &ssp_dma_param[0],
-        .num_chipselect = 3,
 };
 /* CF device registration */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 803de76f5f36..f95e5b2b6686 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,14 +14,6 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
-/* FIXME: probe all these from DT */
+#define NR_IRQS                 256
-#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM           1
-#define SPEAR3XX_IRQ_GEN_RAS_1                  28
-#define SPEAR3XX_IRQ_GEN_RAS_2                  29
-#define SPEAR3XX_IRQ_GEN_RAS_3                  30
-#define SPEAR3XX_IRQ_VIC_END                    32
-#define SPEAR3XX_VIRQ_START                     SPEAR3XX_IRQ_VIC_END
-#define NR_IRQS                 160
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 6ec300549960..a69cbfdb07ee 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -17,102 +17,9 @@
 #include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
-#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE           UL(0x50000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG       0x54
-#define SPEAR300_INT_STS_MASK_REG       0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
-#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
-#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
-        {
-                .virq = SPEAR300_VIRQ_IT_PERS_S,
-                .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
-                .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_IT_CHANGE_S,
-                .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
-                .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_I2S,
-                .enb_mask = SPEAR300_I2S_IRQ_MASK,
-                .status_mask = SPEAR300_I2S_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_TDM,
-                .enb_mask = SPEAR300_TDM_IRQ_MASK,
-                .status_mask = SPEAR300_TDM_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_CAMERA_L,
-                .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
-                .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_CAMERA_F,
-                .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
-                .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_CAMERA_V,
-                .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
-                .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_KEYBOARD,
-                .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
-                .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
-        }, {
-                .virq = SPEAR300_VIRQ_GPIO1,
-                .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
-                .status_mask = SPEAR300_GPIO1_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_ras1 = {
-        .irq = SPEAR3XX_IRQ_GEN_RAS_1,
-        .dev_config = shirq_ras1_config,
-        .dev_count = ARRAY_SIZE(shirq_ras1_config),
-        .regs = {
-                .enb_reg = SPEAR300_INT_ENB_MASK_REG,
-                .status_reg = SPEAR300_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
-                .clear_reg = -1,
-        },
-};
 /* DMAC platform data's slave info */
 struct pl08x_channel_data spear300_dma_info[] = {
        {
@@ -285,21 +192,11 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
 static void __init spear300_dt_init(void)
 {
-        int ret;
        pl080_plat_data.slave_channels = spear300_dma_info;
        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
        of_platform_populate(NULL, of_default_bus_match_table,
                        spear300_auxdata_lookup, NULL);
-        /* shared irq registration */
-        shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
-        if (shirq_ras1.regs.base) {
-                ret = spear_shirq_register(&shirq_ras1);
-                if (ret)
-                        pr_err("Error registering Shared IRQ\n");
-        }
 }
 static const char * const spear300_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 1d0e435b9045..b963ebb10b56 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -18,7 +18,6 @@
 #include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
-#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
@@ -27,176 +26,6 @@
 #define SPEAR310_UART3_BASE             UL(0xB2100000)
 #define SPEAR310_UART4_BASE             UL(0xB2180000)
 #define SPEAR310_UART5_BASE             UL(0xB2200000)
-#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG       0x04
-#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
-#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
-        {
-                .virq = SPEAR310_VIRQ_SMII0,
-                .status_mask = SPEAR310_SMII0_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_SMII1,
-                .status_mask = SPEAR310_SMII1_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_SMII2,
-                .status_mask = SPEAR310_SMII2_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_SMII3,
-                .status_mask = SPEAR310_SMII3_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
-                .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
-                .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
-                .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
-                .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_ras1 = {
-        .irq = SPEAR3XX_IRQ_GEN_RAS_1,
-        .dev_config = shirq_ras1_config,
-        .dev_count = ARRAY_SIZE(shirq_ras1_config),
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
-                .clear_reg = -1,
-        },
-};
-static struct shirq_dev_config shirq_ras2_config[] = {
-        {
-                .virq = SPEAR310_VIRQ_UART1,
-                .status_mask = SPEAR310_UART1_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_UART2,
-                .status_mask = SPEAR310_UART2_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_UART3,
-                .status_mask = SPEAR310_UART3_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_UART4,
-                .status_mask = SPEAR310_UART4_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_UART5,
-                .status_mask = SPEAR310_UART5_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_ras2 = {
-        .irq = SPEAR3XX_IRQ_GEN_RAS_2,
-        .dev_config = shirq_ras2_config,
-        .dev_count = ARRAY_SIZE(shirq_ras2_config),
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
-                .clear_reg = -1,
-        },
-};
-static struct shirq_dev_config shirq_ras3_config[] = {
-        {
-                .virq = SPEAR310_VIRQ_EMI,
-                .status_mask = SPEAR310_EMI_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_ras3 = {
-        .irq = SPEAR3XX_IRQ_GEN_RAS_3,
-        .dev_config = shirq_ras3_config,
-        .dev_count = ARRAY_SIZE(shirq_ras3_config),
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
-                .clear_reg = -1,
-        },
-};
-static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
-        {
-                .virq = SPEAR310_VIRQ_TDM_HDLC,
-                .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_RS485_0,
-                .status_mask = SPEAR310_RS485_0_IRQ_MASK,
-        }, {
-                .virq = SPEAR310_VIRQ_RS485_1,
-                .status_mask = SPEAR310_RS485_1_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_intrcomm_ras = {
-        .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
-        .dev_config = shirq_intrcomm_ras_config,
-        .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
-                .clear_reg = -1,
-        },
-};
 /* DMAC platform data's slave info */
 struct pl08x_channel_data spear310_dma_info[] = {
@@ -405,42 +234,11 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
 static void __init spear310_dt_init(void)
 {
-        void __iomem *base;
-        int ret;
        pl080_plat_data.slave_channels = spear310_dma_info;
        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
        of_platform_populate(NULL, of_default_bus_match_table,
                        spear310_auxdata_lookup, NULL);
-        /* shared irq registration */
-        base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
-        if (base) {
-                /* shirq 1 */
-                shirq_ras1.regs.base = base;
-                ret = spear_shirq_register(&shirq_ras1);
-                if (ret)
-                        pr_err("Error registering Shared IRQ 1\n");
-                /* shirq 2 */
-                shirq_ras2.regs.base = base;
-                ret = spear_shirq_register(&shirq_ras2);
-                if (ret)
-                        pr_err("Error registering Shared IRQ 2\n");
-                /* shirq 3 */
-                shirq_ras3.regs.base = base;
-                ret = spear_shirq_register(&shirq_ras3);
-                if (ret)
-                        pr_err("Error registering Shared IRQ 3\n");
-                /* shirq 4 */
-                shirq_intrcomm_ras.regs.base = base;
-                ret = spear_shirq_register(&shirq_intrcomm_ras);
-                if (ret)
-                        pr_err("Error registering Shared IRQ 4\n");
-        }
 }
 static const char * const spear310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fd823c624575..66e3a0c33e75 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -19,7 +19,6 @@
 #include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
-#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
@@ -28,184 +27,6 @@
 #define SPEAR320_SSP0_BASE              UL(0xA5000000)
 #define SPEAR320_SSP1_BASE              UL(0xA6000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG               0x04
-#define SPEAR320_INT_CLR_MASK_REG               0x04
-#define SPEAR320_INT_ENB_MASK_REG               0x08
-#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
-#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
-        {
-                .virq = SPEAR320_VIRQ_EMI,
-                .status_mask = SPEAR320_EMI_IRQ_MASK,
-                .clear_mask = SPEAR320_EMI_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_CLCD,
-                .status_mask = SPEAR320_CLCD_IRQ_MASK,
-                .clear_mask = SPEAR320_CLCD_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_SPP,
-                .status_mask = SPEAR320_SPP_IRQ_MASK,
-                .clear_mask = SPEAR320_SPP_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_ras1 = {
-        .irq = SPEAR3XX_IRQ_GEN_RAS_1,
-        .dev_config = shirq_ras1_config,
-        .dev_count = ARRAY_SIZE(shirq_ras1_config),
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR320_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
-                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
-                .reset_to_clear = 1,
-        },
-};
-static struct shirq_dev_config shirq_ras3_config[] = {
-        {
-                .virq = SPEAR320_VIRQ_PLGPIO,
-                .enb_mask = SPEAR320_GPIO_IRQ_MASK,
-                .status_mask = SPEAR320_GPIO_IRQ_MASK,
-                .clear_mask = SPEAR320_GPIO_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_I2S_PLAY,
-                .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
-                .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
-                .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_I2S_REC,
-                .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
-                .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
-                .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_ras3 = {
-        .irq = SPEAR3XX_IRQ_GEN_RAS_3,
-        .dev_config = shirq_ras3_config,
-        .dev_count = ARRAY_SIZE(shirq_ras3_config),
-        .regs = {
-                .enb_reg = SPEAR320_INT_ENB_MASK_REG,
-                .reset_to_enb = 1,
-                .status_reg = SPEAR320_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
-                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
-                .reset_to_clear = 1,
-        },
-};
-static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
-        {
-                .virq = SPEAR320_VIRQ_CANU,
-                .status_mask = SPEAR320_CAN_U_IRQ_MASK,
-                .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_CANL,
-                .status_mask = SPEAR320_CAN_L_IRQ_MASK,
-                .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_UART1,
-                .status_mask = SPEAR320_UART1_IRQ_MASK,
-                .clear_mask = SPEAR320_UART1_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_UART2,
-                .status_mask = SPEAR320_UART2_IRQ_MASK,
-                .clear_mask = SPEAR320_UART2_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_SSP1,
-                .status_mask = SPEAR320_SSP1_IRQ_MASK,
-                .clear_mask = SPEAR320_SSP1_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_SSP2,
-                .status_mask = SPEAR320_SSP2_IRQ_MASK,
-                .clear_mask = SPEAR320_SSP2_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_SMII0,
-                .status_mask = SPEAR320_SMII0_IRQ_MASK,
-                .clear_mask = SPEAR320_SMII0_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_MII1_SMII1,
-                .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
-                .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
-                .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
-                .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
-                .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
-                .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
-        }, {
-                .virq = SPEAR320_VIRQ_I2C1,
-                .status_mask = SPEAR320_I2C1_IRQ_MASK,
-                .clear_mask = SPEAR320_I2C1_IRQ_MASK,
-        },
-};
-static struct spear_shirq shirq_intrcomm_ras = {
-        .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
-        .dev_config = shirq_intrcomm_ras_config,
-        .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR320_INT_STS_MASK_REG,
-                .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
-                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
-                .reset_to_clear = 1,
-        },
-};
 /* DMAC platform data's slave info */
 struct pl08x_channel_data spear320_dma_info[] = {
        {
@@ -416,41 +237,17 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
 static void __init spear320_dt_init(void)
 {
-        void __iomem *base;
-        int ret;
        pl080_plat_data.slave_channels = spear320_dma_info;
        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
        of_platform_populate(NULL, of_default_bus_match_table,
                        spear320_auxdata_lookup, NULL);
-        /* shared irq registration */
-        base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
-        if (base) {
-                /* shirq 1 */
-                shirq_ras1.regs.base = base;
-                ret = spear_shirq_register(&shirq_ras1);
-                if (ret)
-                        pr_err("Error registering Shared IRQ 1\n");
-                /* shirq 3 */
-                shirq_ras3.regs.base = base;
-                ret = spear_shirq_register(&shirq_ras3);
-                if (ret)
-                        pr_err("Error registering Shared IRQ 3\n");
-                /* shirq 4 */
-                shirq_intrcomm_ras.regs.base = base;
-                ret = spear_shirq_register(&shirq_intrcomm_ras);
-                if (ret)
-                        pr_err("Error registering Shared IRQ 4\n");
-        }
 }
 static const char * const spear320_dt_board_compat[] = {
        "st,spear320",
        "st,spear320-evb",
+        "st,spear320-hmi",
        NULL,
 };
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 98144baf8883..38fe95db31a7 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -15,6 +15,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
+#include <linux/irqchip/spear-shirq.h>
 #include <linux/of_irq.h>
 #include <linux/io.h>
 #include <asm/hardware/pl080.h>
@@ -121,6 +122,9 @@ struct sys_timer spear3xx_timer = {
 static const struct of_device_id vic_of_match[] __initconst = {
        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+        { .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, },
+        { .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, },
+        { .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, },
        { /* Sentinel */ }
 };
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
new file mode 100644
index 000000000000..3fdd0085e306
--- /dev/null
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -0,0 +1,9 @@
+config ARCH_SUNXI
+        bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+        select CLKSRC_MMIO
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select PINCTRL
+        select SPARSE_IRQ
+        select SUNXI_TIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
new file mode 100644
index 000000000000..93bebfc3ff9f
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot
new file mode 100644
index 000000000000..46d4cf0841c0
--- /dev/null
+++ b/arch/arm/mach-sunxi/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-$(CONFIG_ARCH_SUNXI)   += 0x40008000
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
new file mode 100644
index 000000000000..9be910f7920b
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -0,0 +1,96 @@
+/*
+ * Device Tree support for Allwinner A1X SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/sunxi_timer.h>
+#include <linux/irqchip/sunxi.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include "sunxi.h"
+#define WATCHDOG_CTRL_REG       0x00
+#define WATCHDOG_MODE_REG       0x04
+static void __iomem *wdt_base;
+static void sunxi_setup_restart(void)
+{
+        struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                                "allwinner,sunxi-wdt");
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+        wdt_base = of_iomap(np, 0);
+        WARN(!wdt_base, "failed to map watchdog base address");
+}
+static void sunxi_restart(char mode, const char *cmd)
+{
+        if (!wdt_base)
+                return;
+        /* Enable timer and set reset bit in the watchdog */
+        writel(3, wdt_base + WATCHDOG_MODE_REG);
+        writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG);
+        while(1) {
+                mdelay(5);
+                writel(3, wdt_base + WATCHDOG_MODE_REG);
+        }
+}
+static struct map_desc sunxi_io_desc[] __initdata = {
+        {
+                .virtual        = (unsigned long) SUNXI_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
+                .length         = SUNXI_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+void __init sunxi_map_io(void)
+{
+        iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
+}
+static void __init sunxi_dt_init(void)
+{
+        sunxi_setup_restart();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char * const sunxi_board_dt_compat[] = {
+        "allwinner,sun4i",
+        "allwinner,sun5i",
+        NULL,
+};
+DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+        .init_machine   = sunxi_dt_init,
+        .map_io         = sunxi_map_io,
+        .init_irq       = sunxi_init_irq,
+        .handle_irq     = sunxi_handle_irq,
+        .restart        = sunxi_restart,
+        .timer          = &sunxi_timer,
+        .dt_compat      = sunxi_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
new file mode 100644
index 000000000000..33b58712adea
--- /dev/null
+++ b/arch/arm/mach-sunxi/sunxi.h
@@ -0,0 +1,20 @@
+/*
+ * Generic definitions for Allwinner SunXi SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __MACH_SUNXI_H
+#define __MACH_SUNXI_H
+#define SUNXI_REGS_PHYS_BASE    0x01c00000
+#define SUNXI_REGS_VIRT_BASE    IOMEM(0xf1c00000)
+#define SUNXI_REGS_SIZE         (SZ_2M + SZ_1M)
+#endif /* __MACH_SUNXI_H */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9ff6f6ea3617..b442f15fd01a 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -55,58 +55,7 @@ config TEGRA_AHB
        help
          Adds AHB configuration functionality for NVIDIA Tegra SoCs,
          which controls AHB bus master arbitration and some
-          perfomance parameters(priority, prefech size).
+          performance parameters(priority, prefech size).
-choice
-        prompt "Default low-level debug console UART"
-        default TEGRA_DEBUG_UART_NONE
-config TEGRA_DEBUG_UART_NONE
-        bool "None"
-config TEGRA_DEBUG_UARTA
-        bool "UART-A"
-config TEGRA_DEBUG_UARTB
-        bool "UART-B"
-config TEGRA_DEBUG_UARTC
-        bool "UART-C"
-config TEGRA_DEBUG_UARTD
-        bool "UART-D"
-config TEGRA_DEBUG_UARTE
-        bool "UART-E"
-endchoice
-choice
-        prompt "Automatic low-level debug console UART"
-        default TEGRA_DEBUG_UART_AUTO_NONE
-config TEGRA_DEBUG_UART_AUTO_NONE
-        bool "None"
-config TEGRA_DEBUG_UART_AUTO_ODMDATA
-        bool "Via ODMDATA"
-        help
-          Automatically determines which UART to use for low-level debug based
-          on the ODMDATA value. This value is part of the BCT, and is written
-          to the boot memory device using nvflash, or other flashing tool.
-          When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
-          0/1/2/3/4 are UART A/B/C/D/E.
-config TEGRA_DEBUG_UART_AUTO_SCRATCH
-        bool "Via UART scratch register"
-        help
-          Automatically determines which UART to use for low-level debug based
-          on the UART scratch register value. Some bootloaders put ASCII 'D'
-          in this register when they initialize their own console UART output.
-          Using this option allows the kernel to automatically pick the same
-          UART.
-endchoice
 config TEGRA_EMC_SCALING_ENABLE
        bool "Enable scaling the memory frequency"
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 9aa653b3eb32..0979e8bba78a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,15 +8,24 @@ obj-y					+= pmc.o
 obj-y                                   += flowctrl.o
 obj-y                                   += powergate.o
 obj-y                                   += apbio.o
+obj-y                                   += pm.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_CPU_IDLE)                  += sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-t20.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-tegra20.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += cpuidle-tegra20.o
+endif
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks_data.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-t30.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-tegra30.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += cpuidle-tegra30.o
+endif
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index b5015d0f1912..d091675ba376 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -15,7 +15,6 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <mach/iomap.h>
 #include <linux/of.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
@@ -24,9 +23,8 @@
 #include <linux/sched.h>
 #include <linux/mutex.h>
-#include <mach/dma.h>
 #include "apbio.h"
+#include "iomap.h"
 #if defined(CONFIG_TEGRA20_APB_DMA)
 static DEFINE_MUTEX(tegra_apb_dma_lock);
@@ -71,7 +69,6 @@ bool tegra_apb_dma_init(void)
        dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
        dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-        dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
        dma_sconfig.src_maxburst = 1;
        dma_sconfig.dst_maxburst = 1;
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index aa5325cd1c42..734d9cc87f2e 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -40,12 +40,10 @@
 #include <asm/mach/time.h>
 #include <asm/setup.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
 #include "board.h"
 #include "clock.h"
 #include "common.h"
+#include "iomap.h"
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
        .operating_mode = TEGRA_USB_OTG,
@@ -91,6 +89,17 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
                       &tegra_ehci3_pdata),
        OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
        {}
 };
@@ -104,8 +113,20 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
        { "pll_a",      "pll_p_out1",   56448000,       true },
        { "pll_a_out0", "pll_a",        11289600,       true },
        { "cdev1",      NULL,           0,              true },
+        { "blink",      "clk_32k",      32768,          true },
        { "i2s1",       "pll_a_out0",   11289600,       false},
        { "i2s2",       "pll_a_out0",   11289600,       false},
+        { "sdmmc1",     "pll_p",        48000000,       false},
+        { "sdmmc3",     "pll_p",        48000000,       false},
+        { "sdmmc4",     "pll_p",        48000000,       false},
+        { "spi",        "pll_p",        20000000,       false },
+        { "sbc1",       "pll_p",        100000000,      false },
+        { "sbc2",       "pll_p",        100000000,      false },
+        { "sbc3",       "pll_p",        100000000,      false },
+        { "sbc4",       "pll_p",        100000000,      false },
+        { "host1x",     "pll_c",        150000000,      false },
+        { "disp1",      "pll_p",        600000000,      false },
+        { "disp2",      "pll_p",        600000000,      false },
        { NULL,         NULL,           0,              0},
 };
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 5e92a81f9a2e..6497d1236b08 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -33,11 +33,10 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
-#include <mach/iomap.h>
 #include "board.h"
 #include "clock.h"
 #include "common.h"
+#include "iomap.h"
 struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
@@ -52,6 +51,18 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
        OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
        OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
        {}
 };
@@ -62,11 +73,24 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
        { "pll_a_out0", "pll_a",        11289600,       true },
        { "extern1",    "pll_a_out0",   0,              true },
        { "clk_out_1",  "extern1",      0,              true },
+        { "blink",      "clk_32k",      32768,          true },
        { "i2s0",       "pll_a_out0",   11289600,       false},
        { "i2s1",       "pll_a_out0",   11289600,       false},
        { "i2s2",       "pll_a_out0",   11289600,       false},
        { "i2s3",       "pll_a_out0",   11289600,       false},
        { "i2s4",       "pll_a_out0",   11289600,       false},
+        { "sdmmc1",     "pll_p",        48000000,       false},
+        { "sdmmc3",     "pll_p",        48000000,       false},
+        { "sdmmc4",     "pll_p",        48000000,       false},
+        { "sbc1",       "pll_p",        100000000,      false},
+        { "sbc2",       "pll_p",        100000000,      false},
+        { "sbc3",       "pll_p",        100000000,      false},
+        { "sbc4",       "pll_p",        100000000,      false},
+        { "sbc5",       "pll_p",        100000000,      false},
+        { "sbc6",       "pll_p",        100000000,      false},
+        { "host1x",     "pll_c",        150000000,      false},
+        { "disp1",      "pll_p",        600000000,      false},
+        { "disp2",      "pll_p",        600000000,      false},
        { NULL,         NULL,           0,              0},
 };
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index fd82085eca5d..867bf8bf5561 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -27,8 +27,6 @@
 #include <linux/seq_file.h>
 #include <linux/slab.h>
-#include <mach/clk.h>
 #include "board.h"
 #include "clock.h"
 #include "tegra_cpu_car.h"
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0b0a5f556d34..0816562725f6 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -26,16 +26,17 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
-#include <mach/iomap.h>
 #include <mach/powergate.h>
 #include "board.h"
 #include "clock.h"
 #include "common.h"
 #include "fuse.h"
+#include "iomap.h"
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
+#include "pm.h"
 /*
 * Storage for debug-macro.S's state.
@@ -44,14 +45,15 @@
 * kernel is loaded. The data is declared here rather than debug-macro.S so
 * that multiple inclusions of debug-macro.S point at the same data.
 */
-#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
+u32 tegra_uart_config[4] = {
-u32 tegra_uart_config[3] = {
        /* Debug UART initialization required */
        1,
        /* Debug UART physical address */
-        (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
+        0,
        /* Debug UART virtual address */
-        (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
+        0,
+        /* Scratch space for debug macro */
+        0,
 };
 #ifdef CONFIG_OF
@@ -104,25 +106,30 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
        { "clk_m",      NULL,           0,              true },
        { "pll_p",      "clk_m",        408000000,      true },
        { "pll_p_out1", "pll_p",        9600000,        true },
+        { "pll_p_out4", "pll_p",        102000000,      true },
+        { "sclk",       "pll_p_out4",   102000000,      true },
+        { "hclk",       "sclk",         102000000,      true },
+        { "pclk",       "hclk",         51000000,       true },
+        { "csite",      NULL,           0,              true },
        { NULL,         NULL,           0,              0},
 };
 #endif
-static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
+static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
+        int ret;
        void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
        u32 aux_ctrl, cache_type;
-        writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
-        writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
        cache_type = readl(p + L2X0_CACHE_TYPE);
        aux_ctrl = (cache_type & 0x700) << (17-8);
-        aux_ctrl |= 0x6C000001;
+        aux_ctrl |= 0x7C400001;
-        l2x0_init(p, aux_ctrl, 0x8200c3fe);
+        ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
+        if (!ret)
+                l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
 #endif
 }
@@ -134,7 +141,7 @@ void __init tegra20_init_early(void)
        tegra_init_fuse();
        tegra2_init_clocks();
        tegra_clk_init_from_table(tegra20_clk_init_table);
-        tegra_init_cache(0x331, 0x441);
+        tegra_init_cache();
        tegra_pmc_init();
        tegra_powergate_init();
        tegra20_hotplug_init();
@@ -147,7 +154,7 @@ void __init tegra30_init_early(void)
        tegra_init_fuse();
        tegra30_init_clocks();
        tegra_clk_init_from_table(tegra30_clk_init_table);
-        tegra_init_cache(0x441, 0x551);
+        tegra_init_cache();
        tegra_pmc_init();
        tegra_powergate_init();
        tegra30_hotplug_init();
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 627bf0f4262e..a74d3c7d2e26 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -30,9 +30,6 @@
 #include <linux/io.h>
 #include <linux/suspend.h>
-#include <mach/clk.h>
 /* Frequency table index must be sequential starting at 0 */
 static struct cpufreq_frequency_table freq_table[] = {
        { 0, 216000 },
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
new file mode 100644
index 000000000000..d32e8b0dbd4f
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -0,0 +1,66 @@
+/*
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpuidle.h>
+#include <asm/cpuidle.h>
+static struct cpuidle_driver tegra_idle_driver = {
+        .name = "tegra_idle",
+        .owner = THIS_MODULE,
+        .en_core_tk_irqen = 1,
+        .state_count = 1,
+        .states = {
+                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+        },
+};
+static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+int __init tegra20_cpuidle_init(void)
+{
+        int ret;
+        unsigned int cpu;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &tegra_idle_driver;
+        ret = cpuidle_register_driver(&tegra_idle_driver);
+        if (ret) {
+                pr_err("CPUidle driver registration failed\n");
+                return ret;
+        }
+        for_each_possible_cpu(cpu) {
+                dev = &per_cpu(tegra_idle_device, cpu);
+                dev->cpu = cpu;
+                dev->state_count = drv->state_count;
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("CPU%u: CPUidle device registration failed\n",
+                                cpu);
+                        return ret;
+                }
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
new file mode 100644
index 000000000000..5e8cbf5b799f
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -0,0 +1,188 @@
+/*
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+#include "pm.h"
+#include "sleep.h"
+#include "tegra_cpu_car.h"
+#ifdef CONFIG_PM_SLEEP
+static int tegra30_idle_lp2(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv,
+                            int index);
+#endif
+static struct cpuidle_driver tegra_idle_driver = {
+        .name = "tegra_idle",
+        .owner = THIS_MODULE,
+        .en_core_tk_irqen = 1,
+#ifdef CONFIG_PM_SLEEP
+        .state_count = 2,
+#else
+        .state_count = 1,
+#endif
+        .states = {
+                [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+                [1] = {
+                        .enter                  = tegra30_idle_lp2,
+                        .exit_latency           = 2000,
+                        .target_residency       = 2200,
+                        .power_usage            = 0,
+                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                        .name                   = "powered-down",
+                        .desc                   = "CPU power gated",
+                },
+#endif
+        },
+};
+static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+#ifdef CONFIG_PM_SLEEP
+static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
+                                           struct cpuidle_driver *drv,
+                                           int index)
+{
+        struct cpuidle_state *state = &drv->states[index];
+        u32 cpu_on_time = state->exit_latency;
+        u32 cpu_off_time = state->target_residency - state->exit_latency;
+        /* All CPUs entering LP2 is not working.
+         * Don't let CPU0 enter LP2 when any secondary CPU is online.
+         */
+        if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
+                cpu_do_idle();
+                return false;
+        }
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+        return true;
+}
+#ifdef CONFIG_SMP
+static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
+                                        struct cpuidle_driver *drv,
+                                        int index)
+{
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+        smp_wmb();
+        save_cpu_arch_register();
+        cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+        restore_cpu_arch_register();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+        return true;
+}
+#else
+static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
+                                               struct cpuidle_driver *drv,
+                                               int index)
+{
+        return true;
+}
+#endif
+static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
+                                      struct cpuidle_driver *drv,
+                                      int index)
+{
+        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
+        bool entered_lp2 = false;
+        bool last_cpu;
+        local_fiq_disable();
+        last_cpu = tegra_set_cpu_in_lp2(cpu);
+        cpu_pm_enter();
+        if (cpu == 0) {
+                if (last_cpu)
+                        entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
+                                                                     index);
+                else
+                        cpu_do_idle();
+        } else {
+                entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
+        }
+        cpu_pm_exit();
+        tegra_clear_cpu_in_lp2(cpu);
+        local_fiq_enable();
+        smp_rmb();
+        return (entered_lp2) ? index : 0;
+}
+#endif
+int __init tegra30_cpuidle_init(void)
+{
+        int ret;
+        unsigned int cpu;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &tegra_idle_driver;
+#ifdef CONFIG_PM_SLEEP
+        tegra_tear_down_cpu = tegra30_tear_down_cpu;
+#endif
+        ret = cpuidle_register_driver(&tegra_idle_driver);
+        if (ret) {
+                pr_err("CPUidle driver registration failed\n");
+                return ret;
+        }
+        for_each_possible_cpu(cpu) {
+                dev = &per_cpu(tegra_idle_device, cpu);
+                dev->cpu = cpu;
+                dev->state_count = drv->state_count;
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("CPU%u: CPUidle device registration failed\n",
+                                cpu);
+                        return ret;
+                }
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 566e2f88899b..d0651397aec7 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -23,85 +23,26 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/cpu.h>
-#include <linux/cpuidle.h>
-#include <linux/hrtimer.h>
-#include <asm/proc-fns.h>
+#include "fuse.h"
+#include "cpuidle.h"
-#include <mach/iomap.h>
-static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv, int index);
-struct cpuidle_driver tegra_idle_driver = {
-        .name = "tegra_idle",
-        .owner = THIS_MODULE,
-        .state_count = 1,
-        .states = {
-                [0] = {
-                        .enter                  = tegra_idle_enter_lp3,
-                        .exit_latency           = 10,
-                        .target_residency       = 10,
-                        .power_usage            = 600,
-                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                        .name                   = "LP3",
-                        .desc                   = "CPU flow-controlled",
-                },
-        },
-};
-static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
-        struct cpuidle_driver *drv, int index)
-{
-        ktime_t enter, exit;
-        s64 us;
-        local_irq_disable();
-        local_fiq_disable();
-        enter = ktime_get();
-        cpu_do_idle();
-        exit = ktime_sub(ktime_get(), enter);
-        us = ktime_to_us(exit);
-        local_fiq_enable();
-        local_irq_enable();
-        dev->last_residency = us;
-        return index;
-}
 static int __init tegra_cpuidle_init(void)
 {
        int ret;
-        unsigned int cpu;
-        struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &tegra_idle_driver;
-        ret = cpuidle_register_driver(&tegra_idle_driver);
+        switch (tegra_chip_id) {
-        if (ret) {
+        case TEGRA20:
-                pr_err("CPUidle driver registration failed\n");
+                ret = tegra20_cpuidle_init();
-                return ret;
+                break;
+        case TEGRA30:
+                ret = tegra30_cpuidle_init();
+                break;
+        default:
+                ret = -ENODEV;
+                break;
        }
-        for_each_possible_cpu(cpu) {
+        return ret;
-                dev = &per_cpu(tegra_idle_device, cpu);
-                dev->cpu = cpu;
-                dev->state_count = drv->state_count;
-                ret = cpuidle_register_device(dev);
-                if (ret) {
-                        pr_err("CPU%u: CPUidle device registration failed\n",
-                                cpu);
-                        return ret;
-                }
-        }
-        return 0;
 }
 device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
new file mode 100644
index 000000000000..496204d34e55
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_TEGRA_CPUIDLE_H
+#define __MACH_TEGRA_CPUIDLE_H
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+int tegra20_cpuidle_init(void);
+#else
+static inline int tegra20_cpuidle_init(void) { return -ENODEV; }
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+int tegra30_cpuidle_init(void);
+#else
+static inline int tegra30_cpuidle_init(void) { return -ENODEV; }
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index f07488e0bd32..a2250ddae797 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -21,10 +21,10 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/cpumask.h>
-#include <mach/iomap.h>
 #include "flowctrl.h"
+#include "iomap.h"
 u8 flowctrl_offset_halt_cpu[] = {
        FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -51,6 +51,14 @@ static void flowctrl_update(u8 offset, u32 value)
        readl_relaxed(addr);
 }
+u32 flowctrl_read_cpu_csr(unsigned int cpuid)
+{
+        u8 offset = flowctrl_offset_cpu_csr[cpuid];
+        void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
+        return readl(addr);
+}
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
 {
        return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
@@ -60,3 +68,41 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
 {
        return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
 }
+void flowctrl_cpu_suspend_enter(unsigned int cpuid)
+{
+        unsigned int reg;
+        int i;
+        reg = flowctrl_read_cpu_csr(cpuid);
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
+        reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr flag */
+        reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event flag */
+        reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
+        reg |= FLOW_CTRL_CSR_ENABLE;                    /* pwr gating */
+        flowctrl_write_cpu_csr(cpuid, reg);
+        for (i = 0; i < num_possible_cpus(); i++) {
+                if (i == cpuid)
+                        continue;
+                reg = flowctrl_read_cpu_csr(i);
+                reg |= FLOW_CTRL_CSR_EVENT_FLAG;
+                reg |= FLOW_CTRL_CSR_INTR_FLAG;
+                flowctrl_write_cpu_csr(i, reg);
+        }
+}
+void flowctrl_cpu_suspend_exit(unsigned int cpuid)
+{
+        unsigned int reg;
+        /* Disable powergating via flow controller for CPU0 */
+        reg = flowctrl_read_cpu_csr(cpuid);
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
+        reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
+        reg &= ~FLOW_CTRL_CSR_ENABLE;                   /* clear enable */
+        reg |= FLOW_CTRL_CSR_INTR_FLAG;                 /* clear intr */
+        reg |= FLOW_CTRL_CSR_EVENT_FLAG;                /* clear event */
+        flowctrl_write_cpu_csr(cpuid, reg);
+}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 19428173855e..0798dec1832d 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -34,9 +34,17 @@
 #define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
 #define FLOW_CTRL_CPU1_CSR              0x18
+#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0          (1 << 8)
+#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP        (0xF << 4)
+#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP        (0xF << 8)
 #ifndef __ASSEMBLY__
+u32 flowctrl_read_cpu_csr(unsigned int cpuid);
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
+void flowctrl_cpu_suspend_enter(unsigned int cpuid);
+void flowctrl_cpu_suspend_exit(unsigned int cpuid);
 #endif
 #endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 0b7db174a5de..8121742711fe 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -21,22 +21,28 @@
 #include <linux/io.h>
 #include <linux/export.h>
-#include <mach/iomap.h>
 #include "fuse.h"
+#include "iomap.h"
 #include "apbio.h"
 #define FUSE_UID_LOW            0x108
 #define FUSE_UID_HIGH           0x10c
 #define FUSE_SKU_INFO           0x110
-#define FUSE_SPARE_BIT          0x200
+#define TEGRA20_FUSE_SPARE_BIT          0x200
+#define TEGRA30_FUSE_SPARE_BIT          0x244
 int tegra_sku_id;
 int tegra_cpu_process_id;
 int tegra_core_process_id;
 int tegra_chip_id;
+int tegra_cpu_speedo_id;                /* only exist in Tegra30 and later */
+int tegra_soc_speedo_id;
 enum tegra_revision tegra_revision;
+static int tegra_fuse_spare_bit;
+static void (*tegra_init_speedo_data)(void);
 /* The BCT to use at boot is specified by board straps that can be read
 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
 */
@@ -57,14 +63,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
        [TEGRA_REVISION_A04]     = "A04",
 };
-static inline u32 tegra_fuse_readl(unsigned long offset)
+u32 tegra_fuse_readl(unsigned long offset)
 {
        return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
 }
-static inline bool get_spare_fuse(int bit)
+bool tegra_spare_fuse(int bit)
 {
-        return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
+        return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
 }
 static enum tegra_revision tegra_get_revision(u32 id)
@@ -78,7 +84,7 @@ static enum tegra_revision tegra_get_revision(u32 id)
                return TEGRA_REVISION_A02;
        case 3:
                if (tegra_chip_id == TEGRA20 &&
-                        (get_spare_fuse(18) || get_spare_fuse(19)))
+                        (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
                        return TEGRA_REVISION_A03p;
                else
                        return TEGRA_REVISION_A03;
@@ -89,6 +95,16 @@ static enum tegra_revision tegra_get_revision(u32 id)
        }
 }
+static void tegra_get_process_id(void)
+{
+        u32 reg;
+        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
+        tegra_cpu_process_id = (reg >> 6) & 3;
+        reg = tegra_fuse_readl(tegra_fuse_spare_bit);
+        tegra_core_process_id = (reg >> 12) & 3;
+}
 void tegra_init_fuse(void)
 {
        u32 id;
@@ -100,19 +116,29 @@ void tegra_init_fuse(void)
        reg = tegra_fuse_readl(FUSE_SKU_INFO);
        tegra_sku_id = reg & 0xFF;
-        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
-        tegra_cpu_process_id = (reg >> 6) & 3;
-        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
-        tegra_core_process_id = (reg >> 12) & 3;
        reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
        tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
        id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
        tegra_chip_id = (id >> 8) & 0xff;
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
+                tegra_init_speedo_data = &tegra20_init_speedo_data;
+                break;
+        case TEGRA30:
+                tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
+                tegra_init_speedo_data = &tegra30_init_speedo_data;
+                break;
+        default:
+                pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
+                tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
+                tegra_init_speedo_data = &tegra_get_process_id;
+        }
        tegra_revision = tegra_get_revision(id);
+        tegra_init_speedo_data();
        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
                tegra_revision_name[tegra_revision],
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index d2107b2cb85a..ff1383dd61a7 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -42,11 +42,27 @@ extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
 extern int tegra_chip_id;
+extern int tegra_cpu_speedo_id;         /* only exist in Tegra30 and later */
+extern int tegra_soc_speedo_id;
 extern enum tegra_revision tegra_revision;
 extern int tegra_bct_strapping;
 unsigned long long tegra_chip_uid(void);
 void tegra_init_fuse(void);
+bool tegra_spare_fuse(int bit);
+u32 tegra_fuse_readl(unsigned long offset);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void tegra20_init_speedo_data(void);
+#else
+static inline void tegra20_init_speedo_data(void) {}
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void tegra30_init_speedo_data(void);
+#else
+static inline void tegra30_init_speedo_data(void) {}
+#endif
 #endif
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 6addc78cb6b2..4a317fae6860 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -2,10 +2,11 @@
 #include <linux/init.h>
 #include <asm/cache.h>
+#include <asm/asm-offsets.h>
-#include <mach/iomap.h>
+#include <asm/hardware/cache-l2x0.h>
 #include "flowctrl.h"
+#include "iomap.h"
 #include "reset.h"
 #include "sleep.h"
@@ -69,6 +70,64 @@ ENTRY(tegra_secondary_startup)
        b       secondary_startup
 ENDPROC(tegra_secondary_startup)
+#ifdef CONFIG_PM_SLEEP
+/*
+ *      tegra_resume
+ *
+ *        CPU boot vector when restarting the a CPU following
+ *        an LP2 transition. Also branched to by LP0 and LP1 resume after
+ *        re-enabling sdram.
+ */
+ENTRY(tegra_resume)
+        bl      v7_invalidate_l1
+        /* Enable coresight */
+        mov32   r0, 0xC5ACCE55
+        mcr     p14, 0, r0, c7, c12, 6
+        cpu_id  r0
+        cmp     r0, #0                          @ CPU0?
+        bne     cpu_resume                      @ no
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        /* Are we on Tegra20? */
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
+        and     r0, r0, #0xff00
+        cmp     r0, #(0x20 << 8)
+        beq     1f                              @ Yes
+        /* Clear the flow controller flags for this CPU. */
+        mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
+        ldr     r1, [r2]
+        /* Clear event & intr flag */
+        orr     r1, r1, \
+                #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
+        bic     r1, r1, r0
+        str     r1, [r2]
+1:
+#endif
+#ifdef CONFIG_HAVE_ARM_SCU
+        /* enable SCU */
+        mov32   r0, TEGRA_ARM_PERIF_BASE
+        ldr     r1, [r0]
+        orr     r1, r1, #1
+        str     r1, [r0]
+#endif
+        /* L2 cache resume & re-enable */
+        l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+        b       cpu_resume
+ENDPROC(tegra_resume)
+#endif
+#ifdef CONFIG_CACHE_L2X0
+        .globl  l2x0_saved_regs_addr
+l2x0_saved_regs_addr:
+        .long   0
+#endif
        .align L1_CACHE_SHIFT
 ENTRY(__tegra_cpu_reset_handler_start)
@@ -122,6 +181,17 @@ ENTRY(__tegra_cpu_reset_handler)
 1:
 #endif
+        /* Waking up from LP2? */
+        ldr     r9, [r12, #RESET_DATA(MASK_LP2)]
+        tst     r9, r11                         @ if in_lp2
+        beq     __is_not_lp2
+        ldr     lr, [r12, #RESET_DATA(STARTUP_LP2)]
+        cmp     lr, #0
+        bleq    __die                           @ no LP2 startup handler
+        bx      lr
+__is_not_lp2:
 #ifdef CONFIG_SMP
        /*
         * Can only be secondary boot (initial or hotplug) but CPU 0
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
deleted file mode 100644
index 8ce0661b8a3d..000000000000
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/debug-macro.S
- *
- * Copyright (C) 2010,2011 Google, Inc.
- * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *      Doug Anderson <dianders@chromium.org>
- *      Stephen Warren <swarren@nvidia.com>
- *
- * Portions based on mach-omap2's debug-macro.S
- * Copyright (C) 1994-1999 Russell King
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/serial_reg.h>
-#include <mach/iomap.h>
-#include <mach/irammap.h>
-                .macro  addruart, rp, rv, tmp
-                adr     \rp, 99f                @ actual addr of 99f
-                ldr     \rv, [\rp]              @ linked addr is stored there
-                sub     \rv, \rv, \rp           @ offset between the two
-                ldr     \rp, [\rp, #4]          @ linked tegra_uart_config
-                sub     \tmp, \rp, \rv          @ actual tegra_uart_config
-                ldr     \rp, [\tmp]             @ Load tegra_uart_config
-                cmp     \rp, #1                 @ needs intitialization?
-                bne     100f                    @ no; go load the addresses
-                mov     \rv, #0                 @ yes; record init is done
-                str     \rv, [\tmp]
-                mov     \rp, #TEGRA_IRAM_BASE   @ See if cookie is in IRAM
-                ldr     \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
-                movw    \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
-                movt    \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
-                cmp     \rv, \rp                @ Cookie present?
-                bne     100f                    @ No, use default UART
-                mov     \rp, #TEGRA_IRAM_BASE   @ Load UART address from IRAM
-                ldr     \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
-                str     \rv, [\tmp, #4]         @ Store in tegra_uart_phys
-                sub     \rv, \rv, #IO_APB_PHYS  @ Calculate virt address
-                add     \rv, \rv, #IO_APB_VIRT
-                str     \rv, [\tmp, #8]         @ Store in tegra_uart_virt
-                b       100f
-                .align
-99:             .word   .
-                .word   tegra_uart_config
-                .ltorg
-100:            ldr     \rp, [\tmp, #4]         @ Load tegra_uart_phys
-                ldr     \rv, [\tmp, #8]         @ Load tegra_uart_virt
-                .endm
-#define UART_SHIFT 2
-/*
- * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
- * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
- * We use the fact that all 5 valid UART addresses all have something in the
- * 2nd-to-lowest byte.
- */
-                .macro  senduart, rd, rx
-                tst     \rx, #0x0000ff00
-                strneb  \rd, [\rx, #UART_TX << UART_SHIFT]
-1001:
-                .endm
-                .macro  busyuart, rd, rx
-                tst     \rx, #0x0000ff00
-                beq     1002f
-1001:           ldrb    \rd, [\rx, #UART_LSR << UART_SHIFT]
-                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
-                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
-                bne     1001b
-1002:
-                .endm
-                .macro  waituart, rd, rx
-#ifdef FLOW_CONTROL
-                tst     \rx, #0x0000ff00
-                beq     1002f
-1001:           ldrb    \rd, [\rx, #UART_MSR << UART_SHIFT]
-                tst     \rd, #UART_MSR_CTS
-                beq     1001b
-1002:
-#endif
-                .endm
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
deleted file mode 100644
index 3081cc6dda3b..000000000000
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/dma.h
- *
- * Copyright (c) 2008-2009, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-#ifndef __MACH_TEGRA_DMA_H
-#define __MACH_TEGRA_DMA_H
-#include <linux/list.h>
-#define TEGRA_DMA_REQ_SEL_CNTR                  0
-#define TEGRA_DMA_REQ_SEL_I2S_2                 1
-#define TEGRA_DMA_REQ_SEL_I2S_1                 2
-#define TEGRA_DMA_REQ_SEL_SPD_I                 3
-#define TEGRA_DMA_REQ_SEL_UI_I                  4
-#define TEGRA_DMA_REQ_SEL_MIPI                  5
-#define TEGRA_DMA_REQ_SEL_I2S2_2                6
-#define TEGRA_DMA_REQ_SEL_I2S2_1                7
-#define TEGRA_DMA_REQ_SEL_UARTA                 8
-#define TEGRA_DMA_REQ_SEL_UARTB                 9
-#define TEGRA_DMA_REQ_SEL_UARTC                 10
-#define TEGRA_DMA_REQ_SEL_SPI                   11
-#define TEGRA_DMA_REQ_SEL_AC97                  12
-#define TEGRA_DMA_REQ_SEL_ACMODEM               13
-#define TEGRA_DMA_REQ_SEL_SL4B                  14
-#define TEGRA_DMA_REQ_SEL_SL2B1                 15
-#define TEGRA_DMA_REQ_SEL_SL2B2                 16
-#define TEGRA_DMA_REQ_SEL_SL2B3                 17
-#define TEGRA_DMA_REQ_SEL_SL2B4                 18
-#define TEGRA_DMA_REQ_SEL_UARTD                 19
-#define TEGRA_DMA_REQ_SEL_UARTE                 20
-#define TEGRA_DMA_REQ_SEL_I2C                   21
-#define TEGRA_DMA_REQ_SEL_I2C2                  22
-#define TEGRA_DMA_REQ_SEL_I2C3                  23
-#define TEGRA_DMA_REQ_SEL_DVC_I2C               24
-#define TEGRA_DMA_REQ_SEL_OWR                   25
-#define TEGRA_DMA_REQ_SEL_INVALID               31
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
deleted file mode 100644
index aad1a2c1d714..000000000000
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/irqs.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_IRQS_H
-#define __MACH_TEGRA_IRQS_H
-#define INT_GIC_BASE                    0
-#define IRQ_LOCALTIMER                  29
-/* Primary Interrupt Controller */
-#define INT_PRI_BASE                    (INT_GIC_BASE + 32)
-#define INT_TMR1                        (INT_PRI_BASE + 0)
-#define INT_TMR2                        (INT_PRI_BASE + 1)
-#define INT_RTC                         (INT_PRI_BASE + 2)
-#define INT_I2S2                        (INT_PRI_BASE + 3)
-#define INT_SHR_SEM_INBOX_IBF           (INT_PRI_BASE + 4)
-#define INT_SHR_SEM_INBOX_IBE           (INT_PRI_BASE + 5)
-#define INT_SHR_SEM_OUTBOX_IBF          (INT_PRI_BASE + 6)
-#define INT_SHR_SEM_OUTBOX_IBE          (INT_PRI_BASE + 7)
-#define INT_VDE_UCQ_ERROR               (INT_PRI_BASE + 8)
-#define INT_VDE_SYNC_TOKEN              (INT_PRI_BASE + 9)
-#define INT_VDE_BSE_V                   (INT_PRI_BASE + 10)
-#define INT_VDE_BSE_A                   (INT_PRI_BASE + 11)
-#define INT_VDE_SXE                     (INT_PRI_BASE + 12)
-#define INT_I2S1                        (INT_PRI_BASE + 13)
-#define INT_SDMMC1                      (INT_PRI_BASE + 14)
-#define INT_SDMMC2                      (INT_PRI_BASE + 15)
-#define INT_XIO                         (INT_PRI_BASE + 16)
-#define INT_VDE                         (INT_PRI_BASE + 17)
-#define INT_AVP_UCQ                     (INT_PRI_BASE + 18)
-#define INT_SDMMC3                      (INT_PRI_BASE + 19)
-#define INT_USB                         (INT_PRI_BASE + 20)
-#define INT_USB2                        (INT_PRI_BASE + 21)
-#define INT_PRI_RES_22                  (INT_PRI_BASE + 22)
-#define INT_EIDE                        (INT_PRI_BASE + 23)
-#define INT_NANDFLASH                   (INT_PRI_BASE + 24)
-#define INT_VCP                         (INT_PRI_BASE + 25)
-#define INT_APB_DMA                     (INT_PRI_BASE + 26)
-#define INT_AHB_DMA                     (INT_PRI_BASE + 27)
-#define INT_GNT_0                       (INT_PRI_BASE + 28)
-#define INT_GNT_1                       (INT_PRI_BASE + 29)
-#define INT_OWR                         (INT_PRI_BASE + 30)
-#define INT_SDMMC4                      (INT_PRI_BASE + 31)
-/* Secondary Interrupt Controller */
-#define INT_SEC_BASE                    (INT_PRI_BASE + 32)
-#define INT_GPIO1                       (INT_SEC_BASE + 0)
-#define INT_GPIO2                       (INT_SEC_BASE + 1)
-#define INT_GPIO3                       (INT_SEC_BASE + 2)
-#define INT_GPIO4                       (INT_SEC_BASE + 3)
-#define INT_UARTA                       (INT_SEC_BASE + 4)
-#define INT_UARTB                       (INT_SEC_BASE + 5)
-#define INT_I2C                         (INT_SEC_BASE + 6)
-#define INT_SPI                         (INT_SEC_BASE + 7)
-#define INT_TWC                         (INT_SEC_BASE + 8)
-#define INT_TMR3                        (INT_SEC_BASE + 9)
-#define INT_TMR4                        (INT_SEC_BASE + 10)
-#define INT_FLOW_RSM0                   (INT_SEC_BASE + 11)
-#define INT_FLOW_RSM1                   (INT_SEC_BASE + 12)
-#define INT_SPDIF                       (INT_SEC_BASE + 13)
-#define INT_UARTC                       (INT_SEC_BASE + 14)
-#define INT_MIPI                        (INT_SEC_BASE + 15)
-#define INT_EVENTA                      (INT_SEC_BASE + 16)
-#define INT_EVENTB                      (INT_SEC_BASE + 17)
-#define INT_EVENTC                      (INT_SEC_BASE + 18)
-#define INT_EVENTD                      (INT_SEC_BASE + 19)
-#define INT_VFIR                        (INT_SEC_BASE + 20)
-#define INT_DVC                         (INT_SEC_BASE + 21)
-#define INT_SYS_STATS_MON               (INT_SEC_BASE + 22)
-#define INT_GPIO5                       (INT_SEC_BASE + 23)
-#define INT_CPU0_PMU_INTR               (INT_SEC_BASE + 24)
-#define INT_CPU1_PMU_INTR               (INT_SEC_BASE + 25)
-#define INT_SEC_RES_26                  (INT_SEC_BASE + 26)
-#define INT_S_LINK1                     (INT_SEC_BASE + 27)
-#define INT_APB_DMA_COP                 (INT_SEC_BASE + 28)
-#define INT_AHB_DMA_COP                 (INT_SEC_BASE + 29)
-#define INT_DMA_TX                      (INT_SEC_BASE + 30)
-#define INT_DMA_RX                      (INT_SEC_BASE + 31)
-/* Tertiary Interrupt Controller */
-#define INT_TRI_BASE                    (INT_SEC_BASE + 32)
-#define INT_HOST1X_COP_SYNCPT           (INT_TRI_BASE + 0)
-#define INT_HOST1X_MPCORE_SYNCPT        (INT_TRI_BASE + 1)
-#define INT_HOST1X_COP_GENERAL          (INT_TRI_BASE + 2)
-#define INT_HOST1X_MPCORE_GENERAL       (INT_TRI_BASE + 3)
-#define INT_MPE_GENERAL                 (INT_TRI_BASE + 4)
-#define INT_VI_GENERAL                  (INT_TRI_BASE + 5)
-#define INT_EPP_GENERAL                 (INT_TRI_BASE + 6)
-#define INT_ISP_GENERAL                 (INT_TRI_BASE + 7)
-#define INT_2D_GENERAL                  (INT_TRI_BASE + 8)
-#define INT_DISPLAY_GENERAL             (INT_TRI_BASE + 9)
-#define INT_DISPLAY_B_GENERAL           (INT_TRI_BASE + 10)
-#define INT_HDMI                        (INT_TRI_BASE + 11)
-#define INT_TVO_GENERAL                 (INT_TRI_BASE + 12)
-#define INT_MC_GENERAL                  (INT_TRI_BASE + 13)
-#define INT_EMC_GENERAL                 (INT_TRI_BASE + 14)
-#define INT_TRI_RES_15                  (INT_TRI_BASE + 15)
-#define INT_TRI_RES_16                  (INT_TRI_BASE + 16)
-#define INT_AC97                        (INT_TRI_BASE + 17)
-#define INT_SPI_2                       (INT_TRI_BASE + 18)
-#define INT_SPI_3                       (INT_TRI_BASE + 19)
-#define INT_I2C2                        (INT_TRI_BASE + 20)
-#define INT_KBC                         (INT_TRI_BASE + 21)
-#define INT_EXTERNAL_PMU                (INT_TRI_BASE + 22)
-#define INT_GPIO6                       (INT_TRI_BASE + 23)
-#define INT_TVDAC                       (INT_TRI_BASE + 24)
-#define INT_GPIO7                       (INT_TRI_BASE + 25)
-#define INT_UARTD                       (INT_TRI_BASE + 26)
-#define INT_UARTE                       (INT_TRI_BASE + 27)
-#define INT_I2C3                        (INT_TRI_BASE + 28)
-#define INT_SPI_4                       (INT_TRI_BASE + 29)
-#define INT_TRI_RES_30                  (INT_TRI_BASE + 30)
-#define INT_SW_RESERVED                 (INT_TRI_BASE + 31)
-/* Quaternary Interrupt Controller */
-#define INT_QUAD_BASE                   (INT_TRI_BASE + 32)
-#define INT_SNOR                        (INT_QUAD_BASE + 0)
-#define INT_USB3                        (INT_QUAD_BASE + 1)
-#define INT_PCIE_INTR                   (INT_QUAD_BASE + 2)
-#define INT_PCIE_MSI                    (INT_QUAD_BASE + 3)
-#define INT_QUAD_RES_4                  (INT_QUAD_BASE + 4)
-#define INT_QUAD_RES_5                  (INT_QUAD_BASE + 5)
-#define INT_QUAD_RES_6                  (INT_QUAD_BASE + 6)
-#define INT_QUAD_RES_7                  (INT_QUAD_BASE + 7)
-#define INT_APB_DMA_CH0                 (INT_QUAD_BASE + 8)
-#define INT_APB_DMA_CH1                 (INT_QUAD_BASE + 9)
-#define INT_APB_DMA_CH2                 (INT_QUAD_BASE + 10)
-#define INT_APB_DMA_CH3                 (INT_QUAD_BASE + 11)
-#define INT_APB_DMA_CH4                 (INT_QUAD_BASE + 12)
-#define INT_APB_DMA_CH5                 (INT_QUAD_BASE + 13)
-#define INT_APB_DMA_CH6                 (INT_QUAD_BASE + 14)
-#define INT_APB_DMA_CH7                 (INT_QUAD_BASE + 15)
-#define INT_APB_DMA_CH8                 (INT_QUAD_BASE + 16)
-#define INT_APB_DMA_CH9                 (INT_QUAD_BASE + 17)
-#define INT_APB_DMA_CH10                (INT_QUAD_BASE + 18)
-#define INT_APB_DMA_CH11                (INT_QUAD_BASE + 19)
-#define INT_APB_DMA_CH12                (INT_QUAD_BASE + 20)
-#define INT_APB_DMA_CH13                (INT_QUAD_BASE + 21)
-#define INT_APB_DMA_CH14                (INT_QUAD_BASE + 22)
-#define INT_APB_DMA_CH15                (INT_QUAD_BASE + 23)
-#define INT_QUAD_RES_24                 (INT_QUAD_BASE + 24)
-#define INT_QUAD_RES_25                 (INT_QUAD_BASE + 25)
-#define INT_QUAD_RES_26                 (INT_QUAD_BASE + 26)
-#define INT_QUAD_RES_27                 (INT_QUAD_BASE + 27)
-#define INT_QUAD_RES_28                 (INT_QUAD_BASE + 28)
-#define INT_QUAD_RES_29                 (INT_QUAD_BASE + 29)
-#define INT_QUAD_RES_30                 (INT_QUAD_BASE + 30)
-#define INT_QUAD_RES_31                 (INT_QUAD_BASE + 31)
-/* Tegra30 has 5 banks of 32 IRQs */
-#define INT_MAIN_NR                     (32 * 5)
-#define INT_GPIO_BASE                   (INT_PRI_BASE + INT_MAIN_NR)
-/* Tegra30 has 8 banks of 32 GPIOs */
-#define INT_GPIO_NR                     (32 * 8)
-#define TEGRA_NR_IRQS                   (INT_GPIO_BASE + INT_GPIO_NR)
-#define INT_BOARD_BASE                  TEGRA_NR_IRQS
-#define NR_BOARD_IRQS                   32
-#define NR_IRQS                         (INT_BOARD_BASE + NR_BOARD_IRQS)
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 4752b1a68f35..06763fe7529d 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -20,6 +20,8 @@
 #ifndef _MACH_TEGRA_POWERGATE_H_
 #define _MACH_TEGRA_POWERGATE_H_
+struct clk;
 #define TEGRA_POWERGATE_CPU     0
 #define TEGRA_POWERGATE_3D      1
 #define TEGRA_POWERGATE_VENC    2
diff --git a/arch/arm/mach-tegra/include/mach/tegra-ahb.h b/arch/arm/mach-tegra/include/mach/tegra-ahb.h
deleted file mode 100644
index e0f8c84b1d8c..000000000000
--- a/arch/arm/mach-tegra/include/mach/tegra-ahb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-#ifndef __MACH_TEGRA_AHB_H__
-#define __MACH_TEGRA_AHB_H__
-extern int tegra_ahb_enable_smmu(struct device_node *ahb);
-#endif  /* __MACH_TEGRA_AHB_H__ */
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 937c4c50219e..485003f9b636 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -28,8 +28,7 @@
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <mach/iomap.h>
+#include "../../iomap.h"
-#include <mach/irammap.h>
 #define BIT(x) (1 << (x))
 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
@@ -52,17 +51,6 @@ static inline void flush(void)
 {
 }
-static inline void save_uart_address(void)
-{
-        u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
-        if (uart) {
-                buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
-                buf[1] = (u32)uart;
-        } else
-                buf[0] = 0;
-}
 static const struct {
        u32 base;
        u32 reset_reg;
@@ -139,51 +127,19 @@ int auto_odmdata(void)
 }
 #endif
-#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH
-int auto_scratch(void)
-{
-        int i;
-        /*
-         * Look for the first UART that:
-         * a) Is not in reset.
-         * b) Is clocked.
-         * c) Has a 'D' in the scratchpad register.
-         *
-         * Note that on Tegra30, the first two conditions are required, since
-         * if not true, accesses to the UART scratch register will hang.
-         * Tegra20 doesn't have this issue.
-         *
-         * The intent is that the bootloader will tell the kernel which UART
-         * to use by setting up those conditions. If nothing found, we'll fall
-         * back to what's specified in TEGRA_DEBUG_UART_BASE.
-         */
-        for (i = 0; i < ARRAY_SIZE(uarts); i++) {
-                if (!uart_clocked(i))
-                        continue;
-                uart = (volatile u8 *)uarts[i].base;
-                if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
-                        continue;
-                return i;
-        }
-        return -1;
-}
-#endif
 /*
 * Setup before decompression.  This is where we do UART selection for
 * earlyprintk and init the uart_base register.
 */
 static inline void arch_decomp_setup(void)
 {
-        int uart_id, auto_uart_id;
+        int uart_id;
        volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
        u32 chip, div;
-#if defined(CONFIG_TEGRA_DEBUG_UARTA)
+#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
+        uart_id = auto_odmdata();
+#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
        uart_id = 0;
 #elif defined(CONFIG_TEGRA_DEBUG_UARTB)
        uart_id = 1;
@@ -193,19 +149,7 @@ static inline void arch_decomp_setup(void)
        uart_id = 3;
 #elif defined(CONFIG_TEGRA_DEBUG_UARTE)
        uart_id = 4;
-#else
-        uart_id = -1;
-#endif
-#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
-        auto_uart_id = auto_odmdata();
-#elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH)
-        auto_uart_id = auto_scratch();
-#else
-        auto_uart_id = -1;
 #endif
-        if (auto_uart_id != -1)
-                uart_id = auto_uart_id;
        if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
            !uart_clocked(uart_id))
@@ -213,7 +157,6 @@ static inline void arch_decomp_setup(void)
        else
                uart = (volatile u8 *)uarts[uart_id].base;
-        save_uart_address();
        if (uart == NULL)
                return;
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 58b4baf9c483..bb9c9c29d181 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -26,9 +26,9 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
-#include <mach/iomap.h>
 #include "board.h"
+#include "iomap.h"
 static struct map_desc tegra_io_desc[] __initdata = {
        {
@@ -59,5 +59,6 @@ static struct map_desc tegra_io_desc[] __initdata = {
 void __init tegra_map_common_io(void)
 {
+        debug_ll_io_init();
        iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
 }
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/iomap.h
index fee3a94c4549..db8be51cad80 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/mach-tegra/include/mach/iomap.h
- *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
@@ -263,20 +261,6 @@
 #define TEGRA_SDMMC4_BASE               0xC8000600
 #define TEGRA_SDMMC4_SIZE               SZ_512
-#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
-# define TEGRA_DEBUG_UART_BASE 0
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
-#endif
 /* On TEGRA, many peripherals are very closely packed in
 * two 256MB io windows (that actually only use about 64KB
 * at the start of each).
diff --git a/arch/arm/mach-tegra/include/mach/irammap.h b/arch/arm/mach-tegra/irammap.h
index 0cbe63261854..501952a84344 100644
--- a/arch/arm/mach-tegra/include/mach/irammap.h
+++ b/arch/arm/mach-tegra/irammap.h
@@ -23,13 +23,4 @@
 #define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
 #define TEGRA_IRAM_RESET_HANDLER_SIZE   SZ_1K
-/*
- * These locations are written to by uncompress.h, and read by debug-macro.S.
- * The first word holds the cookie value if the data is valid. The second
- * word holds the UART physical address.
- */
-#define TEGRA_IRAM_DEBUG_UART_OFFSET    SZ_1K
-#define TEGRA_IRAM_DEBUG_UART_SIZE      8
-#define TEGRA_IRAM_DEBUG_UART_COOKIE    0x55415254
 #endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 2f5bd2db8e1f..b7886f183511 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -25,9 +25,8 @@
 #include <asm/hardware/gic.h>
-#include <mach/iomap.h>
 #include "board.h"
+#include "iomap.h"
 #define ICTLR_CPU_IEP_VFIQ      0x08
 #define ICTLR_CPU_IEP_FIR       0x14
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index a8dba6489c9b..53d085871798 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -37,11 +37,14 @@
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
-#include <mach/iomap.h>
 #include <mach/clk.h>
 #include <mach/powergate.h>
 #include "board.h"
+#include "iomap.h"
+/* Hack - need to parse this from DT */
+#define INT_PCIE_INTR 130
 /* register definitions */
 #define AFI_OFFSET      0x3800
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 81cb26591acf..1b926df99c4b 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,8 +24,6 @@
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
-#include <mach/clk.h>
-#include <mach/iomap.h>
 #include <mach/powergate.h>
 #include "fuse.h"
@@ -34,6 +32,7 @@
 #include "tegra_cpu_car.h"
 #include "common.h"
+#include "iomap.h"
 extern void tegra_secondary_startup(void);
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
new file mode 100644
index 000000000000..1b11707eaca0
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.c
@@ -0,0 +1,216 @@
+/*
+ * CPU complex suspend & resume functions for Tegra SoCs
+ *
+ * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <linux/cpu_pm.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm/smp_plat.h>
+#include <asm/cacheflush.h>
+#include <asm/suspend.h>
+#include <asm/idmap.h>
+#include <asm/proc-fns.h>
+#include <asm/tlbflush.h>
+#include "iomap.h"
+#include "reset.h"
+#include "flowctrl.h"
+#include "sleep.h"
+#include "tegra_cpu_car.h"
+#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
+#define PMC_CTRL                0x0
+#define PMC_CPUPWRGOOD_TIMER    0xc8
+#define PMC_CPUPWROFF_TIMER     0xcc
+#ifdef CONFIG_PM_SLEEP
+static unsigned int g_diag_reg;
+static DEFINE_SPINLOCK(tegra_lp2_lock);
+static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+static struct clk *tegra_pclk;
+void (*tegra_tear_down_cpu)(void);
+void save_cpu_arch_register(void)
+{
+        /* read diagnostic register */
+        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
+        return;
+}
+void restore_cpu_arch_register(void)
+{
+        /* write diagnostic register */
+        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
+        return;
+}
+static void set_power_timers(unsigned long us_on, unsigned long us_off)
+{
+        unsigned long long ticks;
+        unsigned long long pclk;
+        unsigned long rate;
+        static unsigned long tegra_last_pclk;
+        if (tegra_pclk == NULL) {
+                tegra_pclk = clk_get_sys(NULL, "pclk");
+                WARN_ON(IS_ERR(tegra_pclk));
+        }
+        rate = clk_get_rate(tegra_pclk);
+        if (WARN_ON_ONCE(rate <= 0))
+                pclk = 100000000;
+        else
+                pclk = rate;
+        if ((rate != tegra_last_pclk)) {
+                ticks = (us_on * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
+                ticks = (us_off * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
+                wmb();
+        }
+        tegra_last_pclk = pclk;
+}
+/*
+ * restore_cpu_complex
+ *
+ * restores cpu clock setting, clears flow controller
+ *
+ * Always called on CPU 0.
+ */
+static void restore_cpu_complex(void)
+{
+        int cpu = smp_processor_id();
+        BUG_ON(cpu != 0);
+#ifdef CONFIG_SMP
+        cpu = cpu_logical_map(cpu);
+#endif
+        /* Restore the CPU clock settings */
+        tegra_cpu_clock_resume();
+        flowctrl_cpu_suspend_exit(cpu);
+        restore_cpu_arch_register();
+}
+/*
+ * suspend_cpu_complex
+ *
+ * saves pll state for use by restart_plls, prepares flow controller for
+ * transition to suspend state
+ *
+ * Must always be called on cpu 0.
+ */
+static void suspend_cpu_complex(void)
+{
+        int cpu = smp_processor_id();
+        BUG_ON(cpu != 0);
+#ifdef CONFIG_SMP
+        cpu = cpu_logical_map(cpu);
+#endif
+        /* Save the CPU clock settings */
+        tegra_cpu_clock_suspend();
+        flowctrl_cpu_suspend_enter(cpu);
+        save_cpu_arch_register();
+}
+void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)
+{
+        u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
+        spin_lock(&tegra_lp2_lock);
+        BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
+        *cpu_in_lp2 &= ~BIT(phy_cpu_id);
+        spin_unlock(&tegra_lp2_lock);
+}
+bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
+{
+        bool last_cpu = false;
+        cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
+        u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
+        spin_lock(&tegra_lp2_lock);
+        BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
+        *cpu_in_lp2 |= BIT(phy_cpu_id);
+        if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
+                last_cpu = true;
+        spin_unlock(&tegra_lp2_lock);
+        return last_cpu;
+}
+static int tegra_sleep_cpu(unsigned long v2p)
+{
+        /* Switch to the identity mapping. */
+        cpu_switch_mm(idmap_pgd, &init_mm);
+        /* Flush the TLB. */
+        local_flush_tlb_all();
+        tegra_sleep_cpu_finish(v2p);
+        /* should never here */
+        BUG();
+        return 0;
+}
+void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+{
+        u32 mode;
+        /* Only the last cpu down does the final suspend steps */
+        mode = readl(pmc + PMC_CTRL);
+        mode |= TEGRA_POWER_CPU_PWRREQ_OE;
+        writel(mode, pmc + PMC_CTRL);
+        set_power_timers(cpu_on_time, cpu_off_time);
+        cpu_cluster_pm_enter();
+        suspend_cpu_complex();
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+        restore_cpu_complex();
+        cpu_cluster_pm_exit();
+}
+#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
new file mode 100644
index 000000000000..787335cc964c
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA Corporation. All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _MACH_TEGRA_PM_H_
+#define _MACH_TEGRA_PM_H_
+extern unsigned long l2x0_saved_regs_addr;
+void save_cpu_arch_register(void);
+void restore_cpu_arch_register(void);
+void tegra_clear_cpu_in_lp2(int phy_cpu_id);
+bool tegra_set_cpu_in_lp2(int phy_cpu_id);
+void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+extern void (*tegra_tear_down_cpu)(void);
+#endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 7af6a54404be..d4fdb5fcec20 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -19,7 +19,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
-#include <mach/iomap.h>
+#include "iomap.h"
 #define PMC_CTRL                0x0
 #define PMC_CTRL_INTR_LOW       (1 << 17)
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index de0662de28a0..2cc1185d902e 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -28,10 +28,10 @@
 #include <linux/spinlock.h>
 #include <mach/clk.h>
-#include <mach/iomap.h>
 #include <mach/powergate.h>
 #include "fuse.h"
+#include "iomap.h"
 #define PWRGATE_TOGGLE          0x30
 #define  PWRGATE_TOGGLE_START   (1 << 8)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 5beb7ebe2948..3fd89ecd158e 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -22,10 +22,10 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/iomap.h>
+#include "iomap.h"
-#include <mach/irammap.h>
+#include "irammap.h"
 #include "reset.h"
+#include "sleep.h"
 #include "fuse.h"
 #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
@@ -80,5 +80,10 @@ void __init tegra_cpu_reset_handler_init(void)
                virt_to_phys((void *)tegra_secondary_startup);
 #endif
+#ifdef CONFIG_PM_SLEEP
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
+                virt_to_phys((void *)tegra_resume);
+#endif
        tegra_cpu_reset_handler_enable();
 }
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index de88bf851dd3..c90d8e9c4ad2 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -29,6 +29,8 @@
 #ifndef __ASSEMBLY__
+#include "irammap.h"
 extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
 void __tegra_cpu_reset_handler_start(void);
@@ -36,6 +38,13 @@ void __tegra_cpu_reset_handler(void);
 void __tegra_cpu_reset_handler_end(void);
 void tegra_secondary_startup(void);
+#ifdef CONFIG_PM_SLEEP
+#define tegra_cpu_lp2_mask \
+        (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
+        ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
+         (u32)__tegra_cpu_reset_handler_start)))
+#endif
 #define tegra_cpu_reset_handler_offset \
                ((u32)__tegra_cpu_reset_handler - \
                 (u32)__tegra_cpu_reset_handler_start)
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index a36ae413e2b8..72ce709799da 100644
--- a/arch/arm/mach-tegra/sleep-t20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -22,8 +22,6 @@
 #include <asm/assembler.h>
-#include <mach/iomap.h>
 #include "sleep.h"
 #include "flowctrl.h"
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 777d9cee8b90..562a8e7e413d 100644
--- a/arch/arm/mach-tegra/sleep-t30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -17,8 +17,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/asm-offsets.h>
-#include <mach/iomap.h>
 #include "sleep.h"
 #include "flowctrl.h"
@@ -82,6 +81,7 @@ delay_1:
        ldr     r3, [r1]                        @ read CSR
        str     r3, [r1]                        @ clear CSR
        tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
        movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
        str     r3, [r2]
        ldr     r0, [r2]
@@ -105,3 +105,67 @@ wfe_war:
 ENDPROC(tegra30_cpu_shutdown)
 #endif
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
+ *
+ * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
+ */
+ENTRY(tegra30_sleep_cpu_secondary_finish)
+        mov     r7, lr
+        /* Flush and disable the L1 data cache */
+        bl      tegra_disable_clean_inv_dcache
+        /* Powergate this CPU. */
+        mov     r0, #0                          @ power mode flags (!hotplug)
+        bl      tegra30_cpu_shutdown
+        mov     r0, #1                          @ never return here
+        mov     pc, r7
+ENDPROC(tegra30_sleep_cpu_secondary_finish)
+/*
+ * tegra30_tear_down_cpu
+ *
+ * Switches the CPU to enter sleep.
+ */
+ENTRY(tegra30_tear_down_cpu)
+        mov32   r6, TEGRA_FLOW_CTRL_BASE
+        b       tegra30_enter_sleep
+ENDPROC(tegra30_tear_down_cpu)
+/*
+ * tegra30_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
+ * executes from SDRAM with target state is LP2
+ * r6 = TEGRA_FLOW_CTRL_BASE
+ */
+tegra30_enter_sleep:
+        cpu_id  r1
+        cpu_to_csr_reg  r2, r1
+        ldr     r0, [r6, r2]
+        orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
+        str     r0, [r6, r2]
+        mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
+        orr     r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+        cpu_to_halt_reg r2, r1
+        str     r0, [r6, r2]
+        dsb
+        ldr     r0, [r6, r2] /* memory barrier */
+halted:
+        isb
+        dsb
+        wfi     /* CPU should be power gated here */
+        /* !!!FIXME!!! Implement halt failure handler */
+        b       halted
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index ea81554c4833..26afa7cbed11 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -25,9 +25,87 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/cache.h>
+#include <asm/cp15.h>
+#include <asm/hardware/cache-l2x0.h>
-#include <mach/iomap.h>
+#include "iomap.h"
 #include "flowctrl.h"
 #include "sleep.h"
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_disable_clean_inv_dcache
+ *
+ * disable, clean & invalidate the D-cache
+ *
+ * Corrupted registers: r1-r3, r6, r8, r9-r11
+ */
+ENTRY(tegra_disable_clean_inv_dcache)
+        stmfd   sp!, {r0, r4-r5, r7, r9-r11, lr}
+        dmb                                     @ ensure ordering
+        /* Disable the D-cache */
+        mrc     p15, 0, r2, c1, c0, 0
+        bic     r2, r2, #CR_C
+        mcr     p15, 0, r2, c1, c0, 0
+        isb
+        /* Flush the D-cache */
+        bl      v7_flush_dcache_louis
+        /* Trun off coherency */
+        exit_smp r4, r5
+        ldmfd   sp!, {r0, r4-r5, r7, r9-r11, pc}
+ENDPROC(tegra_disable_clean_inv_dcache)
+/*
+ * tegra_sleep_cpu_finish(unsigned long v2p)
+ *
+ * enters suspend in LP2 by turning off the mmu and jumping to
+ * tegra?_tear_down_cpu
+ */
+ENTRY(tegra_sleep_cpu_finish)
+        /* Flush and disable the L1 data cache */
+        bl      tegra_disable_clean_inv_dcache
+        mov32   r6, tegra_tear_down_cpu
+        ldr     r1, [r6]
+        add     r1, r1, r0
+        mov32   r3, tegra_shut_off_mmu
+        add     r3, r3, r0
+        mov     r0, r1
+        mov     pc, r3
+ENDPROC(tegra_sleep_cpu_finish)
+/*
+ * tegra_shut_off_mmu
+ *
+ * r0 = physical address to jump to with mmu off
+ *
+ * called with VA=PA mapping
+ * turns off MMU, icache, dcache and branch prediction
+ */
+        .align  L1_CACHE_SHIFT
+        .pushsection    .idmap.text, "ax"
+ENTRY(tegra_shut_off_mmu)
+        mrc     p15, 0, r3, c1, c0, 0
+        movw    r2, #CR_I | CR_Z | CR_C | CR_M
+        bic     r3, r3, r2
+        dsb
+        mcr     p15, 0, r3, c1, c0, 0
+        isb
+#ifdef CONFIG_CACHE_L2X0
+        /* Disable L2 cache */
+        mov32   r4, TEGRA_ARM_PERIF_BASE + 0x3000
+        mov     r5, #0
+        str     r5, [r4, #L2X0_CTRL]
+#endif
+        mov     pc, r0
+ENDPROC(tegra_shut_off_mmu)
+        .popsection
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index e25a7cd703d9..9821ee725420 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -17,7 +17,7 @@
 #ifndef __MACH_TEGRA_SLEEP_H
 #define __MACH_TEGRA_SLEEP_H
-#include <mach/iomap.h>
+#include "iomap.h"
 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
                                        + IO_CPU_VIRT)
@@ -71,7 +71,41 @@
        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
        dsb
 .endm
+/* Macro to resume & re-enable L2 cache */
+#ifndef L2X0_CTRL_EN
+#define L2X0_CTRL_EN    1
+#endif
+#ifdef CONFIG_CACHE_L2X0
+.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
+        adr     \tmp1, \phys_l2x0_saved_regs
+        ldr     \tmp1, [\tmp1]
+        ldr     \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
+        ldr     \tmp3, [\tmp2, #L2X0_CTRL]
+        tst     \tmp3, #L2X0_CTRL_EN
+        bne     exit_l2_resume
+        ldr     \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
+        str     \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
+        str     \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
+        str     \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
+        str     \tmp3, [\tmp2, #L2X0_POWER_CTRL]
+        ldr     \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
+        str     \tmp3, [\tmp2, #L2X0_AUX_CTRL]
+        mov     \tmp3, #L2X0_CTRL_EN
+        str     \tmp3, [\tmp2, #L2X0_CTRL]
+exit_l2_resume:
+.endm
+#else /* CONFIG_CACHE_L2X0 */
+.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
+.endm
+#endif /* CONFIG_CACHE_L2X0 */
 #else
+void tegra_resume(void);
+int tegra_sleep_cpu_finish(unsigned long);
 #ifdef CONFIG_HOTPLUG_CPU
 void tegra20_hotplug_init(void);
@@ -81,5 +115,8 @@ static inline void tegra20_hotplug_init(void) {}
 static inline void tegra30_hotplug_init(void) {}
 #endif
+int tegra30_sleep_cpu_secondary_finish(unsigned long);
+void tegra30_tear_down_cpu(void);
 #endif
 #endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index deb873fb12b6..4eb6bc81a87b 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -27,10 +27,9 @@
 #include <linux/clkdev.h>
 #include <linux/clk.h>
-#include <mach/iomap.h>
 #include "clock.h"
 #include "fuse.h"
+#include "iomap.h"
 #include "tegra2_emc.h"
 #include "tegra_cpu_car.h"
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 8d398a33adf7..a23a0734e352 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -27,8 +27,6 @@
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <mach/iomap.h>
 #include "clock.h"
 #include "fuse.h"
 #include "tegra2_emc.h"
@@ -248,11 +246,16 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
        { 19200000, 216000000, 135, 12, 1, 3},
        { 26000000, 216000000, 216, 26, 1, 4},
+        { 12000000, 297000000,  99,  4, 1, 4 },
+        { 12000000, 339000000, 113,  4, 1, 4 },
        { 12000000, 594000000, 594, 12, 1, 8},
        { 13000000, 594000000, 594, 13, 1, 8},
        { 19200000, 594000000, 495, 16, 1, 8},
        { 26000000, 594000000, 594, 26, 1, 8},
+        { 12000000, 616000000, 616, 12, 1, 8},
        { 12000000, 1000000000, 1000, 12, 1, 12},
        { 13000000, 1000000000, 1000, 13, 1, 12},
        { 19200000, 1000000000, 625,  12, 1, 8},
@@ -1038,9 +1041,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("usbd",   "utmip-pad",    NULL),
        CLK_DUPLICATE("usbd",   "tegra-ehci.0", NULL),
        CLK_DUPLICATE("usbd",   "tegra-otg",    NULL),
-        CLK_DUPLICATE("hdmi",   "tegradc.0",    "hdmi"),
-        CLK_DUPLICATE("hdmi",   "tegradc.1",    "hdmi"),
-        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
        CLK_DUPLICATE("2d",     "tegra_grhost", "gr2d"),
        CLK_DUPLICATE("3d",     "tegra_grhost", "gr3d"),
        CLK_DUPLICATE("epp",    "tegra_grhost", "epp"),
@@ -1053,6 +1053,9 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
+        CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
+        CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
+        CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
 };
 #define CLK(dev, con, ck)       \
diff --git a/arch/arm/mach-tegra/tegra20_speedo.c b/arch/arm/mach-tegra/tegra20_speedo.c
new file mode 100644
index 000000000000..fa6eb570623f
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_speedo.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include "fuse.h"
+#define CPU_SPEEDO_LSBIT                20
+#define CPU_SPEEDO_MSBIT                29
+#define CPU_SPEEDO_REDUND_LSBIT         30
+#define CPU_SPEEDO_REDUND_MSBIT         39
+#define CPU_SPEEDO_REDUND_OFFS  (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
+#define CORE_SPEEDO_LSBIT               40
+#define CORE_SPEEDO_MSBIT               47
+#define CORE_SPEEDO_REDUND_LSBIT        48
+#define CORE_SPEEDO_REDUND_MSBIT        55
+#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
+#define SPEEDO_MULT                     4
+#define PROCESS_CORNERS_NUM             4
+#define SPEEDO_ID_SELECT_0(rev)         ((rev) <= 2)
+#define SPEEDO_ID_SELECT_1(sku)         \
+        (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
+         ((sku) != 27) && ((sku) != 28))
+enum {
+        SPEEDO_ID_0,
+        SPEEDO_ID_1,
+        SPEEDO_ID_2,
+        SPEEDO_ID_COUNT,
+};
+static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
+        {315, 366, 420, UINT_MAX},
+        {303, 368, 419, UINT_MAX},
+        {316, 331, 383, UINT_MAX},
+};
+static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
+        {165, 195, 224, UINT_MAX},
+        {165, 195, 224, UINT_MAX},
+        {165, 195, 224, UINT_MAX},
+};
+void tegra20_init_speedo_data(void)
+{
+        u32 reg;
+        u32 val;
+        int i;
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
+        if (SPEEDO_ID_SELECT_0(tegra_revision))
+                tegra_soc_speedo_id = SPEEDO_ID_0;
+        else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
+                tegra_soc_speedo_id = SPEEDO_ID_1;
+        else
+                tegra_soc_speedo_id = SPEEDO_ID_2;
+        val = 0;
+        for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
+                reg = tegra_spare_fuse(i) |
+                        tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
+                val = (val << 1) | (reg & 0x1);
+        }
+        val = val * SPEEDO_MULT;
+        pr_debug("%s CPU speedo value %u\n", __func__, val);
+        for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+                if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
+                        break;
+        }
+        tegra_cpu_process_id = i;
+        val = 0;
+        for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
+                reg = tegra_spare_fuse(i) |
+                        tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
+                val = (val << 1) | (reg & 0x1);
+        }
+        val = val * SPEEDO_MULT;
+        pr_debug("%s Core speedo value %u\n", __func__, val);
+        for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+                if (val <= core_process_speedos[tegra_soc_speedo_id][i])
+                        break;
+        }
+        tegra_core_process_id = i;
+        pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id);
+}
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 5070d833bdd1..837c7b9ea63b 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -25,8 +25,6 @@
 #include <linux/platform_device.h>
 #include <linux/platform_data/tegra_emc.h>
-#include <mach/iomap.h>
 #include "tegra2_emc.h"
 #include "fuse.h"
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index e9de5dfd94ec..efc000e32e1c 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -31,10 +31,11 @@
 #include <asm/clkdev.h>
-#include <mach/iomap.h>
+#include <mach/powergate.h>
 #include "clock.h"
 #include "fuse.h"
+#include "iomap.h"
 #include "tegra_cpu_car.h"
 #define USE_PLL_LOCK_BITS 0
@@ -310,6 +311,31 @@
 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
+#define CLK_RESET_CCLK_BURST    0x20
+#define CLK_RESET_CCLK_DIVIDER  0x24
+#define CLK_RESET_PLLX_BASE     0xe0
+#define CLK_RESET_PLLX_MISC     0xe4
+#define CLK_RESET_SOURCE_CSITE  0x1d4
+#define CLK_RESET_CCLK_BURST_POLICY_SHIFT       28
+#define CLK_RESET_CCLK_RUN_POLICY_SHIFT         4
+#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT        0
+#define CLK_RESET_CCLK_IDLE_POLICY              1
+#define CLK_RESET_CCLK_RUN_POLICY               2
+#define CLK_RESET_CCLK_BURST_POLICY_PLLX        8
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+        u32 pllx_misc;
+        u32 pllx_base;
+        u32 cpu_burst;
+        u32 clk_csite_src;
+        u32 cclk_divider;
+} tegra30_cpu_clk_sctx;
+#endif
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -792,6 +818,112 @@ struct clk_ops tegra30_twd_ops = {
        .recalc_rate = tegra30_twd_clk_recalc_rate,
 };
+/* bus clock functions */
+static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+        return c->state;
+}
+static int tegra30_bus_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        val = clk_readl(c->reg);
+        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+        clk_writel(val, c->reg);
+        return 0;
+}
+static void tegra30_bus_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        val = clk_readl(c->reg);
+        val |= BUS_CLK_DISABLE << c->reg_shift;
+        clk_writel(val, c->reg);
+}
+static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u64 rate = prate;
+        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+        c->mul = 1;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int ret = -EINVAL;
+        u32 val;
+        int i;
+        val = clk_readl(c->reg);
+        for (i = 1; i <= 4; i++) {
+                if (rate == parent_rate / i) {
+                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+                        val |= (i - 1) << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = i;
+                        c->mul = 1;
+                        ret = 0;
+                        break;
+                }
+        }
+        return ret;
+}
+static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+        s64 divider;
+        if (rate >= parent_rate)
+                return parent_rate;
+        divider = parent_rate;
+        divider += rate - 1;
+        do_div(divider, rate);
+        if (divider < 0)
+                return divider;
+        if (divider > 4)
+                divider = 4;
+        do_div(parent_rate, divider);
+        return parent_rate;
+}
+struct clk_ops tegra30_bus_ops = {
+        .is_enabled = tegra30_bus_clk_is_enabled,
+        .enable = tegra30_bus_clk_enable,
+        .disable = tegra30_bus_clk_disable,
+        .set_rate = tegra30_bus_clk_set_rate,
+        .round_rate = tegra30_bus_clk_round_rate,
+        .recalc_rate = tegra30_bus_clk_recalc_rate,
+};
 /* Blink output functions */
 static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
 {
@@ -2281,12 +2413,93 @@ static void tegra30_disable_cpu_clock(u32 cpu)
               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
 }
+#ifdef CONFIG_PM_SLEEP
+static bool tegra30_cpu_rail_off_ready(void)
+{
+        unsigned int cpu_rst_status;
+        int cpu_pwr_status;
+        cpu_rst_status = readl(reg_clk_base +
+                               TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+        cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
+                         tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
+                         tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
+        if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
+                return false;
+        return true;
+}
+static void tegra30_cpu_clock_suspend(void)
+{
+        /* switch coresite to clk_m, save off original source */
+        tegra30_cpu_clk_sctx.clk_csite_src =
+                                readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
+        writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
+        tegra30_cpu_clk_sctx.cpu_burst =
+                                readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+        tegra30_cpu_clk_sctx.pllx_base =
+                                readl(reg_clk_base + CLK_RESET_PLLX_BASE);
+        tegra30_cpu_clk_sctx.pllx_misc =
+                                readl(reg_clk_base + CLK_RESET_PLLX_MISC);
+        tegra30_cpu_clk_sctx.cclk_divider =
+                                readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+}
+static void tegra30_cpu_clock_resume(void)
+{
+        unsigned int reg, policy;
+        /* Is CPU complex already running on PLLX? */
+        reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+        policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
+        if (policy == CLK_RESET_CCLK_IDLE_POLICY)
+                reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
+        else if (policy == CLK_RESET_CCLK_RUN_POLICY)
+                reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
+        else
+                BUG();
+        if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
+                /* restore PLLX settings if CPU is on different PLL */
+                writel(tegra30_cpu_clk_sctx.pllx_misc,
+                                        reg_clk_base + CLK_RESET_PLLX_MISC);
+                writel(tegra30_cpu_clk_sctx.pllx_base,
+                                        reg_clk_base + CLK_RESET_PLLX_BASE);
+                /* wait for PLL stabilization if PLLX was enabled */
+                if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
+                        udelay(300);
+        }
+        /*
+         * Restore original burst policy setting for calls resulting from CPU
+         * LP2 in idle or system suspend.
+         */
+        writel(tegra30_cpu_clk_sctx.cclk_divider,
+                                        reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+        writel(tegra30_cpu_clk_sctx.cpu_burst,
+                                        reg_clk_base + CLK_RESET_CCLK_BURST);
+        writel(tegra30_cpu_clk_sctx.clk_csite_src,
+                                        reg_clk_base + CLK_RESET_SOURCE_CSITE);
+}
+#endif
 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
        .wait_for_reset = tegra30_wait_cpu_in_reset,
        .put_in_reset   = tegra30_put_cpu_in_reset,
        .out_of_reset   = tegra30_cpu_out_of_reset,
        .enable_clock   = tegra30_enable_cpu_clock,
        .disable_clock  = tegra30_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+        .rail_off_ready = tegra30_cpu_rail_off_ready,
+        .suspend        = tegra30_cpu_clock_suspend,
+        .resume         = tegra30_cpu_clock_resume,
+#endif
 };
 void __init tegra30_cpu_car_ops_init(void)
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
index f2f88fef6b8b..7a34adb2f72d 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -34,6 +34,7 @@ extern struct clk_ops tegra_clk_out_ops;
 extern struct clk_ops tegra30_super_ops;
 extern struct clk_ops tegra30_blink_clk_ops;
 extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_bus_ops;
 extern struct clk_ops tegra30_periph_clk_ops;
 extern struct clk_ops tegra30_dsib_clk_ops;
 extern struct clk_ops tegra_nand_clk_ops;
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 3d2e5532a9ea..6942c7add3bb 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -711,6 +711,50 @@ static struct clk tegra_clk_sclk = {
        .num_parents = ARRAY_SIZE(mux_sclk),
 };
+static const char *tegra_hclk_parent_names[] = {
+        "tegra_sclk",
+};
+static struct clk *tegra_hclk_parents[] = {
+        &tegra_clk_sclk,
+};
+static struct clk tegra_hclk;
+static struct clk_tegra tegra_hclk_hw = {
+        .hw = {
+                .clk = &tegra_hclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 4,
+        .max_rate = 378000000,
+        .min_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
+                tegra_hclk_parents, &tegra_clk_sclk);
+static const char *tegra_pclk_parent_names[] = {
+        "tegra_hclk",
+};
+static struct clk *tegra_pclk_parents[] = {
+        &tegra_hclk,
+};
+static struct clk tegra_pclk;
+static struct clk_tegra tegra_pclk_hw = {
+        .hw = {
+                .clk = &tegra_pclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 0,
+        .max_rate = 167000000,
+        .min_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
+                tegra_pclk_parents, &tegra_hclk);
 static const char *mux_blink[] = {
        "clk_32k",
 };
@@ -1254,8 +1298,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
@@ -1293,6 +1335,9 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
+        CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
+        CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
+        CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
 };
 struct clk *tegra_ptr_clks[] = {
@@ -1325,6 +1370,8 @@ struct clk *tegra_ptr_clks[] = {
        &tegra_cml1,
        &tegra_pciex,
        &tegra_clk_sclk,
+        &tegra_hclk,
+        &tegra_pclk,
        &tegra_clk_blink,
        &tegra30_clk_twd,
 };
diff --git a/arch/arm/mach-tegra/tegra30_speedo.c b/arch/arm/mach-tegra/tegra30_speedo.c
new file mode 100644
index 000000000000..125cb16424a6
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_speedo.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include "fuse.h"
+#define CORE_PROCESS_CORNERS_NUM        1
+#define CPU_PROCESS_CORNERS_NUM         6
+#define FUSE_SPEEDO_CALIB_0     0x114
+#define FUSE_PACKAGE_INFO       0X1FC
+#define FUSE_TEST_PROG_VER      0X128
+#define G_SPEEDO_BIT_MINUS1     58
+#define G_SPEEDO_BIT_MINUS1_R   59
+#define G_SPEEDO_BIT_MINUS2     60
+#define G_SPEEDO_BIT_MINUS2_R   61
+#define LP_SPEEDO_BIT_MINUS1    62
+#define LP_SPEEDO_BIT_MINUS1_R  63
+#define LP_SPEEDO_BIT_MINUS2    64
+#define LP_SPEEDO_BIT_MINUS2_R  65
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_2,
+        THRESHOLD_INDEX_3,
+        THRESHOLD_INDEX_4,
+        THRESHOLD_INDEX_5,
+        THRESHOLD_INDEX_6,
+        THRESHOLD_INDEX_7,
+        THRESHOLD_INDEX_8,
+        THRESHOLD_INDEX_9,
+        THRESHOLD_INDEX_10,
+        THRESHOLD_INDEX_11,
+        THRESHOLD_INDEX_COUNT,
+};
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+        {180},
+        {170},
+        {195},
+        {180},
+        {168},
+        {192},
+        {180},
+        {170},
+        {195},
+        {180},
+        {180},
+        {180},
+};
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+        {306, 338, 360, 376, UINT_MAX},
+        {295, 336, 358, 375, UINT_MAX},
+        {325, 325, 358, 375, UINT_MAX},
+        {325, 325, 358, 375, UINT_MAX},
+        {292, 324, 348, 364, UINT_MAX},
+        {324, 324, 348, 364, UINT_MAX},
+        {324, 324, 348, 364, UINT_MAX},
+        {295, 336, 358, 375, UINT_MAX},
+        {358, 358, 358, 358, 397, UINT_MAX},
+        {364, 364, 364, 364, 397, UINT_MAX},
+        {295, 336, 358, 375, 391, UINT_MAX},
+        {295, 336, 358, 375, 391, UINT_MAX},
+};
+static int threshold_index;
+static int package_id;
+static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
+{
+        u32 reg;
+        int ate_ver;
+        int bit_minus1;
+        int bit_minus2;
+        reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
+        *speedo_lp = (reg & 0xFFFF) * 4;
+        *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
+        ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
+        pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
+        if (ate_ver >= 26) {
+                bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
+                bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
+                bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
+                bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
+                *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
+                bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
+                bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
+                bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
+                bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
+                *speedo_g |= (bit_minus1 << 1) | bit_minus2;
+        } else {
+                *speedo_lp |= 0x3;
+                *speedo_g |= 0x3;
+        }
+}
+static void rev_sku_to_speedo_ids(int rev, int sku)
+{
+        switch (rev) {
+        case TEGRA_REVISION_A01:
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                threshold_index = THRESHOLD_INDEX_0;
+                break;
+        case TEGRA_REVISION_A02:
+        case TEGRA_REVISION_A03:
+                switch (sku) {
+                case 0x87:
+                case 0x82:
+                        tegra_cpu_speedo_id = 1;
+                        tegra_soc_speedo_id = 1;
+                        threshold_index = THRESHOLD_INDEX_1;
+                        break;
+                case 0x81:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 2;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_2;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 4;
+                                tegra_soc_speedo_id = 1;
+                                threshold_index = THRESHOLD_INDEX_7;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                case 0x80:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 5;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_8;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 6;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_9;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                case 0x83:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 7;
+                                tegra_soc_speedo_id = 1;
+                                threshold_index = THRESHOLD_INDEX_10;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 3;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_3;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                case 0x8F:
+                        tegra_cpu_speedo_id = 8;
+                        tegra_soc_speedo_id = 1;
+                        threshold_index = THRESHOLD_INDEX_11;
+                        break;
+                case 0x08:
+                        tegra_cpu_speedo_id = 1;
+                        tegra_soc_speedo_id = 1;
+                        threshold_index = THRESHOLD_INDEX_4;
+                        break;
+                case 0x02:
+                        tegra_cpu_speedo_id = 2;
+                        tegra_soc_speedo_id = 2;
+                        threshold_index = THRESHOLD_INDEX_5;
+                        break;
+                case 0x04:
+                        tegra_cpu_speedo_id = 3;
+                        tegra_soc_speedo_id = 2;
+                        threshold_index = THRESHOLD_INDEX_6;
+                        break;
+                case 0:
+                        switch (package_id) {
+                        case 1:
+                                tegra_cpu_speedo_id = 2;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_2;
+                                break;
+                        case 2:
+                                tegra_cpu_speedo_id = 3;
+                                tegra_soc_speedo_id = 2;
+                                threshold_index = THRESHOLD_INDEX_3;
+                                break;
+                        default:
+                                pr_err("Tegra30: Unknown pkg %d\n", package_id);
+                                BUG();
+                                break;
+                        }
+                        break;
+                default:
+                        pr_warn("Tegra30: Unknown SKU %d\n", sku);
+                        tegra_cpu_speedo_id = 0;
+                        tegra_soc_speedo_id = 0;
+                        threshold_index = THRESHOLD_INDEX_0;
+                        break;
+                }
+                break;
+        default:
+                pr_warn("Tegra30: Unknown chip rev %d\n", rev);
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                threshold_index = THRESHOLD_INDEX_0;
+                break;
+        }
+}
+void tegra30_init_speedo_data(void)
+{
+        u32 cpu_speedo_val;
+        u32 core_speedo_val;
+        int i;
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
+        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
+        fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
+        pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
+        pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
+        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
+                if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
+                        break;
+        }
+        tegra_cpu_process_id = i - 1;
+        if (tegra_cpu_process_id == -1) {
+                pr_warn("Tegra30: CPU speedo value %3d out of range",
+                       cpu_speedo_val);
+                tegra_cpu_process_id = 0;
+                tegra_cpu_speedo_id = 1;
+        }
+        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
+                if (core_speedo_val < core_process_speedos[threshold_index][i])
+                        break;
+        }
+        tegra_core_process_id = i - 1;
+        if (tegra_core_process_id == -1) {
+                pr_warn("Tegra30: CORE speedo value %3d out of range",
+                       core_speedo_val);
+                tegra_core_process_id = 0;
+                tegra_soc_speedo_id = 1;
+        }
+        pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
+                tegra_cpu_speedo_id, tegra_soc_speedo_id);
+}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
index 30d063ad2bef..9764d31032b7 100644
--- a/arch/arm/mach-tegra/tegra_cpu_car.h
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -30,6 +30,12 @@
 *      CPU clock un-gate
 * disable_clock:
 *      CPU clock gate
+ * rail_off_ready:
+ *      CPU is ready for rail off
+ * suspend:
+ *      save the clock settings when CPU go into low-power state
+ * resume:
+ *      restore the clock settings when CPU exit low-power state
 */
 struct tegra_cpu_car_ops {
        void (*wait_for_reset)(u32 cpu);
@@ -37,6 +43,11 @@ struct tegra_cpu_car_ops {
        void (*out_of_reset)(u32 cpu);
        void (*enable_clock)(u32 cpu);
        void (*disable_clock)(u32 cpu);
+#ifdef CONFIG_PM_SLEEP
+        bool (*rail_off_ready)(void);
+        void (*suspend)(void);
+        void (*resume)(void);
+#endif
 };
 extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
@@ -81,6 +92,32 @@ static inline void tegra_disable_cpu_clock(u32 cpu)
        tegra_cpu_car_ops->disable_clock(cpu);
 }
+#ifdef CONFIG_PM_SLEEP
+static inline bool tegra_cpu_rail_off_ready(void)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
+                return false;
+        return tegra_cpu_car_ops->rail_off_ready();
+}
+static inline void tegra_cpu_clock_suspend(void)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->suspend))
+                return;
+        tegra_cpu_car_ops->suspend();
+}
+static inline void tegra_cpu_clock_resume(void)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->resume))
+                return;
+        tegra_cpu_car_ops->resume();
+}
+#endif
 void tegra20_cpu_car_ops_init(void);
 void tegra30_cpu_car_ops_init(void);
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index d3b8c8e7368f..e4863f3e9ee7 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -26,16 +26,14 @@
 #include <linux/clocksource.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
 #include "board.h"
-#include "clock.h"
 #define RTC_SECONDS            0x08
 #define RTC_SHADOW_SECONDS     0x0c
@@ -53,8 +51,8 @@
 #define TIMER_PTV 0x0
 #define TIMER_PCR 0x4
-static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
+static void __iomem *timer_reg_base;
-static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
+static void __iomem *rtc_base;
 static struct timespec persistent_ts;
 static u64 persistent_ms, last_persistent_ms;
@@ -158,40 +156,66 @@ static struct irqaction tegra_timer_irq = {
        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
        .handler        = tegra_timer_interrupt,
        .dev_id         = &tegra_clockevent,
-        .irq            = INT_TMR3,
 };
-#ifdef CONFIG_HAVE_ARM_TWD
+static const struct of_device_id timer_match[] __initconst = {
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+        { .compatible = "nvidia,tegra20-timer" },
-                              TEGRA_ARM_PERIF_BASE + 0x600,
+        {}
-                              IRQ_LOCALTIMER);
+};
-static void __init tegra_twd_init(void)
+static const struct of_device_id rtc_match[] __initconst = {
-{
+        { .compatible = "nvidia,tegra20-rtc" },
-        int err = twd_local_timer_register(&twd_local_timer);
+        {}
-        if (err)
+};
-                pr_err("twd_local_timer_register failed %d\n", err);
-}
-#else
-#define tegra_twd_init()        do {} while(0)
-#endif
 static void __init tegra_init_timer(void)
 {
+        struct device_node *np;
        struct clk *clk;
        unsigned long rate;
        int ret;
+        np = of_find_matching_node(NULL, timer_match);
+        if (!np) {
+                pr_err("Failed to find timer DT node\n");
+                BUG();
+        }
+        timer_reg_base = of_iomap(np, 0);
+        if (!timer_reg_base) {
+                pr_err("Can't map timer registers");
+                BUG();
+        }
+        tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
+        if (tegra_timer_irq.irq <= 0) {
+                pr_err("Failed to map timer IRQ\n");
+                BUG();
+        }
        clk = clk_get_sys("timer", NULL);
        if (IS_ERR(clk)) {
-                pr_warn("Unable to get timer clock."
+                pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
-                        " Assuming 12Mhz input clock.\n");
                rate = 12000000;
        } else {
                clk_prepare_enable(clk);
                rate = clk_get_rate(clk);
        }
+        of_node_put(np);
+        np = of_find_matching_node(NULL, rtc_match);
+        if (!np) {
+                pr_err("Failed to find RTC DT node\n");
+                BUG();
+        }
+        rtc_base = of_iomap(np, 0);
+        if (!rtc_base) {
+                pr_err("Can't map RTC registers");
+                BUG();
+        }
        /*
         * rtc registers are used by read_persistent_clock, keep the rtc clock
         * enabled
@@ -202,6 +226,8 @@ static void __init tegra_init_timer(void)
        else
                clk_prepare_enable(clk);
+        of_node_put(np);
        switch (rate) {
        case 12000000:
                timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -223,13 +249,13 @@ static void __init tegra_init_timer(void)
        if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
                "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
-                printk(KERN_ERR "Failed to register clocksource\n");
+                pr_err("Failed to register clocksource\n");
                BUG();
        }
        ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
        if (ret) {
-                printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
+                pr_err("Failed to register timer IRQ: %d\n", ret);
                BUG();
        }
@@ -241,7 +267,9 @@ static void __init tegra_init_timer(void)
        tegra_clockevent.cpumask = cpu_all_mask;
        tegra_clockevent.irq = tegra_timer_irq.irq;
        clockevents_register_device(&tegra_clockevent);
-        tegra_twd_init();
+#ifdef CONFIG_HAVE_ARM_TWD
+        twd_local_timer_of_register();
+#endif
        register_persistent_clock(NULL, tegra_read_persistent_clock);
 }
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index b8efac4daed8..12f3994c43db 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -82,8 +82,6 @@ static struct map_desc u300_io_desc[] __initdata = {
 static void __init u300_map_io(void)
 {
        iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
-        /* We enable a real big DMA buffer if need be. */
-        init_consistent_dma_size(SZ_4M);
 }
 /*
@@ -1445,8 +1443,6 @@ static struct platform_device pinctrl_device = {
 static struct u300_gpio_platform u300_gpio_plat = {
        .ports = 7,
        .gpio_base = 0,
-        .gpio_irq_base = IRQ_U300_GPIO_BASE,
-        .pinctrl_device = &pinctrl_device,
 };
 static struct platform_device gpio_device = {
@@ -1590,6 +1586,7 @@ static struct platform_device *platform_devs[] __initdata = {
        &i2c1_device,
        &keypad_device,
        &rtc_device,
+        &pinctrl_device,
        &gpio_device,
        &nand_device,
        &wdog_device,
@@ -1804,7 +1801,7 @@ MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
        .atag_offset    = 0x100,
        .map_io         = u300_map_io,
-        .nr_irqs        = NR_IRQS_U300,
+        .nr_irqs        = 0,
        .init_irq       = u300_init_irq,
        .handle_irq     = vic_handle_irq,
        .timer          = &u300_timer,
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index e27425a63fa1..21d5e76a6cd3 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -12,79 +12,69 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
-#define IRQ_U300_INTCON0_START          1
+#define IRQ_U300_INTCON0_START          32
-#define IRQ_U300_INTCON1_START          33
+#define IRQ_U300_INTCON1_START          64
 /* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               1
+#define IRQ_U300_IRQ0_EXT               32
-#define IRQ_U300_IRQ1_EXT               2
+#define IRQ_U300_IRQ1_EXT               33
-#define IRQ_U300_DMA                    3
+#define IRQ_U300_DMA                    34
-#define IRQ_U300_VIDEO_ENC_0            4
+#define IRQ_U300_VIDEO_ENC_0            35
-#define IRQ_U300_VIDEO_ENC_1            5
+#define IRQ_U300_VIDEO_ENC_1            36
-#define IRQ_U300_AAIF_RX                6
+#define IRQ_U300_AAIF_RX                37
-#define IRQ_U300_AAIF_TX                7
+#define IRQ_U300_AAIF_TX                38
-#define IRQ_U300_AAIF_VGPIO             8
+#define IRQ_U300_AAIF_VGPIO             39
-#define IRQ_U300_AAIF_WAKEUP            9
+#define IRQ_U300_AAIF_WAKEUP            40
-#define IRQ_U300_PCM_I2S0_FRAME         10
+#define IRQ_U300_PCM_I2S0_FRAME         41
-#define IRQ_U300_PCM_I2S0_FIFO          11
+#define IRQ_U300_PCM_I2S0_FIFO          42
-#define IRQ_U300_PCM_I2S1_FRAME         12
+#define IRQ_U300_PCM_I2S1_FRAME         43
-#define IRQ_U300_PCM_I2S1_FIFO          13
+#define IRQ_U300_PCM_I2S1_FIFO          44
-#define IRQ_U300_XGAM_GAMCON            14
+#define IRQ_U300_XGAM_GAMCON            45
-#define IRQ_U300_XGAM_CDI               15
+#define IRQ_U300_XGAM_CDI               46
-#define IRQ_U300_XGAM_CDICON            16
+#define IRQ_U300_XGAM_CDICON            47
-#define IRQ_U300_XGAM_PDI               18
+#define IRQ_U300_XGAM_PDI               49
-#define IRQ_U300_XGAM_PDICON            19
+#define IRQ_U300_XGAM_PDICON            50
-#define IRQ_U300_XGAM_GAMEACC           20
+#define IRQ_U300_XGAM_GAMEACC           51
-#define IRQ_U300_XGAM_MCIDCT            21
+#define IRQ_U300_XGAM_MCIDCT            52
-#define IRQ_U300_APEX                   22
+#define IRQ_U300_APEX                   53
-#define IRQ_U300_UART0                  23
+#define IRQ_U300_UART0                  54
-#define IRQ_U300_SPI                    24
+#define IRQ_U300_SPI                    55
-#define IRQ_U300_TIMER_APP_OS           25
+#define IRQ_U300_TIMER_APP_OS           56
-#define IRQ_U300_TIMER_APP_DD           26
+#define IRQ_U300_TIMER_APP_DD           57
-#define IRQ_U300_TIMER_APP_GP1          27
+#define IRQ_U300_TIMER_APP_GP1          58
-#define IRQ_U300_TIMER_APP_GP2          28
+#define IRQ_U300_TIMER_APP_GP2          59
-#define IRQ_U300_TIMER_OS               29
+#define IRQ_U300_TIMER_OS               60
-#define IRQ_U300_TIMER_MS               30
+#define IRQ_U300_TIMER_MS               61
-#define IRQ_U300_KEYPAD_KEYBF           31
+#define IRQ_U300_KEYPAD_KEYBF           62
-#define IRQ_U300_KEYPAD_KEYBR           32
+#define IRQ_U300_KEYPAD_KEYBR           63
 /* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             33
+#define IRQ_U300_GPIO_PORT0             64
-#define IRQ_U300_GPIO_PORT1             34
+#define IRQ_U300_GPIO_PORT1             65
-#define IRQ_U300_GPIO_PORT2             35
+#define IRQ_U300_GPIO_PORT2             66
 /* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   36
+#define IRQ_U300_WDOG                   67
-#define IRQ_U300_EVHIST                 37
+#define IRQ_U300_EVHIST                 68
-#define IRQ_U300_MSPRO                  38
+#define IRQ_U300_MSPRO                  69
-#define IRQ_U300_MMCSD_MCIINTR0         39
+#define IRQ_U300_MMCSD_MCIINTR0         70
-#define IRQ_U300_MMCSD_MCIINTR1         40
+#define IRQ_U300_MMCSD_MCIINTR1         71
-#define IRQ_U300_I2C0                   41
+#define IRQ_U300_I2C0                   72
-#define IRQ_U300_I2C1                   42
+#define IRQ_U300_I2C1                   73
-#define IRQ_U300_RTC                    43
+#define IRQ_U300_RTC                    74
-#define IRQ_U300_NFIF                   44
+#define IRQ_U300_NFIF                   75
-#define IRQ_U300_NFIF2                  45
+#define IRQ_U300_NFIF2                  76
 /* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0                 46
+#define IRQ_U300_ISP_F0                 77
-#define IRQ_U300_ISP_F1                 47
+#define IRQ_U300_ISP_F1                 78
-#define IRQ_U300_ISP_F2                 48
+#define IRQ_U300_ISP_F2                 79
-#define IRQ_U300_ISP_F3                 49
+#define IRQ_U300_ISP_F3                 80
-#define IRQ_U300_ISP_F4                 50
+#define IRQ_U300_ISP_F4                 81
-#define IRQ_U300_GPIO_PORT3             51
+#define IRQ_U300_GPIO_PORT3             82
-#define IRQ_U300_SYSCON_PLL_LOCK        52
+#define IRQ_U300_SYSCON_PLL_LOCK        83
-#define IRQ_U300_UART1                  53
+#define IRQ_U300_UART1                  84
-#define IRQ_U300_GPIO_PORT4             54
+#define IRQ_U300_GPIO_PORT4             85
-#define IRQ_U300_GPIO_PORT5             55
+#define IRQ_U300_GPIO_PORT5             86
-#define IRQ_U300_GPIO_PORT6             56
+#define IRQ_U300_GPIO_PORT6             87
-#define U300_VIC_IRQS_END               57
+#define U300_VIC_IRQS_END               88
-/* Maximum 8*7 GPIO lines */
-#ifdef CONFIG_PINCTRL_COH901
-#define IRQ_U300_GPIO_BASE              (U300_VIC_IRQS_END)
-#define IRQ_U300_GPIO_END               (IRQ_U300_GPIO_BASE + 56)
-#else
-#define IRQ_U300_GPIO_END               (U300_VIC_IRQS_END)
-#endif
-#define NR_IRQS_U300                    (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 #endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index e8c3f0d70ca6..5dea90636d94 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -7,8 +7,8 @@ config UX500_SOC_COMMON
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
        select CACHE_L2X0
+        select CLKSRC_NOMADIK_MTU
        select COMMON_CLK
-        select HAS_MTU
        select PINCTRL
        select PINCTRL_NOMADIK
        select PL310_ERRATA_753970 if CACHE_PL310
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 070629a95625..7209db7cdc72 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,10 +7,8 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
-#include <plat/gpio-nomadik.h>
+#include <linux/platform_data/dma-ste-dma40.h>
-#include <plat/pincfg.h>
-#include <plat/ste_dma40.h>
 #include <mach/devices.h>
 #include <mach/hardware.h>
@@ -150,15 +148,6 @@ static struct platform_device snd_soc_mop500 = {
        },
 };
-/* Platform device for Ux500-PCM */
-static struct platform_device ux500_pcm = {
-                .name = "ux500-pcm",
-                .id = 0,
-                .dev = {
-                        .platform_data = NULL,
-                },
-};
 struct msp_i2s_platform_data msp2_platform_data = {
        .id = MSP_I2S_2,
        .msp_i2s_dma_rx = &msp2_dma_rx,
@@ -186,10 +175,3 @@ void mop500_audio_init(struct device *parent)
        db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
                           &msp3_platform_data);
 }
-/* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_audio_init(struct device *parent)
-{
-        pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
-        platform_device_register(&ux500_pcm);
-}
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index a267c6d30e37..0a3f30df1eb8 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -9,10 +9,9 @@
 #include <linux/bug.h>
 #include <linux/string.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
 #include <asm/mach-types.h>
-#include <plat/pincfg.h>
-#include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
@@ -34,8 +33,6 @@ BIAS(in_nopull, PIN_INPUT_NOPULL);
 BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
 BIAS(in_pu, PIN_INPUT_PULLUP);
 BIAS(in_pd, PIN_INPUT_PULLDOWN);
-BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
-BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
 BIAS(out_hi, PIN_OUTPUT_HIGH);
 BIAS(out_lo, PIN_OUTPUT_LOW);
 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
@@ -47,14 +44,34 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
 /* Sleep modes */
-BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
-BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
+        PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
-BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
-BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
+BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
+        PIN_SLPM_PDIS_ENABLED);
+BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
+        PIN_SLPM_PDIS_DISABLED);
+BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
+        PIN_SLPM_PDIS_DISABLED);
 /* We use these to define hog settings that are always done on boot */
 #define DB8500_MUX_HOG(group,func) \
@@ -70,13 +87,16 @@ BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_NOPULL|PIN_S
        PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
 #define DB8500_PIN(pin,conf,dev) \
        PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
+#define DB8500_PIN_IDLE(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
+        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
                            pin, conf)
+#define DB8500_PIN_SLEEP(pin, conf, dev) \
-#define DB8500_PIN_SLEEP(pin,conf,dev) \
        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
                            pin, conf)
+#define DB8500_MUX_STATE(group, func, dev, state) \
+        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
+#define DB8500_PIN_STATE(pin, conf, dev, state) \
+        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
 /* Pin control settings */
 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
@@ -113,7 +133,7 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         * UART0, we do not mux in u0 here.
         * uart-0 pins gpio configuration should be kept intact to prevent
         * a glitch in tx line when the tty dev is opened. Later these pins
-         * are configured to uart mop500_pins_uart0
+         * are configured by uart driver
         */
        DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
        DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
@@ -124,12 +144,13 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         * TODO: is this used on U8500 variants and Snowball really?
         * The setting on GPIO31 conflicts with magnetometer use on hrefv60
         */
-        DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
+        /* default state for UART2 */
-        DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
+        DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
-        DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
+        DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
-        DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
+        DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
-        DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
+        /* Sleep state for UART2 */
-        DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
+        DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
+        DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
        /*
         * The following pin sets were known as "runtime pins" before being
         * converted to the pinctrl model. Here we model them as "default"
@@ -141,11 +162,18 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
        DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
        DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
-        /* UART0 sleep state */
+        /* Sleep state for UART0 */
        DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
        DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
        DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
        DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
+        /* Mux in UART1 after initialization */
+        DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
+        DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
+        DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
+        /* Sleep state for UART1 */
+        DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
+        DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
        /* MSP1 for ALSA codec */
        DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
        DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
@@ -162,7 +190,10 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
        DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
        /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
-        DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
+        DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
+        DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
+        /* LCD VSI1 sleep state */
+        DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
        /* Mux in i2c0 block, default state */
        DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
        /* i2c0 sleep state */
@@ -195,6 +226,18 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
        DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
        DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
+        /* SDI0 sleep state */
+        DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
+        DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
        /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
        DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
        DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
@@ -204,6 +247,15 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
        DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
        DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
+        /* SDI1 sleep state */
+        DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
+        DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
+        DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
+        DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
+        DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
        /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
        DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
        DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
@@ -217,6 +269,19 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
        DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
        DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
+        /* SDI2 sleep state */
+        DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
+        DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
+        DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
+        DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
+        DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
+        DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
+        DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
+        DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
+        DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
        /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
        DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
        DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
@@ -230,6 +295,19 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
        DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
        DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
+        /*SDI4 sleep state */
+        DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
+        DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
+        DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
+        DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
+        DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
+        DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
+        DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
+        DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
+        DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
        /* Mux in USB pins, drive STP high */
        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
@@ -239,10 +317,232 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
        DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
        DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
+        /* SPI2 idle state */
+        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
        /* SPI2 sleep state */
+        DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
+        /* ske default state */
+        DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
+        DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
+        DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
+        DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
+        DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
+        DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
+        DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
+        DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
+        DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
+        DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
+        DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
+        DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
+        DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
+        DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
+        DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
+        DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
+        DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
+        /* ske sleep state */
+        DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
+        DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
+        DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
+        DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
+        DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
+        DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
+        DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
+        DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
+        DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
+        DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
+        DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
+        DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
+        DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
+        DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
+        DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
+        DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
+        /* STM APE pins states */
+        DB8500_MUX_STATE("stmape_c_1", "stmape",
+                "stm", "ape_mipi34"),
+        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
+                "stm", "ape_mipi34"), /* clk */
+        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
+                "stm", "ape_mipi34"), /* dat3 */
+        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
+                "stm", "ape_mipi34"), /* dat2 */
+        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
+                "stm", "ape_mipi34"), /* dat1 */
+        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
+                "stm", "ape_mipi34"), /* dat0 */
+        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
+                "stm", "ape_mipi34_sleep"), /* clk */
+        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
+                "stm", "ape_mipi34_sleep"), /* dat3 */
+        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
+                "stm", "ape_mipi34_sleep"), /* dat2 */
+        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
+                "stm", "ape_mipi34_sleep"), /* dat1 */
+        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
+                "stm", "ape_mipi34_sleep"), /* dat0 */
+        DB8500_MUX_STATE("stmape_oc1_1", "stmape",
+                "stm", "ape_microsd"),
+        DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
+                "stm", "ape_microsd"), /* clk */
+        DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
+                "stm", "ape_microsd"), /* dat0 */
+        DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
+                "stm", "ape_microsd"), /* dat1 */
+        DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
+                "stm", "ape_microsd"), /* dat2 */
+        DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
+                "stm", "ape_microsd"), /* dat3 */
+        DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
+                "stm", "ape_microsd_sleep"), /* clk */
+        DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
+                "stm", "ape_microsd_sleep"), /* dat0 */
+        DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
+                "stm", "ape_microsd_sleep"), /* dat1 */
+        DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
+                "stm", "ape_microsd_sleep"), /* dat2 */
+        DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
+                "stm", "ape_microsd_sleep"), /* dat3 */
+        /*  STM Modem pins states */
+        DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
+                "stm", "mod_mipi34"),
+        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
+                "stm", "mod_mipi34"),
+        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
+                "stm", "mod_mipi34"),
+        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
+                "stm", "mod_mipi34"), /* clk */
+        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
+                "stm", "mod_mipi34"), /* dat3 */
+        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
+                "stm", "mod_mipi34"), /* dat2 */
+        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
+                "stm", "mod_mipi34"), /* dat1 */
+        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
+                "stm", "mod_mipi34"), /* dat0 */
+        DB8500_PIN_STATE("GPIO75_H2", in_pu,
+                "stm", "mod_mipi34"), /* uartmod rx */
+        DB8500_PIN_STATE("GPIO76_J2", out_lo,
+                "stm", "mod_mipi34"), /* uartmod tx */
+        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_sleep"), /* clk */
+        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_sleep"), /* dat3 */
+        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_sleep"), /* dat2 */
+        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_sleep"), /* dat1 */
+        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_sleep"), /* dat0 */
+        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
+                "stm", "mod_mipi34_sleep"), /* uartmod rx */
+        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
+                "stm", "mod_mipi34_sleep"), /* uartmod tx */
+        DB8500_MUX_STATE("stmmod_b_1", "stmmod",
+                "stm", "mod_microsd"),
+        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
+                "stm", "mod_microsd"),
+        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
+                "stm", "mod_microsd"),
+        DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
+                "stm", "mod_microsd"), /* clk */
+        DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
+                "stm", "mod_microsd"), /* dat0 */
+        DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
+                "stm", "mod_microsd"), /* dat1 */
+        DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
+                "stm", "mod_microsd"), /* dat2 */
+        DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
+                "stm", "mod_microsd"), /* dat3 */
+        DB8500_PIN_STATE("GPIO75_H2", in_pu,
+                "stm", "mod_microsd"), /* uartmod rx */
+        DB8500_PIN_STATE("GPIO76_J2", out_lo,
+                "stm", "mod_microsd"), /* uartmod tx */
+        DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
+                "stm", "mod_microsd_sleep"), /* clk */
+        DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
+                "stm", "mod_microsd_sleep"), /* dat0 */
+        DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
+                "stm", "mod_microsd_sleep"), /* dat1 */
+        DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
+                "stm", "mod_microsd_sleep"), /* dat2 */
+        DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
+                "stm", "mod_microsd_sleep"), /* dat3 */
+        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
+                "stm", "mod_microsd_sleep"), /* uartmod rx */
+        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
+                "stm", "mod_microsd_sleep"), /* uartmod tx */
+        /*  STM dual Modem/APE pins state */
+        DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
+                "stm", "mod_mipi34_ape_mipi60"),
+        DB8500_MUX_STATE("stmape_c_2", "stmape",
+                "stm", "mod_mipi34_ape_mipi60"),
+        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
+                "stm", "mod_mipi34_ape_mipi60"),
+        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
+                "stm", "mod_mipi34_ape_mipi60"),
+        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* clk */
+        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
+        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
+        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
+        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
+        DB8500_PIN_STATE("GPIO75_H2", in_pu,
+                "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
+        DB8500_PIN_STATE("GPIO76_J2", out_lo,
+                "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
+        DB8500_PIN_STATE("GPIO155_C19", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* clk */
+        DB8500_PIN_STATE("GPIO156_C17", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
+        DB8500_PIN_STATE("GPIO157_A18", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
+        DB8500_PIN_STATE("GPIO158_C18", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
+        DB8500_PIN_STATE("GPIO159_B19", in_nopull,
+                "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
+        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
+        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
+        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
+        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
+        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
+        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
+        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
+        DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
+        DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
+        DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
+        DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
+        DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
+                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 };
 /*
@@ -268,32 +568,48 @@ static struct pinctrl_map __initdata mop500_pinmap[] = {
        DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
        /* Mux in UART1 and set the pull-ups */
        DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
-        DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
        DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
        DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
-        DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
-        DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
        /*
         * Runtime stuff: make it possible to mux in the SKE keypad
         * and bias the pins
         */
-        DB8500_MUX("kp_a_2", "kp", "ske"),
+        /* ske default state */
-        DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
+        DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
-        DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
+        DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
+        DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
+        DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
+        DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
+        DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
+        DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
+        DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
+        DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
+        DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
+        DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
+        DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
+        DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
+        DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
+        DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
+        DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
+        DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
+        /* ske sleep state */
+        DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
+        DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
+        DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
+        DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
+        DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
+        DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
+        DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
+        DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
+        DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
+        DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
+        DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
+        DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
+        DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
+        DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
+        DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
+        DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
        /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
        DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
        DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
@@ -396,28 +712,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = {
        DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
        DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
        DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
-        /*
-         * Make it possible to mux in the SKE keypad and bias the pins
-         * FIXME: what's the point with this on HREFv60? KP/SKE is already
-         * muxed in at another place! Enabling this will bork.
-         */
-        DB8500_MUX("kp_a_2", "kp", "ske"),
-        DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
-        DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
-        DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
-        DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
-        DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
-        DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
-        DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
-        DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
-        DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
-        DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
-        DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
-        DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
-        DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
-        DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
-        DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
-        DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
 };
 static struct pinctrl_map __initdata u9500_pinmap[] = {
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 9c8e4a9e83ee..051b62c27102 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -11,9 +11,9 @@
 #include <linux/amba/mmci.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/dma-ste-dma40.h>
 #include <asm/mach-types.h>
-#include <plat/ste_dma40.h>
 #include <mach/devices.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c
index 8c979770d872..564f57d5d8a7 100644
--- a/arch/arm/mach-ux500/board-mop500-stuib.c
+++ b/arch/arm/mach-ux500/board-mop500-stuib.c
@@ -162,18 +162,6 @@ static struct bu21013_platform_device tsc_plat_device = {
        .y_flip = true,
 };
-static struct bu21013_platform_device tsc_plat2_device = {
-        .cs_en = bu21013_gpio_board_init,
-        .cs_dis = bu21013_gpio_board_exit,
-        .irq_read_val = bu21013_read_pin_val,
-        .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
-        .touch_x_max = TOUCH_XMAX,
-        .touch_y_max = TOUCH_YMAX,
-        .ext_clk = false,
-        .x_flip = false,
-        .y_flip = true,
-};
 static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
        {
                I2C_BOARD_INFO("bu21013_tp", 0x5C),
@@ -181,21 +169,17 @@ static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
        },
        {
                I2C_BOARD_INFO("bu21013_tp", 0x5D),
-                .platform_data = &tsc_plat2_device,
+                .platform_data = &tsc_plat_device,
        },
 };
 void __init mop500_stuib_init(void)
 {
-        if (machine_is_hrefv60()) {
+        if (machine_is_hrefv60())
                tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
-                tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
+        else
-        } else {
                tsc_plat_device.cs_pin = GPIO_BU21013_CS;
-                tsc_plat2_device.cs_pin = GPIO_BU21013_CS;
-        }
        mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
                        ARRAY_SIZE(mop500_i2c0_devices_stuib));
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 416d436111f2..d453522edb0d 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2008-2009 ST-Ericsson
+ * Copyright (C) 2008-2012 ST-Ericsson
 *
 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
 *
@@ -16,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/platform_data/i2c-nomadik.h>
+#include <linux/platform_data/db8500_thermal.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
@@ -33,18 +33,15 @@
 #include <linux/smsc911x.h>
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
 #include <linux/leds.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
+#include <linux/platform_data/dma-ste-dma40.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
-#include <plat/ste_dma40.h>
-#include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
@@ -229,6 +226,67 @@ static struct ab8500_platform_data ab8500_platdata = {
 };
 /*
+ * Thermal Sensor
+ */
+static struct resource db8500_thsens_resources[] = {
+        {
+                .name = "IRQ_HOTMON_LOW",
+                .start  = IRQ_PRCMU_HOTMON_LOW,
+                .end    = IRQ_PRCMU_HOTMON_LOW,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name = "IRQ_HOTMON_HIGH",
+                .start  = IRQ_PRCMU_HOTMON_HIGH,
+                .end    = IRQ_PRCMU_HOTMON_HIGH,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct db8500_thsens_platform_data db8500_thsens_data = {
+        .trip_points[0] = {
+                .temp = 70000,
+                .type = THERMAL_TRIP_ACTIVE,
+                .cdev_name = {
+                        [0] = "thermal-cpufreq-0",
+                },
+        },
+        .trip_points[1] = {
+                .temp = 75000,
+                .type = THERMAL_TRIP_ACTIVE,
+                .cdev_name = {
+                        [0] = "thermal-cpufreq-0",
+                },
+        },
+        .trip_points[2] = {
+                .temp = 80000,
+                .type = THERMAL_TRIP_ACTIVE,
+                .cdev_name = {
+                        [0] = "thermal-cpufreq-0",
+                },
+        },
+        .trip_points[3] = {
+                .temp = 85000,
+                .type = THERMAL_TRIP_CRITICAL,
+        },
+        .num_trips = 4,
+};
+static struct platform_device u8500_thsens_device = {
+        .name           = "db8500-thermal",
+        .resource       = db8500_thsens_resources,
+        .num_resources  = ARRAY_SIZE(db8500_thsens_resources),
+        .dev    = {
+                .platform_data  = &db8500_thsens_data,
+        },
+};
+static struct platform_device u8500_cpufreq_cooling_device = {
+        .name           = "db8500-cpufreq-cooling",
+};
+/*
 * TPS61052
 */
@@ -464,7 +522,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
 };
 #endif
-static struct pl022_ssp_controller ssp0_plat = {
+struct pl022_ssp_controller ssp0_plat = {
        .bus_id = 0,
 #ifdef CONFIG_STE_DMA40
        .enable_dma = 1,
@@ -541,7 +599,7 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
 };
 #endif
-static struct amba_pl011_data uart0_plat = {
+struct amba_pl011_data uart0_plat = {
 #ifdef CONFIG_STE_DMA40
        .dma_filter = stedma40_filter,
        .dma_rx_param = &uart0_dma_cfg_rx,
@@ -549,7 +607,7 @@ static struct amba_pl011_data uart0_plat = {
 #endif
 };
-static struct amba_pl011_data uart1_plat = {
+struct amba_pl011_data uart1_plat = {
 #ifdef CONFIG_STE_DMA40
        .dma_filter = stedma40_filter,
        .dma_rx_param = &uart1_dma_cfg_rx,
@@ -557,7 +615,7 @@ static struct amba_pl011_data uart1_plat = {
 #endif
 };
-static struct amba_pl011_data uart2_plat = {
+struct amba_pl011_data uart2_plat = {
 #ifdef CONFIG_STE_DMA40
        .dma_filter = stedma40_filter,
        .dma_rx_param = &uart2_dma_cfg_rx,
@@ -583,6 +641,8 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
        &snowball_key_dev,
        &snowball_sbnet_dev,
        &snowball_gpio_en_3v3_regulator_dev,
+        &u8500_thsens_device,
+        &u8500_cpufreq_cooling_device,
 };
 static void __init mop500_init_machine(void)
@@ -618,8 +678,6 @@ static void __init mop500_init_machine(void)
        /* This board has full regulator constraints */
        regulator_has_full_constraints();
-        mop500_uib_init();
 }
 static void __init snowball_init_machine(void)
@@ -684,8 +742,6 @@ static void __init hrefv60_init_machine(void)
        /* This board has full regulator constraints */
        regulator_has_full_constraints();
-        mop500_uib_init();
 }
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
@@ -701,155 +757,35 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
        .init_late      = ux500_init_late,
 MACHINE_END
-MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
+MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
        .atag_offset    = 0x100,
-        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        .timer          = &ux500_timer,
        .handle_irq     = gic_handle_irq,
-        .init_machine   = hrefv60_init_machine,
+        .init_machine   = mop500_init_machine,
        .init_late      = ux500_init_late,
 MACHINE_END
-MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
+MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
        .atag_offset    = 0x100,
        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
-        /* we re-use nomadik timer here */
        .timer          = &ux500_timer,
        .handle_irq     = gic_handle_irq,
-        .init_machine   = snowball_init_machine,
+        .init_machine   = hrefv60_init_machine,
        .init_late      = ux500_init_late,
 MACHINE_END
-#ifdef CONFIG_MACH_UX500_DT
+MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
+        .atag_offset    = 0x100,
-struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
-        /* Requires call-back bindings. */
-        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
-        /* Requires DMA and call-back bindings. */
-        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
-        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
-        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
-        /* Requires DMA bindings. */
-        OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
-        OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
-        OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
-        OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
-        OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
-        /* Requires clock name bindings. */
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
-        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
-        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
-        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
-        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
-        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
-        /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
-        /* Requires clock name and DMA bindings. */
-        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
-                "ux500-msp-i2s.0", &msp0_platform_data),
-        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
-                "ux500-msp-i2s.1", &msp1_platform_data),
-        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
-                "ux500-msp-i2s.2", &msp2_platform_data),
-        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
-                "ux500-msp-i2s.3", &msp3_platform_data),
-        {},
-};
-static const struct of_device_id u8500_local_bus_nodes[] = {
-        /* only create devices below soc node */
-        { .compatible = "stericsson,db8500", },
-        { .compatible = "stericsson,db8500-prcmu", },
-        { .compatible = "simple-bus"},
-        { },
-};
-static void __init u8500_init_machine(void)
-{
-        struct device *parent = NULL;
-        int i2c0_devs;
-        int i;
-        /* Pinmaps must be in place before devices register */
-        if (of_machine_is_compatible("st-ericsson,mop500"))
-                mop500_pinmaps_init();
-        else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
-                snowball_pinmaps_init();
-        else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
-                hrefv60_pinmaps_init();
-        parent = u8500_of_init_devices();
-        for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
-                mop500_platform_devs[i]->dev.parent = parent;
-        /* automatically probe child nodes of db8500 device */
-        of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
-        if (of_machine_is_compatible("st-ericsson,mop500")) {
-                mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
-                platform_add_devices(mop500_platform_devs,
-                                ARRAY_SIZE(mop500_platform_devs));
-                mop500_sdi_init(parent);
-                mop500_audio_init(parent);
-                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-                i2c_register_board_info(2, mop500_i2c2_devices,
-                                        ARRAY_SIZE(mop500_i2c2_devices));
-                mop500_uib_init();
-        } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                mop500_of_audio_init(parent);
-        } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
-                /*
-                 * The HREFv60 board removed a GPIO expander and routed
-                 * all these GPIO pins to the internal GPIO controller
-                 * instead.
-                 */
-                mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
-                platform_add_devices(mop500_platform_devs,
-                                ARRAY_SIZE(mop500_platform_devs));
-                mop500_uib_init();
-        }
-        /* This board has full regulator constraints */
-        regulator_has_full_constraints();
-}
-static const char * u8500_dt_board_compat[] = {
-        "calaosystems,snowball-a9500",
-        "st-ericsson,hrefv60+",
-        "st-ericsson,u8500",
-        "st-ericsson,mop500",
-        NULL,
-};
-DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
        .timer          = &ux500_timer,
        .handle_irq     = gic_handle_irq,
-        .init_machine   = u8500_init_machine,
+        .init_machine   = snowball_init_machine,
-        .init_late      = ux500_init_late,
+        .init_late      = NULL,
-        .dt_compat      = u8500_dt_board_compat,
 MACHINE_END
-#endif
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index aca39a68712a..eaa605f5d90d 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -89,6 +89,10 @@ extern struct msp_i2s_platform_data msp1_platform_data;
 extern struct msp_i2s_platform_data msp2_platform_data;
 extern struct msp_i2s_platform_data msp3_platform_data;
 extern struct arm_pmu_platdata db8500_pmu_platdata;
+extern struct amba_pl011_data uart0_plat;
+extern struct amba_pl011_data uart1_plat;
+extern struct amba_pl011_data uart2_plat;
+extern struct pl022_ssp_controller ssp0_plat;
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
@@ -100,14 +104,8 @@ void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
 void mop500_audio_init(struct device *parent);
-/* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_audio_init(struct device *parent);
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
                unsigned n);
-/* TODO: Once all pieces are DT:ed, remove completely. */
-struct device * __init u8500_of_init_devices(void);
 #endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index bcdfe6b1d453..db0bb75e2c76 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -17,18 +17,27 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mfd/abx500/ab8500.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/regulator/machine.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
+#include <linux/random.h>
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
-#include <plat/gpio-nomadik.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
-#include <linux/platform_data/usb-musb-ux500.h>
 #include <mach/db8500-regs.h>
+#include <mach/irqs.h>
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
+#include "board-mop500.h"
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -158,7 +167,7 @@ static void __init db8500_add_gpios(struct device *parent)
        dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
                         IRQ_DB8500_GPIO0, &pdata);
-        dbx500_add_pinctrl(parent, "pinctrl-db8500");
+        dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 }
 static int usb_db8500_rx_dma_cfg[] = {
@@ -187,6 +196,8 @@ static const char *db8500_read_soc_id(void)
 {
        void __iomem *uid = __io_address(U8500_BB_UID_BASE);
+        /* Throw these device-specific numbers into the entropy pool */
+        add_device_randomness(uid, 0x14);
        return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
                         readl((u32 *)uid+1),
                         readl((u32 *)uid+1), readl((u32 *)uid+2),
@@ -214,9 +225,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
        db8500_add_gpios(parent);
        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
-        platform_device_register_data(parent,
-                "cpufreq-u8500", -1, NULL, 0);
        for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
                platform_devs[i]->dev.parent = parent;
@@ -227,18 +235,15 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
        return parent;
 }
+#ifdef CONFIG_MACH_UX500_DT
 /* TODO: Once all pieces are DT:ed, remove completely. */
-struct device * __init u8500_of_init_devices(void)
+static struct device * __init u8500_of_init_devices(void)
 {
-        struct device *parent;
+        struct device *parent = db8500_soc_device_init();
-        parent = db8500_soc_device_init();
        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
-        platform_device_register_data(parent,
-                "cpufreq-u8500", -1, NULL, 0);
        u8500_dma40_device.dev.parent = parent;
        /*
@@ -251,3 +256,95 @@ struct device * __init u8500_of_init_devices(void)
        return parent;
 }
+static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+        /* Requires call-back bindings. */
+        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
+        /* Requires DMA bindings. */
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+        OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
+        /* Requires clock name bindings. */
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+        /* Requires device name bindings. */
+        OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
+        /* Requires clock name and DMA bindings. */
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
+                "ux500-msp-i2s.0", &msp0_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
+                "ux500-msp-i2s.1", &msp1_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
+                "ux500-msp-i2s.2", &msp2_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
+                "ux500-msp-i2s.3", &msp3_platform_data),
+        {},
+};
+static const struct of_device_id u8500_local_bus_nodes[] = {
+        /* only create devices below soc node */
+        { .compatible = "stericsson,db8500", },
+        { .compatible = "stericsson,db8500-prcmu", },
+        { .compatible = "simple-bus"},
+        { },
+};
+static void __init u8500_init_machine(void)
+{
+        struct device *parent = NULL;
+        /* Pinmaps must be in place before devices register */
+        if (of_machine_is_compatible("st-ericsson,mop500"))
+                mop500_pinmaps_init();
+        else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
+                snowball_pinmaps_init();
+        else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
+                hrefv60_pinmaps_init();
+        else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
+                /* TODO: Add pinmaps for ccu9540 board. */
+        /* TODO: Export SoC, USB, cpu-freq and DMA40 */
+        parent = u8500_of_init_devices();
+        /* automatically probe child nodes of db8500 device */
+        of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
+}
+static const char * stericsson_dt_platform_compat[] = {
+        "st-ericsson,u8500",
+        "st-ericsson,u8540",
+        "st-ericsson,u9500",
+        "st-ericsson,u9540",
+        NULL,
+};
+DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
+        .smp            = smp_ops(ux500_smp_ops),
+        .map_io         = u8500_map_io,
+        .init_irq       = ux500_init_irq,
+        /* we re-use nomadik timer here */
+        .timer          = &ux500_timer,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = u8500_init_machine,
+        .init_late      = NULL,
+        .dt_compat      = stericsson_dt_platform_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 1f3fbc2bb776..721e7b4275f3 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -26,6 +26,8 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
+#include "board-mop500.h"
 void __iomem *_PRCMU_BASE;
 /*
@@ -82,6 +84,7 @@ void __init ux500_init_irq(void)
 void __init ux500_init_late(void)
 {
+        mop500_uib_init();
 }
 static const char * __init ux500_get_machine(void)
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index dfdd4a54668d..16b5f71e6974 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -11,10 +11,10 @@
 #include <linux/irq.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/pinctrl-nomadik.h>
-#include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 #include "devices-common.h"
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 7fbf0ba336e1..96fa4ac89e2e 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -129,12 +129,18 @@ void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
                      int irq, struct nmk_gpio_platform_data *pdata);
 static inline void
-dbx500_add_pinctrl(struct device *parent, const char *name)
+dbx500_add_pinctrl(struct device *parent, const char *name,
+                   resource_size_t base)
 {
+        struct resource res[] = {
+                DEFINE_RES_MEM(base, SZ_8K),
+        };
        struct platform_device_info pdevinfo = {
                .parent = parent,
                .name = name,
                .id = -1,
+                .res = res,
+                .num_res = ARRAY_SIZE(res),
        };
        platform_device_register_full(&pdevinfo);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 91754a8a0d49..318d49020894 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -12,11 +12,11 @@
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
+#include <linux/platform_data/dma-ste-dma40.h>
-#include <plat/ste_dma40.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
+#include <mach/irqs.h>
 #include "ste-dma40-db8500.h"
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 3c8010f4fb3f..4b24c9992654 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -8,6 +8,7 @@
 #ifndef __DEVICES_DB8500_H
 #define __DEVICES_DB8500_H
+#include <mach/irqs.h>
 #include "devices-common.h"
 struct ske_keypad_platform_data;
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index e8928548b6a3..fc77b4274c8d 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -46,6 +46,6 @@
 #include <mach/irqs-board-mop500.h>
 #endif
-#define NR_IRQS                 IRQ_BOARD_END
+#define UX500_NR_IRQS           IRQ_BOARD_END
 #endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
index 3cc7142eee02..9991aea3d577 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -8,7 +8,7 @@
 #ifndef __MSP_H
 #define __MSP_H
-#include <plat/ste_dma40.h>
+#include <linux/platform_data/dma-ste-dma40.h>
 enum msp_i2s_id {
        MSP_I2S_0 = 0,
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 6f39731951b0..875309acb022 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -9,11 +9,10 @@
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/platform_data/clocksource-nomadik-mtu.h>
 #include <asm/smp_twd.h>
-#include <plat/mtu.h>
 #include <mach/setup.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -96,7 +95,7 @@ dt_fail:
         *
         */
-        nmdk_timer_init(mtu_timer_base);
+        nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
        clksrc_dbx500_prcmu_init(prcmu_timer_base);
        ux500_twd_init();
 }
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 145482e74418..78ac65f62e87 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -7,10 +7,10 @@
 #include <linux/platform_device.h>
 #include <linux/usb/musb.h>
 #include <linux/dma-mapping.h>
+#include <linux/platform_data/usb-musb-ux500.h>
+#include <linux/platform_data/dma-ste-dma40.h>
-#include <plat/ste_dma40.h>
 #include <mach/hardware.h>
-#include <linux/platform_data/usb-musb-ux500.h>
 #define MUSB_DMA40_RX_CH { \
                .mode = STEDMA40_MODE_LOGICAL, \
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 5b5c1eeb5b5c..5d5929450366 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -32,6 +32,7 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/irqchip/versatile-fpga.h>
 #include <linux/gfp.h>
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
@@ -51,7 +52,6 @@
 #include <asm/hardware/timer-sp.h>
 #include <plat/clcd.h>
-#include <plat/fpga-irq.h>
 #include <plat/sched_clock.h>
 #include "core.h"
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index c95296066203..99e63f5f99d1 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,11 +1,12 @@
 config ARCH_VEXPRESS
        bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
        select CLKDEV_LOOKUP
        select COMMON_CLK
+        select COMMON_CLK_VERSATILE
        select CPU_V7
        select GENERIC_CLOCKEVENTS
        select HAVE_CLK
@@ -17,6 +18,7 @@ config ARCH_VEXPRESS
        select PLAT_VERSATILE
        select PLAT_VERSATILE_CLCD
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select VEXPRESS_CONFIG
        help
          This option enables support for systems using Cortex processor based
          ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 42703e8b4d3b..80b64971fbdd 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,7 +4,7 @@
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
        -I$(srctree)/arch/arm/plat-versatile/include
-obj-y                                   := v2m.o
+obj-y                                   := v2m.o reset.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 4f471fa3e3c5..60838ddb8564 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -9,6 +9,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/clkdev.h>
+#include <linux/vexpress.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -64,19 +65,6 @@ static void __init ct_ca9x4_init_irq(void)
        ca9x4_twd_init();
 }
-static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
-{
-        u32 site = v2m_get_master_site();
-        /*
-         * Old firmware was using the "site" component of the command
-         * to control the DVI muxer (while it should be always 0 ie. MB).
-         * Newer firmware uses the data register. Keep both for compatibility.
-         */
-        v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
-        v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
-}
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
 {
        unsigned long framesize = 1024 * 768 * 2;
@@ -93,7 +81,6 @@ static struct clcd_board ct_ca9x4_clcd_data = {
        .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
        .check          = clcdfb_check,
        .decode         = clcdfb_decode,
-        .enable         = ct_ca9x4_clcd_enable,
        .setup          = ct_ca9x4_clcd_setup,
        .mmap           = versatile_clcd_mmap_dma,
        .remove         = versatile_clcd_remove_dma,
@@ -111,14 +98,6 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
        &gpio_device,
 };
-static struct v2m_osc ct_osc1 = {
-        .osc = 1,
-        .rate_min = 10000000,
-        .rate_max = 80000000,
-        .rate_default = 23750000,
-};
 static struct resource pmu_resources[] = {
        [0] = {
                .start  = IRQ_CT_CA9X4_PMU_CPU0,
@@ -149,10 +128,18 @@ static struct platform_device pmu_device = {
        .resource       = pmu_resources,
 };
+static struct platform_device osc1_device = {
+        .name           = "vexpress-osc",
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0xf, 1),
+        },
+};
 static void __init ct_ca9x4_init(void)
 {
        int i;
-        struct clk *clk;
 #ifdef CONFIG_CACHE_L2X0
        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@@ -164,14 +151,14 @@ static void __init ct_ca9x4_init(void)
        l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
-        ct_osc1.site = v2m_get_master_site();
-        clk = v2m_osc_register("ct:osc1", &ct_osc1);
-        clk_register_clkdev(clk, NULL, "ct:clcd");
        for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
                amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
        platform_device_register(&pmu_device);
+        platform_device_register(&osc1_device);
+        WARN_ON(clk_register_clkdev(vexpress_osc_setup(&osc1_device.dev),
+                        NULL, "ct:clcd"));
 }
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 1e388c7bf4d7..68abc8b72781 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -1,8 +1,6 @@
 #ifndef __MACH_MOTHERBOARD_H
 #define __MACH_MOTHERBOARD_H
-#include <linux/clk-provider.h>
 /*
 * Physical addresses, offset from V2M_PA_CS0-3
 */
@@ -41,31 +39,6 @@
 #define V2M_CF                  (V2M_PA_CS7 + 0x0001a000)
 #define V2M_CLCD                (V2M_PA_CS7 + 0x0001f000)
-/*
- * Offsets from SYSREGS base
- */
-#define V2M_SYS_ID              0x000
-#define V2M_SYS_SW              0x004
-#define V2M_SYS_LED             0x008
-#define V2M_SYS_100HZ           0x024
-#define V2M_SYS_FLAGS           0x030
-#define V2M_SYS_FLAGSSET        0x030
-#define V2M_SYS_FLAGSCLR        0x034
-#define V2M_SYS_NVFLAGS         0x038
-#define V2M_SYS_NVFLAGSSET      0x038
-#define V2M_SYS_NVFLAGSCLR      0x03c
-#define V2M_SYS_MCI             0x048
-#define V2M_SYS_FLASH           0x03c
-#define V2M_SYS_CFGSW           0x058
-#define V2M_SYS_24MHZ           0x05c
-#define V2M_SYS_MISC            0x060
-#define V2M_SYS_DMA             0x064
-#define V2M_SYS_PROCID0         0x084
-#define V2M_SYS_PROCID1         0x088
-#define V2M_SYS_CFGDATA         0x0a0
-#define V2M_SYS_CFGCTRL         0x0a4
-#define V2M_SYS_CFGSTAT         0x0a8
 /*
 * Interrupts.  Those in {} are for AMBA devices
@@ -91,43 +64,6 @@
 /*
- * Configuration
- */
-#define SYS_CFG_START           (1 << 31)
-#define SYS_CFG_WRITE           (1 << 30)
-#define SYS_CFG_OSC             (1 << 20)
-#define SYS_CFG_VOLT            (2 << 20)
-#define SYS_CFG_AMP             (3 << 20)
-#define SYS_CFG_TEMP            (4 << 20)
-#define SYS_CFG_RESET           (5 << 20)
-#define SYS_CFG_SCC             (6 << 20)
-#define SYS_CFG_MUXFPGA         (7 << 20)
-#define SYS_CFG_SHUTDOWN        (8 << 20)
-#define SYS_CFG_REBOOT          (9 << 20)
-#define SYS_CFG_DVIMODE         (11 << 20)
-#define SYS_CFG_POWER           (12 << 20)
-#define SYS_CFG_SITE(n)         ((n) << 16)
-#define SYS_CFG_SITE_MB         0
-#define SYS_CFG_SITE_DB1        1
-#define SYS_CFG_SITE_DB2        2
-#define SYS_CFG_STACK(n)        ((n) << 12)
-#define SYS_CFG_ERR             (1 << 1)
-#define SYS_CFG_COMPLETE        (1 << 0)
-int v2m_cfg_write(u32 devfn, u32 data);
-int v2m_cfg_read(u32 devfn, u32 *data);
-void v2m_flags_set(u32 data);
-/*
- * Miscellaneous
- */
-#define SYS_MISC_MASTERSITE     (1 << 14)
-#define SYS_PROCIDx_HBI_MASK    0xfff
-int v2m_get_master_site(void);
-/*
 * Core tile IDs
 */
 #define V2M_CT_ID_CA9           0x0c000191
@@ -149,21 +85,4 @@ struct ct_desc {
 extern struct ct_desc *ct_desc;
-/*
- * OSC clock provider
- */
-struct v2m_osc {
-        struct clk_hw hw;
-        u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
-        u8 stack; /* board stack position */
-        u16 osc;
-        unsigned long rate_min;
-        unsigned long rate_max;
-        unsigned long rate_default;
-};
-#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
-struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
 #endif
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 7db27c8c05cc..c5d70de9bb4e 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -13,6 +13,7 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <linux/of_fdt.h>
+#include <linux/vexpress.h>
 #include <asm/smp_scu.h>
 #include <asm/hardware/gic.h>
@@ -193,7 +194,7 @@ static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-        v2m_flags_set(virt_to_phys(versatile_secondary_startup));
+        vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
 }
 struct smp_operations __initdata vexpress_smp_ops = {
diff --git a/arch/arm/mach-vexpress/reset.c b/arch/arm/mach-vexpress/reset.c
new file mode 100644
index 000000000000..465923aa3819
--- /dev/null
+++ b/arch/arm/mach-vexpress/reset.c
@@ -0,0 +1,141 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+#include <linux/jiffies.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/stat.h>
+#include <linux/vexpress.h>
+static void vexpress_reset_do(struct device *dev, const char *what)
+{
+        int err = -ENOENT;
+        struct vexpress_config_func *func =
+                        vexpress_config_func_get_by_dev(dev);
+        if (func) {
+                unsigned long timeout;
+                err = vexpress_config_write(func, 0, 0);
+                timeout = jiffies + HZ;
+                while (time_before(jiffies, timeout))
+                        cpu_relax();
+        }
+        dev_emerg(dev, "Unable to %s (%d)\n", what, err);
+}
+static struct device *vexpress_power_off_device;
+void vexpress_power_off(void)
+{
+        vexpress_reset_do(vexpress_power_off_device, "power off");
+}
+static struct device *vexpress_restart_device;
+void vexpress_restart(char str, const char *cmd)
+{
+        vexpress_reset_do(vexpress_restart_device, "restart");
+}
+static ssize_t vexpress_reset_active_show(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%d\n", vexpress_restart_device == dev);
+}
+static ssize_t vexpress_reset_active_store(struct device *dev,
+                struct device_attribute *attr, const char *buf, size_t count)
+{
+        long value;
+        int err = kstrtol(buf, 0, &value);
+        if (!err && value)
+                vexpress_restart_device = dev;
+        return err ? err : count;
+}
+DEVICE_ATTR(active, S_IRUGO | S_IWUSR, vexpress_reset_active_show,
+                vexpress_reset_active_store);
+enum vexpress_reset_func { FUNC_RESET, FUNC_SHUTDOWN, FUNC_REBOOT };
+static struct of_device_id vexpress_reset_of_match[] = {
+        {
+                .compatible = "arm,vexpress-reset",
+                .data = (void *)FUNC_RESET,
+        }, {
+                .compatible = "arm,vexpress-shutdown",
+                .data = (void *)FUNC_SHUTDOWN
+        }, {
+                .compatible = "arm,vexpress-reboot",
+                .data = (void *)FUNC_REBOOT
+        },
+        {}
+};
+static int vexpress_reset_probe(struct platform_device *pdev)
+{
+        enum vexpress_reset_func func;
+        const struct of_device_id *match =
+                        of_match_device(vexpress_reset_of_match, &pdev->dev);
+        if (match)
+                func = (enum vexpress_reset_func)match->data;
+        else
+                func = pdev->id_entry->driver_data;
+        switch (func) {
+        case FUNC_SHUTDOWN:
+                vexpress_power_off_device = &pdev->dev;
+                break;
+        case FUNC_RESET:
+                if (!vexpress_restart_device)
+                        vexpress_restart_device = &pdev->dev;
+                device_create_file(&pdev->dev, &dev_attr_active);
+                break;
+        case FUNC_REBOOT:
+                vexpress_restart_device = &pdev->dev;
+                device_create_file(&pdev->dev, &dev_attr_active);
+                break;
+        };
+        return 0;
+}
+static const struct platform_device_id vexpress_reset_id_table[] = {
+        { .name = "vexpress-reset", .driver_data = FUNC_RESET, },
+        { .name = "vexpress-shutdown", .driver_data = FUNC_SHUTDOWN, },
+        { .name = "vexpress-reboot", .driver_data = FUNC_REBOOT, },
+        {}
+};
+static struct platform_driver vexpress_reset_driver = {
+        .probe = vexpress_reset_probe,
+        .driver = {
+                .name = "vexpress-reset",
+                .of_match_table = vexpress_reset_of_match,
+        },
+        .id_table = vexpress_reset_id_table,
+};
+static int __init vexpress_reset_init(void)
+{
+        return platform_driver_register(&vexpress_reset_driver);
+}
+device_initcall(vexpress_reset_init);
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 560e0df728f8..011661a6c5cb 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -16,11 +16,10 @@
 #include <linux/smsc911x.h>
 #include <linux/spinlock.h>
 #include <linux/usb/isp1760.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
 #include <linux/mtd/physmap.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
+#include <linux/vexpress.h>
 #include <asm/arch_timer.h>
 #include <asm/mach-types.h>
@@ -33,7 +32,6 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/timer-sp.h>
-#include <asm/hardware/sp810.h>
 #include <mach/ct-ca9x4.h>
 #include <mach/motherboard.h>
@@ -58,22 +56,6 @@ static struct map_desc v2m_io_desc[] __initdata = {
        },
 };
-static void __iomem *v2m_sysreg_base;
-static void __init v2m_sysctl_init(void __iomem *base)
-{
-        u32 scctrl;
-        if (WARN_ON(!base))
-                return;
-        /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
-        scctrl = readl(base + SCCTRL);
-        scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
-        scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
-        writel(scctrl, base + SCCTRL);
-}
 static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
 {
        if (WARN_ON(!base || irq == NO_IRQ))
@@ -87,69 +69,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
 }
-static DEFINE_SPINLOCK(v2m_cfg_lock);
-int v2m_cfg_write(u32 devfn, u32 data)
-{
-        /* Configuration interface broken? */
-        u32 val;
-        printk("%s: writing %08x to %08x\n", __func__, data, devfn);
-        devfn |= SYS_CFG_START | SYS_CFG_WRITE;
-        spin_lock(&v2m_cfg_lock);
-        val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        writel(data, v2m_sysreg_base +  V2M_SYS_CFGDATA);
-        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
-        do {
-                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        } while (val == 0);
-        spin_unlock(&v2m_cfg_lock);
-        return !!(val & SYS_CFG_ERR);
-}
-int v2m_cfg_read(u32 devfn, u32 *data)
-{
-        u32 val;
-        devfn |= SYS_CFG_START;
-        spin_lock(&v2m_cfg_lock);
-        writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
-        mb();
-        do {
-                cpu_relax();
-                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
-        } while (val == 0);
-        *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
-        spin_unlock(&v2m_cfg_lock);
-        return !!(val & SYS_CFG_ERR);
-}
-void __init v2m_flags_set(u32 data)
-{
-        writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
-        writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
-}
-int v2m_get_master_site(void)
-{
-        u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
-        return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
-}
 static struct resource v2m_pcie_i2c_resource = {
        .start  = V2M_SERIAL_BUS_PCI,
        .end    = V2M_SERIAL_BUS_PCI + SZ_4K - 1,
@@ -237,14 +156,8 @@ static struct platform_device v2m_usb_device = {
        .dev.platform_data = &v2m_usb_config,
 };
-static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
-{
-        writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
-}
 static struct physmap_flash_data v2m_flash_data = {
        .width          = 4,
-        .set_vpp        = v2m_flash_set_vpp,
 };
 static struct resource v2m_flash_resources[] = {
@@ -291,14 +204,61 @@ static struct platform_device v2m_cf_device = {
        .dev.platform_data = &v2m_pata_data,
 };
-static unsigned int v2m_mmci_status(struct device *dev)
-{
-        return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
-}
 static struct mmci_platform_data v2m_mmci_data = {
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .status         = v2m_mmci_status,
+        .gpio_wp        = VEXPRESS_GPIO_MMC_WPROT,
+        .gpio_cd        = VEXPRESS_GPIO_MMC_CARDIN,
+};
+static struct resource v2m_sysreg_resources[] = {
+        {
+                .start  = V2M_SYSREGS,
+                .end    = V2M_SYSREGS + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device v2m_sysreg_device = {
+        .name           = "vexpress-sysreg",
+        .id             = -1,
+        .resource       = v2m_sysreg_resources,
+        .num_resources  = ARRAY_SIZE(v2m_sysreg_resources),
+};
+static struct platform_device v2m_muxfpga_device = {
+        .name           = "vexpress-muxfpga",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 7),
+        }
+};
+static struct platform_device v2m_shutdown_device = {
+        .name           = "vexpress-shutdown",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 8),
+        }
+};
+static struct platform_device v2m_reboot_device = {
+        .name           = "vexpress-reboot",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 9),
+        }
+};
+static struct platform_device v2m_dvimode_device = {
+        .name           = "vexpress-dvimode",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = (struct resource []) {
+                VEXPRESS_RES_FUNC(0, 11),
+        }
 };
 static AMBA_APB_DEVICE(aaci,  "mb:aaci",  0, V2M_AACI, IRQ_V2M_AACI, NULL);
@@ -325,123 +285,9 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
        &rtc_device,
 };
-static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
-                unsigned long parent_rate)
-{
-        struct v2m_osc *osc = to_v2m_osc(hw);
-        return !parent_rate ? osc->rate_default : parent_rate;
-}
-static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long *parent_rate)
-{
-        struct v2m_osc *osc = to_v2m_osc(hw);
-        if (WARN_ON(rate < osc->rate_min))
-                rate = osc->rate_min;
-        if (WARN_ON(rate > osc->rate_max))
-                rate = osc->rate_max;
-        return rate;
-}
-static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
-                unsigned long parent_rate)
-{
-        struct v2m_osc *osc = to_v2m_osc(hw);
-        v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
-                        SYS_CFG_STACK(osc->stack) | osc->osc, rate);
-        return 0;
-}
-static struct clk_ops v2m_osc_ops = {
-        .recalc_rate = v2m_osc_recalc_rate,
-        .round_rate = v2m_osc_round_rate,
-        .set_rate = v2m_osc_set_rate,
-};
-struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
-{
-        struct clk_init_data init;
-        WARN_ON(osc->site > 2);
-        WARN_ON(osc->stack > 15);
-        WARN_ON(osc->osc > 4095);
-        init.name = name;
-        init.ops = &v2m_osc_ops;
-        init.flags = CLK_IS_ROOT;
-        init.num_parents = 0;
-        osc->hw.init = &init;
-        return clk_register(NULL, &osc->hw);
-}
-static struct v2m_osc v2m_mb_osc1 = {
-        .site = SYS_CFG_SITE_MB,
-        .osc = 1,
-        .rate_min = 23750000,
-        .rate_max = 63500000,
-        .rate_default = 23750000,
-};
-static const char *v2m_ref_clk_periphs[] __initconst = {
-        "mb:wdt",   "1000f000.wdt",  "1c0f0000.wdt",    /* SP805 WDT */
-};
-static const char *v2m_osc1_periphs[] __initconst = {
-        "mb:clcd",  "1001f000.clcd", "1c1f0000.clcd",   /* PL111 CLCD */
-};
-static const char *v2m_osc2_periphs[] __initconst = {
-        "mb:mmci",  "10005000.mmci", "1c050000.mmci",   /* PL180 MMCI */
-        "mb:kmi0",  "10006000.kmi",  "1c060000.kmi",    /* PL050 KMI0 */
-        "mb:kmi1",  "10007000.kmi",  "1c070000.kmi",    /* PL050 KMI1 */
-        "mb:uart0", "10009000.uart", "1c090000.uart",   /* PL011 UART0 */
-        "mb:uart1", "1000a000.uart", "1c0a0000.uart",   /* PL011 UART1 */
-        "mb:uart2", "1000b000.uart", "1c0b0000.uart",   /* PL011 UART2 */
-        "mb:uart3", "1000c000.uart", "1c0c0000.uart",   /* PL011 UART3 */
-};
-static void __init v2m_clk_init(void)
-{
-        struct clk *clk;
-        int i;
-        clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
-                        CLK_IS_ROOT, 0);
-        WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
-        clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
-                        CLK_IS_ROOT, 32768);
-        for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
-                WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
-        clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
-                        CLK_IS_ROOT, 1000000);
-        WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
-        WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
-        clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
-        for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
-                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
-        clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
-                        CLK_IS_ROOT, 24000000);
-        for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
-                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
-}
 static void __init v2m_timer_init(void)
 {
-        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+        vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K));
-        v2m_clk_init();
        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
 }
@@ -453,19 +299,7 @@ static void __init v2m_init_early(void)
 {
        if (ct_desc->init_early)
                ct_desc->init_early();
-        versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+        versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000);
-}
-static void v2m_power_off(void)
-{
-        if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
-                printk(KERN_EMERG "Unable to shutdown\n");
-}
-static void v2m_restart(char str, const char *cmd)
-{
-        if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
-                printk(KERN_EMERG "Unable to reboot\n");
 }
 struct ct_desc *ct_desc;
@@ -482,7 +316,7 @@ static void __init v2m_populate_ct_desc(void)
        u32 current_tile_id;
        ct_desc = NULL;
-        current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+        current_tile_id = vexpress_get_procid(VEXPRESS_SITE_MASTER)
                                & V2M_CT_ID_MASK;
        for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
@@ -498,7 +332,7 @@ static void __init v2m_populate_ct_desc(void)
 static void __init v2m_map_io(void)
 {
        iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
-        v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
+        vexpress_sysreg_early_init(ioremap(V2M_SYSREGS, SZ_4K));
        v2m_populate_ct_desc();
        ct_desc->map_io();
 }
@@ -515,6 +349,12 @@ static void __init v2m_init(void)
        regulator_register_fixed(0, v2m_eth_supplies,
                        ARRAY_SIZE(v2m_eth_supplies));
+        platform_device_register(&v2m_muxfpga_device);
+        platform_device_register(&v2m_shutdown_device);
+        platform_device_register(&v2m_reboot_device);
+        platform_device_register(&v2m_dvimode_device);
+        platform_device_register(&v2m_sysreg_device);
        platform_device_register(&v2m_pcie_i2c_device);
        platform_device_register(&v2m_ddc_i2c_device);
        platform_device_register(&v2m_flash_device);
@@ -525,7 +365,7 @@ static void __init v2m_init(void)
        for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
                amba_device_register(v2m_amba_devs[i], &iomem_resource);
-        pm_power_off = v2m_power_off;
+        pm_power_off = vexpress_power_off;
        ct_desc->init_tile();
 }
@@ -539,7 +379,7 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
        .timer          = &v2m_timer,
        .handle_irq     = gic_handle_irq,
        .init_machine   = v2m_init,
-        .restart        = v2m_restart,
+        .restart        = vexpress_restart,
 MACHINE_END
 static struct map_desc v2m_rs1_io_desc __initdata = {
@@ -580,20 +420,13 @@ void __init v2m_dt_map_io(void)
 void __init v2m_dt_init_early(void)
 {
-        struct device_node *node;
        u32 dt_hbi;
-        node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
+        vexpress_sysreg_of_early_init();
-        v2m_sysreg_base = of_iomap(node, 0);
-        if (WARN_ON(!v2m_sysreg_base))
-                return;
        /* Confirm board type against DT property, if available */
-        if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
+        if (of_property_read_u32(of_allnodes, "arm,hbi", &dt_hbi) == 0) {
-                int site = v2m_get_master_site();
+                u32 hbi = vexpress_get_hbi(VEXPRESS_SITE_MASTER);
-                u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
-                                V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
-                u32 hbi = id & SYS_PROCIDx_HBI_MASK;
                if (WARN_ON(dt_hbi != hbi))
                        pr_warning("vexpress: DT HBI (%x) is not matching "
@@ -613,51 +446,47 @@ static void __init v2m_dt_init_irq(void)
 static void __init v2m_dt_timer_init(void)
 {
-        struct device_node *node;
+        struct device_node *node = NULL;
-        const char *path;
-        int err;
-        node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+        vexpress_clk_of_init();
-        v2m_sysctl_init(of_iomap(node, 0));
-        v2m_clk_init();
+        do {
+                node = of_find_compatible_node(node, NULL, "arm,sp804");
+        } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
+        if (node) {
+                pr_info("Using SP804 '%s' as a clock & events source\n",
+                                node->full_name);
+                v2m_sp804_init(of_iomap(node, 0),
+                                irq_of_parse_and_map(node, 0));
+        }
-        err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
        if (arch_timer_of_register() != 0)
                twd_local_timer_of_register();
        if (arch_timer_sched_clock_init() != 0)
-                versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+                versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
+                                24000000);
 }
 static struct sys_timer v2m_dt_timer = {
        .init = v2m_dt_timer_init,
 };
-static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+static const struct of_device_id v2m_dt_bus_match[] __initconst = {
-        OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+        { .compatible = "simple-bus", },
-                        &v2m_flash_data),
+        { .compatible = "arm,amba-bus", },
-        OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+        { .compatible = "arm,vexpress,config-bus", },
-        /* RS1 memory map */
-        OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
-                        &v2m_flash_data),
-        OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
        {}
 };
 static void __init v2m_dt_init(void)
 {
        l2x0_of_init(0x00400000, 0xfe0fffff);
-        of_platform_populate(NULL, of_default_bus_match_table,
+        of_platform_populate(NULL, v2m_dt_bus_match, NULL, NULL);
-                        v2m_dt_auxdata_lookup, NULL);
+        pm_power_off = vexpress_power_off;
-        pm_power_off = v2m_power_off;
 }
-const static char *v2m_dt_match[] __initconst = {
+static const char * const v2m_dt_match[] __initconst = {
        "arm,vexpress",
        "xen,xenvm",
        NULL,
@@ -672,5 +501,5 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
        .timer          = &v2m_dt_timer,
        .init_machine   = v2m_dt_init,
        .handle_irq     = gic_handle_irq,
-        .restart        = v2m_restart,
+        .restart        = vexpress_restart,
 MACHINE_END
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
new file mode 100644
index 000000000000..2ed0b7d95db6
--- /dev/null
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -0,0 +1,12 @@
+config ARCH_VT8500
+        bool "VIA/WonderMedia 85xx" if ARCH_MULTI_V5
+        default ARCH_VT8500_SINGLE
+        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CPU_ARM926T
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select HAVE_CLK
+        help
+          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
index 2b2419646e95..6f2b843115db 100644
--- a/arch/arm/mach-vt8500/common.h
+++ b/arch/arm/mach-vt8500/common.h
@@ -25,4 +25,7 @@ int __init vt8500_irq_init(struct device_node *node,
 /* defined in drivers/clk/clk-vt8500.c */
 void __init vtwm_clk_init(void __iomem *pmc_base);
+/* defined in irq.c */
+asmlinkage void vt8500_handle_irq(struct pt_regs *regs);
 #endif
diff --git a/arch/arm/mach-vt8500/include/mach/entry-macro.S b/arch/arm/mach-vt8500/include/mach/entry-macro.S
deleted file mode 100644
index 367d1b55fb9a..000000000000
--- a/arch/arm/mach-vt8500/include/mach/entry-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-vt8500/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for VIA VT8500
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-        .macro  get_irqnr_preamble, base, tmp
-        @ physical 0xd8140000 is virtual 0xf8140000
-        mov     \base, #0xf8000000
-        orr     \base, \base, #0x00140000
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base]
-        cmp     \irqnr, #63 @ may be false positive, check interrupt status
-        bne     1001f
-        ldr     \irqstat, [\base, #0x84]
-        ands    \irqstat, #0x80000000
-        moveq   \irqnr, #0
-1001:
-        .endm
diff --git a/arch/arm/mach-vt8500/include/mach/hardware.h b/arch/arm/mach-vt8500/include/mach/hardware.h
deleted file mode 100644
index db4163f72c39..000000000000
--- a/arch/arm/mach-vt8500/include/mach/hardware.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* arch/arm/mach-vt8500/include/mach/hardware.h
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
diff --git a/arch/arm/mach-vt8500/include/mach/i8042.h b/arch/arm/mach-vt8500/include/mach/i8042.h
deleted file mode 100644
index cd7143cad6f3..000000000000
--- a/arch/arm/mach-vt8500/include/mach/i8042.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-vt8500/include/mach/i8042.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-extern unsigned long wmt_i8042_base __initdata;
-extern int wmt_i8042_kbd_irq;
-extern int wmt_i8042_aux_irq;
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
deleted file mode 100644
index 738979518acb..000000000000
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.h
- *
- * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-void vt8500_setup_restart(void);
-void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index f8f9ab9bc56e..b9cf5ce9efbb 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -36,7 +36,7 @@
 #include <linux/of_address.h>
 #include <asm/irq.h>
+#include <asm/exception.h>
 #define VT8500_ICPC_IRQ         0x20
 #define VT8500_ICPC_FIQ         0x24
@@ -66,30 +66,34 @@
 #define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
                                | VT8500_TRIGGER_FALLING)
-static int irq_cnt;
+/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
+#define VT8500_INTC_MAX         2
-struct vt8500_irq_priv {
+struct vt8500_irq_data {
-        void __iomem *base;
+        void __iomem            *base;          /* IO Memory base address */
+        struct irq_domain       *domain;        /* Domain for this controller */
 };
+/* Global variable for accessing io-mem addresses */
+static struct vt8500_irq_data intc[VT8500_INTC_MAX];
+static u32 active_cnt = 0;
 static void vt8500_irq_mask(struct irq_data *d)
 {
-        struct vt8500_irq_priv *priv =
+        struct vt8500_irq_data *priv = d->domain->host_data;
-                        (struct vt8500_irq_priv *)(d->domain->host_data);
        void __iomem *base = priv->base;
-        u8 edge;
+        void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
+        u8 edge, dctr;
+        u32 status;
        edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
        if (edge) {
-                void __iomem *stat_reg = base + VT8500_ICIS
+                status = readl(stat_reg);
-                                                + (d->hwirq < 32 ? 0 : 4);
-                unsigned status = readl(stat_reg);
                status |= (1 << (d->hwirq & 0x1f));
                writel(status, stat_reg);
        } else {
-                u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
+                dctr = readb(base + VT8500_ICDC + d->hwirq);
                dctr &= ~VT8500_INT_ENABLE;
                writeb(dctr, base + VT8500_ICDC + d->hwirq);
        }
@@ -97,8 +101,7 @@ static void vt8500_irq_mask(struct irq_data *d)
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-        struct vt8500_irq_priv *priv =
+        struct vt8500_irq_data *priv = d->domain->host_data;
-                        (struct vt8500_irq_priv *)(d->domain->host_data);
        void __iomem *base = priv->base;
        u8 dctr;
@@ -109,8 +112,7 @@ static void vt8500_irq_unmask(struct irq_data *d)
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        struct vt8500_irq_priv *priv =
+        struct vt8500_irq_data *priv = d->domain->host_data;
-                        (struct vt8500_irq_priv *)(d->domain->host_data);
        void __iomem *base = priv->base;
        u8 dctr;
@@ -148,17 +150,15 @@ static struct irq_chip vt8500_irq_chip = {
 static void __init vt8500_init_irq_hw(void __iomem *base)
 {
-        unsigned int i;
+        u32 i;
        /* Enable rotating priority for IRQ */
        writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
        writel(0x00, base + VT8500_ICPC_FIQ);
-        for (i = 0; i < 64; i++) {
+        /* Disable all interrupts and route them to IRQ */
-                /* Disable all interrupts and route them to IRQ */
+        for (i = 0; i < 64; i++)
-                writeb(VT8500_INT_DISABLE | ICDC_IRQ,
+                writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
-                                                base + VT8500_ICDC + i);
-        }
 }
 static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
@@ -175,33 +175,67 @@ static struct irq_domain_ops vt8500_irq_domain_ops = {
        .xlate = irq_domain_xlate_onecell,
 };
+asmlinkage void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
+{
+        u32 stat, i;
+        int irqnr, virq;
+        void __iomem *base;
+        /* Loop through each active controller */
+        for (i=0; i<active_cnt; i++) {
+                base = intc[i].base;
+                irqnr = readl_relaxed(base) & 0x3F;
+                /*
+                  Highest Priority register default = 63, so check that this
+                  is a real interrupt by checking the status register
+                */
+                if (irqnr == 63) {
+                        stat = readl_relaxed(base + VT8500_ICIS + 4);
+                        if (!(stat & BIT(31)))
+                                continue;
+                }
+                virq = irq_find_mapping(intc[i].domain, irqnr);
+                handle_IRQ(virq, regs);
+        }
+}
 int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-        struct irq_domain *vt8500_irq_domain;
-        struct vt8500_irq_priv *priv;
        int irq, i;
        struct device_node *np = node;
-        priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+        if (active_cnt == VT8500_INTC_MAX) {
-        priv->base = of_iomap(np, 0);
+                pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
+                                                                __func__);
+                goto out;
+        }
+        intc[active_cnt].base = of_iomap(np, 0);
+        intc[active_cnt].domain = irq_domain_add_linear(node, 64,
+                        &vt8500_irq_domain_ops, &intc[active_cnt]);
-        vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+        if (!intc[active_cnt].base) {
-                                &vt8500_irq_domain_ops, priv);
+                pr_err("%s: Unable to map IO memory\n", __func__);
-        if (!vt8500_irq_domain)
+                goto out;
-                pr_err("%s: Unable to add wmt irq domain!\n", __func__);
+        }
+        if (!intc[active_cnt].domain) {
+                pr_err("%s: Unable to add irq domain!\n", __func__);
+                goto out;
+        }
-        irq_set_default_host(vt8500_irq_domain);
+        vt8500_init_irq_hw(intc[active_cnt].base);
-        vt8500_init_irq_hw(priv->base);
+        pr_info("vt8500-irq: Added interrupt controller\n");
-        pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
+        active_cnt++;
-                                                (u32)(priv->base), irq_cnt);
        /* check if this is a slaved controller */
        if (of_irq_count(np) != 0) {
                /* check that we have the correct number of interrupts */
                if (of_irq_count(np) != 8) {
-                        pr_err("%s: Incorrect IRQ map for slave controller\n",
+                        pr_err("%s: Incorrect IRQ map for slaved controller\n",
                                        __func__);
                        return -EINVAL;
                }
@@ -213,9 +247,7 @@ int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
                pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
        }
+out:
-        irq_cnt += 64;
        return 0;
 }
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index 050e1833f2d0..3dd21a47881f 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,5 +1,5 @@
 /*
- *  arch/arm/mach-vt8500/timer_dt.c
+ *  arch/arm/mach-vt8500/timer.c
 *
 *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 8d3871f110a5..3c66d48ea082 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -31,8 +31,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <mach/restart.h>
 #include "common.h"
 #define LEGACY_GPIO_BASE        0xD8110000
@@ -194,5 +192,6 @@ DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
        .timer          = &vt8500_timer,
        .init_machine   = vt8500_init,
        .restart        = vt8500_restart,
+        .handle_irq     = vt8500_handle_irq,
 MACHINE_END
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
new file mode 100644
index 000000000000..adb6c0ea0e53
--- /dev/null
+++ b/arch/arm/mach-zynq/Kconfig
@@ -0,0 +1,13 @@
+config ARCH_ZYNQ
+        bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
+        select ARM_AMBA
+        select ARM_GIC
+        select COMMON_CLK
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select ICST
+        select MIGHT_HAVE_CACHE_L2X0
+        select USE_OF
+        select SPARSE_IRQ
+        help
+          Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index ab5cfddc0d7b..e16d4bed0f7a 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -19,19 +19,21 @@
 #include <linux/cpumask.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/clk/zynq.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/time.h>
 #include <asm/mach-types.h>
 #include <asm/page.h>
+#include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/zynq_soc.h>
-#include <mach/clkdev.h>
 #include "common.h"
 static struct of_device_id zynq_of_bus_ids[] __initdata = {
@@ -45,55 +47,57 @@ static struct of_device_id zynq_of_bus_ids[] __initdata = {
 */
 static void __init xilinx_init_machine(void)
 {
-#ifdef CONFIG_CACHE_L2X0
        /*
         * 64KB way size, 8-way associativity, parity disabled
         */
-        l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
+        l2x0_of_init(0x02060000, 0xF0F0FFFF);
-#endif
        of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
 }
+static struct of_device_id irq_match[] __initdata = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { }
+};
 /**
 * xilinx_irq_init() - Interrupt controller initialization for the GIC.
 */
 static void __init xilinx_irq_init(void)
 {
-        gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
+        of_irq_init(irq_match);
 }
-/* The minimum devices needed to be mapped before the VM system is up and
+#define SCU_PERIPH_PHYS         0xF8F00000
- * running include the GIC, UART and Timer Counter.
+#define SCU_PERIPH_SIZE         SZ_8K
- */
+#define SCU_PERIPH_VIRT         (VMALLOC_END - SCU_PERIPH_SIZE)
+static struct map_desc scu_desc __initdata = {
+        .virtual        = SCU_PERIPH_VIRT,
+        .pfn            = __phys_to_pfn(SCU_PERIPH_PHYS),
+        .length         = SCU_PERIPH_SIZE,
+        .type           = MT_DEVICE,
+};
+static void __init xilinx_zynq_timer_init(void)
+{
+        struct device_node *np;
+        void __iomem *slcr;
+        np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
+        slcr = of_iomap(np, 0);
+        WARN_ON(!slcr);
+        xilinx_zynq_clocks_init(slcr);
-static struct map_desc io_desc[] __initdata = {
+        xttcpss_timer_init();
-        {
+}
-                .virtual        = TTC0_VIRT,
-                .pfn            = __phys_to_pfn(TTC0_PHYS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = SCU_PERIPH_VIRT,
-                .pfn            = __phys_to_pfn(SCU_PERIPH_PHYS),
-                .length         = SZ_8K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = PL310_L2CC_VIRT,
-                .pfn            = __phys_to_pfn(PL310_L2CC_PHYS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-#ifdef CONFIG_DEBUG_LL
-        {
-                .virtual        = UART0_VIRT,
-                .pfn            = __phys_to_pfn(UART0_PHYS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-#endif
+/*
+ * Instantiate and initialize the system timer structure
+ */
+static struct sys_timer xttcpss_sys_timer = {
+        .init           = xilinx_zynq_timer_init,
 };
 /**
@@ -101,11 +105,13 @@ static struct map_desc io_desc[] __initdata = {
 */
 static void __init xilinx_map_io(void)
 {
-        iotable_init(io_desc, ARRAY_SIZE(io_desc));
+        debug_ll_io_init();
+        iotable_init(&scu_desc, 1);
 }
 static const char *xilinx_dt_match[] = {
-        "xlnx,zynq-ep107",
+        "xlnx,zynq-zc702",
+        "xlnx,zynq-7000",
        NULL
 };
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index a009644a1555..954b91c13c91 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,8 +17,6 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
-#include <asm/mach/time.h>
+void __init xttcpss_timer_init(void);
-extern struct sys_timer xttcpss_sys_timer;
 #endif
diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h
deleted file mode 100644
index c6e73d81a459..000000000000
--- a/arch/arm/mach-zynq/include/mach/clkdev.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-zynq/include/mach/clkdev.h
- *
- *  Copyright (C) 2011 Xilinx, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-#include <plat/clock.h>
-struct clk {
-        unsigned long           rate;
-        const struct clk_ops    *ops;
-        const struct icst_params *params;
-        void __iomem            *vcoreg;
-};
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
deleted file mode 100644
index d558d8a94be7..000000000000
--- a/arch/arm/mach-zynq/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/hardware.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_HARDWARE_H__
-#define __MACH_HARDWARE_H__
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/irqs.h b/arch/arm/mach-zynq/include/mach/irqs.h
deleted file mode 100644
index 5fb04fd3bac8..000000000000
--- a/arch/arm/mach-zynq/include/mach/irqs.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/irqs.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-#define ARCH_NR_GPIOS   118
-#define NR_IRQS         (128 + ARCH_NR_GPIOS)
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/timex.h b/arch/arm/mach-zynq/include/mach/timex.h
deleted file mode 100644
index 6c0245e42a5e..000000000000
--- a/arch/arm/mach-zynq/include/mach/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/timex.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_TIMEX_H__
-#define __MACH_TIMEX_H__
-/* the following is needed for the system to build but will be removed
-   in the future, the value is not important but won't hurt
-*/
-#define CLOCK_TICK_RATE (100 * HZ)
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/uart.h b/arch/arm/mach-zynq/include/mach/uart.h
deleted file mode 100644
index 5c47c97156f3..000000000000
--- a/arch/arm/mach-zynq/include/mach/uart.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/uart.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_UART_H__
-#define __MACH_UART_H__
-#define UART_CR_OFFSET          0x00  /* Control Register [8:0] */
-#define UART_SR_OFFSET          0x2C  /* Channel Status [11:0] */
-#define UART_FIFO_OFFSET        0x30  /* FIFO [15:0] or [7:0] */
-#define UART_SR_TXFULL          0x00000010      /* TX FIFO full */
-#define UART_SR_TXEMPTY         0x00000008      /* TX FIFO empty */
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/uncompress.h b/arch/arm/mach-zynq/include/mach/uncompress.h
deleted file mode 100644
index af4e8447bfa3..000000000000
--- a/arch/arm/mach-zynq/include/mach/uncompress.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/uncompress.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_UNCOMPRESS_H__
-#define __MACH_UNCOMPRESS_H__
-#include <linux/io.h>
-#include <asm/processor.h>
-#include <mach/zynq_soc.h>
-#include <mach/uart.h>
-void arch_decomp_setup(void)
-{
-}
-static inline void flush(void)
-{
-        /*
-         * Wait while the FIFO is not empty
-         */
-        while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
-                UART_SR_TXEMPTY))
-                cpu_relax();
-}
-#define arch_decomp_wdog()
-static void putc(char ch)
-{
-        /*
-         * Wait for room in the FIFO, then write the char into the FIFO
-         */
-        while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
-                UART_SR_TXFULL)
-                cpu_relax();
-        __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET));
-}
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h
deleted file mode 100644
index d0d3f8fb06dd..000000000000
--- a/arch/arm/mach-zynq/include/mach/zynq_soc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/zynq_soc.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_XILINX_SOC_H__
-#define __MACH_XILINX_SOC_H__
-#define PERIPHERAL_CLOCK_RATE           2500000
-/* For now, all mappings are flat (physical = virtual)
- */
-#define UART0_PHYS                      0xE0000000
-#define UART0_VIRT                      UART0_PHYS
-#define TTC0_PHYS                       0xF8001000
-#define TTC0_VIRT                       TTC0_PHYS
-#define PL310_L2CC_PHYS                 0xF8F02000
-#define PL310_L2CC_VIRT                 PL310_L2CC_PHYS
-#define SCU_PERIPH_PHYS                 0xF8F00000
-#define SCU_PERIPH_VIRT                 SCU_PERIPH_PHYS
-/* The following are intended for the devices that are mapped early */
-#define TTC0_BASE                       IOMEM(TTC0_VIRT)
-#define SCU_PERIPH_BASE                 IOMEM(SCU_PERIPH_VIRT)
-#define SCU_GIC_CPU_BASE                (SCU_PERIPH_BASE + 0x100)
-#define SCU_GIC_DIST_BASE               (SCU_PERIPH_BASE + 0x1000)
-#define PL310_L2CC_BASE                 IOMEM(PL310_L2CC_VIRT)
-/*
- * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
- */
-#define LL_UART_PADDR   UART0_PHYS
-#define LL_UART_VADDR   UART0_VIRT
-#endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index c2c96cc7d6e7..de3df283da74 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -23,32 +23,14 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
-#include <asm/mach/time.h>
-#include <mach/zynq_soc.h>
 #include "common.h"
-#define IRQ_TIMERCOUNTER0       42
-/*
- * This driver configures the 2 16-bit count-up timers as follows:
- *
- * T1: Timer 1, clocksource for generic timekeeping
- * T2: Timer 2, clockevent source for hrtimers
- * T3: Timer 3, <unused>
- *
- * The input frequency to the timer module for emulation is 2.5MHz which is
- * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
- * the timers are clocked at 78.125KHz (12.8 us resolution).
- *
- * The input frequency to the timer module in silicon will be 200MHz. With the
- * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
- */
-#define XTTCPSS_CLOCKSOURCE     0       /* Timer 1 as a generic timekeeping */
-#define XTTCPSS_CLOCKEVENT      1       /* Timer 2 as a clock event */
-#define XTTCPSS_TIMER_BASE              TTC0_BASE
-#define XTTCPCC_EVENT_TIMER_IRQ         (IRQ_TIMERCOUNTER0 + 1)
 /*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
@@ -65,9 +47,14 @@
 #define XTTCPSS_CNT_CNTRL_DISABLE_MASK  0x1
-/* Setup the timers to use pre-scaling */
+/* Setup the timers to use pre-scaling, using a fixed value for now that will
+ * work across most input frequency, but it may need to be more dynamic
-#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32)
+ */
+#define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
+#define PRESCALE                2048    /* The exponent must match this */
+#define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
+#define CLK_CNTRL_PRESCALE_EN   1
+#define CNT_CNTRL_RESET         (1<<4)
 /**
 * struct xttcpss_timer - This definition defines local timer structure
@@ -75,11 +62,25 @@
 * @base_addr:  Base address of timer
 **/
 struct xttcpss_timer {
-        void __iomem *base_addr;
+        void __iomem    *base_addr;
 };
-static struct xttcpss_timer timers[2];
+struct xttcpss_timer_clocksource {
-static struct clock_event_device xttcpss_clockevent;
+        struct xttcpss_timer    xttc;
+        struct clocksource      cs;
+};
+#define to_xttcpss_timer_clksrc(x) \
+                container_of(x, struct xttcpss_timer_clocksource, cs)
+struct xttcpss_timer_clockevent {
+        struct xttcpss_timer            xttc;
+        struct clock_event_device       ce;
+        struct clk                      *clk;
+};
+#define to_xttcpss_timer_clkevent(x) \
+                container_of(x, struct xttcpss_timer_clockevent, ce)
 /**
 * xttcpss_set_interval - Set the timer interval value
@@ -101,7 +102,7 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer,
        /* Reset the counter (0x10) so that it starts from 0, one-shot
           mode makes this needed for timing to be right. */
-        ctrl_reg |= 0x10;
+        ctrl_reg |= CNT_CNTRL_RESET;
        ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
        __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 }
@@ -116,90 +117,31 @@ static void xttcpss_set_interval(struct xttcpss_timer *timer,
 **/
 static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = &xttcpss_clockevent;
+        struct xttcpss_timer_clockevent *xttce = dev_id;
-        struct xttcpss_timer *timer = dev_id;
+        struct xttcpss_timer *timer = &xttce->xttc;
        /* Acknowledge the interrupt and call event handler */
        __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
                        timer->base_addr + XTTCPSS_ISR_OFFSET);
-        evt->event_handler(evt);
+        xttce->ce.event_handler(&xttce->ce);
        return IRQ_HANDLED;
 }
-static struct irqaction event_timer_irq = {
-        .name   = "xttcpss clockevent",
-        .flags  = IRQF_DISABLED | IRQF_TIMER,
-        .handler = xttcpss_clock_event_interrupt,
-};
 /**
- * xttcpss_timer_hardware_init - Initialize the timer hardware
+ * __xttc_clocksource_read - Reads the timer counter register
- *
- * Initialize the hardware to start the clock source, get the clock
- * event timer ready to use, and hook up the interrupt.
- **/
-static void __init xttcpss_timer_hardware_init(void)
-{
-        /* Setup the clock source counter to be an incrementing counter
-         * with no interrupt and it rolls over at 0xFFFF. Pre-scale
-           it by 32 also. Let it start running now.
-         */
-        timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
-        __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
-                                XTTCPSS_IER_OFFSET);
-        __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
-                                XTTCPSS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
-                                XTTCPSS_CNT_CNTRL_OFFSET);
-        /* Setup the clock event timer to be an interval timer which
-         * is prescaled by 32 using the interval interrupt. Leave it
-         * disabled for now.
-         */
-        timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
-        __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
-                        XTTCPSS_CNT_CNTRL_OFFSET);
-        __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
-                        XTTCPSS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
-                        XTTCPSS_IER_OFFSET);
-        /* Setup IRQ the clock event timer */
-        event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
-        setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
-}
-/**
- * __raw_readl_cycles - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
-static cycle_t __raw_readl_cycles(struct clocksource *cs)
+static cycle_t __xttc_clocksource_read(struct clocksource *cs)
 {
-        struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
+        struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
        return (cycle_t)__raw_readl(timer->base_addr +
                                XTTCPSS_COUNT_VAL_OFFSET);
 }
-/*
- * Instantiate and initialize the clock source structure
- */
-static struct clocksource clocksource_xttcpss = {
-        .name           = "xttcpss_timer1",
-        .rating         = 200,                  /* Reasonable clock source */
-        .read           = __raw_readl_cycles,
-        .mask           = CLOCKSOURCE_MASK(16),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
 /**
 * xttcpss_set_next_event - Sets the time interval for next event
 *
@@ -211,7 +153,8 @@ static struct clocksource clocksource_xttcpss = {
 static int xttcpss_set_next_event(unsigned long cycles,
                                        struct clock_event_device *evt)
 {
-        struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+        struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
+        struct xttcpss_timer *timer = &xttce->xttc;
        xttcpss_set_interval(timer, cycles);
        return 0;
@@ -226,12 +169,15 @@ static int xttcpss_set_next_event(unsigned long cycles,
 static void xttcpss_set_mode(enum clock_event_mode mode,
                                        struct clock_event_device *evt)
 {
-        struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+        struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
+        struct xttcpss_timer *timer = &xttce->xttc;
        u32 ctrl_reg;
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
-                xttcpss_set_interval(timer, TIMER_RATE / HZ);
+                xttcpss_set_interval(timer,
+                                     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
+                                                       PRESCALE * HZ));
                break;
        case CLOCK_EVT_MODE_ONESHOT:
        case CLOCK_EVT_MODE_UNUSED:
@@ -252,15 +198,106 @@ static void xttcpss_set_mode(enum clock_event_mode mode,
        }
 }
-/*
+static void __init zynq_ttc_setup_clocksource(struct device_node *np,
- * Instantiate and initialize the clock event structure
+                                             void __iomem *base)
- */
+{
-static struct clock_event_device xttcpss_clockevent = {
+        struct xttcpss_timer_clocksource *ttccs;
-        .name           = "xttcpss_timer2",
+        struct clk *clk;
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        int err;
-        .set_next_event = xttcpss_set_next_event,
+        u32 reg;
-        .set_mode       = xttcpss_set_mode,
-        .rating         = 200,
+        ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
+        if (WARN_ON(!ttccs))
+                return;
+        err = of_property_read_u32(np, "reg", &reg);
+        if (WARN_ON(err))
+                return;
+        clk = of_clk_get_by_name(np, "cpu_1x");
+        if (WARN_ON(IS_ERR(clk)))
+                return;
+        err = clk_prepare_enable(clk);
+        if (WARN_ON(err))
+                return;
+        ttccs->xttc.base_addr = base + reg * 4;
+        ttccs->cs.name = np->name;
+        ttccs->cs.rating = 200;
+        ttccs->cs.read = __xttc_clocksource_read;
+        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
+        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
+        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
+        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
+                     ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
+        __raw_writel(CNT_CNTRL_RESET,
+                     ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
+        if (WARN_ON(err))
+                return;
+}
+static void __init zynq_ttc_setup_clockevent(struct device_node *np,
+                                            void __iomem *base)
+{
+        struct xttcpss_timer_clockevent *ttcce;
+        int err, irq;
+        u32 reg;
+        ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
+        if (WARN_ON(!ttcce))
+                return;
+        err = of_property_read_u32(np, "reg", &reg);
+        if (WARN_ON(err))
+                return;
+        ttcce->xttc.base_addr = base + reg * 4;
+        ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
+        if (WARN_ON(IS_ERR(ttcce->clk)))
+                return;
+        err = clk_prepare_enable(ttcce->clk);
+        if (WARN_ON(err))
+                return;
+        irq = irq_of_parse_and_map(np, 0);
+        if (WARN_ON(!irq))
+                return;
+        ttcce->ce.name = np->name;
+        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        ttcce->ce.set_next_event = xttcpss_set_next_event;
+        ttcce->ce.set_mode = xttcpss_set_mode;
+        ttcce->ce.rating = 200;
+        ttcce->ce.irq = irq;
+        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
+                     ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
+        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
+        err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
+                          np->name, ttcce);
+        if (WARN_ON(err))
+                return;
+        clockevents_config_and_register(&ttcce->ce,
+                                        clk_get_rate(ttcce->clk) / PRESCALE,
+                                        1, 0xfffe);
+}
+static const __initconst struct of_device_id zynq_ttc_match[] = {
+        { .compatible = "xlnx,ttc-counter-clocksource",
+                .data = zynq_ttc_setup_clocksource, },
+        { .compatible = "xlnx,ttc-counter-clockevent",
+                .data = zynq_ttc_setup_clockevent, },
+        {}
 };
 /**
@@ -269,30 +306,27 @@ static struct clock_event_device xttcpss_clockevent = {
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 **/
-static void __init xttcpss_timer_init(void)
+void __init xttcpss_timer_init(void)
 {
-        xttcpss_timer_hardware_init();
+        struct device_node *np;
-        clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE);
+        for_each_compatible_node(np, NULL, "xlnx,ttc") {
-        /* Calculate the parameters to allow the clockevent to operate using
+                struct device_node *np_chld;
-           integer math
+                void __iomem *base;
-        */
-        clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4);
+                base = of_iomap(np, 0);
+                if (WARN_ON(!base))
-        xttcpss_clockevent.max_delta_ns =
+                        return;
-                clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
-        xttcpss_clockevent.min_delta_ns =
+                for_each_available_child_of_node(np, np_chld) {
-                clockevent_delta2ns(1, &xttcpss_clockevent);
+                        int (*cb)(struct device_node *np, void __iomem *base);
+                        const struct of_device_id *match;
-        /* Indicate that clock event is on 1st CPU as SMP boot needs it */
+                        match = of_match_node(zynq_ttc_match, np_chld);
-        xttcpss_clockevent.cpumask = cpumask_of(0);
+                        if (match) {
-        clockevents_register_device(&xttcpss_clockevent);
+                                cb = match->data;
+                                cb(np_chld, base);
+                        }
+                }
+        }
 }
-/*
- * Instantiate and initialize the system timer structure
- */
-struct sys_timer xttcpss_sys_timer = {
-        .init           = xttcpss_timer_init,
-};
diff --git a/arch/arm/mm/cache-aurora-l2.h b/arch/arm/mm/cache-aurora-l2.h
new file mode 100644
index 000000000000..c86124769831
--- /dev/null
+++ b/arch/arm/mm/cache-aurora-l2.h
@@ -0,0 +1,55 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+#define AURORA_SYNC_REG             0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG      0x774
+#define AURORA_CLEAN_RANGE_REG      0x7b4
+#define AURORA_FLUSH_RANGE_REG      0x7f4
+#define AURORA_ACR_REPLACEMENT_OFFSET       27
+#define AURORA_ACR_REPLACEMENT_MASK          \
+        (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+        (0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+        (1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+        (3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET    0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK      \
+        (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS       \
+        (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY      \
+        (1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY      \
+        (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define MAX_RANGE_SIZE          1024
+#define AURORA_WAY_SIZE_SHIFT   2
+#define AURORA_CTRL_FW          0x100
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID        0x100
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 8a97e6443c62..6911b8b2745c 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-aurora-l2.h"
 #define CACHE_LINE_SIZE         32
@@ -34,14 +35,20 @@ static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
        void (*setup)(const struct device_node *, u32 *, u32 *);
        void (*save)(void);
-        void (*resume)(void);
+        struct outer_cache_fns outer_cache;
 };
+static bool of_init = false;
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
        /* wait for cache operation by line or way to complete */
@@ -168,7 +175,7 @@ static void l2x0_inv_all(void)
        /* invalidate all ways */
        raw_spin_lock_irqsave(&l2x0_lock, flags);
        /* Invalidating when L2 is enabled is a nono */
-        BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
+        BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
        cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
        cache_sync();
@@ -292,11 +299,18 @@ static void l2x0_unlock(u32 cache_id)
        int lockregs;
        int i;
-        if (cache_id == L2X0_CACHE_ID_PART_L310)
+        switch (cache_id) {
+        case L2X0_CACHE_ID_PART_L310:
                lockregs = 8;
-        else
+                break;
+        case AURORA_CACHE_ID:
+                lockregs = 4;
+                break;
+        default:
                /* L210 and unknown types */
                lockregs = 1;
+                break;
+        }
        for (i = 0; i < lockregs; i++) {
                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -312,18 +326,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
        u32 cache_id;
        u32 way_size = 0;
        int ways;
+        int way_size_shift = L2X0_WAY_SIZE_SHIFT;
        const char *type;
        l2x0_base = base;
+        if (cache_id_part_number_from_dt)
-        cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+                cache_id = cache_id_part_number_from_dt;
+        else
+                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+                        & L2X0_CACHE_ID_PART_MASK;
        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
        aux &= aux_mask;
        aux |= aux_val;
        /* Determine the number of ways */
-        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+        switch (cache_id) {
        case L2X0_CACHE_ID_PART_L310:
                if (aux & (1 << 16))
                        ways = 16;
@@ -340,6 +358,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                ways = (aux >> 13) & 0xf;
                type = "L210";
                break;
+        case AURORA_CACHE_ID:
+                sync_reg_offset = AURORA_SYNC_REG;
+                ways = (aux >> 13) & 0xf;
+                ways = 2 << ((ways + 1) >> 2);
+                way_size_shift = AURORA_WAY_SIZE_SHIFT;
+                type = "Aurora";
+                break;
        default:
                /* Assume unknown chips have 8 ways */
                ways = 8;
@@ -353,7 +379,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
         * L2 cache Size =  Way size * Number of ways
         */
        way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-        way_size = 1 << (way_size + 3);
+        way_size = 1 << (way_size + way_size_shift);
        l2x0_size = ways * way_size * SZ_1K;
        /*
@@ -361,7 +388,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
         * If you are booting from non-secure mode
         * accessing the below registers will fault.
         */
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
                /* Make sure that I&D is not locked down when starting */
                l2x0_unlock(cache_id);
@@ -371,7 +398,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                l2x0_inv_all();
                /* enable L2X0 */
-                writel_relaxed(1, l2x0_base + L2X0_CTRL);
+                writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
        }
        /* Re-read it in case some bits are reserved. */
@@ -380,13 +407,15 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
        /* Save the value for resuming. */
        l2x0_saved_regs.aux_ctrl = aux;
-        outer_cache.inv_range = l2x0_inv_range;
+        if (!of_init) {
-        outer_cache.clean_range = l2x0_clean_range;
+                outer_cache.inv_range = l2x0_inv_range;
-        outer_cache.flush_range = l2x0_flush_range;
+                outer_cache.clean_range = l2x0_clean_range;
-        outer_cache.sync = l2x0_cache_sync;
+                outer_cache.flush_range = l2x0_flush_range;
-        outer_cache.flush_all = l2x0_flush_all;
+                outer_cache.sync = l2x0_cache_sync;
-        outer_cache.inv_all = l2x0_inv_all;
+                outer_cache.flush_all = l2x0_flush_all;
-        outer_cache.disable = l2x0_disable;
+                outer_cache.inv_all = l2x0_inv_all;
+                outer_cache.disable = l2x0_disable;
+        }
        printk(KERN_INFO "%s cache controller enabled\n", type);
        printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
@@ -394,6 +423,100 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 }
 #ifdef CONFIG_OF
+static int l2_wt_override;
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+        /*
+         * Limit the number of cache lines processed at once,
+         * since cache range operations stall the CPU pipeline
+         * until completion.
+         */
+        if (end > start + MAX_RANGE_SIZE)
+                end = start + MAX_RANGE_SIZE;
+        /*
+         * Cache range operations can't straddle a page boundary.
+         */
+        if (end > PAGE_ALIGN(start+1))
+                end = PAGE_ALIGN(start+1);
+        return end;
+}
+/*
+ * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
+ * and range operations only do a TLB lookup on the start address.
+ */
+static void aurora_pa_range(unsigned long start, unsigned long end,
+                        unsigned long offset)
+{
+        unsigned long flags;
+        raw_spin_lock_irqsave(&l2x0_lock, flags);
+        writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+        writel(end, l2x0_base + offset);
+        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+        cache_sync();
+}
+static void aurora_inv_range(unsigned long start, unsigned long end)
+{
+        /*
+         * round start and end adresses up to cache line size
+         */
+        start &= ~(CACHE_LINE_SIZE - 1);
+        end = ALIGN(end, CACHE_LINE_SIZE);
+        /*
+         * Invalidate all full cache lines between 'start' and 'end'.
+         */
+        while (start < end) {
+                unsigned long range_end = calc_range_end(start, end);
+                aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+                                AURORA_INVAL_RANGE_REG);
+                start = range_end;
+        }
+}
+static void aurora_clean_range(unsigned long start, unsigned long end)
+{
+        /*
+         * If L2 is forced to WT, the L2 will always be clean and we
+         * don't need to do anything here.
+         */
+        if (!l2_wt_override) {
+                start &= ~(CACHE_LINE_SIZE - 1);
+                end = ALIGN(end, CACHE_LINE_SIZE);
+                while (start != end) {
+                        unsigned long range_end = calc_range_end(start, end);
+                        aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+                                        AURORA_CLEAN_RANGE_REG);
+                        start = range_end;
+                }
+        }
+}
+static void aurora_flush_range(unsigned long start, unsigned long end)
+{
+        if (!l2_wt_override) {
+                start &= ~(CACHE_LINE_SIZE - 1);
+                end = ALIGN(end, CACHE_LINE_SIZE);
+                while (start != end) {
+                        unsigned long range_end = calc_range_end(start, end);
+                        aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+                                        AURORA_FLUSH_RANGE_REG);
+                        start = range_end;
+                }
+        }
+}
 static void __init l2x0_of_setup(const struct device_node *np,
                                 u32 *aux_val, u32 *aux_mask)
 {
@@ -491,9 +614,15 @@ static void __init pl310_save(void)
        }
 }
+static void aurora_save(void)
+{
+        l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+        l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
 static void l2x0_resume(void)
 {
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
                /* restore aux ctrl and enable l2 */
                l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
@@ -502,7 +631,7 @@ static void l2x0_resume(void)
                l2x0_inv_all();
-                writel_relaxed(1, l2x0_base + L2X0_CTRL);
+                writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
        }
 }
@@ -510,7 +639,7 @@ static void pl310_resume(void)
 {
        u32 l2x0_revision;
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
                /* restore pl310 setup */
                writel_relaxed(l2x0_saved_regs.tag_latency,
                        l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -536,22 +665,108 @@ static void pl310_resume(void)
        l2x0_resume();
 }
+static void aurora_resume(void)
+{
+        if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+                writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+                writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+        }
+}
+static void __init aurora_broadcast_l2_commands(void)
+{
+        __u32 u;
+        /* Enable Broadcasting of cache commands to L2*/
+        __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+        u |= AURORA_CTRL_FW;            /* Set the FW bit */
+        __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+        isb();
+}
+static void __init aurora_of_setup(const struct device_node *np,
+                                u32 *aux_val, u32 *aux_mask)
+{
+        u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+        u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+        of_property_read_u32(np, "cache-id-part",
+                        &cache_id_part_number_from_dt);
+        /* Determine and save the write policy */
+        l2_wt_override = of_property_read_bool(np, "wt-override");
+        if (l2_wt_override) {
+                val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+                mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+        }
+        *aux_val &= ~mask;
+        *aux_val |= val;
+        *aux_mask &= ~mask;
+}
 static const struct l2x0_of_data pl310_data = {
-        pl310_of_setup,
+        .setup = pl310_of_setup,
-        pl310_save,
+        .save  = pl310_save,
-        pl310_resume,
+        .outer_cache = {
+                .resume      = pl310_resume,
+                .inv_range   = l2x0_inv_range,
+                .clean_range = l2x0_clean_range,
+                .flush_range = l2x0_flush_range,
+                .sync        = l2x0_cache_sync,
+                .flush_all   = l2x0_flush_all,
+                .inv_all     = l2x0_inv_all,
+                .disable     = l2x0_disable,
+                .set_debug   = pl310_set_debug,
+        },
 };
 static const struct l2x0_of_data l2x0_data = {
-        l2x0_of_setup,
+        .setup = l2x0_of_setup,
-        NULL,
+        .save  = NULL,
-        l2x0_resume,
+        .outer_cache = {
+                .resume      = l2x0_resume,
+                .inv_range   = l2x0_inv_range,
+                .clean_range = l2x0_clean_range,
+                .flush_range = l2x0_flush_range,
+                .sync        = l2x0_cache_sync,
+                .flush_all   = l2x0_flush_all,
+                .inv_all     = l2x0_inv_all,
+                .disable     = l2x0_disable,
+        },
+};
+static const struct l2x0_of_data aurora_with_outer_data = {
+        .setup = aurora_of_setup,
+        .save  = aurora_save,
+        .outer_cache = {
+                .resume      = aurora_resume,
+                .inv_range   = aurora_inv_range,
+                .clean_range = aurora_clean_range,
+                .flush_range = aurora_flush_range,
+                .sync        = l2x0_cache_sync,
+                .flush_all   = l2x0_flush_all,
+                .inv_all     = l2x0_inv_all,
+                .disable     = l2x0_disable,
+        },
+};
+static const struct l2x0_of_data aurora_no_outer_data = {
+        .setup = aurora_of_setup,
+        .save  = aurora_save,
+        .outer_cache = {
+                .resume      = aurora_resume,
+        },
 };
 static const struct of_device_id l2x0_ids[] __initconst = {
        { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
        { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
        { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+        { .compatible = "marvell,aurora-system-cache",
+          .data = (void *)&aurora_no_outer_data},
+        { .compatible = "marvell,aurora-outer-cache",
+          .data = (void *)&aurora_with_outer_data},
        {}
 };
@@ -577,17 +792,24 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
        data = of_match_node(l2x0_ids, np)->data;
        /* L2 configuration can only be changed if the cache is disabled */
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
                if (data->setup)
                        data->setup(np, &aux_val, &aux_mask);
+                /* For aurora cache in no outer mode select the
+                 * correct mode using the coprocessor*/
+                if (data == &aurora_no_outer_data)
+                        aurora_broadcast_l2_commands();
        }
        if (data->save)
                data->save();
+        of_init = true;
        l2x0_init(l2x0_base, aux_val, aux_mask);
-        outer_cache.resume = data->resume;
+        memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
        return 0;
 }
 #endif
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 4e07eec1270d..bc4a5e9ebb78 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -2,6 +2,9 @@
 *  linux/arch/arm/mm/context.c
 *
 *  Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
+ *  Copyright (C) 2012 ARM Limited
+ *
+ *  Author: Will Deacon <will.deacon@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -14,14 +17,40 @@
 #include <linux/percpu.h>
 #include <asm/mmu_context.h>
+#include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+/*
+ * On ARMv6, we have the following structure in the Context ID:
+ *
+ * 31                         7          0
+ * +-------------------------+-----------+
+ * |      process ID         |   ASID    |
+ * +-------------------------+-----------+
+ * |              context ID             |
+ * +-------------------------------------+
+ *
+ * The ASID is used to tag entries in the CPU caches and TLBs.
+ * The context ID is used by debuggers and trace logic, and
+ * should be unique within all running processes.
+ */
+#define ASID_FIRST_VERSION      (1ULL << ASID_BITS)
+#define NUM_USER_ASIDS          (ASID_FIRST_VERSION - 1)
+#define ASID_TO_IDX(asid)       ((asid & ~ASID_MASK) - 1)
+#define IDX_TO_ASID(idx)        ((idx + 1) & ~ASID_MASK)
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
-unsigned int cpu_last_asid = ASID_FIRST_VERSION;
+static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
+static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
+static DEFINE_PER_CPU(atomic64_t, active_asids);
+static DEFINE_PER_CPU(u64, reserved_asids);
+static cpumask_t tlb_flush_pending;
 #ifdef CONFIG_ARM_LPAE
-void cpu_set_reserved_ttbr0(void)
+static void cpu_set_reserved_ttbr0(void)
 {
        unsigned long ttbl = __pa(swapper_pg_dir);
        unsigned long ttbh = 0;
@@ -37,7 +66,7 @@ void cpu_set_reserved_ttbr0(void)
        isb();
 }
 #else
-void cpu_set_reserved_ttbr0(void)
+static void cpu_set_reserved_ttbr0(void)
 {
        u32 ttb;
        /* Copy TTBR1 into TTBR0 */
@@ -84,124 +113,104 @@ static int __init contextidr_notifier_init(void)
 arch_initcall(contextidr_notifier_init);
 #endif
-/*
+static void flush_context(unsigned int cpu)
- * We fork()ed a process, and we need a new context for the child
- * to run in.
- */
-void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
-        mm->context.id = 0;
+        int i;
-        raw_spin_lock_init(&mm->context.id_lock);
+        u64 asid;
-}
+        /* Update the list of reserved ASIDs and the ASID bitmap. */
+        bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
+        for_each_possible_cpu(i) {
+                if (i == cpu) {
+                        asid = 0;
+                } else {
+                        asid = atomic64_xchg(&per_cpu(active_asids, i), 0);
+                        __set_bit(ASID_TO_IDX(asid), asid_map);
+                }
+                per_cpu(reserved_asids, i) = asid;
+        }
-static void flush_context(void)
+        /* Queue a TLB invalidate and flush the I-cache if necessary. */
-{
+        if (!tlb_ops_need_broadcast())
-        cpu_set_reserved_ttbr0();
+                cpumask_set_cpu(cpu, &tlb_flush_pending);
-        local_flush_tlb_all();
+        else
-        if (icache_is_vivt_asid_tagged()) {
+                cpumask_setall(&tlb_flush_pending);
+        if (icache_is_vivt_asid_tagged())
                __flush_icache_all();
-                dsb();
-        }
 }
-#ifdef CONFIG_SMP
+static int is_reserved_asid(u64 asid)
+{
+        int cpu;
+        for_each_possible_cpu(cpu)
+                if (per_cpu(reserved_asids, cpu) == asid)
+                        return 1;
+        return 0;
+}
-static void set_mm_context(struct mm_struct *mm, unsigned int asid)
+static void new_context(struct mm_struct *mm, unsigned int cpu)
 {
-        unsigned long flags;
+        u64 asid = mm->context.id;
+        u64 generation = atomic64_read(&asid_generation);
-        /*
+        if (asid != 0 && is_reserved_asid(asid)) {
-         * Locking needed for multi-threaded applications where the
-         * same mm->context.id could be set from different CPUs during
-         * the broadcast. This function is also called via IPI so the
-         * mm->context.id_lock has to be IRQ-safe.
-         */
-        raw_spin_lock_irqsave(&mm->context.id_lock, flags);
-        if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) {
                /*
-                 * Old version of ASID found. Set the new one and
+                 * Our current ASID was active during a rollover, we can
-                 * reset mm_cpumask(mm).
+                 * continue to use it and this was just a false alarm.
                 */
-                mm->context.id = asid;
+                asid = generation | (asid & ~ASID_MASK);
+        } else {
+                /*
+                 * Allocate a free ASID. If we can't find one, take a
+                 * note of the currently active ASIDs and mark the TLBs
+                 * as requiring flushes.
+                 */
+                asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                if (asid == NUM_USER_ASIDS) {
+                        generation = atomic64_add_return(ASID_FIRST_VERSION,
+                                                         &asid_generation);
+                        flush_context(cpu);
+                        asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                }
+                __set_bit(asid, asid_map);
+                asid = generation | IDX_TO_ASID(asid);
                cpumask_clear(mm_cpumask(mm));
        }
-        raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
-        /*
+        mm->context.id = asid;
-         * Set the mm_cpumask(mm) bit for the current CPU.
-         */
-        cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
 }
-/*
+void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
- * Reset the ASID on the current CPU. This function call is broadcast
- * from the CPU handling the ASID rollover and holding cpu_asid_lock.
- */
-static void reset_context(void *info)
 {
-        unsigned int asid;
+        unsigned long flags;
        unsigned int cpu = smp_processor_id();
-        struct mm_struct *mm = current->active_mm;
-        smp_rmb();
+        if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
-        asid = cpu_last_asid + cpu + 1;
+                __check_vmalloc_seq(mm);
-        flush_context();
+        /*
-        set_mm_context(mm, asid);
+         * Required during context switch to avoid speculative page table
+         * walking with the wrong TTBR.
-        /* set the new ASID */
+         */
-        cpu_switch_mm(mm->pgd, mm);
+        cpu_set_reserved_ttbr0();
-}
-#else
+        if (!((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
+            && atomic64_xchg(&per_cpu(active_asids, cpu), mm->context.id))
+                goto switch_mm_fastpath;
-static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
+        raw_spin_lock_irqsave(&cpu_asid_lock, flags);
-{
+        /* Check that our ASID belongs to the current generation. */
-        mm->context.id = asid;
+        if ((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
-        cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
+                new_context(mm, cpu);
-}
-#endif
+        atomic64_set(&per_cpu(active_asids, cpu), mm->context.id);
+        cpumask_set_cpu(cpu, mm_cpumask(mm));
-void __new_context(struct mm_struct *mm)
+        if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
-{
+                local_flush_tlb_all();
-        unsigned int asid;
+        raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
-        raw_spin_lock(&cpu_asid_lock);
+switch_mm_fastpath:
-#ifdef CONFIG_SMP
+        cpu_switch_mm(mm->pgd, mm);
-        /*
-         * Check the ASID again, in case the change was broadcast from
-         * another CPU before we acquired the lock.
-         */
-        if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) {
-                cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
-                raw_spin_unlock(&cpu_asid_lock);
-                return;
-        }
-#endif
-        /*
-         * At this point, it is guaranteed that the current mm (with
-         * an old ASID) isn't active on any other CPU since the ASIDs
-         * are changed simultaneously via IPI.
-         */
-        asid = ++cpu_last_asid;
-        if (asid == 0)
-                asid = cpu_last_asid = ASID_FIRST_VERSION;
-        /*
-         * If we've used up all our ASIDs, we need
-         * to start a new version and flush the TLB.
-         */
-        if (unlikely((asid & ~ASID_MASK) == 0)) {
-                asid = cpu_last_asid + smp_processor_id() + 1;
-                flush_context();
-#ifdef CONFIG_SMP
-                smp_wmb();
-                smp_call_function(reset_context, NULL, 1);
-#endif
-                cpu_last_asid += NR_CPUS;
-        }
-        set_mm_context(mm, asid);
-        raw_spin_unlock(&cpu_asid_lock);
 }
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index ab88ed4f8e08..99db769307ec 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -92,6 +92,9 @@ static int __init init_static_idmap(void)
                (long long)idmap_start, (long long)idmap_end);
        identity_mapping_add(idmap_pgd, idmap_start, idmap_end);
+        /* Flush L1 for the hardware to see this page table content */
+        flush_cache_louis();
        return 0;
 }
 early_initcall(init_static_idmap);
@@ -103,12 +106,15 @@ early_initcall(init_static_idmap);
 */
 void setup_mm_for_reboot(void)
 {
-        /* Clean and invalidate L1. */
-        flush_cache_all();
        /* Switch to the identity mapping. */
        cpu_switch_mm(idmap_pgd, &init_mm);
-        /* Flush the TLB. */
+#ifdef CONFIG_CPU_HAS_ASID
+        /*
+         * We don't have a clean ASID for the identity mapping, which
+         * may clash with virtual addresses of the previous page tables
+         * and therefore potentially in the TLB.
+         */
        local_flush_tlb_all();
+#endif
 }
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 5dcc2fd46c46..88fd86cf3d9a 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -47,18 +47,18 @@ int ioremap_page(unsigned long virt, unsigned long phys,
 }
 EXPORT_SYMBOL(ioremap_page);
-void __check_kvm_seq(struct mm_struct *mm)
+void __check_vmalloc_seq(struct mm_struct *mm)
 {
        unsigned int seq;
        do {
-                seq = init_mm.context.kvm_seq;
+                seq = init_mm.context.vmalloc_seq;
                memcpy(pgd_offset(mm, VMALLOC_START),
                       pgd_offset_k(VMALLOC_START),
                       sizeof(pgd_t) * (pgd_index(VMALLOC_END) -
                                        pgd_index(VMALLOC_START)));
-                mm->context.kvm_seq = seq;
+                mm->context.vmalloc_seq = seq;
-        } while (seq != init_mm.context.kvm_seq);
+        } while (seq != init_mm.context.vmalloc_seq);
 }
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
@@ -89,13 +89,13 @@ static void unmap_area_sections(unsigned long virt, unsigned long size)
                if (!pmd_none(pmd)) {
                        /*
                         * Clear the PMD from the page table, and
-                         * increment the kvm sequence so others
+                         * increment the vmalloc sequence so others
                         * notice this change.
                         *
                         * Note: this is still racy on SMP machines.
                         */
                        pmd_clear(pmdp);
-                        init_mm.context.kvm_seq++;
+                        init_mm.context.vmalloc_seq++;
                        /*
                         * Free the page table, if there was one.
@@ -112,8 +112,8 @@ static void unmap_area_sections(unsigned long virt, unsigned long size)
         * Ensure that the active_mm is up to date - we want to
         * catch any use-after-iounmap cases.
         */
-        if (current->active_mm->context.kvm_seq != init_mm.context.kvm_seq)
+        if (current->active_mm->context.vmalloc_seq != init_mm.context.vmalloc_seq)
-                __check_kvm_seq(current->active_mm);
+                __check_vmalloc_seq(current->active_mm);
        flush_tlb_kernel_range(virt, end);
 }
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index ce8cb1970d7a..10062ceadd1c 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -11,18 +11,6 @@
 #include <linux/random.h>
 #include <asm/cachetype.h>
-static inline unsigned long COLOUR_ALIGN_DOWN(unsigned long addr,
-                                              unsigned long pgoff)
-{
-        unsigned long base = addr & ~(SHMLBA-1);
-        unsigned long off = (pgoff << PAGE_SHIFT) & (SHMLBA-1);
-        if (base + off <= addr)
-                return base + off;
-        return base - off;
-}
 #define COLOUR_ALIGN(addr,pgoff)                \
        ((((addr)+SHMLBA-1)&~(SHMLBA-1)) +      \
         (((pgoff)<<PAGE_SHIFT) & (SHMLBA-1)))
@@ -69,9 +57,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
 {
        struct mm_struct *mm = current->mm;
        struct vm_area_struct *vma;
-        unsigned long start_addr;
        int do_align = 0;
        int aliasing = cache_is_vipt_aliasing();
+        struct vm_unmapped_area_info info;
        /*
         * We only need to do colour alignment if either the I or D
@@ -104,46 +92,14 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
                    (!vma || addr + len <= vma->vm_start))
                        return addr;
        }
-        if (len > mm->cached_hole_size) {
-                start_addr = addr = mm->free_area_cache;
-        } else {
-                start_addr = addr = mm->mmap_base;
-                mm->cached_hole_size = 0;
-        }
-full_search:
+        info.flags = 0;
-        if (do_align)
+        info.length = len;
-                addr = COLOUR_ALIGN(addr, pgoff);
+        info.low_limit = mm->mmap_base;
-        else
+        info.high_limit = TASK_SIZE;
-                addr = PAGE_ALIGN(addr);
+        info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
+        info.align_offset = pgoff << PAGE_SHIFT;
-        for (vma = find_vma(mm, addr); ; vma = vma->vm_next) {
+        return vm_unmapped_area(&info);
-                /* At this point:  (!vma || addr < vma->vm_end). */
-                if (TASK_SIZE - len < addr) {
-                        /*
-                         * Start a new search - just in case we missed
-                         * some holes.
-                         */
-                        if (start_addr != TASK_UNMAPPED_BASE) {
-                                start_addr = addr = TASK_UNMAPPED_BASE;
-                                mm->cached_hole_size = 0;
-                                goto full_search;
-                        }
-                        return -ENOMEM;
-                }
-                if (!vma || addr + len <= vma->vm_start) {
-                        /*
-                         * Remember the place where we stopped the search:
-                         */
-                        mm->free_area_cache = addr + len;
-                        return addr;
-                }
-                if (addr + mm->cached_hole_size < vma->vm_start)
-                        mm->cached_hole_size = vma->vm_start - addr;
-                addr = vma->vm_end;
-                if (do_align)
-                        addr = COLOUR_ALIGN(addr, pgoff);
-        }
 }
 unsigned long
@@ -156,6 +112,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
        unsigned long addr = addr0;
        int do_align = 0;
        int aliasing = cache_is_vipt_aliasing();
+        struct vm_unmapped_area_info info;
        /*
         * We only need to do colour alignment if either the I or D
@@ -187,70 +144,27 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
                        return addr;
        }
-        /* check if free_area_cache is useful for us */
+        info.flags = VM_UNMAPPED_AREA_TOPDOWN;
-        if (len <= mm->cached_hole_size) {
+        info.length = len;
-                mm->cached_hole_size = 0;
+        info.low_limit = PAGE_SIZE;
-                mm->free_area_cache = mm->mmap_base;
+        info.high_limit = mm->mmap_base;
-        }
+        info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
+        info.align_offset = pgoff << PAGE_SHIFT;
-        /* either no address requested or can't fit in requested address hole */
+        addr = vm_unmapped_area(&info);
-        addr = mm->free_area_cache;
-        if (do_align) {
-                unsigned long base = COLOUR_ALIGN_DOWN(addr - len, pgoff);
-                addr = base + len;
-        }
-        /* make sure it can fit in the remaining address space */
-        if (addr > len) {
-                vma = find_vma(mm, addr-len);
-                if (!vma || addr <= vma->vm_start)
-                        /* remember the address as a hint for next time */
-                        return (mm->free_area_cache = addr-len);
-        }
-        if (mm->mmap_base < len)
-                goto bottomup;
-        addr = mm->mmap_base - len;
-        if (do_align)
-                addr = COLOUR_ALIGN_DOWN(addr, pgoff);
-        do {
-                /*
-                 * Lookup failure means no vma is above this address,
-                 * else if new region fits below vma->vm_start,
-                 * return with success:
-                 */
-                vma = find_vma(mm, addr);
-                if (!vma || addr+len <= vma->vm_start)
-                        /* remember the address as a hint for next time */
-                        return (mm->free_area_cache = addr);
-                /* remember the largest hole we saw so far */
-                if (addr + mm->cached_hole_size < vma->vm_start)
-                        mm->cached_hole_size = vma->vm_start - addr;
-                /* try just below the current vma->vm_start */
-                addr = vma->vm_start - len;
-                if (do_align)
-                        addr = COLOUR_ALIGN_DOWN(addr, pgoff);
-        } while (len < vma->vm_start);
-bottomup:
        /*
         * A failed mmap() very likely causes application failure,
         * so fall back to the bottom-up function here. This scenario
         * can happen with large stack limits and large mmap()
         * allocations.
         */
-        mm->cached_hole_size = ~0UL;
+        if (addr & ~PAGE_MASK) {
-        mm->free_area_cache = TASK_UNMAPPED_BASE;
+                VM_BUG_ON(addr != -ENOMEM);
-        addr = arch_get_unmapped_area(filp, addr0, len, pgoff, flags);
+                info.flags = 0;
-        /*
+                info.low_limit = mm->mmap_base;
-         * Restore the topdown base:
+                info.high_limit = TASK_SIZE;
-         */
+                addr = vm_unmapped_area(&info);
-        mm->free_area_cache = mm->mmap_base;
+        }
-        mm->cached_hole_size = ~0UL;
        return addr;
 }
@@ -279,7 +193,7 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
 * You really shouldn't be using read() or write() on /dev/mem.  This
 * might go away in the future.
 */
-int valid_phys_addr_range(unsigned long addr, size_t size)
+int valid_phys_addr_range(phys_addr_t addr, size_t size)
 {
        if (addr < PHYS_OFFSET)
                return 0;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 941dfb9e9a78..9f0610243bd6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -488,7 +488,7 @@ static void __init build_mem_type_table(void)
 #endif
        for (i = 0; i < 16; i++) {
-                unsigned long v = pgprot_val(protection_map[i]);
+                pteval_t v = pgprot_val(protection_map[i]);
                protection_map[i] = __pgprot(v | user_pgprot);
        }
@@ -876,6 +876,22 @@ static void __init pci_reserve_io(void)
 #define pci_reserve_io() do { } while (0)
 #endif
+#ifdef CONFIG_DEBUG_LL
+void __init debug_ll_io_init(void)
+{
+        struct map_desc map;
+        debug_ll_addr(&map.pfn, &map.virtual);
+        if (!map.pfn || !map.virtual)
+                return;
+        map.pfn = __phys_to_pfn(map.pfn);
+        map.virtual &= PAGE_MASK;
+        map.length = PAGE_SIZE;
+        map.type = MT_DEVICE;
+        create_mapping(&map);
+}
+#endif
 static void * __initdata vmalloc_min =
        (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b29a2265af01..eb6aa73bc8b7 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -167,6 +167,10 @@
        tst     r1, #L_PTE_YOUNG
        tstne   r1, #L_PTE_PRESENT
        moveq   r3, #0
+#ifndef CONFIG_CPU_USE_DOMAINS
+        tstne   r1, #L_PTE_NONE
+        movne   r3, #0
+#endif
        str     r3, [r0]
        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 86b8b480634f..09c5233f4dfc 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -89,7 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area)
        mov     pc, lr
 /*
- *      cpu_arm926_switch_mm(pgd_phys, tsk)
+ *      cpu_v6_switch_mm(pgd_phys, tsk)
 *
 *      Set the translation table base pointer to be pgd_phys
 *
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index fd045e706390..6d98c13ab827 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -100,7 +100,11 @@ ENTRY(cpu_v7_set_pte_ext)
        orrne   r3, r3, #PTE_EXT_XN
        tst     r1, #L_PTE_YOUNG
-        tstne   r1, #L_PTE_PRESENT
+        tstne   r1, #L_PTE_VALID
+#ifndef CONFIG_CPU_USE_DOMAINS
+        eorne   r1, r1, #L_PTE_NONE
+        tstne   r1, #L_PTE_NONE
+#endif
        moveq   r3, #0
 ARM(   str     r3, [r0, #2048]! )
@@ -161,11 +165,11 @@ ENDPROC(cpu_v7_set_pte_ext)
         *  TFR   EV X F   I D LR    S
         * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
         * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
-         *    1    0 110       0011 1100 .111 1101 < we want
+         *   01    0 110       0011 1100 .111 1101 < we want
         */
        .align  2
        .type   v7_crval, #object
 v7_crval:
-        crval   clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
+        crval   clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
        .previous
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 8de0f1dd1549..7b56386f9496 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -65,8 +65,11 @@ ENDPROC(cpu_v7_switch_mm)
 */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
-        tst     r2, #L_PTE_PRESENT
+        tst     r2, #L_PTE_VALID
        beq     1f
+        tst     r3, #1 << (57 - 32)             @ L_PTE_NONE
+        bicne   r2, #L_PTE_VALID
+        bne     1f
        tst     r3, #1 << (55 - 32)             @ L_PTE_DIRTY
        orreq   r2, #L_PTE_RDONLY
 1:      strd    r2, r3, [r0]
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7cd0028cab8e..350f6a74992b 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -57,7 +57,7 @@ ENTRY(cpu_v7_reset)
 THUMB( bic     r1, r1, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
        mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
        isb
-        mov     pc, r0
+        bx      r0
 ENDPROC(cpu_v7_reset)
        .popsection
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index c641fb685017..a34f1e214116 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -16,6 +16,7 @@
 #include <linux/netdevice.h>
 #include <linux/string.h>
 #include <linux/slab.h>
+#include <linux/if_vlan.h>
 #include <asm/cacheflush.h>
 #include <asm/hwcap.h>
@@ -42,7 +43,7 @@
 #define r_skb_hl        ARM_R8
 #define SCRATCH_SP_OFFSET       0
-#define SCRATCH_OFF(k)          (SCRATCH_SP_OFFSET + (k))
+#define SCRATCH_OFF(k)          (SCRATCH_SP_OFFSET + 4 * (k))
 #define SEEN_MEM                ((1 << BPF_MEMWORDS) - 1)
 #define SEEN_MEM_WORD(k)        (1 << (k))
@@ -168,6 +169,8 @@ static inline bool is_load_to_a(u16 inst)
        case BPF_S_ANC_MARK:
        case BPF_S_ANC_PROTOCOL:
        case BPF_S_ANC_RXHASH:
+        case BPF_S_ANC_VLAN_TAG:
+        case BPF_S_ANC_VLAN_TAG_PRESENT:
        case BPF_S_ANC_QUEUE:
                return true;
        default:
@@ -646,6 +649,16 @@ load_ind:
                        update_on_xread(ctx);
                        emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
                        break;
+                case BPF_S_ALU_XOR_K:
+                        /* A ^= K; */
+                        OP_IMM3(ARM_EOR, r_A, r_A, k, ctx);
+                        break;
+                case BPF_S_ANC_ALU_XOR_X:
+                case BPF_S_ALU_XOR_X:
+                        /* A ^= X */
+                        update_on_xread(ctx);
+                        emit(ARM_EOR_R(r_A, r_A, r_X), ctx);
+                        break;
                case BPF_S_ALU_AND_K:
                        /* A &= K */
                        OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
@@ -762,11 +775,6 @@ b_epilogue:
                        update_on_xread(ctx);
                        emit(ARM_MOV_R(r_A, r_X), ctx);
                        break;
-                case BPF_S_ANC_ALU_XOR_X:
-                        /* A ^= X */
-                        update_on_xread(ctx);
-                        emit(ARM_EOR_R(r_A, r_A, r_X), ctx);
-                        break;
                case BPF_S_ANC_PROTOCOL:
                        /* A = ntohs(skb->protocol) */
                        ctx->seen |= SEEN_SKB;
@@ -810,6 +818,17 @@ b_epilogue:
                        off = offsetof(struct sk_buff, rxhash);
                        emit(ARM_LDR_I(r_A, r_skb, off), ctx);
                        break;
+                case BPF_S_ANC_VLAN_TAG:
+                case BPF_S_ANC_VLAN_TAG_PRESENT:
+                        ctx->seen |= SEEN_SKB;
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, vlan_tci) != 2);
+                        off = offsetof(struct sk_buff, vlan_tci);
+                        emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
+                        if (inst->code == BPF_S_ANC_VLAN_TAG)
+                                OP_IMM3(ARM_AND, r_A, r_A, VLAN_VID_MASK, ctx);
+                        else
+                                OP_IMM3(ARM_AND, r_A, r_A, VLAN_TAG_PRESENT, ctx);
+                        break;
                case BPF_S_ANC_QUEUE:
                        ctx->seen |= SEEN_SKB;
                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
@@ -845,7 +864,7 @@ void bpf_jit_compile(struct sk_filter *fp)
        ctx.skf         = fp;
        ctx.ret0_fp_idx = -1;
-        ctx.offsets = kzalloc(GFP_KERNEL, 4 * (ctx.skf->len + 1));
+        ctx.offsets = kzalloc(4 * (ctx.skf->len + 1), GFP_KERNEL);
        if (ctx.offsets == NULL)
                return;
@@ -864,7 +883,7 @@ void bpf_jit_compile(struct sk_filter *fp)
        ctx.idx += ctx.imm_count;
        if (ctx.imm_count) {
-                ctx.imms = kzalloc(GFP_KERNEL, 4 * ctx.imm_count);
+                ctx.imms = kzalloc(4 * ctx.imm_count, GFP_KERNEL);
                if (ctx.imms == NULL)
                        goto out;
        }
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index 7fa2f7d3cb90..afb84621ff6f 100644
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -69,6 +69,7 @@
 #define ARM_INST_CMP_I          0x03500000
 #define ARM_INST_EOR_R          0x00200000
+#define ARM_INST_EOR_I          0x02200000
 #define ARM_INST_LDRB_I         0x05d00000
 #define ARM_INST_LDRB_R         0x07d00000
@@ -135,6 +136,7 @@
 #define ARM_CMP_I(rn, imm)      _AL3_I(ARM_INST_CMP, 0, rn, imm)
 #define ARM_EOR_R(rd, rn, rm)   _AL3_R(ARM_INST_EOR, rd, rn, rm)
+#define ARM_EOR_I(rd, rn, imm)  _AL3_I(ARM_INST_EOR, rd, rn, imm)
 #define ARM_LDR_I(rt, rn, off)  (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
                                 | (off))
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
deleted file mode 100644
index 88e1e2e7a20d..000000000000
--- a/arch/arm/plat-mxc/Kconfig
+++ /dev/null
@@ -1,89 +0,0 @@
-if ARCH_MXC
-source "arch/arm/plat-mxc/devices/Kconfig"
-menu "Freescale MXC Implementations"
-choice
-        prompt "Freescale CPU family:"
-        default ARCH_IMX_V6_V7
-config ARCH_IMX_V4_V5
-        bool "i.MX1, i.MX21, i.MX25, i.MX27"
-        select ARM_PATCH_PHYS_VIRT
-        select AUTO_ZRELADDR if !ZBOOT_ROM
-        help
-          This enables support for systems based on the Freescale i.MX ARMv4
-          and ARMv5 SoCs
-config ARCH_IMX_V6_V7
-        bool "i.MX3, i.MX5, i.MX6"
-        select ARM_PATCH_PHYS_VIRT
-        select AUTO_ZRELADDR if !ZBOOT_ROM
-        select MIGHT_HAVE_CACHE_L2X0
-        help
-          This enables support for systems based on the Freescale i.MX3, i.MX5
-          and i.MX6 family.
-endchoice
-source "arch/arm/mach-imx/Kconfig"
-endmenu
-config MXC_IRQ_PRIOR
-        bool "Use IRQ priority"
-        help
-          Select this if you want to use prioritized IRQ handling.
-          This feature prevents higher priority ISR to be interrupted
-          by lower priority IRQ even IRQF_DISABLED flag is not set.
-          This may be useful in embedded applications, where are strong
-          requirements for timing.
-          Say N here, unless you have a specialized requirement.
-config MXC_TZIC
-        bool
-config MXC_AVIC
-        bool
-config MXC_DEBUG_BOARD
-        bool "Enable MXC debug board(for 3-stack)"
-        help
-          The debug board is an integral part of the MXC 3-stack(PDK)
-          platforms, it can be attached or removed from the peripheral
-          board. On debug board, several debug devices(ethernet, UART,
-          buttons, LEDs and JTAG) are implemented. Between the MCU and
-          these devices, a CPLD is added as a bridge which performs
-          data/address de-multiplexing and decode, signal level shift,
-          interrupt control and various board functions.
-config HAVE_EPIT
-        bool
-config MXC_USE_EPIT
-        bool "Use EPIT instead of GPT"
-        depends on HAVE_EPIT
-        help
-          Use EPIT as the system timer on systems that have it. Normally you
-          don't have a reason to do so as the EPIT has the same features and
-          uses the same clocks as the GPT. Anyway, on some systems the GPT
-          may be in use for other purposes.
-config MXC_ULPI
-        bool
-config ARCH_HAS_RNGA
-        bool
-config IMX_HAVE_IOMUX_V1
-        bool
-config ARCH_MXC_IOMUX_V3
-        bool
-config IRAM_ALLOC
-        bool
-        select GENERIC_ALLOCATOR
-endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
deleted file mode 100644
index 149237e24850..000000000000
--- a/arch/arm/plat-mxc/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-# Common support
-obj-y := time.o devices.o cpu.o system.o irq-common.o
-obj-$(CONFIG_MXC_TZIC) += tzic.o
-obj-$(CONFIG_MXC_AVIC) += avic.o
-obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
-obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
-obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
-obj-$(CONFIG_MXC_ULPI) += ulpi.o
-obj-$(CONFIG_MXC_USE_EPIT) += epit.o
-obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
-obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
-ifdef CONFIG_SND_IMX_SOC
-obj-y += ssi-fiq.o
-obj-y += ssi-fiq-ksym.o
-endif
-obj-y += devices/
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-emma.c b/arch/arm/plat-mxc/devices/platform-mx2-emma.c
new file mode 100644
index 000000000000..508404ddd4ea
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx2-emma.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#define imx_mx2_emmaprp_data_entry_single(soc)                          \
+        {                                                               \
+                .iobase = soc ## _EMMAPRP_BASE_ADDR,                    \
+                .iosize = SZ_32,                                        \
+                .irq = soc ## _INT_EMMAPRP,                             \
+        }
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mx2_emma_data imx27_mx2_emmaprp_data __initconst =
+        imx_mx2_emmaprp_data_entry_single(MX27);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+struct platform_device *__init imx_add_mx2_emmaprp(
+                const struct imx_mx2_emma_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
+                        res, 2, NULL, 0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
deleted file mode 100644
index 761e45f9456f..000000000000
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/* arch/arm/mach-imx/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <mach/hardware.h>
-#ifdef CONFIG_DEBUG_IMX1_UART
-#define UART_PADDR      MX1_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX25_UART)
-#define UART_PADDR      MX25_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
-#define UART_PADDR      MX2x_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
-#define UART_PADDR      MX3x_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX51_UART)
-#define UART_PADDR      MX51_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
-#define UART_PADDR      MX53_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX6Q_UART2)
-#define UART_PADDR      MX6Q_UART2_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
-#define UART_PADDR      MX6Q_UART4_BASE_ADDR
-#endif
-#define UART_VADDR      IMX_IO_ADDRESS(UART_PADDR)
-                .macro  addruart, rp, rv, tmp
-                ldr     \rp, =UART_PADDR        @ physical
-                ldr     \rv, =UART_VADDR        @ virtual
-                .endm
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x40]       @ TXDATA
-                .endm
-                .macro  waituart,rd,rx
-                .endm
-                .macro  busyuart,rd,rx
-1002:           ldr     \rd, [\rx, #0x98]       @ SR2
-                tst     \rd, #1 << 3            @ TXDC
-                beq     1002b                   @ wait until transmit done
-                .endm
diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h
deleted file mode 100644
index 539e559d18b2..000000000000
--- a/arch/arm/plat-mxc/include/mach/ipu.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2008
- * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- *
- * Copyright (C) 2005-2007 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _IPU_H_
-#define _IPU_H_
-#include <linux/types.h>
-#include <linux/dmaengine.h>
-/* IPU DMA Controller channel definitions. */
-enum ipu_channel {
-        IDMAC_IC_0 = 0,         /* IC (encoding task) to memory */
-        IDMAC_IC_1 = 1,         /* IC (viewfinder task) to memory */
-        IDMAC_ADC_0 = 1,
-        IDMAC_IC_2 = 2,
-        IDMAC_ADC_1 = 2,
-        IDMAC_IC_3 = 3,
-        IDMAC_IC_4 = 4,
-        IDMAC_IC_5 = 5,
-        IDMAC_IC_6 = 6,
-        IDMAC_IC_7 = 7,         /* IC (sensor data) to memory */
-        IDMAC_IC_8 = 8,
-        IDMAC_IC_9 = 9,
-        IDMAC_IC_10 = 10,
-        IDMAC_IC_11 = 11,
-        IDMAC_IC_12 = 12,
-        IDMAC_IC_13 = 13,
-        IDMAC_SDC_0 = 14,       /* Background synchronous display data */
-        IDMAC_SDC_1 = 15,       /* Foreground data (overlay) */
-        IDMAC_SDC_2 = 16,
-        IDMAC_SDC_3 = 17,
-        IDMAC_ADC_2 = 18,
-        IDMAC_ADC_3 = 19,
-        IDMAC_ADC_4 = 20,
-        IDMAC_ADC_5 = 21,
-        IDMAC_ADC_6 = 22,
-        IDMAC_ADC_7 = 23,
-        IDMAC_PF_0 = 24,
-        IDMAC_PF_1 = 25,
-        IDMAC_PF_2 = 26,
-        IDMAC_PF_3 = 27,
-        IDMAC_PF_4 = 28,
-        IDMAC_PF_5 = 29,
-        IDMAC_PF_6 = 30,
-        IDMAC_PF_7 = 31,
-};
-/* Order significant! */
-enum ipu_channel_status {
-        IPU_CHANNEL_FREE,
-        IPU_CHANNEL_INITIALIZED,
-        IPU_CHANNEL_READY,
-        IPU_CHANNEL_ENABLED,
-};
-#define IPU_CHANNELS_NUM 32
-enum pixel_fmt {
-        /* 1 byte */
-        IPU_PIX_FMT_GENERIC,
-        IPU_PIX_FMT_RGB332,
-        IPU_PIX_FMT_YUV420P,
-        IPU_PIX_FMT_YUV422P,
-        IPU_PIX_FMT_YUV420P2,
-        IPU_PIX_FMT_YVU422P,
-        /* 2 bytes */
-        IPU_PIX_FMT_RGB565,
-        IPU_PIX_FMT_RGB666,
-        IPU_PIX_FMT_BGR666,
-        IPU_PIX_FMT_YUYV,
-        IPU_PIX_FMT_UYVY,
-        /* 3 bytes */
-        IPU_PIX_FMT_RGB24,
-        IPU_PIX_FMT_BGR24,
-        /* 4 bytes */
-        IPU_PIX_FMT_GENERIC_32,
-        IPU_PIX_FMT_RGB32,
-        IPU_PIX_FMT_BGR32,
-        IPU_PIX_FMT_ABGR32,
-        IPU_PIX_FMT_BGRA32,
-        IPU_PIX_FMT_RGBA32,
-};
-enum ipu_color_space {
-        IPU_COLORSPACE_RGB,
-        IPU_COLORSPACE_YCBCR,
-        IPU_COLORSPACE_YUV
-};
-/*
- * Enumeration of IPU rotation modes
- */
-enum ipu_rotate_mode {
-        /* Note the enum values correspond to BAM value */
-        IPU_ROTATE_NONE = 0,
-        IPU_ROTATE_VERT_FLIP = 1,
-        IPU_ROTATE_HORIZ_FLIP = 2,
-        IPU_ROTATE_180 = 3,
-        IPU_ROTATE_90_RIGHT = 4,
-        IPU_ROTATE_90_RIGHT_VFLIP = 5,
-        IPU_ROTATE_90_RIGHT_HFLIP = 6,
-        IPU_ROTATE_90_LEFT = 7,
-};
-/*
- * Enumeration of DI ports for ADC.
- */
-enum display_port {
-        DISP0,
-        DISP1,
-        DISP2,
-        DISP3
-};
-struct idmac_video_param {
-        unsigned short          in_width;
-        unsigned short          in_height;
-        uint32_t                in_pixel_fmt;
-        unsigned short          out_width;
-        unsigned short          out_height;
-        uint32_t                out_pixel_fmt;
-        unsigned short          out_stride;
-        bool                    graphics_combine_en;
-        bool                    global_alpha_en;
-        bool                    key_color_en;
-        enum display_port       disp;
-        unsigned short          out_left;
-        unsigned short          out_top;
-};
-/*
- * Union of initialization parameters for a logical channel. So far only video
- * parameters are used.
- */
-union ipu_channel_param {
-        struct idmac_video_param video;
-};
-struct idmac_tx_desc {
-        struct dma_async_tx_descriptor  txd;
-        struct scatterlist              *sg;    /* scatterlist for this */
-        unsigned int                    sg_len; /* tx-descriptor. */
-        struct list_head                list;
-};
-struct idmac_channel {
-        struct dma_chan         dma_chan;
-        dma_cookie_t            completed;      /* last completed cookie           */
-        union ipu_channel_param params;
-        enum ipu_channel        link;   /* input channel, linked to the output     */
-        enum ipu_channel_status status;
-        void                    *client;        /* Only one client per channel     */
-        unsigned int            n_tx_desc;
-        struct idmac_tx_desc    *desc;          /* allocated tx-descriptors        */
-        struct scatterlist      *sg[2]; /* scatterlist elements in buffer-0 and -1 */
-        struct list_head        free_list;      /* free tx-descriptors             */
-        struct list_head        queue;          /* queued tx-descriptors           */
-        spinlock_t              lock;           /* protects sg[0,1], queue         */
-        struct mutex            chan_mutex; /* protects status, cookie, free_list  */
-        bool                    sec_chan_en;
-        int                     active_buffer;
-        unsigned int            eof_irq;
-        char                    eof_name[16];   /* EOF IRQ name for request_irq()  */
-};
-#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)
-#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
deleted file mode 100644
index d73f5e8ea9cb..000000000000
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_MXC_IRQS_H__
-#define __ASM_ARCH_MXC_IRQS_H__
-extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
-/* all normal IRQs can be FIQs */
-#define FIQ_START       0
-/* switch between IRQ and FIQ */
-extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
-#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
deleted file mode 100644
index 10343d1f87e1..000000000000
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MXC_TIMEX_H__
-#define __ASM_ARCH_MXC_TIMEX_H__
-/* Bogus value */
-#define CLOCK_TICK_RATE 12345678
-#endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
deleted file mode 100644
index 477971b00930..000000000000
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  arch/arm/plat-mxc/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
-#define __ASM_ARCH_MXC_UNCOMPRESS_H__
-#define __MXC_BOOT_UNCOMPRESS
-#include <asm/mach-types.h>
-unsigned long uart_base;
-#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
-#define USR2 0x98
-#define USR2_TXFE (1<<14)
-#define TXR  0x40
-#define UCR1 0x80
-#define UCR1_UARTEN 1
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-static void putc(int ch)
-{
-        if (!uart_base)
-                return;
-        if (!(UART(UCR1) & UCR1_UARTEN))
-                return;
-        while (!(UART(USR2) & USR2_TXFE))
-                barrier();
-        UART(TXR) = ch;
-}
-static inline void flush(void)
-{
-}
-#define MX1_UART1_BASE_ADDR     0x00206000
-#define MX25_UART1_BASE_ADDR    0x43f90000
-#define MX2X_UART1_BASE_ADDR    0x1000a000
-#define MX3X_UART1_BASE_ADDR    0x43F90000
-#define MX3X_UART2_BASE_ADDR    0x43F94000
-#define MX3X_UART5_BASE_ADDR    0x43FB4000
-#define MX51_UART1_BASE_ADDR    0x73fbc000
-#define MX50_UART1_BASE_ADDR    0x53fbc000
-#define MX53_UART1_BASE_ADDR    0x53fbc000
-static __inline__ void __arch_decomp_setup(unsigned long arch_id)
-{
-        switch (arch_id) {
-        case MACH_TYPE_MX1ADS:
-        case MACH_TYPE_SCB9328:
-                uart_base = MX1_UART1_BASE_ADDR;
-                break;
-        case MACH_TYPE_MX25_3DS:
-                uart_base = MX25_UART1_BASE_ADDR;
-                break;
-        case MACH_TYPE_IMX27LITE:
-        case MACH_TYPE_MX27_3DS:
-        case MACH_TYPE_MX27ADS:
-        case MACH_TYPE_PCM038:
-        case MACH_TYPE_MX21ADS:
-        case MACH_TYPE_PCA100:
-        case MACH_TYPE_MXT_TD60:
-        case MACH_TYPE_IMX27IPCAM:
-                uart_base = MX2X_UART1_BASE_ADDR;
-                break;
-        case MACH_TYPE_MX31LITE:
-        case MACH_TYPE_ARMADILLO5X0:
-        case MACH_TYPE_MX31MOBOARD:
-        case MACH_TYPE_QONG:
-        case MACH_TYPE_MX31_3DS:
-        case MACH_TYPE_PCM037:
-        case MACH_TYPE_MX31ADS:
-        case MACH_TYPE_MX35_3DS:
-        case MACH_TYPE_PCM043:
-        case MACH_TYPE_LILLY1131:
-        case MACH_TYPE_VPR200:
-        case MACH_TYPE_EUKREA_CPUIMX35SD:
-                uart_base = MX3X_UART1_BASE_ADDR;
-                break;
-        case MACH_TYPE_MAGX_ZN5:
-                uart_base = MX3X_UART2_BASE_ADDR;
-                break;
-        case MACH_TYPE_BUG:
-                uart_base = MX3X_UART5_BASE_ADDR;
-                break;
-        case MACH_TYPE_MX51_BABBAGE:
-        case MACH_TYPE_EUKREA_CPUIMX51SD:
-        case MACH_TYPE_MX51_3DS:
-                uart_base = MX51_UART1_BASE_ADDR;
-                break;
-        case MACH_TYPE_MX50_RDP:
-                uart_base = MX50_UART1_BASE_ADDR;
-                break;
-        case MACH_TYPE_MX53_EVK:
-        case MACH_TYPE_MX53_LOCO:
-        case MACH_TYPE_MX53_SMD:
-        case MACH_TYPE_MX53_ARD:
-                uart_base = MX53_UART1_BASE_ADDR;
-                break;
-        default:
-                break;
-        }
-}
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
-#endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
deleted file mode 100644
index 19f55cae5d73..000000000000
--- a/arch/arm/plat-nomadik/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-# We keep common IP's here for Nomadik and other similar
-# familiy of processors from ST-Ericsson. At the moment we have
-# just MTU, others to follow soon.
-config PLAT_NOMADIK
-        bool
-        depends on ARCH_NOMADIK || ARCH_U8500
-        default y
-        select CLKSRC_MMIO
-        help
-          Common platform code for Nomadik and other ST-Ericsson
-          platforms.
-if PLAT_NOMADIK
-config HAS_MTU
-        bool
-        help
-          Support for Multi Timer Unit. MTU provides access
-          to multiple interrupt generating programmable
-          32-bit free running decrementing counters.
-config NOMADIK_MTU_SCHED_CLOCK
-        bool
-        depends on HAS_MTU
-        help
-          Use the Multi Timer Unit as the sched_clock.
-endif
diff --git a/arch/arm/plat-nomadik/Makefile b/arch/arm/plat-nomadik/Makefile
deleted file mode 100644
index 37c7cdd0f8f0..000000000000
--- a/arch/arm/plat-nomadik/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# arch/arm/plat-nomadik/Makefile
-# Copyright 2009 ST-Ericsson
-# Licensed under GPLv2
-obj-$(CONFIG_HAS_MTU)   += timer.o
diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
deleted file mode 100644
index c08a54d9d889..000000000000
--- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Structures and registers for GPIO access in the Nomadik SoC
- *
- * Copyright (C) 2008 STMicroelectronics
- *     Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
- * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __PLAT_NOMADIK_GPIO
-#define __PLAT_NOMADIK_GPIO
-/*
- * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
- * the "gpio" namespace for generic and cross-machine functions
- */
-/* Register in the logic block */
-#define NMK_GPIO_DAT    0x00
-#define NMK_GPIO_DATS   0x04
-#define NMK_GPIO_DATC   0x08
-#define NMK_GPIO_PDIS   0x0c
-#define NMK_GPIO_DIR    0x10
-#define NMK_GPIO_DIRS   0x14
-#define NMK_GPIO_DIRC   0x18
-#define NMK_GPIO_SLPC   0x1c
-#define NMK_GPIO_AFSLA  0x20
-#define NMK_GPIO_AFSLB  0x24
-#define NMK_GPIO_LOWEMI 0x28
-#define NMK_GPIO_RIMSC  0x40
-#define NMK_GPIO_FIMSC  0x44
-#define NMK_GPIO_IS     0x48
-#define NMK_GPIO_IC     0x4c
-#define NMK_GPIO_RWIMSC 0x50
-#define NMK_GPIO_FWIMSC 0x54
-#define NMK_GPIO_WKS    0x58
-/* Alternate functions: function C is set in hw by setting both A and B */
-#define NMK_GPIO_ALT_GPIO       0
-#define NMK_GPIO_ALT_A  1
-#define NMK_GPIO_ALT_B  2
-#define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
-#define NMK_GPIO_ALT_CX_SHIFT 2
-#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
-/* Pull up/down values */
-enum nmk_gpio_pull {
-        NMK_GPIO_PULL_NONE,
-        NMK_GPIO_PULL_UP,
-        NMK_GPIO_PULL_DOWN,
-};
-/* Sleep mode */
-enum nmk_gpio_slpm {
-        NMK_GPIO_SLPM_INPUT,
-        NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
-        NMK_GPIO_SLPM_NOCHANGE,
-        NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
-};
-extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
-extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
-#ifdef CONFIG_PINCTRL_NOMADIK
-extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
-#else
-static inline int nmk_gpio_set_mode(int gpio, int gpio_mode)
-{
-        return -ENODEV;
-}
-#endif
-extern int nmk_gpio_get_mode(int gpio);
-extern void nmk_gpio_wakeups_suspend(void);
-extern void nmk_gpio_wakeups_resume(void);
-extern void nmk_gpio_clocks_enable(void);
-extern void nmk_gpio_clocks_disable(void);
-extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up);
-/*
- * Platform data to register a block: only the initial gpio/irq number.
- */
-struct nmk_gpio_platform_data {
-        char *name;
-        int first_gpio;
-        int first_irq;
-        int num_gpio;
-        u32 (*get_secondary_status)(unsigned int bank);
-        void (*set_ioforce)(bool enable);
-        bool supports_sleepmode;
-};
-#endif /* __PLAT_NOMADIK_GPIO */
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
deleted file mode 100644
index 582641f3dc01..000000000000
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __PLAT_MTU_H
-#define __PLAT_MTU_H
-void nmdk_timer_init(void __iomem *base);
-void nmdk_clkevt_reset(void);
-void nmdk_clksrc_reset(void);
-#endif /* __PLAT_MTU_H */
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
deleted file mode 100644
index 3b8ec60af351..000000000000
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License, version 2
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- *
- * Based on arch/arm/mach-pxa/include/mach/mfp.h:
- *   Copyright (C) 2007 Marvell International Ltd.
- *   eric miao <eric.miao@marvell.com>
- */
-#ifndef __PLAT_PINCFG_H
-#define __PLAT_PINCFG_H
-/*
- * pin configurations are represented by 32-bit integers:
- *
- *      bit  0.. 8 - Pin Number (512 Pins Maximum)
- *      bit  9..10 - Alternate Function Selection
- *      bit 11..12 - Pull up/down state
- *      bit     13 - Sleep mode behaviour
- *      bit     14 - Direction
- *      bit     15 - Value (if output)
- *      bit 16..18 - SLPM pull up/down state
- *      bit 19..20 - SLPM direction
- *      bit 21..22 - SLPM Value (if output)
- *      bit 23..25 - PDIS value (if input)
- *      bit     26 - Gpio mode
- *      bit     27 - Sleep mode
- *
- * to facilitate the definition, the following macros are provided
- *
- * PIN_CFG_DEFAULT - default config (0):
- *                   pull up/down = disabled
- *                   sleep mode = input/wakeup
- *                   direction = input
- *                   value = low
- *                   SLPM direction = same as normal
- *                   SLPM pull = same as normal
- *                   SLPM value = same as normal
- *
- * PIN_CFG         - default config with alternate function
- */
-typedef unsigned long pin_cfg_t;
-#define PIN_NUM_MASK            0x1ff
-#define PIN_NUM(x)              ((x) & PIN_NUM_MASK)
-#define PIN_ALT_SHIFT           9
-#define PIN_ALT_MASK            (0x3 << PIN_ALT_SHIFT)
-#define PIN_ALT(x)              (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
-#define PIN_GPIO                (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
-#define PIN_ALT_A               (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
-#define PIN_ALT_B               (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
-#define PIN_ALT_C               (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
-#define PIN_PULL_SHIFT          11
-#define PIN_PULL_MASK           (0x3 << PIN_PULL_SHIFT)
-#define PIN_PULL(x)             (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
-#define PIN_PULL_NONE           (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
-#define PIN_PULL_UP             (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
-#define PIN_PULL_DOWN           (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
-#define PIN_SLPM_SHIFT          13
-#define PIN_SLPM_MASK           (0x1 << PIN_SLPM_SHIFT)
-#define PIN_SLPM(x)             (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
-#define PIN_SLPM_MAKE_INPUT     (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
-#define PIN_SLPM_NOCHANGE       (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
-/* These two replace the above in DB8500v2+ */
-#define PIN_SLPM_WAKEUP_ENABLE  (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
-#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
-#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
-#define PIN_SLPM_GPIO  PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
-#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
-#define PIN_DIR_SHIFT           14
-#define PIN_DIR_MASK            (0x1 << PIN_DIR_SHIFT)
-#define PIN_DIR(x)              (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
-#define PIN_DIR_INPUT           (0 << PIN_DIR_SHIFT)
-#define PIN_DIR_OUTPUT          (1 << PIN_DIR_SHIFT)
-#define PIN_VAL_SHIFT           15
-#define PIN_VAL_MASK            (0x1 << PIN_VAL_SHIFT)
-#define PIN_VAL(x)              (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
-#define PIN_VAL_LOW             (0 << PIN_VAL_SHIFT)
-#define PIN_VAL_HIGH            (1 << PIN_VAL_SHIFT)
-#define PIN_SLPM_PULL_SHIFT     16
-#define PIN_SLPM_PULL_MASK      (0x7 << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL(x)        \
-        (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_NONE      \
-        ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_UP        \
-        ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_DOWN      \
-        ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_DIR_SHIFT      19
-#define PIN_SLPM_DIR_MASK       (0x3 << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR(x)         \
-        (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_INPUT      ((1 + 0) << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_OUTPUT     ((1 + 1) << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_VAL_SHIFT      21
-#define PIN_SLPM_VAL_MASK       (0x3 << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL(x)         \
-        (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_PDIS_SHIFT             23
-#define PIN_SLPM_PDIS_MASK              (0x3 << PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS(x)        \
-        (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS_NO_CHANGE         (0 << PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS_DISABLED          (1 << PIN_SLPM_PDIS_SHIFT)
-#define PIN_SLPM_PDIS_ENABLED           (2 << PIN_SLPM_PDIS_SHIFT)
-#define PIN_LOWEMI_SHIFT        25
-#define PIN_LOWEMI_MASK         (0x1 << PIN_LOWEMI_SHIFT)
-#define PIN_LOWEMI(x)           (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
-#define PIN_LOWEMI_DISABLED     (0 << PIN_LOWEMI_SHIFT)
-#define PIN_LOWEMI_ENABLED      (1 << PIN_LOWEMI_SHIFT)
-#define PIN_GPIOMODE_SHIFT      26
-#define PIN_GPIOMODE_MASK       (0x1 << PIN_GPIOMODE_SHIFT)
-#define PIN_GPIOMODE(x)         (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
-#define PIN_GPIOMODE_DISABLED   (0 << PIN_GPIOMODE_SHIFT)
-#define PIN_GPIOMODE_ENABLED    (1 << PIN_GPIOMODE_SHIFT)
-#define PIN_SLEEPMODE_SHIFT     27
-#define PIN_SLEEPMODE_MASK      (0x1 << PIN_SLEEPMODE_SHIFT)
-#define PIN_SLEEPMODE(x)        (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
-#define PIN_SLEEPMODE_DISABLED  (0 << PIN_SLEEPMODE_SHIFT)
-#define PIN_SLEEPMODE_ENABLED   (1 << PIN_SLEEPMODE_SHIFT)
-/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
-#define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
-#define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
-#define PIN_INPUT_NOPULL        (PIN_DIR_INPUT | PIN_PULL_NONE)
-#define PIN_OUTPUT_LOW          (PIN_DIR_OUTPUT | PIN_VAL_LOW)
-#define PIN_OUTPUT_HIGH         (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
-#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
-#define PIN_SLPM_INPUT_PULLUP   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
-#define PIN_SLPM_INPUT_NOPULL   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
-#define PIN_SLPM_OUTPUT_LOW     (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
-#define PIN_SLPM_OUTPUT_HIGH    (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
-#define PIN_CFG_DEFAULT         (0)
-#define PIN_CFG(num, alt)               \
-        (PIN_CFG_DEFAULT |\
-         (PIN_NUM(num) | PIN_##alt))
-#define PIN_CFG_INPUT(num, alt, pull)           \
-        (PIN_CFG_DEFAULT |\
-         (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
-#define PIN_CFG_OUTPUT(num, alt, val)           \
-        (PIN_CFG_DEFAULT |\
-         (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
-extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
-extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
-extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
-#endif
diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
deleted file mode 100644
index 9ff93b065686..000000000000
--- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2007-2010
- * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef STE_DMA40_H
-#define STE_DMA40_H
-#include <linux/dmaengine.h>
-#include <linux/scatterlist.h>
-#include <linux/workqueue.h>
-#include <linux/interrupt.h>
-/*
- * Maxium size for a single dma descriptor
- * Size is limited to 16 bits.
- * Size is in the units of addr-widths (1,2,4,8 bytes)
- * Larger transfers will be split up to multiple linked desc
- */
-#define STEDMA40_MAX_SEG_SIZE 0xFFFF
-/* dev types for memcpy */
-#define STEDMA40_DEV_DST_MEMORY (-1)
-#define STEDMA40_DEV_SRC_MEMORY (-1)
-enum stedma40_mode {
-        STEDMA40_MODE_LOGICAL = 0,
-        STEDMA40_MODE_PHYSICAL,
-        STEDMA40_MODE_OPERATION,
-};
-enum stedma40_mode_opt {
-        STEDMA40_PCHAN_BASIC_MODE = 0,
-        STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
-        STEDMA40_PCHAN_MODULO_MODE,
-        STEDMA40_PCHAN_DOUBLE_DST_MODE,
-        STEDMA40_LCHAN_SRC_PHY_DST_LOG,
-        STEDMA40_LCHAN_SRC_LOG_DST_PHY,
-};
-#define STEDMA40_ESIZE_8_BIT  0x0
-#define STEDMA40_ESIZE_16_BIT 0x1
-#define STEDMA40_ESIZE_32_BIT 0x2
-#define STEDMA40_ESIZE_64_BIT 0x3
-/* The value 4 indicates that PEN-reg shall be set to 0 */
-#define STEDMA40_PSIZE_PHY_1  0x4
-#define STEDMA40_PSIZE_PHY_2  0x0
-#define STEDMA40_PSIZE_PHY_4  0x1
-#define STEDMA40_PSIZE_PHY_8  0x2
-#define STEDMA40_PSIZE_PHY_16 0x3
-/*
- * The number of elements differ in logical and
- * physical mode
- */
-#define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
-#define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
-#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
-#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
-/* Maximum number of possible physical channels */
-#define STEDMA40_MAX_PHYS 32
-enum stedma40_flow_ctrl {
-        STEDMA40_NO_FLOW_CTRL,
-        STEDMA40_FLOW_CTRL,
-};
-enum stedma40_periph_data_width {
-        STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
-        STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
-        STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
-        STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
-};
-enum stedma40_xfer_dir {
-        STEDMA40_MEM_TO_MEM = 1,
-        STEDMA40_MEM_TO_PERIPH,
-        STEDMA40_PERIPH_TO_MEM,
-        STEDMA40_PERIPH_TO_PERIPH
-};
-/**
- * struct stedma40_chan_cfg - dst/src channel configuration
- *
- * @big_endian: true if the src/dst should be read as big endian
- * @data_width: Data width of the src/dst hardware
- * @p_size: Burst size
- * @flow_ctrl: Flow control on/off.
- */
-struct stedma40_half_channel_info {
-        bool big_endian;
-        enum stedma40_periph_data_width data_width;
-        int psize;
-        enum stedma40_flow_ctrl flow_ctrl;
-};
-/**
- * struct stedma40_chan_cfg - Structure to be filled by client drivers.
- *
- * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
- * @high_priority: true if high-priority
- * @realtime: true if realtime mode is to be enabled.  Only available on DMA40
- * version 3+, i.e DB8500v2+
- * @mode: channel mode: physical, logical, or operation
- * @mode_opt: options for the chosen channel mode
- * @src_dev_type: Src device type
- * @dst_dev_type: Dst device type
- * @src_info: Parameters for dst half channel
- * @dst_info: Parameters for dst half channel
- * @use_fixed_channel: if true, use physical channel specified by phy_channel
- * @phy_channel: physical channel to use, only if use_fixed_channel is true
- *
- * This structure has to be filled by the client drivers.
- * It is recommended to do all dma configurations for clients in the machine.
- *
- */
-struct stedma40_chan_cfg {
-        enum stedma40_xfer_dir                   dir;
-        bool                                     high_priority;
-        bool                                     realtime;
-        enum stedma40_mode                       mode;
-        enum stedma40_mode_opt                   mode_opt;
-        int                                      src_dev_type;
-        int                                      dst_dev_type;
-        struct stedma40_half_channel_info        src_info;
-        struct stedma40_half_channel_info        dst_info;
-        bool                                     use_fixed_channel;
-        int                                      phy_channel;
-};
-/**
- * struct stedma40_platform_data - Configuration struct for the dma device.
- *
- * @dev_len: length of dev_tx and dev_rx
- * @dev_tx: mapping between destination event line and io address
- * @dev_rx: mapping between source event line and io address
- * @memcpy: list of memcpy event lines
- * @memcpy_len: length of memcpy
- * @memcpy_conf_phy: default configuration of physical channel memcpy
- * @memcpy_conf_log: default configuration of logical channel memcpy
- * @disabled_channels: A vector, ending with -1, that marks physical channels
- * that are for different reasons not available for the driver.
- */
-struct stedma40_platform_data {
-        u32                              dev_len;
-        const dma_addr_t                *dev_tx;
-        const dma_addr_t                *dev_rx;
-        int                             *memcpy;
-        u32                              memcpy_len;
-        struct stedma40_chan_cfg        *memcpy_conf_phy;
-        struct stedma40_chan_cfg        *memcpy_conf_log;
-        int                              disabled_channels[STEDMA40_MAX_PHYS];
-        bool                             use_esram_lcla;
-};
-#ifdef CONFIG_STE_DMA40
-/**
- * stedma40_filter() - Provides stedma40_chan_cfg to the
- * ste_dma40 dma driver via the dmaengine framework.
- * does some checking of what's provided.
- *
- * Never directly called by client. It used by dmaengine.
- * @chan: dmaengine handle.
- * @data: Must be of type: struct stedma40_chan_cfg and is
- * the configuration of the framework.
- *
- *
- */
-bool stedma40_filter(struct dma_chan *chan, void *data);
-/**
- * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
- * (=device)
- *
- * @chan: dmaengine handle
- * @addr: source or destination physicall address.
- * @size: bytes to transfer
- * @direction: direction of transfer
- * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
- */
-static inline struct
-dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
-                                            dma_addr_t addr,
-                                            unsigned int size,
-                                            enum dma_transfer_direction direction,
-                                            unsigned long flags)
-{
-        struct scatterlist sg;
-        sg_init_table(&sg, 1);
-        sg.dma_address = addr;
-        sg.length = size;
-        return dmaengine_prep_slave_sg(chan, &sg, 1, direction, flags);
-}
-#else
-static inline bool stedma40_filter(struct dma_chan *chan, void *data)
-{
-        return false;
-}
-static inline struct
-dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
-                                            dma_addr_t addr,
-                                            unsigned int size,
-                                            enum dma_transfer_direction direction,
-                                            unsigned long flags)
-{
-        return NULL;
-}
-#endif
-#endif
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
deleted file mode 100644
index 9222e5522a43..000000000000
--- a/arch/arm/plat-nomadik/timer.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- *  linux/arch/arm/plat-nomadik/timer.c
- *
- * Copyright (C) 2008 STMicroelectronics
- * Copyright (C) 2010 Alessandro Rubini
- * Copyright (C) 2010 Linus Walleij for ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/jiffies.h>
-#include <linux/err.h>
-#include <asm/mach/time.h>
-#include <asm/sched_clock.h>
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
-#define MTU_RIS         0x04    /* Raw interrupt status */
-#define MTU_MIS         0x08    /* Masked interrupt status */
-#define MTU_ICR         0x0C    /* Interrupt clear register */
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
-#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
-#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
-#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
-/* bits for the control register */
-#define MTU_CRn_ENA             0x80
-#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK   0x0c
-#define MTU_CRn_PRESCALE_1              0x00
-#define MTU_CRn_PRESCALE_16             0x04
-#define MTU_CRn_PRESCALE_256            0x08
-#define MTU_CRn_32BITS          0x02
-#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR        0xff0
-#define MTU_ITOP        0xff4
-#define MTU_PERIPH_ID0  0xfe0
-#define MTU_PERIPH_ID1  0xfe4
-#define MTU_PERIPH_ID2  0xfe8
-#define MTU_PERIPH_ID3  0xfeC
-#define MTU_PCELL0      0xff0
-#define MTU_PCELL1      0xff4
-#define MTU_PCELL2      0xff8
-#define MTU_PCELL3      0xffC
-static void __iomem *mtu_base;
-static bool clkevt_periodic;
-static u32 clk_prescale;
-static u32 nmdk_cycle;          /* write-once */
-#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
-/*
- * Override the global weak sched_clock symbol with this
- * local implementation which uses the clocksource to get some
- * better resolution when scheduling the kernel.
- */
-static u32 notrace nomadik_read_sched_clock(void)
-{
-        if (unlikely(!mtu_base))
-                return 0;
-        return -readl(mtu_base + MTU_VAL(0));
-}
-#endif
-/* Clockevent device: use one-shot mode */
-static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
-{
-        writel(1 << 1, mtu_base + MTU_IMSC);
-        writel(evt, mtu_base + MTU_LR(1));
-        /* Load highest value, enable device, enable interrupts */
-        writel(MTU_CRn_ONESHOT | clk_prescale |
-               MTU_CRn_32BITS | MTU_CRn_ENA,
-               mtu_base + MTU_CR(1));
-        return 0;
-}
-void nmdk_clkevt_reset(void)
-{
-        if (clkevt_periodic) {
-                /* Timer: configure load and background-load, and fire it up */
-                writel(nmdk_cycle, mtu_base + MTU_LR(1));
-                writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
-                writel(MTU_CRn_PERIODIC | clk_prescale |
-                       MTU_CRn_32BITS | MTU_CRn_ENA,
-                       mtu_base + MTU_CR(1));
-                writel(1 << 1, mtu_base + MTU_IMSC);
-        } else {
-                /* Generate an interrupt to start the clockevent again */
-                (void) nmdk_clkevt_next(nmdk_cycle, NULL);
-        }
-}
-static void nmdk_clkevt_mode(enum clock_event_mode mode,
-                             struct clock_event_device *dev)
-{
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                clkevt_periodic = true;
-                nmdk_clkevt_reset();
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                clkevt_periodic = false;
-                break;
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-                writel(0, mtu_base + MTU_IMSC);
-                /* disable timer */
-                writel(0, mtu_base + MTU_CR(1));
-                /* load some high default value */
-                writel(0xffffffff, mtu_base + MTU_LR(1));
-                break;
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-static struct clock_event_device nmdk_clkevt = {
-        .name           = "mtu_1",
-        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
-        .rating         = 200,
-        .set_mode       = nmdk_clkevt_mode,
-        .set_next_event = nmdk_clkevt_next,
-};
-/*
- * IRQ Handler for timer 1 of the MTU block.
- */
-static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evdev = dev_id;
-        writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
-        evdev->event_handler(evdev);
-        return IRQ_HANDLED;
-}
-static struct irqaction nmdk_timer_irq = {
-        .name           = "Nomadik Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
-        .handler        = nmdk_timer_interrupt,
-        .dev_id         = &nmdk_clkevt,
-};
-void nmdk_clksrc_reset(void)
-{
-        /* Disable */
-        writel(0, mtu_base + MTU_CR(0));
-        /* ClockSource: configure load and background-load, and fire it up */
-        writel(nmdk_cycle, mtu_base + MTU_LR(0));
-        writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
-        writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
-               mtu_base + MTU_CR(0));
-}
-void __init nmdk_timer_init(void __iomem *base)
-{
-        unsigned long rate;
-        struct clk *clk0;
-        mtu_base = base;
-        clk0 = clk_get_sys("mtu0", NULL);
-        BUG_ON(IS_ERR(clk0));
-        BUG_ON(clk_prepare(clk0) < 0);
-        BUG_ON(clk_enable(clk0) < 0);
-        /*
-         * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
-         * for ux500.
-         * Use a divide-by-16 counter if the tick rate is more than 32MHz.
-         * At 32 MHz, the timer (with 32 bit counter) can be programmed
-         * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
-         * with 16 gives too low timer resolution.
-         */
-        rate = clk_get_rate(clk0);
-        if (rate > 32000000) {
-                rate /= 16;
-                clk_prescale = MTU_CRn_PRESCALE_16;
-        } else {
-                clk_prescale = MTU_CRn_PRESCALE_1;
-        }
-        nmdk_cycle = (rate + HZ/2) / HZ;
-        /* Timer 0 is the free running clocksource */
-        nmdk_clksrc_reset();
-        if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
-                        rate, 200, 32, clocksource_mmio_readl_down))
-                pr_err("timer: failed to initialize clock source %s\n",
-                       "mtu_0");
-#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
-        setup_sched_clock(nomadik_read_sched_clock, 32, rate);
-#endif
-        /* Timer 1 is used for events, register irq and clockevents */
-        setup_irq(IRQ_MTU0, &nmdk_timer_irq);
-        nmdk_clkevt.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
-}
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 82fcb206b5b2..665870dce3c8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -154,6 +154,12 @@ config OMAP_32K_TIMER
          intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
          currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
+          On OMAP2PLUS this value is only used for CONFIG_HZ and
+          CLOCK_TICK_RATE compile time calculation.
+          The actual timer selection is done in the board file
+          through the (DT_)MACHINE_START structure.
 config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
        bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
        depends on ARCH_OMAP3 && PM
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index dacaee009a4e..8d885848600a 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,13 +3,12 @@
 #
 # Common support
-obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o
+obj-y := sram.o dma.o fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
 # omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
@@ -20,4 +19,3 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
 # OMAP mailbox framework
 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
-obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
deleted file mode 100644
index 9d7ac20ef8f9..000000000000
--- a/arch/arm/plat-omap/clock.c
+++ /dev/null
@@ -1,544 +0,0 @@
-/*
- *  linux/arch/arm/plat-omap/clock.c
- *
- *  Copyright (C) 2004 - 2008 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *
- *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/export.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/cpufreq.h>
-#include <linux/io.h>
-#include <plat/clock.h>
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clockfw_lock);
-static struct clk_functions *arch_clock;
-/*
- * Standard clock functions defined in include/linux/clk.h
- */
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        int ret;
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-        if (!arch_clock || !arch_clock->clk_enable)
-                return -EINVAL;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = arch_clock->clk_enable(clk);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-        if (clk == NULL || IS_ERR(clk))
-                return;
-        if (!arch_clock || !arch_clock->clk_disable)
-                return;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        if (clk->usecount == 0) {
-                pr_err("Trying disable clock %s with 0 usecount\n",
-                       clk->name);
-                WARN_ON(1);
-                goto out;
-        }
-        arch_clock->clk_disable(clk);
-out:
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long flags;
-        unsigned long ret;
-        if (clk == NULL || IS_ERR(clk))
-                return 0;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = clk->rate;
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-/*
- * Optional clock functions defined in include/linux/clk.h
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        long ret;
-        if (clk == NULL || IS_ERR(clk))
-                return 0;
-        if (!arch_clock || !arch_clock->clk_round_rate)
-                return 0;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = arch_clock->clk_round_rate(clk, rate);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-        if (clk == NULL || IS_ERR(clk))
-                return ret;
-        if (!arch_clock || !arch_clock->clk_set_rate)
-                return ret;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = arch_clock->clk_set_rate(clk, rate);
-        if (ret == 0)
-                propagate_rate(clk);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-        if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
-                return ret;
-        if (!arch_clock || !arch_clock->clk_set_parent)
-                return ret;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        if (clk->usecount == 0) {
-                ret = arch_clock->clk_set_parent(clk, parent);
-                if (ret == 0)
-                        propagate_rate(clk);
-        } else
-                ret = -EBUSY;
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-struct clk *clk_get_parent(struct clk *clk)
-{
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-/*
- * OMAP specific clock functions shared between omap1 and omap2
- */
-int __initdata mpurate;
-/*
- * By default we use the rate set by the bootloader.
- * You can override this with mpurate= cmdline option.
- */
-static int __init omap_clk_setup(char *str)
-{
-        get_option(&str, &mpurate);
-        if (!mpurate)
-                return 1;
-        if (mpurate < 1000)
-                mpurate *= 1000000;
-        return 1;
-}
-__setup("mpurate=", omap_clk_setup);
-/* Used for clocks that always have same value as the parent clock */
-unsigned long followparent_recalc(struct clk *clk)
-{
-        return clk->parent->rate;
-}
-/*
- * Used for clocks that have the same value as the parent clock,
- * divided by some factor
- */
-unsigned long omap_fixed_divisor_recalc(struct clk *clk)
-{
-        WARN_ON(!clk->fixed_div);
-        return clk->parent->rate / clk->fixed_div;
-}
-void clk_reparent(struct clk *child, struct clk *parent)
-{
-        list_del_init(&child->sibling);
-        if (parent)
-                list_add(&child->sibling, &parent->children);
-        child->parent = parent;
-        /* now do the debugfs renaming to reattach the child
-           to the proper parent */
-}
-/* Propagate rate to children */
-void propagate_rate(struct clk *tclk)
-{
-        struct clk *clkp;
-        list_for_each_entry(clkp, &tclk->children, sibling) {
-                if (clkp->recalc)
-                        clkp->rate = clkp->recalc(clkp);
-                propagate_rate(clkp);
-        }
-}
-static LIST_HEAD(root_clks);
-/**
- * recalculate_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- * Called at init.
- */
-void recalculate_root_clocks(void)
-{
-        struct clk *clkp;
-        list_for_each_entry(clkp, &root_clks, sibling) {
-                if (clkp->recalc)
-                        clkp->rate = clkp->recalc(clkp);
-                propagate_rate(clkp);
-        }
-}
-/**
- * clk_preinit - initialize any fields in the struct clk before clk init
- * @clk: struct clk * to initialize
- *
- * Initialize any struct clk fields needed before normal clk initialization
- * can run.  No return value.
- */
-void clk_preinit(struct clk *clk)
-{
-        INIT_LIST_HEAD(&clk->children);
-}
-int clk_register(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-        /*
-         * trap out already registered clocks
-         */
-        if (clk->node.next || clk->node.prev)
-                return 0;
-        mutex_lock(&clocks_mutex);
-        if (clk->parent)
-                list_add(&clk->sibling, &clk->parent->children);
-        else
-                list_add(&clk->sibling, &root_clks);
-        list_add(&clk->node, &clocks);
-        if (clk->init)
-                clk->init(clk);
-        mutex_unlock(&clocks_mutex);
-        return 0;
-}
-EXPORT_SYMBOL(clk_register);
-void clk_unregister(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-        mutex_lock(&clocks_mutex);
-        list_del(&clk->sibling);
-        list_del(&clk->node);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unregister);
-void clk_enable_init_clocks(void)
-{
-        struct clk *clkp;
-        list_for_each_entry(clkp, &clocks, node) {
-                if (clkp->flags & ENABLE_ON_INIT)
-                        clk_enable(clkp);
-        }
-}
-int omap_clk_enable_autoidle_all(void)
-{
-        struct clk *c;
-        unsigned long flags;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        list_for_each_entry(c, &clocks, node)
-                if (c->ops->allow_idle)
-                        c->ops->allow_idle(c);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return 0;
-}
-int omap_clk_disable_autoidle_all(void)
-{
-        struct clk *c;
-        unsigned long flags;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        list_for_each_entry(c, &clocks, node)
-                if (c->ops->deny_idle)
-                        c->ops->deny_idle(c);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return 0;
-}
-/*
- * Low level helpers
- */
-static int clkll_enable_null(struct clk *clk)
-{
-        return 0;
-}
-static void clkll_disable_null(struct clk *clk)
-{
-}
-const struct clkops clkops_null = {
-        .enable         = clkll_enable_null,
-        .disable        = clkll_disable_null,
-};
-/*
- * Dummy clock
- *
- * Used for clock aliases that are needed on some OMAPs, but not others
- */
-struct clk dummy_ck = {
-        .name   = "dummy",
-        .ops    = &clkops_null,
-};
-/*
- *
- */
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-/*
- * Disable any unused clocks left on by the bootloader
- */
-static int __init clk_disable_unused(void)
-{
-        struct clk *ck;
-        unsigned long flags;
-        if (!arch_clock || !arch_clock->clk_disable_unused)
-                return 0;
-        pr_info("clock: disabling unused clocks to save power\n");
-        spin_lock_irqsave(&clockfw_lock, flags);
-        list_for_each_entry(ck, &clocks, node) {
-                if (ck->ops == &clkops_null)
-                        continue;
-                if (ck->usecount > 0 || !ck->enable_reg)
-                        continue;
-                arch_clock->clk_disable_unused(ck);
-        }
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-        return 0;
-}
-late_initcall(clk_disable_unused);
-late_initcall(omap_clk_enable_autoidle_all);
-#endif
-int __init clk_init(struct clk_functions * custom_clocks)
-{
-        if (!custom_clocks) {
-                pr_err("No custom clock functions registered\n");
-                BUG();
-        }
-        arch_clock = custom_clocks;
-        return 0;
-}
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-/*
- *      debugfs support to trace clock tree hierarchy and attributes
- */
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-static struct dentry *clk_debugfs_root;
-static int clk_dbg_show_summary(struct seq_file *s, void *unused)
-{
-        struct clk *c;
-        struct clk *pa;
-        mutex_lock(&clocks_mutex);
-        seq_printf(s, "%-30s %-30s %-10s %s\n",
-                "clock-name", "parent-name", "rate", "use-count");
-        list_for_each_entry(c, &clocks, node) {
-                pa = c->parent;
-                seq_printf(s, "%-30s %-30s %-10lu %d\n",
-                        c->name, pa ? pa->name : "none", c->rate, c->usecount);
-        }
-        mutex_unlock(&clocks_mutex);
-        return 0;
-}
-static int clk_dbg_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, clk_dbg_show_summary, inode->i_private);
-}
-static const struct file_operations debug_clock_fops = {
-        .open           = clk_dbg_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-static int clk_debugfs_register_one(struct clk *c)
-{
-        int err;
-        struct dentry *d;
-        struct clk *pa = c->parent;
-        d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dent = d;
-        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return err;
-}
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent;
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-static int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err;
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-        list_for_each_entry(c, &clocks, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        d = debugfs_create_file("summary", S_IRUGO,
-                d, NULL, &debug_clock_fops);
-        if (!d)
-                return -ENOMEM;
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-late_initcall(clk_debugfs_init);
-#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
deleted file mode 100644
index 111315a69354..000000000000
--- a/arch/arm/plat-omap/common.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/common.c
- *
- * Code common to all OMAP machines.
- * The file is created by Tony Lindgren <tony@atomide.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/dma-mapping.h>
-#include <plat/common.h>
-#include <plat/vram.h>
-#include <linux/platform_data/dsp-omap.h>
-#include <plat/dma.h>
-#include <plat/omap-secure.h>
-void __init omap_reserve(void)
-{
-        omap_vram_reserve_sdram_memblock();
-        omap_dsp_reserve_sdram_memblock();
-        omap_secure_ram_reserve_memblock();
-        omap_barrier_reserve_memblock();
-}
-void __init omap_init_consistent_dma_size(void)
-{
-#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-        init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
-#endif
-}
-/*
- * Stub function for OMAP2 so that common files
- * continue to build when custom builds are used
- */
-int __weak omap_secure_ram_reserve_memblock(void)
-{
-        return 0;
-}
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 87ba8dd0d791..f3771cdb9838 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,9 +22,6 @@
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
-#include <plat/common.h>
-#include <plat/clock.h>
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
 #define OMAP2_32KSYNCNT_REV_OFF         0x0
 #define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 5a4678edd65a..a609e2161817 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -15,8 +15,7 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
-#include <mach/hardware.h>
+#include <plat/debug-devices.h>
-#include "../mach-omap2/debug-devices.h"
 /* Many OMAP development platforms reuse the same "debug board"; these
 * platforms include H2, H3, H4, and Perseus2.
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index ea29bbe8e5cf..aa7ebc6bcd65 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -17,16 +17,33 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/slab.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <plat/fpga.h>
 /* Many OMAP development platforms reuse the same "debug board"; these
 * platforms include H2, H3, H4, and Perseus2.  There are 16 LEDs on the
 * debug board (all green), accessed through FPGA registers.
 */
+/* NOTE:  most boards don't have a static mapping for the FPGA ... */
+struct h2p2_dbg_fpga {
+        /* offset 0x00 */
+        u16             smc91x[8];
+        /* offset 0x10 */
+        u16             fpga_rev;
+        u16             board_rev;
+        u16             gpio_outputs;
+        u16             leds;
+        /* offset 0x18 */
+        u16             misc_inputs;
+        u16             lan_status;
+        u16             lan_reset;
+        u16             reserved0;
+        /* offset 0x20 */
+        u16             ps2_data;
+        u16             ps2_ctrl;
+        /* plus also 4 rs232 ports ... */
+};
 static struct h2p2_dbg_fpga __iomem *fpga;
 static u16 fpga_led_state;
@@ -94,7 +111,7 @@ static int fpga_probe(struct platform_device *pdev)
        if (!iomem)
                return -ENODEV;
-        fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
+        fpga = ioremap(iomem->start, resource_size(iomem));
        __raw_writew(0xff, &fpga->leds);
        for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c76ed8bff838..37a488aaa2ba 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,7 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
-#include <plat/cpu.h>
+#include <linux/omap-dma.h>
-#include <plat/dma.h>
-#include <plat/tc.h>
 /*
 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
@@ -175,12 +173,13 @@ static inline void set_gdma_dev(int req, int dev)
 #define omap_writel(val, reg)   do {} while (0)
 #endif
+#ifdef CONFIG_ARCH_OMAP1
 void omap_set_dma_priority(int lch, int dst_port, int priority)
 {
        unsigned long reg;
        u32 l;
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                switch (dst_port) {
                case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
                        reg = OMAP_TC_OCPT1_PRIOR;
@@ -203,18 +202,22 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
                l |= (priority & 0xf) << 8;
                omap_writel(l, reg);
        }
+}
+#endif
-        if (cpu_class_is_omap2()) {
+#ifdef CONFIG_ARCH_OMAP2PLUS
-                u32 ccr;
+void omap_set_dma_priority(int lch, int dst_port, int priority)
+{
+        u32 ccr;
-                ccr = p->dma_read(CCR, lch);
+        ccr = p->dma_read(CCR, lch);
-                if (priority)
+        if (priority)
-                        ccr |= (1 << 6);
+                ccr |= (1 << 6);
-                else
+        else
-                        ccr &= ~(1 << 6);
+                ccr &= ~(1 << 6);
-                p->dma_write(ccr, CCR, lch);
+        p->dma_write(ccr, CCR, lch);
-        }
 }
+#endif
 EXPORT_SYMBOL(omap_set_dma_priority);
 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
@@ -228,7 +231,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
        l |= data_type;
        p->dma_write(l, CSDP, lch);
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                u16 ccr;
                ccr = p->dma_read(CCR, lch);
@@ -244,7 +247,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                p->dma_write(ccr, CCR2, lch);
        }
-        if (cpu_class_is_omap2() && dma_trigger) {
+        if (dma_omap2plus() && dma_trigger) {
                u32 val;
                val = p->dma_read(CCR, lch);
@@ -284,7 +287,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 {
        BUG_ON(omap_dma_in_1510_mode());
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                u16 w;
                w = p->dma_read(CCR2, lch);
@@ -314,7 +317,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                p->dma_write(w, LCH_CTRL, lch);
        }
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                u32 val;
                val = p->dma_read(CCR, lch);
@@ -342,7 +345,7 @@ EXPORT_SYMBOL(omap_set_dma_color_mode);
 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 {
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                u32 csdp;
                csdp = p->dma_read(CSDP, lch);
@@ -355,7 +358,7 @@ EXPORT_SYMBOL(omap_set_dma_write_mode);
 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 {
-        if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+        if (dma_omap1() && !dma_omap15xx()) {
                u32 l;
                l = p->dma_read(LCH_CTRL, lch);
@@ -373,7 +376,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 {
        u32 l;
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                u16 w;
                w = p->dma_read(CSDP, lch);
@@ -415,7 +418,7 @@ EXPORT_SYMBOL(omap_set_dma_params);
 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                return;
        p->dma_write(eidx, CSEI, lch);
@@ -447,13 +450,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        case OMAP_DMA_DATA_BURST_DIS:
                break;
        case OMAP_DMA_DATA_BURST_4:
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                        burst = 0x1;
                else
                        burst = 0x2;
                break;
        case OMAP_DMA_DATA_BURST_8:
-                if (cpu_class_is_omap2()) {
+                if (dma_omap2plus()) {
                        burst = 0x2;
                        break;
                }
@@ -463,7 +466,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
                 * fall through
                 */
        case OMAP_DMA_DATA_BURST_16:
-                if (cpu_class_is_omap2()) {
+                if (dma_omap2plus()) {
                        burst = 0x3;
                        break;
                }
@@ -487,7 +490,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 {
        u32 l;
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                l = p->dma_read(CSDP, lch);
                l &= ~(0x1f << 9);
                l |= dest_port << 9;
@@ -508,7 +511,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_params);
 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 {
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                return;
        p->dma_write(eidx, CDEI, lch);
@@ -540,19 +543,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        case OMAP_DMA_DATA_BURST_DIS:
                break;
        case OMAP_DMA_DATA_BURST_4:
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                        burst = 0x1;
                else
                        burst = 0x2;
                break;
        case OMAP_DMA_DATA_BURST_8:
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                        burst = 0x2;
                else
                        burst = 0x3;
                break;
        case OMAP_DMA_DATA_BURST_16:
-                if (cpu_class_is_omap2()) {
+                if (dma_omap2plus()) {
                        burst = 0x3;
                        break;
                }
@@ -573,7 +576,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 static inline void omap_enable_channel_irq(int lch)
 {
        /* Clear CSR */
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                p->dma_read(CSR, lch);
        else
                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -587,7 +590,7 @@ static inline void omap_disable_channel_irq(int lch)
        /* disable channel interrupts */
        p->dma_write(0, CICR, lch);
        /* Clear CSR */
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                p->dma_read(CSR, lch);
        else
                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -611,7 +614,7 @@ static inline void enable_lnk(int lch)
        l = p->dma_read(CLNK_CTRL, lch);
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                l &= ~(1 << 14);
        /* Set the ENABLE_LNK bits */
@@ -619,7 +622,7 @@ static inline void enable_lnk(int lch)
                l = dma_chan[lch].next_lch | (1 << 15);
 #ifndef CONFIG_ARCH_OMAP1
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                if (dma_chan[lch].next_linked_ch != -1)
                        l = dma_chan[lch].next_linked_ch | (1 << 15);
 #endif
@@ -636,12 +639,12 @@ static inline void disable_lnk(int lch)
        /* Disable interrupts */
        omap_disable_channel_irq(lch);
-        if (cpu_class_is_omap1()) {
+        if (dma_omap1()) {
                /* Set the STOP_LNK bit */
                l |= 1 << 14;
        }
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                /* Clear the ENABLE_LNK bit */
                l &= ~(1 << 15);
        }
@@ -655,7 +658,7 @@ static inline void omap2_enable_irq_lch(int lch)
        u32 val;
        unsigned long flags;
-        if (!cpu_class_is_omap2())
+        if (dma_omap1())
                return;
        spin_lock_irqsave(&dma_chan_lock, flags);
@@ -673,7 +676,7 @@ static inline void omap2_disable_irq_lch(int lch)
        u32 val;
        unsigned long flags;
-        if (!cpu_class_is_omap2())
+        if (dma_omap1())
                return;
        spin_lock_irqsave(&dma_chan_lock, flags);
@@ -712,7 +715,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
        if (p->clear_lch_regs)
                p->clear_lch_regs(free_ch);
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                omap_clear_dma(free_ch);
        spin_unlock_irqrestore(&dma_chan_lock, flags);
@@ -723,7 +726,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
        chan->flags = 0;
 #ifndef CONFIG_ARCH_OMAP1
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                chan->chain_id = -1;
                chan->next_linked_ch = -1;
        }
@@ -731,13 +734,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
        chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
-        else if (cpu_class_is_omap2())
+        else if (dma_omap2plus())
                chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
                        OMAP2_DMA_TRANS_ERR_IRQ;
-        if (cpu_is_omap16xx()) {
+        if (dma_omap16xx()) {
                /* If the sync device is set, configure it dynamically. */
                if (dev_id != 0) {
                        set_gdma_dev(free_ch + 1, dev_id);
@@ -748,11 +751,11 @@ int omap_request_dma(int dev_id, const char *dev_name,
                 * id.
                 */
                p->dma_write(dev_id | (1 << 10), CCR, free_ch);
-        } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
+        } else if (dma_omap1()) {
                p->dma_write(dev_id, CCR, free_ch);
        }
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                omap_enable_channel_irq(free_ch);
                omap2_enable_irq_lch(free_ch);
        }
@@ -774,7 +777,7 @@ void omap_free_dma(int lch)
        }
        /* Disable interrupt for logical channel */
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                omap2_disable_irq_lch(lch);
        /* Disable all DMA interrupts for the channel. */
@@ -784,7 +787,7 @@ void omap_free_dma(int lch)
        p->dma_write(0, CCR, lch);
        /* Clear registers */
-        if (cpu_class_is_omap2())
+        if (dma_omap2plus())
                omap_clear_dma(lch);
        spin_lock_irqsave(&dma_chan_lock, flags);
@@ -810,7 +813,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 {
        u32 reg;
-        if (!cpu_class_is_omap2()) {
+        if (dma_omap1()) {
                printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
                return;
        }
@@ -849,7 +852,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
        }
        l = p->dma_read(CCR, lch);
        l &= ~((1 << 6) | (1 << 26));
-        if (cpu_class_is_omap2() && !cpu_is_omap242x())
+        if (d->dev_caps & IS_RW_PRIORITY)
                l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
        else
                l |= ((read_prio & 0x1) << 6);
@@ -882,7 +885,7 @@ void omap_start_dma(int lch)
         * The CPC/CDAC register needs to be initialized to zero
         * before starting dma transfer.
         */
-        if (cpu_is_omap15xx())
+        if (dma_omap15xx())
                p->dma_write(0, CPC, lch);
        else
                p->dma_write(0, CDAC, lch);
@@ -1045,7 +1048,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
 {
        dma_addr_t offset = 0;
-        if (cpu_is_omap15xx())
+        if (dma_omap15xx())
                offset = p->dma_read(CPC, lch);
        else
                offset = p->dma_read(CSAC, lch);
@@ -1053,7 +1056,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
        if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
                offset = p->dma_read(CSAC, lch);
-        if (!cpu_is_omap15xx()) {
+        if (!dma_omap15xx()) {
                /*
                 * CDAC == 0 indicates that the DMA transfer on the channel has
                 * not been started (no data has been transferred so far).
@@ -1065,7 +1068,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
                        offset = p->dma_read(CSSA, lch);
        }
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
        return offset;
@@ -1084,7 +1087,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
 {
        dma_addr_t offset = 0;
-        if (cpu_is_omap15xx())
+        if (dma_omap15xx())
                offset = p->dma_read(CPC, lch);
        else
                offset = p->dma_read(CDAC, lch);
@@ -1093,7 +1096,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
         * read before the DMA controller finished disabling the channel.
         */
-        if (!cpu_is_omap15xx() && offset == 0) {
+        if (!dma_omap15xx() && offset == 0) {
                offset = p->dma_read(CDAC, lch);
                /*
                 * CDAC == 0 indicates that the DMA transfer on the channel has
@@ -1104,7 +1107,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
                        offset = p->dma_read(CDSA, lch);
        }
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
        return offset;
@@ -1121,7 +1124,7 @@ int omap_dma_running(void)
 {
        int lch;
-        if (cpu_class_is_omap1())
+        if (dma_omap1())
                if (omap_lcd_dma_running())
                        return 1;
@@ -2024,7 +2027,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
        dma_chan                = d->chan;
        enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                dma_lch_count, GFP_KERNEL);
                if (!dma_linked_lch) {
@@ -2036,7 +2039,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
        spin_lock_init(&dma_chan_lock);
        for (ch = 0; ch < dma_chan_count; ch++) {
                omap_clear_dma(ch);
-                if (cpu_class_is_omap2())
+                if (dma_omap2plus())
                        omap2_disable_irq_lch(ch);
                dma_chan[ch].dev_id = -1;
@@ -2045,7 +2048,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                if (ch >= 6 && enable_1510_mode)
                        continue;
-                if (cpu_class_is_omap1()) {
+                if (dma_omap1()) {
                        /*
                         * request_irq() doesn't like dev_id (ie. ch) being
                         * zero, so we have to kludge around this.
@@ -2070,11 +2073,11 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                }
        }
-        if (cpu_class_is_omap2() && !cpu_is_omap242x())
+        if (d->dev_caps & IS_RW_PRIORITY)
                omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
                                DMA_DEFAULT_FIFO_DEPTH, 0);
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                strcpy(irq_name, "0");
                dma_irq = platform_get_irq_byname(pdev, irq_name);
                if (dma_irq < 0) {
@@ -2089,9 +2092,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                }
        }
-        /* reserve dma channels 0 and 1 in high security devices */
+        /* reserve dma channels 0 and 1 in high security devices on 34xx */
-        if (cpu_is_omap34xx() &&
+        if (d->dev_caps & HS_CHANNELS_RESERVED) {
-                (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
                pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
                dma_chan[0].dev_id = 0;
                dma_chan[1].dev_id = 1;
@@ -2118,7 +2120,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
 {
        int dma_irq;
-        if (cpu_class_is_omap2()) {
+        if (dma_omap2plus()) {
                char irq_name[4];
                strcpy(irq_name, "0");
                dma_irq = platform_get_irq_byname(pdev, irq_name);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 938b50a33439..89585c293554 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -35,16 +35,18 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
+#include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/dmtimer-omap.h>
 #include <plat/dmtimer.h>
-#include <plat/omap-pm.h>
-#include <mach/hardware.h>
 static u32 omap_reserved_systimers;
 static LIST_HEAD(omap_timer_list);
@@ -84,10 +86,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
 static void omap_timer_restore_context(struct omap_dm_timer *timer)
 {
-        if (timer->revision == 1)
-                __raw_writel(timer->context.tistat, timer->sys_stat);
-        __raw_writel(timer->context.tisr, timer->irq_stat);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
                                timer->context.twer);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
@@ -103,39 +101,38 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
                                timer->context.tclr);
 }
-static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
+static int omap_dm_timer_reset(struct omap_dm_timer *timer)
 {
-        int c;
+        u32 l, timeout = 100000;
-        if (!timer->sys_stat)
+        if (timer->revision != 1)
-                return;
+                return -EINVAL;
-        c = 0;
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
-        while (!(__raw_readl(timer->sys_stat) & 1)) {
-                c++;
-                if (c > 100000) {
-                        printk(KERN_ERR "Timer failed to reset\n");
-                        return;
-                }
-        }
-}
-static void omap_dm_timer_reset(struct omap_dm_timer *timer)
+        do {
-{
+                l = __omap_dm_timer_read(timer,
-        omap_dm_timer_enable(timer);
+                                         OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
-        if (timer->pdev->id != 1) {
+        } while (!l && timeout--);
-                omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
-                omap_dm_timer_wait_for_reset(timer);
+        if (!timeout) {
+                dev_err(&timer->pdev->dev, "Timer failed to reset\n");
+                return -ETIMEDOUT;
        }
-        __omap_dm_timer_reset(timer, 0, 0);
+        /* Configure timer for smart-idle mode */
-        omap_dm_timer_disable(timer);
+        l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
-        timer->posted = 1;
+        l |= 0x2 << 0x3;
+        __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
+        timer->posted = 0;
+        return 0;
 }
-int omap_dm_timer_prepare(struct omap_dm_timer *timer)
+static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 {
-        int ret;
+        int rc;
        /*
         * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
@@ -150,13 +147,20 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
                }
        }
-        if (timer->capability & OMAP_TIMER_NEEDS_RESET)
+        omap_dm_timer_enable(timer);
-                omap_dm_timer_reset(timer);
-        ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
+        if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
+                rc = omap_dm_timer_reset(timer);
+                if (rc) {
+                        omap_dm_timer_disable(timer);
+                        return rc;
+                }
+        }
-        timer->posted = 1;
+        __omap_dm_timer_enable_posted(timer);
-        return ret;
+        omap_dm_timer_disable(timer);
+        return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 }
 static inline u32 omap_dm_timer_reserved_systimer(int id)
@@ -212,6 +216,13 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
        unsigned long flags;
        int ret = 0;
+        /* Requesting timer by ID is not supported when device tree is used */
+        if (of_have_populated_dt()) {
+                pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n",
+                        __func__);
+                return NULL;
+        }
        spin_lock_irqsave(&dm_timer_lock, flags);
        list_for_each_entry(t, &omap_timer_list, node) {
                if (t->pdev->id == id && !t->reserved) {
@@ -237,6 +248,58 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
+/**
+ * omap_dm_timer_request_by_cap - Request a timer by capability
+ * @cap:        Bit mask of capabilities to match
+ *
+ * Find a timer based upon capabilities bit mask. Callers of this function
+ * should use the definitions found in the plat/dmtimer.h file under the
+ * comment "timer capabilities used in hwmod database". Returns pointer to
+ * timer handle on success and a NULL pointer on failure.
+ */
+struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
+{
+        struct omap_dm_timer *timer = NULL, *t;
+        unsigned long flags;
+        if (!cap)
+                return NULL;
+        spin_lock_irqsave(&dm_timer_lock, flags);
+        list_for_each_entry(t, &omap_timer_list, node) {
+                if ((!t->reserved) && ((t->capability & cap) == cap)) {
+                        /*
+                         * If timer is not NULL, we have already found one timer
+                         * but it was not an exact match because it had more
+                         * capabilites that what was required. Therefore,
+                         * unreserve the last timer found and see if this one
+                         * is a better match.
+                         */
+                        if (timer)
+                                timer->reserved = 0;
+                        timer = t;
+                        timer->reserved = 1;
+                        /* Exit loop early if we find an exact match */
+                        if (t->capability == cap)
+                                break;
+                }
+        }
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
+        if (timer && omap_dm_timer_prepare(timer)) {
+                timer->reserved = 0;
+                timer = NULL;
+        }
+        if (!timer)
+                pr_debug("%s: timer request failed!\n", __func__);
+        return timer;
+}
+EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
 int omap_dm_timer_free(struct omap_dm_timer *timer)
 {
        if (unlikely(!timer))
@@ -271,7 +334,7 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 #if defined(CONFIG_ARCH_OMAP1)
+#include <mach/hardware.h>
 /**
 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 * @inputmask: current value of idlect mask
@@ -348,7 +411,8 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
        omap_dm_timer_enable(timer);
        if (!(timer->capability & OMAP_TIMER_ALWON)) {
-                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                if (timer->get_context_loss_count &&
+                        timer->get_context_loss_count(&timer->pdev->dev) !=
                                timer->ctx_loss_count)
                        omap_timer_restore_context(timer);
        }
@@ -377,9 +441,11 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
        __omap_dm_timer_stop(timer, timer->posted, rate);
-        if (!(timer->capability & OMAP_TIMER_ALWON))
+        if (!(timer->capability & OMAP_TIMER_ALWON)) {
-                timer->ctx_loss_count =
+                if (timer->get_context_loss_count)
-                        omap_pm_get_dev_context_loss_count(&timer->pdev->dev);
+                        timer->ctx_loss_count =
+                                timer->get_context_loss_count(&timer->pdev->dev);
+        }
        /*
         * Since the register values are computed and written within
@@ -388,7 +454,6 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
         */
        timer->context.tclr =
                        omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
-        timer->context.tisr = __raw_readl(timer->irq_stat);
        omap_dm_timer_disable(timer);
        return 0;
 }
@@ -398,7 +463,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 {
        int ret;
        char *parent_name = NULL;
-        struct clk *fclk, *parent;
+        struct clk *parent;
        struct dmtimer_platform_data *pdata;
        if (unlikely(!timer))
@@ -414,14 +479,11 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         * use the clock framework to set the parent clock. To be removed
         * once OMAP1 migrated to using clock framework for dmtimers
         */
-        if (pdata->set_timer_src)
+        if (pdata && pdata->set_timer_src)
                return pdata->set_timer_src(timer->pdev, source);
-        fclk = clk_get(&timer->pdev->dev, "fck");
+        if (!timer->fclk)
-        if (IS_ERR_OR_NULL(fclk)) {
-                pr_err("%s: fck not found\n", __func__);
                return -EINVAL;
-        }
        switch (source) {
        case OMAP_TIMER_SRC_SYS_CLK:
@@ -440,18 +502,15 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
        parent = clk_get(&timer->pdev->dev, parent_name);
        if (IS_ERR_OR_NULL(parent)) {
                pr_err("%s: %s not found\n", __func__, parent_name);
-                ret = -EINVAL;
+                return -EINVAL;
-                goto out;
        }
-        ret = clk_set_parent(fclk, parent);
+        ret = clk_set_parent(timer->fclk, parent);
        if (IS_ERR_VALUE(ret))
                pr_err("%s: failed to set %s as parent\n", __func__,
                        parent_name);
        clk_put(parent);
-out:
-        clk_put(fclk);
        return ret;
 }
@@ -495,7 +554,8 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
        omap_dm_timer_enable(timer);
        if (!(timer->capability & OMAP_TIMER_ALWON)) {
-                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                if (timer->get_context_loss_count &&
+                        timer->get_context_loss_count(&timer->pdev->dev) !=
                                timer->ctx_loss_count)
                        omap_timer_restore_context(timer);
        }
@@ -533,8 +593,8 @@ int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                l |= OMAP_TIMER_CTRL_CE;
        else
                l &= ~OMAP_TIMER_CTRL_CE;
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
        /* Save the context */
        timer->context.tclr = l;
@@ -610,6 +670,37 @@ int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
+/**
+ * omap_dm_timer_set_int_disable - disable timer interrupts
+ * @timer:      pointer to timer handle
+ * @mask:       bit mask of interrupts to be disabled
+ *
+ * Disables the specified timer interrupts for a timer.
+ */
+int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
+{
+        u32 l = mask;
+        if (unlikely(!timer))
+                return -EINVAL;
+        omap_dm_timer_enable(timer);
+        if (timer->revision == 1)
+                l = __raw_readl(timer->irq_ena) & ~mask;
+        __raw_writel(l, timer->irq_dis);
+        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
+        omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
+        /* Save the context */
+        timer->context.tier &= ~mask;
+        timer->context.twer &= ~mask;
+        omap_dm_timer_disable(timer);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 {
        unsigned int l;
@@ -631,8 +722,7 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
                return -EINVAL;
        __omap_dm_timer_write_status(timer, value);
-        /* Save the context */
-        timer->context.tisr = value;
        return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
@@ -695,7 +785,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
        struct device *dev = &pdev->dev;
        struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
-        if (!pdata) {
+        if (!pdata && !dev->of_node) {
                dev_err(dev, "%s: no platform data.\n", __func__);
                return -ENODEV;
        }
@@ -724,11 +814,25 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
                return -ENOMEM;
        }
-        timer->id = pdev->id;
+        if (dev->of_node) {
+                if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
+                        timer->capability |= OMAP_TIMER_ALWON;
+                if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
+                        timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
+                if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
+                        timer->capability |= OMAP_TIMER_HAS_PWM;
+                if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
+                        timer->capability |= OMAP_TIMER_SECURE;
+        } else {
+                timer->id = pdev->id;
+                timer->errata = pdata->timer_errata;
+                timer->capability = pdata->timer_capability;
+                timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
+                timer->get_context_loss_count = pdata->get_context_loss_count;
+        }
        timer->irq = irq->start;
-        timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
        timer->pdev = pdev;
-        timer->capability = pdata->timer_capability;
        /* Skip pm_runtime_enable for OMAP1 */
        if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
@@ -768,7 +872,8 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
        spin_lock_irqsave(&dm_timer_lock, flags);
        list_for_each_entry(timer, &omap_timer_list, node)
-                if (timer->pdev->id == pdev->id) {
+                if (!strcmp(dev_name(&timer->pdev->dev),
+                            dev_name(&pdev->dev))) {
                        list_del(&timer->node);
                        ret = 0;
                        break;
@@ -778,11 +883,18 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
        return ret;
 }
+static const struct of_device_id omap_timer_match[] = {
+        { .compatible = "ti,omap2-timer", },
+        {},
+};
+MODULE_DEVICE_TABLE(of, omap_timer_match);
 static struct platform_driver omap_dm_timer_driver = {
        .probe  = omap_dm_timer_probe,
        .remove = __devexit_p(omap_dm_timer_remove),
        .driver = {
                .name   = "omap_timer",
+                .of_match_table = of_match_ptr(omap_timer_match),
        },
 };
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index bcbb9d5dc293..3a77b30f53d4 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -30,9 +30,69 @@
 #include <linux/io.h>
 #include <linux/omapfb.h>
-#include <mach/hardware.h>
 #include <asm/mach/map.h>
+#include <plat/cpu.h>
+#ifdef CONFIG_OMAP2_VRFB
+/*
+ * The first memory resource is the register region for VRFB,
+ * the rest are VRFB virtual memory areas for each VRFB context.
+ */
+static const struct resource omap2_vrfb_resources[] = {
+        DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
+        DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
+        DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
+        DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
+        DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
+};
+static const struct resource omap3_vrfb_resources[] = {
+        DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
+        DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
+        DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
+        DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
+        DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
+        DEFINE_RES_MEM_NAMED(0xe0000000u, 0x4000000, "vrfb-area-4"),
+        DEFINE_RES_MEM_NAMED(0xe4000000u, 0x4000000, "vrfb-area-5"),
+        DEFINE_RES_MEM_NAMED(0xe8000000u, 0x4000000, "vrfb-area-6"),
+        DEFINE_RES_MEM_NAMED(0xec000000u, 0x4000000, "vrfb-area-7"),
+        DEFINE_RES_MEM_NAMED(0xf0000000u, 0x4000000, "vrfb-area-8"),
+        DEFINE_RES_MEM_NAMED(0xf4000000u, 0x4000000, "vrfb-area-9"),
+        DEFINE_RES_MEM_NAMED(0xf8000000u, 0x4000000, "vrfb-area-10"),
+        DEFINE_RES_MEM_NAMED(0xfc000000u, 0x4000000, "vrfb-area-11"),
+};
+static int __init omap_init_vrfb(void)
+{
+        struct platform_device *pdev;
+        const struct resource *res;
+        unsigned int num_res;
+        if (cpu_is_omap24xx()) {
+                res = omap2_vrfb_resources;
+                num_res = ARRAY_SIZE(omap2_vrfb_resources);
+        } else if (cpu_is_omap34xx()) {
+                res = omap3_vrfb_resources;
+                num_res = ARRAY_SIZE(omap3_vrfb_resources);
+        } else {
+                return 0;
+        }
+        pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
+                        res, num_res, NULL, 0);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+        else
+                return 0;
+}
+arch_initcall(omap_init_vrfb);
+#endif
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 6013831a043e..f9df624d108c 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -31,176 +31,13 @@
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <mach/irqs.h>
 #include <plat/i2c.h>
-#include <plat/omap-pm.h>
-#include <plat/omap_device.h>
-#define OMAP_I2C_SIZE           0x3f
-#define OMAP1_I2C_BASE          0xfffb3800
-#define OMAP1_INT_I2C           (32 + 4)
-static const char name[] = "omap_i2c";
-#define I2C_RESOURCE_BUILDER(base, irq)                 \
-        {                                               \
-                .start  = (base),                       \
-                .end    = (base) + OMAP_I2C_SIZE,       \
-                .flags  = IORESOURCE_MEM,               \
-        },                                              \
-        {                                               \
-                .start  = (irq),                        \
-                .flags  = IORESOURCE_IRQ,               \
-        },
-static struct resource i2c_resources[][2] = {
-        { I2C_RESOURCE_BUILDER(0, 0) },
-};
-#define I2C_DEV_BUILDER(bus_id, res, data)              \
-        {                                               \
-                .id     = (bus_id),                     \
-                .name   = name,                         \
-                .num_resources  = ARRAY_SIZE(res),      \
-                .resource       = (res),                \
-                .dev            = {                     \
-                        .platform_data  = (data),       \
-                },                                      \
-        }
-#define MAX_OMAP_I2C_HWMOD_NAME_LEN     16
 #define OMAP_I2C_MAX_CONTROLLERS 4
 static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
-static struct platform_device omap_i2c_devices[] = {
-        I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
-};
 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
-static int __init omap_i2c_nr_ports(void)
-{
-        int ports = 0;
-        if (cpu_class_is_omap1())
-                ports = 1;
-        else if (cpu_is_omap24xx())
-                ports = 2;
-        else if (cpu_is_omap34xx())
-                ports = 3;
-        else if (cpu_is_omap44xx())
-                ports = 4;
-        return ports;
-}
-static inline int omap1_i2c_add_bus(int bus_id)
-{
-        struct platform_device *pdev;
-        struct omap_i2c_bus_platform_data *pdata;
-        struct resource *res;
-        omap1_i2c_mux_pins(bus_id);
-        pdev = &omap_i2c_devices[bus_id - 1];
-        res = pdev->resource;
-        res[0].start = OMAP1_I2C_BASE;
-        res[0].end = res[0].start + OMAP_I2C_SIZE;
-        res[1].start = OMAP1_INT_I2C;
-        pdata = &i2c_pdata[bus_id - 1];
-        /* all OMAP1 have IP version 1 register set */
-        pdata->rev = OMAP_I2C_IP_VERSION_1;
-        /* all OMAP1 I2C are implemented like this */
-        pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
-                       OMAP_I2C_FLAG_SIMPLE_CLOCK |
-                       OMAP_I2C_FLAG_16BIT_DATA_REG |
-                       OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
-        /* how the cpu bus is wired up differs for 7xx only */
-        if (cpu_is_omap7xx())
-                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
-        else
-                pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
-        return platform_device_register(pdev);
-}
-#ifdef CONFIG_ARCH_OMAP2PLUS
-/*
- * XXX This function is a temporary compatibility wrapper - only
- * needed until the I2C driver can be converted to call
- * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
- */
-static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
-{
-        omap_pm_set_max_mpu_wakeup_lat(dev, t);
-}
-static inline int omap2_i2c_add_bus(int bus_id)
-{
-        int l;
-        struct omap_hwmod *oh;
-        struct platform_device *pdev;
-        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
-        struct omap_i2c_bus_platform_data *pdata;
-        struct omap_i2c_dev_attr *dev_attr;
-        omap2_i2c_mux_pins(bus_id);
-        l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
-        WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
-                "String buffer overflow in I2C%d device setup\n", bus_id);
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                        pr_err("Could not look up %s\n", oh_name);
-                        return -EEXIST;
-        }
-        pdata = &i2c_pdata[bus_id - 1];
-        /*
-         * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
-         * use, and functionality implementation flags, up to the OMAP I2C
-         * driver via platform data
-         */
-        pdata->rev = oh->class->rev;
-        dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
-        pdata->flags = dev_attr->flags;
-        /*
-         * When waiting for completion of a i2c transfer, we need to
-         * set a wake up latency constraint for the MPU. This is to
-         * ensure quick enough wakeup from idle, when transfer
-         * completes.
-         * Only omap3 has support for constraints
-         */
-        if (cpu_is_omap34xx())
-                pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
-        pdev = omap_device_build(name, bus_id, oh, pdata,
-                        sizeof(struct omap_i2c_bus_platform_data),
-                        NULL, 0, 0);
-        WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
-        return PTR_RET(pdev);
-}
-#else
-static inline int omap2_i2c_add_bus(int bus_id)
-{
-        return 0;
-}
-#endif
-static int __init omap_i2c_add_bus(int bus_id)
-{
-        if (cpu_class_is_omap1())
-                return omap1_i2c_add_bus(bus_id);
-        else
-                return omap2_i2c_add_bus(bus_id);
-}
 /**
 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
 * @str: String of options
@@ -214,12 +51,11 @@ static int __init omap_i2c_add_bus(int bus_id)
 */
 static int __init omap_i2c_bus_setup(char *str)
 {
-        int ports;
        int ints[3];
-        ports = omap_i2c_nr_ports();
        get_options(str, 3, ints);
-        if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
+        if (ints[0] < 2 || ints[1] < 1 ||
+                        ints[1] > OMAP_I2C_MAX_CONTROLLERS)
                return 0;
        i2c_pdata[ints[1] - 1].clkrate = ints[2];
        i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
@@ -239,7 +75,7 @@ static int __init omap_register_i2c_bus_cmdline(void)
        for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
                if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
                        i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
-                        err = omap_i2c_add_bus(i + 1);
+                        err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
                        if (err)
                                goto out;
                }
@@ -264,7 +100,7 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
 {
        int err;
-        BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());
+        BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
        if (info) {
                err = i2c_register_board_info(bus_id, info, len);
@@ -277,5 +113,5 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
        i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
-        return omap_i2c_add_bus(bus_id);
+        return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
 }
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
deleted file mode 100644
index 025d85a3ee86..000000000000
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * clkdev <-> OMAP integration
- *
- * Russell King <linux@arm.linux.org.uk>
- *
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
-#include <linux/clkdev.h>
-struct omap_clk {
-        u16                             cpu;
-        struct clk_lookup               lk;
-};
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-/* Platform flags for the clkdev-OMAP integration code */
-#define CK_310          (1 << 0)
-#define CK_7XX          (1 << 1)        /* 7xx, 850 */
-#define CK_1510         (1 << 2)
-#define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
-#define CK_242X         (1 << 4)
-#define CK_243X         (1 << 5)        /* 243x, 253x */
-#define CK_3430ES1      (1 << 6)        /* 34xxES1 only */
-#define CK_3430ES2PLUS  (1 << 7)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_AM35XX       (1 << 9)        /* Sitara AM35xx */
-#define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
-#define CK_443X         (1 << 11)
-#define CK_TI816X       (1 << 12)
-#define CK_446X         (1 << 13)
-#define CK_AM33XX       (1 << 14)       /* AM33xx specific clocks */
-#define CK_1710         (1 << 15)       /* 1710 extra for rate selection */
-#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
-#endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
deleted file mode 100644
index e2e2d045e428..000000000000
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * OMAP clock: data structure definitions, function prototypes, shared macros
- *
- * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ARM_OMAP_CLOCK_H
-#define __ARCH_ARM_OMAP_CLOCK_H
-#include <linux/list.h>
-struct module;
-struct clk;
-struct clockdomain;
-/* Temporary, needed during the common clock framework conversion */
-#define __clk_get_name(clk)     (clk->name)
-#define __clk_get_parent(clk)   (clk->parent)
-#define __clk_get_rate(clk)     (clk->rate)
-/**
- * struct clkops - some clock function pointers
- * @enable: fn ptr that enables the current clock in hardware
- * @disable: fn ptr that enables the current clock in hardware
- * @find_idlest: function returning the IDLEST register for the clock's IP blk
- * @find_companion: function returning the "companion" clk reg for the clock
- * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
- * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
- *
- * A "companion" clk is an accompanying clock to the one being queried
- * that must be enabled for the IP module connected to the clock to
- * become accessible by the hardware.  Neither @find_idlest nor
- * @find_companion should be needed; that information is IP
- * block-specific; the hwmod code has been created to handle this, but
- * until hwmod data is ready and drivers have been converted to use PM
- * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
- * @find_companion must, unfortunately, remain.
- */
-struct clkops {
-        int                     (*enable)(struct clk *);
-        void                    (*disable)(struct clk *);
-        void                    (*find_idlest)(struct clk *, void __iomem **,
-                                               u8 *, u8 *);
-        void                    (*find_companion)(struct clk *, void __iomem **,
-                                                  u8 *);
-        void                    (*allow_idle)(struct clk *);
-        void                    (*deny_idle)(struct clk *);
-};
-#ifdef CONFIG_ARCH_OMAP2PLUS
-/* struct clksel_rate.flags possibilities */
-#define RATE_IN_242X            (1 << 0)
-#define RATE_IN_243X            (1 << 1)
-#define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
-#define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
-#define RATE_IN_36XX            (1 << 4)
-#define RATE_IN_4430            (1 << 5)
-#define RATE_IN_TI816X          (1 << 6)
-#define RATE_IN_4460            (1 << 7)
-#define RATE_IN_AM33XX          (1 << 8)
-#define RATE_IN_TI814X          (1 << 9)
-#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
-#define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
-#define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
-#define RATE_IN_44XX            (RATE_IN_4430 | RATE_IN_4460)
-/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
-#define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
-/**
- * struct clksel_rate - register bitfield values corresponding to clk divisors
- * @val: register bitfield value (shifted to bit 0)
- * @div: clock divisor corresponding to @val
- * @flags: (see "struct clksel_rate.flags possibilities" above)
- *
- * @val should match the value of a read from struct clk.clksel_reg
- * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
- *
- * @div is the divisor that should be applied to the parent clock's rate
- * to produce the current clock's rate.
- */
-struct clksel_rate {
-        u32                     val;
-        u8                      div;
-        u16                     flags;
-};
-/**
- * struct clksel - available parent clocks, and a pointer to their divisors
- * @parent: struct clk * to a possible parent clock
- * @rates: available divisors for this parent clock
- *
- * A struct clksel is always associated with one or more struct clks
- * and one or more struct clksel_rates.
- */
-struct clksel {
-        struct clk               *parent;
-        const struct clksel_rate *rates;
-};
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-        void __iomem            *mult_div1_reg;
-        u32                     mult_mask;
-        u32                     div1_mask;
-        struct clk              *clk_bypass;
-        struct clk              *clk_ref;
-        void __iomem            *control_reg;
-        u32                     enable_mask;
-        unsigned long           last_rounded_rate;
-        u16                     last_rounded_m;
-        u16                     max_multiplier;
-        u8                      last_rounded_n;
-        u8                      min_divider;
-        u16                     max_divider;
-        u8                      modes;
-        void __iomem            *autoidle_reg;
-        void __iomem            *idlest_reg;
-        u32                     autoidle_mask;
-        u32                     freqsel_mask;
-        u32                     idlest_mask;
-        u32                     dco_mask;
-        u32                     sddiv_mask;
-        u8                      auto_recal_bit;
-        u8                      recal_en_bit;
-        u8                      recal_st_bit;
-        u8                      flags;
-};
-#endif
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- *     bits share the same register.  This flag allows the
- *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
- *     should be used.  This is a temporary solution - a better approach
- *     would be to associate clock type-specific data with the clock,
- *     similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL      (1 << 1)
-#define CLOCK_NO_IDLE_PARENT    (1 << 2)
-#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2          (1 << 5)
-/**
- * struct clk - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @ops: struct clkops * for this clock
- * @name: the name of the clock in the hardware (used in hwmod data and debug)
- * @parent: pointer to this clock's parent struct clk
- * @children: list_head connecting to the child clks' @sibling list_heads
- * @sibling: list_head connecting this clk to its parent clk's @children
- * @rate: current clock rate
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @recalc: fn ptr that returns the clock's current rate
- * @set_rate: fn ptr that can change the clock's current rate
- * @round_rate: fn ptr that can round the clock's current rate
- * @init: fn ptr to do clock-specific initialization
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @usecount: number of users that have requested this clock to be enabled
- * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- * XXX @usecount is poorly named.  It should be "enable_count" or
- * something similar.  "users" in the description refers to kernel
- * code (core code or drivers) that have called clk_enable() and not
- * yet called clk_disable(); the usecount of parent clocks is also
- * incremented by the clock code when clk_enable() is called on child
- * clocks and decremented by the clock code when clk_disable() is
- * called on child clocks.
- *
- * XXX @clkdm, @usecount, @children, @sibling should be marked for
- * internal use only.
- *
- * @children and @sibling are used to optimize parent-to-child clock
- * tree traversals.  (child-to-parent traversals use @parent.)
- *
- * XXX The notion of the clock's current rate probably needs to be
- * separated from the clock's target rate.
- */
-struct clk {
-        struct list_head        node;
-        const struct clkops     *ops;
-        const char              *name;
-        struct clk              *parent;
-        struct list_head        children;
-        struct list_head        sibling;        /* node for children */
-        unsigned long           rate;
-        void __iomem            *enable_reg;
-        unsigned long           (*recalc)(struct clk *);
-        int                     (*set_rate)(struct clk *, unsigned long);
-        long                    (*round_rate)(struct clk *, unsigned long);
-        void                    (*init)(struct clk *);
-        u8                      enable_bit;
-        s8                      usecount;
-        u8                      fixed_div;
-        u8                      flags;
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        void __iomem            *clksel_reg;
-        u32                     clksel_mask;
-        const struct clksel     *clksel;
-        struct dpll_data        *dpll_data;
-        const char              *clkdm_name;
-        struct clockdomain      *clkdm;
-#else
-        u8                      rate_offset;
-        u8                      src_offset;
-#endif
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-        struct dentry           *dent;  /* For visible tree hierarchy */
-#endif
-};
-struct clk_functions {
-        int             (*clk_enable)(struct clk *clk);
-        void            (*clk_disable)(struct clk *clk);
-        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
-        void            (*clk_allow_idle)(struct clk *clk);
-        void            (*clk_deny_idle)(struct clk *clk);
-        void            (*clk_disable_unused)(struct clk *clk);
-};
-extern int mpurate;
-extern int clk_init(struct clk_functions *custom_clocks);
-extern void clk_preinit(struct clk *clk);
-extern int clk_register(struct clk *clk);
-extern void clk_reparent(struct clk *child, struct clk *parent);
-extern void clk_unregister(struct clk *clk);
-extern void propagate_rate(struct clk *clk);
-extern void recalculate_root_clocks(void);
-extern unsigned long followparent_recalc(struct clk *clk);
-extern void clk_enable_init_clocks(void);
-unsigned long omap_fixed_divisor_recalc(struct clk *clk);
-extern struct clk *omap_clk_get_by_name(const char *name);
-extern int omap_clk_enable_autoidle_all(void);
-extern int omap_clk_disable_autoidle_all(void);
-extern const struct clkops clkops_null;
-extern struct clk dummy_ck;
-#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
deleted file mode 100644
index d1cb6f527b7e..000000000000
--- a/arch/arm/plat-omap/include/plat/common.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/common.h
- *
- * Header for code common to all OMAP machines.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
-#define __ARCH_ARM_MACH_OMAP_COMMON_H
-#include <plat/i2c.h>
-#include <plat/omap_hwmod.h>
-extern int __init omap_init_clocksource_32k(void __iomem *vbase);
-extern void __init omap_check_revision(void);
-extern void omap_reserve(void);
-extern int omap_dss_reset(struct omap_hwmod *);
-void omap_sram_init(void);
-#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/counter-32k.h b/arch/arm/plat-omap/include/plat/counter-32k.h
new file mode 100644
index 000000000000..da000d482ff2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/counter-32k.h
@@ -0,0 +1 @@
+int omap_init_clocksource_32k(void __iomem *vbase);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67da857783ce..b4516aba67ed 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/cpu.h
- *
 * OMAP cpu type detection
 *
 * Copyright (C) 2004, 2008 Nokia Corporation
@@ -30,470 +28,12 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
-#ifndef __ASSEMBLY__
+#ifdef CONFIG_ARCH_OMAP1
+#include <mach/soc.h>
-#include <linux/bitops.h>
-#include <plat/multi.h>
-/*
- * Omap device type i.e. EMU/HS/TST/GP/BAD
- */
-#define OMAP2_DEVICE_TYPE_TEST          0
-#define OMAP2_DEVICE_TYPE_EMU           1
-#define OMAP2_DEVICE_TYPE_SEC           2
-#define OMAP2_DEVICE_TYPE_GP            3
-#define OMAP2_DEVICE_TYPE_BAD           4
-int omap_type(void);
-/*
- * omap_rev bits:
- * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
- * CPU revision (See _REV_ defined in cpu.h)    [15:08]
- * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
- */
-unsigned int omap_rev(void);
-/*
- * Get the CPU revision for OMAP devices
- */
-#define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
-/*
- * Macros to group OMAP into cpu classes.
- * These can be used in most places.
- * cpu_is_omap7xx():    True for OMAP730, OMAP850
- * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
- * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
- * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
- * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
- * cpu_is_omap243x():   True for OMAP2430
- * cpu_is_omap343x():   True for OMAP3430
- * cpu_is_omap443x():   True for OMAP4430
- * cpu_is_omap446x():   True for OMAP4460
- * cpu_is_omap447x():   True for OMAP4470
- * soc_is_omap543x():   True for OMAP5430, OMAP5432
- */
-#define GET_OMAP_CLASS  (omap_rev() & 0xff)
-#define IS_OMAP_CLASS(class, id)                        \
-static inline int is_omap ##class (void)                \
-{                                                       \
-        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
-}
-#define GET_AM_CLASS    ((omap_rev() >> 24) & 0xff)
-#define IS_AM_CLASS(class, id)                          \
-static inline int is_am ##class (void)                  \
-{                                                       \
-        return (GET_AM_CLASS == (id)) ? 1 : 0;          \
-}
-#define GET_TI_CLASS    ((omap_rev() >> 24) & 0xff)
-#define IS_TI_CLASS(class, id)                  \
-static inline int is_ti ##class (void)          \
-{                                                       \
-        return (GET_TI_CLASS == (id)) ? 1 : 0;  \
-}
-#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
-#define IS_OMAP_SUBCLASS(subclass, id)                  \
-static inline int is_omap ##subclass (void)             \
-{                                                       \
-        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
-}
-#define IS_TI_SUBCLASS(subclass, id)                    \
-static inline int is_ti ##subclass (void)               \
-{                                                       \
-        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
-}
-#define IS_AM_SUBCLASS(subclass, id)                    \
-static inline int is_am ##subclass (void)               \
-{                                                       \
-        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
-}
-IS_OMAP_CLASS(7xx, 0x07)
-IS_OMAP_CLASS(15xx, 0x15)
-IS_OMAP_CLASS(16xx, 0x16)
-IS_OMAP_CLASS(24xx, 0x24)
-IS_OMAP_CLASS(34xx, 0x34)
-IS_OMAP_CLASS(44xx, 0x44)
-IS_AM_CLASS(35xx, 0x35)
-IS_OMAP_CLASS(54xx, 0x54)
-IS_AM_CLASS(33xx, 0x33)
-IS_TI_CLASS(81xx, 0x81)
-IS_OMAP_SUBCLASS(242x, 0x242)
-IS_OMAP_SUBCLASS(243x, 0x243)
-IS_OMAP_SUBCLASS(343x, 0x343)
-IS_OMAP_SUBCLASS(363x, 0x363)
-IS_OMAP_SUBCLASS(443x, 0x443)
-IS_OMAP_SUBCLASS(446x, 0x446)
-IS_OMAP_SUBCLASS(447x, 0x447)
-IS_OMAP_SUBCLASS(543x, 0x543)
-IS_TI_SUBCLASS(816x, 0x816)
-IS_TI_SUBCLASS(814x, 0x814)
-IS_AM_SUBCLASS(335x, 0x335)
-#define cpu_is_omap7xx()                0
-#define cpu_is_omap15xx()               0
-#define cpu_is_omap16xx()               0
-#define cpu_is_omap24xx()               0
-#define cpu_is_omap242x()               0
-#define cpu_is_omap243x()               0
-#define cpu_is_omap34xx()               0
-#define cpu_is_omap343x()               0
-#define cpu_is_ti81xx()                 0
-#define cpu_is_ti816x()                 0
-#define cpu_is_ti814x()                 0
-#define soc_is_am35xx()                 0
-#define soc_is_am33xx()                 0
-#define soc_is_am335x()                 0
-#define cpu_is_omap44xx()               0
-#define cpu_is_omap443x()               0
-#define cpu_is_omap446x()               0
-#define cpu_is_omap447x()               0
-#define soc_is_omap54xx()               0
-#define soc_is_omap543x()               0
-#if defined(MULTI_OMAP1)
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              is_omap7xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP850)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              is_omap7xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP15XX)
-#  undef  cpu_is_omap15xx
-#  define cpu_is_omap15xx()             is_omap15xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  undef  cpu_is_omap16xx
-#  define cpu_is_omap16xx()             is_omap16xx()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              1
-# endif
-# if defined(CONFIG_ARCH_OMAP850)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              1
-# endif
-# if defined(CONFIG_ARCH_OMAP15XX)
-#  undef  cpu_is_omap15xx
-#  define cpu_is_omap15xx()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  undef  cpu_is_omap16xx
-#  define cpu_is_omap16xx()             1
-# endif
-#endif
-#if defined(MULTI_OMAP2)
-# if defined(CONFIG_ARCH_OMAP2)
-#  undef  cpu_is_omap24xx
-#  define cpu_is_omap24xx()             is_omap24xx()
-# endif
-# if defined (CONFIG_SOC_OMAP2420)
-#  undef  cpu_is_omap242x
-#  define cpu_is_omap242x()             is_omap242x()
-# endif
-# if defined (CONFIG_SOC_OMAP2430)
-#  undef  cpu_is_omap243x
-#  define cpu_is_omap243x()             is_omap243x()
-# endif
-# if defined(CONFIG_ARCH_OMAP3)
-#  undef  cpu_is_omap34xx
-#  undef  cpu_is_omap343x
-#  define cpu_is_omap34xx()             is_omap34xx()
-#  define cpu_is_omap343x()             is_omap343x()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP2)
-#  undef  cpu_is_omap24xx
-#  define cpu_is_omap24xx()             1
-# endif
-# if defined(CONFIG_SOC_OMAP2420)
-#  undef  cpu_is_omap242x
-#  define cpu_is_omap242x()             1
-# endif
-# if defined(CONFIG_SOC_OMAP2430)
-#  undef  cpu_is_omap243x
-#  define cpu_is_omap243x()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP3)
-#  undef  cpu_is_omap34xx
-#  define cpu_is_omap34xx()             1
-# endif
-# if defined(CONFIG_SOC_OMAP3430)
-#  undef  cpu_is_omap343x
-#  define cpu_is_omap343x()             1
-# endif
-#endif
-/*
- * Macros to detect individual cpu types.
- * These are only rarely needed.
- * cpu_is_omap310():    True for OMAP310
- * cpu_is_omap1510():   True for OMAP1510
- * cpu_is_omap1610():   True for OMAP1610
- * cpu_is_omap1611():   True for OMAP1611
- * cpu_is_omap5912():   True for OMAP5912
- * cpu_is_omap1621():   True for OMAP1621
- * cpu_is_omap1710():   True for OMAP1710
- * cpu_is_omap2420():   True for OMAP2420
- * cpu_is_omap2422():   True for OMAP2422
- * cpu_is_omap2423():   True for OMAP2423
- * cpu_is_omap2430():   True for OMAP2430
- * cpu_is_omap3430():   True for OMAP3430
- */
-#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
-#define IS_OMAP_TYPE(type, id)                          \
-static inline int is_omap ##type (void)                 \
-{                                                       \
-        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
-}
-IS_OMAP_TYPE(310, 0x0310)
-IS_OMAP_TYPE(1510, 0x1510)
-IS_OMAP_TYPE(1610, 0x1610)
-IS_OMAP_TYPE(1611, 0x1611)
-IS_OMAP_TYPE(5912, 0x1611)
-IS_OMAP_TYPE(1621, 0x1621)
-IS_OMAP_TYPE(1710, 0x1710)
-IS_OMAP_TYPE(2420, 0x2420)
-IS_OMAP_TYPE(2422, 0x2422)
-IS_OMAP_TYPE(2423, 0x2423)
-IS_OMAP_TYPE(2430, 0x2430)
-IS_OMAP_TYPE(3430, 0x3430)
-#define cpu_is_omap310()                0
-#define cpu_is_omap1510()               0
-#define cpu_is_omap1610()               0
-#define cpu_is_omap5912()               0
-#define cpu_is_omap1611()               0
-#define cpu_is_omap1621()               0
-#define cpu_is_omap1710()               0
-#define cpu_is_omap2420()               0
-#define cpu_is_omap2422()               0
-#define cpu_is_omap2423()               0
-#define cpu_is_omap2430()               0
-#define cpu_is_omap3430()               0
-#define cpu_is_omap3630()               0
-#define soc_is_omap5430()               0
-/*
- * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 310 vs. 1510 and 1611B/5912 vs. 1710.
- */
-#if defined(CONFIG_ARCH_OMAP15XX)
-# undef  cpu_is_omap310
-# undef  cpu_is_omap1510
-# define cpu_is_omap310()               is_omap310()
-# define cpu_is_omap1510()              is_omap1510()
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-# undef  cpu_is_omap1610
-# undef  cpu_is_omap1611
-# undef  cpu_is_omap5912
-# undef  cpu_is_omap1621
-# undef  cpu_is_omap1710
-# define cpu_is_omap1610()              is_omap1610()
-# define cpu_is_omap1611()              is_omap1611()
-# define cpu_is_omap5912()              is_omap5912()
-# define cpu_is_omap1621()              is_omap1621()
-# define cpu_is_omap1710()              is_omap1710()
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
-# undef  cpu_is_omap2420
-# undef  cpu_is_omap2422
-# undef  cpu_is_omap2423
-# undef  cpu_is_omap2430
-# define cpu_is_omap2420()              is_omap2420()
-# define cpu_is_omap2422()              is_omap2422()
-# define cpu_is_omap2423()              is_omap2423()
-# define cpu_is_omap2430()              is_omap2430()
-#endif
-#if defined(CONFIG_ARCH_OMAP3)
-# undef cpu_is_omap3430
-# undef cpu_is_ti81xx
-# undef cpu_is_ti816x
-# undef cpu_is_ti814x
-# undef soc_is_am35xx
-# define cpu_is_omap3430()              is_omap3430()
-# undef cpu_is_omap3630
-# define cpu_is_omap3630()              is_omap363x()
-# define cpu_is_ti81xx()                is_ti81xx()
-# define cpu_is_ti816x()                is_ti816x()
-# define cpu_is_ti814x()                is_ti814x()
-# define soc_is_am35xx()                is_am35xx()
 #endif
-# if defined(CONFIG_SOC_AM33XX)
+#ifdef CONFIG_ARCH_OMAP2PLUS
-# undef soc_is_am33xx
+#include "../../mach-omap2/soc.h"
-# undef soc_is_am335x
-# define soc_is_am33xx()                is_am33xx()
-# define soc_is_am335x()                is_am335x()
 #endif
-# if defined(CONFIG_ARCH_OMAP4)
-# undef cpu_is_omap44xx
-# undef cpu_is_omap443x
-# undef cpu_is_omap446x
-# undef cpu_is_omap447x
-# define cpu_is_omap44xx()              is_omap44xx()
-# define cpu_is_omap443x()              is_omap443x()
-# define cpu_is_omap446x()              is_omap446x()
-# define cpu_is_omap447x()              is_omap447x()
-# endif
-# if defined(CONFIG_SOC_OMAP5)
-# undef soc_is_omap54xx
-# undef soc_is_omap543x
-# define soc_is_omap54xx()              is_omap54xx()
-# define soc_is_omap543x()              is_omap543x()
-#endif
-/* Macros to detect if we have OMAP1 or OMAP2 */
-#define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
-                                cpu_is_omap16xx())
-#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
-                                cpu_is_omap44xx() || soc_is_omap54xx() || \
-                                soc_is_am33xx())
-/* Various silicon revisions for omap2 */
-#define OMAP242X_CLASS          0x24200024
-#define OMAP2420_REV_ES1_0      OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
-#define OMAP243X_CLASS          0x24300024
-#define OMAP2430_REV_ES1_0      OMAP243X_CLASS
-#define OMAP343X_CLASS          0x34300034
-#define OMAP3430_REV_ES1_0      OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
-#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
-#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
-#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
-#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
-#define OMAP363X_CLASS          0x36300034
-#define OMAP3630_REV_ES1_0      OMAP363X_CLASS
-#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
-#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
-#define TI816X_CLASS            0x81600034
-#define TI8168_REV_ES1_0        TI816X_CLASS
-#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
-#define TI814X_CLASS            0x81400034
-#define TI8148_REV_ES1_0        TI814X_CLASS
-#define TI8148_REV_ES2_0        (TI814X_CLASS | (0x1 << 8))
-#define TI8148_REV_ES2_1        (TI814X_CLASS | (0x2 << 8))
-#define AM35XX_CLASS            0x35170034
-#define AM35XX_REV_ES1_0        AM35XX_CLASS
-#define AM35XX_REV_ES1_1        (AM35XX_CLASS | (0x1 << 8))
-#define AM335X_CLASS            0x33500033
-#define AM335X_REV_ES1_0        AM335X_CLASS
-#define OMAP443X_CLASS          0x44300044
-#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
-#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
-#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
-#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
-#define OMAP4430_REV_ES2_3      (OMAP443X_CLASS | (0x23 << 8))
-#define OMAP446X_CLASS          0x44600044
-#define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
-#define OMAP4460_REV_ES1_1      (OMAP446X_CLASS | (0x11 << 8))
-#define OMAP447X_CLASS          0x44700044
-#define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
-#define OMAP54XX_CLASS          0x54000054
-#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
-#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
-void omap2xxx_check_revision(void);
-void omap3xxx_check_revision(void);
-void omap4xxx_check_revision(void);
-void omap5xxx_check_revision(void);
-void omap3xxx_check_features(void);
-void ti81xx_check_features(void);
-void omap4xxx_check_features(void);
-/*
- * Runtime detection of OMAP3 features
- *
- * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
- *    family have OS-level control over the I/O chain clock.  This is
- *    to avoid a window during which wakeups could potentially be lost
- *    during powerdomain transitions.  If this bit is set, it
- *    indicates that the chip does support OS-level control of this
- *    feature.
- */
-extern u32 omap_features;
-#define OMAP3_HAS_L2CACHE               BIT(0)
-#define OMAP3_HAS_IVA                   BIT(1)
-#define OMAP3_HAS_SGX                   BIT(2)
-#define OMAP3_HAS_NEON                  BIT(3)
-#define OMAP3_HAS_ISP                   BIT(4)
-#define OMAP3_HAS_192MHZ_CLK            BIT(5)
-#define OMAP3_HAS_IO_WAKEUP             BIT(6)
-#define OMAP3_HAS_SDRC                  BIT(7)
-#define OMAP3_HAS_IO_CHAIN_CTRL         BIT(8)
-#define OMAP4_HAS_MPU_1GHZ              BIT(9)
-#define OMAP4_HAS_MPU_1_2GHZ            BIT(10)
-#define OMAP4_HAS_MPU_1_5GHZ            BIT(11)
-#define OMAP3_HAS_FEATURE(feat,flag)                    \
-static inline unsigned int omap3_has_ ##feat(void)      \
-{                                                       \
-        return omap_features & OMAP3_HAS_ ##flag;       \
-}                                                       \
-OMAP3_HAS_FEATURE(l2cache, L2CACHE)
-OMAP3_HAS_FEATURE(sgx, SGX)
-OMAP3_HAS_FEATURE(iva, IVA)
-OMAP3_HAS_FEATURE(neon, NEON)
-OMAP3_HAS_FEATURE(isp, ISP)
-OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
-OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
-OMAP3_HAS_FEATURE(sdrc, SDRC)
-OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
-/*
- * Runtime detection of OMAP4 features
- */
-#define OMAP4_HAS_FEATURE(feat, flag)                   \
-static inline unsigned int omap4_has_ ##feat(void)      \
-{                                                       \
-        return omap_features & OMAP4_HAS_ ##flag;       \
-}                                                       \
-OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
-OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
-OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
-#endif  /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h
index a4edbd2f7484..8fc4287222dd 100644
--- a/arch/arm/mach-omap2/debug-devices.h
+++ b/arch/arm/plat-omap/include/plat/debug-devices.h
@@ -1,9 +1,2 @@
-#ifndef _OMAP_DEBUG_DEVICES_H
-#define _OMAP_DEBUG_DEVICES_H
-#include <linux/types.h>
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h
deleted file mode 100644
index 1f767cb2f38a..000000000000
--- a/arch/arm/plat-omap/include/plat/dma-44xx.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * OMAP4 SDMA channel definitions
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- * Paul Walmsley (paul@pwsan.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
-#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
-#define OMAP44XX_DMA_SYS_REQ0                   2
-#define OMAP44XX_DMA_SYS_REQ1                   3
-#define OMAP44XX_DMA_GPMC                       4
-#define OMAP44XX_DMA_DSS_DISPC_REQ              6
-#define OMAP44XX_DMA_SYS_REQ2                   7
-#define OMAP44XX_DMA_MCASP1_AXEVT               8
-#define OMAP44XX_DMA_ISS_REQ1                   9
-#define OMAP44XX_DMA_ISS_REQ2                   10
-#define OMAP44XX_DMA_MCASP1_AREVT               11
-#define OMAP44XX_DMA_ISS_REQ3                   12
-#define OMAP44XX_DMA_ISS_REQ4                   13
-#define OMAP44XX_DMA_DSS_RFBI_REQ               14
-#define OMAP44XX_DMA_SPI3_TX0                   15
-#define OMAP44XX_DMA_SPI3_RX0                   16
-#define OMAP44XX_DMA_MCBSP2_TX                  17
-#define OMAP44XX_DMA_MCBSP2_RX                  18
-#define OMAP44XX_DMA_MCBSP3_TX                  19
-#define OMAP44XX_DMA_MCBSP3_RX                  20
-#define OMAP44XX_DMA_C2C_SSCM_GPO0              21
-#define OMAP44XX_DMA_C2C_SSCM_GPO1              22
-#define OMAP44XX_DMA_SPI3_TX1                   23
-#define OMAP44XX_DMA_SPI3_RX1                   24
-#define OMAP44XX_DMA_I2C3_TX                    25
-#define OMAP44XX_DMA_I2C3_RX                    26
-#define OMAP44XX_DMA_I2C1_TX                    27
-#define OMAP44XX_DMA_I2C1_RX                    28
-#define OMAP44XX_DMA_I2C2_TX                    29
-#define OMAP44XX_DMA_I2C2_RX                    30
-#define OMAP44XX_DMA_MCBSP4_TX                  31
-#define OMAP44XX_DMA_MCBSP4_RX                  32
-#define OMAP44XX_DMA_MCBSP1_TX                  33
-#define OMAP44XX_DMA_MCBSP1_RX                  34
-#define OMAP44XX_DMA_SPI1_TX0                   35
-#define OMAP44XX_DMA_SPI1_RX0                   36
-#define OMAP44XX_DMA_SPI1_TX1                   37
-#define OMAP44XX_DMA_SPI1_RX1                   38
-#define OMAP44XX_DMA_SPI1_TX2                   39
-#define OMAP44XX_DMA_SPI1_RX2                   40
-#define OMAP44XX_DMA_SPI1_TX3                   41
-#define OMAP44XX_DMA_SPI1_RX3                   42
-#define OMAP44XX_DMA_SPI2_TX0                   43
-#define OMAP44XX_DMA_SPI2_RX0                   44
-#define OMAP44XX_DMA_SPI2_TX1                   45
-#define OMAP44XX_DMA_SPI2_RX1                   46
-#define OMAP44XX_DMA_MMC2_TX                    47
-#define OMAP44XX_DMA_MMC2_RX                    48
-#define OMAP44XX_DMA_UART1_TX                   49
-#define OMAP44XX_DMA_UART1_RX                   50
-#define OMAP44XX_DMA_UART2_TX                   51
-#define OMAP44XX_DMA_UART2_RX                   52
-#define OMAP44XX_DMA_UART3_TX                   53
-#define OMAP44XX_DMA_UART3_RX                   54
-#define OMAP44XX_DMA_UART4_TX                   55
-#define OMAP44XX_DMA_UART4_RX                   56
-#define OMAP44XX_DMA_MMC4_TX                    57
-#define OMAP44XX_DMA_MMC4_RX                    58
-#define OMAP44XX_DMA_MMC5_TX                    59
-#define OMAP44XX_DMA_MMC5_RX                    60
-#define OMAP44XX_DMA_MMC1_TX                    61
-#define OMAP44XX_DMA_MMC1_RX                    62
-#define OMAP44XX_DMA_SYS_REQ3                   64
-#define OMAP44XX_DMA_MCPDM_UP                   65
-#define OMAP44XX_DMA_MCPDM_DL                   66
-#define OMAP44XX_DMA_DMIC_REQ                   67
-#define OMAP44XX_DMA_C2C_SSCM_GPO2              68
-#define OMAP44XX_DMA_C2C_SSCM_GPO3              69
-#define OMAP44XX_DMA_SPI4_TX0                   70
-#define OMAP44XX_DMA_SPI4_RX0                   71
-#define OMAP44XX_DMA_DSS_DSI1_REQ0              72
-#define OMAP44XX_DMA_DSS_DSI1_REQ1              73
-#define OMAP44XX_DMA_DSS_DSI1_REQ2              74
-#define OMAP44XX_DMA_DSS_DSI1_REQ3              75
-#define OMAP44XX_DMA_DSS_HDMI_REQ               76
-#define OMAP44XX_DMA_MMC3_TX                    77
-#define OMAP44XX_DMA_MMC3_RX                    78
-#define OMAP44XX_DMA_USIM_TX                    79
-#define OMAP44XX_DMA_USIM_RX                    80
-#define OMAP44XX_DMA_DSS_DSI2_REQ0              81
-#define OMAP44XX_DMA_DSS_DSI2_REQ1              82
-#define OMAP44XX_DMA_DSS_DSI2_REQ2              83
-#define OMAP44XX_DMA_DSS_DSI2_REQ3              84
-#define OMAP44XX_DMA_SLIMBUS1_TX0               85
-#define OMAP44XX_DMA_SLIMBUS1_TX1               86
-#define OMAP44XX_DMA_SLIMBUS1_TX2               87
-#define OMAP44XX_DMA_SLIMBUS1_TX3               88
-#define OMAP44XX_DMA_SLIMBUS1_RX0               89
-#define OMAP44XX_DMA_SLIMBUS1_RX1               90
-#define OMAP44XX_DMA_SLIMBUS1_RX2               91
-#define OMAP44XX_DMA_SLIMBUS1_RX3               92
-#define OMAP44XX_DMA_SLIMBUS2_TX0               93
-#define OMAP44XX_DMA_SLIMBUS2_TX1               94
-#define OMAP44XX_DMA_SLIMBUS2_TX2               95
-#define OMAP44XX_DMA_SLIMBUS2_TX3               96
-#define OMAP44XX_DMA_SLIMBUS2_RX0               97
-#define OMAP44XX_DMA_SLIMBUS2_RX1               98
-#define OMAP44XX_DMA_SLIMBUS2_RX2               99
-#define OMAP44XX_DMA_SLIMBUS2_RX3               100
-#define OMAP44XX_DMA_ABE_REQ_0                  101
-#define OMAP44XX_DMA_ABE_REQ_1                  102
-#define OMAP44XX_DMA_ABE_REQ_2                  103
-#define OMAP44XX_DMA_ABE_REQ_3                  104
-#define OMAP44XX_DMA_ABE_REQ_4                  105
-#define OMAP44XX_DMA_ABE_REQ_5                  106
-#define OMAP44XX_DMA_ABE_REQ_6                  107
-#define OMAP44XX_DMA_ABE_REQ_7                  108
-#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ          109
-#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ         110
-#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ        111
-#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ          112
-#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ         113
-#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ        114
-#define OMAP44XX_DMA_DES_P_CTX_IN_REQ           115
-#define OMAP44XX_DMA_DES_P_DATA_IN_REQ          116
-#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ         117
-#define OMAP44XX_DMA_SHA2_CTXIN_P               118
-#define OMAP44XX_DMA_SHA2_DIN_P                 119
-#define OMAP44XX_DMA_SHA2_CTXOUT_P              120
-#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ     121
-#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ     122
-#define OMAP44XX_DMA_I2C4_TX                    124
-#define OMAP44XX_DMA_I2C4_RX                    125
-#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
deleted file mode 100644
index 0a87b052f8f7..000000000000
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/dma.h
- *
- *  Copyright (C) 2003 Nokia Corporation
- *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#include <linux/platform_device.h>
-/*
- * TODO: These dma channel defines should go away once all
- * the omap drivers hwmod adapted.
- */
-/* Move omap4 specific defines to dma-44xx.h */
-#include "dma-44xx.h"
-#define INT_DMA_LCD                     25
-/* DMA channels for omap1 */
-#define OMAP_DMA_NO_DEVICE              0
-#define OMAP_DMA_MCSI1_TX               1
-#define OMAP_DMA_MCSI1_RX               2
-#define OMAP_DMA_I2C_RX                 3
-#define OMAP_DMA_I2C_TX                 4
-#define OMAP_DMA_EXT_NDMA_REQ           5
-#define OMAP_DMA_EXT_NDMA_REQ2          6
-#define OMAP_DMA_UWIRE_TX               7
-#define OMAP_DMA_MCBSP1_TX              8
-#define OMAP_DMA_MCBSP1_RX              9
-#define OMAP_DMA_MCBSP3_TX              10
-#define OMAP_DMA_MCBSP3_RX              11
-#define OMAP_DMA_UART1_TX               12
-#define OMAP_DMA_UART1_RX               13
-#define OMAP_DMA_UART2_TX               14
-#define OMAP_DMA_UART2_RX               15
-#define OMAP_DMA_MCBSP2_TX              16
-#define OMAP_DMA_MCBSP2_RX              17
-#define OMAP_DMA_UART3_TX               18
-#define OMAP_DMA_UART3_RX               19
-#define OMAP_DMA_CAMERA_IF_RX           20
-#define OMAP_DMA_MMC_TX                 21
-#define OMAP_DMA_MMC_RX                 22
-#define OMAP_DMA_NAND                   23
-#define OMAP_DMA_IRQ_LCD_LINE           24
-#define OMAP_DMA_MEMORY_STICK           25
-#define OMAP_DMA_USB_W2FC_RX0           26
-#define OMAP_DMA_USB_W2FC_RX1           27
-#define OMAP_DMA_USB_W2FC_RX2           28
-#define OMAP_DMA_USB_W2FC_TX0           29
-#define OMAP_DMA_USB_W2FC_TX1           30
-#define OMAP_DMA_USB_W2FC_TX2           31
-/* These are only for 1610 */
-#define OMAP_DMA_CRYPTO_DES_IN          32
-#define OMAP_DMA_SPI_TX                 33
-#define OMAP_DMA_SPI_RX                 34
-#define OMAP_DMA_CRYPTO_HASH            35
-#define OMAP_DMA_CCP_ATTN               36
-#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
-#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
-#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
-#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
-#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
-#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
-#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
-#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
-#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
-#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
-#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
-#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
-#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
-#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
-#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
-#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
-#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
-#define OMAP_DMA_MMC2_TX                54
-#define OMAP_DMA_MMC2_RX                55
-#define OMAP_DMA_CRYPTO_DES_OUT         56
-/* DMA channels for 24xx */
-#define OMAP24XX_DMA_NO_DEVICE          0
-#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
-#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
-#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
-#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
-#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
-#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
-#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
-#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
-#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
-#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
-#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
-#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
-#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
-#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
-#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
-#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
-#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
-#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
-#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
-#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
-#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
-#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
-#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
-#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
-#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
-#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
-#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
-#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
-#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
-#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
-#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
-#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
-#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
-#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
-#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
-#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
-#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
-#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
-#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
-#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
-#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
-#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
-#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
-#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
-#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
-/* Only for AM35xx */
-#define AM35XX_DMA_UART4_TX             54
-#define AM35XX_DMA_UART4_RX             55
-/*----------------------------------------------------------------------------*/
-#define OMAP1_DMA_TOUT_IRQ              (1 << 0)
-#define OMAP_DMA_DROP_IRQ               (1 << 1)
-#define OMAP_DMA_HALF_IRQ               (1 << 2)
-#define OMAP_DMA_FRAME_IRQ              (1 << 3)
-#define OMAP_DMA_LAST_IRQ               (1 << 4)
-#define OMAP_DMA_BLOCK_IRQ              (1 << 5)
-#define OMAP1_DMA_SYNC_IRQ              (1 << 6)
-#define OMAP2_DMA_PKT_IRQ               (1 << 7)
-#define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
-#define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
-#define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
-#define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
-#define OMAP_DMA_CCR_EN                 (1 << 7)
-#define OMAP_DMA_CCR_RD_ACTIVE          (1 << 9)
-#define OMAP_DMA_CCR_WR_ACTIVE          (1 << 10)
-#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC   (1 << 24)
-#define OMAP_DMA_CCR_BUFFERING_DISABLE  (1 << 25)
-#define OMAP_DMA_DATA_TYPE_S8           0x00
-#define OMAP_DMA_DATA_TYPE_S16          0x01
-#define OMAP_DMA_DATA_TYPE_S32          0x02
-#define OMAP_DMA_SYNC_ELEMENT           0x00
-#define OMAP_DMA_SYNC_FRAME             0x01
-#define OMAP_DMA_SYNC_BLOCK             0x02
-#define OMAP_DMA_SYNC_PACKET            0x03
-#define OMAP_DMA_DST_SYNC_PREFETCH      0x02
-#define OMAP_DMA_SRC_SYNC               0x01
-#define OMAP_DMA_DST_SYNC               0x00
-#define OMAP_DMA_PORT_EMIFF             0x00
-#define OMAP_DMA_PORT_EMIFS             0x01
-#define OMAP_DMA_PORT_OCP_T1            0x02
-#define OMAP_DMA_PORT_TIPB              0x03
-#define OMAP_DMA_PORT_OCP_T2            0x04
-#define OMAP_DMA_PORT_MPUI              0x05
-#define OMAP_DMA_AMODE_CONSTANT         0x00
-#define OMAP_DMA_AMODE_POST_INC         0x01
-#define OMAP_DMA_AMODE_SINGLE_IDX       0x02
-#define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
-#define DMA_DEFAULT_FIFO_DEPTH          0x10
-#define DMA_DEFAULT_ARB_RATE            0x01
-/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
-#define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
-#define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
-#define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
-#define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
-#define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
-#define DMA_THREAD_FIFO_75              (0x01 << 14)
-#define DMA_THREAD_FIFO_25              (0x02 << 14)
-#define DMA_THREAD_FIFO_50              (0x03 << 14)
-/* DMA4_OCP_SYSCONFIG bits */
-#define DMA_SYSCONFIG_MIDLEMODE_MASK            (3 << 12)
-#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK        (3 << 8)
-#define DMA_SYSCONFIG_EMUFREE                   (1 << 5)
-#define DMA_SYSCONFIG_SIDLEMODE_MASK            (3 << 3)
-#define DMA_SYSCONFIG_SOFTRESET                 (1 << 2)
-#define DMA_SYSCONFIG_AUTOIDLE                  (1 << 0)
-#define DMA_SYSCONFIG_MIDLEMODE(n)              ((n) << 12)
-#define DMA_SYSCONFIG_SIDLEMODE(n)              ((n) << 3)
-#define DMA_IDLEMODE_SMARTIDLE                  0x2
-#define DMA_IDLEMODE_NO_IDLE                    0x1
-#define DMA_IDLEMODE_FORCE_IDLE                 0x0
-/* Chaining modes*/
-#ifndef CONFIG_ARCH_OMAP1
-#define OMAP_DMA_STATIC_CHAIN           0x1
-#define OMAP_DMA_DYNAMIC_CHAIN          0x2
-#define OMAP_DMA_CHAIN_ACTIVE           0x1
-#define OMAP_DMA_CHAIN_INACTIVE         0x0
-#endif
-#define DMA_CH_PRIO_HIGH                0x1
-#define DMA_CH_PRIO_LOW                 0x0 /* Def */
-/* Errata handling */
-#define IS_DMA_ERRATA(id)               (errata & (id))
-#define SET_DMA_ERRATA(id)              (errata |= (id))
-#define DMA_ERRATA_IFRAME_BUFFERING     BIT(0x0)
-#define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
-#define DMA_ERRATA_i378                 BIT(0x2)
-#define DMA_ERRATA_i541                 BIT(0x3)
-#define DMA_ERRATA_i88                  BIT(0x4)
-#define DMA_ERRATA_3_3                  BIT(0x5)
-#define DMA_ROMCODE_BUG                 BIT(0x6)
-/* Attributes for OMAP DMA Contrller */
-#define DMA_LINKED_LCH                  BIT(0x0)
-#define GLOBAL_PRIORITY                 BIT(0x1)
-#define RESERVE_CHANNEL                 BIT(0x2)
-#define IS_CSSA_32                      BIT(0x3)
-#define IS_CDSA_32                      BIT(0x4)
-#define IS_RW_PRIORITY                  BIT(0x5)
-#define ENABLE_1510_MODE                BIT(0x6)
-#define SRC_PORT                        BIT(0x7)
-#define DST_PORT                        BIT(0x8)
-#define SRC_INDEX                       BIT(0x9)
-#define DST_INDEX                       BIT(0xA)
-#define IS_BURST_ONLY4                  BIT(0xB)
-#define CLEAR_CSR_ON_READ               BIT(0xC)
-#define IS_WORD_16                      BIT(0xD)
-/* Defines for DMA Capabilities */
-#define DMA_HAS_TRANSPARENT_CAPS        (0x1 << 18)
-#define DMA_HAS_CONSTANT_FILL_CAPS      (0x1 << 19)
-#define DMA_HAS_DESCRIPTOR_CAPS         (0x3 << 20)
-enum omap_reg_offsets {
-GCR,            GSCR,           GRST1,          HW_ID,
-PCH2_ID,        PCH0_ID,        PCH1_ID,        PCHG_ID,
-PCHD_ID,        CAPS_0,         CAPS_1,         CAPS_2,
-CAPS_3,         CAPS_4,         PCH2_SR,        PCH0_SR,
-PCH1_SR,        PCHD_SR,        REVISION,       IRQSTATUS_L0,
-IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
-IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
-OCP_SYSCONFIG,
-/* omap1+ specific */
-CPC, CCR2, LCH_CTRL,
-/* Common registers for all omap's */
-CSDP,           CCR,            CICR,           CSR,
-CEN,            CFN,            CSFI,           CSEI,
-CSAC,           CDAC,           CDEI,
-CDFI,           CLNK_CTRL,
-/* Channel specific registers */
-CSSA,           CDSA,           COLOR,
-CCEN,           CCFN,
-/* omap3630 and omap4 specific */
-CDP,            CNDP,           CCDN,
-};
-enum omap_dma_burst_mode {
-        OMAP_DMA_DATA_BURST_DIS = 0,
-        OMAP_DMA_DATA_BURST_4,
-        OMAP_DMA_DATA_BURST_8,
-        OMAP_DMA_DATA_BURST_16,
-};
-enum end_type {
-        OMAP_DMA_LITTLE_ENDIAN = 0,
-        OMAP_DMA_BIG_ENDIAN
-};
-enum omap_dma_color_mode {
-        OMAP_DMA_COLOR_DIS = 0,
-        OMAP_DMA_CONSTANT_FILL,
-        OMAP_DMA_TRANSPARENT_COPY
-};
-enum omap_dma_write_mode {
-        OMAP_DMA_WRITE_NON_POSTED = 0,
-        OMAP_DMA_WRITE_POSTED,
-        OMAP_DMA_WRITE_LAST_NON_POSTED
-};
-enum omap_dma_channel_mode {
-        OMAP_DMA_LCH_2D = 0,
-        OMAP_DMA_LCH_G,
-        OMAP_DMA_LCH_P,
-        OMAP_DMA_LCH_PD
-};
-struct omap_dma_channel_params {
-        int data_type;          /* data type 8,16,32 */
-        int elem_count;         /* number of elements in a frame */
-        int frame_count;        /* number of frames in a element */
-        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int src_amode;          /* constant, post increment, indexed,
-                                        double indexed */
-        unsigned long src_start;        /* source address : physical */
-        int src_ei;             /* source element index */
-        int src_fi;             /* source frame index */
-        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int dst_amode;          /* constant, post increment, indexed,
-                                        double indexed */
-        unsigned long dst_start;        /* source address : physical */
-        int dst_ei;             /* source element index */
-        int dst_fi;             /* source frame index */
-        int trigger;            /* trigger attached if the channel is
-                                        synchronized */
-        int sync_mode;          /* sycn on element, frame , block or packet */
-        int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
-        int ie;                 /* interrupt enabled */
-        unsigned char read_prio;/* read priority */
-        unsigned char write_prio;/* write priority */
-#ifndef CONFIG_ARCH_OMAP1
-        enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
-#endif
-};
-struct omap_dma_lch {
-        int next_lch;
-        int dev_id;
-        u16 saved_csr;
-        u16 enabled_irqs;
-        const char *dev_name;
-        void (*callback)(int lch, u16 ch_status, void *data);
-        void *data;
-        long flags;
-        /* required for Dynamic chaining */
-        int prev_linked_ch;
-        int next_linked_ch;
-        int state;
-        int chain_id;
-        int status;
-};
-struct omap_dma_dev_attr {
-        u32 dev_caps;
-        u16 lch_count;
-        u16 chan_count;
-        struct omap_dma_lch *chan;
-};
-/* System DMA platform data structure */
-struct omap_system_dma_plat_info {
-        struct omap_dma_dev_attr *dma_attr;
-        u32 errata;
-        void (*disable_irq_lch)(int lch);
-        void (*show_dma_caps)(void);
-        void (*clear_lch_regs)(int lch);
-        void (*clear_dma)(int lch);
-        void (*dma_write)(u32 val, int reg, int lch);
-        u32 (*dma_read)(int reg, int lch);
-};
-extern void __init omap_init_consistent_dma_size(void);
-extern void omap_set_dma_priority(int lch, int dst_port, int priority);
-extern int omap_request_dma(int dev_id, const char *dev_name,
-                        void (*callback)(int lch, u16 ch_status, void *data),
-                        void *data, int *dma_ch);
-extern void omap_enable_dma_irq(int ch, u16 irq_bits);
-extern void omap_disable_dma_irq(int ch, u16 irq_bits);
-extern void omap_free_dma(int ch);
-extern void omap_start_dma(int lch);
-extern void omap_stop_dma(int lch);
-extern void omap_set_dma_transfer_params(int lch, int data_type,
-                                         int elem_count, int frame_count,
-                                         int sync_mode,
-                                         int dma_trigger, int src_or_dst_synch);
-extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
-                                    u32 color);
-extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
-extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
-extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
-                                    unsigned long src_start,
-                                    int src_ei, int src_fi);
-extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
-extern void omap_set_dma_src_data_pack(int lch, int enable);
-extern void omap_set_dma_src_burst_mode(int lch,
-                                        enum omap_dma_burst_mode burst_mode);
-extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
-                                     unsigned long dest_start,
-                                     int dst_ei, int dst_fi);
-extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
-extern void omap_set_dma_dest_data_pack(int lch, int enable);
-extern void omap_set_dma_dest_burst_mode(int lch,
-                                         enum omap_dma_burst_mode burst_mode);
-extern void omap_set_dma_params(int lch,
-                                struct omap_dma_channel_params *params);
-extern void omap_dma_link_lch(int lch_head, int lch_queue);
-extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
-extern int omap_set_dma_callback(int lch,
-                        void (*callback)(int lch, u16 ch_status, void *data),
-                        void *data);
-extern dma_addr_t omap_get_dma_src_pos(int lch);
-extern dma_addr_t omap_get_dma_dst_pos(int lch);
-extern void omap_clear_dma(int lch);
-extern int omap_get_dma_active_status(int lch);
-extern int omap_dma_running(void);
-extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
-                                       int tparams);
-extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
-                                 unsigned char write_prio);
-extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
-extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
-extern int omap_get_dma_index(int lch, int *ei, int *fi);
-void omap_dma_global_context_save(void);
-void omap_dma_global_context_restore(void);
-extern void omap_dma_disable_irq(int lch);
-/* Chaining APIs */
-#ifndef CONFIG_ARCH_OMAP1
-extern int omap_request_dma_chain(int dev_id, const char *dev_name,
-                                  void (*callback) (int lch, u16 ch_status,
-                                                    void *data),
-                                  int *chain_id, int no_of_chans,
-                                  int chain_mode,
-                                  struct omap_dma_channel_params params);
-extern int omap_free_dma_chain(int chain_id);
-extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
-                                     int dest_start, int elem_count,
-                                     int frame_count, void *callbk_data);
-extern int omap_start_dma_chain_transfers(int chain_id);
-extern int omap_stop_dma_chain_transfers(int chain_id);
-extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
-extern int omap_get_dma_chain_dst_pos(int chain_id);
-extern int omap_get_dma_chain_src_pos(int chain_id);
-extern int omap_modify_dma_chain_params(int chain_id,
-                                        struct omap_dma_channel_params params);
-extern int omap_dma_chain_status(int chain_id);
-#endif
-#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
-#include <mach/lcd_dma.h>
-#else
-static inline int omap_lcd_dma_running(void)
-{
-        return 0;
-}
-#endif
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 85868e98c11c..a3fbc48c332e 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -32,7 +32,6 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
@@ -55,6 +54,10 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
+/* posted mode types */
+#define OMAP_TIMER_NONPOSTED                    0x00
+#define OMAP_TIMER_POSTED                       0x01
 /* timer capabilities used in hwmod database */
 #define OMAP_TIMER_SECURE                               0x80000000
 #define OMAP_TIMER_ALWON                                0x40000000
@@ -62,16 +65,22 @@
 #define OMAP_TIMER_NEEDS_RESET                          0x10000000
 #define OMAP_TIMER_HAS_DSP_IRQ                          0x08000000
+/*
+ * timer errata flags
+ *
+ * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
+ * errata prevents us from using posted mode on these devices, unless the
+ * timer counter register is never read. For more details please refer to
+ * the OMAP3/4/5 errata documents.
+ */
+#define OMAP_TIMER_ERRATA_I103_I767                     0x80000000
 struct omap_timer_capability_dev_attr {
        u32 timer_capability;
 };
-struct omap_dm_timer;
 struct timer_regs {
        u32 tidr;
-        u32 tistat;
-        u32 tisr;
        u32 tier;
        u32 twer;
        u32 tclr;
@@ -90,15 +99,35 @@ struct timer_regs {
        u32 towr;
 };
-struct dmtimer_platform_data {
+struct omap_dm_timer {
-        /* set_timer_src - Only used for OMAP1 devices */
+        int id;
-        int (*set_timer_src)(struct platform_device *pdev, int source);
+        int irq;
-        u32 timer_capability;
+        struct clk *fclk;
+        void __iomem    *io_base;
+        void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
+        void __iomem    *irq_ena;       /* irq enable */
+        void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
+        void __iomem    *pend;          /* write pending */
+        void __iomem    *func_base;     /* function register base */
+        unsigned long rate;
+        unsigned reserved:1;
+        unsigned posted:1;
+        struct timer_regs context;
+        int (*get_context_loss_count)(struct device *);
+        int ctx_loss_count;
+        int revision;
+        u32 capability;
+        u32 errata;
+        struct platform_device *pdev;
+        struct list_head node;
 };
 int omap_dm_timer_reserve_systimer(int id);
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
+struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
 int omap_dm_timer_free(struct omap_dm_timer *timer);
 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 void omap_dm_timer_disable(struct omap_dm_timer *timer);
@@ -120,6 +149,7 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, i
 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
@@ -245,33 +275,6 @@ int omap_dm_timers_active(void);
 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
                (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
-struct omap_dm_timer {
-        unsigned long phys_base;
-        int id;
-        int irq;
-        struct clk *fclk;
-        void __iomem    *io_base;
-        void __iomem    *sys_stat;      /* TISTAT timer status */
-        void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
-        void __iomem    *irq_ena;       /* irq enable */
-        void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
-        void __iomem    *pend;          /* write pending */
-        void __iomem    *func_base;     /* function register base */
-        unsigned long rate;
-        unsigned reserved:1;
-        unsigned posted:1;
-        struct timer_regs context;
-        int ctx_loss_count;
-        int revision;
-        u32 capability;
-        struct platform_device *pdev;
-        struct list_head node;
-};
-int omap_dm_timer_prepare(struct omap_dm_timer *timer);
 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
                                                int posted)
 {
@@ -300,16 +303,13 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
        tidr = __raw_readl(timer->io_base);
        if (!(tidr >> 16)) {
                timer->revision = 1;
-                timer->sys_stat = timer->io_base +
-                                OMAP_TIMER_V1_SYS_STAT_OFFSET;
                timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
                timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
-                timer->irq_dis = NULL;
+                timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
                timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
                timer->func_base = timer->io_base;
        } else {
                timer->revision = 2;
-                timer->sys_stat = NULL;
                timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
                timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
                timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
@@ -320,45 +320,44 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
        }
 }
-/* Assumes the source clock has been set by caller */
+/*
-static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
+ * __omap_dm_timer_enable_posted - enables write posted mode
-                                        int autoidle, int wakeup)
+ * @timer:      pointer to timer instance handle
+ *
+ * Enables the write posted mode for the timer. When posted mode is enabled
+ * writes to certain timer registers are immediately acknowledged by the
+ * internal bus and hence prevents stalling the CPU waiting for the write to
+ * complete. Enabling this feature can improve performance for writing to the
+ * timer registers.
+ */
+static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
 {
-        u32 l;
+        if (timer->posted)
+                return;
-        l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
+        if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
-        l |= 0x02 << 3;  /* Set to smart-idle mode */
+                return;
-        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
-        if (autoidle)
-                l |= 0x1 << 0;
-        if (wakeup)
-                l |= 1 << 2;
-        __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
-        /* Match hardware reset default of posted mode */
        __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
-                                        OMAP_TIMER_CTRL_POSTED, 0);
+                              OMAP_TIMER_CTRL_POSTED, 0);
+        timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
+        timer->posted = OMAP_TIMER_POSTED;
 }
-static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
+/**
-                                                struct clk *parent)
+ * __omap_dm_timer_override_errata - override errata flags for a timer
+ * @timer:      pointer to timer handle
+ * @errata:     errata flags to be ignored
+ *
+ * For a given timer, override a timer errata by clearing the flags
+ * specified by the errata argument. A specific erratum should only be
+ * overridden for a timer if the timer is used in such a way the erratum
+ * has no impact.
+ */
+static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
+                                                   u32 errata)
 {
-        int ret;
+        timer->errata &= ~errata;
-        clk_disable(timer_fck);
-        ret = clk_set_parent(timer_fck, parent);
-        clk_enable(timer_fck);
-        /*
-         * When the functional clock disappears, too quick writes seem
-         * to cause an abort. XXX Is this still necessary?
-         */
-        __delay(300000);
-        return ret;
 }
 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
deleted file mode 100644
index bd3c6324ae1f..000000000000
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/fpga.h
- *
- * Interrupt handler for OMAP-1510 FPGA
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_OMAP_FPGA_H
-#define __ASM_ARCH_OMAP_FPGA_H
-extern void omap1510_fpga_init_irq(void);
-#define fpga_read(reg)                  __raw_readb(reg)
-#define fpga_write(val, reg)            __raw_writeb(val, reg)
-/*
- * ---------------------------------------------------------------------------
- *  H2/P2 Debug board FPGA
- * ---------------------------------------------------------------------------
- */
-/* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE              0xE8000000              /* VA */
-#define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
-#define H2P2_DBG_FPGA_START             0x04000000              /* PA */
-#define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV          IOMEM(H2P2_DBG_FPGA_BASE + 0x10)        /* FPGA Revision */
-#define H2P2_DBG_FPGA_BOARD_REV         IOMEM(H2P2_DBG_FPGA_BASE + 0x12)        /* Board Revision */
-#define H2P2_DBG_FPGA_GPIO              IOMEM(H2P2_DBG_FPGA_BASE + 0x14)        /* GPIO outputs */
-#define H2P2_DBG_FPGA_LEDS              IOMEM(H2P2_DBG_FPGA_BASE + 0x16)        /* LEDs outputs */
-#define H2P2_DBG_FPGA_MISC_INPUTS       IOMEM(H2P2_DBG_FPGA_BASE + 0x18)        /* Misc inputs */
-#define H2P2_DBG_FPGA_LAN_STATUS        IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)        /* LAN Status line */
-#define H2P2_DBG_FPGA_LAN_RESET         IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)        /* LAN Reset line */
-/* NOTE:  most boards don't have a static mapping for the FPGA ... */
-struct h2p2_dbg_fpga {
-        /* offset 0x00 */
-        u16             smc91x[8];
-        /* offset 0x10 */
-        u16             fpga_rev;
-        u16             board_rev;
-        u16             gpio_outputs;
-        u16             leds;
-        /* offset 0x18 */
-        u16             misc_inputs;
-        u16             lan_status;
-        u16             lan_reset;
-        u16             reserved0;
-        /* offset 0x20 */
-        u16             ps2_data;
-        u16             ps2_ctrl;
-        /* plus also 4 rs232 ports ... */
-};
-/* LEDs definition on debug board (16 LEDs, all physically green) */
-#define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
-#define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
-#define H2P2_DBG_FPGA_LED_RED           (1 << 13)
-#define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
-/*  cpu0 load-meter LEDs */
-#define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
-#define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
-#define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
-#define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
-#define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
-/*
- * ---------------------------------------------------------------------------
- *  OMAP-1510 FPGA
- * ---------------------------------------------------------------------------
- */
-#define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
-#define OMAP1510_FPGA_SIZE              SZ_4K
-#define OMAP1510_FPGA_START             0x08000000              /* PA */
-/* Revision */
-#define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
-/* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
-/* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
-/* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
-#define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
-#define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
-#define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
-#define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
-#define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
-#define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
-/*
- * Power up Giga UART driver, turn on HID clock.
- * Turn off BT power, since we're not using it and it
- * draws power.
- */
-#define OMAP1510_FPGA_RESET_VALUE               0x42
-#define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
-#define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
-#define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
-#define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
-#define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
-#define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
-#define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
-#define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
-/*
- * Innovator/OMAP1510 FPGA HID register bit definitions
- */
-#define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
-#define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
-#define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
-#define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
-#define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
-#define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
-#define OMAP1510_FPGA_HID_rsrvd (1<<6)
-#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
-/* The FPGA IRQ is cascaded through GPIO_13 */
-#define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
-/* IRQ Numbers for interrupts muxed through the FPGA */
-#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
-#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
-#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
-#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
-#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
-#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
-#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
-#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
-#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
-#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
-#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
-#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
-#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
-#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
-#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
-#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
-#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
-#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
-#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
-#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
-#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
-#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
-#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
-#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
-#endif
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 7c22b9e10dc3..7a9028cb5a75 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,11 +18,15 @@
 * 02110-1301 USA
 *
 */
-#ifndef __ASM__ARCH_OMAP_I2C_H
-#define __ASM__ARCH_OMAP_I2C_H
-#include <linux/i2c.h>
+#ifndef __PLAT_OMAP_I2C_H
-#include <linux/i2c-omap.h>
+#define __PLAT_OMAP_I2C_H
+struct i2c_board_info;
+struct omap_i2c_bus_platform_data;
+int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
+                        int bus_id);
 #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -37,23 +41,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
-/**
- * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
- * @fifo_depth: total controller FIFO size (in bytes)
- * @flags: differences in hardware support capability
- *
- * @fifo_depth represents what exists on the hardware, not what is
- * actually configured at runtime by the device driver.
- */
-struct omap_i2c_dev_attr {
-        u8      fifo_depth;
-        u32     flags;
-};
-void __init omap1_i2c_mux_pins(int bus_id);
-void __init omap2_i2c_mux_pins(int bus_id);
 struct omap_hwmod;
 int omap_i2c_reset(struct omap_hwmod *oh);
-#endif /* __ASM__ARCH_OMAP_I2C_H */
+#endif /* __PLAT_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
deleted file mode 100644
index 68b5f0362f35..000000000000
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * omap iommu: main structures
- *
- * Copyright (C) 2008-2009 Nokia Corporation
- *
- * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __MACH_IOMMU_H
-#define __MACH_IOMMU_H
-struct iotlb_entry {
-        u32 da;
-        u32 pa;
-        u32 pgsz, prsvd, valid;
-        union {
-                u16 ap;
-                struct {
-                        u32 endian, elsz, mixed;
-                };
-        };
-};
-struct omap_iommu {
-        const char      *name;
-        struct module   *owner;
-        struct clk      *clk;
-        void __iomem    *regbase;
-        struct device   *dev;
-        void            *isr_priv;
-        struct iommu_domain *domain;
-        unsigned int    refcount;
-        spinlock_t      iommu_lock;     /* global for this whole object */
-        /*
-         * We don't change iopgd for a situation like pgd for a task,
-         * but share it globally for each iommu.
-         */
-        u32             *iopgd;
-        spinlock_t      page_table_lock; /* protect iopgd */
-        int             nr_tlb_entries;
-        struct list_head        mmap;
-        struct mutex            mmap_lock; /* protect mmap */
-        void *ctx; /* iommu context: registres saved area */
-        u32 da_start;
-        u32 da_end;
-};
-struct cr_regs {
-        union {
-                struct {
-                        u16 cam_l;
-                        u16 cam_h;
-                };
-                u32 cam;
-        };
-        union {
-                struct {
-                        u16 ram_l;
-                        u16 ram_h;
-                };
-                u32 ram;
-        };
-};
-struct iotlb_lock {
-        short base;
-        short vict;
-};
-/* architecture specific functions */
-struct iommu_functions {
-        unsigned long   version;
-        int (*enable)(struct omap_iommu *obj);
-        void (*disable)(struct omap_iommu *obj);
-        void (*set_twl)(struct omap_iommu *obj, bool on);
-        u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
-        void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
-        void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
-        struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
-                                                        struct iotlb_entry *e);
-        int (*cr_valid)(struct cr_regs *cr);
-        u32 (*cr_to_virt)(struct cr_regs *cr);
-        void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
-        ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
-                                                        char *buf);
-        u32 (*get_pte_attr)(struct iotlb_entry *e);
-        void (*save_ctx)(struct omap_iommu *obj);
-        void (*restore_ctx)(struct omap_iommu *obj);
-        ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
-};
-/**
- * struct omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod
- * @da_start:           device address where the va space starts.
- * @da_end:             device address where the va space ends.
- * @nr_tlb_entries:     number of entries supported by the translation
- *                      look-aside buffer (TLB).
- */
-struct omap_mmu_dev_attr {
-        u32 da_start;
-        u32 da_end;
-        int nr_tlb_entries;
-};
-struct iommu_platform_data {
-        const char *name;
-        const char *clk_name;
-        const int nr_tlb_entries;
-        u32 da_start;
-        u32 da_end;
-};
-/**
- * struct iommu_arch_data - omap iommu private data
- * @name: name of the iommu device
- * @iommu_dev: handle of the iommu device
- *
- * This is an omap iommu private data object, which binds an iommu user
- * to its iommu device. This object should be placed at the iommu user's
- * dev_archdata so generic IOMMU API can be used without having to
- * utilize omap-specific plumbing anymore.
- */
-struct omap_iommu_arch_data {
-        const char *name;
-        struct omap_iommu *iommu_dev;
-};
-#ifdef CONFIG_IOMMU_API
-/**
- * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
- * @dev: iommu client device
- */
-static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
-{
-        struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
-        return arch_data->iommu_dev;
-}
-#endif
-/* IOMMU errors */
-#define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
-#define OMAP_IOMMU_ERR_TRANS_FAULT      (1 << 1)
-#define OMAP_IOMMU_ERR_EMU_MISS         (1 << 2)
-#define OMAP_IOMMU_ERR_TBLWALK_FAULT    (1 << 3)
-#define OMAP_IOMMU_ERR_MULTIHIT_FAULT   (1 << 4)
-#if defined(CONFIG_ARCH_OMAP1)
-#error "iommu for this processor not implemented yet"
-#else
-#include <plat/iommu2.h>
-#endif
-/*
- * utilities for super page(16MB, 1MB, 64KB and 4KB)
- */
-#define iopgsz_max(bytes)                       \
-        (((bytes) >= SZ_16M) ? SZ_16M :         \
-         ((bytes) >= SZ_1M)  ? SZ_1M  :         \
-         ((bytes) >= SZ_64K) ? SZ_64K :         \
-         ((bytes) >= SZ_4K)  ? SZ_4K  : 0)
-#define bytes_to_iopgsz(bytes)                          \
-        (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :       \
-         ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :       \
-         ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :       \
-         ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
-#define iopgsz_to_bytes(iopgsz)                         \
-        (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M :      \
-         ((iopgsz) == MMU_CAM_PGSZ_1M)  ? SZ_1M  :      \
-         ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K :      \
-         ((iopgsz) == MMU_CAM_PGSZ_4K)  ? SZ_4K  : 0)
-#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
-/*
- * global functions
- */
-extern u32 omap_iommu_arch_version(void);
-extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
-extern int
-omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
-extern int omap_iommu_set_isr(const char *name,
-                 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
-                                    void *priv),
-                         void *isr_priv);
-extern void omap_iommu_save_ctx(struct device *dev);
-extern void omap_iommu_restore_ctx(struct device *dev);
-extern int omap_install_iommu_arch(const struct iommu_functions *ops);
-extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
-extern int omap_foreach_iommu_device(void *data,
-                                int (*fn)(struct device *, void *));
-extern ssize_t
-omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
-extern size_t
-omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
-#endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/plat/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
deleted file mode 100644
index d4116b595e40..000000000000
--- a/arch/arm/plat-omap/include/plat/iommu2.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * omap iommu: omap2 architecture specific definitions
- *
- * Copyright (C) 2008-2009 Nokia Corporation
- *
- * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __MACH_IOMMU2_H
-#define __MACH_IOMMU2_H
-#include <linux/io.h>
-/*
- * MMU Register offsets
- */
-#define MMU_REVISION            0x00
-#define MMU_SYSCONFIG           0x10
-#define MMU_SYSSTATUS           0x14
-#define MMU_IRQSTATUS           0x18
-#define MMU_IRQENABLE           0x1c
-#define MMU_WALKING_ST          0x40
-#define MMU_CNTL                0x44
-#define MMU_FAULT_AD            0x48
-#define MMU_TTB                 0x4c
-#define MMU_LOCK                0x50
-#define MMU_LD_TLB              0x54
-#define MMU_CAM                 0x58
-#define MMU_RAM                 0x5c
-#define MMU_GFLUSH              0x60
-#define MMU_FLUSH_ENTRY         0x64
-#define MMU_READ_CAM            0x68
-#define MMU_READ_RAM            0x6c
-#define MMU_EMU_FAULT_AD        0x70
-#define MMU_REG_SIZE            256
-/*
- * MMU Register bit definitions
- */
-#define MMU_LOCK_BASE_SHIFT     10
-#define MMU_LOCK_BASE_MASK      (0x1f << MMU_LOCK_BASE_SHIFT)
-#define MMU_LOCK_BASE(x)        \
-        ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
-#define MMU_LOCK_VICT_SHIFT     4
-#define MMU_LOCK_VICT_MASK      (0x1f << MMU_LOCK_VICT_SHIFT)
-#define MMU_LOCK_VICT(x)        \
-        ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
-#define MMU_CAM_VATAG_SHIFT     12
-#define MMU_CAM_VATAG_MASK \
-        ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
-#define MMU_CAM_P               (1 << 3)
-#define MMU_CAM_V               (1 << 2)
-#define MMU_CAM_PGSZ_MASK       3
-#define MMU_CAM_PGSZ_1M         (0 << 0)
-#define MMU_CAM_PGSZ_64K        (1 << 0)
-#define MMU_CAM_PGSZ_4K         (2 << 0)
-#define MMU_CAM_PGSZ_16M        (3 << 0)
-#define MMU_RAM_PADDR_SHIFT     12
-#define MMU_RAM_PADDR_MASK \
-        ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
-#define MMU_RAM_ENDIAN_SHIFT    9
-#define MMU_RAM_ENDIAN_MASK     (1 << MMU_RAM_ENDIAN_SHIFT)
-#define MMU_RAM_ENDIAN_BIG      (1 << MMU_RAM_ENDIAN_SHIFT)
-#define MMU_RAM_ENDIAN_LITTLE   (0 << MMU_RAM_ENDIAN_SHIFT)
-#define MMU_RAM_ELSZ_SHIFT      7
-#define MMU_RAM_ELSZ_MASK       (3 << MMU_RAM_ELSZ_SHIFT)
-#define MMU_RAM_ELSZ_8          (0 << MMU_RAM_ELSZ_SHIFT)
-#define MMU_RAM_ELSZ_16         (1 << MMU_RAM_ELSZ_SHIFT)
-#define MMU_RAM_ELSZ_32         (2 << MMU_RAM_ELSZ_SHIFT)
-#define MMU_RAM_ELSZ_NONE       (3 << MMU_RAM_ELSZ_SHIFT)
-#define MMU_RAM_MIXED_SHIFT     6
-#define MMU_RAM_MIXED_MASK      (1 << MMU_RAM_MIXED_SHIFT)
-#define MMU_RAM_MIXED           MMU_RAM_MIXED_MASK
-/*
- * register accessors
- */
-static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
-{
-        return __raw_readl(obj->regbase + offs);
-}
-static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
-{
-        __raw_writel(val, obj->regbase + offs);
-}
-#endif /* __MACH_IOMMU2_H */
diff --git a/arch/arm/plat-omap/include/plat/iopgtable.h b/arch/arm/plat-omap/include/plat/iopgtable.h
deleted file mode 100644
index 66a813977d52..000000000000
--- a/arch/arm/plat-omap/include/plat/iopgtable.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * omap iommu: pagetable definitions
- *
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __PLAT_OMAP_IOMMU_H
-#define __PLAT_OMAP_IOMMU_H
-/*
- * "L2 table" address mask and size definitions.
- */
-#define IOPGD_SHIFT             20
-#define IOPGD_SIZE              (1UL << IOPGD_SHIFT)
-#define IOPGD_MASK              (~(IOPGD_SIZE - 1))
-/*
- * "section" address mask and size definitions.
- */
-#define IOSECTION_SHIFT         20
-#define IOSECTION_SIZE          (1UL << IOSECTION_SHIFT)
-#define IOSECTION_MASK          (~(IOSECTION_SIZE - 1))
-/*
- * "supersection" address mask and size definitions.
- */
-#define IOSUPER_SHIFT           24
-#define IOSUPER_SIZE            (1UL << IOSUPER_SHIFT)
-#define IOSUPER_MASK            (~(IOSUPER_SIZE - 1))
-#define PTRS_PER_IOPGD          (1UL << (32 - IOPGD_SHIFT))
-#define IOPGD_TABLE_SIZE        (PTRS_PER_IOPGD * sizeof(u32))
-/*
- * "small page" address mask and size definitions.
- */
-#define IOPTE_SHIFT             12
-#define IOPTE_SIZE              (1UL << IOPTE_SHIFT)
-#define IOPTE_MASK              (~(IOPTE_SIZE - 1))
-/*
- * "large page" address mask and size definitions.
- */
-#define IOLARGE_SHIFT           16
-#define IOLARGE_SIZE            (1UL << IOLARGE_SHIFT)
-#define IOLARGE_MASK            (~(IOLARGE_SIZE - 1))
-#define PTRS_PER_IOPTE          (1UL << (IOPGD_SHIFT - IOPTE_SHIFT))
-#define IOPTE_TABLE_SIZE        (PTRS_PER_IOPTE * sizeof(u32))
-#define IOPAGE_MASK             IOPTE_MASK
-/**
- * omap_iommu_translate() - va to pa translation
- * @d:          omap iommu descriptor
- * @va:         virtual address
- * @mask:       omap iommu descriptor mask
- *
- * va to pa translation
- */
-static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask)
-{
-        return (d & mask) | (va & (~mask));
-}
-/*
- * some descriptor attributes.
- */
-#define IOPGD_TABLE             (1 << 0)
-#define IOPGD_SECTION           (2 << 0)
-#define IOPGD_SUPER             (1 << 18 | 2 << 0)
-#define iopgd_is_table(x)       (((x) & 3) == IOPGD_TABLE)
-#define iopgd_is_section(x)     (((x) & (1 << 18 | 3)) == IOPGD_SECTION)
-#define iopgd_is_super(x)       (((x) & (1 << 18 | 3)) == IOPGD_SUPER)
-#define IOPTE_SMALL             (2 << 0)
-#define IOPTE_LARGE             (1 << 0)
-#define iopte_is_small(x)       (((x) & 2) == IOPTE_SMALL)
-#define iopte_is_large(x)       (((x) & 3) == IOPTE_LARGE)
-/* to find an entry in a page-table-directory */
-#define iopgd_index(da)         (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
-#define iopgd_offset(obj, da)   ((obj)->iopgd + iopgd_index(da))
-#define iopgd_page_paddr(iopgd) (*iopgd & ~((1 << 10) - 1))
-#define iopgd_page_vaddr(iopgd) ((u32 *)phys_to_virt(iopgd_page_paddr(iopgd)))
-/* to find an entry in the second-level page table. */
-#define iopte_index(da)         (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
-#define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da))
-static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
-                                   u32 flags)
-{
-        memset(e, 0, sizeof(*e));
-        e->da           = da;
-        e->pa           = pa;
-        e->valid        = 1;
-        /* FIXME: add OMAP1 support */
-        e->pgsz         = flags & MMU_CAM_PGSZ_MASK;
-        e->endian       = flags & MMU_RAM_ENDIAN_MASK;
-        e->elsz         = flags & MMU_RAM_ELSZ_MASK;
-        e->mixed        = flags & MMU_RAM_MIXED_MASK;
-        return iopgsz_to_bytes(e->pgsz);
-}
-#define to_iommu(dev)                                                   \
-        (struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))
-#endif /* __PLAT_OMAP_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
deleted file mode 100644
index 498e57cda6cd..000000000000
--- a/arch/arm/plat-omap/include/plat/iovmm.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * omap iommu: simple virtual address space management
- *
- * Copyright (C) 2008-2009 Nokia Corporation
- *
- * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __IOMMU_MMAP_H
-#define __IOMMU_MMAP_H
-#include <linux/iommu.h>
-struct iovm_struct {
-        struct omap_iommu       *iommu; /* iommu object which this belongs to */
-        u32                     da_start; /* area definition */
-        u32                     da_end;
-        u32                     flags; /* IOVMF_: see below */
-        struct list_head        list; /* linked in ascending order */
-        const struct sg_table   *sgt; /* keep 'page' <-> 'da' mapping */
-        void                    *va; /* mpu side mapped address */
-};
-/*
- * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
- *
- * lower 16 bit is used for h/w and upper 16 bit is for s/w.
- */
-#define IOVMF_SW_SHIFT          16
-/*
- * iovma: h/w flags derived from cam and ram attribute
- */
-#define IOVMF_CAM_MASK          (~((1 << 10) - 1))
-#define IOVMF_RAM_MASK          (~IOVMF_CAM_MASK)
-#define IOVMF_PGSZ_MASK         (3 << 0)
-#define IOVMF_PGSZ_1M           MMU_CAM_PGSZ_1M
-#define IOVMF_PGSZ_64K          MMU_CAM_PGSZ_64K
-#define IOVMF_PGSZ_4K           MMU_CAM_PGSZ_4K
-#define IOVMF_PGSZ_16M          MMU_CAM_PGSZ_16M
-#define IOVMF_ENDIAN_MASK       (1 << 9)
-#define IOVMF_ENDIAN_BIG        MMU_RAM_ENDIAN_BIG
-#define IOVMF_ENDIAN_LITTLE     MMU_RAM_ENDIAN_LITTLE
-#define IOVMF_ELSZ_MASK         (3 << 7)
-#define IOVMF_ELSZ_8            MMU_RAM_ELSZ_8
-#define IOVMF_ELSZ_16           MMU_RAM_ELSZ_16
-#define IOVMF_ELSZ_32           MMU_RAM_ELSZ_32
-#define IOVMF_ELSZ_NONE         MMU_RAM_ELSZ_NONE
-#define IOVMF_MIXED_MASK        (1 << 6)
-#define IOVMF_MIXED             MMU_RAM_MIXED
-/*
- * iovma: s/w flags, used for mapping and umapping internally.
- */
-#define IOVMF_MMIO              (1 << IOVMF_SW_SHIFT)
-#define IOVMF_ALLOC             (2 << IOVMF_SW_SHIFT)
-#define IOVMF_ALLOC_MASK        (3 << IOVMF_SW_SHIFT)
-/* "superpages" is supported just with physically linear pages */
-#define IOVMF_DISCONT           (1 << (2 + IOVMF_SW_SHIFT))
-#define IOVMF_LINEAR            (2 << (2 + IOVMF_SW_SHIFT))
-#define IOVMF_LINEAR_MASK       (3 << (2 + IOVMF_SW_SHIFT))
-#define IOVMF_DA_FIXED          (1 << (4 + IOVMF_SW_SHIFT))
-extern struct iovm_struct *omap_find_iovm_area(struct device *dev, u32 da);
-extern u32
-omap_iommu_vmap(struct iommu_domain *domain, struct device *dev, u32 da,
-                        const struct sg_table *sgt, u32 flags);
-extern struct sg_table *omap_iommu_vunmap(struct iommu_domain *domain,
-                                struct device *dev, u32 da);
-extern u32
-omap_iommu_vmalloc(struct iommu_domain *domain, struct device *dev,
-                                u32 da, size_t bytes, u32 flags);
-extern void
-omap_iommu_vfree(struct iommu_domain *domain, struct device *dev,
-                                const u32 da);
-extern void *omap_da_to_va(struct device *dev, u32 da);
-#endif /* __IOMMU_MMAP_H */
diff --git a/arch/arm/plat-omap/include/plat/led.h b/arch/arm/plat-omap/include/plat/led.h
deleted file mode 100644
index 25e451e7e2fd..000000000000
--- a/arch/arm/plat-omap/include/plat/led.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/led.h
- *
- *  Copyright (C) 2006 Samsung Electronics
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_LED_H
-#define ASMARM_ARCH_LED_H
-struct omap_led_config {
-        struct led_classdev     cdev;
-        s16                     gpio;
-};
-struct omap_led_platform_data {
-        s16                     nr_leds;
-        struct omap_led_config  *leds;
-};
-#endif
diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
deleted file mode 100644
index 4a970ec62dd1..000000000000
--- a/arch/arm/plat-omap/include/plat/menelaus.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/menelaus.h
- *
- * Functions to access Menelaus power management chip
- */
-#ifndef __ASM_ARCH_MENELAUS_H
-#define __ASM_ARCH_MENELAUS_H
-struct device;
-struct menelaus_platform_data {
-        int (* late_init)(struct device *dev);
-};
-extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
-                                          void *data);
-extern void menelaus_unregister_mmc_callback(void);
-extern int menelaus_set_mmc_opendrain(int slot, int enable);
-extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
-extern int menelaus_set_vmem(unsigned int mV);
-extern int menelaus_set_vio(unsigned int mV);
-extern int menelaus_set_vmmc(unsigned int mV);
-extern int menelaus_set_vaux(unsigned int mV);
-extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
-extern int menelaus_set_slot_sel(int enable);
-extern int menelaus_get_slot_pin_states(void);
-extern int menelaus_set_vcore_sw(unsigned int mV);
-extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
-#define EN_VPLL_SLEEP   (1 << 7)
-#define EN_VMMC_SLEEP   (1 << 6)
-#define EN_VAUX_SLEEP   (1 << 5)
-#define EN_VIO_SLEEP    (1 << 4)
-#define EN_VMEM_SLEEP   (1 << 3)
-#define EN_DC3_SLEEP    (1 << 2)
-#define EN_DC2_SLEEP    (1 << 1)
-#define EN_VC_SLEEP     (1 << 0)
-extern int menelaus_set_regulator_sleep(int enable, u32 val);
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
-#define omap_has_menelaus()     1
-#else
-#define omap_has_menelaus()     0
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
deleted file mode 100644
index 8b4e4f2da2f5..000000000000
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * MMC definitions for OMAP2
- *
- * Copyright (C) 2006 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __OMAP2_MMC_H
-#define __OMAP2_MMC_H
-#include <linux/types.h>
-#include <linux/device.h>
-#include <linux/mmc/host.h>
-#include <plat/omap_hwmod.h>
-#define OMAP15XX_NR_MMC         1
-#define OMAP16XX_NR_MMC         2
-#define OMAP1_MMC_SIZE          0x080
-#define OMAP1_MMC1_BASE         0xfffb7800
-#define OMAP1_MMC2_BASE         0xfffb7c00      /* omap16xx only */
-#define OMAP24XX_NR_MMC         2
-#define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
-#define OMAP2_MMC1_BASE         0x4809c000
-#define OMAP4_MMC_REG_OFFSET    0x100
-#define OMAP_MMC_MAX_SLOTS      2
-/*
- * struct omap_mmc_dev_attr.flags possibilities
- *
- * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
- *    operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
- *    should be set if this is the case.  See for example Section 22.5.3
- *    "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
- *    Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
- *
- * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
- *    don't work correctly on some MMC controller instances on some
- *    OMAP3 SoCs; this flag should be set if this is the case.  See
- *    for example Advisory 2.1.1.128 "MMC: Multiple Block Read
- *    Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
- *    Revision F (October 2010) (SPRZ278F).
- */
-#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
-#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ       BIT(1)
-struct omap_mmc_dev_attr {
-        u8 flags;
-};
-struct omap_mmc_platform_data {
-        /* back-link to device */
-        struct device *dev;
-        /* number of slots per controller */
-        unsigned nr_slots:2;
-        /* set if your board has components or wiring that limits the
-         * maximum frequency on the MMC bus */
-        unsigned int max_freq;
-        /* switch the bus to a new slot */
-        int (*switch_slot)(struct device *dev, int slot);
-        /* initialize board-specific MMC functionality, can be NULL if
-         * not supported */
-        int (*init)(struct device *dev);
-        void (*cleanup)(struct device *dev);
-        void (*shutdown)(struct device *dev);
-        /* To handle board related suspend/resume functionality for MMC */
-        int (*suspend)(struct device *dev, int slot);
-        int (*resume)(struct device *dev, int slot);
-        /* Return context loss count due to PM states changing */
-        int (*get_context_loss_count)(struct device *dev);
-        /* Integrating attributes from the omap_hwmod layer */
-        u8 controller_flags;
-        /* Register offset deviation */
-        u16 reg_offset;
-        struct omap_mmc_slot_data {
-                /*
-                 * 4/8 wires and any additional host capabilities
-                 * need to OR'd all capabilities (ref. linux/mmc/host.h)
-                 */
-                u8  wires;      /* Used for the MMC driver on omap1 and 2420 */
-                u32 caps;       /* Used for the MMC driver on 2430 and later */
-                u32 pm_caps;    /* PM capabilities of the mmc */
-                /*
-                 * nomux means "standard" muxing is wrong on this board, and
-                 * that board-specific code handled it before common init logic.
-                 */
-                unsigned nomux:1;
-                /* switch pin can be for card detect (default) or card cover */
-                unsigned cover:1;
-                /* use the internal clock */
-                unsigned internal_clock:1;
-                /* nonremovable e.g. eMMC */
-                unsigned nonremovable:1;
-                /* Try to sleep or power off when possible */
-                unsigned power_saving:1;
-                /* If using power_saving and the MMC power is not to go off */
-                unsigned no_off:1;
-                /* eMMC does not handle power off when not in sleep state */
-                unsigned no_regulator_off_init:1;
-                /* Regulator off remapped to sleep */
-                unsigned vcc_aux_disable_is_sleep:1;
-                /* we can put the features above into this variable */
-#define HSMMC_HAS_PBIAS         (1 << 0)
-#define HSMMC_HAS_UPDATED_RESET (1 << 1)
-                unsigned features;
-                int switch_pin;                 /* gpio (card detect) */
-                int gpio_wp;                    /* gpio (write protect) */
-                int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
-                int (*set_power)(struct device *dev, int slot,
-                                 int power_on, int vdd);
-                int (*get_ro)(struct device *dev, int slot);
-                void (*remux)(struct device *dev, int slot, int power_on);
-                /* Call back before enabling / disabling regulators */
-                void (*before_set_reg)(struct device *dev, int slot,
-                                       int power_on, int vdd);
-                /* Call back after enabling / disabling regulators */
-                void (*after_set_reg)(struct device *dev, int slot,
-                                      int power_on, int vdd);
-                /* if we have special card, init it using this callback */
-                void (*init_card)(struct mmc_card *card);
-                /* return MMC cover switch state, can be NULL if not supported.
-                 *
-                 * possible return values:
-                 *   0 - closed
-                 *   1 - open
-                 */
-                int (*get_cover_state)(struct device *dev, int slot);
-                const char *name;
-                u32 ocr_mask;
-                /* Card detection IRQs */
-                int card_detect_irq;
-                int (*card_detect)(struct device *dev, int slot);
-                unsigned int ban_openended:1;
-        } slots[OMAP_MMC_MAX_SLOTS];
-};
-/* called from board-specific card detection service routine */
-extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
-                                        int is_closed);
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
-void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers);
-void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
-#else
-static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers)
-{
-}
-static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
-{
-}
-#endif
-extern int omap_msdi_reset(struct omap_hwmod *oh);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
deleted file mode 100644
index 324d31b14852..000000000000
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Support for compiling in multiple OMAP processors
- *
- * Copyright (C) 2010 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef __PLAT_OMAP_MULTI_H
-#define __PLAT_OMAP_MULTI_H
-/*
- * Test if multicore OMAP support is needed
- */
-#undef MULTI_OMAP1
-#undef MULTI_OMAP2
-#undef OMAP_NAME
-#ifdef CONFIG_ARCH_OMAP730
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap730
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP850
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap850
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap1510
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap16xx
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
-#  error "OMAP1 and OMAP2PLUS can't be selected at the same time"
-# endif
-#endif
-#ifdef CONFIG_SOC_OMAP2420
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2420
-# endif
-#endif
-#ifdef CONFIG_SOC_OMAP2430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2430
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap3
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap4
-# endif
-#endif
-#ifdef CONFIG_SOC_OMAP5
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap5
-# endif
-#endif
-#ifdef CONFIG_SOC_AM33XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME am33xx
-# endif
-#endif
-#endif  /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
deleted file mode 100644
index 0e4acd2d2deb..000000000000
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __OMAP_SECURE_H__
-#define __OMAP_SECURE_H__
-#include <linux/types.h>
-extern int omap_secure_ram_reserve_memblock(void);
-#ifdef CONFIG_OMAP4_ERRATA_I688
-extern int omap_barrier_reserve_memblock(void);
-#else
-static inline void omap_barrier_reserve_memblock(void)
-{ }
-#endif
-#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1957a8516e93..ff9b0aab5281 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -30,35 +30,6 @@
 */
 #define OMAP_SERIAL_NAME        "ttyO"
-#define OMAP_MODE13X_SPEED      230400
-#define OMAP_UART_SCR_TX_EMPTY  0x08
-/* WER = 0x7F
- * Enable module level wakeup in WER reg
- */
-#define OMAP_UART_WER_MOD_WKUP  0X7F
-/* Enable XON/XOFF flow control on output */
-#define OMAP_UART_SW_TX         0x04
-/* Enable XON/XOFF flow control on input */
-#define OMAP_UART_SW_RX         0x04
-#define OMAP_UART_SYSC_RESET    0X07
-#define OMAP_UART_TCR_TRIG      0X0F
-#define OMAP_UART_SW_CLR        0XF0
-#define OMAP_UART_FIFO_CLR      0X06
-#define OMAP_UART_DMA_CH_FREE   -1
-#define OMAP_MAX_HSUART_PORTS   6
-#define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
-#define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
-#define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
 struct omap_uart_port_info {
        bool                    dma_enabled;    /* To specify DMA Mode */
        unsigned int            uartclk;        /* UART clock rate */
@@ -77,30 +48,4 @@ struct omap_uart_port_info {
        void (*enable_wakeup)(struct device *, bool);
 };
-struct uart_omap_dma {
-        u8                      uart_dma_tx;
-        u8                      uart_dma_rx;
-        int                     rx_dma_channel;
-        int                     tx_dma_channel;
-        dma_addr_t              rx_buf_dma_phys;
-        dma_addr_t              tx_buf_dma_phys;
-        unsigned int            uart_base;
-        /*
-         * Buffer for rx dma.It is not required for tx because the buffer
-         * comes from port structure.
-         */
-        unsigned char           *rx_buf;
-        unsigned int            prev_rx_dma_pos;
-        int                     tx_buf_size;
-        int                     tx_dma_used;
-        int                     rx_dma_used;
-        spinlock_t              tx_lock;
-        spinlock_t              rx_lock;
-        /* timer to poll activity on rx dma */
-        struct timer_list       rx_timer;
-        unsigned int            rx_buf_size;
-        unsigned int            rx_poll_rate;
-        unsigned int            rx_timeout;
-};
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
deleted file mode 100644
index 267f43bb2a4e..000000000000
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/prcm.h
- *
- * Access definations for use in OMAP24XX clock and power management
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * XXX This file is deprecated.  The PRCM is an OMAP2+-only subsystem,
- * so this file doesn't belong in plat-omap/include/plat.  Please
- * do not add anything new to this file.
- */
-#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
-#define __ASM_ARM_ARCH_OMAP_PRCM_H
-u32 omap_prcm_get_reset_sources(void);
-int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
-                         const char *name);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
deleted file mode 100644
index 36d6a7666216..000000000000
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ /dev/null
@@ -1,164 +0,0 @@
-#ifndef ____ASM_ARCH_SDRC_H
-#define ____ASM_ARCH_SDRC_H
-/*
- * OMAP2/3 SDRC/SMS register definitions
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Tony Lindgren
- * Paul Walmsley
- * Richard Woodruff
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
-#define SDRC_SYSCONFIG          0x010
-#define SDRC_CS_CFG             0x040
-#define SDRC_SHARING            0x044
-#define SDRC_ERR_TYPE           0x04C
-#define SDRC_DLLA_CTRL          0x060
-#define SDRC_DLLA_STATUS        0x064
-#define SDRC_DLLB_CTRL          0x068
-#define SDRC_DLLB_STATUS        0x06C
-#define SDRC_POWER              0x070
-#define SDRC_MCFG_0             0x080
-#define SDRC_MR_0               0x084
-#define SDRC_EMR2_0             0x08c
-#define SDRC_ACTIM_CTRL_A_0     0x09c
-#define SDRC_ACTIM_CTRL_B_0     0x0a0
-#define SDRC_RFR_CTRL_0         0x0a4
-#define SDRC_MANUAL_0           0x0a8
-#define SDRC_MCFG_1             0x0B0
-#define SDRC_MR_1               0x0B4
-#define SDRC_EMR2_1             0x0BC
-#define SDRC_ACTIM_CTRL_A_1     0x0C4
-#define SDRC_ACTIM_CTRL_B_1     0x0C8
-#define SDRC_RFR_CTRL_1         0x0D4
-#define SDRC_MANUAL_1           0x0D8
-#define SDRC_POWER_AUTOCOUNT_SHIFT      8
-#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
-#define SDRC_POWER_CLKCTRL_SHIFT        4
-#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
-#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
-/*
- * These values represent the number of memory clock cycles between
- * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
- * rows per device, and include a subtraction of a 50 cycle window in the
- * event that the autorefresh command is delayed due to other SDRC activity.
- * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
- * counter reaches 0.
- *
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
-#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
-#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
-#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
-#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
-/*
- * SMS register access
- */
-#define OMAP242X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
-/* SMS register offsets - read/write with sms_{read,write}_reg() */
-#define SMS_SYSCONFIG                   0x010
-#define SMS_ROT_CONTROL(context)        (0x180 + 0x10 * context)
-#define SMS_ROT_SIZE(context)           (0x184 + 0x10 * context)
-#define SMS_ROT_PHYSICAL_BA(context)    (0x188 + 0x10 * context)
-/* REVISIT: fill in other SMS registers here */
-#ifndef __ASSEMBLER__
-/**
- * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
- * @rate: SDRC clock rate (in Hz)
- * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
- * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
- * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
- * @mr: Value to program to SDRC_MR for this rate
- *
- * This structure holds a pre-computed set of register values for the
- * SDRC for a given SDRC clock rate and SDRAM chip.  These are
- * intended to be pre-computed and specified in an array in the board-*.c
- * files.  The structure is keyed off the 'rate' field.
- */
-struct omap_sdrc_params {
-        unsigned long rate;
-        u32 actim_ctrla;
-        u32 actim_ctrlb;
-        u32 rfr_ctrl;
-        u32 mr;
-};
-#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
-void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                            struct omap_sdrc_params *sdrc_cs1);
-#else
-static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                                          struct omap_sdrc_params *sdrc_cs1) {};
-#endif
-int omap2_sdrc_get_params(unsigned long r,
-                          struct omap_sdrc_params **sdrc_cs0,
-                          struct omap_sdrc_params **sdrc_cs1);
-void omap2_sms_save_context(void);
-void omap2_sms_restore_context(void);
-void omap2_sms_write_rot_control(u32 val, unsigned ctx);
-void omap2_sms_write_rot_size(u32 val, unsigned ctx);
-void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
-#ifdef CONFIG_ARCH_OMAP2
-struct memory_timings {
-        u32 m_type;             /* ddr = 1, sdr = 0 */
-        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
-        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
-        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
-        u32 base_cs;            /* base chip select to use for calculations */
-};
-extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
-struct omap_sdrc_params *rx51_get_sdram_timings(void);
-u32 omap2xxx_sdrc_dll_is_unlocked(void);
-u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
-#endif  /* CONFIG_ARCH_OMAP2 */
-#endif  /* __ASSEMBLER__ */
-#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 227ae2657554..ba4525059a99 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -1,18 +1,8 @@
-/*
+int omap_sram_init(void);
- * arch/arm/plat-omap/include/mach/sram.h
- *
- * Interface for functions that need to be run in internal SRAM
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ARM_OMAP_SRAM_H
+void omap_map_sram(unsigned long start, unsigned long size,
-#define __ARCH_ARM_OMAP_SRAM_H
+                        unsigned long skip, int cached);
+void omap_sram_reset(void);
-#ifndef __ASSEMBLY__
-#include <asm/fncpy.h>
 extern void *omap_sram_push_address(unsigned long size);
@@ -24,82 +14,3 @@ extern void *omap_sram_push_address(unsigned long size);
                _res = fncpy(_sram_address, &(funcp), size);    \
        _res;                                                   \
 })
-extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
-extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                u32 base_cs, u32 force_unlock);
-extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                      u32 mem_type);
-extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-extern u32 omap3_configure_core_dpll(
-                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
-extern void omap3_sram_restore_context(void);
-/* Do not use these */
-extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long omap1_sram_reprogram_clock_sz;
-extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long omap24xx_sram_reprogram_clock_sz;
-extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                                u32 base_cs, u32 force_unlock);
-extern unsigned long omap242x_sram_ddr_init_sz;
-extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
-                                                int bypass);
-extern unsigned long omap242x_sram_set_prcm_sz;
-extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                                u32 mem_type);
-extern unsigned long omap242x_sram_reprogram_sdrc_sz;
-extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                                u32 base_cs, u32 force_unlock);
-extern unsigned long omap243x_sram_ddr_init_sz;
-extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
-                                                int bypass);
-extern unsigned long omap243x_sram_set_prcm_sz;
-extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                                u32 mem_type);
-extern unsigned long omap243x_sram_reprogram_sdrc_sz;
-extern u32 omap3_sram_configure_core_dpll(
-                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
-extern unsigned long omap3_sram_configure_core_dpll_sz;
-#ifdef CONFIG_PM
-extern void omap_push_sram_idle(void);
-#else
-static inline void omap_push_sram_idle(void) {}
-#endif /* CONFIG_PM */
-#endif /* __ASSEMBLY__ */
-/*
- * OMAP2+: define the SRAM PA addresses.
- * Used by the SRAM management code and the idle sleep code.
- */
-#define OMAP2_SRAM_PA           0x40200000
-#define OMAP3_SRAM_PA           0x40200000
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PA           0x40304000
-#define OMAP4_SRAM_VA           0xfe404000
-#else
-#define OMAP4_SRAM_PA           0x40300000
-#endif
-#define AM33XX_SRAM_PA          0x40300000
-#endif
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
deleted file mode 100644
index 7f7b112acccb..000000000000
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <plat/serial.h>
-#define MDR1_MODE_MASK                  0x07
-volatile u8 *uart_base;
-int uart_shift;
-/*
- * Store the DEBUG_LL uart number into memory.
- * See also debug-macro.S, and serial.c for related code.
- */
-static void set_omap_uart_info(unsigned char port)
-{
-        /*
-         * Get address of some.bss variable and round it down
-         * a la CONFIG_AUTO_ZRELADDR.
-         */
-        u32 ram_start = (u32)&uart_shift & 0xf8000000;
-        u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
-        *uart_info = port;
-}
-static void putc(int c)
-{
-        if (!uart_base)
-                return;
-        /* Check for UART 16x mode */
-        if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
-                return;
-        while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
-                barrier();
-        uart_base[UART_TX << uart_shift] = c;
-}
-static inline void flush(void)
-{
-}
-/*
- * Macros to configure UART1 and debug UART
- */
-#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id)               \
-        if (machine_is_##mach()) {                                      \
-                uart_base = (volatile u8 *)(dbg_uart);                  \
-                uart_shift = (dbg_shft);                                \
-                port = (dbg_id);                                        \
-                set_omap_uart_info(port);                               \
-                break;                                                  \
-        }
-#define DEBUG_LL_OMAP7XX(p, mach)                                       \
-        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
-                OMAP1UART##p)
-#define DEBUG_LL_OMAP1(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP1UART##p)
-#define DEBUG_LL_OMAP2(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP2UART##p)
-#define DEBUG_LL_OMAP3(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP3UART##p)
-#define DEBUG_LL_OMAP4(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP4UART##p)
-#define DEBUG_LL_OMAP5(p, mach)                                         \
-        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
-                OMAP5UART##p)
-/* Zoom2/3 shift is different for UART1 and external port */
-#define DEBUG_LL_ZOOM(mach)                                             \
-        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-#define DEBUG_LL_TI81XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                TI81XXUART##p)
-#define DEBUG_LL_AM33XX(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                AM33XXUART##p)
-static inline void arch_decomp_setup(void)
-{
-        int port = 0;
-        /*
-         * Initialize the port based on the machine ID from the bootloader.
-         * Note that we're using macros here instead of switch statement
-         * as machine_is functions are optimized out for the boards that
-         * are not selected.
-         */
-        do {
-                /* omap7xx/8xx based boards using UART1 with shift 0 */
-                DEBUG_LL_OMAP7XX(1, herald);
-                DEBUG_LL_OMAP7XX(1, omap_perseus2);
-                /* omap15xx/16xx based boards using UART1 */
-                DEBUG_LL_OMAP1(1, ams_delta);
-                DEBUG_LL_OMAP1(1, nokia770);
-                DEBUG_LL_OMAP1(1, omap_h2);
-                DEBUG_LL_OMAP1(1, omap_h3);
-                DEBUG_LL_OMAP1(1, omap_innovator);
-                DEBUG_LL_OMAP1(1, omap_osk);
-                DEBUG_LL_OMAP1(1, omap_palmte);
-                DEBUG_LL_OMAP1(1, omap_palmz71);
-                /* omap15xx/16xx based boards using UART2 */
-                DEBUG_LL_OMAP1(2, omap_palmtt);
-                /* omap15xx/16xx based boards using UART3 */
-                DEBUG_LL_OMAP1(3, sx1);
-                /* omap2 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap_2430sdp);
-                DEBUG_LL_OMAP2(1, omap_apollon);
-                DEBUG_LL_OMAP2(1, omap_h4);
-                /* omap2 based boards using UART3 */
-                DEBUG_LL_OMAP2(3, nokia_n800);
-                DEBUG_LL_OMAP2(3, nokia_n810);
-                DEBUG_LL_OMAP2(3, nokia_n810_wimax);
-                /* omap3 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap3evm);
-                DEBUG_LL_OMAP3(1, omap_3430sdp);
-                DEBUG_LL_OMAP3(1, omap_3630sdp);
-                DEBUG_LL_OMAP3(1, omap3530_lv_som);
-                DEBUG_LL_OMAP3(1, omap3_torpedo);
-                /* omap3 based boards using UART3 */
-                DEBUG_LL_OMAP3(3, cm_t35);
-                DEBUG_LL_OMAP3(3, cm_t3517);
-                DEBUG_LL_OMAP3(3, cm_t3730);
-                DEBUG_LL_OMAP3(3, craneboard);
-                DEBUG_LL_OMAP3(3, devkit8000);
-                DEBUG_LL_OMAP3(3, igep0020);
-                DEBUG_LL_OMAP3(3, igep0030);
-                DEBUG_LL_OMAP3(3, nokia_rm680);
-                DEBUG_LL_OMAP3(3, nokia_rm696);
-                DEBUG_LL_OMAP3(3, nokia_rx51);
-                DEBUG_LL_OMAP3(3, omap3517evm);
-                DEBUG_LL_OMAP3(3, omap3_beagle);
-                DEBUG_LL_OMAP3(3, omap3_pandora);
-                DEBUG_LL_OMAP3(3, omap_ldp);
-                DEBUG_LL_OMAP3(3, overo);
-                DEBUG_LL_OMAP3(3, touchbook);
-                /* omap4 based boards using UART3 */
-                DEBUG_LL_OMAP4(3, omap_4430sdp);
-                DEBUG_LL_OMAP4(3, omap4_panda);
-                /* omap5 based boards using UART3 */
-                DEBUG_LL_OMAP5(3, omap5_sevm);
-                /* zoom2/3 external uart */
-                DEBUG_LL_ZOOM(omap_zoom2);
-                DEBUG_LL_ZOOM(omap_zoom3);
-                /* TI8168 base boards using UART3 */
-                DEBUG_LL_TI81XX(3, ti8168evm);
-                /* TI8148 base boards using UART1 */
-                DEBUG_LL_TI81XX(1, ti8148evm);
-                /* AM33XX base boards using UART1 */
-                DEBUG_LL_AM33XX(1, am335xevm);
-        } while (0);
-}
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
deleted file mode 100644
index 87ee140fefaa..000000000000
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ /dev/null
@@ -1,179 +0,0 @@
-// include/asm-arm/mach-omap/usb.h
-#ifndef __ASM_ARCH_OMAP_USB_H
-#define __ASM_ARCH_OMAP_USB_H
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/usb/musb.h>
-#define OMAP3_HS_USB_PORTS      3
-enum usbhs_omap_port_mode {
-        OMAP_USBHS_PORT_MODE_UNUSED,
-        OMAP_EHCI_PORT_MODE_PHY,
-        OMAP_EHCI_PORT_MODE_TLL,
-        OMAP_EHCI_PORT_MODE_HSIC,
-        OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
-        OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
-};
-struct usbhs_omap_board_data {
-        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-        /* have to be valid if phy_reset is true and portx is in phy mode */
-        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
-        /* Set this to true for ES2.x silicon */
-        unsigned                        es2_compatibility:1;
-        unsigned                        phy_reset:1;
-        /*
-         * Regulators for USB PHYs.
-         * Each PHY can have a separate regulator.
-         */
-        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
-};
-#ifdef CONFIG_ARCH_OMAP2PLUS
-struct ehci_hcd_omap_platform_data {
-        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-        int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
-        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
-        unsigned                        phy_reset:1;
-};
-struct ohci_hcd_omap_platform_data {
-        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-        unsigned                        es2_compatibility:1;
-};
-struct usbhs_omap_platform_data {
-        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
-        struct ehci_hcd_omap_platform_data      *ehci_data;
-        struct ohci_hcd_omap_platform_data      *ohci_data;
-};
-struct usbtll_omap_platform_data {
-        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
-};
-/*-------------------------------------------------------------------------*/
-struct omap_musb_board_data {
-        u8      interface_type;
-        u8      mode;
-        u16     power;
-        unsigned extvbus:1;
-        void    (*set_phy_power)(u8 on);
-        void    (*clear_irq)(void);
-        void    (*set_mode)(u8 mode);
-        void    (*reset)(void);
-};
-enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
-extern void usb_musb_init(struct omap_musb_board_data *board_data);
-extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
-extern int omap_tll_enable(void);
-extern int omap_tll_disable(void);
-extern int omap4430_phy_power(struct device *dev, int ID, int on);
-extern int omap4430_phy_set_clk(struct device *dev, int on);
-extern int omap4430_phy_init(struct device *dev);
-extern int omap4430_phy_exit(struct device *dev);
-extern int omap4430_phy_suspend(struct device *dev, int suspend);
-#endif
-extern void am35x_musb_reset(void);
-extern void am35x_musb_phy_power(u8 on);
-extern void am35x_musb_clear_irq(void);
-extern void am35x_set_mode(u8 musb_mode);
-extern void ti81xx_musb_phy_power(u8 on);
-/* AM35x */
-/* USB 2.0 PHY Control */
-#define CONF2_PHY_GPIOMODE      (1 << 23)
-#define CONF2_OTGMODE           (3 << 14)
-#define CONF2_NO_OVERRIDE       (0 << 14)
-#define CONF2_FORCE_HOST        (1 << 14)
-#define CONF2_FORCE_DEVICE      (2 << 14)
-#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
-#define CONF2_SESENDEN          (1 << 13)
-#define CONF2_VBDTCTEN          (1 << 12)
-#define CONF2_REFFREQ_24MHZ     (2 << 8)
-#define CONF2_REFFREQ_26MHZ     (7 << 8)
-#define CONF2_REFFREQ_13MHZ     (6 << 8)
-#define CONF2_REFFREQ           (0xf << 8)
-#define CONF2_PHYCLKGD          (1 << 7)
-#define CONF2_VBUSSENSE         (1 << 6)
-#define CONF2_PHY_PLLON         (1 << 5)
-#define CONF2_RESET             (1 << 4)
-#define CONF2_PHYPWRDN          (1 << 3)
-#define CONF2_OTGPWRDN          (1 << 2)
-#define CONF2_DATPOL            (1 << 1)
-/* TI81XX specific definitions */
-#define USBCTRL0        0x620
-#define USBSTAT0        0x624
-/* TI816X PHY controls bits */
-#define TI816X_USBPHY0_NORMAL_MODE      (1 << 0)
-#define TI816X_USBPHY_REFCLK_OSC        (1 << 8)
-/* TI814X PHY controls bits */
-#define USBPHY_CM_PWRDN         (1 << 0)
-#define USBPHY_OTG_PWRDN        (1 << 1)
-#define USBPHY_CHGDET_DIS       (1 << 2)
-#define USBPHY_CHGDET_RSTRT     (1 << 3)
-#define USBPHY_SRCONDM          (1 << 4)
-#define USBPHY_SINKONDP         (1 << 5)
-#define USBPHY_CHGISINK_EN      (1 << 6)
-#define USBPHY_CHGVSRC_EN       (1 << 7)
-#define USBPHY_DMPULLUP         (1 << 8)
-#define USBPHY_DPPULLUP         (1 << 9)
-#define USBPHY_CDET_EXTCTL      (1 << 10)
-#define USBPHY_GPIO_MODE        (1 << 12)
-#define USBPHY_DPOPBUFCTL       (1 << 13)
-#define USBPHY_DMOPBUFCTL       (1 << 14)
-#define USBPHY_DPINPUT          (1 << 15)
-#define USBPHY_DMINPUT          (1 << 16)
-#define USBPHY_DPGPIO_PD        (1 << 17)
-#define USBPHY_DMGPIO_PD        (1 << 18)
-#define USBPHY_OTGVDET_EN       (1 << 19)
-#define USBPHY_OTGSESSEND_EN    (1 << 20)
-#define USBPHY_DATA_POLARITY    (1 << 23)
-#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
-u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
-u32 omap1_usb1_init(unsigned nwires);
-u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
-#else
-static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
-{
-        return 0;
-}
-static inline u32 omap1_usb1_init(unsigned nwires)
-{
-        return 0;
-}
-static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-        return 0;
-}
-#endif
-#endif  /* __ASM_ARCH_OMAP_USB_H */
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
deleted file mode 100644
index 3792bdea2f6d..000000000000
--- a/arch/arm/plat-omap/include/plat/vrfb.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * VRFB Rotation Engine
- *
- * Copyright (C) 2009 Nokia Corporation
- * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-#ifndef __OMAP_VRFB_H__
-#define __OMAP_VRFB_H__
-#define OMAP_VRFB_LINE_LEN 2048
-struct vrfb {
-        u8 context;
-        void __iomem *vaddr[4];
-        unsigned long paddr[4];
-        u16 xres;
-        u16 yres;
-        u16 xoffset;
-        u16 yoffset;
-        u8 bytespp;
-        bool yuv_mode;
-};
-#ifdef CONFIG_OMAP2_VRFB
-extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
-extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
-extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
-                u8 bytespp);
-extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
-extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
-extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-                u16 width, u16 height,
-                unsigned bytespp, bool yuv_mode);
-extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
-extern void omap_vrfb_restore_context(void);
-#else
-static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
-static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
-static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
-                u8 bytespp) {}
-static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
-                { return 0; }
-static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
-                { return 0; }
-static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
-                u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
-static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
-                { return 0; }
-static inline void omap_vrfb_restore_context(void) {}
-#endif
-#endif /* __VRFB_H */
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 28acb383e7df..743fc2836f7a 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -20,198 +20,20 @@
 #include <linux/init.h>
 #include <linux/io.h>
+#include <asm/fncpy.h>
 #include <asm/tlb.h>
 #include <asm/cacheflush.h>
 #include <asm/mach/map.h>
-#include <plat/sram.h>
-#include <plat/cpu.h>
-#include "sram.h"
-/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
-#include "../mach-omap2/iomap.h"
-#include "../mach-omap2/prm2xxx_3xxx.h"
-#include "../mach-omap2/sdrc.h"
-#define OMAP1_SRAM_PA           0x20000000
-#define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
-#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
-#ifdef CONFIG_OMAP4_ERRATA_I688
-#define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
-#else
-#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
-#endif
-#define OMAP5_SRAM_PA           0x40300000
-#if defined(CONFIG_ARCH_OMAP2PLUS)
-#define SRAM_BOOTLOADER_SZ      0x00
-#else
-#define SRAM_BOOTLOADER_SZ      0x80
-#endif
-#define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
-#define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
-#define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
-#define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
-#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
-#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
-#define GP_DEVICE               0x300
 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
-static unsigned long omap_sram_start;
 static void __iomem *omap_sram_base;
 static unsigned long omap_sram_skip;
 static unsigned long omap_sram_size;
 static void __iomem *omap_sram_ceil;
 /*
- * Depending on the target RAMFS firewall setup, the public usable amount of
- * SRAM varies.  The default accessible size for all device types is 2k. A GP
- * device allows ARM11 but not other initiators for full size. This
- * functionality seems ok until some nice security API happens.
- */
-static int is_sram_locked(void)
-{
-        if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
-                /* RAMFW: R/W access to all initiators for all qualifier sets */
-                if (cpu_is_omap242x()) {
-                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
-                }
-                if (cpu_is_omap34xx()) {
-                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
-                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
-                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
-                }
-                return 0;
-        } else
-                return 1; /* assume locked with no PPA or security driver */
-}
-/*
- * The amount of SRAM depends on the core type.
- * Note that we cannot try to test for SRAM here because writes
- * to secure SRAM will hang the system. Also the SRAM is not
- * yet mapped at this point.
- */
-static void __init omap_detect_sram(void)
-{
-        omap_sram_skip = SRAM_BOOTLOADER_SZ;
-        if (cpu_class_is_omap2()) {
-                if (is_sram_locked()) {
-                        if (cpu_is_omap34xx()) {
-                                omap_sram_start = OMAP3_SRAM_PUB_PA;
-                                if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
-                                    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
-                                        omap_sram_size = 0x7000; /* 28K */
-                                        omap_sram_skip += SZ_16K;
-                                } else {
-                                        omap_sram_size = 0x8000; /* 32K */
-                                }
-                        } else if (cpu_is_omap44xx()) {
-                                omap_sram_start = OMAP4_SRAM_PUB_PA;
-                                omap_sram_size = 0xa000; /* 40K */
-                        } else if (soc_is_omap54xx()) {
-                                omap_sram_start = OMAP5_SRAM_PA;
-                                omap_sram_size = SZ_128K; /* 128KB */
-                        } else {
-                                omap_sram_start = OMAP2_SRAM_PUB_PA;
-                                omap_sram_size = 0x800; /* 2K */
-                        }
-                } else {
-                        if (soc_is_am33xx()) {
-                                omap_sram_start = AM33XX_SRAM_PA;
-                                omap_sram_size = 0x10000; /* 64K */
-                        } else if (cpu_is_omap34xx()) {
-                                omap_sram_start = OMAP3_SRAM_PA;
-                                omap_sram_size = 0x10000; /* 64K */
-                        } else if (cpu_is_omap44xx()) {
-                                omap_sram_start = OMAP4_SRAM_PA;
-                                omap_sram_size = 0xe000; /* 56K */
-                        } else if (soc_is_omap54xx()) {
-                                omap_sram_start = OMAP5_SRAM_PA;
-                                omap_sram_size = SZ_128K; /* 128KB */
-                        } else {
-                                omap_sram_start = OMAP2_SRAM_PA;
-                                if (cpu_is_omap242x())
-                                        omap_sram_size = 0xa0000; /* 640K */
-                                else if (cpu_is_omap243x())
-                                        omap_sram_size = 0x10000; /* 64K */
-                        }
-                }
-        } else {
-                omap_sram_start = OMAP1_SRAM_PA;
-                if (cpu_is_omap7xx())
-                        omap_sram_size = 0x32000;       /* 200K */
-                else if (cpu_is_omap15xx())
-                        omap_sram_size = 0x30000;       /* 192K */
-                else if (cpu_is_omap1610() || cpu_is_omap1611() ||
-                                cpu_is_omap1621() || cpu_is_omap1710())
-                        omap_sram_size = 0x4000;        /* 16K */
-                else {
-                        pr_err("Could not detect SRAM size\n");
-                        omap_sram_size = 0x4000;
-                }
-        }
-}
-/*
- * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
- */
-static void __init omap_map_sram(void)
-{
-        int cached = 1;
-        if (omap_sram_size == 0)
-                return;
-#ifdef CONFIG_OMAP4_ERRATA_I688
-        if (cpu_is_omap44xx()) {
-                omap_sram_start += PAGE_SIZE;
-                omap_sram_size -= SZ_16K;
-        }
-#endif
-        if (cpu_is_omap34xx()) {
-                /*
-                 * SRAM must be marked as non-cached on OMAP3 since the
-                 * CORE DPLL M2 divider change code (in SRAM) runs with the
-                 * SDRAM controller disabled, and if it is marked cached,
-                 * the ARM may attempt to write cache lines back to SDRAM
-                 * which will cause the system to hang.
-                 */
-                cached = 0;
-        }
-        omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
-        omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
-                                                cached);
-        if (!omap_sram_base) {
-                pr_err("SRAM: Could not map\n");
-                return;
-        }
-        omap_sram_ceil = omap_sram_base + omap_sram_size;
-        /*
-         * Looks like we need to preserve some bootloader code at the
-         * beginning of SRAM for jumping to flash for reboot to work...
-         */
-        memset_io(omap_sram_base + omap_sram_skip, 0,
-                  omap_sram_size - omap_sram_skip);
-}
-/*
 * Memory allocator for SRAM: calculates the new ceiling address
 * for pushing a function using the fncpy API.
 *
@@ -236,171 +58,39 @@ void *omap_sram_push_address(unsigned long size)
        return (void *)omap_sram_ceil;
 }
-#ifdef CONFIG_ARCH_OMAP1
+/*
+ * The SRAM context is lost during off-idle and stack
-static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
+ * needs to be reset.
+ */
-void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
+void omap_sram_reset(void)
-{
-        BUG_ON(!_omap_sram_reprogram_clock);
-        /* On 730, bit 13 must always be 1 */
-        if (cpu_is_omap7xx())
-                ckctl |= 0x2000;
-        _omap_sram_reprogram_clock(dpllctl, ckctl);
-}
-static int __init omap1_sram_init(void)
-{
-        _omap_sram_reprogram_clock =
-                        omap_sram_push(omap1_sram_reprogram_clock,
-                                        omap1_sram_reprogram_clock_sz);
-        return 0;
-}
-#else
-#define omap1_sram_init()       do {} while (0)
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
-static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                              u32 base_cs, u32 force_unlock);
-void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                   u32 base_cs, u32 force_unlock)
-{
-        BUG_ON(!_omap2_sram_ddr_init);
-        _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
-                             base_cs, force_unlock);
-}
-static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
-                                          u32 mem_type);
-void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
-{
-        BUG_ON(!_omap2_sram_reprogram_sdrc);
-        _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
-}
-static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
-{
-        BUG_ON(!_omap2_set_prcm);
-        return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
-}
-#endif
-#ifdef CONFIG_SOC_OMAP2420
-static int __init omap242x_sram_init(void)
-{
-        _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
-                                        omap242x_sram_ddr_init_sz);
-        _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
-                                            omap242x_sram_reprogram_sdrc_sz);
-        _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
-                                         omap242x_sram_set_prcm_sz);
-        return 0;
-}
-#else
-static inline int omap242x_sram_init(void)
-{
-        return 0;
-}
-#endif
-#ifdef CONFIG_SOC_OMAP2430
-static int __init omap243x_sram_init(void)
-{
-        _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
-                                        omap243x_sram_ddr_init_sz);
-        _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
-                                            omap243x_sram_reprogram_sdrc_sz);
-        _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
-                                         omap243x_sram_set_prcm_sz);
-        return 0;
-}
-#else
-static inline int omap243x_sram_init(void)
-{
-        return 0;
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-static u32 (*_omap3_sram_configure_core_dpll)(
-                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
-u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
-                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
-                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
-                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
-                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
-{
-        BUG_ON(!_omap3_sram_configure_core_dpll);
-        return _omap3_sram_configure_core_dpll(
-                        m2, unlock_dll, f, inc,
-                        sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
-                        sdrc_actim_ctrl_b_0, sdrc_mr_0,
-                        sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
-                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
-}
-void omap3_sram_restore_context(void)
 {
        omap_sram_ceil = omap_sram_base + omap_sram_size;
-        _omap3_sram_configure_core_dpll =
-                omap_sram_push(omap3_sram_configure_core_dpll,
-                               omap3_sram_configure_core_dpll_sz);
-        omap_push_sram_idle();
 }
-static inline int omap34xx_sram_init(void)
+/*
-{
+ * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
-        omap3_sram_restore_context();
+ */
-        return 0;
+void __init omap_map_sram(unsigned long start, unsigned long size,
-}
+                                 unsigned long skip, int cached)
-#else
-static inline int omap34xx_sram_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_ARCH_OMAP3 */
-static inline int am33xx_sram_init(void)
 {
-        return 0;
+        if (size == 0)
-}
+                return;
-int __init omap_sram_init(void)
+        start = ROUND_DOWN(start, PAGE_SIZE);
-{
+        omap_sram_size = size;
-        omap_detect_sram();
+        omap_sram_skip = skip;
-        omap_map_sram();
+        omap_sram_base = __arm_ioremap_exec(start, size, cached);
+        if (!omap_sram_base) {
+                pr_err("SRAM: Could not map\n");
+                return;
+        }
-        if (!(cpu_class_is_omap2()))
+        omap_sram_reset();
-                omap1_sram_init();
-        else if (cpu_is_omap242x())
-                omap242x_sram_init();
-        else if (cpu_is_omap2430())
-                omap243x_sram_init();
-        else if (soc_is_am33xx())
-                am33xx_sram_init();
-        else if (cpu_is_omap34xx())
-                omap34xx_sram_init();
-        return 0;
+        /*
+         * Looks like we need to preserve some bootloader code at the
+         * beginning of SRAM for jumping to flash for reboot to work...
+         */
+        memset_io(omap_sram_base + omap_sram_skip, 0,
+                  omap_sram_size - omap_sram_skip);
 }
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
deleted file mode 100644
index 29b43ef97f20..000000000000
--- a/arch/arm/plat-omap/sram.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PLAT_OMAP_SRAM_H__
-#define __PLAT_OMAP_SRAM_H__
-extern int __init omap_sram_init(void);
-#endif /* __PLAT_OMAP_SRAM_H__ */
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 1867944415ca..8db0b981ca64 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -41,7 +41,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 static int __init orion_add_irq_domain(struct device_node *np,
                                       struct device_node *interrupt_parent)
 {
-        int i = 0, irq_gpio;
+        int i = 0;
        void __iomem *base;
        do {
@@ -54,10 +54,6 @@ static int __init orion_add_irq_domain(struct device_node *np,
        irq_domain_add_legacy(np, i * 32, 0, 0,
                              &irq_domain_simple_ops, NULL);
-        irq_gpio = i * 32;
-        orion_gpio_of_init(irq_gpio);
        return 0;
 }
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index af8e484001e5..1fc941944912 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -5,7 +5,6 @@
 obj-y   := dma.o
 obj-$(CONFIG_PXA3xx)            += mfp.o
-obj-$(CONFIG_PXA95x)            += mfp.o
 obj-$(CONFIG_ARCH_MMP)          += mfp.o
 obj-$(CONFIG_PXA_SSP)           += ssp.o
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 5c79c29f2833..10bc4f3757d1 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -423,7 +423,7 @@ typedef unsigned long mfp_cfg_t;
        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) || defined(CONFIG_ARCH_MMP)
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
 /*
 * each MFP pin will have a MFPR register, since the offset of the
 * register varies between processors, the processor specific code
@@ -470,6 +470,6 @@ void mfp_write(int mfp, unsigned long mfpr_val);
 void mfp_config(unsigned long *mfp_cfgs, int num);
 void mfp_config_run(void);
 void mfp_config_lpm(void);
-#endif /* CONFIG_PXA3xx || CONFIG_PXA95x || CONFIG_ARCH_MMP */
+#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
 #endif /* __ASM_PLAT_MFP_H */
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index db98e7021f0d..ba3e76c95504 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -325,7 +325,7 @@ static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
        chan->state = S3C2410_DMA_RUNNING;
-        /* check wether there is anything to load, and if not, see
+        /* check whether there is anything to load, and if not, see
         * if we can find anything to load
         */
@@ -473,12 +473,13 @@ int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
                pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
                         chan->number, __func__, buf);
-                if (chan->end == NULL)
+                if (chan->end == NULL) {
                        pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
                                 chan->number, __func__, chan);
+                } else {
-                chan->end->next = buf;
+                        chan->end->next = buf;
-                chan->end = buf;
+                        chan->end = buf;
+                }
        }
        /* if necessary, update the next buffer field */
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 59401e1cc530..a9d52167e16e 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -414,6 +414,11 @@ config S5P_SETUP_MIPIPHY
        help
          Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
+config S3C_SETUP_CAMIF
+        bool
+        help
+          Compile in common setup code for S3C CAMIF devices
 # DMA
 config S3C_DMA
@@ -502,5 +507,6 @@ config DEBUG_S3C_UART
        default "0" if DEBUG_S3C_UART0
        default "1" if DEBUG_S3C_UART1
        default "2" if DEBUG_S3C_UART2
+        default "3" if DEBUG_S3C_UART3
 endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 9e40e8d00740..3a7c64d1814a 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_S5P_DEV_UART)	+= s5p-dev-uart.o
 obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT)     += dev-backlight.o
+obj-$(CONFIG_S3C_SETUP_CAMIF)   += setup-camif.o
 obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
 # DMA support
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index b1e05ccff3ac..37542c2689a2 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -344,7 +344,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
        int ret;
        unsigned tmp;
-        adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
+        adc = devm_kzalloc(dev, sizeof(struct adc_device), GFP_KERNEL);
        if (adc == NULL) {
                dev_err(dev, "failed to allocate adc_device\n");
                return -ENOMEM;
@@ -355,50 +355,46 @@ static int s3c_adc_probe(struct platform_device *pdev)
        adc->pdev = pdev;
        adc->prescale = S3C2410_ADCCON_PRSCVL(49);
-        adc->vdd = regulator_get(dev, "vdd");
+        adc->vdd = devm_regulator_get(dev, "vdd");
        if (IS_ERR(adc->vdd)) {
                dev_err(dev, "operating without regulator \"vdd\" .\n");
-                ret = PTR_ERR(adc->vdd);
+                return PTR_ERR(adc->vdd);
-                goto err_alloc;
        }
        adc->irq = platform_get_irq(pdev, 1);
        if (adc->irq <= 0) {
                dev_err(dev, "failed to get adc irq\n");
-                ret = -ENOENT;
+                return -ENOENT;
-                goto err_reg;
        }
-        ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
+        ret = devm_request_irq(dev, adc->irq, s3c_adc_irq, 0, dev_name(dev),
+                                adc);
        if (ret < 0) {
                dev_err(dev, "failed to attach adc irq\n");
-                goto err_reg;
+                return ret;
        }
-        adc->clk = clk_get(dev, "adc");
+        adc->clk = devm_clk_get(dev, "adc");
        if (IS_ERR(adc->clk)) {
                dev_err(dev, "failed to get adc clock\n");
-                ret = PTR_ERR(adc->clk);
+                return PTR_ERR(adc->clk);
-                goto err_irq;
        }
        regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!regs) {
                dev_err(dev, "failed to find registers\n");
-                ret = -ENXIO;
+                return -ENXIO;
-                goto err_clk;
        }
-        adc->regs = ioremap(regs->start, resource_size(regs));
+        adc->regs = devm_request_and_ioremap(dev, regs);
        if (!adc->regs) {
                dev_err(dev, "failed to map registers\n");
-                ret = -ENXIO;
+                return -ENXIO;
-                goto err_clk;
        }
        ret = regulator_enable(adc->vdd);
        if (ret)
-                goto err_ioremap;
+                return ret;
        clk_enable(adc->clk);
@@ -418,32 +414,14 @@ static int s3c_adc_probe(struct platform_device *pdev)
        adc_dev = adc;
        return 0;
- err_ioremap:
-        iounmap(adc->regs);
- err_clk:
-        clk_put(adc->clk);
- err_irq:
-        free_irq(adc->irq, adc);
- err_reg:
-        regulator_put(adc->vdd);
- err_alloc:
-        kfree(adc);
-        return ret;
 }
 static int __devexit s3c_adc_remove(struct platform_device *pdev)
 {
        struct adc_device *adc = platform_get_drvdata(pdev);
-        iounmap(adc->regs);
-        free_irq(adc->irq, adc);
        clk_disable(adc->clk);
        regulator_disable(adc->vdd);
-        regulator_put(adc->vdd);
-        clk_put(adc->clk);
-        kfree(adc);
        return 0;
 }
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 012bbd0b8d81..47c9fad43f00 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -389,6 +389,72 @@ int __init s3c24xx_register_baseclocks(unsigned long xtal)
 static struct dentry *clk_debugfs_root;
+static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
+{
+        struct clk *child;
+        const char *state;
+        char buf[255] = { 0 };
+        int n = 0;
+        if (c->name)
+                n = snprintf(buf, sizeof(buf) - 1, "%s", c->name);
+        if (c->devname)
+                n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname);
+        state = (c->usage > 0) ? "on" : "off";
+        seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n",
+                   level * 3 + 1, "",
+                   50 - level * 3, buf,
+                   state, c->usage, clk_get_rate(c));
+        list_for_each_entry(child, &clocks, list) {
+                if (child->parent != c)
+                        continue;
+                clock_tree_show_one(s, child, level + 1);
+        }
+}
+static int clock_tree_show(struct seq_file *s, void *data)
+{
+        struct clk *c;
+        unsigned long flags;
+        seq_printf(s, " clock state ref rate\n");
+        seq_printf(s, "----------------------------------------------------\n");
+        spin_lock_irqsave(&clocks_lock, flags);
+        list_for_each_entry(c, &clocks, list)
+                if (c->parent == NULL)
+                        clock_tree_show_one(s, c, 0);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+        return 0;
+}
+static int clock_tree_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, clock_tree_show, inode->i_private);
+}
+static const struct file_operations clock_tree_fops = {
+        .open           = clock_tree_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+static int clock_rate_show(void *data, u64 *val)
+{
+        struct clk *c = data;
+        *val = clk_get_rate(c);
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n");
 static int clk_debugfs_register_one(struct clk *c)
 {
        int err;
@@ -411,7 +477,7 @@ static int clk_debugfs_register_one(struct clk *c)
                goto err_out;
        }
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops);
        if (!d) {
                err = -ENOMEM;
                goto err_out;
@@ -446,13 +512,18 @@ static int __init clk_debugfs_init(void)
 {
        struct clk *c;
        struct dentry *d;
-        int err;
+        int err = -ENOMEM;
        d = debugfs_create_dir("clock", NULL);
        if (!d)
                return -ENOMEM;
        clk_debugfs_root = d;
+        d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
+                                 &clock_tree_fops);
+        if (!d)
+                goto err_out;
        list_for_each_entry(c, &clocks, list) {
                err = clk_debugfs_register(c);
                if (err)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 03f654d55eff..51afedda9ab6 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -146,15 +146,6 @@ struct platform_device s3c_device_camif = {
 /* ASOC DMA */
-struct platform_device samsung_asoc_dma = {
-        .name           = "samsung-audio",
-        .id             = -1,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
 struct platform_device samsung_asoc_idma = {
        .name           = "samsung-idma",
        .id             = -1,
@@ -486,11 +477,7 @@ static struct resource s3c_i2c0_resource[] = {
 struct platform_device s3c_device_i2c0 = {
        .name           = "s3c2410-i2c",
-#ifdef CONFIG_S3C_DEV_I2C1
        .id             = 0,
-#else
-        .id             = -1,
-#endif
        .num_resources  = ARRAY_SIZE(s3c_i2c0_resource),
        .resource       = s3c_i2c0_resource,
 };
@@ -933,6 +920,7 @@ struct platform_device s5p_device_mfc_r = {
                .coherent_dma_mask      = DMA_BIT_MASK(32),
        },
 };
 #endif /* CONFIG_S5P_DEV_MFC */
 /* MIPI CSIS */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index ace4451b7651..e0072ce8d6e9 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,6 +43,7 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4_CPU_MASK        0xFFFE0000
 #define EXYNOS5250_SOC_ID       0x43520000
+#define EXYNOS5440_SOC_ID       0x54400000
 #define EXYNOS5_SOC_MASK        0xFFFFF000
 #define IS_SAMSUNG_CPU(name, id, mask)          \
@@ -62,6 +63,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
    defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -130,6 +132,12 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5250()    0
 #endif
+#if defined(CONFIG_SOC_EXYNOS5440)
+# define soc_is_exynos5440()    is_samsung_exynos5440()
+#else
+# define soc_is_exynos5440()    0
+#endif
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 #ifndef KHZ
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5da4b4f38f40..87d501ff3328 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -123,7 +123,6 @@ extern struct platform_device s5pv210_device_spdif;
 extern struct platform_device exynos4_device_ac97;
 extern struct platform_device exynos4_device_ahci;
-extern struct platform_device exynos4_device_dwmci;
 extern struct platform_device exynos4_device_i2s0;
 extern struct platform_device exynos4_device_i2s1;
 extern struct platform_device exynos4_device_i2s2;
@@ -133,9 +132,6 @@ extern struct platform_device exynos4_device_pcm1;
 extern struct platform_device exynos4_device_pcm2;
 extern struct platform_device exynos4_device_spdif;
-extern struct platform_device exynos_device_drm;
-extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 1fe6917f6a2a..dfd8b7af8c7a 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -48,6 +48,7 @@ struct samsung_gpio_cfg;
 * @config: special function and pull-resistor control information.
 * @lock: Lock for exclusive access to this gpio bank.
 * @pm_save: Save information for suspend/resume support.
+ * @bitmap_gpio_int: Bitmap for representing GPIO interrupt or not.
 *
 * This wrapper provides the necessary information for the Samsung
 * specific gpios being registered with gpiolib.
@@ -71,6 +72,7 @@ struct samsung_gpio_chip {
 #ifdef CONFIG_PM
        u32                     pm_save[4];
 #endif
+        u32                     bitmap_gpio_int;
 };
 static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc)
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
index ac13227272f0..e6d7c42d68b6 100644
--- a/arch/arm/plat-samsung/include/plat/mfc.h
+++ b/arch/arm/plat-samsung/include/plat/mfc.h
@@ -10,6 +10,14 @@
 #ifndef __PLAT_SAMSUNG_MFC_H
 #define __PLAT_SAMSUNG_MFC_H __FILE__
+struct s5p_mfc_dt_meminfo {
+        unsigned long   loff;
+        unsigned long   lsize;
+        unsigned long   roff;
+        unsigned long   rsize;
+        char            *compatible;
+};
 /**
 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
 * @rbase:      base address for MFC 'right' memory interface
@@ -24,4 +32,7 @@
 void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                phys_addr_t lbase, unsigned int lsize);
+int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
+                                int depth, void *data);
 #endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 61fc53740fbd..887a0c954379 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -107,10 +107,12 @@ extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
 extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
 #ifdef CONFIG_PM
+extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
 extern int s3c24xx_irq_suspend(void);
 extern void s3c24xx_irq_resume(void);
 #else
+#define s3c_irq_wake NULL
 #define s3c_irqext_wake NULL
 #define s3c24xx_irq_suspend NULL
 #define s3c24xx_irq_resume  NULL
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index ad6089465e2a..5ec104b5408b 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -14,6 +14,8 @@
 #include <linux/dma-mapping.h>
 #include <linux/memblock.h>
 #include <linux/ioport.h>
+#include <linux/of_fdt.h>
+#include <linux/of.h>
 #include <mach/map.h>
 #include <plat/devs.h>
@@ -69,3 +71,35 @@ static int __init s5p_mfc_memory_init(void)
        return 0;
 }
 device_initcall(s5p_mfc_memory_init);
+#ifdef CONFIG_OF
+int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
+                                int depth, void *data)
+{
+        __be32 *prop;
+        unsigned long len;
+        struct s5p_mfc_dt_meminfo *mfc_mem = data;
+        if (!data)
+                return 0;
+        if (!of_flat_dt_is_compatible(node, mfc_mem->compatible))
+                return 0;
+        prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len);
+        if (!prop || (len != 2 * sizeof(unsigned long)))
+                return 0;
+        mfc_mem->loff = be32_to_cpu(prop[0]);
+        mfc_mem->lsize = be32_to_cpu(prop[1]);
+        prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len);
+        if (!prop || (len != 2 * sizeof(unsigned long)))
+                return 0;
+        mfc_mem->roff = be32_to_cpu(prop[0]);
+        mfc_mem->rsize = be32_to_cpu(prop[1]);
+        return 1;
+}
+#endif
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index 23557d30e44c..bae56131a50a 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -185,7 +185,7 @@ int __init s5p_register_gpio_interrupt(int pin)
        /* check if the group has been already registered */
        if (my_chip->irq_base)
-                return my_chip->irq_base + offset;
+                goto success;
        /* register gpio group */
        ret = s5p_gpioint_add(my_chip);
@@ -193,9 +193,13 @@ int __init s5p_register_gpio_interrupt(int pin)
                my_chip->chip.to_irq = samsung_gpiolib_to_irq;
                printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
                       group);
-                return my_chip->irq_base + offset;
+                goto success;
        }
        return ret;
+success:
+        my_chip->bitmap_gpio_int |= BIT(offset);
+        return my_chip->irq_base + offset;
 }
 int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
diff --git a/arch/arm/plat-samsung/setup-camif.c b/arch/arm/plat-samsung/setup-camif.c
new file mode 100644
index 000000000000..e01bf760af2c
--- /dev/null
+++ b/arch/arm/plat-samsung/setup-camif.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
+ *
+ * Helper functions for S3C24XX/S3C64XX SoC series CAMIF driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+/* Number of camera port pins, without FIELD */
+#define S3C_CAMIF_NUM_GPIOS     13
+/* Default camera port configuration helpers. */
+static void camif_get_gpios(int *gpio_start, int *gpio_reset)
+{
+#ifdef CONFIG_ARCH_S3C24XX
+        *gpio_start = S3C2410_GPJ(0);
+        *gpio_reset = S3C2410_GPJ(12);
+#else
+        /* s3c64xx */
+        *gpio_start = S3C64XX_GPF(0);
+        *gpio_reset = S3C64XX_GPF(3);
+#endif
+}
+int s3c_camif_gpio_get(void)
+{
+        int gpio_start, gpio_reset;
+        int ret, i;
+        camif_get_gpios(&gpio_start, &gpio_reset);
+        for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) {
+                int gpio = gpio_start + i;
+                if (gpio == gpio_reset)
+                        continue;
+                ret = gpio_request(gpio, "camif");
+                if (!ret)
+                        ret = s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                if (ret) {
+                        pr_err("failed to configure GPIO %d\n", gpio);
+                        for (--i; i >= 0; i--)
+                                gpio_free(gpio--);
+                        return ret;
+                }
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        return 0;
+}
+void s3c_camif_gpio_put(void)
+{
+        int i, gpio_start, gpio_reset;
+        camif_get_gpios(&gpio_start, &gpio_reset);
+        for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) {
+                int gpio = gpio_start + i;
+                if (gpio != gpio_reset)
+                        gpio_free(gpio);
+        }
+}
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index f8db7b2deb36..87dbd81bdf51 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -12,6 +12,7 @@ config ARCH_SPEAR13XX
        bool "ST SPEAr13xx with Device Tree"
        select ARM_GIC
        select CPU_V7
+        select GPIO_SPEAR_SPICS
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 2607bd05c525..01e88532a5db 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,5 +5,5 @@
 # Common support
 obj-y   := restart.o time.o
-obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o shirq.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o
 obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
diff --git a/arch/arm/plat-spear/include/plat/shirq.h b/arch/arm/plat-spear/include/plat/shirq.h
deleted file mode 100644
index 88a7fbd24793..000000000000
--- a/arch/arm/plat-spear/include/plat/shirq.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/shirq.h
- *
- * SPEAr platform shared irq layer header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_SHIRQ_H
-#define __PLAT_SHIRQ_H
-#include <linux/irq.h>
-#include <linux/types.h>
-/*
- * struct shirq_dev_config: shared irq device configuration
- *
- * virq: virtual irq number of device
- * enb_mask: enable mask of device
- * status_mask: status mask of device
- * clear_mask: clear mask of device
- */
-struct shirq_dev_config {
-        u32 virq;
-        u32 enb_mask;
-        u32 status_mask;
-        u32 clear_mask;
-};
-/*
- * struct shirq_regs: shared irq register configuration
- *
- * base: base address of shared irq register
- * enb_reg: enable register offset
- * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
- * status_reg: status register offset
- * status_reg_mask: status register valid mask
- * clear_reg: clear register offset
- * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
- */
-struct shirq_regs {
-        void __iomem *base;
-        u32 enb_reg;
-        u32 reset_to_enb;
-        u32 status_reg;
-        u32 status_reg_mask;
-        u32 clear_reg;
-        u32 reset_to_clear;
-};
-/*
- * struct spear_shirq: shared irq structure
- *
- * irq: hardware irq number
- * dev_config: array of device config structures which are using "irq" line
- * dev_count: size of dev_config array
- * regs: register configuration for shared irq block
- */
-struct spear_shirq {
-        u32 irq;
-        struct shirq_dev_config *dev_config;
-        u32 dev_count;
-        struct shirq_regs regs;
-};
-int spear_shirq_register(struct spear_shirq *shirq);
-#endif /* __PLAT_SHIRQ_H */
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
deleted file mode 100644
index 853e891e1184..000000000000
--- a/arch/arm/plat-spear/shirq.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/arm/plat-spear/shirq.c
- *
- * SPEAr platform shared irq layer source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/spinlock.h>
-#include <plat/shirq.h>
-struct spear_shirq *shirq;
-static DEFINE_SPINLOCK(lock);
-static void shirq_irq_mask(struct irq_data *d)
-{
-        struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
-        u32 val, id = d->irq - shirq->dev_config[0].virq;
-        unsigned long flags;
-        if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
-                return;
-        spin_lock_irqsave(&lock, flags);
-        val = readl(shirq->regs.base + shirq->regs.enb_reg);
-        if (shirq->regs.reset_to_enb)
-                val |= shirq->dev_config[id].enb_mask;
-        else
-                val &= ~(shirq->dev_config[id].enb_mask);
-        writel(val, shirq->regs.base + shirq->regs.enb_reg);
-        spin_unlock_irqrestore(&lock, flags);
-}
-static void shirq_irq_unmask(struct irq_data *d)
-{
-        struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
-        u32 val, id = d->irq - shirq->dev_config[0].virq;
-        unsigned long flags;
-        if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
-                return;
-        spin_lock_irqsave(&lock, flags);
-        val = readl(shirq->regs.base + shirq->regs.enb_reg);
-        if (shirq->regs.reset_to_enb)
-                val &= ~(shirq->dev_config[id].enb_mask);
-        else
-                val |= shirq->dev_config[id].enb_mask;
-        writel(val, shirq->regs.base + shirq->regs.enb_reg);
-        spin_unlock_irqrestore(&lock, flags);
-}
-static struct irq_chip shirq_chip = {
-        .name           = "spear_shirq",
-        .irq_ack        = shirq_irq_mask,
-        .irq_mask       = shirq_irq_mask,
-        .irq_unmask     = shirq_irq_unmask,
-};
-static void shirq_handler(unsigned irq, struct irq_desc *desc)
-{
-        u32 i, val, mask;
-        struct spear_shirq *shirq = irq_get_handler_data(irq);
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-        while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
-                                shirq->regs.status_reg_mask)) {
-                for (i = 0; (i < shirq->dev_count) && val; i++) {
-                        if (!(shirq->dev_config[i].status_mask & val))
-                                continue;
-                        generic_handle_irq(shirq->dev_config[i].virq);
-                        /* clear interrupt */
-                        val &= ~shirq->dev_config[i].status_mask;
-                        if ((shirq->regs.clear_reg == -1) ||
-                                        shirq->dev_config[i].clear_mask == -1)
-                                continue;
-                        mask = readl(shirq->regs.base + shirq->regs.clear_reg);
-                        if (shirq->regs.reset_to_clear)
-                                mask &= ~shirq->dev_config[i].clear_mask;
-                        else
-                                mask |= shirq->dev_config[i].clear_mask;
-                        writel(mask, shirq->regs.base + shirq->regs.clear_reg);
-                }
-        }
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-int spear_shirq_register(struct spear_shirq *shirq)
-{
-        int i;
-        if (!shirq || !shirq->dev_config || !shirq->regs.base)
-                return -EFAULT;
-        if (!shirq->dev_count)
-                return -EINVAL;
-        irq_set_chained_handler(shirq->irq, shirq_handler);
-        for (i = 0; i < shirq->dev_count; i++) {
-                irq_set_chip_and_handler(shirq->dev_config[i].virq,
-                                         &shirq_chip, handle_simple_irq);
-                set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
-                irq_set_chip_data(shirq->dev_config[i].virq, shirq);
-        }
-        irq_set_handler_data(shirq->irq, shirq);
-        return 0;
-}
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 2a4ae8a6a081..2c4332b9f948 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -6,20 +6,11 @@ config PLAT_VERSATILE_CLOCK
 config PLAT_VERSATILE_CLCD
        bool
-config PLAT_VERSATILE_FPGA_IRQ
-        bool
-        select IRQ_DOMAIN
-config PLAT_VERSATILE_FPGA_IRQ_NR
-       int
-       default 4
-       depends on PLAT_VERSATILE_FPGA_IRQ
 config PLAT_VERSATILE_LEDS
        def_bool y if NEW_LEDS
        depends on ARCH_REALVIEW || ARCH_VERSATILE
        select LEDS_CLASS
-        select LEDS_TRIGGER
+        select LEDS_TRIGGERS
 config PLAT_VERSATILE_SCHED_CLOCK
        def_bool y
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 74cfd94cbf80..f88d448b629c 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,7 +2,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
-obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
 obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
 obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
deleted file mode 100644
index 091ae1030045..000000000000
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- *  Support for Versatile FPGA-based IRQ controllers
- */
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/irqdomain.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
-#include <plat/fpga-irq.h>
-#define IRQ_STATUS              0x00
-#define IRQ_RAW_STATUS          0x04
-#define IRQ_ENABLE_SET          0x08
-#define IRQ_ENABLE_CLEAR        0x0c
-#define INT_SOFT_SET            0x10
-#define INT_SOFT_CLEAR          0x14
-#define FIQ_STATUS              0x20
-#define FIQ_RAW_STATUS          0x24
-#define FIQ_ENABLE              0x28
-#define FIQ_ENABLE_SET          0x28
-#define FIQ_ENABLE_CLEAR        0x2C
-/**
- * struct fpga_irq_data - irq data container for the FPGA IRQ controller
- * @base: memory offset in virtual memory
- * @chip: chip container for this instance
- * @domain: IRQ domain for this instance
- * @valid: mask for valid IRQs on this controller
- * @used_irqs: number of active IRQs on this controller
- */
-struct fpga_irq_data {
-        void __iomem *base;
-        struct irq_chip chip;
-        u32 valid;
-        struct irq_domain *domain;
-        u8 used_irqs;
-};
-/* we cannot allocate memory when the controllers are initially registered */
-static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
-static int fpga_irq_id;
-static void fpga_irq_mask(struct irq_data *d)
-{
-        struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
-        u32 mask = 1 << d->hwirq;
-        writel(mask, f->base + IRQ_ENABLE_CLEAR);
-}
-static void fpga_irq_unmask(struct irq_data *d)
-{
-        struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
-        u32 mask = 1 << d->hwirq;
-        writel(mask, f->base + IRQ_ENABLE_SET);
-}
-static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
-{
-        struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
-        u32 status = readl(f->base + IRQ_STATUS);
-        if (status == 0) {
-                do_bad_IRQ(irq, desc);
-                return;
-        }
-        do {
-                irq = ffs(status) - 1;
-                status &= ~(1 << irq);
-                generic_handle_irq(irq_find_mapping(f->domain, irq));
-        } while (status);
-}
-/*
- * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
- * if we've handled at least one interrupt.  This does a single read of the
- * status register and handles all interrupts in order from LSB first.
- */
-static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
-{
-        int handled = 0;
-        int irq;
-        u32 status;
-        while ((status  = readl(f->base + IRQ_STATUS))) {
-                irq = ffs(status) - 1;
-                handle_IRQ(irq_find_mapping(f->domain, irq), regs);
-                handled = 1;
-        }
-        return handled;
-}
-/*
- * Keep iterating over all registered FPGA IRQ controllers until there are
- * no pending interrupts.
- */
-asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
-{
-        int i, handled;
-        do {
-                for (i = 0, handled = 0; i < fpga_irq_id; ++i)
-                        handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
-        } while (handled);
-}
-static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
-                irq_hw_number_t hwirq)
-{
-        struct fpga_irq_data *f = d->host_data;
-        /* Skip invalid IRQs, only register handlers for the real ones */
-        if (!(f->valid & (1 << hwirq)))
-                return -ENOTSUPP;
-        irq_set_chip_data(irq, f);
-        irq_set_chip_and_handler(irq, &f->chip,
-                                handle_level_irq);
-        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        f->used_irqs++;
-        return 0;
-}
-static struct irq_domain_ops fpga_irqdomain_ops = {
-        .map = fpga_irqdomain_map,
-        .xlate = irq_domain_xlate_onetwocell,
-};
-static __init struct fpga_irq_data *
-fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
-        struct fpga_irq_data *f;
-        if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
-                printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
-                return NULL;
-        }
-        f = &fpga_irq_devices[fpga_irq_id];
-        f->base = base;
-        f->chip.name = name;
-        f->chip.irq_ack = fpga_irq_mask;
-        f->chip.irq_mask = fpga_irq_mask;
-        f->chip.irq_unmask = fpga_irq_unmask;
-        f->valid = valid;
-        fpga_irq_id++;
-        return f;
-}
-void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
-                          int parent_irq, u32 valid, struct device_node *node)
-{
-        struct fpga_irq_data *f;
-        f = fpga_irq_prep_struct(base, name, valid);
-        if (!f)
-                return;
-        if (parent_irq != -1) {
-                irq_set_handler_data(parent_irq, f);
-                irq_set_chained_handler(parent_irq, fpga_irq_handle);
-        }
-        f->domain = irq_domain_add_legacy(node, fls(valid), irq_start, 0,
-                                          &fpga_irqdomain_ops, f);
-        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
-                fpga_irq_id, name, base, f->used_irqs);
-}
-#ifdef CONFIG_OF
-int __init fpga_irq_of_init(struct device_node *node,
-                            struct device_node *parent)
-{
-        struct fpga_irq_data *f;
-        void __iomem *base;
-        u32 clear_mask;
-        u32 valid_mask;
-        if (WARN_ON(!node))
-                return -ENODEV;
-        base = of_iomap(node, 0);
-        WARN(!base, "unable to map fpga irq registers\n");
-        if (of_property_read_u32(node, "clear-mask", &clear_mask))
-                clear_mask = 0;
-        if (of_property_read_u32(node, "valid-mask", &valid_mask))
-                valid_mask = 0;
-        f = fpga_irq_prep_struct(base, node->name, valid_mask);
-        if (!f)
-                return -ENOMEM;
-        writel(clear_mask, base + IRQ_ENABLE_CLEAR);
-        writel(clear_mask, base + FIQ_ENABLE_CLEAR);
-        f->domain = irq_domain_add_linear(node, fls(valid_mask), &fpga_irqdomain_ops, f);
-        f->used_irqs = hweight32(valid_mask);
-        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
-                fpga_irq_id, node->name, base, f->used_irqs);
-        return 0;
-}
-#endif
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h
deleted file mode 100644
index 1fac9651d3ca..000000000000
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef PLAT_FPGA_IRQ_H
-#define PLAT_FPGA_IRQ_H
-struct device_node;
-struct pt_regs;
-void fpga_handle_irq(struct pt_regs *regs);
-void fpga_irq_init(void __iomem *, const char *, int, int, u32,
-                struct device_node *node);
-int fpga_irq_of_init(struct device_node *node,
-                     struct device_node *parent);
-#endif
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index f57609275449..7a32976fa2a3 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -8,6 +8,8 @@
 #include <xen/features.h>
 #include <xen/platform_pci.h>
 #include <xen/xenbus.h>
+#include <xen/page.h>
+#include <xen/xen-ops.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 #include <linux/interrupt.h>
@@ -17,6 +19,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
+#include <linux/mm.h>
 struct start_info _xen_start_info;
 struct start_info *xen_start_info = &_xen_start_info;
 EXPORT_SYMBOL_GPL(xen_start_info);
@@ -29,6 +33,10 @@ struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
 DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
+/* These are unused until we support booting "pre-ballooned" */
+unsigned long xen_released_pages;
+struct xen_memory_region xen_extra_mem[XEN_EXTRA_MEM_MAX_REGIONS] __initdata;
 /* TODO: to be removed */
 __read_mostly int xen_have_vector_callback;
 EXPORT_SYMBOL_GPL(xen_have_vector_callback);
@@ -38,15 +46,106 @@ EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
 static __read_mostly int xen_events_irq = -1;
+/* map fgmfn of domid to lpfn in the current domain */
+static int map_foreign_page(unsigned long lpfn, unsigned long fgmfn,
+                            unsigned int domid)
+{
+        int rc;
+        struct xen_add_to_physmap_range xatp = {
+                .domid = DOMID_SELF,
+                .foreign_domid = domid,
+                .size = 1,
+                .space = XENMAPSPACE_gmfn_foreign,
+        };
+        xen_ulong_t idx = fgmfn;
+        xen_pfn_t gpfn = lpfn;
+        set_xen_guest_handle(xatp.idxs, &idx);
+        set_xen_guest_handle(xatp.gpfns, &gpfn);
+        rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap_range, &xatp);
+        if (rc) {
+                pr_warn("Failed to map pfn to mfn rc:%d pfn:%lx mfn:%lx\n",
+                        rc, lpfn, fgmfn);
+                return 1;
+        }
+        return 0;
+}
+struct remap_data {
+        xen_pfn_t fgmfn; /* foreign domain's gmfn */
+        pgprot_t prot;
+        domid_t  domid;
+        struct vm_area_struct *vma;
+        int index;
+        struct page **pages;
+        struct xen_remap_mfn_info *info;
+};
+static int remap_pte_fn(pte_t *ptep, pgtable_t token, unsigned long addr,
+                        void *data)
+{
+        struct remap_data *info = data;
+        struct page *page = info->pages[info->index++];
+        unsigned long pfn = page_to_pfn(page);
+        pte_t pte = pfn_pte(pfn, info->prot);
+        if (map_foreign_page(pfn, info->fgmfn, info->domid))
+                return -EFAULT;
+        set_pte_at(info->vma->vm_mm, addr, ptep, pte);
+        return 0;
+}
 int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
                               unsigned long addr,
-                               unsigned long mfn, int nr,
+                               xen_pfn_t mfn, int nr,
-                               pgprot_t prot, unsigned domid)
+                               pgprot_t prot, unsigned domid,
+                               struct page **pages)
 {
-        return -ENOSYS;
+        int err;
+        struct remap_data data;
+        /* TBD: Batching, current sole caller only does page at a time */
+        if (nr > 1)
+                return -EINVAL;
+        data.fgmfn = mfn;
+        data.prot = prot;
+        data.domid = domid;
+        data.vma = vma;
+        data.index = 0;
+        data.pages = pages;
+        err = apply_to_page_range(vma->vm_mm, addr, nr << PAGE_SHIFT,
+                                  remap_pte_fn, &data);
+        return err;
 }
 EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
+int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
+                               int nr, struct page **pages)
+{
+        int i;
+        for (i = 0; i < nr; i++) {
+                struct xen_remove_from_physmap xrp;
+                unsigned long rc, pfn;
+                pfn = page_to_pfn(pages[i]);
+                xrp.domid = DOMID_SELF;
+                xrp.gpfn = pfn;
+                rc = HYPERVISOR_memory_op(XENMEM_remove_from_physmap, &xrp);
+                if (rc) {
+                        pr_warn("Failed to unmap pfn:%lx rc:%ld\n",
+                                pfn, rc);
+                        return rc;
+                }
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
 /*
 * see Documentation/devicetree/bindings/arm/xen.txt for the
 * documentation of the Xen Device Tree format.
@@ -149,24 +248,6 @@ static int __init xen_init_events(void)
 }
 postcore_initcall(xen_init_events);
-/* XXX: only until balloon is properly working */
-int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem)
-{
-        *pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL,
-                        get_order(nr_pages));
-        if (*pages == NULL)
-                return -ENOMEM;
-        return 0;
-}
-EXPORT_SYMBOL_GPL(alloc_xenballooned_pages);
-void free_xenballooned_pages(int nr_pages, struct page **pages)
-{
-        kfree(*pages);
-        *pages = NULL;
-}
-EXPORT_SYMBOL_GPL(free_xenballooned_pages);
 /* In the hypervisor.S file. */
 EXPORT_SYMBOL_GPL(HYPERVISOR_event_channel_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_grant_table_op);