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-rw-r--r--arch/arm/Kconfig205
-rw-r--r--arch/arm/Makefile10
-rw-r--r--arch/arm/boot/Makefile8
-rw-r--r--arch/arm/boot/compressed/Makefile15
-rw-r--r--arch/arm/boot/compressed/Makefile.debug23
-rw-r--r--arch/arm/boot/compressed/head-l7200.S29
-rw-r--r--arch/arm/boot/compressed/head.S40
-rw-r--r--arch/arm/boot/compressed/misc.c20
-rw-r--r--arch/arm/common/gic.c46
-rw-r--r--arch/arm/common/sa1111.c5
-rw-r--r--arch/arm/configs/kirkwood_defconfig8
-rw-r--r--arch/arm/configs/lusl7200_defconfig23
-rw-r--r--arch/arm/include/asm/elf.h4
-rw-r--r--arch/arm/include/asm/hwcap.h1
-rw-r--r--arch/arm/include/asm/irq.h2
-rw-r--r--arch/arm/include/asm/kexec.h22
-rw-r--r--arch/arm/include/asm/mach/arch.h2
-rw-r--r--arch/arm/include/asm/mach/irq.h1
-rw-r--r--arch/arm/include/asm/mach/map.h2
-rw-r--r--arch/arm/include/asm/mach/pci.h1
-rw-r--r--arch/arm/include/asm/memblock.h16
-rw-r--r--arch/arm/include/asm/memory.h76
-rw-r--r--arch/arm/include/asm/mmzone.h30
-rw-r--r--arch/arm/include/asm/ptrace.h36
-rw-r--r--arch/arm/include/asm/setup.h8
-rw-r--r--arch/arm/include/asm/stackprotector.h38
-rw-r--r--arch/arm/include/asm/system.h2
-rw-r--r--arch/arm/include/asm/tls.h46
-rw-r--r--arch/arm/include/asm/vfpmacros.h18
-rw-r--r--arch/arm/kernel/Makefile5
-rw-r--r--arch/arm/kernel/asm-offsets.c3
-rw-r--r--arch/arm/kernel/compat.c7
-rw-r--r--arch/arm/kernel/compat.h2
-rw-r--r--arch/arm/kernel/crash_dump.c60
-rw-r--r--arch/arm/kernel/entry-armv.S29
-rw-r--r--arch/arm/kernel/irq.c41
-rw-r--r--arch/arm/kernel/machine_kexec.c14
-rw-r--r--arch/arm/kernel/process.c42
-rw-r--r--arch/arm/kernel/ptrace.c96
-rw-r--r--arch/arm/kernel/relocate_kernel.S6
-rw-r--r--arch/arm/kernel/setup.c111
-rw-r--r--arch/arm/kernel/smp.c17
-rw-r--r--arch/arm/kernel/smp_twd.c3
-rw-r--r--arch/arm/kernel/tcm.c118
-rw-r--r--arch/arm/kernel/traps.c41
-rw-r--r--arch/arm/lib/Makefile1
-rw-r--r--arch/arm/mach-aaec2000/include/mach/memory.h10
-rw-r--r--arch/arm/mach-at91/Kconfig11
-rw-r--r--arch/arm/mach-at91/Makefile3
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c11
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c45
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek.c45
-rw-r--r--arch/arm/mach-at91/board-snapper9260.c189
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h22
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h130
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h2
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h10
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-at91/pm.h49
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S74
-rw-r--r--arch/arm/mach-bcmring/core.c23
-rw-r--r--arch/arm/mach-clps711x/Kconfig1
-rw-r--r--arch/arm/mach-clps711x/clep7312.c1
-rw-r--r--arch/arm/mach-clps711x/edb7211-arch.c10
-rw-r--r--arch/arm/mach-clps711x/fortunet.c1
-rw-r--r--arch/arm/mach-clps711x/include/mach/memory.h2
-rw-r--r--arch/arm/mach-cns3xxx/Makefile3
-rw-r--r--arch/arm/mach-cns3xxx/cns3420vb.c4
-rw-r--r--arch/arm/mach-cns3xxx/devices.c111
-rw-r--r--arch/arm/mach-cns3xxx/devices.h20
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/cns3xxx.h91
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c389
-rw-r--r--arch/arm/mach-cns3xxx/pm.c31
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h9
-rw-r--r--arch/arm/mach-dove/common.c61
-rw-r--r--arch/arm/mach-dove/common.h2
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c2
-rw-r--r--arch/arm/mach-ep93xx/adssphere.c24
-rw-r--r--arch/arm/mach-ep93xx/clock.c2
-rw-r--r--arch/arm/mach-ep93xx/core.c46
-rw-r--r--arch/arm/mach-ep93xx/edb93xx.c31
-rw-r--r--arch/arm/mach-ep93xx/gesbc9312.c24
-rw-r--r--arch/arm/mach-ep93xx/include/mach/platform.h3
-rw-r--r--arch/arm/mach-ep93xx/micro9.c37
-rw-r--r--arch/arm/mach-ep93xx/simone.c24
-rw-r--r--arch/arm/mach-ep93xx/ts72xx.c27
-rw-r--r--arch/arm/mach-imx/Kconfig (renamed from arch/arm/mach-mx2/Kconfig)101
-rw-r--r--arch/arm/mach-imx/Makefile (renamed from arch/arm/mach-mx2/Makefile)18
-rw-r--r--arch/arm/mach-imx/Makefile.boot (renamed from arch/arm/mach-mx2/Makefile.boot)4
-rw-r--r--arch/arm/mach-imx/clock-imx1.c (renamed from arch/arm/mach-mx1/clock.c)50
-rw-r--r--arch/arm/mach-imx/clock-imx21.c (renamed from arch/arm/mach-mx2/clock_imx21.c)0
-rw-r--r--arch/arm/mach-imx/clock-imx27.c (renamed from arch/arm/mach-mx2/clock_imx27.c)2
-rw-r--r--arch/arm/mach-imx/cpu-imx27.c (renamed from arch/arm/mach-mx2/cpu_imx27.c)0
-rw-r--r--arch/arm/mach-imx/devices-imx1.h18
-rw-r--r--arch/arm/mach-imx/devices-imx21.h30
-rw-r--r--arch/arm/mach-imx/devices-imx27.h38
-rw-r--r--arch/arm/mach-imx/devices.c (renamed from arch/arm/mach-mx2/devices.c)296
-rw-r--r--arch/arm/mach-imx/devices.h (renamed from arch/arm/mach-mx2/devices.h)32
-rw-r--r--arch/arm/mach-imx/dma-v1.c (renamed from arch/arm/plat-mxc/dma-mx1-mx2.c)4
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c (renamed from arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c)197
-rw-r--r--arch/arm/mach-imx/include/mach/dma-mx1-mx2.h10
-rw-r--r--arch/arm/mach-imx/include/mach/dma-v1.h (renamed from arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h)10
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c (renamed from arch/arm/mach-mx2/mach-cpuimx27.c)122
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c (renamed from arch/arm/mach-mx2/mach-imx27lite.c)11
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c (renamed from arch/arm/mach-mx1/mach-mx1ads.c)34
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c (renamed from arch/arm/mach-mx2/mach-mx21ads.c)58
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c (renamed from arch/arm/mach-mx2/mach-mx27_3ds.c)40
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c (renamed from arch/arm/mach-mx2/mach-mx27ads.c)76
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c (renamed from arch/arm/mach-mx2/mach-mxt_td60.c)36
-rw-r--r--arch/arm/mach-imx/mach-pca100.c (renamed from arch/arm/mach-mx2/mach-pca100.c)114
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c (renamed from arch/arm/mach-mx2/mach-pcm038.c)33
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c (renamed from arch/arm/mach-mx1/mach-scb9328.c)21
-rw-r--r--arch/arm/mach-imx/mm-imx1.c (renamed from arch/arm/mach-mx1/generic.c)23
-rw-r--r--arch/arm/mach-imx/mm-imx21.c (renamed from arch/arm/mach-mx2/mm-imx21.c)5
-rw-r--r--arch/arm/mach-imx/mm-imx27.c (renamed from arch/arm/mach-mx2/mm-imx27.c)5
-rw-r--r--arch/arm/mach-imx/mx1-camera-fiq-ksym.c (renamed from arch/arm/mach-mx1/ksym_mx1.c)0
-rw-r--r--arch/arm/mach-imx/mx1-camera-fiq.S (renamed from arch/arm/mach-mx1/mx1_camera_fiq.S)0
-rw-r--r--arch/arm/mach-imx/pcm970-baseboard.c (renamed from arch/arm/mach-mx2/pcm970-baseboard.c)0
-rw-r--r--arch/arm/mach-imx/pm-imx27.c46
-rw-r--r--arch/arm/mach-integrator/common.h1
-rw-r--r--arch/arm/mach-integrator/core.c19
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c3
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c3
-rw-r--r--arch/arm/mach-integrator/pci_v3.c8
-rw-r--r--arch/arm/mach-iop13xx/include/mach/memory.h2
-rw-r--r--arch/arm/mach-iop13xx/pci.c2
-rw-r--r--arch/arm/mach-ixp2000/pci.c2
-rw-r--r--arch/arm/mach-ixp23xx/pci.c2
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c7
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/memory.h6
-rw-r--r--arch/arm/mach-kirkwood/Kconfig19
-rw-r--r--arch/arm/mach-kirkwood/Makefile2
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c10
-rw-r--r--arch/arm/mach-kirkwood/common.c38
-rw-r--r--arch/arm/mach-kirkwood/common.h5
-rw-r--r--arch/arm/mach-kirkwood/db88f6281-bp-setup.c18
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h3
-rw-r--r--arch/arm/mach-kirkwood/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h39
-rw-r--r--arch/arm/mach-kirkwood/include/mach/leds-ns2.h26
-rw-r--r--arch/arm/mach-kirkwood/mpp.c3
-rw-r--r--arch/arm/mach-kirkwood/mpp.h596
-rw-r--r--arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/netspace_v2-setup.c104
-rw-r--r--arch/arm/mach-kirkwood/netxbig_v2-setup.c32
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c29
-rw-r--r--arch/arm/mach-kirkwood/pcie.c174
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c194
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c11
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c39
-rw-r--r--arch/arm/mach-ks8695/pci.c4
-rw-r--r--arch/arm/mach-l7200/Makefile11
-rw-r--r--arch/arm/mach-l7200/Makefile.boot2
-rw-r--r--arch/arm/mach-l7200/core.c100
-rw-r--r--arch/arm/mach-l7200/include/mach/aux_reg.h28
-rw-r--r--arch/arm/mach-l7200/include/mach/debug-macro.S40
-rw-r--r--arch/arm/mach-l7200/include/mach/entry-macro.S35
-rw-r--r--arch/arm/mach-l7200/include/mach/gp_timers.h42
-rw-r--r--arch/arm/mach-l7200/include/mach/gpio.h105
-rw-r--r--arch/arm/mach-l7200/include/mach/hardware.h57
-rw-r--r--arch/arm/mach-l7200/include/mach/io.h21
-rw-r--r--arch/arm/mach-l7200/include/mach/irqs.h56
-rw-r--r--arch/arm/mach-l7200/include/mach/memory.h26
-rw-r--r--arch/arm/mach-l7200/include/mach/pmpcon.h46
-rw-r--r--arch/arm/mach-l7200/include/mach/pmu.h125
-rw-r--r--arch/arm/mach-l7200/include/mach/serial.h37
-rw-r--r--arch/arm/mach-l7200/include/mach/serial_l7200.h101
-rw-r--r--arch/arm/mach-l7200/include/mach/sib.h119
-rw-r--r--arch/arm/mach-l7200/include/mach/sys-clock.h67
-rw-r--r--arch/arm/mach-l7200/include/mach/system.h29
-rw-r--r--arch/arm/mach-l7200/include/mach/time.h73
-rw-r--r--arch/arm/mach-l7200/include/mach/timex.h20
-rw-r--r--arch/arm/mach-l7200/include/mach/uncompress.h39
-rw-r--r--arch/arm/mach-l7200/include/mach/vmalloc.h4
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/memory.h44
-rw-r--r--arch/arm/mach-lpc32xx/Kconfig33
-rw-r--r--arch/arm/mach-lpc32xx/Makefile8
-rw-r--r--arch/arm/mach-lpc32xx/Makefile.boot4
-rw-r--r--arch/arm/mach-lpc32xx/clock.c1137
-rw-r--r--arch/arm/mach-lpc32xx/clock.h38
-rw-r--r--arch/arm/mach-lpc32xx/common.c271
-rw-r--r--arch/arm/mach-lpc32xx/common.h73
-rw-r--r--arch/arm/mach-lpc32xx/gpiolib.c446
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/clkdev.h (renamed from arch/arm/plat-mxc/include/mach/board-pcm043.h)19
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/debug-macro.S (renamed from arch/arm/plat-mxc/include/mach/board-mx35pdk.h)25
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/entry-macro.S47
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/gpio.h74
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/hardware.h34
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/i2c.h63
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/io.h (renamed from arch/arm/plat-mxc/include/mach/board-pcm037.h)21
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/irqs.h117
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/memory.h27
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/platform.h694
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/system.h52
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/timex.h28
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/uncompress.h60
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/vmalloc.h24
-rw-r--r--arch/arm/mach-lpc32xx/irq.c432
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c397
-rw-r--r--arch/arm/mach-lpc32xx/pm.c146
-rw-r--r--arch/arm/mach-lpc32xx/serial.c190
-rw-r--r--arch/arm/mach-lpc32xx/suspend.S151
-rw-r--r--arch/arm/mach-lpc32xx/timer.c182
-rw-r--r--arch/arm/mach-msm/Makefile2
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c112
-rw-r--r--arch/arm/mach-msm/board-trout.c1
-rw-r--r--arch/arm/mach-msm/board-trout.h157
-rw-r--r--arch/arm/mach-msm/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-mx1/Kconfig19
-rw-r--r--arch/arm/mach-mx1/Makefile15
-rw-r--r--arch/arm/mach-mx1/Makefile.boot4
-rw-r--r--arch/arm/mach-mx1/crm_regs.h55
-rw-r--r--arch/arm/mach-mx1/devices.c242
-rw-r--r--arch/arm/mach-mx1/devices.h7
-rw-r--r--arch/arm/mach-mx2/serial.c141
-rw-r--r--arch/arm/mach-mx25/Kconfig23
-rw-r--r--arch/arm/mach-mx25/Makefile4
-rw-r--r--arch/arm/mach-mx25/clock.c70
-rw-r--r--arch/arm/mach-mx25/devices-imx25.h43
-rw-r--r--arch/arm/mach-mx25/devices.c313
-rw-r--r--arch/arm/mach-mx25/devices.h16
-rw-r--r--arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c260
-rw-r--r--arch/arm/mach-mx25/mach-cpuimx25.c173
-rw-r--r--arch/arm/mach-mx25/mach-mx25_3ds.c (renamed from arch/arm/mach-mx25/mach-mx25pdk.c)58
-rw-r--r--arch/arm/mach-mx25/mm.c7
-rw-r--r--arch/arm/mach-mx3/Kconfig53
-rw-r--r--arch/arm/mach-mx3/Makefile4
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c6
-rw-r--r--arch/arm/mach-mx3/devices-imx31.h38
-rw-r--r--arch/arm/mach-mx3/devices-imx35.h37
-rw-r--r--arch/arm/mach-mx3/devices.c247
-rw-r--r--arch/arm/mach-mx3/devices.h13
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c263
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c17
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c227
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c31
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c256
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c55
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c15
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c17
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c50
-rw-r--r--arch/arm/mach-mx3/mach-mx35_3ds.c (renamed from arch/arm/mach-mx3/mach-mx35pdk.c)16
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c34
-rw-r--r--arch/arm/mach-mx3/mach-pcm037_eet.c7
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c31
-rw-r--r--arch/arm/mach-mx3/mach-qong.c16
-rw-r--r--arch/arm/mach-mx3/mm.c7
-rw-r--r--arch/arm/mach-mx3/mx31lilly-db.c14
-rw-r--r--arch/arm/mach-mx3/mx31lite-db.c15
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c10
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c4
-rw-r--r--arch/arm/mach-mx3/mx31moboard-smartbot.c11
-rw-r--r--arch/arm/mach-mx5/Kconfig27
-rw-r--r--arch/arm/mach-mx5/Makefile4
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c293
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c164
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c28
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c16
-rw-r--r--arch/arm/mach-mx5/devices.c83
-rw-r--r--arch/arm/mach-mx5/devices.h4
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c200
-rw-r--r--arch/arm/mach-mx5/mm.c3
-rw-r--r--arch/arm/mach-mxc91231/crm_regs.h5
-rw-r--r--arch/arm/mach-mxc91231/devices.c2
-rw-r--r--arch/arm/mach-mxc91231/mm.c8
-rw-r--r--arch/arm/mach-nomadik/clock.c4
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c1
-rw-r--r--arch/arm/mach-omap1/board-fsample.c1
-rw-r--r--arch/arm/mach-omap1/board-generic.c1
-rw-r--r--arch/arm/mach-omap1/board-h2.c1
-rw-r--r--arch/arm/mach-omap1/board-h3.c1
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c1
-rw-r--r--arch/arm/mach-omap1/board-innovator.c1
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c1
-rw-r--r--arch/arm/mach-omap1/board-osk.c1
-rw-r--r--arch/arm/mach-omap1/board-palmte.c1
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c1
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c14
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c1
-rw-r--r--arch/arm/mach-omap1/board-sx1.c3
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c1
-rw-r--r--arch/arm/mach-omap1/io.c2
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c1
-rw-r--r--arch/arm/mach-omap2/board-apollon.c1
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c1
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c1
-rw-r--r--arch/arm/mach-omap2/board-generic.c1
-rw-r--r--arch/arm/mach-omap2/board-h4.c1
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c1
-rw-r--r--arch/arm/mach-omap2/board-ldp.c1
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c3
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c1
-rw-r--r--arch/arm/mach-omap2/board-overo.c1
-rw-r--r--arch/arm/mach-omap2/board-rx51.c1
-rw-r--r--arch/arm/mach-omap2/board-zoom2.c1
-rw-r--r--arch/arm/mach-omap2/board-zoom3.c1
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c5
-rw-r--r--arch/arm/mach-omap2/io.c3
-rw-r--r--arch/arm/mach-orion5x/Kconfig1
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c370
-rw-r--r--arch/arm/mach-orion5x/include/mach/system.h2
-rw-r--r--arch/arm/mach-pxa/cm-x2xx-pci.c4
-rw-r--r--arch/arm/mach-pxa/corgi.c1
-rw-r--r--arch/arm/mach-pxa/eseries.c1
-rw-r--r--arch/arm/mach-pxa/generic.h3
-rw-r--r--arch/arm/mach-pxa/include/mach/memory.h19
-rw-r--r--arch/arm/mach-pxa/palmt5.c7
-rw-r--r--arch/arm/mach-pxa/palmtreo.c9
-rw-r--r--arch/arm/mach-pxa/poodle.c1
-rw-r--r--arch/arm/mach-pxa/spitz.c1
-rw-r--r--arch/arm/mach-pxa/tosa.c1
-rw-r--r--arch/arm/mach-realview/core.c40
-rw-r--r--arch/arm/mach-realview/include/mach/board-pb1176.h1
-rw-r--r--arch/arm/mach-realview/include/mach/irqs-pb1176.h2
-rw-r--r--arch/arm/mach-realview/include/mach/memory.h7
-rw-r--r--arch/arm/mach-realview/realview_eb.c30
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c46
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c9
-rw-r--r--arch/arm/mach-realview/realview_pba8.c9
-rw-r--r--arch/arm/mach-realview/realview_pbx.c9
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c9
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c1
-rw-r--r--arch/arm/mach-s3c2412/mach-vstms.c1
-rw-r--r--arch/arm/mach-s3c2440/mach-rx1950.c9
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c9
-rw-r--r--arch/arm/mach-sa1100/generic.h3
-rw-r--r--arch/arm/mach-sa1100/include/mach/memory.h6
-rw-r--r--arch/arm/mach-shark/include/mach/memory.h7
-rw-r--r--arch/arm/mach-shmobile/Kconfig12
-rw-r--r--arch/arm/mach-shmobile/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-spear3xx/clock.c3
-rw-r--r--arch/arm/mach-spear6xx/clock.c3
-rw-r--r--arch/arm/mach-u300/clock.c6
-rw-r--r--arch/arm/mach-u300/include/mach/memory.h8
-rw-r--r--arch/arm/mach-u300/u300.c17
-rw-r--r--arch/arm/mach-ux500/board-mop500.c36
-rw-r--r--arch/arm/mach-ux500/clock.c4
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c14
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-mop500.h23
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h85
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db8500.h96
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h22
-rw-r--r--arch/arm/mach-ux500/pins-db8500.h742
-rw-r--r--arch/arm/mach-versatile/core.c35
-rw-r--r--arch/arm/mach-versatile/pci.c2
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c2
-rw-r--r--arch/arm/mach-vexpress/include/mach/ct-ca9x4.h1
-rw-r--r--arch/arm/mach-vexpress/v2m.c7
-rw-r--r--arch/arm/mach-w90x900/dev.c96
-rw-r--r--arch/arm/mach-w90x900/include/mach/regs-gcr.h39
-rw-r--r--arch/arm/mach-w90x900/mach-nuc950evb.c44
-rw-r--r--arch/arm/mach-w90x900/nuc910.c2
-rw-r--r--arch/arm/mach-w90x900/nuc950.c2
-rw-r--r--arch/arm/mm/Kconfig11
-rw-r--r--arch/arm/mm/Makefile1
-rw-r--r--arch/arm/mm/alignment.c16
-rw-r--r--arch/arm/mm/discontig.c45
-rw-r--r--arch/arm/mm/dma-mapping.c15
-rw-r--r--arch/arm/mm/fault.c56
-rw-r--r--arch/arm/mm/init.c424
-rw-r--r--arch/arm/mm/ioremap.c80
-rw-r--r--arch/arm/mm/mm.h4
-rw-r--r--arch/arm/mm/mmap.c4
-rw-r--r--arch/arm/mm/mmu.c174
-rw-r--r--arch/arm/mm/nommu.c22
-rw-r--r--arch/arm/mm/proc-arm1020.S6
-rw-r--r--arch/arm/mm/proc-arm1020e.S6
-rw-r--r--arch/arm/mm/proc-arm1022.S6
-rw-r--r--arch/arm/mm/proc-arm1026.S6
-rw-r--r--arch/arm/mm/proc-arm6_7.S2
-rw-r--r--arch/arm/mm/proc-arm720.S6
-rw-r--r--arch/arm/mm/proc-arm740.S6
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S2
-rw-r--r--arch/arm/mm/proc-arm920.S10
-rw-r--r--arch/arm/mm/proc-arm922.S10
-rw-r--r--arch/arm/mm/proc-arm925.S6
-rw-r--r--arch/arm/mm/proc-arm926.S6
-rw-r--r--arch/arm/mm/proc-arm940.S6
-rw-r--r--arch/arm/mm/proc-arm946.S6
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S2
-rw-r--r--arch/arm/mm/proc-fa526.S6
-rw-r--r--arch/arm/mm/proc-feroceon.S7
-rw-r--r--arch/arm/mm/proc-mohawk.S6
-rw-r--r--arch/arm/mm/proc-sa110.S8
-rw-r--r--arch/arm/mm/proc-sa1100.S6
-rw-r--r--arch/arm/mm/proc-v6.S10
-rw-r--r--arch/arm/mm/proc-v7.S7
-rw-r--r--arch/arm/mm/proc-xsc3.S6
-rw-r--r--arch/arm/mm/proc-xscale.S6
-rw-r--r--arch/arm/mm/vmregion.c5
-rw-r--r--arch/arm/mm/vmregion.h2
-rw-r--r--arch/arm/plat-iop/pci.c2
-rw-r--r--arch/arm/plat-iop/time.c53
-rw-r--r--arch/arm/plat-mxc/3ds_debugboard.c202
-rw-r--r--arch/arm/plat-mxc/Kconfig22
-rw-r--r--arch/arm/plat-mxc/Makefile5
-rw-r--r--arch/arm/plat-mxc/audmux-v1.c4
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c19
-rw-r--r--arch/arm/plat-mxc/clock.c37
-rw-r--r--arch/arm/plat-mxc/devices.c33
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig15
-rw-r--r--arch/arm/plat-mxc/devices/Makefile8
-rw-r--r--arch/arm/plat-mxc/devices/platform-flexcan.c30
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c29
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-uart.c60
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_nand.c44
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c30
-rw-r--r--arch/arm/plat-mxc/ehci.c50
-rw-r--r--arch/arm/plat-mxc/gpio.c14
-rw-r--r--arch/arm/plat-mxc/include/mach/3ds_debugboard.h18
-rw-r--r--arch/arm/plat-mxc/include/mach/board-armadillo5x0.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/board-kzmarm11.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx21ads.h52
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h344
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27lite.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27pdk.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31_3ds.h59
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h117
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lilly.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm038.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-qong.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S4
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h60
-rw-r--r--arch/arm/plat-mxc/include/mach/eukrea-baseboards.h (renamed from arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h)19
-rw-r--r--arch/arm/plat-mxc/include/mach/gpio.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h559
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mmc.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h50
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2_cam.h46
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3_camera.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_nand.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/vmalloc.h4
-rw-r--r--arch/arm/plat-mxc/irq.c3
-rw-r--r--arch/arm/plat-mxc/system.c4
-rw-r--r--arch/arm/plat-mxc/tzic.c2
-rw-r--r--arch/arm/plat-nomadik/gpio.c316
-rw-r--r--arch/arm/plat-nomadik/include/plat/gpio.h15
-rw-r--r--arch/arm/plat-nomadik/include/plat/mtu.h6
-rw-r--r--arch/arm/plat-nomadik/include/plat/pincfg.h72
-rw-r--r--arch/arm/plat-nomadik/timer.c14
-rw-r--r--arch/arm/plat-omap/common.c8
-rw-r--r--arch/arm/plat-omap/fb.c77
-rw-r--r--arch/arm/plat-omap/include/plat/common.h2
-rw-r--r--arch/arm/plat-omap/include/plat/vram.h4
-rw-r--r--arch/arm/plat-orion/pcie.c34
-rw-r--r--arch/arm/plat-spear/time.c47
-rw-r--r--arch/arm/plat-versatile/Makefile4
-rw-r--r--arch/arm/plat-versatile/leds.c103
-rw-r--r--arch/arm/vfp/vfpmodule.c10
477 files changed, 15546 insertions, 6260 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 98922f7d2d12..e39caa8b0c93 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,7 @@ config ARM
10 default y 10 default y
11 select HAVE_AOUT 11 select HAVE_AOUT
12 select HAVE_IDE 12 select HAVE_IDE
13 select HAVE_MEMBLOCK
13 select RTC_LIB 14 select RTC_LIB
14 select SYS_SUPPORTS_APM_EMULATION 15 select SYS_SUPPORTS_APM_EMULATION
15 select GENERIC_ATOMIC64 if (!CPU_32v6K) 16 select GENERIC_ATOMIC64 if (!CPU_32v6K)
@@ -24,6 +25,7 @@ config ARM
24 select HAVE_KERNEL_LZMA 25 select HAVE_KERNEL_LZMA
25 select HAVE_PERF_EVENTS 26 select HAVE_PERF_EVENTS
26 select PERF_USE_VMALLOC 27 select PERF_USE_VMALLOC
28 select HAVE_REGS_AND_STACK_ACCESS_API
27 help 29 help
28 The ARM series is a line of low-power-consumption RISC chip designs 30 The ARM series is a line of low-power-consumption RISC chip designs
29 licensed by ARM Ltd and targeted at embedded applications and 31 licensed by ARM Ltd and targeted at embedded applications and
@@ -55,7 +57,7 @@ config GENERIC_CLOCKEVENTS
55config GENERIC_CLOCKEVENTS_BROADCAST 57config GENERIC_CLOCKEVENTS_BROADCAST
56 bool 58 bool
57 depends on GENERIC_CLOCKEVENTS 59 depends on GENERIC_CLOCKEVENTS
58 default y if SMP && !LOCAL_TIMERS 60 default y if SMP
59 61
60config HAVE_TCM 62config HAVE_TCM
61 bool 63 bool
@@ -301,6 +303,7 @@ config ARCH_CNS3XXX
301 select CPU_V6 303 select CPU_V6
302 select GENERIC_CLOCKEVENTS 304 select GENERIC_CLOCKEVENTS
303 select ARM_GIC 305 select ARM_GIC
306 select PCI_DOMAINS if PCI
304 help 307 help
305 Support for Cavium Networks CNS3XXX platform. 308 Support for Cavium Networks CNS3XXX platform.
306 309
@@ -439,21 +442,6 @@ config ARCH_IXP4XX
439 help 442 help
440 Support for Intel's IXP4XX (XScale) family of processors. 443 Support for Intel's IXP4XX (XScale) family of processors.
441 444
442config ARCH_L7200
443 bool "LinkUp-L7200"
444 select CPU_ARM720T
445 select FIQ
446 select ARCH_USES_GETTIMEOFFSET
447 help
448 Say Y here if you intend to run this kernel on a LinkUp Systems
449 L7200 Software Development Board which uses an ARM720T processor.
450 Information on this board can be obtained at:
451
452 <http://www.linkupsys.com/>
453
454 If you have any questions or comments about the Linux kernel port
455 to this board, send e-mail to <sjhill@cotw.com>.
456
457config ARCH_DOVE 445config ARCH_DOVE
458 bool "Marvell Dove" 446 bool "Marvell Dove"
459 select PCI 447 select PCI
@@ -482,6 +470,19 @@ config ARCH_LOKI
482 help 470 help
483 Support for the Marvell Loki (88RC8480) SoC. 471 Support for the Marvell Loki (88RC8480) SoC.
484 472
473config ARCH_LPC32XX
474 bool "NXP LPC32XX"
475 select CPU_ARM926T
476 select ARCH_REQUIRE_GPIOLIB
477 select HAVE_IDE
478 select ARM_AMBA
479 select USB_ARCH_HAS_OHCI
480 select COMMON_CLKDEV
481 select GENERIC_TIME
482 select GENERIC_CLOCKEVENTS
483 help
484 Support for the NXP LPC32XX family of processors
485
485config ARCH_MV78XX0 486config ARCH_MV78XX0
486 bool "Marvell MV78xx0" 487 bool "Marvell MV78xx0"
487 select CPU_FEROCEON 488 select CPU_FEROCEON
@@ -586,6 +587,7 @@ config ARCH_MSM
586 bool "Qualcomm MSM" 587 bool "Qualcomm MSM"
587 select HAVE_CLK 588 select HAVE_CLK
588 select GENERIC_CLOCKEVENTS 589 select GENERIC_CLOCKEVENTS
590 select ARCH_REQUIRE_GPIOLIB
589 help 591 help
590 Support for Qualcomm MSM/QSD based systems. This runs on the 592 Support for Qualcomm MSM/QSD based systems. This runs on the
591 apps processor of the MSM/QSD and depends on a shared memory 593 apps processor of the MSM/QSD and depends on a shared memory
@@ -719,7 +721,6 @@ config ARCH_SHARK
719config ARCH_LH7A40X 721config ARCH_LH7A40X
720 bool "Sharp LH7A40X" 722 bool "Sharp LH7A40X"
721 select CPU_ARM922T 723 select CPU_ARM922T
722 select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
723 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM 724 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
724 select ARCH_USES_GETTIMEOFFSET 725 select ARCH_USES_GETTIMEOFFSET
725 help 726 help
@@ -845,6 +846,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
845 846
846source "arch/arm/mach-loki/Kconfig" 847source "arch/arm/mach-loki/Kconfig"
847 848
849source "arch/arm/mach-lpc32xx/Kconfig"
850
848source "arch/arm/mach-msm/Kconfig" 851source "arch/arm/mach-msm/Kconfig"
849 852
850source "arch/arm/mach-mv78xx0/Kconfig" 853source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1031,11 +1034,6 @@ endmenu
1031 1034
1032source "arch/arm/common/Kconfig" 1035source "arch/arm/common/Kconfig"
1033 1036
1034config FORCE_MAX_ZONEORDER
1035 int
1036 depends on SA1111
1037 default "9"
1038
1039menu "Bus support" 1037menu "Bus support"
1040 1038
1041config ARM_AMBA 1039config ARM_AMBA
@@ -1060,7 +1058,7 @@ config ISA_DMA_API
1060 bool 1058 bool
1061 1059
1062config PCI 1060config PCI
1063 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE 1061 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
1064 help 1062 help
1065 Find out whether you have a PCI motherboard. PCI is the name of a 1063 Find out whether you have a PCI motherboard. PCI is the name of a
1066 bus system, i.e. the way the CPU talks to the other stuff inside 1064 bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1172,9 +1170,10 @@ config HOTPLUG_CPU
1172config LOCAL_TIMERS 1170config LOCAL_TIMERS
1173 bool "Use local timer interrupts" 1171 bool "Use local timer interrupts"
1174 depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \ 1172 depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
1175 REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500) 1173 REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1174 ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
1176 default y 1175 default y
1177 select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500) 1176 select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
1178 help 1177 help
1179 Enable support for local timers on SMP platforms, rather then the 1178 Enable support for local timers on SMP platforms, rather then the
1180 legacy IPI broadcast method. Local timers allows the system 1179 legacy IPI broadcast method. Local timers allows the system
@@ -1185,10 +1184,10 @@ source kernel/Kconfig.preempt
1185 1184
1186config HZ 1185config HZ
1187 int 1186 int
1188 default 128 if ARCH_L7200
1189 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210 1187 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
1190 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1188 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1191 default AT91_TIMER_HZ if ARCH_AT91 1189 default AT91_TIMER_HZ if ARCH_AT91
1190 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1192 default 100 1191 default 100
1193 1192
1194config THUMB2_KERNEL 1193config THUMB2_KERNEL
@@ -1241,10 +1240,6 @@ config OABI_COMPAT
1241config ARCH_HAS_HOLES_MEMORYMODEL 1240config ARCH_HAS_HOLES_MEMORYMODEL
1242 bool 1241 bool
1243 1242
1244# Discontigmem is deprecated
1245config ARCH_DISCONTIGMEM_ENABLE
1246 bool
1247
1248config ARCH_SPARSEMEM_ENABLE 1243config ARCH_SPARSEMEM_ENABLE
1249 bool 1244 bool
1250 1245
@@ -1252,13 +1247,7 @@ config ARCH_SPARSEMEM_DEFAULT
1252 def_bool ARCH_SPARSEMEM_ENABLE 1247 def_bool ARCH_SPARSEMEM_ENABLE
1253 1248
1254config ARCH_SELECT_MEMORY_MODEL 1249config ARCH_SELECT_MEMORY_MODEL
1255 def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE 1250 def_bool ARCH_SPARSEMEM_ENABLE
1256
1257config NODES_SHIFT
1258 int
1259 default "4" if ARCH_LH7A40X
1260 default "2"
1261 depends on NEED_MULTIPLE_NODES
1262 1251
1263config HIGHMEM 1252config HIGHMEM
1264 bool "High Memory Support (EXPERIMENTAL)" 1253 bool "High Memory Support (EXPERIMENTAL)"
@@ -1290,8 +1279,33 @@ config HW_PERF_EVENTS
1290 Enable hardware performance counter support for perf events. If 1279 Enable hardware performance counter support for perf events. If
1291 disabled, perf events will use software events only. 1280 disabled, perf events will use software events only.
1292 1281
1282config SPARSE_IRQ
1283 def_bool n
1284 help
1285 This enables support for sparse irqs. This is useful in general
1286 as most CPUs have a fairly sparse array of IRQ vectors, which
1287 the irq_desc then maps directly on to. Systems with a high
1288 number of off-chip IRQs will want to treat this as
1289 experimental until they have been independently verified.
1290
1293source "mm/Kconfig" 1291source "mm/Kconfig"
1294 1292
1293config FORCE_MAX_ZONEORDER
1294 int "Maximum zone order" if ARCH_SHMOBILE
1295 range 11 64 if ARCH_SHMOBILE
1296 default "9" if SA1111
1297 default "11"
1298 help
1299 The kernel memory allocator divides physically contiguous memory
1300 blocks into "zones", where each zone is a power of two number of
1301 pages. This option selects the largest power of two that the kernel
1302 keeps in the memory allocator. If you need to allocate very large
1303 blocks of physically contiguous memory, then you may need to
1304 increase this value.
1305
1306 This config option is actually maximum order plus one. For example,
1307 a value of 11 means that the largest free memory block is 2^10 pages.
1308
1295config LEDS 1309config LEDS
1296 bool "Timer and CPU usage LEDs" 1310 bool "Timer and CPU usage LEDs"
1297 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1311 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
@@ -1375,6 +1389,24 @@ config UACCESS_WITH_MEMCPY
1375 However, if the CPU data cache is using a write-allocate mode, 1389 However, if the CPU data cache is using a write-allocate mode,
1376 this option is unlikely to provide any performance gain. 1390 this option is unlikely to provide any performance gain.
1377 1391
1392config CC_STACKPROTECTOR
1393 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1394 help
1395 This option turns on the -fstack-protector GCC feature. This
1396 feature puts, at the beginning of functions, a canary value on
1397 the stack just before the return address, and validates
1398 the value just before actually returning. Stack based buffer
1399 overflows (that need to overwrite this return address) now also
1400 overwrite the canary, which gets detected and the attack is then
1401 neutralized via a kernel panic.
1402 This feature requires gcc version 4.2 or above.
1403
1404config DEPRECATED_PARAM_STRUCT
1405 bool "Provide old way to pass kernel parameters"
1406 help
1407 This was deprecated in 2001 and announced to live on for 5 years.
1408 Some old boot loaders still use this way.
1409
1378endmenu 1410endmenu
1379 1411
1380menu "Boot options" 1412menu "Boot options"
@@ -1485,6 +1517,105 @@ config ATAGS_PROC
1485 Should the atags used to boot the kernel be exported in an "atags" 1517 Should the atags used to boot the kernel be exported in an "atags"
1486 file in procfs. Useful with kexec. 1518 file in procfs. Useful with kexec.
1487 1519
1520config AUTO_ZRELADDR
1521 bool "Auto calculation of the decompressed kernel image address"
1522 depends on !ZBOOT_ROM && !ARCH_U300
1523 help
1524 ZRELADDR is the physical address where the decompressed kernel
1525 image will be placed. If AUTO_ZRELADDR is selected, the address
1526 will be determined at run-time by masking the current IP with
1527 0xf8000000. This assumes the zImage being placed in the first 128MB
1528 from start of memory.
1529
1530config ZRELADDR
1531 hex "Physical address of the decompressed kernel image"
1532 depends on !AUTO_ZRELADDR
1533 default 0x00008000 if ARCH_BCMRING ||\
1534 ARCH_CNS3XXX ||\
1535 ARCH_DOVE ||\
1536 ARCH_EBSA110 ||\
1537 ARCH_FOOTBRIDGE ||\
1538 ARCH_INTEGRATOR ||\
1539 ARCH_IOP13XX ||\
1540 ARCH_IOP33X ||\
1541 ARCH_IXP2000 ||\
1542 ARCH_IXP23XX ||\
1543 ARCH_IXP4XX ||\
1544 ARCH_KIRKWOOD ||\
1545 ARCH_KS8695 ||\
1546 ARCH_LOKI ||\
1547 ARCH_MMP ||\
1548 ARCH_MV78XX0 ||\
1549 ARCH_NOMADIK ||\
1550 ARCH_NUC93X ||\
1551 ARCH_NS9XXX ||\
1552 ARCH_ORION5X ||\
1553 ARCH_SPEAR3XX ||\
1554 ARCH_SPEAR6XX ||\
1555 ARCH_U8500 ||\
1556 ARCH_VERSATILE ||\
1557 ARCH_W90X900
1558 default 0x08008000 if ARCH_MX1 ||\
1559 ARCH_SHARK
1560 default 0x10008000 if ARCH_MSM ||\
1561 ARCH_OMAP1 ||\
1562 ARCH_RPC
1563 default 0x20008000 if ARCH_S5P6440 ||\
1564 ARCH_S5P6442 ||\
1565 ARCH_S5PC100 ||\
1566 ARCH_S5PV210
1567 default 0x30008000 if ARCH_S3C2410 ||\
1568 ARCH_S3C2400 ||\
1569 ARCH_S3C2412 ||\
1570 ARCH_S3C2416 ||\
1571 ARCH_S3C2440 ||\
1572 ARCH_S3C2443
1573 default 0x40008000 if ARCH_STMP378X ||\
1574 ARCH_STMP37XX ||\
1575 ARCH_SH7372 ||\
1576 ARCH_SH7377
1577 default 0x50008000 if ARCH_S3C64XX ||\
1578 ARCH_SH7367
1579 default 0x60008000 if ARCH_VEXPRESS
1580 default 0x80008000 if ARCH_MX25 ||\
1581 ARCH_MX3 ||\
1582 ARCH_NETX ||\
1583 ARCH_OMAP2PLUS ||\
1584 ARCH_PNX4008
1585 default 0x90008000 if ARCH_MX5 ||\
1586 ARCH_MX91231
1587 default 0xa0008000 if ARCH_IOP32X ||\
1588 ARCH_PXA ||\
1589 MACH_MX27
1590 default 0xc0008000 if ARCH_LH7A40X ||\
1591 MACH_MX21
1592 default 0xf0008000 if ARCH_AAEC2000 ||\
1593 ARCH_L7200
1594 default 0xc0028000 if ARCH_CLPS711X
1595 default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
1596 default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
1597 default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
1598 default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
1599 default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
1600 default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
1601 default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
1602 default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
1603 default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
1604 default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
1605 default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
1606 default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
1607 default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
1608 default 0xc0208000 if ARCH_SA1100 && SA1111
1609 default 0xc0008000 if ARCH_SA1100 && !SA1111
1610 default 0x30108000 if ARCH_S3C2410 && PM_H1940
1611 default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
1612 default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
1613 help
1614 ZRELADDR is the physical address where the decompressed kernel
1615 image will be placed. ZRELADDR has to be specified when the
1616 assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
1617 selected.
1618
1488endmenu 1619endmenu
1489 1620
1490menu "CPU Power Management" 1621menu "CPU Power Management"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313724d2..63d998e8c672 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
34KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog 34KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
35endif 35endif
36 36
37ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
38KBUILD_CFLAGS +=-fstack-protector
39endif
40
37ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) 41ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
38KBUILD_CPPFLAGS += -mbig-endian 42KBUILD_CPPFLAGS += -mbig-endian
39AS += -EB 43AS += -EB
@@ -139,14 +143,14 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
139machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 143machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
140machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood 144machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
141machine-$(CONFIG_ARCH_KS8695) := ks8695 145machine-$(CONFIG_ARCH_KS8695) := ks8695
142machine-$(CONFIG_ARCH_L7200) := l7200
143machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x 146machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
144machine-$(CONFIG_ARCH_LOKI) := loki 147machine-$(CONFIG_ARCH_LOKI) := loki
148machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
145machine-$(CONFIG_ARCH_MMP) := mmp 149machine-$(CONFIG_ARCH_MMP) := mmp
146machine-$(CONFIG_ARCH_MSM) := msm 150machine-$(CONFIG_ARCH_MSM) := msm
147machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 151machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
148machine-$(CONFIG_ARCH_MX1) := mx1 152machine-$(CONFIG_ARCH_MX1) := imx
149machine-$(CONFIG_ARCH_MX2) := mx2 153machine-$(CONFIG_ARCH_MX2) := imx
150machine-$(CONFIG_ARCH_MX25) := mx25 154machine-$(CONFIG_ARCH_MX25) := mx25
151machine-$(CONFIG_ARCH_MX3) := mx3 155machine-$(CONFIG_ARCH_MX3) := mx3
152machine-$(CONFIG_ARCH_MX5) := mx5 156machine-$(CONFIG_ARCH_MX5) := mx5
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4113e2..f705213caa88 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -14,18 +14,16 @@
14MKIMAGE := $(srctree)/scripts/mkuboot.sh 14MKIMAGE := $(srctree)/scripts/mkuboot.sh
15 15
16ifneq ($(MACHINE),) 16ifneq ($(MACHINE),)
17include $(srctree)/$(MACHINE)/Makefile.boot 17-include $(srctree)/$(MACHINE)/Makefile.boot
18endif 18endif
19 19
20# Note: the following conditions must always be true: 20# Note: the following conditions must always be true:
21# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
22# PARAMS_PHYS must be within 4MB of ZRELADDR 21# PARAMS_PHYS must be within 4MB of ZRELADDR
23# INITRD_PHYS must be in RAM 22# INITRD_PHYS must be in RAM
24ZRELADDR := $(zreladdr-y)
25PARAMS_PHYS := $(params_phys-y) 23PARAMS_PHYS := $(params_phys-y)
26INITRD_PHYS := $(initrd_phys-y) 24INITRD_PHYS := $(initrd_phys-y)
27 25
28export ZRELADDR INITRD_PHYS PARAMS_PHYS 26export INITRD_PHYS PARAMS_PHYS
29 27
30targets := Image zImage xipImage bootpImage uImage 28targets := Image zImage xipImage bootpImage uImage
31 29
@@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE $@
67ifeq ($(CONFIG_ZBOOT_ROM),y) 65ifeq ($(CONFIG_ZBOOT_ROM),y)
68$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT) 66$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
69else 67else
70$(obj)/uImage: LOADADDR=$(ZRELADDR) 68$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
71endif 69endif
72 70
73ifeq ($(CONFIG_THUMB2_KERNEL),y) 71ifeq ($(CONFIG_THUMB2_KERNEL),y)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 864a002137fe..7636c9b3f9a7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -4,6 +4,7 @@
4# create a compressed vmlinuz image from the original vmlinux 4# create a compressed vmlinuz image from the original vmlinux
5# 5#
6 6
7AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
7HEAD = head.o 8HEAD = head.o
8OBJS = misc.o decompress.o 9OBJS = misc.o decompress.o
9FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c 10FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c
@@ -19,10 +20,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
19OBJS += head-shark.o ofw-shark.o 20OBJS += head-shark.o ofw-shark.o
20endif 21endif
21 22
22ifeq ($(CONFIG_ARCH_L7200),y)
23OBJS += head-l7200.o
24endif
25
26ifeq ($(CONFIG_ARCH_P720T),y) 23ifeq ($(CONFIG_ARCH_P720T),y)
27# Borrow this code from SA1100 24# Borrow this code from SA1100
28OBJS += head-sa1100.o 25OBJS += head-sa1100.o
@@ -82,19 +79,9 @@ endif
82EXTRA_CFLAGS := -fpic -fno-builtin 79EXTRA_CFLAGS := -fpic -fno-builtin
83EXTRA_AFLAGS := -Wa,-march=all 80EXTRA_AFLAGS := -Wa,-march=all
84 81
85# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
86# linker symbols. We only define initrd_phys and params_phys if the
87# machine class defined the corresponding makefile variable.
88LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
89ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) 82ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
90LDFLAGS_vmlinux += --be8 83LDFLAGS_vmlinux += --be8
91endif 84endif
92ifneq ($(INITRD_PHYS),)
93LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
94endif
95ifneq ($(PARAMS_PHYS),)
96LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
97endif
98# ? 85# ?
99LDFLAGS_vmlinux += -p 86LDFLAGS_vmlinux += -p
100# Report unresolved symbol references 87# Report unresolved symbol references
diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug
deleted file mode 100644
index 491a037b2973..000000000000
--- a/arch/arm/boot/compressed/Makefile.debug
+++ /dev/null
@@ -1,23 +0,0 @@
1#
2# linux/arch/arm/boot/compressed/Makefile
3#
4# create a compressed vmlinux image from the original vmlinux
5#
6
7COMPRESSED_EXTRA=../../lib/ll_char_wr.o
8OBJECTS=misc-debug.o ll_char_wr.aout.o
9
10CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
11
12test-gzip: piggy.aout.o $(OBJECTS)
13 $(CC) -o $@ $(OBJECTS) piggy.aout.o
14
15misc-debug.o: misc.c
16 $(CC) $(CFLAGS) -o $@ misc.c
17
18piggy.aout.o: piggy.o
19 arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
20
21ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
22 arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
23
diff --git a/arch/arm/boot/compressed/head-l7200.S b/arch/arm/boot/compressed/head-l7200.S
deleted file mode 100644
index d0e3b20856cd..000000000000
--- a/arch/arm/boot/compressed/head-l7200.S
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * linux/arch/arm/boot/compressed/head-l7200.S
3 *
4 * Copyright (C) 2000 Steve Hill <sjhill@cotw.com>
5 *
6 * Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This
7 * is merged with head.S by the linker.
8 */
9
10#include <asm/mach-types.h>
11
12#ifndef CONFIG_ARCH_L7200
13#error What am I doing here...
14#endif
15
16 .section ".start", "ax"
17
18__L7200_start:
19 mov r0, #0x00100000 @ FLASH address of initrd
20 mov r2, #0xf1000000 @ RAM address of initrd
21 add r3, r2, #0x00700000 @ Size of initrd
221:
23 ldmia r0!, {r4, r5, r6, r7}
24 stmia r2!, {r4, r5, r6, r7}
25 cmp r2, r3
26 ble 1b
27
28 mov r8, #0 @ Zero it out
29 mov r7, #MACH_TYPE_L7200 @ Set architecture ID
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5191b1532e8..abf4d65acf62 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -170,9 +170,16 @@ not_angel:
170 170
171 .text 171 .text
172 adr r0, LC0 172 adr r0, LC0
173 ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp}) 173 ARM( ldmia r0, {r1, r2, r3, r5, r6, r11, ip, sp})
174 THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} ) 174 THUMB( ldmia r0, {r1, r2, r3, r5, r6, r11, ip} )
175 THUMB( ldr sp, [r0, #32] ) 175 THUMB( ldr sp, [r0, #32] )
176#ifdef CONFIG_AUTO_ZRELADDR
177 @ determine final kernel image address
178 and r4, pc, #0xf8000000
179 add r4, r4, #TEXT_OFFSET
180#else
181 ldr r4, =CONFIG_ZRELADDR
182#endif
176 subs r0, r0, r1 @ calculate the delta offset 183 subs r0, r0, r1 @ calculate the delta offset
177 184
178 @ if delta is zero, we are 185 @ if delta is zero, we are
@@ -310,18 +317,17 @@ wont_overwrite: mov r0, r4
310LC0: .word LC0 @ r1 317LC0: .word LC0 @ r1
311 .word __bss_start @ r2 318 .word __bss_start @ r2
312 .word _end @ r3 319 .word _end @ r3
313 .word zreladdr @ r4
314 .word _start @ r5 320 .word _start @ r5
315 .word _image_size @ r6 321 .word _image_size @ r6
316 .word _got_start @ r11 322 .word _got_start @ r11
317 .word _got_end @ ip 323 .word _got_end @ ip
318 .word user_stack+4096 @ sp 324 .word user_stack_end @ sp
319LC1: .word reloc_end - reloc_start 325LC1: .word reloc_end - reloc_start
320 .size LC0, . - LC0 326 .size LC0, . - LC0
321 327
322#ifdef CONFIG_ARCH_RPC 328#ifdef CONFIG_ARCH_RPC
323 .globl params 329 .globl params
324params: ldr r0, =params_phys 330params: ldr r0, =0x10000100 @ params_phys for RPC
325 mov pc, lr 331 mov pc, lr
326 .ltorg 332 .ltorg
327 .align 333 .align
@@ -339,9 +345,8 @@ params: ldr r0, =params_phys
339 * r4 = kernel execution address 345 * r4 = kernel execution address
340 * r7 = architecture number 346 * r7 = architecture number
341 * r8 = atags pointer 347 * r8 = atags pointer
342 * r9 = run-time address of "start" (???)
343 * On exit, 348 * On exit,
344 * r1, r2, r3, r9, r10, r12 corrupted 349 * r0, r1, r2, r3, r9, r10, r12 corrupted
345 * This routine must preserve: 350 * This routine must preserve:
346 * r4, r5, r6, r7, r8 351 * r4, r5, r6, r7, r8
347 */ 352 */
@@ -396,12 +401,18 @@ __armv3_mpu_cache_on:
396 401
397 mov r0, #0 402 mov r0, #0
398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 403 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
404 /*
405 * ?? ARMv3 MMU does not allow reading the control register,
406 * does this really work on ARMv3 MPU?
407 */
399 mrc p15, 0, r0, c1, c0, 0 @ read control reg 408 mrc p15, 0, r0, c1, c0, 0 @ read control reg
400 @ .... .... .... WC.M 409 @ .... .... .... WC.M
401 orr r0, r0, #0x000d @ .... .... .... 11.1 410 orr r0, r0, #0x000d @ .... .... .... 11.1
411 /* ?? this overwrites the value constructed above? */
402 mov r0, #0 412 mov r0, #0
403 mcr p15, 0, r0, c1, c0, 0 @ write control reg 413 mcr p15, 0, r0, c1, c0, 0 @ write control reg
404 414
415 /* ?? invalidate for the second time? */
405 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 416 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
406 mov pc, lr 417 mov pc, lr
407 418
@@ -771,8 +782,10 @@ proc_types:
771 * Turn off the Cache and MMU. ARMv3 does not support 782 * Turn off the Cache and MMU. ARMv3 does not support
772 * reading the control register, but ARMv4 does. 783 * reading the control register, but ARMv4 does.
773 * 784 *
774 * On exit, r0, r1, r2, r3, r9, r12 corrupted 785 * On exit,
775 * This routine must preserve: r4, r6, r7 786 * r0, r1, r2, r3, r9, r12 corrupted
787 * This routine must preserve:
788 * r4, r6, r7
776 */ 789 */
777 .align 5 790 .align 5
778cache_off: mov r3, #12 @ cache_off function 791cache_off: mov r3, #12 @ cache_off function
@@ -845,7 +858,7 @@ __armv3_mmu_cache_off:
845 * Clean and flush the cache to maintain consistency. 858 * Clean and flush the cache to maintain consistency.
846 * 859 *
847 * On exit, 860 * On exit,
848 * r1, r2, r3, r9, r11, r12 corrupted 861 * r1, r2, r3, r9, r10, r11, r12 corrupted
849 * This routine must preserve: 862 * This routine must preserve:
850 * r0, r4, r5, r6, r7 863 * r0, r4, r5, r6, r7
851 */ 864 */
@@ -988,7 +1001,7 @@ no_cache_id:
988__armv3_mmu_cache_flush: 1001__armv3_mmu_cache_flush:
989__armv3_mpu_cache_flush: 1002__armv3_mpu_cache_flush:
990 mov r1, #0 1003 mov r1, #0
991 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 1004 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
992 mov pc, lr 1005 mov pc, lr
993 1006
994/* 1007/*
@@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush:
1001phexbuf: .space 12 1014phexbuf: .space 12
1002 .size phexbuf, . - phexbuf 1015 .size phexbuf, . - phexbuf
1003 1016
1017@ phex corrupts {r0, r1, r2, r3}
1004phex: adr r3, phexbuf 1018phex: adr r3, phexbuf
1005 mov r2, #0 1019 mov r2, #0
1006 strb r2, [r3, r1] 1020 strb r2, [r3, r1]
@@ -1015,6 +1029,7 @@ phex: adr r3, phexbuf
1015 strb r2, [r3, r1] 1029 strb r2, [r3, r1]
1016 b 1b 1030 b 1b
1017 1031
1032@ puts corrupts {r0, r1, r2, r3}
1018puts: loadsp r3, r1 1033puts: loadsp r3, r1
10191: ldrb r2, [r0], #1 10341: ldrb r2, [r0], #1
1020 teq r2, #0 1035 teq r2, #0
@@ -1029,12 +1044,14 @@ puts: loadsp r3, r1
1029 teq r0, #0 1044 teq r0, #0
1030 bne 1b 1045 bne 1b
1031 mov pc, lr 1046 mov pc, lr
1047@ putc corrupts {r0, r1, r2, r3}
1032putc: 1048putc:
1033 mov r2, r0 1049 mov r2, r0
1034 mov r0, #0 1050 mov r0, #0
1035 loadsp r3, r1 1051 loadsp r3, r1
1036 b 2b 1052 b 2b
1037 1053
1054@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1038memdump: mov r12, r0 1055memdump: mov r12, r0
1039 mov r10, lr 1056 mov r10, lr
1040 mov r11, #0 1057 mov r11, #0
@@ -1070,3 +1087,4 @@ reloc_end:
1070 .align 1087 .align
1071 .section ".stack", "w" 1088 .section ".stack", "w"
1072user_stack: .space 4096 1089user_stack: .space 4096
1090user_stack_end:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index d2b2ef41cd4f..e653a6d3c8d9 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
28 28
29#include <asm/unaligned.h> 29#include <asm/unaligned.h>
30 30
31#ifdef STANDALONE_DEBUG
32#define putstr printf
33#else
34 31
35static void putstr(const char *ptr); 32static void putstr(const char *ptr);
36extern void error(char *x); 33extern void error(char *x);
@@ -116,7 +113,6 @@ static void putstr(const char *ptr)
116 flush(); 113 flush();
117} 114}
118 115
119#endif
120 116
121void *memcpy(void *__dest, __const void *__src, size_t __n) 117void *memcpy(void *__dest, __const void *__src, size_t __n)
122{ 118{
@@ -186,7 +182,6 @@ asmlinkage void __div0(void)
186 182
187extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); 183extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
188 184
189#ifndef STANDALONE_DEBUG
190 185
191unsigned long 186unsigned long
192decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, 187decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
@@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
211 putstr(" done, booting the kernel.\n"); 206 putstr(" done, booting the kernel.\n");
212 return output_ptr; 207 return output_ptr;
213} 208}
214#else
215
216char output_buffer[1500*1024];
217
218int main()
219{
220 output_data = output_buffer;
221
222 putstr("Uncompressing Linux...");
223 decompress(input_data, input_data_end - input_data,
224 NULL, NULL, output_data, NULL, error);
225 putstr("done.\n");
226 return 0;
227}
228#endif
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 337741f734ac..7dfa9a85bc0c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq)
108 spin_unlock(&irq_controller_lock); 108 spin_unlock(&irq_controller_lock);
109} 109}
110 110
111static int gic_set_type(unsigned int irq, unsigned int type)
112{
113 void __iomem *base = gic_dist_base(irq);
114 unsigned int gicirq = gic_irq(irq);
115 u32 enablemask = 1 << (gicirq % 32);
116 u32 enableoff = (gicirq / 32) * 4;
117 u32 confmask = 0x2 << ((gicirq % 16) * 2);
118 u32 confoff = (gicirq / 16) * 4;
119 bool enabled = false;
120 u32 val;
121
122 /* Interrupt configuration for SGIs can't be changed */
123 if (gicirq < 16)
124 return -EINVAL;
125
126 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
127 return -EINVAL;
128
129 spin_lock(&irq_controller_lock);
130
131 val = readl(base + GIC_DIST_CONFIG + confoff);
132 if (type == IRQ_TYPE_LEVEL_HIGH)
133 val &= ~confmask;
134 else if (type == IRQ_TYPE_EDGE_RISING)
135 val |= confmask;
136
137 /*
138 * As recommended by the spec, disable the interrupt before changing
139 * the configuration
140 */
141 if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
142 writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
143 enabled = true;
144 }
145
146 writel(val, base + GIC_DIST_CONFIG + confoff);
147
148 if (enabled)
149 writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
150
151 spin_unlock(&irq_controller_lock);
152
153 return 0;
154}
155
111#ifdef CONFIG_SMP 156#ifdef CONFIG_SMP
112static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) 157static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
113{ 158{
@@ -161,6 +206,7 @@ static struct irq_chip gic_chip = {
161 .ack = gic_ack_irq, 206 .ack = gic_ack_irq,
162 .mask = gic_mask_irq, 207 .mask = gic_mask_irq,
163 .unmask = gic_unmask_irq, 208 .unmask = gic_unmask_irq,
209 .set_type = gic_set_type,
164#ifdef CONFIG_SMP 210#ifdef CONFIG_SMP
165 .set_affinity = gic_set_cpu, 211 .set_affinity = gic_set_cpu,
166#endif 212#endif
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 9eaf65f43642..517d50ddbeb3 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -185,13 +185,10 @@ static struct sa1111_dev_info sa1111_devices[] = {
185 }, 185 },
186}; 186};
187 187
188void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes) 188void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
189{ 189{
190 unsigned int sz = SZ_1M >> PAGE_SHIFT; 190 unsigned int sz = SZ_1M >> PAGE_SHIFT;
191 191
192 if (node != 0)
193 sz = 0;
194
195 size[1] = size[0] - sz; 192 size[1] = size[0] - sz;
196 size[0] = sz; 193 size[0] = sz;
197} 194}
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index f2e3a9088df6..ccc9c9959b82 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y
13CONFIG_MACH_RD88F6281=y 13CONFIG_MACH_RD88F6281=y
14CONFIG_MACH_MV88F6281GTW_GE=y 14CONFIG_MACH_MV88F6281GTW_GE=y
15CONFIG_MACH_SHEEVAPLUG=y 15CONFIG_MACH_SHEEVAPLUG=y
16CONFIG_MACH_ESATA_SHEEVAPLUG=y
17CONFIG_MACH_GURUPLUG=y
16CONFIG_MACH_TS219=y 18CONFIG_MACH_TS219=y
17CONFIG_MACH_TS41X=y 19CONFIG_MACH_TS41X=y
18CONFIG_MACH_OPENRD_BASE=y 20CONFIG_MACH_OPENRD_BASE=y
19CONFIG_MACH_OPENRD_CLIENT=y 21CONFIG_MACH_OPENRD_CLIENT=y
22CONFIG_MACH_OPENRD_ULTIMATE=y
20CONFIG_MACH_NETSPACE_V2=y 23CONFIG_MACH_NETSPACE_V2=y
24CONFIG_MACH_INETSPACE_V2=y
25CONFIG_MACH_NETSPACE_MAX_V2=y
26CONFIG_MACH_NET2BIG_V2=y
27CONFIG_MACH_NET5BIG_V2=y
28CONFIG_MACH_T5325=y
21# CONFIG_CPU_FEROCEON_OLD_ID is not set 29# CONFIG_CPU_FEROCEON_OLD_ID is not set
22CONFIG_NO_HZ=y 30CONFIG_NO_HZ=y
23CONFIG_HIGH_RES_TIMERS=y 31CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/lusl7200_defconfig b/arch/arm/configs/lusl7200_defconfig
deleted file mode 100644
index 816fc42884c9..000000000000
--- a/arch/arm/configs/lusl7200_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EMBEDDED=y
7# CONFIG_HOTPLUG is not set
8CONFIG_MODULES=y
9CONFIG_ARCH_L7200=y
10# CONFIG_ARM_THUMB is not set
11CONFIG_ZBOOT_ROM_TEXT=0x00010000
12CONFIG_ZBOOT_ROM_BSS=0xf03e0000
13CONFIG_ZBOOT_ROM=y
14CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M"
15CONFIG_BINFMT_AOUT=y
16CONFIG_BLK_DEV_RAM=y
17# CONFIG_INPUT is not set
18# CONFIG_SERIO_SERPORT is not set
19# CONFIG_VT is not set
20CONFIG_SERIAL_NONSTANDARD=y
21CONFIG_EXT2_FS=y
22CONFIG_DEBUG_USER=y
23# CONFIG_CRC32 is not set
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662feb9f1d..6750b8e45a49 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
121extern void elf_set_personality(const struct elf32_hdr *); 121extern void elf_set_personality(const struct elf32_hdr *);
122#define SET_PERSONALITY(ex) elf_set_personality(&(ex)) 122#define SET_PERSONALITY(ex) elf_set_personality(&(ex))
123 123
124struct mm_struct;
125extern unsigned long arch_randomize_brk(struct mm_struct *mm);
126#define arch_randomize_brk arch_randomize_brk
127
124#endif 128#endif
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index f7bd52b1c365..c1062c317103 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -19,6 +19,7 @@
19#define HWCAP_NEON 4096 19#define HWCAP_NEON 4096
20#define HWCAP_VFPv3 8192 20#define HWCAP_VFPv3 8192
21#define HWCAP_VFPv3D16 16384 21#define HWCAP_VFPv3D16 16384
22#define HWCAP_TLS 32768
22 23
23#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 24#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
24/* 25/*
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 237282f7c762..2721a5814cb9 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -7,6 +7,8 @@
7#define irq_canonicalize(i) (i) 7#define irq_canonicalize(i) (i)
8#endif 8#endif
9 9
10#define NR_IRQS_LEGACY 16
11
10/* 12/*
11 * Use this value to indicate lack of interrupt 13 * Use this value to indicate lack of interrupt
12 * capability 14 * capability
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index df15a0dc228e..8ec9ef5c3c7b 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -19,10 +19,26 @@
19 19
20#ifndef __ASSEMBLY__ 20#ifndef __ASSEMBLY__
21 21
22struct kimage; 22/**
23/* Provide a dummy definition to avoid build failures. */ 23 * crash_setup_regs() - save registers for the panic kernel
24 * @newregs: registers are saved here
25 * @oldregs: registers to be saved (may be %NULL)
26 *
27 * Function copies machine registers from @oldregs to @newregs. If @oldregs is
28 * %NULL then current registers are stored there.
29 */
24static inline void crash_setup_regs(struct pt_regs *newregs, 30static inline void crash_setup_regs(struct pt_regs *newregs,
25 struct pt_regs *oldregs) { } 31 struct pt_regs *oldregs)
32{
33 if (oldregs) {
34 memcpy(newregs, oldregs, sizeof(*newregs));
35 } else {
36 __asm__ __volatile__ ("stmia %0, {r0 - r15}"
37 : : "r" (&newregs->ARM_r0));
38 __asm__ __volatile__ ("mrs %0, cpsr"
39 : "=r" (newregs->ARM_cpsr));
40 }
41}
26 42
27#endif /* __ASSEMBLY__ */ 43#endif /* __ASSEMBLY__ */
28 44
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index c59842dc7cb8..8a0dd18ba642 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -20,6 +20,7 @@ struct machine_desc {
20 * by assembler code in head.S, head-common.S 20 * by assembler code in head.S, head-common.S
21 */ 21 */
22 unsigned int nr; /* architecture number */ 22 unsigned int nr; /* architecture number */
23 unsigned int nr_irqs; /* number of IRQs */
23 unsigned int phys_io; /* start of physical io */ 24 unsigned int phys_io; /* start of physical io */
24 unsigned int io_pg_offst; /* byte offset for io 25 unsigned int io_pg_offst; /* byte offset for io
25 * page tabe entry */ 26 * page tabe entry */
@@ -37,6 +38,7 @@ struct machine_desc {
37 void (*fixup)(struct machine_desc *, 38 void (*fixup)(struct machine_desc *,
38 struct tag *, char **, 39 struct tag *, char **,
39 struct meminfo *); 40 struct meminfo *);
41 void (*reserve)(void);/* reserve mem blocks */
40 void (*map_io)(void);/* IO mapping function */ 42 void (*map_io)(void);/* IO mapping function */
41 void (*init_irq)(void); 43 void (*init_irq)(void);
42 struct sys_timer *timer; /* system tick timer */ 44 struct sys_timer *timer; /* system tick timer */
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 8920b2d6e3b8..ce3eee9fe26c 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,6 +17,7 @@ struct seq_file;
17/* 17/*
18 * This is internal. Do not use it. 18 * This is internal. Do not use it.
19 */ 19 */
20extern unsigned int arch_nr_irqs;
20extern void (*init_arch_irq)(void); 21extern void (*init_arch_irq)(void);
21extern void init_FIQ(void); 22extern void init_FIQ(void);
22extern int show_fiq_list(struct seq_file *, void *); 23extern int show_fiq_list(struct seq_file *, void *);
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 742c2aaeb020..d2fedb5aeb1f 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -27,6 +27,8 @@ struct map_desc {
27#define MT_MEMORY 9 27#define MT_MEMORY 9
28#define MT_ROM 10 28#define MT_ROM 10
29#define MT_MEMORY_NONCACHED 11 29#define MT_MEMORY_NONCACHED 11
30#define MT_MEMORY_DTCM 12
31#define MT_MEMORY_ITCM 13
30 32
31#ifdef CONFIG_MMU 33#ifdef CONFIG_MMU
32extern void iotable_init(struct map_desc *, int); 34extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 52f0da1e97df..16330bd0657c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -46,6 +46,7 @@ struct pci_sys_data {
46 /* IRQ mapping */ 46 /* IRQ mapping */
47 int (*map_irq)(struct pci_dev *, u8, u8); 47 int (*map_irq)(struct pci_dev *, u8, u8);
48 struct hw_pci *hw; 48 struct hw_pci *hw;
49 void *private_data; /* platform controller private data */
49}; 50};
50 51
51/* 52/*
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
new file mode 100644
index 000000000000..fdbc43b2e6c0
--- /dev/null
+++ b/arch/arm/include/asm/memblock.h
@@ -0,0 +1,16 @@
1#ifndef _ASM_ARM_MEMBLOCK_H
2#define _ASM_ARM_MEMBLOCK_H
3
4#ifdef CONFIG_MMU
5extern phys_addr_t lowmem_end_addr;
6#define MEMBLOCK_REAL_LIMIT lowmem_end_addr
7#else
8#define MEMBLOCK_REAL_LIMIT 0
9#endif
10
11struct meminfo;
12struct machine_desc;
13
14extern void arm_memblock_init(struct meminfo *, struct machine_desc *);
15
16#endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4312ee5e3d0b..23c2e8e5c0fa 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -124,6 +124,15 @@
124#endif /* !CONFIG_MMU */ 124#endif /* !CONFIG_MMU */
125 125
126/* 126/*
127 * We fix the TCM memories max 32 KiB ITCM resp DTCM at these
128 * locations
129 */
130#ifdef CONFIG_HAVE_TCM
131#define ITCM_OFFSET UL(0xfffe0000)
132#define DTCM_OFFSET UL(0xfffe8000)
133#endif
134
135/*
127 * Physical vs virtual RAM address space conversion. These are 136 * Physical vs virtual RAM address space conversion. These are
128 * private definitions which should NOT be used outside memory.h 137 * private definitions which should NOT be used outside memory.h
129 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. 138 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
@@ -158,7 +167,7 @@
158#endif 167#endif
159 168
160#ifndef arch_adjust_zones 169#ifndef arch_adjust_zones
161#define arch_adjust_zones(node,size,holes) do { } while (0) 170#define arch_adjust_zones(size,holes) do { } while (0)
162#elif !defined(CONFIG_ZONE_DMA) 171#elif !defined(CONFIG_ZONE_DMA)
163#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA" 172#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
164#endif 173#endif
@@ -234,76 +243,11 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
234 * virt_to_page(k) convert a _valid_ virtual address to struct page * 243 * virt_to_page(k) convert a _valid_ virtual address to struct page *
235 * virt_addr_valid(k) indicates whether a virtual address is valid 244 * virt_addr_valid(k) indicates whether a virtual address is valid
236 */ 245 */
237#ifndef CONFIG_DISCONTIGMEM
238
239#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET 246#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
240 247
241#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 248#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
242#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) 249#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
243 250
244#define PHYS_TO_NID(addr) (0)
245
246#else /* CONFIG_DISCONTIGMEM */
247
248/*
249 * This is more complex. We have a set of mem_map arrays spread
250 * around in memory.
251 */
252#include <linux/numa.h>
253
254#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn)
255#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
256
257#define virt_to_page(kaddr) \
258 (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
259
260#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < MAX_NUMNODES)
261
262/*
263 * Common discontigmem stuff.
264 * PHYS_TO_NID is used by the ARM kernel/setup.c
265 */
266#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT)
267
268/*
269 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
270 * and returns the mem_map of that node.
271 */
272#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
273
274/*
275 * Given a page frame number, find the owning node of the memory
276 * and returns the mem_map of that node.
277 */
278#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
279
280#ifdef NODE_MEM_SIZE_BITS
281#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1)
282
283/*
284 * Given a kernel address, find the home node of the underlying memory.
285 */
286#define KVADDR_TO_NID(addr) \
287 (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
288
289/*
290 * Given a page frame number, convert it to a node id.
291 */
292#define PFN_TO_NID(pfn) \
293 (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
294
295/*
296 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
297 * and returns the index corresponding to the appropriate page in the
298 * node's mem_map.
299 */
300#define LOCAL_MAP_NR(addr) \
301 (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
302
303#endif /* NODE_MEM_SIZE_BITS */
304
305#endif /* !CONFIG_DISCONTIGMEM */
306
307/* 251/*
308 * Optional coherency support. Currently used only by selected 252 * Optional coherency support. Currently used only by selected
309 * Intel XSC3-based systems. 253 * Intel XSC3-based systems.
diff --git a/arch/arm/include/asm/mmzone.h b/arch/arm/include/asm/mmzone.h
deleted file mode 100644
index ae63a4fd28c8..000000000000
--- a/arch/arm/include/asm/mmzone.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * arch/arm/include/asm/mmzone.h
3 *
4 * 1999-12-29 Nicolas Pitre Created
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_MMZONE_H
11#define __ASM_MMZONE_H
12
13/*
14 * Currently defined in arch/arm/mm/discontig.c
15 */
16extern pg_data_t discontig_node_data[];
17
18/*
19 * Return a pointer to the node data for node n.
20 */
21#define NODE_DATA(nid) (&discontig_node_data[nid])
22
23/*
24 * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
25 */
26#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map)
27
28#include <mach/memory.h>
29
30#endif
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 9dcb11e59026..c974be8913a7 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs);
184#define predicate(x) ((x) & 0xf0000000) 184#define predicate(x) ((x) & 0xf0000000)
185#define PREDICATE_ALWAYS 0xe0000000 185#define PREDICATE_ALWAYS 0xe0000000
186 186
187/*
188 * kprobe-based event tracer support
189 */
190#include <linux/stddef.h>
191#include <linux/types.h>
192#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
193
194extern int regs_query_register_offset(const char *name);
195extern const char *regs_query_register_name(unsigned int offset);
196extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
197extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
198 unsigned int n);
199
200/**
201 * regs_get_register() - get register value from its offset
202 * @regs: pt_regs from which register value is gotten
203 * @offset: offset number of the register.
204 *
205 * regs_get_register returns the value of a register whose offset from @regs.
206 * The @offset is the offset of the register in struct pt_regs.
207 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
208 */
209static inline unsigned long regs_get_register(struct pt_regs *regs,
210 unsigned int offset)
211{
212 if (unlikely(offset > MAX_REG_OFFSET))
213 return 0;
214 return *(unsigned long *)((unsigned long)regs + offset);
215}
216
217/* Valid only for Kernel mode traps. */
218static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
219{
220 return regs->ARM_sp;
221}
222
187#endif /* __KERNEL__ */ 223#endif /* __KERNEL__ */
188 224
189#endif /* __ASSEMBLY__ */ 225#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index f392fb4437af..f1e5a9bca249 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -201,8 +201,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
201struct membank { 201struct membank {
202 unsigned long start; 202 unsigned long start;
203 unsigned long size; 203 unsigned long size;
204 unsigned short node; 204 unsigned int highmem;
205 unsigned short highmem;
206}; 205};
207 206
208struct meminfo { 207struct meminfo {
@@ -212,9 +211,8 @@ struct meminfo {
212 211
213extern struct meminfo meminfo; 212extern struct meminfo meminfo;
214 213
215#define for_each_nodebank(iter,mi,no) \ 214#define for_each_bank(iter,mi) \
216 for (iter = 0; iter < (mi)->nr_banks; iter++) \ 215 for (iter = 0; iter < (mi)->nr_banks; iter++)
217 if ((mi)->bank[iter].node == no)
218 216
219#define bank_pfn_start(bank) __phys_to_pfn((bank)->start) 217#define bank_pfn_start(bank) __phys_to_pfn((bank)->start)
220#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) 218#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size)
diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
new file mode 100644
index 000000000000..de003327be97
--- /dev/null
+++ b/arch/arm/include/asm/stackprotector.h
@@ -0,0 +1,38 @@
1/*
2 * GCC stack protector support.
3 *
4 * Stack protector works by putting predefined pattern at the start of
5 * the stack frame and verifying that it hasn't been overwritten when
6 * returning from the function. The pattern is called stack canary
7 * and gcc expects it to be defined by a global variable called
8 * "__stack_chk_guard" on ARM. This unfortunately means that on SMP
9 * we cannot have a different canary value per task.
10 */
11
12#ifndef _ASM_STACKPROTECTOR_H
13#define _ASM_STACKPROTECTOR_H 1
14
15#include <linux/random.h>
16#include <linux/version.h>
17
18extern unsigned long __stack_chk_guard;
19
20/*
21 * Initialize the stackprotector canary value.
22 *
23 * NOTE: this must only be called from functions that never return,
24 * and it must always be inlined.
25 */
26static __always_inline void boot_init_stack_canary(void)
27{
28 unsigned long canary;
29
30 /* Try to get a semi random initial value. */
31 get_random_bytes(&canary, sizeof(canary));
32 canary ^= LINUX_VERSION_CODE;
33
34 current->stack_canary = canary;
35 __stack_chk_guard = current->stack_canary;
36}
37
38#endif /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f48002734..8ba1ccf82a02 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -83,7 +83,7 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
83 83
84void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, 84void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
85 struct pt_regs *), 85 struct pt_regs *),
86 int sig, const char *name); 86 int sig, int code, const char *name);
87 87
88#define xchg(ptr,x) \ 88#define xchg(ptr,x) \
89 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 89 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
new file mode 100644
index 000000000000..e71d6ff8d104
--- /dev/null
+++ b/arch/arm/include/asm/tls.h
@@ -0,0 +1,46 @@
1#ifndef __ASMARM_TLS_H
2#define __ASMARM_TLS_H
3
4#ifdef __ASSEMBLY__
5 .macro set_tls_none, tp, tmp1, tmp2
6 .endm
7
8 .macro set_tls_v6k, tp, tmp1, tmp2
9 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
10 .endm
11
12 .macro set_tls_v6, tp, tmp1, tmp2
13 ldr \tmp1, =elf_hwcap
14 ldr \tmp1, [\tmp1, #0]
15 mov \tmp2, #0xffff0fff
16 tst \tmp1, #HWCAP_TLS @ hardware TLS available?
17 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
18 streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
19 .endm
20
21 .macro set_tls_software, tp, tmp1, tmp2
22 mov \tmp1, #0xffff0fff
23 str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
24 .endm
25#endif
26
27#ifdef CONFIG_TLS_REG_EMUL
28#define tls_emu 1
29#define has_tls_reg 1
30#define set_tls set_tls_none
31#elif __LINUX_ARM_ARCH__ >= 7 || \
32 (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
33#define tls_emu 0
34#define has_tls_reg 1
35#define set_tls set_tls_v6k
36#elif __LINUX_ARM_ARCH__ == 6
37#define tls_emu 0
38#define has_tls_reg (elf_hwcap & HWCAP_TLS)
39#define set_tls set_tls_v6
40#else
41#define tls_emu 0
42#define has_tls_reg 0
43#define set_tls set_tls_software
44#endif
45
46#endif /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 422f3cc204a2..3d5fc41ae8d3 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -3,6 +3,8 @@
3 * 3 *
4 * Assembler-only file containing VFP macros and register definitions. 4 * Assembler-only file containing VFP macros and register definitions.
5 */ 5 */
6#include <asm/hwcap.h>
7
6#include "vfp.h" 8#include "vfp.h"
7 9
8@ Macros to allow building with old toolkits (with no VFP support) 10@ Macros to allow building with old toolkits (with no VFP support)
@@ -22,12 +24,20 @@
22 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} 24 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
23#endif 25#endif
24#ifdef CONFIG_VFPv3 26#ifdef CONFIG_VFPv3
27#if __LINUX_ARM_ARCH__ <= 6
28 ldr \tmp, =elf_hwcap @ may not have MVFR regs
29 ldr \tmp, [\tmp, #0]
30 tst \tmp, #HWCAP_VFPv3D16
31 ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
32 addne \base, \base, #32*4 @ step over unused register space
33#else
25 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 34 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
26 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 35 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
27 cmp \tmp, #2 @ 32 x 64bit registers? 36 cmp \tmp, #2 @ 32 x 64bit registers?
28 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} 37 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
29 addne \base, \base, #32*4 @ step over unused register space 38 addne \base, \base, #32*4 @ step over unused register space
30#endif 39#endif
40#endif
31 .endm 41 .endm
32 42
33 @ write all the working registers out of the VFP 43 @ write all the working registers out of the VFP
@@ -38,10 +48,18 @@
38 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} 48 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
39#endif 49#endif
40#ifdef CONFIG_VFPv3 50#ifdef CONFIG_VFPv3
51#if __LINUX_ARM_ARCH__ <= 6
52 ldr \tmp, =elf_hwcap @ may not have MVFR regs
53 ldr \tmp, [\tmp, #0]
54 tst \tmp, #HWCAP_VFPv3D16
55 stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
56 addne \base, \base, #32*4 @ step over unused register space
57#else
41 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 58 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
42 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 59 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
43 cmp \tmp, #2 @ 32 x 64bit registers? 60 cmp \tmp, #2 @ 32 x 64bit registers?
44 stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} 61 stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
45 addne \base, \base, #32*4 @ step over unused register space 62 addne \base, \base, #32*4 @ step over unused register space
46#endif 63#endif
64#endif
47 .endm 65 .endm
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c28e13..980b78e31328 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
13 13
14# Object file lists. 14# Object file lists.
15 15
16obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \ 16obj-y := elf.o entry-armv.o entry-common.o irq.o \
17 process.o ptrace.o return_address.o setup.o signal.o \ 17 process.o ptrace.o return_address.o setup.o signal.o \
18 sys_arm.o stacktrace.o time.o traps.o 18 sys_arm.o stacktrace.o time.o traps.o
19 19
20obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
21
20obj-$(CONFIG_LEDS) += leds.o 22obj-$(CONFIG_LEDS) += leds.o
21obj-$(CONFIG_OC_ETM) += etm.o 23obj-$(CONFIG_OC_ETM) += etm.o
22 24
@@ -39,6 +41,7 @@ obj-$(CONFIG_ARM_THUMBEE) += thumbee.o
39obj-$(CONFIG_KGDB) += kgdb.o 41obj-$(CONFIG_KGDB) += kgdb.o
40obj-$(CONFIG_ARM_UNWIND) += unwind.o 42obj-$(CONFIG_ARM_UNWIND) += unwind.o
41obj-$(CONFIG_HAVE_TCM) += tcm.o 43obj-$(CONFIG_HAVE_TCM) += tcm.o
44obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
42 45
43obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o 46obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
44AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 47AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 883511522fca..85f2a019f77b 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -40,6 +40,9 @@
40int main(void) 40int main(void)
41{ 41{
42 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); 42 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
43#ifdef CONFIG_CC_STACKPROTECTOR
44 DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
45#endif
43 BLANK(); 46 BLANK();
44 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); 47 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
45 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); 48 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/compat.c
index 0a1385442f43..925652318b8b 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/compat.c
@@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
217 struct param_struct *params = (struct param_struct *)tags; 217 struct param_struct *params = (struct param_struct *)tags;
218 build_tag_list(params, &params->u2); 218 build_tag_list(params, &params->u2);
219} 219}
220
221void __init squash_mem_tags(struct tag *tag)
222{
223 for (; tag->hdr.size; tag = tag_next(tag))
224 if (tag->hdr.tag == ATAG_MEM)
225 tag->hdr.tag = ATAG_NONE;
226}
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
index 27e61a68bd1c..39264ab1b9c6 100644
--- a/arch/arm/kernel/compat.h
+++ b/arch/arm/kernel/compat.h
@@ -9,5 +9,3 @@
9*/ 9*/
10 10
11extern void convert_to_tag_list(struct tag *tags); 11extern void convert_to_tag_list(struct tag *tags);
12
13extern void squash_mem_tags(struct tag *tag);
diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
new file mode 100644
index 000000000000..cd3b853a8a6d
--- /dev/null
+++ b/arch/arm/kernel/crash_dump.c
@@ -0,0 +1,60 @@
1/*
2 * arch/arm/kernel/crash_dump.c
3 *
4 * Copyright (C) 2010 Nokia Corporation.
5 * Author: Mika Westerberg
6 *
7 * This code is taken from arch/x86/kernel/crash_dump_64.c
8 * Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
9 * Copyright (C) IBM Corporation, 2004. All rights reserved
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/errno.h>
17#include <linux/crash_dump.h>
18#include <linux/uaccess.h>
19#include <linux/io.h>
20
21/* stores the physical address of elf header of crash image */
22unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
23
24/**
25 * copy_oldmem_page() - copy one page from old kernel memory
26 * @pfn: page frame number to be copied
27 * @buf: buffer where the copied page is placed
28 * @csize: number of bytes to copy
29 * @offset: offset in bytes into the page
30 * @userbuf: if set, @buf is int he user address space
31 *
32 * This function copies one page from old kernel memory into buffer pointed by
33 * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
34 * copied or negative error in case of failure.
35 */
36ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
37 size_t csize, unsigned long offset,
38 int userbuf)
39{
40 void *vaddr;
41
42 if (!csize)
43 return 0;
44
45 vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
46 if (!vaddr)
47 return -ENOMEM;
48
49 if (userbuf) {
50 if (copy_to_user(buf, vaddr + offset, csize)) {
51 iounmap(vaddr);
52 return -EFAULT;
53 }
54 } else {
55 memcpy(buf, vaddr + offset, csize);
56 }
57
58 iounmap(vaddr);
59 return csize;
60}
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3fd7861de4d1..bb8e93a76407 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -22,6 +22,7 @@
22#include <asm/thread_notify.h> 22#include <asm/thread_notify.h>
23#include <asm/unwind.h> 23#include <asm/unwind.h>
24#include <asm/unistd.h> 24#include <asm/unistd.h>
25#include <asm/tls.h>
25 26
26#include "entry-header.S" 27#include "entry-header.S"
27 28
@@ -735,11 +736,11 @@ ENTRY(__switch_to)
735#ifdef CONFIG_MMU 736#ifdef CONFIG_MMU
736 ldr r6, [r2, #TI_CPU_DOMAIN] 737 ldr r6, [r2, #TI_CPU_DOMAIN]
737#endif 738#endif
738#if defined(CONFIG_HAS_TLS_REG) 739 set_tls r3, r4, r5
739 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 740#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
740#elif !defined(CONFIG_TLS_REG_EMUL) 741 ldr r7, [r2, #TI_TASK]
741 mov r4, #0xffff0fff 742 ldr r8, =__stack_chk_guard
742 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 743 ldr r7, [r7, #TSK_STACK_CANARY]
743#endif 744#endif
744#ifdef CONFIG_MMU 745#ifdef CONFIG_MMU
745 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 746 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
@@ -749,6 +750,9 @@ ENTRY(__switch_to)
749 ldr r0, =thread_notify_head 750 ldr r0, =thread_notify_head
750 mov r1, #THREAD_NOTIFY_SWITCH 751 mov r1, #THREAD_NOTIFY_SWITCH
751 bl atomic_notifier_call_chain 752 bl atomic_notifier_call_chain
753#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
754 str r7, [r8]
755#endif
752 THUMB( mov ip, r4 ) 756 THUMB( mov ip, r4 )
753 mov r0, r5 757 mov r0, r5
754 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 758 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
@@ -1005,17 +1009,12 @@ kuser_cmpxchg_fixup:
1005 */ 1009 */
1006 1010
1007__kuser_get_tls: @ 0xffff0fe0 1011__kuser_get_tls: @ 0xffff0fe0
1008 1012 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1009#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
1010 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
1011#else
1012 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
1013#endif
1014 usr_ret lr 1013 usr_ret lr
1015 1014 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1016 .rep 5 1015 .rep 4
1017 .word 0 @ pad up to __kuser_helper_version 1016 .word 0 @ 0xffff0ff0 software TLS value, then
1018 .endr 1017 .endr @ pad up to __kuser_helper_version
1019 1018
1020/* 1019/*
1021 * Reference declaration: 1020 * Reference declaration:
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3b3d2c80509c..c0d5c3b3a760 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -47,12 +47,14 @@
47#define irq_finish(irq) do { } while (0) 47#define irq_finish(irq) do { } while (0)
48#endif 48#endif
49 49
50unsigned int arch_nr_irqs;
50void (*init_arch_irq)(void) __initdata = NULL; 51void (*init_arch_irq)(void) __initdata = NULL;
51unsigned long irq_err_count; 52unsigned long irq_err_count;
52 53
53int show_interrupts(struct seq_file *p, void *v) 54int show_interrupts(struct seq_file *p, void *v)
54{ 55{
55 int i = *(loff_t *) v, cpu; 56 int i = *(loff_t *) v, cpu;
57 struct irq_desc *desc;
56 struct irqaction * action; 58 struct irqaction * action;
57 unsigned long flags; 59 unsigned long flags;
58 60
@@ -67,24 +69,25 @@ int show_interrupts(struct seq_file *p, void *v)
67 seq_putc(p, '\n'); 69 seq_putc(p, '\n');
68 } 70 }
69 71
70 if (i < NR_IRQS) { 72 if (i < nr_irqs) {
71 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 73 desc = irq_to_desc(i);
72 action = irq_desc[i].action; 74 raw_spin_lock_irqsave(&desc->lock, flags);
75 action = desc->action;
73 if (!action) 76 if (!action)
74 goto unlock; 77 goto unlock;
75 78
76 seq_printf(p, "%3d: ", i); 79 seq_printf(p, "%3d: ", i);
77 for_each_present_cpu(cpu) 80 for_each_present_cpu(cpu)
78 seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); 81 seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
79 seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-"); 82 seq_printf(p, " %10s", desc->chip->name ? : "-");
80 seq_printf(p, " %s", action->name); 83 seq_printf(p, " %s", action->name);
81 for (action = action->next; action; action = action->next) 84 for (action = action->next; action; action = action->next)
82 seq_printf(p, ", %s", action->name); 85 seq_printf(p, ", %s", action->name);
83 86
84 seq_putc(p, '\n'); 87 seq_putc(p, '\n');
85unlock: 88unlock:
86 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 89 raw_spin_unlock_irqrestore(&desc->lock, flags);
87 } else if (i == NR_IRQS) { 90 } else if (i == nr_irqs) {
88#ifdef CONFIG_FIQ 91#ifdef CONFIG_FIQ
89 show_fiq_list(p, v); 92 show_fiq_list(p, v);
90#endif 93#endif
@@ -112,7 +115,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
112 * Some hardware gives randomly wrong interrupts. Rather 115 * Some hardware gives randomly wrong interrupts. Rather
113 * than crashing, do something sensible. 116 * than crashing, do something sensible.
114 */ 117 */
115 if (unlikely(irq >= NR_IRQS)) { 118 if (unlikely(irq >= nr_irqs)) {
116 if (printk_ratelimit()) 119 if (printk_ratelimit())
117 printk(KERN_WARNING "Bad IRQ%u\n", irq); 120 printk(KERN_WARNING "Bad IRQ%u\n", irq);
118 ack_bad_irq(irq); 121 ack_bad_irq(irq);
@@ -132,12 +135,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
132 struct irq_desc *desc; 135 struct irq_desc *desc;
133 unsigned long flags; 136 unsigned long flags;
134 137
135 if (irq >= NR_IRQS) { 138 if (irq >= nr_irqs) {
136 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); 139 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
137 return; 140 return;
138 } 141 }
139 142
140 desc = irq_desc + irq; 143 desc = irq_to_desc(irq);
141 raw_spin_lock_irqsave(&desc->lock, flags); 144 raw_spin_lock_irqsave(&desc->lock, flags);
142 desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 145 desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
143 if (iflags & IRQF_VALID) 146 if (iflags & IRQF_VALID)
@@ -151,14 +154,25 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
151 154
152void __init init_IRQ(void) 155void __init init_IRQ(void)
153{ 156{
157 struct irq_desc *desc;
154 int irq; 158 int irq;
155 159
156 for (irq = 0; irq < NR_IRQS; irq++) 160 for (irq = 0; irq < nr_irqs; irq++) {
157 irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE; 161 desc = irq_to_desc_alloc_node(irq, 0);
162 desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
163 }
158 164
159 init_arch_irq(); 165 init_arch_irq();
160} 166}
161 167
168#ifdef CONFIG_SPARSE_IRQ
169int __init arch_probe_nr_irqs(void)
170{
171 nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
172 return 0;
173}
174#endif
175
162#ifdef CONFIG_HOTPLUG_CPU 176#ifdef CONFIG_HOTPLUG_CPU
163 177
164static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) 178static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
@@ -178,10 +192,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
178void migrate_irqs(void) 192void migrate_irqs(void)
179{ 193{
180 unsigned int i, cpu = smp_processor_id(); 194 unsigned int i, cpu = smp_processor_id();
195 struct irq_desc *desc;
181 196
182 for (i = 0; i < NR_IRQS; i++) { 197 for_each_irq_desc(i, desc) {
183 struct irq_desc *desc = irq_desc + i;
184
185 if (desc->node == cpu) { 198 if (desc->node == cpu) {
186 unsigned int newcpu = cpumask_any_and(desc->affinity, 199 unsigned int newcpu = cpumask_any_and(desc->affinity,
187 cpu_online_mask); 200 cpu_online_mask);
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 598ca61e7bca..1fc74cbd1a19 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -37,12 +37,12 @@ void machine_kexec_cleanup(struct kimage *image)
37{ 37{
38} 38}
39 39
40void machine_shutdown(void)
41{
42}
43
44void machine_crash_shutdown(struct pt_regs *regs) 40void machine_crash_shutdown(struct pt_regs *regs)
45{ 41{
42 local_irq_disable();
43 crash_save_cpu(regs, smp_processor_id());
44
45 printk(KERN_INFO "Loading crashdump kernel...\n");
46} 46}
47 47
48void machine_kexec(struct kimage *image) 48void machine_kexec(struct kimage *image)
@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image)
74 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); 74 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
75 printk(KERN_INFO "Bye!\n"); 75 printk(KERN_INFO "Bye!\n");
76 76
77 cpu_proc_fin(); 77 local_irq_disable();
78 local_fiq_disable();
78 setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ 79 setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
80 flush_cache_all();
81 cpu_proc_fin();
82 flush_cache_all();
79 cpu_reset(reboot_code_buffer_phys); 83 cpu_reset(reboot_code_buffer_phys);
80} 84}
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index a4a9cc88bec7..401e38be1f78 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -28,7 +28,9 @@
28#include <linux/tick.h> 28#include <linux/tick.h>
29#include <linux/utsname.h> 29#include <linux/utsname.h>
30#include <linux/uaccess.h> 30#include <linux/uaccess.h>
31#include <linux/random.h>
31 32
33#include <asm/cacheflush.h>
32#include <asm/leds.h> 34#include <asm/leds.h>
33#include <asm/processor.h> 35#include <asm/processor.h>
34#include <asm/system.h> 36#include <asm/system.h>
@@ -36,6 +38,12 @@
36#include <asm/stacktrace.h> 38#include <asm/stacktrace.h>
37#include <asm/mach/time.h> 39#include <asm/mach/time.h>
38 40
41#ifdef CONFIG_CC_STACKPROTECTOR
42#include <linux/stackprotector.h>
43unsigned long __stack_chk_guard __read_mostly;
44EXPORT_SYMBOL(__stack_chk_guard);
45#endif
46
39static const char *processor_modes[] = { 47static const char *processor_modes[] = {
40 "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , 48 "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
41 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", 49 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -84,10 +92,9 @@ __setup("hlt", hlt_setup);
84 92
85void arm_machine_restart(char mode, const char *cmd) 93void arm_machine_restart(char mode, const char *cmd)
86{ 94{
87 /* 95 /* Disable interrupts first */
88 * Clean and disable cache, and turn off interrupts 96 local_irq_disable();
89 */ 97 local_fiq_disable();
90 cpu_proc_fin();
91 98
92 /* 99 /*
93 * Tell the mm system that we are going to reboot - 100 * Tell the mm system that we are going to reboot -
@@ -96,6 +103,15 @@ void arm_machine_restart(char mode, const char *cmd)
96 */ 103 */
97 setup_mm_for_reboot(mode); 104 setup_mm_for_reboot(mode);
98 105
106 /* Clean and invalidate caches */
107 flush_cache_all();
108
109 /* Turn off caching */
110 cpu_proc_fin();
111
112 /* Push out any further dirty data, and ensure cache is empty */
113 flush_cache_all();
114
99 /* 115 /*
100 * Now call the architecture specific reboot code. 116 * Now call the architecture specific reboot code.
101 */ 117 */
@@ -189,19 +205,29 @@ int __init reboot_setup(char *str)
189 205
190__setup("reboot=", reboot_setup); 206__setup("reboot=", reboot_setup);
191 207
192void machine_halt(void) 208void machine_shutdown(void)
193{ 209{
210#ifdef CONFIG_SMP
211 smp_send_stop();
212#endif
194} 213}
195 214
215void machine_halt(void)
216{
217 machine_shutdown();
218 while (1);
219}
196 220
197void machine_power_off(void) 221void machine_power_off(void)
198{ 222{
223 machine_shutdown();
199 if (pm_power_off) 224 if (pm_power_off)
200 pm_power_off(); 225 pm_power_off();
201} 226}
202 227
203void machine_restart(char *cmd) 228void machine_restart(char *cmd)
204{ 229{
230 machine_shutdown();
205 arm_pm_restart(reboot_mode, cmd); 231 arm_pm_restart(reboot_mode, cmd);
206} 232}
207 233
@@ -426,3 +452,9 @@ unsigned long get_wchan(struct task_struct *p)
426 } while (count ++ < 16); 452 } while (count ++ < 16);
427 return 0; 453 return 0;
428} 454}
455
456unsigned long arch_randomize_brk(struct mm_struct *mm)
457{
458 unsigned long range_end = mm->brk + 0x02000000;
459 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
460}
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3f562a7c0a99..f99d489822d5 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -52,6 +52,102 @@
52#define BREAKINST_THUMB 0xde01 52#define BREAKINST_THUMB 0xde01
53#endif 53#endif
54 54
55struct pt_regs_offset {
56 const char *name;
57 int offset;
58};
59
60#define REG_OFFSET_NAME(r) \
61 {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
62#define REG_OFFSET_END {.name = NULL, .offset = 0}
63
64static const struct pt_regs_offset regoffset_table[] = {
65 REG_OFFSET_NAME(r0),
66 REG_OFFSET_NAME(r1),
67 REG_OFFSET_NAME(r2),
68 REG_OFFSET_NAME(r3),
69 REG_OFFSET_NAME(r4),
70 REG_OFFSET_NAME(r5),
71 REG_OFFSET_NAME(r6),
72 REG_OFFSET_NAME(r7),
73 REG_OFFSET_NAME(r8),
74 REG_OFFSET_NAME(r9),
75 REG_OFFSET_NAME(r10),
76 REG_OFFSET_NAME(fp),
77 REG_OFFSET_NAME(ip),
78 REG_OFFSET_NAME(sp),
79 REG_OFFSET_NAME(lr),
80 REG_OFFSET_NAME(pc),
81 REG_OFFSET_NAME(cpsr),
82 REG_OFFSET_NAME(ORIG_r0),
83 REG_OFFSET_END,
84};
85
86/**
87 * regs_query_register_offset() - query register offset from its name
88 * @name: the name of a register
89 *
90 * regs_query_register_offset() returns the offset of a register in struct
91 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
92 */
93int regs_query_register_offset(const char *name)
94{
95 const struct pt_regs_offset *roff;
96 for (roff = regoffset_table; roff->name != NULL; roff++)
97 if (!strcmp(roff->name, name))
98 return roff->offset;
99 return -EINVAL;
100}
101
102/**
103 * regs_query_register_name() - query register name from its offset
104 * @offset: the offset of a register in struct pt_regs.
105 *
106 * regs_query_register_name() returns the name of a register from its
107 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
108 */
109const char *regs_query_register_name(unsigned int offset)
110{
111 const struct pt_regs_offset *roff;
112 for (roff = regoffset_table; roff->name != NULL; roff++)
113 if (roff->offset == offset)
114 return roff->name;
115 return NULL;
116}
117
118/**
119 * regs_within_kernel_stack() - check the address in the stack
120 * @regs: pt_regs which contains kernel stack pointer.
121 * @addr: address which is checked.
122 *
123 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
124 * If @addr is within the kernel stack, it returns true. If not, returns false.
125 */
126bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
127{
128 return ((addr & ~(THREAD_SIZE - 1)) ==
129 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
130}
131
132/**
133 * regs_get_kernel_stack_nth() - get Nth entry of the stack
134 * @regs: pt_regs which contains kernel stack pointer.
135 * @n: stack entry number.
136 *
137 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
138 * is specified by @regs. If the @n th entry is NOT in the kernel stack,
139 * this returns 0.
140 */
141unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
142{
143 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
144 addr += n;
145 if (regs_within_kernel_stack(regs, (unsigned long)addr))
146 return *addr;
147 else
148 return 0;
149}
150
55/* 151/*
56 * this routine will get a word off of the processes privileged stack. 152 * this routine will get a word off of the processes privileged stack.
57 * the offset is how far from the base addr as stored in the THREAD. 153 * the offset is how far from the base addr as stored in the THREAD.
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 61930eb09029..fd26f8d65151 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -10,6 +10,12 @@ relocate_new_kernel:
10 ldr r0,kexec_indirection_page 10 ldr r0,kexec_indirection_page
11 ldr r1,kexec_start_address 11 ldr r1,kexec_start_address
12 12
13 /*
14 * If there is no indirection page (we are doing crashdumps)
15 * skip any relocation.
16 */
17 cmp r0, #0
18 beq 2f
13 19
140: /* top, read another word for the indirection page */ 200: /* top, read another word for the indirection page */
15 ldr r3, [r0],#4 21 ldr r3, [r0],#4
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999bdc7c..d5231ae7355a 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -19,12 +19,15 @@
19#include <linux/seq_file.h> 19#include <linux/seq_file.h>
20#include <linux/screen_info.h> 20#include <linux/screen_info.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kexec.h>
23#include <linux/crash_dump.h>
22#include <linux/root_dev.h> 24#include <linux/root_dev.h>
23#include <linux/cpu.h> 25#include <linux/cpu.h>
24#include <linux/interrupt.h> 26#include <linux/interrupt.h>
25#include <linux/smp.h> 27#include <linux/smp.h>
26#include <linux/fs.h> 28#include <linux/fs.h>
27#include <linux/proc_fs.h> 29#include <linux/proc_fs.h>
30#include <linux/memblock.h>
28 31
29#include <asm/unified.h> 32#include <asm/unified.h>
30#include <asm/cpu.h> 33#include <asm/cpu.h>
@@ -44,7 +47,9 @@
44#include <asm/traps.h> 47#include <asm/traps.h>
45#include <asm/unwind.h> 48#include <asm/unwind.h>
46 49
50#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
47#include "compat.h" 51#include "compat.h"
52#endif
48#include "atags.h" 53#include "atags.h"
49#include "tcm.h" 54#include "tcm.h"
50 55
@@ -269,6 +274,21 @@ static void __init cacheid_init(void)
269extern struct proc_info_list *lookup_processor_type(unsigned int); 274extern struct proc_info_list *lookup_processor_type(unsigned int);
270extern struct machine_desc *lookup_machine_type(unsigned int); 275extern struct machine_desc *lookup_machine_type(unsigned int);
271 276
277static void __init feat_v6_fixup(void)
278{
279 int id = read_cpuid_id();
280
281 if ((id & 0xff0f0000) != 0x41070000)
282 return;
283
284 /*
285 * HWCAP_TLS is available only on 1136 r1p0 and later,
286 * see also kuser_get_tls_init.
287 */
288 if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
289 elf_hwcap &= ~HWCAP_TLS;
290}
291
272static void __init setup_processor(void) 292static void __init setup_processor(void)
273{ 293{
274 struct proc_info_list *list; 294 struct proc_info_list *list;
@@ -311,6 +331,8 @@ static void __init setup_processor(void)
311 elf_hwcap &= ~HWCAP_THUMB; 331 elf_hwcap &= ~HWCAP_THUMB;
312#endif 332#endif
313 333
334 feat_v6_fixup();
335
314 cacheid_init(); 336 cacheid_init();
315 cpu_proc_init(); 337 cpu_proc_init();
316} 338}
@@ -402,13 +424,12 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
402 size -= start & ~PAGE_MASK; 424 size -= start & ~PAGE_MASK;
403 bank->start = PAGE_ALIGN(start); 425 bank->start = PAGE_ALIGN(start);
404 bank->size = size & PAGE_MASK; 426 bank->size = size & PAGE_MASK;
405 bank->node = PHYS_TO_NID(start);
406 427
407 /* 428 /*
408 * Check whether this memory region has non-zero size or 429 * Check whether this memory region has non-zero size or
409 * invalid node number. 430 * invalid node number.
410 */ 431 */
411 if (bank->size == 0 || bank->node >= MAX_NUMNODES) 432 if (bank->size == 0)
412 return -EINVAL; 433 return -EINVAL;
413 434
414 meminfo.nr_banks++; 435 meminfo.nr_banks++;
@@ -663,6 +684,86 @@ static int __init customize_machine(void)
663} 684}
664arch_initcall(customize_machine); 685arch_initcall(customize_machine);
665 686
687#ifdef CONFIG_KEXEC
688static inline unsigned long long get_total_mem(void)
689{
690 unsigned long total;
691
692 total = max_low_pfn - min_low_pfn;
693 return total << PAGE_SHIFT;
694}
695
696/**
697 * reserve_crashkernel() - reserves memory are for crash kernel
698 *
699 * This function reserves memory area given in "crashkernel=" kernel command
700 * line parameter. The memory reserved is used by a dump capture kernel when
701 * primary kernel is crashing.
702 */
703static void __init reserve_crashkernel(void)
704{
705 unsigned long long crash_size, crash_base;
706 unsigned long long total_mem;
707 int ret;
708
709 total_mem = get_total_mem();
710 ret = parse_crashkernel(boot_command_line, total_mem,
711 &crash_size, &crash_base);
712 if (ret)
713 return;
714
715 ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
716 if (ret < 0) {
717 printk(KERN_WARNING "crashkernel reservation failed - "
718 "memory is in use (0x%lx)\n", (unsigned long)crash_base);
719 return;
720 }
721
722 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
723 "for crashkernel (System RAM: %ldMB)\n",
724 (unsigned long)(crash_size >> 20),
725 (unsigned long)(crash_base >> 20),
726 (unsigned long)(total_mem >> 20));
727
728 crashk_res.start = crash_base;
729 crashk_res.end = crash_base + crash_size - 1;
730 insert_resource(&iomem_resource, &crashk_res);
731}
732#else
733static inline void reserve_crashkernel(void) {}
734#endif /* CONFIG_KEXEC */
735
736/*
737 * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
738 * is_kdump_kernel() to determine if we are booting after a panic. Hence
739 * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
740 */
741
742#ifdef CONFIG_CRASH_DUMP
743/*
744 * elfcorehdr= specifies the location of elf core header stored by the crashed
745 * kernel. This option will be passed by kexec loader to the capture kernel.
746 */
747static int __init setup_elfcorehdr(char *arg)
748{
749 char *end;
750
751 if (!arg)
752 return -EINVAL;
753
754 elfcorehdr_addr = memparse(arg, &end);
755 return end > arg ? 0 : -EINVAL;
756}
757early_param("elfcorehdr", setup_elfcorehdr);
758#endif /* CONFIG_CRASH_DUMP */
759
760static void __init squash_mem_tags(struct tag *tag)
761{
762 for (; tag->hdr.size; tag = tag_next(tag))
763 if (tag->hdr.tag == ATAG_MEM)
764 tag->hdr.tag = ATAG_NONE;
765}
766
666void __init setup_arch(char **cmdline_p) 767void __init setup_arch(char **cmdline_p)
667{ 768{
668 struct tag *tags = (struct tag *)&init_tags; 769 struct tag *tags = (struct tag *)&init_tags;
@@ -683,12 +784,14 @@ void __init setup_arch(char **cmdline_p)
683 else if (mdesc->boot_params) 784 else if (mdesc->boot_params)
684 tags = phys_to_virt(mdesc->boot_params); 785 tags = phys_to_virt(mdesc->boot_params);
685 786
787#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
686 /* 788 /*
687 * If we have the old style parameters, convert them to 789 * If we have the old style parameters, convert them to
688 * a tag list. 790 * a tag list.
689 */ 791 */
690 if (tags->hdr.tag != ATAG_CORE) 792 if (tags->hdr.tag != ATAG_CORE)
691 convert_to_tag_list(tags); 793 convert_to_tag_list(tags);
794#endif
692 if (tags->hdr.tag != ATAG_CORE) 795 if (tags->hdr.tag != ATAG_CORE)
693 tags = (struct tag *)&init_tags; 796 tags = (struct tag *)&init_tags;
694 797
@@ -716,12 +819,15 @@ void __init setup_arch(char **cmdline_p)
716 819
717 parse_early_param(); 820 parse_early_param();
718 821
822 arm_memblock_init(&meminfo, mdesc);
823
719 paging_init(mdesc); 824 paging_init(mdesc);
720 request_standard_resources(&meminfo, mdesc); 825 request_standard_resources(&meminfo, mdesc);
721 826
722#ifdef CONFIG_SMP 827#ifdef CONFIG_SMP
723 smp_init_cpus(); 828 smp_init_cpus();
724#endif 829#endif
830 reserve_crashkernel();
725 831
726 cpu_init(); 832 cpu_init();
727 tcm_init(); 833 tcm_init();
@@ -729,6 +835,7 @@ void __init setup_arch(char **cmdline_p)
729 /* 835 /*
730 * Set up various architecture-specific pointers 836 * Set up various architecture-specific pointers
731 */ 837 */
838 arch_nr_irqs = mdesc->nr_irqs;
732 init_arch_irq = mdesc->init_irq; 839 init_arch_irq = mdesc->init_irq;
733 system_timer = mdesc->timer; 840 system_timer = mdesc->timer;
734 init_machine = mdesc->init_machine; 841 init_machine = mdesc->init_machine;
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index b8c3d0f689d9..40dc74f2b27f 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -429,7 +429,11 @@ static void smp_timer_broadcast(const struct cpumask *mask)
429{ 429{
430 send_ipi_message(mask, IPI_TIMER); 430 send_ipi_message(mask, IPI_TIMER);
431} 431}
432#else
433#define smp_timer_broadcast NULL
434#endif
432 435
436#ifndef CONFIG_LOCAL_TIMERS
433static void broadcast_timer_set_mode(enum clock_event_mode mode, 437static void broadcast_timer_set_mode(enum clock_event_mode mode,
434 struct clock_event_device *evt) 438 struct clock_event_device *evt)
435{ 439{
@@ -444,7 +448,6 @@ static void local_timer_setup(struct clock_event_device *evt)
444 evt->rating = 400; 448 evt->rating = 400;
445 evt->mult = 1; 449 evt->mult = 1;
446 evt->set_mode = broadcast_timer_set_mode; 450 evt->set_mode = broadcast_timer_set_mode;
447 evt->broadcast = smp_timer_broadcast;
448 451
449 clockevents_register_device(evt); 452 clockevents_register_device(evt);
450} 453}
@@ -456,6 +459,7 @@ void __cpuinit percpu_timer_setup(void)
456 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); 459 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
457 460
458 evt->cpumask = cpumask_of(cpu); 461 evt->cpumask = cpumask_of(cpu);
462 evt->broadcast = smp_timer_broadcast;
459 463
460 local_timer_setup(evt); 464 local_timer_setup(evt);
461} 465}
@@ -467,10 +471,13 @@ static DEFINE_SPINLOCK(stop_lock);
467 */ 471 */
468static void ipi_cpu_stop(unsigned int cpu) 472static void ipi_cpu_stop(unsigned int cpu)
469{ 473{
470 spin_lock(&stop_lock); 474 if (system_state == SYSTEM_BOOTING ||
471 printk(KERN_CRIT "CPU%u: stopping\n", cpu); 475 system_state == SYSTEM_RUNNING) {
472 dump_stack(); 476 spin_lock(&stop_lock);
473 spin_unlock(&stop_lock); 477 printk(KERN_CRIT "CPU%u: stopping\n", cpu);
478 dump_stack();
479 spin_unlock(&stop_lock);
480 }
474 481
475 set_cpu_online(cpu, false); 482 set_cpu_online(cpu, false);
476 483
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 7c5f0c024db7..35882fbf37f9 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -132,7 +132,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
132 twd_calibrate_rate(); 132 twd_calibrate_rate();
133 133
134 clk->name = "local_timer"; 134 clk->name = "local_timer";
135 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 135 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
136 CLOCK_EVT_FEAT_C3STOP;
136 clk->rating = 350; 137 clk->rating = 350;
137 clk->set_mode = twd_set_mode; 138 clk->set_mode = twd_set_mode;
138 clk->set_next_event = twd_set_next_event; 139 clk->set_next_event = twd_set_next_event;
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index e50303868f1b..26685c2f7a49 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -13,38 +13,35 @@
13#include <linux/ioport.h> 13#include <linux/ioport.h>
14#include <linux/genalloc.h> 14#include <linux/genalloc.h>
15#include <linux/string.h> /* memcpy */ 15#include <linux/string.h> /* memcpy */
16#include <asm/page.h> /* PAGE_SHIFT */
17#include <asm/cputype.h> 16#include <asm/cputype.h>
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
19#include <mach/memory.h> 18#include <mach/memory.h>
20#include "tcm.h" 19#include "tcm.h"
21 20
22/* Scream and warn about misuse */
23#if !defined(ITCM_OFFSET) || !defined(ITCM_END) || \
24 !defined(DTCM_OFFSET) || !defined(DTCM_END)
25#error "TCM support selected but offsets not defined!"
26#endif
27
28static struct gen_pool *tcm_pool; 21static struct gen_pool *tcm_pool;
29 22
30/* TCM section definitions from the linker */ 23/* TCM section definitions from the linker */
31extern char __itcm_start, __sitcm_text, __eitcm_text; 24extern char __itcm_start, __sitcm_text, __eitcm_text;
32extern char __dtcm_start, __sdtcm_data, __edtcm_data; 25extern char __dtcm_start, __sdtcm_data, __edtcm_data;
33 26
27/* These will be increased as we run */
28u32 dtcm_end = DTCM_OFFSET;
29u32 itcm_end = ITCM_OFFSET;
30
34/* 31/*
35 * TCM memory resources 32 * TCM memory resources
36 */ 33 */
37static struct resource dtcm_res = { 34static struct resource dtcm_res = {
38 .name = "DTCM RAM", 35 .name = "DTCM RAM",
39 .start = DTCM_OFFSET, 36 .start = DTCM_OFFSET,
40 .end = DTCM_END, 37 .end = DTCM_OFFSET,
41 .flags = IORESOURCE_MEM 38 .flags = IORESOURCE_MEM
42}; 39};
43 40
44static struct resource itcm_res = { 41static struct resource itcm_res = {
45 .name = "ITCM RAM", 42 .name = "ITCM RAM",
46 .start = ITCM_OFFSET, 43 .start = ITCM_OFFSET,
47 .end = ITCM_END, 44 .end = ITCM_OFFSET,
48 .flags = IORESOURCE_MEM 45 .flags = IORESOURCE_MEM
49}; 46};
50 47
@@ -52,8 +49,8 @@ static struct map_desc dtcm_iomap[] __initdata = {
52 { 49 {
53 .virtual = DTCM_OFFSET, 50 .virtual = DTCM_OFFSET,
54 .pfn = __phys_to_pfn(DTCM_OFFSET), 51 .pfn = __phys_to_pfn(DTCM_OFFSET),
55 .length = (DTCM_END - DTCM_OFFSET + 1), 52 .length = 0,
56 .type = MT_UNCACHED 53 .type = MT_MEMORY_DTCM
57 } 54 }
58}; 55};
59 56
@@ -61,8 +58,8 @@ static struct map_desc itcm_iomap[] __initdata = {
61 { 58 {
62 .virtual = ITCM_OFFSET, 59 .virtual = ITCM_OFFSET,
63 .pfn = __phys_to_pfn(ITCM_OFFSET), 60 .pfn = __phys_to_pfn(ITCM_OFFSET),
64 .length = (ITCM_END - ITCM_OFFSET + 1), 61 .length = 0,
65 .type = MT_UNCACHED 62 .type = MT_MEMORY_ITCM
66 } 63 }
67}; 64};
68 65
@@ -93,14 +90,24 @@ void tcm_free(void *addr, size_t len)
93} 90}
94EXPORT_SYMBOL(tcm_free); 91EXPORT_SYMBOL(tcm_free);
95 92
96 93static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
97static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size) 94 u32 *offset)
98{ 95{
99 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, 96 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
100 256, 512, 1024, -1, -1, -1, -1 }; 97 256, 512, 1024, -1, -1, -1, -1 };
101 u32 tcm_region; 98 u32 tcm_region;
102 int tcm_size; 99 int tcm_size;
103 100
101 /*
102 * If there are more than one TCM bank of this type,
103 * select the TCM bank to operate on in the TCM selection
104 * register.
105 */
106 if (banks > 1)
107 asm("mcr p15, 0, %0, c9, c2, 0"
108 : /* No output operands */
109 : "r" (bank));
110
104 /* Read the special TCM region register c9, 0 */ 111 /* Read the special TCM region register c9, 0 */
105 if (!type) 112 if (!type)
106 asm("mrc p15, 0, %0, c9, c1, 0" 113 asm("mrc p15, 0, %0, c9, c1, 0"
@@ -111,26 +118,24 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
111 118
112 tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f]; 119 tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
113 if (tcm_size < 0) { 120 if (tcm_size < 0) {
114 pr_err("CPU: %sTCM of unknown size!\n", 121 pr_err("CPU: %sTCM%d of unknown size\n",
115 type ? "I" : "D"); 122 type ? "I" : "D", bank);
123 return -EINVAL;
124 } else if (tcm_size > 32) {
125 pr_err("CPU: %sTCM%d larger than 32k found\n",
126 type ? "I" : "D", bank);
127 return -EINVAL;
116 } else { 128 } else {
117 pr_info("CPU: found %sTCM %dk @ %08x, %senabled\n", 129 pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
118 type ? "I" : "D", 130 type ? "I" : "D",
131 bank,
119 tcm_size, 132 tcm_size,
120 (tcm_region & 0xfffff000U), 133 (tcm_region & 0xfffff000U),
121 (tcm_region & 1) ? "" : "not "); 134 (tcm_region & 1) ? "" : "not ");
122 } 135 }
123 136
124 if (tcm_size != expected_size) {
125 pr_crit("CPU: %sTCM was detected %dk but expected %dk!\n",
126 type ? "I" : "D",
127 tcm_size,
128 expected_size);
129 /* Adjust to the expected size? what can we do... */
130 }
131
132 /* Force move the TCM bank to where we want it, enable */ 137 /* Force move the TCM bank to where we want it, enable */
133 tcm_region = offset | (tcm_region & 0x00000ffeU) | 1; 138 tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
134 139
135 if (!type) 140 if (!type)
136 asm("mcr p15, 0, %0, c9, c1, 0" 141 asm("mcr p15, 0, %0, c9, c1, 0"
@@ -141,10 +146,15 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
141 : /* No output operands */ 146 : /* No output operands */
142 : "r" (tcm_region)); 147 : "r" (tcm_region));
143 148
144 pr_debug("CPU: moved %sTCM %dk to %08x, enabled\n", 149 /* Increase offset */
145 type ? "I" : "D", 150 *offset += (tcm_size << 10);
146 tcm_size, 151
147 (tcm_region & 0xfffff000U)); 152 pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
153 type ? "I" : "D",
154 bank,
155 tcm_size,
156 (tcm_region & 0xfffff000U));
157 return 0;
148} 158}
149 159
150/* 160/*
@@ -153,34 +163,52 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
153void __init tcm_init(void) 163void __init tcm_init(void)
154{ 164{
155 u32 tcm_status = read_cpuid_tcmstatus(); 165 u32 tcm_status = read_cpuid_tcmstatus();
166 u8 dtcm_banks = (tcm_status >> 16) & 0x03;
167 u8 itcm_banks = (tcm_status & 0x03);
156 char *start; 168 char *start;
157 char *end; 169 char *end;
158 char *ram; 170 char *ram;
171 int ret;
172 int i;
159 173
160 /* Setup DTCM if present */ 174 /* Setup DTCM if present */
161 if (tcm_status & (1 << 16)) { 175 if (dtcm_banks > 0) {
162 setup_tcm_bank(0, DTCM_OFFSET, 176 for (i = 0; i < dtcm_banks; i++) {
163 (DTCM_END - DTCM_OFFSET + 1) >> 10); 177 ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
178 if (ret)
179 return;
180 }
181 dtcm_res.end = dtcm_end - 1;
164 request_resource(&iomem_resource, &dtcm_res); 182 request_resource(&iomem_resource, &dtcm_res);
183 dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
165 iotable_init(dtcm_iomap, 1); 184 iotable_init(dtcm_iomap, 1);
166 /* Copy data from RAM to DTCM */ 185 /* Copy data from RAM to DTCM */
167 start = &__sdtcm_data; 186 start = &__sdtcm_data;
168 end = &__edtcm_data; 187 end = &__edtcm_data;
169 ram = &__dtcm_start; 188 ram = &__dtcm_start;
189 /* This means you compiled more code than fits into DTCM */
190 BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET));
170 memcpy(start, ram, (end-start)); 191 memcpy(start, ram, (end-start));
171 pr_debug("CPU DTCM: copied data from %p - %p\n", start, end); 192 pr_debug("CPU DTCM: copied data from %p - %p\n", start, end);
172 } 193 }
173 194
174 /* Setup ITCM if present */ 195 /* Setup ITCM if present */
175 if (tcm_status & 1) { 196 if (itcm_banks > 0) {
176 setup_tcm_bank(1, ITCM_OFFSET, 197 for (i = 0; i < itcm_banks; i++) {
177 (ITCM_END - ITCM_OFFSET + 1) >> 10); 198 ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
199 if (ret)
200 return;
201 }
202 itcm_res.end = itcm_end - 1;
178 request_resource(&iomem_resource, &itcm_res); 203 request_resource(&iomem_resource, &itcm_res);
204 itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
179 iotable_init(itcm_iomap, 1); 205 iotable_init(itcm_iomap, 1);
180 /* Copy code from RAM to ITCM */ 206 /* Copy code from RAM to ITCM */
181 start = &__sitcm_text; 207 start = &__sitcm_text;
182 end = &__eitcm_text; 208 end = &__eitcm_text;
183 ram = &__itcm_start; 209 ram = &__itcm_start;
210 /* This means you compiled more code than fits into ITCM */
211 BUG_ON((end - start) > (itcm_end - ITCM_OFFSET));
184 memcpy(start, ram, (end-start)); 212 memcpy(start, ram, (end-start));
185 pr_debug("CPU ITCM: copied code from %p - %p\n", start, end); 213 pr_debug("CPU ITCM: copied code from %p - %p\n", start, end);
186 } 214 }
@@ -208,10 +236,10 @@ static int __init setup_tcm_pool(void)
208 pr_debug("Setting up TCM memory pool\n"); 236 pr_debug("Setting up TCM memory pool\n");
209 237
210 /* Add the rest of DTCM to the TCM pool */ 238 /* Add the rest of DTCM to the TCM pool */
211 if (tcm_status & (1 << 16)) { 239 if (tcm_status & (0x03 << 16)) {
212 if (dtcm_pool_start < DTCM_END) { 240 if (dtcm_pool_start < dtcm_end) {
213 ret = gen_pool_add(tcm_pool, dtcm_pool_start, 241 ret = gen_pool_add(tcm_pool, dtcm_pool_start,
214 DTCM_END - dtcm_pool_start + 1, -1); 242 dtcm_end - dtcm_pool_start, -1);
215 if (ret) { 243 if (ret) {
216 pr_err("CPU DTCM: could not add DTCM " \ 244 pr_err("CPU DTCM: could not add DTCM " \
217 "remainder to pool!\n"); 245 "remainder to pool!\n");
@@ -219,16 +247,16 @@ static int __init setup_tcm_pool(void)
219 } 247 }
220 pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \ 248 pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
221 "the TCM memory pool\n", 249 "the TCM memory pool\n",
222 DTCM_END - dtcm_pool_start + 1, 250 dtcm_end - dtcm_pool_start,
223 dtcm_pool_start); 251 dtcm_pool_start);
224 } 252 }
225 } 253 }
226 254
227 /* Add the rest of ITCM to the TCM pool */ 255 /* Add the rest of ITCM to the TCM pool */
228 if (tcm_status & 1) { 256 if (tcm_status & 0x03) {
229 if (itcm_pool_start < ITCM_END) { 257 if (itcm_pool_start < itcm_end) {
230 ret = gen_pool_add(tcm_pool, itcm_pool_start, 258 ret = gen_pool_add(tcm_pool, itcm_pool_start,
231 ITCM_END - itcm_pool_start + 1, -1); 259 itcm_end - itcm_pool_start, -1);
232 if (ret) { 260 if (ret) {
233 pr_err("CPU ITCM: could not add ITCM " \ 261 pr_err("CPU ITCM: could not add ITCM " \
234 "remainder to pool!\n"); 262 "remainder to pool!\n");
@@ -236,7 +264,7 @@ static int __init setup_tcm_pool(void)
236 } 264 }
237 pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \ 265 pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
238 "the TCM memory pool\n", 266 "the TCM memory pool\n",
239 ITCM_END - itcm_pool_start + 1, 267 itcm_end - itcm_pool_start,
240 itcm_pool_start); 268 itcm_pool_start);
241 } 269 }
242 } 270 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e5327b2a..cda78d59aa31 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -30,6 +30,7 @@
30#include <asm/unistd.h> 30#include <asm/unistd.h>
31#include <asm/traps.h> 31#include <asm/traps.h>
32#include <asm/unwind.h> 32#include <asm/unwind.h>
33#include <asm/tls.h>
33 34
34#include "ptrace.h" 35#include "ptrace.h"
35#include "signal.h" 36#include "signal.h"
@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
518 519
519 case NR(set_tls): 520 case NR(set_tls):
520 thread->tp_value = regs->ARM_r0; 521 thread->tp_value = regs->ARM_r0;
521#if defined(CONFIG_HAS_TLS_REG) 522 if (tls_emu)
522 asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) ); 523 return 0;
523#elif !defined(CONFIG_TLS_REG_EMUL) 524 if (has_tls_reg) {
524 /* 525 asm ("mcr p15, 0, %0, c13, c0, 3"
525 * User space must never try to access this directly. 526 : : "r" (regs->ARM_r0));
526 * Expect your app to break eventually if you do so. 527 } else {
527 * The user helper at 0xffff0fe0 must be used instead. 528 /*
528 * (see entry-armv.S for details) 529 * User space must never try to access this directly.
529 */ 530 * Expect your app to break eventually if you do so.
530 *((unsigned int *)0xffff0ff0) = regs->ARM_r0; 531 * The user helper at 0xffff0fe0 must be used instead.
531#endif 532 * (see entry-armv.S for details)
533 */
534 *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
535 }
532 return 0; 536 return 0;
533 537
534#ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG 538#ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
@@ -743,6 +747,16 @@ void __init trap_init(void)
743 return; 747 return;
744} 748}
745 749
750static void __init kuser_get_tls_init(unsigned long vectors)
751{
752 /*
753 * vectors + 0xfe0 = __kuser_get_tls
754 * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
755 */
756 if (tls_emu || has_tls_reg)
757 memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
758}
759
746void __init early_trap_init(void) 760void __init early_trap_init(void)
747{ 761{
748 unsigned long vectors = CONFIG_VECTORS_BASE; 762 unsigned long vectors = CONFIG_VECTORS_BASE;
@@ -761,6 +775,11 @@ void __init early_trap_init(void)
761 memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz); 775 memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
762 776
763 /* 777 /*
778 * Do processor specific fixups for the kuser helpers
779 */
780 kuser_get_tls_init(vectors);
781
782 /*
764 * Copy signal return handlers into the vector page, and 783 * Copy signal return handlers into the vector page, and
765 * set sigreturn to be a pointer to these. 784 * set sigreturn to be a pointer to these.
766 */ 785 */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 030ba7219f48..59ff42ddf0ae 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -41,7 +41,6 @@ else
41endif 41endif
42 42
43lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o 43lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
44lib-$(CONFIG_ARCH_L7200) += io-acorn.o
45lib-$(CONFIG_ARCH_SHARK) += io-shark.o 44lib-$(CONFIG_ARCH_SHARK) += io-shark.o
46 45
47$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S 46$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h
index c00822543d9f..4f93c567a35a 100644
--- a/arch/arm/mach-aaec2000/include/mach/memory.h
+++ b/arch/arm/mach-aaec2000/include/mach/memory.h
@@ -14,14 +14,4 @@
14 14
15#define PHYS_OFFSET UL(0xf0000000) 15#define PHYS_OFFSET UL(0xf0000000)
16 16
17/*
18 * The nodes are the followings:
19 *
20 * node 0: 0xf000.0000 - 0xf3ff.ffff
21 * node 1: 0xf400.0000 - 0xf7ff.ffff
22 * node 2: 0xf800.0000 - 0xfbff.ffff
23 * node 3: 0xfc00.0000 - 0xffff.ffff
24 */
25#define NODE_MEM_SIZE_BITS 26
26
27#endif /* __ASM_ARCH_MEMORY_H */ 17#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 841eaf8f27e2..939bccd70569 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
366 366
367endif 367endif
368 368
369if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
370comment "AT91SAM9260/AT91SAM9G20 boards"
371
372config MACH_SNAPPER_9260
373 bool "Bluewater Systems Snapper 9260/9G20 module"
374 help
375 Select this if you are using the Bluewater Systems Snapper 9260 or
376 Snapper 9G20 modules.
377 <http://www.bluewatersys.com/>
378endif
379
369# ---------------------------------------------------------- 380# ----------------------------------------------------------
370 381
371if ARCH_AT91SAM9G45 382if ARCH_AT91SAM9G45
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1f821e58222..ca2ac003f41f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o 66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
68 68
69# AT91SAM9260/AT91SAM9G20 board-specific support
70obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
71
69# AT91SAM9G45 board-specific support 72# AT91SAM9G45 board-specific support
70obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o 73obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
71 74
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 85166b7e69a1..753c0d31a3d3 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,6 +20,7 @@
20#include <mach/at91_pmc.h> 20#include <mach/at91_pmc.h>
21#include <mach/at91_rstc.h> 21#include <mach/at91_rstc.h>
22#include <mach/at91_shdwc.h> 22#include <mach/at91_shdwc.h>
23#include <mach/cpu.h>
23 24
24#include "generic.h" 25#include "generic.h"
25#include "clock.h" 26#include "clock.h"
@@ -176,6 +177,13 @@ static struct clk mmc1_clk = {
176 .type = CLK_TYPE_PERIPHERAL, 177 .type = CLK_TYPE_PERIPHERAL,
177}; 178};
178 179
180/* Video decoder clock - Only for sam9m10/sam9m11 */
181static struct clk vdec_clk = {
182 .name = "vdec_clk",
183 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
184 .type = CLK_TYPE_PERIPHERAL,
185};
186
179/* One additional fake clock for ohci */ 187/* One additional fake clock for ohci */
180static struct clk ohci_clk = { 188static struct clk ohci_clk = {
181 .name = "ohci_clk", 189 .name = "ohci_clk",
@@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void)
239 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) 247 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
240 clk_register(periph_clocks[i]); 248 clk_register(periph_clocks[i]);
241 249
250 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
251 clk_register(&vdec_clk);
252
242 clk_register(&pck0); 253 clk_register(&pck0);
243 clk_register(&pck1); 254 clk_register(&pck1);
244} 255}
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
index a4102d72cc9b..c49f5c003ee1 100644
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
@@ -26,6 +26,9 @@
26#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
27#include <linux/spi/at73c213.h> 27#include <linux/spi/at73c213.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/fixed.h>
31#include <linux/regulator/consumer.h>
29 32
30#include <mach/hardware.h> 33#include <mach/hardware.h>
31#include <asm/setup.h> 34#include <asm/setup.h>
@@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = {
235 } 238 }
236}; 239};
237 240
241#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
242static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
243 REGULATOR_SUPPLY("AVDD", "0-001b"),
244 REGULATOR_SUPPLY("HPVDD", "0-001b"),
245 REGULATOR_SUPPLY("DBVDD", "0-001b"),
246 REGULATOR_SUPPLY("DCVDD", "0-001b"),
247};
248
249static struct regulator_init_data ek_avdd_reg_init_data = {
250 .constraints = {
251 .name = "3V3",
252 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
253 },
254 .consumer_supplies = ek_audio_consumer_supplies,
255 .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
256};
257
258static struct fixed_voltage_config ek_vdd_pdata = {
259 .supply_name = "board-3V3",
260 .microvolts = 3300000,
261 .gpio = -EINVAL,
262 .enabled_at_boot = 0,
263 .init_data = &ek_avdd_reg_init_data,
264};
265static struct platform_device ek_voltage_regulator = {
266 .name = "reg-fixed-voltage",
267 .id = -1,
268 .num_resources = 0,
269 .dev = {
270 .platform_data = &ek_vdd_pdata,
271 },
272};
273static void __init ek_add_regulators(void)
274{
275 platform_device_register(&ek_voltage_regulator);
276}
277#else
278static void __init ek_add_regulators(void) {}
279#endif
280
238static struct i2c_board_info __initdata ek_i2c_devices[] = { 281static struct i2c_board_info __initdata ek_i2c_devices[] = {
239 { 282 {
240 I2C_BOARD_INFO("24c512", 0x50), 283 I2C_BOARD_INFO("24c512", 0x50),
@@ -256,6 +299,8 @@ static void __init ek_board_init(void)
256 ek_add_device_nand(); 299 ek_add_device_nand();
257 /* Ethernet */ 300 /* Ethernet */
258 at91_add_device_eth(&ek_macb_data); 301 at91_add_device_eth(&ek_macb_data);
302 /* Regulators */
303 ek_add_regulators();
259 /* MMC */ 304 /* MMC */
260#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) 305#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
261 at91_add_device_mci(0, &ek_mmc_data); 306 at91_add_device_mci(0, &ek_mmc_data);
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index c11fd47aec5d..6ea9808b8868 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -27,6 +27,9 @@
27#include <linux/gpio_keys.h> 27#include <linux/gpio_keys.h>
28#include <linux/input.h> 28#include <linux/input.h>
29#include <linux/clk.h> 29#include <linux/clk.h>
30#include <linux/regulator/machine.h>
31#include <linux/regulator/fixed.h>
32#include <linux/regulator/consumer.h>
30 33
31#include <mach/hardware.h> 34#include <mach/hardware.h>
32#include <asm/setup.h> 35#include <asm/setup.h>
@@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void)
269static void __init ek_add_device_buttons(void) {} 272static void __init ek_add_device_buttons(void) {}
270#endif 273#endif
271 274
275#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
276static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
277 REGULATOR_SUPPLY("AVDD", "0-001b"),
278 REGULATOR_SUPPLY("HPVDD", "0-001b"),
279 REGULATOR_SUPPLY("DBVDD", "0-001b"),
280 REGULATOR_SUPPLY("DCVDD", "0-001b"),
281};
282
283static struct regulator_init_data ek_avdd_reg_init_data = {
284 .constraints = {
285 .name = "3V3",
286 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
287 },
288 .consumer_supplies = ek_audio_consumer_supplies,
289 .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
290};
291
292static struct fixed_voltage_config ek_vdd_pdata = {
293 .supply_name = "board-3V3",
294 .microvolts = 3300000,
295 .gpio = -EINVAL,
296 .enabled_at_boot = 0,
297 .init_data = &ek_avdd_reg_init_data,
298};
299static struct platform_device ek_voltage_regulator = {
300 .name = "reg-fixed-voltage",
301 .id = -1,
302 .num_resources = 0,
303 .dev = {
304 .platform_data = &ek_vdd_pdata,
305 },
306};
307static void __init ek_add_regulators(void)
308{
309 platform_device_register(&ek_voltage_regulator);
310}
311#else
312static void __init ek_add_regulators(void) {}
313#endif
314
272 315
273static struct i2c_board_info __initdata ek_i2c_devices[] = { 316static struct i2c_board_info __initdata ek_i2c_devices[] = {
274 { 317 {
@@ -294,6 +337,8 @@ static void __init ek_board_init(void)
294 ek_add_device_nand(); 337 ek_add_device_nand();
295 /* Ethernet */ 338 /* Ethernet */
296 at91_add_device_eth(&ek_macb_data); 339 at91_add_device_eth(&ek_macb_data);
340 /* Regulators */
341 ek_add_regulators();
297 /* MMC */ 342 /* MMC */
298 at91_add_device_mmc(0, &ek_mmc_data); 343 at91_add_device_mmc(0, &ek_mmc_data);
299 /* I2C */ 344 /* I2C */
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644
index 000000000000..2c08ae4ad3a1
--- /dev/null
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -0,0 +1,189 @@
1/*
2 * linux/arch/arm/mach-at91/board-snapper9260.c
3 *
4 * Copyright (C) 2010 Bluewater System Ltd
5 *
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/gpio.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/i2c/pca953x.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33
34#include <mach/hardware.h>
35#include <mach/board.h>
36#include <mach/at91sam9_smc.h>
37
38#include "sam9_smc.h"
39#include "generic.h"
40
41#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x))
42
43static void __init snapper9260_map_io(void)
44{
45 at91sam9260_initialize(18432000);
46
47 /* Debug on ttyS0 */
48 at91_register_uart(0, 0, 0);
49 at91_set_serial_console(0);
50
51 at91_register_uart(AT91SAM9260_ID_US0, 1,
52 ATMEL_UART_CTS | ATMEL_UART_RTS);
53 at91_register_uart(AT91SAM9260_ID_US1, 2,
54 ATMEL_UART_CTS | ATMEL_UART_RTS);
55 at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
56}
57
58static void __init snapper9260_init_irq(void)
59{
60 at91sam9260_init_interrupts(NULL);
61}
62
63static struct at91_usbh_data __initdata snapper9260_usbh_data = {
64 .ports = 2,
65};
66
67static struct at91_udc_data __initdata snapper9260_udc_data = {
68 .vbus_pin = SNAPPER9260_IO_EXP_GPIO(5),
69 .vbus_active_low = 1,
70 .vbus_polled = 1,
71};
72
73static struct at91_eth_data snapper9260_macb_data = {
74 .is_rmii = 1,
75};
76
77static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
78 {
79 .name = "Preboot",
80 .offset = 0,
81 .size = SZ_128K,
82 },
83 {
84 .name = "Bootloader",
85 .offset = MTDPART_OFS_APPEND,
86 .size = SZ_256K,
87 },
88 {
89 .name = "Environment",
90 .offset = MTDPART_OFS_APPEND,
91 .size = SZ_128K,
92 },
93 {
94 .name = "Kernel",
95 .offset = MTDPART_OFS_APPEND,
96 .size = SZ_4M,
97 },
98 {
99 .name = "Filesystem",
100 .offset = MTDPART_OFS_APPEND,
101 .size = MTDPART_SIZ_FULL,
102 },
103};
104
105static struct mtd_partition * __init
106snapper9260_nand_partition_info(int size, int *num_partitions)
107{
108 *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
109 return snapper9260_nand_partitions;
110}
111
112static struct atmel_nand_data __initdata snapper9260_nand_data = {
113 .ale = 21,
114 .cle = 22,
115 .rdy_pin = AT91_PIN_PC13,
116 .partition_info = snapper9260_nand_partition_info,
117 .bus_width_16 = 0,
118};
119
120static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
121 .ncs_read_setup = 0,
122 .nrd_setup = 0,
123 .ncs_write_setup = 0,
124 .nwe_setup = 0,
125
126 .ncs_read_pulse = 5,
127 .nrd_pulse = 2,
128 .ncs_write_pulse = 5,
129 .nwe_pulse = 2,
130
131 .read_cycle = 7,
132 .write_cycle = 7,
133
134 .mode = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
135 AT91_SMC_EXNWMODE_DISABLE),
136 .tdf_cycles = 1,
137};
138
139static struct pca953x_platform_data snapper9260_io_expander_data = {
140 .gpio_base = SNAPPER9260_IO_EXP_GPIO(0),
141};
142
143static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
144 {
145 /* IO expander */
146 I2C_BOARD_INFO("max7312", 0x28),
147 .platform_data = &snapper9260_io_expander_data,
148 },
149 {
150 /* Audio codec */
151 I2C_BOARD_INFO("tlv320aic23", 0x1a),
152 },
153 {
154 /* RTC */
155 I2C_BOARD_INFO("isl1208", 0x6f),
156 },
157};
158
159static void __init snapper9260_add_device_nand(void)
160{
161 at91_set_A_periph(AT91_PIN_PC14, 0);
162 sam9_smc_configure(3, &snapper9260_nand_smc_config);
163 at91_add_device_nand(&snapper9260_nand_data);
164}
165
166static void __init snapper9260_board_init(void)
167{
168 at91_add_device_i2c(snapper9260_i2c_devices,
169 ARRAY_SIZE(snapper9260_i2c_devices));
170 at91_add_device_serial();
171 at91_add_device_usbh(&snapper9260_usbh_data);
172 at91_add_device_udc(&snapper9260_udc_data);
173 at91_add_device_eth(&snapper9260_macb_data);
174 at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
175 ATMEL_SSC_TD | ATMEL_SSC_RD));
176 snapper9260_add_device_nand();
177}
178
179MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
180 .phys_io = AT91_BASE_SYS,
181 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
182 .boot_params = AT91_SDRAM_BASE + 0x100,
183 .timer = &at91sam926x_timer,
184 .map_io = snapper9260_map_io,
185 .init_irq = snapper9260_init_irq,
186 .init_machine = snapper9260_board_init,
187MACHINE_END
188
189
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index d8c1ededaa75..9c6af9737485 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -84,7 +84,7 @@
84 */ 84 */
85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) 85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) 86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
87#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) 87#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) 88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) 90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
index 1499b1cbffdd..976f4a6c3353 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -15,7 +15,7 @@
15#ifndef AT91CAP9_DDRSDR_H 15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H 16#define AT91CAP9_DDRSDR_H
17 17
18#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ 18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ 19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0 20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1 21#define AT91_DDRSDRC_MODE_NOP 1
@@ -25,10 +25,10 @@
25#define AT91_DDRSDRC_MODE_EXT_LMR 5 25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6 26#define AT91_DDRSDRC_MODE_DEEP 6
27 27
28#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ 28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30 30
31#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ 31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ 32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0) 33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0) 34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
@@ -49,7 +49,7 @@
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ 49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51 51
52#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ 52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ 54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ 55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
@@ -59,13 +59,13 @@
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ 59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61 61
62#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ 62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ 63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ 64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67 67
68#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ 68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0 70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -80,14 +80,14 @@
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) 80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) 81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82 82
83#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ 83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0 85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2 87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89 89
90#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ 90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
@@ -98,5 +98,11 @@
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ 98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ 99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100 100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
101 107
102#endif 108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 43c396b9b4cb..4e79036d3b80 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -84,7 +84,7 @@
84 * System Peripherals (offset from AT91_BASE_SYS) 84 * System Peripherals (offset from AT91_BASE_SYS)
85 */ 85 */
86#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 86#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
87#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 87#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 88#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 89#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 90#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 87de8be17484..2b5618518129 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,7 @@
68/* 68/*
69 * System Peripherals (offset from AT91_BASE_SYS) 69 * System Peripherals (offset from AT91_BASE_SYS)
70 */ 70 */
71#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 71#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
new file mode 100644
index 000000000000..d27b15ba8ebf
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -0,0 +1,130 @@
1/*
2 * Header file for the Atmel DDR/SDR SDRAM Controller
3 *
4 * Copyright (C) 2010 Atmel Corporation
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#ifndef AT91SAM9_DDRSDR_H
13#define AT91SAM9_DDRSDR_H
14
15#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
16#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
17#define AT91_DDRSDRC_MODE_NORMAL 0
18#define AT91_DDRSDRC_MODE_NOP 1
19#define AT91_DDRSDRC_MODE_PRECHARGE 2
20#define AT91_DDRSDRC_MODE_LMR 3
21#define AT91_DDRSDRC_MODE_REFRESH 4
22#define AT91_DDRSDRC_MODE_EXT_LMR 5
23#define AT91_DDRSDRC_MODE_DEEP 6
24
25#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
26#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
27
28#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
29#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
30#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
31#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
32#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
33#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
34#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
35#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
36#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
37#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
38#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
39#define AT91_DDRSDRC_NR_11 (0 << 2)
40#define AT91_DDRSDRC_NR_12 (1 << 2)
41#define AT91_DDRSDRC_NR_13 (2 << 2)
42#define AT91_DDRSDRC_NR_14 (3 << 2)
43#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
44#define AT91_DDRSDRC_CAS_2 (2 << 4)
45#define AT91_DDRSDRC_CAS_3 (3 << 4)
46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
56#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
57#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
58#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
66#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
67#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
81#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
82#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
83#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
84#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
85#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
86#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
87#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
88#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
89#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
90#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
91#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
109
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123
124/* Register access macros */
125#define at91_ramc_read(num, reg) \
126 at91_sys_read(AT91_DDRSDRC##num + reg)
127#define at91_ramc_write(num, reg, value) \
128 at91_sys_write(AT91_DDRSDRC##num + reg, value)
129
130#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index b7260389f7ca..100f5a592926 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -17,7 +17,7 @@
17#define AT91SAM9_SDRAMC_H 17#define AT91SAM9_SDRAMC_H
18 18
19/* SDRAM Controller (SDRAMC) registers */ 19/* SDRAM Controller (SDRAMC) registers */
20#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ 20#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
21#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ 21#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91_SDRAMC_MODE_NORMAL 0 22#define AT91_SDRAMC_MODE_NORMAL 0
23#define AT91_SDRAMC_MODE_NOP 1 23#define AT91_SDRAMC_MODE_NOP 1
@@ -27,10 +27,10 @@
27#define AT91_SDRAMC_MODE_EXT_LMR 5 27#define AT91_SDRAMC_MODE_EXT_LMR 5
28#define AT91_SDRAMC_MODE_DEEP 6 28#define AT91_SDRAMC_MODE_DEEP 6
29 29
30#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ 30#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
31#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 31#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
32 32
33#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ 33#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
34#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ 34#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
35#define AT91_SDRAMC_NC_8 (0 << 0) 35#define AT91_SDRAMC_NC_8 (0 << 0)
36#define AT91_SDRAMC_NC_9 (1 << 0) 36#define AT91_SDRAMC_NC_9 (1 << 0)
@@ -57,7 +57,7 @@
57#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ 57#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
58#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ 58#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
59 59
60#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ 60#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
61#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ 61#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62#define AT91_SDRAMC_LPCB_DISABLE 0 62#define AT91_SDRAMC_LPCB_DISABLE 0
63#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 63#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
@@ -71,16 +71,21 @@
71#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) 71#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
72#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) 72#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
73 73
74#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ 74#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
75#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ 75#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
76#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ 76#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
77#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ 77#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
78#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ 78#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
79 79
80#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ 80#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
81#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ 81#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
82#define AT91_SDRAMC_MD_SDRAM 0 82#define AT91_SDRAMC_MD_SDRAM 0
83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
84 84
85/* Register access macros */
86#define at91_ramc_read(num, reg) \
87 at91_sys_read(AT91_SDRAMC##num + reg)
88#define at91_ramc_write(num, reg, value) \
89 at91_sys_write(AT91_SDRAMC##num + reg, value)
85 90
86#endif 91#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index fc2de6c09c86..87ba8517ad98 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -74,7 +74,7 @@
74 */ 74 */
75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) 75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
77#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 77#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed848c9f8..58528aa9c8a8 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
44 /* USB Device */ 44 /* USB Device */
45struct at91_udc_data { 45struct at91_udc_data {
46 u8 vbus_pin; /* high == host powering us */ 46 u8 vbus_pin; /* high == host powering us */
47 u8 vbus_active_low; /* vbus polarity */
48 u8 vbus_polled; /* Use polling, not interrupt */
47 u8 pullup_pin; /* active == D+ pulled up */ 49 u8 pullup_pin; /* active == D+ pulled up */
48 u8 pullup_active_low; /* true == pullup_pin is active low */ 50 u8 pullup_active_low; /* true == pullup_pin is active low */
49}; 51};
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 833659d1200a..3bef931d0b1c 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
52 52
53#define ARCH_EXID_AT91SAM9M11 0x00000001 53#define ARCH_EXID_AT91SAM9M11 0x00000001
54#define ARCH_EXID_AT91SAM9M10 0x00000002 54#define ARCH_EXID_AT91SAM9M10 0x00000002
55#define ARCH_EXID_AT91SAM9G46 0x00000003
55#define ARCH_EXID_AT91SAM9G45 0x00000004 56#define ARCH_EXID_AT91SAM9G45 0x00000004
56 57
57static inline unsigned long at91_exid_identify(void) 58static inline unsigned long at91_exid_identify(void)
@@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void)
128#ifdef CONFIG_ARCH_AT91SAM9G45 129#ifdef CONFIG_ARCH_AT91SAM9G45
129#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) 130#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
130#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) 131#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
132#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \
133 (at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
134#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \
135 (at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
136#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \
137 (at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
131#else 138#else
132#define cpu_is_at91sam9g45() (0) 139#define cpu_is_at91sam9g45() (0)
133#define cpu_is_at91sam9g45es() (0) 140#define cpu_is_at91sam9g45es() (0)
141#define cpu_is_at91sam9m10() (0)
142#define cpu_is_at91sam9g46() (0)
143#define cpu_is_at91sam9m11() (0)
134#endif 144#endif
135 145
136#ifdef CONFIG_ARCH_AT91CAP9 146#ifdef CONFIG_ARCH_AT91CAP9
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 04c91e31c9c5..bfdd8ab26dc8 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -19,6 +19,7 @@
19#define PIN_BASE NR_AIC_IRQS 19#define PIN_BASE NR_AIC_IRQS
20 20
21#define MAX_GPIO_BANKS 5 21#define MAX_GPIO_BANKS 5
22#define NR_BUILTIN_GPIO (PIN_BASE + (MAX_GPIO_BANKS * 32))
22 23
23/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ 24/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
24 25
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 08322c44df1a..8c87d0c1b8f8 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
30{ 30{
31 u32 saved_lpr, lpr; 31 u32 saved_lpr, lpr;
32 32
33 saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR); 33 saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
34 34
35 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; 35 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
36 at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); 36 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
37 return saved_lpr; 37 return saved_lpr;
38} 38}
39 39
40#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr) 40#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
41
42#elif defined(CONFIG_ARCH_AT91SAM9G45)
43#include <mach/at91sam9_ddrsdr.h>
44
45/* We manage both DDRAM/SDRAM controllers, we need more than one value to
46 * remember.
47 */
48static u32 saved_lpr1;
49
50static inline u32 sdram_selfrefresh_enable(void)
51{
52 /* Those tow values allow us to delay self-refresh activation
53 * to the maximum. */
54 u32 lpr0, lpr1;
55 u32 saved_lpr0;
56
57 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
58 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
59 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
60
61 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
62 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
63 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
64
65 /* self-refresh mode now */
66 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
67 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
68
69 return saved_lpr0;
70}
71
72#define sdram_selfrefresh_disable(saved_lpr0) \
73 do { \
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
75 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
76 } while (0)
41 77
42#else 78#else
43#include <mach/at91sam9_sdramc.h> 79#include <mach/at91sam9_sdramc.h>
@@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
47 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; 83 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
48 * handle those cases both here and in the Suspend-To-RAM support. 84 * handle those cases both here and in the Suspend-To-RAM support.
49 */ 85 */
50#define AT91_SDRAMC AT91_SDRAMC0
51#warning Assuming EB1 SDRAM controller is *NOT* used 86#warning Assuming EB1 SDRAM controller is *NOT* used
52#endif 87#endif
53 88
@@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
55{ 90{
56 u32 saved_lpr, lpr; 91 u32 saved_lpr, lpr;
57 92
58 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR); 93 saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
59 94
60 lpr = saved_lpr & ~AT91_SDRAMC_LPCB; 95 lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
61 at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); 96 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
62 return saved_lpr; 97 return saved_lpr;
63} 98}
64 99
65#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) 100#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
66 101
67#endif 102#endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 9c5b48e68a71..b6b00a1f6125 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,10 +16,12 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <mach/at91_pmc.h> 17#include <mach/at91_pmc.h>
18 18
19#ifdef CONFIG_ARCH_AT91RM9200 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h> 20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) 21#elif defined(CONFIG_ARCH_AT91CAP9)
22#include <mach/at91cap9_ddrsdr.h> 22#include <mach/at91cap9_ddrsdr.h>
23#elif defined(CONFIG_ARCH_AT91SAM9G45)
24#include <mach/at91sam9_ddrsdr.h>
23#else 25#else
24#include <mach/at91sam9_sdramc.h> 26#include <mach/at91sam9_sdramc.h>
25#endif 27#endif
@@ -30,7 +32,6 @@
30 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; 32 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
31 * handle those cases both here and in the Suspend-To-RAM support. 33 * handle those cases both here and in the Suspend-To-RAM support.
32 */ 34 */
33#define AT91_SDRAMC AT91_SDRAMC0
34#warning Assuming EB1 SDRAM controller is *NOT* used 35#warning Assuming EB1 SDRAM controller is *NOT* used
35#endif 36#endif
36 37
@@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
113 /* 114 /*
114 * Register usage: 115 * Register usage:
115 * R1 = Base address of AT91_PMC 116 * R1 = Base address of AT91_PMC
116 * R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200) 117 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
117 * R3 = temporary register 118 * R3 = temporary register
118 * R4 = temporary register 119 * R4 = temporary register
120 * R5 = Base address of second RAM Controller or 0 if not present
119 */ 121 */
120 ldr r1, .at91_va_base_pmc 122 ldr r1, .at91_va_base_pmc
121 ldr r2, .at91_va_base_sdramc 123 ldr r2, .at91_va_base_sdramc
124 ldr r5, .at91_va_base_ramc1
122 125
123 /* Drain write buffer */ 126 /* Drain write buffer */
124 mcr p15, 0, r0, c7, c10, 4 127 mcr p15, 0, r0, c7, c10, 4
@@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
127 /* Put SDRAM in self-refresh mode */ 130 /* Put SDRAM in self-refresh mode */
128 mov r3, #1 131 mov r3, #1
129 str r3, [r2, #AT91_SDRAMC_SRR] 132 str r3, [r2, #AT91_SDRAMC_SRR]
130#elif defined(CONFIG_ARCH_AT91CAP9) 133#elif defined(CONFIG_ARCH_AT91CAP9) \
131 /* Enable SDRAM self-refresh mode */ 134 || defined(CONFIG_ARCH_AT91SAM9G45)
132 ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
133 str r3, .saved_sam9_lpr
134 135
135 mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 136 /* prepare for DDRAM self-refresh mode */
136 str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] 137 ldr r3, [r2, #AT91_DDRSDRC_LPR]
138 str r3, .saved_sam9_lpr
139 bic r3, #AT91_DDRSDRC_LPCB
140 orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
141
142 /* figure out if we use the second ram controller */
143 cmp r5, #0
144 ldrne r4, [r5, #AT91_DDRSDRC_LPR]
145 strne r4, .saved_sam9_lpr1
146 bicne r4, #AT91_DDRSDRC_LPCB
147 orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
148
149 /* Enable DDRAM self-refresh mode */
150 str r3, [r2, #AT91_DDRSDRC_LPR]
151 strne r4, [r5, #AT91_DDRSDRC_LPR]
137#else 152#else
138 /* Enable SDRAM self-refresh mode */ 153 /* Enable SDRAM self-refresh mode */
139 ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 154 ldr r3, [r2, #AT91_SDRAMC_LPR]
140 str r3, .saved_sam9_lpr 155 str r3, .saved_sam9_lpr
141 156
142 mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 157 bic r3, #AT91_SDRAMC_LPCB
143 str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 158 orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
159 str r3, [r2, #AT91_SDRAMC_LPR]
144#endif 160#endif
145 161
146 /* Save Master clock setting */ 162 /* Save Master clock setting */
@@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
247 263
248#ifdef CONFIG_ARCH_AT91RM9200 264#ifdef CONFIG_ARCH_AT91RM9200
249 /* Do nothing - self-refresh is automatically disabled. */ 265 /* Do nothing - self-refresh is automatically disabled. */
250#elif defined(CONFIG_ARCH_AT91CAP9) 266#elif defined(CONFIG_ARCH_AT91CAP9) \
251 /* Restore LPR on AT91CAP9 */ 267 || defined(CONFIG_ARCH_AT91SAM9G45)
268 /* Restore LPR on AT91 with DDRAM */
252 ldr r3, .saved_sam9_lpr 269 ldr r3, .saved_sam9_lpr
253 str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] 270 str r3, [r2, #AT91_DDRSDRC_LPR]
271
272 /* if we use the second ram controller */
273 cmp r5, #0
274 ldrne r4, .saved_sam9_lpr1
275 strne r4, [r5, #AT91_DDRSDRC_LPR]
276
254#else 277#else
255 /* Restore LPR on AT91SAM9 */ 278 /* Restore LPR on AT91 with SDRAM */
256 ldr r3, .saved_sam9_lpr 279 ldr r3, .saved_sam9_lpr
257 str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 280 str r3, [r2, #AT91_SDRAMC_LPR]
258#endif 281#endif
259 282
260 /* Restore registers, and return */ 283 /* Restore registers, and return */
@@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
273.saved_sam9_lpr: 296.saved_sam9_lpr:
274 .word 0 297 .word 0
275 298
299.saved_sam9_lpr1:
300 .word 0
301
276.at91_va_base_pmc: 302.at91_va_base_pmc:
277 .word AT91_VA_BASE_SYS + AT91_PMC 303 .word AT91_VA_BASE_SYS + AT91_PMC
278 304
279#ifdef CONFIG_ARCH_AT91RM9200 305#ifdef CONFIG_ARCH_AT91RM9200
280.at91_va_base_sdramc: 306.at91_va_base_sdramc:
281 .word AT91_VA_BASE_SYS 307 .word AT91_VA_BASE_SYS
282#elif defined(CONFIG_ARCH_AT91CAP9) 308#elif defined(CONFIG_ARCH_AT91CAP9) \
309 || defined(CONFIG_ARCH_AT91SAM9G45)
283.at91_va_base_sdramc: 310.at91_va_base_sdramc:
284 .word AT91_VA_BASE_SYS + AT91_DDRSDRC 311 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
285#else 312#else
286.at91_va_base_sdramc: 313.at91_va_base_sdramc:
287 .word AT91_VA_BASE_SYS + AT91_SDRAMC 314 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
315#endif
316
317.at91_va_base_ramc1:
318#if defined(CONFIG_ARCH_AT91SAM9G45)
319 .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
320#else
321 .word 0
288#endif 322#endif
289 323
290ENTRY(at91_slow_clock_sz) 324ENTRY(at91_slow_clock_sz)
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 72e405df0fb0..d3f959e92b2d 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -91,14 +91,23 @@ static struct clk uart_clk = {
91 .parent = &pll1_clk, 91 .parent = &pll1_clk,
92}; 92};
93 93
94static struct clk dummy_apb_pclk = {
95 .name = "BUSCLK",
96 .type = CLK_TYPE_PRIMARY,
97 .mode = CLK_MODE_XTAL,
98};
99
94static struct clk_lookup lookups[] = { 100static struct clk_lookup lookups[] = {
95 { /* UART0 */ 101 { /* Bus clock */
96 .dev_id = "uarta", 102 .con_id = "apb_pclk",
97 .clk = &uart_clk, 103 .clk = &dummy_apb_pclk,
98 }, { /* UART1 */ 104 }, { /* UART0 */
99 .dev_id = "uartb", 105 .dev_id = "uarta",
100 .clk = &uart_clk, 106 .clk = &uart_clk,
101 } 107 }, { /* UART1 */
108 .dev_id = "uartb",
109 .clk = &uart_clk,
110 }
102}; 111};
103 112
104static struct amba_device *amba_devs[] __initdata = { 113static struct amba_device *amba_devs[] __initdata = {
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index dbaae5f746a1..eb34bd1251d4 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -30,7 +30,6 @@ config ARCH_CLEP7312
30config ARCH_EDB7211 30config ARCH_EDB7211
31 bool "EDB7211" 31 bool "EDB7211"
32 select ISA 32 select ISA
33 select ARCH_DISCONTIGMEM_ENABLE
34 select ARCH_SPARSEMEM_ENABLE 33 select ARCH_SPARSEMEM_ENABLE
35 select ARCH_SELECT_MEMORY_MODEL 34 select ARCH_SELECT_MEMORY_MODEL
36 help 35 help
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 09fb57e45213..3c3bf45039ff 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -32,7 +32,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
32 mi->nr_banks=1; 32 mi->nr_banks=1;
33 mi->bank[0].start = 0xc0000000; 33 mi->bank[0].start = 0xc0000000;
34 mi->bank[0].size = 0x01000000; 34 mi->bank[0].size = 0x01000000;
35 mi->bank[0].node = 0;
36} 35}
37 36
38 37
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index dc81cc68595d..4a7a2322979a 100644
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -18,6 +18,7 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/memblock.h>
21#include <linux/types.h> 22#include <linux/types.h>
22#include <linux/string.h> 23#include <linux/string.h>
23 24
@@ -29,6 +30,12 @@
29 30
30extern void edb7211_map_io(void); 31extern void edb7211_map_io(void);
31 32
33/* Reserve screen memory region at the start of main system memory. */
34static void __init edb7211_reserve(void)
35{
36 memblock_reserve(PHYS_OFFSET, 0x00020000);
37}
38
32static void __init 39static void __init
33fixup_edb7211(struct machine_desc *desc, struct tag *tags, 40fixup_edb7211(struct machine_desc *desc, struct tag *tags,
34 char **cmdline, struct meminfo *mi) 41 char **cmdline, struct meminfo *mi)
@@ -43,10 +50,8 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
43 */ 50 */
44 mi->bank[0].start = 0xc0000000; 51 mi->bank[0].start = 0xc0000000;
45 mi->bank[0].size = 8*1024*1024; 52 mi->bank[0].size = 8*1024*1024;
46 mi->bank[0].node = 0;
47 mi->bank[1].start = 0xc1000000; 53 mi->bank[1].start = 0xc1000000;
48 mi->bank[1].size = 8*1024*1024; 54 mi->bank[1].size = 8*1024*1024;
49 mi->bank[1].node = 1;
50 mi->nr_banks = 2; 55 mi->nr_banks = 2;
51} 56}
52 57
@@ -57,6 +62,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
57 .boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */ 62 .boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */
58 .fixup = fixup_edb7211, 63 .fixup = fixup_edb7211,
59 .map_io = edb7211_map_io, 64 .map_io = edb7211_map_io,
65 .reserve = edb7211_reserve,
60 .init_irq = clps711x_init_irq, 66 .init_irq = clps711x_init_irq,
61 .timer = &clps711x_timer, 67 .timer = &clps711x_timer,
62MACHINE_END 68MACHINE_END
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 7430e4049d87..a696099aa4f8 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -39,7 +39,6 @@ struct meminfo memmap = {
39 { 39 {
40 .start = 0xC0000000, 40 .start = 0xC0000000,
41 .size = 0x01000000, 41 .size = 0x01000000,
42 .node = 0
43 }, 42 },
44 }, 43 },
45}; 44};
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
index f70d52be48a2..f45c8e892cb5 100644
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -20,7 +20,6 @@
20#ifndef __ASM_ARCH_MEMORY_H 20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H 21#define __ASM_ARCH_MEMORY_H
22 22
23
24/* 23/*
25 * Physical DRAM offset. 24 * Physical DRAM offset.
26 */ 25 */
@@ -72,7 +71,6 @@
72 * node 2: 0xd0000000 - 0xd7ffffff 71 * node 2: 0xd0000000 - 0xd7ffffff
73 * node 3: 0xd8000000 - 0xdfffffff 72 * node 3: 0xd8000000 - 0xdfffffff
74 */ 73 */
75#define NODE_MEM_SIZE_BITS 24
76#define SECTION_SIZE_BITS 24 74#define SECTION_SIZE_BITS 24
77#define MAX_PHYSMEM_BITS 32 75#define MAX_PHYSMEM_BITS 32
78 76
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 427507a2d696..11033f1c2e23 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,2 +1,3 @@
1obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o 1obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
2obj-$(CONFIG_PCI) += pcie.o
2obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o 3obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2e30c8288740..9df8391fd78a 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -32,6 +32,7 @@
32#include <mach/cns3xxx.h> 32#include <mach/cns3xxx.h>
33#include <mach/irqs.h> 33#include <mach/irqs.h>
34#include "core.h" 34#include "core.h"
35#include "devices.h"
35 36
36/* 37/*
37 * NOR Flash 38 * NOR Flash
@@ -117,6 +118,9 @@ static void __init cns3420_init(void)
117{ 118{
118 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); 119 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
119 120
121 cns3xxx_ahci_init();
122 cns3xxx_sdhci_init();
123
120 pm_power_off = cns3xxx_power_off; 124 pm_power_off = cns3xxx_power_off;
121} 125}
122 126
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644
index 000000000000..50b4d31c27c0
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -0,0 +1,111 @@
1/*
2 * CNS3xxx common devices
3 *
4 * Copyright 2008 Cavium Networks
5 * Scott Shu
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/io.h>
15#include <linux/init.h>
16#include <linux/compiler.h>
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
19#include <mach/cns3xxx.h>
20#include <mach/irqs.h>
21#include "core.h"
22#include "devices.h"
23
24/*
25 * AHCI
26 */
27static struct resource cns3xxx_ahci_resource[] = {
28 [0] = {
29 .start = CNS3XXX_SATA2_BASE,
30 .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [1] = {
34 .start = IRQ_CNS3XXX_SATA,
35 .end = IRQ_CNS3XXX_SATA,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
41
42static struct platform_device cns3xxx_ahci_pdev = {
43 .name = "ahci",
44 .id = 0,
45 .resource = cns3xxx_ahci_resource,
46 .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
47 .dev = {
48 .dma_mask = &cns3xxx_ahci_dmamask,
49 .coherent_dma_mask = DMA_BIT_MASK(32),
50 },
51};
52
53void __init cns3xxx_ahci_init(void)
54{
55 u32 tmp;
56
57 tmp = __raw_readl(MISC_SATA_POWER_MODE);
58 tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
59 tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
60 __raw_writel(tmp, MISC_SATA_POWER_MODE);
61
62 /* Enable SATA PHY */
63 cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
64 cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
65
66 /* Enable SATA Clock */
67 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
68
69 /* De-Asscer SATA Reset */
70 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
71
72 platform_device_register(&cns3xxx_ahci_pdev);
73}
74
75/*
76 * SDHCI
77 */
78static struct resource cns3xxx_sdhci_resources[] = {
79 [0] = {
80 .start = CNS3XXX_SDIO_BASE,
81 .end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
82 .flags = IORESOURCE_MEM,
83 },
84 [1] = {
85 .start = IRQ_CNS3XXX_SDIO,
86 .end = IRQ_CNS3XXX_SDIO,
87 .flags = IORESOURCE_IRQ,
88 },
89};
90
91static struct platform_device cns3xxx_sdhci_pdev = {
92 .name = "sdhci-cns3xxx",
93 .id = 0,
94 .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
95 .resource = cns3xxx_sdhci_resources,
96};
97
98void __init cns3xxx_sdhci_init(void)
99{
100 u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
101 u32 gpioa_pins = __raw_readl(gpioa);
102
103 /* MMC/SD pins share with GPIOA */
104 gpioa_pins |= 0x1fff0004;
105 __raw_writel(gpioa_pins, gpioa);
106
107 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
108 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
109
110 platform_device_register(&cns3xxx_sdhci_pdev);
111}
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644
index 000000000000..27e15a10aa85
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -0,0 +1,20 @@
1/*
2 * CNS3xxx common devices
3 *
4 * Copyright 2008 Cavium Networks
5 * Scott Shu
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __CNS3XXX_DEVICES_H_
15#define __CNS3XXX_DEVICES_H_
16
17void __init cns3xxx_ahci_init(void);
18void __init cns3xxx_sdhci_init(void);
19
20#endif /* __CNS3XXX_DEVICES_H_ */
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 8a2f5a21d4ee..6dbce13771ca 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -247,37 +247,36 @@
247 * Misc block 247 * Misc block
248 */ 248 */
249#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) 249#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
250#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset)))) 250
251 251#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
252#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00) 252#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
253#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04) 253#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
254#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08) 254#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
255#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C) 255#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
256#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10) 256#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
257#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14) 257#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
258#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18) 258#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
259#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C) 259#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
260#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20) 260#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
261#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24) 261#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
262#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28) 262#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
263#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C) 263#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
264#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30) 264#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
265#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34) 265#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
266#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40) 266#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
267#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44) 267#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
268#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48) 268#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
269#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C) 269#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
270#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50) 270#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
271#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54) 271
272 272#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
273#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310) 273
274 274#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
275#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800) 275#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
276#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804) 276#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
277#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808) 277#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
278#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c) 278#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
279#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810) 279#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
280#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
281 280
282#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) 281#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
283#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) 282#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
@@ -300,21 +299,21 @@
300/* 299/*
301 * Power management and clock control 300 * Power management and clock control
302 */ 301 */
303#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset)))) 302#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
304 303
305#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000) 304#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
306#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004) 305#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
307#define PM_HS_CFG_REG PMU_REG_VALUE(0x008) 306#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
308#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C) 307#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
309#define PM_PWR_STA_REG PMU_REG_VALUE(0x010) 308#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
310#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014) 309#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
311#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018) 310#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
312#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C) 311#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
313#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020) 312#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
314#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024) 313#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
315#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028) 314#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
316#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C) 315#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
317#define PM_CSR_REG PMU_REG_VALUE(0x030) 316#define PM_CSR_REG PMU_MEM_MAP(0x030)
318 317
319/* PM_CLK_GATE_REG */ 318/* PM_CLK_GATE_REG */
320#define PM_CLK_GATE_REG_OFFSET_SDIO (25) 319#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644
index 000000000000..38088c36936c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -0,0 +1,389 @@
1/*
2 * PCI-E support for CNS3xxx
3 *
4 * Copyright 2008 Cavium Networks
5 * Richard Liu <richard.liu@caviumnetworks.com>
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/bug.h>
17#include <linux/pci.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/ptrace.h>
22#include <asm/mach/map.h>
23#include <mach/cns3xxx.h>
24#include "core.h"
25
26enum cns3xxx_access_type {
27 CNS3XXX_HOST_TYPE = 0,
28 CNS3XXX_CFG0_TYPE,
29 CNS3XXX_CFG1_TYPE,
30 CNS3XXX_NUM_ACCESS_TYPES,
31};
32
33struct cns3xxx_pcie {
34 struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
35 unsigned int irqs[2];
36 struct resource res_io;
37 struct resource res_mem;
38 struct hw_pci hw_pci;
39
40 bool linked;
41};
42
43static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
44
45static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
46{
47 struct pci_sys_data *root = sysdata;
48
49 return &cns3xxx_pcie[root->domain];
50}
51
52static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
53{
54 return sysdata_to_cnspci(dev->sysdata);
55}
56
57static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
58{
59 return sysdata_to_cnspci(bus->sysdata);
60}
61
62static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
63 unsigned int devfn, int where)
64{
65 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
66 int busno = bus->number;
67 int slot = PCI_SLOT(devfn);
68 int offset;
69 enum cns3xxx_access_type type;
70 void __iomem *base;
71
72 /* If there is no link, just show the CNS PCI bridge. */
73 if (!cnspci->linked && (busno > 0 || slot > 0))
74 return NULL;
75
76 /*
77 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
78 * we still want to access it. For this to work, we must place
79 * the first device on the same bus as the CNS PCI bridge.
80 */
81 if (busno == 0) {
82 if (slot > 1)
83 return NULL;
84 type = slot;
85 } else {
86 type = CNS3XXX_CFG1_TYPE;
87 }
88
89 base = (void __iomem *)cnspci->cfg_bases[type].virtual;
90 offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
91
92 return base + offset;
93}
94
95static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
96 int where, int size, u32 *val)
97{
98 u32 v;
99 void __iomem *base;
100 u32 mask = (0x1ull << (size * 8)) - 1;
101 int shift = (where % 4) * 8;
102
103 base = cns3xxx_pci_cfg_base(bus, devfn, where);
104 if (!base) {
105 *val = 0xffffffff;
106 return PCIBIOS_SUCCESSFUL;
107 }
108
109 v = __raw_readl(base);
110
111 if (bus->number == 0 && devfn == 0 &&
112 (where & 0xffc) == PCI_CLASS_REVISION) {
113 /*
114 * RC's class is 0xb, but Linux PCI driver needs 0x604
115 * for a PCIe bridge. So we must fixup the class code
116 * to 0x604 here.
117 */
118 v &= 0xff;
119 v |= 0x604 << 16;
120 }
121
122 *val = (v >> shift) & mask;
123
124 return PCIBIOS_SUCCESSFUL;
125}
126
127static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
128 int where, int size, u32 val)
129{
130 u32 v;
131 void __iomem *base;
132 u32 mask = (0x1ull << (size * 8)) - 1;
133 int shift = (where % 4) * 8;
134
135 base = cns3xxx_pci_cfg_base(bus, devfn, where);
136 if (!base)
137 return PCIBIOS_SUCCESSFUL;
138
139 v = __raw_readl(base);
140
141 v &= ~(mask << shift);
142 v |= (val & mask) << shift;
143
144 __raw_writel(v, base);
145
146 return PCIBIOS_SUCCESSFUL;
147}
148
149static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
150{
151 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
152 struct resource *res_io = &cnspci->res_io;
153 struct resource *res_mem = &cnspci->res_mem;
154 struct resource **sysres = sys->resource;
155
156 BUG_ON(request_resource(&iomem_resource, res_io) ||
157 request_resource(&iomem_resource, res_mem));
158
159 sysres[0] = res_io;
160 sysres[1] = res_mem;
161
162 return 1;
163}
164
165static struct pci_ops cns3xxx_pcie_ops = {
166 .read = cns3xxx_pci_read_config,
167 .write = cns3xxx_pci_write_config,
168};
169
170static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
171{
172 return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
173}
174
175static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
176{
177 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
178 int irq = cnspci->irqs[slot];
179
180 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
181 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
182 PCI_FUNC(dev->devfn), slot, pin, irq);
183
184 return irq;
185}
186
187static struct cns3xxx_pcie cns3xxx_pcie[] = {
188 [0] = {
189 .cfg_bases = {
190 [CNS3XXX_HOST_TYPE] = {
191 .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
192 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
193 .length = SZ_16M,
194 .type = MT_DEVICE,
195 },
196 [CNS3XXX_CFG0_TYPE] = {
197 .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
198 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
199 .length = SZ_16M,
200 .type = MT_DEVICE,
201 },
202 [CNS3XXX_CFG1_TYPE] = {
203 .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
204 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
205 .length = SZ_16M,
206 .type = MT_DEVICE,
207 },
208 },
209 .res_io = {
210 .name = "PCIe0 I/O space",
211 .start = CNS3XXX_PCIE0_IO_BASE,
212 .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
213 .flags = IORESOURCE_IO,
214 },
215 .res_mem = {
216 .name = "PCIe0 non-prefetchable",
217 .start = CNS3XXX_PCIE0_MEM_BASE,
218 .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
222 .hw_pci = {
223 .domain = 0,
224 .swizzle = pci_std_swizzle,
225 .nr_controllers = 1,
226 .setup = cns3xxx_pci_setup,
227 .scan = cns3xxx_pci_scan_bus,
228 .map_irq = cns3xxx_pcie_map_irq,
229 },
230 },
231 [1] = {
232 .cfg_bases = {
233 [CNS3XXX_HOST_TYPE] = {
234 .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
235 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
236 .length = SZ_16M,
237 .type = MT_DEVICE,
238 },
239 [CNS3XXX_CFG0_TYPE] = {
240 .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
241 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
242 .length = SZ_16M,
243 .type = MT_DEVICE,
244 },
245 [CNS3XXX_CFG1_TYPE] = {
246 .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
247 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
248 .length = SZ_16M,
249 .type = MT_DEVICE,
250 },
251 },
252 .res_io = {
253 .name = "PCIe1 I/O space",
254 .start = CNS3XXX_PCIE1_IO_BASE,
255 .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
256 .flags = IORESOURCE_IO,
257 },
258 .res_mem = {
259 .name = "PCIe1 non-prefetchable",
260 .start = CNS3XXX_PCIE1_MEM_BASE,
261 .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
262 .flags = IORESOURCE_MEM,
263 },
264 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
265 .hw_pci = {
266 .domain = 1,
267 .swizzle = pci_std_swizzle,
268 .nr_controllers = 1,
269 .setup = cns3xxx_pci_setup,
270 .scan = cns3xxx_pci_scan_bus,
271 .map_irq = cns3xxx_pcie_map_irq,
272 },
273 },
274};
275
276static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
277{
278 int port = cnspci->hw_pci.domain;
279 u32 reg;
280 unsigned long time;
281
282 reg = __raw_readl(MISC_PCIE_CTRL(port));
283 /*
284 * Enable Application Request to 1, it will exit L1 automatically,
285 * but when chip back, it will use another clock, still can use 0x1.
286 */
287 reg |= 0x3;
288 __raw_writel(reg, MISC_PCIE_CTRL(port));
289
290 pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
291 pr_info("PCIe: Port[%d] Check data link layer...", port);
292
293 time = jiffies;
294 while (1) {
295 reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
296 if (reg & 0x1) {
297 pr_info("Link up.\n");
298 cnspci->linked = 1;
299 break;
300 } else if (time_after(jiffies, time + 50)) {
301 pr_info("Device not found.\n");
302 break;
303 }
304 }
305}
306
307static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
308{
309 int port = cnspci->hw_pci.domain;
310 struct pci_sys_data sd = {
311 .domain = port,
312 };
313 struct pci_bus bus = {
314 .number = 0,
315 .ops = &cns3xxx_pcie_ops,
316 .sysdata = &sd,
317 };
318 u32 io_base = cnspci->res_io.start >> 16;
319 u32 mem_base = cnspci->res_mem.start >> 16;
320 u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
321 u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
322 u32 devfn = 0;
323 u8 tmp8;
324 u16 pos;
325 u16 dc;
326
327 host_base = (__pfn_to_phys(host_base) - 1) >> 16;
328 cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
329
330 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
331 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
332 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
333
334 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
335 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
336 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
337
338 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
339 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
340 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
341 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
342
343 if (!cnspci->linked)
344 return;
345
346 /* Set Device Max_Read_Request_Size to 128 byte */
347 devfn = PCI_DEVFN(1, 0);
348 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
349 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
350 dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
351 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
352 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
353 if (!(dc & (0x3 << 12)))
354 pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
355
356 /* Disable PCIe0 Interrupt Mask INTA to INTD */
357 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
358}
359
360static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
361 struct pt_regs *regs)
362{
363 if (fsr & (1 << 10))
364 regs->ARM_pc += 4;
365 return 0;
366}
367
368static int __init cns3xxx_pcie_init(void)
369{
370 int i;
371
372 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
373 "imprecise external abort");
374
375 for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
376 iotable_init(cns3xxx_pcie[i].cfg_bases,
377 ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
378 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
379 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
380 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
381 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
382 pci_common_init(&cns3xxx_pcie[i].hw_pci);
383 }
384
385 pci_assign_unassigned_resources();
386
387 return 0;
388}
389device_initcall(cns3xxx_pcie_init);
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 725e1a4fc231..38e44706feab 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,18 +6,25 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include <linux/io.h>
9#include <linux/delay.h> 10#include <linux/delay.h>
10#include <mach/system.h> 11#include <mach/system.h>
11#include <mach/cns3xxx.h> 12#include <mach/cns3xxx.h>
12 13
13void cns3xxx_pwr_clk_en(unsigned int block) 14void cns3xxx_pwr_clk_en(unsigned int block)
14{ 15{
15 PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK); 16 u32 reg = __raw_readl(PM_CLK_GATE_REG);
17
18 reg |= (block & PM_CLK_GATE_REG_MASK);
19 __raw_writel(reg, PM_CLK_GATE_REG);
16} 20}
17 21
18void cns3xxx_pwr_power_up(unsigned int block) 22void cns3xxx_pwr_power_up(unsigned int block)
19{ 23{
20 PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL); 24 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
25
26 reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
27 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
21 28
22 /* Wait for 300us for the PLL output clock locked. */ 29 /* Wait for 300us for the PLL output clock locked. */
23 udelay(300); 30 udelay(300);
@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
25 32
26void cns3xxx_pwr_power_down(unsigned int block) 33void cns3xxx_pwr_power_down(unsigned int block)
27{ 34{
35 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
36
28 /* write '1' to power down */ 37 /* write '1' to power down */
29 PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL); 38 reg |= (block & CNS3XXX_PWR_PLL_ALL);
39 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
30}; 40};
31 41
32static void cns3xxx_pwr_soft_rst_force(unsigned int block) 42static void cns3xxx_pwr_soft_rst_force(unsigned int block)
33{ 43{
44 u32 reg = __raw_readl(PM_SOFT_RST_REG);
45
34 /* 46 /*
35 * bit 0, 28, 29 => program low to reset, 47 * bit 0, 28, 29 => program low to reset,
36 * the other else program low and then high 48 * the other else program low and then high
37 */ 49 */
38 if (block & 0x30000001) { 50 if (block & 0x30000001) {
39 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); 51 reg &= ~(block & PM_SOFT_RST_REG_MASK);
40 } else { 52 } else {
41 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK); 53 reg &= ~(block & PM_SOFT_RST_REG_MASK);
42 PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK); 54 reg |= (block & PM_SOFT_RST_REG_MASK);
43 } 55 }
56
57 __raw_writel(reg, PM_SOFT_RST_REG);
44} 58}
45 59
46void cns3xxx_pwr_soft_rst(unsigned int block) 60void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
73 */ 87 */
74int cns3xxx_cpu_clock(void) 88int cns3xxx_cpu_clock(void)
75{ 89{
90 u32 reg = __raw_readl(PM_CLK_CTRL_REG);
76 int cpu; 91 int cpu;
77 int cpu_sel; 92 int cpu_sel;
78 int div_sel; 93 int div_sel;
79 94
80 cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; 95 cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
81 div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; 96 div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
82 97
83 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; 98 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
84 99
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index a91edfb8beea..22eb97c1c30b 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -48,19 +48,16 @@
48 * below 128M 48 * below 128M
49 */ 49 */
50static inline void 50static inline void
51__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) 51__arch_adjust_zones(unsigned long *size, unsigned long *holes)
52{ 52{
53 unsigned int sz = (128<<20) >> PAGE_SHIFT; 53 unsigned int sz = (128<<20) >> PAGE_SHIFT;
54 54
55 if (node != 0)
56 sz = 0;
57
58 size[1] = size[0] - sz; 55 size[1] = size[0] - sz;
59 size[0] = sz; 56 size[0] = sz;
60} 57}
61 58
62#define arch_adjust_zones(node, zone_size, holes) \ 59#define arch_adjust_zones(zone_size, holes) \
63 if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) 60 if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
64 61
65#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) 62#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
66#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20)) 63#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 5da2cf402c81..f7a12586a1f5 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -752,6 +752,67 @@ void __init dove_xor1_init(void)
752 platform_device_register(&dove_xor11_channel); 752 platform_device_register(&dove_xor11_channel);
753} 753}
754 754
755/*****************************************************************************
756 * SDIO
757 ****************************************************************************/
758static u64 sdio_dmamask = DMA_BIT_MASK(32);
759
760static struct resource dove_sdio0_resources[] = {
761 {
762 .start = DOVE_SDIO0_PHYS_BASE,
763 .end = DOVE_SDIO0_PHYS_BASE + 0xff,
764 .flags = IORESOURCE_MEM,
765 }, {
766 .start = IRQ_DOVE_SDIO0,
767 .end = IRQ_DOVE_SDIO0,
768 .flags = IORESOURCE_IRQ,
769 },
770};
771
772static struct platform_device dove_sdio0 = {
773 .name = "sdhci-mv",
774 .id = 0,
775 .dev = {
776 .dma_mask = &sdio_dmamask,
777 .coherent_dma_mask = DMA_BIT_MASK(32),
778 },
779 .resource = dove_sdio0_resources,
780 .num_resources = ARRAY_SIZE(dove_sdio0_resources),
781};
782
783void __init dove_sdio0_init(void)
784{
785 platform_device_register(&dove_sdio0);
786}
787
788static struct resource dove_sdio1_resources[] = {
789 {
790 .start = DOVE_SDIO1_PHYS_BASE,
791 .end = DOVE_SDIO1_PHYS_BASE + 0xff,
792 .flags = IORESOURCE_MEM,
793 }, {
794 .start = IRQ_DOVE_SDIO1,
795 .end = IRQ_DOVE_SDIO1,
796 .flags = IORESOURCE_IRQ,
797 },
798};
799
800static struct platform_device dove_sdio1 = {
801 .name = "sdhci-mv",
802 .id = 1,
803 .dev = {
804 .dma_mask = &sdio_dmamask,
805 .coherent_dma_mask = DMA_BIT_MASK(32),
806 },
807 .resource = dove_sdio1_resources,
808 .num_resources = ARRAY_SIZE(dove_sdio1_resources),
809};
810
811void __init dove_sdio1_init(void)
812{
813 platform_device_register(&dove_sdio1);
814}
815
755void __init dove_init(void) 816void __init dove_init(void)
756{ 817{
757 int tclk; 818 int tclk;
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index b29e8937de4f..a51517c3fe76 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -36,5 +36,7 @@ void dove_uart3_init(void);
36void dove_spi0_init(void); 36void dove_spi0_init(void);
37void dove_spi1_init(void); 37void dove_spi1_init(void);
38void dove_i2c_init(void); 38void dove_i2c_init(void);
39void dove_sdio0_init(void);
40void dove_sdio1_init(void);
39 41
40#endif 42#endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index f2971b745224..bef70460fbc6 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -82,6 +82,8 @@ static void __init dove_db_init(void)
82 dove_ehci0_init(); 82 dove_ehci0_init();
83 dove_ehci1_init(); 83 dove_ehci1_init();
84 dove_sata_init(&dove_db_sata_data); 84 dove_sata_init(&dove_db_sata_data);
85 dove_sdio0_init();
86 dove_sdio1_init();
85 dove_spi0_init(); 87 dove_spi0_init();
86 dove_spi1_init(); 88 dove_spi1_init();
87 dove_uart0_init(); 89 dove_uart0_init();
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3a1a855bfdca..f744f676783f 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -13,7 +13,6 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/mtd/physmap.h>
17 16
18#include <mach/hardware.h> 17#include <mach/hardware.h>
19 18
@@ -21,26 +20,6 @@
21#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
22 21
23 22
24static struct physmap_flash_data adssphere_flash_data = {
25 .width = 4,
26};
27
28static struct resource adssphere_flash_resource = {
29 .start = EP93XX_CS6_PHYS_BASE,
30 .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
31 .flags = IORESOURCE_MEM,
32};
33
34static struct platform_device adssphere_flash = {
35 .name = "physmap-flash",
36 .id = 0,
37 .dev = {
38 .platform_data = &adssphere_flash_data,
39 },
40 .num_resources = 1,
41 .resource = &adssphere_flash_resource,
42};
43
44static struct ep93xx_eth_data __initdata adssphere_eth_data = { 23static struct ep93xx_eth_data __initdata adssphere_eth_data = {
45 .phy_id = 1, 24 .phy_id = 1,
46}; 25};
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
48static void __init adssphere_init_machine(void) 27static void __init adssphere_init_machine(void)
49{ 28{
50 ep93xx_init_devices(); 29 ep93xx_init_devices();
51 platform_device_register(&adssphere_flash); 30 ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
52
53 ep93xx_register_eth(&adssphere_eth_data, 1); 31 ep93xx_register_eth(&adssphere_eth_data, 1);
54} 32}
55 33
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index e29bdef9b2e2..7f3039761d91 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = {
185 INIT_CK(NULL, "pll1", &clk_pll1), 185 INIT_CK(NULL, "pll1", &clk_pll1),
186 INIT_CK(NULL, "fclk", &clk_f), 186 INIT_CK(NULL, "fclk", &clk_f),
187 INIT_CK(NULL, "hclk", &clk_h), 187 INIT_CK(NULL, "hclk", &clk_h),
188 INIT_CK(NULL, "pclk", &clk_p), 188 INIT_CK(NULL, "apb_pclk", &clk_p),
189 INIT_CK(NULL, "pll2", &clk_pll2), 189 INIT_CK(NULL, "pll2", &clk_pll2),
190 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), 190 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
191 INIT_CK("ep93xx-keypad", NULL, &clk_keypad), 191 INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 9092677f63eb..8e37a045188c 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -29,6 +29,7 @@
29#include <linux/termios.h> 29#include <linux/termios.h>
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/amba/serial.h> 31#include <linux/amba/serial.h>
32#include <linux/mtd/physmap.h>
32#include <linux/i2c.h> 33#include <linux/i2c.h>
33#include <linux/i2c-gpio.h> 34#include <linux/i2c-gpio.h>
34#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
@@ -215,8 +216,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
215 spin_lock_irqsave(&syscon_swlock, flags); 216 spin_lock_irqsave(&syscon_swlock, flags);
216 217
217 val = __raw_readl(EP93XX_SYSCON_DEVCFG); 218 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
218 val |= set_bits;
219 val &= ~clear_bits; 219 val &= ~clear_bits;
220 val |= set_bits;
220 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 221 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
221 __raw_writel(val, EP93XX_SYSCON_DEVCFG); 222 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
222 223
@@ -348,6 +349,43 @@ static struct platform_device ep93xx_ohci_device = {
348 349
349 350
350/************************************************************************* 351/*************************************************************************
352 * EP93xx physmap'ed flash
353 *************************************************************************/
354static struct physmap_flash_data ep93xx_flash_data;
355
356static struct resource ep93xx_flash_resource = {
357 .flags = IORESOURCE_MEM,
358};
359
360static struct platform_device ep93xx_flash = {
361 .name = "physmap-flash",
362 .id = 0,
363 .dev = {
364 .platform_data = &ep93xx_flash_data,
365 },
366 .num_resources = 1,
367 .resource = &ep93xx_flash_resource,
368};
369
370/**
371 * ep93xx_register_flash() - Register the external flash device.
372 * @width: bank width in octets
373 * @start: resource start address
374 * @size: resource size
375 */
376void __init ep93xx_register_flash(unsigned int width,
377 resource_size_t start, resource_size_t size)
378{
379 ep93xx_flash_data.width = width;
380
381 ep93xx_flash_resource.start = start;
382 ep93xx_flash_resource.end = start + size - 1;
383
384 platform_device_register(&ep93xx_flash);
385}
386
387
388/*************************************************************************
351 * EP93xx ethernet peripheral handling 389 * EP93xx ethernet peripheral handling
352 *************************************************************************/ 390 *************************************************************************/
353static struct ep93xx_eth_data ep93xx_eth_data; 391static struct ep93xx_eth_data ep93xx_eth_data;
@@ -620,6 +658,11 @@ static struct platform_device ep93xx_fb_device = {
620 .resource = ep93xx_fb_resource, 658 .resource = ep93xx_fb_resource,
621}; 659};
622 660
661static struct platform_device ep93xx_bl_device = {
662 .name = "ep93xx-bl",
663 .id = -1,
664};
665
623/** 666/**
624 * ep93xx_register_fb - Register the framebuffer platform device. 667 * ep93xx_register_fb - Register the framebuffer platform device.
625 * @data: platform specific framebuffer configuration (__initdata) 668 * @data: platform specific framebuffer configuration (__initdata)
@@ -628,6 +671,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
628{ 671{
629 ep93xxfb_data = *data; 672 ep93xxfb_data = *data;
630 platform_device_register(&ep93xx_fb_device); 673 platform_device_register(&ep93xx_fb_device);
674 platform_device_register(&ep93xx_bl_device);
631} 675}
632 676
633 677
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 3884182cd362..c2ce9034ba87 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,7 +27,6 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/platform_device.h> 29#include <linux/platform_device.h>
30#include <linux/mtd/physmap.h>
31#include <linux/gpio.h> 30#include <linux/gpio.h>
32#include <linux/i2c.h> 31#include <linux/i2c.h>
33#include <linux/i2c-gpio.h> 32#include <linux/i2c-gpio.h>
@@ -38,39 +37,13 @@
38#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
39 38
40 39
41static struct physmap_flash_data edb93xx_flash_data;
42
43static struct resource edb93xx_flash_resource = {
44 .flags = IORESOURCE_MEM,
45};
46
47static struct platform_device edb93xx_flash = {
48 .name = "physmap-flash",
49 .id = 0,
50 .dev = {
51 .platform_data = &edb93xx_flash_data,
52 },
53 .num_resources = 1,
54 .resource = &edb93xx_flash_resource,
55};
56
57static void __init __edb93xx_register_flash(unsigned int width,
58 resource_size_t start, resource_size_t size)
59{
60 edb93xx_flash_data.width = width;
61 edb93xx_flash_resource.start = start;
62 edb93xx_flash_resource.end = start + size - 1;
63
64 platform_device_register(&edb93xx_flash);
65}
66
67static void __init edb93xx_register_flash(void) 40static void __init edb93xx_register_flash(void)
68{ 41{
69 if (machine_is_edb9307() || machine_is_edb9312() || 42 if (machine_is_edb9307() || machine_is_edb9312() ||
70 machine_is_edb9315()) { 43 machine_is_edb9315()) {
71 __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); 44 ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
72 } else { 45 } else {
73 __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); 46 ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
74 } 47 }
75} 48}
76 49
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index a809618e9f05..d97168c0ba33 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -13,7 +13,6 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/mtd/physmap.h>
17 16
18#include <mach/hardware.h> 17#include <mach/hardware.h>
19 18
@@ -21,26 +20,6 @@
21#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
22 21
23 22
24static struct physmap_flash_data gesbc9312_flash_data = {
25 .width = 4,
26};
27
28static struct resource gesbc9312_flash_resource = {
29 .start = EP93XX_CS6_PHYS_BASE,
30 .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
31 .flags = IORESOURCE_MEM,
32};
33
34static struct platform_device gesbc9312_flash = {
35 .name = "physmap-flash",
36 .id = 0,
37 .dev = {
38 .platform_data = &gesbc9312_flash_data,
39 },
40 .num_resources = 1,
41 .resource = &gesbc9312_flash_resource,
42};
43
44static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { 23static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
45 .phy_id = 1, 24 .phy_id = 1,
46}; 25};
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
48static void __init gesbc9312_init_machine(void) 27static void __init gesbc9312_init_machine(void)
49{ 28{
50 ep93xx_init_devices(); 29 ep93xx_init_devices();
51 platform_device_register(&gesbc9312_flash); 30 ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
52
53 ep93xx_register_eth(&gesbc9312_eth_data, 0); 31 ep93xx_register_eth(&gesbc9312_eth_data, 0);
54} 32}
55 33
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 9a4413dd44bb..a6c09176334c 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
43 43
44unsigned int ep93xx_chip_revision(void); 44unsigned int ep93xx_chip_revision(void);
45 45
46void ep93xx_register_flash(unsigned int width,
47 resource_size_t start, resource_size_t size);
48
46void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); 49void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
47void ep93xx_register_i2c(struct i2c_gpio_platform_data *data, 50void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
48 struct i2c_board_info *devices, int num); 51 struct i2c_board_info *devices, int num);
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 1cc911b4efa6..2ba776320a82 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -14,7 +14,6 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/io.h> 17#include <linux/io.h>
19 18
20#include <mach/hardware.h> 19#include <mach/hardware.h>
@@ -31,31 +30,6 @@
31 * Micro9-Lite uses a separate MTD map driver for flash support 30 * Micro9-Lite uses a separate MTD map driver for flash support
32 * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1 31 * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
33 *************************************************************************/ 32 *************************************************************************/
34static struct physmap_flash_data micro9_flash_data;
35
36static struct resource micro9_flash_resource = {
37 .start = EP93XX_CS1_PHYS_BASE,
38 .end = EP93XX_CS1_PHYS_BASE + SZ_64M - 1,
39 .flags = IORESOURCE_MEM,
40};
41
42static struct platform_device micro9_flash = {
43 .name = "physmap-flash",
44 .id = 0,
45 .dev = {
46 .platform_data = &micro9_flash_data,
47 },
48 .num_resources = 1,
49 .resource = &micro9_flash_resource,
50};
51
52static void __init __micro9_register_flash(unsigned int width)
53{
54 micro9_flash_data.width = width;
55
56 platform_device_register(&micro9_flash);
57}
58
59static unsigned int __init micro9_detect_bootwidth(void) 33static unsigned int __init micro9_detect_bootwidth(void)
60{ 34{
61 u32 v; 35 u32 v;
@@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void)
70 44
71static void __init micro9_register_flash(void) 45static void __init micro9_register_flash(void)
72{ 46{
47 unsigned int width;
48
73 if (machine_is_micro9()) 49 if (machine_is_micro9())
74 __micro9_register_flash(4); 50 width = 4;
75 else if (machine_is_micro9m() || machine_is_micro9s()) 51 else if (machine_is_micro9m() || machine_is_micro9s())
76 __micro9_register_flash(micro9_detect_bootwidth()); 52 width = micro9_detect_bootwidth();
53 else
54 width = 0;
55
56 if (width)
57 ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
77} 58}
78 59
79 60
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 388aec95f60e..5dded5884133 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -18,7 +18,6 @@
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/mtd/physmap.h>
22#include <linux/gpio.h> 21#include <linux/gpio.h>
23#include <linux/i2c.h> 22#include <linux/i2c.h>
24#include <linux/i2c-gpio.h> 23#include <linux/i2c-gpio.h>
@@ -29,26 +28,6 @@
29#include <asm/mach-types.h> 28#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
31 30
32static struct physmap_flash_data simone_flash_data = {
33 .width = 2,
34};
35
36static struct resource simone_flash_resource = {
37 .start = EP93XX_CS6_PHYS_BASE,
38 .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
39 .flags = IORESOURCE_MEM,
40};
41
42static struct platform_device simone_flash = {
43 .name = "physmap-flash",
44 .id = 0,
45 .num_resources = 1,
46 .resource = &simone_flash_resource,
47 .dev = {
48 .platform_data = &simone_flash_data,
49 },
50};
51
52static struct ep93xx_eth_data __initdata simone_eth_data = { 31static struct ep93xx_eth_data __initdata simone_eth_data = {
53 .phy_id = 1, 32 .phy_id = 1,
54}; 33};
@@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
77static void __init simone_init_machine(void) 56static void __init simone_init_machine(void)
78{ 57{
79 ep93xx_init_devices(); 58 ep93xx_init_devices();
80 59 ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
81 platform_device_register(&simone_flash);
82 ep93xx_register_eth(&simone_eth_data, 1); 60 ep93xx_register_eth(&simone_eth_data, 1);
83 ep93xx_register_fb(&simone_fb_info); 61 ep93xx_register_fb(&simone_fb_info);
84 ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info, 62 ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index ae7319e588c7..93aeab8af705 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -17,7 +17,6 @@
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/m48t86.h> 19#include <linux/m48t86.h>
20#include <linux/mtd/physmap.h>
21#include <linux/mtd/nand.h> 20#include <linux/mtd/nand.h>
22#include <linux/mtd/partitions.h> 21#include <linux/mtd/partitions.h>
23 22
@@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = {
173}; 172};
174 173
175 174
176/*************************************************************************
177 * NOR flash (TS-7200 only)
178 *************************************************************************/
179static struct physmap_flash_data ts72xx_nor_data = {
180 .width = 2,
181};
182
183static struct resource ts72xx_nor_resource = {
184 .start = EP93XX_CS6_PHYS_BASE,
185 .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
186 .flags = IORESOURCE_MEM,
187};
188
189static struct platform_device ts72xx_nor_flash = {
190 .name = "physmap-flash",
191 .id = 0,
192 .dev.platform_data = &ts72xx_nor_data,
193 .resource = &ts72xx_nor_resource,
194 .num_resources = 1,
195};
196
197static void __init ts72xx_register_flash(void) 175static void __init ts72xx_register_flash(void)
198{ 176{
177 /*
178 * TS7200 has NOR flash all other TS72xx board have NAND flash.
179 */
199 if (board_is_ts7200()) { 180 if (board_is_ts7200()) {
200 platform_device_register(&ts72xx_nor_flash); 181 ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
201 } else { 182 } else {
202 resource_size_t start; 183 resource_size_t start;
203 184
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-imx/Kconfig
index 742fd4e6dcb9..c5c0369bb481 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,42 +1,103 @@
1config IMX_HAVE_DMA_V1
2 bool
3
4if ARCH_MX1
5
6config SOC_IMX1
7 select CPU_ARM920T
8 select IMX_HAVE_DMA_V1
9 select IMX_HAVE_IOMUX_V1
10 bool
11
12comment "MX1 platforms:"
13config MACH_MXLADS
14 bool
15
16config ARCH_MX1ADS
17 bool "MX1ADS platform"
18 select MACH_MXLADS
19 select IMX_HAVE_PLATFORM_IMX_I2C
20 select IMX_HAVE_PLATFORM_IMX_UART
21 help
22 Say Y here if you are using Motorola MX1ADS/MXLADS boards
23
24config MACH_SCB9328
25 bool "Synertronixx scb9328"
26 select IMX_HAVE_PLATFORM_IMX_UART
27 help
28 Say Y here if you are using a Synertronixx scb9328 board
29
30endif
31
1if ARCH_MX2 32if ARCH_MX2
2 33
34config SOC_IMX21
35 select CPU_ARM926T
36 select ARCH_MXC_AUDMUX_V1
37 select IMX_HAVE_DMA_V1
38 select IMX_HAVE_IOMUX_V1
39 bool
40
41config SOC_IMX27
42 select CPU_ARM926T
43 select ARCH_MXC_AUDMUX_V1
44 select IMX_HAVE_DMA_V1
45 select IMX_HAVE_IOMUX_V1
46 bool
47
3choice 48choice
4 prompt "CPUs:" 49 prompt "CPUs:"
5 default MACH_MX21 50 default MACH_MX21
6 51
7config MACH_MX21 52config MACH_MX21
8 bool "i.MX21 support" 53 bool "i.MX21 support"
9 select ARCH_MXC_AUDMUX_V1 54 select SOC_IMX21
10 help 55 help
11 This enables support for Freescale's MX2 based i.MX21 processor. 56 This enables support for Freescale's MX2 based i.MX21 processor.
12 57
13config MACH_MX27 58config MACH_MX27
14 bool "i.MX27 support" 59 bool "i.MX27 support"
15 select ARCH_MXC_AUDMUX_V1 60 select SOC_IMX27
16 help 61 help
17 This enables support for Freescale's MX2 based i.MX27 processor. 62 This enables support for Freescale's MX2 based i.MX27 processor.
18 63
19endchoice 64endchoice
20 65
21comment "MX2 platforms:" 66endif
67
68if MACH_MX21
69
70comment "MX21 platforms:"
22 71
23config MACH_MX21ADS 72config MACH_MX21ADS
24 bool "MX21ADS platform" 73 bool "MX21ADS platform"
25 depends on MACH_MX21 74 select IMX_HAVE_PLATFORM_IMX_UART
75 select IMX_HAVE_PLATFORM_MXC_NAND
26 help 76 help
27 Include support for MX21ADS platform. This includes specific 77 Include support for MX21ADS platform. This includes specific
28 configurations for the board and its peripherals. 78 configurations for the board and its peripherals.
29 79
80endif
81
82if MACH_MX27
83
84comment "MX27 platforms:"
85
30config MACH_MX27ADS 86config MACH_MX27ADS
31 bool "MX27ADS platform" 87 bool "MX27ADS platform"
32 depends on MACH_MX27 88 select IMX_HAVE_PLATFORM_IMX_I2C
89 select IMX_HAVE_PLATFORM_IMX_UART
90 select IMX_HAVE_PLATFORM_MXC_NAND
33 help 91 help
34 Include support for MX27ADS platform. This includes specific 92 Include support for MX27ADS platform. This includes specific
35 configurations for the board and its peripherals. 93 configurations for the board and its peripherals.
36 94
37config MACH_PCM038 95config MACH_PCM038
38 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" 96 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
39 depends on MACH_MX27 97 select IMX_HAVE_PLATFORM_IMX_I2C
98 select IMX_HAVE_PLATFORM_IMX_UART
99 select IMX_HAVE_PLATFORM_MXC_NAND
100 select IMX_HAVE_PLATFORM_SPI_IMX
40 select MXC_ULPI if USB_ULPI 101 select MXC_ULPI if USB_ULPI
41 help 102 help
42 Include support for phyCORE-i.MX27 (aka pcm038) platform. This 103 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -58,7 +119,9 @@ endchoice
58 119
59config MACH_CPUIMX27 120config MACH_CPUIMX27
60 bool "Eukrea CPUIMX27 module" 121 bool "Eukrea CPUIMX27 module"
61 depends on MACH_MX27 122 select IMX_HAVE_PLATFORM_IMX_I2C
123 select IMX_HAVE_PLATFORM_IMX_UART
124 select IMX_HAVE_PLATFORM_MXC_NAND
62 help 125 help
63 Include support for Eukrea CPUIMX27 platform. This includes 126 Include support for Eukrea CPUIMX27 platform. This includes
64 specific configurations for the module and its peripherals. 127 specific configurations for the module and its peripherals.
@@ -67,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2
67 bool "CPUIMX27 integrates SDHC2 module" 130 bool "CPUIMX27 integrates SDHC2 module"
68 depends on MACH_CPUIMX27 131 depends on MACH_CPUIMX27
69 help 132 help
70 This adds support for the internal SDHC2 used on CPUIMX27 used 133 This adds support for the internal SDHC2 used on CPUIMX27
71 for wifi or eMMC. 134 for wifi or eMMC.
72 135
136config MACH_EUKREA_CPUIMX27_USEUART4
137 bool "CPUIMX27 integrates UART4 module"
138 depends on MACH_CPUIMX27
139 help
140 This adds support for the internal UART4 used on CPUIMX27
141 for bluetooth.
142
73choice 143choice
74 prompt "Baseboard" 144 prompt "Baseboard"
75 depends on MACH_CPUIMX27 145 depends on MACH_CPUIMX27
@@ -78,6 +148,8 @@ choice
78config MACH_EUKREA_MBIMX27_BASEBOARD 148config MACH_EUKREA_MBIMX27_BASEBOARD
79 prompt "Eukrea MBIMX27 development board" 149 prompt "Eukrea MBIMX27 development board"
80 bool 150 bool
151 select IMX_HAVE_PLATFORM_IMX_UART
152 select IMX_HAVE_PLATFORM_SPI_IMX
81 help 153 help
82 This adds board specific devices that can be found on Eukrea's 154 This adds board specific devices that can be found on Eukrea's
83 MBIMX27 evaluation board. 155 MBIMX27 evaluation board.
@@ -86,21 +158,24 @@ endchoice
86 158
87config MACH_MX27_3DS 159config MACH_MX27_3DS
88 bool "MX27PDK platform" 160 bool "MX27PDK platform"
89 depends on MACH_MX27 161 select IMX_HAVE_PLATFORM_IMX_UART
90 help 162 help
91 Include support for MX27PDK platform. This includes specific 163 Include support for MX27PDK platform. This includes specific
92 configurations for the board and its peripherals. 164 configurations for the board and its peripherals.
93 165
94config MACH_IMX27LITE 166config MACH_IMX27LITE
95 bool "LogicPD MX27 LITEKIT platform" 167 bool "LogicPD MX27 LITEKIT platform"
96 depends on MACH_MX27 168 select IMX_HAVE_PLATFORM_IMX_UART
97 help 169 help
98 Include support for MX27 LITEKIT platform. This includes specific 170 Include support for MX27 LITEKIT platform. This includes specific
99 configurations for the board and its peripherals. 171 configurations for the board and its peripherals.
100 172
101config MACH_PCA100 173config MACH_PCA100
102 bool "Phytec phyCARD-s (pca100)" 174 bool "Phytec phyCARD-s (pca100)"
103 depends on MACH_MX27 175 select IMX_HAVE_PLATFORM_IMX_I2C
176 select IMX_HAVE_PLATFORM_IMX_UART
177 select IMX_HAVE_PLATFORM_MXC_NAND
178 select IMX_HAVE_PLATFORM_SPI_IMX
104 select MXC_ULPI if USB_ULPI 179 select MXC_ULPI if USB_ULPI
105 help 180 help
106 Include support for phyCARD-s (aka pca100) platform. This 181 Include support for phyCARD-s (aka pca100) platform. This
@@ -108,7 +183,9 @@ config MACH_PCA100
108 183
109config MACH_MXT_TD60 184config MACH_MXT_TD60
110 bool "Maxtrack i-MXT TD60" 185 bool "Maxtrack i-MXT TD60"
111 depends on MACH_MX27 186 select IMX_HAVE_PLATFORM_IMX_I2C
187 select IMX_HAVE_PLATFORM_IMX_UART
188 select IMX_HAVE_PLATFORM_MXC_NAND
112 help 189 help
113 Include support for i-MXT (aka td60) platform. This 190 Include support for i-MXT (aka td60) platform. This
114 includes specific configurations for the module and its peripherals. 191 includes specific configurations for the module and its peripherals.
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-imx/Makefile
index e3254faac828..46a9fdfbbd15 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,14 +4,24 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := devices.o serial.o 7obj-y := devices.o
8 8
9obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o 9obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
10 10
11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o 11obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
12obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o 12obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
13
14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
16
17# Support for CMOS sensor interface
18obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
19
20obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
21obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
13 22
14obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 23obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
24
15obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 25obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
16obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o 26obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
17obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 27obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index e867398a8fdb..7988a85cf07d 100644
--- a/arch/arm/mach-mx2/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -1,3 +1,7 @@
1zreladdr-$(CONFIG_ARCH_MX1) := 0x08008000
2params_phys-$(CONFIG_ARCH_MX1) := 0x08000100
3initrd_phys-$(CONFIG_ARCH_MX1) := 0x08800000
4
1zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 5zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
2params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 6params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
3initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 7initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-imx/clock-imx1.c
index 6cf2d4a7511d..c05096c38301 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -2,18 +2,17 @@
2 * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix 2 * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License version 2 as
6 * the Free Software Foundation; either version 2 of the License, or 6 * published by the Free Software Foundation.
7 * (at your option) any later version.
8 * 7 *
9 * This program is distributed in the hope that it will be useful, 8 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 11 * GNU General Public License for more details.
13 * 12 *
14 * You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License along
15 * along with this program; if not, write to the Free Software 14 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 15 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
17 */ 16 */
18 17
19#include <linux/kernel.h> 18#include <linux/kernel.h>
@@ -29,7 +28,41 @@
29#include <mach/clock.h> 28#include <mach/clock.h>
30#include <mach/hardware.h> 29#include <mach/hardware.h>
31#include <mach/common.h> 30#include <mach/common.h>
32#include "crm_regs.h" 31
32#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
33
34/* CCM register addresses */
35#define CCM_CSCR IO_ADDR_CCM(0x0)
36#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
37#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
38#define CCM_PCDR IO_ADDR_CCM(0x20)
39
40#define CCM_CSCR_CLKO_OFFSET 29
41#define CCM_CSCR_CLKO_MASK (0x7 << 29)
42#define CCM_CSCR_USB_OFFSET 26
43#define CCM_CSCR_USB_MASK (0x7 << 26)
44#define CCM_CSCR_OSC_EN_SHIFT 17
45#define CCM_CSCR_SYSTEM_SEL (1 << 16)
46#define CCM_CSCR_BCLK_OFFSET 10
47#define CCM_CSCR_BCLK_MASK (0xf << 10)
48#define CCM_CSCR_PRESC (1 << 15)
49
50#define CCM_PCDR_PCLK3_OFFSET 16
51#define CCM_PCDR_PCLK3_MASK (0x7f << 16)
52#define CCM_PCDR_PCLK2_OFFSET 4
53#define CCM_PCDR_PCLK2_MASK (0xf << 4)
54#define CCM_PCDR_PCLK1_OFFSET 0
55#define CCM_PCDR_PCLK1_MASK 0xf
56
57#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
58
59/* SCM register addresses */
60#define SCM_GCCR IO_ADDR_SCM(0xc)
61
62#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
63#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
64#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
65#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
33 66
34static int _clk_enable(struct clk *clk) 67static int _clk_enable(struct clk *clk)
35{ 68{
@@ -596,7 +629,8 @@ int __init mx1_clocks_init(unsigned long fref)
596 clk_enable(&hclk); 629 clk_enable(&hclk);
597 clk_enable(&fclk); 630 clk_enable(&fclk);
598 631
599 mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT); 632 mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
633 MX1_TIM1_INT);
600 634
601 return 0; 635 return 0;
602} 636}
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bb419ef4d133..bb419ef4d133 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 0f0823c8b170..5a1aa15c8a16 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
644 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 644 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
645 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) 645 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
646 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 646 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
647 _REGISTER_CLOCK(NULL, "csi", csi_clk) 647 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
648 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) 648 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
649 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1) 649 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
650 _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk) 650 _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index d8d3b2d84dc5..d8d3b2d84dc5 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
new file mode 100644
index 000000000000..a8d94f078196
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx1.h>
10#include <mach/devices-common.h>
11
12#define imx1_add_i2c_imx(pdata) \
13 imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
14
15#define imx1_add_imx_uart0(pdata) \
16 imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
17#define imx1_add_imx_uart1(pdata) \
18 imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
new file mode 100644
index 000000000000..42788e99d127
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx21.h>
10#include <mach/devices-common.h>
11
12#define imx21_add_i2c_imx(pdata) \
13 imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
14
15#define imx21_add_imx_uart0(pdata) \
16 imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
17#define imx21_add_imx_uart1(pdata) \
18 imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
19#define imx21_add_imx_uart2(pdata) \
20 imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
21#define imx21_add_imx_uart3(pdata) \
22 imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
23
24#define imx21_add_mxc_nand(pdata) \
25 imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
26
27#define imx21_add_spi_imx0(pdata) \
28 imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
29#define imx21_add_spi_imx1(pdata) \
30 imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
new file mode 100644
index 000000000000..65e7bb7ec2e8
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx27.h>
10#include <mach/devices-common.h>
11
12#define imx27_add_i2c_imx0(pdata) \
13 imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
14#define imx27_add_i2c_imx1(pdata) \
15 imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
16
17#define imx27_add_imx_uart0(pdata) \
18 imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
19#define imx27_add_imx_uart1(pdata) \
20 imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
21#define imx27_add_imx_uart2(pdata) \
22 imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
23#define imx27_add_imx_uart3(pdata) \
24 imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
25#define imx27_add_imx_uart4(pdata) \
26 imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
27#define imx27_add_imx_uart5(pdata) \
28 imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
29
30#define imx27_add_mxc_nand(pdata) \
31 imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
32
33#define imx27_add_spi_imx0(pdata) \
34 imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
35#define imx27_add_spi_imx1(pdata) \
36 imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
37#define imx27_add_spi_imx2(pdata) \
38 imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-imx/devices.c
index a0aeb8a4adc1..9c271a752b84 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -11,6 +11,9 @@
11 * 11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. 12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
14 * 17 *
15 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License 19 * modify it under the terms of the GNU General Public License
@@ -32,6 +35,7 @@
32#include <linux/platform_device.h> 35#include <linux/platform_device.h>
33#include <linux/gpio.h> 36#include <linux/gpio.h>
34#include <linux/dma-mapping.h> 37#include <linux/dma-mapping.h>
38#include <linux/serial.h>
35 39
36#include <mach/irqs.h> 40#include <mach/irqs.h>
37#include <mach/hardware.h> 41#include <mach/hardware.h>
@@ -40,38 +44,179 @@
40 44
41#include "devices.h" 45#include "devices.h"
42 46
43/* 47#if defined(CONFIG_ARCH_MX1)
44 * SPI master controller 48static struct resource imx1_camera_resources[] = {
45 * 49 {
46 * - i.MX1: 2 channel (slighly different register setting) 50 .start = 0x00224000,
47 * - i.MX21: 2 channel 51 .end = 0x00224010,
48 * - i.MX27: 3 channel 52 .flags = IORESOURCE_MEM,
49 */ 53 }, {
50#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ 54 .start = MX1_CSI_INT,
51 static struct resource mxc_spi_resources ## n[] = { \ 55 .end = MX1_CSI_INT,
52 { \ 56 .flags = IORESOURCE_IRQ,
53 .start = baseaddr, \ 57 },
54 .end = baseaddr + SZ_4K - 1, \ 58};
55 .flags = IORESOURCE_MEM, \ 59
56 }, { \ 60static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
57 .start = irq, \ 61
58 .end = irq, \ 62struct platform_device imx1_camera_device = {
59 .flags = IORESOURCE_IRQ, \ 63 .name = "mx1-camera",
60 }, \ 64 .id = 0, /* This is used to put cameras on this interface */
61 }; \ 65 .dev = {
62 \ 66 .dma_mask = &imx1_camera_dmamask,
63 struct platform_device mxc_spi_device ## n = { \ 67 .coherent_dma_mask = DMA_BIT_MASK(32),
64 .name = "spi_imx", \ 68 },
65 .id = n, \ 69 .resource = imx1_camera_resources,
66 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ 70 .num_resources = ARRAY_SIZE(imx1_camera_resources),
67 .resource = mxc_spi_resources ## n, \ 71};
72
73static struct resource imx_rtc_resources[] = {
74 {
75 .start = 0x00204000,
76 .end = 0x00204024,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX1_RTC_INT,
80 .end = MX1_RTC_INT,
81 .flags = IORESOURCE_IRQ,
82 }, {
83 .start = MX1_RTC_SAMINT,
84 .end = MX1_RTC_SAMINT,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89struct platform_device imx_rtc_device = {
90 .name = "rtc-imx",
91 .id = 0,
92 .resource = imx_rtc_resources,
93 .num_resources = ARRAY_SIZE(imx_rtc_resources),
94};
95
96static struct resource imx_wdt_resources[] = {
97 {
98 .start = 0x00201000,
99 .end = 0x00201008,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = MX1_WDT_INT,
103 .end = MX1_WDT_INT,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108struct platform_device imx_wdt_device = {
109 .name = "imx-wdt",
110 .id = 0,
111 .resource = imx_wdt_resources,
112 .num_resources = ARRAY_SIZE(imx_wdt_resources),
113};
114
115static struct resource imx_usb_resources[] = {
116 {
117 .start = 0x00212000,
118 .end = 0x00212148,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = MX1_USBD_INT0,
122 .end = MX1_USBD_INT0,
123 .flags = IORESOURCE_IRQ,
124 }, {
125 .start = MX1_USBD_INT1,
126 .end = MX1_USBD_INT1,
127 .flags = IORESOURCE_IRQ,
128 }, {
129 .start = MX1_USBD_INT2,
130 .end = MX1_USBD_INT2,
131 .flags = IORESOURCE_IRQ,
132 }, {
133 .start = MX1_USBD_INT3,
134 .end = MX1_USBD_INT3,
135 .flags = IORESOURCE_IRQ,
136 }, {
137 .start = MX1_USBD_INT4,
138 .end = MX1_USBD_INT4,
139 .flags = IORESOURCE_IRQ,
140 }, {
141 .start = MX1_USBD_INT5,
142 .end = MX1_USBD_INT5,
143 .flags = IORESOURCE_IRQ,
144 }, {
145 .start = MX1_USBD_INT6,
146 .end = MX1_USBD_INT6,
147 .flags = IORESOURCE_IRQ,
148 },
149};
150
151struct platform_device imx_usb_device = {
152 .name = "imx_udc",
153 .id = 0,
154 .num_resources = ARRAY_SIZE(imx_usb_resources),
155 .resource = imx_usb_resources,
156};
157
158/* GPIO port description */
159static struct mxc_gpio_port imx_gpio_ports[] = {
160 {
161 .chip.label = "gpio-0",
162 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
163 .irq = MX1_GPIO_INT_PORTA,
164 .virtual_irq_start = MXC_GPIO_IRQ_START,
165 }, {
166 .chip.label = "gpio-1",
167 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
168 .irq = MX1_GPIO_INT_PORTB,
169 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
170 }, {
171 .chip.label = "gpio-2",
172 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
173 .irq = MX1_GPIO_INT_PORTC,
174 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
175 }, {
176 .chip.label = "gpio-3",
177 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
178 .irq = MX1_GPIO_INT_PORTD,
179 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
68 } 180 }
181};
182
183int __init imx1_register_gpios(void)
184{
185 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
186}
187#endif
69 188
70DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); 189#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
71DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
72 190
73#ifdef CONFIG_MACH_MX27 191#ifdef CONFIG_MACH_MX27
74DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); 192static struct resource mx27_camera_resources[] = {
193 {
194 .start = MX27_CSI_BASE_ADDR,
195 .end = MX27_CSI_BASE_ADDR + 0x1f,
196 .flags = IORESOURCE_MEM,
197 }, {
198 .start = MX27_EMMA_PRP_BASE_ADDR,
199 .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
200 .flags = IORESOURCE_MEM,
201 }, {
202 .start = MX27_INT_CSI,
203 .end = MX27_INT_CSI,
204 .flags = IORESOURCE_IRQ,
205 },{
206 .start = MX27_INT_EMMAPRP,
207 .end = MX27_INT_EMMAPRP,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211struct platform_device mx27_camera_device = {
212 .name = "mx2-camera",
213 .id = 0,
214 .num_resources = ARRAY_SIZE(mx27_camera_resources),
215 .resource = mx27_camera_resources,
216 .dev = {
217 .coherent_dma_mask = 0xffffffff,
218 },
219};
75#endif 220#endif
76 221
77/* 222/*
@@ -140,34 +285,6 @@ struct platform_device mxc_w1_master_device = {
140 .resource = mxc_w1_master_resources, 285 .resource = mxc_w1_master_resources,
141}; 286};
142 287
143#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
144 static struct resource pfx ## _nand_resources[] = { \
145 { \
146 .start = baseaddr, \
147 .end = baseaddr + SZ_4K - 1, \
148 .flags = IORESOURCE_MEM, \
149 }, { \
150 .start = irq, \
151 .end = irq, \
152 .flags = IORESOURCE_IRQ, \
153 }, \
154 }; \
155 \
156 struct platform_device pfx ## _nand_device = { \
157 .name = "mxc_nand", \
158 .id = 0, \
159 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
160 .resource = pfx ## _nand_resources, \
161 }
162
163#ifdef CONFIG_MACH_MX21
164DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
165#endif
166
167#ifdef CONFIG_MACH_MX27
168DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
169#endif
170
171/* 288/*
172 * lcdc: 289 * lcdc:
173 * - i.MX1: the basic controller 290 * - i.MX1: the basic controller
@@ -218,32 +335,6 @@ struct platform_device mxc_fec_device = {
218}; 335};
219#endif 336#endif
220 337
221#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
222 static struct resource mxc_i2c_resources ## n[] = { \
223 { \
224 .start = baseaddr, \
225 .end = baseaddr + SZ_4K - 1, \
226 .flags = IORESOURCE_MEM, \
227 }, { \
228 .start = irq, \
229 .end = irq, \
230 .flags = IORESOURCE_IRQ, \
231 } \
232 }; \
233 \
234 struct platform_device mxc_i2c_device ## n = { \
235 .name = "imx-i2c", \
236 .id = n, \
237 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
238 .resource = mxc_i2c_resources ## n, \
239 }
240
241DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
242
243#ifdef CONFIG_MACH_MX27
244DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
245#endif
246
247static struct resource mxc_pwm_resources[] = { 338static struct resource mxc_pwm_resources[] = {
248 { 339 {
249 .start = MX2x_PWM_BASE_ADDR, 340 .start = MX2x_PWM_BASE_ADDR,
@@ -454,26 +545,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
454 545
455#ifdef CONFIG_MACH_MX21 546#ifdef CONFIG_MACH_MX21
456DEFINE_MXC_GPIO_PORTS(MX21, imx21); 547DEFINE_MXC_GPIO_PORTS(MX21, imx21);
548
549int __init imx21_register_gpios(void)
550{
551 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
552}
457#endif 553#endif
458 554
459#ifdef CONFIG_MACH_MX27 555#ifdef CONFIG_MACH_MX27
460DEFINE_MXC_GPIO_PORTS(MX27, imx27); 556DEFINE_MXC_GPIO_PORTS(MX27, imx27);
461#endif
462 557
463int __init mxc_register_gpios(void) 558int __init imx27_register_gpios(void)
464{ 559{
465#ifdef CONFIG_MACH_MX21 560 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
466 if (cpu_is_mx21())
467 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
468 else
469#endif
470#ifdef CONFIG_MACH_MX27
471 if (cpu_is_mx27())
472 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
473 else
474#endif
475 return 0;
476} 561}
562#endif
477 563
478#ifdef CONFIG_MACH_MX21 564#ifdef CONFIG_MACH_MX21
479static struct resource mx21_usbhc_resources[] = { 565static struct resource mx21_usbhc_resources[] = {
@@ -501,3 +587,23 @@ struct platform_device mx21_usbhc_device = {
501}; 587};
502#endif 588#endif
503 589
590static struct resource imx_kpp_resources[] = {
591 {
592 .start = MX2x_KPP_BASE_ADDR,
593 .end = MX2x_KPP_BASE_ADDR + 0xf,
594 .flags = IORESOURCE_MEM
595 }, {
596 .start = MX2x_INT_KPP,
597 .end = MX2x_INT_KPP,
598 .flags = IORESOURCE_IRQ,
599 },
600};
601
602struct platform_device imx_kpp_device = {
603 .name = "imx-keypad",
604 .id = -1,
605 .num_resources = ARRAY_SIZE(imx_kpp_resources),
606 .resource = imx_kpp_resources,
607};
608
609#endif
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-imx/devices.h
index 84ed51380174..efd4527506a5 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -1,3 +1,11 @@
1#ifdef CONFIG_ARCH_MX1
2extern struct platform_device imx1_camera_device;
3extern struct platform_device imx_rtc_device;
4extern struct platform_device imx_wdt_device;
5extern struct platform_device imx_usb_device;
6#endif
7
8#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
1extern struct platform_device mxc_gpt1; 9extern struct platform_device mxc_gpt1;
2extern struct platform_device mxc_gpt2; 10extern struct platform_device mxc_gpt2;
3#ifdef CONFIG_MACH_MX27 11#ifdef CONFIG_MACH_MX27
@@ -6,37 +14,19 @@ extern struct platform_device mxc_gpt4;
6extern struct platform_device mxc_gpt5; 14extern struct platform_device mxc_gpt5;
7#endif 15#endif
8extern struct platform_device mxc_wdt; 16extern struct platform_device mxc_wdt;
9extern struct platform_device mxc_uart_device0;
10extern struct platform_device mxc_uart_device1;
11extern struct platform_device mxc_uart_device2;
12extern struct platform_device mxc_uart_device3;
13extern struct platform_device mxc_uart_device4;
14extern struct platform_device mxc_uart_device5;
15extern struct platform_device mxc_w1_master_device; 17extern struct platform_device mxc_w1_master_device;
16#ifdef CONFIG_MACH_MX21
17extern struct platform_device imx21_nand_device;
18#endif
19#ifdef CONFIG_MACH_MX27
20extern struct platform_device imx27_nand_device;
21#endif
22extern struct platform_device mxc_fb_device; 18extern struct platform_device mxc_fb_device;
23extern struct platform_device mxc_fec_device; 19extern struct platform_device mxc_fec_device;
24extern struct platform_device mxc_pwm_device; 20extern struct platform_device mxc_pwm_device;
25extern struct platform_device mxc_i2c_device0;
26#ifdef CONFIG_MACH_MX27
27extern struct platform_device mxc_i2c_device1;
28#endif
29extern struct platform_device mxc_sdhc_device0; 21extern struct platform_device mxc_sdhc_device0;
30extern struct platform_device mxc_sdhc_device1; 22extern struct platform_device mxc_sdhc_device1;
31extern struct platform_device mxc_otg_udc_device; 23extern struct platform_device mxc_otg_udc_device;
24extern struct platform_device mx27_camera_device;
32extern struct platform_device mxc_otg_host; 25extern struct platform_device mxc_otg_host;
33extern struct platform_device mxc_usbh1; 26extern struct platform_device mxc_usbh1;
34extern struct platform_device mxc_usbh2; 27extern struct platform_device mxc_usbh2;
35extern struct platform_device mxc_spi_device0;
36extern struct platform_device mxc_spi_device1;
37#ifdef CONFIG_MACH_MX27
38extern struct platform_device mxc_spi_device2;
39#endif
40extern struct platform_device mx21_usbhc_device; 28extern struct platform_device mx21_usbhc_device;
41extern struct platform_device imx_ssi_device0; 29extern struct platform_device imx_ssi_device0;
42extern struct platform_device imx_ssi_device1; 30extern struct platform_device imx_ssi_device1;
31extern struct platform_device imx_kpp_device;
32#endif
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/mach-imx/dma-v1.c
index e16014b0d13c..fd1d9197d06e 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/plat-mxc/dma-mx1-mx2.c 2 * linux/arch/arm/plat-mxc/dma-v1.c
3 * 3 *
4 * i.MX DMA registration and IRQ dispatching 4 * i.MX DMA registration and IRQ dispatching
5 * 5 *
@@ -34,7 +34,7 @@
34#include <asm/system.h> 34#include <asm/system.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/dma-mx1-mx2.h> 37#include <mach/dma-v1.h>
38 38
39#define DMA_DCR 0x00 /* Control Register */ 39#define DMA_DCR 0x00 /* Control Register */
40#define DMA_DISR 0x04 /* Interrupt status Register */ 40#define DMA_DISR 0x04 /* Interrupt status Register */
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index f3b169d5245f..4edc5f439201 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com 2 * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
3 * 3 *
4 * Based on pcm970-baseboard.c which is : 4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -24,6 +24,9 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h> 26#include <linux/spi/ads7846.h>
27#include <linux/backlight.h>
28#include <video/platform_lcd.h>
29#include <linux/input/matrix_keypad.h>
27 30
28#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
29 32
@@ -32,8 +35,11 @@
32#include <mach/imxfb.h> 35#include <mach/imxfb.h>
33#include <mach/hardware.h> 36#include <mach/hardware.h>
34#include <mach/mmc.h> 37#include <mach/mmc.h>
35#include <mach/imx-uart.h> 38#include <mach/spi.h>
39#include <mach/ssi.h>
40#include <mach/audmux.h>
36 41
42#include "devices-imx27.h"
37#include "devices.h" 43#include "devices.h"
38 44
39static int eukrea_mbimx27_pins[] = { 45static int eukrea_mbimx27_pins[] = {
@@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = {
48 PE10_PF_UART3_CTS, 54 PE10_PF_UART3_CTS,
49 PE11_PF_UART3_RTS, 55 PE11_PF_UART3_RTS,
50 /* UART4 */ 56 /* UART4 */
57#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
51 PB26_AF_UART4_RTS, 58 PB26_AF_UART4_RTS,
52 PB28_AF_UART4_TXD, 59 PB28_AF_UART4_TXD,
53 PB29_AF_UART4_CTS, 60 PB29_AF_UART4_CTS,
54 PB31_AF_UART4_RXD, 61 PB31_AF_UART4_RXD,
62#endif
55 /* SDHC1*/ 63 /* SDHC1*/
56 PE18_PF_SD1_D0, 64 PE18_PF_SD1_D0,
57 PE19_PF_SD1_D1, 65 PE19_PF_SD1_D1,
@@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = {
84 PA30_PF_CONTRAST, 92 PA30_PF_CONTRAST,
85 PA31_PF_OE_ACD, 93 PA31_PF_OE_ACD,
86 /* SPI1 */ 94 /* SPI1 */
87 PD28_PF_CSPI1_SS0,
88 PD29_PF_CSPI1_SCLK, 95 PD29_PF_CSPI1_SCLK,
89 PD30_PF_CSPI1_MISO, 96 PD30_PF_CSPI1_MISO,
90 PD31_PF_CSPI1_MOSI, 97 PD31_PF_CSPI1_MOSI,
98 /* SSI4 */
99#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
100 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
101 PC16_PF_SSI4_FS,
102 PC17_PF_SSI4_RXD | GPIO_PUEN,
103 PC18_PF_SSI4_TXD | GPIO_PUEN,
104 PC19_PF_SSI4_CLK,
105#endif
106};
107
108static const uint32_t eukrea_mbimx27_keymap[] = {
109 KEY(0, 0, KEY_UP),
110 KEY(0, 1, KEY_DOWN),
111 KEY(1, 0, KEY_RIGHT),
112 KEY(1, 1, KEY_LEFT),
113};
114
115static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
116 .keymap = eukrea_mbimx27_keymap,
117 .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
91}; 118};
92 119
93static struct gpio_led gpio_leds[] = { 120static struct gpio_led gpio_leds[] = {
@@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = {
103 .active_low = 1, 130 .active_low = 1,
104 .gpio = GPIO_PORTF | 19, 131 .gpio = GPIO_PORTF | 19,
105 }, 132 },
106 {
107 .name = "backlight",
108 .default_trigger = "backlight",
109 .active_low = 0,
110 .gpio = GPIO_PORTE | 5,
111 },
112}; 133};
113 134
114static struct gpio_led_platform_data gpio_led_info = { 135static struct gpio_led_platform_data gpio_led_info = {
@@ -127,7 +148,7 @@ static struct platform_device leds_gpio = {
127static struct imx_fb_videomode eukrea_mbimx27_modes[] = { 148static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
128 { 149 {
129 .mode = { 150 .mode = {
130 .name = "CMO-QGVA", 151 .name = "CMO-QVGA",
131 .refresh = 60, 152 .refresh = 60,
132 .xres = 320, 153 .xres = 320,
133 .yres = 240, 154 .yres = 240,
@@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
141 }, 162 },
142 .pcr = 0xFAD08B80, 163 .pcr = 0xFAD08B80,
143 .bpp = 16, 164 .bpp = 16,
165 }, {
166 .mode = {
167 .name = "DVI-VGA",
168 .refresh = 60,
169 .xres = 640,
170 .yres = 480,
171 .pixclock = 32000,
172 .hsync_len = 1,
173 .left_margin = 35,
174 .right_margin = 0,
175 .vsync_len = 1,
176 .upper_margin = 7,
177 .lower_margin = 0,
178 },
179 .pcr = 0xFA208B80,
180 .bpp = 16,
181 }, {
182 .mode = {
183 .name = "DVI-SVGA",
184 .refresh = 60,
185 .xres = 800,
186 .yres = 600,
187 .pixclock = 25000,
188 .hsync_len = 1,
189 .left_margin = 35,
190 .right_margin = 0,
191 .vsync_len = 1,
192 .upper_margin = 7,
193 .lower_margin = 0,
194 },
195 .pcr = 0xFA208B80,
196 .bpp = 16,
144 }, 197 },
145}; 198};
146 199
@@ -153,16 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
153 .dmacr = 0x00040060, 206 .dmacr = 0x00040060,
154}; 207};
155 208
156static struct imxuart_platform_data uart_pdata[] = { 209static void eukrea_mbimx27_bl_set_intensity(int intensity)
157 { 210{
158 .flags = IMXUART_HAVE_RTSCTS, 211 if (intensity)
159 }, 212 gpio_direction_output(GPIO_PORTE | 5, 1);
160 { 213 else
161 .flags = IMXUART_HAVE_RTSCTS, 214 gpio_direction_output(GPIO_PORTE | 5, 0);
215}
216
217static struct generic_bl_info eukrea_mbimx27_bl_info = {
218 .name = "eukrea_mbimx27-bl",
219 .max_intensity = 0xff,
220 .default_intensity = 0xff,
221 .set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
222};
223
224static struct platform_device eukrea_mbimx27_bl_dev = {
225 .name = "generic-bl",
226 .id = 1,
227 .dev = {
228 .platform_data = &eukrea_mbimx27_bl_info,
162 }, 229 },
163}; 230};
164 231
165#if defined(CONFIG_TOUCHSCREEN_ADS7846) 232static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
233 unsigned int power)
234{
235 if (power)
236 gpio_direction_output(GPIO_PORTA | 25, 1);
237 else
238 gpio_direction_output(GPIO_PORTA | 25, 0);
239}
240
241static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
242 .set_power = eukrea_mbimx27_lcd_power_set,
243};
244
245static struct platform_device eukrea_mbimx27_lcd_powerdev = {
246 .name = "platform-lcd",
247 .dev.platform_data = &eukrea_mbimx27_lcd_power_data,
248};
249
250static const struct imxuart_platform_data uart_pdata __initconst = {
251 .flags = IMXUART_HAVE_RTSCTS,
252};
253
254#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
166 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 255 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
167 256
168#define ADS7846_PENDOWN (GPIO_PORTD | 25) 257#define ADS7846_PENDOWN (GPIO_PORTD | 25)
@@ -173,7 +262,6 @@ static void ads7846_dev_init(void)
173 printk(KERN_ERR "can't get ads746 pen down GPIO\n"); 262 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
174 return; 263 return;
175 } 264 }
176
177 gpio_direction_input(ADS7846_PENDOWN); 265 gpio_direction_input(ADS7846_PENDOWN);
178} 266}
179 267
@@ -186,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = {
186 .get_pendown_state = ads7846_get_pendown_state, 274 .get_pendown_state = ads7846_get_pendown_state,
187 .keep_vref_on = 1, 275 .keep_vref_on = 1,
188}; 276};
277#endif
189 278
279#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
190static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { 280static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
191 [0] = { 281 [0] = {
192 .modalias = "ads7846", 282 .modalias = "ads7846",
@@ -201,16 +291,30 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
201 291
202static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28}; 292static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
203 293
204static struct spi_imx_master eukrea_mbimx27_spi_0_data = { 294static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
205 .chipselect = eukrea_mbimx27_spi_cs, 295 .chipselect = eukrea_mbimx27_spi_cs,
206 .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs), 296 .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
207}; 297};
208#endif 298#endif
209 299
300static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
301 {
302 I2C_BOARD_INFO("tlv320aic23", 0x1a),
303 },
304};
305
210static struct platform_device *platform_devices[] __initdata = { 306static struct platform_device *platform_devices[] __initdata = {
211 &leds_gpio, 307 &leds_gpio,
212}; 308};
213 309
310static struct imxmmc_platform_data sdhc_pdata = {
311 .dat3_card_detect = 1,
312};
313
314struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
315 .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
316};
317
214/* 318/*
215 * system init for baseboard usage. Will be called by cpuimx27 init. 319 * system init for baseboard usage. Will be called by cpuimx27 init.
216 * 320 *
@@ -222,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void)
222 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins, 326 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
223 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27"); 327 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
224 328
225 mxc_register_device(&mxc_uart_device1, &uart_pdata[0]); 329#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
226 mxc_register_device(&mxc_uart_device2, &uart_pdata[1]); 330 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
331 /* SSI unit master I2S codec connected to SSI_PINS_4*/
332 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
333 MXC_AUDMUX_V1_PCR_SYN |
334 MXC_AUDMUX_V1_PCR_TFSDIR |
335 MXC_AUDMUX_V1_PCR_TCLKDIR |
336 MXC_AUDMUX_V1_PCR_RFSDIR |
337 MXC_AUDMUX_V1_PCR_RCLKDIR |
338 MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
339 MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
340 MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
341 );
342 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
343 MXC_AUDMUX_V1_PCR_SYN |
344 MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
345 );
346#endif
347
348 imx27_add_imx_uart1(&uart_pdata);
349 imx27_add_imx_uart2(&uart_pdata);
350#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
351 imx27_add_imx_uart3(&uart_pdata);
352#endif
227 353
228 mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); 354 mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
229 mxc_register_device(&mxc_sdhc_device0, NULL); 355 mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
230 356
231#if defined(CONFIG_TOUCHSCREEN_ADS7846) 357 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
358 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
359
360 mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
361
362#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
232 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 363 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
233 /* SPI and ADS7846 Touchscreen controler init */ 364 /* ADS7846 Touchscreen controller init */
234 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
235 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN); 365 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
236 mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data); 366 ads7846_dev_init();
367#endif
368
369#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
370 /* SPI_CS0 init */
371 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
372 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
237 spi_register_board_info(eukrea_mbimx27_spi_board_info, 373 spi_register_board_info(eukrea_mbimx27_spi_board_info,
238 ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); 374 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
239 ads7846_dev_init();
240#endif 375#endif
241 376
242 /* Leds configuration */ 377 /* Leds configuration */
@@ -244,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void)
244 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT); 379 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
245 /* Backlight */ 380 /* Backlight */
246 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT); 381 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
382 gpio_request(GPIO_PORTE | 5, "backlight");
383 platform_device_register(&eukrea_mbimx27_bl_dev);
384 /* LCD Reset */
385 mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
386 gpio_request(GPIO_PORTA | 25, "lcd_enable");
387 platform_device_register(&eukrea_mbimx27_lcd_powerdev);
388
389 mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
247 390
248 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 391 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
249} 392}
diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
new file mode 100644
index 000000000000..df5f522da6b3
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,10 @@
1#ifndef __MACH_DMA_MX1_MX2_H__
2#define __MACH_DMA_MX1_MX2_H__
3/*
4 * Don't use this header in new code, it will go away when all users are
5 * converted to mach/dma-v1.h
6 */
7
8#include <mach/dma-v1.h>
9
10#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-v1.h
index 7c4870bd5a21..287431cc13e5 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/mach-imx/include/mach/dma-v1.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h 2 * linux/arch/arm/mach-imx/include/mach/dma-v1.h
3 * 3 *
4 * i.MX DMA registration and IRQ dispatching 4 * i.MX DMA registration and IRQ dispatching
5 * 5 *
@@ -22,8 +22,10 @@
22 * MA 02110-1301, USA. 22 * MA 02110-1301, USA.
23 */ 23 */
24 24
25#ifndef __ASM_ARCH_MXC_DMA_H 25#ifndef __MACH_DMA_V1_H__
26#define __ASM_ARCH_MXC_DMA_H 26#define __MACH_DMA_V1_H__
27
28#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
27 29
28#define IMX_DMA_CHANNELS 16 30#define IMX_DMA_CHANNELS 16
29 31
@@ -102,4 +104,4 @@ enum imx_dma_prio {
102 104
103int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); 105int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
104 106
105#endif /* _ASM_ARCH_MXC_DMA_H */ 107#endif /* __MACH_DMA_V1_H__ */
diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 1f616dcaabc9..575ff1ae85a7 100644
--- a/arch/arm/mach-mx2/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -26,20 +26,24 @@
26#include <linux/mtd/physmap.h> 26#include <linux/mtd/physmap.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/serial_8250.h> 28#include <linux/serial_8250.h>
29#include <linux/usb/otg.h>
30#include <linux/usb/ulpi.h>
31#include <linux/fsl_devices.h>
29 32
30#include <asm/mach-types.h> 33#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
32#include <asm/mach/time.h> 35#include <asm/mach/time.h>
33#include <asm/mach/map.h> 36#include <asm/mach/map.h>
34 37
35#include <mach/board-eukrea_cpuimx27.h> 38#include <mach/eukrea-baseboards.h>
36#include <mach/common.h> 39#include <mach/common.h>
37#include <mach/hardware.h> 40#include <mach/hardware.h>
38#include <mach/i2c.h>
39#include <mach/iomux-mx27.h> 41#include <mach/iomux-mx27.h>
40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h> 42#include <mach/mxc_nand.h>
43#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h>
42 45
46#include "devices-imx27.h"
43#include "devices.h" 47#include "devices.h"
44 48
45static int eukrea_cpuimx27_pins[] = { 49static int eukrea_cpuimx27_pins[] = {
@@ -49,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = {
49 PE14_PF_UART1_CTS, 53 PE14_PF_UART1_CTS,
50 PE15_PF_UART1_RTS, 54 PE15_PF_UART1_RTS,
51 /* UART4 */ 55 /* UART4 */
56#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
52 PB26_AF_UART4_RTS, 57 PB26_AF_UART4_RTS,
53 PB28_AF_UART4_TXD, 58 PB28_AF_UART4_TXD,
54 PB29_AF_UART4_CTS, 59 PB29_AF_UART4_CTS,
55 PB31_AF_UART4_RXD, 60 PB31_AF_UART4_RXD,
61#endif
56 /* FEC */ 62 /* FEC */
57 PD0_AIN_FEC_TXD0, 63 PD0_AIN_FEC_TXD0,
58 PD1_AIN_FEC_TXD1, 64 PD1_AIN_FEC_TXD1,
@@ -76,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = {
76 PD17_PF_I2C_DATA, 82 PD17_PF_I2C_DATA,
77 PD18_PF_I2C_CLK, 83 PD18_PF_I2C_CLK,
78 /* SDHC2 */ 84 /* SDHC2 */
85#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
79 PB4_PF_SD2_D0, 86 PB4_PF_SD2_D0,
80 PB5_PF_SD2_D1, 87 PB5_PF_SD2_D1,
81 PB6_PF_SD2_D2, 88 PB6_PF_SD2_D2,
82 PB7_PF_SD2_D3, 89 PB7_PF_SD2_D3,
83 PB8_PF_SD2_CMD, 90 PB8_PF_SD2_CMD,
84 PB9_PF_SD2_CLK, 91 PB9_PF_SD2_CLK,
92#endif
85#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 93#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
86 /* Quad UART's IRQ */ 94 /* Quad UART's IRQ */
87 GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN, 95 GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
88 GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN, 96 GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
89 GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN, 97 GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
90 GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN, 98 GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
91#endif 99#endif
100 /* OTG */
101 PC7_PF_USBOTG_DATA5,
102 PC8_PF_USBOTG_DATA6,
103 PC9_PF_USBOTG_DATA0,
104 PC10_PF_USBOTG_DATA2,
105 PC11_PF_USBOTG_DATA1,
106 PC12_PF_USBOTG_DATA4,
107 PC13_PF_USBOTG_DATA3,
108 PE0_PF_USBOTG_NXT,
109 PE1_PF_USBOTG_STP,
110 PE2_PF_USBOTG_DIR,
111 PE24_PF_USBOTG_CLK,
112 PE25_PF_USBOTG_DATA7,
113 /* USBH2 */
114 PA0_PF_USBH2_CLK,
115 PA1_PF_USBH2_DIR,
116 PA2_PF_USBH2_DATA7,
117 PA3_PF_USBH2_NXT,
118 PA4_PF_USBH2_STP,
119 PD19_AF_USBH2_DATA4,
120 PD20_AF_USBH2_DATA3,
121 PD21_AF_USBH2_DATA6,
122 PD22_AF_USBH2_DATA0,
123 PD23_AF_USBH2_DATA2,
124 PD24_AF_USBH2_DATA1,
125 PD26_AF_USBH2_DATA5,
92}; 126};
93 127
94static struct physmap_flash_data eukrea_cpuimx27_flash_data = { 128static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
@@ -111,15 +145,12 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
111 .resource = &eukrea_cpuimx27_flash_resource, 145 .resource = &eukrea_cpuimx27_flash_resource,
112}; 146};
113 147
114static struct imxuart_platform_data uart_pdata[] = { 148static const struct imxuart_platform_data uart_pdata __initconst = {
115 { 149 .flags = IMXUART_HAVE_RTSCTS,
116 .flags = IMXUART_HAVE_RTSCTS,
117 }, {
118 .flags = IMXUART_HAVE_RTSCTS,
119 },
120}; 150};
121 151
122static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = { 152static const struct mxc_nand_platform_data
153cpuimx27_nand_board_info __initconst = {
123 .width = 1, 154 .width = 1,
124 .hw_ecc = 1, 155 .hw_ecc = 1,
125}; 156};
@@ -127,9 +158,11 @@ static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
127static struct platform_device *platform_devices[] __initdata = { 158static struct platform_device *platform_devices[] __initdata = {
128 &eukrea_cpuimx27_nor_mtd_device, 159 &eukrea_cpuimx27_nor_mtd_device,
129 &mxc_fec_device, 160 &mxc_fec_device,
161 &mxc_wdt,
162 &mxc_w1_master_device,
130}; 163};
131 164
132static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = { 165static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
133 .bitrate = 100000, 166 .bitrate = 100000,
134}; 167};
135 168
@@ -182,34 +215,83 @@ static struct platform_device serial_device = {
182}; 215};
183#endif 216#endif
184 217
218#if defined(CONFIG_USB_ULPI)
219static struct mxc_usbh_platform_data otg_pdata = {
220 .portsc = MXC_EHCI_MODE_ULPI,
221 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
222};
223
224static struct mxc_usbh_platform_data usbh2_pdata = {
225 .portsc = MXC_EHCI_MODE_ULPI,
226 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
227};
228#endif
229
230static struct fsl_usb2_platform_data otg_device_pdata = {
231 .operating_mode = FSL_USB2_DR_DEVICE,
232 .phy_mode = FSL_USB2_PHY_ULPI,
233};
234
235static int otg_mode_host;
236
237static int __init eukrea_cpuimx27_otg_mode(char *options)
238{
239 if (!strcmp(options, "host"))
240 otg_mode_host = 1;
241 else if (!strcmp(options, "device"))
242 otg_mode_host = 0;
243 else
244 pr_info("otg_mode neither \"host\" nor \"device\". "
245 "Defaulting to device\n");
246 return 0;
247}
248__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
249
185static void __init eukrea_cpuimx27_init(void) 250static void __init eukrea_cpuimx27_init(void)
186{ 251{
187 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins, 252 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
188 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27"); 253 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
189 254
190 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 255 imx27_add_imx_uart0(&uart_pdata);
191 256
192 mxc_register_device(&imx27_nand_device, 257 imx27_add_mxc_nand(&cpuimx27_nand_board_info);
193 &eukrea_cpuimx27_nand_board_info);
194 258
195 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, 259 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
196 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); 260 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
197 261
198 mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data); 262 imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
199 263
200 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 264 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
201 265
202#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) 266#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
203 /* SDHC2 can be used for Wifi */ 267 /* SDHC2 can be used for Wifi */
204 mxc_register_device(&mxc_sdhc_device1, NULL); 268 mxc_register_device(&mxc_sdhc_device1, NULL);
269#endif
270#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
205 /* in which case UART4 is also used for Bluetooth */ 271 /* in which case UART4 is also used for Bluetooth */
206 mxc_register_device(&mxc_uart_device3, &uart_pdata[1]); 272 imx27_add_imx_uart3(&uart_pdata);
207#endif 273#endif
208 274
209#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 275#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
210 platform_device_register(&serial_device); 276 platform_device_register(&serial_device);
211#endif 277#endif
212 278
279#if defined(CONFIG_USB_ULPI)
280 if (otg_mode_host) {
281 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
282 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
283
284 mxc_register_device(&mxc_otg_host, &otg_pdata);
285 }
286
287 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
288 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
289
290 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
291#endif
292 if (!otg_mode_host)
293 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
294
213#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD 295#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
214 eukrea_mbimx27_baseboard_init(); 296 eukrea_mbimx27_baseboard_init();
215#endif 297#endif
diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index b5710bf18b96..22a2b5d91213 100644
--- a/arch/arm/mach-mx2/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#include <linux/platform_device.h> 17#include <linux/platform_device.h>
@@ -26,10 +22,9 @@
26#include <asm/mach/map.h> 22#include <asm/mach/map.h>
27#include <mach/hardware.h> 23#include <mach/hardware.h>
28#include <mach/common.h> 24#include <mach/common.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx27.h> 25#include <mach/iomux-mx27.h>
31#include <mach/board-mx27lite.h>
32 26
27#include "devices-imx27.h"
33#include "devices.h" 28#include "devices.h"
34 29
35static unsigned int mx27lite_pins[] = { 30static unsigned int mx27lite_pins[] = {
@@ -59,7 +54,7 @@ static unsigned int mx27lite_pins[] = {
59 PF23_AIN_FEC_TX_EN, 54 PF23_AIN_FEC_TX_EN,
60}; 55};
61 56
62static struct imxuart_platform_data uart_pdata = { 57static const struct imxuart_platform_data uart_pdata __initconst = {
63 .flags = IMXUART_HAVE_RTSCTS, 58 .flags = IMXUART_HAVE_RTSCTS,
64}; 59};
65 60
@@ -71,7 +66,7 @@ static void __init mx27lite_init(void)
71{ 66{
72 mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), 67 mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
73 "imx27lite"); 68 "imx27lite");
74 mxc_register_device(&mxc_uart_device0, &uart_pdata); 69 imx27_add_imx_uart0(&uart_pdata);
75 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 70 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
76} 71}
77 72
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 51f3cfd83db2..77a760cfadc0 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -26,10 +26,10 @@
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/i2c.h> 28#include <mach/i2c.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx1.h> 29#include <mach/iomux-mx1.h>
31#include <mach/irqs.h> 30#include <mach/irqs.h>
32 31
32#include "devices-imx1.h"
33#include "devices.h" 33#include "devices.h"
34 34
35static int mx1ads_pins[] = { 35static int mx1ads_pins[] = {
@@ -58,12 +58,12 @@ static int mx1ads_pins[] = {
58 * UARTs platform data 58 * UARTs platform data
59 */ 59 */
60 60
61static struct imxuart_platform_data uart_pdata[] = { 61static const struct imxuart_platform_data uart0_pdata __initconst = {
62 { 62 .flags = IMXUART_HAVE_RTSCTS,
63 .flags = IMXUART_HAVE_RTSCTS, 63};
64 }, { 64
65 .flags = IMXUART_HAVE_RTSCTS, 65static const struct imxuart_platform_data uart1_pdata __initconst = {
66 }, 66 .flags = IMXUART_HAVE_RTSCTS,
67}; 67};
68 68
69/* 69/*
@@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = {
75}; 75};
76 76
77static struct resource flash_resource = { 77static struct resource flash_resource = {
78 .start = IMX_CS0_PHYS, 78 .start = MX1_CS0_PHYS,
79 .end = IMX_CS0_PHYS + SZ_32M - 1, 79 .end = MX1_CS0_PHYS + SZ_32M - 1,
80 .flags = IORESOURCE_MEM, 80 .flags = IORESOURCE_MEM,
81}; 81};
82 82
@@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = {
98 } 98 }
99}; 99};
100 100
101static struct imxi2c_platform_data mx1ads_i2c_data = { 101static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
102 .bitrate = 100000, 102 .bitrate = 100000,
103}; 103};
104 104
@@ -121,8 +121,8 @@ static void __init mx1ads_init(void)
121 ARRAY_SIZE(mx1ads_pins), "mx1ads"); 121 ARRAY_SIZE(mx1ads_pins), "mx1ads");
122 122
123 /* UART */ 123 /* UART */
124 mxc_register_device(&imx_uart1_device, &uart_pdata[0]); 124 imx1_add_imx_uart0(&uart0_pdata);
125 mxc_register_device(&imx_uart2_device, &uart_pdata[1]); 125 imx1_add_imx_uart1(&uart1_pdata);
126 126
127 /* Physmap flash */ 127 /* Physmap flash */
128 mxc_register_device(&flash_device, &mx1ads_flash_data); 128 mxc_register_device(&flash_device, &mx1ads_flash_data);
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
131 i2c_register_board_info(0, mx1ads_i2c_devices, 131 i2c_register_board_info(0, mx1ads_i2c_devices,
132 ARRAY_SIZE(mx1ads_i2c_devices)); 132 ARRAY_SIZE(mx1ads_i2c_devices));
133 133
134 mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data); 134 imx1_add_i2c_imx(&mx1ads_i2c_data);
135} 135}
136 136
137static void __init mx1ads_timer_init(void) 137static void __init mx1ads_timer_init(void)
@@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = {
145 145
146MACHINE_START(MX1ADS, "Freescale MX1ADS") 146MACHINE_START(MX1ADS, "Freescale MX1ADS")
147 /* Maintainer: Sascha Hauer, Pengutronix */ 147 /* Maintainer: Sascha Hauer, Pengutronix */
148 .phys_io = IMX_IO_PHYS, 148 .phys_io = MX1_IO_BASE_ADDR,
149 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, 149 .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
150 .boot_params = MX1_PHYS_OFFSET + 0x100, 150 .boot_params = MX1_PHYS_OFFSET + 0x100,
151 .map_io = mx1_map_io, 151 .map_io = mx1_map_io,
152 .init_irq = mx1_init_irq, 152 .init_irq = mx1_init_irq,
@@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
155MACHINE_END 155MACHINE_END
156 156
157MACHINE_START(MXLADS, "Freescale MXLADS") 157MACHINE_START(MXLADS, "Freescale MXLADS")
158 .phys_io = IMX_IO_PHYS, 158 .phys_io = MX1_IO_BASE_ADDR,
159 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, 159 .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
160 .boot_params = MX1_PHYS_OFFSET + 0x100, 160 .boot_params = MX1_PHYS_OFFSET + 0x100,
161 .map_io = mx1_map_io, 161 .map_io = mx1_map_io,
162 .init_irq = mx1_init_irq, 162 .init_irq = mx1_init_irq,
diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 113e58d7cb40..96d7f8189f32 100644
--- a/arch/arm/mach-mx2/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#include <linux/platform_device.h> 17#include <linux/platform_device.h>
@@ -28,15 +24,49 @@
28#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
29#include <asm/mach/time.h> 25#include <asm/mach/time.h>
30#include <asm/mach/map.h> 26#include <asm/mach/map.h>
31#include <mach/imx-uart.h>
32#include <mach/imxfb.h> 27#include <mach/imxfb.h>
33#include <mach/iomux-mx21.h> 28#include <mach/iomux-mx21.h>
34#include <mach/mxc_nand.h> 29#include <mach/mxc_nand.h>
35#include <mach/mmc.h> 30#include <mach/mmc.h>
36#include <mach/board-mx21ads.h>
37 31
32#include "devices-imx21.h"
38#include "devices.h" 33#include "devices.h"
39 34
35/*
36 * Memory-mapped I/O on MX21ADS base board
37 */
38#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
39#define MX21ADS_MMIO_SIZE SZ_16M
40
41#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
42 (MX21ADS_MMIO_BASE_ADDR + (offset))
43
44#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
45#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
46#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
47#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
48#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
49
50/* MX21ADS_IO_REG bit definitions */
51#define MX21ADS_IO_SD_WP 0x0001 /* read */
52#define MX21ADS_IO_TP6 0x0001 /* write */
53#define MX21ADS_IO_SW_SEL 0x0002 /* read */
54#define MX21ADS_IO_TP7 0x0002 /* write */
55#define MX21ADS_IO_RESET_E_UART 0x0004
56#define MX21ADS_IO_RESET_BASE 0x0008
57#define MX21ADS_IO_CSI_CTL2 0x0010
58#define MX21ADS_IO_CSI_CTL1 0x0020
59#define MX21ADS_IO_CSI_CTL0 0x0040
60#define MX21ADS_IO_UART1_EN 0x0080
61#define MX21ADS_IO_UART4_EN 0x0100
62#define MX21ADS_IO_LCDON 0x0200
63#define MX21ADS_IO_IRDA_EN 0x0400
64#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
65#define MX21ADS_IO_IRDA_MD0_B 0x1000
66#define MX21ADS_IO_IRDA_MD1 0x2000
67#define MX21ADS_IO_LED4_ON 0x4000
68#define MX21ADS_IO_LED3_ON 0x8000
69
40static unsigned int mx21ads_pins[] = { 70static unsigned int mx21ads_pins[] = {
41 71
42 /* CS8900A */ 72 /* CS8900A */
@@ -133,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = {
133 .resource = &mx21ads_flash_resource, 163 .resource = &mx21ads_flash_resource,
134}; 164};
135 165
136static struct imxuart_platform_data uart_pdata = { 166static const struct imxuart_platform_data uart_pdata_rts __initconst = {
137 .flags = IMXUART_HAVE_RTSCTS, 167 .flags = IMXUART_HAVE_RTSCTS,
138}; 168};
139 169
140static struct imxuart_platform_data uart_norts_pdata = { 170static const struct imxuart_platform_data uart_pdata_norts __initconst = {
141}; 171};
142 172
143
144static int mx21ads_fb_init(struct platform_device *pdev) 173static int mx21ads_fb_init(struct platform_device *pdev)
145{ 174{
146 u16 tmp; 175 u16 tmp;
@@ -227,7 +256,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
227 .exit = mx21ads_sdhc_exit, 256 .exit = mx21ads_sdhc_exit,
228}; 257};
229 258
230static struct mxc_nand_platform_data mx21ads_nand_board_info = { 259static const struct mxc_nand_platform_data
260mx21ads_nand_board_info __initconst = {
231 .width = 1, 261 .width = 1,
232 .hw_ecc = 1, 262 .hw_ecc = 1,
233}; 263};
@@ -263,12 +293,12 @@ static void __init mx21ads_board_init(void)
263 mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), 293 mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
264 "mx21ads"); 294 "mx21ads");
265 295
266 mxc_register_device(&mxc_uart_device0, &uart_pdata); 296 imx21_add_imx_uart0(&uart_pdata_rts);
267 mxc_register_device(&mxc_uart_device2, &uart_norts_pdata); 297 imx21_add_imx_uart2(&uart_pdata_norts);
268 mxc_register_device(&mxc_uart_device3, &uart_pdata); 298 imx21_add_imx_uart3(&uart_pdata_rts);
269 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); 299 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
270 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); 300 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
271 mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info); 301 imx21_add_mxc_nand(&mx21ads_nand_board_info);
272 302
273 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 303 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
274} 304}
diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index b2f4e0db3fb3..e66ffaa1c26c 100644
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -12,23 +12,25 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 */
16 * You should have received a copy of the GNU General Public License 16
17 * along with this program; if not, write to the Free Software 17/*
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * This machine is known as:
19 * - i.MX27 3-Stack Development System
20 * - i.MX27 Platform Development Kit (i.MX27 PDK)
19 */ 21 */
20 22
21#include <linux/platform_device.h> 23#include <linux/platform_device.h>
22#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/input/matrix_keypad.h>
23#include <asm/mach-types.h> 26#include <asm/mach-types.h>
24#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
25#include <asm/mach/time.h> 28#include <asm/mach/time.h>
26#include <mach/hardware.h> 29#include <mach/hardware.h>
27#include <mach/common.h> 30#include <mach/common.h>
28#include <mach/imx-uart.h>
29#include <mach/iomux-mx27.h> 31#include <mach/iomux-mx27.h>
30#include <mach/board-mx27pdk.h>
31 32
33#include "devices-imx27.h"
32#include "devices.h" 34#include "devices.h"
33 35
34static unsigned int mx27pdk_pins[] = { 36static unsigned int mx27pdk_pins[] = {
@@ -58,7 +60,7 @@ static unsigned int mx27pdk_pins[] = {
58 PF23_AIN_FEC_TX_EN, 60 PF23_AIN_FEC_TX_EN,
59}; 61};
60 62
61static struct imxuart_platform_data uart_pdata = { 63static const struct imxuart_platform_data uart_pdata __initconst = {
62 .flags = IMXUART_HAVE_RTSCTS, 64 .flags = IMXUART_HAVE_RTSCTS,
63}; 65};
64 66
@@ -66,12 +68,34 @@ static struct platform_device *platform_devices[] __initdata = {
66 &mxc_fec_device, 68 &mxc_fec_device,
67}; 69};
68 70
71/*
72 * Matrix keyboard
73 */
74
75static const uint32_t mx27_3ds_keymap[] = {
76 KEY(0, 0, KEY_UP),
77 KEY(0, 1, KEY_DOWN),
78 KEY(1, 0, KEY_RIGHT),
79 KEY(1, 1, KEY_LEFT),
80 KEY(1, 2, KEY_ENTER),
81 KEY(2, 0, KEY_F6),
82 KEY(2, 1, KEY_F8),
83 KEY(2, 2, KEY_F9),
84 KEY(2, 3, KEY_F10),
85};
86
87static struct matrix_keymap_data mx27_3ds_keymap_data = {
88 .keymap = mx27_3ds_keymap,
89 .keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
90};
91
69static void __init mx27pdk_init(void) 92static void __init mx27pdk_init(void)
70{ 93{
71 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), 94 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
72 "mx27pdk"); 95 "mx27pdk");
73 mxc_register_device(&mxc_uart_device0, &uart_pdata); 96 imx27_add_imx_uart0(&uart_pdata);
74 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 97 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
98 mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
75} 99}
76 100
77static void __init mx27pdk_timer_init(void) 101static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 6ce323669e58..9c77da98a10e 100644
--- a/arch/arm/mach-mx2/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#include <linux/platform_device.h> 17#include <linux/platform_device.h>
@@ -32,16 +28,44 @@
32#include <asm/mach/time.h> 28#include <asm/mach/time.h>
33#include <asm/mach/map.h> 29#include <asm/mach/map.h>
34#include <mach/gpio.h> 30#include <mach/gpio.h>
35#include <mach/imx-uart.h>
36#include <mach/iomux-mx27.h> 31#include <mach/iomux-mx27.h>
37#include <mach/board-mx27ads.h>
38#include <mach/mxc_nand.h> 32#include <mach/mxc_nand.h>
39#include <mach/i2c.h>
40#include <mach/imxfb.h> 33#include <mach/imxfb.h>
41#include <mach/mmc.h> 34#include <mach/mmc.h>
42 35
36#include "devices-imx27.h"
43#include "devices.h" 37#include "devices.h"
44 38
39/*
40 * Base address of PBC controller, CS4
41 */
42#define PBC_BASE_ADDRESS 0xf4300000
43#define PBC_REG_ADDR(offset) (void __force __iomem *) \
44 (PBC_BASE_ADDRESS + (offset))
45
46/* When the PBC address connection is fixed in h/w, defined as 1 */
47#define PBC_ADDR_SH 0
48
49/* Offsets for the PBC Controller register */
50/*
51 * PBC Board version register offset
52 */
53#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
54/*
55 * PBC Board control register 1 set address.
56 */
57#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
58/*
59 * PBC Board control register 1 clear address.
60 */
61#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
62
63/* PBC Board Control Register 1 bit definitions */
64#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
65
66/* to determine the correct external crystal reference */
67#define CKIH_27MHZ_BIT_SET (1 << 3)
68
45static unsigned int mx27ads_pins[] = { 69static unsigned int mx27ads_pins[] = {
46 /* UART0 */ 70 /* UART0 */
47 PE12_PF_UART1_TXD, 71 PE12_PF_UART1_TXD,
@@ -141,7 +165,8 @@ static unsigned int mx27ads_pins[] = {
141 PB9_PF_SD2_CLK, 165 PB9_PF_SD2_CLK,
142}; 166};
143 167
144static struct mxc_nand_platform_data mx27ads_nand_board_info = { 168static const struct mxc_nand_platform_data
169mx27ads_nand_board_info __initconst = {
145 .width = 1, 170 .width = 1,
146 .hw_ecc = 1, 171 .hw_ecc = 1,
147}; 172};
@@ -168,7 +193,7 @@ static struct platform_device mx27ads_nor_mtd_device = {
168 .resource = &mx27ads_flash_resource, 193 .resource = &mx27ads_flash_resource,
169}; 194};
170 195
171static struct imxi2c_platform_data mx27ads_i2c_data = { 196static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
172 .bitrate = 100000, 197 .bitrate = 100000,
173}; 198};
174 199
@@ -263,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = {
263 &mxc_w1_master_device, 288 &mxc_w1_master_device,
264}; 289};
265 290
266static struct imxuart_platform_data uart_pdata[] = { 291static const struct imxuart_platform_data uart_pdata __initconst = {
267 { 292 .flags = IMXUART_HAVE_RTSCTS,
268 .flags = IMXUART_HAVE_RTSCTS,
269 }, {
270 .flags = IMXUART_HAVE_RTSCTS,
271 }, {
272 .flags = IMXUART_HAVE_RTSCTS,
273 }, {
274 .flags = IMXUART_HAVE_RTSCTS,
275 }, {
276 .flags = IMXUART_HAVE_RTSCTS,
277 }, {
278 .flags = IMXUART_HAVE_RTSCTS,
279 },
280}; 293};
281 294
282static void __init mx27ads_board_init(void) 295static void __init mx27ads_board_init(void)
@@ -284,18 +297,18 @@ static void __init mx27ads_board_init(void)
284 mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), 297 mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
285 "mx27ads"); 298 "mx27ads");
286 299
287 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 300 imx27_add_imx_uart0(&uart_pdata);
288 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 301 imx27_add_imx_uart1(&uart_pdata);
289 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 302 imx27_add_imx_uart2(&uart_pdata);
290 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); 303 imx27_add_imx_uart3(&uart_pdata);
291 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); 304 imx27_add_imx_uart4(&uart_pdata);
292 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); 305 imx27_add_imx_uart5(&uart_pdata);
293 mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info); 306 imx27_add_mxc_nand(&mx27ads_nand_board_info);
294 307
295 /* only the i2c master 1 is used on this CPU card */ 308 /* only the i2c master 1 is used on this CPU card */
296 i2c_register_board_info(1, mx27ads_i2c_devices, 309 i2c_register_board_info(1, mx27ads_i2c_devices,
297 ARRAY_SIZE(mx27ads_i2c_devices)); 310 ARRAY_SIZE(mx27ads_i2c_devices));
298 mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data); 311 imx27_add_i2c_imx1(&mx27ads_i2c1_data);
299 mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); 312 mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
300 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); 313 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
301 mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); 314 mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
@@ -342,4 +355,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
342 .init_machine = mx27ads_board_init, 355 .init_machine = mx27ads_board_init,
343 .timer = &mx27ads_timer, 356 .timer = &mx27ads_timer,
344MACHINE_END 357MACHINE_END
345
diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index bc3855992677..a3a1e452d4c5 100644
--- a/arch/arm/mach-mx2/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#include <linux/platform_device.h> 17#include <linux/platform_device.h>
@@ -32,14 +28,13 @@
32#include <asm/mach/time.h> 28#include <asm/mach/time.h>
33#include <asm/mach/map.h> 29#include <asm/mach/map.h>
34#include <linux/gpio.h> 30#include <linux/gpio.h>
35#include <mach/imx-uart.h>
36#include <mach/iomux-mx27.h> 31#include <mach/iomux-mx27.h>
37#include <mach/mxc_nand.h> 32#include <mach/mxc_nand.h>
38#include <mach/i2c.h>
39#include <linux/i2c/pca953x.h> 33#include <linux/i2c/pca953x.h>
40#include <mach/imxfb.h> 34#include <mach/imxfb.h>
41#include <mach/mmc.h> 35#include <mach/mmc.h>
42 36
37#include "devices-imx27.h"
43#include "devices.h" 38#include "devices.h"
44 39
45static unsigned int mxt_td60_pins[] __initdata = { 40static unsigned int mxt_td60_pins[] __initdata = {
@@ -128,12 +123,13 @@ static unsigned int mxt_td60_pins[] __initdata = {
128 PB9_PF_SD2_CLK, 123 PB9_PF_SD2_CLK,
129}; 124};
130 125
131static struct mxc_nand_platform_data mxt_td60_nand_board_info = { 126static const struct mxc_nand_platform_data
127mxt_td60_nand_board_info __initconst = {
132 .width = 1, 128 .width = 1,
133 .hw_ecc = 1, 129 .hw_ecc = 1,
134}; 130};
135 131
136static struct imxi2c_platform_data mxt_td60_i2c_data = { 132static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
137 .bitrate = 100000, 133 .bitrate = 100000,
138}; 134};
139 135
@@ -173,7 +169,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = {
173 }, 169 },
174}; 170};
175 171
176static struct imxi2c_platform_data mxt_td60_i2c2_data = { 172static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
177 .bitrate = 100000, 173 .bitrate = 100000,
178}; 174};
179 175
@@ -239,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = {
239 &mxc_fec_device, 235 &mxc_fec_device,
240}; 236};
241 237
242static struct imxuart_platform_data uart_pdata[] = { 238static const struct imxuart_platform_data uart_pdata __initconst = {
243 { 239 .flags = IMXUART_HAVE_RTSCTS,
244 .flags = IMXUART_HAVE_RTSCTS,
245 }, {
246 .flags = IMXUART_HAVE_RTSCTS,
247 }, {
248 .flags = IMXUART_HAVE_RTSCTS,
249 },
250}; 240};
251 241
252static void __init mxt_td60_board_init(void) 242static void __init mxt_td60_board_init(void)
@@ -254,10 +244,10 @@ static void __init mxt_td60_board_init(void)
254 mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), 244 mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
255 "MXT_TD60"); 245 "MXT_TD60");
256 246
257 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 247 imx27_add_imx_uart0(&uart_pdata);
258 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 248 imx27_add_imx_uart1(&uart_pdata);
259 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 249 imx27_add_imx_uart2(&uart_pdata);
260 mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info); 250 imx27_add_mxc_nand(&mxt_td60_nand_board_info);
261 251
262 i2c_register_board_info(0, mxt_td60_i2c_devices, 252 i2c_register_board_info(0, mxt_td60_i2c_devices,
263 ARRAY_SIZE(mxt_td60_i2c_devices)); 253 ARRAY_SIZE(mxt_td60_i2c_devices));
@@ -265,8 +255,8 @@ static void __init mxt_td60_board_init(void)
265 i2c_register_board_info(1, mxt_td60_i2c2_devices, 255 i2c_register_board_info(1, mxt_td60_i2c2_devices,
266 ARRAY_SIZE(mxt_td60_i2c2_devices)); 256 ARRAY_SIZE(mxt_td60_i2c2_devices));
267 257
268 mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data); 258 imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
269 mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data); 259 imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
270 mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); 260 mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
271 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); 261 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
272 262
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index a87422ed4ff5..6c92deaf468f 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,12 +36,7 @@
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/iomux-mx27.h> 38#include <mach/iomux-mx27.h>
39#include <mach/i2c.h>
40#include <asm/mach/time.h> 39#include <asm/mach/time.h>
41#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
42#include <mach/spi.h>
43#endif
44#include <mach/imx-uart.h>
45#include <mach/audmux.h> 40#include <mach/audmux.h>
46#include <mach/ssi.h> 41#include <mach/ssi.h>
47#include <mach/mxc_nand.h> 42#include <mach/mxc_nand.h>
@@ -49,11 +44,16 @@
49#include <mach/mmc.h> 44#include <mach/mmc.h>
50#include <mach/mxc_ehci.h> 45#include <mach/mxc_ehci.h>
51#include <mach/ulpi.h> 46#include <mach/ulpi.h>
47#include <mach/imxfb.h>
52 48
49#include "devices-imx27.h"
53#include "devices.h" 50#include "devices.h"
54 51
55#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) 52#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
56#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) 53#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
54#define SPI1_SS0 (GPIO_PORTD + 28)
55#define SPI1_SS1 (GPIO_PORTD + 27)
56#define SD2_CD (GPIO_PORTC + 29)
57 57
58static int pca100_pins[] = { 58static int pca100_pins[] = {
59 /* UART1 */ 59 /* UART1 */
@@ -68,6 +68,7 @@ static int pca100_pins[] = {
68 PB7_PF_SD2_D3, 68 PB7_PF_SD2_D3,
69 PB8_PF_SD2_CMD, 69 PB8_PF_SD2_CMD,
70 PB9_PF_SD2_CLK, 70 PB9_PF_SD2_CLK,
71 SD2_CD | GPIO_GPIO | GPIO_IN,
71 /* FEC */ 72 /* FEC */
72 PD0_AIN_FEC_TXD0, 73 PD0_AIN_FEC_TXD0,
73 PD1_AIN_FEC_TXD1, 74 PD1_AIN_FEC_TXD1,
@@ -131,13 +132,42 @@ static int pca100_pins[] = {
131 PD23_AF_USBH2_DATA2, 132 PD23_AF_USBH2_DATA2,
132 PD24_AF_USBH2_DATA1, 133 PD24_AF_USBH2_DATA1,
133 PD26_AF_USBH2_DATA5, 134 PD26_AF_USBH2_DATA5,
135 /* display */
136 PA5_PF_LSCLK,
137 PA6_PF_LD0,
138 PA7_PF_LD1,
139 PA8_PF_LD2,
140 PA9_PF_LD3,
141 PA10_PF_LD4,
142 PA11_PF_LD5,
143 PA12_PF_LD6,
144 PA13_PF_LD7,
145 PA14_PF_LD8,
146 PA15_PF_LD9,
147 PA16_PF_LD10,
148 PA17_PF_LD11,
149 PA18_PF_LD12,
150 PA19_PF_LD13,
151 PA20_PF_LD14,
152 PA21_PF_LD15,
153 PA22_PF_LD16,
154 PA23_PF_LD17,
155 PA26_PF_PS,
156 PA28_PF_HSYNC,
157 PA29_PF_VSYNC,
158 PA31_PF_OE_ACD,
159 /* free GPIO */
160 GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
161 GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
162 GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
134}; 163};
135 164
136static struct imxuart_platform_data uart_pdata = { 165static const struct imxuart_platform_data uart_pdata __initconst = {
137 .flags = IMXUART_HAVE_RTSCTS, 166 .flags = IMXUART_HAVE_RTSCTS,
138}; 167};
139 168
140static struct mxc_nand_platform_data pca100_nand_board_info = { 169static const struct mxc_nand_platform_data
170pca100_nand_board_info __initconst = {
141 .width = 1, 171 .width = 1,
142 .hw_ecc = 1, 172 .hw_ecc = 1,
143}; 173};
@@ -148,7 +178,7 @@ static struct platform_device *platform_devices[] __initdata = {
148 &mxc_wdt, 178 &mxc_wdt,
149}; 179};
150 180
151static struct imxi2c_platform_data pca100_i2c_1_data = { 181static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
152 .bitrate = 100000, 182 .bitrate = 100000,
153}; 183};
154 184
@@ -189,9 +219,9 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
189 }, 219 },
190}; 220};
191 221
192static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27}; 222static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
193 223
194static struct spi_imx_master pca100_spi_0_data = { 224static const struct spi_imx_master pca100_spi0_data __initconst = {
195 .chipselect = pca100_spi_cs, 225 .chipselect = pca100_spi_cs,
196 .num_chipselect = ARRAY_SIZE(pca100_spi_cs), 226 .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
197}; 227};
@@ -253,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = {
253 .exit = pca100_sdhc2_exit, 283 .exit = pca100_sdhc2_exit,
254}; 284};
255 285
286#if defined(CONFIG_USB_ULPI)
256static int otg_phy_init(struct platform_device *pdev) 287static int otg_phy_init(struct platform_device *pdev)
257{ 288{
258 gpio_set_value(OTG_PHY_CS_GPIO, 0); 289 gpio_set_value(OTG_PHY_CS_GPIO, 0);
@@ -276,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
276 .portsc = MXC_EHCI_MODE_ULPI, 307 .portsc = MXC_EHCI_MODE_ULPI,
277 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 308 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
278}; 309};
310#endif
279 311
280static struct fsl_usb2_platform_data otg_device_pdata = { 312static struct fsl_usb2_platform_data otg_device_pdata = {
281 .operating_mode = FSL_USB2_DR_DEVICE, 313 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -297,6 +329,45 @@ static int __init pca100_otg_mode(char *options)
297} 329}
298__setup("otg_mode=", pca100_otg_mode); 330__setup("otg_mode=", pca100_otg_mode);
299 331
332/* framebuffer info */
333static struct imx_fb_videomode pca100_fb_modes[] = {
334 {
335 .mode = {
336 .name = "EMERGING-ETV570G0DHU",
337 .refresh = 60,
338 .xres = 640,
339 .yres = 480,
340 .pixclock = 39722, /* in ps (25.175 MHz) */
341 .hsync_len = 30,
342 .left_margin = 114,
343 .right_margin = 16,
344 .vsync_len = 3,
345 .upper_margin = 32,
346 .lower_margin = 0,
347 },
348 /*
349 * TFT
350 * Pixel pol active high
351 * HSYNC active low
352 * VSYNC active low
353 * use HSYNC for ACD count
354 * line clock disable while idle
355 * always enable line clock even if no data
356 */
357 .pcr = 0xf0c08080,
358 .bpp = 16,
359 },
360};
361
362static struct imx_fb_platform_data pca100_fb_data = {
363 .mode = pca100_fb_modes,
364 .num_modes = ARRAY_SIZE(pca100_fb_modes),
365
366 .pwmr = 0x00A903FF,
367 .lscr1 = 0x00120300,
368 .dmacr = 0x00020010,
369};
370
300static void __init pca100_init(void) 371static void __init pca100_init(void)
301{ 372{
302 int ret; 373 int ret;
@@ -320,33 +391,24 @@ static void __init pca100_init(void)
320 391
321 mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); 392 mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
322 393
323 mxc_register_device(&mxc_uart_device0, &uart_pdata); 394 imx27_add_imx_uart0(&uart_pdata);
324 395
325 mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
326 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 396 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
327 397
328 mxc_register_device(&imx27_nand_device, &pca100_nand_board_info); 398 imx27_add_mxc_nand(&pca100_nand_board_info);
329 399
330 /* only the i2c master 1 is used on this CPU card */ 400 /* only the i2c master 1 is used on this CPU card */
331 i2c_register_board_info(1, pca100_i2c_devices, 401 i2c_register_board_info(1, pca100_i2c_devices,
332 ARRAY_SIZE(pca100_i2c_devices)); 402 ARRAY_SIZE(pca100_i2c_devices));
333 403
334 mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data); 404 imx27_add_i2c_imx1(&pca100_i2c1_data);
335
336 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
337 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
338
339 /* GPIO0_IRQ */
340 mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
341 /* GPIO1_IRQ */
342 mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
343 /* GPIO2_IRQ */
344 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
345 405
346#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 406#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
407 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
408 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
347 spi_register_board_info(pca100_spi_board_info, 409 spi_register_board_info(pca100_spi_board_info,
348 ARRAY_SIZE(pca100_spi_board_info)); 410 ARRAY_SIZE(pca100_spi_board_info));
349 mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data); 411 imx27_add_spi_imx0(&pca100_spi_0_data);
350#endif 412#endif
351 413
352 gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); 414 gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
@@ -372,6 +434,8 @@ static void __init pca100_init(void)
372 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 434 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
373 } 435 }
374 436
437 mxc_register_device(&mxc_fb_device, &pca100_fb_data);
438
375 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 439 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
376} 440}
377 441
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 36c89431679a..9212e8f37001 100644
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -35,14 +35,12 @@
35#include <mach/board-pcm038.h> 35#include <mach/board-pcm038.h>
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/i2c.h>
39#include <mach/iomux-mx27.h> 38#include <mach/iomux-mx27.h>
40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h> 39#include <mach/mxc_nand.h>
42#include <mach/spi.h>
43#include <mach/mxc_ehci.h> 40#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h> 41#include <mach/ulpi.h>
45 42
43#include "devices-imx27.h"
46#include "devices.h" 44#include "devices.h"
47 45
48static int pcm038_pins[] = { 46static int pcm038_pins[] = {
@@ -162,17 +160,12 @@ static struct platform_device pcm038_nor_mtd_device = {
162 .resource = &pcm038_flash_resource, 160 .resource = &pcm038_flash_resource,
163}; 161};
164 162
165static struct imxuart_platform_data uart_pdata[] = { 163static const struct imxuart_platform_data uart_pdata __initconst = {
166 { 164 .flags = IMXUART_HAVE_RTSCTS,
167 .flags = IMXUART_HAVE_RTSCTS,
168 }, {
169 .flags = IMXUART_HAVE_RTSCTS,
170 }, {
171 .flags = IMXUART_HAVE_RTSCTS,
172 },
173}; 165};
174 166
175static struct mxc_nand_platform_data pcm038_nand_board_info = { 167static const struct mxc_nand_platform_data
168pcm038_nand_board_info __initconst = {
176 .width = 1, 169 .width = 1,
177 .hw_ecc = 1, 170 .hw_ecc = 1,
178}; 171};
@@ -192,7 +185,7 @@ static void __init pcm038_init_sram(void)
192 mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); 185 mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
193} 186}
194 187
195static struct imxi2c_platform_data pcm038_i2c_1_data = { 188static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
196 .bitrate = 100000, 189 .bitrate = 100000,
197}; 190};
198 191
@@ -215,7 +208,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
215 208
216static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; 209static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
217 210
218static struct spi_imx_master pcm038_spi_0_data = { 211static const struct spi_imx_master pcm038_spi0_data __initconst = {
219 .chipselect = pcm038_spi_cs, 212 .chipselect = pcm038_spi_cs,
220 .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), 213 .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
221}; 214};
@@ -305,18 +298,18 @@ static void __init pcm038_init(void)
305 298
306 pcm038_init_sram(); 299 pcm038_init_sram();
307 300
308 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 301 imx27_add_imx_uart0(&uart_pdata);
309 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 302 imx27_add_imx_uart1(&uart_pdata);
310 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 303 imx27_add_imx_uart2(&uart_pdata);
311 304
312 mxc_gpio_mode(PE16_AF_OWIRE); 305 mxc_gpio_mode(PE16_AF_OWIRE);
313 mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info); 306 imx27_add_mxc_nand(&pcm038_nand_board_info);
314 307
315 /* only the i2c master 1 is used on this CPU card */ 308 /* only the i2c master 1 is used on this CPU card */
316 i2c_register_board_info(1, pcm038_i2c_devices, 309 i2c_register_board_info(1, pcm038_i2c_devices,
317 ARRAY_SIZE(pcm038_i2c_devices)); 310 ARRAY_SIZE(pcm038_i2c_devices));
318 311
319 mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); 312 imx27_add_i2c_imx1(&pcm038_i2c1_data);
320 313
321 /* PE18 for user-LED D40 */ 314 /* PE18 for user-LED D40 */
322 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); 315 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@@ -326,7 +319,7 @@ static void __init pcm038_init(void)
326 /* MC13783 IRQ */ 319 /* MC13783 IRQ */
327 mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN); 320 mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
328 321
329 mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data); 322 imx27_add_spi_imx0(&pcm038_spi0_data);
330 spi_register_board_info(pcm038_spi_board_info, 323 spi_register_board_info(pcm038_spi_board_info,
331 ARRAY_SIZE(pcm038_spi_board_info)); 324 ARRAY_SIZE(pcm038_spi_board_info));
332 325
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 7587a7a12460..88bf0d1e26e6 100644
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -22,17 +22,17 @@
22#include <mach/common.h> 22#include <mach/common.h>
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/irqs.h> 24#include <mach/irqs.h>
25#include <mach/imx-uart.h>
26#include <mach/iomux-mx1.h> 25#include <mach/iomux-mx1.h>
27 26
27#include "devices-imx1.h"
28#include "devices.h" 28#include "devices.h"
29 29
30/* 30/*
31 * This scb9328 has a 32MiB flash 31 * This scb9328 has a 32MiB flash
32 */ 32 */
33static struct resource flash_resource = { 33static struct resource flash_resource = {
34 .start = IMX_CS0_PHYS, 34 .start = MX1_CS0_PHYS,
35 .end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1, 35 .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
36 .flags = IORESOURCE_MEM, 36 .flags = IORESOURCE_MEM,
37}; 37};
38 38
@@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = {
70static struct resource dm9000x_resources[] = { 70static struct resource dm9000x_resources[] = {
71 { 71 {
72 .name = "address area", 72 .name = "address area",
73 .start = IMX_CS5_PHYS, 73 .start = MX1_CS5_PHYS,
74 .end = IMX_CS5_PHYS + 1, 74 .end = MX1_CS5_PHYS + 1,
75 .flags = IORESOURCE_MEM, /* address access */ 75 .flags = IORESOURCE_MEM, /* address access */
76 }, { 76 }, {
77 .name = "data area", 77 .name = "data area",
78 .start = IMX_CS5_PHYS + 4, 78 .start = MX1_CS5_PHYS + 4,
79 .end = IMX_CS5_PHYS + 5, 79 .end = MX1_CS5_PHYS + 5,
80 .flags = IORESOURCE_MEM, /* data access */ 80 .flags = IORESOURCE_MEM, /* data access */
81 }, { 81 }, {
82 .start = IRQ_GPIOC(3), 82 .start = IRQ_GPIOC(3),
@@ -108,14 +108,13 @@ static int uart1_mxc_init(struct platform_device *pdev)
108 ARRAY_SIZE(mxc_uart1_pins), "UART1"); 108 ARRAY_SIZE(mxc_uart1_pins), "UART1");
109} 109}
110 110
111static int uart1_mxc_exit(struct platform_device *pdev) 111static void uart1_mxc_exit(struct platform_device *pdev)
112{ 112{
113 mxc_gpio_release_multiple_pins(mxc_uart1_pins, 113 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
114 ARRAY_SIZE(mxc_uart1_pins)); 114 ARRAY_SIZE(mxc_uart1_pins));
115 return 0;
116} 115}
117 116
118static struct imxuart_platform_data uart_pdata = { 117static const struct imxuart_platform_data uart_pdata __initconst = {
119 .init = uart1_mxc_init, 118 .init = uart1_mxc_init,
120 .exit = uart1_mxc_exit, 119 .exit = uart1_mxc_exit,
121 .flags = IMXUART_HAVE_RTSCTS, 120 .flags = IMXUART_HAVE_RTSCTS,
@@ -131,7 +130,7 @@ static struct platform_device *devices[] __initdata = {
131 */ 130 */
132static void __init scb9328_init(void) 131static void __init scb9328_init(void)
133{ 132{
134 mxc_register_device(&imx_uart1_device, &uart_pdata); 133 imx1_add_imx_uart0(&uart_pdata);
135 134
136 printk(KERN_INFO"Scb9328: Adding devices\n"); 135 printk(KERN_INFO"Scb9328: Adding devices\n");
137 platform_add_devices(devices, ARRAY_SIZE(devices)); 136 platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-imx/mm-imx1.c
index 7f9fc1034c08..9be92b96dc89 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -3,7 +3,7 @@
3 * Created: april 20th, 2004 3 * Created: april 20th, 2004
4 * Copyright: Synertronixx GmbH 4 * Copyright: Synertronixx GmbH
5 * 5 *
6 * Common code for i.MX machines 6 * Common code for i.MX1 machines
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */ 17 */
23#include <linux/kernel.h> 18#include <linux/kernel.h>
24#include <linux/init.h> 19#include <linux/init.h>
@@ -31,23 +26,25 @@
31 26
32static struct map_desc imx_io_desc[] __initdata = { 27static struct map_desc imx_io_desc[] __initdata = {
33 { 28 {
34 .virtual = IMX_IO_BASE, 29 .virtual = MX1_IO_BASE_ADDR_VIRT,
35 .pfn = __phys_to_pfn(IMX_IO_PHYS), 30 .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
36 .length = IMX_IO_SIZE, 31 .length = MX1_IO_SIZE,
37 .type = MT_DEVICE 32 .type = MT_DEVICE
38 } 33 }
39}; 34};
40 35
41void __init mx1_map_io(void) 36void __init mx1_map_io(void)
42{ 37{
43 mxc_set_cpu_type(MXC_CPU_MX1); 38 mxc_set_cpu_type(MXC_CPU_MX1);
44 mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR)); 39 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
45 40
46 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); 41 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
47} 42}
48 43
44int imx1_register_gpios(void);
45
49void __init mx1_init_irq(void) 46void __init mx1_init_irq(void)
50{ 47{
51 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); 48 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
49 imx1_register_gpios();
52} 50}
53
diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 64134314d012..12faeeaa0a97 100644
--- a/arch/arm/mach-mx2/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-mx2/mm-imx21.c 2 * arch/arm/mach-imx/mm-imx21.c
3 * 3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 * 5 *
@@ -77,7 +77,10 @@ void __init mx21_map_io(void)
77 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); 77 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
78} 78}
79 79
80int imx21_register_gpios(void);
81
80void __init mx21_init_irq(void) 82void __init mx21_init_irq(void)
81{ 83{
82 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); 84 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
85 imx21_register_gpios();
83} 86}
diff --git a/arch/arm/mach-mx2/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 3366ed44cfd5..a24622957ff2 100644
--- a/arch/arm/mach-mx2/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-mx2/mm-imx27.c 2 * arch/arm/mach-imx/mm-imx27.c
3 * 3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 * 5 *
@@ -77,7 +77,10 @@ void __init mx27_map_io(void)
77 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); 77 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
78} 78}
79 79
80int imx27_register_gpios(void);
81
80void __init mx27_init_irq(void) 82void __init mx27_init_irq(void)
81{ 83{
82 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); 84 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
85 imx27_register_gpios();
83} 86}
diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
index b09ee12a4ff0..b09ee12a4ff0 100644
--- a/arch/arm/mach-mx1/ksym_mx1.c
+++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S
index 9c69aa65bf17..9c69aa65bf17 100644
--- a/arch/arm/mach-mx1/mx1_camera_fiq.S
+++ b/arch/arm/mach-imx/mx1-camera-fiq.S
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index f490a406d57e..f490a406d57e 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
new file mode 100644
index 000000000000..afc17ce0bb54
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -0,0 +1,46 @@
1/*
2 * i.MX27 Power Management Routines
3 *
4 * Based on Freescale's BSP
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License.
8 */
9
10#include <linux/kernel.h>
11#include <linux/suspend.h>
12#include <linux/io.h>
13#include <mach/system.h>
14#include <mach/mx27.h>
15
16static int mx27_suspend_enter(suspend_state_t state)
17{
18 u32 cscr;
19 switch (state) {
20 case PM_SUSPEND_MEM:
21 /* Clear MPEN and SPEN to disable MPLL/SPLL */
22 cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
23 cscr &= 0xFFFFFFFC;
24 __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
25 /* Executes WFI */
26 arch_idle();
27 break;
28
29 default:
30 return -EINVAL;
31 }
32 return 0;
33}
34
35static struct platform_suspend_ops mx27_suspend_ops = {
36 .enter = mx27_suspend_enter,
37 .valid = suspend_valid_only_mem,
38};
39
40static int __init mx27_pm_init(void)
41{
42 suspend_set_ops(&mx27_suspend_ops);
43 return 0;
44}
45
46device_initcall(mx27_pm_init);
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
new file mode 100644
index 000000000000..5f96e1518aa9
--- /dev/null
+++ b/arch/arm/mach-integrator/common.h
@@ -0,0 +1 @@
void integrator_reserve(void);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index b02cfc06e0ae..8f4fb6d638f7 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -14,6 +14,7 @@
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/memblock.h>
17#include <linux/sched.h> 18#include <linux/sched.h>
18#include <linux/smp.h> 19#include <linux/smp.h>
19#include <linux/termios.h> 20#include <linux/termios.h>
@@ -30,6 +31,7 @@
30#include <asm/system.h> 31#include <asm/system.h>
31#include <asm/leds.h> 32#include <asm/leds.h>
32#include <asm/mach/time.h> 33#include <asm/mach/time.h>
34#include <asm/pgtable.h>
33 35
34static struct amba_pl010_data integrator_uart_data; 36static struct amba_pl010_data integrator_uart_data;
35 37
@@ -119,8 +121,13 @@ static struct clk uartclk = {
119 .rate = 14745600, 121 .rate = 14745600,
120}; 122};
121 123
124static struct clk dummy_apb_pclk;
125
122static struct clk_lookup lookups[] = { 126static struct clk_lookup lookups[] = {
123 { /* UART0 */ 127 { /* Bus clock */
128 .con_id = "apb_pclk",
129 .clk = &dummy_apb_pclk,
130 }, { /* UART0 */
124 .dev_id = "mb:16", 131 .dev_id = "mb:16",
125 .clk = &uartclk, 132 .clk = &uartclk,
126 }, { /* UART1 */ 133 }, { /* UART1 */
@@ -215,3 +222,13 @@ void cm_control(u32 mask, u32 set)
215} 222}
216 223
217EXPORT_SYMBOL(cm_control); 224EXPORT_SYMBOL(cm_control);
225
226/*
227 * We need to stop things allocating the low memory; ideally we need a
228 * better implementation of GFP_DMA which does not assume that DMA-able
229 * memory starts at zero.
230 */
231void __init integrator_reserve(void)
232{
233 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
234}
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 227cf4d05088..6ab5a03ab9d8 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -48,6 +48,8 @@
48#include <asm/mach/map.h> 48#include <asm/mach/map.h>
49#include <asm/mach/time.h> 49#include <asm/mach/time.h>
50 50
51#include "common.h"
52
51/* 53/*
52 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx 54 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
53 * is the (PA >> 12). 55 * is the (PA >> 12).
@@ -502,6 +504,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
502 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, 504 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
503 .boot_params = 0x00000100, 505 .boot_params = 0x00000100,
504 .map_io = ap_map_io, 506 .map_io = ap_map_io,
507 .reserve = integrator_reserve,
505 .init_irq = ap_init_irq, 508 .init_irq = ap_init_irq,
506 .timer = &ap_timer, 509 .timer = &ap_timer,
507 .init_machine = ap_init, 510 .init_machine = ap_init,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index cde57b2b83b5..05db40e3c4f7 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -43,6 +43,8 @@
43 43
44#include <plat/timer-sp.h> 44#include <plat/timer-sp.h>
45 45
46#include "common.h"
47
46#define INTCP_PA_FLASH_BASE 0x24000000 48#define INTCP_PA_FLASH_BASE 0x24000000
47#define INTCP_FLASH_SIZE SZ_32M 49#define INTCP_FLASH_SIZE SZ_32M
48 50
@@ -601,6 +603,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
601 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, 603 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
602 .boot_params = 0x00000100, 604 .boot_params = 0x00000100,
603 .map_io = intcp_map_io, 605 .map_io = intcp_map_io,
606 .reserve = integrator_reserve,
604 .init_irq = intcp_init_irq, 607 .init_irq = intcp_init_irq,
605 .timer = &cp_timer, 608 .timer = &cp_timer,
606 .init_machine = intcp_init, 609 .init_machine = intcp_init,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 9cef0590d5aa..6467d99fa2ee 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -505,10 +505,10 @@ void __init pci_v3_preinit(void)
505 /* 505 /*
506 * Hook in our fault handler for PCI errors 506 * Hook in our fault handler for PCI errors
507 */ 507 */
508 hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch"); 508 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
509 hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch"); 509 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
510 hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); 510 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
511 hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch"); 511 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
512 512
513 spin_lock_irqsave(&v3_lock, flags); 513 spin_lock_irqsave(&v3_lock, flags);
514 514
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 25b1da9a5035..7415e4338651 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -69,6 +69,4 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
69#endif /* CONFIG_ARCH_IOP13XX */ 69#endif /* CONFIG_ARCH_IOP13XX */
70#endif /* !ASSEMBLY */ 70#endif /* !ASSEMBLY */
71 71
72#define PFN_TO_NID(addr) (0)
73
74#endif 72#endif
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 6d5a90813d31..773ea0c95b9f 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -987,7 +987,7 @@ void __init iop13xx_pci_init(void)
987 iop13xx_atux_setup(); 987 iop13xx_atux_setup();
988 } 988 }
989 989
990 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 990 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
991 "imprecise external abort"); 991 "imprecise external abort");
992} 992}
993 993
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 90771cad06f8..f797c5f538b0 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -209,7 +209,7 @@ ixp2000_pci_preinit(void)
209 "the needed workaround has not been configured in"); 209 "the needed workaround has not been configured in");
210#endif 210#endif
211 211
212 hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 212 hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0,
213 "PCI config cycle to non-existent device"); 213 "PCI config cycle to non-existent device");
214} 214}
215 215
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 4b0e598a91c9..563819a83292 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -229,7 +229,7 @@ void __init ixp23xx_pci_preinit(void)
229{ 229{
230 ixp23xx_pci_common_init(); 230 ixp23xx_pci_common_init();
231 231
232 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 232 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
233 "PCI config cycle to non-existent device"); 233 "PCI config cycle to non-existent device");
234 234
235 *IXP23XX_PCI_ADDR_EXT = 0x0000e000; 235 *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index e3181534c7f9..61cd4d64b985 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -348,7 +348,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
348 * This is really ugly and we need a better way of specifying 348 * This is really ugly and we need a better way of specifying
349 * DMA-capable regions of memory. 349 * DMA-capable regions of memory.
350 */ 350 */
351void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, 351void __init ixp4xx_adjust_zones(unsigned long *zone_size,
352 unsigned long *zhole_size) 352 unsigned long *zhole_size)
353{ 353{
354 unsigned int sz = SZ_64M >> PAGE_SHIFT; 354 unsigned int sz = SZ_64M >> PAGE_SHIFT;
@@ -356,7 +356,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
356 /* 356 /*
357 * Only adjust if > 64M on current system 357 * Only adjust if > 64M on current system
358 */ 358 */
359 if (node || (zone_size[0] <= sz)) 359 if (zone_size[0] <= sz)
360 return; 360 return;
361 361
362 zone_size[1] = zone_size[0] - sz; 362 zone_size[1] = zone_size[0] - sz;
@@ -382,7 +382,8 @@ void __init ixp4xx_pci_preinit(void)
382 382
383 383
384 /* hook in our fault handler for PCI errors */ 384 /* hook in our fault handler for PCI errors */
385 hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort"); 385 hook_fault_code(16+6, abort_handler, SIGBUS, 0,
386 "imprecise external abort");
386 387
387 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); 388 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
388 389
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 98f5e5e20980..0136eaa29224 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -16,10 +16,10 @@
16 16
17#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) 17#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
18 18
19void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes); 19void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
20 20
21#define arch_adjust_zones(node, size, holes) \ 21#define arch_adjust_zones(size, holes) \
22 ixp4xx_adjust_zones(node, size, holes) 22 ixp4xx_adjust_zones(size, holes)
23 23
24#define ISA_DMA_THRESHOLD (SZ_64M - 1) 24#define ISA_DMA_THRESHOLD (SZ_64M - 1)
25#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) 25#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163b1fe3..cc25501b57fa 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
75 Say 'Y' here if you want your kernel to support the 75 Say 'Y' here if you want your kernel to support the
76 Marvell OpenRD Client Board. 76 Marvell OpenRD Client Board.
77 77
78config MACH_OPENRD_ULTIMATE
79 bool "Marvell OpenRD Ultimate Board"
80 select MACH_OPENRD
81 help
82 Say 'Y' here if you want your kernel to support the
83 Marvell OpenRD Ultimate Board.
84
78config MACH_NETSPACE_V2 85config MACH_NETSPACE_V2
79 bool "LaCie Network Space v2 NAS Board" 86 bool "LaCie Network Space v2 NAS Board"
80 help 87 help
@@ -87,6 +94,12 @@ config MACH_INETSPACE_V2
87 Say 'Y' here if you want your kernel to support the 94 Say 'Y' here if you want your kernel to support the
88 LaCie Internet Space v2 NAS. 95 LaCie Internet Space v2 NAS.
89 96
97config MACH_NETSPACE_MAX_V2
98 bool "LaCie Network Space Max v2 NAS Board"
99 help
100 Say 'Y' here if you want your kernel to support the
101 LaCie Network Space Max v2 NAS.
102
90config MACH_NET2BIG_V2 103config MACH_NET2BIG_V2
91 bool "LaCie 2Big Network v2 NAS Board" 104 bool "LaCie 2Big Network v2 NAS Board"
92 help 105 help
@@ -99,6 +112,12 @@ config MACH_NET5BIG_V2
99 Say 'Y' here if you want your kernel to support the 112 Say 'Y' here if you want your kernel to support the
100 LaCie 5Big Network v2 NAS. 113 LaCie 5Big Network v2 NAS.
101 114
115config MACH_T5325
116 bool "HP t5325 Thin Client"
117 help
118 Say 'Y' here if you want your kernel to support the
119 HP t5325 Thin Client.
120
102endmenu 121endmenu
103 122
104endif 123endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index c0cd5d362002..295d7baa6ae1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
12obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o 12obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
13obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o 13obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o
14obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o 14obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o
15obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o
15obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o 16obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o
16obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o 17obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o
18obj-$(CONFIG_MACH_T5325) += t5325-setup.o
17 19
18obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168fc699..8d03bcef5182 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
31#define ATTR_DEV_CS0 0x3e 31#define ATTR_DEV_CS0 0x3e
32#define ATTR_PCIE_IO 0xe0 32#define ATTR_PCIE_IO 0xe0
33#define ATTR_PCIE_MEM 0xe8 33#define ATTR_PCIE_MEM 0xe8
34#define ATTR_PCIE1_IO 0xd0
35#define ATTR_PCIE1_MEM 0xd8
34#define ATTR_SRAM 0x01 36#define ATTR_SRAM 0x01
35 37
36/* 38/*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
106 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); 108 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
107 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, 109 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
108 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); 110 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
111 setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
112 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
113 setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
114 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
109 115
110 /* 116 /*
111 * Setup window for NAND controller. 117 * Setup window for NAND controller.
112 */ 118 */
113 setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, 119 setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
114 TARGET_DEV_BUS, ATTR_DEV_NAND, -1); 120 TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
115 121
116 /* 122 /*
117 * Setup window for SRAM. 123 * Setup window for SRAM.
118 */ 124 */
119 setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, 125 setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
120 TARGET_SRAM, ATTR_SRAM, -1); 126 TARGET_SRAM, ATTR_SRAM, -1);
121 127
122 /* 128 /*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa5e66a..9dd67c7b4459 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
44 .length = KIRKWOOD_PCIE_IO_SIZE, 44 .length = KIRKWOOD_PCIE_IO_SIZE,
45 .type = MT_DEVICE, 45 .type = MT_DEVICE,
46 }, { 46 }, {
47 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
48 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
49 .length = KIRKWOOD_PCIE1_IO_SIZE,
50 .type = MT_DEVICE,
51 }, {
47 .virtual = KIRKWOOD_REGS_VIRT_BASE, 52 .virtual = KIRKWOOD_REGS_VIRT_BASE,
48 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), 53 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
49 .length = KIRKWOOD_REGS_SIZE, 54 .length = KIRKWOOD_REGS_SIZE,
@@ -402,7 +407,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
402 u32 dev, rev; 407 u32 dev, rev;
403 408
404 kirkwood_pcie_id(&dev, &rev); 409 kirkwood_pcie_id(&dev, &rev);
405 if (rev == 0) /* catch all Kirkwood Z0's */ 410 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
406 mvsdio_data->clock = 100000000; 411 mvsdio_data->clock = 100000000;
407 else 412 else
408 mvsdio_data->clock = 200000000; 413 mvsdio_data->clock = 200000000;
@@ -847,8 +852,10 @@ int __init kirkwood_find_tclk(void)
847 u32 dev, rev; 852 u32 dev, rev;
848 853
849 kirkwood_pcie_id(&dev, &rev); 854 kirkwood_pcie_id(&dev, &rev);
850 if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 || 855
851 rev == MV88F6281_REV_A1)) 856 if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
857 rev == MV88F6281_REV_A1)) ||
858 (dev == MV88F6282_DEV_ID))
852 return 200000000; 859 return 200000000;
853 860
854 return 166666667; 861 return 166666667;
@@ -891,13 +898,22 @@ static char * __init kirkwood_id(void)
891 return "MV88F6192-Z0"; 898 return "MV88F6192-Z0";
892 else if (rev == MV88F6192_REV_A0) 899 else if (rev == MV88F6192_REV_A0)
893 return "MV88F6192-A0"; 900 return "MV88F6192-A0";
901 else if (rev == MV88F6192_REV_A1)
902 return "MV88F6192-A1";
894 else 903 else
895 return "MV88F6192-Rev-Unsupported"; 904 return "MV88F6192-Rev-Unsupported";
896 } else if (dev == MV88F6180_DEV_ID) { 905 } else if (dev == MV88F6180_DEV_ID) {
897 if (rev == MV88F6180_REV_A0) 906 if (rev == MV88F6180_REV_A0)
898 return "MV88F6180-Rev-A0"; 907 return "MV88F6180-Rev-A0";
908 else if (rev == MV88F6180_REV_A1)
909 return "MV88F6180-Rev-A1";
899 else 910 else
900 return "MV88F6180-Rev-Unsupported"; 911 return "MV88F6180-Rev-Unsupported";
912 } else if (dev == MV88F6282_DEV_ID) {
913 if (rev == MV88F6282_REV_A0)
914 return "MV88F6282-Rev-A0";
915 else
916 return "MV88F6282-Rev-Unsupported";
901 } else { 917 } else {
902 return "Device-Unknown"; 918 return "Device-Unknown";
903 } 919 }
@@ -949,12 +965,14 @@ void __init kirkwood_init(void)
949static int __init kirkwood_clock_gate(void) 965static int __init kirkwood_clock_gate(void)
950{ 966{
951 unsigned int curr = readl(CLOCK_GATING_CTRL); 967 unsigned int curr = readl(CLOCK_GATING_CTRL);
968 u32 dev, rev;
952 969
970 kirkwood_pcie_id(&dev, &rev);
953 printk(KERN_DEBUG "Gating clock of unused units\n"); 971 printk(KERN_DEBUG "Gating clock of unused units\n");
954 printk(KERN_DEBUG "before: 0x%08x\n", curr); 972 printk(KERN_DEBUG "before: 0x%08x\n", curr);
955 973
956 /* Make sure those units are accessible */ 974 /* Make sure those units are accessible */
957 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL); 975 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
958 976
959 /* For SATA: first shutdown the phy */ 977 /* For SATA: first shutdown the phy */
960 if (!(kirkwood_clk_ctrl & CGC_SATA0)) { 978 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -979,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
979 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); 997 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
980 } 998 }
981 999
1000 /* For PCIe 1: first shutdown the phy */
1001 if (dev == MV88F6282_DEV_ID) {
1002 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
1003 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
1004 while (1)
1005 if (readl(PCIE1_STATUS) & 0x1)
1006 break;
1007 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
1008 }
1009 } else /* keep this bit set for devices that don't have PCIe1 */
1010 kirkwood_clk_ctrl |= CGC_PEX1;
1011
982 /* Now gate clock the required units */ 1012 /* Now gate clock the required units */
983 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); 1013 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
984 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); 1014 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a5692e..5b2c1c18d641 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
18struct mtd_partition; 18struct mtd_partition;
19struct mtd_info; 19struct mtd_info;
20 20
21#define KW_PCIE0 (1 << 0)
22#define KW_PCIE1 (1 << 1)
23
21/* 24/*
22 * Basic Kirkwood init functions used early by machine-setup. 25 * Basic Kirkwood init functions used early by machine-setup.
23 */ 26 */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
34void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); 37void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
35void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); 38void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
36void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); 39void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
37void kirkwood_pcie_init(void); 40void kirkwood_pcie_init(unsigned int portmask);
38void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); 41void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
39void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data); 42void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
40void kirkwood_spi_init(void); 43void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4bcace9..16f6691e7c68 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
51}; 51};
52 52
53static unsigned int db88f6281_mpp_config[] __initdata = { 53static unsigned int db88f6281_mpp_config[] __initdata = {
54 MPP0_NF_IO2,
55 MPP1_NF_IO3,
56 MPP2_NF_IO4,
57 MPP3_NF_IO5,
58 MPP4_NF_IO6,
59 MPP5_NF_IO7,
60 MPP18_NF_IO0,
61 MPP19_NF_IO1,
54 MPP37_GPIO, 62 MPP37_GPIO,
55 MPP38_GPIO, 63 MPP38_GPIO,
56 0 64 0
@@ -74,9 +82,15 @@ static void __init db88f6281_init(void)
74 82
75static int __init db88f6281_pci_init(void) 83static int __init db88f6281_pci_init(void)
76{ 84{
77 if (machine_is_db88f6281_bp()) 85 if (machine_is_db88f6281_bp()) {
78 kirkwood_pcie_init(); 86 u32 dev, rev;
79 87
88 kirkwood_pcie_id(&dev, &rev);
89 if (dev == MV88F6282_DEV_ID)
90 kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
91 else
92 kirkwood_pcie_init(KW_PCIE0);
93 }
80 return 0; 94 return 0;
81} 95}
82subsys_initcall(db88f6281_pci_init); 96subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f5017c50e..aff0e1327e38 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
59#define CGC_SATA1 (1 << 15) 59#define CGC_SATA1 (1 << 15)
60#define CGC_XOR1 (1 << 16) 60#define CGC_XOR1 (1 << 16)
61#define CGC_CRYPTO (1 << 17) 61#define CGC_CRYPTO (1 << 17)
62#define CGC_PEX1 (1 << 18)
62#define CGC_GE1 (1 << 19) 63#define CGC_GE1 (1 << 19)
63#define CGC_TDM (1 << 20) 64#define CGC_TDM (1 << 20)
64#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) 65#define CGC_RESERVED (0x6 << 21)
65 66
66#endif 67#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a45a67e..9da2eb59180b 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
23#define IRQ_KIRKWOOD_XOR_10 7 23#define IRQ_KIRKWOOD_XOR_10 7
24#define IRQ_KIRKWOOD_XOR_11 8 24#define IRQ_KIRKWOOD_XOR_11 8
25#define IRQ_KIRKWOOD_PCIE 9 25#define IRQ_KIRKWOOD_PCIE 9
26#define IRQ_KIRKWOOD_PCIE1 10
26#define IRQ_KIRKWOOD_GE00_SUM 11 27#define IRQ_KIRKWOOD_GE00_SUM 11
27#define IRQ_KIRKWOOD_GE01_SUM 15 28#define IRQ_KIRKWOOD_GE01_SUM 15
28#define IRQ_KIRKWOOD_USB 19 29#define IRQ_KIRKWOOD_USB 19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0ee22bd..d141af4c2744 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
16 * Marvell Kirkwood address maps. 16 * Marvell Kirkwood address maps.
17 * 17 *
18 * phys 18 * phys
19 * e0000000 PCIe Memory space 19 * e0000000 PCIe #0 Memory space
20 * e8000000 PCIe #1 Memory space
20 * f1000000 on-chip peripheral registers 21 * f1000000 on-chip peripheral registers
21 * f2000000 PCIe I/O space 22 * f2000000 PCIe #0 I/O space
22 * f3000000 NAND controller address window 23 * f3000000 PCIe #1 I/O space
23 * f4000000 Security Accelerator SRAM 24 * f4000000 NAND controller address window
25 * f5000000 Security Accelerator SRAM
24 * 26 *
25 * virt phys size 27 * virt phys size
26 * fee00000 f1000000 1M on-chip peripheral registers 28 * fed00000 f1000000 1M on-chip peripheral registers
27 * fef00000 f2000000 1M PCIe I/O space 29 * fee00000 f2000000 1M PCIe #0 I/O space
30 * fef00000 f3000000 1M PCIe #1 I/O space
28 */ 31 */
29 32
30#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 33#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
31#define KIRKWOOD_SRAM_SIZE SZ_2K 34#define KIRKWOOD_SRAM_SIZE SZ_2K
32 35
33#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 36#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
34#define KIRKWOOD_NAND_MEM_SIZE SZ_1K 37#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
35 38
39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
40#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
41#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000
42#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
43
36#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 44#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
37#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 45#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
38#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 46#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
39#define KIRKWOOD_PCIE_IO_SIZE SZ_1M 47#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
40 48
41#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 49#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
42#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 50#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
43#define KIRKWOOD_REGS_SIZE SZ_1M 51#define KIRKWOOD_REGS_SIZE SZ_1M
44 52
45#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 53#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
46#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000 54#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
47#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M 55#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
48 56
57#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
58#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
59#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
60
49/* 61/*
50 * Register Map 62 * Register Map
51 */ 63 */
@@ -72,6 +84,9 @@
72#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) 84#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
73#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) 85#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
74#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) 86#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
87#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
88#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
89#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
75 90
76#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) 91#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
77 92
@@ -107,8 +122,12 @@
107#define MV88F6192_DEV_ID 0x6192 122#define MV88F6192_DEV_ID 0x6192
108#define MV88F6192_REV_Z0 0 123#define MV88F6192_REV_Z0 0
109#define MV88F6192_REV_A0 2 124#define MV88F6192_REV_A0 2
125#define MV88F6192_REV_A1 3
110 126
111#define MV88F6180_DEV_ID 0x6180 127#define MV88F6180_DEV_ID 0x6180
112#define MV88F6180_REV_A0 2 128#define MV88F6180_REV_A0 2
129#define MV88F6180_REV_A1 3
113 130
131#define MV88F6282_DEV_ID 0x6282
132#define MV88F6282_REV_A0 0
114#endif 133#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
new file mode 100644
index 000000000000..e21272e5f668
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-kirkwood/include/mach/leds-ns2.h
3 *
4 * Platform data structure for Network Space v2 LED driver
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __MACH_LEDS_NS2_H
12#define __MACH_LEDS_NS2_H
13
14struct ns2_led {
15 const char *name;
16 const char *default_trigger;
17 unsigned cmd;
18 unsigned slow;
19};
20
21struct ns2_led_platform_data {
22 int num_leds;
23 struct ns2_led *leds;
24};
25
26#endif /* __MACH_LEDS_NS2_H */
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f64e38c..065187d177c6 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
23 23
24 kirkwood_pcie_id(&dev, &rev); 24 kirkwood_pcie_id(&dev, &rev);
25 25
26 if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) 26 if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
27 (dev == MV88F6282_DEV_ID))
27 return MPP_F6281_MASK; 28 return MPP_F6281_MASK;
28 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) 29 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
29 return MPP_F6192_MASK; 30 return MPP_F6192_MASK;
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278ed311..9b0a94d85c3e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
11#ifndef __KIRKWOOD_MPP_H 11#ifndef __KIRKWOOD_MPP_H
12#define __KIRKWOOD_MPP_H 12#define __KIRKWOOD_MPP_H
13 13
14#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ 14#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
15 /* MPP number */ ((_num) & 0xff) | \ 15 /* MPP number */ ((_num) & 0xff) | \
16 /* MPP select value */ (((_sel) & 0xf) << 8) | \ 16 /* MPP select value */ (((_sel) & 0xf) << 8) | \
17 /* may be input signal */ ((!!(_in)) << 12) | \ 17 /* may be input signal */ ((!!(_in)) << 12) | \
@@ -19,282 +19,332 @@
19 /* available on F6180 */ ((!!(_F6180)) << 14) | \ 19 /* available on F6180 */ ((!!(_F6180)) << 14) | \
20 /* available on F6190 */ ((!!(_F6190)) << 15) | \ 20 /* available on F6190 */ ((!!(_F6190)) << 15) | \
21 /* available on F6192 */ ((!!(_F6192)) << 16) | \ 21 /* available on F6192 */ ((!!(_F6192)) << 16) | \
22 /* available on F6281 */ ((!!(_F6281)) << 17)) 22 /* available on F6281 */ ((!!(_F6281)) << 17) | \
23 /* available on F6282 */ ((!!(_F6282)) << 18))
23 24
24#define MPP_NUM(x) ((x) & 0xff) 25#define MPP_NUM(x) ((x) & 0xff)
25#define MPP_SEL(x) (((x) >> 8) & 0xf) 26#define MPP_SEL(x) (((x) >> 8) & 0xf)
26 27
27 /* num sel i o 6180 6190 6192 6281 */ 28 /* num sel i o 6180 6190 6192 6281 6282 */
28 29
29#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) 30#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
30#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) 31#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
31 32
32#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) 33#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
33#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) 34#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
34#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) 35#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
35#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) 36#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1, 0 )
36 37#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
37#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) 38
38#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) 39#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
39#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) 40#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 )
40 41#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 )
41#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) 42
42#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) 43#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
43#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) 44#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 )
44 45#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 )
45#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) 46
46#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) 47#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
47#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) 48#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 )
48 49#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 )
49#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) 50
50#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) 51#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
51#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) 52#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 )
52 53#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 )
53#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) 54
54#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) 55#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
55#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) 56#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 )
56#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) 57#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 )
57#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) 58#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 )
58 59#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
59#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) 60#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 )
60#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) 61
61#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) 62#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
62#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) 63#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 )
63#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) 64#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 )
64 65#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 )
65#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) 66#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 )
66#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) 67#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
67#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) 68
68 69#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 )
69#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) 70#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 )
70#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) 71#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 )
71#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) 72
72#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) 73#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
73 74#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 )
74#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) 75#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 )
75#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) 76#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 )
76#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) 77#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 )
77#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) 78
78#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) 79#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
79#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) 80#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 )
80#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) 81#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 )
81#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) 82#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 )
82 83#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 )
83#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) 84#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 )
84#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) 85#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 )
85#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) 86#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 )
86#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) 87
87#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) 88#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
88#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) 89#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 )
89#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) 90#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 )
90 91#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 )
91#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) 92#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 )
92#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) 93#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 )
93#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) 94#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 )
94#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) 95
95#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) 96#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
96 97#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 )
97#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) 98#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 )
98#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) 99#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 )
99#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) 100#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 )
100#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) 101
101#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) 102#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
102#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) 103#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 )
103#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) 104#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 )
104 105#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 )
105#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) 106#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 )
106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) 107#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 )
107 108#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
108#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) 109
109#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) 110#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
110#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) 111#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
111 112#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
112#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) 113#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
113#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) 114#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 )
114#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) 115
115#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) 116#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
116#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) 117#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 )
117 118#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 )
118#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) 119#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 )
119#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) 120#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 )
120#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) 121
121#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) 122#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
122#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) 123#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 )
123 124#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 )
124#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) 125#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 )
125#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) 126#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 )
126#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) 127#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 )
127#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) 128#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 )
128#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) 129
129#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) 130#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
130 131#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 )
131#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) 132#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 )
132#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) 133#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 )
133#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) 134#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 )
134 135#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 )
135#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) 136
136#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) 137#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
137 138#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 )
138#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) 139#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 )
139#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) 140#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 )
140 141#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 )
141#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) 142#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 )
142#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) 143#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 )
143#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) 144
144#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) 145#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
145#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) 146#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 )
146#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) 147#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 )
147 148#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 )
148#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) 149#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 )
149#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) 150
150#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) 151#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
151#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) 152#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 )
152#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) 153#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 )
153#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) 154
154 155#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
155#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) 156#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 )
156#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) 157
157#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) 158#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
158#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) 159#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 )
159#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) 160#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 )
160#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) 161#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
161 162#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 )
162#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) 163#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 )
163#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) 164#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
164#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) 165
165#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) 166#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
166#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) 167#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 )
167#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) 168#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 )
168 169#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
169#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) 170#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 )
170#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) 171#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 )
171#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) 172#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
172#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) 173
173#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) 174#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
174 175#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 )
175#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) 176#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 )
176#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) 177#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
177#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) 178#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 )
178#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) 179#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 )
179#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) 180#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
180 181
181#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) 182#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
182#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) 183#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 )
183#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) 184#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 )
184#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) 185#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
185#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) 186#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 )
186 187#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 )
187#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) 188#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
188#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) 189
189#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) 190#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
190#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) 191#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 )
191#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) 192#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 )
192 193#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
193#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) 194#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 )
194#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) 195#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
195#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) 196
196#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) 197#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
197#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) 198#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 )
198 199#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 )
199#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) 200#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
200#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) 201#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 )
201#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) 202#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
202#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) 203
203 204#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
204#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) 205#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 )
205#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) 206#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 )
206#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) 207#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
207#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) 208#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 )
208 209#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
209#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) 210
210#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) 211#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
211#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) 212#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 )
212#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) 213#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 )
213 214#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
214#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) 215#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 )
215#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) 216#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
216#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) 217
217#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) 218#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
218 219#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 )
219#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) 220#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
220#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) 221#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
221#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) 222#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 )
222 223#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
223#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) 224
224#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) 225#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
225#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) 226#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 )
226 227#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
227#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) 228#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
228#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) 229#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
229#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) 230
230#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) 231#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
231#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) 232#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 )
232 233#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 )
233#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) 234#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
234#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) 235#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
235#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) 236
236#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) 237#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
237 238#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 )
238#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) 239#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 )
239#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) 240#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
240#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) 241#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
241#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) 242
242 243#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
243#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) 244#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 )
244#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) 245#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 )
245#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) 246#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
246#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) 247#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
247 248
248#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) 249#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
249#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) 250#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 )
250#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) 251#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
251#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) 252#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
252 253
253#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) 254#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
254#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) 255#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 )
255#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) 256#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
256#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) 257#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 )
257 258#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
258#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) 259
259#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) 260#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
260#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) 261#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 )
261#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) 262#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
262 263#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 )
263#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) 264#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
264#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) 265#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 )
265#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) 266
266#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) 267#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
267 268#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 )
268#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) 269#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 )
269#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) 270#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 )
270#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) 271#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 )
271#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) 272
272 273#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
273#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) 274#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 )
274#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) 275#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 )
275#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) 276#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 )
276#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) 277#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 )
277 278
278#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) 279#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
279#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) 280#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 )
280#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) 281#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 )
281 282#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 )
282#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) 283#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
283#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) 284
284#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) 285#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
285 286#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 )
286#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) 287#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 )
287#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) 288#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 )
288#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) 289#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
289 290
290#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) 291#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
291#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) 292#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 )
292#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) 293#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 )
293 294#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 )
294#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) 295#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
295#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) 296
296#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) 297#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
297#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) 298#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 )
299#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 )
300#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 )
301#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
302
303#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
304#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 )
305#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 )
306#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 )
307#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
308
309#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
310#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 )
311#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
312#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 )
313#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
314
315#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
316#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 )
317#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
318#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 )
319#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
320
321#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
322#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 )
323#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 )
324#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
325
326#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
327#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 )
328#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 )
329#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
330
331#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
332#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 )
333#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 )
334#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
335
336#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
337#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 )
338#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 )
339#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
340
341#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
342#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
343#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 )
344#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 )
345#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 )
346#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 )
347#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
298 348
299#define MPP_MAX 49 349#define MPP_MAX 49
300 350
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711b1c67..c6b92b42eb4e 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
155static int __init mv88f6281gtw_ge_pci_init(void) 155static int __init mv88f6281gtw_ge_pci_init(void)
156{ 156{
157 if (machine_is_mv88f6281gtw_ge()) 157 if (machine_is_mv88f6281gtw_ge())
158 kirkwood_pcie_init(); 158 kirkwood_pcie_init(KW_PCIE0);
159 159
160 return 0; 160 return 0;
161} 161}
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d72681..d26bf324738b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -39,6 +39,7 @@
39#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
40#include <asm/mach/time.h> 40#include <asm/mach/time.h>
41#include <mach/kirkwood.h> 41#include <mach/kirkwood.h>
42#include <mach/leds-ns2.h>
42#include <plat/time.h> 43#include <plat/time.h>
43#include "common.h" 44#include "common.h"
44#include "mpp.h" 45#include "mpp.h"
@@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void)
126 } 127 }
127 if (err) 128 if (err)
128 pr_err("netspace_v2: failed to setup SATA0 power\n"); 129 pr_err("netspace_v2: failed to setup SATA0 power\n");
130
131 if (machine_is_netspace_max_v2()) {
132 err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
133 if (err == 0) {
134 err = gpio_direction_output(
135 NETSPACE_V2_GPIO_SATA1_POWER, 1);
136 if (err)
137 gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
138 }
139 if (err)
140 pr_err("netspace_v2: failed to setup SATA1 power\n");
141 }
129} 142}
130 143
131/***************************************************************************** 144/*****************************************************************************
@@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = {
160 * GPIO LEDs 173 * GPIO LEDs
161 ****************************************************************************/ 174 ****************************************************************************/
162 175
163/*
164 * The blue front LED is wired to a CPLD and can blink in relation with the
165 * SATA activity.
166 *
167 * The following array detail the different LED registers and the combination
168 * of their possible values:
169 *
170 * cmd_led | slow_led | /SATA active | LED state
171 * | | |
172 * 1 | 0 | x | off
173 * - | 1 | x | on
174 * 0 | 0 | 1 | on
175 * 0 | 0 | 0 | blink (rate 300ms)
176 */
177
178#define NETSPACE_V2_GPIO_RED_LED 12 176#define NETSPACE_V2_GPIO_RED_LED 12
179#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
180#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
181
182 177
183static struct gpio_led netspace_v2_gpio_led_pins[] = { 178static struct gpio_led netspace_v2_gpio_led_pins[] = {
184 { 179 {
185 .name = "ns_v2:blue:sata", 180 .name = "ns_v2:red:fail",
186 .default_trigger = "default-on", 181 .gpio = NETSPACE_V2_GPIO_RED_LED,
187 .gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD,
188 .active_low = 1,
189 },
190 {
191 .name = "ns_v2:red:fail",
192 .gpio = NETSPACE_V2_GPIO_RED_LED,
193 }, 182 },
194}; 183};
195 184
@@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = {
206 }, 195 },
207}; 196};
208 197
209static void __init netspace_v2_gpio_leds_init(void) 198/*****************************************************************************
210{ 199 * Dual-GPIO CPLD LEDs
211 int err; 200 ****************************************************************************/
212 201
213 /* Configure register slow_led to allow SATA activity LED blinking */ 202#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
214 err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow"); 203#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
215 if (err == 0) {
216 err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0);
217 if (err)
218 gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
219 }
220 if (err)
221 pr_err("netspace_v2: failed to configure blue LED slow GPIO\n");
222 204
223 platform_device_register(&netspace_v2_gpio_leds); 205static struct ns2_led netspace_v2_led_pins[] = {
224} 206 {
207 .name = "ns_v2:blue:sata",
208 .cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD,
209 .slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
210 },
211};
212
213static struct ns2_led_platform_data netspace_v2_leds_data = {
214 .num_leds = ARRAY_SIZE(netspace_v2_led_pins),
215 .leds = netspace_v2_led_pins,
216};
217
218static struct platform_device netspace_v2_leds = {
219 .name = "leds-ns2",
220 .id = -1,
221 .dev = {
222 .platform_data = &netspace_v2_leds_data,
223 },
224};
225 225
226/***************************************************************************** 226/*****************************************************************************
227 * Timer 227 * Timer
@@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
249 MPP4_NF_IO6, 249 MPP4_NF_IO6,
250 MPP5_NF_IO7, 250 MPP5_NF_IO7,
251 MPP6_SYSRST_OUTn, 251 MPP6_SYSRST_OUTn,
252 MPP8_TW_SDA, 252 MPP7_GPO, /* Fan speed (bit 1) */
253 MPP9_TW_SCK, 253 MPP8_TW0_SDA,
254 MPP9_TW0_SCK,
254 MPP10_UART0_TXD, 255 MPP10_UART0_TXD,
255 MPP11_UART0_RXD, 256 MPP11_UART0_RXD,
256 MPP12_GPO, /* Red led */ 257 MPP12_GPO, /* Red led */
257 MPP14_GPIO, /* USB fuse */ 258 MPP14_GPIO, /* USB fuse */
258 MPP16_GPIO, /* SATA 0 power */ 259 MPP16_GPIO, /* SATA 0 power */
260 MPP17_GPIO, /* SATA 1 power */
259 MPP18_NF_IO0, 261 MPP18_NF_IO0,
260 MPP19_NF_IO1, 262 MPP19_NF_IO1,
261 MPP20_SATA1_ACTn, 263 MPP20_SATA1_ACTn,
262 MPP21_SATA0_ACTn, 264 MPP21_SATA0_ACTn,
265 MPP22_GPIO, /* Fan speed (bit 0) */
266 MPP23_GPIO, /* Fan power */
263 MPP24_GPIO, /* USB mode select */ 267 MPP24_GPIO, /* USB mode select */
264 MPP25_GPIO, /* Fan rotation fail */ 268 MPP25_GPIO, /* Fan rotation fail */
265 MPP26_GPIO, /* USB device vbus */ 269 MPP26_GPIO, /* USB device vbus */
@@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
268 MPP30_GPIO, /* Blue led (command register) */ 272 MPP30_GPIO, /* Blue led (command register) */
269 MPP31_GPIO, /* Board power off */ 273 MPP31_GPIO, /* Board power off */
270 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ 274 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
275 MPP33_GPO, /* Fan speed (bit 2) */
271 0 276 0
272}; 277};
273 278
@@ -299,7 +304,8 @@ static void __init netspace_v2_init(void)
299 i2c_register_board_info(0, netspace_v2_i2c_info, 304 i2c_register_board_info(0, netspace_v2_i2c_info,
300 ARRAY_SIZE(netspace_v2_i2c_info)); 305 ARRAY_SIZE(netspace_v2_i2c_info));
301 306
302 netspace_v2_gpio_leds_init(); 307 platform_device_register(&netspace_v2_leds);
308 platform_device_register(&netspace_v2_gpio_leds);
303 platform_device_register(&netspace_v2_gpio_buttons); 309 platform_device_register(&netspace_v2_gpio_buttons);
304 310
305 if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && 311 if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
332 .timer = &netspace_v2_timer, 338 .timer = &netspace_v2_timer,
333MACHINE_END 339MACHINE_END
334#endif 340#endif
341
342#ifdef CONFIG_MACH_NETSPACE_MAX_V2
343MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
344 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
345 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
346 .boot_params = 0x00000100,
347 .init_machine = netspace_v2_init,
348 .map_io = kirkwood_map_io,
349 .init_irq = kirkwood_init_irq,
350 .timer = &netspace_v2_timer,
351MACHINE_END
352#endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb0228e4f..2bd14c5079de 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
270 MPP3_SPI_MISO, 270 MPP3_SPI_MISO,
271 MPP6_SYSRST_OUTn, 271 MPP6_SYSRST_OUTn,
272 MPP7_GPO, /* Request power-off */ 272 MPP7_GPO, /* Request power-off */
273 MPP8_TW_SDA, 273 MPP8_TW0_SDA,
274 MPP9_TW_SCK, 274 MPP9_TW0_SCK,
275 MPP10_UART0_TXD, 275 MPP10_UART0_TXD,
276 MPP11_UART0_RXD, 276 MPP11_UART0_RXD,
277 MPP13_GPIO, /* Rear power switch (on|auto) */ 277 MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
306 MPP3_SPI_MISO, 306 MPP3_SPI_MISO,
307 MPP6_SYSRST_OUTn, 307 MPP6_SYSRST_OUTn,
308 MPP7_GPO, /* Request power-off */ 308 MPP7_GPO, /* Request power-off */
309 MPP8_TW_SDA, 309 MPP8_TW0_SDA,
310 MPP9_TW_SCK, 310 MPP9_TW0_SCK,
311 MPP10_UART0_TXD, 311 MPP10_UART0_TXD,
312 MPP11_UART0_RXD, 312 MPP11_UART0_RXD,
313 MPP13_GPIO, /* Rear power switch (on|auto) */ 313 MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
315 MPP15_GPIO, /* Rear power switch (auto|off) */ 315 MPP15_GPIO, /* Rear power switch (auto|off) */
316 MPP16_GPIO, /* SATA HDD1 power */ 316 MPP16_GPIO, /* SATA HDD1 power */
317 MPP17_GPIO, /* SATA HDD2 power */ 317 MPP17_GPIO, /* SATA HDD2 power */
318 MPP20_GE1_0, 318 MPP20_GE1_TXD0,
319 MPP21_GE1_1, 319 MPP21_GE1_TXD1,
320 MPP22_GE1_2, 320 MPP22_GE1_TXD2,
321 MPP23_GE1_3, 321 MPP23_GE1_TXD3,
322 MPP24_GE1_4, 322 MPP24_GE1_RXD0,
323 MPP25_GE1_5, 323 MPP25_GE1_RXD1,
324 MPP26_GE1_6, 324 MPP26_GE1_RXD2,
325 MPP27_GE1_7, 325 MPP27_GE1_RXD3,
326 MPP28_GPIO, /* USB enable host vbus */ 326 MPP28_GPIO, /* USB enable host vbus */
327 MPP29_GPIO, /* CPLD extension ALE */ 327 MPP29_GPIO, /* CPLD extension ALE */
328 MPP30_GE1_10, 328 MPP30_GE1_RXCTL,
329 MPP31_GE1_11, 329 MPP31_GE1_RXCLK,
330 MPP32_GE1_12, 330 MPP32_GE1_TCLKOUT,
331 MPP33_GE1_13, 331 MPP33_GE1_TXCTL,
332 MPP34_GPIO, /* Rear Push button */ 332 MPP34_GPIO, /* Rear Push button */
333 MPP35_GPIO, /* Inhibit switch power-off */ 333 MPP35_GPIO, /* Inhibit switch power-off */
334 MPP36_GPIO, /* SATA HDD1 presence */ 334 MPP36_GPIO, /* SATA HDD1 presence */
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec33796..fd64cd2b4e0a 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-kirkwood/openrd-setup.c 2 * arch/arm/mach-kirkwood/openrd-setup.c
3 * 3 *
4 * Marvell OpenRD (Base|Client) Board Setup 4 * Marvell OpenRD (Base|Client|Ultimate) Board Setup
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 7 * License version 2. This program is licensed "as is" without any
@@ -73,9 +73,15 @@ static void __init openrd_init(void)
73 73
74 kirkwood_ehci_init(); 74 kirkwood_ehci_init();
75 75
76 if (machine_is_openrd_ultimate()) {
77 openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
78 openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
79 }
80
76 kirkwood_ge00_init(&openrd_ge00_data); 81 kirkwood_ge00_init(&openrd_ge00_data);
77 if (machine_is_openrd_client()) 82 if (!machine_is_openrd_base())
78 kirkwood_ge01_init(&openrd_ge01_data); 83 kirkwood_ge01_init(&openrd_ge01_data);
84
79 kirkwood_sata_init(&openrd_sata_data); 85 kirkwood_sata_init(&openrd_sata_data);
80 kirkwood_sdio_init(&openrd_mvsdio_data); 86 kirkwood_sdio_init(&openrd_mvsdio_data);
81 87
@@ -84,8 +90,10 @@ static void __init openrd_init(void)
84 90
85static int __init openrd_pci_init(void) 91static int __init openrd_pci_init(void)
86{ 92{
87 if (machine_is_openrd_base() || machine_is_openrd_client()) 93 if (machine_is_openrd_base() ||
88 kirkwood_pcie_init(); 94 machine_is_openrd_client() ||
95 machine_is_openrd_ultimate())
96 kirkwood_pcie_init(KW_PCIE0);
89 97
90 return 0; 98 return 0;
91} 99}
@@ -116,3 +124,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
116 .timer = &kirkwood_timer, 124 .timer = &kirkwood_timer,
117MACHINE_END 125MACHINE_END
118#endif 126#endif
127
128#ifdef CONFIG_MACH_OPENRD_ULTIMATE
129MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
130 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
131 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
132 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
133 .boot_params = 0x00000100,
134 .init_machine = openrd_init,
135 .map_io = kirkwood_map_io,
136 .init_irq = kirkwood_init_irq,
137 .timer = &kirkwood_timer,
138MACHINE_END
139#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff50d39..55e7f00836b7 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
18#include <mach/bridge-regs.h> 18#include <mach/bridge-regs.h>
19#include "common.h" 19#include "common.h"
20 20
21void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
22{
23 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
24 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
25}
21 26
22#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) 27struct pcie_port {
28 u8 root_bus_nr;
29 void __iomem *base;
30 spinlock_t conf_lock;
31 int irq;
32 struct resource res[2];
33};
23 34
24void __init kirkwood_pcie_id(u32 *dev, u32 *rev) 35static int pcie_port_map[2];
36static int num_pcie_ports;
37
38static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
25{ 39{
26 *dev = orion_pcie_dev_id(PCIE_BASE); 40 struct pci_sys_data *sys = bus->sysdata;
27 *rev = orion_pcie_rev(PCIE_BASE); 41 return sys->private_data;
28} 42}
29 43
30static int pcie_valid_config(int bus, int dev) 44static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
31{ 45{
32 /* 46 /*
33 * Don't go out when trying to access -- 47 * Don't go out when trying to access --
34 * 1. nonexisting device on local bus 48 * 1. nonexisting device on local bus
35 * 2. where there's no device connected (no link) 49 * 2. where there's no device connected (no link)
36 */ 50 */
37 if (bus == 0 && dev == 0) 51 if (bus == pp->root_bus_nr && dev == 0)
38 return 1; 52 return 1;
39 53
40 if (!orion_pcie_link_up(PCIE_BASE)) 54 if (!orion_pcie_link_up(pp->base))
41 return 0; 55 return 0;
42 56
43 if (bus == 0 && dev != 1) 57 if (bus == pp->root_bus_nr && dev != 1)
44 return 0; 58 return 0;
45 59
46 return 1; 60 return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
52 * and then reading the PCIE_CONF_DATA register. Need to make sure these 66 * and then reading the PCIE_CONF_DATA register. Need to make sure these
53 * transactions are atomic. 67 * transactions are atomic.
54 */ 68 */
55static DEFINE_SPINLOCK(kirkwood_pcie_lock);
56 69
57static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 70static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
58 int size, u32 *val) 71 int size, u32 *val)
59{ 72{
73 struct pcie_port *pp = bus_to_port(bus);
60 unsigned long flags; 74 unsigned long flags;
61 int ret; 75 int ret;
62 76
63 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 77 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
64 *val = 0xffffffff; 78 *val = 0xffffffff;
65 return PCIBIOS_DEVICE_NOT_FOUND; 79 return PCIBIOS_DEVICE_NOT_FOUND;
66 } 80 }
67 81
68 spin_lock_irqsave(&kirkwood_pcie_lock, flags); 82 spin_lock_irqsave(&pp->conf_lock, flags);
69 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 83 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
70 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); 84 spin_unlock_irqrestore(&pp->conf_lock, flags);
71 85
72 return ret; 86 return ret;
73} 87}
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
75static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 89static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
76 int where, int size, u32 val) 90 int where, int size, u32 val)
77{ 91{
92 struct pcie_port *pp = bus_to_port(bus);
78 unsigned long flags; 93 unsigned long flags;
79 int ret; 94 int ret;
80 95
81 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 96 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
82 return PCIBIOS_DEVICE_NOT_FOUND; 97 return PCIBIOS_DEVICE_NOT_FOUND;
83 98
84 spin_lock_irqsave(&kirkwood_pcie_lock, flags); 99 spin_lock_irqsave(&pp->conf_lock, flags);
85 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 100 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
86 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); 101 spin_unlock_irqrestore(&pp->conf_lock, flags);
87 102
88 return ret; 103 return ret;
89} 104}
@@ -93,50 +108,98 @@ static struct pci_ops pcie_ops = {
93 .write = pcie_wr_conf, 108 .write = pcie_wr_conf,
94}; 109};
95 110
96 111static void __init pcie0_ioresources_init(struct pcie_port *pp)
97static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
98{ 112{
99 struct resource *res; 113 pp->base = (void __iomem *)PCIE_VIRT_BASE;
100 extern unsigned int kirkwood_clk_ctrl; 114 pp->irq = IRQ_KIRKWOOD_PCIE;
101 115
102 /* 116 /*
103 * Generic PCIe unit setup. 117 * IORESOURCE_IO
104 */ 118 */
105 orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); 119 pp->res[0].name = "PCIe 0 I/O Space";
120 pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
121 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
122 pp->res[0].flags = IORESOURCE_IO;
106 123
107 /* 124 /*
108 * Request resources. 125 * IORESOURCE_MEM
109 */ 126 */
110 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 127 pp->res[1].name = "PCIe 0 MEM";
111 if (!res) 128 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
112 panic("pcie_setup unable to alloc resources"); 129 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
130 pp->res[1].flags = IORESOURCE_MEM;
131}
132
133static void __init pcie1_ioresources_init(struct pcie_port *pp)
134{
135 pp->base = (void __iomem *)PCIE1_VIRT_BASE;
136 pp->irq = IRQ_KIRKWOOD_PCIE1;
113 137
114 /* 138 /*
115 * IORESOURCE_IO 139 * IORESOURCE_IO
116 */ 140 */
117 res[0].name = "PCIe I/O Space"; 141 pp->res[0].name = "PCIe 1 I/O Space";
118 res[0].flags = IORESOURCE_IO; 142 pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
119 res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; 143 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
120 res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; 144 pp->res[0].flags = IORESOURCE_IO;
121 if (request_resource(&ioport_resource, &res[0]))
122 panic("Request PCIe IO resource failed\n");
123 sys->resource[0] = &res[0];
124 145
125 /* 146 /*
126 * IORESOURCE_MEM 147 * IORESOURCE_MEM
127 */ 148 */
128 res[1].name = "PCIe Memory Space"; 149 pp->res[1].name = "PCIe 1 MEM";
129 res[1].flags = IORESOURCE_MEM; 150 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
130 res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE; 151 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
131 res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; 152 pp->res[1].flags = IORESOURCE_MEM;
132 if (request_resource(&iomem_resource, &res[1])) 153}
133 panic("Request PCIe Memory resource failed\n"); 154
134 sys->resource[1] = &res[1]; 155static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
156{
157 extern unsigned int kirkwood_clk_ctrl;
158 struct pcie_port *pp;
159 int index;
135 160
161 if (nr >= num_pcie_ports)
162 return 0;
163
164 index = pcie_port_map[nr];
165 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
166
167 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
168 if (!pp)
169 panic("PCIe: failed to allocate pcie_port data");
170 sys->private_data = pp;
171 pp->root_bus_nr = sys->busnr;
172 spin_lock_init(&pp->conf_lock);
173
174 switch (index) {
175 case 0:
176 kirkwood_clk_ctrl |= CGC_PEX0;
177 pcie0_ioresources_init(pp);
178 break;
179 case 1:
180 kirkwood_clk_ctrl |= CGC_PEX1;
181 pcie1_ioresources_init(pp);
182 break;
183 default:
184 panic("PCIe setup: invalid controller %d", index);
185 }
186
187 if (request_resource(&ioport_resource, &pp->res[0]))
188 panic("Request PCIe%d IO resource failed\n", index);
189 if (request_resource(&iomem_resource, &pp->res[1]))
190 panic("Request PCIe%d Memory resource failed\n", index);
191
192 sys->resource[0] = &pp->res[0];
193 sys->resource[1] = &pp->res[1];
136 sys->resource[2] = NULL; 194 sys->resource[2] = NULL;
137 sys->io_offset = 0; 195 sys->io_offset = 0;
138 196
139 kirkwood_clk_ctrl |= CGC_PEX0; 197 /*
198 * Generic PCIe unit setup.
199 */
200 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
201
202 orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
140 203
141 return 1; 204 return 1;
142} 205}
@@ -163,7 +226,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
163{ 226{
164 struct pci_bus *bus; 227 struct pci_bus *bus;
165 228
166 if (nr == 0) { 229 if (nr < num_pcie_ports) {
167 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 230 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
168 } else { 231 } else {
169 bus = NULL; 232 bus = NULL;
@@ -175,18 +238,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
175 238
176static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 239static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
177{ 240{
178 return IRQ_KIRKWOOD_PCIE; 241 struct pcie_port *pp = bus_to_port(dev->bus);
242
243 return pp->irq;
179} 244}
180 245
181static struct hw_pci kirkwood_pci __initdata = { 246static struct hw_pci kirkwood_pci __initdata = {
182 .nr_controllers = 1,
183 .swizzle = pci_std_swizzle, 247 .swizzle = pci_std_swizzle,
184 .setup = kirkwood_pcie_setup, 248 .setup = kirkwood_pcie_setup,
185 .scan = kirkwood_pcie_scan_bus, 249 .scan = kirkwood_pcie_scan_bus,
186 .map_irq = kirkwood_pcie_map_irq, 250 .map_irq = kirkwood_pcie_map_irq,
187}; 251};
188 252
189void __init kirkwood_pcie_init(void) 253static void __init add_pcie_port(int index, unsigned long base)
190{ 254{
255 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
256
257 if (orion_pcie_link_up((void __iomem *)base)) {
258 printk(KERN_INFO "link up\n");
259 pcie_port_map[num_pcie_ports++] = index;
260 } else
261 printk(KERN_INFO "link down, ignoring\n");
262}
263
264void __init kirkwood_pcie_init(unsigned int portmask)
265{
266 if (portmask & KW_PCIE0)
267 add_pcie_port(0, PCIE_VIRT_BASE);
268
269 if (portmask & KW_PCIE1)
270 add_pcie_port(1, PCIE1_VIRT_BASE);
271
272 kirkwood_pci.nr_controllers = num_pcie_ports;
191 pci_common_init(&kirkwood_pci); 273 pci_common_init(&kirkwood_pci);
192} 274}
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304158f6..c34718c2cfe5 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
71static int __init rd88f6192_pci_init(void) 71static int __init rd88f6192_pci_init(void)
72{ 72{
73 if (machine_is_rd88f6192_nas()) 73 if (machine_is_rd88f6192_nas())
74 kirkwood_pcie_init(); 74 kirkwood_pcie_init(KW_PCIE0);
75 75
76 return 0; 76 return 0;
77} 77}
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708ddbc83e..3d1477135e12 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
107static int __init rd88f6281_pci_init(void) 107static int __init rd88f6281_pci_init(void)
108{ 108{
109 if (machine_is_rd88f6281()) 109 if (machine_is_rd88f6281())
110 kirkwood_pcie_init(); 110 kirkwood_pcie_init(KW_PCIE0);
111 111
112 return 0; 112 return 0;
113} 113}
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
new file mode 100644
index 000000000000..d01bf89cedbe
--- /dev/null
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -0,0 +1,194 @@
1/*
2 *
3 * HP t5325 Thin Client setup
4 *
5 * Copyright (C) 2010 Martin Michlmayr <tbm@cyrius.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/physmap.h>
17#include <linux/spi/flash.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/orion_spi.h>
20#include <linux/i2c.h>
21#include <linux/mv643xx_eth.h>
22#include <linux/ata_platform.h>
23#include <linux/gpio.h>
24#include <linux/gpio_keys.h>
25#include <linux/input.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <mach/kirkwood.h>
29#include "common.h"
30#include "mpp.h"
31
32struct mtd_partition hp_t5325_partitions[] = {
33 {
34 .name = "u-boot env",
35 .size = SZ_64K,
36 .offset = SZ_512K + SZ_256K,
37 },
38 {
39 .name = "permanent u-boot env",
40 .size = SZ_64K,
41 .offset = MTDPART_OFS_APPEND,
42 .mask_flags = MTD_WRITEABLE,
43 },
44 {
45 .name = "HP env",
46 .size = SZ_64K,
47 .offset = MTDPART_OFS_APPEND,
48 },
49 {
50 .name = "u-boot",
51 .size = SZ_512K,
52 .offset = 0,
53 .mask_flags = MTD_WRITEABLE,
54 },
55 {
56 .name = "SSD firmware",
57 .size = SZ_256K,
58 .offset = SZ_512K,
59 },
60};
61
62const struct flash_platform_data hp_t5325_flash = {
63 .type = "mx25l8005",
64 .name = "spi_flash",
65 .parts = hp_t5325_partitions,
66 .nr_parts = ARRAY_SIZE(hp_t5325_partitions),
67};
68
69struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
70 {
71 .modalias = "m25p80",
72 .platform_data = &hp_t5325_flash,
73 .irq = -1,
74 },
75};
76
77static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
78 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
79};
80
81static struct mv_sata_platform_data hp_t5325_sata_data = {
82 .n_ports = 2,
83};
84
85static struct gpio_keys_button hp_t5325_buttons[] = {
86 {
87 .code = KEY_POWER,
88 .gpio = 45,
89 .desc = "Power",
90 .active_low = 1,
91 },
92};
93
94static struct gpio_keys_platform_data hp_t5325_button_data = {
95 .buttons = hp_t5325_buttons,
96 .nbuttons = ARRAY_SIZE(hp_t5325_buttons),
97};
98
99static struct platform_device hp_t5325_button_device = {
100 .name = "gpio-keys",
101 .id = -1,
102 .num_resources = 0,
103 .dev = {
104 .platform_data = &hp_t5325_button_data,
105 }
106};
107
108static unsigned int hp_t5325_mpp_config[] __initdata = {
109 MPP0_NF_IO2,
110 MPP1_SPI_MOSI,
111 MPP2_SPI_SCK,
112 MPP3_SPI_MISO,
113 MPP4_NF_IO6,
114 MPP5_NF_IO7,
115 MPP6_SYSRST_OUTn,
116 MPP7_SPI_SCn,
117 MPP8_TW0_SDA,
118 MPP9_TW0_SCK,
119 MPP10_UART0_TXD,
120 MPP11_UART0_RXD,
121 MPP12_SD_CLK,
122 MPP13_GPIO,
123 MPP14_GPIO,
124 MPP15_GPIO,
125 MPP16_GPIO,
126 MPP17_GPIO,
127 MPP18_NF_IO0,
128 MPP19_NF_IO1,
129 MPP20_GPIO,
130 MPP21_GPIO,
131 MPP22_GPIO,
132 MPP23_GPIO,
133 MPP32_GPIO,
134 MPP33_GE1_TXCTL,
135 MPP39_AU_I2SBCLK,
136 MPP40_AU_I2SDO,
137 MPP41_AU_I2SLRCLK,
138 MPP42_AU_I2SMCLK,
139 MPP45_GPIO, /* Power button */
140 MPP48_GPIO, /* Board power off */
141 0
142};
143
144#define HP_T5325_GPIO_POWER_OFF 48
145
146static void hp_t5325_power_off(void)
147{
148 gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
149}
150
151static void __init hp_t5325_init(void)
152{
153 /*
154 * Basic setup. Needs to be called early.
155 */
156 kirkwood_init();
157 kirkwood_mpp_conf(hp_t5325_mpp_config);
158
159 kirkwood_uart0_init();
160 spi_register_board_info(hp_t5325_spi_slave_info,
161 ARRAY_SIZE(hp_t5325_spi_slave_info));
162 kirkwood_spi_init();
163 kirkwood_i2c_init();
164 kirkwood_ge00_init(&hp_t5325_ge00_data);
165 kirkwood_sata_init(&hp_t5325_sata_data);
166 kirkwood_ehci_init();
167 platform_device_register(&hp_t5325_button_device);
168
169 if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
170 gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
171 pm_power_off = hp_t5325_power_off;
172 else
173 pr_err("t5325: failed to configure power-off GPIO\n");
174}
175
176static int __init hp_t5325_pci_init(void)
177{
178 if (machine_is_t5325())
179 kirkwood_pcie_init(KW_PCIE0);
180
181 return 0;
182}
183subsys_initcall(hp_t5325_pci_init);
184
185MACHINE_START(T5325, "HP t5325 Thin Client")
186 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
187 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
188 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
189 .boot_params = 0x00000100,
190 .init_machine = hp_t5325_init,
191 .map_io = kirkwood_map_io,
192 .init_irq = kirkwood_init_irq,
193 .timer = &kirkwood_timer,
194MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0fe80e0..a5bd7fde04a9 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
74 MPP3_SPI_MISO, 74 MPP3_SPI_MISO,
75 MPP4_SATA1_ACTn, 75 MPP4_SATA1_ACTn,
76 MPP5_SATA0_ACTn, 76 MPP5_SATA0_ACTn,
77 MPP8_TW_SDA, 77 MPP8_TW0_SDA,
78 MPP9_TW_SCK, 78 MPP9_TW0_SCK,
79 MPP10_UART0_TXD, 79 MPP10_UART0_TXD,
80 MPP11_UART0_RXD, 80 MPP11_UART0_RXD,
81 MPP13_UART1_TXD, /* PIC controller */ 81 MPP13_UART1_TXD, /* PIC controller */
@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
83 MPP15_GPIO, /* USB Copy button */ 83 MPP15_GPIO, /* USB Copy button */
84 MPP16_GPIO, /* Reset button */ 84 MPP16_GPIO, /* Reset button */
85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
86 MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
86 0 87 0
87}; 88};
88 89
@@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void)
110 111
111static int __init ts219_pci_init(void) 112static int __init ts219_pci_init(void)
112{ 113{
113 if (machine_is_ts219()) 114 if (machine_is_ts219())
114 kirkwood_pcie_init(); 115 kirkwood_pcie_init(KW_PCIE0);
115 116
116 return 0; 117 return 0;
117} 118}
118subsys_initcall(ts219_pci_init); 119subsys_initcall(ts219_pci_init);
119 120
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d9e74b..2e14afef07a2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -2,7 +2,7 @@
2 * 2 *
3 * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup 3 * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
4 * 4 *
5 * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> 5 * Copyright (C) 2009-2010 Martin Michlmayr <tbm@cyrius.com>
6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> 6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
@@ -17,6 +17,7 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/mv643xx_eth.h> 18#include <linux/mv643xx_eth.h>
19#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
20#include <linux/gpio.h>
20#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
21#include <linux/input.h> 22#include <linux/input.h>
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
@@ -26,6 +27,8 @@
26#include "mpp.h" 27#include "mpp.h"
27#include "tsx1x-common.h" 28#include "tsx1x-common.h"
28 29
30#define QNAP_TS41X_JUMPER_JP1 45
31
29static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { 32static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
30 I2C_BOARD_INFO("s35390a", 0x30), 33 I2C_BOARD_INFO("s35390a", 0x30),
31}; 34};
@@ -78,31 +81,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
78 MPP3_SPI_MISO, 81 MPP3_SPI_MISO,
79 MPP6_SYSRST_OUTn, 82 MPP6_SYSRST_OUTn,
80 MPP7_PEX_RST_OUTn, 83 MPP7_PEX_RST_OUTn,
81 MPP8_TW_SDA, 84 MPP8_TW0_SDA,
82 MPP9_TW_SCK, 85 MPP9_TW0_SCK,
83 MPP10_UART0_TXD, 86 MPP10_UART0_TXD,
84 MPP11_UART0_RXD, 87 MPP11_UART0_RXD,
85 MPP13_UART1_TXD, /* PIC controller */ 88 MPP13_UART1_TXD, /* PIC controller */
86 MPP14_UART1_RXD, /* PIC controller */ 89 MPP14_UART1_RXD, /* PIC controller */
87 MPP15_SATA0_ACTn, 90 MPP15_SATA0_ACTn,
88 MPP16_SATA1_ACTn, 91 MPP16_SATA1_ACTn,
89 MPP20_GE1_0, 92 MPP20_GE1_TXD0,
90 MPP21_GE1_1, 93 MPP21_GE1_TXD1,
91 MPP22_GE1_2, 94 MPP22_GE1_TXD2,
92 MPP23_GE1_3, 95 MPP23_GE1_TXD3,
93 MPP24_GE1_4, 96 MPP24_GE1_RXD0,
94 MPP25_GE1_5, 97 MPP25_GE1_RXD1,
95 MPP26_GE1_6, 98 MPP26_GE1_RXD2,
96 MPP27_GE1_7, 99 MPP27_GE1_RXD3,
97 MPP30_GE1_10, 100 MPP30_GE1_RXCTL,
98 MPP31_GE1_11, 101 MPP31_GE1_RXCLK,
99 MPP32_GE1_12, 102 MPP32_GE1_TCLKOUT,
100 MPP33_GE1_13, 103 MPP33_GE1_TXCTL,
101 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 104 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
102 MPP37_GPIO, /* Reset button */ 105 MPP37_GPIO, /* Reset button */
103 MPP43_GPIO, /* USB Copy button */ 106 MPP43_GPIO, /* USB Copy button */
104 MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */ 107 MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */
105 MPP45_GPIO, /* JP1: 0: console, 1: LCD */ 108 MPP45_GPIO, /* JP1: 0: LCD, 1: serial console */
106 MPP46_GPIO, /* External SATA HDD1 error indicator */ 109 MPP46_GPIO, /* External SATA HDD1 error indicator */
107 MPP47_GPIO, /* External SATA HDD2 error indicator */ 110 MPP47_GPIO, /* External SATA HDD2 error indicator */
108 MPP48_GPIO, /* External SATA HDD3 error indicator */ 111 MPP48_GPIO, /* External SATA HDD3 error indicator */
@@ -131,12 +134,14 @@ static void __init qnap_ts41x_init(void)
131 134
132 pm_power_off = qnap_tsx1x_power_off; 135 pm_power_off = qnap_tsx1x_power_off;
133 136
137 if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0)
138 gpio_export(QNAP_TS41X_JUMPER_JP1, 0);
134} 139}
135 140
136static int __init ts41x_pci_init(void) 141static int __init ts41x_pci_init(void)
137{ 142{
138 if (machine_is_ts41x()) 143 if (machine_is_ts41x())
139 kirkwood_pcie_init(); 144 kirkwood_pcie_init(KW_PCIE0);
140 145
141 return 0; 146 return 0;
142} 147}
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index 78499667eb7b..5fcd082a17f9 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -268,8 +268,8 @@ static void __init ks8695_pci_preinit(void)
268 __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC); 268 __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC);
269 269
270 /* hook in fault handlers */ 270 /* hook in fault handlers */
271 hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); 271 hook_fault_code(8, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
272 hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch"); 272 hook_fault_code(10, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
273} 273}
274 274
275static void ks8695_show_pciregs(void) 275static void ks8695_show_pciregs(void)
diff --git a/arch/arm/mach-l7200/Makefile b/arch/arm/mach-l7200/Makefile
deleted file mode 100644
index 4bd8ebd70e7b..000000000000
--- a/arch/arm/mach-l7200/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := core.o
8obj-m :=
9obj-n :=
10obj- :=
11
diff --git a/arch/arm/mach-l7200/Makefile.boot b/arch/arm/mach-l7200/Makefile.boot
deleted file mode 100644
index 6c72ecbe6b64..000000000000
--- a/arch/arm/mach-l7200/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0xf0008000
2
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
deleted file mode 100644
index 50d23246d4f0..000000000000
--- a/arch/arm/mach-l7200/core.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * linux/arch/arm/mm/mm-lusl7200.c
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Extra MM routines for L7200 architecture
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/irq.h>
11#include <linux/device.h>
12
13#include <asm/types.h>
14#include <asm/irq.h>
15#include <asm/mach-types.h>
16#include <mach/hardware.h>
17#include <asm/page.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/mach/irq.h>
22
23/*
24 * IRQ base register
25 */
26#define IRQ_BASE (IO_BASE_2 + 0x1000)
27
28/*
29 * Normal IRQ registers
30 */
31#define IRQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x000))
32#define IRQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x004))
33#define IRQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x008))
34#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c))
35#define IRQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x010))
36#define IRQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x018))
37
38/*
39 * Fast IRQ registers
40 */
41#define FIQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x100))
42#define FIQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x104))
43#define FIQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x108))
44#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c))
45#define FIQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x110))
46#define FIQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x118))
47
48static void l7200_mask_irq(unsigned int irq)
49{
50 IRQ_ENABLECLEAR = 1 << irq;
51}
52
53static void l7200_unmask_irq(unsigned int irq)
54{
55 IRQ_ENABLE = 1 << irq;
56}
57
58static struct irq_chip l7200_irq_chip = {
59 .ack = l7200_mask_irq,
60 .mask = l7200_mask_irq,
61 .unmask = l7200_unmask_irq
62};
63
64static void __init l7200_init_irq(void)
65{
66 int irq;
67
68 IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */
69 FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */
70
71 for (irq = 0; irq < NR_IRQS; irq++) {
72 set_irq_chip(irq, &l7200_irq_chip);
73 set_irq_flags(irq, IRQF_VALID);
74 set_irq_handler(irq, handle_level_irq);
75 }
76
77 init_FIQ();
78}
79
80static struct map_desc l7200_io_desc[] __initdata = {
81 { IO_BASE, IO_START, IO_SIZE, MT_DEVICE },
82 { IO_BASE_2, IO_START_2, IO_SIZE_2, MT_DEVICE },
83 { AUX_BASE, AUX_START, AUX_SIZE, MT_DEVICE },
84 { FLASH1_BASE, FLASH1_START, FLASH1_SIZE, MT_DEVICE },
85 { FLASH2_BASE, FLASH2_START, FLASH2_SIZE, MT_DEVICE }
86};
87
88static void __init l7200_map_io(void)
89{
90 iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc));
91}
92
93MACHINE_START(L7200, "LinkUp Systems L7200")
94 /* Maintainer: Steve Hill / Scott McConnell */
95 .phys_io = 0x80040000,
96 .io_pg_offst = ((0xd0000000) >> 18) & 0xfffc,
97 .map_io = l7200_map_io,
98 .init_irq = l7200_init_irq,
99MACHINE_END
100
diff --git a/arch/arm/mach-l7200/include/mach/aux_reg.h b/arch/arm/mach-l7200/include/mach/aux_reg.h
deleted file mode 100644
index 4671558cdd51..000000000000
--- a/arch/arm/mach-l7200/include/mach/aux_reg.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/aux_reg.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 08-02-2000 SJH Created file
8 */
9#ifndef _ASM_ARCH_AUXREG_H
10#define _ASM_ARCH_AUXREG_H
11
12#include <mach/hardware.h>
13
14#define l7200aux_reg *((volatile unsigned int *) (AUX_BASE))
15
16/*
17 * Auxillary register values
18 */
19#define AUX_CLEAR 0x00000000
20#define AUX_DIAG_LED_ON 0x00000002
21#define AUX_RTS_UART1 0x00000004
22#define AUX_DTR_UART1 0x00000008
23#define AUX_KBD_COLUMN_12_HIGH 0x00000010
24#define AUX_KBD_COLUMN_12_OFF 0x00000020
25#define AUX_KBD_COLUMN_13_HIGH 0x00000040
26#define AUX_KBD_COLUMN_13_OFF 0x00000080
27
28#endif
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
deleted file mode 100644
index b69ed344c7c9..000000000000
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
1/* arch/arm/mach-l7200/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .equ io_virt, IO_BASE
15 .equ io_phys, IO_START
16
17 .macro addruart, rx, tmp
18 mrc p15, 0, \rx, c1, c0
19 tst \rx, #1 @ MMU enabled?
20 moveq \rx, #io_phys @ physical base address
21 movne \rx, #io_virt @ virtual address
22 add \rx, \rx, #0x00044000 @ UART1
23@ add \rx, \rx, #0x00045000 @ UART2
24 .endm
25
26 .macro senduart,rd,rx
27 str \rd, [\rx, #0x0] @ UARTDR
28 .endm
29
30 .macro waituart,rd,rx
311001: ldr \rd, [\rx, #0x18] @ UARTFLG
32 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
33 bne 1001b
34 .endm
35
36 .macro busyuart,rd,rx
371001: ldr \rd, [\rx, #0x18] @ UARTFLG
38 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
39 bne 1001b
40 .endm
diff --git a/arch/arm/mach-l7200/include/mach/entry-macro.S b/arch/arm/mach-l7200/include/mach/entry-macro.S
deleted file mode 100644
index 1726d91fc1d3..000000000000
--- a/arch/arm/mach-l7200/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for L7200-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/hardware.h>
11
12 .equ irq_base_addr, IO_BASE_2
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
25 add \irqstat, \irqstat, #0x00001000 @ Status reg
26 ldr \irqstat, [\irqstat, #0] @ get interrupts
27 mov \irqnr, #0
281001: tst \irqstat, #1
29 addeq \irqnr, \irqnr, #1
30 moveq \irqstat, \irqstat, lsr #1
31 tsteq \irqnr, #32
32 beq 1001b
33 teq \irqnr, #32
34 .endm
35
diff --git a/arch/arm/mach-l7200/include/mach/gp_timers.h b/arch/arm/mach-l7200/include/mach/gp_timers.h
deleted file mode 100644
index 2b7086a26b81..000000000000
--- a/arch/arm/mach-l7200/include/mach/gp_timers.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/gp_timers.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 07-28-2000 SJH Created file
8 * 08-02-2000 SJH Used structure for registers
9 */
10#ifndef _ASM_ARCH_GPTIMERS_H
11#define _ASM_ARCH_GPTIMERS_H
12
13#include <mach/hardware.h>
14
15/*
16 * Layout of L7200 general purpose timer registers
17 */
18struct GPT_Regs {
19 unsigned int TIMERLOAD;
20 unsigned int TIMERVALUE;
21 unsigned int TIMERCONTROL;
22 unsigned int TIMERCLEAR;
23};
24
25#define GPT_BASE (IO_BASE_2 + 0x3000)
26#define l7200_timer1_regs ((volatile struct GPT_Regs *) (GPT_BASE))
27#define l7200_timer2_regs ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
28
29/*
30 * General register values
31 */
32#define GPT_PRESCALE_1 0x00000000
33#define GPT_PRESCALE_16 0x00000004
34#define GPT_PRESCALE_256 0x00000008
35#define GPT_MODE_FREERUN 0x00000000
36#define GPT_MODE_PERIODIC 0x00000040
37#define GPT_ENABLE 0x00000080
38#define GPT_BZTOG 0x00000100
39#define GPT_BZMOD 0x00000200
40#define GPT_LOAD_MASK 0x0000ffff
41
42#endif
diff --git a/arch/arm/mach-l7200/include/mach/gpio.h b/arch/arm/mach-l7200/include/mach/gpio.h
deleted file mode 100644
index c7b0a5d7b8bb..000000000000
--- a/arch/arm/mach-l7200/include/mach/gpio.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/gpio.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * GPIO.
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define GPIO_OFF 0x00005000 /* Offset from IO_START to the GPIO reg's. */
18
19/* IO_START and IO_BASE are defined in hardware.h */
20
21#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
22#define GPIO_BASE (IO_BASE_2 + GPIO_OFF) /* Virtual addr of the GPIO reg. */
23
24/* Offsets from the start of the GPIO for all the registers. */
25#define PADR_OFF 0x000
26#define PADDR_OFF 0x004
27#define PASBSR_OFF 0x008
28#define PAEENR_OFF 0x00c
29#define PAESNR_OFF 0x010
30#define PAESTR_OFF 0x014
31#define PAIMR_OFF 0x018
32#define PAINT_OFF 0x01c
33
34#define PBDR_OFF 0x020
35#define PBDDR_OFF 0x024
36#define PBSBSR_OFF 0x028
37#define PBIMR_OFF 0x038
38#define PBINT_OFF 0x03c
39
40#define PCDR_OFF 0x040
41#define PCDDR_OFF 0x044
42#define PCSBSR_OFF 0x048
43#define PCIMR_OFF 0x058
44#define PCINT_OFF 0x05c
45
46#define PDDR_OFF 0x060
47#define PDDDR_OFF 0x064
48#define PDSBSR_OFF 0x068
49#define PDEENR_OFF 0x06c
50#define PDESNR_OFF 0x070
51#define PDESTR_OFF 0x074
52#define PDIMR_OFF 0x078
53#define PDINT_OFF 0x07c
54
55#define PEDR_OFF 0x080
56#define PEDDR_OFF 0x084
57#define PESBSR_OFF 0x088
58#define PEEENR_OFF 0x08c
59#define PEESNR_OFF 0x090
60#define PEESTR_OFF 0x094
61#define PEIMR_OFF 0x098
62#define PEINT_OFF 0x09c
63
64/* Define the GPIO registers for use by device drivers and the kernel. */
65#define PADR (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
66#define PADDR (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
67#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
68#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
69#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
70#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
71#define PAIMR (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
72#define PAINT (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
73
74#define PBDR (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
75#define PBDDR (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
76#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
77#define PBIMR (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
78#define PBINT (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
79
80#define PCDR (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
81#define PCDDR (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
82#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
83#define PCIMR (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
84#define PCINT (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
85
86#define PDDR (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
87#define PDDDR (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
88#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
89#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
90#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
91#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
92#define PDIMR (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
93#define PDINT (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
94
95#define PEDR (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
96#define PEDDR (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
97#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
98#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
99#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
100#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
101#define PEIMR (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
102#define PEINT (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
103
104#define VEE_EN 0x02
105#define BACKLIGHT_EN 0x04
diff --git a/arch/arm/mach-l7200/include/mach/hardware.h b/arch/arm/mach-l7200/include/mach/hardware.h
deleted file mode 100644
index c31909cfc254..000000000000
--- a/arch/arm/mach-l7200/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/hardware.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * This file contains the hardware definitions for the
8 * LinkUp Systems L7200 SOC development board.
9 *
10 * Changelog:
11 * 02-01-2000 RS Created L7200 version, derived from rpc code
12 * 03-21-2000 SJH Cleaned up file
13 * 04-21-2000 RS Changed mapping of I/O in virtual space
14 * 04-25-2000 SJH Removed unused symbols and such
15 * 05-05-2000 SJH Complete rewrite
16 * 07-31-2000 SJH Added undocumented debug auxillary port to
17 * get at last two columns for keyboard driver
18 */
19#ifndef __ASM_ARCH_HARDWARE_H
20#define __ASM_ARCH_HARDWARE_H
21
22/* Hardware addresses of major areas.
23 * *_START is the physical address
24 * *_SIZE is the size of the region
25 * *_BASE is the virtual address
26 */
27#define RAM_START 0xf0000000
28#define RAM_SIZE 0x02000000
29#define RAM_BASE 0xc0000000
30
31#define IO_START 0x80000000 /* I/O */
32#define IO_SIZE 0x01000000
33#define IO_BASE 0xd0000000
34
35#define IO_START_2 0x90000000 /* I/O */
36#define IO_SIZE_2 0x01000000
37#define IO_BASE_2 0xd1000000
38
39#define AUX_START 0x1a000000 /* AUX PORT */
40#define AUX_SIZE 0x01000000
41#define AUX_BASE 0xd2000000
42
43#define FLASH1_START 0x00000000 /* FLASH BANK 1 */
44#define FLASH1_SIZE 0x01000000
45#define FLASH1_BASE 0xd3000000
46
47#define FLASH2_START 0x10000000 /* FLASH BANK 2 */
48#define FLASH2_SIZE 0x01000000
49#define FLASH2_BASE 0xd4000000
50
51#define ISA_START 0x20000000 /* ISA */
52#define ISA_SIZE 0x20000000
53#define ISA_BASE 0xe0000000
54
55#define PCIO_BASE IO_BASE
56
57#endif
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
deleted file mode 100644
index a770a89fb708..000000000000
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/io.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 03-21-2000 SJH Created from arch/arm/mach-nexuspci/include/mach/io.h
8 * 08-31-2000 SJH Added in IO functions necessary for new drivers
9 */
10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H
12
13#define IO_SPACE_LIMIT 0xffffffff
14
15/*
16 * There are not real ISA nor PCI buses, so we fake it.
17 */
18#define __io(a) __typesafe_io(a)
19#define __mem_pci(a) (a)
20
21#endif
diff --git a/arch/arm/mach-l7200/include/mach/irqs.h b/arch/arm/mach-l7200/include/mach/irqs.h
deleted file mode 100644
index 7edffd713c5b..000000000000
--- a/arch/arm/mach-l7200/include/mach/irqs.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/irqs.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * Changelog:
8 * 01-02-2000 RS Create l7200 version
9 * 03-28-2000 SJH Removed unused interrupt
10 * 07-28-2000 SJH Added pseudo-keyboard interrupt
11 */
12
13/*
14 * NOTE: The second timer (Timer 2) is used as the keyboard
15 * interrupt when the keyboard driver is enabled.
16 */
17
18#define NR_IRQS 32
19
20#define IRQ_STWDOG 0 /* Watchdog timer */
21#define IRQ_PROG 1 /* Programmable interrupt */
22#define IRQ_DEBUG_RX 2 /* Comm Rx debug */
23#define IRQ_DEBUG_TX 3 /* Comm Tx debug */
24#define IRQ_GCTC1 4 /* Timer 1 */
25#define IRQ_GCTC2 5 /* Timer 2 / Keyboard */
26#define IRQ_DMA 6 /* DMA controller */
27#define IRQ_CLCD 7 /* Color LCD controller */
28#define IRQ_SM_RX 8 /* Smart card */
29#define IRQ_SM_TX 9 /* Smart cart */
30#define IRQ_SM_RST 10 /* Smart card */
31#define IRQ_SIB 11 /* Serial Interface Bus */
32#define IRQ_MMC 12 /* MultiMediaCard */
33#define IRQ_SSP1 13 /* Synchronous Serial Port 1 */
34#define IRQ_SSP2 14 /* Synchronous Serial Port 1 */
35#define IRQ_SPI 15 /* SPI slave */
36#define IRQ_UART_1 16 /* UART 1 */
37#define IRQ_UART_2 17 /* UART 2 */
38#define IRQ_IRDA 18 /* IRDA */
39#define IRQ_RTC_TICK 19 /* Real Time Clock tick */
40#define IRQ_RTC_ALARM 20 /* Real Time Clock alarm */
41#define IRQ_GPIO 21 /* General Purpose IO */
42#define IRQ_GPIO_DMA 22 /* General Purpose IO, DMA */
43#define IRQ_M2M 23 /* Memory to memory DMA */
44#define IRQ_RESERVED 24 /* RESERVED, don't use */
45#define IRQ_INTF 25 /* External active low interrupt */
46#define IRQ_INT0 26 /* External active low interrupt */
47#define IRQ_INT1 27 /* External active low interrupt */
48#define IRQ_INT2 28 /* External active low interrupt */
49#define IRQ_UCB1200 29 /* Interrupt generated by UCB1200*/
50#define IRQ_BAT_LO 30 /* Low batery or external power */
51#define IRQ_MEDIA_CHG 31 /* Media change interrupt */
52
53/*
54 * This is the offset of the FIQ "IRQ" numbers
55 */
56#define FIQ_START 64
diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h
deleted file mode 100644
index 9fb40ed2f03b..000000000000
--- a/arch/arm/mach-l7200/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/memory.h
3 *
4 * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
5 * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
6 *
7 * Changelog:
8 * 03-13-2000 SJH Created
9 * 04-13-2000 RS Changed bus macros for new addr
10 * 05-03-2000 SJH Removed bus macros and fixed virt_to_phys macro
11 */
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15/*
16 * Physical DRAM offset on the L7200 SDB.
17 */
18#define PHYS_OFFSET UL(0xf0000000)
19
20/*
21 * Cache flushing area - ROM
22 */
23#define FLUSH_BASE_PHYS 0x40000000
24#define FLUSH_BASE 0xdf000000
25
26#endif
diff --git a/arch/arm/mach-l7200/include/mach/pmpcon.h b/arch/arm/mach-l7200/include/mach/pmpcon.h
deleted file mode 100644
index 3959871e8361..000000000000
--- a/arch/arm/mach-l7200/include/mach/pmpcon.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/pmpcon.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * DC/DC converter register.
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define PMPCON_OFF 0x00006000 /* Offset from IO_START_2. */
18
19/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
20
21#define PMPCON_START (IO_START_2 + PMPCON_OFF) /* Physical address of reg. */
22#define PMPCON_BASE (IO_BASE_2 + PMPCON_OFF) /* Virtual address of reg. */
23
24
25#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
26
27#define PWM2_50CYCLE 0x800
28#define CONTRAST 0x9
29
30#define PWM1H (CONTRAST)
31#define PWM1L (CONTRAST << 4)
32
33#define PMPCON_VALUE (PWM2_50CYCLE | PWM1L | PWM1H)
34
35/* PMPCON = 0x811; // too light and fuzzy
36 * PMPCON = 0x844;
37 * PMPCON = 0x866; // better color poor depth
38 * PMPCON = 0x888; // Darker but better depth
39 * PMPCON = 0x899; // Darker even better depth
40 * PMPCON = 0x8aa; // too dark even better depth
41 * PMPCON = 0X8cc; // Way too dark
42 */
43
44/* As CONTRAST value increases the greater the depth perception and
45 * the darker the colors.
46 */
diff --git a/arch/arm/mach-l7200/include/mach/pmu.h b/arch/arm/mach-l7200/include/mach/pmu.h
deleted file mode 100644
index a2da7aedf208..000000000000
--- a/arch/arm/mach-l7200/include/mach/pmu.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/pmu.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * Power Management Unit (PMU).
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */
18
19/* IO_START and IO_BASE are defined in hardware.h */
20
21#define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */
22#define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */
23
24
25/* Define the PMU registers for use by device drivers and the kernel. */
26
27typedef struct {
28 unsigned int CURRENT; /* Current configuration register */
29 unsigned int NEXT; /* Next configuration register */
30 unsigned int reserved;
31 unsigned int RUN; /* Run configuration register */
32 unsigned int COMM; /* Configuration command register */
33 unsigned int SDRAM; /* SDRAM configuration bypass register */
34} pmu_interface;
35
36#define PMU ((volatile pmu_interface *)(PMU_BASE))
37
38
39/* Macro's for reading the common register fields. */
40
41#define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */
42#define GET_OSCEN(reg) ((reg >> 16) & 0x01)
43#define GET_OSCMUX(reg) ((reg >> 15) & 0x01)
44#define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */
45#define GET_PLLEN(reg) ((reg >> 8) & 0x01)
46#define GET_PLLMUX(reg) ((reg >> 7) & 0x01)
47#define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */
48#define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01)
49#define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01)
50#define GET_FASTBUS(reg) (reg & 0x1)
51
52/* CFG_NEXT register */
53
54#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */
55#define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01)
56#define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01)
57#define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01)
58
59/* Useful field values that can be used to construct the
60 * CFG_NEXT and CFG_RUN registers.
61 */
62
63#define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */
64#define NOCHANGE_STALL 1<<25
65#define CHANGE_NOSTALL 2<<25
66#define CHANGE_STALL 3<<25
67
68#define INTRET 1<<17
69#define OSCEN 1<<16
70#define OSCMUX 1<<15
71
72/* PLL frequencies */
73
74#define PLLMUL_0 0<<9 /* 3.6864 MHz */
75#define PLLMUL_1 1<<9 /* ?????? MHz */
76#define PLLMUL_5 5<<9 /* 18.432 MHz */
77#define PLLMUL_10 10<<9 /* 36.864 MHz */
78#define PLLMUL_18 18<<9 /* ?????? MHz */
79#define PLLMUL_20 20<<9 /* 73.728 MHz */
80#define PLLMUL_32 32<<9 /* ?????? MHz */
81#define PLLMUL_35 35<<9 /* 129.024 MHz */
82#define PLLMUL_36 36<<9 /* ?????? MHz */
83#define PLLMUL_39 39<<9 /* ?????? MHz */
84#define PLLMUL_40 40<<9 /* 147.456 MHz */
85
86/* Clock recovery times */
87
88#define CRCLOCK_1 1<<18
89#define CRCLOCK_2 2<<18
90#define CRCLOCK_4 4<<18
91#define CRCLOCK_8 8<<18
92#define CRCLOCK_16 16<<18
93#define CRCLOCK_32 32<<18
94#define CRCLOCK_63 63<<18
95#define CRCLOCK_127 127<<18
96
97#define PLLEN 1<<8
98#define PLLMUX 1<<7
99#define SDR_STOP 1<<6
100#define SYSCLKEN 1<<5
101
102#define BCLK_DIV_4 2<<3
103#define BCLK_DIV_2 1<<3
104#define BCLK_DIV_1 0<<3
105
106#define SDRB_SEL 1<<2
107#define SDRF_SEL 1<<1
108#define FASTBUS 1<<0
109
110
111/* CFG_SDRAM */
112
113#define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */
114#define SDRREFACK 1<<1 /* Read-only */
115#define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */
116#define SDRSTOPACK 1<<3 /* Read-only */
117#define PICEN 1<<4 /* Enable Co-procesor */
118#define PICTEST 1<<5
119
120#define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01)
121#define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
122#define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01)
123#define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
124#define GET_PICEN ((PMU->SDRAM >> 4) & 0x01)
125#define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01)
diff --git a/arch/arm/mach-l7200/include/mach/serial.h b/arch/arm/mach-l7200/include/mach/serial.h
deleted file mode 100644
index adc05e5f8378..000000000000
--- a/arch/arm/mach-l7200/include/mach/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/serial.h
3 *
4 * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * Changelog:
8 * 03-20-2000 SJH Created
9 * 03-26-2000 SJH Added flags for serial ports
10 * 03-27-2000 SJH Corrected BASE_BAUD value
11 * 04-14-2000 RS Made register addr dependent on IO_BASE
12 * 05-03-2000 SJH Complete rewrite
13 * 05-09-2000 SJH Stripped out architecture specific serial stuff
14 * and placed it in a separate file
15 * 07-28-2000 SJH Moved base baud rate variable
16 */
17#ifndef __ASM_ARCH_SERIAL_H
18#define __ASM_ARCH_SERIAL_H
19
20/*
21 * This assumes you have a 3.6864 MHz clock for your UART.
22 */
23#define BASE_BAUD 3686400
24
25/*
26 * Standard COM flags
27 */
28#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
29
30#define STD_SERIAL_PORT_DEFNS \
31 /* MAGIC UART CLK PORT IRQ FLAGS */ \
32 { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS }, /* ttyLU0 */ \
33 { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS }, /* ttyLU1 */ \
34
35#define EXTRA_SERIAL_PORT_DEFNS
36
37#endif
diff --git a/arch/arm/mach-l7200/include/mach/serial_l7200.h b/arch/arm/mach-l7200/include/mach/serial_l7200.h
deleted file mode 100644
index 645f1c5e568d..000000000000
--- a/arch/arm/mach-l7200/include/mach/serial_l7200.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/serial_l7200.h
3 *
4 * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 05-09-2000 SJH Created
8 */
9#ifndef __ASM_ARCH_SERIAL_L7200_H
10#define __ASM_ARCH_SERIAL_L7200_H
11
12#include <mach/memory.h>
13
14/*
15 * This assumes you have a 3.6864 MHz clock for your UART.
16 */
17#define BASE_BAUD 3686400
18
19/*
20 * UART base register addresses
21 */
22#define UART1_BASE (IO_BASE + 0x00044000)
23#define UART2_BASE (IO_BASE + 0x00045000)
24
25/*
26 * UART register offsets
27 */
28#define UARTDR 0x00 /* Tx/Rx data */
29#define RXSTAT 0x04 /* Rx status */
30#define H_UBRLCR 0x08 /* mode register high */
31#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/
32#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/
33#define UARTCON 0x14 /* control register */
34#define UARTFLG 0x18 /* flag register */
35#define UARTINTSTAT 0x1C /* FIFO IRQ status register */
36#define UARTINTMASK 0x20 /* FIFO IRQ mask register */
37
38/*
39 * UART baud rate register values
40 */
41#define BR_110 0x827
42#define BR_1200 0x06e
43#define BR_2400 0x05f
44#define BR_4800 0x02f
45#define BR_9600 0x017
46#define BR_14400 0x00f
47#define BR_19200 0x00b
48#define BR_38400 0x005
49#define BR_57600 0x003
50#define BR_76800 0x002
51#define BR_115200 0x001
52
53/*
54 * Receiver status register (RXSTAT) mask values
55 */
56#define RXSTAT_NO_ERR 0x00 /* No error */
57#define RXSTAT_FRM_ERR 0x01 /* Framing error */
58#define RXSTAT_PAR_ERR 0x02 /* Parity error */
59#define RXSTAT_OVR_ERR 0x04 /* Overrun error */
60
61/*
62 * High byte of UART bit rate and line control register (H_UBRLCR) values
63 */
64#define UBRLCR_BRK 0x01 /* generate break on tx */
65#define UBRLCR_PEN 0x02 /* enable parity */
66#define UBRLCR_PDIS 0x00 /* disable parity */
67#define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */
68#define UBRLCR_STP2 0x08 /* transmit 2 stop bits */
69#define UBRLCR_FIFO 0x10 /* enable FIFO */
70#define UBRLCR_LEN5 0x60 /* word length5 */
71#define UBRLCR_LEN6 0x40 /* word length6 */
72#define UBRLCR_LEN7 0x20 /* word length7 */
73#define UBRLCR_LEN8 0x00 /* word length8 */
74
75/*
76 * UART control register (UARTCON) values
77 */
78#define UARTCON_UARTEN 0x01 /* Enable UART */
79#define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */
80
81/*
82 * UART flag register (UARTFLG) mask values
83 */
84#define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */
85#define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */
86#define UARTFLG_UBUSY 0x08 /* Transmitter busy */
87#define UARTFLG_DCD 0x04 /* Data carrier detect */
88#define UARTFLG_DSR 0x02 /* Data set ready */
89#define UARTFLG_CTS 0x01 /* Clear to send */
90
91/*
92 * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
93 */
94#define UART_TXINT 0x01 /* TX interrupt */
95#define UART_RXINT 0x02 /* RX interrupt */
96#define UART_RXERRINT 0x04 /* RX error interrupt */
97#define UART_MSINT 0x08 /* Modem Status interrupt */
98#define UART_UDINT 0x10 /* UART Disabled interrupt */
99#define UART_ALLIRQS 0x1f /* All interrupts */
100
101#endif
diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h
deleted file mode 100644
index 965728712cf3..000000000000
--- a/arch/arm/mach-l7200/include/mach/sib.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/sib.h
4 *
5 * Registers and helper functions for the Serial Interface Bus.
6 *
7 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14/****************************************************************************/
15
16#define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */
17
18/* IO_START and IO_BASE are defined in hardware.h */
19
20#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
21#define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */
22
23/* Offsets from the start of the SIB for all the registers. */
24
25/* Define the SIB registers for use by device drivers and the kernel. */
26
27typedef struct
28{
29 unsigned int MCCR; /* SIB Control Register Offset: 0x00 */
30 unsigned int RES1; /* Reserved Offset: 0x04 */
31 unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */
32 unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */
33 unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */
34 unsigned int RES2; /* Reserved Offset: 0x14 */
35 unsigned int MCSR; /* SIB Status Register Offset: 0x18 */
36} SIB_Interface;
37
38#define SIB ((volatile SIB_Interface *) (SIB_BASE))
39
40/* MCCR */
41
42#define INTERNAL_FREQ 9216000 /* Hertz */
43#define AUDIO_FREQ 5000 /* Hertz */
44#define TELECOM_FREQ 5000 /* Hertz */
45
46#define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ))
47#define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ))
48
49#define MCCR_ASD57 AUDIO_DIVIDE
50#define MCCR_TSD57 (TELECOM_DIVIDE << 8)
51#define MCCR_MCE (1 << 16) /* SIB enable */
52#define MCCR_ECS (1 << 17) /* External Clock Select */
53#define MCCR_ADM (1 << 18) /* A/D Data Sampling */
54#define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */
55
56
57#define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */
58#define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */
59#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
60#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
61#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
62#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */
63#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
64#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */
65#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
66#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
67#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
68#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
69#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
70#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
71
72/* MCDR0 */
73
74#define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff)
75#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
76
77/* MCDR1 */
78
79#define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff)
80#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
81
82
83/* MCSR */
84
85#define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */
86#define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */
87#define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */
88#define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */
89
90#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
91
92
93#define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/
94#define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/
95#define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */
96#define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */
97#define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */
98#define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */
99#define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */
100#define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */
101#define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */
102#define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */
103#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
104#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
105#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
106#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
107#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
108#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
109
110/* MCDR2 */
111
112#define MCDR2_rW (1 << 16)
113
114#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
115#define MCDR2_WRITE_COMPLETE GET_CWC
116
117#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
118#define MCDR2_READ_COMPLETE GET_CRC
119#define MCDR2_READ (SIB->MCDR2 & 0xffff)
diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h
deleted file mode 100644
index e9729a35751d..000000000000
--- a/arch/arm/mach-l7200/include/mach/sys-clock.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/sys-clock.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * System clocks.
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define SYS_CLOCK_OFF 0x00050030 /* Offset from IO_START. */
18
19/* IO_START and IO_BASE are defined in hardware.h */
20
21#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF) /* Physical address */
22#define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */
23
24/* Define the interface to the SYS_CLOCK */
25
26typedef struct
27{
28 unsigned int ENABLE;
29 unsigned int ESYNC;
30 unsigned int SELECT;
31} sys_clock_interface;
32
33#define SYS_CLOCK ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
34
35//#define CLOCK_EN (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
36//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
37//#define CLOCK_SEL (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
38
39/* SYS_CLOCK -> ENABLE */
40
41#define SYN_EN 1<<0
42#define B18M_EN 1<<1
43#define CLK3M6_EN 1<<2
44#define BUART_EN 1<<3
45#define CLK18MU_EN 1<<4
46#define FIR_EN 1<<5
47#define MIRN_EN 1<<6
48#define UARTM_EN 1<<7
49#define SIBADC_EN 1<<8
50#define ALTD_EN 1<<9
51#define CLCLK_EN 1<<10
52
53/* SYS_CLOCK -> SELECT */
54
55#define CLK18M_DIV 1<<0
56#define MIR_SEL 1<<1
57#define SSP_SEL 1<<4
58#define MM_DIV 1<<5
59#define MM_SEL 1<<6
60#define ADC_SEL_2 0<<7
61#define ADC_SEL_4 1<<7
62#define ADC_SEL_8 3<<7
63#define ADC_SEL_16 7<<7
64#define ADC_SEL_32 0x0f<<7
65#define ADC_SEL_64 0x1f<<7
66#define ADC_SEL_128 0x3f<<7
67#define ALTD_SEL 1<<13
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h
deleted file mode 100644
index e0dd3b6ae4aa..000000000000
--- a/arch/arm/mach-l7200/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/system.h
3 *
4 * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog
7 * 03-21-2000 SJH Created
8 * 04-26-2000 SJH Fixed functions
9 * 05-03-2000 SJH Removed usage of obsolete 'iomd.h'
10 * 05-31-2000 SJH Properly implemented 'arch_idle'
11 */
12#ifndef __ASM_ARCH_SYSTEM_H
13#define __ASM_ARCH_SYSTEM_H
14
15#include <mach/hardware.h>
16
17static inline void arch_idle(void)
18{
19 *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */
20}
21
22static inline void arch_reset(char mode, const char *cmd)
23{
24 if (mode == 's') {
25 cpu_reset(0);
26 }
27}
28
29#endif
diff --git a/arch/arm/mach-l7200/include/mach/time.h b/arch/arm/mach-l7200/include/mach/time.h
deleted file mode 100644
index 061771c2c2bd..000000000000
--- a/arch/arm/mach-l7200/include/mach/time.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/time.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * Changelog:
8 * 01-02-2000 RS Created l7200 version, derived from rpc code
9 * 05-03-2000 SJH Complete rewrite
10 */
11#ifndef _ASM_ARCH_TIME_H
12#define _ASM_ARCH_TIME_H
13
14#include <mach/irqs.h>
15
16/*
17 * RTC base register address
18 */
19#define RTC_BASE (IO_BASE_2 + 0x2000)
20
21/*
22 * RTC registers
23 */
24#define RTC_RTCDR (*(volatile unsigned char *) (RTC_BASE + 0x000))
25#define RTC_RTCMR (*(volatile unsigned char *) (RTC_BASE + 0x004))
26#define RTC_RTCS (*(volatile unsigned char *) (RTC_BASE + 0x008))
27#define RTC_RTCC (*(volatile unsigned char *) (RTC_BASE + 0x008))
28#define RTC_RTCDV (*(volatile unsigned char *) (RTC_BASE + 0x00c))
29#define RTC_RTCCR (*(volatile unsigned char *) (RTC_BASE + 0x010))
30
31/*
32 * RTCCR register values
33 */
34#define RTC_RATE_32 0x00 /* 32 Hz tick */
35#define RTC_RATE_64 0x10 /* 64 Hz tick */
36#define RTC_RATE_128 0x20 /* 128 Hz tick */
37#define RTC_RATE_256 0x30 /* 256 Hz tick */
38#define RTC_EN_ALARM 0x01 /* Enable alarm */
39#define RTC_EN_TIC 0x04 /* Enable counter */
40#define RTC_EN_STWDOG 0x08 /* Enable watchdog */
41
42/*
43 * Handler for RTC timer interrupt
44 */
45static irqreturn_t
46timer_interrupt(int irq, void *dev_id)
47{
48 struct pt_regs *regs = get_irq_regs();
49 do_timer(1);
50#ifndef CONFIG_SMP
51 update_process_times(user_mode(regs));
52#endif
53 do_profile(regs);
54 RTC_RTCC = 0; /* Clear interrupt */
55
56 return IRQ_HANDLED;
57}
58
59/*
60 * Set up RTC timer interrupt, and return the current time in seconds.
61 */
62void __init time_init(void)
63{
64 RTC_RTCC = 0; /* Clear interrupt */
65
66 timer_irq.handler = timer_interrupt;
67
68 setup_irq(IRQ_RTC_TICK, &timer_irq);
69
70 RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC; /* Set rate and enable timer */
71}
72
73#endif
diff --git a/arch/arm/mach-l7200/include/mach/timex.h b/arch/arm/mach-l7200/include/mach/timex.h
deleted file mode 100644
index ffc96a63b5a2..000000000000
--- a/arch/arm/mach-l7200/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/timex.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * 04-21-2000 RS Created file
8 * 05-03-2000 SJH Tick rate was wrong
9 *
10 */
11
12/*
13 * On the ARM720T, clock ticks are set to 128 Hz.
14 *
15 * NOTE: The actual RTC value is set in 'time.h' which
16 * must be changed when choosing a different tick
17 * rate. The value of HZ in 'param.h' must also
18 * be changed to match below.
19 */
20#define CLOCK_TICK_RATE 128
diff --git a/arch/arm/mach-l7200/include/mach/uncompress.h b/arch/arm/mach-l7200/include/mach/uncompress.h
deleted file mode 100644
index 591c962bb315..000000000000
--- a/arch/arm/mach-l7200/include/mach/uncompress.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/uncompress.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 05-01-2000 SJH Created
8 * 05-13-2000 SJH Filled in function bodies
9 * 07-26-2000 SJH Removed hard coded baud rate
10 */
11
12#include <mach/hardware.h>
13
14#define IO_UART IO_START + 0x00044000
15
16#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v))
17#define __raw_readb(p) (*(volatile unsigned char *)(p))
18
19static inline void putc(int c)
20{
21 while(__raw_readb(IO_UART + 0x18) & 0x20 ||
22 __raw_readb(IO_UART + 0x18) & 0x08)
23 barrier();
24
25 __raw_writeb(c, IO_UART + 0x00);
26}
27
28static inline void flush(void)
29{
30}
31
32static __inline__ void arch_decomp_setup(void)
33{
34 __raw_writeb(0x00, IO_UART + 0x08); /* Set HSB */
35 __raw_writeb(0x00, IO_UART + 0x20); /* Disable IRQs */
36 __raw_writeb(0x01, IO_UART + 0x14); /* Enable UART */
37}
38
39#define arch_decomp_wdog()
diff --git a/arch/arm/mach-l7200/include/mach/vmalloc.h b/arch/arm/mach-l7200/include/mach/vmalloc.h
deleted file mode 100644
index 85f0abbf15f1..000000000000
--- a/arch/arm/mach-l7200/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/vmalloc.h
3 */
4#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
index 189d20e543e7..edb8f5faf5d5 100644
--- a/arch/arm/mach-lh7a40x/include/mach/memory.h
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -19,50 +19,6 @@
19 */ 19 */
20#define PHYS_OFFSET UL(0xc0000000) 20#define PHYS_OFFSET UL(0xc0000000)
21 21
22#ifdef CONFIG_DISCONTIGMEM
23
24/*
25 * Given a kernel address, find the home node of the underlying memory.
26 */
27
28# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
29# define KVADDR_TO_NID(addr) \
30 ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\
31 | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
32# else /* 2 banks per node */
33# define KVADDR_TO_NID(addr) \
34 (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
35# endif
36
37/*
38 * Given a page frame number, convert it to a node id.
39 */
40
41# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
42# define PFN_TO_NID(pfn) \
43 (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\
44 | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
45# else /* 2 banks per node */
46# define PFN_TO_NID(pfn) \
47 (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
48#endif
49
50/*
51 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
52 * and returns the index corresponding to the appropriate page in the
53 * node's mem_map.
54 */
55
56# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
57# define LOCAL_MAP_NR(addr) \
58 (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
59# else /* 2 banks per node */
60# define LOCAL_MAP_NR(addr) \
61 (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
62# endif
63
64#endif
65
66/* 22/*
67 * Sparsemem version of the above 23 * Sparsemem version of the above
68 */ 24 */
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
new file mode 100644
index 000000000000..fde663508696
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -0,0 +1,33 @@
1if ARCH_LPC32XX
2
3menu "Individual UART enable selections"
4
5config ARCH_LPC32XX_UART3_SELECT
6 bool "Add support for standard UART3"
7 help
8 Adds support for standard UART 3 when the 8250 serial support
9 is enabled.
10
11config ARCH_LPC32XX_UART4_SELECT
12 bool "Add support for standard UART4"
13 help
14 Adds support for standard UART 4 when the 8250 serial support
15 is enabled.
16
17config ARCH_LPC32XX_UART5_SELECT
18 bool "Add support for standard UART5"
19 default y
20 help
21 Adds support for standard UART 5 when the 8250 serial support
22 is enabled.
23
24config ARCH_LPC32XX_UART6_SELECT
25 bool "Add support for standard UART6"
26 help
27 Adds support for standard UART 6 when the 8250 serial support
28 is enabled.
29
30endmenu
31
32endif
33
diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
new file mode 100644
index 000000000000..a5fc5d0eeaeb
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := timer.o irq.o common.o serial.o clock.o
6obj-y += gpiolib.o pm.o suspend.o
7obj-y += phy3250.o
8
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
new file mode 100644
index 000000000000..b796b41ebf8f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -0,0 +1,4 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x82000000
4
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
new file mode 100644
index 000000000000..32d63796430a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -0,0 +1,1137 @@
1/*
2 * arch/arm/mach-lpc32xx/clock.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19/*
20 * LPC32xx clock management driver overview
21 *
22 * The LPC32XX contains a number of high level system clocks that can be
23 * generated from different sources. These system clocks are used to
24 * generate the CPU and bus rates and the individual peripheral clocks in
25 * the system. When Linux is started by the boot loader, the system
26 * clocks are already running. Stopping a system clock during normal
27 * Linux operation should never be attempted, as peripherals that require
28 * those clocks will quit working (ie, DRAM).
29 *
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
31 * an asterisk are always on and cannot be disabled. Clocks marked with
32 * an ampersand can only be disabled in CPU suspend mode. Clocks marked
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
35 * disabled normally.
36 * 32KHz oscillator*
37 * / | \
38 * RTC* PLL397^ TOUCH
39 * /
40 * Main oscillator^ /
41 * | \ /
42 * | SYSCLK&
43 * | \
44 * | \
45 * USB_PLL HCLK_PLL&
46 * | | |
47 * USB host/device PCLK& |
48 * | |
49 * Peripherals
50 *
51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
52 * generate various clock rates up to 266MHz and beyond. The internal bus
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
57 * dividers as part of the IP itself. Because of this, the system clock
58 * rates should not be changed.
59 *
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
61 * main oscillator or PLL397. PLL397 generates a rate that is 397 times
62 * the 32KHz oscillator rate. The main oscillator runs at the selected
63 * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
64 * is normally 13MHz, but depends on the selection of external crystals
65 * or oscillators. If USB operation is required, the main oscillator must
66 * be used in the system.
67 *
68 * Switching SYSCLK between sources during normal Linux operation is not
69 * supported. SYSCLK is preset in the bootloader. Because of the
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
72 * - The PLL397 and main oscillator can be enabled and disabled by the
73 * clk_enable() and clk_disable() functions unless SYSCLK is based
74 * on that clock. This allows the other oscillator that isn't driving
75 * the HCLK PLL to be used as another system clock that can be routed
76 * to an external pin.
77 * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
78 * this driver.
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
80 * - Most peripherals have their own dividers are part of the peripheral
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
82 * will also impact the individual peripheral rates.
83 */
84
85#include <linux/kernel.h>
86#include <linux/list.h>
87#include <linux/errno.h>
88#include <linux/device.h>
89#include <linux/err.h>
90#include <linux/clk.h>
91#include <linux/amba/bus.h>
92#include <linux/amba/clcd.h>
93
94#include <mach/hardware.h>
95#include <asm/clkdev.h>
96#include <mach/clkdev.h>
97#include <mach/platform.h>
98#include "clock.h"
99#include "common.h"
100
101static struct clk clk_armpll;
102static struct clk clk_usbpll;
103static DEFINE_MUTEX(clkm_lock);
104
105/*
106 * Post divider values for PLLs based on selected register value
107 */
108static const u32 pll_postdivs[4] = {1, 2, 4, 8};
109
110static unsigned long local_return_parent_rate(struct clk *clk)
111{
112 /*
113 * If a clock has a rate of 0, then it inherits it's parent
114 * clock rate
115 */
116 while (clk->rate == 0)
117 clk = clk->parent;
118
119 return clk->rate;
120}
121
122/* 32KHz clock has a fixed rate and is not stoppable */
123static struct clk osc_32KHz = {
124 .rate = LPC32XX_CLOCK_OSC_FREQ,
125 .get_rate = local_return_parent_rate,
126};
127
128static int local_pll397_enable(struct clk *clk, int enable)
129{
130 u32 reg;
131 unsigned long timeout = 1 + msecs_to_jiffies(10);
132
133 reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
134
135 if (enable == 0) {
136 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
137 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
138 } else {
139 /* Enable PLL397 */
140 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
141 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
142
143 /* Wait for PLL397 lock */
144 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
145 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
146 (timeout > jiffies))
147 cpu_relax();
148
149 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
150 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
151 return -ENODEV;
152 }
153
154 return 0;
155}
156
157static int local_oscmain_enable(struct clk *clk, int enable)
158{
159 u32 reg;
160 unsigned long timeout = 1 + msecs_to_jiffies(10);
161
162 reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
163
164 if (enable == 0) {
165 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
166 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
167 } else {
168 /* Enable main oscillator */
169 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
170 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
171
172 /* Wait for main oscillator to start */
173 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
174 LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
175 (timeout > jiffies))
176 cpu_relax();
177
178 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
179 LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
180 return -ENODEV;
181 }
182
183 return 0;
184}
185
186static struct clk osc_pll397 = {
187 .parent = &osc_32KHz,
188 .enable = local_pll397_enable,
189 .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
190 .get_rate = local_return_parent_rate,
191};
192
193static struct clk osc_main = {
194 .enable = local_oscmain_enable,
195 .rate = LPC32XX_MAIN_OSC_FREQ,
196 .get_rate = local_return_parent_rate,
197};
198
199static struct clk clk_sys;
200
201/*
202 * Convert a PLL register value to a PLL output frequency
203 */
204u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
205{
206 struct clk_pll_setup pllcfg;
207
208 pllcfg.cco_bypass_b15 = 0;
209 pllcfg.direct_output_b14 = 0;
210 pllcfg.fdbk_div_ctrl_b13 = 0;
211 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
212 pllcfg.cco_bypass_b15 = 1;
213 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
214 pllcfg.direct_output_b14 = 1;
215 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
216 pllcfg.fdbk_div_ctrl_b13 = 1;
217 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
218 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
219 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
220
221 return clk_check_pll_setup(inputclk, &pllcfg);
222}
223
224/*
225 * Setup the HCLK PLL with a PLL structure
226 */
227static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
228{
229 u32 tv, tmp = 0;
230
231 if (PllSetup->analog_on != 0)
232 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
233 if (PllSetup->cco_bypass_b15 != 0)
234 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
235 if (PllSetup->direct_output_b14 != 0)
236 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
237 if (PllSetup->fdbk_div_ctrl_b13 != 0)
238 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
239
240 tv = ffs(PllSetup->pll_p) - 1;
241 if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
242 return 0;
243
244 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
245 tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
246 tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
247
248 return tmp;
249}
250
251/*
252 * Update the ARM core PLL frequency rate variable from the actual PLL setting
253 */
254static void local_update_armpll_rate(void)
255{
256 u32 clkin, pllreg;
257
258 clkin = clk_armpll.parent->rate;
259 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
260
261 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
262}
263
264/*
265 * Find a PLL configuration for the selected input frequency
266 */
267static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
268 struct clk_pll_setup *pllsetup)
269{
270 u32 ifreq, freqtol, m, n, p, fclkout;
271
272 /* Determine frequency tolerance limits */
273 freqtol = target_freq / 250;
274 ifreq = pllin_freq;
275
276 /* Is direct bypass mode possible? */
277 if (abs(pllin_freq - target_freq) <= freqtol) {
278 pllsetup->analog_on = 0;
279 pllsetup->cco_bypass_b15 = 1;
280 pllsetup->direct_output_b14 = 1;
281 pllsetup->fdbk_div_ctrl_b13 = 1;
282 pllsetup->pll_p = pll_postdivs[0];
283 pllsetup->pll_n = 1;
284 pllsetup->pll_m = 1;
285 return clk_check_pll_setup(ifreq, pllsetup);
286 } else if (target_freq <= ifreq) {
287 pllsetup->analog_on = 0;
288 pllsetup->cco_bypass_b15 = 1;
289 pllsetup->direct_output_b14 = 0;
290 pllsetup->fdbk_div_ctrl_b13 = 1;
291 pllsetup->pll_n = 1;
292 pllsetup->pll_m = 1;
293 for (p = 0; p <= 3; p++) {
294 pllsetup->pll_p = pll_postdivs[p];
295 fclkout = clk_check_pll_setup(ifreq, pllsetup);
296 if (abs(target_freq - fclkout) <= freqtol)
297 return fclkout;
298 }
299 }
300
301 /* Is direct mode possible? */
302 pllsetup->analog_on = 1;
303 pllsetup->cco_bypass_b15 = 0;
304 pllsetup->direct_output_b14 = 1;
305 pllsetup->fdbk_div_ctrl_b13 = 0;
306 pllsetup->pll_p = pll_postdivs[0];
307 for (m = 1; m <= 256; m++) {
308 for (n = 1; n <= 4; n++) {
309 /* Compute output frequency for this value */
310 pllsetup->pll_n = n;
311 pllsetup->pll_m = m;
312 fclkout = clk_check_pll_setup(ifreq,
313 pllsetup);
314 if (abs(target_freq - fclkout) <=
315 freqtol)
316 return fclkout;
317 }
318 }
319
320 /* Is integer mode possible? */
321 pllsetup->analog_on = 1;
322 pllsetup->cco_bypass_b15 = 0;
323 pllsetup->direct_output_b14 = 0;
324 pllsetup->fdbk_div_ctrl_b13 = 1;
325 for (m = 1; m <= 256; m++) {
326 for (n = 1; n <= 4; n++) {
327 for (p = 0; p < 4; p++) {
328 /* Compute output frequency */
329 pllsetup->pll_p = pll_postdivs[p];
330 pllsetup->pll_n = n;
331 pllsetup->pll_m = m;
332 fclkout = clk_check_pll_setup(
333 ifreq, pllsetup);
334 if (abs(target_freq - fclkout) <= freqtol)
335 return fclkout;
336 }
337 }
338 }
339
340 /* Try non-integer mode */
341 pllsetup->analog_on = 1;
342 pllsetup->cco_bypass_b15 = 0;
343 pllsetup->direct_output_b14 = 0;
344 pllsetup->fdbk_div_ctrl_b13 = 0;
345 for (m = 1; m <= 256; m++) {
346 for (n = 1; n <= 4; n++) {
347 for (p = 0; p < 4; p++) {
348 /* Compute output frequency */
349 pllsetup->pll_p = pll_postdivs[p];
350 pllsetup->pll_n = n;
351 pllsetup->pll_m = m;
352 fclkout = clk_check_pll_setup(
353 ifreq, pllsetup);
354 if (abs(target_freq - fclkout) <= freqtol)
355 return fclkout;
356 }
357 }
358 }
359
360 return 0;
361}
362
363static struct clk clk_armpll = {
364 .parent = &clk_sys,
365 .get_rate = local_return_parent_rate,
366};
367
368/*
369 * Setup the USB PLL with a PLL structure
370 */
371static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
372{
373 u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
374
375 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
376 reg |= tmp;
377 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
378
379 return clk_check_pll_setup(clk_usbpll.parent->rate,
380 pHCLKPllSetup);
381}
382
383static int local_usbpll_enable(struct clk *clk, int enable)
384{
385 u32 reg;
386 int ret = -ENODEV;
387 unsigned long timeout = 1 + msecs_to_jiffies(10);
388
389 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
390
391 if (enable == 0) {
392 reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
393 LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
394 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
395 } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
396 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
397 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
398
399 /* Wait for PLL lock */
400 while ((timeout > jiffies) & (ret == -ENODEV)) {
401 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
402 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
403 ret = 0;
404 }
405
406 if (ret == 0) {
407 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
408 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
409 }
410 }
411
412 return ret;
413}
414
415static unsigned long local_usbpll_round_rate(struct clk *clk,
416 unsigned long rate)
417{
418 u32 clkin, usbdiv;
419 struct clk_pll_setup pllsetup;
420
421 /*
422 * Unlike other clocks, this clock has a KHz input rate, so bump
423 * it up to work with the PLL function
424 */
425 rate = rate * 1000;
426
427 clkin = clk->parent->rate;
428 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
429 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
430 clkin = clkin / usbdiv;
431
432 /* Try to find a good rate setup */
433 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
434 return 0;
435
436 return clk_check_pll_setup(clkin, &pllsetup);
437}
438
439static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
440{
441 u32 clkin, reg, usbdiv;
442 struct clk_pll_setup pllsetup;
443
444 /*
445 * Unlike other clocks, this clock has a KHz input rate, so bump
446 * it up to work with the PLL function
447 */
448 rate = rate * 1000;
449
450 clkin = clk->get_rate(clk);
451 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
452 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
453 clkin = clkin / usbdiv;
454
455 /* Try to find a good rate setup */
456 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
457 return -EINVAL;
458
459 local_usbpll_enable(clk, 0);
460
461 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
462 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
463 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
464
465 pllsetup.analog_on = 1;
466 local_clk_usbpll_setup(&pllsetup);
467
468 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
469
470 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
471 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
472 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
473
474 return 0;
475}
476
477static struct clk clk_usbpll = {
478 .parent = &osc_main,
479 .set_rate = local_usbpll_set_rate,
480 .enable = local_usbpll_enable,
481 .rate = 48000, /* In KHz */
482 .get_rate = local_return_parent_rate,
483 .round_rate = local_usbpll_round_rate,
484};
485
486static u32 clk_get_hclk_div(void)
487{
488 static const u32 hclkdivs[4] = {1, 2, 4, 4};
489 return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
490 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
491}
492
493static struct clk clk_hclk = {
494 .parent = &clk_armpll,
495 .get_rate = local_return_parent_rate,
496};
497
498static struct clk clk_pclk = {
499 .parent = &clk_armpll,
500 .get_rate = local_return_parent_rate,
501};
502
503static int local_onoff_enable(struct clk *clk, int enable)
504{
505 u32 tmp;
506
507 tmp = __raw_readl(clk->enable_reg);
508
509 if (enable == 0)
510 tmp &= ~clk->enable_mask;
511 else
512 tmp |= clk->enable_mask;
513
514 __raw_writel(tmp, clk->enable_reg);
515
516 return 0;
517}
518
519/* Peripheral clock sources */
520static struct clk clk_timer0 = {
521 .parent = &clk_pclk,
522 .enable = local_onoff_enable,
523 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
524 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
525 .get_rate = local_return_parent_rate,
526};
527static struct clk clk_timer1 = {
528 .parent = &clk_pclk,
529 .enable = local_onoff_enable,
530 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
531 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
532 .get_rate = local_return_parent_rate,
533};
534static struct clk clk_timer2 = {
535 .parent = &clk_pclk,
536 .enable = local_onoff_enable,
537 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
538 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
539 .get_rate = local_return_parent_rate,
540};
541static struct clk clk_timer3 = {
542 .parent = &clk_pclk,
543 .enable = local_onoff_enable,
544 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
545 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
546 .get_rate = local_return_parent_rate,
547};
548static struct clk clk_wdt = {
549 .parent = &clk_pclk,
550 .enable = local_onoff_enable,
551 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
552 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
553 .get_rate = local_return_parent_rate,
554};
555static struct clk clk_vfp9 = {
556 .parent = &clk_pclk,
557 .enable = local_onoff_enable,
558 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
559 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
560 .get_rate = local_return_parent_rate,
561};
562static struct clk clk_dma = {
563 .parent = &clk_hclk,
564 .enable = local_onoff_enable,
565 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
566 .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
567 .get_rate = local_return_parent_rate,
568};
569
570static struct clk clk_uart3 = {
571 .parent = &clk_pclk,
572 .enable = local_onoff_enable,
573 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
574 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
575 .get_rate = local_return_parent_rate,
576};
577
578static struct clk clk_uart4 = {
579 .parent = &clk_pclk,
580 .enable = local_onoff_enable,
581 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
582 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
583 .get_rate = local_return_parent_rate,
584};
585
586static struct clk clk_uart5 = {
587 .parent = &clk_pclk,
588 .enable = local_onoff_enable,
589 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
590 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
591 .get_rate = local_return_parent_rate,
592};
593
594static struct clk clk_uart6 = {
595 .parent = &clk_pclk,
596 .enable = local_onoff_enable,
597 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
598 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
599 .get_rate = local_return_parent_rate,
600};
601
602static struct clk clk_i2c0 = {
603 .parent = &clk_hclk,
604 .enable = local_onoff_enable,
605 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
606 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
607 .get_rate = local_return_parent_rate,
608};
609
610static struct clk clk_i2c1 = {
611 .parent = &clk_hclk,
612 .enable = local_onoff_enable,
613 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
614 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
615 .get_rate = local_return_parent_rate,
616};
617
618static struct clk clk_i2c2 = {
619 .parent = &clk_pclk,
620 .enable = local_onoff_enable,
621 .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
622 .enable_mask = 0x4,
623 .get_rate = local_return_parent_rate,
624};
625
626static struct clk clk_ssp0 = {
627 .parent = &clk_hclk,
628 .enable = local_onoff_enable,
629 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
630 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
631 .get_rate = local_return_parent_rate,
632};
633
634static struct clk clk_ssp1 = {
635 .parent = &clk_hclk,
636 .enable = local_onoff_enable,
637 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
638 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
639 .get_rate = local_return_parent_rate,
640};
641
642static struct clk clk_kscan = {
643 .parent = &osc_32KHz,
644 .enable = local_onoff_enable,
645 .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
646 .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
647 .get_rate = local_return_parent_rate,
648};
649
650static struct clk clk_nand = {
651 .parent = &clk_hclk,
652 .enable = local_onoff_enable,
653 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
654 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
655 .get_rate = local_return_parent_rate,
656};
657
658static struct clk clk_i2s0 = {
659 .parent = &clk_hclk,
660 .enable = local_onoff_enable,
661 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
662 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
663 .get_rate = local_return_parent_rate,
664};
665
666static struct clk clk_i2s1 = {
667 .parent = &clk_hclk,
668 .enable = local_onoff_enable,
669 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
670 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
671 .get_rate = local_return_parent_rate,
672};
673
674static struct clk clk_net = {
675 .parent = &clk_hclk,
676 .enable = local_onoff_enable,
677 .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
678 .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
679 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
680 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
681 .get_rate = local_return_parent_rate,
682};
683
684static struct clk clk_rtc = {
685 .parent = &osc_32KHz,
686 .rate = 1, /* 1 Hz */
687 .get_rate = local_return_parent_rate,
688};
689
690static struct clk clk_usbd = {
691 .parent = &clk_usbpll,
692 .enable = local_onoff_enable,
693 .enable_reg = LPC32XX_CLKPWR_USB_CTRL,
694 .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
695 .get_rate = local_return_parent_rate,
696};
697
698static int tsc_onoff_enable(struct clk *clk, int enable)
699{
700 u32 tmp;
701
702 /* Make sure 32KHz clock is the selected clock */
703 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
704 tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
705 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
706
707 if (enable == 0)
708 __raw_writel(0, clk->enable_reg);
709 else
710 __raw_writel(clk->enable_mask, clk->enable_reg);
711
712 return 0;
713}
714
715static struct clk clk_tsc = {
716 .parent = &osc_32KHz,
717 .enable = tsc_onoff_enable,
718 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
719 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
720 .get_rate = local_return_parent_rate,
721};
722
723static int mmc_onoff_enable(struct clk *clk, int enable)
724{
725 u32 tmp;
726
727 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
728 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
729
730 /* If rate is 0, disable clock */
731 if (enable != 0)
732 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
733
734 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
735
736 return 0;
737}
738
739static unsigned long mmc_get_rate(struct clk *clk)
740{
741 u32 div, rate, oldclk;
742
743 /* The MMC clock must be on when accessing an MMC register */
744 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
745 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
746 LPC32XX_CLKPWR_MS_CTRL);
747 div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
748 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
749
750 /* Get the parent clock rate */
751 rate = clk->parent->get_rate(clk->parent);
752
753 /* Get the MMC controller clock divider value */
754 div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
755
756 if (!div)
757 div = 1;
758
759 return rate / div;
760}
761
762static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
763{
764 unsigned long div, prate;
765
766 /* Get the parent clock rate */
767 prate = clk->parent->get_rate(clk->parent);
768
769 if (rate >= prate)
770 return prate;
771
772 div = prate / rate;
773 if (div > 0xf)
774 div = 0xf;
775
776 return prate / div;
777}
778
779static int mmc_set_rate(struct clk *clk, unsigned long rate)
780{
781 u32 oldclk, tmp;
782 unsigned long prate, div, crate = mmc_round_rate(clk, rate);
783
784 prate = clk->parent->get_rate(clk->parent);
785
786 div = prate / crate;
787
788 /* The MMC clock must be on when accessing an MMC register */
789 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
790 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
791 LPC32XX_CLKPWR_MS_CTRL);
792 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
793 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
794 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
795 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
796
797 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
798
799 return 0;
800}
801
802static struct clk clk_mmc = {
803 .parent = &clk_armpll,
804 .set_rate = mmc_set_rate,
805 .get_rate = mmc_get_rate,
806 .round_rate = mmc_round_rate,
807 .enable = mmc_onoff_enable,
808 .enable_reg = LPC32XX_CLKPWR_MS_CTRL,
809 .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
810};
811
812static unsigned long clcd_get_rate(struct clk *clk)
813{
814 u32 tmp, div, rate, oldclk;
815
816 /* The LCD clock must be on when accessing an LCD register */
817 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
818 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
819 LPC32XX_CLKPWR_LCDCLK_CTRL);
820 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
821 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
822
823 rate = clk->parent->get_rate(clk->parent);
824
825 /* Only supports internal clocking */
826 if (tmp & TIM2_BCD)
827 return rate;
828
829 div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
830 tmp = rate / (2 + div);
831
832 return tmp;
833}
834
835static int clcd_set_rate(struct clk *clk, unsigned long rate)
836{
837 u32 tmp, prate, div, oldclk;
838
839 /* The LCD clock must be on when accessing an LCD register */
840 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
841 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
842 LPC32XX_CLKPWR_LCDCLK_CTRL);
843
844 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
845 prate = clk->parent->get_rate(clk->parent);
846
847 if (rate < prate) {
848 /* Find closest divider */
849 div = prate / rate;
850 if (div >= 2) {
851 div -= 2;
852 tmp &= ~TIM2_BCD;
853 }
854
855 tmp &= ~(0xF800001F);
856 tmp |= (div & 0x1F);
857 tmp |= (((div >> 5) & 0x1F) << 27);
858 }
859
860 __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
861 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
862
863 return 0;
864}
865
866static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
867{
868 u32 prate, div;
869
870 prate = clk->parent->get_rate(clk->parent);
871
872 if (rate >= prate)
873 rate = prate;
874 else {
875 div = prate / rate;
876 if (div > 0x3ff)
877 div = 0x3ff;
878
879 rate = prate / div;
880 }
881
882 return rate;
883}
884
885static struct clk clk_lcd = {
886 .parent = &clk_hclk,
887 .set_rate = clcd_set_rate,
888 .get_rate = clcd_get_rate,
889 .round_rate = clcd_round_rate,
890 .enable = local_onoff_enable,
891 .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
892 .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
893};
894
895static inline void clk_lock(void)
896{
897 mutex_lock(&clkm_lock);
898}
899
900static inline void clk_unlock(void)
901{
902 mutex_unlock(&clkm_lock);
903}
904
905static void local_clk_disable(struct clk *clk)
906{
907 WARN_ON(clk->usecount == 0);
908
909 /* Don't attempt to disable clock if it has no users */
910 if (clk->usecount > 0) {
911 clk->usecount--;
912
913 /* Only disable clock when it has no more users */
914 if ((clk->usecount == 0) && (clk->enable))
915 clk->enable(clk, 0);
916
917 /* Check parent clocks, they may need to be disabled too */
918 if (clk->parent)
919 local_clk_disable(clk->parent);
920 }
921}
922
923static int local_clk_enable(struct clk *clk)
924{
925 int ret = 0;
926
927 /* Enable parent clocks first and update use counts */
928 if (clk->parent)
929 ret = local_clk_enable(clk->parent);
930
931 if (!ret) {
932 /* Only enable clock if it's currently disabled */
933 if ((clk->usecount == 0) && (clk->enable))
934 ret = clk->enable(clk, 1);
935
936 if (!ret)
937 clk->usecount++;
938 else if (clk->parent)
939 local_clk_disable(clk->parent);
940 }
941
942 return ret;
943}
944
945/*
946 * clk_enable - inform the system when the clock source should be running.
947 */
948int clk_enable(struct clk *clk)
949{
950 int ret;
951
952 clk_lock();
953 ret = local_clk_enable(clk);
954 clk_unlock();
955
956 return ret;
957}
958EXPORT_SYMBOL(clk_enable);
959
960/*
961 * clk_disable - inform the system when the clock source is no longer required
962 */
963void clk_disable(struct clk *clk)
964{
965 clk_lock();
966 local_clk_disable(clk);
967 clk_unlock();
968}
969EXPORT_SYMBOL(clk_disable);
970
971/*
972 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
973 */
974unsigned long clk_get_rate(struct clk *clk)
975{
976 unsigned long rate;
977
978 clk_lock();
979 rate = clk->get_rate(clk);
980 clk_unlock();
981
982 return rate;
983}
984EXPORT_SYMBOL(clk_get_rate);
985
986/*
987 * clk_set_rate - set the clock rate for a clock source
988 */
989int clk_set_rate(struct clk *clk, unsigned long rate)
990{
991 int ret = -EINVAL;
992
993 /*
994 * Most system clocks can only be enabled or disabled, with
995 * the actual rate set as part of the peripheral dividers
996 * instead of high level clock control
997 */
998 if (clk->set_rate) {
999 clk_lock();
1000 ret = clk->set_rate(clk, rate);
1001 clk_unlock();
1002 }
1003
1004 return ret;
1005}
1006EXPORT_SYMBOL(clk_set_rate);
1007
1008/*
1009 * clk_round_rate - adjust a rate to the exact rate a clock can provide
1010 */
1011long clk_round_rate(struct clk *clk, unsigned long rate)
1012{
1013 clk_lock();
1014
1015 if (clk->round_rate)
1016 rate = clk->round_rate(clk, rate);
1017 else
1018 rate = clk->get_rate(clk);
1019
1020 clk_unlock();
1021
1022 return rate;
1023}
1024EXPORT_SYMBOL(clk_round_rate);
1025
1026/*
1027 * clk_set_parent - set the parent clock source for this clock
1028 */
1029int clk_set_parent(struct clk *clk, struct clk *parent)
1030{
1031 /* Clock re-parenting is not supported */
1032 return -EINVAL;
1033}
1034EXPORT_SYMBOL(clk_set_parent);
1035
1036/*
1037 * clk_get_parent - get the parent clock source for this clock
1038 */
1039struct clk *clk_get_parent(struct clk *clk)
1040{
1041 return clk->parent;
1042}
1043EXPORT_SYMBOL(clk_get_parent);
1044
1045#define _REGISTER_CLOCK(d, n, c) \
1046 { \
1047 .dev_id = (d), \
1048 .con_id = (n), \
1049 .clk = &(c), \
1050 },
1051
1052static struct clk_lookup lookups[] = {
1053 _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
1054 _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
1055 _REGISTER_CLOCK(NULL, "osc_main", osc_main)
1056 _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
1057 _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
1058 _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
1059 _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
1060 _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
1061 _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
1062 _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
1063 _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
1064 _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
1065 _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
1066 _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
1067 _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
1068 _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
1069 _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
1070 _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
1071 _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
1072 _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
1073 _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
1074 _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
1075 _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
1076 _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
1077 _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
1078 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1079 _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
1080 _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
1081 _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
1082 _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
1083 _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
1084 _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
1085 _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
1086 _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
1087};
1088
1089static int __init clk_init(void)
1090{
1091 int i;
1092
1093 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1094 clkdev_add(&lookups[i]);
1095
1096 /*
1097 * Setup muxed SYSCLK for HCLK PLL base -this selects the
1098 * parent clock used for the ARM PLL and is used to derive
1099 * the many system clock rates in the device.
1100 */
1101 if (clk_is_sysclk_mainosc() != 0)
1102 clk_sys.parent = &osc_main;
1103 else
1104 clk_sys.parent = &osc_pll397;
1105
1106 clk_sys.rate = clk_sys.parent->rate;
1107
1108 /* Compute the current ARM PLL and USB PLL frequencies */
1109 local_update_armpll_rate();
1110
1111 /* Compute HCLK and PCLK bus rates */
1112 clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1113 clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1114
1115 /*
1116 * Enable system clocks - this step is somewhat formal, as the
1117 * clocks are already running, but it does get the clock data
1118 * inline with the actual system state. Never disable these
1119 * clocks as they will only stop if the system is going to sleep.
1120 * In that case, the chip/system power management functions will
1121 * handle clock gating.
1122 */
1123 if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1124 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1125
1126 /*
1127 * Timers 0 and 1 were enabled and are being used by the high
1128 * resolution tick function prior to this driver being initialized.
1129 * Tag them now as used.
1130 */
1131 if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1132 printk(KERN_ERR "Error enabling timer tick clocks\n");
1133
1134 return 0;
1135}
1136core_initcall(clk_init);
1137
diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
new file mode 100644
index 000000000000..c0a8434307f7
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.h
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/mach-lpc32xx/clock.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __LPC32XX_CLOCK_H
20#define __LPC32XX_CLOCK_H
21
22struct clk {
23 struct list_head node;
24 struct clk *parent;
25 u32 rate;
26 u32 usecount;
27
28 int (*set_rate) (struct clk *, unsigned long);
29 unsigned long (*round_rate) (struct clk *, unsigned long);
30 unsigned long (*get_rate) (struct clk *clk);
31 int (*enable) (struct clk *, int);
32
33 /* Register address and bit mask for simple clocks */
34 void __iomem *enable_reg;
35 u32 enable_mask;
36};
37
38#endif
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
new file mode 100644
index 000000000000..ee24dc28e93e
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -0,0 +1,271 @@
1/*
2 * arch/arm/mach-lpc32xx/common.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/err.h>
24#include <linux/i2c.h>
25#include <linux/i2c-pnx.h>
26#include <linux/io.h>
27
28#include <asm/mach/map.h>
29
30#include <mach/i2c.h>
31#include <mach/hardware.h>
32#include <mach/platform.h>
33#include "common.h"
34
35/*
36 * Watchdog timer
37 */
38static struct resource watchdog_resources[] = {
39 [0] = {
40 .start = LPC32XX_WDTIM_BASE,
41 .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
42 .flags = IORESOURCE_MEM,
43 },
44};
45
46struct platform_device lpc32xx_watchdog_device = {
47 .name = "pnx4008-watchdog",
48 .id = -1,
49 .num_resources = ARRAY_SIZE(watchdog_resources),
50 .resource = watchdog_resources,
51};
52
53/*
54 * I2C busses
55 */
56static struct i2c_pnx_data i2c0_data = {
57 .name = I2C_CHIP_NAME "1",
58 .base = LPC32XX_I2C1_BASE,
59 .irq = IRQ_LPC32XX_I2C_1,
60};
61
62static struct i2c_pnx_data i2c1_data = {
63 .name = I2C_CHIP_NAME "2",
64 .base = LPC32XX_I2C2_BASE,
65 .irq = IRQ_LPC32XX_I2C_2,
66};
67
68static struct i2c_pnx_data i2c2_data = {
69 .name = "USB-I2C",
70 .base = LPC32XX_OTG_I2C_BASE,
71 .irq = IRQ_LPC32XX_USB_I2C,
72};
73
74struct platform_device lpc32xx_i2c0_device = {
75 .name = "pnx-i2c",
76 .id = 0,
77 .dev = {
78 .platform_data = &i2c0_data,
79 },
80};
81
82struct platform_device lpc32xx_i2c1_device = {
83 .name = "pnx-i2c",
84 .id = 1,
85 .dev = {
86 .platform_data = &i2c1_data,
87 },
88};
89
90struct platform_device lpc32xx_i2c2_device = {
91 .name = "pnx-i2c",
92 .id = 2,
93 .dev = {
94 .platform_data = &i2c2_data,
95 },
96};
97
98/*
99 * Returns the unique ID for the device
100 */
101void lpc32xx_get_uid(u32 devid[4])
102{
103 int i;
104
105 for (i = 0; i < 4; i++)
106 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
107}
108
109/*
110 * Returns SYSCLK source
111 * 0 = PLL397, 1 = main oscillator
112 */
113int clk_is_sysclk_mainosc(void)
114{
115 if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
116 LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
117 return 1;
118
119 return 0;
120}
121
122/*
123 * System reset via the watchdog timer
124 */
125void lpc32xx_watchdog_reset(void)
126{
127 /* Make sure WDT clocks are enabled */
128 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
129 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
130
131 /* Instant assert of RESETOUT_N with pulse length 1mS */
132 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
133 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
134}
135
136/*
137 * Detects and returns IRAM size for the device variation
138 */
139#define LPC32XX_IRAM_BANK_SIZE SZ_128K
140static u32 iram_size;
141u32 lpc32xx_return_iram_size(void)
142{
143 if (iram_size == 0) {
144 u32 savedval1, savedval2;
145 void __iomem *iramptr1, *iramptr2;
146
147 iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
148 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
149 savedval1 = __raw_readl(iramptr1);
150 savedval2 = __raw_readl(iramptr2);
151
152 if (savedval1 == savedval2) {
153 __raw_writel(savedval2 + 1, iramptr2);
154 if (__raw_readl(iramptr1) == savedval2 + 1)
155 iram_size = LPC32XX_IRAM_BANK_SIZE;
156 else
157 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
158 __raw_writel(savedval2, iramptr2);
159 } else
160 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
161 }
162
163 return iram_size;
164}
165
166/*
167 * Computes PLL rate from PLL register and input clock
168 */
169u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
170{
171 u32 ilfreq, p, m, n, fcco, fref, cfreq;
172 int mode;
173
174 /*
175 * PLL requirements
176 * ifreq must be >= 1MHz and <= 20MHz
177 * FCCO must be >= 156MHz and <= 320MHz
178 * FREF must be >= 1MHz and <= 27MHz
179 * Assume the passed input data is not valid
180 */
181
182 ilfreq = ifreq;
183 m = pllsetup->pll_m;
184 n = pllsetup->pll_n;
185 p = pllsetup->pll_p;
186
187 mode = (pllsetup->cco_bypass_b15 << 2) |
188 (pllsetup->direct_output_b14 << 1) |
189 pllsetup->fdbk_div_ctrl_b13;
190
191 switch (mode) {
192 case 0x0: /* Non-integer mode */
193 cfreq = (m * ilfreq) / (2 * p * n);
194 fcco = (m * ilfreq) / n;
195 fref = ilfreq / n;
196 break;
197
198 case 0x1: /* integer mode */
199 cfreq = (m * ilfreq) / n;
200 fcco = (m * ilfreq) / (n * 2 * p);
201 fref = ilfreq / n;
202 break;
203
204 case 0x2:
205 case 0x3: /* Direct mode */
206 cfreq = (m * ilfreq) / n;
207 fcco = cfreq;
208 fref = ilfreq / n;
209 break;
210
211 case 0x4:
212 case 0x5: /* Bypass mode */
213 cfreq = ilfreq / (2 * p);
214 fcco = 156000000;
215 fref = 1000000;
216 break;
217
218 case 0x6:
219 case 0x7: /* Direct bypass mode */
220 default:
221 cfreq = ilfreq;
222 fcco = 156000000;
223 fref = 1000000;
224 break;
225 }
226
227 if (fcco < 156000000 || fcco > 320000000)
228 cfreq = 0;
229
230 if (fref < 1000000 || fref > 27000000)
231 cfreq = 0;
232
233 return (u32) cfreq;
234}
235
236u32 clk_get_pclk_div(void)
237{
238 return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
239}
240
241static struct map_desc lpc32xx_io_desc[] __initdata = {
242 {
243 .virtual = IO_ADDRESS(LPC32XX_AHB0_START),
244 .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
245 .length = LPC32XX_AHB0_SIZE,
246 .type = MT_DEVICE
247 },
248 {
249 .virtual = IO_ADDRESS(LPC32XX_AHB1_START),
250 .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
251 .length = LPC32XX_AHB1_SIZE,
252 .type = MT_DEVICE
253 },
254 {
255 .virtual = IO_ADDRESS(LPC32XX_FABAPB_START),
256 .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
257 .length = LPC32XX_FABAPB_SIZE,
258 .type = MT_DEVICE
259 },
260 {
261 .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE),
262 .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
263 .length = (LPC32XX_IRAM_BANK_SIZE * 2),
264 .type = MT_DEVICE
265 },
266};
267
268void __init lpc32xx_map_io(void)
269{
270 iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
271}
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
new file mode 100644
index 000000000000..f82211fd80c1
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -0,0 +1,73 @@
1/*
2 * arch/arm/mach-lpc32xx/common.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2009-2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __LPC32XX_COMMON_H
20#define __LPC32XX_COMMON_H
21
22#include <linux/platform_device.h>
23
24/*
25 * Arch specific platform device structures
26 */
27extern struct platform_device lpc32xx_watchdog_device;
28extern struct platform_device lpc32xx_i2c0_device;
29extern struct platform_device lpc32xx_i2c1_device;
30extern struct platform_device lpc32xx_i2c2_device;
31
32/*
33 * Other arch specific structures and functions
34 */
35extern struct sys_timer lpc32xx_timer;
36extern void __init lpc32xx_init_irq(void);
37extern void __init lpc32xx_map_io(void);
38extern void __init lpc32xx_serial_init(void);
39extern void __init lpc32xx_gpio_init(void);
40
41/*
42 * Structure used for setting up and querying the PLLS
43 */
44struct clk_pll_setup {
45 int analog_on;
46 int cco_bypass_b15;
47 int direct_output_b14;
48 int fdbk_div_ctrl_b13;
49 int pll_p;
50 int pll_n;
51 u32 pll_m;
52};
53
54extern int clk_is_sysclk_mainosc(void);
55extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
56extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
57extern u32 clk_get_pclk_div(void);
58
59/*
60 * Returns the LPC32xx unique 128-bit chip ID
61 */
62extern void lpc32xx_get_uid(u32 devid[4]);
63
64extern void lpc32xx_watchdog_reset(void);
65extern u32 lpc32xx_return_iram_size(void);
66
67/*
68 * Pointers used for sizing and copying suspend function data
69 */
70extern int lpc32xx_sys_suspend(void);
71extern int lpc32xx_sys_suspend_sz;
72
73#endif
diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
new file mode 100644
index 000000000000..69061ea8997a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -0,0 +1,446 @@
1/*
2 * arch/arm/mach-lpc32xx/gpiolib.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/errno.h>
23#include <linux/gpio.h>
24
25#include <mach/hardware.h>
26#include <mach/platform.h>
27#include "common.h"
28
29#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
30#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
31#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
32#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
33#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
34#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
35#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
36#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
37#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
38#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
39#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
40#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
41#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
42#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
43#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
44#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
45#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
46#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
47#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
48#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
49#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
50#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
51#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
52#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
53#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
54#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
55#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
56
57#define GPIO012_PIN_TO_BIT(x) (1 << (x))
58#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
59#define GPO3_PIN_TO_BIT(x) (1 << (x))
60#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
61#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
62#define GPIO3_PIN_IN_SEL(x, y) ((x) >> GPIO3_PIN_IN_SHIFT(y))
63#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
64#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
65
66struct gpio_regs {
67 void __iomem *inp_state;
68 void __iomem *outp_set;
69 void __iomem *outp_clr;
70 void __iomem *dir_set;
71 void __iomem *dir_clr;
72};
73
74/*
75 * GPIO names
76 */
77static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
78 "p0.0", "p0.1", "p0.2", "p0.3",
79 "p0.4", "p0.5", "p0.6", "p0.7"
80};
81
82static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
83 "p1.0", "p1.1", "p1.2", "p1.3",
84 "p1.4", "p1.5", "p1.6", "p1.7",
85 "p1.8", "p1.9", "p1.10", "p1.11",
86 "p1.12", "p1.13", "p1.14", "p1.15",
87 "p1.16", "p1.17", "p1.18", "p1.19",
88 "p1.20", "p1.21", "p1.22", "p1.23",
89};
90
91static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
92 "p2.0", "p2.1", "p2.2", "p2.3",
93 "p2.4", "p2.5", "p2.6", "p2.7",
94 "p2.8", "p2.9", "p2.10", "p2.11",
95 "p2.12"
96};
97
98static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
99 "gpi000", "gpio01", "gpio02", "gpio03",
100 "gpio04", "gpio05"
101};
102
103static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
104 "gpi00", "gpi01", "gpi02", "gpi03",
105 "gpi04", "gpi05", "gpi06", "gpi07",
106 "gpi08", "gpi09", NULL, NULL,
107 NULL, NULL, NULL, "gpi15",
108 "gpi16", "gpi17", "gpi18", "gpi19",
109 "gpi20", "gpi21", "gpi22", "gpi23",
110 "gpi24", "gpi25", "gpi26", "gpi27"
111};
112
113static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
114 "gpo00", "gpo01", "gpo02", "gpo03",
115 "gpo04", "gpo05", "gpo06", "gpo07",
116 "gpo08", "gpo09", "gpo10", "gpo11",
117 "gpo12", "gpo13", "gpo14", "gpo15",
118 "gpo16", "gpo17", "gpo18", "gpo19",
119 "gpo20", "gpo21", "gpo22", "gpo23"
120};
121
122static struct gpio_regs gpio_grp_regs_p0 = {
123 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
124 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
125 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
126 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
127 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
128};
129
130static struct gpio_regs gpio_grp_regs_p1 = {
131 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
132 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
133 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
134 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
135 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
136};
137
138static struct gpio_regs gpio_grp_regs_p2 = {
139 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
140 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
141 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
142 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
143 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
144};
145
146static struct gpio_regs gpio_grp_regs_p3 = {
147 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
148 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
149 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
150 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
151 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
152};
153
154struct lpc32xx_gpio_chip {
155 struct gpio_chip chip;
156 struct gpio_regs *gpio_grp;
157};
158
159static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
160 struct gpio_chip *gpc)
161{
162 return container_of(gpc, struct lpc32xx_gpio_chip, chip);
163}
164
165static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
166 unsigned pin, int input)
167{
168 if (input)
169 __raw_writel(GPIO012_PIN_TO_BIT(pin),
170 group->gpio_grp->dir_clr);
171 else
172 __raw_writel(GPIO012_PIN_TO_BIT(pin),
173 group->gpio_grp->dir_set);
174}
175
176static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
177 unsigned pin, int input)
178{
179 u32 u = GPIO3_PIN_TO_BIT(pin);
180
181 if (input)
182 __raw_writel(u, group->gpio_grp->dir_clr);
183 else
184 __raw_writel(u, group->gpio_grp->dir_set);
185}
186
187static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
188 unsigned pin, int high)
189{
190 if (high)
191 __raw_writel(GPIO012_PIN_TO_BIT(pin),
192 group->gpio_grp->outp_set);
193 else
194 __raw_writel(GPIO012_PIN_TO_BIT(pin),
195 group->gpio_grp->outp_clr);
196}
197
198static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
199 unsigned pin, int high)
200{
201 u32 u = GPIO3_PIN_TO_BIT(pin);
202
203 if (high)
204 __raw_writel(u, group->gpio_grp->outp_set);
205 else
206 __raw_writel(u, group->gpio_grp->outp_clr);
207}
208
209static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
210 unsigned pin, int high)
211{
212 if (high)
213 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
214 else
215 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
216}
217
218static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
219 unsigned pin)
220{
221 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
222 pin);
223}
224
225static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
226 unsigned pin)
227{
228 int state = __raw_readl(group->gpio_grp->inp_state);
229
230 /*
231 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
232 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
233 */
234 return GPIO3_PIN_IN_SEL(state, pin);
235}
236
237static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
238 unsigned pin)
239{
240 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
241}
242
243/*
244 * GENERIC_GPIO primitives.
245 */
246static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
247 unsigned pin)
248{
249 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
250
251 __set_gpio_dir_p012(group, pin, 1);
252
253 return 0;
254}
255
256static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
257 unsigned pin)
258{
259 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
260
261 __set_gpio_dir_p3(group, pin, 1);
262
263 return 0;
264}
265
266static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
267 unsigned pin)
268{
269 return 0;
270}
271
272static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
273{
274 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
275
276 return __get_gpio_state_p012(group, pin);
277}
278
279static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
280{
281 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
282
283 return __get_gpio_state_p3(group, pin);
284}
285
286static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
287{
288 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
289
290 return __get_gpi_state_p3(group, pin);
291}
292
293static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
294 int value)
295{
296 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
297
298 __set_gpio_dir_p012(group, pin, 0);
299
300 return 0;
301}
302
303static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
304 int value)
305{
306 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
307
308 __set_gpio_dir_p3(group, pin, 0);
309
310 return 0;
311}
312
313static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
314 int value)
315{
316 return 0;
317}
318
319static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
320 int value)
321{
322 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
323
324 __set_gpio_level_p012(group, pin, value);
325}
326
327static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
328 int value)
329{
330 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
331
332 __set_gpio_level_p3(group, pin, value);
333}
334
335static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
336 int value)
337{
338 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
339
340 __set_gpo_level_p3(group, pin, value);
341}
342
343static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
344{
345 if (pin < chip->ngpio)
346 return 0;
347
348 return -EINVAL;
349}
350
351static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
352 {
353 .chip = {
354 .label = "gpio_p0",
355 .direction_input = lpc32xx_gpio_dir_input_p012,
356 .get = lpc32xx_gpio_get_value_p012,
357 .direction_output = lpc32xx_gpio_dir_output_p012,
358 .set = lpc32xx_gpio_set_value_p012,
359 .request = lpc32xx_gpio_request,
360 .base = LPC32XX_GPIO_P0_GRP,
361 .ngpio = LPC32XX_GPIO_P0_MAX,
362 .names = gpio_p0_names,
363 .can_sleep = 0,
364 },
365 .gpio_grp = &gpio_grp_regs_p0,
366 },
367 {
368 .chip = {
369 .label = "gpio_p1",
370 .direction_input = lpc32xx_gpio_dir_input_p012,
371 .get = lpc32xx_gpio_get_value_p012,
372 .direction_output = lpc32xx_gpio_dir_output_p012,
373 .set = lpc32xx_gpio_set_value_p012,
374 .request = lpc32xx_gpio_request,
375 .base = LPC32XX_GPIO_P1_GRP,
376 .ngpio = LPC32XX_GPIO_P1_MAX,
377 .names = gpio_p1_names,
378 .can_sleep = 0,
379 },
380 .gpio_grp = &gpio_grp_regs_p1,
381 },
382 {
383 .chip = {
384 .label = "gpio_p2",
385 .direction_input = lpc32xx_gpio_dir_input_p012,
386 .get = lpc32xx_gpio_get_value_p012,
387 .direction_output = lpc32xx_gpio_dir_output_p012,
388 .set = lpc32xx_gpio_set_value_p012,
389 .request = lpc32xx_gpio_request,
390 .base = LPC32XX_GPIO_P2_GRP,
391 .ngpio = LPC32XX_GPIO_P2_MAX,
392 .names = gpio_p2_names,
393 .can_sleep = 0,
394 },
395 .gpio_grp = &gpio_grp_regs_p2,
396 },
397 {
398 .chip = {
399 .label = "gpio_p3",
400 .direction_input = lpc32xx_gpio_dir_input_p3,
401 .get = lpc32xx_gpio_get_value_p3,
402 .direction_output = lpc32xx_gpio_dir_output_p3,
403 .set = lpc32xx_gpio_set_value_p3,
404 .request = lpc32xx_gpio_request,
405 .base = LPC32XX_GPIO_P3_GRP,
406 .ngpio = LPC32XX_GPIO_P3_MAX,
407 .names = gpio_p3_names,
408 .can_sleep = 0,
409 },
410 .gpio_grp = &gpio_grp_regs_p3,
411 },
412 {
413 .chip = {
414 .label = "gpi_p3",
415 .direction_input = lpc32xx_gpio_dir_in_always,
416 .get = lpc32xx_gpi_get_value,
417 .request = lpc32xx_gpio_request,
418 .base = LPC32XX_GPI_P3_GRP,
419 .ngpio = LPC32XX_GPI_P3_MAX,
420 .names = gpi_p3_names,
421 .can_sleep = 0,
422 },
423 .gpio_grp = &gpio_grp_regs_p3,
424 },
425 {
426 .chip = {
427 .label = "gpo_p3",
428 .direction_output = lpc32xx_gpio_dir_out_always,
429 .set = lpc32xx_gpo_set_value,
430 .request = lpc32xx_gpio_request,
431 .base = LPC32XX_GPO_P3_GRP,
432 .ngpio = LPC32XX_GPO_P3_MAX,
433 .names = gpo_p3_names,
434 .can_sleep = 0,
435 },
436 .gpio_grp = &gpio_grp_regs_p3,
437 },
438};
439
440void __init lpc32xx_gpio_init(void)
441{
442 int i;
443
444 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
445 gpiochip_add(&lpc32xx_gpiochip[i].chip);
446}
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
index 1ac4e1682e5c..9bf0637e29ce 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
@@ -1,5 +1,9 @@
1/* 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix 2 * arch/arm/mach-lpc32xx/include/mach/clkdev.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
3 * 7 *
4 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,12 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 16 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 17 */
18 18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ 19#ifndef __ASM_ARCH_CLKDEV_H
20#define __ASM_ARCH_MXC_BOARD_PCM043_H__ 20#define __ASM_ARCH_CLKDEV_H
21
22#define __clk_get(clk) ({ 1; })
23#define __clk_put(clk) do { } while (0)
21 24
22#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ 25#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 383f1c04df06..621744d6b152 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -1,5 +1,9 @@
1/* 1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved 2 * arch/arm/mach-lpc32xx/include/mach/debug-macro.S
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
3 * 7 *
4 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,18 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 16 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 17 */
18 18
19#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ 19/*
20#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ 20 * Debug output is hardcoded to standard UART 5
21*/
22
23 .macro addruart,rx, tmp
24 mrc p15, 0, \rx, c1, c0
25 tst \rx, #1 @ MMU enabled?
26 ldreq \rx, =0x40090000
27 ldrne \rx, =0xF4090000
28 .endm
21 29
22#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ 30#define UART_SHIFT 2
31#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..870227c96602
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <mach/hardware.h>
20#include <mach/platform.h>
21
22#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
23
24 .macro disable_fiq
25 .endm
26
27 .macro get_irqnr_preamble, base, tmp
28 ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
29 .endm
30
31 .macro arch_ret_to_user, tmp1, tmp2
32 .endm
33
34/*
35 * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
36 * as set if an interrupt is pending.
37 */
38 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
39 ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
40 clz \irqnr, \irqstat
41 rsb \irqnr, \irqnr, #31
42 teq \irqstat, #0
43 .endm
44
45 .macro irq_prio_table
46 .endm
47
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
new file mode 100644
index 000000000000..67d03da1eee9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -0,0 +1,74 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/gpio.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_GPIO_H
20#define __ASM_ARCH_GPIO_H
21
22#include <asm-generic/gpio.h>
23
24/*
25 * Note!
26 * Muxed GP pins need to be setup to the GP state in the board level
27 * code prior to using this driver.
28 * GPI pins : 28xP3 group
29 * GPO pins : 24xP3 group
30 * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
31 */
32
33#define LPC32XX_GPIO_P0_MAX 8
34#define LPC32XX_GPIO_P1_MAX 24
35#define LPC32XX_GPIO_P2_MAX 13
36#define LPC32XX_GPIO_P3_MAX 6
37#define LPC32XX_GPI_P3_MAX 28
38#define LPC32XX_GPO_P3_MAX 24
39
40#define LPC32XX_GPIO_P0_GRP 0
41#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
42#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
43#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
44#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
45#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
46
47/*
48 * A specific GPIO can be selected with this macro
49 * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
50 * See the LPC32x0 User's guide for GPIO group numbers
51 */
52#define LPC32XX_GPIO(x, y) ((x) + (y))
53
54static inline int gpio_get_value(unsigned gpio)
55{
56 return __gpio_get_value(gpio);
57}
58
59static inline void gpio_set_value(unsigned gpio, int value)
60{
61 __gpio_set_value(gpio, value);
62}
63
64static inline int gpio_cansleep(unsigned gpio)
65{
66 return __gpio_cansleep(gpio);
67}
68
69static inline int gpio_to_irq(unsigned gpio)
70{
71 return __gpio_to_irq(gpio);
72}
73
74#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
new file mode 100644
index 000000000000..33e1dde37bd9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -0,0 +1,34 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/hardware.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __ASM_ARCH_HARDWARE_H
18#define __ASM_ARCH_HARDWARE_H
19
20/*
21 * Start of virtual addresses for IO devices
22 */
23#define IO_BASE 0xF0000000
24
25/*
26 * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
27 */
28#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
29 IO_BASE)
30
31#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
32#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
33
34#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
new file mode 100644
index 000000000000..034dc9286bcc
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/i2c.h
@@ -0,0 +1,63 @@
1/*
2 * PNX4008-specific tweaks for I2C IP3204 block
3 *
4 * Author: Vitaly Wool <vwool@ru.mvista.com>
5 *
6 * 2005 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __ASM_ARCH_I2C_H
13#define __ASM_ARCH_I2C_H
14
15enum {
16 mstatus_tdi = 0x00000001,
17 mstatus_afi = 0x00000002,
18 mstatus_nai = 0x00000004,
19 mstatus_drmi = 0x00000008,
20 mstatus_active = 0x00000020,
21 mstatus_scl = 0x00000040,
22 mstatus_sda = 0x00000080,
23 mstatus_rff = 0x00000100,
24 mstatus_rfe = 0x00000200,
25 mstatus_tff = 0x00000400,
26 mstatus_tfe = 0x00000800,
27};
28
29enum {
30 mcntrl_tdie = 0x00000001,
31 mcntrl_afie = 0x00000002,
32 mcntrl_naie = 0x00000004,
33 mcntrl_drmie = 0x00000008,
34 mcntrl_daie = 0x00000020,
35 mcntrl_rffie = 0x00000040,
36 mcntrl_tffie = 0x00000080,
37 mcntrl_reset = 0x00000100,
38 mcntrl_cdbmode = 0x00000400,
39};
40
41enum {
42 rw_bit = 1 << 0,
43 start_bit = 1 << 8,
44 stop_bit = 1 << 9,
45};
46
47#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
48#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
49#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
50#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
51#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
52#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
53#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
54#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
55#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
56#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
57#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
58#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
59#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
60
61#define I2C_CHIP_NAME "PNX4008-I2C"
62
63#endif /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/mach-lpc32xx/include/mach/io.h
index 13411709b13a..9b59ab5cef89 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/mach-lpc32xx/include/mach/io.h
@@ -1,5 +1,9 @@
1/* 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix 2 * arch/arm/mach-lpc32xx/include/mach/io.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
3 * 7 *
4 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,14 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 16 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 17 */
18 18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ 19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARCH_MXC_BOARD_PCM037_H__ 20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) __typesafe_io(a)
25#define __mem_pci(a) (a)
21 26
22#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ 27#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
new file mode 100644
index 000000000000..2667f52e3b04
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -0,0 +1,117 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/irqs.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARM_ARCH_IRQS_H
20#define __ASM_ARM_ARCH_IRQS_H
21
22#define LPC32XX_SIC1_IRQ(n) (32 + (n))
23#define LPC32XX_SIC2_IRQ(n) (64 + (n))
24
25/*
26 * MIC interrupts
27 */
28#define IRQ_LPC32XX_SUB1IRQ 0
29#define IRQ_LPC32XX_SUB2IRQ 1
30#define IRQ_LPC32XX_PWM3 3
31#define IRQ_LPC32XX_PWM4 4
32#define IRQ_LPC32XX_HSTIMER 5
33#define IRQ_LPC32XX_WATCH 6
34#define IRQ_LPC32XX_UART_IIR3 7
35#define IRQ_LPC32XX_UART_IIR4 8
36#define IRQ_LPC32XX_UART_IIR5 9
37#define IRQ_LPC32XX_UART_IIR6 10
38#define IRQ_LPC32XX_FLASH 11
39#define IRQ_LPC32XX_SD1 13
40#define IRQ_LPC32XX_LCD 14
41#define IRQ_LPC32XX_SD0 15
42#define IRQ_LPC32XX_TIMER0 16
43#define IRQ_LPC32XX_TIMER1 17
44#define IRQ_LPC32XX_TIMER2 18
45#define IRQ_LPC32XX_TIMER3 19
46#define IRQ_LPC32XX_SSP0 20
47#define IRQ_LPC32XX_SSP1 21
48#define IRQ_LPC32XX_I2S0 22
49#define IRQ_LPC32XX_I2S1 23
50#define IRQ_LPC32XX_UART_IIR7 24
51#define IRQ_LPC32XX_UART_IIR2 25
52#define IRQ_LPC32XX_UART_IIR1 26
53#define IRQ_LPC32XX_MSTIMER 27
54#define IRQ_LPC32XX_DMA 28
55#define IRQ_LPC32XX_ETHERNET 29
56#define IRQ_LPC32XX_SUB1FIQ 30
57#define IRQ_LPC32XX_SUB2FIQ 31
58
59/*
60 * SIC1 interrupts start at offset 32
61 */
62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
64#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4)
65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
68#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12)
69#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13)
70#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14)
71#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17)
72#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18)
73#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19)
74#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20)
75#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22)
76#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23)
77#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24)
78#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25)
79#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26)
80#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27)
81#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28)
82#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29)
83#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30)
84#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31)
85
86/*
87 * SIC2 interrupts start at offset 64
88 */
89#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0)
90#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1)
91#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2)
92#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3)
93#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4)
94#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5)
95#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6)
96#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7)
97#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8)
98#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9)
99#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10)
100#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11)
101#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12)
102#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15)
103#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18)
104#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19)
105#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20)
106#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22)
107#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23)
108#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24)
109#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25)
110#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26)
111#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27)
112#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)
113#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31)
114
115#define NR_IRQS 96
116
117#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h
new file mode 100644
index 000000000000..044e1acecbe6
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/memory.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/memory.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_MEMORY_H
20#define __ASM_ARCH_MEMORY_H
21
22/*
23 * Physical DRAM offset of bank 0
24 */
25#define PHYS_OFFSET UL(0x80000000)
26
27#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
new file mode 100644
index 000000000000..14ea8d1aadb5
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -0,0 +1,694 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/platform.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_PLATFORM_H
20#define __ASM_ARCH_PLATFORM_H
21
22#define _SBF(f, v) ((v) << (f))
23#define _BIT(n) _SBF(n, 1)
24
25/*
26 * AHB 0 physical base addresses
27 */
28#define LPC32XX_SLC_BASE 0x20020000
29#define LPC32XX_SSP0_BASE 0x20084000
30#define LPC32XX_SPI1_BASE 0x20088000
31#define LPC32XX_SSP1_BASE 0x2008C000
32#define LPC32XX_SPI2_BASE 0x20090000
33#define LPC32XX_I2S0_BASE 0x20094000
34#define LPC32XX_SD_BASE 0x20098000
35#define LPC32XX_I2S1_BASE 0x2009C000
36#define LPC32XX_MLC_BASE 0x200A8000
37#define LPC32XX_AHB0_START LPC32XX_SLC_BASE
38#define LPC32XX_AHB0_SIZE 0x00089000
39
40/*
41 * AHB 1 physical base addresses
42 */
43#define LPC32XX_DMA_BASE 0x31000000
44#define LPC32XX_USB_BASE 0x31020000
45#define LPC32XX_USBH_BASE 0x31020000
46#define LPC32XX_USB_OTG_BASE 0x31020000
47#define LPC32XX_OTG_I2C_BASE 0x31020300
48#define LPC32XX_LCD_BASE 0x31040000
49#define LPC32XX_ETHERNET_BASE 0x31060000
50#define LPC32XX_EMC_BASE 0x31080000
51#define LPC32XX_ETB_CFG_BASE 0x310C0000
52#define LPC32XX_ETB_DATA_BASE 0x310E0000
53#define LPC32XX_AHB1_START LPC32XX_DMA_BASE
54#define LPC32XX_AHB1_SIZE 0x000E1000
55
56/*
57 * FAB physical base addresses
58 */
59#define LPC32XX_CLK_PM_BASE 0x40004000
60#define LPC32XX_MIC_BASE 0x40008000
61#define LPC32XX_SIC1_BASE 0x4000C000
62#define LPC32XX_SIC2_BASE 0x40010000
63#define LPC32XX_HS_UART1_BASE 0x40014000
64#define LPC32XX_HS_UART2_BASE 0x40018000
65#define LPC32XX_HS_UART7_BASE 0x4001C000
66#define LPC32XX_RTC_BASE 0x40024000
67#define LPC32XX_RTC_RAM_BASE 0x40024080
68#define LPC32XX_GPIO_BASE 0x40028000
69#define LPC32XX_PWM3_BASE 0x4002C000
70#define LPC32XX_PWM4_BASE 0x40030000
71#define LPC32XX_MSTIM_BASE 0x40034000
72#define LPC32XX_HSTIM_BASE 0x40038000
73#define LPC32XX_WDTIM_BASE 0x4003C000
74#define LPC32XX_DEBUG_CTRL_BASE 0x40040000
75#define LPC32XX_TIMER0_BASE 0x40044000
76#define LPC32XX_ADC_BASE 0x40048000
77#define LPC32XX_TIMER1_BASE 0x4004C000
78#define LPC32XX_KSCAN_BASE 0x40050000
79#define LPC32XX_UART_CTRL_BASE 0x40054000
80#define LPC32XX_TIMER2_BASE 0x40058000
81#define LPC32XX_PWM1_BASE 0x4005C000
82#define LPC32XX_PWM2_BASE 0x4005C004
83#define LPC32XX_TIMER3_BASE 0x40060000
84
85/*
86 * APB physical base addresses
87 */
88#define LPC32XX_UART3_BASE 0x40080000
89#define LPC32XX_UART4_BASE 0x40088000
90#define LPC32XX_UART5_BASE 0x40090000
91#define LPC32XX_UART6_BASE 0x40098000
92#define LPC32XX_I2C1_BASE 0x400A0000
93#define LPC32XX_I2C2_BASE 0x400A8000
94
95/*
96 * FAB and APB base and sizing
97 */
98#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE
99#define LPC32XX_FABAPB_SIZE 0x000A5000
100
101/*
102 * Internal memory bases and sizes
103 */
104#define LPC32XX_IRAM_BASE 0x08000000
105#define LPC32XX_IROM_BASE 0x0C000000
106
107/*
108 * External Static Memory Bank Address Space Bases
109 */
110#define LPC32XX_EMC_CS0_BASE 0xE0000000
111#define LPC32XX_EMC_CS1_BASE 0xE1000000
112#define LPC32XX_EMC_CS2_BASE 0xE2000000
113#define LPC32XX_EMC_CS3_BASE 0xE3000000
114
115/*
116 * External SDRAM Memory Bank Address Space Bases
117 */
118#define LPC32XX_EMC_DYCS0_BASE 0x80000000
119#define LPC32XX_EMC_DYCS1_BASE 0xA0000000
120
121/*
122 * Clock and crystal information
123 */
124#define LPC32XX_MAIN_OSC_FREQ 13000000
125#define LPC32XX_CLOCK_OSC_FREQ 32768
126
127/*
128 * Clock and Power control register offsets
129 */
130#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
131 (x))
132#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000)
133#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014)
134#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018)
135#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C)
136#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020)
137#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024)
138#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028)
139#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C)
140#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030)
141#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034)
142#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038)
143#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C)
144#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040)
145#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044)
146#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048)
147#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C)
148#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050)
149#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054)
150#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058)
151#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060)
152#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064)
153#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068)
154#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C)
155#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070)
156#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074)
157#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078)
158#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C)
159#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080)
160#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090)
161#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4)
162#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8)
163#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC)
164#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0)
165#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4)
166#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8)
167#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC)
168#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0)
169#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4)
170#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8)
171#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0)
172#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4)
173#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8)
174#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC)
175#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0)
176#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4)
177#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8)
178#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC)
179#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x))
180
181/*
182 * clkpwr_debug_ctrl register definitions
183*/
184#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4)
185
186/*
187 * clkpwr_bootmap register definitions
188 */
189#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1)
190
191/*
192 * clkpwr_start_gpio register bit definitions
193 */
194#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31)
195#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30)
196#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29)
197#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28)
198#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27)
199#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26)
200#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25)
201#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24)
202#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23)
203#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22)
204#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21)
205#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20)
206#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19)
207#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18)
208#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17)
209#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16)
210#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15)
211#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14)
212#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13)
213#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12)
214#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11)
215#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10)
216#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9)
217#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8)
218#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7)
219#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6)
220#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5)
221#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4)
222#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3)
223#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2)
224#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1)
225#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0)
226
227/*
228 * clkpwr_usbclk_pdiv register definitions
229 */
230#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF
231
232/*
233 * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
234 * clkpwr_start_pol_int, register bit definitions
235 */
236#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31)
237#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30)
238#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29)
239#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26)
240#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25)
241#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24)
242#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23)
243#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22)
244#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21)
245#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20)
246#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19)
247#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16)
248#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7)
249#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6)
250#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5)
251#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4)
252#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3)
253#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2)
254#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1)
255#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0)
256
257/*
258 * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
259 * clkpwr_start_pol_pin register bit definitions
260 */
261#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31)
262#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30)
263#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28)
264#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26)
265#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25)
266#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24)
267#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23)
268#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22)
269#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21)
270#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18)
271#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17)
272#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16)
273#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15)
274#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14)
275#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13)
276#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12)
277#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11)
278#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10)
279#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9)
280#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8)
281#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7)
282#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6)
283#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5)
284#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4)
285#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3)
286
287/*
288 * clkpwr_hclk_div register definitions
289 */
290#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7)
291#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7)
292#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7)
293#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2)
294#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3)
295
296/*
297 * clkpwr_pwr_ctrl register definitions
298 */
299#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10)
300#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9)
301#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8)
302#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7)
303#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5)
304#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4)
305#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3)
306#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2)
307#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1)
308#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0)
309
310/*
311 * clkpwr_pll397_ctrl register definitions
312 */
313#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10)
314#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9)
315#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000
316#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040
317#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080
318#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0
319#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100
320#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140
321#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180
322#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0
323#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0
324#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1)
325#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0)
326
327/*
328 * clkpwr_main_osc_ctrl register definitions
329 */
330#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2)
331#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2)
332#define LPC32XX_CLKPWR_TEST_MODE _BIT(1)
333#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0)
334
335/*
336 * clkpwr_sysclk_ctrl register definitions
337 */
338#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2)
339#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2)
340#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1)
341#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0)
342
343/*
344 * clkpwr_lcdclk_ctrl register definitions
345 */
346#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000
347#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040
348#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080
349#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0
350#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100
351#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140
352#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180
353#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0
354#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0
355#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020
356#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F)
357#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F
358
359/*
360 * clkpwr_hclkpll_ctrl register definitions
361 */
362#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16)
363#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15)
364#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14)
365#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13)
366#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
367#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
368#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1)
369#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0)
370
371/*
372 * clkpwr_adc_clk_ctrl_1 register definitions
373 */
374#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0)
375#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8)
376
377/*
378 * clkpwr_usb_ctrl register definitions
379 */
380#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24)
381#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23)
382#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22)
383#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21)
384#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19)
385#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19)
386#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19)
387#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18)
388#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17)
389#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16)
390#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15)
391#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14)
392#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13)
393#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
394#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
395#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
396#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0)
397
398/*
399 * clkpwr_sdramclk_ctrl register definitions
400 */
401#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22)
402#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21)
403#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20)
404#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19)
405#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14)
406#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13)
407#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10)
408#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9)
409#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8)
410#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7)
411#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2)
412#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1)
413#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0)
414
415/*
416 * clkpwr_ssp_blk_ctrl register definitions
417 */
418#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5)
419#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4)
420#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3)
421#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2)
422#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1)
423#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0)
424
425/*
426 * clkpwr_i2s_clk_ctrl register definitions
427 */
428#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6)
429#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5)
430#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4)
431#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3)
432#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2)
433#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1)
434#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0)
435
436/*
437 * clkpwr_ms_ctrl register definitions
438 */
439#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10)
440#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9)
441#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8)
442#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7)
443#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6)
444#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5)
445#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF)
446
447/*
448 * clkpwr_macclk_ctrl register definitions
449 */
450#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00
451#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08
452#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18
453#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18
454#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2)
455#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1)
456#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0)
457
458/*
459 * clkpwr_test_clk_sel register definitions
460 */
461#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5)
462#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5)
463#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5)
464#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5)
465#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4)
466#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1)
467#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1)
468#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1)
469#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1)
470#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1)
471#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1)
472#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0)
473
474/*
475 * clkpwr_sw_int register definitions
476 */
477#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1))
478#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1)
479
480/*
481 * clkpwr_i2c_clk_ctrl register definitions
482 */
483#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4)
484#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3)
485#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2)
486#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1)
487#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0)
488
489/*
490 * clkpwr_key_clk_ctrl register definitions
491 */
492#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1
493
494/*
495 * clkpwr_adc_clk_ctrl register definitions
496 */
497#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1
498
499/*
500 * clkpwr_pwm_clk_ctrl register definitions
501 */
502#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8)
503#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4)
504#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8
505#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4
506#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2
507#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1
508
509/*
510 * clkpwr_timer_clk_ctrl register definitions
511 */
512#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2
513#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1
514
515/*
516 * clkpwr_timers_pwms_clk_ctrl_1 register definitions
517 */
518#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
519#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
520#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
521#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04
522#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02
523#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01
524
525/*
526 * clkpwr_spi_clk_ctrl register definitions
527 */
528#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80
529#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40
530#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20
531#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10
532#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08
533#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04
534#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02
535#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01
536
537/*
538 * clkpwr_nand_clk_ctrl register definitions
539 */
540#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20
541#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10
542#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08
543#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04
544#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02
545#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01
546
547/*
548 * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
549 * and clkpwr_uart6_clk_ctrl register definitions
550 */
551#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF)
552#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8)
553#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16)
554
555/*
556 * clkpwr_irda_clk_ctrl register definitions
557 */
558#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF)
559#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8)
560
561/*
562 * clkpwr_uart_clk_ctrl register definitions
563 */
564#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3)
565#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2)
566#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1)
567#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0)
568
569/*
570 * clkpwr_dmaclk_ctrl register definitions
571 */
572#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1
573
574/*
575 * clkpwr_autoclock register definitions
576 */
577#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40
578#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02
579#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01
580
581/*
582 * Interrupt controller register offsets
583 */
584#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
585#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
586#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
587#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
588#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
589#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
590
591/*
592 * Timer/counter register offsets
593 */
594#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00)
595#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
596#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08)
597#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
598#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10)
599#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
600#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
601#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
602#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
603#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
604#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
605#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
606#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
607#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
608#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
609#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
610#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
611
612/*
613 * ir register definitions
614 */
615#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
616#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
617
618/*
619 * tcr register definitions
620 */
621#define LCP32XX_TIMER_CNTR_TCR_EN 0x1
622#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2
623
624/*
625 * mcr register definitions
626 */
627#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
628#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
629#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
630
631/*
632 * Standard UART register offsets
633 */
634#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00)
635#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04)
636#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08)
637#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C)
638#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10)
639#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14)
640#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18)
641#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C)
642
643/*
644 * UART control structure offsets
645 */
646#define _UCREG(x) io_p2v(\
647 LPC32XX_UART_CTRL_BASE + (x))
648#define LPC32XX_UARTCTL_CTRL _UCREG(0x00)
649#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04)
650#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08)
651
652/*
653 * ctrl register definitions
654 */
655#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11)
656#define LPC32XX_UART_IRRX6_INV_EN _BIT(10)
657#define LPC32XX_UART_HDPX_EN _BIT(9)
658#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5)
659#define LPC32XX_RT_IRTX6_INV_EN _BIT(4)
660#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3)
661#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2)
662#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1)
663#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0)
664
665/*
666 * clkmode register definitions
667 */
668#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F)
669#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1)
670#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14)
671#define LPC32XX_UART_CLKMODE_OFF 0x0
672#define LPC32XX_UART_CLKMODE_ON 0x1
673#define LPC32XX_UART_CLKMODE_AUTO 0x2
674#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4))
675#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4))
676
677/*
678 * GPIO Module Register offsets
679 */
680#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x))
681#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100)
682#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104)
683#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108)
684#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110)
685#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114)
686#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118)
687#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120)
688#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124)
689#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128)
690#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
691#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
692#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
693
694#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
new file mode 100644
index 000000000000..df3b0dea4d7b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
@@ -0,0 +1,52 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/system.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_SYSTEM_H
20#define __ASM_ARCH_SYSTEM_H
21
22static void arch_idle(void)
23{
24 cpu_do_idle();
25}
26
27static inline void arch_reset(char mode, const char *cmd)
28{
29 extern void lpc32xx_watchdog_reset(void);
30
31 switch (mode) {
32 case 's':
33 case 'h':
34 printk(KERN_CRIT "RESET: Rebooting system\n");
35
36 /* Disable interrupts */
37 local_irq_disable();
38
39 lpc32xx_watchdog_reset();
40 break;
41
42 default:
43 /* Do nothing */
44 break;
45 }
46
47 /* Wait for watchdog to reset system */
48 while (1)
49 ;
50}
51
52#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-lpc32xx/include/mach/timex.h
new file mode 100644
index 000000000000..8d4066b16b3f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/timex.h
@@ -0,0 +1,28 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/timex.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_TIMEX_H
20#define __ASM_ARCH_TIMEX_H
21
22/*
23 * Rate in Hz of the main system oscillator. This value should match
24 * the value 'MAIN_OSC_FREQ' in platform.h
25 */
26#define CLOCK_TICK_RATE 13000000
27
28#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c142487d299a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -0,0 +1,60 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/uncompress.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
20#define __ASM_ARM_ARCH_UNCOMPRESS_H
21
22#include <linux/io.h>
23
24#include <mach/hardware.h>
25#include <mach/platform.h>
26
27/*
28 * Uncompress output is hardcoded to standard UART 5
29 */
30
31#define UART_FIFO_CTL_TX_RESET (1 << 2)
32#define UART_STATUS_TX_MT (1 << 6)
33
34#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
35
36#define LPC32XX_UART_DLLFIFO_O 0x00
37#define LPC32XX_UART_IIRFCR_O 0x08
38#define LPC32XX_UART_LSR_O 0x14
39
40static inline void putc(int ch)
41{
42 /* Wait for transmit FIFO to empty */
43 while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
44 UART_STATUS_TX_MT) == 0)
45 ;
46
47 __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
48}
49
50static inline void flush(void)
51{
52 __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
53 UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
54}
55
56/* NULL functions; we don't presently need them */
57#define arch_decomp_setup()
58#define arch_decomp_wdog()
59
60#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..d1d936c7236d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_VMALLOC_H
20#define __ASM_ARCH_VMALLOC_H
21
22#define VMALLOC_END 0xF0000000
23
24#endif
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
new file mode 100644
index 000000000000..bd0df26c415b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -0,0 +1,432 @@
1/*
2 * arch/arm/mach-lpc32xx/irq.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/err.h>
24#include <linux/io.h>
25
26#include <mach/irqs.h>
27#include <mach/hardware.h>
28#include <mach/platform.h>
29#include "common.h"
30
31/*
32 * Default value representing the Activation polarity of all internal
33 * interrupt sources
34 */
35#define MIC_APR_DEFAULT 0x3FF0EFE0
36#define SIC1_APR_DEFAULT 0xFBD27186
37#define SIC2_APR_DEFAULT 0x801810C0
38
39/*
40 * Default value representing the Activation Type of all internal
41 * interrupt sources. All are level sensitive.
42 */
43#define MIC_ATR_DEFAULT 0x00000000
44#define SIC1_ATR_DEFAULT 0x00026000
45#define SIC2_ATR_DEFAULT 0x00000000
46
47struct lpc32xx_event_group_regs {
48 void __iomem *enab_reg;
49 void __iomem *edge_reg;
50 void __iomem *maskstat_reg;
51 void __iomem *rawstat_reg;
52};
53
54static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
55 .enab_reg = LPC32XX_CLKPWR_INT_ER,
56 .edge_reg = LPC32XX_CLKPWR_INT_AP,
57 .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
58 .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
59};
60
61static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
62 .enab_reg = LPC32XX_CLKPWR_PIN_ER,
63 .edge_reg = LPC32XX_CLKPWR_PIN_AP,
64 .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
65 .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
66};
67
68struct lpc32xx_event_info {
69 const struct lpc32xx_event_group_regs *event_group;
70 u32 mask;
71};
72
73/*
74 * Maps an IRQ number to and event mask and register
75 */
76static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
77 [IRQ_LPC32XX_GPI_08] = {
78 .event_group = &lpc32xx_event_pin_regs,
79 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
80 },
81 [IRQ_LPC32XX_GPI_09] = {
82 .event_group = &lpc32xx_event_pin_regs,
83 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
84 },
85 [IRQ_LPC32XX_GPI_19] = {
86 .event_group = &lpc32xx_event_pin_regs,
87 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
88 },
89 [IRQ_LPC32XX_GPI_07] = {
90 .event_group = &lpc32xx_event_pin_regs,
91 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
92 },
93 [IRQ_LPC32XX_GPI_00] = {
94 .event_group = &lpc32xx_event_pin_regs,
95 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
96 },
97 [IRQ_LPC32XX_GPI_01] = {
98 .event_group = &lpc32xx_event_pin_regs,
99 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
100 },
101 [IRQ_LPC32XX_GPI_02] = {
102 .event_group = &lpc32xx_event_pin_regs,
103 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
104 },
105 [IRQ_LPC32XX_GPI_03] = {
106 .event_group = &lpc32xx_event_pin_regs,
107 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
108 },
109 [IRQ_LPC32XX_GPI_04] = {
110 .event_group = &lpc32xx_event_pin_regs,
111 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
112 },
113 [IRQ_LPC32XX_GPI_05] = {
114 .event_group = &lpc32xx_event_pin_regs,
115 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
116 },
117 [IRQ_LPC32XX_GPI_06] = {
118 .event_group = &lpc32xx_event_pin_regs,
119 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
120 },
121 [IRQ_LPC32XX_GPIO_00] = {
122 .event_group = &lpc32xx_event_int_regs,
123 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
124 },
125 [IRQ_LPC32XX_GPIO_01] = {
126 .event_group = &lpc32xx_event_int_regs,
127 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
128 },
129 [IRQ_LPC32XX_GPIO_02] = {
130 .event_group = &lpc32xx_event_int_regs,
131 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
132 },
133 [IRQ_LPC32XX_GPIO_03] = {
134 .event_group = &lpc32xx_event_int_regs,
135 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
136 },
137 [IRQ_LPC32XX_GPIO_04] = {
138 .event_group = &lpc32xx_event_int_regs,
139 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
140 },
141 [IRQ_LPC32XX_GPIO_05] = {
142 .event_group = &lpc32xx_event_int_regs,
143 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
144 },
145 [IRQ_LPC32XX_KEY] = {
146 .event_group = &lpc32xx_event_int_regs,
147 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
148 },
149 [IRQ_LPC32XX_USB_OTG_ATX] = {
150 .event_group = &lpc32xx_event_int_regs,
151 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
152 },
153 [IRQ_LPC32XX_USB_HOST] = {
154 .event_group = &lpc32xx_event_int_regs,
155 .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
156 },
157 [IRQ_LPC32XX_RTC] = {
158 .event_group = &lpc32xx_event_int_regs,
159 .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
160 },
161 [IRQ_LPC32XX_MSTIMER] = {
162 .event_group = &lpc32xx_event_int_regs,
163 .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
164 },
165 [IRQ_LPC32XX_TS_AUX] = {
166 .event_group = &lpc32xx_event_int_regs,
167 .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
168 },
169 [IRQ_LPC32XX_TS_P] = {
170 .event_group = &lpc32xx_event_int_regs,
171 .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
172 },
173 [IRQ_LPC32XX_TS_IRQ] = {
174 .event_group = &lpc32xx_event_int_regs,
175 .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
176 },
177};
178
179static void get_controller(unsigned int irq, unsigned int *base,
180 unsigned int *irqbit)
181{
182 if (irq < 32) {
183 *base = LPC32XX_MIC_BASE;
184 *irqbit = 1 << irq;
185 } else if (irq < 64) {
186 *base = LPC32XX_SIC1_BASE;
187 *irqbit = 1 << (irq - 32);
188 } else {
189 *base = LPC32XX_SIC2_BASE;
190 *irqbit = 1 << (irq - 64);
191 }
192}
193
194static void lpc32xx_mask_irq(unsigned int irq)
195{
196 unsigned int reg, ctrl, mask;
197
198 get_controller(irq, &ctrl, &mask);
199
200 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
201 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
202}
203
204static void lpc32xx_unmask_irq(unsigned int irq)
205{
206 unsigned int reg, ctrl, mask;
207
208 get_controller(irq, &ctrl, &mask);
209
210 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
211 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
212}
213
214static void lpc32xx_ack_irq(unsigned int irq)
215{
216 unsigned int ctrl, mask;
217
218 get_controller(irq, &ctrl, &mask);
219
220 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
221
222 /* Also need to clear pending wake event */
223 if (lpc32xx_events[irq].mask != 0)
224 __raw_writel(lpc32xx_events[irq].mask,
225 lpc32xx_events[irq].event_group->rawstat_reg);
226}
227
228static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
229 int use_edge)
230{
231 unsigned int reg, ctrl, mask;
232
233 get_controller(irq, &ctrl, &mask);
234
235 /* Activation level, high or low */
236 reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
237 if (use_high_level)
238 reg |= mask;
239 else
240 reg &= ~mask;
241 __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
242
243 /* Activation type, edge or level */
244 reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
245 if (use_edge)
246 reg |= mask;
247 else
248 reg &= ~mask;
249 __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
250
251 /* Use same polarity for the wake events */
252 if (lpc32xx_events[irq].mask != 0) {
253 reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
254
255 if (use_high_level)
256 reg |= lpc32xx_events[irq].mask;
257 else
258 reg &= ~lpc32xx_events[irq].mask;
259
260 __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
261 }
262}
263
264static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
265{
266 switch (type) {
267 case IRQ_TYPE_EDGE_RISING:
268 /* Rising edge sensitive */
269 __lpc32xx_set_irq_type(irq, 1, 1);
270 break;
271
272 case IRQ_TYPE_EDGE_FALLING:
273 /* Falling edge sensitive */
274 __lpc32xx_set_irq_type(irq, 0, 1);
275 break;
276
277 case IRQ_TYPE_LEVEL_LOW:
278 /* Low level sensitive */
279 __lpc32xx_set_irq_type(irq, 0, 0);
280 break;
281
282 case IRQ_TYPE_LEVEL_HIGH:
283 /* High level sensitive */
284 __lpc32xx_set_irq_type(irq, 1, 0);
285 break;
286
287 /* Other modes are not supported */
288 default:
289 return -EINVAL;
290 }
291
292 /* Ok to use the level handler for all types */
293 set_irq_handler(irq, handle_level_irq);
294
295 return 0;
296}
297
298static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
299{
300 unsigned long eventreg;
301
302 if (lpc32xx_events[irqno].mask != 0) {
303 eventreg = __raw_readl(lpc32xx_events[irqno].
304 event_group->enab_reg);
305
306 if (state)
307 eventreg |= lpc32xx_events[irqno].mask;
308 else
309 eventreg &= ~lpc32xx_events[irqno].mask;
310
311 __raw_writel(eventreg,
312 lpc32xx_events[irqno].event_group->enab_reg);
313
314 return 0;
315 }
316
317 /* Clear event */
318 __raw_writel(lpc32xx_events[irqno].mask,
319 lpc32xx_events[irqno].event_group->rawstat_reg);
320
321 return -ENODEV;
322}
323
324static void __init lpc32xx_set_default_mappings(unsigned int apr,
325 unsigned int atr, unsigned int offset)
326{
327 unsigned int i;
328
329 /* Set activation levels for each interrupt */
330 i = 0;
331 while (i < 32) {
332 __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
333 ((atr >> i) & 0x1));
334 i++;
335 }
336}
337
338static struct irq_chip lpc32xx_irq_chip = {
339 .ack = lpc32xx_ack_irq,
340 .mask = lpc32xx_mask_irq,
341 .unmask = lpc32xx_unmask_irq,
342 .set_type = lpc32xx_set_irq_type,
343 .set_wake = lpc32xx_irq_wake
344};
345
346static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
347{
348 unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
349
350 while (ints != 0) {
351 int irqno = fls(ints) - 1;
352
353 ints &= ~(1 << irqno);
354
355 generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
356 }
357}
358
359static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
360{
361 unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
362
363 while (ints != 0) {
364 int irqno = fls(ints) - 1;
365
366 ints &= ~(1 << irqno);
367
368 generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
369 }
370}
371
372void __init lpc32xx_init_irq(void)
373{
374 unsigned int i;
375
376 /* Setup MIC */
377 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
378 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
379 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
380
381 /* Setup SIC1 */
382 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
383 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
384 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
385
386 /* Setup SIC2 */
387 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
388 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
389 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
390
391 /* Configure supported IRQ's */
392 for (i = 0; i < NR_IRQS; i++) {
393 set_irq_chip(i, &lpc32xx_irq_chip);
394 set_irq_handler(i, handle_level_irq);
395 set_irq_flags(i, IRQF_VALID);
396 }
397
398 /* Set default mappings */
399 lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
400 lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
401 lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
402
403 /* mask all interrupts except SUBIRQ */
404 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
405 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
406 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
407
408 /* MIC SUBIRQx interrupts will route handling to the chain handlers */
409 set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
410 set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
411
412 /* Initially disable all wake events */
413 __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
414 __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
415 __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
416
417 /*
418 * Default wake activation polarities, all pin sources are low edge
419 * triggered
420 */
421 __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
422 LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
423 LPC32XX_CLKPWR_INTSRC_RTC_BIT,
424 LPC32XX_CLKPWR_INT_AP);
425 __raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
426
427 /* Clear latched wake event states */
428 __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
429 LPC32XX_CLKPWR_PIN_RS);
430 __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
431 LPC32XX_CLKPWR_INT_RS);
432}
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
new file mode 100644
index 000000000000..bc9a42da2145
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -0,0 +1,397 @@
1/*
2 * arch/arm/mach-lpc32xx/phy3250.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/dma-mapping.h>
25#include <linux/device.h>
26#include <linux/spi/spi.h>
27#include <linux/spi/eeprom.h>
28#include <linux/leds.h>
29#include <linux/gpio.h>
30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h>
33
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37
38#include <mach/hardware.h>
39#include <mach/platform.h>
40#include "common.h"
41
42/*
43 * Mapped GPIOLIB GPIOs
44 */
45#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
46#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
47#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
48#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
49
50/*
51 * AMBA LCD controller
52 */
53static struct clcd_panel conn_lcd_panel = {
54 .mode = {
55 .name = "QVGA portrait",
56 .refresh = 60,
57 .xres = 240,
58 .yres = 320,
59 .pixclock = 191828,
60 .left_margin = 22,
61 .right_margin = 11,
62 .upper_margin = 2,
63 .lower_margin = 1,
64 .hsync_len = 5,
65 .vsync_len = 2,
66 .sync = 0,
67 .vmode = FB_VMODE_NONINTERLACED,
68 },
69 .width = -1,
70 .height = -1,
71 .tim2 = (TIM2_IVS | TIM2_IHS),
72 .cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
73 CNTL_LCDBPP16_565),
74 .bpp = 16,
75};
76#define PANEL_SIZE (3 * SZ_64K)
77
78static int lpc32xx_clcd_setup(struct clcd_fb *fb)
79{
80 dma_addr_t dma;
81
82 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
83 PANEL_SIZE, &dma, GFP_KERNEL);
84 if (!fb->fb.screen_base) {
85 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
86 return -ENOMEM;
87 }
88
89 fb->fb.fix.smem_start = dma;
90 fb->fb.fix.smem_len = PANEL_SIZE;
91 fb->panel = &conn_lcd_panel;
92
93 if (gpio_request(LCD_POWER_GPIO, "LCD power"))
94 printk(KERN_ERR "Error requesting gpio %u",
95 LCD_POWER_GPIO);
96 else if (gpio_direction_output(LCD_POWER_GPIO, 1))
97 printk(KERN_ERR "Error setting gpio %u to output",
98 LCD_POWER_GPIO);
99
100 if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
101 printk(KERN_ERR "Error requesting gpio %u",
102 BKL_POWER_GPIO);
103 else if (gpio_direction_output(BKL_POWER_GPIO, 1))
104 printk(KERN_ERR "Error setting gpio %u to output",
105 BKL_POWER_GPIO);
106
107 return 0;
108}
109
110static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
111{
112 return dma_mmap_writecombine(&fb->dev->dev, vma,
113 fb->fb.screen_base, fb->fb.fix.smem_start,
114 fb->fb.fix.smem_len);
115}
116
117static void lpc32xx_clcd_remove(struct clcd_fb *fb)
118{
119 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
120 fb->fb.screen_base, fb->fb.fix.smem_start);
121}
122
123/*
124 * On some early LCD modules (1307.0), the backlight logic is inverted.
125 * For those board variants, swap the disable and enable states for
126 * BKL_POWER_GPIO.
127*/
128static void clcd_disable(struct clcd_fb *fb)
129{
130 gpio_set_value(BKL_POWER_GPIO, 0);
131 gpio_set_value(LCD_POWER_GPIO, 0);
132}
133
134static void clcd_enable(struct clcd_fb *fb)
135{
136 gpio_set_value(BKL_POWER_GPIO, 1);
137 gpio_set_value(LCD_POWER_GPIO, 1);
138}
139
140static struct clcd_board lpc32xx_clcd_data = {
141 .name = "Phytec LCD",
142 .check = clcdfb_check,
143 .decode = clcdfb_decode,
144 .disable = clcd_disable,
145 .enable = clcd_enable,
146 .setup = lpc32xx_clcd_setup,
147 .mmap = lpc32xx_clcd_mmap,
148 .remove = lpc32xx_clcd_remove,
149};
150
151static struct amba_device lpc32xx_clcd_device = {
152 .dev = {
153 .coherent_dma_mask = ~0,
154 .init_name = "dev:clcd",
155 .platform_data = &lpc32xx_clcd_data,
156 },
157 .res = {
158 .start = LPC32XX_LCD_BASE,
159 .end = (LPC32XX_LCD_BASE + SZ_4K - 1),
160 .flags = IORESOURCE_MEM,
161 },
162 .dma_mask = ~0,
163 .irq = {IRQ_LPC32XX_LCD, NO_IRQ},
164};
165
166/*
167 * AMBA SSP (SPI)
168 */
169static void phy3250_spi_cs_set(u32 control)
170{
171 gpio_set_value(SPI0_CS_GPIO, (int) control);
172}
173
174static struct pl022_config_chip spi0_chip_info = {
175 .lbm = LOOPBACK_DISABLED,
176 .com_mode = INTERRUPT_TRANSFER,
177 .iface = SSP_INTERFACE_MOTOROLA_SPI,
178 .hierarchy = SSP_MASTER,
179 .slave_tx_disable = 0,
180 .endian_tx = SSP_TX_LSB,
181 .endian_rx = SSP_RX_LSB,
182 .data_size = SSP_DATA_BITS_8,
183 .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
184 .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
185 .clk_phase = SSP_CLK_FIRST_EDGE,
186 .clk_pol = SSP_CLK_POL_IDLE_LOW,
187 .ctrl_len = SSP_BITS_8,
188 .wait_state = SSP_MWIRE_WAIT_ZERO,
189 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
190 .cs_control = phy3250_spi_cs_set,
191};
192
193static struct pl022_ssp_controller lpc32xx_ssp0_data = {
194 .bus_id = 0,
195 .num_chipselect = 1,
196 .enable_dma = 0,
197};
198
199static struct amba_device lpc32xx_ssp0_device = {
200 .dev = {
201 .coherent_dma_mask = ~0,
202 .init_name = "dev:ssp0",
203 .platform_data = &lpc32xx_ssp0_data,
204 },
205 .res = {
206 .start = LPC32XX_SSP0_BASE,
207 .end = (LPC32XX_SSP0_BASE + SZ_4K - 1),
208 .flags = IORESOURCE_MEM,
209 },
210 .dma_mask = ~0,
211 .irq = {IRQ_LPC32XX_SSP0, NO_IRQ},
212};
213
214/* AT25 driver registration */
215static int __init phy3250_spi_board_register(void)
216{
217#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
218 static struct spi_board_info info[] = {
219 {
220 .modalias = "spidev",
221 .max_speed_hz = 5000000,
222 .bus_num = 0,
223 .chip_select = 0,
224 .controller_data = &spi0_chip_info,
225 },
226 };
227
228#else
229 static struct spi_eeprom eeprom = {
230 .name = "at25256a",
231 .byte_len = 0x8000,
232 .page_size = 64,
233 .flags = EE_ADDR2,
234 };
235
236 static struct spi_board_info info[] = {
237 {
238 .modalias = "at25",
239 .max_speed_hz = 5000000,
240 .bus_num = 0,
241 .chip_select = 0,
242 .platform_data = &eeprom,
243 .controller_data = &spi0_chip_info,
244 },
245 };
246#endif
247 return spi_register_board_info(info, ARRAY_SIZE(info));
248}
249arch_initcall(phy3250_spi_board_register);
250
251static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
252 {
253 I2C_BOARD_INFO("pcf8563", 0x51),
254 },
255};
256
257static struct gpio_led phy_leds[] = {
258 {
259 .name = "led0",
260 .gpio = LED_GPIO,
261 .active_low = 1,
262 .default_trigger = "heartbeat",
263 },
264};
265
266static struct gpio_led_platform_data led_data = {
267 .leds = phy_leds,
268 .num_leds = ARRAY_SIZE(phy_leds),
269};
270
271static struct platform_device lpc32xx_gpio_led_device = {
272 .name = "leds-gpio",
273 .id = -1,
274 .dev.platform_data = &led_data,
275};
276
277static struct platform_device *phy3250_devs[] __initdata = {
278 &lpc32xx_i2c0_device,
279 &lpc32xx_i2c1_device,
280 &lpc32xx_i2c2_device,
281 &lpc32xx_watchdog_device,
282 &lpc32xx_gpio_led_device,
283};
284
285static struct amba_device *amba_devs[] __initdata = {
286 &lpc32xx_clcd_device,
287 &lpc32xx_ssp0_device,
288};
289
290/*
291 * Board specific functions
292 */
293static void __init phy3250_board_init(void)
294{
295 u32 tmp;
296 int i;
297
298 lpc32xx_gpio_init();
299
300 /* Register GPIOs used on this board */
301 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
302 printk(KERN_ERR "Error requesting gpio %u",
303 SPI0_CS_GPIO);
304 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
305 printk(KERN_ERR "Error setting gpio %u to output",
306 SPI0_CS_GPIO);
307
308 /* Setup network interface for RMII mode */
309 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
310 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
311 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
312 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
313
314 /* Setup SLC NAND controller muxing */
315 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
316 LPC32XX_CLKPWR_NAND_CLK_CTRL);
317
318 /* Setup LCD muxing to RGB565 */
319 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
320 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
321 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
322 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
323 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
324
325 /* Set up I2C pull levels */
326 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
327 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
328 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
329 __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
330
331 /* Disable IrDA pulsing support on UART6 */
332 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
333 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
334 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
335
336 /* Enable DMA for I2S1 channel */
337 tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
338 tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
339 __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
340
341 lpc32xx_serial_init();
342
343 /*
344 * AMBA peripheral clocks need to be enabled prior to AMBA device
345 * detection or a data fault will occur, so enable the clocks
346 * here. However, we don't want to enable them if the peripheral
347 * isn't included in the image
348 */
349#ifdef CONFIG_FB_ARMCLCD
350 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
351 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
352 LPC32XX_CLKPWR_LCDCLK_CTRL);
353#endif
354#ifdef CONFIG_SPI_PL022
355 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
356 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
357 LPC32XX_CLKPWR_SSP_CLK_CTRL);
358#endif
359
360 platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
361 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
362 struct amba_device *d = amba_devs[i];
363 amba_device_register(d, &iomem_resource);
364 }
365
366 /* Test clock needed for UDA1380 initial init */
367 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
368 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
369 LPC32XX_CLKPWR_TEST_CLK_SEL);
370
371 i2c_register_board_info(0, phy3250_i2c_board_info,
372 ARRAY_SIZE(phy3250_i2c_board_info));
373}
374
375static int __init lpc32xx_display_uid(void)
376{
377 u32 uid[4];
378
379 lpc32xx_get_uid(uid);
380
381 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
382 uid[3], uid[2], uid[1], uid[0]);
383
384 return 1;
385}
386arch_initcall(lpc32xx_display_uid);
387
388MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
389 /* Maintainer: Kevin Wells, NXP Semiconductors */
390 .phys_io = LPC32XX_UART5_BASE,
391 .io_pg_offst = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
392 .boot_params = 0x80000100,
393 .map_io = lpc32xx_map_io,
394 .init_irq = lpc32xx_init_irq,
395 .timer = &lpc32xx_timer,
396 .init_machine = phy3250_board_init,
397MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
new file mode 100644
index 000000000000..a6e2aed9a49f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -0,0 +1,146 @@
1/*
2 * arch/arm/mach-lpc32xx/pm.c
3 *
4 * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
5 * Modified by Kevin Wells <kevin.wells@nxp.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * LPC32XX CPU and system power management
15 *
16 * The LCP32XX has three CPU modes for controlling system power: run,
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
19 * mode is not used in normal operation. Halt mode is used when the
20 * system is fully suspended.
21 *
22 * Run mode:
23 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
24 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
25 * the HCLK_PLL rate. Linux runs in this mode.
26 *
27 * Direct-run mode:
28 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
29 * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
30 * source or the frequency of the main oscillator. In this mode, the
31 * HCLK_PLL can be safely enabled, changed, or disabled.
32 *
33 * Halt mode:
34 * SYSCLK is gated off and the CPU and system clocks are halted.
35 * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
36 * key scanner, etc.) still operate if enabled. In this state, an enabled
37 * system event (ie, GPIO state change, RTC match, key press, etc.) will
38 * wake the system up back into direct-run mode.
39 *
40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
42 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transistion to direct-run mode will stop all DDR accesses (no clocks).
45 * Because of this, the code to switch power modes and the code to enter
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
47 * section of IRAM is used instead for this.
48 *
49 * Suspend is handled with the following logic:
50 * Backup a small area of IRAM used for the suspend code
51 * Copy suspend code to IRAM
52 * Transfer control to code in IRAM
53 * Places DRAMs in self-refresh mode
54 * Enter direct-run mode
55 * Save state of HCLK_PLL PLL
56 * Disable HCLK_PLL PLL
57 * Enter halt mode - CPU and buses will stop
58 * System enters direct-run mode when an enabled event occurs
59 * HCLK PLL state is restored
60 * Run mode is entered
61 * DRAMS are placed back into normal mode
62 * Code execution returns from IRAM
63 * IRAM code are used for suspend is restored
64 * Suspend mode is exited
65 */
66
67#include <linux/suspend.h>
68#include <linux/io.h>
69#include <linux/slab.h>
70
71#include <asm/cacheflush.h>
72
73#include <mach/hardware.h>
74#include <mach/platform.h>
75#include "common.h"
76#include "clock.h"
77
78#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
79
80/*
81 * Both STANDBY and MEM suspend states are handled the same with no
82 * loss of CPU or memory state
83 */
84static int lpc32xx_pm_enter(suspend_state_t state)
85{
86 int (*lpc32xx_suspend_ptr) (void);
87 void *iram_swap_area;
88
89 /* Allocate some space for temporary IRAM storage */
90 iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
91 if (!iram_swap_area) {
92 printk(KERN_ERR
93 "PM Suspend: cannot allocate memory to save portion "
94 "of SRAM\n");
95 return -ENOMEM;
96 }
97
98 /* Backup a small area of IRAM used for the suspend code */
99 memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
100 lpc32xx_sys_suspend_sz);
101
102 /*
103 * Copy code to suspend system into IRAM. The suspend code
104 * needs to run from IRAM as DRAM may no longer be available
105 * when the PLL is stopped.
106 */
107 memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
108 lpc32xx_sys_suspend_sz);
109 flush_icache_range((unsigned long)TEMP_IRAM_AREA,
110 (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
111
112 /* Transfer to suspend code in IRAM */
113 lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
114 flush_cache_all();
115 (void) lpc32xx_suspend_ptr();
116
117 /* Restore original IRAM contents */
118 memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
119 lpc32xx_sys_suspend_sz);
120
121 kfree(iram_swap_area);
122
123 return 0;
124}
125
126static struct platform_suspend_ops lpc32xx_pm_ops = {
127 .valid = suspend_valid_only_mem,
128 .enter = lpc32xx_pm_enter,
129};
130
131#define EMC_DYN_MEM_CTRL_OFS 0x20
132#define EMC_SRMMC (1 << 3)
133#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
134static int __init lpc32xx_pm_init(void)
135{
136 /*
137 * Setup SDRAM self-refresh clock to automatically disable o
138 * start of self-refresh. This only needs to be done once.
139 */
140 __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
141
142 suspend_set_ops(&lpc32xx_pm_ops);
143
144 return 0;
145}
146arch_initcall(lpc32xx_pm_init);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
new file mode 100644
index 000000000000..429cfdbb2b3d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -0,0 +1,190 @@
1/*
2 * arch/arm/mach-lpc32xx/serial.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/serial.h>
22#include <linux/serial_core.h>
23#include <linux/serial_reg.h>
24#include <linux/serial_8250.h>
25#include <linux/clk.h>
26#include <linux/io.h>
27
28#include <mach/hardware.h>
29#include <mach/platform.h>
30#include "common.h"
31
32#define LPC32XX_SUART_FIFO_SIZE 64
33
34/* Standard 8250/16550 compatible serial ports */
35static struct plat_serial8250_port serial_std_platform_data[] = {
36#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
37 {
38 .membase = io_p2v(LPC32XX_UART5_BASE),
39 .mapbase = LPC32XX_UART5_BASE,
40 .irq = IRQ_LPC32XX_UART_IIR5,
41 .uartclk = LPC32XX_MAIN_OSC_FREQ,
42 .regshift = 2,
43 .iotype = UPIO_MEM32,
44 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
45 UPF_SKIP_TEST,
46 },
47#endif
48#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
49 {
50 .membase = io_p2v(LPC32XX_UART3_BASE),
51 .mapbase = LPC32XX_UART3_BASE,
52 .irq = IRQ_LPC32XX_UART_IIR3,
53 .uartclk = LPC32XX_MAIN_OSC_FREQ,
54 .regshift = 2,
55 .iotype = UPIO_MEM32,
56 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
57 UPF_SKIP_TEST,
58 },
59#endif
60#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
61 {
62 .membase = io_p2v(LPC32XX_UART4_BASE),
63 .mapbase = LPC32XX_UART4_BASE,
64 .irq = IRQ_LPC32XX_UART_IIR4,
65 .uartclk = LPC32XX_MAIN_OSC_FREQ,
66 .regshift = 2,
67 .iotype = UPIO_MEM32,
68 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
69 UPF_SKIP_TEST,
70 },
71#endif
72#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
73 {
74 .membase = io_p2v(LPC32XX_UART6_BASE),
75 .mapbase = LPC32XX_UART6_BASE,
76 .irq = IRQ_LPC32XX_UART_IIR6,
77 .uartclk = LPC32XX_MAIN_OSC_FREQ,
78 .regshift = 2,
79 .iotype = UPIO_MEM32,
80 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
81 UPF_SKIP_TEST,
82 },
83#endif
84 { },
85};
86
87struct uartinit {
88 char *uart_ck_name;
89 u32 ck_mode_mask;
90 void __iomem *pdiv_clk_reg;
91};
92
93static struct uartinit uartinit_data[] __initdata = {
94#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
95 {
96 .uart_ck_name = "uart5_ck",
97 .ck_mode_mask =
98 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
99 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
100 },
101#endif
102#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
103 {
104 .uart_ck_name = "uart3_ck",
105 .ck_mode_mask =
106 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
107 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
108 },
109#endif
110#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
111 {
112 .uart_ck_name = "uart4_ck",
113 .ck_mode_mask =
114 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
115 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
116 },
117#endif
118#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
119 {
120 .uart_ck_name = "uart6_ck",
121 .ck_mode_mask =
122 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
123 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
124 },
125#endif
126};
127
128static struct platform_device serial_std_platform_device = {
129 .name = "serial8250",
130 .id = 0,
131 .dev = {
132 .platform_data = serial_std_platform_data,
133 },
134};
135
136static struct platform_device *lpc32xx_serial_devs[] __initdata = {
137 &serial_std_platform_device,
138};
139
140void __init lpc32xx_serial_init(void)
141{
142 u32 tmp, clkmodes = 0;
143 struct clk *clk;
144 unsigned int puart;
145 int i, j;
146
147 /* UART clocks are off, let clock driver manage them */
148 __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
149
150 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
151 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
152 if (!IS_ERR(clk)) {
153 clk_enable(clk);
154 serial_std_platform_data[i].uartclk =
155 clk_get_rate(clk);
156 }
157
158 /* Fall back on main osc rate if clock rate return fails */
159 if (serial_std_platform_data[i].uartclk == 0)
160 serial_std_platform_data[i].uartclk =
161 LPC32XX_MAIN_OSC_FREQ;
162
163 /* Setup UART clock modes for all UARTs, disable autoclock */
164 clkmodes |= uartinit_data[i].ck_mode_mask;
165
166 /* pre-UART clock divider set to 1 */
167 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
168 }
169
170 /* This needs to be done after all UART clocks are setup */
171 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
172 for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
173 /* Force a flush of the RX FIFOs to work around a HW bug */
174 puart = serial_std_platform_data[i].mapbase;
175 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
176 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
177 j = LPC32XX_SUART_FIFO_SIZE;
178 while (j--)
179 tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
180 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
181 }
182
183 /* Disable UART5->USB transparent mode or USB won't work */
184 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
185 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
186 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
187
188 platform_add_devices(lpc32xx_serial_devs,
189 ARRAY_SIZE(lpc32xx_serial_devs));
190}
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
new file mode 100644
index 000000000000..374f9f07fe48
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -0,0 +1,151 @@
1/*
2 * arch/arm/mach-lpc32xx/suspend.S
3 *
4 * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
5 * Modified by Kevin Wells <kevin.wells@nxp.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <mach/platform.h>
15#include <mach/hardware.h>
16
17/* Using named register defines makes the code easier to follow */
18#define WORK1_REG r0
19#define WORK2_REG r1
20#define SAVED_HCLK_DIV_REG r2
21#define SAVED_HCLK_PLL_REG r3
22#define SAVED_DRAM_CLKCTRL_REG r4
23#define SAVED_PWR_CTRL_REG r5
24#define CLKPWRBASE_REG r6
25#define EMCBASE_REG r7
26
27#define LPC32XX_EMC_STATUS_OFFS 0x04
28#define LPC32XX_EMC_STATUS_BUSY 0x1
29#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
30
31#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
32#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
33#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
34
35#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
36
37 .text
38
39ENTRY(lpc32xx_sys_suspend)
40 @ Save a copy of the used registers in IRAM, r0 is corrupted
41 adr r0, tmp_stack_end
42 stmfd r0!, {r3 - r7, sp, lr}
43
44 @ Load a few common register addresses
45 adr WORK1_REG, reg_bases
46 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
47 ldr EMCBASE_REG, [WORK1_REG, #4]
48
49 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
50 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
51 orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
52
53 @ Wait for SDRAM busy status to go busy and then idle
54 @ This guarantees a small windows where DRAM isn't busy
551:
56 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
57 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
58 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
59 bne 1b @ Branch while idle
602:
61 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
62 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
63 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
64 beq 2b @ Branch until idle
65
66 @ Setup self-refresh with support for manual exit of
67 @ self-refresh mode
68 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
69 orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
70 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
71 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
72
73 @ Wait for self-refresh acknowledge, clocks to the DRAM device
74 @ will automatically stop on start of self-refresh
753:
76 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
77 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
78 cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
79 bne 3b @ Branch until self-refresh mode starts
80
81 @ Enter direct-run mode from run mode
82 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
83 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
84
85 @ Safe disable of DRAM clock in EMC block, prevents DDR sync
86 @ issues on restart
87 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
88 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
89 and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
90 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
91
92 @ Save HCLK PLL state and disable HCLK PLL
93 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
94 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
95 bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
96 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
97
98 @ Enter stop mode until an enabled event occurs
99 orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
100 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
101 .rept 9
102 nop
103 .endr
104
105 @ Clear stop status
106 bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
107
108 @ Restore original HCLK PLL value and wait for PLL lock
109 str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
110 #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
1114:
112 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
113 and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
114 bne 4b
115
116 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
117 @ update yet. DRAM is still in self-refresh
118 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
119 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
120
121 @ Restore original DRAM clock mode to restore DRAM clocks
122 str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
123 #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
124
125 @ Clear self-refresh mode
126 orr WORK1_REG, SAVED_PWR_CTRL_REG,\
127 #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
128 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
129 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
130 #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
131
132 @ Wait for EMC to clear self-refresh mode
1335:
134 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
135 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
136 bne 5b @ Branch until self-refresh has exited
137
138 @ restore regs and return
139 adr r0, tmp_stack
140 ldmfd r0!, {r3 - r7, sp, pc}
141
142reg_bases:
143 .long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
144 .long IO_ADDRESS(LPC32XX_EMC_BASE)
145
146tmp_stack:
147 .long 0, 0, 0, 0, 0, 0, 0
148tmp_stack_end:
149
150ENTRY(lpc32xx_sys_suspend_sz)
151 .word . - lpc32xx_sys_suspend
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
new file mode 100644
index 000000000000..630dd4a74b26
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -0,0 +1,182 @@
1/*
2 * arch/arm/mach-lpc32xx/timer.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2009 - 2010 NXP Semiconductors
7 * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
8 * Ed Schouten <e.schouten@fontys.nl>
9 * Laurens Timmermans <l.timmermans@fontys.nl>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/time.h>
25#include <linux/err.h>
26#include <linux/clockchips.h>
27
28#include <asm/mach/time.h>
29
30#include <mach/hardware.h>
31#include <mach/platform.h>
32#include "common.h"
33
34static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
35{
36 return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
37}
38
39static struct clocksource lpc32xx_clksrc = {
40 .name = "lpc32xx_clksrc",
41 .shift = 24,
42 .rating = 300,
43 .read = lpc32xx_clksrc_read,
44 .mask = CLOCKSOURCE_MASK(32),
45 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
46};
47
48static int lpc32xx_clkevt_next_event(unsigned long delta,
49 struct clock_event_device *dev)
50{
51 __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
52 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
53 __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
54 __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
55 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
56
57 return 0;
58}
59
60static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
61 struct clock_event_device *dev)
62{
63 switch (mode) {
64 case CLOCK_EVT_MODE_PERIODIC:
65 WARN_ON(1);
66 break;
67
68 case CLOCK_EVT_MODE_ONESHOT:
69 case CLOCK_EVT_MODE_SHUTDOWN:
70 /*
71 * Disable the timer. When using oneshot, we must also
72 * disable the timer to wait for the first call to
73 * set_next_event().
74 */
75 __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
76 break;
77
78 case CLOCK_EVT_MODE_UNUSED:
79 case CLOCK_EVT_MODE_RESUME:
80 break;
81 }
82}
83
84static struct clock_event_device lpc32xx_clkevt = {
85 .name = "lpc32xx_clkevt",
86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 .shift = 32,
88 .rating = 300,
89 .set_next_event = lpc32xx_clkevt_next_event,
90 .set_mode = lpc32xx_clkevt_mode,
91};
92
93static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
94{
95 struct clock_event_device *evt = &lpc32xx_clkevt;
96
97 /* Clear match */
98 __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
99 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
100
101 evt->event_handler(evt);
102
103 return IRQ_HANDLED;
104}
105
106static struct irqaction lpc32xx_timer_irq = {
107 .name = "LPC32XX Timer Tick",
108 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
109 .handler = lpc32xx_timer_interrupt,
110};
111
112/*
113 * The clock management driver isn't initialized at this point, so the
114 * clocks need to be enabled here manually and then tagged as used in
115 * the clock driver initialization
116 */
117static void __init lpc32xx_timer_init(void)
118{
119 u32 clkrate, pllreg;
120
121 /* Enable timer clock */
122 __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
123 LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
124 LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
125
126 /*
127 * The clock driver isn't initialized at this point. So determine if
128 * the SYSCLK is driven from the PLL397 or main oscillator and then use
129 * it to compute the PLL frequency and the PCLK divider to get the base
130 * timer rates. This rate is needed to compute the tick rate.
131 */
132 if (clk_is_sysclk_mainosc() != 0)
133 clkrate = LPC32XX_MAIN_OSC_FREQ;
134 else
135 clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
136
137 /* Get ARM HCLKPLL register and convert it into a frequency */
138 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
139 clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
140
141 /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
142 clkrate = clkrate / clk_get_pclk_div();
143
144 /* Initial timer setup */
145 __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
146 __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
147 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
148 __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
149 __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
150 LCP32XX_TIMER_CNTR_MCR_STOP(0) |
151 LCP32XX_TIMER_CNTR_MCR_RESET(0),
152 LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
153
154 /* Setup tick interrupt */
155 setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
156
157 /* Setup the clockevent structure. */
158 lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
159 lpc32xx_clkevt.shift);
160 lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
161 &lpc32xx_clkevt);
162 lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
163 &lpc32xx_clkevt) + 1;
164 lpc32xx_clkevt.cpumask = cpumask_of(0);
165 clockevents_register_device(&lpc32xx_clkevt);
166
167 /* Use timer1 as clock source. */
168 __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
169 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
170 __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
171 __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
172 __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
173 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
174 lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
175 lpc32xx_clksrc.shift);
176 clocksource_register(&lpc32xx_clksrc);
177}
178
179struct sys_timer lpc32xx_timer = {
180 .init = &lpc32xx_timer_init,
181};
182
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 66677f0acaed..7ff8020d4d24 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o 15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
16obj-$(CONFIG_MSM_SMD) += last_radio_log.o 16obj-$(CONFIG_MSM_SMD) += last_radio_log.o
17 17
18obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o 18obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o
19obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o 19obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
20obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o 20obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
21obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o 21obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
new file mode 100644
index 000000000000..523d213bf79e
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -0,0 +1,112 @@
1/*
2 * linux/arch/arm/mach-msm/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 * Copyright (C) 2008 Google, Inc.
6 * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/gpio.h>
19
20#include "board-trout.h"
21
22struct msm_gpio_chip {
23 struct gpio_chip chip;
24 void __iomem *reg; /* Base of register bank */
25 u8 shadow;
26};
27
28#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
29
30static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
31{
32 struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
33 unsigned mask = 1 << offset;
34
35 return !!(readb(msm_gpio->reg) & mask);
36}
37
38static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
39{
40 struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
41 unsigned mask = 1 << offset;
42
43 if (val)
44 msm_gpio->shadow |= mask;
45 else
46 msm_gpio->shadow &= ~mask;
47
48 writeb(msm_gpio->shadow, msm_gpio->reg);
49}
50
51static int msm_gpiolib_direction_input(struct gpio_chip *chip,
52 unsigned offset)
53{
54 msm_gpiolib_set(chip, offset, 0);
55 return 0;
56}
57
58static int msm_gpiolib_direction_output(struct gpio_chip *chip,
59 unsigned offset, int val)
60{
61 msm_gpiolib_set(chip, offset, val);
62 return 0;
63}
64
65#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \
66 { \
67 .chip = { \
68 .label = name, \
69 .direction_input = msm_gpiolib_direction_input,\
70 .direction_output = msm_gpiolib_direction_output, \
71 .get = msm_gpiolib_get, \
72 .set = msm_gpiolib_set, \
73 .base = base_gpio, \
74 .ngpio = 8, \
75 }, \
76 .reg = (void *) reg_num + TROUT_CPLD_BASE, \
77 .shadow = shadow_val, \
78 }
79
80static struct msm_gpio_chip msm_gpio_banks[] = {
81#if defined(CONFIG_MSM_DEBUG_UART1)
82 /* H2W pins <-> UART1 */
83 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),
84#else
85 /* H2W pins <-> UART3, Bluetooth <-> UART1 */
86 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x80),
87#endif
88 /* I2C pull */
89 TROUT_GPIO_BANK("MISC3", 0x02, TROUT_GPIO_MISC3_BASE, 0x04),
90 TROUT_GPIO_BANK("MISC4", 0x04, TROUT_GPIO_MISC4_BASE, 0),
91 /* mmdi 32k en */
92 TROUT_GPIO_BANK("MISC5", 0x06, TROUT_GPIO_MISC5_BASE, 0x04),
93 TROUT_GPIO_BANK("INT2", 0x08, TROUT_GPIO_INT2_BASE, 0),
94 TROUT_GPIO_BANK("MISC1", 0x0a, TROUT_GPIO_MISC1_BASE, 0),
95 TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
96};
97
98/*
99 * Called from the processor-specific init to enable GPIO pin support.
100 */
101int __init trout_init_gpio(void)
102{
103 int i;
104
105 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
106 gpiochip_add(&msm_gpio_banks[i].chip);
107
108 return 0;
109}
110
111postcore_initcall(trout_init_gpio);
112
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index dca5a5f062dc..e69a1502e4e8 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -50,7 +50,6 @@ static void __init trout_fixup(struct machine_desc *desc, struct tag *tags,
50{ 50{
51 mi->nr_banks = 1; 51 mi->nr_banks = 1;
52 mi->bank[0].start = PHYS_OFFSET; 52 mi->bank[0].start = PHYS_OFFSET;
53 mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
54 mi->bank[0].size = (101*1024*1024); 53 mi->bank[0].size = (101*1024*1024);
55} 54}
56 55
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 4f345a5a0a61..651851c3e1dd 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -1,5 +1,162 @@
1/* linux/arch/arm/mach-msm/board-trout.h
2** Author: Brian Swetland <swetland@google.com>
3*/
4#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
5#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
6
7#include <mach/board.h>
8
9#define MSM_SMI_BASE 0x00000000
10#define MSM_SMI_SIZE 0x00800000
11
12#define MSM_EBI_BASE 0x10000000
13#define MSM_EBI_SIZE 0x06e00000
14
15#define MSM_PMEM_GPU0_BASE 0x00000000
16#define MSM_PMEM_GPU0_SIZE 0x00700000
17
18#define MSM_PMEM_MDP_BASE 0x02000000
19#define MSM_PMEM_MDP_SIZE 0x00800000
20
21#define MSM_PMEM_ADSP_BASE 0x02800000
22#define MSM_PMEM_ADSP_SIZE 0x00800000
23
24#define MSM_PMEM_CAMERA_BASE 0x03000000
25#define MSM_PMEM_CAMERA_SIZE 0x00800000
26
27#define MSM_FB_BASE 0x03800000
28#define MSM_FB_SIZE 0x00100000
29
30#define MSM_LINUX_BASE MSM_EBI_BASE
31#define MSM_LINUX_SIZE 0x06500000
32
33#define MSM_PMEM_GPU1_SIZE 0x800000
34#define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
35
36#define MSM_RAM_CONSOLE_BASE (MSM_EBI_BASE + 0x6d00000)
37#define MSM_RAM_CONSOLE_SIZE (128 * SZ_1K)
38
39#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
40#error invalid memory map
41#endif
42
43#define DECLARE_MSM_IOMAP
44#include <mach/msm_iomap.h>
45
46#define TROUT_4_BALL_UP_0 1
47#define TROUT_4_BALL_LEFT_0 18
48#define TROUT_4_BALL_DOWN_0 57
49#define TROUT_4_BALL_RIGHT_0 91
50
51#define TROUT_5_BALL_UP_0 94
52#define TROUT_5_BALL_LEFT_0 18
53#define TROUT_5_BALL_DOWN_0 90
54#define TROUT_5_BALL_RIGHT_0 19
55
56#define TROUT_POWER_KEY 20
57
58#define TROUT_4_TP_LS_EN 19
59#define TROUT_5_TP_LS_EN 1
1 60
2#define TROUT_CPLD_BASE 0xE8100000 61#define TROUT_CPLD_BASE 0xE8100000
3#define TROUT_CPLD_START 0x98000000 62#define TROUT_CPLD_START 0x98000000
4#define TROUT_CPLD_SIZE SZ_4K 63#define TROUT_CPLD_SIZE SZ_4K
5 64
65#define TROUT_GPIO_CABLE_IN1 (83)
66#define TROUT_GPIO_CABLE_IN2 (49)
67
68#define TROUT_GPIO_START (128)
69
70#define TROUT_GPIO_INT_MASK0_REG (0x0c)
71#define TROUT_GPIO_INT_STAT0_REG (0x0e)
72#define TROUT_GPIO_INT_MASK1_REG (0x14)
73#define TROUT_GPIO_INT_STAT1_REG (0x10)
74
75#define TROUT_GPIO_HAPTIC_PWM (28)
76#define TROUT_GPIO_PS_HOLD (25)
77
78#define TROUT_GPIO_MISC2_BASE (TROUT_GPIO_START + 0x00)
79#define TROUT_GPIO_MISC3_BASE (TROUT_GPIO_START + 0x08)
80#define TROUT_GPIO_MISC4_BASE (TROUT_GPIO_START + 0x10)
81#define TROUT_GPIO_MISC5_BASE (TROUT_GPIO_START + 0x18)
82#define TROUT_GPIO_INT2_BASE (TROUT_GPIO_START + 0x20)
83#define TROUT_GPIO_MISC1_BASE (TROUT_GPIO_START + 0x28)
84#define TROUT_GPIO_VIRTUAL_BASE (TROUT_GPIO_START + 0x30)
85#define TROUT_GPIO_INT5_BASE (TROUT_GPIO_START + 0x48)
86
87#define TROUT_GPIO_CHARGER_EN (TROUT_GPIO_MISC2_BASE + 0)
88#define TROUT_GPIO_ISET (TROUT_GPIO_MISC2_BASE + 1)
89#define TROUT_GPIO_H2W_DAT_DIR (TROUT_GPIO_MISC2_BASE + 2)
90#define TROUT_GPIO_H2W_CLK_DIR (TROUT_GPIO_MISC2_BASE + 3)
91#define TROUT_GPIO_H2W_DAT_GPO (TROUT_GPIO_MISC2_BASE + 4)
92#define TROUT_GPIO_H2W_CLK_GPO (TROUT_GPIO_MISC2_BASE + 5)
93#define TROUT_GPIO_H2W_SEL0 (TROUT_GPIO_MISC2_BASE + 6)
94#define TROUT_GPIO_H2W_SEL1 (TROUT_GPIO_MISC2_BASE + 7)
95
96#define TROUT_GPIO_SPOTLIGHT_EN (TROUT_GPIO_MISC3_BASE + 0)
97#define TROUT_GPIO_FLASH_EN (TROUT_GPIO_MISC3_BASE + 1)
98#define TROUT_GPIO_I2C_PULL (TROUT_GPIO_MISC3_BASE + 2)
99#define TROUT_GPIO_TP_I2C_PULL (TROUT_GPIO_MISC3_BASE + 3)
100#define TROUT_GPIO_TP_EN (TROUT_GPIO_MISC3_BASE + 4)
101#define TROUT_GPIO_JOG_EN (TROUT_GPIO_MISC3_BASE + 5)
102#define TROUT_GPIO_UI_LED_EN (TROUT_GPIO_MISC3_BASE + 6)
103#define TROUT_GPIO_QTKEY_LED_EN (TROUT_GPIO_MISC3_BASE + 7)
104
105#define TROUT_GPIO_VCM_PWDN (TROUT_GPIO_MISC4_BASE + 0)
106#define TROUT_GPIO_USB_H2W_SW (TROUT_GPIO_MISC4_BASE + 1)
107#define TROUT_GPIO_COMPASS_RST_N (TROUT_GPIO_MISC4_BASE + 2)
108#define TROUT_GPIO_HAPTIC_EN_UP (TROUT_GPIO_MISC4_BASE + 3)
109#define TROUT_GPIO_HAPTIC_EN_MAIN (TROUT_GPIO_MISC4_BASE + 4)
110#define TROUT_GPIO_USB_PHY_RST_N (TROUT_GPIO_MISC4_BASE + 5)
111#define TROUT_GPIO_WIFI_PA_RESETX (TROUT_GPIO_MISC4_BASE + 6)
112#define TROUT_GPIO_WIFI_EN (TROUT_GPIO_MISC4_BASE + 7)
113
114#define TROUT_GPIO_BT_32K_EN (TROUT_GPIO_MISC5_BASE + 0)
115#define TROUT_GPIO_MAC_32K_EN (TROUT_GPIO_MISC5_BASE + 1)
116#define TROUT_GPIO_MDDI_32K_EN (TROUT_GPIO_MISC5_BASE + 2)
117#define TROUT_GPIO_COMPASS_32K_EN (TROUT_GPIO_MISC5_BASE + 3)
118
119#define TROUT_GPIO_NAVI_ACT_N (TROUT_GPIO_INT2_BASE + 0)
120#define TROUT_GPIO_COMPASS_IRQ (TROUT_GPIO_INT2_BASE + 1)
121#define TROUT_GPIO_SLIDING_DET (TROUT_GPIO_INT2_BASE + 2)
122#define TROUT_GPIO_AUD_HSMIC_DET_N (TROUT_GPIO_INT2_BASE + 3)
123#define TROUT_GPIO_SD_DOOR_N (TROUT_GPIO_INT2_BASE + 4)
124#define TROUT_GPIO_CAM_BTN_STEP1_N (TROUT_GPIO_INT2_BASE + 5)
125#define TROUT_GPIO_CAM_BTN_STEP2_N (TROUT_GPIO_INT2_BASE + 6)
126#define TROUT_GPIO_TP_ATT_N (TROUT_GPIO_INT2_BASE + 7)
127#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE (TROUT_GPIO_NAVI_ACT_N)
128#define TROUT_GPIO_BANK0_LAST_INT_SOURCE (TROUT_GPIO_TP_ATT_N)
129
130#define TROUT_GPIO_H2W_DAT_GPI (TROUT_GPIO_MISC1_BASE + 0)
131#define TROUT_GPIO_H2W_CLK_GPI (TROUT_GPIO_MISC1_BASE + 1)
132#define TROUT_GPIO_CPLD128_VER_0 (TROUT_GPIO_MISC1_BASE + 4)
133#define TROUT_GPIO_CPLD128_VER_1 (TROUT_GPIO_MISC1_BASE + 5)
134#define TROUT_GPIO_CPLD128_VER_2 (TROUT_GPIO_MISC1_BASE + 6)
135#define TROUT_GPIO_CPLD128_VER_3 (TROUT_GPIO_MISC1_BASE + 7)
136
137#define TROUT_GPIO_SDMC_CD_N (TROUT_GPIO_VIRTUAL_BASE + 0)
138#define TROUT_GPIO_END (TROUT_GPIO_SDMC_CD_N)
139#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
140#define TROUT_GPIO_BANK1_LAST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
141
142#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
143 (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
144
145#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
146#define TROUT_INT_BANK0_COUNT (8)
147#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
148#define TROUT_INT_BANK1_COUNT (1)
149#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
150 TROUT_INT_BANK1_COUNT - 1)
151#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
152 (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
153 (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
154
155#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
156#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
157#define TROUT_BANK_TO_MASK_REG(bank) \
158 (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
159#define TROUT_BANK_TO_STAT_REG(bank) \
160 (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
161
162#endif /* GUARD */
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 262b441b4374..83e47c0d5c2e 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -16,6 +16,13 @@
16#ifndef __ASM_ARCH_MSM_GPIO_H 16#ifndef __ASM_ARCH_MSM_GPIO_H
17#define __ASM_ARCH_MSM_GPIO_H 17#define __ASM_ARCH_MSM_GPIO_H
18 18
19#include <asm-generic/gpio.h>
20
21#define gpio_get_value __gpio_get_value
22#define gpio_set_value __gpio_set_value
23#define gpio_cansleep __gpio_cansleep
24#define gpio_to_irq __gpio_to_irq
25
19/** 26/**
20 * struct msm_gpio - GPIO pin description 27 * struct msm_gpio - GPIO pin description
21 * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() 28 * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
deleted file mode 100644
index eb7660f5d4b7..000000000000
--- a/arch/arm/mach-mx1/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
1if ARCH_MX1
2
3comment "MX1 platforms:"
4
5config MACH_MXLADS
6 bool
7
8config ARCH_MX1ADS
9 bool "MX1ADS platform"
10 select MACH_MXLADS
11 help
12 Say Y here if you are using Motorola MX1ADS/MXLADS boards
13
14config MACH_SCB9328
15 bool "Synertronixx scb9328"
16 help
17 Say Y here if you are using a Synertronixx scb9328 board
18
19endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
deleted file mode 100644
index fc2ddf82441b..000000000000
--- a/arch/arm/mach-mx1/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS
8obj-y += generic.o clock.o devices.o
9
10# Support for CMOS sensor interface
11obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o
12
13# Specific board support
14obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
15obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot
deleted file mode 100644
index 8ed1492288a2..000000000000
--- a/arch/arm/mach-mx1/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1 zreladdr-y := 0x08008000
2params_phys-y := 0x08000100
3initrd_phys-y := 0x08800000
4
diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h
deleted file mode 100644
index 22e866ff0c09..000000000000
--- a/arch/arm/mach-mx1/crm_regs.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License, version 2.
7 */
8
9#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
10#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
11
12#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
13#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR)
14
15/* CCM register addresses */
16#define CCM_CSCR (CCM_BASE + 0x0)
17#define CCM_MPCTL0 (CCM_BASE + 0x4)
18#define CCM_MPCTL1 (CCM_BASE + 0x8)
19#define CCM_SPCTL0 (CCM_BASE + 0xC)
20#define CCM_SPCTL1 (CCM_BASE + 0x10)
21#define CCM_PCDR (CCM_BASE + 0x20)
22
23#define CCM_CSCR_CLKO_OFFSET 29
24#define CCM_CSCR_CLKO_MASK (0x7 << 29)
25#define CCM_CSCR_USB_OFFSET 26
26#define CCM_CSCR_USB_MASK (0x7 << 26)
27#define CCM_CSCR_SPLL_RESTART (1 << 22)
28#define CCM_CSCR_MPLL_RESTART (1 << 21)
29#define CCM_CSCR_OSC_EN_SHIFT 17
30#define CCM_CSCR_SYSTEM_SEL (1 << 16)
31#define CCM_CSCR_BCLK_OFFSET 10
32#define CCM_CSCR_BCLK_MASK (0xF << 10)
33#define CCM_CSCR_PRESC (1 << 15)
34#define CCM_CSCR_SPEN (1 << 1)
35#define CCM_CSCR_MPEN (1 << 0)
36
37#define CCM_PCDR_PCLK3_OFFSET 16
38#define CCM_PCDR_PCLK3_MASK (0x7F << 16)
39#define CCM_PCDR_PCLK2_OFFSET 4
40#define CCM_PCDR_PCLK2_MASK (0xF << 4)
41#define CCM_PCDR_PCLK1_OFFSET 0
42#define CCM_PCDR_PCLK1_MASK 0xF
43
44/* SCM register addresses */
45#define SCM_SIDR (SCM_BASE + 0x0)
46#define SCM_FMCR (SCM_BASE + 0x4)
47#define SCM_GPCR (SCM_BASE + 0x8)
48#define SCM_GCCR (SCM_BASE + 0xC)
49
50#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
51#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
52#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
53#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
54
55#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
deleted file mode 100644
index b6be29d1cb08..000000000000
--- a/arch/arm/mach-mx1/devices.c
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 * Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/platform_device.h>
25#include <linux/gpio.h>
26#include <mach/irqs.h>
27#include <mach/hardware.h>
28
29#include "devices.h"
30
31static struct resource imx_csi_resources[] = {
32 {
33 .start = 0x00224000,
34 .end = 0x00224010,
35 .flags = IORESOURCE_MEM,
36 }, {
37 .start = CSI_INT,
38 .end = CSI_INT,
39 .flags = IORESOURCE_IRQ,
40 },
41};
42
43static u64 imx_csi_dmamask = 0xffffffffUL;
44
45struct platform_device imx_csi_device = {
46 .name = "mx1-camera",
47 .id = 0, /* This is used to put cameras on this interface */
48 .dev = {
49 .dma_mask = &imx_csi_dmamask,
50 .coherent_dma_mask = 0xffffffff,
51 },
52 .resource = imx_csi_resources,
53 .num_resources = ARRAY_SIZE(imx_csi_resources),
54};
55
56static struct resource imx_i2c_resources[] = {
57 {
58 .start = 0x00217000,
59 .end = 0x00217010,
60 .flags = IORESOURCE_MEM,
61 }, {
62 .start = I2C_INT,
63 .end = I2C_INT,
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68struct platform_device imx_i2c_device = {
69 .name = "imx-i2c",
70 .id = 0,
71 .resource = imx_i2c_resources,
72 .num_resources = ARRAY_SIZE(imx_i2c_resources),
73};
74
75static struct resource imx_uart1_resources[] = {
76 {
77 .start = UART1_BASE_ADDR,
78 .end = UART1_BASE_ADDR + 0xD0,
79 .flags = IORESOURCE_MEM,
80 }, {
81 .start = UART1_MINT_RX,
82 .end = UART1_MINT_RX,
83 .flags = IORESOURCE_IRQ,
84 }, {
85 .start = UART1_MINT_TX,
86 .end = UART1_MINT_TX,
87 .flags = IORESOURCE_IRQ,
88 }, {
89 .start = UART1_MINT_RTS,
90 .end = UART1_MINT_RTS,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95struct platform_device imx_uart1_device = {
96 .name = "imx-uart",
97 .id = 0,
98 .num_resources = ARRAY_SIZE(imx_uart1_resources),
99 .resource = imx_uart1_resources,
100};
101
102static struct resource imx_uart2_resources[] = {
103 {
104 .start = UART2_BASE_ADDR,
105 .end = UART2_BASE_ADDR + 0xD0,
106 .flags = IORESOURCE_MEM,
107 }, {
108 .start = UART2_MINT_RX,
109 .end = UART2_MINT_RX,
110 .flags = IORESOURCE_IRQ,
111 }, {
112 .start = UART2_MINT_TX,
113 .end = UART2_MINT_TX,
114 .flags = IORESOURCE_IRQ,
115 }, {
116 .start = UART2_MINT_RTS,
117 .end = UART2_MINT_RTS,
118 .flags = IORESOURCE_IRQ,
119 },
120};
121
122struct platform_device imx_uart2_device = {
123 .name = "imx-uart",
124 .id = 1,
125 .num_resources = ARRAY_SIZE(imx_uart2_resources),
126 .resource = imx_uart2_resources,
127};
128
129static struct resource imx_rtc_resources[] = {
130 {
131 .start = 0x00204000,
132 .end = 0x00204024,
133 .flags = IORESOURCE_MEM,
134 }, {
135 .start = RTC_INT,
136 .end = RTC_INT,
137 .flags = IORESOURCE_IRQ,
138 }, {
139 .start = RTC_SAMINT,
140 .end = RTC_SAMINT,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145struct platform_device imx_rtc_device = {
146 .name = "rtc-imx",
147 .id = 0,
148 .resource = imx_rtc_resources,
149 .num_resources = ARRAY_SIZE(imx_rtc_resources),
150};
151
152static struct resource imx_wdt_resources[] = {
153 {
154 .start = 0x00201000,
155 .end = 0x00201008,
156 .flags = IORESOURCE_MEM,
157 }, {
158 .start = WDT_INT,
159 .end = WDT_INT,
160 .flags = IORESOURCE_IRQ,
161 },
162};
163
164struct platform_device imx_wdt_device = {
165 .name = "imx-wdt",
166 .id = 0,
167 .resource = imx_wdt_resources,
168 .num_resources = ARRAY_SIZE(imx_wdt_resources),
169};
170
171static struct resource imx_usb_resources[] = {
172 {
173 .start = 0x00212000,
174 .end = 0x00212148,
175 .flags = IORESOURCE_MEM,
176 }, {
177 .start = USBD_INT0,
178 .end = USBD_INT0,
179 .flags = IORESOURCE_IRQ,
180 }, {
181 .start = USBD_INT1,
182 .end = USBD_INT1,
183 .flags = IORESOURCE_IRQ,
184 }, {
185 .start = USBD_INT2,
186 .end = USBD_INT2,
187 .flags = IORESOURCE_IRQ,
188 }, {
189 .start = USBD_INT3,
190 .end = USBD_INT3,
191 .flags = IORESOURCE_IRQ,
192 }, {
193 .start = USBD_INT4,
194 .end = USBD_INT4,
195 .flags = IORESOURCE_IRQ,
196 }, {
197 .start = USBD_INT5,
198 .end = USBD_INT5,
199 .flags = IORESOURCE_IRQ,
200 }, {
201 .start = USBD_INT6,
202 .end = USBD_INT6,
203 .flags = IORESOURCE_IRQ,
204 },
205};
206
207struct platform_device imx_usb_device = {
208 .name = "imx_udc",
209 .id = 0,
210 .num_resources = ARRAY_SIZE(imx_usb_resources),
211 .resource = imx_usb_resources,
212};
213
214/* GPIO port description */
215static struct mxc_gpio_port imx_gpio_ports[] = {
216 {
217 .chip.label = "gpio-0",
218 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
219 .irq = GPIO_INT_PORTA,
220 .virtual_irq_start = MXC_GPIO_IRQ_START,
221 }, {
222 .chip.label = "gpio-1",
223 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
224 .irq = GPIO_INT_PORTB,
225 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
226 }, {
227 .chip.label = "gpio-2",
228 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
229 .irq = GPIO_INT_PORTC,
230 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
231 }, {
232 .chip.label = "gpio-3",
233 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
234 .irq = GPIO_INT_PORTD,
235 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
236 }
237};
238
239int __init mxc_register_gpios(void)
240{
241 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
242}
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
deleted file mode 100644
index 0da5d7cce3a2..000000000000
--- a/arch/arm/mach-mx1/devices.h
+++ /dev/null
@@ -1,7 +0,0 @@
1extern struct platform_device imx_csi_device;
2extern struct platform_device imx_i2c_device;
3extern struct platform_device imx_uart1_device;
4extern struct platform_device imx_uart2_device;
5extern struct platform_device imx_rtc_device;
6extern struct platform_device imx_wdt_device;
7extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
deleted file mode 100644
index 1c0c835b2252..000000000000
--- a/arch/arm/mach-mx2/serial.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <mach/hardware.h>
24#include <mach/imx-uart.h>
25#include "devices.h"
26
27static struct resource uart0[] = {
28 {
29 .start = MX2x_UART1_BASE_ADDR,
30 .end = MX2x_UART1_BASE_ADDR + 0x0B5,
31 .flags = IORESOURCE_MEM,
32 }, {
33 .start = MX2x_INT_UART1,
34 .end = MX2x_INT_UART1,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device mxc_uart_device0 = {
40 .name = "imx-uart",
41 .id = 0,
42 .resource = uart0,
43 .num_resources = ARRAY_SIZE(uart0),
44};
45
46static struct resource uart1[] = {
47 {
48 .start = MX2x_UART2_BASE_ADDR,
49 .end = MX2x_UART2_BASE_ADDR + 0x0B5,
50 .flags = IORESOURCE_MEM,
51 }, {
52 .start = MX2x_INT_UART2,
53 .end = MX2x_INT_UART2,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58struct platform_device mxc_uart_device1 = {
59 .name = "imx-uart",
60 .id = 1,
61 .resource = uart1,
62 .num_resources = ARRAY_SIZE(uart1),
63};
64
65static struct resource uart2[] = {
66 {
67 .start = MX2x_UART3_BASE_ADDR,
68 .end = MX2x_UART3_BASE_ADDR + 0x0B5,
69 .flags = IORESOURCE_MEM,
70 }, {
71 .start = MX2x_INT_UART3,
72 .end = MX2x_INT_UART3,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77struct platform_device mxc_uart_device2 = {
78 .name = "imx-uart",
79 .id = 2,
80 .resource = uart2,
81 .num_resources = ARRAY_SIZE(uart2),
82};
83
84static struct resource uart3[] = {
85 {
86 .start = MX2x_UART4_BASE_ADDR,
87 .end = MX2x_UART4_BASE_ADDR + 0x0B5,
88 .flags = IORESOURCE_MEM,
89 }, {
90 .start = MX2x_INT_UART4,
91 .end = MX2x_INT_UART4,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96struct platform_device mxc_uart_device3 = {
97 .name = "imx-uart",
98 .id = 3,
99 .resource = uart3,
100 .num_resources = ARRAY_SIZE(uart3),
101};
102
103#ifdef CONFIG_MACH_MX27
104static struct resource uart4[] = {
105 {
106 .start = MX27_UART5_BASE_ADDR,
107 .end = MX27_UART5_BASE_ADDR + 0x0B5,
108 .flags = IORESOURCE_MEM,
109 }, {
110 .start = MX27_INT_UART5,
111 .end = MX27_INT_UART5,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116struct platform_device mxc_uart_device4 = {
117 .name = "imx-uart",
118 .id = 4,
119 .resource = uart4,
120 .num_resources = ARRAY_SIZE(uart4),
121};
122
123static struct resource uart5[] = {
124 {
125 .start = MX27_UART6_BASE_ADDR,
126 .end = MX27_UART6_BASE_ADDR + 0x0B5,
127 .flags = IORESOURCE_MEM,
128 }, {
129 .start = MX27_INT_UART6,
130 .end = MX27_INT_UART6,
131 .flags = IORESOURCE_IRQ,
132 },
133};
134
135struct platform_device mxc_uart_device5 = {
136 .name = "imx-uart",
137 .id = 5,
138 .resource = uart5,
139 .num_resources = ARRAY_SIZE(uart5),
140};
141#endif
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 54d217314ee9..c71a7bc19284 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -4,5 +4,28 @@ comment "MX25 platforms:"
4 4
5config MACH_MX25_3DS 5config MACH_MX25_3DS
6 bool "Support MX25PDK (3DS) Platform" 6 bool "Support MX25PDK (3DS) Platform"
7 select IMX_HAVE_PLATFORM_IMX_UART
8 select IMX_HAVE_PLATFORM_MXC_NAND
9
10config MACH_EUKREA_CPUIMX25
11 bool "Support Eukrea CPUIMX25 Platform"
12 select IMX_HAVE_PLATFORM_IMX_I2C
13 select IMX_HAVE_PLATFORM_IMX_UART
14 select IMX_HAVE_PLATFORM_MXC_NAND
15 select MXC_ULPI if USB_ULPI
16
17choice
18 prompt "Baseboard"
19 depends on MACH_EUKREA_CPUIMX25
20 default MACH_EUKREA_MBIMXSD25_BASEBOARD
21
22config MACH_EUKREA_MBIMXSD25_BASEBOARD
23 prompt "Eukrea MBIMXSD development board"
24 bool
25 help
26 This adds board specific devices that can be found on Eukrea's
27 MBIMXSD evaluation board.
28
29endchoice
7 30
8endif 31endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 10cebc5ced8c..d9e46ce00a4e 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,5 @@
1obj-y := mm.o devices.o 1obj-y := mm.o devices.o
2obj-$(CONFIG_ARCH_MX25) += clock.o 2obj-$(CONFIG_ARCH_MX25) += clock.o
3obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o 3obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
4obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o
5obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 155014993b13..40c7cc41cee3 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk)
109 return get_rate_per(15); 109 return get_rate_per(15);
110} 110}
111 111
112static unsigned long get_rate_ssi2(struct clk *clk)
113{
114 return get_rate_per(14);
115}
116
117static unsigned long get_rate_ssi1(struct clk *clk)
118{
119 return get_rate_per(13);
120}
121
112static unsigned long get_rate_i2c(struct clk *clk) 122static unsigned long get_rate_i2c(struct clk *clk)
113{ 123{
114 return get_rate_per(6); 124 return get_rate_per(6);
@@ -129,9 +139,17 @@ static unsigned long get_rate_lcdc(struct clk *clk)
129 return get_rate_per(7); 139 return get_rate_per(7);
130} 140}
131 141
142static unsigned long get_rate_csi(struct clk *clk)
143{
144 return get_rate_per(0);
145}
146
132static unsigned long get_rate_otg(struct clk *clk) 147static unsigned long get_rate_otg(struct clk *clk)
133{ 148{
134 return 48000000; /* FIXME */ 149 unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
150 unsigned long rate = get_rate_upll();
151
152 return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
135} 153}
136 154
137static int clk_cgcr_enable(struct clk *clk) 155static int clk_cgcr_enable(struct clk *clk)
@@ -166,14 +184,40 @@ static void clk_cgcr_disable(struct clk *clk)
166 .secondary = s, \ 184 .secondary = s, \
167 } 185 }
168 186
187/*
188 * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
189 * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
190 * taken from the Freescale released BSP.
191 *
192 * bit reg offset clock
193 *
194 * 0 CGCR1 0 AUDMUX
195 * 12 CGCR1 12 ESAI
196 * 16 CGCR1 16 GPIO1
197 * 17 CGCR1 17 GPIO2
198 * 18 CGCR1 18 GPIO3
199 * 23 CGCR1 23 I2C1
200 * 24 CGCR1 24 I2C2
201 * 25 CGCR1 25 I2C3
202 * 27 CGCR1 27 IOMUXC
203 * 28 CGCR1 28 KPP
204 * 30 CGCR1 30 OWIRE
205 * 36 CGCR2 4 RTIC
206 * 51 CGCR2 19 WDOG
207 */
208
169DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); 209DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
170DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); 210DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
211DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
212DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
171DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); 213DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
172DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); 214DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
173DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); 215DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
174DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); 216DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
175DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); 217DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
176DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); 218DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
219DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
220DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
177DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); 221DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
178DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); 222DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
179DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); 223DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
@@ -191,6 +235,13 @@ DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
191DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); 235DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
192DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); 236DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL);
193DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); 237DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
238DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
239DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
240DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
241DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
242DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
243DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL);
244DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
194 245
195#define _REGISTER_CLOCK(d, n, c) \ 246#define _REGISTER_CLOCK(d, n, c) \
196 { \ 247 { \
@@ -217,7 +268,7 @@ static struct clk_lookup lookups[] = {
217 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) 268 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
218 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) 269 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
219 _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk) 270 _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
220 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) 271 _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
221 _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk) 272 _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
222 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 273 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
223 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) 274 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
@@ -225,6 +276,13 @@ static struct clk_lookup lookups[] = {
225 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 276 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
226 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) 277 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
227 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 278 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
279 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
280 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
281 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
282 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
283 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
284 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
285 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
228}; 286};
229 287
230int __init mx25_clocks_init(void) 288int __init mx25_clocks_init(void)
@@ -238,9 +296,13 @@ int __init mx25_clocks_init(void)
238 __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0); 296 __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
239 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); 297 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
240 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); 298 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
299#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
300 clk_enable(&uart1_clk);
301#endif
241 302
242 /* Clock source for lcdc is upll */ 303 /* Clock source for lcdc and csi is upll */
243 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); 304 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
305 CRM_BASE + 0x64);
244 306
245 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 307 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
246 308
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
new file mode 100644
index 000000000000..d86a7c3ca8b0
--- /dev/null
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx25.h>
10#include <mach/devices-common.h>
11
12#define imx25_add_flexcan0(pdata) \
13 imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
14#define imx25_add_flexcan1(pdata) \
15 imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
16
17#define imx25_add_imx_i2c0(pdata) \
18 imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
19#define imx25_add_imx_i2c1(pdata) \
20 imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
21#define imx25_add_imx_i2c2(pdata) \
22 imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
23
24#define imx25_add_imx_uart0(pdata) \
25 imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
26#define imx25_add_imx_uart1(pdata) \
27 imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
28#define imx25_add_imx_uart2(pdata) \
29 imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
30#define imx25_add_imx_uart3(pdata) \
31 imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
32#define imx25_add_imx_uart4(pdata) \
33 imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
34
35#define imx25_add_mxc_nand(pdata) \
36 imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
37
38#define imx25_add_spi_imx0(pdata) \
39 imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
40#define imx25_add_spi_imx1(pdata) \
41 imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
42#define imx25_add_spi_imx2(pdata) \
43 imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3a405fa400eb..3468eb15b236 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -22,103 +22,6 @@
22#include <mach/mx25.h> 22#include <mach/mx25.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24 24
25static struct resource uart0[] = {
26 {
27 .start = 0x43f90000,
28 .end = 0x43f93fff,
29 .flags = IORESOURCE_MEM,
30 }, {
31 .start = 45,
32 .end = 45,
33 .flags = IORESOURCE_IRQ,
34 },
35};
36
37struct platform_device mxc_uart_device0 = {
38 .name = "imx-uart",
39 .id = 0,
40 .resource = uart0,
41 .num_resources = ARRAY_SIZE(uart0),
42};
43
44static struct resource uart1[] = {
45 {
46 .start = 0x43f94000,
47 .end = 0x43f97fff,
48 .flags = IORESOURCE_MEM,
49 }, {
50 .start = 32,
51 .end = 32,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
56struct platform_device mxc_uart_device1 = {
57 .name = "imx-uart",
58 .id = 1,
59 .resource = uart1,
60 .num_resources = ARRAY_SIZE(uart1),
61};
62
63static struct resource uart2[] = {
64 {
65 .start = 0x5000c000,
66 .end = 0x5000ffff,
67 .flags = IORESOURCE_MEM,
68 }, {
69 .start = 18,
70 .end = 18,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75struct platform_device mxc_uart_device2 = {
76 .name = "imx-uart",
77 .id = 2,
78 .resource = uart2,
79 .num_resources = ARRAY_SIZE(uart2),
80};
81
82static struct resource uart3[] = {
83 {
84 .start = 0x50008000,
85 .end = 0x5000bfff,
86 .flags = IORESOURCE_MEM,
87 }, {
88 .start = 5,
89 .end = 5,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94struct platform_device mxc_uart_device3 = {
95 .name = "imx-uart",
96 .id = 3,
97 .resource = uart3,
98 .num_resources = ARRAY_SIZE(uart3),
99};
100
101static struct resource uart4[] = {
102 {
103 .start = 0x5002c000,
104 .end = 0x5002ffff,
105 .flags = IORESOURCE_MEM,
106 }, {
107 .start = 40,
108 .end = 40,
109 .flags = IORESOURCE_IRQ,
110 },
111};
112
113struct platform_device mxc_uart_device4 = {
114 .name = "imx-uart",
115 .id = 4,
116 .resource = uart4,
117 .num_resources = ARRAY_SIZE(uart4),
118};
119
120#define MX25_OTG_BASE_ADDR 0x53FF4000
121
122static u64 otg_dmamask = DMA_BIT_MASK(32); 25static u64 otg_dmamask = DMA_BIT_MASK(32);
123 26
124static struct resource mxc_otg_resources[] = { 27static struct resource mxc_otg_resources[] = {
@@ -181,63 +84,6 @@ struct platform_device mxc_usbh2 = {
181 .num_resources = ARRAY_SIZE(mxc_usbh2_resources), 84 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
182}; 85};
183 86
184static struct resource mxc_spi_resources0[] = {
185 {
186 .start = 0x43fa4000,
187 .end = 0x43fa7fff,
188 .flags = IORESOURCE_MEM,
189 }, {
190 .start = 14,
191 .end = 14,
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196struct platform_device mxc_spi_device0 = {
197 .name = "spi_imx",
198 .id = 0,
199 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
200 .resource = mxc_spi_resources0,
201};
202
203static struct resource mxc_spi_resources1[] = {
204 {
205 .start = 0x50010000,
206 .end = 0x50013fff,
207 .flags = IORESOURCE_MEM,
208 }, {
209 .start = 13,
210 .end = 13,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215struct platform_device mxc_spi_device1 = {
216 .name = "spi_imx",
217 .id = 1,
218 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
219 .resource = mxc_spi_resources1,
220};
221
222static struct resource mxc_spi_resources2[] = {
223 {
224 .start = 0x50004000,
225 .end = 0x50007fff,
226 .flags = IORESOURCE_MEM,
227 }, {
228 .start = 0,
229 .end = 0,
230 .flags = IORESOURCE_IRQ,
231 },
232};
233
234struct platform_device mxc_spi_device2 = {
235 .name = "spi_imx",
236 .id = 2,
237 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
238 .resource = mxc_spi_resources2,
239};
240
241static struct resource mxc_pwm_resources0[] = { 87static struct resource mxc_pwm_resources0[] = {
242 { 88 {
243 .start = 0x53fe0000, 89 .start = 0x53fe0000,
@@ -333,63 +179,6 @@ struct platform_device mxc_pwm_device3 = {
333 .resource = mxc_pwm_resources3, 179 .resource = mxc_pwm_resources3,
334}; 180};
335 181
336static struct resource mxc_i2c_1_resources[] = {
337 {
338 .start = 0x43f80000,
339 .end = 0x43f83fff,
340 .flags = IORESOURCE_MEM,
341 }, {
342 .start = 3,
343 .end = 3,
344 .flags = IORESOURCE_IRQ,
345 }
346};
347
348struct platform_device mxc_i2c_device0 = {
349 .name = "imx-i2c",
350 .id = 0,
351 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
352 .resource = mxc_i2c_1_resources,
353};
354
355static struct resource mxc_i2c_2_resources[] = {
356 {
357 .start = 0x43f98000,
358 .end = 0x43f9bfff,
359 .flags = IORESOURCE_MEM,
360 }, {
361 .start = 4,
362 .end = 4,
363 .flags = IORESOURCE_IRQ,
364 }
365};
366
367struct platform_device mxc_i2c_device1 = {
368 .name = "imx-i2c",
369 .id = 1,
370 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
371 .resource = mxc_i2c_2_resources,
372};
373
374static struct resource mxc_i2c_3_resources[] = {
375 {
376 .start = 0x43f84000,
377 .end = 0x43f87fff,
378 .flags = IORESOURCE_MEM,
379 }, {
380 .start = 10,
381 .end = 10,
382 .flags = IORESOURCE_IRQ,
383 }
384};
385
386struct platform_device mxc_i2c_device2 = {
387 .name = "imx-i2c",
388 .id = 2,
389 .num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
390 .resource = mxc_i2c_3_resources,
391};
392
393static struct mxc_gpio_port imx_gpio_ports[] = { 182static struct mxc_gpio_port imx_gpio_ports[] = {
394 { 183 {
395 .chip.label = "gpio-0", 184 .chip.label = "gpio-0",
@@ -414,7 +203,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
414 } 203 }
415}; 204};
416 205
417int __init mxc_register_gpios(void) 206int __init imx25_register_gpios(void)
418{ 207{
419 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 208 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
420} 209}
@@ -439,26 +228,6 @@ struct platform_device mx25_fec_device = {
439 .resource = mx25_fec_resources, 228 .resource = mx25_fec_resources,
440}; 229};
441 230
442static struct resource mxc_nand_resources[] = {
443 {
444 .start = MX25_NFC_BASE_ADDR,
445 .end = MX25_NFC_BASE_ADDR + 0x1fff,
446 .flags = IORESOURCE_MEM,
447 },
448 {
449 .start = MX25_INT_NANDFC,
450 .end = MX25_INT_NANDFC,
451 .flags = IORESOURCE_IRQ,
452 },
453};
454
455struct platform_device mxc_nand_device = {
456 .name = "mxc_nand",
457 .id = 0,
458 .num_resources = ARRAY_SIZE(mxc_nand_resources),
459 .resource = mxc_nand_resources,
460};
461
462static struct resource mx25_rtc_resources[] = { 231static struct resource mx25_rtc_resources[] = {
463 { 232 {
464 .start = MX25_DRYICE_BASE_ADDR, 233 .start = MX25_DRYICE_BASE_ADDR,
@@ -515,3 +284,83 @@ struct platform_device mxc_wdt = {
515 .num_resources = ARRAY_SIZE(mxc_wdt_resources), 284 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
516 .resource = mxc_wdt_resources, 285 .resource = mxc_wdt_resources,
517}; 286};
287
288static struct resource mx25_kpp_resources[] = {
289 {
290 .start = MX25_KPP_BASE_ADDR,
291 .end = MX25_KPP_BASE_ADDR + 0xf,
292 .flags = IORESOURCE_MEM,
293 },
294 {
295 .start = MX25_INT_KPP,
296 .end = MX25_INT_KPP,
297 .flags = IORESOURCE_IRQ,
298 },
299};
300
301struct platform_device mx25_kpp_device = {
302 .name = "imx-keypad",
303 .id = -1,
304 .num_resources = ARRAY_SIZE(mx25_kpp_resources),
305 .resource = mx25_kpp_resources,
306};
307
308static struct resource imx_ssi_resources0[] = {
309 {
310 .start = MX25_SSI1_BASE_ADDR,
311 .end = MX25_SSI1_BASE_ADDR + 0x3fff,
312 .flags = IORESOURCE_MEM,
313 }, {
314 .start = MX25_INT_SSI1,
315 .end = MX25_INT_SSI1,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct resource imx_ssi_resources1[] = {
321 {
322 .start = MX25_SSI2_BASE_ADDR,
323 .end = MX25_SSI2_BASE_ADDR + 0x3fff,
324 .flags = IORESOURCE_MEM
325 }, {
326 .start = MX25_INT_SSI2,
327 .end = MX25_INT_SSI2,
328 .flags = IORESOURCE_IRQ,
329 },
330};
331
332struct platform_device imx_ssi_device0 = {
333 .name = "imx-ssi",
334 .id = 0,
335 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
336 .resource = imx_ssi_resources0,
337};
338
339struct platform_device imx_ssi_device1 = {
340 .name = "imx-ssi",
341 .id = 1,
342 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
343 .resource = imx_ssi_resources1,
344};
345
346static struct resource mx25_csi_resources[] = {
347 {
348 .start = MX25_CSI_BASE_ADDR,
349 .end = MX25_CSI_BASE_ADDR + 0xfff,
350 .flags = IORESOURCE_MEM,
351 },
352 {
353 .start = MX25_INT_CSI,
354 .flags = IORESOURCE_IRQ
355 },
356};
357
358struct platform_device mx25_csi_device = {
359 .name = "mx2-camera",
360 .id = 0,
361 .num_resources = ARRAY_SIZE(mx25_csi_resources),
362 .resource = mx25_csi_resources,
363 .dev = {
364 .coherent_dma_mask = 0xffffffff,
365 },
366};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index cee12c0a0be6..4aceb68e35a7 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -1,24 +1,16 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4extern struct platform_device mxc_uart_device3;
5extern struct platform_device mxc_uart_device4;
6extern struct platform_device mxc_otg; 1extern struct platform_device mxc_otg;
7extern struct platform_device otg_udc_device; 2extern struct platform_device otg_udc_device;
8extern struct platform_device mxc_usbh2; 3extern struct platform_device mxc_usbh2;
9extern struct platform_device mxc_spi_device0;
10extern struct platform_device mxc_spi_device1;
11extern struct platform_device mxc_spi_device2;
12extern struct platform_device mxc_pwm_device0; 4extern struct platform_device mxc_pwm_device0;
13extern struct platform_device mxc_pwm_device1; 5extern struct platform_device mxc_pwm_device1;
14extern struct platform_device mxc_pwm_device2; 6extern struct platform_device mxc_pwm_device2;
15extern struct platform_device mxc_pwm_device3; 7extern struct platform_device mxc_pwm_device3;
16extern struct platform_device mxc_keypad_device; 8extern struct platform_device mxc_keypad_device;
17extern struct platform_device mxc_i2c_device0;
18extern struct platform_device mxc_i2c_device1;
19extern struct platform_device mxc_i2c_device2;
20extern struct platform_device mx25_fec_device; 9extern struct platform_device mx25_fec_device;
21extern struct platform_device mxc_nand_device;
22extern struct platform_device mx25_rtc_device; 10extern struct platform_device mx25_rtc_device;
23extern struct platform_device mx25_fb_device; 11extern struct platform_device mx25_fb_device;
24extern struct platform_device mxc_wdt; 12extern struct platform_device mxc_wdt;
13extern struct platform_device mx25_kpp_device;
14extern struct platform_device imx_ssi_device0;
15extern struct platform_device imx_ssi_device1;
16extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..91931dcb0689
--- /dev/null
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,260 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/gpio.h>
23#include <linux/leds.h>
24#include <linux/platform_device.h>
25#include <linux/gpio_keys.h>
26#include <linux/input.h>
27#include <video/platform_lcd.h>
28
29#include <mach/hardware.h>
30#include <mach/iomux-mx25.h>
31#include <mach/common.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <mach/mx25.h>
35#include <mach/imx-uart.h>
36#include <mach/imxfb.h>
37#include <mach/ssi.h>
38#include <mach/audmux.h>
39
40#include "devices-imx25.h"
41#include "devices.h"
42
43static struct pad_desc eukrea_mbimxsd_pads[] = {
44 /* LCD */
45 MX25_PAD_LD0__LD0,
46 MX25_PAD_LD1__LD1,
47 MX25_PAD_LD2__LD2,
48 MX25_PAD_LD3__LD3,
49 MX25_PAD_LD4__LD4,
50 MX25_PAD_LD5__LD5,
51 MX25_PAD_LD6__LD6,
52 MX25_PAD_LD7__LD7,
53 MX25_PAD_LD8__LD8,
54 MX25_PAD_LD9__LD9,
55 MX25_PAD_LD10__LD10,
56 MX25_PAD_LD11__LD11,
57 MX25_PAD_LD12__LD12,
58 MX25_PAD_LD13__LD13,
59 MX25_PAD_LD14__LD14,
60 MX25_PAD_LD15__LD15,
61 MX25_PAD_GPIO_E__LD16,
62 MX25_PAD_GPIO_F__LD17,
63 MX25_PAD_HSYNC__HSYNC,
64 MX25_PAD_VSYNC__VSYNC,
65 MX25_PAD_LSCLK__LSCLK,
66 MX25_PAD_OE_ACD__OE_ACD,
67 MX25_PAD_CONTRAST__CONTRAST,
68 /* LCD_PWR */
69 MX25_PAD_PWM__GPIO_1_26,
70 /* LED */
71 MX25_PAD_POWER_FAIL__GPIO_3_19,
72 /* SWITCH */
73 MX25_PAD_VSTBY_ACK__GPIO_3_18,
74 /* UART2 */
75 MX25_PAD_UART2_RTS__UART2_RTS,
76 MX25_PAD_UART2_CTS__UART2_CTS,
77 MX25_PAD_UART2_TXD__UART2_TXD,
78 MX25_PAD_UART2_RXD__UART2_RXD,
79 /* SD1 */
80 MX25_PAD_SD1_CMD__SD1_CMD,
81 MX25_PAD_SD1_CLK__SD1_CLK,
82 MX25_PAD_SD1_DATA0__SD1_DATA0,
83 MX25_PAD_SD1_DATA1__SD1_DATA1,
84 MX25_PAD_SD1_DATA2__SD1_DATA2,
85 MX25_PAD_SD1_DATA3__SD1_DATA3,
86 /* SD1 CD */
87 MX25_PAD_DE_B__GPIO_2_20,
88 /* I2S */
89 MX25_PAD_KPP_COL3__AUD5_TXFS,
90 MX25_PAD_KPP_COL2__AUD5_TXC,
91 MX25_PAD_KPP_COL1__AUD5_RXD,
92 MX25_PAD_KPP_COL0__AUD5_TXD,
93};
94
95#define GPIO_LED1 83
96#define GPIO_SWITCH1 82
97#define GPIO_SD1CD 52
98#define GPIO_LCDPWR 26
99
100static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
101 {
102 .mode = {
103 .name = "CMO-QVGA",
104 .refresh = 60,
105 .xres = 320,
106 .yres = 240,
107 .pixclock = KHZ2PICOS(6500),
108 .left_margin = 30,
109 .right_margin = 38,
110 .upper_margin = 20,
111 .lower_margin = 3,
112 .hsync_len = 15,
113 .vsync_len = 4,
114 },
115 .bpp = 16,
116 .pcr = 0xCAD08B80,
117 },
118};
119
120static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
121 .mode = eukrea_mximxsd_modes,
122 .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
123 .pwmr = 0x00A903FF,
124 .lscr1 = 0x00120300,
125 .dmacr = 0x00040060,
126};
127
128static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
129 unsigned int power)
130{
131 if (power)
132 gpio_direction_output(GPIO_LCDPWR, 1);
133 else
134 gpio_direction_output(GPIO_LCDPWR, 0);
135}
136
137static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
138 .set_power = eukrea_mbimxsd_lcd_power_set,
139};
140
141static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
142 .name = "platform-lcd",
143 .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
144};
145
146static struct gpio_led eukrea_mbimxsd_leds[] = {
147 {
148 .name = "led1",
149 .default_trigger = "heartbeat",
150 .active_low = 1,
151 .gpio = GPIO_LED1,
152 },
153};
154
155static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
156 .leds = eukrea_mbimxsd_leds,
157 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
158};
159
160static struct platform_device eukrea_mbimxsd_leds_gpio = {
161 .name = "leds-gpio",
162 .id = -1,
163 .dev = {
164 .platform_data = &eukrea_mbimxsd_led_info,
165 },
166};
167
168static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
169 {
170 .gpio = GPIO_SWITCH1,
171 .code = BTN_0,
172 .desc = "BP1",
173 .active_low = 1,
174 .wakeup = 1,
175 },
176};
177
178static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
179 .buttons = eukrea_mbimxsd_gpio_buttons,
180 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
181};
182
183static struct platform_device eukrea_mbimxsd_button_device = {
184 .name = "gpio-keys",
185 .id = -1,
186 .num_resources = 0,
187 .dev = {
188 .platform_data = &eukrea_mbimxsd_button_data,
189 }
190};
191
192static struct platform_device *platform_devices[] __initdata = {
193 &eukrea_mbimxsd_leds_gpio,
194 &eukrea_mbimxsd_button_device,
195 &eukrea_mbimxsd_lcd_powerdev,
196};
197
198static const struct imxuart_platform_data uart_pdata __initconst = {
199 .flags = IMXUART_HAVE_RTSCTS,
200};
201
202static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
203 {
204 I2C_BOARD_INFO("tlv320aic23", 0x1a),
205 },
206};
207
208struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
209 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
210};
211
212/*
213 * system init for baseboard usage. Will be called by cpuimx25 init.
214 *
215 * Add platform devices present on this baseboard and init
216 * them from CPU side as far as required to use them later on
217 */
218void __init eukrea_mbimxsd_baseboard_init(void)
219{
220 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
221 ARRAY_SIZE(eukrea_mbimxsd_pads)))
222 printk(KERN_ERR "error setting mbimxsd pads !\n");
223
224#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
225 /* SSI unit master I2S codec connected to SSI_AUD5*/
226 mxc_audmux_v2_configure_port(0,
227 MXC_AUDMUX_V2_PTCR_SYN |
228 MXC_AUDMUX_V2_PTCR_TFSDIR |
229 MXC_AUDMUX_V2_PTCR_TFSEL(4) |
230 MXC_AUDMUX_V2_PTCR_TCLKDIR |
231 MXC_AUDMUX_V2_PTCR_TCSEL(4),
232 MXC_AUDMUX_V2_PDCR_RXDSEL(4)
233 );
234 mxc_audmux_v2_configure_port(4,
235 MXC_AUDMUX_V2_PTCR_SYN,
236 MXC_AUDMUX_V2_PDCR_RXDSEL(0)
237 );
238#endif
239
240 imx25_add_imx_uart1(&uart_pdata);
241 mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
242 mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
243
244 gpio_request(GPIO_LED1, "LED1");
245 gpio_direction_output(GPIO_LED1, 1);
246 gpio_free(GPIO_LED1);
247
248 gpio_request(GPIO_SWITCH1, "SWITCH1");
249 gpio_direction_input(GPIO_SWITCH1);
250 gpio_free(GPIO_SWITCH1);
251
252 gpio_request(GPIO_LCDPWR, "LCDPWR");
253 gpio_direction_output(GPIO_LCDPWR, 1);
254 gpio_free(GPIO_SWITCH1);
255
256 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
257 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
258
259 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
260}
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
new file mode 100644
index 000000000000..56b2e26d23b4
--- /dev/null
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
3 * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/irq.h>
25#include <linux/gpio.h>
26#include <linux/fec.h>
27#include <linux/platform_device.h>
28#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h>
30#include <linux/fsl_devices.h>
31
32#include <mach/eukrea-baseboards.h>
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/memory.h>
38#include <asm/mach/map.h>
39#include <mach/common.h>
40#include <mach/mx25.h>
41#include <mach/mxc_nand.h>
42#include <mach/imxfb.h>
43#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h>
45#include <mach/iomux-mx25.h>
46
47#include "devices-imx25.h"
48#include "devices.h"
49
50static const struct imxuart_platform_data uart_pdata __initconst = {
51 .flags = IMXUART_HAVE_RTSCTS,
52};
53
54static struct pad_desc eukrea_cpuimx25_pads[] = {
55 /* FEC - RMII */
56 MX25_PAD_FEC_MDC__FEC_MDC,
57 MX25_PAD_FEC_MDIO__FEC_MDIO,
58 MX25_PAD_FEC_TDATA0__FEC_TDATA0,
59 MX25_PAD_FEC_TDATA1__FEC_TDATA1,
60 MX25_PAD_FEC_TX_EN__FEC_TX_EN,
61 MX25_PAD_FEC_RDATA0__FEC_RDATA0,
62 MX25_PAD_FEC_RDATA1__FEC_RDATA1,
63 MX25_PAD_FEC_RX_DV__FEC_RX_DV,
64 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
65 /* I2C1 */
66 MX25_PAD_I2C1_CLK__I2C1_CLK,
67 MX25_PAD_I2C1_DAT__I2C1_DAT,
68};
69
70static struct fec_platform_data mx25_fec_pdata = {
71 .phy = PHY_INTERFACE_MODE_RMII,
72};
73
74static const struct mxc_nand_platform_data
75eukrea_cpuimx25_nand_board_info __initconst = {
76 .width = 1,
77 .hw_ecc = 1,
78 .flash_bbt = 1,
79};
80
81static const struct imxi2c_platform_data
82eukrea_cpuimx25_i2c0_data __initconst = {
83 .bitrate = 100000,
84};
85
86static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
87 {
88 I2C_BOARD_INFO("pcf8563", 0x51),
89 },
90};
91
92static struct mxc_usbh_platform_data otg_pdata = {
93 .portsc = MXC_EHCI_MODE_UTMI,
94 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
95};
96
97static struct mxc_usbh_platform_data usbh2_pdata = {
98 .portsc = MXC_EHCI_MODE_SERIAL,
99 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
100 MXC_EHCI_IPPUE_DOWN,
101};
102
103static struct fsl_usb2_platform_data otg_device_pdata = {
104 .operating_mode = FSL_USB2_DR_DEVICE,
105 .phy_mode = FSL_USB2_PHY_UTMI,
106};
107
108static int otg_mode_host;
109
110static int __init eukrea_cpuimx25_otg_mode(char *options)
111{
112 if (!strcmp(options, "host"))
113 otg_mode_host = 1;
114 else if (!strcmp(options, "device"))
115 otg_mode_host = 0;
116 else
117 pr_info("otg_mode neither \"host\" nor \"device\". "
118 "Defaulting to device\n");
119 return 0;
120}
121__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
122
123static void __init eukrea_cpuimx25_init(void)
124{
125 if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
126 ARRAY_SIZE(eukrea_cpuimx25_pads)))
127 printk(KERN_ERR "error setting cpuimx25 pads !\n");
128
129 imx25_add_imx_uart0(&uart_pdata);
130 imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
131 mxc_register_device(&mx25_rtc_device, NULL);
132 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
133
134 i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
135 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
136 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
137
138#if defined(CONFIG_USB_ULPI)
139 if (otg_mode_host) {
140 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
141 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
142
143 mxc_register_device(&mxc_otg, &otg_pdata);
144 }
145 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
146#endif
147 if (!otg_mode_host)
148 mxc_register_device(&otg_udc_device, &otg_device_pdata);
149
150#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
151 eukrea_mbimxsd_baseboard_init();
152#endif
153}
154
155static void __init eukrea_cpuimx25_timer_init(void)
156{
157 mx25_clocks_init();
158}
159
160static struct sys_timer eukrea_cpuimx25_timer = {
161 .init = eukrea_cpuimx25_timer_init,
162};
163
164MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
165 /* Maintainer: Eukrea Electromatique */
166 .phys_io = MX25_AIPS1_BASE_ADDR,
167 .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
168 .boot_params = MX25_PHYS_OFFSET + 0x100,
169 .map_io = mx25_map_io,
170 .init_irq = mx25_init_irq,
171 .init_machine = eukrea_cpuimx25_init,
172 .timer = &eukrea_cpuimx25_timer,
173MACHINE_END
diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 83d74109e7d8..62bc21f11a71 100644
--- a/arch/arm/mach-mx25/mach-mx25pdk.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -16,6 +16,12 @@
16 * Boston, MA 02110-1301, USA. 16 * Boston, MA 02110-1301, USA.
17 */ 17 */
18 18
19/*
20 * This machine is known as:
21 * - i.MX25 3-Stack Development System
22 * - i.MX25 Platform Development Kit (i.MX25 PDK)
23 */
24
19#include <linux/types.h> 25#include <linux/types.h>
20#include <linux/init.h> 26#include <linux/init.h>
21#include <linux/delay.h> 27#include <linux/delay.h>
@@ -24,6 +30,7 @@
24#include <linux/gpio.h> 30#include <linux/gpio.h>
25#include <linux/fec.h> 31#include <linux/fec.h>
26#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/input/matrix_keypad.h>
27 34
28#include <mach/hardware.h> 35#include <mach/hardware.h>
29#include <asm/mach-types.h> 36#include <asm/mach-types.h>
@@ -32,14 +39,14 @@
32#include <asm/memory.h> 39#include <asm/memory.h>
33#include <asm/mach/map.h> 40#include <asm/mach/map.h>
34#include <mach/common.h> 41#include <mach/common.h>
35#include <mach/imx-uart.h>
36#include <mach/mx25.h> 42#include <mach/mx25.h>
37#include <mach/mxc_nand.h>
38#include <mach/imxfb.h> 43#include <mach/imxfb.h>
39#include "devices.h"
40#include <mach/iomux-mx25.h> 44#include <mach/iomux-mx25.h>
41 45
42static struct imxuart_platform_data uart_pdata = { 46#include "devices-imx25.h"
47#include "devices.h"
48
49static const struct imxuart_platform_data uart_pdata __initconst = {
43 .flags = IMXUART_HAVE_RTSCTS, 50 .flags = IMXUART_HAVE_RTSCTS,
44}; 51};
45 52
@@ -80,6 +87,16 @@ static struct pad_desc mx25pdk_pads[] = {
80 MX25_PAD_LSCLK__LSCLK, 87 MX25_PAD_LSCLK__LSCLK,
81 MX25_PAD_OE_ACD__OE_ACD, 88 MX25_PAD_OE_ACD__OE_ACD,
82 MX25_PAD_CONTRAST__CONTRAST, 89 MX25_PAD_CONTRAST__CONTRAST,
90
91 /* Keypad */
92 MX25_PAD_KPP_ROW0__KPP_ROW0,
93 MX25_PAD_KPP_ROW1__KPP_ROW1,
94 MX25_PAD_KPP_ROW2__KPP_ROW2,
95 MX25_PAD_KPP_ROW3__KPP_ROW3,
96 MX25_PAD_KPP_COL0__KPP_COL0,
97 MX25_PAD_KPP_COL1__KPP_COL1,
98 MX25_PAD_KPP_COL2__KPP_COL2,
99 MX25_PAD_KPP_COL3__KPP_COL3,
83}; 100};
84 101
85static struct fec_platform_data mx25_fec_pdata = { 102static struct fec_platform_data mx25_fec_pdata = {
@@ -103,7 +120,8 @@ static void __init mx25pdk_fec_reset(void)
103 gpio_set_value(FEC_RESET_B_GPIO, 1); 120 gpio_set_value(FEC_RESET_B_GPIO, 1);
104} 121}
105 122
106static struct mxc_nand_platform_data mx25pdk_nand_board_info = { 123static const struct mxc_nand_platform_data
124mx25pdk_nand_board_info __initconst = {
107 .width = 1, 125 .width = 1,
108 .hw_ecc = 1, 126 .hw_ecc = 1,
109 .flash_bbt = 1, 127 .flash_bbt = 1,
@@ -137,19 +155,45 @@ static struct imx_fb_platform_data mx25pdk_fb_pdata = {
137 .dmacr = 0x00020010, 155 .dmacr = 0x00020010,
138}; 156};
139 157
158static const uint32_t mx25pdk_keymap[] = {
159 KEY(0, 0, KEY_UP),
160 KEY(0, 1, KEY_DOWN),
161 KEY(0, 2, KEY_VOLUMEDOWN),
162 KEY(0, 3, KEY_HOME),
163 KEY(1, 0, KEY_RIGHT),
164 KEY(1, 1, KEY_LEFT),
165 KEY(1, 2, KEY_ENTER),
166 KEY(1, 3, KEY_VOLUMEUP),
167 KEY(2, 0, KEY_F6),
168 KEY(2, 1, KEY_F8),
169 KEY(2, 2, KEY_F9),
170 KEY(2, 3, KEY_F10),
171 KEY(3, 0, KEY_F1),
172 KEY(3, 1, KEY_F2),
173 KEY(3, 2, KEY_F3),
174 KEY(3, 3, KEY_POWER),
175};
176
177static struct matrix_keymap_data mx25pdk_keymap_data = {
178 .keymap = mx25pdk_keymap,
179 .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
180};
181
140static void __init mx25pdk_init(void) 182static void __init mx25pdk_init(void)
141{ 183{
142 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, 184 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
143 ARRAY_SIZE(mx25pdk_pads)); 185 ARRAY_SIZE(mx25pdk_pads));
144 186
145 mxc_register_device(&mxc_uart_device0, &uart_pdata); 187 imx25_add_imx_uart0(&uart_pdata);
146 mxc_register_device(&mxc_usbh2, NULL); 188 mxc_register_device(&mxc_usbh2, NULL);
147 mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info); 189 imx25_add_mxc_nand(&mx25pdk_nand_board_info);
148 mxc_register_device(&mx25_rtc_device, NULL); 190 mxc_register_device(&mx25_rtc_device, NULL);
149 mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); 191 mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
192 mxc_register_device(&mxc_wdt, NULL);
150 193
151 mx25pdk_fec_reset(); 194 mx25pdk_fec_reset();
152 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); 195 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
196 mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
153} 197}
154 198
155static void __init mx25pdk_timer_init(void) 199static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
index a7e587ff3e9e..bb677111fb0f 100644
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-mx25/mm.c
@@ -14,10 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */ 17 */
22 18
23#include <linux/mm.h> 19#include <linux/mm.h>
@@ -69,8 +65,11 @@ void __init mx25_map_io(void)
69 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 65 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
70} 66}
71 67
68int imx25_register_gpios(void);
69
72void __init mx25_init_irq(void) 70void __init mx25_init_irq(void)
73{ 71{
74 mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT); 72 mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
73 imx25_register_gpios();
75} 74}
76 75
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753fdf25e..85beece802aa 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -15,6 +15,8 @@ comment "MX3 platforms:"
15config MACH_MX31ADS 15config MACH_MX31ADS
16 bool "Support MX31ADS platforms" 16 bool "Support MX31ADS platforms"
17 select ARCH_MX31 17 select ARCH_MX31
18 select IMX_HAVE_PLATFORM_IMX_I2C
19 select IMX_HAVE_PLATFORM_IMX_UART
18 default y 20 default y
19 help 21 help
20 Include support for MX31ADS platform. This includes specific 22 Include support for MX31ADS platform. This includes specific
@@ -34,6 +36,9 @@ config MACH_MX31ADS_WM1133_EV1
34config MACH_PCM037 36config MACH_PCM037
35 bool "Support Phytec pcm037 (i.MX31) platforms" 37 bool "Support Phytec pcm037 (i.MX31) platforms"
36 select ARCH_MX31 38 select ARCH_MX31
39 select IMX_HAVE_PLATFORM_IMX_I2C
40 select IMX_HAVE_PLATFORM_IMX_UART
41 select IMX_HAVE_PLATFORM_MXC_NAND
37 select MXC_ULPI if USB_ULPI 42 select MXC_ULPI if USB_ULPI
38 help 43 help
39 Include support for Phytec pcm037 platform. This includes 44 Include support for Phytec pcm037 platform. This includes
@@ -42,6 +47,7 @@ config MACH_PCM037
42config MACH_PCM037_EET 47config MACH_PCM037_EET
43 bool "Support pcm037 EET board extensions" 48 bool "Support pcm037 EET board extensions"
44 depends on MACH_PCM037 49 depends on MACH_PCM037
50 select IMX_HAVE_PLATFORM_SPI_IMX
45 help 51 help
46 Add support for PCM037 EET baseboard extensions. If you are using the 52 Add support for PCM037 EET baseboard extensions. If you are using the
47 OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel 53 OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
@@ -51,6 +57,9 @@ config MACH_MX31LITE
51 bool "Support MX31 LITEKIT (LogicPD)" 57 bool "Support MX31 LITEKIT (LogicPD)"
52 select ARCH_MX31 58 select ARCH_MX31
53 select MXC_ULPI if USB_ULPI 59 select MXC_ULPI if USB_ULPI
60 select IMX_HAVE_PLATFORM_IMX_UART
61 select IMX_HAVE_PLATFORM_MXC_NAND
62 select IMX_HAVE_PLATFORM_SPI_IMX
54 help 63 help
55 Include support for MX31 LITEKIT platform. This includes specific 64 Include support for MX31 LITEKIT platform. This includes specific
56 configurations for the board and its peripherals. 65 configurations for the board and its peripherals.
@@ -58,6 +67,10 @@ config MACH_MX31LITE
58config MACH_MX31_3DS 67config MACH_MX31_3DS
59 bool "Support MX31PDK (3DS)" 68 bool "Support MX31PDK (3DS)"
60 select ARCH_MX31 69 select ARCH_MX31
70 select MXC_DEBUG_BOARD
71 select IMX_HAVE_PLATFORM_IMX_UART
72 select IMX_HAVE_PLATFORM_MXC_NAND
73 select IMX_HAVE_PLATFORM_SPI_IMX
61 help 74 help
62 Include support for MX31PDK (3DS) platform. This includes specific 75 Include support for MX31PDK (3DS) platform. This includes specific
63 configurations for the board and its peripherals. 76 configurations for the board and its peripherals.
@@ -74,6 +87,9 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
74config MACH_MX31MOBOARD 87config MACH_MX31MOBOARD
75 bool "Support mx31moboard platforms (EPFL Mobots group)" 88 bool "Support mx31moboard platforms (EPFL Mobots group)"
76 select ARCH_MX31 89 select ARCH_MX31
90 select IMX_HAVE_PLATFORM_IMX_I2C
91 select IMX_HAVE_PLATFORM_IMX_UART
92 select IMX_HAVE_PLATFORM_SPI_IMX
77 select MXC_ULPI if USB_ULPI 93 select MXC_ULPI if USB_ULPI
78 help 94 help
79 Include support for mx31moboard platform. This includes specific 95 Include support for mx31moboard platform. This includes specific
@@ -82,6 +98,8 @@ config MACH_MX31MOBOARD
82config MACH_MX31LILLY 98config MACH_MX31LILLY
83 bool "Support MX31 LILLY-1131 platforms (INCO startec)" 99 bool "Support MX31 LILLY-1131 platforms (INCO startec)"
84 select ARCH_MX31 100 select ARCH_MX31
101 select IMX_HAVE_PLATFORM_IMX_UART
102 select IMX_HAVE_PLATFORM_SPI_IMX
85 select MXC_ULPI if USB_ULPI 103 select MXC_ULPI if USB_ULPI
86 help 104 help
87 Include support for mx31 based LILLY1131 modules. This includes 105 Include support for mx31 based LILLY1131 modules. This includes
@@ -90,6 +108,7 @@ config MACH_MX31LILLY
90config MACH_QONG 108config MACH_QONG
91 bool "Support Dave/DENX QongEVB-LITE platform" 109 bool "Support Dave/DENX QongEVB-LITE platform"
92 select ARCH_MX31 110 select ARCH_MX31
111 select IMX_HAVE_PLATFORM_IMX_UART
93 help 112 help
94 Include support for Dave/DENX QongEVB-LITE platform. This includes 113 Include support for Dave/DENX QongEVB-LITE platform. This includes
95 specific configurations for the board and its peripherals. 114 specific configurations for the board and its peripherals.
@@ -97,6 +116,10 @@ config MACH_QONG
97config MACH_PCM043 116config MACH_PCM043
98 bool "Support Phytec pcm043 (i.MX35) platforms" 117 bool "Support Phytec pcm043 (i.MX35) platforms"
99 select ARCH_MX35 118 select ARCH_MX35
119 select IMX_HAVE_PLATFORM_IMX_I2C
120 select IMX_HAVE_PLATFORM_IMX_UART
121 select IMX_HAVE_PLATFORM_MXC_NAND
122 select IMX_HAVE_PLATFORM_FLEXCAN
100 select MXC_ULPI if USB_ULPI 123 select MXC_ULPI if USB_ULPI
101 help 124 help
102 Include support for Phytec pcm043 platform. This includes 125 Include support for Phytec pcm043 platform. This includes
@@ -105,6 +128,9 @@ config MACH_PCM043
105config MACH_ARMADILLO5X0 128config MACH_ARMADILLO5X0
106 bool "Support Atmark Armadillo-500 Development Base Board" 129 bool "Support Atmark Armadillo-500 Development Base Board"
107 select ARCH_MX31 130 select ARCH_MX31
131 select IMX_HAVE_PLATFORM_IMX_I2C
132 select IMX_HAVE_PLATFORM_IMX_UART
133 select IMX_HAVE_PLATFORM_MXC_NAND
108 select MXC_ULPI if USB_ULPI 134 select MXC_ULPI if USB_ULPI
109 help 135 help
110 Include support for Atmark Armadillo-500 platform. This includes 136 Include support for Atmark Armadillo-500 platform. This includes
@@ -113,6 +139,7 @@ config MACH_ARMADILLO5X0
113config MACH_MX35_3DS 139config MACH_MX35_3DS
114 bool "Support MX35PDK platform" 140 bool "Support MX35PDK platform"
115 select ARCH_MX35 141 select ARCH_MX35
142 select IMX_HAVE_PLATFORM_IMX_UART
116 default n 143 default n
117 help 144 help
118 Include support for MX35PDK platform. This includes specific 145 Include support for MX35PDK platform. This includes specific
@@ -121,8 +148,34 @@ config MACH_MX35_3DS
121config MACH_KZM_ARM11_01 148config MACH_KZM_ARM11_01
122 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" 149 bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
123 select ARCH_MX31 150 select ARCH_MX31
151 select IMX_HAVE_PLATFORM_IMX_UART
124 help 152 help
125 Include support for KZM-ARM11-01. This includes specific 153 Include support for KZM-ARM11-01. This includes specific
126 configurations for the board and its peripherals. 154 configurations for the board and its peripherals.
127 155
156config MACH_EUKREA_CPUIMX35
157 bool "Support Eukrea CPUIMX35 Platform"
158 select ARCH_MX35
159 select IMX_HAVE_PLATFORM_IMX_UART
160 select IMX_HAVE_PLATFORM_IMX_I2C
161 select IMX_HAVE_PLATFORM_MXC_NAND
162 select MXC_ULPI if USB_ULPI
163 help
164 Include support for Eukrea CPUIMX35 platform. This includes
165 specific configurations for the board and its peripherals.
166
167choice
168 prompt "Baseboard"
169 depends on MACH_EUKREA_CPUIMX35
170 default MACH_EUKREA_MBIMXSD35_BASEBOARD
171
172config MACH_EUKREA_MBIMXSD35_BASEBOARD
173 prompt "Eukrea MBIMXSD development board"
174 bool
175 help
176 This adds board specific devices that can be found on Eukrea's
177 MBIMXSD evaluation board.
178
179endchoice
180
128endif 181endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5d650fda5d5d..2bd7beceb991 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -22,5 +22,7 @@ obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
22obj-$(CONFIG_MACH_QONG) += mach-qong.o 22obj-$(CONFIG_MACH_QONG) += mach-qong.o
23obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o 23obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
24obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o 24obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
25obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o 25obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
26obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o 26obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
27obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
28obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 9f3e943e2232..d3af0fdf8475 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
359DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); 359DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
360DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); 360DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
361DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); 361DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
362DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL); 362DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_ahb, NULL);
363DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); 363DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
364DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); 364DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
365DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); 365DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
@@ -428,8 +428,8 @@ static struct clk nfc_clk = {
428static struct clk_lookup lookups[] = { 428static struct clk_lookup lookups[] = {
429 _REGISTER_CLOCK(NULL, "asrc", asrc_clk) 429 _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
430 _REGISTER_CLOCK(NULL, "ata", ata_clk) 430 _REGISTER_CLOCK(NULL, "ata", ata_clk)
431 _REGISTER_CLOCK(NULL, "can", can1_clk) 431 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
432 _REGISTER_CLOCK(NULL, "can", can2_clk) 432 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
433 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 433 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
434 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 434 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
435 _REGISTER_CLOCK(NULL, "ect", ect_clk) 435 _REGISTER_CLOCK(NULL, "ect", ect_clk)
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
new file mode 100644
index 000000000000..3b1a44a20585
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx31.h>
10#include <mach/devices-common.h>
11
12#define imx31_add_imx_i2c0(pdata) \
13 imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
14#define imx31_add_imx_i2c1(pdata) \
15 imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata)
16#define imx31_add_imx_i2c2(pdata) \
17 imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
18
19#define imx31_add_imx_uart0(pdata) \
20 imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
21#define imx31_add_imx_uart1(pdata) \
22 imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
23#define imx31_add_imx_uart2(pdata) \
24 imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
25#define imx31_add_imx_uart3(pdata) \
26 imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
27#define imx31_add_imx_uart4(pdata) \
28 imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
29
30#define imx31_add_mxc_nand(pdata) \
31 imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
32
33#define imx31_add_spi_imx0(pdata) \
34 imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
35#define imx31_add_spi_imx1(pdata) \
36 imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
37#define imx31_add_spi_imx2(pdata) \
38 imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
new file mode 100644
index 000000000000..f6a431a4c3d2
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -0,0 +1,37 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx35.h>
10#include <mach/devices-common.h>
11
12#define imx35_add_flexcan0(pdata) \
13 imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
14#define imx35_add_flexcan1(pdata) \
15 imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
16
17#define imx35_add_imx_i2c0(pdata) \
18 imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
19#define imx35_add_imx_i2c1(pdata) \
20 imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
21#define imx35_add_imx_i2c2(pdata) \
22 imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
23
24#define imx35_add_imx_uart0(pdata) \
25 imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
26#define imx35_add_imx_uart1(pdata) \
27 imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata)
28#define imx35_add_imx_uart2(pdata) \
29 imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata)
30
31#define imx35_add_mxc_nand(pdata) \
32 imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
33
34#define imx35_add_spi_imx0(pdata) \
35 imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
36#define imx35_add_spi_imx1(pdata) \
37 imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index db7acd6e9101..a4fd1a26fc91 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -25,108 +25,10 @@
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <mach/irqs.h> 26#include <mach/irqs.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/imx-uart.h>
29#include <mach/mx3_camera.h> 28#include <mach/mx3_camera.h>
30 29
31#include "devices.h" 30#include "devices.h"
32 31
33static struct resource uart0[] = {
34 {
35 .start = UART1_BASE_ADDR,
36 .end = UART1_BASE_ADDR + 0x0B5,
37 .flags = IORESOURCE_MEM,
38 }, {
39 .start = MXC_INT_UART1,
40 .end = MXC_INT_UART1,
41 .flags = IORESOURCE_IRQ,
42 },
43};
44
45struct platform_device mxc_uart_device0 = {
46 .name = "imx-uart",
47 .id = 0,
48 .resource = uart0,
49 .num_resources = ARRAY_SIZE(uart0),
50};
51
52static struct resource uart1[] = {
53 {
54 .start = UART2_BASE_ADDR,
55 .end = UART2_BASE_ADDR + 0x0B5,
56 .flags = IORESOURCE_MEM,
57 }, {
58 .start = MXC_INT_UART2,
59 .end = MXC_INT_UART2,
60 .flags = IORESOURCE_IRQ,
61 },
62};
63
64struct platform_device mxc_uart_device1 = {
65 .name = "imx-uart",
66 .id = 1,
67 .resource = uart1,
68 .num_resources = ARRAY_SIZE(uart1),
69};
70
71static struct resource uart2[] = {
72 {
73 .start = UART3_BASE_ADDR,
74 .end = UART3_BASE_ADDR + 0x0B5,
75 .flags = IORESOURCE_MEM,
76 }, {
77 .start = MXC_INT_UART3,
78 .end = MXC_INT_UART3,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83struct platform_device mxc_uart_device2 = {
84 .name = "imx-uart",
85 .id = 2,
86 .resource = uart2,
87 .num_resources = ARRAY_SIZE(uart2),
88};
89
90#ifdef CONFIG_ARCH_MX31
91static struct resource uart3[] = {
92 {
93 .start = UART4_BASE_ADDR,
94 .end = UART4_BASE_ADDR + 0x0B5,
95 .flags = IORESOURCE_MEM,
96 }, {
97 .start = MXC_INT_UART4,
98 .end = MXC_INT_UART4,
99 .flags = IORESOURCE_IRQ,
100 },
101};
102
103struct platform_device mxc_uart_device3 = {
104 .name = "imx-uart",
105 .id = 3,
106 .resource = uart3,
107 .num_resources = ARRAY_SIZE(uart3),
108};
109
110static struct resource uart4[] = {
111 {
112 .start = UART5_BASE_ADDR,
113 .end = UART5_BASE_ADDR + 0x0B5,
114 .flags = IORESOURCE_MEM,
115 }, {
116 .start = MXC_INT_UART5,
117 .end = MXC_INT_UART5,
118 .flags = IORESOURCE_IRQ,
119 },
120};
121
122struct platform_device mxc_uart_device4 = {
123 .name = "imx-uart",
124 .id = 4,
125 .resource = uart4,
126 .num_resources = ARRAY_SIZE(uart4),
127};
128#endif /* CONFIG_ARCH_MX31 */
129
130/* GPIO port description */ 32/* GPIO port description */
131static struct mxc_gpio_port imx_gpio_ports[] = { 33static struct mxc_gpio_port imx_gpio_ports[] = {
132 { 34 {
@@ -147,7 +49,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
147 } 49 }
148}; 50};
149 51
150int __init mxc_register_gpios(void) 52int __init imx3x_register_gpios(void)
151{ 53{
152 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 54 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
153} 55}
@@ -167,82 +69,6 @@ struct platform_device mxc_w1_master_device = {
167 .resource = mxc_w1_master_resources, 69 .resource = mxc_w1_master_resources,
168}; 70};
169 71
170static struct resource mxc_nand_resources[] = {
171 {
172 .start = 0, /* runtime dependent */
173 .end = 0,
174 .flags = IORESOURCE_MEM,
175 }, {
176 .start = MXC_INT_NANDFC,
177 .end = MXC_INT_NANDFC,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182struct platform_device mxc_nand_device = {
183 .name = "mxc_nand",
184 .id = 0,
185 .num_resources = ARRAY_SIZE(mxc_nand_resources),
186 .resource = mxc_nand_resources,
187};
188
189static struct resource mxc_i2c0_resources[] = {
190 {
191 .start = I2C_BASE_ADDR,
192 .end = I2C_BASE_ADDR + SZ_4K - 1,
193 .flags = IORESOURCE_MEM,
194 }, {
195 .start = MXC_INT_I2C,
196 .end = MXC_INT_I2C,
197 .flags = IORESOURCE_IRQ,
198 },
199};
200
201struct platform_device mxc_i2c_device0 = {
202 .name = "imx-i2c",
203 .id = 0,
204 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
205 .resource = mxc_i2c0_resources,
206};
207
208static struct resource mxc_i2c1_resources[] = {
209 {
210 .start = I2C2_BASE_ADDR,
211 .end = I2C2_BASE_ADDR + SZ_4K - 1,
212 .flags = IORESOURCE_MEM,
213 }, {
214 .start = MXC_INT_I2C2,
215 .end = MXC_INT_I2C2,
216 .flags = IORESOURCE_IRQ,
217 },
218};
219
220struct platform_device mxc_i2c_device1 = {
221 .name = "imx-i2c",
222 .id = 1,
223 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
224 .resource = mxc_i2c1_resources,
225};
226
227static struct resource mxc_i2c2_resources[] = {
228 {
229 .start = I2C3_BASE_ADDR,
230 .end = I2C3_BASE_ADDR + SZ_4K - 1,
231 .flags = IORESOURCE_MEM,
232 }, {
233 .start = MXC_INT_I2C3,
234 .end = MXC_INT_I2C3,
235 .flags = IORESOURCE_IRQ,
236 },
237};
238
239struct platform_device mxc_i2c_device2 = {
240 .name = "imx-i2c",
241 .id = 2,
242 .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
243 .resource = mxc_i2c2_resources,
244};
245
246#ifdef CONFIG_ARCH_MX31 72#ifdef CONFIG_ARCH_MX31
247static struct resource mxcsdhc0_resources[] = { 73static struct resource mxcsdhc0_resources[] = {
248 { 74 {
@@ -455,68 +281,7 @@ struct platform_device mxc_usbh2 = {
455 .num_resources = ARRAY_SIZE(mxc_usbh2_resources), 281 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
456}; 282};
457 283
458/* 284#if defined(CONFIG_ARCH_MX35)
459 * SPI master controller
460 * 3 channels
461 */
462static struct resource mxc_spi_0_resources[] = {
463 {
464 .start = CSPI1_BASE_ADDR,
465 .end = CSPI1_BASE_ADDR + SZ_4K - 1,
466 .flags = IORESOURCE_MEM,
467 }, {
468 .start = MXC_INT_CSPI1,
469 .end = MXC_INT_CSPI1,
470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474static struct resource mxc_spi_1_resources[] = {
475 {
476 .start = CSPI2_BASE_ADDR,
477 .end = CSPI2_BASE_ADDR + SZ_4K - 1,
478 .flags = IORESOURCE_MEM,
479 }, {
480 .start = MXC_INT_CSPI2,
481 .end = MXC_INT_CSPI2,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static struct resource mxc_spi_2_resources[] = {
487 {
488 .start = CSPI3_BASE_ADDR,
489 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
490 .flags = IORESOURCE_MEM,
491 }, {
492 .start = MXC_INT_CSPI3,
493 .end = MXC_INT_CSPI3,
494 .flags = IORESOURCE_IRQ,
495 },
496};
497
498struct platform_device mxc_spi_device0 = {
499 .name = "spi_imx",
500 .id = 0,
501 .num_resources = ARRAY_SIZE(mxc_spi_0_resources),
502 .resource = mxc_spi_0_resources,
503};
504
505struct platform_device mxc_spi_device1 = {
506 .name = "spi_imx",
507 .id = 1,
508 .num_resources = ARRAY_SIZE(mxc_spi_1_resources),
509 .resource = mxc_spi_1_resources,
510};
511
512struct platform_device mxc_spi_device2 = {
513 .name = "spi_imx",
514 .id = 2,
515 .num_resources = ARRAY_SIZE(mxc_spi_2_resources),
516 .resource = mxc_spi_2_resources,
517};
518
519#ifdef CONFIG_ARCH_MX35
520static struct resource mxc_fec_resources[] = { 285static struct resource mxc_fec_resources[] = {
521 { 286 {
522 .start = MXC_FEC_BASE_ADDR, 287 .start = MXC_FEC_BASE_ADDR,
@@ -628,16 +393,15 @@ struct platform_device imx_kpp_device = {
628 393
629static int __init mx3_devices_init(void) 394static int __init mx3_devices_init(void)
630{ 395{
396#if defined(CONFIG_ARCH_MX31)
631 if (cpu_is_mx31()) { 397 if (cpu_is_mx31()) {
632 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
633 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
634 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; 398 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
635 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; 399 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
636 mxc_register_device(&mxc_rnga_device, NULL); 400 mxc_register_device(&mxc_rnga_device, NULL);
637 } 401 }
402#endif
403#if defined(CONFIG_ARCH_MX35)
638 if (cpu_is_mx35()) { 404 if (cpu_is_mx35()) {
639 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
640 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
641 otg_resources[0].start = MX35_OTG_BASE_ADDR; 405 otg_resources[0].start = MX35_OTG_BASE_ADDR;
642 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; 406 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
643 otg_resources[1].start = MXC_INT_USBOTG; 407 otg_resources[1].start = MXC_INT_USBOTG;
@@ -653,6 +417,7 @@ static int __init mx3_devices_init(void)
653 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; 417 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
654 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; 418 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
655 } 419 }
420#endif
656 421
657 return 0; 422 return 0;
658} 423}
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 2c3c8646a29e..e5535234839f 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,14 +1,4 @@
1
2extern struct platform_device mxc_uart_device0;
3extern struct platform_device mxc_uart_device1;
4extern struct platform_device mxc_uart_device2;
5extern struct platform_device mxc_uart_device3;
6extern struct platform_device mxc_uart_device4;
7extern struct platform_device mxc_w1_master_device; 1extern struct platform_device mxc_w1_master_device;
8extern struct platform_device mxc_nand_device;
9extern struct platform_device mxc_i2c_device0;
10extern struct platform_device mxc_i2c_device1;
11extern struct platform_device mxc_i2c_device2;
12extern struct platform_device mx3_ipu; 2extern struct platform_device mx3_ipu;
13extern struct platform_device mx3_fb; 3extern struct platform_device mx3_fb;
14extern struct platform_device mx3_camera; 4extern struct platform_device mx3_camera;
@@ -20,9 +10,6 @@ extern struct platform_device mxc_otg_host;
20extern struct platform_device mxc_usbh1; 10extern struct platform_device mxc_usbh1;
21extern struct platform_device mxc_usbh2; 11extern struct platform_device mxc_usbh2;
22extern struct platform_device mxc_rnga_device; 12extern struct platform_device mxc_rnga_device;
23extern struct platform_device mxc_spi_device0;
24extern struct platform_device mxc_spi_device1;
25extern struct platform_device mxc_spi_device2;
26extern struct platform_device imx_ssi_device0; 13extern struct platform_device imx_ssi_device0;
27extern struct platform_device imx_ssi_device1; 14extern struct platform_device imx_ssi_device1;
28extern struct platform_device imx_ssi_device1; 15extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..1dc5004df866
--- /dev/null
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,263 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31#include <video/platform_lcd.h>
32#include <linux/i2c.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include <mach/hardware.h>
40#include <mach/common.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx35.h>
43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
45#include <mach/audmux.h>
46#include <mach/ssi.h>
47
48#include "devices-imx35.h"
49#include "devices.h"
50
51static const struct fb_videomode fb_modedb[] = {
52 {
53 .name = "CMO_QVGA",
54 .refresh = 60,
55 .xres = 320,
56 .yres = 240,
57 .pixclock = KHZ2PICOS(6500),
58 .left_margin = 68,
59 .right_margin = 20,
60 .upper_margin = 15,
61 .lower_margin = 4,
62 .hsync_len = 30,
63 .vsync_len = 3,
64 .sync = 0,
65 .vmode = FB_VMODE_NONINTERLACED,
66 .flag = 0,
67 },
68};
69
70static struct ipu_platform_data mx3_ipu_data = {
71 .irq_base = MXC_IPU_IRQ_START,
72};
73
74static struct mx3fb_platform_data mx3fb_pdata = {
75 .dma_dev = &mx3_ipu.dev,
76 .name = "CMO_QVGA",
77 .mode = fb_modedb,
78 .num_modes = ARRAY_SIZE(fb_modedb),
79};
80
81static struct pad_desc eukrea_mbimxsd_pads[] = {
82 /* LCD */
83 MX35_PAD_LD0__IPU_DISPB_DAT_0,
84 MX35_PAD_LD1__IPU_DISPB_DAT_1,
85 MX35_PAD_LD2__IPU_DISPB_DAT_2,
86 MX35_PAD_LD3__IPU_DISPB_DAT_3,
87 MX35_PAD_LD4__IPU_DISPB_DAT_4,
88 MX35_PAD_LD5__IPU_DISPB_DAT_5,
89 MX35_PAD_LD6__IPU_DISPB_DAT_6,
90 MX35_PAD_LD7__IPU_DISPB_DAT_7,
91 MX35_PAD_LD8__IPU_DISPB_DAT_8,
92 MX35_PAD_LD9__IPU_DISPB_DAT_9,
93 MX35_PAD_LD10__IPU_DISPB_DAT_10,
94 MX35_PAD_LD11__IPU_DISPB_DAT_11,
95 MX35_PAD_LD12__IPU_DISPB_DAT_12,
96 MX35_PAD_LD13__IPU_DISPB_DAT_13,
97 MX35_PAD_LD14__IPU_DISPB_DAT_14,
98 MX35_PAD_LD15__IPU_DISPB_DAT_15,
99 MX35_PAD_LD16__IPU_DISPB_DAT_16,
100 MX35_PAD_LD17__IPU_DISPB_DAT_17,
101 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
102 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
103 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
104 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
105 /* Backlight */
106 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
107 /* LCD_PWR */
108 MX35_PAD_D3_CLS__GPIO1_4,
109 /* LED */
110 MX35_PAD_LD23__GPIO3_29,
111 /* SWITCH */
112 MX35_PAD_LD19__GPIO3_25,
113 /* UART2 */
114 MX35_PAD_CTS2__UART2_CTS,
115 MX35_PAD_RTS2__UART2_RTS,
116 MX35_PAD_TXD2__UART2_TXD_MUX,
117 MX35_PAD_RXD2__UART2_RXD_MUX,
118 /* I2S */
119 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
120 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
121 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
122 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
123};
124
125#define GPIO_LED1 (2 * 32 + 29)
126#define GPIO_SWITCH1 (2 * 32 + 25)
127#define GPIO_LCDPWR (4)
128
129static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
130 unsigned int power)
131{
132 if (power)
133 gpio_direction_output(GPIO_LCDPWR, 1);
134 else
135 gpio_direction_output(GPIO_LCDPWR, 0);
136}
137
138static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
139 .set_power = eukrea_mbimxsd_lcd_power_set,
140};
141
142static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
143 .name = "platform-lcd",
144 .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
145};
146
147static struct gpio_led eukrea_mbimxsd_leds[] = {
148 {
149 .name = "led1",
150 .default_trigger = "heartbeat",
151 .active_low = 1,
152 .gpio = GPIO_LED1,
153 },
154};
155
156static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
157 .leds = eukrea_mbimxsd_leds,
158 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
159};
160
161static struct platform_device eukrea_mbimxsd_leds_gpio = {
162 .name = "leds-gpio",
163 .id = -1,
164 .dev = {
165 .platform_data = &eukrea_mbimxsd_led_info,
166 },
167};
168
169static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
170 {
171 .gpio = GPIO_SWITCH1,
172 .code = BTN_0,
173 .desc = "BP1",
174 .active_low = 1,
175 .wakeup = 1,
176 },
177};
178
179static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
180 .buttons = eukrea_mbimxsd_gpio_buttons,
181 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
182};
183
184static struct platform_device eukrea_mbimxsd_button_device = {
185 .name = "gpio-keys",
186 .id = -1,
187 .num_resources = 0,
188 .dev = {
189 .platform_data = &eukrea_mbimxsd_button_data,
190 }
191};
192
193static struct platform_device *platform_devices[] __initdata = {
194 &eukrea_mbimxsd_leds_gpio,
195 &eukrea_mbimxsd_button_device,
196 &eukrea_mbimxsd_lcd_powerdev,
197};
198
199static const struct imxuart_platform_data uart_pdata __initconst = {
200 .flags = IMXUART_HAVE_RTSCTS,
201};
202
203static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
204 {
205 I2C_BOARD_INFO("tlv320aic23", 0x1a),
206 },
207};
208
209struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
210 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
211};
212
213/*
214 * system init for baseboard usage. Will be called by cpuimx35 init.
215 *
216 * Add platform devices present on this baseboard and init
217 * them from CPU side as far as required to use them later on
218 */
219void __init eukrea_mbimxsd_baseboard_init(void)
220{
221 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
222 ARRAY_SIZE(eukrea_mbimxsd_pads)))
223 printk(KERN_ERR "error setting mbimxsd pads !\n");
224
225#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
226 /* SSI unit master I2S codec connected to SSI_AUD4 */
227 mxc_audmux_v2_configure_port(0,
228 MXC_AUDMUX_V2_PTCR_SYN |
229 MXC_AUDMUX_V2_PTCR_TFSDIR |
230 MXC_AUDMUX_V2_PTCR_TFSEL(3) |
231 MXC_AUDMUX_V2_PTCR_TCLKDIR |
232 MXC_AUDMUX_V2_PTCR_TCSEL(3),
233 MXC_AUDMUX_V2_PDCR_RXDSEL(3)
234 );
235 mxc_audmux_v2_configure_port(3,
236 MXC_AUDMUX_V2_PTCR_SYN,
237 MXC_AUDMUX_V2_PDCR_RXDSEL(0)
238 );
239#endif
240
241 imx35_add_imx_uart1(&uart_pdata);
242 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
243 mxc_register_device(&mx3_fb, &mx3fb_pdata);
244
245 mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
246
247 gpio_request(GPIO_LED1, "LED1");
248 gpio_direction_output(GPIO_LED1, 1);
249 gpio_free(GPIO_LED1);
250
251 gpio_request(GPIO_SWITCH1, "SWITCH1");
252 gpio_direction_input(GPIO_SWITCH1);
253 gpio_free(GPIO_SWITCH1);
254
255 gpio_request(GPIO_LCDPWR, "LCDPWR");
256 gpio_direction_output(GPIO_LCDPWR, 1);
257 gpio_free(GPIO_SWITCH1);
258
259 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
260 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
261
262 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
263}
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 5f72ec91af2d..96aadcadb4ff 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -48,16 +48,14 @@
48#include <asm/mach/map.h> 48#include <asm/mach/map.h>
49 49
50#include <mach/common.h> 50#include <mach/common.h>
51#include <mach/imx-uart.h>
52#include <mach/iomux-mx3.h> 51#include <mach/iomux-mx3.h>
53#include <mach/board-armadillo5x0.h>
54#include <mach/mmc.h> 52#include <mach/mmc.h>
55#include <mach/ipu.h> 53#include <mach/ipu.h>
56#include <mach/mx3fb.h> 54#include <mach/mx3fb.h>
57#include <mach/mxc_nand.h>
58#include <mach/mxc_ehci.h> 55#include <mach/mxc_ehci.h>
59#include <mach/ulpi.h> 56#include <mach/ulpi.h>
60 57
58#include "devices-imx31.h"
61#include "devices.h" 59#include "devices.h"
62#include "crm_regs.h" 60#include "crm_regs.h"
63 61
@@ -301,7 +299,8 @@ static struct platform_device armadillo5x0_button_device = {
301/* 299/*
302 * NAND Flash 300 * NAND Flash
303 */ 301 */
304static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = { 302static const struct mxc_nand_platform_data
303armadillo5x0_nand_board_info __initconst = {
305 .width = 1, 304 .width = 1,
306 .hw_ecc = 1, 305 .hw_ecc = 1,
307}; 306};
@@ -493,13 +492,12 @@ static struct platform_device armadillo5x0_smc911x_device = {
493}; 492};
494 493
495/* UART device data */ 494/* UART device data */
496static struct imxuart_platform_data uart_pdata = { 495static const struct imxuart_platform_data uart_pdata __initconst = {
497 .flags = IMXUART_HAVE_RTSCTS, 496 .flags = IMXUART_HAVE_RTSCTS,
498}; 497};
499 498
500static struct platform_device *devices[] __initdata = { 499static struct platform_device *devices[] __initdata = {
501 &armadillo5x0_smc911x_device, 500 &armadillo5x0_smc911x_device,
502 &mxc_i2c_device1,
503 &armadillo5x0_button_device, 501 &armadillo5x0_button_device,
504}; 502};
505 503
@@ -512,10 +510,11 @@ static void __init armadillo5x0_init(void)
512 ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); 510 ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
513 511
514 platform_add_devices(devices, ARRAY_SIZE(devices)); 512 platform_add_devices(devices, ARRAY_SIZE(devices));
513 imx31_add_imx_i2c1(NULL);
515 514
516 /* Register UART */ 515 /* Register UART */
517 mxc_register_device(&mxc_uart_device0, &uart_pdata); 516 imx31_add_imx_uart0(&uart_pdata);
518 mxc_register_device(&mxc_uart_device1, &uart_pdata); 517 imx31_add_imx_uart1(&uart_pdata);
519 518
520 /* SMSC9118 IRQ pin */ 519 /* SMSC9118 IRQ pin */
521 gpio_direction_input(MX31_PIN_GPIO1_0); 520 gpio_direction_input(MX31_PIN_GPIO1_0);
@@ -532,7 +531,7 @@ static void __init armadillo5x0_init(void)
532 &armadillo5x0_nor_flash_pdata); 531 &armadillo5x0_nor_flash_pdata);
533 532
534 /* Register NAND Flash */ 533 /* Register NAND Flash */
535 mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata); 534 imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
536 535
537 /* set NAND page size to 2k if not configured via boot mode pins */ 536 /* set NAND page size to 2k if not configured via boot mode pins */
538 __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); 537 __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
new file mode 100644
index 000000000000..63f970f340a2
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -0,0 +1,227 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22
23#include <linux/platform_device.h>
24#include <linux/mtd/physmap.h>
25#include <linux/memory.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/i2c/tsc2007.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <linux/fsl_devices.h>
34
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/time.h>
38#include <asm/mach/map.h>
39
40#include <mach/eukrea-baseboards.h>
41#include <mach/hardware.h>
42#include <mach/common.h>
43#include <mach/iomux-mx35.h>
44#include <mach/mxc_nand.h>
45#include <mach/mxc_ehci.h>
46#include <mach/ulpi.h>
47
48#include "devices-imx35.h"
49#include "devices.h"
50
51static const struct imxuart_platform_data uart_pdata __initconst = {
52 .flags = IMXUART_HAVE_RTSCTS,
53};
54
55static const struct imxi2c_platform_data
56eukrea_cpuimx35_i2c0_data __initconst = {
57 .bitrate = 50000,
58};
59
60#define TSC2007_IRQGPIO (2 * 32 + 2)
61static int ts_get_pendown_state(void)
62{
63 int val = 0;
64 gpio_free(TSC2007_IRQGPIO);
65 gpio_request(TSC2007_IRQGPIO, NULL);
66 gpio_direction_input(TSC2007_IRQGPIO);
67
68 val = gpio_get_value(TSC2007_IRQGPIO);
69
70 gpio_free(TSC2007_IRQGPIO);
71 gpio_request(TSC2007_IRQGPIO, NULL);
72
73 return val ? 0 : 1;
74}
75
76static int ts_init(void)
77{
78 gpio_request(TSC2007_IRQGPIO, NULL);
79 return 0;
80}
81
82static struct tsc2007_platform_data tsc2007_info = {
83 .model = 2007,
84 .x_plate_ohms = 180,
85 .get_pendown_state = ts_get_pendown_state,
86 .init_platform_hw = ts_init,
87};
88
89static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
90 {
91 I2C_BOARD_INFO("pcf8563", 0x51),
92 }, {
93 I2C_BOARD_INFO("tsc2007", 0x48),
94 .type = "tsc2007",
95 .platform_data = &tsc2007_info,
96 .irq = gpio_to_irq(TSC2007_IRQGPIO),
97 },
98};
99
100static struct platform_device *devices[] __initdata = {
101 &mxc_fec_device,
102 &imx_wdt_device0,
103};
104
105static struct pad_desc eukrea_cpuimx35_pads[] = {
106 /* UART1 */
107 MX35_PAD_CTS1__UART1_CTS,
108 MX35_PAD_RTS1__UART1_RTS,
109 MX35_PAD_TXD1__UART1_TXD_MUX,
110 MX35_PAD_RXD1__UART1_RXD_MUX,
111 /* FEC */
112 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
113 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
114 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
115 MX35_PAD_FEC_COL__FEC_COL,
116 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
117 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
118 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
119 MX35_PAD_FEC_MDC__FEC_MDC,
120 MX35_PAD_FEC_MDIO__FEC_MDIO,
121 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
122 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
123 MX35_PAD_FEC_CRS__FEC_CRS,
124 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
125 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
126 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
127 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
128 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
129 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
130 /* I2C1 */
131 MX35_PAD_I2C1_CLK__I2C1_SCL,
132 MX35_PAD_I2C1_DAT__I2C1_SDA,
133 /* TSC2007 IRQ */
134 MX35_PAD_ATA_DA2__GPIO3_2,
135};
136
137static const struct mxc_nand_platform_data
138eukrea_cpuimx35_nand_board_info __initconst = {
139 .width = 1,
140 .hw_ecc = 1,
141 .flash_bbt = 1,
142};
143
144static struct mxc_usbh_platform_data otg_pdata = {
145 .portsc = MXC_EHCI_MODE_UTMI,
146 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
147};
148
149static struct mxc_usbh_platform_data usbh1_pdata = {
150 .portsc = MXC_EHCI_MODE_SERIAL,
151 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
152 MXC_EHCI_IPPUE_DOWN,
153};
154
155static struct fsl_usb2_platform_data otg_device_pdata = {
156 .operating_mode = FSL_USB2_DR_DEVICE,
157 .phy_mode = FSL_USB2_PHY_UTMI,
158};
159
160static int otg_mode_host;
161
162static int __init eukrea_cpuimx35_otg_mode(char *options)
163{
164 if (!strcmp(options, "host"))
165 otg_mode_host = 1;
166 else if (!strcmp(options, "device"))
167 otg_mode_host = 0;
168 else
169 pr_info("otg_mode neither \"host\" nor \"device\". "
170 "Defaulting to device\n");
171 return 0;
172}
173__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
174
175/*
176 * Board specific initialization.
177 */
178static void __init mxc_board_init(void)
179{
180 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
181 ARRAY_SIZE(eukrea_cpuimx35_pads));
182
183 platform_add_devices(devices, ARRAY_SIZE(devices));
184
185 imx35_add_imx_uart0(&uart_pdata);
186 imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
187
188 i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
189 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
190 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
191
192#if defined(CONFIG_USB_ULPI)
193 if (otg_mode_host) {
194 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
195 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
196
197 mxc_register_device(&mxc_otg_host, &otg_pdata);
198 }
199 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
200#endif
201 if (!otg_mode_host)
202 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
203
204#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
205 eukrea_mbimxsd_baseboard_init();
206#endif
207}
208
209static void __init eukrea_cpuimx35_timer_init(void)
210{
211 mx35_clocks_init();
212}
213
214struct sys_timer eukrea_cpuimx35_timer = {
215 .init = eukrea_cpuimx35_timer_init,
216};
217
218MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
219 /* Maintainer: Eukrea Electromatique */
220 .phys_io = MX35_AIPS1_BASE_ADDR,
221 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
222 .boot_params = MX3x_PHYS_OFFSET + 0x100,
223 .map_io = mx35_map_io,
224 .init_irq = mx35_init_irq,
225 .init_machine = mxc_board_init,
226 .timer = &eukrea_cpuimx35_timer,
227MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index f085d5d1a6de..5b23e416d6c7 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -16,10 +16,6 @@
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */ 19 */
24 20
25#include <linux/gpio.h> 21#include <linux/gpio.h>
@@ -37,13 +33,12 @@
37#include <asm/mach/map.h> 33#include <asm/mach/map.h>
38#include <asm/mach/time.h> 34#include <asm/mach/time.h>
39 35
40#include <mach/board-kzmarm11.h>
41#include <mach/clock.h> 36#include <mach/clock.h>
42#include <mach/common.h> 37#include <mach/common.h>
43#include <mach/imx-uart.h>
44#include <mach/iomux-mx3.h> 38#include <mach/iomux-mx3.h>
45#include <mach/memory.h> 39#include <mach/memory.h>
46 40
41#include "devices-imx31.h"
47#include "devices.h" 42#include "devices.h"
48 43
49#define KZM_ARM11_IO_ADDRESS(x) ( \ 44#define KZM_ARM11_IO_ADDRESS(x) ( \
@@ -51,6 +46,23 @@
51 IMX_IO_ADDRESS(x, MX31_CS5) ?: \ 46 IMX_IO_ADDRESS(x, MX31_CS5) ?: \
52 MX31_IO_ADDRESS(x)) 47 MX31_IO_ADDRESS(x))
53 48
49/*
50 * KZM-ARM11-01 Board Control Registers on FPGA
51 */
52#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
53#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
54#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
55#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
56#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
57#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
58#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
59#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
60
61/*
62 * External UART for touch panel on FPGA
63 */
64#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
65
54#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 66#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
55/* 67/*
56 * KZM-ARM11-01 has an external UART on FPGA 68 * KZM-ARM11-01 has an external UART on FPGA
@@ -173,15 +185,14 @@ static inline int kzm_init_smsc9118(void)
173#endif 185#endif
174 186
175#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 187#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
176static struct imxuart_platform_data uart_pdata = { 188static const struct imxuart_platform_data uart_pdata __initconst = {
177 .flags = IMXUART_HAVE_RTSCTS, 189 .flags = IMXUART_HAVE_RTSCTS,
178}; 190};
179 191
180static void __init kzm_init_imx_uart(void) 192static void __init kzm_init_imx_uart(void)
181{ 193{
182 mxc_register_device(&mxc_uart_device0, &uart_pdata); 194 imx31_add_imx_uart0(&uart_pdata);
183 195 imx31_add_imx_uart1(&uart_pdata);
184 mxc_register_device(&mxc_uart_device1, &uart_pdata);
185} 196}
186#else 197#else
187static inline void kzm_init_imx_uart(void) 198static inline void kzm_init_imx_uart(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e57291b79d..6fe69e124d30 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/delay.h> 15#include <linux/delay.h>
@@ -22,7 +18,6 @@
22#include <linux/clk.h> 18#include <linux/clk.h>
23#include <linux/irq.h> 19#include <linux/irq.h>
24#include <linux/gpio.h> 20#include <linux/gpio.h>
25#include <linux/smsc911x.h>
26#include <linux/platform_device.h> 21#include <linux/platform_device.h>
27#include <linux/mfd/mc13783.h> 22#include <linux/mfd/mc13783.h>
28#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
@@ -37,19 +32,47 @@
37#include <asm/memory.h> 32#include <asm/memory.h>
38#include <asm/mach/map.h> 33#include <asm/mach/map.h>
39#include <mach/common.h> 34#include <mach/common.h>
40#include <mach/board-mx31_3ds.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx3.h> 35#include <mach/iomux-mx3.h>
43#include <mach/mxc_nand.h> 36#include <mach/3ds_debugboard.h>
44#include <mach/spi.h> 37
38#include "devices-imx31.h"
45#include "devices.h" 39#include "devices.h"
46 40
47/*! 41/* Definitions for components on the Debug board */
48 * @file mx31_3ds.c 42
49 * 43/* Base address of CPLD controller on the Debug board */
50 * @brief This file contains the board-specific initialization routines. 44#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
51 * 45
52 * @ingroup System 46/* LAN9217 ethernet base address */
47#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
48
49/* CPLD config and interrupt base address */
50#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
51
52/* status, interrupt */
53#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
54#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
55#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
56/* magic word for debug CPLD */
57#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
58#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
59/* CPLD code version */
60#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
61/* magic word for debug CPLD */
62#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
63
64/* CPLD IRQ line for external uart, external ethernet etc */
65#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
66
67#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
68#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
69
70#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
71
72#define MXC_MAX_EXP_IO_LINES 16
73
74/*
75 * This file contains the board-specific initialization routines.
53 */ 76 */
54 77
55static int mx31_3ds_pins[] = { 78static int mx31_3ds_pins[] = {
@@ -145,7 +168,7 @@ static int spi1_internal_chipselect[] = {
145 MXC_SPI_CS(2), 168 MXC_SPI_CS(2),
146}; 169};
147 170
148static struct spi_imx_master spi1_pdata = { 171static const struct spi_imx_master spi1_pdata __initconst = {
149 .chipselect = spi1_internal_chipselect, 172 .chipselect = spi1_internal_chipselect,
150 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), 173 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
151}; 174};
@@ -165,7 +188,8 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
165/* 188/*
166 * NAND Flash 189 * NAND Flash
167 */ 190 */
168static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = { 191static const struct mxc_nand_platform_data
192mx31_3ds_nand_board_info __initconst = {
169 .width = 1, 193 .width = 1,
170 .hw_ecc = 1, 194 .hw_ecc = 1,
171#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT 195#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
@@ -182,8 +206,10 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
182 206
183#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) 207#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
184 208
185static void mx31_3ds_usbotg_init(void) 209static int mx31_3ds_usbotg_init(void)
186{ 210{
211 int err;
212
187 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); 213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
188 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); 214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
189 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); 215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
@@ -197,10 +223,25 @@ static void mx31_3ds_usbotg_init(void)
197 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); 223 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
198 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); 224 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
199 225
200 gpio_request(USBOTG_RST_B, "otgusb-reset"); 226 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
201 gpio_direction_output(USBOTG_RST_B, 0); 227 if (err) {
228 pr_err("Failed to request the USB OTG reset gpio\n");
229 return err;
230 }
231
232 err = gpio_direction_output(USBOTG_RST_B, 0);
233 if (err) {
234 pr_err("Failed to drive the USB OTG reset gpio\n");
235 goto usbotg_free_reset;
236 }
237
202 mdelay(1); 238 mdelay(1);
203 gpio_set_value(USBOTG_RST_B, 1); 239 gpio_set_value(USBOTG_RST_B, 1);
240 return 0;
241
242usbotg_free_reset:
243 gpio_free(USBOTG_RST_B);
244 return err;
204} 245}
205 246
206static struct fsl_usb2_platform_data usbotg_pdata = { 247static struct fsl_usb2_platform_data usbotg_pdata = {
@@ -208,178 +249,16 @@ static struct fsl_usb2_platform_data usbotg_pdata = {
208 .phy_mode = FSL_USB2_PHY_ULPI, 249 .phy_mode = FSL_USB2_PHY_ULPI,
209}; 250};
210 251
211static struct imxuart_platform_data uart_pdata = { 252static const struct imxuart_platform_data uart_pdata __initconst = {
212 .flags = IMXUART_HAVE_RTSCTS, 253 .flags = IMXUART_HAVE_RTSCTS,
213}; 254};
214 255
215/* 256/*
216 * Support for the SMSC9217 on the Debug board.
217 */
218
219static struct smsc911x_platform_config smsc911x_config = {
220 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
221 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
222 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
223 .phy_interface = PHY_INTERFACE_MODE_MII,
224};
225
226static struct resource smsc911x_resources[] = {
227 {
228 .start = LAN9217_BASE_ADDR,
229 .end = LAN9217_BASE_ADDR + 0xff,
230 .flags = IORESOURCE_MEM,
231 }, {
232 .start = EXPIO_INT_ENET,
233 .end = EXPIO_INT_ENET,
234 .flags = IORESOURCE_IRQ,
235 },
236};
237
238static struct platform_device smsc911x_device = {
239 .name = "smsc911x",
240 .id = -1,
241 .num_resources = ARRAY_SIZE(smsc911x_resources),
242 .resource = smsc911x_resources,
243 .dev = {
244 .platform_data = &smsc911x_config,
245 },
246};
247
248/*
249 * Routines for the CPLD on the debug board. It contains a CPLD handling
250 * LEDs, switches, interrupts for Ethernet.
251 */
252
253static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
254{
255 uint32_t imr_val;
256 uint32_t int_valid;
257 uint32_t expio_irq;
258
259 imr_val = __raw_readw(CPLD_INT_MASK_REG);
260 int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
261
262 expio_irq = MXC_EXP_IO_BASE;
263 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
264 if ((int_valid & 1) == 0)
265 continue;
266 generic_handle_irq(expio_irq);
267 }
268}
269
270/*
271 * Disable an expio pin's interrupt by setting the bit in the imr.
272 * @param irq an expio virtual irq number
273 */
274static void expio_mask_irq(uint32_t irq)
275{
276 uint16_t reg;
277 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
278
279 /* mask the interrupt */
280 reg = __raw_readw(CPLD_INT_MASK_REG);
281 reg |= 1 << expio;
282 __raw_writew(reg, CPLD_INT_MASK_REG);
283}
284
285/*
286 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
287 * @param irq an expanded io virtual irq number
288 */
289static void expio_ack_irq(uint32_t irq)
290{
291 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
292
293 /* clear the interrupt status */
294 __raw_writew(1 << expio, CPLD_INT_RESET_REG);
295 __raw_writew(0, CPLD_INT_RESET_REG);
296 /* mask the interrupt */
297 expio_mask_irq(irq);
298}
299
300/*
301 * Enable a expio pin's interrupt by clearing the bit in the imr.
302 * @param irq a expio virtual irq number
303 */
304static void expio_unmask_irq(uint32_t irq)
305{
306 uint16_t reg;
307 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
308
309 /* unmask the interrupt */
310 reg = __raw_readw(CPLD_INT_MASK_REG);
311 reg &= ~(1 << expio);
312 __raw_writew(reg, CPLD_INT_MASK_REG);
313}
314
315static struct irq_chip expio_irq_chip = {
316 .ack = expio_ack_irq,
317 .mask = expio_mask_irq,
318 .unmask = expio_unmask_irq,
319};
320
321static int __init mx31_3ds_init_expio(void)
322{
323 int i;
324 int ret;
325
326 /* Check if there's a debug board connected */
327 if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
328 (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
329 (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
330 /* No Debug board found */
331 return -ENODEV;
332 }
333
334 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
335 __raw_readw(CPLD_CODE_VER_REG));
336
337 /*
338 * Configure INT line as GPIO input
339 */
340 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
341 if (ret)
342 pr_warning("could not get LAN irq gpio\n");
343 else
344 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
345
346 /* Disable the interrupts and clear the status */
347 __raw_writew(0, CPLD_INT_MASK_REG);
348 __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
349 __raw_writew(0, CPLD_INT_RESET_REG);
350 __raw_writew(0x1F, CPLD_INT_MASK_REG);
351 for (i = MXC_EXP_IO_BASE;
352 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
353 i++) {
354 set_irq_chip(i, &expio_irq_chip);
355 set_irq_handler(i, handle_level_irq);
356 set_irq_flags(i, IRQF_VALID);
357 }
358 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
359 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
360
361 return 0;
362}
363
364/*
365 * This structure defines the MX31 memory map.
366 */
367static struct map_desc mx31_3ds_io_desc[] __initdata = {
368 {
369 .virtual = MX31_CS5_BASE_ADDR_VIRT,
370 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
371 .length = MX31_CS5_SIZE,
372 .type = MT_DEVICE,
373 },
374};
375
376/*
377 * Set up static virtual mappings. 257 * Set up static virtual mappings.
378 */ 258 */
379static void __init mx31_3ds_map_io(void) 259static void __init mx31_3ds_map_io(void)
380{ 260{
381 mx31_map_io(); 261 mx31_map_io();
382 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
383} 262}
384 263
385/*! 264/*!
@@ -390,10 +269,10 @@ static void __init mxc_board_init(void)
390 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), 269 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
391 "mx31_3ds"); 270 "mx31_3ds");
392 271
393 mxc_register_device(&mxc_uart_device0, &uart_pdata); 272 imx31_add_imx_uart0(&uart_pdata);
394 mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata); 273 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
395 274
396 mxc_register_device(&mxc_spi_device1, &spi1_pdata); 275 imx31_add_spi_imx0(&spi1_pdata);
397 spi_register_board_info(mx31_3ds_spi_devs, 276 spi_register_board_info(mx31_3ds_spi_devs,
398 ARRAY_SIZE(mx31_3ds_spi_devs)); 277 ARRAY_SIZE(mx31_3ds_spi_devs));
399 278
@@ -402,8 +281,9 @@ static void __init mxc_board_init(void)
402 mx31_3ds_usbotg_init(); 281 mx31_3ds_usbotg_init();
403 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); 282 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
404 283
405 if (!mx31_3ds_init_expio()) 284 if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
406 platform_device_register(&smsc911x_device); 285 printk(KERN_WARNING "Init of the debugboard failed, all "
286 "devices on the board are unusable.\n");
407} 287}
408 288
409static void __init mx31_3ds_timer_init(void) 289static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index b3d1a1895c20..94b3e7c42404 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#include <linux/types.h> 17#include <linux/types.h>
@@ -33,8 +29,6 @@
33#include <asm/memory.h> 29#include <asm/memory.h>
34#include <asm/mach/map.h> 30#include <asm/mach/map.h>
35#include <mach/common.h> 31#include <mach/common.h>
36#include <mach/board-mx31ads.h>
37#include <mach/imx-uart.h>
38#include <mach/iomux-mx3.h> 32#include <mach/iomux-mx3.h>
39 33
40#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -43,14 +37,45 @@
43#include <linux/mfd/wm8350/pmic.h> 37#include <linux/mfd/wm8350/pmic.h>
44#endif 38#endif
45 39
40#include "devices-imx31.h"
46#include "devices.h" 41#include "devices.h"
47 42
48/*! 43/* Base address of PBC controller */
49 * @file mx31ads.c 44#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
50 * 45/* Offsets for the PBC Controller register */
51 * @brief This file contains the board-specific initialization routines. 46
52 * 47/* PBC Board interrupt status register */
53 * @ingroup System 48#define PBC_INTSTATUS 0x000016
49
50/* PBC Board interrupt current status register */
51#define PBC_INTCURR_STATUS 0x000018
52
53/* PBC Interrupt mask register set address */
54#define PBC_INTMASK_SET 0x00001A
55
56/* PBC Interrupt mask register clear address */
57#define PBC_INTMASK_CLEAR 0x00001C
58
59/* External UART A */
60#define PBC_SC16C652_UARTA 0x010000
61
62/* External UART B */
63#define PBC_SC16C652_UARTB 0x010010
64
65#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
66#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
67#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
68#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
69
70#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
71#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
72
73#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
74#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
75
76#define MXC_MAX_EXP_IO_LINES 16
77/*
78 * This file contains the board-specific initialization routines.
54 */ 79 */
55 80
56#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 81#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
@@ -98,7 +123,7 @@ static inline int mxc_init_extuart(void)
98#endif 123#endif
99 124
100#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 125#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
101static struct imxuart_platform_data uart_pdata = { 126static const struct imxuart_platform_data uart_pdata __initconst = {
102 .flags = IMXUART_HAVE_RTSCTS, 127 .flags = IMXUART_HAVE_RTSCTS,
103}; 128};
104 129
@@ -112,7 +137,7 @@ static unsigned int uart_pins[] = {
112static inline void mxc_init_imx_uart(void) 137static inline void mxc_init_imx_uart(void)
113{ 138{
114 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); 139 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
115 mxc_register_device(&mxc_uart_device0, &uart_pdata); 140 imx31_add_imx_uart0(&uart_pdata);
116} 141}
117#else /* !SERIAL_IMX */ 142#else /* !SERIAL_IMX */
118static inline void mxc_init_imx_uart(void) 143static inline void mxc_init_imx_uart(void)
@@ -475,7 +500,7 @@ static void mxc_init_i2c(void)
475 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); 500 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
476 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); 501 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
477 502
478 mxc_register_device(&mxc_i2c_device1, NULL); 503 imx31_add_imx_i2c1(NULL);
479} 504}
480#else 505#else
481static void mxc_init_i2c(void) 506static void mxc_init_i2c(void)
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index b2c7f512070f..8f66f65e80e2 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -18,10 +18,6 @@
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details. 20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */ 21 */
26 22
27#include <linux/types.h> 23#include <linux/types.h>
@@ -46,10 +42,10 @@
46#include <mach/common.h> 42#include <mach/common.h>
47#include <mach/iomux-mx3.h> 43#include <mach/iomux-mx3.h>
48#include <mach/board-mx31lilly.h> 44#include <mach/board-mx31lilly.h>
49#include <mach/spi.h>
50#include <mach/mxc_ehci.h> 45#include <mach/mxc_ehci.h>
51#include <mach/ulpi.h> 46#include <mach/ulpi.h>
52 47
48#include "devices-imx31.h"
53#include "devices.h" 49#include "devices.h"
54 50
55/* 51/*
@@ -269,12 +265,12 @@ static int spi_internal_chipselect[] = {
269 MXC_SPI_CS(2), 265 MXC_SPI_CS(2),
270}; 266};
271 267
272static struct spi_imx_master spi0_pdata = { 268static const struct spi_imx_master spi0_pdata __initconst = {
273 .chipselect = spi_internal_chipselect, 269 .chipselect = spi_internal_chipselect,
274 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 270 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
275}; 271};
276 272
277static struct spi_imx_master spi1_pdata = { 273static const struct spi_imx_master spi1_pdata __initconst = {
278 .chipselect = spi_internal_chipselect, 274 .chipselect = spi_internal_chipselect,
279 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 275 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
280}; 276};
@@ -289,6 +285,7 @@ static struct spi_board_info mc13783_dev __initdata = {
289 .bus_num = 1, 285 .bus_num = 1,
290 .chip_select = 0, 286 .chip_select = 0,
291 .platform_data = &mc13783_pdata, 287 .platform_data = &mc13783_pdata,
288 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
292}; 289};
293 290
294static struct platform_device *devices[] __initdata = { 291static struct platform_device *devices[] __initdata = {
@@ -331,8 +328,8 @@ static void __init mx31lilly_board_init(void)
331 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); 328 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
332 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); 329 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
333 330
334 mxc_register_device(&mxc_spi_device0, &spi0_pdata); 331 imx31_add_spi_imx0(&spi0_pdata);
335 mxc_register_device(&mxc_spi_device1, &spi1_pdata); 332 imx31_add_spi_imx1(&spi1_pdata);
336 spi_register_board_info(&mc13783_dev, 1); 333 spi_register_board_info(&mc13783_dev, 1);
337 334
338 platform_add_devices(devices, ARRAY_SIZE(devices)); 335 platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 2b6d11400877..da236c497d2a 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 16 */
21 17
22#include <linux/types.h> 18#include <linux/types.h>
@@ -42,14 +38,12 @@
42#include <mach/hardware.h> 38#include <mach/hardware.h>
43#include <mach/common.h> 39#include <mach/common.h>
44#include <mach/board-mx31lite.h> 40#include <mach/board-mx31lite.h>
45#include <mach/imx-uart.h>
46#include <mach/iomux-mx3.h> 41#include <mach/iomux-mx3.h>
47#include <mach/irqs.h> 42#include <mach/irqs.h>
48#include <mach/mxc_nand.h>
49#include <mach/spi.h>
50#include <mach/mxc_ehci.h> 43#include <mach/mxc_ehci.h>
51#include <mach/ulpi.h> 44#include <mach/ulpi.h>
52 45
46#include "devices-imx31.h"
53#include "devices.h" 47#include "devices.h"
54 48
55/* 49/*
@@ -69,7 +63,8 @@ static unsigned int mx31lite_pins[] = {
69 MX31_PIN_CSPI2_SS2__SS2, 63 MX31_PIN_CSPI2_SS2__SS2,
70}; 64};
71 65
72static struct mxc_nand_platform_data mx31lite_nand_board_info = { 66static const struct mxc_nand_platform_data
67mx31lite_nand_board_info __initconst = {
73 .width = 1, 68 .width = 1,
74 .hw_ecc = 1, 69 .hw_ecc = 1,
75}; 70};
@@ -112,7 +107,7 @@ static int spi_internal_chipselect[] = {
112 MXC_SPI_CS(0), 107 MXC_SPI_CS(0),
113}; 108};
114 109
115static struct spi_imx_master spi1_pdata = { 110static const struct spi_imx_master spi1_pdata __initconst = {
116 .chipselect = spi_internal_chipselect, 111 .chipselect = spi_internal_chipselect,
117 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 112 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
118}; 113};
@@ -253,9 +248,9 @@ static void __init mxc_board_init(void)
253 248
254 /* NOR and NAND flash */ 249 /* NOR and NAND flash */
255 platform_device_register(&physmap_flash_device); 250 platform_device_register(&physmap_flash_device);
256 mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); 251 imx31_add_mxc_nand(&mx31lite_nand_board_info);
257 252
258 mxc_register_device(&mxc_spi_device1, &spi1_pdata); 253 imx31_add_spi_imx1(&spi1_pdata);
259 spi_register_board_info(&mc13783_spi_dev, 1); 254 spi_register_board_info(&mc13783_spi_dev, 1);
260 255
261#if defined(CONFIG_USB_ULPI) 256#if defined(CONFIG_USB_ULPI)
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 62b5e40165df..67776bc61c33 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/delay.h> 15#include <linux/delay.h>
@@ -42,16 +38,15 @@
42#include <mach/board-mx31moboard.h> 38#include <mach/board-mx31moboard.h>
43#include <mach/common.h> 39#include <mach/common.h>
44#include <mach/hardware.h> 40#include <mach/hardware.h>
45#include <mach/imx-uart.h>
46#include <mach/iomux-mx3.h> 41#include <mach/iomux-mx3.h>
47#include <mach/ipu.h> 42#include <mach/ipu.h>
48#include <mach/i2c.h>
49#include <mach/mmc.h> 43#include <mach/mmc.h>
50#include <mach/mxc_ehci.h> 44#include <mach/mxc_ehci.h>
51#include <mach/mx3_camera.h> 45#include <mach/mx3_camera.h>
52#include <mach/spi.h> 46#include <mach/spi.h>
53#include <mach/ulpi.h> 47#include <mach/ulpi.h>
54 48
49#include "devices-imx31.h"
55#include "devices.h" 50#include "devices.h"
56 51
57static unsigned int moboard_pins[] = { 52static unsigned int moboard_pins[] = {
@@ -130,24 +125,36 @@ static struct platform_device mx31moboard_flash = {
130 125
131static int moboard_uart0_init(struct platform_device *pdev) 126static int moboard_uart0_init(struct platform_device *pdev)
132{ 127{
133 gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); 128 int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
134 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); 129 if (ret)
135 return 0; 130 return ret;
131
132 ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
133 if (ret)
134 gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
135
136 return ret;
137}
138
139static void moboard_uart0_exit(struct platform_device *pdev)
140{
141 gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
136} 142}
137 143
138static struct imxuart_platform_data uart0_pdata = { 144static const struct imxuart_platform_data uart0_pdata __initconst = {
139 .init = moboard_uart0_init, 145 .init = moboard_uart0_init,
146 .exit = moboard_uart0_exit,
140}; 147};
141 148
142static struct imxuart_platform_data uart4_pdata = { 149static const struct imxuart_platform_data uart4_pdata __initconst = {
143 .flags = IMXUART_HAVE_RTSCTS, 150 .flags = IMXUART_HAVE_RTSCTS,
144}; 151};
145 152
146static struct imxi2c_platform_data moboard_i2c0_pdata = { 153static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
147 .bitrate = 400000, 154 .bitrate = 400000,
148}; 155};
149 156
150static struct imxi2c_platform_data moboard_i2c1_pdata = { 157static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
151 .bitrate = 100000, 158 .bitrate = 100000,
152}; 159};
153 160
@@ -156,7 +163,7 @@ static int moboard_spi1_cs[] = {
156 MXC_SPI_CS(2), 163 MXC_SPI_CS(2),
157}; 164};
158 165
159static struct spi_imx_master moboard_spi1_master = { 166static const struct spi_imx_master moboard_spi1_pdata __initconst = {
160 .chipselect = moboard_spi1_cs, 167 .chipselect = moboard_spi1_cs,
161 .num_chipselect = ARRAY_SIZE(moboard_spi1_cs), 168 .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
162}; 169};
@@ -286,7 +293,7 @@ static int moboard_spi2_cs[] = {
286 MXC_SPI_CS(1), 293 MXC_SPI_CS(1),
287}; 294};
288 295
289static struct spi_imx_master moboard_spi2_master = { 296static const struct spi_imx_master moboard_spi2_pdata __initconst = {
290 .chipselect = moboard_spi2_cs, 297 .chipselect = moboard_spi2_cs,
291 .num_chipselect = ARRAY_SIZE(moboard_spi2_cs), 298 .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
292}; 299};
@@ -499,15 +506,14 @@ static void __init mxc_board_init(void)
499 506
500 platform_add_devices(devices, ARRAY_SIZE(devices)); 507 platform_add_devices(devices, ARRAY_SIZE(devices));
501 508
502 mxc_register_device(&mxc_uart_device0, &uart0_pdata); 509 imx31_add_imx_uart0(&uart0_pdata);
503 510 imx31_add_imx_uart4(&uart4_pdata);
504 mxc_register_device(&mxc_uart_device4, &uart4_pdata);
505 511
506 mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); 512 imx31_add_imx_i2c0(&moboard_i2c0_data);
507 mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); 513 imx31_add_imx_i2c1(&moboard_i2c1_data);
508 514
509 mxc_register_device(&mxc_spi_device1, &moboard_spi1_master); 515 imx31_add_spi_imx1(&moboard_spi1_pdata);
510 mxc_register_device(&mxc_spi_device2, &moboard_spi2_master); 516 imx31_add_spi_imx2(&moboard_spi2_pdata);
511 517
512 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); 518 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
513 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); 519 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index bcac84d4dca4..1c30d7212f17 100644
--- a/arch/arm/mach-mx3/mach-mx35pdk.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -12,10 +12,12 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 */
16 * You should have received a copy of the GNU General Public License 16
17 * along with this program; if not, write to the Free Software 17/*
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * This machine is known as:
19 * - i.MX35 3-Stack Development System
20 * - i.MX35 Platform Development Kit (i.MX35 PDK)
19 */ 21 */
20 22
21#include <linux/types.h> 23#include <linux/types.h>
@@ -32,12 +34,12 @@
32 34
33#include <mach/hardware.h> 35#include <mach/hardware.h>
34#include <mach/common.h> 36#include <mach/common.h>
35#include <mach/imx-uart.h>
36#include <mach/iomux-mx35.h> 37#include <mach/iomux-mx35.h>
37 38
39#include "devices-imx35.h"
38#include "devices.h" 40#include "devices.h"
39 41
40static struct imxuart_platform_data uart_pdata = { 42static const struct imxuart_platform_data uart_pdata __initconst = {
41 .flags = IMXUART_HAVE_RTSCTS, 43 .flags = IMXUART_HAVE_RTSCTS,
42}; 44};
43 45
@@ -90,7 +92,7 @@ static void __init mxc_board_init(void)
90 92
91 platform_add_devices(devices, ARRAY_SIZE(devices)); 93 platform_add_devices(devices, ARRAY_SIZE(devices));
92 94
93 mxc_register_device(&mxc_uart_device0, &uart_pdata); 95 imx35_add_imx_uart0(&uart_pdata);
94 96
95 mxc_register_device(&mxc_otg_udc_device, &usb_pdata); 97 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
96} 98}
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index cce410662383..8a292dd1a714 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/types.h> 15#include <linux/types.h>
@@ -43,20 +39,17 @@
43#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
44#include <asm/mach/time.h> 40#include <asm/mach/time.h>
45#include <asm/mach/map.h> 41#include <asm/mach/map.h>
46#include <mach/board-pcm037.h>
47#include <mach/common.h> 42#include <mach/common.h>
48#include <mach/hardware.h> 43#include <mach/hardware.h>
49#include <mach/i2c.h>
50#include <mach/imx-uart.h>
51#include <mach/iomux-mx3.h> 44#include <mach/iomux-mx3.h>
52#include <mach/ipu.h> 45#include <mach/ipu.h>
53#include <mach/mmc.h> 46#include <mach/mmc.h>
54#include <mach/mx3_camera.h> 47#include <mach/mx3_camera.h>
55#include <mach/mx3fb.h> 48#include <mach/mx3fb.h>
56#include <mach/mxc_nand.h>
57#include <mach/mxc_ehci.h> 49#include <mach/mxc_ehci.h>
58#include <mach/ulpi.h> 50#include <mach/ulpi.h>
59 51
52#include "devices-imx31.h"
60#include "devices.h" 53#include "devices.h"
61#include "pcm037.h" 54#include "pcm037.h"
62 55
@@ -225,7 +218,7 @@ static struct platform_device pcm037_flash = {
225 .num_resources = 1, 218 .num_resources = 1,
226}; 219};
227 220
228static struct imxuart_platform_data uart_pdata = { 221static const struct imxuart_platform_data uart_pdata __initconst = {
229 .flags = IMXUART_HAVE_RTSCTS, 222 .flags = IMXUART_HAVE_RTSCTS,
230}; 223};
231 224
@@ -279,16 +272,17 @@ static struct platform_device pcm037_sram_device = {
279 .resource = &pcm038_sram_resource, 272 .resource = &pcm038_sram_resource,
280}; 273};
281 274
282static struct mxc_nand_platform_data pcm037_nand_board_info = { 275static const struct mxc_nand_platform_data
276pcm037_nand_board_info __initconst = {
283 .width = 1, 277 .width = 1,
284 .hw_ecc = 1, 278 .hw_ecc = 1,
285}; 279};
286 280
287static struct imxi2c_platform_data pcm037_i2c_1_data = { 281static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
288 .bitrate = 100000, 282 .bitrate = 100000,
289}; 283};
290 284
291static struct imxi2c_platform_data pcm037_i2c_2_data = { 285static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
292 .bitrate = 20000, 286 .bitrate = 20000,
293}; 287};
294 288
@@ -545,6 +539,7 @@ static struct platform_device pcm970_sja1000 = {
545 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), 539 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
546}; 540};
547 541
542#if defined(CONFIG_USB_ULPI)
548static struct mxc_usbh_platform_data otg_pdata = { 543static struct mxc_usbh_platform_data otg_pdata = {
549 .portsc = MXC_EHCI_MODE_ULPI, 544 .portsc = MXC_EHCI_MODE_ULPI,
550 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 545 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -554,6 +549,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
554 .portsc = MXC_EHCI_MODE_ULPI, 549 .portsc = MXC_EHCI_MODE_ULPI,
555 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 550 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
556}; 551};
552#endif
557 553
558static struct fsl_usb2_platform_data otg_device_pdata = { 554static struct fsl_usb2_platform_data otg_device_pdata = {
559 .operating_mode = FSL_USB2_DR_DEVICE, 555 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -581,7 +577,6 @@ __setup("otg_mode=", pcm037_otg_mode);
581static void __init mxc_board_init(void) 577static void __init mxc_board_init(void)
582{ 578{
583 int ret; 579 int ret;
584 u32 tmp;
585 580
586 mxc_iomux_set_gpr(MUX_PGP_UH2, 1); 581 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
587 582
@@ -614,9 +609,10 @@ static void __init mxc_board_init(void)
614 609
615 platform_add_devices(devices, ARRAY_SIZE(devices)); 610 platform_add_devices(devices, ARRAY_SIZE(devices));
616 611
617 mxc_register_device(&mxc_uart_device0, &uart_pdata); 612 imx31_add_imx_uart0(&uart_pdata);
618 mxc_register_device(&mxc_uart_device1, &uart_pdata); 613 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
619 mxc_register_device(&mxc_uart_device2, &uart_pdata); 614 imx31_add_imx_uart1(&uart_pdata);
615 imx31_add_imx_uart2(&uart_pdata);
620 616
621 mxc_register_device(&mxc_w1_master_device, NULL); 617 mxc_register_device(&mxc_w1_master_device, NULL);
622 618
@@ -634,10 +630,10 @@ static void __init mxc_board_init(void)
634 i2c_register_board_info(1, pcm037_i2c_devices, 630 i2c_register_board_info(1, pcm037_i2c_devices,
635 ARRAY_SIZE(pcm037_i2c_devices)); 631 ARRAY_SIZE(pcm037_i2c_devices));
636 632
637 mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data); 633 imx31_add_imx_i2c1(&pcm037_i2c1_data);
638 mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data); 634 imx31_add_imx_i2c2(&pcm037_i2c2_data);
639 635
640 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); 636 imx31_add_mxc_nand(&pcm037_nand_board_info);
641 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); 637 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
642 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 638 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
643 mxc_register_device(&mx3_fb, &mx3fb_pdata); 639 mxc_register_device(&mx3_fb, &mx3fb_pdata);
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index 8d386000fc40..c8b98218efee 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -13,9 +13,6 @@
13#include <linux/spi/spi.h> 13#include <linux/spi/spi.h>
14 14
15#include <mach/common.h> 15#include <mach/common.h>
16#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
17#include <mach/spi.h>
18#endif
19#include <mach/iomux-mx3.h> 16#include <mach/iomux-mx3.h>
20 17
21#include <asm/mach-types.h> 18#include <asm/mach-types.h>
@@ -64,7 +61,7 @@ static struct spi_board_info pcm037_spi_dev[] = {
64#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 61#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
65static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)}; 62static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
66 63
67struct spi_imx_master pcm037_spi1_master = { 64static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
68 .chipselect = pcm037_spi1_cs, 65 .chipselect = pcm037_spi1_cs,
69 .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs), 66 .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
70}; 67};
@@ -184,7 +181,7 @@ static int eet_init_devices(void)
184 /* SPI */ 181 /* SPI */
185 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); 182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
186#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 183#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
187 mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master); 184 imx35_add_spi_imx0(&pcm037_spi1_pdata);
188#endif 185#endif
189 186
190 platform_device_register(&pcm037_gpio_keys_device); 187 platform_device_register(&pcm037_gpio_keys_device);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 78d9185a9d4b..47f5311b301a 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/types.h> 15#include <linux/types.h>
@@ -40,19 +36,15 @@
40 36
41#include <mach/hardware.h> 37#include <mach/hardware.h>
42#include <mach/common.h> 38#include <mach/common.h>
43#include <mach/imx-uart.h>
44#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
45#include <mach/i2c.h>
46#endif
47#include <mach/iomux-mx35.h> 39#include <mach/iomux-mx35.h>
48#include <mach/ipu.h> 40#include <mach/ipu.h>
49#include <mach/mx3fb.h> 41#include <mach/mx3fb.h>
50#include <mach/mxc_nand.h>
51#include <mach/mxc_ehci.h> 42#include <mach/mxc_ehci.h>
52#include <mach/ulpi.h> 43#include <mach/ulpi.h>
53#include <mach/audmux.h> 44#include <mach/audmux.h>
54#include <mach/ssi.h> 45#include <mach/ssi.h>
55 46
47#include "devices-imx35.h"
56#include "devices.h" 48#include "devices.h"
57 49
58static const struct fb_videomode fb_modedb[] = { 50static const struct fb_videomode fb_modedb[] = {
@@ -122,12 +114,12 @@ static struct platform_device pcm043_flash = {
122 .num_resources = 1, 114 .num_resources = 1,
123}; 115};
124 116
125static struct imxuart_platform_data uart_pdata = { 117static const struct imxuart_platform_data uart_pdata __initconst = {
126 .flags = IMXUART_HAVE_RTSCTS, 118 .flags = IMXUART_HAVE_RTSCTS,
127}; 119};
128 120
129#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE 121#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
130static struct imxi2c_platform_data pcm043_i2c_1_data = { 122static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
131 .bitrate = 50000, 123 .bitrate = 50000,
132}; 124};
133 125
@@ -222,6 +214,9 @@ static struct pad_desc pcm043_pads[] = {
222 MX35_PAD_STXD4__AUDMUX_AUD4_TXD, 214 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
223 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, 215 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
224 MX35_PAD_SCK4__AUDMUX_AUD4_TXC, 216 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
217 /* CAN2 */
218 MX35_PAD_TX5_RX0__CAN2_TXCAN,
219 MX35_PAD_TX4_RX1__CAN2_RXCAN,
225}; 220};
226 221
227#define AC97_GPIO_TXFS (1 * 32 + 31) 222#define AC97_GPIO_TXFS (1 * 32 + 31)
@@ -304,11 +299,13 @@ static struct imx_ssi_platform_data pcm043_ssi_pdata = {
304 .flags = IMX_SSI_USE_AC97, 299 .flags = IMX_SSI_USE_AC97,
305}; 300};
306 301
307static struct mxc_nand_platform_data pcm037_nand_board_info = { 302static const struct mxc_nand_platform_data
303pcm037_nand_board_info __initconst = {
308 .width = 1, 304 .width = 1,
309 .hw_ecc = 1, 305 .hw_ecc = 1,
310}; 306};
311 307
308#if defined(CONFIG_USB_ULPI)
312static struct mxc_usbh_platform_data otg_pdata = { 309static struct mxc_usbh_platform_data otg_pdata = {
313 .portsc = MXC_EHCI_MODE_UTMI, 310 .portsc = MXC_EHCI_MODE_UTMI,
314 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 311 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -319,6 +316,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
319 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | 316 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
320 MXC_EHCI_IPPUE_DOWN, 317 MXC_EHCI_IPPUE_DOWN,
321}; 318};
319#endif
322 320
323static struct fsl_usb2_platform_data otg_device_pdata = { 321static struct fsl_usb2_platform_data otg_device_pdata = {
324 .operating_mode = FSL_USB2_DR_DEVICE, 322 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -361,17 +359,17 @@ static void __init mxc_board_init(void)
361 359
362 platform_add_devices(devices, ARRAY_SIZE(devices)); 360 platform_add_devices(devices, ARRAY_SIZE(devices));
363 361
364 mxc_register_device(&mxc_uart_device0, &uart_pdata); 362 imx35_add_imx_uart0(&uart_pdata);
365 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); 363 imx35_add_mxc_nand(&pcm037_nand_board_info);
366 mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); 364 mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
367 365
368 mxc_register_device(&mxc_uart_device1, &uart_pdata); 366 imx35_add_imx_uart1(&uart_pdata);
369 367
370#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE 368#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
371 i2c_register_board_info(0, pcm043_i2c_devices, 369 i2c_register_board_info(0, pcm043_i2c_devices,
372 ARRAY_SIZE(pcm043_i2c_devices)); 370 ARRAY_SIZE(pcm043_i2c_devices));
373 371
374 mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data); 372 imx35_add_imx_i2c0(&pcm043_i2c0_data);
375#endif 373#endif
376 374
377 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 375 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
@@ -390,6 +388,7 @@ static void __init mxc_board_init(void)
390 if (!otg_mode_host) 388 if (!otg_mode_host)
391 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 389 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
392 390
391 imx35_add_flexcan1(NULL);
393} 392}
394 393
395static void __init pcm043_timer_init(void) 394static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index e5b5b8323a17..d44ac70222a5 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/types.h> 15#include <linux/types.h>
@@ -34,9 +30,9 @@
34#include <mach/common.h> 30#include <mach/common.h>
35#include <asm/page.h> 31#include <asm/page.h>
36#include <asm/setup.h> 32#include <asm/setup.h>
37#include <mach/board-qong.h>
38#include <mach/imx-uart.h>
39#include <mach/iomux-mx3.h> 33#include <mach/iomux-mx3.h>
34
35#include "devices-imx31.h"
40#include "devices.h" 36#include "devices.h"
41 37
42/* FPGA defines */ 38/* FPGA defines */
@@ -62,7 +58,7 @@
62 * This file contains the board-specific initialization routines. 58 * This file contains the board-specific initialization routines.
63 */ 59 */
64 60
65static struct imxuart_platform_data uart_pdata = { 61static const struct imxuart_platform_data uart_pdata __initconst = {
66 .flags = IMXUART_HAVE_RTSCTS, 62 .flags = IMXUART_HAVE_RTSCTS,
67}; 63};
68 64
@@ -73,11 +69,11 @@ static int uart_pins[] = {
73 MX31_PIN_RXD1__RXD1 69 MX31_PIN_RXD1__RXD1
74}; 70};
75 71
76static inline void mxc_init_imx_uart(void) 72static inline void __init mxc_init_imx_uart(void)
77{ 73{
78 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), 74 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
79 "uart-0"); 75 "uart-0");
80 mxc_register_device(&mxc_uart_device0, &uart_pdata); 76 imx31_add_imx_uart0(&uart_pdata);
81} 77}
82 78
83static struct resource dnet_resources[] = { 79static struct resource dnet_resources[] = {
@@ -116,7 +112,7 @@ static struct physmap_flash_data qong_flash_data = {
116 112
117static struct resource qong_flash_resource = { 113static struct resource qong_flash_resource = {
118 .start = MX31_CS0_BASE_ADDR, 114 .start = MX31_CS0_BASE_ADDR,
119 .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1, 115 .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
120 .flags = IORESOURCE_MEM, 116 .flags = IORESOURCE_MEM,
121}; 117};
122 118
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 6858a4f9806c..20e48c0195c4 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -14,10 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */ 17 */
22 18
23#include <linux/mm.h> 19#include <linux/mm.h>
@@ -97,9 +93,12 @@ void __init mx35_map_io(void)
97} 93}
98#endif 94#endif
99 95
96int imx3x_register_gpios(void);
97
100void __init mx31_init_irq(void) 98void __init mx31_init_irq(void)
101{ 99{
102 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); 100 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
101 imx3x_register_gpios();
103} 102}
104 103
105void __init mx35_init_irq(void) 104void __init mx35_init_irq(void)
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 7aebd74a12e8..827fd3c80201 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -18,10 +18,6 @@
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details. 20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */ 21 */
26 22
27#include <linux/kernel.h> 23#include <linux/kernel.h>
@@ -36,13 +32,13 @@
36 32
37#include <mach/hardware.h> 33#include <mach/hardware.h>
38#include <mach/common.h> 34#include <mach/common.h>
39#include <mach/imx-uart.h>
40#include <mach/iomux-mx3.h> 35#include <mach/iomux-mx3.h>
41#include <mach/board-mx31lilly.h> 36#include <mach/board-mx31lilly.h>
42#include <mach/mmc.h> 37#include <mach/mmc.h>
43#include <mach/mx3fb.h> 38#include <mach/mx3fb.h>
44#include <mach/ipu.h> 39#include <mach/ipu.h>
45 40
41#include "devices-imx31.h"
46#include "devices.h" 42#include "devices.h"
47 43
48/* 44/*
@@ -96,7 +92,7 @@ static unsigned int lilly_db_board_pins[] __initdata = {
96}; 92};
97 93
98/* UART */ 94/* UART */
99static struct imxuart_platform_data uart_pdata __initdata = { 95static const struct imxuart_platform_data uart_pdata __initconst = {
100 .flags = IMXUART_HAVE_RTSCTS, 96 .flags = IMXUART_HAVE_RTSCTS,
101}; 97};
102 98
@@ -217,9 +213,9 @@ void __init mx31lilly_db_init(void)
217 mxc_iomux_setup_multiple_pins(lilly_db_board_pins, 213 mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
218 ARRAY_SIZE(lilly_db_board_pins), 214 ARRAY_SIZE(lilly_db_board_pins),
219 "development board pins"); 215 "development board pins");
220 mxc_register_device(&mxc_uart_device0, &uart_pdata); 216 imx31_add_imx_uart0(&uart_pdata);
221 mxc_register_device(&mxc_uart_device1, &uart_pdata); 217 imx31_add_imx_uart1(&uart_pdata);
222 mxc_register_device(&mxc_uart_device2, &uart_pdata); 218 imx31_add_imx_uart2(&uart_pdata);
223 mxc_register_device(&mxcsdhc_device0, &mmc_pdata); 219 mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
224 mx31lilly_init_fb(); 220 mx31lilly_init_fb();
225} 221}
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 5f05bfbec380..7b0e74e275ba 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -18,10 +18,6 @@
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details. 20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */ 21 */
26 22
27#include <linux/kernel.h> 23#include <linux/kernel.h>
@@ -37,12 +33,11 @@
37 33
38#include <mach/hardware.h> 34#include <mach/hardware.h>
39#include <mach/common.h> 35#include <mach/common.h>
40#include <mach/imx-uart.h>
41#include <mach/iomux-mx3.h> 36#include <mach/iomux-mx3.h>
42#include <mach/board-mx31lite.h> 37#include <mach/board-mx31lite.h>
43#include <mach/mmc.h> 38#include <mach/mmc.h>
44#include <mach/spi.h>
45 39
40#include "devices-imx31.h"
46#include "devices.h" 41#include "devices.h"
47 42
48/* 43/*
@@ -76,7 +71,7 @@ static unsigned int litekit_db_board_pins[] __initdata = {
76}; 71};
77 72
78/* UART */ 73/* UART */
79static struct imxuart_platform_data uart_pdata __initdata = { 74static const struct imxuart_platform_data uart_pdata __initconst = {
80 .flags = IMXUART_HAVE_RTSCTS, 75 .flags = IMXUART_HAVE_RTSCTS,
81}; 76};
82 77
@@ -161,7 +156,7 @@ static int spi_internal_chipselect[] = {
161 MXC_SPI_CS(2), 156 MXC_SPI_CS(2),
162}; 157};
163 158
164static struct spi_imx_master spi0_pdata = { 159static const struct spi_imx_master spi0_pdata __initconst = {
165 .chipselect = spi_internal_chipselect, 160 .chipselect = spi_internal_chipselect,
166 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 161 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
167}; 162};
@@ -201,9 +196,9 @@ void __init mx31lite_db_init(void)
201 mxc_iomux_setup_multiple_pins(litekit_db_board_pins, 196 mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
202 ARRAY_SIZE(litekit_db_board_pins), 197 ARRAY_SIZE(litekit_db_board_pins),
203 "development board pins"); 198 "development board pins");
204 mxc_register_device(&mxc_uart_device0, &uart_pdata); 199 imx31_add_imx_uart0(&uart_pdata);
205 mxc_register_device(&mxcsdhc_device0, &mmc_pdata); 200 mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
206 mxc_register_device(&mxc_spi_device0, &spi0_pdata); 201 imx31_add_spi_imx0(&spi0_pdata);
207 platform_device_register(&litekit_led_device); 202 platform_device_register(&litekit_led_device);
208 mxc_register_device(&imx_wdt_device0, NULL); 203 mxc_register_device(&imx_wdt_device0, NULL);
209 mxc_register_device(&imx_rtc_device0, NULL); 204 mxc_register_device(&imx_rtc_device0, NULL);
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 582299cb2c08..fc395a7a8599 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/gpio.h> 15#include <linux/gpio.h>
@@ -27,13 +23,13 @@
27#include <linux/usb/otg.h> 23#include <linux/usb/otg.h>
28 24
29#include <mach/common.h> 25#include <mach/common.h>
30#include <mach/imx-uart.h>
31#include <mach/iomux-mx3.h> 26#include <mach/iomux-mx3.h>
32#include <mach/hardware.h> 27#include <mach/hardware.h>
33#include <mach/mmc.h> 28#include <mach/mmc.h>
34#include <mach/mxc_ehci.h> 29#include <mach/mxc_ehci.h>
35#include <mach/ulpi.h> 30#include <mach/ulpi.h>
36 31
32#include "devices-imx31.h"
37#include "devices.h" 33#include "devices.h"
38 34
39static unsigned int devboard_pins[] = { 35static unsigned int devboard_pins[] = {
@@ -56,7 +52,7 @@ static unsigned int devboard_pins[] = {
56 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, 52 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
57}; 53};
58 54
59static struct imxuart_platform_data uart_pdata = { 55static const struct imxuart_platform_data uart_pdata __initconst = {
60 .flags = IMXUART_HAVE_RTSCTS, 56 .flags = IMXUART_HAVE_RTSCTS,
61}; 57};
62 58
@@ -230,7 +226,7 @@ void __init mx31moboard_devboard_init(void)
230 mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), 226 mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
231 "devboard"); 227 "devboard");
232 228
233 mxc_register_device(&mxc_uart_device1, &uart_pdata); 229 imx31_add_imx_uart1(&uart_pdata);
234 230
235 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); 231 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
236 232
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 4930f8c27e66..0551eb39d97e 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/delay.h> 15#include <linux/delay.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 293eea6d9d97..40c3e7564cb6 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 13 */
18 14
19#include <linux/delay.h> 15#include <linux/delay.h>
@@ -30,7 +26,6 @@
30 26
31#include <mach/common.h> 27#include <mach/common.h>
32#include <mach/hardware.h> 28#include <mach/hardware.h>
33#include <mach/imx-uart.h>
34#include <mach/iomux-mx3.h> 29#include <mach/iomux-mx3.h>
35#include <mach/board-mx31moboard.h> 30#include <mach/board-mx31moboard.h>
36#include <mach/mxc_ehci.h> 31#include <mach/mxc_ehci.h>
@@ -38,6 +33,7 @@
38 33
39#include <media/soc_camera.h> 34#include <media/soc_camera.h>
40 35
36#include "devices-imx31.h"
41#include "devices.h" 37#include "devices.h"
42 38
43static unsigned int smartbot_pins[] = { 39static unsigned int smartbot_pins[] = {
@@ -59,7 +55,7 @@ static unsigned int smartbot_pins[] = {
59 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, 55 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
60}; 56};
61 57
62static struct imxuart_platform_data uart_pdata = { 58static const struct imxuart_platform_data uart_pdata __initconst = {
63 .flags = IMXUART_HAVE_RTSCTS, 59 .flags = IMXUART_HAVE_RTSCTS,
64}; 60};
65 61
@@ -183,8 +179,7 @@ void __init mx31moboard_smartbot_init(int board)
183 mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), 179 mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
184 "smartbot"); 180 "smartbot");
185 181
186 mxc_register_device(&mxc_uart_device1, &uart_pdata); 182 imx31_add_imx_uart1(&uart_pdata);
187
188 183
189 switch (board) { 184 switch (board) {
190 case MX31SMARTBOT: 185 case MX31SMARTBOT:
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51e676c..0848db5dd364 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,31 @@ config MACH_MX51_BABBAGE
15 u-boot. This includes specific configurations for the board and its 15 u-boot. This includes specific configurations for the board and its
16 peripherals. 16 peripherals.
17 17
18config MACH_MX51_3DS
19 bool "Support MX51PDK (3DS)"
20 select MXC_DEBUG_BOARD
21 help
22 Include support for MX51PDK (3DS) platform. This includes specific
23 configurations for the board and its peripherals.
24
25config MACH_EUKREA_CPUIMX51
26 bool "Support Eukrea CPUIMX51 module"
27 help
28 Include support for Eukrea CPUIMX51 platform. This includes
29 specific configurations for the module and its peripherals.
30
31choice
32 prompt "Baseboard"
33 depends on MACH_EUKREA_CPUIMX51
34 default MACH_EUKREA_MBIMX51_BASEBOARD
35
36config MACH_EUKREA_MBIMX51_BASEBOARD
37 prompt "Eukrea MBIMX51 development board"
38 bool
39 help
40 This adds board specific devices that can be found on Eukrea's
41 MBIMX51 evaluation board.
42
43endchoice
44
18endif 45endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f869ef51..86c66e7f52f3 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,6 @@
6obj-y := cpu.o mm.o clock-mx51.o devices.o 6obj-y := cpu.o mm.o clock-mx51.o devices.o
7 7
8obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o 8obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
9 9obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
10obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
11obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
new file mode 100644
index 000000000000..623607a20f57
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -0,0 +1,293 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/serial_8250.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/fsl_devices.h>
27
28#include <mach/eukrea-baseboards.h>
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/imx-uart.h>
32#include <mach/iomux-mx51.h>
33#include <mach/i2c.h>
34#include <mach/mxc_ehci.h>
35
36#include <asm/irq.h>
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41
42#include "devices.h"
43
44#define CPUIMX51_USBH1_STP (0*32 + 27)
45#define CPUIMX51_QUARTA_GPIO (2*32 + 28)
46#define CPUIMX51_QUARTB_GPIO (2*32 + 25)
47#define CPUIMX51_QUARTC_GPIO (2*32 + 26)
48#define CPUIMX51_QUARTD_GPIO (2*32 + 27)
49#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
50#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
51#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
52#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
53#define CPUIMX51_QUART_XTAL 14745600
54#define CPUIMX51_QUART_REGSHIFT 17
55
56/* USB_CTRL_1 */
57#define MX51_USB_CTRL_1_OFFSET 0x10
58#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
59
60#define MX51_USB_PLLDIV_12_MHZ 0x00
61#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
62#define MX51_USB_PLL_DIV_24_MHZ 0x02
63
64#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
65static struct plat_serial8250_port serial_platform_data[] = {
66 {
67 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
68 .irq = CPUIMX51_QUARTA_IRQ,
69 .irqflags = IRQF_TRIGGER_HIGH,
70 .uartclk = CPUIMX51_QUART_XTAL,
71 .regshift = CPUIMX51_QUART_REGSHIFT,
72 .iotype = UPIO_MEM,
73 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
74 }, {
75 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
76 .irq = CPUIMX51_QUARTB_IRQ,
77 .irqflags = IRQF_TRIGGER_HIGH,
78 .uartclk = CPUIMX51_QUART_XTAL,
79 .regshift = CPUIMX51_QUART_REGSHIFT,
80 .iotype = UPIO_MEM,
81 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
82 }, {
83 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
84 .irq = CPUIMX51_QUARTC_IRQ,
85 .irqflags = IRQF_TRIGGER_HIGH,
86 .uartclk = CPUIMX51_QUART_XTAL,
87 .regshift = CPUIMX51_QUART_REGSHIFT,
88 .iotype = UPIO_MEM,
89 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
90 }, {
91 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
92 .irq = CPUIMX51_QUARTD_IRQ,
93 .irqflags = IRQF_TRIGGER_HIGH,
94 .uartclk = CPUIMX51_QUART_XTAL,
95 .regshift = CPUIMX51_QUART_REGSHIFT,
96 .iotype = UPIO_MEM,
97 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
98 }, {
99 }
100};
101
102static struct platform_device serial_device = {
103 .name = "serial8250",
104 .id = 0,
105 .dev = {
106 .platform_data = serial_platform_data,
107 },
108};
109#endif
110
111static struct platform_device *devices[] __initdata = {
112 &mxc_fec_device,
113#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
114 &serial_device,
115#endif
116};
117
118static struct pad_desc eukrea_cpuimx51_pads[] = {
119 /* UART1 */
120 MX51_PAD_UART1_RXD__UART1_RXD,
121 MX51_PAD_UART1_TXD__UART1_TXD,
122 MX51_PAD_UART1_RTS__UART1_RTS,
123 MX51_PAD_UART1_CTS__UART1_CTS,
124
125 /* I2C2 */
126 MX51_PAD_GPIO_1_2__I2C2_SCL,
127 MX51_PAD_GPIO_1_3__I2C2_SDA,
128 MX51_PAD_NANDF_D10__GPIO_3_30,
129
130 /* QUART IRQ */
131 MX51_PAD_NANDF_D15__GPIO_3_25,
132 MX51_PAD_NANDF_D14__GPIO_3_26,
133 MX51_PAD_NANDF_D13__GPIO_3_27,
134 MX51_PAD_NANDF_D12__GPIO_3_28,
135
136 /* USB HOST1 */
137 MX51_PAD_USBH1_CLK__USBH1_CLK,
138 MX51_PAD_USBH1_DIR__USBH1_DIR,
139 MX51_PAD_USBH1_NXT__USBH1_NXT,
140 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
141 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
142 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
143 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
144 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
145 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
146 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
147 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
148 MX51_PAD_USBH1_STP__USBH1_STP,
149};
150
151static struct imxuart_platform_data uart_pdata = {
152 .flags = IMXUART_HAVE_RTSCTS,
153};
154
155static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
156 .bitrate = 100000,
157};
158
159static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
160 {
161 I2C_BOARD_INFO("pcf8563", 0x51),
162 },
163};
164
165/* This function is board specific as the bit mask for the plldiv will also
166be different for other Freescale SoCs, thus a common bitmask is not
167possible and cannot get place in /plat-mxc/ehci.c.*/
168static int initialize_otg_port(struct platform_device *pdev)
169{
170 u32 v;
171 void __iomem *usb_base;
172 void __iomem *usbother_base;
173
174 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
175 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
176
177 /* Set the PHY clock to 19.2MHz */
178 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
179 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
180 v |= MX51_USB_PLL_DIV_19_2_MHZ;
181 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
182 iounmap(usb_base);
183 return 0;
184}
185
186static int initialize_usbh1_port(struct platform_device *pdev)
187{
188 u32 v;
189 void __iomem *usb_base;
190 void __iomem *usbother_base;
191
192 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
193 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
194
195 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
196 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
197 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
198 iounmap(usb_base);
199 return 0;
200}
201
202static struct mxc_usbh_platform_data dr_utmi_config = {
203 .init = initialize_otg_port,
204 .portsc = MXC_EHCI_UTMI_16BIT,
205 .flags = MXC_EHCI_INTERNAL_PHY,
206};
207
208static struct fsl_usb2_platform_data usb_pdata = {
209 .operating_mode = FSL_USB2_DR_DEVICE,
210 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
211};
212
213static struct mxc_usbh_platform_data usbh1_config = {
214 .init = initialize_usbh1_port,
215 .portsc = MXC_EHCI_MODE_ULPI,
216 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
217};
218
219static int otg_mode_host;
220
221static int __init eukrea_cpuimx51_otg_mode(char *options)
222{
223 if (!strcmp(options, "host"))
224 otg_mode_host = 1;
225 else if (!strcmp(options, "device"))
226 otg_mode_host = 0;
227 else
228 pr_info("otg_mode neither \"host\" nor \"device\". "
229 "Defaulting to device\n");
230 return 0;
231}
232__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
233
234/*
235 * Board specific initialization.
236 */
237static void __init eukrea_cpuimx51_init(void)
238{
239 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
240 ARRAY_SIZE(eukrea_cpuimx51_pads));
241
242 mxc_register_device(&mxc_uart_device0, &uart_pdata);
243 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
244 gpio_direction_input(CPUIMX51_QUARTA_GPIO);
245 gpio_free(CPUIMX51_QUARTA_GPIO);
246 gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
247 gpio_direction_input(CPUIMX51_QUARTB_GPIO);
248 gpio_free(CPUIMX51_QUARTB_GPIO);
249 gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
250 gpio_direction_input(CPUIMX51_QUARTC_GPIO);
251 gpio_free(CPUIMX51_QUARTC_GPIO);
252 gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
253 gpio_direction_input(CPUIMX51_QUARTD_GPIO);
254 gpio_free(CPUIMX51_QUARTD_GPIO);
255
256 platform_add_devices(devices, ARRAY_SIZE(devices));
257
258 mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
259 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
260 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
261
262 if (otg_mode_host)
263 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
264 else {
265 initialize_otg_port(NULL);
266 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
267 }
268 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
269
270#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
271 eukrea_mbimx51_baseboard_init();
272#endif
273}
274
275static void __init eukrea_cpuimx51_timer_init(void)
276{
277 mx51_clocks_init(32768, 24000000, 22579200, 0);
278}
279
280static struct sys_timer mxc_timer = {
281 .init = eukrea_cpuimx51_timer_init,
282};
283
284MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
285 /* Maintainer: Eric Bénard <eric@eukrea.com> */
286 .phys_io = MX51_AIPS1_BASE_ADDR,
287 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
288 .boot_params = PHYS_OFFSET + 0x100,
289 .map_io = mx51_map_io,
290 .init_irq = mx51_init_irq,
291 .init_machine = eukrea_cpuimx51_init,
292 .timer = &mxc_timer,
293MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 000000000000..f95c2fd94667
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,164 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/irq.h>
14#include <linux/platform_device.h>
15#include <linux/input/matrix_keypad.h>
16
17#include <asm/mach-types.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/time.h>
20
21#include <mach/hardware.h>
22#include <mach/common.h>
23#include <mach/iomux-mx51.h>
24#include <mach/imx-uart.h>
25#include <mach/3ds_debugboard.h>
26
27#include "devices.h"
28
29#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
30
31static struct pad_desc mx51_3ds_pads[] = {
32 /* UART1 */
33 MX51_PAD_UART1_RXD__UART1_RXD,
34 MX51_PAD_UART1_TXD__UART1_TXD,
35 MX51_PAD_UART1_RTS__UART1_RTS,
36 MX51_PAD_UART1_CTS__UART1_CTS,
37
38 /* UART2 */
39 MX51_PAD_UART2_RXD__UART2_RXD,
40 MX51_PAD_UART2_TXD__UART2_TXD,
41 MX51_PAD_EIM_D25__UART2_CTS,
42 MX51_PAD_EIM_D26__UART2_RTS,
43
44 /* UART3 */
45 MX51_PAD_UART3_RXD__UART3_RXD,
46 MX51_PAD_UART3_TXD__UART3_TXD,
47 MX51_PAD_EIM_D24__UART3_CTS,
48 MX51_PAD_EIM_D27__UART3_RTS,
49
50 /* CPLD PARENT IRQ PIN */
51 MX51_PAD_GPIO_1_6__GPIO_1_6,
52
53 /* KPP */
54 MX51_PAD_KEY_ROW0__KEY_ROW0,
55 MX51_PAD_KEY_ROW1__KEY_ROW1,
56 MX51_PAD_KEY_ROW2__KEY_ROW2,
57 MX51_PAD_KEY_ROW3__KEY_ROW3,
58 MX51_PAD_KEY_COL0__KEY_COL0,
59 MX51_PAD_KEY_COL1__KEY_COL1,
60 MX51_PAD_KEY_COL2__KEY_COL2,
61 MX51_PAD_KEY_COL3__KEY_COL3,
62 MX51_PAD_KEY_COL4__KEY_COL4,
63 MX51_PAD_KEY_COL5__KEY_COL5,
64};
65
66/* Serial ports */
67#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
68static struct imxuart_platform_data uart_pdata = {
69 .flags = IMXUART_HAVE_RTSCTS,
70};
71
72static inline void mxc_init_imx_uart(void)
73{
74 mxc_register_device(&mxc_uart_device0, &uart_pdata);
75 mxc_register_device(&mxc_uart_device1, &uart_pdata);
76 mxc_register_device(&mxc_uart_device2, &uart_pdata);
77}
78#else /* !SERIAL_IMX */
79static inline void mxc_init_imx_uart(void)
80{
81}
82#endif /* SERIAL_IMX */
83
84#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
85static int mx51_3ds_board_keymap[] = {
86 KEY(0, 0, KEY_1),
87 KEY(0, 1, KEY_2),
88 KEY(0, 2, KEY_3),
89 KEY(0, 3, KEY_F1),
90 KEY(0, 4, KEY_UP),
91 KEY(0, 5, KEY_F2),
92
93 KEY(1, 0, KEY_4),
94 KEY(1, 1, KEY_5),
95 KEY(1, 2, KEY_6),
96 KEY(1, 3, KEY_LEFT),
97 KEY(1, 4, KEY_SELECT),
98 KEY(1, 5, KEY_RIGHT),
99
100 KEY(2, 0, KEY_7),
101 KEY(2, 1, KEY_8),
102 KEY(2, 2, KEY_9),
103 KEY(2, 3, KEY_F3),
104 KEY(2, 4, KEY_DOWN),
105 KEY(2, 5, KEY_F4),
106
107 KEY(3, 0, KEY_0),
108 KEY(3, 1, KEY_OK),
109 KEY(3, 2, KEY_ESC),
110 KEY(3, 3, KEY_ENTER),
111 KEY(3, 4, KEY_MENU),
112 KEY(3, 5, KEY_BACK)
113};
114
115static struct matrix_keymap_data mx51_3ds_map_data = {
116 .keymap = mx51_3ds_board_keymap,
117 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
118};
119
120static void mxc_init_keypad(void)
121{
122 mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
123}
124#else
125static inline void mxc_init_keypad(void)
126{
127}
128#endif
129
130/*
131 * Board specific initialization.
132 */
133static void __init mxc_board_init(void)
134{
135 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
136 ARRAY_SIZE(mx51_3ds_pads));
137 mxc_init_imx_uart();
138
139 if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
140 printk(KERN_WARNING "Init of the debugboard failed, all "
141 "devices on the board are unusable.\n");
142
143 mxc_init_keypad();
144}
145
146static void __init mx51_3ds_timer_init(void)
147{
148 mx51_clocks_init(32768, 24000000, 22579200, 0);
149}
150
151static struct sys_timer mxc_timer = {
152 .init = mx51_3ds_timer_init,
153};
154
155MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
156 /* Maintainer: Freescale Semiconductor, Inc. */
157 .phys_io = MX51_AIPS1_BASE_ADDR,
158 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
159 .boot_params = PHYS_OFFSET + 0x100,
160 .map_io = mx51_map_io,
161 .init_irq = mx51_init_irq,
162 .init_machine = mxc_board_init,
163 .timer = &mxc_timer,
164MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ed885f9d7b73..6e384d92e625 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/i2c.h>
15#include <linux/gpio.h> 16#include <linux/gpio.h>
16#include <linux/delay.h> 17#include <linux/delay.h>
17#include <linux/io.h> 18#include <linux/io.h>
@@ -21,6 +22,7 @@
21#include <mach/hardware.h> 22#include <mach/hardware.h>
22#include <mach/imx-uart.h> 23#include <mach/imx-uart.h>
23#include <mach/iomux-mx51.h> 24#include <mach/iomux-mx51.h>
25#include <mach/i2c.h>
24#include <mach/mxc_ehci.h> 26#include <mach/mxc_ehci.h>
25 27
26#include <asm/irq.h> 28#include <asm/irq.h>
@@ -64,6 +66,18 @@ static struct pad_desc mx51babbage_pads[] = {
64 MX51_PAD_EIM_D27__UART3_RTS, 66 MX51_PAD_EIM_D27__UART3_RTS,
65 MX51_PAD_EIM_D24__UART3_CTS, 67 MX51_PAD_EIM_D24__UART3_CTS,
66 68
69 /* I2C1 */
70 MX51_PAD_EIM_D16__I2C1_SDA,
71 MX51_PAD_EIM_D19__I2C1_SCL,
72
73 /* I2C2 */
74 MX51_PAD_KEY_COL4__I2C2_SCL,
75 MX51_PAD_KEY_COL5__I2C2_SDA,
76
77 /* HSI2C */
78 MX51_PAD_I2C1_CLK__HSI2C_CLK,
79 MX51_PAD_I2C1_DAT__HSI2C_DAT,
80
67 /* USB HOST1 */ 81 /* USB HOST1 */
68 MX51_PAD_USBH1_CLK__USBH1_CLK, 82 MX51_PAD_USBH1_CLK__USBH1_CLK,
69 MX51_PAD_USBH1_DIR__USBH1_DIR, 83 MX51_PAD_USBH1_DIR__USBH1_DIR,
@@ -78,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = {
78 MX51_PAD_USBH1_DATA7__USBH1_DATA7, 92 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
79 93
80 /* USB HUB reset line*/ 94 /* USB HUB reset line*/
81 MX51_PAD_GPIO_1_7__GPIO1_7, 95 MX51_PAD_GPIO_1_7__GPIO_1_7,
82}; 96};
83 97
84/* Serial ports */ 98/* Serial ports */
@@ -99,6 +113,14 @@ static inline void mxc_init_imx_uart(void)
99} 113}
100#endif /* SERIAL_IMX */ 114#endif /* SERIAL_IMX */
101 115
116static struct imxi2c_platform_data babbage_i2c_data = {
117 .bitrate = 100000,
118};
119
120static struct imxi2c_platform_data babbage_hsi2c_data = {
121 .bitrate = 400000,
122};
123
102static int gpio_usbh1_active(void) 124static int gpio_usbh1_active(void)
103{ 125{
104 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; 126 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
@@ -230,6 +252,10 @@ static void __init mxc_board_init(void)
230 mxc_init_imx_uart(); 252 mxc_init_imx_uart();
231 platform_add_devices(devices, ARRAY_SIZE(devices)); 253 platform_add_devices(devices, ARRAY_SIZE(devices));
232 254
255 mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
256 mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
257 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
258
233 if (otg_mode_host) 259 if (otg_mode_host)
234 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); 260 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
235 else { 261 else {
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d3370e..6af69def357f 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
758 .parent = &ckil_clk, 758 .parent = &ckil_clk,
759}; 759};
760 760
761static struct clk kpp_clk = {
762 .id = 0,
763};
764
761#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ 765#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
762 static struct clk name = { \ 766 static struct clk name = { \
763 .id = i, \ 767 .id = i, \
@@ -798,6 +802,14 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
798DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, 802DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
799 NULL, NULL, &ipg_clk, NULL); 803 NULL, NULL, &ipg_clk, NULL);
800 804
805/* I2C */
806DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
807 NULL, NULL, &ipg_clk, NULL);
808DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
809 NULL, NULL, &ipg_clk, NULL);
810DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
811 NULL, NULL, &ipg_clk, NULL);
812
801/* FEC */ 813/* FEC */
802DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, 814DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
803 NULL, NULL, &ipg_clk, NULL); 815 NULL, NULL, &ipg_clk, NULL);
@@ -815,12 +827,16 @@ static struct clk_lookup lookups[] = {
815 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 827 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
816 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 828 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
817 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 829 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
830 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
831 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
832 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
818 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) 833 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
819 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) 834 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
820 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) 835 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
821 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) 836 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
822 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) 837 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
823 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) 838 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
839 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
824}; 840};
825 841
826static void clk_tree_init(void) 842static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449aacdc..1920ff4963b2 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -93,6 +93,64 @@ struct platform_device mxc_fec_device = {
93 .resource = mxc_fec_resources, 93 .resource = mxc_fec_resources,
94}; 94};
95 95
96static struct resource mxc_i2c0_resources[] = {
97 {
98 .start = MX51_I2C1_BASE_ADDR,
99 .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = MX51_MXC_INT_I2C1,
103 .end = MX51_MXC_INT_I2C1,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108struct platform_device mxc_i2c_device0 = {
109 .name = "imx-i2c",
110 .id = 0,
111 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
112 .resource = mxc_i2c0_resources,
113};
114
115static struct resource mxc_i2c1_resources[] = {
116 {
117 .start = MX51_I2C2_BASE_ADDR,
118 .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = MX51_MXC_INT_I2C2,
122 .end = MX51_MXC_INT_I2C2,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127struct platform_device mxc_i2c_device1 = {
128 .name = "imx-i2c",
129 .id = 1,
130 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
131 .resource = mxc_i2c1_resources,
132};
133
134static struct resource mxc_hsi2c_resources[] = {
135 {
136 .start = MX51_HSI2C_DMA_BASE_ADDR,
137 .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
138 .flags = IORESOURCE_MEM,
139 },
140 {
141 .start = MX51_MXC_INT_HS_I2C,
142 .end = MX51_MXC_INT_HS_I2C,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147struct platform_device mxc_hsi2c_device = {
148 .name = "imx-i2c",
149 .id = 2,
150 .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
151 .resource = mxc_hsi2c_resources
152};
153
96static u64 usb_dma_mask = DMA_BIT_MASK(32); 154static u64 usb_dma_mask = DMA_BIT_MASK(32);
97 155
98static struct resource usbotg_resources[] = { 156static struct resource usbotg_resources[] = {
@@ -168,34 +226,57 @@ struct platform_device mxc_wdt = {
168 .resource = mxc_wdt_resources, 226 .resource = mxc_wdt_resources,
169}; 227};
170 228
229static struct resource mxc_kpp_resources[] = {
230 {
231 .start = MX51_MXC_INT_KPP,
232 .end = MX51_MXC_INT_KPP,
233 .flags = IORESOURCE_IRQ,
234 } , {
235 .start = MX51_KPP_BASE_ADDR,
236 .end = MX51_KPP_BASE_ADDR + 0x8 - 1,
237 .flags = IORESOURCE_MEM,
238 },
239};
240
241struct platform_device mxc_keypad_device = {
242 .name = "imx-keypad",
243 .id = 0,
244 .num_resources = ARRAY_SIZE(mxc_kpp_resources),
245 .resource = mxc_kpp_resources,
246};
247
171static struct mxc_gpio_port mxc_gpio_ports[] = { 248static struct mxc_gpio_port mxc_gpio_ports[] = {
172 { 249 {
173 .chip.label = "gpio-0", 250 .chip.label = "gpio-0",
174 .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR), 251 .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
175 .irq = MX51_MXC_INT_GPIO1_LOW, 252 .irq = MX51_MXC_INT_GPIO1_LOW,
253 .irq_high = MX51_MXC_INT_GPIO1_HIGH,
176 .virtual_irq_start = MXC_GPIO_IRQ_START 254 .virtual_irq_start = MXC_GPIO_IRQ_START
177 }, 255 },
178 { 256 {
179 .chip.label = "gpio-1", 257 .chip.label = "gpio-1",
180 .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR), 258 .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
181 .irq = MX51_MXC_INT_GPIO2_LOW, 259 .irq = MX51_MXC_INT_GPIO2_LOW,
260 .irq_high = MX51_MXC_INT_GPIO2_HIGH,
182 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 261 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
183 }, 262 },
184 { 263 {
185 .chip.label = "gpio-2", 264 .chip.label = "gpio-2",
186 .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR), 265 .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
187 .irq = MX51_MXC_INT_GPIO3_LOW, 266 .irq = MX51_MXC_INT_GPIO3_LOW,
267 .irq_high = MX51_MXC_INT_GPIO3_HIGH,
188 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 268 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
189 }, 269 },
190 { 270 {
191 .chip.label = "gpio-3", 271 .chip.label = "gpio-3",
192 .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR), 272 .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
193 .irq = MX51_MXC_INT_GPIO4_LOW, 273 .irq = MX51_MXC_INT_GPIO4_LOW,
274 .irq_high = MX51_MXC_INT_GPIO4_HIGH,
194 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 275 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
195 }, 276 },
196}; 277};
197 278
198int __init mxc_register_gpios(void) 279int __init imx51_register_gpios(void)
199{ 280{
200 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); 281 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
201} 282}
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae71cd5b..e509cfaad1d4 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,7 @@ extern struct platform_device mxc_usbdr_host_device;
6extern struct platform_device mxc_usbh1_device; 6extern struct platform_device mxc_usbh1_device;
7extern struct platform_device mxc_usbdr_udc_device; 7extern struct platform_device mxc_usbdr_udc_device;
8extern struct platform_device mxc_wdt; 8extern struct platform_device mxc_wdt;
9extern struct platform_device mxc_i2c_device0;
10extern struct platform_device mxc_i2c_device1;
11extern struct platform_device mxc_hsi2c_device;
12extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
new file mode 100644
index 000000000000..ffa93d1d6ef8
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -0,0 +1,200 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/serial_8250.h>
16#include <linux/i2c.h>
17#include <linux/gpio.h>
18#include <linux/io.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/fsl_devices.h>
22#include <linux/i2c/tsc2007.h>
23#include <linux/leds.h>
24#include <linux/input/matrix_keypad.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/imx-uart.h>
29#include <mach/iomux-mx51.h>
30
31#include <asm/mach/arch.h>
32
33#include "devices.h"
34
35#define MBIMX51_TSC2007_GPIO (2*32 + 30)
36#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
37#define MBIMX51_LED0 (2*32 + 5)
38#define MBIMX51_LED1 (2*32 + 6)
39#define MBIMX51_LED2 (2*32 + 7)
40#define MBIMX51_LED3 (2*32 + 8)
41
42static struct gpio_led mbimx51_leds[] = {
43 {
44 .name = "led0",
45 .default_trigger = "heartbeat",
46 .active_low = 1,
47 .gpio = MBIMX51_LED0,
48 },
49 {
50 .name = "led1",
51 .default_trigger = "nand-disk",
52 .active_low = 1,
53 .gpio = MBIMX51_LED1,
54 },
55 {
56 .name = "led2",
57 .default_trigger = "mmc0",
58 .active_low = 1,
59 .gpio = MBIMX51_LED2,
60 },
61 {
62 .name = "led3",
63 .default_trigger = "default-on",
64 .active_low = 1,
65 .gpio = MBIMX51_LED3,
66 },
67};
68
69static struct gpio_led_platform_data mbimx51_leds_info = {
70 .leds = mbimx51_leds,
71 .num_leds = ARRAY_SIZE(mbimx51_leds),
72};
73
74static struct platform_device mbimx51_leds_gpio = {
75 .name = "leds-gpio",
76 .id = -1,
77 .dev = {
78 .platform_data = &mbimx51_leds_info,
79 },
80};
81
82static struct platform_device *devices[] __initdata = {
83 &mbimx51_leds_gpio,
84};
85
86static struct pad_desc mbimx51_pads[] = {
87 /* UART2 */
88 MX51_PAD_UART2_RXD__UART2_RXD,
89 MX51_PAD_UART2_TXD__UART2_TXD,
90
91 /* UART3 */
92 MX51_PAD_UART3_RXD__UART3_RXD,
93 MX51_PAD_UART3_TXD__UART3_TXD,
94 MX51_PAD_KEY_COL4__UART3_RTS,
95 MX51_PAD_KEY_COL5__UART3_CTS,
96
97 /* TSC2007 IRQ */
98 MX51_PAD_NANDF_D10__GPIO_3_30,
99
100 /* LEDS */
101 MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
102 MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
103 MX51_PAD_DISPB2_SER_CLK__GPIO_3_7,
104 MX51_PAD_DISPB2_SER_RS__GPIO_3_8,
105
106 /* KPP */
107 MX51_PAD_KEY_ROW0__KEY_ROW0,
108 MX51_PAD_KEY_ROW1__KEY_ROW1,
109 MX51_PAD_KEY_ROW2__KEY_ROW2,
110 MX51_PAD_KEY_ROW3__KEY_ROW3,
111 MX51_PAD_KEY_COL0__KEY_COL0,
112 MX51_PAD_KEY_COL1__KEY_COL1,
113 MX51_PAD_KEY_COL2__KEY_COL2,
114 MX51_PAD_KEY_COL3__KEY_COL3,
115};
116
117static struct imxuart_platform_data uart_pdata = {
118 .flags = IMXUART_HAVE_RTSCTS,
119};
120
121static int mbimx51_keymap[] = {
122 KEY(0, 0, KEY_1),
123 KEY(0, 1, KEY_2),
124 KEY(0, 2, KEY_3),
125 KEY(0, 3, KEY_UP),
126
127 KEY(1, 0, KEY_4),
128 KEY(1, 1, KEY_5),
129 KEY(1, 2, KEY_6),
130 KEY(1, 3, KEY_LEFT),
131
132 KEY(2, 0, KEY_7),
133 KEY(2, 1, KEY_8),
134 KEY(2, 2, KEY_9),
135 KEY(2, 3, KEY_RIGHT),
136
137 KEY(3, 0, KEY_0),
138 KEY(3, 1, KEY_DOWN),
139 KEY(3, 2, KEY_ESC),
140 KEY(3, 3, KEY_ENTER),
141};
142
143static struct matrix_keymap_data mbimx51_map_data = {
144 .keymap = mbimx51_keymap,
145 .keymap_size = ARRAY_SIZE(mbimx51_keymap),
146};
147
148static int tsc2007_get_pendown_state(void)
149{
150 return !gpio_get_value(MBIMX51_TSC2007_GPIO);
151}
152
153struct tsc2007_platform_data tsc2007_data = {
154 .model = 2007,
155 .x_plate_ohms = 180,
156 .get_pendown_state = tsc2007_get_pendown_state,
157};
158
159static struct i2c_board_info mbimx51_i2c_devices[] = {
160 {
161 I2C_BOARD_INFO("tsc2007", 0x48),
162 .irq = MBIMX51_TSC2007_IRQ,
163 .platform_data = &tsc2007_data,
164 },
165};
166
167/*
168 * baseboard initialization.
169 */
170void __init eukrea_mbimx51_baseboard_init(void)
171{
172 mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
173 ARRAY_SIZE(mbimx51_pads));
174
175 mxc_register_device(&mxc_uart_device1, NULL);
176 mxc_register_device(&mxc_uart_device2, &uart_pdata);
177
178 gpio_request(MBIMX51_LED0, "LED0");
179 gpio_direction_output(MBIMX51_LED0, 1);
180 gpio_free(MBIMX51_LED0);
181 gpio_request(MBIMX51_LED1, "LED1");
182 gpio_direction_output(MBIMX51_LED1, 1);
183 gpio_free(MBIMX51_LED1);
184 gpio_request(MBIMX51_LED2, "LED2");
185 gpio_direction_output(MBIMX51_LED2, 1);
186 gpio_free(MBIMX51_LED2);
187 gpio_request(MBIMX51_LED3, "LED3");
188 gpio_direction_output(MBIMX51_LED3, 1);
189 gpio_free(MBIMX51_LED3);
190
191 platform_add_devices(devices, ARRAY_SIZE(devices));
192
193 mxc_register_device(&mxc_keypad_device, &mbimx51_map_data);
194
195 gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
196 gpio_direction_input(MBIMX51_TSC2007_GPIO);
197 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
198 i2c_register_board_info(1, mbimx51_i2c_devices,
199 ARRAY_SIZE(mbimx51_i2c_devices));
200}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index b7677ef80cc4..bc3f30db8d9a 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -65,6 +65,8 @@ void __init mx51_map_io(void)
65 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 65 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
66} 66}
67 67
68int imx51_register_gpios(void);
69
68void __init mx51_init_irq(void) 70void __init mx51_init_irq(void)
69{ 71{
70 unsigned long tzic_addr; 72 unsigned long tzic_addr;
@@ -80,4 +82,5 @@ void __init mx51_init_irq(void)
80 panic("unable to map TZIC interrupt controller\n"); 82 panic("unable to map TZIC interrupt controller\n");
81 83
82 tzic_init_irq(tzic_virt); 84 tzic_init_irq(tzic_virt);
85 imx51_register_gpios();
83} 86}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
index ce4f59058189..b989baccd675 100644
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -11,11 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */ 14 */
20 15
21#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ 16#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
index 353bd977b393..027af4f0d18a 100644
--- a/arch/arm/mach-mxc91231/devices.c
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -135,7 +135,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
135 }, 135 },
136}; 136};
137 137
138int __init mxc_register_gpios(void) 138int __init mxc91231_register_gpios(void)
139{ 139{
140 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); 140 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
141} 141}
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 6becda3ff331..aeccfd755fee 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -15,11 +15,6 @@
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */ 18 */
24 19
25#include <linux/mm.h> 20#include <linux/mm.h>
@@ -88,7 +83,10 @@ void __init mxc91231_map_io(void)
88 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 83 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
89} 84}
90 85
86int mxc91231_register_gpios(void);
87
91void __init mxc91231_init_irq(void) 88void __init mxc91231_init_irq(void)
92{ 89{
90 mxc91231_register_gpios();
93 mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR)); 91 mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
94} 92}
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
index f035f4185274..89f793adf776 100644
--- a/arch/arm/mach-nomadik/clock.c
+++ b/arch/arm/mach-nomadik/clock.c
@@ -53,6 +53,10 @@ static struct clk clk_default;
53 } 53 }
54 54
55static struct clk_lookup lookups[] = { 55static struct clk_lookup lookups[] = {
56 {
57 .con_id = "apb_pclk",
58 .clk = &clk_default,
59 },
56 CLK(&clk_24, "mtu0"), 60 CLK(&clk_24, "mtu0"),
57 CLK(&clk_24, "mtu1"), 61 CLK(&clk_24, "mtu1"),
58 CLK(&clk_48, "uart0"), 62 CLK(&clk_48, "uart0"),
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index fdd1dd53fa9c..0a9d61d2d229 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -301,6 +301,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
301 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 301 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
302 .boot_params = 0x10000100, 302 .boot_params = 0x10000100,
303 .map_io = ams_delta_map_io, 303 .map_io = ams_delta_map_io,
304 .reserve = omap_reserve,
304 .init_irq = ams_delta_init_irq, 305 .init_irq = ams_delta_init_irq,
305 .init_machine = ams_delta_init, 306 .init_machine = ams_delta_init,
306 .timer = &omap_timer, 307 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 096f2ed102cb..059bac60b35a 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -378,6 +378,7 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
378 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 378 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
379 .boot_params = 0x10000100, 379 .boot_params = 0x10000100,
380 .map_io = omap_fsample_map_io, 380 .map_io = omap_fsample_map_io,
381 .reserve = omap_reserve,
381 .init_irq = omap_fsample_init_irq, 382 .init_irq = omap_fsample_init_irq,
382 .init_machine = omap_fsample_init, 383 .init_machine = omap_fsample_init,
383 .timer = &omap_timer, 384 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e1195a3467b8..7a65684d2a15 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -98,6 +98,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
98 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 98 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
99 .boot_params = 0x10000100, 99 .boot_params = 0x10000100,
100 .map_io = omap_generic_map_io, 100 .map_io = omap_generic_map_io,
101 .reserve = omap_reserve,
101 .init_irq = omap_generic_init_irq, 102 .init_irq = omap_generic_init_irq,
102 .init_machine = omap_generic_init, 103 .init_machine = omap_generic_init,
103 .timer = &omap_timer, 104 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index d1100e4f65ac..68b2beda8b99 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -467,6 +467,7 @@ MACHINE_START(OMAP_H2, "TI-H2")
467 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 467 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
468 .boot_params = 0x10000100, 468 .boot_params = 0x10000100,
469 .map_io = h2_map_io, 469 .map_io = h2_map_io,
470 .reserve = omap_reserve,
470 .init_irq = h2_init_irq, 471 .init_irq = h2_init_irq,
471 .init_machine = h2_init, 472 .init_machine = h2_init,
472 .timer = &omap_timer, 473 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index a53ab8297d25..0b0825fe6751 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -437,6 +437,7 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
437 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 437 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
438 .boot_params = 0x10000100, 438 .boot_params = 0x10000100,
439 .map_io = h3_map_io, 439 .map_io = h3_map_io,
440 .reserve = omap_reserve,
440 .init_irq = h3_init_irq, 441 .init_irq = h3_init_irq,
441 .init_machine = h3_init, 442 .init_machine = h3_init,
442 .timer = &omap_timer, 443 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 8e313b4b99a9..d70a4f0923f5 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -304,6 +304,7 @@ MACHINE_START(HERALD, "HTC Herald")
304 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 304 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
305 .boot_params = 0x10000100, 305 .boot_params = 0x10000100,
306 .map_io = htcherald_map_io, 306 .map_io = htcherald_map_io,
307 .reserve = omap_reserve,
307 .init_irq = htcherald_init_irq, 308 .init_irq = htcherald_init_irq,
308 .init_machine = htcherald_init, 309 .init_machine = htcherald_init,
309 .timer = &omap_timer, 310 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 5d12fd35681b..91064b37859a 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -463,6 +463,7 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
463 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 463 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
464 .boot_params = 0x10000100, 464 .boot_params = 0x10000100,
465 .map_io = innovator_map_io, 465 .map_io = innovator_map_io,
466 .reserve = omap_reserve,
466 .init_irq = innovator_init_irq, 467 .init_irq = innovator_init_irq,
467 .init_machine = innovator_init, 468 .init_machine = innovator_init,
468 .timer = &omap_timer, 469 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 71e1a3fad0ea..8c28b10f3dae 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -400,6 +400,7 @@ MACHINE_START(NOKIA770, "Nokia 770")
400 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 400 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
401 .boot_params = 0x10000100, 401 .boot_params = 0x10000100,
402 .map_io = omap_nokia770_map_io, 402 .map_io = omap_nokia770_map_io,
403 .reserve = omap_reserve,
403 .init_irq = omap_nokia770_init_irq, 404 .init_irq = omap_nokia770_init_irq,
404 .init_machine = omap_nokia770_init, 405 .init_machine = omap_nokia770_init,
405 .timer = &omap_timer, 406 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 80d862001def..e2a72af30890 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -584,6 +584,7 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
584 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 584 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
585 .boot_params = 0x10000100, 585 .boot_params = 0x10000100,
586 .map_io = osk_map_io, 586 .map_io = osk_map_io,
587 .reserve = omap_reserve,
587 .init_irq = osk_init_irq, 588 .init_irq = osk_init_irq,
588 .init_machine = osk_init, 589 .init_machine = osk_init,
589 .timer = &omap_timer, 590 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 569b4c9085cd..61a2321b9732 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -373,6 +373,7 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
373 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 373 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
374 .boot_params = 0x10000100, 374 .boot_params = 0x10000100,
375 .map_io = omap_palmte_map_io, 375 .map_io = omap_palmte_map_io,
376 .reserve = omap_reserve,
376 .init_irq = omap_palmte_init_irq, 377 .init_irq = omap_palmte_init_irq,
377 .init_machine = omap_palmte_init, 378 .init_machine = omap_palmte_init,
378 .timer = &omap_timer, 379 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 6ad49a2cc1a0..21c01c6afcc1 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -321,6 +321,7 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
321 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 321 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
322 .boot_params = 0x10000100, 322 .boot_params = 0x10000100,
323 .map_io = omap_palmtt_map_io, 323 .map_io = omap_palmtt_map_io,
324 .reserve = omap_reserve,
324 .init_irq = omap_palmtt_init_irq, 325 .init_irq = omap_palmtt_init_irq,
325 .init_machine = omap_palmtt_init, 326 .init_machine = omap_palmtt_init,
326 .timer = &omap_timer, 327 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 6641de9257ef..f32492451533 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -338,10 +338,12 @@ omap_palmz71_map_io(void)
338} 338}
339 339
340MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") 340MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
341 .phys_io = 0xfff00000, 341 .phys_io = 0xfff00000,
342 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 342 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
343 .boot_params = 0x10000100,.map_io = omap_palmz71_map_io, 343 .boot_params = 0x10000100,
344 .init_irq = omap_palmz71_init_irq, 344 .map_io = omap_palmz71_map_io,
345 .init_machine = omap_palmz71_init, 345 .reserve = omap_reserve,
346 .timer = &omap_timer, 346 .init_irq = omap_palmz71_init_irq,
347 .init_machine = omap_palmz71_init,
348 .timer = &omap_timer,
347MACHINE_END 349MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index e854d5741c88..8b5ab1fcc405 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -339,6 +339,7 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
339 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 339 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
340 .boot_params = 0x10000100, 340 .boot_params = 0x10000100,
341 .map_io = omap_perseus2_map_io, 341 .map_io = omap_perseus2_map_io,
342 .reserve = omap_reserve,
342 .init_irq = omap_perseus2_init_irq, 343 .init_irq = omap_perseus2_init_irq,
343 .init_machine = omap_perseus2_init, 344 .init_machine = omap_perseus2_init,
344 .timer = &omap_timer, 345 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2fb1e5f8e2ec..995566b862bb 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -423,7 +423,8 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
423 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 423 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
424 .boot_params = 0x10000100, 424 .boot_params = 0x10000100,
425 .map_io = omap_sx1_map_io, 425 .map_io = omap_sx1_map_io,
426 .init_irq = omap_sx1_init_irq, 426 .reserve = omap_reserve,
427 .init_irq = omap_sx1_init_irq,
427 .init_machine = omap_sx1_init, 428 .init_machine = omap_sx1_init,
428 .timer = &omap_timer, 429 .timer = &omap_timer,
429MACHINE_END 430MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 87b9436fe7c0..4c483dc1de5c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -287,6 +287,7 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
287 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, 287 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
288 .boot_params = 0x10000100, 288 .boot_params = 0x10000100,
289 .map_io = voiceblue_map_io, 289 .map_io = voiceblue_map_io,
290 .reserve = omap_reserve,
290 .init_irq = voiceblue_init_irq, 291 .init_irq = voiceblue_init_irq,
291 .init_machine = voiceblue_init, 292 .init_machine = voiceblue_init,
292 .timer = &omap_timer, 293 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index d9b8d82530ae..0ce3fec2d257 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -22,7 +22,6 @@
22 22
23extern void omap_check_revision(void); 23extern void omap_check_revision(void);
24extern void omap_sram_init(void); 24extern void omap_sram_init(void);
25extern void omapfb_reserve_sdram(void);
26 25
27/* 26/*
28 * The machine specific code may provide the extra mapping besides the 27 * The machine specific code may provide the extra mapping besides the
@@ -122,7 +121,6 @@ void __init omap1_map_common_io(void)
122#endif 121#endif
123 122
124 omap_sram_init(); 123 omap_sram_init();
125 omapfb_reserve_sdram();
126} 124}
127 125
128/* 126/*
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index a11a575745e4..42f49f785c93 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -248,6 +248,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
248 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 248 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
249 .boot_params = 0x80000100, 249 .boot_params = 0x80000100,
250 .map_io = omap_2430sdp_map_io, 250 .map_io = omap_2430sdp_map_io,
251 .reserve = omap_reserve,
251 .init_irq = omap_2430sdp_init_irq, 252 .init_irq = omap_2430sdp_init_irq,
252 .init_machine = omap_2430sdp_init, 253 .init_machine = omap_2430sdp_init,
253 .timer = &omap_timer, 254 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index f474a80b8867..dd9c03171a19 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -815,6 +815,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
815 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 815 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
816 .boot_params = 0x80000100, 816 .boot_params = 0x80000100,
817 .map_io = omap_3430sdp_map_io, 817 .map_io = omap_3430sdp_map_io,
818 .reserve = omap_reserve,
818 .init_irq = omap_3430sdp_init_irq, 819 .init_irq = omap_3430sdp_init_irq,
819 .init_machine = omap_3430sdp_init, 820 .init_machine = omap_3430sdp_init,
820 .timer = &omap_timer, 821 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 504d2bd222fe..57290fb3fcd7 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -108,6 +108,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
108 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 108 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
109 .boot_params = 0x80000100, 109 .boot_params = 0x80000100,
110 .map_io = omap_sdp_map_io, 110 .map_io = omap_sdp_map_io,
111 .reserve = omap_reserve,
111 .init_irq = omap_sdp_init_irq, 112 .init_irq = omap_sdp_init_irq,
112 .init_machine = omap_sdp_init, 113 .init_machine = omap_sdp_init,
113 .timer = &omap_timer, 114 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index e4a5d66b83b8..4bb2c5d151ec 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -402,6 +402,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
402 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 402 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
403 .boot_params = 0x80000100, 403 .boot_params = 0x80000100,
404 .map_io = omap_4430sdp_map_io, 404 .map_io = omap_4430sdp_map_io,
405 .reserve = omap_reserve,
405 .init_irq = omap_4430sdp_init_irq, 406 .init_irq = omap_4430sdp_init_irq,
406 .init_machine = omap_4430sdp_init, 407 .init_machine = omap_4430sdp_init,
407 .timer = &omap_timer, 408 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index af383a876943..7da92defcde0 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -472,6 +472,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
472 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 472 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
473 .boot_params = 0x80000100, 473 .boot_params = 0x80000100,
474 .map_io = am3517_evm_map_io, 474 .map_io = am3517_evm_map_io,
475 .reserve = omap_reserve,
475 .init_irq = am3517_evm_init_irq, 476 .init_irq = am3517_evm_init_irq,
476 .init_machine = am3517_evm_init, 477 .init_machine = am3517_evm_init,
477 .timer = &omap_timer, 478 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index aa69fb999748..bd75642aee65 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -346,6 +346,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
346 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 346 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
347 .boot_params = 0x80000100, 347 .boot_params = 0x80000100,
348 .map_io = omap_apollon_map_io, 348 .map_io = omap_apollon_map_io,
349 .reserve = omap_reserve,
349 .init_irq = omap_apollon_init_irq, 350 .init_irq = omap_apollon_init_irq,
350 .init_machine = omap_apollon_init, 351 .init_machine = omap_apollon_init,
351 .timer = &omap_timer, 352 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e679a2cc86c3..bc4c3f807068 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -837,6 +837,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
837 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 837 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
838 .boot_params = 0x80000100, 838 .boot_params = 0x80000100,
839 .map_io = cm_t35_map_io, 839 .map_io = cm_t35_map_io,
840 .reserve = omap_reserve,
840 .init_irq = cm_t35_init_irq, 841 .init_irq = cm_t35_init_irq,
841 .init_machine = cm_t35_init, 842 .init_machine = cm_t35_init,
842 .timer = &omap_timer, 843 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 77022b588816..922b7464807f 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -825,6 +825,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
825 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 825 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
826 .boot_params = 0x80000100, 826 .boot_params = 0x80000100,
827 .map_io = devkit8000_map_io, 827 .map_io = devkit8000_map_io,
828 .reserve = omap_reserve,
828 .init_irq = devkit8000_init_irq, 829 .init_irq = devkit8000_init_irq,
829 .init_machine = devkit8000_init, 830 .init_machine = devkit8000_init,
830 .timer = &omap_timer, 831 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 16cc06860670..9242902d3a43 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -59,6 +59,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
59 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 59 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
60 .boot_params = 0x80000100, 60 .boot_params = 0x80000100,
61 .map_io = omap_generic_map_io, 61 .map_io = omap_generic_map_io,
62 .reserve = omap_reserve,
62 .init_irq = omap_generic_init_irq, 63 .init_irq = omap_generic_init_irq,
63 .init_machine = omap_generic_init, 64 .init_machine = omap_generic_init,
64 .timer = &omap_timer, 65 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 0665f2c8dc8e..16703fdb3515 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -378,6 +378,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
378 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 378 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
379 .boot_params = 0x80000100, 379 .boot_params = 0x80000100,
380 .map_io = omap_h4_map_io, 380 .map_io = omap_h4_map_io,
381 .reserve = omap_reserve,
381 .init_irq = omap_h4_init_irq, 382 .init_irq = omap_h4_init_irq,
382 .init_machine = omap_h4_init, 383 .init_machine = omap_h4_init,
383 .timer = &omap_timer, 384 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index d55c57b761a9..759e39d1a702 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -543,6 +543,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
543 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 543 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
544 .boot_params = 0x80000100, 544 .boot_params = 0x80000100,
545 .map_io = igep2_map_io, 545 .map_io = igep2_map_io,
546 .reserve = omap_reserve,
546 .init_irq = igep2_init_irq, 547 .init_irq = igep2_init_irq,
547 .init_machine = igep2_init, 548 .init_machine = igep2_init,
548 .timer = &omap_timer, 549 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index fefd7e6e9779..9cd2669113e4 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -417,6 +417,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
417 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 417 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
418 .boot_params = 0x80000100, 418 .boot_params = 0x80000100,
419 .map_io = omap_ldp_map_io, 419 .map_io = omap_ldp_map_io,
420 .reserve = omap_reserve,
420 .init_irq = omap_ldp_init_irq, 421 .init_irq = omap_ldp_init_irq,
421 .init_machine = omap_ldp_init, 422 .init_machine = omap_ldp_init,
422 .timer = &omap_timer, 423 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 3ccc34ebdcc7..2565ff08a221 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -667,6 +667,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
667 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 667 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
668 .boot_params = 0x80000100, 668 .boot_params = 0x80000100,
669 .map_io = n8x0_map_io, 669 .map_io = n8x0_map_io,
670 .reserve = omap_reserve,
670 .init_irq = n8x0_init_irq, 671 .init_irq = n8x0_init_irq,
671 .init_machine = n8x0_init_machine, 672 .init_machine = n8x0_init_machine,
672 .timer = &omap_timer, 673 .timer = &omap_timer,
@@ -677,6 +678,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
677 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 678 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
678 .boot_params = 0x80000100, 679 .boot_params = 0x80000100,
679 .map_io = n8x0_map_io, 680 .map_io = n8x0_map_io,
681 .reserve = omap_reserve,
680 .init_irq = n8x0_init_irq, 682 .init_irq = n8x0_init_irq,
681 .init_machine = n8x0_init_machine, 683 .init_machine = n8x0_init_machine,
682 .timer = &omap_timer, 684 .timer = &omap_timer,
@@ -687,6 +689,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
687 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 689 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
688 .boot_params = 0x80000100, 690 .boot_params = 0x80000100,
689 .map_io = n8x0_map_io, 691 .map_io = n8x0_map_io,
692 .reserve = omap_reserve,
690 .init_irq = n8x0_init_irq, 693 .init_irq = n8x0_init_irq,
691 .init_machine = n8x0_init_machine, 694 .init_machine = n8x0_init_machine,
692 .timer = &omap_timer, 695 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 69b154cdc75d..0ab0c26db4dd 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -519,6 +519,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
519 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 519 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
520 .boot_params = 0x80000100, 520 .boot_params = 0x80000100,
521 .map_io = omap3_beagle_map_io, 521 .map_io = omap3_beagle_map_io,
522 .reserve = omap_reserve,
522 .init_irq = omap3_beagle_init_irq, 523 .init_irq = omap3_beagle_init_irq,
523 .init_machine = omap3_beagle_init, 524 .init_machine = omap3_beagle_init,
524 .timer = &omap_timer, 525 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b95261013812..a3d2e285e116 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -727,6 +727,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
727 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 727 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
728 .boot_params = 0x80000100, 728 .boot_params = 0x80000100,
729 .map_io = omap3_evm_map_io, 729 .map_io = omap3_evm_map_io,
730 .reserve = omap_reserve,
730 .init_irq = omap3_evm_init_irq, 731 .init_irq = omap3_evm_init_irq,
731 .init_machine = omap3_evm_init, 732 .init_machine = omap3_evm_init,
732 .timer = &omap_timer, 733 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index db06dc910ba7..c0f4f12eba54 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -601,6 +601,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
601 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 601 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
602 .boot_params = 0x80000100, 602 .boot_params = 0x80000100,
603 .map_io = omap3pandora_map_io, 603 .map_io = omap3pandora_map_io,
604 .reserve = omap_reserve,
604 .init_irq = omap3pandora_init_irq, 605 .init_irq = omap3pandora_init_irq,
605 .init_machine = omap3pandora_init, 606 .init_machine = omap3pandora_init,
606 .timer = &omap_timer, 607 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 2f5f8233dd5b..f05b867c5851 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -571,6 +571,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
571 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 571 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
572 .boot_params = 0x80000100, 572 .boot_params = 0x80000100,
573 .map_io = omap3_touchbook_map_io, 573 .map_io = omap3_touchbook_map_io,
574 .reserve = omap_reserve,
574 .init_irq = omap3_touchbook_init_irq, 575 .init_irq = omap3_touchbook_init_irq,
575 .init_machine = omap3_touchbook_init, 576 .init_machine = omap3_touchbook_init,
576 .timer = &omap_timer, 577 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 79ac41400c21..87acb2f198ec 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -495,6 +495,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
495 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 495 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
496 .boot_params = 0x80000100, 496 .boot_params = 0x80000100,
497 .map_io = overo_map_io, 497 .map_io = overo_map_io,
498 .reserve = omap_reserve,
498 .init_irq = overo_init_irq, 499 .init_irq = overo_init_irq,
499 .init_machine = overo_init, 500 .init_machine = overo_init,
500 .timer = &omap_timer, 501 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 1b86b5bb87a2..3bd956f9e19f 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -154,6 +154,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
154 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 154 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
155 .boot_params = 0x80000100, 155 .boot_params = 0x80000100,
156 .map_io = rx51_map_io, 156 .map_io = rx51_map_io,
157 .reserve = omap_reserve,
157 .init_irq = rx51_init_irq, 158 .init_irq = rx51_init_irq,
158 .init_machine = rx51_init, 159 .init_machine = rx51_init,
159 .timer = &omap_timer, 160 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 803ef14cbf2d..ffe188cb18e9 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -95,6 +95,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
95 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, 95 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
96 .boot_params = 0x80000100, 96 .boot_params = 0x80000100,
97 .map_io = omap_zoom2_map_io, 97 .map_io = omap_zoom2_map_io,
98 .reserve = omap_reserve,
98 .init_irq = omap_zoom2_init_irq, 99 .init_irq = omap_zoom2_init_irq,
99 .init_machine = omap_zoom2_init, 100 .init_machine = omap_zoom2_init,
100 .timer = &omap_timer, 101 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index 33147042485f..5b605eba3e7b 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -77,6 +77,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
77 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, 77 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
78 .boot_params = 0x80000100, 78 .boot_params = 0x80000100,
79 .map_io = omap_zoom_map_io, 79 .map_io = omap_zoom_map_io,
80 .reserve = omap_reserve,
80 .init_irq = omap_zoom_init_irq, 81 .init_irq = omap_zoom_init_irq,
81 .init_machine = omap_zoom_init, 82 .init_machine = omap_zoom_init,
82 .timer = &omap_timer, 83 .timer = &omap_timer,
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 41b155acfca7..d33744117ce2 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3166,6 +3166,10 @@ static struct clk uart4_ick_am35xx = {
3166 .recalc = &followparent_recalc, 3166 .recalc = &followparent_recalc,
3167}; 3167};
3168 3168
3169static struct clk dummy_apb_pclk = {
3170 .name = "apb_pclk",
3171 .ops = &clkops_null,
3172};
3169 3173
3170/* 3174/*
3171 * clkdev 3175 * clkdev
@@ -3173,6 +3177,7 @@ static struct clk uart4_ick_am35xx = {
3173 3177
3174/* XXX At some point we should rename this file to clock3xxx_data.c */ 3178/* XXX At some point we should rename this file to clock3xxx_data.c */
3175static struct omap_clk omap3xxx_clks[] = { 3179static struct omap_clk omap3xxx_clks[] = {
3180 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3176 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), 3181 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3177 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3182 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3178 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3183 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3cfb425ea67e..4e1f53d0b880 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,7 +33,6 @@
33#include <plat/sdrc.h> 33#include <plat/sdrc.h>
34#include <plat/gpmc.h> 34#include <plat/gpmc.h>
35#include <plat/serial.h> 35#include <plat/serial.h>
36#include <plat/vram.h>
37 36
38#include "clock2xxx.h" 37#include "clock2xxx.h"
39#include "clock3xxx.h" 38#include "clock3xxx.h"
@@ -241,8 +240,6 @@ static void __init _omap2_map_common_io(void)
241 240
242 omap2_check_revision(); 241 omap2_check_revision();
243 omap_sram_init(); 242 omap_sram_init();
244 omapfb_reserve_sdram();
245 omap_vram_reserve_sdram();
246} 243}
247 244
248#ifdef CONFIG_ARCH_OMAP2420 245#ifdef CONFIG_ARCH_OMAP2420
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 905719a677ae..c897e03e413d 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -26,6 +26,7 @@ config MACH_KUROBOX_PRO
26config MACH_DNS323 26config MACH_DNS323
27 bool "D-Link DNS-323" 27 bool "D-Link DNS-323"
28 select I2C_BOARDINFO 28 select I2C_BOARDINFO
29 select PHYLIB
29 help 30 help
30 Say 'Y' here if you want your kernel to support the 31 Say 'Y' here if you want your kernel to support the
31 D-Link DNS-323 platform. 32 D-Link DNS-323 platform.
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index fe0de1698edc..a47100d46a4e 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -3,6 +3,10 @@
3 * 3 *
4 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> 4 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
5 * 5 *
6 * Support for HW Rev C1:
7 *
8 * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 *
6 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as 11 * it under the terms of the GNU Lesser General Public License as
8 * published by the Free Software Foundation; either version 2 of the 12 * published by the Free Software Foundation; either version 2 of the
@@ -23,6 +27,8 @@
23#include <linux/input.h> 27#include <linux/input.h>
24#include <linux/i2c.h> 28#include <linux/i2c.h>
25#include <linux/ata_platform.h> 29#include <linux/ata_platform.h>
30#include <linux/phy.h>
31#include <linux/marvell_phy.h>
26#include <asm/mach-types.h> 32#include <asm/mach-types.h>
27#include <asm/gpio.h> 33#include <asm/gpio.h>
28#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
@@ -31,6 +37,7 @@
31#include "common.h" 37#include "common.h"
32#include "mpp.h" 38#include "mpp.h"
33 39
40/* Rev A1 and B1 */
34#define DNS323_GPIO_LED_RIGHT_AMBER 1 41#define DNS323_GPIO_LED_RIGHT_AMBER 1
35#define DNS323_GPIO_LED_LEFT_AMBER 2 42#define DNS323_GPIO_LED_LEFT_AMBER 2
36#define DNS323_GPIO_SYSTEM_UP 3 43#define DNS323_GPIO_SYSTEM_UP 3
@@ -42,6 +49,23 @@
42#define DNS323_GPIO_KEY_POWER 9 49#define DNS323_GPIO_KEY_POWER 9
43#define DNS323_GPIO_KEY_RESET 10 50#define DNS323_GPIO_KEY_RESET 10
44 51
52/* Rev C1 */
53#define DNS323C_GPIO_KEY_POWER 1
54#define DNS323C_GPIO_POWER_OFF 2
55#define DNS323C_GPIO_LED_RIGHT_AMBER 8
56#define DNS323C_GPIO_LED_LEFT_AMBER 9
57#define DNS323C_GPIO_LED_POWER 17
58#define DNS323C_GPIO_FAN_BIT1 18
59#define DNS323C_GPIO_FAN_BIT0 19
60
61/* Exposed to userspace, do not change */
62enum {
63 DNS323_REV_A1, /* 0 */
64 DNS323_REV_B1, /* 1 */
65 DNS323_REV_C1, /* 2 */
66};
67
68
45/**************************************************************************** 69/****************************************************************************
46 * PCI setup 70 * PCI setup
47 */ 71 */
@@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = {
68 .map_irq = dns323_pci_map_irq, 92 .map_irq = dns323_pci_map_irq,
69}; 93};
70 94
71static int __init dns323_dev_id(void)
72{
73 u32 dev, rev;
74
75 orion5x_pcie_id(&dev, &rev);
76
77 return dev;
78}
79
80static int __init dns323_pci_init(void) 95static int __init dns323_pci_init(void)
81{ 96{
82 /* The 5182 doesn't really use its PCI bus, and initialising PCI 97 /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
83 * gets in the way of initialising the SATA controller. 98 * gets in the way of initialising the SATA controller.
84 */ 99 */
85 if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) 100 if (machine_is_dns323() && system_rev == DNS323_REV_A1)
86 pci_common_init(&dns323_pci); 101 pci_common_init(&dns323_pci);
87 102
88 return 0; 103 return 0;
@@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void)
221 } 236 }
222 237
223 iounmap(mac_page); 238 iounmap(mac_page);
224 printk("DNS323: Found ethernet MAC address: "); 239 printk("DNS-323: Found ethernet MAC address: ");
225 for (i = 0; i < 6; i++) 240 for (i = 0; i < 6; i++)
226 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); 241 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
227 242
@@ -259,12 +274,11 @@ static int dns323_gpio_blink_set(unsigned gpio, int state,
259 return 0; 274 return 0;
260} 275}
261 276
262static struct gpio_led dns323_leds[] = { 277static struct gpio_led dns323ab_leds[] = {
263 { 278 {
264 .name = "power:blue", 279 .name = "power:blue",
265 .gpio = DNS323_GPIO_LED_POWER2, 280 .gpio = DNS323_GPIO_LED_POWER2,
266 .default_trigger = "timer", 281 .default_trigger = "default-on",
267 .active_low = 1,
268 }, { 282 }, {
269 .name = "right:amber", 283 .name = "right:amber",
270 .gpio = DNS323_GPIO_LED_RIGHT_AMBER, 284 .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
@@ -276,9 +290,34 @@ static struct gpio_led dns323_leds[] = {
276 }, 290 },
277}; 291};
278 292
279static struct gpio_led_platform_data dns323_led_data = { 293
280 .num_leds = ARRAY_SIZE(dns323_leds), 294static struct gpio_led dns323c_leds[] = {
281 .leds = dns323_leds, 295 {
296 .name = "power:blue",
297 .gpio = DNS323C_GPIO_LED_POWER,
298 .default_trigger = "timer",
299 .active_low = 1,
300 }, {
301 .name = "right:amber",
302 .gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
303 .active_low = 1,
304 }, {
305 .name = "left:amber",
306 .gpio = DNS323C_GPIO_LED_LEFT_AMBER,
307 .active_low = 1,
308 },
309};
310
311
312static struct gpio_led_platform_data dns323ab_led_data = {
313 .num_leds = ARRAY_SIZE(dns323ab_leds),
314 .leds = dns323ab_leds,
315 .gpio_blink_set = dns323_gpio_blink_set,
316};
317
318static struct gpio_led_platform_data dns323c_led_data = {
319 .num_leds = ARRAY_SIZE(dns323c_leds),
320 .leds = dns323c_leds,
282 .gpio_blink_set = dns323_gpio_blink_set, 321 .gpio_blink_set = dns323_gpio_blink_set,
283}; 322};
284 323
@@ -286,7 +325,7 @@ static struct platform_device dns323_gpio_leds = {
286 .name = "leds-gpio", 325 .name = "leds-gpio",
287 .id = -1, 326 .id = -1,
288 .dev = { 327 .dev = {
289 .platform_data = &dns323_led_data, 328 .platform_data = &dns323ab_led_data,
290 }, 329 },
291}; 330};
292 331
@@ -294,7 +333,7 @@ static struct platform_device dns323_gpio_leds = {
294 * GPIO Attached Keys 333 * GPIO Attached Keys
295 */ 334 */
296 335
297static struct gpio_keys_button dns323_buttons[] = { 336static struct gpio_keys_button dns323ab_buttons[] = {
298 { 337 {
299 .code = KEY_RESTART, 338 .code = KEY_RESTART,
300 .gpio = DNS323_GPIO_KEY_RESET, 339 .gpio = DNS323_GPIO_KEY_RESET,
@@ -308,9 +347,23 @@ static struct gpio_keys_button dns323_buttons[] = {
308 }, 347 },
309}; 348};
310 349
311static struct gpio_keys_platform_data dns323_button_data = { 350static struct gpio_keys_platform_data dns323ab_button_data = {
312 .buttons = dns323_buttons, 351 .buttons = dns323ab_buttons,
313 .nbuttons = ARRAY_SIZE(dns323_buttons), 352 .nbuttons = ARRAY_SIZE(dns323ab_buttons),
353};
354
355static struct gpio_keys_button dns323c_buttons[] = {
356 {
357 .code = KEY_POWER,
358 .gpio = DNS323C_GPIO_KEY_POWER,
359 .desc = "Power Button",
360 .active_low = 1,
361 },
362};
363
364static struct gpio_keys_platform_data dns323c_button_data = {
365 .buttons = dns323c_buttons,
366 .nbuttons = ARRAY_SIZE(dns323c_buttons),
314}; 367};
315 368
316static struct platform_device dns323_button_device = { 369static struct platform_device dns323_button_device = {
@@ -318,7 +371,7 @@ static struct platform_device dns323_button_device = {
318 .id = -1, 371 .id = -1,
319 .num_resources = 0, 372 .num_resources = 0,
320 .dev = { 373 .dev = {
321 .platform_data = &dns323_button_data, 374 .platform_data = &dns323ab_button_data,
322 }, 375 },
323}; 376};
324 377
@@ -332,7 +385,7 @@ static struct mv_sata_platform_data dns323_sata_data = {
332/**************************************************************************** 385/****************************************************************************
333 * General Setup 386 * General Setup
334 */ 387 */
335static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = { 388static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
336 { 0, MPP_PCIE_RST_OUTn }, 389 { 0, MPP_PCIE_RST_OUTn },
337 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 390 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
338 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 391 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
@@ -356,7 +409,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
356 { -1 }, 409 { -1 },
357}; 410};
358 411
359static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = { 412static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
360 { 0, MPP_UNUSED }, 413 { 0, MPP_UNUSED },
361 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 414 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
362 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 415 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
@@ -380,15 +433,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
380 { -1 }, 433 { -1 },
381}; 434};
382 435
436static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
437 { 0, MPP_GPIO }, /* ? input */
438 { 1, MPP_GPIO }, /* input power switch (0 = pressed) */
439 { 2, MPP_GPIO }, /* output power off */
440 { 3, MPP_UNUSED }, /* ? output */
441 { 4, MPP_UNUSED }, /* ? output */
442 { 5, MPP_UNUSED }, /* ? output */
443 { 6, MPP_UNUSED }, /* ? output */
444 { 7, MPP_UNUSED }, /* ? output */
445 { 8, MPP_GPIO }, /* i/o right amber LED */
446 { 9, MPP_GPIO }, /* i/o left amber LED */
447 { 10, MPP_GPIO }, /* input */
448 { 11, MPP_UNUSED },
449 { 12, MPP_SATA_LED },
450 { 13, MPP_SATA_LED },
451 { 14, MPP_SATA_LED },
452 { 15, MPP_SATA_LED },
453 { 16, MPP_UNUSED },
454 { 17, MPP_GPIO }, /* power button LED */
455 { 18, MPP_GPIO }, /* fan speed bit 0 */
456 { 19, MPP_GPIO }, /* fan speed bit 1 */
457 { -1 },
458};
459
460/* Rev C1 Fan speed notes:
461 *
462 * The fan is controlled by 2 GPIOs on this board. The settings
463 * of the bits is as follow:
464 *
465 * GPIO 18 GPIO 19 Fan
466 *
467 * 0 0 stopped
468 * 0 1 low speed
469 * 1 0 high speed
470 * 1 1 don't do that (*)
471 *
472 * (*) I think the two bits control two feed-in resistors into a fixed
473 * PWN circuit, setting both bits will basically go a 'bit' faster
474 * than high speed, but d-link doesn't do it and you may get out of
475 * HW spec so don't do it.
476 */
477
383/* 478/*
384 * On the DNS-323 the following devices are attached via I2C: 479 * On the DNS-323 A1 and B1 the following devices are attached via I2C:
385 * 480 *
386 * i2c addr | chip | description 481 * i2c addr | chip | description
387 * 0x3e | GMT G760Af | fan speed PWM controller 482 * 0x3e | GMT G760Af | fan speed PWM controller
388 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible) 483 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
389 * 0x68 | ST M41T80 | RTC w/ alarm 484 * 0x68 | ST M41T80 | RTC w/ alarm
390 */ 485 */
391static struct i2c_board_info __initdata dns323_i2c_devices[] = { 486static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
392 { 487 {
393 I2C_BOARD_INFO("g760a", 0x3e), 488 I2C_BOARD_INFO("g760a", 0x3e),
394 }, { 489 }, {
@@ -398,36 +493,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
398 }, 493 },
399}; 494};
400 495
496/*
497 * On the DNS-323 C1 the following devices are attached via I2C:
498 *
499 * i2c addr | chip | description
500 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
501 * 0x68 | ST M41T80 | RTC w/ alarm
502 */
503static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
504 {
505 I2C_BOARD_INFO("lm75", 0x48),
506 }, {
507 I2C_BOARD_INFO("m41t80", 0x68),
508 },
509};
510
401/* DNS-323 rev. A specific power off method */ 511/* DNS-323 rev. A specific power off method */
402static void dns323a_power_off(void) 512static void dns323a_power_off(void)
403{ 513{
404 pr_info("%s: triggering power-off...\n", __func__); 514 pr_info("DNS-323: Triggering power-off...\n");
405 gpio_set_value(DNS323_GPIO_POWER_OFF, 1); 515 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
406} 516}
407 517
408/* DNS-323 rev B specific power off method */ 518/* DNS-323 rev B specific power off method */
409static void dns323b_power_off(void) 519static void dns323b_power_off(void)
410{ 520{
411 pr_info("%s: triggering power-off...\n", __func__); 521 pr_info("DNS-323: Triggering power-off...\n");
412 /* Pin has to be changed to 1 and back to 0 to do actual power off. */ 522 /* Pin has to be changed to 1 and back to 0 to do actual power off. */
413 gpio_set_value(DNS323_GPIO_POWER_OFF, 1); 523 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
414 mdelay(100); 524 mdelay(100);
415 gpio_set_value(DNS323_GPIO_POWER_OFF, 0); 525 gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
416} 526}
417 527
528/* DNS-323 rev. C specific power off method */
529static void dns323c_power_off(void)
530{
531 pr_info("DNS-323: Triggering power-off...\n");
532 gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
533}
534
535static int dns323c_phy_fixup(struct phy_device *phy)
536{
537 phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
538
539 return 0;
540}
541
542static int __init dns323_identify_rev(void)
543{
544 u32 dev, rev, i, reg;
545
546 pr_debug("DNS-323: Identifying board ... \n");
547
548 /* Rev A1 has a 5181 */
549 orion5x_pcie_id(&dev, &rev);
550 if (dev == MV88F5181_DEV_ID) {
551 pr_debug("DNS-323: 5181 found, board is A1\n");
552 return DNS323_REV_A1;
553 }
554 pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
555
556 /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
557 * a bit gross but we want to do that without links into the eth
558 * driver so let's poke at it directly. We default to rev B1 in
559 * case the accesses fail
560 */
561
562#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
563#define SMI_BUSY 0x10000000
564#define SMI_READ_VALID 0x08000000
565#define SMI_OPCODE_READ 0x04000000
566#define SMI_OPCODE_WRITE 0x00000000
567
568 for (i = 0; i < 1000; i++) {
569 reg = readl(ETH_SMI_REG);
570 if (!(reg & SMI_BUSY))
571 break;
572 }
573 if (i >= 1000) {
574 pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
575 return DNS323_REV_B1;
576 }
577 writel((3 << 21) /* phy ID reg */ |
578 (8 << 16) /* phy addr */ |
579 SMI_OPCODE_READ, ETH_SMI_REG);
580 for (i = 0; i < 1000; i++) {
581 reg = readl(ETH_SMI_REG);
582 if (reg & SMI_READ_VALID)
583 break;
584 }
585 if (i >= 1000) {
586 pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
587 return DNS323_REV_B1;
588 }
589 pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
590
591 /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
592 * but I don't see that making a difference here, at least with
593 * any known Marvell PHY ID
594 */
595 switch(reg & 0xfff0) {
596 case 0x0cc0: /* MV88E1111 */
597 return DNS323_REV_B1;
598 case 0x0e10: /* MV88E1118 */
599 return DNS323_REV_C1;
600 default:
601 pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
602 reg & 0xffff);
603 }
604 return DNS323_REV_B1;
605}
606
418static void __init dns323_init(void) 607static void __init dns323_init(void)
419{ 608{
420 /* Setup basic Orion functions. Need to be called early. */ 609 /* Setup basic Orion functions. Need to be called early. */
421 orion5x_init(); 610 orion5x_init();
422 611
612 /* Identify revision */
613 system_rev = dns323_identify_rev();
614 pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
615
423 /* Just to be tricky, the 5182 has a completely different 616 /* Just to be tricky, the 5182 has a completely different
424 * set of MPP modes to the 5181. 617 * set of MPP modes to the 5181.
425 */ 618 */
426 if (dns323_dev_id() == MV88F5182_DEV_ID) 619 switch(system_rev) {
427 orion5x_mpp_conf(dns323_mv88f5182_mpp_modes); 620 case DNS323_REV_A1:
428 else { 621 orion5x_mpp_conf(dns323a_mpp_modes);
429 orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
430 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ 622 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
623 break;
624 case DNS323_REV_B1:
625 orion5x_mpp_conf(dns323b_mpp_modes);
626 break;
627 case DNS323_REV_C1:
628 orion5x_mpp_conf(dns323c_mpp_modes);
629 break;
431 } 630 }
432 631
433 /* setup flash mapping 632 /* setup flash mapping
@@ -436,53 +635,96 @@ static void __init dns323_init(void)
436 orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); 635 orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
437 platform_device_register(&dns323_nor_flash); 636 platform_device_register(&dns323_nor_flash);
438 637
439 /* The 5181 power LED is active low and requires 638 /* Sort out LEDs, Buttons and i2c devices */
440 * DNS323_GPIO_LED_POWER1 to also be low. 639 switch(system_rev) {
441 */ 640 case DNS323_REV_A1:
442 if (dns323_dev_id() == MV88F5181_DEV_ID) { 641 /* The 5181 power LED is active low and requires
443 dns323_leds[0].active_low = 1; 642 * DNS323_GPIO_LED_POWER1 to also be low.
444 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); 643 */
445 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); 644 dns323ab_leds[0].active_low = 1;
645 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
646 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
647 /* Fall through */
648 case DNS323_REV_B1:
649 i2c_register_board_info(0, dns323ab_i2c_devices,
650 ARRAY_SIZE(dns323ab_i2c_devices));
651 break;
652 case DNS323_REV_C1:
653 /* Hookup LEDs & Buttons */
654 dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
655 dns323_button_device.dev.platform_data = &dns323c_button_data;
656
657 /* Hookup i2c devices and fan driver */
658 i2c_register_board_info(0, dns323c_i2c_devices,
659 ARRAY_SIZE(dns323c_i2c_devices));
660 platform_device_register_simple("dns323c-fan", 0, NULL, 0);
661
662 /* Register fixup for the PHY LEDs */
663 phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
664 MARVELL_PHY_ID_MASK,
665 dns323c_phy_fixup);
446 } 666 }
447 667
448 platform_device_register(&dns323_gpio_leds); 668 platform_device_register(&dns323_gpio_leds);
449
450 platform_device_register(&dns323_button_device); 669 platform_device_register(&dns323_button_device);
451 670
452 i2c_register_board_info(0, dns323_i2c_devices,
453 ARRAY_SIZE(dns323_i2c_devices));
454
455 /* 671 /*
456 * Configure peripherals. 672 * Configure peripherals.
457 */ 673 */
458 if (dns323_read_mac_addr() < 0) 674 if (dns323_read_mac_addr() < 0)
459 printk("DNS323: Failed to read MAC address\n"); 675 printk("DNS-323: Failed to read MAC address\n");
460
461 orion5x_ehci0_init(); 676 orion5x_ehci0_init();
462 orion5x_eth_init(&dns323_eth_data); 677 orion5x_eth_init(&dns323_eth_data);
463 orion5x_i2c_init(); 678 orion5x_i2c_init();
464 orion5x_uart0_init(); 679 orion5x_uart0_init();
465 680
466 /* The 5182 has its SATA controller on-chip, and needs its own little 681 /* Remaining GPIOs */
467 * init routine. 682 switch(system_rev) {
468 */ 683 case DNS323_REV_A1:
469 if (dns323_dev_id() == MV88F5182_DEV_ID) 684 /* Poweroff GPIO */
685 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
686 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
687 pr_err("DNS-323: failed to setup power-off GPIO\n");
688 pm_power_off = dns323a_power_off;
689 break;
690 case DNS323_REV_B1:
691 /* 5182 built-in SATA init */
470 orion5x_sata_init(&dns323_sata_data); 692 orion5x_sata_init(&dns323_sata_data);
471 693
472 /* The 5182 has flag to indicate the system is up. Without this flag 694 /* The DNS323 rev B1 has flag to indicate the system is up.
473 * set, power LED will flash and cannot be controlled via leds-gpio. 695 * Without this flag set, power LED will flash and cannot be
474 */ 696 * controlled via leds-gpio.
475 if (dns323_dev_id() == MV88F5182_DEV_ID) 697 */
476 gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1); 698 if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
477 699 gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
478 /* Register dns323 specific power-off method */ 700
479 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || 701 /* Poweroff GPIO */
480 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) 702 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
481 pr_err("DNS323: failed to setup power-off GPIO\n"); 703 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
482 if (dns323_dev_id() == MV88F5182_DEV_ID) 704 pr_err("DNS-323: failed to setup power-off GPIO\n");
483 pm_power_off = dns323b_power_off; 705 pm_power_off = dns323b_power_off;
484 else 706 break;
485 pm_power_off = dns323a_power_off; 707 case DNS323_REV_C1:
708 /* 5182 built-in SATA init */
709 orion5x_sata_init(&dns323_sata_data);
710
711 /* Poweroff GPIO */
712 if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
713 gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
714 pr_err("DNS-323: failed to setup power-off GPIO\n");
715 pm_power_off = dns323c_power_off;
716
717 /* Now, -this- should theorically be done by the sata_mv driver
718 * once I figure out what's going on there. Maybe the behaviour
719 * of the LEDs should be somewhat passed via the platform_data.
720 * for now, just whack the register and make the LEDs happy
721 *
722 * Note: AFAIK, rev B1 needs the same treatement but I'll let
723 * somebody else test it.
724 */
725 writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
726 break;
727 }
486} 728}
487 729
488/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 730/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 60e734c10458..a1d6e46ab035 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd)
25 */ 25 */
26 orion5x_setbits(RSTOUTn_MASK, (1 << 2)); 26 orion5x_setbits(RSTOUTn_MASK, (1 << 2));
27 orion5x_setbits(CPU_SOFT_RESET, 1); 27 orion5x_setbits(CPU_SOFT_RESET, 1);
28 mdelay(200);
29 orion5x_clrbits(CPU_SOFT_RESET, 1);
28} 30}
29 31
30 32
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 161fc2d61207..0f3130599770 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -35,7 +35,7 @@ static int cmx2xx_it8152_irq_gpio;
35 * This is really ugly and we need a better way of specifying 35 * This is really ugly and we need a better way of specifying
36 * DMA-capable regions of memory. 36 * DMA-capable regions of memory.
37 */ 37 */
38void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size, 38void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
39 unsigned long *zhole_size) 39 unsigned long *zhole_size)
40{ 40{
41 unsigned int sz = SZ_64M >> PAGE_SHIFT; 41 unsigned int sz = SZ_64M >> PAGE_SHIFT;
@@ -46,7 +46,7 @@ void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size,
46 /* 46 /*
47 * Only adjust if > 64M on current system 47 * Only adjust if > 64M on current system
48 */ 48 */
49 if (node || (zone_size[0] <= sz)) 49 if (zone_size[0] <= sz)
50 return; 50 return;
51 51
52 zone_size[1] = zone_size[0] - sz; 52 zone_size[1] = zone_size[0] - sz;
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 51ffa6afb675..461ba4080155 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -715,7 +715,6 @@ static void __init fixup_corgi(struct machine_desc *desc,
715 sharpsl_save_param(); 715 sharpsl_save_param();
716 mi->nr_banks=1; 716 mi->nr_banks=1;
717 mi->bank[0].start = 0xa0000000; 717 mi->bank[0].start = 0xa0000000;
718 mi->bank[0].node = 0;
719 if (machine_is_corgi()) 718 if (machine_is_corgi())
720 mi->bank[0].size = (32*1024*1024); 719 mi->bank[0].size = (32*1024*1024);
721 else 720 else
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 96ed13081639..a0ab3082a000 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -34,7 +34,6 @@ void __init eseries_fixup(struct machine_desc *desc,
34{ 34{
35 mi->nr_banks=1; 35 mi->nr_banks=1;
36 mi->bank[0].start = 0xa0000000; 36 mi->bank[0].start = 0xa0000000;
37 mi->bank[0].node = 0;
38 if (machine_is_e800()) 37 if (machine_is_e800())
39 mi->bank[0].size = (128*1024*1024); 38 mi->bank[0].size = (128*1024*1024);
40 else 39 else
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 890fb90a672f..c6305c5b8a72 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -26,8 +26,7 @@ extern unsigned int get_clk_frequency_khz(int info);
26 26
27#define SET_BANK(__nr,__start,__size) \ 27#define SET_BANK(__nr,__start,__size) \
28 mi->bank[__nr].start = (__start), \ 28 mi->bank[__nr].start = (__start), \
29 mi->bank[__nr].size = (__size), \ 29 mi->bank[__nr].size = (__size)
30 mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
31 30
32#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) 31#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
33 32
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index f626730ee42e..92361a66b223 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -17,24 +17,11 @@
17 */ 17 */
18#define PHYS_OFFSET UL(0xa0000000) 18#define PHYS_OFFSET UL(0xa0000000)
19 19
20/*
21 * The nodes are matched with the physical SDRAM banks as follows:
22 *
23 * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff
24 * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
25 * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
26 * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
27 *
28 * This needs a node mem size of 26 bits.
29 */
30#define NODE_MEM_SIZE_BITS 26
31
32#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 20#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
33void cmx2xx_pci_adjust_zones(int node, unsigned long *size, 21void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
34 unsigned long *holes);
35 22
36#define arch_adjust_zones(node, size, holes) \ 23#define arch_adjust_zones(size, holes) \
37 cmx2xx_pci_adjust_zones(node, size, holes) 24 cmx2xx_pci_adjust_zones(size, holes)
38 25
39#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) 26#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
40#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) 27#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5305a3993e69..5e92d84fe50d 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -21,6 +21,7 @@
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/gpio_keys.h> 22#include <linux/gpio_keys.h>
23#include <linux/input.h> 23#include <linux/input.h>
24#include <linux/memblock.h>
24#include <linux/pda_power.h> 25#include <linux/pda_power.h>
25#include <linux/pwm_backlight.h> 26#include <linux/pwm_backlight.h>
26#include <linux/gpio.h> 27#include <linux/gpio.h>
@@ -396,6 +397,11 @@ static void __init palmt5_udc_init(void)
396 } 397 }
397} 398}
398 399
400static void __init palmt5_reserve(void)
401{
402 memblock_reserve(0xa0200000, 0x1000);
403}
404
399static void __init palmt5_init(void) 405static void __init palmt5_init(void)
400{ 406{
401 pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); 407 pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config));
@@ -421,6 +427,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
421 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, 427 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
422 .boot_params = 0xa0000100, 428 .boot_params = 0xa0000100,
423 .map_io = pxa_map_io, 429 .map_io = pxa_map_io,
430 .reserve = palmt5_reserve,
424 .init_irq = pxa27x_init_irq, 431 .init_irq = pxa27x_init_irq,
425 .timer = &pxa_timer, 432 .timer = &pxa_timer,
426 .init_machine = palmt5_init 433 .init_machine = palmt5_init
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index d8b4469607a1..3d0c9cc2a406 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -20,6 +20,7 @@
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/memblock.h>
23#include <linux/pda_power.h> 24#include <linux/pda_power.h>
24#include <linux/pwm_backlight.h> 25#include <linux/pwm_backlight.h>
25#include <linux/gpio.h> 26#include <linux/gpio.h>
@@ -633,6 +634,12 @@ static void __init treo_lcd_power_init(void)
633 treo_lcd_screen.pxafb_lcd_power = treo_lcd_power; 634 treo_lcd_screen.pxafb_lcd_power = treo_lcd_power;
634} 635}
635 636
637static void __init treo_reserve(void)
638{
639 memblock_reserve(0xa0000000, 0x1000);
640 memblock_reserve(0xa2000000, 0x1000);
641}
642
636static void __init treo_init(void) 643static void __init treo_init(void)
637{ 644{
638 pxa_set_ffuart_info(NULL); 645 pxa_set_ffuart_info(NULL);
@@ -668,6 +675,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
668 .io_pg_offst = io_p2v(0x40000000), 675 .io_pg_offst = io_p2v(0x40000000),
669 .boot_params = 0xa0000100, 676 .boot_params = 0xa0000100,
670 .map_io = pxa_map_io, 677 .map_io = pxa_map_io,
678 .reserve = treo_reserve,
671 .init_irq = pxa27x_init_irq, 679 .init_irq = pxa27x_init_irq,
672 .timer = &pxa_timer, 680 .timer = &pxa_timer,
673 .init_machine = treo680_init, 681 .init_machine = treo680_init,
@@ -691,6 +699,7 @@ MACHINE_START(CENTRO, "Palm Centro 685")
691 .io_pg_offst = io_p2v(0x40000000), 699 .io_pg_offst = io_p2v(0x40000000),
692 .boot_params = 0xa0000100, 700 .boot_params = 0xa0000100,
693 .map_io = pxa_map_io, 701 .map_io = pxa_map_io,
702 .reserve = treo_reserve,
694 .init_irq = pxa27x_init_irq, 703 .init_irq = pxa27x_init_irq,
695 .timer = &pxa_timer, 704 .timer = &pxa_timer,
696 .init_machine = centro_init, 705 .init_machine = centro_init,
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index f4abdaafdac4..bc2758b54446 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -463,7 +463,6 @@ static void __init fixup_poodle(struct machine_desc *desc,
463 sharpsl_save_param(); 463 sharpsl_save_param();
464 mi->nr_banks=1; 464 mi->nr_banks=1;
465 mi->bank[0].start = 0xa0000000; 465 mi->bank[0].start = 0xa0000000;
466 mi->bank[0].node = 0;
467 mi->bank[0].size = (32*1024*1024); 466 mi->bank[0].size = (32*1024*1024);
468} 467}
469 468
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c1048a35f187..51756c723557 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -847,7 +847,6 @@ static void __init fixup_spitz(struct machine_desc *desc,
847 sharpsl_save_param(); 847 sharpsl_save_param();
848 mi->nr_banks = 1; 848 mi->nr_banks = 1;
849 mi->bank[0].start = 0xa0000000; 849 mi->bank[0].start = 0xa0000000;
850 mi->bank[0].node = 0;
851 mi->bank[0].size = (64*1024*1024); 850 mi->bank[0].size = (64*1024*1024);
852} 851}
853 852
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 7512b822c6ca..83cc3a18c2e9 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -948,7 +948,6 @@ static void __init fixup_tosa(struct machine_desc *desc,
948 sharpsl_save_param(); 948 sharpsl_save_param();
949 mi->nr_banks=1; 949 mi->nr_banks=1;
950 mi->bank[0].start = 0xa0000000; 950 mi->bank[0].start = 0xa0000000;
951 mi->bank[0].node = 0;
952 mi->bank[0].size = (64*1024*1024); 951 mi->bank[0].size = (64*1024*1024);
953} 952}
954 953
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 02e9fdeb8faf..2fa38df28414 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -61,12 +61,11 @@ void __iomem *gic_cpu_base_addr;
61/* 61/*
62 * Adjust the zones if there are restrictions for DMA access. 62 * Adjust the zones if there are restrictions for DMA access.
63 */ 63 */
64void __init realview_adjust_zones(int node, unsigned long *size, 64void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
65 unsigned long *hole)
66{ 65{
67 unsigned long dma_size = SZ_256M >> PAGE_SHIFT; 66 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
68 67
69 if (!machine_is_realview_pbx() || node || (size[0] <= dma_size)) 68 if (!machine_is_realview_pbx() || size[0] <= dma_size)
70 return; 69 return;
71 70
72 size[ZONE_NORMAL] = size[0] - dma_size; 71 size[ZONE_NORMAL] = size[0] - dma_size;
@@ -232,6 +231,21 @@ static unsigned int realview_mmc_status(struct device *dev)
232 struct amba_device *adev = container_of(dev, struct amba_device, dev); 231 struct amba_device *adev = container_of(dev, struct amba_device, dev);
233 u32 mask; 232 u32 mask;
234 233
234 if (machine_is_realview_pb1176()) {
235 static bool inserted = false;
236
237 /*
238 * The PB1176 does not have the status register,
239 * assume it is inserted at startup, then invert
240 * for each call so card insertion/removal will
241 * be detected anyway. This will not be called if
242 * GPIO on PL061 is active, which is the proper
243 * way to do this on the PB1176.
244 */
245 inserted = !inserted;
246 return inserted ? 0 : 1;
247 }
248
235 if (adev->res.start == REALVIEW_MMCI0_BASE) 249 if (adev->res.start == REALVIEW_MMCI0_BASE)
236 mask = 1; 250 mask = 1;
237 else 251 else
@@ -300,8 +314,13 @@ static struct clk ref24_clk = {
300 .rate = 24000000, 314 .rate = 24000000,
301}; 315};
302 316
317static struct clk dummy_apb_pclk;
318
303static struct clk_lookup lookups[] = { 319static struct clk_lookup lookups[] = {
304 { /* UART0 */ 320 { /* Bus clock */
321 .con_id = "apb_pclk",
322 .clk = &dummy_apb_pclk,
323 }, { /* UART0 */
305 .dev_id = "dev:uart0", 324 .dev_id = "dev:uart0",
306 .clk = &ref24_clk, 325 .clk = &ref24_clk,
307 }, { /* UART1 */ 326 }, { /* UART1 */
@@ -313,6 +332,12 @@ static struct clk_lookup lookups[] = {
313 }, { /* UART3 */ 332 }, { /* UART3 */
314 .dev_id = "fpga:uart3", 333 .dev_id = "fpga:uart3",
315 .clk = &ref24_clk, 334 .clk = &ref24_clk,
335 }, { /* UART3 is on the dev chip in PB1176 */
336 .dev_id = "dev:uart3",
337 .clk = &ref24_clk,
338 }, { /* UART4 only exists in PB1176 */
339 .dev_id = "fpga:uart4",
340 .clk = &ref24_clk,
316 }, { /* KMI0 */ 341 }, { /* KMI0 */
317 .dev_id = "fpga:kmi0", 342 .dev_id = "fpga:kmi0",
318 .clk = &ref24_clk, 343 .clk = &ref24_clk,
@@ -322,12 +347,15 @@ static struct clk_lookup lookups[] = {
322 }, { /* MMC0 */ 347 }, { /* MMC0 */
323 .dev_id = "fpga:mmc0", 348 .dev_id = "fpga:mmc0",
324 .clk = &ref24_clk, 349 .clk = &ref24_clk,
325 }, { /* EB:CLCD */ 350 }, { /* CLCD is in the PB1176 and EB DevChip */
326 .dev_id = "dev:clcd", 351 .dev_id = "dev:clcd",
327 .clk = &oscvco_clk, 352 .clk = &oscvco_clk,
328 }, { /* PB:CLCD */ 353 }, { /* PB:CLCD */
329 .dev_id = "issp:clcd", 354 .dev_id = "issp:clcd",
330 .clk = &oscvco_clk, 355 .clk = &oscvco_clk,
356 }, { /* SSP */
357 .dev_id = "dev:ssp0",
358 .clk = &ref24_clk,
331 } 359 }
332}; 360};
333 361
@@ -342,7 +370,7 @@ static int __init clk_init(void)
342 370
343 return 0; 371 return 0;
344} 372}
345arch_initcall(clk_init); 373core_initcall(clk_init);
346 374
347/* 375/*
348 * CLCD support. 376 * CLCD support.
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 2f5ccb298858..002ab5d8c11c 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -26,6 +26,7 @@
26/* 26/*
27 * Peripheral addresses 27 * Peripheral addresses
28 */ 28 */
29#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */
29#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */ 30#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */
30#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */ 31#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */
31#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */ 32#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 830055bb8628..5c3c625e3e04 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -40,6 +40,7 @@
40#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) 40#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
41#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) 41#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
42#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ 42#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
43#define IRQ_DC1176_SSP (IRQ_DC1176_GIC_START + 17) /* SSP port */
43#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ 44#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
44#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ 45#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
45#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ 46#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */
@@ -73,7 +74,6 @@
73#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ 74#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */
74 75
75#define IRQ_PB1176_GPIO0 -1 76#define IRQ_PB1176_GPIO0 -1
76#define IRQ_PB1176_SSP -1
77#define IRQ_PB1176_SCTL -1 77#define IRQ_PB1176_SCTL -1
78 78
79#define NR_GIC_PB1176 2 79#define NR_GIC_PB1176 2
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index 2417bbcf97fd..5dafc157b276 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -30,10 +30,9 @@
30#endif 30#endif
31 31
32#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) 32#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA)
33extern void realview_adjust_zones(int node, unsigned long *size, 33extern void realview_adjust_zones(unsigned long *size, unsigned long *hole);
34 unsigned long *hole); 34#define arch_adjust_zones(size, hole) \
35#define arch_adjust_zones(node, size, hole) \ 35 realview_adjust_zones(size, hole)
36 realview_adjust_zones(node, size, hole)
37 36
38#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) 37#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1)
39#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) 38#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 4425018fab82..991c1f8390e2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -25,6 +25,7 @@
25#include <linux/amba/bus.h> 25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h> 26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h> 27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
28#include <linux/io.h> 29#include <linux/io.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -129,6 +130,12 @@ static struct pl061_platform_data gpio2_plat_data = {
129 .irq_base = -1, 130 .irq_base = -1,
130}; 131};
131 132
133static struct pl022_ssp_controller ssp0_plat_data = {
134 .bus_id = 0,
135 .enable_dma = 0,
136 .num_chipselect = 1,
137};
138
132/* 139/*
133 * RealView EB AMBA devices 140 * RealView EB AMBA devices
134 */ 141 */
@@ -213,7 +220,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
213AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL); 220AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
214AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL); 221AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
215AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL); 222AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
216AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, NULL); 223AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data);
217 224
218static struct amba_device *amba_devs[] __initdata = { 225static struct amba_device *amba_devs[] __initdata = {
219 &dmac_device, 226 &dmac_device,
@@ -324,6 +331,26 @@ static struct platform_device pmu_device = {
324 .resource = pmu_resources, 331 .resource = pmu_resources,
325}; 332};
326 333
334static struct resource char_lcd_resources[] = {
335 {
336 .start = REALVIEW_CHAR_LCD_BASE,
337 .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
338 .flags = IORESOURCE_MEM,
339 },
340 {
341 .start = IRQ_EB_CHARLCD,
342 .end = IRQ_EB_CHARLCD,
343 .flags = IORESOURCE_IRQ,
344 },
345};
346
347static struct platform_device char_lcd_device = {
348 .name = "arm-charlcd",
349 .id = -1,
350 .num_resources = ARRAY_SIZE(char_lcd_resources),
351 .resource = char_lcd_resources,
352};
353
327static void __init gic_init_irq(void) 354static void __init gic_init_irq(void)
328{ 355{
329 if (core_tile_eb11mp() || core_tile_a9mp()) { 356 if (core_tile_eb11mp() || core_tile_a9mp()) {
@@ -442,6 +469,7 @@ static void __init realview_eb_init(void)
442 469
443 realview_flash_register(&realview_eb_flash_resource, 1); 470 realview_flash_register(&realview_eb_flash_resource, 1);
444 platform_device_register(&realview_i2c_device); 471 platform_device_register(&realview_i2c_device);
472 platform_device_register(&char_lcd_device);
445 eth_device_register(); 473 eth_device_register();
446 realview_usb_register(realview_eb_isp1761_resources); 474 realview_usb_register(realview_eb_isp1761_resources);
447 475
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 099a1f125cf8..d2be12eb829e 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -25,6 +25,7 @@
25#include <linux/amba/bus.h> 25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h> 26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h> 27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
28#include <linux/io.h> 29#include <linux/io.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -123,6 +124,12 @@ static struct pl061_platform_data gpio2_plat_data = {
123 .irq_base = -1, 124 .irq_base = -1,
124}; 125};
125 126
127static struct pl022_ssp_controller ssp0_plat_data = {
128 .bus_id = 0,
129 .enable_dma = 0,
130 .num_chipselect = 1,
131};
132
126/* 133/*
127 * RealView PB1176 AMBA devices 134 * RealView PB1176 AMBA devices
128 */ 135 */
@@ -144,8 +151,6 @@ static struct pl061_platform_data gpio2_plat_data = {
144#define MPMC_DMA { 0, 0 } 151#define MPMC_DMA { 0, 0 }
145#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } 152#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
146#define PB1176_CLCD_DMA { 0, 0 } 153#define PB1176_CLCD_DMA { 0, 0 }
147#define DMAC_IRQ { IRQ_PB1176_DMAC, NO_IRQ }
148#define DMAC_DMA { 0, 0 }
149#define SCTL_IRQ { NO_IRQ, NO_IRQ } 154#define SCTL_IRQ { NO_IRQ, NO_IRQ }
150#define SCTL_DMA { 0, 0 } 155#define SCTL_DMA { 0, 0 }
151#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } 156#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ }
@@ -166,7 +171,9 @@ static struct pl061_platform_data gpio2_plat_data = {
166#define PB1176_UART2_DMA { 11, 10 } 171#define PB1176_UART2_DMA { 11, 10 }
167#define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } 172#define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ }
168#define PB1176_UART3_DMA { 0x86, 0x87 } 173#define PB1176_UART3_DMA { 0x86, 0x87 }
169#define PB1176_SSP_IRQ { IRQ_PB1176_SSP, NO_IRQ } 174#define PB1176_UART4_IRQ { IRQ_PB1176_UART4, NO_IRQ }
175#define PB1176_UART4_DMA { 0, 0 }
176#define PB1176_SSP_IRQ { IRQ_DC1176_SSP, NO_IRQ }
170#define PB1176_SSP_DMA { 9, 8 } 177#define PB1176_SSP_DMA { 9, 8 }
171 178
172/* FPGA Primecells */ 179/* FPGA Primecells */
@@ -174,7 +181,7 @@ AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
174AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); 181AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
175AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); 182AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
176AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); 183AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
177AMBA_DEVICE(uart3, "fpga:uart3", PB1176_UART3, NULL); 184AMBA_DEVICE(uart4, "fpga:uart4", PB1176_UART4, NULL);
178 185
179/* DevChip Primecells */ 186/* DevChip Primecells */
180AMBA_DEVICE(smc, "dev:smc", PB1176_SMC, NULL); 187AMBA_DEVICE(smc, "dev:smc", PB1176_SMC, NULL);
@@ -188,18 +195,16 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
188AMBA_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL); 195AMBA_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL);
189AMBA_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL); 196AMBA_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL);
190AMBA_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL); 197AMBA_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL);
191AMBA_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, NULL); 198AMBA_DEVICE(uart3, "dev:uart3", PB1176_UART3, NULL);
192 199AMBA_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, &ssp0_plat_data);
193/* Primecells on the NEC ISSP chip */ 200AMBA_DEVICE(clcd, "dev:clcd", PB1176_CLCD, &clcd_plat_data);
194AMBA_DEVICE(clcd, "issp:clcd", PB1176_CLCD, &clcd_plat_data);
195//AMBA_DEVICE(dmac, "issp:dmac", PB1176_DMAC, NULL);
196 201
197static struct amba_device *amba_devs[] __initdata = { 202static struct amba_device *amba_devs[] __initdata = {
198// &dmac_device,
199 &uart0_device, 203 &uart0_device,
200 &uart1_device, 204 &uart1_device,
201 &uart2_device, 205 &uart2_device,
202 &uart3_device, 206 &uart3_device,
207 &uart4_device,
203 &smc_device, 208 &smc_device,
204 &clcd_device, 209 &clcd_device,
205 &sctl_device, 210 &sctl_device,
@@ -276,6 +281,26 @@ static struct platform_device pmu_device = {
276 .resource = &pmu_resource, 281 .resource = &pmu_resource,
277}; 282};
278 283
284static struct resource char_lcd_resources[] = {
285 {
286 .start = REALVIEW_CHAR_LCD_BASE,
287 .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .start = IRQ_PB1176_CHARLCD,
292 .end = IRQ_PB1176_CHARLCD,
293 .flags = IORESOURCE_IRQ,
294 },
295};
296
297static struct platform_device char_lcd_device = {
298 .name = "arm-charlcd",
299 .id = -1,
300 .num_resources = ARRAY_SIZE(char_lcd_resources),
301 .resource = char_lcd_resources,
302};
303
279static void __init gic_init_irq(void) 304static void __init gic_init_irq(void)
280{ 305{
281 /* ARM1176 DevChip GIC, primary */ 306 /* ARM1176 DevChip GIC, primary */
@@ -338,6 +363,7 @@ static void __init realview_pb1176_init(void)
338 platform_device_register(&realview_i2c_device); 363 platform_device_register(&realview_i2c_device);
339 realview_usb_register(realview_pb1176_isp1761_resources); 364 realview_usb_register(realview_pb1176_isp1761_resources);
340 platform_device_register(&pmu_device); 365 platform_device_register(&pmu_device);
366 platform_device_register(&char_lcd_device);
341 367
342 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 368 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
343 struct amba_device *d = amba_devs[i]; 369 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 0e07a5ccb75f..d591bc00b86e 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -25,6 +25,7 @@
25#include <linux/amba/bus.h> 25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h> 26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h> 27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
28#include <linux/io.h> 29#include <linux/io.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -124,6 +125,12 @@ static struct pl061_platform_data gpio2_plat_data = {
124 .irq_base = -1, 125 .irq_base = -1,
125}; 126};
126 127
128static struct pl022_ssp_controller ssp0_plat_data = {
129 .bus_id = 0,
130 .enable_dma = 0,
131 .num_chipselect = 1,
132};
133
127/* 134/*
128 * RealView PB11MPCore AMBA devices 135 * RealView PB11MPCore AMBA devices
129 */ 136 */
@@ -190,7 +197,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
190AMBA_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL); 197AMBA_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL);
191AMBA_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL); 198AMBA_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL);
192AMBA_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL); 199AMBA_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL);
193AMBA_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, NULL); 200AMBA_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data);
194 201
195/* Primecells on the NEC ISSP chip */ 202/* Primecells on the NEC ISSP chip */
196AMBA_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data); 203AMBA_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index ac2f06f1ca50..6c37621217bc 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -25,6 +25,7 @@
25#include <linux/amba/bus.h> 25#include <linux/amba/bus.h>
26#include <linux/amba/pl061.h> 26#include <linux/amba/pl061.h>
27#include <linux/amba/mmci.h> 27#include <linux/amba/mmci.h>
28#include <linux/amba/pl022.h>
28#include <linux/io.h> 29#include <linux/io.h>
29 30
30#include <asm/irq.h> 31#include <asm/irq.h>
@@ -114,6 +115,12 @@ static struct pl061_platform_data gpio2_plat_data = {
114 .irq_base = -1, 115 .irq_base = -1,
115}; 116};
116 117
118static struct pl022_ssp_controller ssp0_plat_data = {
119 .bus_id = 0,
120 .enable_dma = 0,
121 .num_chipselect = 1,
122};
123
117/* 124/*
118 * RealView PBA8Core AMBA devices 125 * RealView PBA8Core AMBA devices
119 */ 126 */
@@ -180,7 +187,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
180AMBA_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL); 187AMBA_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL);
181AMBA_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL); 188AMBA_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL);
182AMBA_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL); 189AMBA_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL);
183AMBA_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, NULL); 190AMBA_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, &ssp0_plat_data);
184 191
185/* Primecells on the NEC ISSP chip */ 192/* Primecells on the NEC ISSP chip */
186AMBA_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data); 193AMBA_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 08fd683adc4c..9428eff0b116 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -24,6 +24,7 @@
24#include <linux/amba/bus.h> 24#include <linux/amba/bus.h>
25#include <linux/amba/pl061.h> 25#include <linux/amba/pl061.h>
26#include <linux/amba/mmci.h> 26#include <linux/amba/mmci.h>
27#include <linux/amba/pl022.h>
27#include <linux/io.h> 28#include <linux/io.h>
28 29
29#include <asm/irq.h> 30#include <asm/irq.h>
@@ -136,6 +137,12 @@ static struct pl061_platform_data gpio2_plat_data = {
136 .irq_base = -1, 137 .irq_base = -1,
137}; 138};
138 139
140static struct pl022_ssp_controller ssp0_plat_data = {
141 .bus_id = 0,
142 .enable_dma = 0,
143 .num_chipselect = 1,
144};
145
139/* 146/*
140 * RealView PBXCore AMBA devices 147 * RealView PBXCore AMBA devices
141 */ 148 */
@@ -202,7 +209,7 @@ AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
202AMBA_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL); 209AMBA_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL);
203AMBA_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL); 210AMBA_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL);
204AMBA_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL); 211AMBA_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL);
205AMBA_DEVICE(ssp0, "dev:ssp0", PBX_SSP, NULL); 212AMBA_DEVICE(ssp0, "dev:ssp0", PBX_SSP, &ssp0_plat_data);
206 213
207/* Primecells on the NEC ISSP chip */ 214/* Primecells on the NEC ISSP chip */
208AMBA_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data); 215AMBA_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data);
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 779b45b3f80f..3ba3bab139d0 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -15,6 +15,7 @@
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/memblock.h>
18#include <linux/timer.h> 19#include <linux/timer.h>
19#include <linux/init.h> 20#include <linux/init.h>
20#include <linux/sysdev.h> 21#include <linux/sysdev.h>
@@ -304,6 +305,13 @@ static void __init h1940_map_io(void)
304 s3c_pm_init(); 305 s3c_pm_init();
305} 306}
306 307
308/* H1940 and RX3715 need to reserve this for suspend */
309static void __init h1940_reserve(void)
310{
311 memblock_reserve(0x30003000, 0x1000);
312 memblock_reserve(0x30081000, 0x1000);
313}
314
307static void __init h1940_init_irq(void) 315static void __init h1940_init_irq(void)
308{ 316{
309 s3c24xx_init_irq(); 317 s3c24xx_init_irq();
@@ -346,6 +354,7 @@ MACHINE_START(H1940, "IPAQ-H1940")
346 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 354 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
347 .boot_params = S3C2410_SDRAM_PA + 0x100, 355 .boot_params = S3C2410_SDRAM_PA + 0x100,
348 .map_io = h1940_map_io, 356 .map_io = h1940_map_io,
357 .reserve = h1940_reserve,
349 .init_irq = h1940_init_irq, 358 .init_irq = h1940_init_irq,
350 .init_machine = h1940_init, 359 .init_machine = h1940_init,
351 .timer = &s3c24xx_timer, 360 .timer = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index ba93a356a839..054c9f92232a 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -119,7 +119,6 @@ static void __init smdk2413_fixup(struct machine_desc *desc,
119 mi->nr_banks=1; 119 mi->nr_banks=1;
120 mi->bank[0].start = 0x30000000; 120 mi->bank[0].start = 0x30000000;
121 mi->bank[0].size = SZ_64M; 121 mi->bank[0].size = SZ_64M;
122 mi->bank[0].node = 0;
123 } 122 }
124} 123}
125 124
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 3ca9265b6997..f291ac25d312 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -137,7 +137,6 @@ static void __init vstms_fixup(struct machine_desc *desc,
137 mi->nr_banks=1; 137 mi->nr_banks=1;
138 mi->bank[0].start = 0x30000000; 138 mi->bank[0].start = 0x30000000;
139 mi->bank[0].size = SZ_64M; 139 mi->bank[0].size = SZ_64M;
140 mi->bank[0].node = 0;
141 } 140 }
142} 141}
143 142
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 8603b577a24b..142d1f921176 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -15,6 +15,7 @@
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/memblock.h>
18#include <linux/delay.h> 19#include <linux/delay.h>
19#include <linux/timer.h> 20#include <linux/timer.h>
20#include <linux/init.h> 21#include <linux/init.h>
@@ -570,12 +571,20 @@ static void __init rx1950_init_machine(void)
570 platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices)); 571 platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
571} 572}
572 573
574/* H1940 and RX3715 need to reserve this for suspend */
575static void __init rx1950_reserve(void)
576{
577 memblock_reserve(0x30003000, 0x1000);
578 memblock_reserve(0x30081000, 0x1000);
579}
580
573MACHINE_START(RX1950, "HP iPAQ RX1950") 581MACHINE_START(RX1950, "HP iPAQ RX1950")
574 /* Maintainers: Vasily Khoruzhick */ 582 /* Maintainers: Vasily Khoruzhick */
575 .phys_io = S3C2410_PA_UART, 583 .phys_io = S3C2410_PA_UART,
576 .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc, 584 .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
577 .boot_params = S3C2410_SDRAM_PA + 0x100, 585 .boot_params = S3C2410_SDRAM_PA + 0x100,
578 .map_io = rx1950_map_io, 586 .map_io = rx1950_map_io,
587 .reserve = rx1950_reserve,
579 .init_irq = s3c24xx_init_irq, 588 .init_irq = s3c24xx_init_irq,
580 .init_machine = rx1950_init_machine, 589 .init_machine = rx1950_init_machine,
581 .timer = &s3c24xx_timer, 590 .timer = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index d2946de3f365..6bb44f75a9ce 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -15,6 +15,7 @@
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/memblock.h>
18#include <linux/timer.h> 19#include <linux/timer.h>
19#include <linux/init.h> 20#include <linux/init.h>
20#include <linux/tty.h> 21#include <linux/tty.h>
@@ -191,6 +192,13 @@ static void __init rx3715_map_io(void)
191 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); 192 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
192} 193}
193 194
195/* H1940 and RX3715 need to reserve this for suspend */
196static void __init rx3715_reserve(void)
197{
198 memblock_reserve(0x30003000, 0x1000);
199 memblock_reserve(0x30081000, 0x1000);
200}
201
194static void __init rx3715_init_irq(void) 202static void __init rx3715_init_irq(void)
195{ 203{
196 s3c24xx_init_irq(); 204 s3c24xx_init_irq();
@@ -214,6 +222,7 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
214 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 222 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
215 .boot_params = S3C2410_SDRAM_PA + 0x100, 223 .boot_params = S3C2410_SDRAM_PA + 0x100,
216 .map_io = rx3715_map_io, 224 .map_io = rx3715_map_io,
225 .reserve = rx3715_reserve,
217 .init_irq = rx3715_init_irq, 226 .init_irq = rx3715_init_irq,
218 .init_machine = rx3715_init_machine, 227 .init_machine = rx3715_init_machine,
219 .timer = &s3c24xx_timer, 228 .timer = &s3c24xx_timer,
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index ec03f187c52b..b7a9a601c2d1 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -13,8 +13,7 @@ extern void __init sa1100_init_gpio(void);
13 13
14#define SET_BANK(__nr,__start,__size) \ 14#define SET_BANK(__nr,__start,__size) \
15 mi->bank[__nr].start = (__start), \ 15 mi->bank[__nr].start = (__start), \
16 mi->bank[__nr].size = (__size), \ 16 mi->bank[__nr].size = (__size)
17 mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
18 17
19extern void (*sa1100fb_backlight_power)(int on); 18extern void (*sa1100fb_backlight_power)(int on);
20extern void (*sa1100fb_lcd_power)(int on); 19extern void (*sa1100fb_lcd_power)(int on);
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index d5277f9bee77..128a1dfa96b9 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -17,10 +17,10 @@
17#ifndef __ASSEMBLY__ 17#ifndef __ASSEMBLY__
18 18
19#ifdef CONFIG_SA1111 19#ifdef CONFIG_SA1111
20void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); 20void sa1111_adjust_zones(unsigned long *size, unsigned long *holes);
21 21
22#define arch_adjust_zones(node, size, holes) \ 22#define arch_adjust_zones(size, holes) \
23 sa1111_adjust_zones(node, size, holes) 23 sa1111_adjust_zones(size, holes)
24 24
25#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) 25#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1)
26#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M) 26#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M)
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index 3053e5b7f168..d9c4812f1c31 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -19,9 +19,8 @@
19 19
20#ifndef __ASSEMBLY__ 20#ifndef __ASSEMBLY__
21 21
22static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) 22static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size)
23{ 23{
24 if (node != 0) return;
25 /* Only the first 4 MB (=1024 Pages) are usable for DMA */ 24 /* Only the first 4 MB (=1024 Pages) are usable for DMA */
26 /* See dev / -> .properties in OpenFirmware. */ 25 /* See dev / -> .properties in OpenFirmware. */
27 zone_size[1] = zone_size[0] - 1024; 26 zone_size[1] = zone_size[0] - 1024;
@@ -30,8 +29,8 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig
30 zhole_size[0] = 0; 29 zhole_size[0] = 0;
31} 30}
32 31
33#define arch_adjust_zones(node, size, holes) \ 32#define arch_adjust_zones(size, holes) \
34 __arch_adjust_zones(node, size, holes) 33 __arch_adjust_zones(size, holes)
35 34
36#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) 35#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1)
37#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M) 36#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f2b88c5fe142..4c704b4e8b34 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -70,6 +70,18 @@ endmenu
70 70
71menu "Timer and clock configuration" 71menu "Timer and clock configuration"
72 72
73config SHMOBILE_TIMER_HZ
74 int "Kernel HZ (jiffies per second)"
75 range 32 1024
76 default "128"
77 help
78 Allows the configuration of the timer frequency. It is customary
79 to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
80 case of low timer frequencies other values may be more suitable.
81 SH-Mobile systems using a 32768 Hz RCLK for clock events may want
82 to select a HZ value such as 128 that can evenly divide RCLK.
83 A HZ value that does not divide evenly may cause timer drift.
84
73config SH_TIMER_CMT 85config SH_TIMER_CMT
74 bool "CMT timer driver" 86 bool "CMT timer driver"
75 default y 87 default y
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 5179b72e1ee3..132256bb8c81 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -2,7 +2,6 @@
2#define __ASM_MACH_IRQS_H 2#define __ASM_MACH_IRQS_H
3 3
4#define NR_IRQS 512 4#define NR_IRQS 512
5#define NR_IRQS_LEGACY 8
6 5
7#define evt2irq(evt) (((evt) >> 5) - 16) 6#define evt2irq(evt) (((evt) >> 5) - 16)
8#define irq2evt(irq) (((irq) + 16) << 5) 7#define irq2evt(irq) (((irq) + 16) << 5)
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 39f6ccf22294..18febf92f20a 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -341,8 +341,11 @@ static struct clk gpio_clk = {
341 .recalc = &follow_parent, 341 .recalc = &follow_parent,
342}; 342};
343 343
344static struct clk dummy_apb_pclk;
345
344/* array of all spear 3xx clock lookups */ 346/* array of all spear 3xx clock lookups */
345static struct clk_lookup spear_clk_lookups[] = { 347static struct clk_lookup spear_clk_lookups[] = {
348 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
346 /* root clks */ 349 /* root clks */
347 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, 350 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
348 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, 351 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 13e27c769685..36ff056b7321 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -428,8 +428,11 @@ static struct clk gpio2_clk = {
428 .recalc = &follow_parent, 428 .recalc = &follow_parent,
429}; 429};
430 430
431static struct clk dummy_apb_pclk;
432
431/* array of all spear 6xx clock lookups */ 433/* array of all spear 6xx clock lookups */
432static struct clk_lookup spear_clk_lookups[] = { 434static struct clk_lookup spear_clk_lookups[] = {
435 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
433 /* root clks */ 436 /* root clks */
434 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, 437 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
435 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, 438 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 5af71d5ba665..5d12d547789e 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -1212,6 +1212,8 @@ static struct clk ppm_clk = {
1212}; 1212};
1213#endif 1213#endif
1214 1214
1215static struct clk dummy_apb_pclk;
1216
1215#define DEF_LOOKUP(devid, clkref) \ 1217#define DEF_LOOKUP(devid, clkref) \
1216 { \ 1218 { \
1217 .dev_id = devid, \ 1219 .dev_id = devid, \
@@ -1223,6 +1225,10 @@ static struct clk ppm_clk = {
1223 * look up through clockdevice. 1225 * look up through clockdevice.
1224 */ 1226 */
1225static struct clk_lookup lookups[] = { 1227static struct clk_lookup lookups[] = {
1228 {
1229 .con_id = "apb_pclk",
1230 .clk = &dummy_apb_pclk,
1231 },
1226 /* Connected directly to the AMBA bus */ 1232 /* Connected directly to the AMBA bus */
1227 DEF_LOOKUP("amba", &amba_clk), 1233 DEF_LOOKUP("amba", &amba_clk),
1228 DEF_LOOKUP("cpu", &cpu_clk), 1234 DEF_LOOKUP("cpu", &cpu_clk),
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
index ab000df7fc03..bf134bcc129d 100644
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -35,14 +35,6 @@
35#endif 35#endif
36 36
37/* 37/*
38 * TCM memory whereabouts
39 */
40#define ITCM_OFFSET 0xffff2000
41#define ITCM_END 0xffff3fff
42#define DTCM_OFFSET 0xffff4000
43#define DTCM_END 0xffff5fff
44
45/*
46 * We enable a real big DMA buffer if need be. 38 * We enable a real big DMA buffer if need be.
47 */ 39 */
48#define CONSISTENT_DMA_SIZE SZ_4M 40#define CONSISTENT_DMA_SIZE SZ_4M
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index d2a0b8847a18..bfcda9820888 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -14,6 +14,7 @@
14#include <linux/sched.h> 14#include <linux/sched.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/memblock.h>
17#include <linux/platform_device.h> 18#include <linux/platform_device.h>
18#include <linux/io.h> 19#include <linux/io.h>
19#include <mach/hardware.h> 20#include <mach/hardware.h>
@@ -22,6 +23,21 @@
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24 25
26static void __init u300_reserve(void)
27{
28 /*
29 * U300 - This platform family can share physical memory
30 * between two ARM cpus, one running Linux and the other
31 * running another OS.
32 */
33#ifdef CONFIG_MACH_U300_SINGLE_RAM
34#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
35 CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
36 memblock_reserve(PHYS_OFFSET, 0x00100000);
37#endif
38#endif
39}
40
25static void __init u300_init_machine(void) 41static void __init u300_init_machine(void)
26{ 42{
27 u300_init_devices(); 43 u300_init_devices();
@@ -49,6 +65,7 @@ MACHINE_START(U300, MACH_U300_STRING)
49 .io_pg_offst = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc, 65 .io_pg_offst = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
50 .boot_params = BOOT_PARAMS_OFFSET, 66 .boot_params = BOOT_PARAMS_OFFSET,
51 .map_io = u300_map_io, 67 .map_io = u300_map_io,
68 .reserve = u300_reserve,
52 .init_irq = u300_init_irq, 69 .init_irq = u300_init_irq,
53 .timer = &u300_timer, 70 .timer = &u300_timer,
54 .init_machine = u300_init_machine, 71 .init_machine = u300_init_machine,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index bb8d7b771817..0e8fd135a57d 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -13,19 +13,42 @@
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/gpio.h>
16#include <linux/amba/bus.h> 17#include <linux/amba/bus.h>
17#include <linux/amba/pl022.h> 18#include <linux/amba/pl022.h>
18#include <linux/spi/spi.h> 19#include <linux/spi/spi.h>
20#include <linux/mfd/ab8500.h>
19 21
20#include <asm/mach-types.h> 22#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
22 24
25#include <plat/pincfg.h>
23#include <plat/i2c.h> 26#include <plat/i2c.h>
24 27
25#include <mach/hardware.h> 28#include <mach/hardware.h>
26#include <mach/setup.h> 29#include <mach/setup.h>
27#include <mach/devices.h> 30#include <mach/devices.h>
28 31
32#include "pins-db8500.h"
33
34static pin_cfg_t mop500_pins[] = {
35 /* SSP0 */
36 GPIO143_SSP0_CLK,
37 GPIO144_SSP0_FRM,
38 GPIO145_SSP0_RXD,
39 GPIO146_SSP0_TXD,
40
41 /* I2C */
42 GPIO147_I2C0_SCL,
43 GPIO148_I2C0_SDA,
44 GPIO16_I2C1_SCL,
45 GPIO17_I2C1_SDA,
46 GPIO10_I2C2_SDA,
47 GPIO11_I2C2_SCL,
48 GPIO229_I2C3_SDA,
49 GPIO230_I2C3_SCL,
50};
51
29static void ab4500_spi_cs_control(u32 command) 52static void ab4500_spi_cs_control(u32 command)
30{ 53{
31 /* set the FRM signal, which is CS - TODO */ 54 /* set the FRM signal, which is CS - TODO */
@@ -48,15 +71,20 @@ struct pl022_config_chip ab4500_chip_info = {
48 .cs_control = ab4500_spi_cs_control, 71 .cs_control = ab4500_spi_cs_control,
49}; 72};
50 73
74static struct ab8500_platform_data ab8500_platdata = {
75 .irq_base = MOP500_AB8500_IRQ_BASE,
76};
77
51static struct spi_board_info u8500_spi_devices[] = { 78static struct spi_board_info u8500_spi_devices[] = {
52 { 79 {
53 .modalias = "ab8500", 80 .modalias = "ab8500",
54 .controller_data = &ab4500_chip_info, 81 .controller_data = &ab4500_chip_info,
82 .platform_data = &ab8500_platdata,
55 .max_speed_hz = 12000000, 83 .max_speed_hz = 12000000,
56 .bus_num = 0, 84 .bus_num = 0,
57 .chip_select = 0, 85 .chip_select = 0,
58 .mode = SPI_MODE_0, 86 .mode = SPI_MODE_0,
59 .irq = IRQ_AB4500, 87 .irq = IRQ_DB8500_AB8500,
60 }, 88 },
61}; 89};
62 90
@@ -118,6 +146,10 @@ static void __init u8500_init_machine(void)
118{ 146{
119 int i; 147 int i;
120 148
149 u8500_init_devices();
150
151 nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
152
121 u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data; 153 u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data;
122 ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data; 154 ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
123 ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data; 155 ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
@@ -133,8 +165,6 @@ static void __init u8500_init_machine(void)
133 165
134 spi_register_board_info(u8500_spi_devices, 166 spi_register_board_info(u8500_spi_devices,
135 ARRAY_SIZE(u8500_spi_devices)); 167 ARRAY_SIZE(u8500_spi_devices));
136
137 u8500_init_devices();
138} 168}
139 169
140MACHINE_START(U8500, "ST-Ericsson MOP500 platform") 170MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 0a1318fc8e2b..d8ab7f184fe4 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -453,7 +453,11 @@ static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
453static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); 453static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
454static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); 454static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
455 455
456static struct clk clk_dummy_apb_pclk;
457
456static struct clk_lookup u8500_common_clks[] = { 458static struct clk_lookup u8500_common_clks[] = {
459 CLK(dummy_apb_pclk, NULL, "apb_pclk"),
460
457 /* Peripheral Cluster #1 */ 461 /* Peripheral Cluster #1 */
458 CLK(gpio0, "gpio.0", NULL), 462 CLK(gpio0, "gpio.0", NULL),
459 CLK(gpio0, "gpio.1", NULL), 463 CLK(gpio0, "gpio.1", NULL),
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 822903421943..654fca944e65 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -65,7 +65,7 @@ struct amba_device u8500_ssp0_device = {
65 .end = U8500_SSP0_BASE + SZ_4K - 1, 65 .end = U8500_SSP0_BASE + SZ_4K - 1,
66 .flags = IORESOURCE_MEM, 66 .flags = IORESOURCE_MEM,
67 }, 67 },
68 .irq = {IRQ_SSP0, NO_IRQ }, 68 .irq = {IRQ_DB8500_SSP0, NO_IRQ },
69 /* ST-Ericsson modified id */ 69 /* ST-Ericsson modified id */
70 .periphid = SSP_PER_ID, 70 .periphid = SSP_PER_ID,
71}; 71};
@@ -77,8 +77,8 @@ static struct resource u8500_i2c0_resources[] = {
77 .flags = IORESOURCE_MEM, 77 .flags = IORESOURCE_MEM,
78 }, 78 },
79 [1] = { 79 [1] = {
80 .start = IRQ_I2C0, 80 .start = IRQ_DB8500_I2C0,
81 .end = IRQ_I2C0, 81 .end = IRQ_DB8500_I2C0,
82 .flags = IORESOURCE_IRQ, 82 .flags = IORESOURCE_IRQ,
83 } 83 }
84}; 84};
@@ -97,8 +97,8 @@ static struct resource u8500_i2c4_resources[] = {
97 .flags = IORESOURCE_MEM, 97 .flags = IORESOURCE_MEM,
98 }, 98 },
99 [1] = { 99 [1] = {
100 .start = IRQ_I2C4, 100 .start = IRQ_DB8500_I2C4,
101 .end = IRQ_I2C4, 101 .end = IRQ_DB8500_I2C4,
102 .flags = IORESOURCE_IRQ, 102 .flags = IORESOURCE_IRQ,
103 } 103 }
104}; 104};
@@ -130,8 +130,8 @@ static struct resource dma40_resources[] = {
130 .name = "lcla", 130 .name = "lcla",
131 }, 131 },
132 [3] = { 132 [3] = {
133 .start = IRQ_DMA, 133 .start = IRQ_DB8500_DMA,
134 .end = IRQ_DMA, 134 .end = IRQ_DB8500_DMA,
135 .flags = IORESOURCE_IRQ} 135 .flags = IORESOURCE_IRQ}
136}; 136};
137 137
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
new file mode 100644
index 000000000000..cca4f705601e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_BOARD_MOP500_H
9#define __MACH_IRQS_BOARD_MOP500_H
10
11#define AB8500_NR_IRQS 104
12
13#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START
14#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \
15 + AB8500_NR_IRQS)
16#define MOP500_IRQ_END MOP500_AB8500_IRQ_END
17
18#if MOP500_IRQ_END > IRQ_BOARD_END
19#undef IRQ_BOARD_END
20#define IRQ_BOARD_END MOP500_IRQ_END
21#endif
22
23#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
new file mode 100644
index 000000000000..6fbfe5e2065a
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB5500_H
9#define __MACH_IRQS_DB5500_H
10
11#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7)
14#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16)
23#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29)
36#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30)
37#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31)
38#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33)
39#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34)
40#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35)
41#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36)
42#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37)
43#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38)
44#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39)
45#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40)
46#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44)
50#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50)
55#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52)
56#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53)
57#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55)
58#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56)
59#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57)
60#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59)
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
65#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
66#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
67#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108)
68#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109)
69#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110)
70#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112)
71#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113)
72#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114)
73#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115)
74#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116)
75#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118)
76#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119)
77#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120)
78#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121)
79#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122)
80#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123)
81#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124)
82#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
83#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
84
85#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
new file mode 100644
index 000000000000..8b5d9f0a1633
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB8500_H
9#define __MACH_IRQS_DB8500_H
10
11#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7)
14#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16)
23#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29)
36#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31)
37#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
38#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
39#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
40#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
41#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36)
42#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37)
43#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38)
44#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39)
45#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40)
46#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44)
50#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49)
55#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50)
56#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51)
57#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52)
58#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53)
59#define IRQ_DB8500_KB (IRQ_SHPI_START + 54)
60#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55)
61#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56)
62#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57)
63#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59)
64#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60)
65#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61)
66#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62)
67#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63)
68#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96)
69#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97)
70#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98)
71#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99)
72#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100)
73#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104)
74#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105)
75#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106)
76#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107)
77#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108)
78#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109)
79#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110)
80#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112)
81#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113)
82#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114)
83#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115)
84#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116)
85#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118)
86#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119)
87#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120)
88#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121)
89#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122)
90#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123)
91#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124)
92#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125)
93#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126)
94#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127)
95
96#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 7970684b1d09..10385bdc2b77 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,7 +10,8 @@
10#ifndef ASM_ARCH_IRQS_H 10#ifndef ASM_ARCH_IRQS_H
11#define ASM_ARCH_IRQS_H 11#define ASM_ARCH_IRQS_H
12 12
13#include <mach/hardware.h> 13#include <mach/irqs-db5500.h>
14#include <mach/irqs-db8500.h>
14 15
15#define IRQ_LOCALTIMER 29 16#define IRQ_LOCALTIMER 29
16#define IRQ_LOCALWDOG 30 17#define IRQ_LOCALWDOG 30
@@ -67,12 +68,21 @@
67/* There are 128 shared peripheral interrupts assigned to 68/* There are 128 shared peripheral interrupts assigned to
68 * INTID[160:32]. The first 32 interrupts are reserved. 69 * INTID[160:32]. The first 32 interrupts are reserved.
69 */ 70 */
70#define U8500_SOC_NR_IRQS 161 71#define DBX500_NR_INTERNAL_IRQS 161
71 72
72/* After chip-specific IRQ numbers we have the GPIO ones */ 73/* After chip-specific IRQ numbers we have the GPIO ones */
73#define NOMADIK_NR_GPIO 288 74#define NOMADIK_NR_GPIO 288
74#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS) 75#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS)
75#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS) 76#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS)
76#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) 77#define IRQ_BOARD_START NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
77 78
78#endif /*ASM_ARCH_IRQS_H*/ 79/* This will be overridden by board-specific irq headers */
80#define IRQ_BOARD_END IRQ_BOARD_START
81
82#ifdef CONFIG_MACH_U8500_MOP
83#include <mach/irqs-board-mop500.h>
84#endif
85
86#define NR_IRQS IRQ_BOARD_END
87
88#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
new file mode 100644
index 000000000000..9055d5d3233c
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -0,0 +1,742 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_PINS_DB8500_H
9#define __MACH_PINS_DB8500_H
10
11/*
12 * TODO: Eventually encode all non-board specific pull up/down configuration
13 * here.
14 */
15
16#define GPIO0_GPIO PIN_CFG(0, GPIO)
17#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
18#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
19#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
20
21#define GPIO1_GPIO PIN_CFG(1, GPIO)
22#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
23#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
24#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
25
26#define GPIO2_GPIO PIN_CFG(2, GPIO)
27#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
28#define GPIO2_NONE PIN_CFG(2, ALT_B)
29#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
30
31#define GPIO3_GPIO PIN_CFG(3, GPIO)
32#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
33#define GPIO3_NONE PIN_CFG(3, ALT_B)
34#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
35
36#define GPIO4_GPIO PIN_CFG(4, GPIO)
37#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
38#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP)
39#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
40
41#define GPIO5_GPIO PIN_CFG(5, GPIO)
42#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
43#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP)
44#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
45
46#define GPIO6_GPIO PIN_CFG(6, GPIO)
47#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
48#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP)
49#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
50
51#define GPIO7_GPIO PIN_CFG(7, GPIO)
52#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
53#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP)
54#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
55
56#define GPIO8_GPIO PIN_CFG(8, GPIO)
57#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP)
58#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP)
59
60#define GPIO9_GPIO PIN_CFG(9, GPIO)
61#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP)
62#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP)
63
64#define GPIO10_GPIO PIN_CFG(10, GPIO)
65#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP)
66#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP)
67#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
68
69#define GPIO11_GPIO PIN_CFG(11, GPIO)
70#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP)
71#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP)
72#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
73
74#define GPIO12_GPIO PIN_CFG(12, GPIO)
75#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
76#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
77
78#define GPIO13_GPIO PIN_CFG(13, GPIO)
79#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
80
81#define GPIO14_GPIO PIN_CFG(14, GPIO)
82#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
83
84#define GPIO15_GPIO PIN_CFG(15, GPIO)
85#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
86#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
87
88#define GPIO16_GPIO PIN_CFG(16, GPIO)
89#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
90#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP)
91#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
92
93#define GPIO17_GPIO PIN_CFG(17, GPIO)
94#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
95#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP)
96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
97
98#define GPIO18_GPIO PIN_CFG(18, GPIO)
99#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A)
100#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
101#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
102
103#define GPIO19_GPIO PIN_CFG(19, GPIO)
104#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A)
105#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
106#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
107
108#define GPIO20_GPIO PIN_CFG(20, GPIO)
109#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A)
110#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
111#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
112
113#define GPIO21_GPIO PIN_CFG(21, GPIO)
114#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A)
115#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
116#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
117
118#define GPIO22_GPIO PIN_CFG(22, GPIO)
119#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A)
120#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
121#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
122
123#define GPIO23_GPIO PIN_CFG(23, GPIO)
124#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A)
125#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
126#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
127
128#define GPIO24_GPIO PIN_CFG(24, GPIO)
129#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A)
130#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
131#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
132
133#define GPIO25_GPIO PIN_CFG(25, GPIO)
134#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A)
135#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
136#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
137
138#define GPIO26_GPIO PIN_CFG(26, GPIO)
139#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A)
140#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
141#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
142
143#define GPIO27_GPIO PIN_CFG(27, GPIO)
144#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A)
145#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
146#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
147
148#define GPIO28_GPIO PIN_CFG(28, GPIO)
149#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A)
150#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
151#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
152
153#define GPIO29_GPIO PIN_CFG(29, GPIO)
154#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
155#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
156#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
157
158#define GPIO30_GPIO PIN_CFG(30, GPIO)
159#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
160#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
161#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
162
163#define GPIO31_GPIO PIN_CFG(31, GPIO)
164#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
165#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
166#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
167
168#define GPIO32_GPIO PIN_CFG(32, GPIO)
169#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
170#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
171#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
172
173#define GPIO33_GPIO PIN_CFG(33, GPIO)
174#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
175#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
176#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
177
178#define GPIO34_GPIO PIN_CFG(34, GPIO)
179#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
180#define GPIO34_NONE PIN_CFG(34, ALT_B)
181#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
182
183#define GPIO35_GPIO PIN_CFG(35, GPIO)
184#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
185#define GPIO35_NONE PIN_CFG(35, ALT_B)
186#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
187
188#define GPIO36_GPIO PIN_CFG(36, GPIO)
189#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
190#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
191#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
192
193#define GPIO64_GPIO PIN_CFG(64, GPIO)
194#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
195#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
196#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
197
198#define GPIO65_GPIO PIN_CFG(65, GPIO)
199#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
200#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
201#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
202
203#define GPIO66_GPIO PIN_CFG(66, GPIO)
204#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
205#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
206#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
207
208#define GPIO67_GPIO PIN_CFG(67, GPIO)
209#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
210#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
211#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
212
213#define GPIO68_GPIO PIN_CFG(68, GPIO)
214#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
215#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
216#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
217
218#define GPIO69_GPIO PIN_CFG(69, GPIO)
219#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
220#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
221#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
222
223#define GPIO70_GPIO PIN_CFG(70, GPIO)
224#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
225#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
226#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
227
228#define GPIO71_GPIO PIN_CFG(71, GPIO)
229#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
230#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
231#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
232
233#define GPIO72_GPIO PIN_CFG(72, GPIO)
234#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
235#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
236#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
237
238#define GPIO73_GPIO PIN_CFG(73, GPIO)
239#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
240#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
241#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
242
243#define GPIO74_GPIO PIN_CFG(74, GPIO)
244#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
245#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
246#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
247
248#define GPIO75_GPIO PIN_CFG(75, GPIO)
249#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
250#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
251#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
252
253#define GPIO76_GPIO PIN_CFG(76, GPIO)
254#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
255#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
256#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
257
258#define GPIO77_GPIO PIN_CFG(77, GPIO)
259#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
260#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
261#define GPIO77_NONE PIN_CFG(77, ALT_C)
262
263#define GPIO78_GPIO PIN_CFG(78, GPIO)
264#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
265#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
266#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
267
268#define GPIO79_GPIO PIN_CFG(79, GPIO)
269#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
270#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
271#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
272
273#define GPIO80_GPIO PIN_CFG(80, GPIO)
274#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
275#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
276#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
277
278#define GPIO81_GPIO PIN_CFG(81, GPIO)
279#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
280#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
281#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
282
283#define GPIO82_GPIO PIN_CFG(82, GPIO)
284#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
285#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
286
287#define GPIO83_GPIO PIN_CFG(83, GPIO)
288#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
289#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
290
291#define GPIO84_GPIO PIN_CFG(84, GPIO)
292#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
293#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
294
295#define GPIO85_GPIO PIN_CFG(85, GPIO)
296#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
297#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
298
299#define GPIO86_GPIO PIN_CFG(86, GPIO)
300#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
301#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
302#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
303
304#define GPIO87_GPIO PIN_CFG(87, GPIO)
305#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
306#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
307#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
308
309#define GPIO88_GPIO PIN_CFG(88, GPIO)
310#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
311#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
312#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
313
314#define GPIO89_GPIO PIN_CFG(89, GPIO)
315#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
316#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
317#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
318
319#define GPIO90_GPIO PIN_CFG(90, GPIO)
320#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
321#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
322#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
323
324#define GPIO91_GPIO PIN_CFG(91, GPIO)
325#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
326#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
327#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
328
329#define GPIO92_GPIO PIN_CFG(92, GPIO)
330#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
331#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
332#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
333
334#define GPIO93_GPIO PIN_CFG(93, GPIO)
335#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
336#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
337#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
338
339#define GPIO94_GPIO PIN_CFG(94, GPIO)
340#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
341#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
342#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
343
344#define GPIO95_GPIO PIN_CFG(95, GPIO)
345#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
346#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
347#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
348
349#define GPIO96_GPIO PIN_CFG(96, GPIO)
350#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
351#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
352#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
353
354#define GPIO97_GPIO PIN_CFG(97, GPIO)
355#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
356#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
357#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
358
359#define GPIO128_GPIO PIN_CFG(128, GPIO)
360#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A)
361#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
362
363#define GPIO129_GPIO PIN_CFG(129, GPIO)
364#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A)
365#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
366
367#define GPIO130_GPIO PIN_CFG(130, GPIO)
368#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A)
369#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
370#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
371
372#define GPIO131_GPIO PIN_CFG(131, GPIO)
373#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A)
374#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
375
376#define GPIO132_GPIO PIN_CFG(132, GPIO)
377#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A)
378#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
379
380#define GPIO133_GPIO PIN_CFG(133, GPIO)
381#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A)
382#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
383
384#define GPIO134_GPIO PIN_CFG(134, GPIO)
385#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A)
386#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
387
388#define GPIO135_GPIO PIN_CFG(135, GPIO)
389#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A)
390#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
391
392#define GPIO136_GPIO PIN_CFG(136, GPIO)
393#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A)
394#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
395
396#define GPIO137_GPIO PIN_CFG(137, GPIO)
397#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A)
398#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
399
400#define GPIO138_GPIO PIN_CFG(138, GPIO)
401#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A)
402#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
403
404#define GPIO139_GPIO PIN_CFG(139, GPIO)
405#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
406#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
407#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
408
409#define GPIO140_GPIO PIN_CFG(140, GPIO)
410#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
411#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
412#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
413
414#define GPIO141_GPIO PIN_CFG(141, GPIO)
415#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
416#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
417#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
418
419#define GPIO142_GPIO PIN_CFG(142, GPIO)
420#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
421#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
422#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
423
424#define GPIO143_GPIO PIN_CFG(143, GPIO)
425#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
426
427#define GPIO144_GPIO PIN_CFG(144, GPIO)
428#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
429
430#define GPIO145_GPIO PIN_CFG(145, GPIO)
431#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
432
433#define GPIO146_GPIO PIN_CFG(146, GPIO)
434#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
435
436#define GPIO147_GPIO PIN_CFG(147, GPIO)
437#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP)
438
439#define GPIO148_GPIO PIN_CFG(148, GPIO)
440#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP)
441
442#define GPIO149_GPIO PIN_CFG(149, GPIO)
443#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
444#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
445#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
446
447#define GPIO150_GPIO PIN_CFG(150, GPIO)
448#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
449#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
450
451#define GPIO151_GPIO PIN_CFG(151, GPIO)
452#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
453#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
454#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
455
456#define GPIO152_GPIO PIN_CFG(152, GPIO)
457#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
458#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
459#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
460
461#define GPIO153_GPIO PIN_CFG(153, GPIO)
462#define GPIO153_KP_I7 PIN_CFG(153, ALT_A)
463#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
464#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
465
466#define GPIO154_GPIO PIN_CFG(154, GPIO)
467#define GPIO154_KP_I6 PIN_CFG(154, ALT_A)
468#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
469#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
470
471#define GPIO155_GPIO PIN_CFG(155, GPIO)
472#define GPIO155_KP_I5 PIN_CFG(155, ALT_A)
473#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
474#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
475
476#define GPIO156_GPIO PIN_CFG(156, GPIO)
477#define GPIO156_KP_I4 PIN_CFG(156, ALT_A)
478#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
479#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
480
481#define GPIO157_GPIO PIN_CFG(157, GPIO)
482#define GPIO157_KP_O7 PIN_CFG(157, ALT_A)
483#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
484#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
485
486#define GPIO158_GPIO PIN_CFG(158, GPIO)
487#define GPIO158_KP_O6 PIN_CFG(158, ALT_A)
488#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
489#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
490
491#define GPIO159_GPIO PIN_CFG(159, GPIO)
492#define GPIO159_KP_O5 PIN_CFG(159, ALT_A)
493#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
494#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
495
496#define GPIO160_GPIO PIN_CFG(160, GPIO)
497#define GPIO160_KP_O4 PIN_CFG(160, ALT_A)
498#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
499#define GPIO160_NONE PIN_CFG(160, ALT_C)
500
501#define GPIO161_GPIO PIN_CFG(161, GPIO)
502#define GPIO161_KP_I3 PIN_CFG(161, ALT_A)
503#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
504#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
505
506#define GPIO162_GPIO PIN_CFG(162, GPIO)
507#define GPIO162_KP_I2 PIN_CFG(162, ALT_A)
508#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
509#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
510
511#define GPIO163_GPIO PIN_CFG(163, GPIO)
512#define GPIO163_KP_I1 PIN_CFG(163, ALT_A)
513#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
514#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
515
516#define GPIO164_GPIO PIN_CFG(164, GPIO)
517#define GPIO164_KP_I0 PIN_CFG(164, ALT_A)
518#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
519#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
520
521#define GPIO165_GPIO PIN_CFG(165, GPIO)
522#define GPIO165_KP_O3 PIN_CFG(165, ALT_A)
523#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
524#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
525
526#define GPIO166_GPIO PIN_CFG(166, GPIO)
527#define GPIO166_KP_O2 PIN_CFG(166, ALT_A)
528#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
529#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
530
531#define GPIO167_GPIO PIN_CFG(167, GPIO)
532#define GPIO167_KP_O1 PIN_CFG(167, ALT_A)
533#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
534#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
535
536#define GPIO168_GPIO PIN_CFG(168, GPIO)
537#define GPIO168_KP_O0 PIN_CFG(168, ALT_A)
538#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
539#define GPIO168_NONE PIN_CFG(168, ALT_C)
540
541#define GPIO169_GPIO PIN_CFG(169, GPIO)
542#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
543#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
544#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
545
546#define GPIO170_GPIO PIN_CFG(170, GPIO)
547#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
548#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
549#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
550
551#define GPIO171_GPIO PIN_CFG(171, GPIO)
552#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
553#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
554#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
555
556#define GPIO192_GPIO PIN_CFG(192, GPIO)
557#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
558
559#define GPIO193_GPIO PIN_CFG(193, GPIO)
560#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
561
562#define GPIO194_GPIO PIN_CFG(194, GPIO)
563#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
564
565#define GPIO195_GPIO PIN_CFG(195, GPIO)
566#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
567
568#define GPIO196_GPIO PIN_CFG(196, GPIO)
569#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
570
571#define GPIO197_GPIO PIN_CFG(197, GPIO)
572#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A)
573
574#define GPIO198_GPIO PIN_CFG(198, GPIO)
575#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A)
576
577#define GPIO199_GPIO PIN_CFG(199, GPIO)
578#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A)
579
580#define GPIO200_GPIO PIN_CFG(200, GPIO)
581#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A)
582
583#define GPIO201_GPIO PIN_CFG(201, GPIO)
584#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A)
585
586#define GPIO202_GPIO PIN_CFG(202, GPIO)
587#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A)
588#define GPIO202_PWL PIN_CFG(202, ALT_B)
589#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
590
591#define GPIO203_GPIO PIN_CFG(203, GPIO)
592#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A)
593
594#define GPIO204_GPIO PIN_CFG(204, GPIO)
595#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A)
596
597#define GPIO205_GPIO PIN_CFG(205, GPIO)
598#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A)
599
600#define GPIO206_GPIO PIN_CFG(206, GPIO)
601#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A)
602
603#define GPIO207_GPIO PIN_CFG(207, GPIO)
604#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A)
605
606#define GPIO208_GPIO PIN_CFG(208, GPIO)
607#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
608
609#define GPIO209_GPIO PIN_CFG(209, GPIO)
610#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
611#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
612
613#define GPIO210_GPIO PIN_CFG(210, GPIO)
614#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
615
616#define GPIO211_GPIO PIN_CFG(211, GPIO)
617#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
618
619#define GPIO212_GPIO PIN_CFG(212, GPIO)
620#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
621#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
622
623#define GPIO213_GPIO PIN_CFG(213, GPIO)
624#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
625#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
626
627#define GPIO214_GPIO PIN_CFG(214, GPIO)
628#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
629#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
630
631#define GPIO215_GPIO PIN_CFG(215, GPIO)
632#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
633#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
634#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
635
636#define GPIO216_GPIO PIN_CFG(216, GPIO)
637#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
638#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
639#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP)
640
641#define GPIO217_GPIO PIN_CFG(217, GPIO)
642#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
643#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
644#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
645
646#define GPIO218_GPIO PIN_CFG(218, GPIO)
647#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
648#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
649#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP)
650
651#define GPIO219_GPIO PIN_CFG(219, GPIO)
652#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
653#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
654
655#define GPIO220_GPIO PIN_CFG(220, GPIO)
656#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
657#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
658#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
659
660#define GPIO221_GPIO PIN_CFG(221, GPIO)
661#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
662#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
663
664#define GPIO222_GPIO PIN_CFG(222, GPIO)
665#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
666#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
667
668#define GPIO223_GPIO PIN_CFG(223, GPIO)
669#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
670#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
671#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
672
673#define GPIO224_GPIO PIN_CFG(224, GPIO)
674#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
675#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
676#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
677
678#define GPIO225_GPIO PIN_CFG(225, GPIO)
679#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
680#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
681#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
682
683#define GPIO226_GPIO PIN_CFG(226, GPIO)
684#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
685#define GPIO226_PWL PIN_CFG(226, ALT_B)
686#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
687
688#define GPIO227_GPIO PIN_CFG(227, GPIO)
689#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
690
691#define GPIO228_GPIO PIN_CFG(228, GPIO)
692#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
693
694#define GPIO229_GPIO PIN_CFG(229, GPIO)
695#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
696#define GPIO229_PWL PIN_CFG(229, ALT_B)
697#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP)
698
699#define GPIO230_GPIO PIN_CFG(230, GPIO)
700#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
701#define GPIO230_PWL PIN_CFG(230, ALT_B)
702#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP)
703
704#define GPIO256_GPIO PIN_CFG(256, GPIO)
705#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
706
707#define GPIO257_GPIO PIN_CFG(257, GPIO)
708#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
709
710#define GPIO258_GPIO PIN_CFG(258, GPIO)
711#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
712#define GPIO258_NONE PIN_CFG(258, ALT_B)
713#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
714
715#define GPIO259_GPIO PIN_CFG(259, GPIO)
716#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
717
718#define GPIO260_GPIO PIN_CFG(260, GPIO)
719#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
720
721#define GPIO261_GPIO PIN_CFG(261, GPIO)
722#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
723
724#define GPIO262_GPIO PIN_CFG(262, GPIO)
725#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
726
727#define GPIO263_GPIO PIN_CFG(263, GPIO)
728#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
729
730#define GPIO264_GPIO PIN_CFG(264, GPIO)
731#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
732
733#define GPIO265_GPIO PIN_CFG(265, GPIO)
734#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
735
736#define GPIO266_GPIO PIN_CFG(266, GPIO)
737#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
738
739#define GPIO267_GPIO PIN_CFG(267, GPIO)
740#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
741
742#endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3dff8641b03f..e38acb0f89c8 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -28,6 +28,7 @@
28#include <linux/amba/clcd.h> 28#include <linux/amba/clcd.h>
29#include <linux/amba/pl061.h> 29#include <linux/amba/pl061.h>
30#include <linux/amba/mmci.h> 30#include <linux/amba/mmci.h>
31#include <linux/amba/pl022.h>
31#include <linux/io.h> 32#include <linux/io.h>
32#include <linux/gfp.h> 33#include <linux/gfp.h>
33 34
@@ -354,6 +355,21 @@ static struct mmci_platform_data mmc0_plat_data = {
354 .gpio_cd = -1, 355 .gpio_cd = -1,
355}; 356};
356 357
358static struct resource char_lcd_resources[] = {
359 {
360 .start = VERSATILE_CHAR_LCD_BASE,
361 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
362 .flags = IORESOURCE_MEM,
363 },
364};
365
366static struct platform_device char_lcd_device = {
367 .name = "arm-charlcd",
368 .id = -1,
369 .num_resources = ARRAY_SIZE(char_lcd_resources),
370 .resource = char_lcd_resources,
371};
372
357/* 373/*
358 * Clock handling 374 * Clock handling
359 */ 375 */
@@ -400,8 +416,13 @@ static struct clk ref24_clk = {
400 .rate = 24000000, 416 .rate = 24000000,
401}; 417};
402 418
419static struct clk dummy_apb_pclk;
420
403static struct clk_lookup lookups[] = { 421static struct clk_lookup lookups[] = {
404 { /* UART0 */ 422 { /* AMBA bus clock */
423 .con_id = "apb_pclk",
424 .clk = &dummy_apb_pclk,
425 }, { /* UART0 */
405 .dev_id = "dev:f1", 426 .dev_id = "dev:f1",
406 .clk = &ref24_clk, 427 .clk = &ref24_clk,
407 }, { /* UART1 */ 428 }, { /* UART1 */
@@ -425,6 +446,9 @@ static struct clk_lookup lookups[] = {
425 }, { /* MMC1 */ 446 }, { /* MMC1 */
426 .dev_id = "fpga:0b", 447 .dev_id = "fpga:0b",
427 .clk = &ref24_clk, 448 .clk = &ref24_clk,
449 }, { /* SSP */
450 .dev_id = "dev:f4",
451 .clk = &ref24_clk,
428 }, { /* CLCD */ 452 }, { /* CLCD */
429 .dev_id = "dev:20", 453 .dev_id = "dev:20",
430 .clk = &osc4_clk, 454 .clk = &osc4_clk,
@@ -703,6 +727,12 @@ static struct pl061_platform_data gpio1_plat_data = {
703 .irq_base = IRQ_GPIO1_START, 727 .irq_base = IRQ_GPIO1_START,
704}; 728};
705 729
730static struct pl022_ssp_controller ssp0_plat_data = {
731 .bus_id = 0,
732 .enable_dma = 0,
733 .num_chipselect = 1,
734};
735
706#define AACI_IRQ { IRQ_AACI, NO_IRQ } 736#define AACI_IRQ { IRQ_AACI, NO_IRQ }
707#define AACI_DMA { 0x80, 0x81 } 737#define AACI_DMA { 0x80, 0x81 }
708#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } 738#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
@@ -772,7 +802,7 @@ AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
772AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); 802AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
773AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); 803AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
774AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); 804AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
775AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL); 805AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
776 806
777static struct amba_device *amba_devs[] __initdata = { 807static struct amba_device *amba_devs[] __initdata = {
778 &dmac_device, 808 &dmac_device,
@@ -843,6 +873,7 @@ void __init versatile_init(void)
843 platform_device_register(&versatile_flash_device); 873 platform_device_register(&versatile_flash_device);
844 platform_device_register(&versatile_i2c_device); 874 platform_device_register(&versatile_i2c_device);
845 platform_device_register(&smc91x_device); 875 platform_device_register(&smc91x_device);
876 platform_device_register(&char_lcd_device);
846 877
847 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 878 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
848 struct amba_device *d = amba_devs[i]; 879 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 334f0df4e948..13c7e5f90a82 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -304,7 +304,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
304} 304}
305 305
306 306
307struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) 307struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
308{ 308{
309 return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys); 309 return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
310} 310}
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 6353459bb567..577df6cccb08 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -16,6 +16,7 @@
16#include <asm/hardware/gic.h> 16#include <asm/hardware/gic.h>
17#include <asm/mach-types.h> 17#include <asm/mach-types.h>
18#include <asm/pmu.h> 18#include <asm/pmu.h>
19#include <asm/smp_twd.h>
19 20
20#include <mach/clkdev.h> 21#include <mach/clkdev.h>
21#include <mach/ct-ca9x4.h> 22#include <mach/ct-ca9x4.h>
@@ -53,6 +54,7 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = {
53 54
54static void __init ct_ca9x4_map_io(void) 55static void __init ct_ca9x4_map_io(void)
55{ 56{
57 twd_base = MMIO_P2V(A9_MPCORE_TWD);
56 v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); 58 v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
57} 59}
58 60
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index 8650f04136ef..f9e2f8d22962 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -28,6 +28,7 @@
28#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000) 28#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
29#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100) 29#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
30#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200) 30#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
31#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
31#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000) 32#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
32 33
33/* 34/*
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index c84239761cb4..817f0ad38a0b 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -298,8 +298,13 @@ static struct clk osc2_clk = {
298 .rate = 24000000, 298 .rate = 24000000,
299}; 299};
300 300
301static struct clk dummy_apb_pclk;
302
301static struct clk_lookup v2m_lookups[] = { 303static struct clk_lookup v2m_lookups[] = {
302 { /* UART0 */ 304 { /* AMBA bus clock */
305 .con_id = "apb_pclk",
306 .clk = &dummy_apb_pclk,
307 }, { /* UART0 */
303 .dev_id = "mb:uart0", 308 .dev_id = "mb:uart0",
304 .clk = &osc2_clk, 309 .clk = &osc2_clk,
305 }, { /* UART1 */ 310 }, { /* UART1 */
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index b2eda4dc1c34..7a1fa6adb7c3 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -36,6 +36,8 @@
36#include <mach/nuc900_spi.h> 36#include <mach/nuc900_spi.h>
37#include <mach/map.h> 37#include <mach/map.h>
38#include <mach/fb.h> 38#include <mach/fb.h>
39#include <mach/regs-ldm.h>
40#include <mach/w90p910_keypad.h>
39 41
40#include "cpu.h" 42#include "cpu.h"
41 43
@@ -207,7 +209,7 @@ static struct nuc900_spi_info nuc900_spiflash_data = {
207 .divider = 24, 209 .divider = 24,
208 .sleep = 0, 210 .sleep = 0,
209 .txnum = 0, 211 .txnum = 0,
210 .txbitlen = 1, 212 .txbitlen = 8,
211 .bus_num = 0, 213 .bus_num = 0,
212}; 214};
213 215
@@ -256,7 +258,7 @@ static struct spi_board_info nuc900_spi_board_info[] __initdata = {
256 .modalias = "m25p80", 258 .modalias = "m25p80",
257 .max_speed_hz = 20000000, 259 .max_speed_hz = 20000000,
258 .bus_num = 0, 260 .bus_num = 0,
259 .chip_select = 1, 261 .chip_select = 0,
260 .platform_data = &nuc900_spi_flash_data, 262 .platform_data = &nuc900_spi_flash_data,
261 .mode = SPI_MODE_0, 263 .mode = SPI_MODE_0,
262 }, 264 },
@@ -361,6 +363,39 @@ struct platform_device nuc900_device_fmi = {
361 363
362/* KPI controller*/ 364/* KPI controller*/
363 365
366static int nuc900_keymap[] = {
367 KEY(0, 0, KEY_A),
368 KEY(0, 1, KEY_B),
369 KEY(0, 2, KEY_C),
370 KEY(0, 3, KEY_D),
371
372 KEY(1, 0, KEY_E),
373 KEY(1, 1, KEY_F),
374 KEY(1, 2, KEY_G),
375 KEY(1, 3, KEY_H),
376
377 KEY(2, 0, KEY_I),
378 KEY(2, 1, KEY_J),
379 KEY(2, 2, KEY_K),
380 KEY(2, 3, KEY_L),
381
382 KEY(3, 0, KEY_M),
383 KEY(3, 1, KEY_N),
384 KEY(3, 2, KEY_O),
385 KEY(3, 3, KEY_P),
386};
387
388static struct matrix_keymap_data nuc900_map_data = {
389 .keymap = nuc900_keymap,
390 .keymap_size = ARRAY_SIZE(nuc900_keymap),
391};
392
393struct w90p910_keypad_platform_data nuc900_keypad_info = {
394 .keymap_data = &nuc900_map_data,
395 .prescale = 0xfa,
396 .debounce = 0x50,
397};
398
364static struct resource nuc900_kpi_resource[] = { 399static struct resource nuc900_kpi_resource[] = {
365 [0] = { 400 [0] = {
366 .start = W90X900_PA_KPI, 401 .start = W90X900_PA_KPI,
@@ -380,9 +415,49 @@ struct platform_device nuc900_device_kpi = {
380 .id = -1, 415 .id = -1,
381 .num_resources = ARRAY_SIZE(nuc900_kpi_resource), 416 .num_resources = ARRAY_SIZE(nuc900_kpi_resource),
382 .resource = nuc900_kpi_resource, 417 .resource = nuc900_kpi_resource,
418 .dev = {
419 .platform_data = &nuc900_keypad_info,
420 }
383}; 421};
384 422
385#ifdef CONFIG_FB_NUC900 423/* LCD controller*/
424
425static struct nuc900fb_display __initdata nuc900_lcd_info[] = {
426 /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
427 [0] = {
428 .type = LCM_DCCS_VA_SRC_RGB565,
429 .width = 320,
430 .height = 240,
431 .xres = 320,
432 .yres = 240,
433 .bpp = 16,
434 .pixclock = 200000,
435 .left_margin = 34,
436 .right_margin = 54,
437 .hsync_len = 10,
438 .upper_margin = 18,
439 .lower_margin = 4,
440 .vsync_len = 1,
441 .dccs = 0x8e00041a,
442 .devctl = 0x060800c0,
443 .fbctrl = 0x00a000a0,
444 .scale = 0x04000400,
445 },
446};
447
448static struct nuc900fb_mach_info nuc900_fb_info __initdata = {
449#if defined(CONFIG_GPM1040A0_320X240)
450 .displays = &nuc900_lcd_info[0],
451#else
452 .displays = nuc900_lcd_info,
453#endif
454 .num_displays = ARRAY_SIZE(nuc900_lcd_info),
455 .default_display = 0,
456 .gpio_dir = 0x00000004,
457 .gpio_dir_mask = 0xFFFFFFFD,
458 .gpio_data = 0x00000004,
459 .gpio_data_mask = 0xFFFFFFFD,
460};
386 461
387static struct resource nuc900_lcd_resource[] = { 462static struct resource nuc900_lcd_resource[] = {
388 [0] = { 463 [0] = {
@@ -406,23 +481,10 @@ struct platform_device nuc900_device_lcd = {
406 .dev = { 481 .dev = {
407 .dma_mask = &nuc900_device_lcd_dmamask, 482 .dma_mask = &nuc900_device_lcd_dmamask,
408 .coherent_dma_mask = -1, 483 .coherent_dma_mask = -1,
484 .platform_data = &nuc900_fb_info,
409 } 485 }
410}; 486};
411 487
412void nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd)
413{
414 struct nuc900fb_mach_info *npd;
415
416 npd = kmalloc(sizeof(*npd), GFP_KERNEL);
417 if (npd) {
418 memcpy(npd, pd, sizeof(*npd));
419 nuc900_device_lcd.dev.platform_data = npd;
420 } else {
421 printk(KERN_ERR "no memory for LCD platform data\n");
422 }
423}
424#endif
425
426/* AUDIO controller*/ 488/* AUDIO controller*/
427static u64 nuc900_device_audio_dmamask = -1; 489static u64 nuc900_device_audio_dmamask = -1;
428static struct resource nuc900_ac97_resource[] = { 490static struct resource nuc900_ac97_resource[] = {
diff --git a/arch/arm/mach-w90x900/include/mach/regs-gcr.h b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
new file mode 100644
index 000000000000..6087abd93ef5
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-w90x900/include/mach/regs-gcr.h
3 *
4 * Copyright (c) 2010 Nuvoton technology corporation
5 * All rights reserved.
6 *
7 * Wan ZongShun <mcuos.com@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#ifndef __ASM_ARCH_REGS_GCR_H
17#define __ASM_ARCH_REGS_GCR_H
18
19/* Global control registers */
20
21#define GCR_BA W90X900_VA_GCR
22#define REG_PDID (GCR_BA+0x000)
23#define REG_PWRON (GCR_BA+0x004)
24#define REG_ARBCON (GCR_BA+0x008)
25#define REG_MFSEL (GCR_BA+0x00C)
26#define REG_EBIDPE (GCR_BA+0x010)
27#define REG_LCDDPE (GCR_BA+0x014)
28#define REG_GPIOCPE (GCR_BA+0x018)
29#define REG_GPIODPE (GCR_BA+0x01C)
30#define REG_GPIOEPE (GCR_BA+0x020)
31#define REG_GPIOFPE (GCR_BA+0x024)
32#define REG_GPIOGPE (GCR_BA+0x028)
33#define REG_GPIOHPE (GCR_BA+0x02C)
34#define REG_GPIOIPE (GCR_BA+0x030)
35#define REG_GTMP1 (GCR_BA+0x034)
36#define REG_GTMP2 (GCR_BA+0x038)
37#define REG_GTMP3 (GCR_BA+0x03C)
38
39#endif /* __ASM_ARCH_REGS_GCR_H */
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index b3edc3cccf52..04d295f89eb0 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -20,51 +20,10 @@
20#include <asm/mach/map.h> 20#include <asm/mach/map.h>
21#include <asm/mach-types.h> 21#include <asm/mach-types.h>
22#include <mach/map.h> 22#include <mach/map.h>
23#include <mach/regs-ldm.h>
24#include <mach/fb.h> 23#include <mach/fb.h>
25 24
26#include "nuc950.h" 25#include "nuc950.h"
27 26
28#ifdef CONFIG_FB_NUC900
29/* LCD Controller */
30static struct nuc900fb_display __initdata nuc950_lcd_info[] = {
31 /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
32 [0] = {
33 .type = LCM_DCCS_VA_SRC_RGB565,
34 .width = 320,
35 .height = 240,
36 .xres = 320,
37 .yres = 240,
38 .bpp = 16,
39 .pixclock = 200000,
40 .left_margin = 34,
41 .right_margin = 54,
42 .hsync_len = 10,
43 .upper_margin = 18,
44 .lower_margin = 4,
45 .vsync_len = 1,
46 .dccs = 0x8e00041a,
47 .devctl = 0x060800c0,
48 .fbctrl = 0x00a000a0,
49 .scale = 0x04000400,
50 },
51};
52
53static struct nuc900fb_mach_info nuc950_fb_info __initdata = {
54#if defined(CONFIG_GPM1040A0_320X240)
55 .displays = &nuc950_lcd_info[0],
56#else
57 .displays = nuc950_lcd_info,
58#endif
59 .num_displays = ARRAY_SIZE(nuc950_lcd_info),
60 .default_display = 0,
61 .gpio_dir = 0x00000004,
62 .gpio_dir_mask = 0xFFFFFFFD,
63 .gpio_data = 0x00000004,
64 .gpio_data_mask = 0xFFFFFFFD,
65};
66#endif
67
68static void __init nuc950evb_map_io(void) 27static void __init nuc950evb_map_io(void)
69{ 28{
70 nuc950_map_io(); 29 nuc950_map_io();
@@ -74,9 +33,6 @@ static void __init nuc950evb_map_io(void)
74static void __init nuc950evb_init(void) 33static void __init nuc950evb_init(void)
75{ 34{
76 nuc950_board_init(); 35 nuc950_board_init();
77#ifdef CONFIG_FB_NUC900
78 nuc900_fb_set_platdata(&nuc950_fb_info);
79#endif
80} 36}
81 37
82MACHINE_START(W90P950EVB, "W90P950EVB") 38MACHINE_START(W90P950EVB, "W90P950EVB")
diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c
index 656f03b3b629..1523f4136985 100644
--- a/arch/arm/mach-w90x900/nuc910.c
+++ b/arch/arm/mach-w90x900/nuc910.c
@@ -26,6 +26,8 @@
26static struct platform_device *nuc910_dev[] __initdata = { 26static struct platform_device *nuc910_dev[] __initdata = {
27 &nuc900_device_ts, 27 &nuc900_device_ts,
28 &nuc900_device_rtc, 28 &nuc900_device_rtc,
29 &nuc900_device_lcd,
30 &nuc900_device_kpi,
29}; 31};
30 32
31/* define specific CPU platform io map */ 33/* define specific CPU platform io map */
diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c
index 4d1f1ab044c4..5704f74a50ee 100644
--- a/arch/arm/mach-w90x900/nuc950.c
+++ b/arch/arm/mach-w90x900/nuc950.c
@@ -26,9 +26,7 @@
26static struct platform_device *nuc950_dev[] __initdata = { 26static struct platform_device *nuc950_dev[] __initdata = {
27 &nuc900_device_kpi, 27 &nuc900_device_kpi,
28 &nuc900_device_fmi, 28 &nuc900_device_fmi,
29#ifdef CONFIG_FB_NUC900
30 &nuc900_device_lcd, 29 &nuc900_device_lcd,
31#endif
32}; 30};
33 31
34/* define specific CPU platform io map */ 32/* define specific CPU platform io map */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 101105e52610..87ec141fcaa6 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -717,17 +717,6 @@ config TLS_REG_EMUL
717 a few prototypes like that in existence) and therefore access to 717 a few prototypes like that in existence) and therefore access to
718 that required register must be emulated. 718 that required register must be emulated.
719 719
720config HAS_TLS_REG
721 bool
722 depends on !TLS_REG_EMUL
723 default y if SMP || CPU_32v7
724 help
725 This selects support for the CP15 thread register.
726 It is defined to be available on some ARMv6 processors (including
727 all SMP capable ARMv6's) or later processors. User space may
728 assume directly accessing that register and always obtain the
729 expected value only on ARMv7 and above.
730
731config NEEDS_SYSCALL_FOR_CMPXCHG 720config NEEDS_SYSCALL_FOR_CMPXCHG
732 bool 721 bool
733 help 722 help
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index e8d34a80851c..d63b6c413758 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -15,7 +15,6 @@ endif
15obj-$(CONFIG_MODULES) += proc-syms.o 15obj-$(CONFIG_MODULES) += proc-syms.o
16 16
17obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o 17obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
18obj-$(CONFIG_DISCONTIGMEM) += discontig.o
19obj-$(CONFIG_HIGHMEM) += highmem.o 18obj-$(CONFIG_HIGHMEM) += highmem.o
20 19
21obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o 20obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 6f98c358989a..d073b64ae87e 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -924,8 +924,20 @@ static int __init alignment_init(void)
924 ai_usermode = UM_FIXUP; 924 ai_usermode = UM_FIXUP;
925 } 925 }
926 926
927 hook_fault_code(1, do_alignment, SIGILL, "alignment exception"); 927 hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
928 hook_fault_code(3, do_alignment, SIGILL, "alignment exception"); 928 "alignment exception");
929
930 /*
931 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
932 * fault, not as alignment error.
933 *
934 * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
935 * needed.
936 */
937 if (cpu_architecture() <= CPU_ARCH_ARMv6) {
938 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
939 "alignment exception");
940 }
929 941
930 return 0; 942 return 0;
931} 943}
diff --git a/arch/arm/mm/discontig.c b/arch/arm/mm/discontig.c
deleted file mode 100644
index c8c0c4b0f0a3..000000000000
--- a/arch/arm/mm/discontig.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/arch/arm/mm/discontig.c
3 *
4 * Discontiguous memory support.
5 *
6 * Initial code: Copyright (C) 1999-2000 Nicolas Pitre
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/module.h>
13#include <linux/mmzone.h>
14#include <linux/bootmem.h>
15
16#if MAX_NUMNODES != 4 && MAX_NUMNODES != 16
17# error Fix Me Please
18#endif
19
20/*
21 * Our node_data structure for discontiguous memory.
22 */
23
24pg_data_t discontig_node_data[MAX_NUMNODES] = {
25 { .bdata = &bootmem_node_data[0] },
26 { .bdata = &bootmem_node_data[1] },
27 { .bdata = &bootmem_node_data[2] },
28 { .bdata = &bootmem_node_data[3] },
29#if MAX_NUMNODES == 16
30 { .bdata = &bootmem_node_data[4] },
31 { .bdata = &bootmem_node_data[5] },
32 { .bdata = &bootmem_node_data[6] },
33 { .bdata = &bootmem_node_data[7] },
34 { .bdata = &bootmem_node_data[8] },
35 { .bdata = &bootmem_node_data[9] },
36 { .bdata = &bootmem_node_data[10] },
37 { .bdata = &bootmem_node_data[11] },
38 { .bdata = &bootmem_node_data[12] },
39 { .bdata = &bootmem_node_data[13] },
40 { .bdata = &bootmem_node_data[14] },
41 { .bdata = &bootmem_node_data[15] },
42#endif
43};
44
45EXPORT_SYMBOL(discontig_node_data);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 9e7742f0a102..c704eed63c5d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -183,6 +183,8 @@ static void *
183__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot) 183__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
184{ 184{
185 struct arm_vmregion *c; 185 struct arm_vmregion *c;
186 size_t align;
187 int bit;
186 188
187 if (!consistent_pte[0]) { 189 if (!consistent_pte[0]) {
188 printk(KERN_ERR "%s: not initialised\n", __func__); 190 printk(KERN_ERR "%s: not initialised\n", __func__);
@@ -191,9 +193,20 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
191 } 193 }
192 194
193 /* 195 /*
196 * Align the virtual region allocation - maximum alignment is
197 * a section size, minimum is a page size. This helps reduce
198 * fragmentation of the DMA space, and also prevents allocations
199 * smaller than a section from crossing a section boundary.
200 */
201 bit = fls(size - 1) + 1;
202 if (bit > SECTION_SHIFT)
203 bit = SECTION_SHIFT;
204 align = 1 << bit;
205
206 /*
194 * Allocate a virtual address in the consistent mapping region. 207 * Allocate a virtual address in the consistent mapping region.
195 */ 208 */
196 c = arm_vmregion_alloc(&consistent_head, size, 209 c = arm_vmregion_alloc(&consistent_head, align, size,
197 gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); 210 gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
198 if (c) { 211 if (c) {
199 pte_t *pte; 212 pte_t *pte;
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index cbfb2edcf7d1..23b0b03af5ea 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -413,7 +413,16 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
413 pmd_k = pmd_offset(pgd_k, addr); 413 pmd_k = pmd_offset(pgd_k, addr);
414 pmd = pmd_offset(pgd, addr); 414 pmd = pmd_offset(pgd, addr);
415 415
416 if (pmd_none(*pmd_k)) 416 /*
417 * On ARM one Linux PGD entry contains two hardware entries (see page
418 * tables layout in pgtable.h). We normally guarantee that we always
419 * fill both L1 entries. But create_mapping() doesn't follow the rule.
420 * It can create inidividual L1 entries, so here we have to call
421 * pmd_none() check for the entry really corresponded to address, not
422 * for the first of pair.
423 */
424 index = (addr >> SECTION_SHIFT) & 1;
425 if (pmd_none(pmd_k[index]))
417 goto bad_area; 426 goto bad_area;
418 427
419 copy_pmd(pmd, pmd_k); 428 copy_pmd(pmd, pmd_k);
@@ -463,15 +472,10 @@ static struct fsr_info {
463 * defines these to be "precise" aborts. 472 * defines these to be "precise" aborts.
464 */ 473 */
465 { do_bad, SIGSEGV, 0, "vector exception" }, 474 { do_bad, SIGSEGV, 0, "vector exception" },
466 { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, 475 { do_bad, SIGBUS, BUS_ADRALN, "alignment exception" },
467 { do_bad, SIGKILL, 0, "terminal exception" }, 476 { do_bad, SIGKILL, 0, "terminal exception" },
468 { do_bad, SIGILL, BUS_ADRALN, "alignment exception" }, 477 { do_bad, SIGBUS, BUS_ADRALN, "alignment exception" },
469/* Do we need runtime check ? */
470#if __LINUX_ARM_ARCH__ < 6
471 { do_bad, SIGBUS, 0, "external abort on linefetch" }, 478 { do_bad, SIGBUS, 0, "external abort on linefetch" },
472#else
473 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "I-cache maintenance fault" },
474#endif
475 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" }, 479 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" },
476 { do_bad, SIGBUS, 0, "external abort on linefetch" }, 480 { do_bad, SIGBUS, 0, "external abort on linefetch" },
477 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" }, 481 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" },
@@ -508,13 +512,15 @@ static struct fsr_info {
508 512
509void __init 513void __init
510hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), 514hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
511 int sig, const char *name) 515 int sig, int code, const char *name)
512{ 516{
513 if (nr >= 0 && nr < ARRAY_SIZE(fsr_info)) { 517 if (nr < 0 || nr >= ARRAY_SIZE(fsr_info))
514 fsr_info[nr].fn = fn; 518 BUG();
515 fsr_info[nr].sig = sig; 519
516 fsr_info[nr].name = name; 520 fsr_info[nr].fn = fn;
517 } 521 fsr_info[nr].sig = sig;
522 fsr_info[nr].code = code;
523 fsr_info[nr].name = name;
518} 524}
519 525
520/* 526/*
@@ -594,3 +600,25 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
594 arm_notify_die("", regs, &info, ifsr, 0); 600 arm_notify_die("", regs, &info, ifsr, 0);
595} 601}
596 602
603static int __init exceptions_init(void)
604{
605 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
606 hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR,
607 "I-cache maintenance fault");
608 }
609
610 if (cpu_architecture() >= CPU_ARCH_ARMv7) {
611 /*
612 * TODO: Access flag faults introduced in ARMv6K.
613 * Runtime check for 'K' extension is needed
614 */
615 hook_fault_code(3, do_bad, SIGSEGV, SEGV_MAPERR,
616 "section access flag fault");
617 hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR,
618 "section access flag fault");
619 }
620
621 return 0;
622}
623
624arch_initcall(exceptions_init);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f6a999465323..7185b00650fe 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -17,6 +17,7 @@
17#include <linux/initrd.h> 17#include <linux/initrd.h>
18#include <linux/highmem.h> 18#include <linux/highmem.h>
19#include <linux/gfp.h> 19#include <linux/gfp.h>
20#include <linux/memblock.h>
20 21
21#include <asm/mach-types.h> 22#include <asm/mach-types.h>
22#include <asm/sections.h> 23#include <asm/sections.h>
@@ -79,38 +80,37 @@ struct meminfo meminfo;
79void show_mem(void) 80void show_mem(void)
80{ 81{
81 int free = 0, total = 0, reserved = 0; 82 int free = 0, total = 0, reserved = 0;
82 int shared = 0, cached = 0, slab = 0, node, i; 83 int shared = 0, cached = 0, slab = 0, i;
83 struct meminfo * mi = &meminfo; 84 struct meminfo * mi = &meminfo;
84 85
85 printk("Mem-info:\n"); 86 printk("Mem-info:\n");
86 show_free_areas(); 87 show_free_areas();
87 for_each_online_node(node) { 88
88 for_each_nodebank (i,mi,node) { 89 for_each_bank (i, mi) {
89 struct membank *bank = &mi->bank[i]; 90 struct membank *bank = &mi->bank[i];
90 unsigned int pfn1, pfn2; 91 unsigned int pfn1, pfn2;
91 struct page *page, *end; 92 struct page *page, *end;
92 93
93 pfn1 = bank_pfn_start(bank); 94 pfn1 = bank_pfn_start(bank);
94 pfn2 = bank_pfn_end(bank); 95 pfn2 = bank_pfn_end(bank);
95 96
96 page = pfn_to_page(pfn1); 97 page = pfn_to_page(pfn1);
97 end = pfn_to_page(pfn2 - 1) + 1; 98 end = pfn_to_page(pfn2 - 1) + 1;
98 99
99 do { 100 do {
100 total++; 101 total++;
101 if (PageReserved(page)) 102 if (PageReserved(page))
102 reserved++; 103 reserved++;
103 else if (PageSwapCache(page)) 104 else if (PageSwapCache(page))
104 cached++; 105 cached++;
105 else if (PageSlab(page)) 106 else if (PageSlab(page))
106 slab++; 107 slab++;
107 else if (!page_count(page)) 108 else if (!page_count(page))
108 free++; 109 free++;
109 else 110 else
110 shared += page_count(page) - 1; 111 shared += page_count(page) - 1;
111 page++; 112 page++;
112 } while (page < end); 113 } while (page < end);
113 }
114 } 114 }
115 115
116 printk("%d pages of RAM\n", total); 116 printk("%d pages of RAM\n", total);
@@ -121,7 +121,7 @@ void show_mem(void)
121 printk("%d pages swap cached\n", cached); 121 printk("%d pages swap cached\n", cached);
122} 122}
123 123
124static void __init find_node_limits(int node, struct meminfo *mi, 124static void __init find_limits(struct meminfo *mi,
125 unsigned long *min, unsigned long *max_low, unsigned long *max_high) 125 unsigned long *min, unsigned long *max_low, unsigned long *max_high)
126{ 126{
127 int i; 127 int i;
@@ -129,7 +129,7 @@ static void __init find_node_limits(int node, struct meminfo *mi,
129 *min = -1UL; 129 *min = -1UL;
130 *max_low = *max_high = 0; 130 *max_low = *max_high = 0;
131 131
132 for_each_nodebank(i, mi, node) { 132 for_each_bank (i, mi) {
133 struct membank *bank = &mi->bank[i]; 133 struct membank *bank = &mi->bank[i];
134 unsigned long start, end; 134 unsigned long start, end;
135 135
@@ -147,155 +147,64 @@ static void __init find_node_limits(int node, struct meminfo *mi,
147 } 147 }
148} 148}
149 149
150/* 150static void __init arm_bootmem_init(struct meminfo *mi,
151 * FIXME: We really want to avoid allocating the bootmap bitmap
152 * over the top of the initrd. Hopefully, this is located towards
153 * the start of a bank, so if we allocate the bootmap bitmap at
154 * the end, we won't clash.
155 */
156static unsigned int __init
157find_bootmap_pfn(int node, struct meminfo *mi, unsigned int bootmap_pages)
158{
159 unsigned int start_pfn, i, bootmap_pfn;
160
161 start_pfn = PAGE_ALIGN(__pa(_end)) >> PAGE_SHIFT;
162 bootmap_pfn = 0;
163
164 for_each_nodebank(i, mi, node) {
165 struct membank *bank = &mi->bank[i];
166 unsigned int start, end;
167
168 start = bank_pfn_start(bank);
169 end = bank_pfn_end(bank);
170
171 if (end < start_pfn)
172 continue;
173
174 if (start < start_pfn)
175 start = start_pfn;
176
177 if (end <= start)
178 continue;
179
180 if (end - start >= bootmap_pages) {
181 bootmap_pfn = start;
182 break;
183 }
184 }
185
186 if (bootmap_pfn == 0)
187 BUG();
188
189 return bootmap_pfn;
190}
191
192static int __init check_initrd(struct meminfo *mi)
193{
194 int initrd_node = -2;
195#ifdef CONFIG_BLK_DEV_INITRD
196 unsigned long end = phys_initrd_start + phys_initrd_size;
197
198 /*
199 * Make sure that the initrd is within a valid area of
200 * memory.
201 */
202 if (phys_initrd_size) {
203 unsigned int i;
204
205 initrd_node = -1;
206
207 for (i = 0; i < mi->nr_banks; i++) {
208 struct membank *bank = &mi->bank[i];
209 if (bank_phys_start(bank) <= phys_initrd_start &&
210 end <= bank_phys_end(bank))
211 initrd_node = bank->node;
212 }
213 }
214
215 if (initrd_node == -1) {
216 printk(KERN_ERR "INITRD: 0x%08lx+0x%08lx extends beyond "
217 "physical memory - disabling initrd\n",
218 phys_initrd_start, phys_initrd_size);
219 phys_initrd_start = phys_initrd_size = 0;
220 }
221#endif
222
223 return initrd_node;
224}
225
226static void __init bootmem_init_node(int node, struct meminfo *mi,
227 unsigned long start_pfn, unsigned long end_pfn) 151 unsigned long start_pfn, unsigned long end_pfn)
228{ 152{
229 unsigned long boot_pfn;
230 unsigned int boot_pages; 153 unsigned int boot_pages;
154 phys_addr_t bitmap;
231 pg_data_t *pgdat; 155 pg_data_t *pgdat;
232 int i; 156 int i;
233 157
234 /* 158 /*
235 * Allocate the bootmem bitmap page. 159 * Allocate the bootmem bitmap page. This must be in a region
160 * of memory which has already been mapped.
236 */ 161 */
237 boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn); 162 boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
238 boot_pfn = find_bootmap_pfn(node, mi, boot_pages); 163 bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES,
164 __pfn_to_phys(end_pfn));
239 165
240 /* 166 /*
241 * Initialise the bootmem allocator for this node, handing the 167 * Initialise the bootmem allocator, handing the
242 * memory banks over to bootmem. 168 * memory banks over to bootmem.
243 */ 169 */
244 node_set_online(node); 170 node_set_online(0);
245 pgdat = NODE_DATA(node); 171 pgdat = NODE_DATA(0);
246 init_bootmem_node(pgdat, boot_pfn, start_pfn, end_pfn); 172 init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn);
247 173
248 for_each_nodebank(i, mi, node) { 174 for_each_bank(i, mi) {
249 struct membank *bank = &mi->bank[i]; 175 struct membank *bank = &mi->bank[i];
250 if (!bank->highmem) 176 if (!bank->highmem)
251 free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank)); 177 free_bootmem(bank_phys_start(bank), bank_phys_size(bank));
252 } 178 }
253 179
254 /* 180 /*
255 * Reserve the bootmem bitmap for this node. 181 * Reserve the memblock reserved regions in bootmem.
256 */ 182 */
257 reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT, 183 for (i = 0; i < memblock.reserved.cnt; i++) {
258 boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT); 184 phys_addr_t start = memblock_start_pfn(&memblock.reserved, i);
259} 185 if (start >= start_pfn &&
260 186 memblock_end_pfn(&memblock.reserved, i) <= end_pfn)
261static void __init bootmem_reserve_initrd(int node) 187 reserve_bootmem_node(pgdat, __pfn_to_phys(start),
262{ 188 memblock_size_bytes(&memblock.reserved, i),
263#ifdef CONFIG_BLK_DEV_INITRD 189 BOOTMEM_DEFAULT);
264 pg_data_t *pgdat = NODE_DATA(node);
265 int res;
266
267 res = reserve_bootmem_node(pgdat, phys_initrd_start,
268 phys_initrd_size, BOOTMEM_EXCLUSIVE);
269
270 if (res == 0) {
271 initrd_start = __phys_to_virt(phys_initrd_start);
272 initrd_end = initrd_start + phys_initrd_size;
273 } else {
274 printk(KERN_ERR
275 "INITRD: 0x%08lx+0x%08lx overlaps in-use "
276 "memory region - disabling initrd\n",
277 phys_initrd_start, phys_initrd_size);
278 } 190 }
279#endif
280} 191}
281 192
282static void __init bootmem_free_node(int node, struct meminfo *mi) 193static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min,
194 unsigned long max_low, unsigned long max_high)
283{ 195{
284 unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES]; 196 unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
285 unsigned long min, max_low, max_high;
286 int i; 197 int i;
287 198
288 find_node_limits(node, mi, &min, &max_low, &max_high);
289
290 /* 199 /*
291 * initialise the zones within this node. 200 * initialise the zones.
292 */ 201 */
293 memset(zone_size, 0, sizeof(zone_size)); 202 memset(zone_size, 0, sizeof(zone_size));
294 203
295 /* 204 /*
296 * The size of this node has already been determined. If we need 205 * The memory size has already been determined. If we need
297 * to do anything fancy with the allocation of this memory to the 206 * to do anything fancy with the allocation of this memory
298 * zones, now is the time to do it. 207 * to the zones, now is the time to do it.
299 */ 208 */
300 zone_size[0] = max_low - min; 209 zone_size[0] = max_low - min;
301#ifdef CONFIG_HIGHMEM 210#ifdef CONFIG_HIGHMEM
@@ -303,11 +212,11 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
303#endif 212#endif
304 213
305 /* 214 /*
306 * For each bank in this node, calculate the size of the holes. 215 * Calculate the size of the holes.
307 * holes = node_size - sum(bank_sizes_in_node) 216 * holes = node_size - sum(bank_sizes)
308 */ 217 */
309 memcpy(zhole_size, zone_size, sizeof(zhole_size)); 218 memcpy(zhole_size, zone_size, sizeof(zhole_size));
310 for_each_nodebank(i, mi, node) { 219 for_each_bank(i, mi) {
311 int idx = 0; 220 int idx = 0;
312#ifdef CONFIG_HIGHMEM 221#ifdef CONFIG_HIGHMEM
313 if (mi->bank[i].highmem) 222 if (mi->bank[i].highmem)
@@ -320,24 +229,23 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
320 * Adjust the sizes according to any special requirements for 229 * Adjust the sizes according to any special requirements for
321 * this machine type. 230 * this machine type.
322 */ 231 */
323 arch_adjust_zones(node, zone_size, zhole_size); 232 arch_adjust_zones(zone_size, zhole_size);
324 233
325 free_area_init_node(node, zone_size, min, zhole_size); 234 free_area_init_node(0, zone_size, min, zhole_size);
326} 235}
327 236
328#ifndef CONFIG_SPARSEMEM 237#ifndef CONFIG_SPARSEMEM
329int pfn_valid(unsigned long pfn) 238int pfn_valid(unsigned long pfn)
330{ 239{
331 struct meminfo *mi = &meminfo; 240 struct memblock_region *mem = &memblock.memory;
332 unsigned int left = 0, right = mi->nr_banks; 241 unsigned int left = 0, right = mem->cnt;
333 242
334 do { 243 do {
335 unsigned int mid = (right + left) / 2; 244 unsigned int mid = (right + left) / 2;
336 struct membank *bank = &mi->bank[mid];
337 245
338 if (pfn < bank_pfn_start(bank)) 246 if (pfn < memblock_start_pfn(mem, mid))
339 right = mid; 247 right = mid;
340 else if (pfn >= bank_pfn_end(bank)) 248 else if (pfn >= memblock_end_pfn(mem, mid))
341 left = mid + 1; 249 left = mid + 1;
342 else 250 else
343 return 1; 251 return 1;
@@ -346,73 +254,69 @@ int pfn_valid(unsigned long pfn)
346} 254}
347EXPORT_SYMBOL(pfn_valid); 255EXPORT_SYMBOL(pfn_valid);
348 256
349static void arm_memory_present(struct meminfo *mi, int node) 257static void arm_memory_present(void)
350{ 258{
351} 259}
352#else 260#else
353static void arm_memory_present(struct meminfo *mi, int node) 261static void arm_memory_present(void)
354{ 262{
355 int i; 263 int i;
356 for_each_nodebank(i, mi, node) { 264 for (i = 0; i < memblock.memory.cnt; i++)
357 struct membank *bank = &mi->bank[i]; 265 memory_present(0, memblock_start_pfn(&memblock.memory, i),
358 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank)); 266 memblock_end_pfn(&memblock.memory, i));
359 }
360} 267}
361#endif 268#endif
362 269
363void __init bootmem_init(void) 270void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
364{ 271{
365 struct meminfo *mi = &meminfo; 272 int i;
366 unsigned long min, max_low, max_high;
367 int node, initrd_node;
368 273
369 /* 274 memblock_init();
370 * Locate which node contains the ramdisk image, if any. 275 for (i = 0; i < mi->nr_banks; i++)
371 */ 276 memblock_add(mi->bank[i].start, mi->bank[i].size);
372 initrd_node = check_initrd(mi);
373 277
374 max_low = max_high = 0; 278 /* Register the kernel text, kernel data and initrd with memblock. */
279#ifdef CONFIG_XIP_KERNEL
280 memblock_reserve(__pa(_data), _end - _data);
281#else
282 memblock_reserve(__pa(_stext), _end - _stext);
283#endif
284#ifdef CONFIG_BLK_DEV_INITRD
285 if (phys_initrd_size) {
286 memblock_reserve(phys_initrd_start, phys_initrd_size);
375 287
376 /* 288 /* Now convert initrd to virtual addresses */
377 * Run through each node initialising the bootmem allocator. 289 initrd_start = __phys_to_virt(phys_initrd_start);
378 */ 290 initrd_end = initrd_start + phys_initrd_size;
379 for_each_node(node) { 291 }
380 unsigned long node_low, node_high; 292#endif
381 293
382 find_node_limits(node, mi, &min, &node_low, &node_high); 294 arm_mm_memblock_reserve();
383 295
384 if (node_low > max_low) 296 /* reserve any platform specific memblock areas */
385 max_low = node_low; 297 if (mdesc->reserve)
386 if (node_high > max_high) 298 mdesc->reserve();
387 max_high = node_high;
388 299
389 /* 300 memblock_analyze();
390 * If there is no memory in this node, ignore it. 301 memblock_dump_all();
391 * (We can't have nodes which have no lowmem) 302}
392 */
393 if (node_low == 0)
394 continue;
395 303
396 bootmem_init_node(node, mi, min, node_low); 304void __init bootmem_init(void)
305{
306 struct meminfo *mi = &meminfo;
307 unsigned long min, max_low, max_high;
397 308
398 /* 309 max_low = max_high = 0;
399 * Reserve any special node zero regions.
400 */
401 if (node == 0)
402 reserve_node_zero(NODE_DATA(node));
403 310
404 /* 311 find_limits(mi, &min, &max_low, &max_high);
405 * If the initrd is in this node, reserve its memory.
406 */
407 if (node == initrd_node)
408 bootmem_reserve_initrd(node);
409 312
410 /* 313 arm_bootmem_init(mi, min, max_low);
411 * Sparsemem tries to allocate bootmem in memory_present(), 314
412 * so must be done after the fixed reservations 315 /*
413 */ 316 * Sparsemem tries to allocate bootmem in memory_present(),
414 arm_memory_present(mi, node); 317 * so must be done after the fixed reservations
415 } 318 */
319 arm_memory_present();
416 320
417 /* 321 /*
418 * sparse_init() needs the bootmem allocator up and running. 322 * sparse_init() needs the bootmem allocator up and running.
@@ -420,12 +324,11 @@ void __init bootmem_init(void)
420 sparse_init(); 324 sparse_init();
421 325
422 /* 326 /*
423 * Now free memory in each node - free_area_init_node needs 327 * Now free the memory - free_area_init_node needs
424 * the sparse mem_map arrays initialized by sparse_init() 328 * the sparse mem_map arrays initialized by sparse_init()
425 * for memmap_init_zone(), otherwise all PFNs are invalid. 329 * for memmap_init_zone(), otherwise all PFNs are invalid.
426 */ 330 */
427 for_each_node(node) 331 arm_bootmem_free(mi, min, max_low, max_high);
428 bootmem_free_node(node, mi);
429 332
430 high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1; 333 high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
431 334
@@ -460,7 +363,7 @@ static inline int free_area(unsigned long pfn, unsigned long end, char *s)
460} 363}
461 364
462static inline void 365static inline void
463free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn) 366free_memmap(unsigned long start_pfn, unsigned long end_pfn)
464{ 367{
465 struct page *start_pg, *end_pg; 368 struct page *start_pg, *end_pg;
466 unsigned long pg, pgend; 369 unsigned long pg, pgend;
@@ -483,40 +386,39 @@ free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
483 * free the section of the memmap array. 386 * free the section of the memmap array.
484 */ 387 */
485 if (pg < pgend) 388 if (pg < pgend)
486 free_bootmem_node(NODE_DATA(node), pg, pgend - pg); 389 free_bootmem(pg, pgend - pg);
487} 390}
488 391
489/* 392/*
490 * The mem_map array can get very big. Free the unused area of the memory map. 393 * The mem_map array can get very big. Free the unused area of the memory map.
491 */ 394 */
492static void __init free_unused_memmap_node(int node, struct meminfo *mi) 395static void __init free_unused_memmap(struct meminfo *mi)
493{ 396{
494 unsigned long bank_start, prev_bank_end = 0; 397 unsigned long bank_start, prev_bank_end = 0;
495 unsigned int i; 398 unsigned int i;
496 399
497 /* 400 /*
498 * [FIXME] This relies on each bank being in address order. This 401 * This relies on each bank being in address order.
499 * may not be the case, especially if the user has provided the 402 * The banks are sorted previously in bootmem_init().
500 * information on the command line.
501 */ 403 */
502 for_each_nodebank(i, mi, node) { 404 for_each_bank(i, mi) {
503 struct membank *bank = &mi->bank[i]; 405 struct membank *bank = &mi->bank[i];
504 406
505 bank_start = bank_pfn_start(bank); 407 bank_start = bank_pfn_start(bank);
506 if (bank_start < prev_bank_end) {
507 printk(KERN_ERR "MEM: unordered memory banks. "
508 "Not freeing memmap.\n");
509 break;
510 }
511 408
512 /* 409 /*
513 * If we had a previous bank, and there is a space 410 * If we had a previous bank, and there is a space
514 * between the current bank and the previous, free it. 411 * between the current bank and the previous, free it.
515 */ 412 */
516 if (prev_bank_end && prev_bank_end != bank_start) 413 if (prev_bank_end && prev_bank_end < bank_start)
517 free_memmap(node, prev_bank_end, bank_start); 414 free_memmap(prev_bank_end, bank_start);
518 415
519 prev_bank_end = bank_pfn_end(bank); 416 /*
417 * Align up here since the VM subsystem insists that the
418 * memmap entries are valid from the bank end aligned to
419 * MAX_ORDER_NR_PAGES.
420 */
421 prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
520 } 422 }
521} 423}
522 424
@@ -528,21 +430,19 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
528void __init mem_init(void) 430void __init mem_init(void)
529{ 431{
530 unsigned long reserved_pages, free_pages; 432 unsigned long reserved_pages, free_pages;
531 int i, node; 433 int i;
434#ifdef CONFIG_HAVE_TCM
435 /* These pointers are filled in on TCM detection */
436 extern u32 dtcm_end;
437 extern u32 itcm_end;
438#endif
532 439
533#ifndef CONFIG_DISCONTIGMEM
534 max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map; 440 max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
535#endif
536 441
537 /* this will put all unused low memory onto the freelists */ 442 /* this will put all unused low memory onto the freelists */
538 for_each_online_node(node) { 443 free_unused_memmap(&meminfo);
539 pg_data_t *pgdat = NODE_DATA(node);
540 444
541 free_unused_memmap_node(node, &meminfo); 445 totalram_pages += free_all_bootmem();
542
543 if (pgdat->node_spanned_pages != 0)
544 totalram_pages += free_all_bootmem_node(pgdat);
545 }
546 446
547#ifdef CONFIG_SA1111 447#ifdef CONFIG_SA1111
548 /* now that our DMA memory is actually so designated, we can free it */ 448 /* now that our DMA memory is actually so designated, we can free it */
@@ -552,39 +452,35 @@ void __init mem_init(void)
552 452
553#ifdef CONFIG_HIGHMEM 453#ifdef CONFIG_HIGHMEM
554 /* set highmem page free */ 454 /* set highmem page free */
555 for_each_online_node(node) { 455 for_each_bank (i, &meminfo) {
556 for_each_nodebank (i, &meminfo, node) { 456 unsigned long start = bank_pfn_start(&meminfo.bank[i]);
557 unsigned long start = bank_pfn_start(&meminfo.bank[i]); 457 unsigned long end = bank_pfn_end(&meminfo.bank[i]);
558 unsigned long end = bank_pfn_end(&meminfo.bank[i]); 458 if (start >= max_low_pfn + PHYS_PFN_OFFSET)
559 if (start >= max_low_pfn + PHYS_PFN_OFFSET) 459 totalhigh_pages += free_area(start, end, NULL);
560 totalhigh_pages += free_area(start, end, NULL);
561 }
562 } 460 }
563 totalram_pages += totalhigh_pages; 461 totalram_pages += totalhigh_pages;
564#endif 462#endif
565 463
566 reserved_pages = free_pages = 0; 464 reserved_pages = free_pages = 0;
567 465
568 for_each_online_node(node) { 466 for_each_bank(i, &meminfo) {
569 for_each_nodebank(i, &meminfo, node) { 467 struct membank *bank = &meminfo.bank[i];
570 struct membank *bank = &meminfo.bank[i]; 468 unsigned int pfn1, pfn2;
571 unsigned int pfn1, pfn2; 469 struct page *page, *end;
572 struct page *page, *end; 470
573 471 pfn1 = bank_pfn_start(bank);
574 pfn1 = bank_pfn_start(bank); 472 pfn2 = bank_pfn_end(bank);
575 pfn2 = bank_pfn_end(bank); 473
576 474 page = pfn_to_page(pfn1);
577 page = pfn_to_page(pfn1); 475 end = pfn_to_page(pfn2 - 1) + 1;
578 end = pfn_to_page(pfn2 - 1) + 1; 476
579 477 do {
580 do { 478 if (PageReserved(page))
581 if (PageReserved(page)) 479 reserved_pages++;
582 reserved_pages++; 480 else if (!page_count(page))
583 else if (!page_count(page)) 481 free_pages++;
584 free_pages++; 482 page++;
585 page++; 483 } while (page < end);
586 } while (page < end);
587 }
588 } 484 }
589 485
590 /* 486 /*
@@ -611,6 +507,10 @@ void __init mem_init(void)
611 507
612 printk(KERN_NOTICE "Virtual kernel memory layout:\n" 508 printk(KERN_NOTICE "Virtual kernel memory layout:\n"
613 " vector : 0x%08lx - 0x%08lx (%4ld kB)\n" 509 " vector : 0x%08lx - 0x%08lx (%4ld kB)\n"
510#ifdef CONFIG_HAVE_TCM
511 " DTCM : 0x%08lx - 0x%08lx (%4ld kB)\n"
512 " ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n"
513#endif
614 " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" 514 " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n"
615#ifdef CONFIG_MMU 515#ifdef CONFIG_MMU
616 " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n" 516 " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n"
@@ -627,6 +527,10 @@ void __init mem_init(void)
627 527
628 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + 528 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
629 (PAGE_SIZE)), 529 (PAGE_SIZE)),
530#ifdef CONFIG_HAVE_TCM
531 MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
532 MLK(ITCM_OFFSET, (unsigned long) itcm_end),
533#endif
630 MLK(FIXADDR_START, FIXADDR_TOP), 534 MLK(FIXADDR_START, FIXADDR_TOP),
631#ifdef CONFIG_MMU 535#ifdef CONFIG_MMU
632 MLM(CONSISTENT_BASE, CONSISTENT_END), 536 MLM(CONSISTENT_BASE, CONSISTENT_END),
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 28c8b950ef04..ab506272b2d3 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -42,78 +42,11 @@
42 */ 42 */
43#define VM_ARM_SECTION_MAPPING 0x80000000 43#define VM_ARM_SECTION_MAPPING 0x80000000
44 44
45static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
46 unsigned long phys_addr, const struct mem_type *type)
47{
48 pgprot_t prot = __pgprot(type->prot_pte);
49 pte_t *pte;
50
51 pte = pte_alloc_kernel(pmd, addr);
52 if (!pte)
53 return -ENOMEM;
54
55 do {
56 if (!pte_none(*pte))
57 goto bad;
58
59 set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
60 phys_addr += PAGE_SIZE;
61 } while (pte++, addr += PAGE_SIZE, addr != end);
62 return 0;
63
64 bad:
65 printk(KERN_CRIT "remap_area_pte: page already exists\n");
66 BUG();
67}
68
69static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
70 unsigned long end, unsigned long phys_addr,
71 const struct mem_type *type)
72{
73 unsigned long next;
74 pmd_t *pmd;
75 int ret = 0;
76
77 pmd = pmd_alloc(&init_mm, pgd, addr);
78 if (!pmd)
79 return -ENOMEM;
80
81 do {
82 next = pmd_addr_end(addr, end);
83 ret = remap_area_pte(pmd, addr, next, phys_addr, type);
84 if (ret)
85 return ret;
86 phys_addr += next - addr;
87 } while (pmd++, addr = next, addr != end);
88 return ret;
89}
90
91static int remap_area_pages(unsigned long start, unsigned long pfn,
92 size_t size, const struct mem_type *type)
93{
94 unsigned long addr = start;
95 unsigned long next, end = start + size;
96 unsigned long phys_addr = __pfn_to_phys(pfn);
97 pgd_t *pgd;
98 int err = 0;
99
100 BUG_ON(addr >= end);
101 pgd = pgd_offset_k(addr);
102 do {
103 next = pgd_addr_end(addr, end);
104 err = remap_area_pmd(pgd, addr, next, phys_addr, type);
105 if (err)
106 break;
107 phys_addr += next - addr;
108 } while (pgd++, addr = next, addr != end);
109
110 return err;
111}
112
113int ioremap_page(unsigned long virt, unsigned long phys, 45int ioremap_page(unsigned long virt, unsigned long phys,
114 const struct mem_type *mtype) 46 const struct mem_type *mtype)
115{ 47{
116 return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype); 48 return ioremap_page_range(virt, virt + PAGE_SIZE, phys,
49 __pgprot(mtype->prot_pte));
117} 50}
118EXPORT_SYMBOL(ioremap_page); 51EXPORT_SYMBOL(ioremap_page);
119 52
@@ -268,6 +201,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
268 if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK)) 201 if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
269 return NULL; 202 return NULL;
270 203
204 /*
205 * Don't allow RAM to be mapped - this causes problems with ARMv6+
206 */
207 if (WARN_ON(pfn_valid(pfn)))
208 return NULL;
209
271 type = get_mem_type(mtype); 210 type = get_mem_type(mtype);
272 if (!type) 211 if (!type)
273 return NULL; 212 return NULL;
@@ -294,7 +233,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
294 err = remap_area_sections(addr, pfn, size, type); 233 err = remap_area_sections(addr, pfn, size, type);
295 } else 234 } else
296#endif 235#endif
297 err = remap_area_pages(addr, pfn, size, type); 236 err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn),
237 __pgprot(type->prot_pte));
298 238
299 if (err) { 239 if (err) {
300 vunmap((void *)addr); 240 vunmap((void *)addr);
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 815d08eecbb0..6630620380a4 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -28,7 +28,5 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
28 28
29#endif 29#endif
30 30
31struct pglist_data;
32
33void __init bootmem_init(void); 31void __init bootmem_init(void);
34void reserve_node_zero(struct pglist_data *pgdat); 32void arm_mm_memblock_reserve(void);
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index f5abc51c5a07..4f5b39687df5 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -7,6 +7,7 @@
7#include <linux/shm.h> 7#include <linux/shm.h>
8#include <linux/sched.h> 8#include <linux/sched.h>
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/random.h>
10#include <asm/cputype.h> 11#include <asm/cputype.h>
11#include <asm/system.h> 12#include <asm/system.h>
12 13
@@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
80 start_addr = addr = TASK_UNMAPPED_BASE; 81 start_addr = addr = TASK_UNMAPPED_BASE;
81 mm->cached_hole_size = 0; 82 mm->cached_hole_size = 0;
82 } 83 }
84 /* 8 bits of randomness in 20 address space bits */
85 if (current->flags & PF_RANDOMIZE)
86 addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
83 87
84full_search: 88full_search:
85 if (do_align) 89 if (do_align)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 285894171186..6e1c4f6a2b3f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -11,13 +11,12 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mman.h> 14#include <linux/mman.h>
16#include <linux/nodemask.h> 15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/sort.h> 17#include <linux/sort.h>
18 18
19#include <asm/cputype.h> 19#include <asm/cputype.h>
20#include <asm/mach-types.h>
21#include <asm/sections.h> 20#include <asm/sections.h>
22#include <asm/cachetype.h> 21#include <asm/cachetype.h>
23#include <asm/setup.h> 22#include <asm/setup.h>
@@ -258,6 +257,19 @@ static struct mem_type mem_types[] = {
258 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 257 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
259 .domain = DOMAIN_KERNEL, 258 .domain = DOMAIN_KERNEL,
260 }, 259 },
260 [MT_MEMORY_DTCM] = {
261 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG |
262 L_PTE_DIRTY | L_PTE_WRITE,
263 .prot_l1 = PMD_TYPE_TABLE,
264 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
265 .domain = DOMAIN_KERNEL,
266 },
267 [MT_MEMORY_ITCM] = {
268 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
269 L_PTE_USER | L_PTE_EXEC,
270 .prot_l1 = PMD_TYPE_TABLE,
271 .domain = DOMAIN_IO,
272 },
261}; 273};
262 274
263const struct mem_type *get_mem_type(unsigned int type) 275const struct mem_type *get_mem_type(unsigned int type)
@@ -488,18 +500,28 @@ static void __init build_mem_type_table(void)
488 500
489#define vectors_base() (vectors_high() ? 0xffff0000 : 0) 501#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
490 502
491static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 503static void __init *early_alloc(unsigned long sz)
492 unsigned long end, unsigned long pfn,
493 const struct mem_type *type)
494{ 504{
495 pte_t *pte; 505 void *ptr = __va(memblock_alloc(sz, sz));
506 memset(ptr, 0, sz);
507 return ptr;
508}
496 509
510static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
511{
497 if (pmd_none(*pmd)) { 512 if (pmd_none(*pmd)) {
498 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); 513 pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
499 __pmd_populate(pmd, __pa(pte) | type->prot_l1); 514 __pmd_populate(pmd, __pa(pte) | prot);
500 } 515 }
516 BUG_ON(pmd_bad(*pmd));
517 return pte_offset_kernel(pmd, addr);
518}
501 519
502 pte = pte_offset_kernel(pmd, addr); 520static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
521 unsigned long end, unsigned long pfn,
522 const struct mem_type *type)
523{
524 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
503 do { 525 do {
504 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); 526 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
505 pfn++; 527 pfn++;
@@ -668,7 +690,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
668 create_mapping(io_desc + i); 690 create_mapping(io_desc + i);
669} 691}
670 692
671static unsigned long __initdata vmalloc_reserve = SZ_128M; 693static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
672 694
673/* 695/*
674 * vmalloc=size forces the vmalloc area to be exactly 'size' 696 * vmalloc=size forces the vmalloc area to be exactly 'size'
@@ -677,7 +699,7 @@ static unsigned long __initdata vmalloc_reserve = SZ_128M;
677 */ 699 */
678static int __init early_vmalloc(char *arg) 700static int __init early_vmalloc(char *arg)
679{ 701{
680 vmalloc_reserve = memparse(arg, NULL); 702 unsigned long vmalloc_reserve = memparse(arg, NULL);
681 703
682 if (vmalloc_reserve < SZ_16M) { 704 if (vmalloc_reserve < SZ_16M) {
683 vmalloc_reserve = SZ_16M; 705 vmalloc_reserve = SZ_16M;
@@ -692,22 +714,26 @@ static int __init early_vmalloc(char *arg)
692 "vmalloc area is too big, limiting to %luMB\n", 714 "vmalloc area is too big, limiting to %luMB\n",
693 vmalloc_reserve >> 20); 715 vmalloc_reserve >> 20);
694 } 716 }
717
718 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
695 return 0; 719 return 0;
696} 720}
697early_param("vmalloc", early_vmalloc); 721early_param("vmalloc", early_vmalloc);
698 722
699#define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) 723phys_addr_t lowmem_end_addr;
700 724
701static void __init sanity_check_meminfo(void) 725static void __init sanity_check_meminfo(void)
702{ 726{
703 int i, j, highmem = 0; 727 int i, j, highmem = 0;
704 728
729 lowmem_end_addr = __pa(vmalloc_min - 1) + 1;
730
705 for (i = 0, j = 0; i < meminfo.nr_banks; i++) { 731 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
706 struct membank *bank = &meminfo.bank[j]; 732 struct membank *bank = &meminfo.bank[j];
707 *bank = meminfo.bank[i]; 733 *bank = meminfo.bank[i];
708 734
709#ifdef CONFIG_HIGHMEM 735#ifdef CONFIG_HIGHMEM
710 if (__va(bank->start) > VMALLOC_MIN || 736 if (__va(bank->start) > vmalloc_min ||
711 __va(bank->start) < (void *)PAGE_OFFSET) 737 __va(bank->start) < (void *)PAGE_OFFSET)
712 highmem = 1; 738 highmem = 1;
713 739
@@ -717,8 +743,8 @@ static void __init sanity_check_meminfo(void)
717 * Split those memory banks which are partially overlapping 743 * Split those memory banks which are partially overlapping
718 * the vmalloc area greatly simplifying things later. 744 * the vmalloc area greatly simplifying things later.
719 */ 745 */
720 if (__va(bank->start) < VMALLOC_MIN && 746 if (__va(bank->start) < vmalloc_min &&
721 bank->size > VMALLOC_MIN - __va(bank->start)) { 747 bank->size > vmalloc_min - __va(bank->start)) {
722 if (meminfo.nr_banks >= NR_BANKS) { 748 if (meminfo.nr_banks >= NR_BANKS) {
723 printk(KERN_CRIT "NR_BANKS too low, " 749 printk(KERN_CRIT "NR_BANKS too low, "
724 "ignoring high memory\n"); 750 "ignoring high memory\n");
@@ -727,12 +753,12 @@ static void __init sanity_check_meminfo(void)
727 (meminfo.nr_banks - i) * sizeof(*bank)); 753 (meminfo.nr_banks - i) * sizeof(*bank));
728 meminfo.nr_banks++; 754 meminfo.nr_banks++;
729 i++; 755 i++;
730 bank[1].size -= VMALLOC_MIN - __va(bank->start); 756 bank[1].size -= vmalloc_min - __va(bank->start);
731 bank[1].start = __pa(VMALLOC_MIN - 1) + 1; 757 bank[1].start = __pa(vmalloc_min - 1) + 1;
732 bank[1].highmem = highmem = 1; 758 bank[1].highmem = highmem = 1;
733 j++; 759 j++;
734 } 760 }
735 bank->size = VMALLOC_MIN - __va(bank->start); 761 bank->size = vmalloc_min - __va(bank->start);
736 } 762 }
737#else 763#else
738 bank->highmem = highmem; 764 bank->highmem = highmem;
@@ -741,7 +767,7 @@ static void __init sanity_check_meminfo(void)
741 * Check whether this memory bank would entirely overlap 767 * Check whether this memory bank would entirely overlap
742 * the vmalloc area. 768 * the vmalloc area.
743 */ 769 */
744 if (__va(bank->start) >= VMALLOC_MIN || 770 if (__va(bank->start) >= vmalloc_min ||
745 __va(bank->start) < (void *)PAGE_OFFSET) { 771 __va(bank->start) < (void *)PAGE_OFFSET) {
746 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " 772 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
747 "(vmalloc region overlap).\n", 773 "(vmalloc region overlap).\n",
@@ -753,9 +779,9 @@ static void __init sanity_check_meminfo(void)
753 * Check whether this memory bank would partially overlap 779 * Check whether this memory bank would partially overlap
754 * the vmalloc area. 780 * the vmalloc area.
755 */ 781 */
756 if (__va(bank->start + bank->size) > VMALLOC_MIN || 782 if (__va(bank->start + bank->size) > vmalloc_min ||
757 __va(bank->start + bank->size) < __va(bank->start)) { 783 __va(bank->start + bank->size) < __va(bank->start)) {
758 unsigned long newsize = VMALLOC_MIN - __va(bank->start); 784 unsigned long newsize = vmalloc_min - __va(bank->start);
759 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " 785 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
760 "to -%.8lx (vmalloc region overlap).\n", 786 "to -%.8lx (vmalloc region overlap).\n",
761 bank->start, bank->start + bank->size - 1, 787 bank->start, bank->start + bank->size - 1,
@@ -827,101 +853,23 @@ static inline void prepare_page_table(void)
827} 853}
828 854
829/* 855/*
830 * Reserve the various regions of node 0 856 * Reserve the special regions of memory
831 */ 857 */
832void __init reserve_node_zero(pg_data_t *pgdat) 858void __init arm_mm_memblock_reserve(void)
833{ 859{
834 unsigned long res_size = 0;
835
836 /*
837 * Register the kernel text and data with bootmem.
838 * Note that this can only be in node 0.
839 */
840#ifdef CONFIG_XIP_KERNEL
841 reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
842 BOOTMEM_DEFAULT);
843#else
844 reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
845 BOOTMEM_DEFAULT);
846#endif
847
848 /* 860 /*
849 * Reserve the page tables. These are already in use, 861 * Reserve the page tables. These are already in use,
850 * and can only be in node 0. 862 * and can only be in node 0.
851 */ 863 */
852 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), 864 memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
853 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
854
855 /*
856 * Hmm... This should go elsewhere, but we really really need to
857 * stop things allocating the low memory; ideally we need a better
858 * implementation of GFP_DMA which does not assume that DMA-able
859 * memory starts at zero.
860 */
861 if (machine_is_integrator() || machine_is_cintegrator())
862 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
863
864 /*
865 * These should likewise go elsewhere. They pre-reserve the
866 * screen memory region at the start of main system memory.
867 */
868 if (machine_is_edb7211())
869 res_size = 0x00020000;
870 if (machine_is_p720t())
871 res_size = 0x00014000;
872
873 /* H1940, RX3715 and RX1950 need to reserve this for suspend */
874
875 if (machine_is_h1940() || machine_is_rx3715()
876 || machine_is_rx1950()) {
877 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
878 BOOTMEM_DEFAULT);
879 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
880 BOOTMEM_DEFAULT);
881 }
882
883 if (machine_is_palmld() || machine_is_palmtx()) {
884 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
885 BOOTMEM_EXCLUSIVE);
886 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
887 BOOTMEM_EXCLUSIVE);
888 }
889
890 if (machine_is_treo680() || machine_is_centro()) {
891 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
892 BOOTMEM_EXCLUSIVE);
893 reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
894 BOOTMEM_EXCLUSIVE);
895 }
896
897 if (machine_is_palmt5())
898 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
899 BOOTMEM_EXCLUSIVE);
900
901 /*
902 * U300 - This platform family can share physical memory
903 * between two ARM cpus, one running Linux and the other
904 * running another OS.
905 */
906 if (machine_is_u300()) {
907#ifdef CONFIG_MACH_U300_SINGLE_RAM
908#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
909 CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
910 res_size = 0x00100000;
911#endif
912#endif
913 }
914 865
915#ifdef CONFIG_SA1111 866#ifdef CONFIG_SA1111
916 /* 867 /*
917 * Because of the SA1111 DMA bug, we want to preserve our 868 * Because of the SA1111 DMA bug, we want to preserve our
918 * precious DMA-able memory... 869 * precious DMA-able memory...
919 */ 870 */
920 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; 871 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
921#endif 872#endif
922 if (res_size)
923 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
924 BOOTMEM_DEFAULT);
925} 873}
926 874
927/* 875/*
@@ -940,7 +888,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
940 /* 888 /*
941 * Allocate the vector page early. 889 * Allocate the vector page early.
942 */ 890 */
943 vectors = alloc_bootmem_low_pages(PAGE_SIZE); 891 vectors = early_alloc(PAGE_SIZE);
944 892
945 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) 893 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
946 pmd_clear(pmd_off_k(addr)); 894 pmd_clear(pmd_off_k(addr));
@@ -1011,11 +959,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
1011static void __init kmap_init(void) 959static void __init kmap_init(void)
1012{ 960{
1013#ifdef CONFIG_HIGHMEM 961#ifdef CONFIG_HIGHMEM
1014 pmd_t *pmd = pmd_off_k(PKMAP_BASE); 962 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1015 pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); 963 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1016 BUG_ON(!pmd_none(*pmd) || !pte);
1017 __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE);
1018 pkmap_page_table = pte + PTRS_PER_PTE;
1019#endif 964#endif
1020} 965}
1021 966
@@ -1066,17 +1011,16 @@ void __init paging_init(struct machine_desc *mdesc)
1066 sanity_check_meminfo(); 1011 sanity_check_meminfo();
1067 prepare_page_table(); 1012 prepare_page_table();
1068 map_lowmem(); 1013 map_lowmem();
1069 bootmem_init();
1070 devicemaps_init(mdesc); 1014 devicemaps_init(mdesc);
1071 kmap_init(); 1015 kmap_init();
1072 1016
1073 top_pmd = pmd_off_k(0xffff0000); 1017 top_pmd = pmd_off_k(0xffff0000);
1074 1018
1075 /* 1019 /* allocate the zero page. */
1076 * allocate the zero page. Note that this always succeeds and 1020 zero_page = early_alloc(PAGE_SIZE);
1077 * returns a zeroed result. 1021
1078 */ 1022 bootmem_init();
1079 zero_page = alloc_bootmem_low_pages(PAGE_SIZE); 1023
1080 empty_zero_page = virt_to_page(zero_page); 1024 empty_zero_page = virt_to_page(zero_page);
1081 __flush_dcache_page(NULL, empty_zero_page); 1025 __flush_dcache_page(NULL, empty_zero_page);
1082} 1026}
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 33b327379f07..687d02319a41 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -6,8 +6,8 @@
6#include <linux/module.h> 6#include <linux/module.h>
7#include <linux/mm.h> 7#include <linux/mm.h>
8#include <linux/pagemap.h> 8#include <linux/pagemap.h>
9#include <linux/bootmem.h>
10#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/memblock.h>
11 11
12#include <asm/cacheflush.h> 12#include <asm/cacheflush.h>
13#include <asm/sections.h> 13#include <asm/sections.h>
@@ -17,30 +17,14 @@
17 17
18#include "mm.h" 18#include "mm.h"
19 19
20/* 20void __init arm_mm_memblock_reserve(void)
21 * Reserve the various regions of node 0
22 */
23void __init reserve_node_zero(pg_data_t *pgdat)
24{ 21{
25 /* 22 /*
26 * Register the kernel text and data with bootmem.
27 * Note that this can only be in node 0.
28 */
29#ifdef CONFIG_XIP_KERNEL
30 reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
31 BOOTMEM_DEFAULT);
32#else
33 reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
34 BOOTMEM_DEFAULT);
35#endif
36
37 /*
38 * Register the exception vector page. 23 * Register the exception vector page.
39 * some architectures which the DRAM is the exception vector to trap, 24 * some architectures which the DRAM is the exception vector to trap,
40 * alloc_page breaks with error, although it is not NULL, but "0." 25 * alloc_page breaks with error, although it is not NULL, but "0."
41 */ 26 */
42 reserve_bootmem_node(pgdat, CONFIG_VECTORS_BASE, PAGE_SIZE, 27 memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
43 BOOTMEM_DEFAULT);
44} 28}
45 29
46/* 30/*
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 72507c630ceb..203a4e944d9e 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init)
79 * cpu_arm1020_proc_fin() 79 * cpu_arm1020_proc_fin()
80 */ 80 */
81ENTRY(cpu_arm1020_proc_fin) 81ENTRY(cpu_arm1020_proc_fin)
82 stmfd sp!, {lr}
83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 msr cpsr_c, ip
85 bl arm1020_flush_kern_cache_all
86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
87 bic r0, r0, #0x1000 @ ...i............ 83 bic r0, r0, #0x1000 @ ...i............
88 bic r0, r0, #0x000e @ ............wca. 84 bic r0, r0, #0x000e @ ............wca.
89 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 ldmfd sp!, {pc} 86 mov pc, lr
91 87
92/* 88/*
93 * cpu_arm1020_reset(loc) 89 * cpu_arm1020_reset(loc)
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index d27829805609..1a511e765909 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init)
79 * cpu_arm1020e_proc_fin() 79 * cpu_arm1020e_proc_fin()
80 */ 80 */
81ENTRY(cpu_arm1020e_proc_fin) 81ENTRY(cpu_arm1020e_proc_fin)
82 stmfd sp!, {lr}
83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 msr cpsr_c, ip
85 bl arm1020e_flush_kern_cache_all
86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
87 bic r0, r0, #0x1000 @ ...i............ 83 bic r0, r0, #0x1000 @ ...i............
88 bic r0, r0, #0x000e @ ............wca. 84 bic r0, r0, #0x000e @ ............wca.
89 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 ldmfd sp!, {pc} 86 mov pc, lr
91 87
92/* 88/*
93 * cpu_arm1020e_reset(loc) 89 * cpu_arm1020e_reset(loc)
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index ce13e4a827de..1ffa4eb9c34f 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init)
68 * cpu_arm1022_proc_fin() 68 * cpu_arm1022_proc_fin()
69 */ 69 */
70ENTRY(cpu_arm1022_proc_fin) 70ENTRY(cpu_arm1022_proc_fin)
71 stmfd sp!, {lr}
72 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
73 msr cpsr_c, ip
74 bl arm1022_flush_kern_cache_all
75 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
76 bic r0, r0, #0x1000 @ ...i............ 72 bic r0, r0, #0x1000 @ ...i............
77 bic r0, r0, #0x000e @ ............wca. 73 bic r0, r0, #0x000e @ ............wca.
78 mcr p15, 0, r0, c1, c0, 0 @ disable caches 74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 ldmfd sp!, {pc} 75 mov pc, lr
80 76
81/* 77/*
82 * cpu_arm1022_reset(loc) 78 * cpu_arm1022_reset(loc)
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 636672a29c6d..5697c34b95b0 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init)
68 * cpu_arm1026_proc_fin() 68 * cpu_arm1026_proc_fin()
69 */ 69 */
70ENTRY(cpu_arm1026_proc_fin) 70ENTRY(cpu_arm1026_proc_fin)
71 stmfd sp!, {lr}
72 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
73 msr cpsr_c, ip
74 bl arm1026_flush_kern_cache_all
75 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
76 bic r0, r0, #0x1000 @ ...i............ 72 bic r0, r0, #0x1000 @ ...i............
77 bic r0, r0, #0x000e @ ............wca. 73 bic r0, r0, #0x000e @ ............wca.
78 mcr p15, 0, r0, c1, c0, 0 @ disable caches 74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 ldmfd sp!, {pc} 75 mov pc, lr
80 76
81/* 77/*
82 * cpu_arm1026_reset(loc) 78 * cpu_arm1026_reset(loc)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 795dc615f43b..64e0b327c7c5 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init)
184 184
185ENTRY(cpu_arm6_proc_fin) 185ENTRY(cpu_arm6_proc_fin)
186ENTRY(cpu_arm7_proc_fin) 186ENTRY(cpu_arm7_proc_fin)
187 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
188 msr cpsr_c, r0
189 mov r0, #0x31 @ ....S..DP...M 187 mov r0, #0x31 @ ....S..DP...M
190 mcr p15, 0, r0, c1, c0, 0 @ disable caches 188 mcr p15, 0, r0, c1, c0, 0 @ disable caches
191 mov pc, lr 189 mov pc, lr
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0b62de244666..9d96824134fc 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init)
54 mov pc, lr 54 mov pc, lr
55 55
56ENTRY(cpu_arm720_proc_fin) 56ENTRY(cpu_arm720_proc_fin)
57 stmfd sp!, {lr}
58 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
59 msr cpsr_c, ip
60 mrc p15, 0, r0, c1, c0, 0 57 mrc p15, 0, r0, c1, c0, 0
61 bic r0, r0, #0x1000 @ ...i............ 58 bic r0, r0, #0x1000 @ ...i............
62 bic r0, r0, #0x000e @ ............wca. 59 bic r0, r0, #0x000e @ ............wca.
63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 61 mov pc, lr
65 ldmfd sp!, {pc}
66 62
67/* 63/*
68 * Function: arm720_proc_do_idle(void) 64 * Function: arm720_proc_do_idle(void)
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 01860cdeb2ec..6c1a9ab059ae 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm)
36 * cpu_arm740_proc_fin() 36 * cpu_arm740_proc_fin()
37 */ 37 */
38ENTRY(cpu_arm740_proc_fin) 38ENTRY(cpu_arm740_proc_fin)
39 stmfd sp!, {lr}
40 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
41 msr cpsr_c, ip
42 mrc p15, 0, r0, c1, c0, 0 39 mrc p15, 0, r0, c1, c0, 0
43 bic r0, r0, #0x3f000000 @ bank/f/lock/s 40 bic r0, r0, #0x3f000000 @ bank/f/lock/s
44 bic r0, r0, #0x0000000c @ w-buffer/cache 41 bic r0, r0, #0x0000000c @ w-buffer/cache
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
46 mcr p15, 0, r0, c7, c0, 0 @ invalidate cache 43 mov pc, lr
47 ldmfd sp!, {pc}
48 44
49/* 45/*
50 * cpu_arm740_reset(loc) 46 * cpu_arm740_reset(loc)
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 1201b9863829..6a850dbba22e 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm)
36 * cpu_arm7tdmi_proc_fin() 36 * cpu_arm7tdmi_proc_fin()
37 */ 37 */
38ENTRY(cpu_arm7tdmi_proc_fin) 38ENTRY(cpu_arm7tdmi_proc_fin)
39 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
40 msr cpsr_c, r0
41 mov pc, lr 39 mov pc, lr
42 40
43/* 41/*
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 8be81992645d..86f80aa56216 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init)
69 * cpu_arm920_proc_fin() 69 * cpu_arm920_proc_fin()
70 */ 70 */
71ENTRY(cpu_arm920_proc_fin) 71ENTRY(cpu_arm920_proc_fin)
72 stmfd sp!, {lr}
73 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
74 msr cpsr_c, ip
75#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
76 bl arm920_flush_kern_cache_all
77#else
78 bl v4wt_flush_kern_cache_all
79#endif
80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............ 73 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca. 74 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
84 ldmfd sp!, {pc} 76 mov pc, lr
85 77
86/* 78/*
87 * cpu_arm920_reset(loc) 79 * cpu_arm920_reset(loc)
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index c0ff8e4b1074..f76ce9b62883 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init)
71 * cpu_arm922_proc_fin() 71 * cpu_arm922_proc_fin()
72 */ 72 */
73ENTRY(cpu_arm922_proc_fin) 73ENTRY(cpu_arm922_proc_fin)
74 stmfd sp!, {lr}
75 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
76 msr cpsr_c, ip
77#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
78 bl arm922_flush_kern_cache_all
79#else
80 bl v4wt_flush_kern_cache_all
81#endif
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............ 75 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca. 76 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 ldmfd sp!, {pc} 78 mov pc, lr
87 79
88/* 80/*
89 * cpu_arm922_reset(loc) 81 * cpu_arm922_reset(loc)
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 3c6cffe400f6..657bd3f7c153 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init)
92 * cpu_arm925_proc_fin() 92 * cpu_arm925_proc_fin()
93 */ 93 */
94ENTRY(cpu_arm925_proc_fin) 94ENTRY(cpu_arm925_proc_fin)
95 stmfd sp!, {lr}
96 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
97 msr cpsr_c, ip
98 bl arm925_flush_kern_cache_all
99 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
100 bic r0, r0, #0x1000 @ ...i............ 96 bic r0, r0, #0x1000 @ ...i............
101 bic r0, r0, #0x000e @ ............wca. 97 bic r0, r0, #0x000e @ ............wca.
102 mcr p15, 0, r0, c1, c0, 0 @ disable caches 98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
103 ldmfd sp!, {pc} 99 mov pc, lr
104 100
105/* 101/*
106 * cpu_arm925_reset(loc) 102 * cpu_arm925_reset(loc)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 75b707c9cce1..73f1f3c68910 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init)
61 * cpu_arm926_proc_fin() 61 * cpu_arm926_proc_fin()
62 */ 62 */
63ENTRY(cpu_arm926_proc_fin) 63ENTRY(cpu_arm926_proc_fin)
64 stmfd sp!, {lr}
65 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
66 msr cpsr_c, ip
67 bl arm926_flush_kern_cache_all
68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 bic r0, r0, #0x1000 @ ...i............ 65 bic r0, r0, #0x1000 @ ...i............
70 bic r0, r0, #0x000e @ ............wca. 66 bic r0, r0, #0x000e @ ............wca.
71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 ldmfd sp!, {pc} 68 mov pc, lr
73 69
74/* 70/*
75 * cpu_arm926_reset(loc) 71 * cpu_arm926_reset(loc)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 1af1657819eb..fffb061a45a5 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm)
37 * cpu_arm940_proc_fin() 37 * cpu_arm940_proc_fin()
38 */ 38 */
39ENTRY(cpu_arm940_proc_fin) 39ENTRY(cpu_arm940_proc_fin)
40 stmfd sp!, {lr}
41 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
42 msr cpsr_c, ip
43 bl arm940_flush_kern_cache_all
44 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
45 bic r0, r0, #0x00001000 @ i-cache 41 bic r0, r0, #0x00001000 @ i-cache
46 bic r0, r0, #0x00000004 @ d-cache 42 bic r0, r0, #0x00000004 @ d-cache
47 mcr p15, 0, r0, c1, c0, 0 @ disable caches 43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
48 ldmfd sp!, {pc} 44 mov pc, lr
49 45
50/* 46/*
51 * cpu_arm940_reset(loc) 47 * cpu_arm940_reset(loc)
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1664b6aaff79..249a6053760a 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm)
44 * cpu_arm946_proc_fin() 44 * cpu_arm946_proc_fin()
45 */ 45 */
46ENTRY(cpu_arm946_proc_fin) 46ENTRY(cpu_arm946_proc_fin)
47 stmfd sp!, {lr}
48 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
49 msr cpsr_c, ip
50 bl arm946_flush_kern_cache_all
51 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 bic r0, r0, #0x00001000 @ i-cache 48 bic r0, r0, #0x00001000 @ i-cache
53 bic r0, r0, #0x00000004 @ d-cache 49 bic r0, r0, #0x00000004 @ d-cache
54 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 ldmfd sp!, {pc} 51 mov pc, lr
56 52
57/* 53/*
58 * cpu_arm946_reset(loc) 54 * cpu_arm946_reset(loc)
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 28545c29dbcd..db475667fac2 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm)
36 * cpu_arm9tdmi_proc_fin() 36 * cpu_arm9tdmi_proc_fin()
37 */ 37 */
38ENTRY(cpu_arm9tdmi_proc_fin) 38ENTRY(cpu_arm9tdmi_proc_fin)
39 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
40 msr cpsr_c, r0
41 mov pc, lr 39 mov pc, lr
42 40
43/* 41/*
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 08f5ac237ad4..7803fdf70029 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init)
39 * cpu_fa526_proc_fin() 39 * cpu_fa526_proc_fin()
40 */ 40 */
41ENTRY(cpu_fa526_proc_fin) 41ENTRY(cpu_fa526_proc_fin)
42 stmfd sp!, {lr}
43 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
44 msr cpsr_c, ip
45 bl fa_flush_kern_cache_all
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............ 43 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x000e @ ............wca. 44 bic r0, r0, #0x000e @ ............wca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches 45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 nop 46 nop
51 nop 47 nop
52 ldmfd sp!, {pc} 48 mov pc, lr
53 49
54/* 50/*
55 * cpu_fa526_reset(loc) 51 * cpu_fa526_reset(loc)
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 53e632343849..b304d0104a4e 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init)
75 * cpu_feroceon_proc_fin() 75 * cpu_feroceon_proc_fin()
76 */ 76 */
77ENTRY(cpu_feroceon_proc_fin) 77ENTRY(cpu_feroceon_proc_fin)
78 stmfd sp!, {lr}
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
80 msr cpsr_c, ip
81 bl feroceon_flush_kern_cache_all
82
83#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 78#if defined(CONFIG_CACHE_FEROCEON_L2) && \
84 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 79 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
85 mov r0, #0 80 mov r0, #0
@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
91 bic r0, r0, #0x1000 @ ...i............ 86 bic r0, r0, #0x1000 @ ...i............
92 bic r0, r0, #0x000e @ ............wca. 87 bic r0, r0, #0x000e @ ............wca.
93 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
94 ldmfd sp!, {pc} 89 mov pc, lr
95 90
96/* 91/*
97 * cpu_feroceon_reset(loc) 92 * cpu_feroceon_reset(loc)
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index caa31154e7db..5f6892fcc167 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init)
51 * cpu_mohawk_proc_fin() 51 * cpu_mohawk_proc_fin()
52 */ 52 */
53ENTRY(cpu_mohawk_proc_fin) 53ENTRY(cpu_mohawk_proc_fin)
54 stmfd sp!, {lr}
55 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
56 msr cpsr_c, ip
57 bl mohawk_flush_kern_cache_all
58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
59 bic r0, r0, #0x1800 @ ...iz........... 55 bic r0, r0, #0x1800 @ ...iz...........
60 bic r0, r0, #0x0006 @ .............ca. 56 bic r0, r0, #0x0006 @ .............ca.
61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 ldmfd sp!, {pc} 58 mov pc, lr
63 59
64/* 60/*
65 * cpu_mohawk_reset(loc) 61 * cpu_mohawk_reset(loc)
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 7b706b389906..a201eb04b5e1 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
44 * cpu_sa110_proc_fin() 44 * cpu_sa110_proc_fin()
45 */ 45 */
46ENTRY(cpu_sa110_proc_fin) 46ENTRY(cpu_sa110_proc_fin)
47 stmfd sp!, {lr} 47 mov r0, #0
48 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
49 msr cpsr_c, ip
50 bl v4wb_flush_kern_cache_all @ clean caches
511: mov r0, #0
52 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
53 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
54 bic r0, r0, #0x1000 @ ...i............ 50 bic r0, r0, #0x1000 @ ...i............
55 bic r0, r0, #0x000e @ ............wca. 51 bic r0, r0, #0x000e @ ............wca.
56 mcr p15, 0, r0, c1, c0, 0 @ disable caches 52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 ldmfd sp!, {pc} 53 mov pc, lr
58 54
59/* 55/*
60 * cpu_sa110_reset(loc) 56 * cpu_sa110_reset(loc)
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 5c47760c2064..7ddc4805bf97 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init)
55 * - Clean and turn off caches. 55 * - Clean and turn off caches.
56 */ 56 */
57ENTRY(cpu_sa1100_proc_fin) 57ENTRY(cpu_sa1100_proc_fin)
58 stmfd sp!, {lr}
59 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
60 msr cpsr_c, ip
61 bl v4wb_flush_kern_cache_all
62 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 58 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
63 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 59 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
64 bic r0, r0, #0x1000 @ ...i............ 60 bic r0, r0, #0x1000 @ ...i............
65 bic r0, r0, #0x000e @ ............wca. 61 bic r0, r0, #0x000e @ ............wca.
66 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, r0, c1, c0, 0 @ disable caches
67 ldmfd sp!, {pc} 63 mov pc, lr
68 64
69/* 65/*
70 * cpu_sa1100_reset(loc) 66 * cpu_sa1100_reset(loc)
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7a5337ed7d68..22aac8515196 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init)
42 mov pc, lr 42 mov pc, lr
43 43
44ENTRY(cpu_v6_proc_fin) 44ENTRY(cpu_v6_proc_fin)
45 stmfd sp!, {lr}
46 cpsid if @ disable interrupts
47 bl v6_flush_kern_cache_all
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 45 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............ 46 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x0006 @ .............ca. 47 bic r0, r0, #0x0006 @ .............ca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 48 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 ldmfd sp!, {pc} 49 mov pc, lr
53 50
54/* 51/*
55 * cpu_v6_reset(loc) 52 * cpu_v6_reset(loc)
@@ -239,7 +236,8 @@ __v6_proc_info:
239 b __v6_setup 236 b __v6_setup
240 .long cpu_arch_name 237 .long cpu_arch_name
241 .long cpu_elf_name 238 .long cpu_elf_name
242 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA 239 /* See also feat_v6_fixup() for HWCAP_TLS */
240 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
243 .long cpu_v6_name 241 .long cpu_v6_name
244 .long v6_processor_functions 242 .long v6_processor_functions
245 .long v6wbi_tlb_fns 243 .long v6wbi_tlb_fns
@@ -262,7 +260,7 @@ __pj4_v6_proc_info:
262 b __v6_setup 260 b __v6_setup
263 .long cpu_arch_name 261 .long cpu_arch_name
264 .long cpu_elf_name 262 .long cpu_elf_name
265 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 263 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
266 .long cpu_pj4_name 264 .long cpu_pj4_name
267 .long v6_processor_functions 265 .long v6_processor_functions
268 .long v6wbi_tlb_fns 266 .long v6wbi_tlb_fns
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a3b7aa..6a8506d99ee9 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init)
45ENDPROC(cpu_v7_proc_init) 45ENDPROC(cpu_v7_proc_init)
46 46
47ENTRY(cpu_v7_proc_fin) 47ENTRY(cpu_v7_proc_fin)
48 stmfd sp!, {lr}
49 cpsid if @ disable interrupts
50 bl v7_flush_kern_cache_all
51 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 bic r0, r0, #0x1000 @ ...i............ 49 bic r0, r0, #0x1000 @ ...i............
53 bic r0, r0, #0x0006 @ .............ca. 50 bic r0, r0, #0x0006 @ .............ca.
54 mcr p15, 0, r0, c1, c0, 0 @ disable caches 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 ldmfd sp!, {pc} 52 mov pc, lr
56ENDPROC(cpu_v7_proc_fin) 53ENDPROC(cpu_v7_proc_fin)
57 54
58/* 55/*
@@ -344,7 +341,7 @@ __v7_proc_info:
344 b __v7_setup 341 b __v7_setup
345 .long cpu_arch_name 342 .long cpu_arch_name
346 .long cpu_elf_name 343 .long cpu_elf_name
347 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 344 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
348 .long cpu_v7_name 345 .long cpu_v7_name
349 .long v7_processor_functions 346 .long v7_processor_functions
350 .long v7wbi_tlb_fns 347 .long v7wbi_tlb_fns
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e5797f1c1db7..361a51e49030 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init)
90 * cpu_xsc3_proc_fin() 90 * cpu_xsc3_proc_fin()
91 */ 91 */
92ENTRY(cpu_xsc3_proc_fin) 92ENTRY(cpu_xsc3_proc_fin)
93 str lr, [sp, #-4]!
94 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
95 msr cpsr_c, r0
96 bl xsc3_flush_kern_cache_all @ clean caches
97 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 93 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
98 bic r0, r0, #0x1800 @ ...IZ........... 94 bic r0, r0, #0x1800 @ ...IZ...........
99 bic r0, r0, #0x0006 @ .............CA. 95 bic r0, r0, #0x0006 @ .............CA.
100 mcr p15, 0, r0, c1, c0, 0 @ disable caches 96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
101 ldr pc, [sp], #4 97 mov pc, lr
102 98
103/* 99/*
104 * cpu_xsc3_reset(loc) 100 * cpu_xsc3_reset(loc)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 63037e2162f2..14075979bcba 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init)
124 * cpu_xscale_proc_fin() 124 * cpu_xscale_proc_fin()
125 */ 125 */
126ENTRY(cpu_xscale_proc_fin) 126ENTRY(cpu_xscale_proc_fin)
127 str lr, [sp, #-4]!
128 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
129 msr cpsr_c, r0
130 bl xscale_flush_kern_cache_all @ clean caches
131 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
132 bic r0, r0, #0x1800 @ ...IZ........... 128 bic r0, r0, #0x1800 @ ...IZ...........
133 bic r0, r0, #0x0006 @ .............CA. 129 bic r0, r0, #0x0006 @ .............CA.
134 mcr p15, 0, r0, c1, c0, 0 @ disable caches 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
135 ldr pc, [sp], #4 131 mov pc, lr
136 132
137/* 133/*
138 * cpu_xscale_reset(loc) 134 * cpu_xscale_reset(loc)
diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
index 19e09bdb1b8a..935993e1b1ef 100644
--- a/arch/arm/mm/vmregion.c
+++ b/arch/arm/mm/vmregion.c
@@ -35,7 +35,8 @@
35 */ 35 */
36 36
37struct arm_vmregion * 37struct arm_vmregion *
38arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp) 38arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
39 size_t size, gfp_t gfp)
39{ 40{
40 unsigned long addr = head->vm_start, end = head->vm_end - size; 41 unsigned long addr = head->vm_start, end = head->vm_end - size;
41 unsigned long flags; 42 unsigned long flags;
@@ -58,7 +59,7 @@ arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp)
58 goto nospc; 59 goto nospc;
59 if ((addr + size) <= c->vm_start) 60 if ((addr + size) <= c->vm_start)
60 goto found; 61 goto found;
61 addr = c->vm_end; 62 addr = ALIGN(c->vm_end, align);
62 if (addr > end) 63 if (addr > end)
63 goto nospc; 64 goto nospc;
64 } 65 }
diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h
index 6b2cdbdf3a85..15e9f044db9f 100644
--- a/arch/arm/mm/vmregion.h
+++ b/arch/arm/mm/vmregion.h
@@ -21,7 +21,7 @@ struct arm_vmregion {
21 int vm_active; 21 int vm_active;
22}; 22};
23 23
24struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, gfp_t); 24struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t);
25struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long); 25struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long);
26struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long); 26struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long);
27void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *); 27void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *);
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index ce31f316ac75..43f2b158237c 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -359,7 +359,7 @@ static void __init iop3xx_atu_debug(void)
359 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); 359 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
360 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); 360 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
361 361
362 hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); 362 hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
363} 363}
364 364
365/* for platforms that might be host-bus-adapters */ 365/* for platforms that might be host-bus-adapters */
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 6c8a02ad98e3..85d3e55ca4a9 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -29,6 +29,11 @@
29#include <mach/time.h> 29#include <mach/time.h>
30 30
31/* 31/*
32 * Minimum clocksource/clockevent timer range in seconds
33 */
34#define IOP_MIN_RANGE 4
35
36/*
32 * IOP clocksource (free-running timer 1). 37 * IOP clocksource (free-running timer 1).
33 */ 38 */
34static cycle_t iop_clocksource_read(struct clocksource *unused) 39static cycle_t iop_clocksource_read(struct clocksource *unused)
@@ -44,27 +49,6 @@ static struct clocksource iop_clocksource = {
44 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 49 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
45}; 50};
46 51
47static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
48{
49 u64 temp;
50 u32 shift;
51
52 /* Find shift and mult values for hz. */
53 shift = 32;
54 do {
55 temp = (u64) NSEC_PER_SEC << shift;
56 do_div(temp, hz);
57 if ((temp >> 32) == 0)
58 break;
59 } while (--shift != 0);
60
61 cs->shift = shift;
62 cs->mult = (u32) temp;
63
64 printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
65 cs->name, cs->shift, cs->mult);
66}
67
68/* 52/*
69 * IOP sched_clock() implementation via its clocksource. 53 * IOP sched_clock() implementation via its clocksource.
70 */ 54 */
@@ -130,27 +114,6 @@ static struct clock_event_device iop_clockevent = {
130 .set_mode = iop_set_mode, 114 .set_mode = iop_set_mode,
131}; 115};
132 116
133static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
134{
135 u64 temp;
136 u32 shift;
137
138 /* Find shift and mult values for hz. */
139 shift = 32;
140 do {
141 temp = (u64) hz << shift;
142 do_div(temp, NSEC_PER_SEC);
143 if ((temp >> 32) == 0)
144 break;
145 } while (--shift != 0);
146
147 ce->shift = shift;
148 ce->mult = (u32) temp;
149
150 printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
151 ce->name, ce->shift, ce->mult);
152}
153
154static irqreturn_t 117static irqreturn_t
155iop_timer_interrupt(int irq, void *dev_id) 118iop_timer_interrupt(int irq, void *dev_id)
156{ 119{
@@ -190,7 +153,8 @@ void __init iop_init_time(unsigned long tick_rate)
190 */ 153 */
191 write_tmr0(timer_ctl & ~IOP_TMR_EN); 154 write_tmr0(timer_ctl & ~IOP_TMR_EN);
192 setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); 155 setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
193 iop_clockevent_set_hz(&iop_clockevent, tick_rate); 156 clockevents_calc_mult_shift(&iop_clockevent,
157 tick_rate, IOP_MIN_RANGE);
194 iop_clockevent.max_delta_ns = 158 iop_clockevent.max_delta_ns =
195 clockevent_delta2ns(0xfffffffe, &iop_clockevent); 159 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
196 iop_clockevent.min_delta_ns = 160 iop_clockevent.min_delta_ns =
@@ -207,6 +171,7 @@ void __init iop_init_time(unsigned long tick_rate)
207 write_trr1(0xffffffff); 171 write_trr1(0xffffffff);
208 write_tcr1(0xffffffff); 172 write_tcr1(0xffffffff);
209 write_tmr1(timer_ctl); 173 write_tmr1(timer_ctl);
210 iop_clocksource_set_hz(&iop_clocksource, tick_rate); 174 clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
175 IOP_MIN_RANGE);
211 clocksource_register(&iop_clocksource); 176 clocksource_register(&iop_clocksource);
212} 177}
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
new file mode 100644
index 000000000000..639c54a07992
--- /dev/null
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -0,0 +1,202 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <linux/smsc911x.h>
19
20#include <mach/hardware.h>
21
22/* LAN9217 ethernet base address */
23#define LAN9217_BASE_ADDR(n) (n + 0x0)
24/* External UART */
25#define UARTA_BASE_ADDR(n) (n + 0x8000)
26#define UARTB_BASE_ADDR(n) (n + 0x10000)
27
28#define BOARD_IO_ADDR(n) (n + 0x20000)
29/* LED switchs */
30#define LED_SWITCH_REG 0x00
31/* buttons */
32#define SWITCH_BUTTONS_REG 0x08
33/* status, interrupt */
34#define INTR_STATUS_REG 0x10
35#define INTR_MASK_REG 0x38
36#define INTR_RESET_REG 0x20
37/* magic word for debug CPLD */
38#define MAGIC_NUMBER1_REG 0x40
39#define MAGIC_NUMBER2_REG 0x48
40/* CPLD code version */
41#define CPLD_CODE_VER_REG 0x50
42/* magic word for debug CPLD */
43#define MAGIC_NUMBER3_REG 0x58
44/* module reset register*/
45#define MODULE_RESET_REG 0x60
46/* CPU ID and Personality ID */
47#define MCU_BOARD_ID_REG 0x68
48
49#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START)
50#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_INTERNAL_IRQS)
51
52#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
53#define MXC_MAX_EXP_IO_LINES 16
54
55/* interrupts like external uart , external ethernet etc*/
56#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0)
57#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1)
58#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2)
59#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3)
60#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4)
61
62static void __iomem *brd_io;
63static void expio_ack_irq(u32 irq);
64
65static struct resource smsc911x_resources[] = {
66 {
67 .flags = IORESOURCE_MEM,
68 } , {
69 .start = EXPIO_INT_ENET,
70 .end = EXPIO_INT_ENET,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75static struct smsc911x_platform_config smsc911x_config = {
76 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
77 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
78};
79
80static struct platform_device smsc_lan9217_device = {
81 .name = "smsc911x",
82 .id = 0,
83 .dev = {
84 .platform_data = &smsc911x_config,
85 },
86 .num_resources = ARRAY_SIZE(smsc911x_resources),
87 .resource = smsc911x_resources,
88};
89
90static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
91{
92 u32 imr_val;
93 u32 int_valid;
94 u32 expio_irq;
95
96 desc->chip->mask(irq); /* irq = gpio irq number */
97
98 imr_val = __raw_readw(brd_io + INTR_MASK_REG);
99 int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
100
101 expio_irq = MXC_BOARD_IRQ_START;
102 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
103 struct irq_desc *d;
104 if ((int_valid & 1) == 0)
105 continue;
106 d = irq_desc + expio_irq;
107 if (unlikely(!(d->handle_irq)))
108 pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
109 else
110 d->handle_irq(expio_irq, d);
111 }
112
113 desc->chip->ack(irq);
114 desc->chip->unmask(irq);
115}
116
117/*
118 * Disable an expio pin's interrupt by setting the bit in the imr.
119 * Irq is an expio virtual irq number
120 */
121static void expio_mask_irq(u32 irq)
122{
123 u16 reg;
124 u32 expio = MXC_IRQ_TO_EXPIO(irq);
125
126 reg = __raw_readw(brd_io + INTR_MASK_REG);
127 reg |= (1 << expio);
128 __raw_writew(reg, brd_io + INTR_MASK_REG);
129}
130
131static void expio_ack_irq(u32 irq)
132{
133 u32 expio = MXC_IRQ_TO_EXPIO(irq);
134
135 __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
136 __raw_writew(0, brd_io + INTR_RESET_REG);
137 expio_mask_irq(irq);
138}
139
140static void expio_unmask_irq(u32 irq)
141{
142 u16 reg;
143 u32 expio = MXC_IRQ_TO_EXPIO(irq);
144
145 reg = __raw_readw(brd_io + INTR_MASK_REG);
146 reg &= ~(1 << expio);
147 __raw_writew(reg, brd_io + INTR_MASK_REG);
148}
149
150static struct irq_chip expio_irq_chip = {
151 .ack = expio_ack_irq,
152 .mask = expio_mask_irq,
153 .unmask = expio_unmask_irq,
154};
155
156int __init mxc_expio_init(u32 base, u32 p_irq)
157{
158 int i;
159
160 brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
161 if (brd_io == NULL)
162 return -ENOMEM;
163
164 if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
165 (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
166 (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
167 pr_info("3-Stack Debug board not detected\n");
168 iounmap(brd_io);
169 brd_io = NULL;
170 return -ENODEV;
171 }
172
173 pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
174 readw(brd_io + CPLD_CODE_VER_REG));
175
176 /*
177 * Configure INT line as GPIO input
178 */
179 gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
180 gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
181
182 /* disable the interrupt and clear the status */
183 __raw_writew(0, brd_io + INTR_MASK_REG);
184 __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
185 __raw_writew(0, brd_io + INTR_RESET_REG);
186 __raw_writew(0x1F, brd_io + INTR_MASK_REG);
187 for (i = MXC_EXP_IO_BASE;
188 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
189 set_irq_chip(i, &expio_irq_chip);
190 set_irq_handler(i, handle_level_irq);
191 set_irq_flags(i, IRQF_VALID);
192 }
193 set_irq_type(p_irq, IRQF_TRIGGER_LOW);
194 set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
195
196 /* Register Lan device on the debugboard */
197 smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
198 smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
199 platform_device_register(&smsc_lan9217_device);
200
201 return 0;
202}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f289bd..0527e65318f4 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -1,5 +1,7 @@
1if ARCH_MXC 1if ARCH_MXC
2 2
3source "arch/arm/plat-mxc/devices/Kconfig"
4
3menu "Freescale MXC Implementations" 5menu "Freescale MXC Implementations"
4 6
5choice 7choice
@@ -8,15 +10,12 @@ choice
8 10
9config ARCH_MX1 11config ARCH_MX1
10 bool "MX1-based" 12 bool "MX1-based"
11 select CPU_ARM920T 13 select SOC_IMX1
12 select IMX_HAVE_IOMUX_V1
13 help 14 help
14 This enables support for systems based on the Freescale i.MX1 family 15 This enables support for systems based on the Freescale i.MX1 family
15 16
16config ARCH_MX2 17config ARCH_MX2
17 bool "MX2-based" 18 bool "MX2-based"
18 select CPU_ARM926T
19 select IMX_HAVE_IOMUX_V1
20 help 19 help
21 This enables support for systems based on the Freescale i.MX2 family 20 This enables support for systems based on the Freescale i.MX2 family
22 21
@@ -25,6 +24,7 @@ config ARCH_MX25
25 select CPU_ARM926T 24 select CPU_ARM926T
26 select ARCH_MXC_IOMUX_V3 25 select ARCH_MXC_IOMUX_V3
27 select HAVE_FB_IMX 26 select HAVE_FB_IMX
27 select ARCH_MXC_AUDMUX_V2
28 help 28 help
29 This enables support for systems based on the Freescale i.MX25 family 29 This enables support for systems based on the Freescale i.MX25 family
30 30
@@ -48,8 +48,7 @@ config ARCH_MX5
48 48
49endchoice 49endchoice
50 50
51source "arch/arm/mach-mx1/Kconfig" 51source "arch/arm/mach-imx/Kconfig"
52source "arch/arm/mach-mx2/Kconfig"
53source "arch/arm/mach-mx3/Kconfig" 52source "arch/arm/mach-mx3/Kconfig"
54source "arch/arm/mach-mx25/Kconfig" 53source "arch/arm/mach-mx25/Kconfig"
55source "arch/arm/mach-mxc91231/Kconfig" 54source "arch/arm/mach-mxc91231/Kconfig"
@@ -81,6 +80,17 @@ config MXC_PWM
81 help 80 help
82 Enable support for the i.MX PWM controller(s). 81 Enable support for the i.MX PWM controller(s).
83 82
83config MXC_DEBUG_BOARD
84 bool "Enable MXC debug board(for 3-stack)"
85 help
86 The debug board is an integral part of the MXC 3-stack(PDK)
87 platforms, it can be attached or removed from the peripheral
88 board. On debug board, several debug devices(ethernet, UART,
89 buttons, LEDs and JTAG) are implemented. Between the MCU and
90 these devices, a CPLD is added as a bridge which performs
91 data/address de-multiplexing and decode, signal level shift,
92 interrupt control and various board functions.
93
84config MXC_ULPI 94config MXC_ULPI
85 bool 95 bool
86 96
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c5e0c0..78d405ed8616 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) 8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
9obj-$(CONFIG_MXC_TZIC) += tzic.o 9obj-$(CONFIG_MXC_TZIC) += tzic.o
10 10
11obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
12obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
13obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
14obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
15obj-$(CONFIG_MXC_PWM) += pwm.o 13obj-$(CONFIG_MXC_PWM) += pwm.o
@@ -17,7 +15,10 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
17obj-$(CONFIG_MXC_ULPI) += ulpi.o 15obj-$(CONFIG_MXC_ULPI) += ulpi.o
18obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o 16obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
19obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o 17obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
18obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
20ifdef CONFIG_SND_IMX_SOC 19ifdef CONFIG_SND_IMX_SOC
21obj-y += ssi-fiq.o 20obj-y += ssi-fiq.o
22obj-y += ssi-fiq-ksym.o 21obj-y += ssi-fiq-ksym.o
23endif 22endif
23
24obj-y += devices/
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index b62917ca3f95..1180bef7664b 100644
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 16 */
21 17
22#include <linux/module.h> 18#include <linux/module.h>
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0c2cc5cd4d83..f9e7cdbd0005 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 16 */
21 17
22#include <linux/module.h> 18#include <linux/module.h>
@@ -191,6 +187,7 @@ static int mxc_audmux_v2_init(void)
191{ 187{
192 int ret; 188 int ret;
193 189
190#if defined(CONFIG_ARCH_MX3)
194 if (cpu_is_mx31()) 191 if (cpu_is_mx31())
195 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); 192 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
196 193
@@ -204,7 +201,19 @@ static int mxc_audmux_v2_init(void)
204 } 201 }
205 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); 202 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
206 } 203 }
207 204#endif
205#if defined(CONFIG_ARCH_MX25)
206 if (cpu_is_mx25()) {
207 audmux_clk = clk_get(NULL, "audmux");
208 if (IS_ERR(audmux_clk)) {
209 ret = PTR_ERR(audmux_clk);
210 printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
211 ret);
212 return ret;
213 }
214 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
215 }
216#endif
208 audmux_debugfs_init(); 217 audmux_debugfs_init();
209 218
210 return 0; 219 return 0;
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 323ff8ccc877..2ed3ab173add 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -52,13 +52,14 @@ static void __clk_disable(struct clk *clk)
52{ 52{
53 if (clk == NULL || IS_ERR(clk)) 53 if (clk == NULL || IS_ERR(clk))
54 return; 54 return;
55
56 __clk_disable(clk->parent);
57 __clk_disable(clk->secondary);
58
59 WARN_ON(!clk->usecount); 55 WARN_ON(!clk->usecount);
60 if (!(--clk->usecount) && clk->disable) 56
61 clk->disable(clk); 57 if (!(--clk->usecount)) {
58 if (clk->disable)
59 clk->disable(clk);
60 __clk_disable(clk->parent);
61 __clk_disable(clk->secondary);
62 }
62} 63}
63 64
64static int __clk_enable(struct clk *clk) 65static int __clk_enable(struct clk *clk)
@@ -66,12 +67,13 @@ static int __clk_enable(struct clk *clk)
66 if (clk == NULL || IS_ERR(clk)) 67 if (clk == NULL || IS_ERR(clk))
67 return -EINVAL; 68 return -EINVAL;
68 69
69 __clk_enable(clk->parent); 70 if (clk->usecount++ == 0) {
70 __clk_enable(clk->secondary); 71 __clk_enable(clk->parent);
71 72 __clk_enable(clk->secondary);
72 if (clk->usecount++ == 0 && clk->enable)
73 clk->enable(clk);
74 73
74 if (clk->enable)
75 clk->enable(clk);
76 }
75 return 0; 77 return 0;
76} 78}
77 79
@@ -160,17 +162,28 @@ EXPORT_SYMBOL(clk_set_rate);
160int clk_set_parent(struct clk *clk, struct clk *parent) 162int clk_set_parent(struct clk *clk, struct clk *parent)
161{ 163{
162 int ret = -EINVAL; 164 int ret = -EINVAL;
165 struct clk *old;
163 166
164 if (clk == NULL || IS_ERR(clk) || parent == NULL || 167 if (clk == NULL || IS_ERR(clk) || parent == NULL ||
165 IS_ERR(parent) || clk->set_parent == NULL) 168 IS_ERR(parent) || clk->set_parent == NULL)
166 return ret; 169 return ret;
167 170
171 if (clk->usecount)
172 clk_enable(parent);
173
168 mutex_lock(&clocks_mutex); 174 mutex_lock(&clocks_mutex);
169 ret = clk->set_parent(clk, parent); 175 ret = clk->set_parent(clk, parent);
170 if (ret == 0) 176 if (ret == 0) {
177 old = clk->parent;
171 clk->parent = parent; 178 clk->parent = parent;
179 } else {
180 old = parent;
181 }
172 mutex_unlock(&clocks_mutex); 182 mutex_unlock(&clocks_mutex);
173 183
184 if (clk->usecount)
185 clk_disable(old);
186
174 return ret; 187 return ret;
175} 188}
176EXPORT_SYMBOL(clk_set_parent); 189EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 56f2fb5cc456..735776d84956 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -18,6 +18,7 @@
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/err.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
22#include <mach/common.h> 23#include <mach/common.h>
23 24
@@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
35 return ret; 36 return ret;
36} 37}
37 38
39struct platform_device *__init imx_add_platform_device(const char *name, int id,
40 const struct resource *res, unsigned int num_resources,
41 const void *data, size_t size_data)
42{
43 int ret = -ENOMEM;
44 struct platform_device *pdev;
45
46 pdev = platform_device_alloc(name, id);
47 if (!pdev)
48 goto err;
49
50 if (res) {
51 ret = platform_device_add_resources(pdev, res, num_resources);
52 if (ret)
53 goto err;
54 }
55
56 if (data) {
57 ret = platform_device_add_data(pdev, data, size_data);
58 if (ret)
59 goto err;
60 }
61
62 ret = platform_device_add(pdev);
63 if (ret) {
64err:
65 platform_device_put(pdev);
66 return ERR_PTR(ret);
67 }
68
69 return pdev;
70}
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
new file mode 100644
index 000000000000..9ab784b776f9
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -0,0 +1,15 @@
1config IMX_HAVE_PLATFORM_FLEXCAN
2 select HAVE_CAN_FLEXCAN
3 bool
4
5config IMX_HAVE_PLATFORM_IMX_I2C
6 bool
7
8config IMX_HAVE_PLATFORM_IMX_UART
9 bool
10
11config IMX_HAVE_PLATFORM_MXC_NAND
12 bool
13
14config IMX_HAVE_PLATFORM_SPI_IMX
15 bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
new file mode 100644
index 000000000000..347da5161f7e
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -0,0 +1,8 @@
1ifdef CONFIG_CAN_FLEXCAN
2# the ifdef can be removed once the flexcan driver has been merged
3obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
4endif
5obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
7obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
8obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c
new file mode 100644
index 000000000000..5e97a01f14f3
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-flexcan.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <mach/devices-common.h>
10
11struct platform_device *__init imx_add_flexcan(int id,
12 resource_size_t iobase, resource_size_t iosize,
13 resource_size_t irq,
14 const struct flexcan_platform_data *pdata)
15{
16 struct resource res[] = {
17 {
18 .start = iobase,
19 .end = iobase + iosize - 1,
20 .flags = IORESOURCE_MEM,
21 }, {
22 .start = irq,
23 .end = irq,
24 .flags = IORESOURCE_IRQ,
25 },
26 };
27
28 return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res),
29 pdata, sizeof(*pdata));
30}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
new file mode 100644
index 000000000000..d0af9f7d8aed
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/devices-common.h>
10
11struct platform_device *__init imx_add_imx_i2c(int id,
12 resource_size_t iobase, resource_size_t iosize, int irq,
13 const struct imxi2c_platform_data *pdata)
14{
15 struct resource res[] = {
16 {
17 .start = iobase,
18 .end = iobase + iosize - 1,
19 .flags = IORESOURCE_MEM,
20 }, {
21 .start = irq,
22 .end = irq,
23 .flags = IORESOURCE_IRQ,
24 },
25 };
26
27 return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
28 pdata, sizeof(*pdata));
29}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
new file mode 100644
index 000000000000..fa3dff1433e8
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/devices-common.h>
10
11struct platform_device *__init imx_add_imx_uart_3irq(int id,
12 resource_size_t iobase, resource_size_t iosize,
13 resource_size_t irqrx, resource_size_t irqtx,
14 resource_size_t irqrts,
15 const struct imxuart_platform_data *pdata)
16{
17 struct resource res[] = {
18 {
19 .start = iobase,
20 .end = iobase + iosize - 1,
21 .flags = IORESOURCE_MEM,
22 }, {
23 .start = irqrx,
24 .end = irqrx,
25 .flags = IORESOURCE_IRQ,
26 }, {
27 .start = irqtx,
28 .end = irqtx,
29 .flags = IORESOURCE_IRQ,
30 }, {
31 .start = irqrts,
32 .end = irqrx,
33 .flags = IORESOURCE_IRQ,
34 },
35 };
36
37 return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
38 pdata, sizeof(*pdata));
39}
40
41struct platform_device *__init imx_add_imx_uart_1irq(int id,
42 resource_size_t iobase, resource_size_t iosize,
43 resource_size_t irq,
44 const struct imxuart_platform_data *pdata)
45{
46 struct resource res[] = {
47 {
48 .start = iobase,
49 .end = iobase + iosize - 1,
50 .flags = IORESOURCE_MEM,
51 }, {
52 .start = irq,
53 .end = irq,
54 .flags = IORESOURCE_IRQ,
55 },
56 };
57
58 return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
59 pdata, sizeof(*pdata));
60}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
new file mode 100644
index 000000000000..1c286418d123
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -0,0 +1,44 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/devices-common.h>
11
12static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
13 int irq, const struct mxc_nand_platform_data *pdata,
14 resource_size_t iosize)
15{
16 static int id = 0;
17
18 struct resource res[] = {
19 {
20 .start = iobase,
21 .end = iobase + iosize - 1,
22 .flags = IORESOURCE_MEM,
23 }, {
24 .start = irq,
25 .end = irq,
26 .flags = IORESOURCE_IRQ,
27 },
28 };
29
30 return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
31 pdata, sizeof(*pdata));
32}
33
34struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
35 int irq, const struct mxc_nand_platform_data *pdata)
36{
37 return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
38}
39
40struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
41 int irq, const struct mxc_nand_platform_data *pdata)
42{
43 return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
44}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
new file mode 100644
index 000000000000..2831a6d3eb4b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/devices-common.h>
11
12struct platform_device *__init imx_add_spi_imx(int id,
13 resource_size_t iobase, resource_size_t iosize, int irq,
14 const struct spi_imx_master *pdata)
15{
16 struct resource res[] = {
17 {
18 .start = iobase,
19 .end = iobase + iosize - 1,
20 .flags = IORESOURCE_MEM,
21 }, {
22 .start = irq,
23 .end = irq,
24 .flags = IORESOURCE_IRQ,
25 },
26 };
27
28 return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
29 pdata, sizeof(*pdata));
30}
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 2a8646173c2f..35a064ff02ba 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -11,10 +11,6 @@
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details. 13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 14 */
19 15
20#include <linux/platform_device.h> 16#include <linux/platform_device.h>
@@ -73,7 +69,51 @@
73int mxc_initialize_usb_hw(int port, unsigned int flags) 69int mxc_initialize_usb_hw(int port, unsigned int flags)
74{ 70{
75 unsigned int v; 71 unsigned int v;
76#ifdef CONFIG_ARCH_MX3 72#if defined(CONFIG_ARCH_MX25)
73 if (cpu_is_mx25()) {
74 v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
75 USBCTRL_OTGBASE_OFFSET));
76
77 switch (port) {
78 case 0: /* OTG port */
79 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
80 v |= (flags & MXC_EHCI_INTERFACE_MASK)
81 << MX35_OTG_SIC_SHIFT;
82 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
83 v |= MX35_OTG_PM_BIT;
84
85 break;
86 case 1: /* H1 port */
87 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
88 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
89 v |= (flags & MXC_EHCI_INTERFACE_MASK)
90 << MX35_H1_SIC_SHIFT;
91 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
92 v |= MX35_H1_PM_BIT;
93
94 if (!(flags & MXC_EHCI_TTL_ENABLED))
95 v |= MX35_H1_TLL_BIT;
96
97 if (flags & MXC_EHCI_INTERNAL_PHY)
98 v |= MX35_H1_USBTE_BIT;
99
100 if (flags & MXC_EHCI_IPPUE_DOWN)
101 v |= MX35_H1_IPPUE_DOWN_BIT;
102
103 if (flags & MXC_EHCI_IPPUE_UP)
104 v |= MX35_H1_IPPUE_UP_BIT;
105
106 break;
107 default:
108 return -EINVAL;
109 }
110
111 writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
112 USBCTRL_OTGBASE_OFFSET));
113 return 0;
114 }
115#endif /* CONFIG_ARCH_MX25 */
116#if defined(CONFIG_ARCH_MX3)
77 if (cpu_is_mx31()) { 117 if (cpu_is_mx31()) {
78 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + 118 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
79 USBCTRL_OTGBASE_OFFSET)); 119 USBCTRL_OTGBASE_OFFSET));
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 71437c61cfd7..57ec4a896a5d 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -214,13 +214,16 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
214 struct mxc_gpio_port *port = 214 struct mxc_gpio_port *port =
215 container_of(chip, struct mxc_gpio_port, chip); 215 container_of(chip, struct mxc_gpio_port, chip);
216 u32 l; 216 u32 l;
217 unsigned long flags;
217 218
219 spin_lock_irqsave(&port->lock, flags);
218 l = __raw_readl(port->base + GPIO_GDIR); 220 l = __raw_readl(port->base + GPIO_GDIR);
219 if (dir) 221 if (dir)
220 l |= 1 << offset; 222 l |= 1 << offset;
221 else 223 else
222 l &= ~(1 << offset); 224 l &= ~(1 << offset);
223 __raw_writel(l, port->base + GPIO_GDIR); 225 __raw_writel(l, port->base + GPIO_GDIR);
226 spin_unlock_irqrestore(&port->lock, flags);
224} 227}
225 228
226static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 229static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -229,9 +232,12 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
229 container_of(chip, struct mxc_gpio_port, chip); 232 container_of(chip, struct mxc_gpio_port, chip);
230 void __iomem *reg = port->base + GPIO_DR; 233 void __iomem *reg = port->base + GPIO_DR;
231 u32 l; 234 u32 l;
235 unsigned long flags;
232 236
237 spin_lock_irqsave(&port->lock, flags);
233 l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset); 238 l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
234 __raw_writel(l, reg); 239 __raw_writel(l, reg);
240 spin_unlock_irqrestore(&port->lock, flags);
235} 241}
236 242
237static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) 243static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -285,6 +291,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
285 port[i].chip.base = i * 32; 291 port[i].chip.base = i * 32;
286 port[i].chip.ngpio = 32; 292 port[i].chip.ngpio = 32;
287 293
294 spin_lock_init(&port[i].lock);
295
288 /* its a serious configuration bug when it fails */ 296 /* its a serious configuration bug when it fails */
289 BUG_ON( gpiochip_add(&port[i].chip) < 0 ); 297 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
290 298
@@ -292,6 +300,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
292 /* setup one handler for each entry */ 300 /* setup one handler for each entry */
293 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); 301 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
294 set_irq_data(port[i].irq, &port[i]); 302 set_irq_data(port[i].irq, &port[i]);
303 if (port[i].irq_high) {
304 /* setup handler for GPIO 16 to 31 */
305 set_irq_chained_handler(port[i].irq_high,
306 mx3_gpio_irq_handler);
307 set_irq_data(port[i].irq_high, &port[i]);
308 }
295 } 309 }
296 } 310 }
297 311
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
new file mode 100644
index 000000000000..a384fdd49c62
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#ifndef __ASM_ARCH_MXC_3DS_DB_H__
14#define __ASM_ARCH_MXC_3DS_DB_H__
15
16extern int __init mxc_expio_init(u32 base, u32 p_irq);
17
18#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
deleted file mode 100644
index 0376c133c9f4..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>.
3 * All Rights Reserved.
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
13#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
14
15#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
deleted file mode 100644
index 93cc66f104c7..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
19#define __ARM_ARCH_BOARD_KZM_ARM11_H
20
21/*
22 * KZM-ARM11-01 Board Control Registers on FPGA
23 */
24#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
25#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
26#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
27#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
28#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
29#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
30#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
31#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
32
33/*
34 * External UART for touch panel on FPGA
35 */
36#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
37
38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
39
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
deleted file mode 100644
index 0cf4fa29510c..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
16
17/*
18 * Memory-mapped I/O on MX21ADS base board
19 */
20#define MX21ADS_MMIO_BASE_ADDR 0xF5000000
21#define MX21ADS_MMIO_SIZE SZ_16M
22
23#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
24 (MX21ADS_MMIO_BASE_ADDR + (offset))
25
26#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
27#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
28#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
29#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
30#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
31
32/* MX21ADS_IO_REG bit definitions */
33#define MX21ADS_IO_SD_WP 0x0001 /* read */
34#define MX21ADS_IO_TP6 0x0001 /* write */
35#define MX21ADS_IO_SW_SEL 0x0002 /* read */
36#define MX21ADS_IO_TP7 0x0002 /* write */
37#define MX21ADS_IO_RESET_E_UART 0x0004
38#define MX21ADS_IO_RESET_BASE 0x0008
39#define MX21ADS_IO_CSI_CTL2 0x0010
40#define MX21ADS_IO_CSI_CTL1 0x0020
41#define MX21ADS_IO_CSI_CTL0 0x0040
42#define MX21ADS_IO_UART1_EN 0x0080
43#define MX21ADS_IO_UART4_EN 0x0100
44#define MX21ADS_IO_LCDON 0x0200
45#define MX21ADS_IO_IRDA_EN 0x0400
46#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
47#define MX21ADS_IO_IRDA_MD0_B 0x1000
48#define MX21ADS_IO_IRDA_MD1 0x2000
49#define MX21ADS_IO_LED4_ON 0x4000
50#define MX21ADS_IO_LED3_ON 0x8000
51
52#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
deleted file mode 100644
index 7776d230327f..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ /dev/null
@@ -1,344 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
16
17/* external interrupt multiplexer */
18#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
19
20#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
24
25#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
26 MXC_MAX_VIRTUAL_INTS)
27
28/*
29 * @name Memory Size parameters
30 */
31
32/*
33 * Size of SDRAM memory
34 */
35#define SDRAM_MEM_SIZE SZ_128M
36
37/*
38 * PBC Controller parameters
39 */
40
41/*
42 * Base address of PBC controller, CS4
43 */
44#define PBC_BASE_ADDRESS 0xf4300000
45#define PBC_REG_ADDR(offset) (void __force __iomem *) \
46 (PBC_BASE_ADDRESS + (offset))
47
48/*
49 * PBC Interupt name definitions
50 */
51#define PBC_GPIO1_0 0
52#define PBC_GPIO1_1 1
53#define PBC_GPIO1_2 2
54#define PBC_GPIO1_3 3
55#define PBC_GPIO1_4 4
56#define PBC_GPIO1_5 5
57
58#define PBC_INTR_MAX_NUM 6
59#define PBC_INTR_SHARED_MAX_NUM 8
60
61/* When the PBC address connection is fixed in h/w, defined as 1 */
62#define PBC_ADDR_SH 0
63
64/* Offsets for the PBC Controller register */
65/*
66 * PBC Board version register offset
67 */
68#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
69/*
70 * PBC Board control register 1 set address.
71 */
72#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
73/*
74 * PBC Board control register 1 clear address.
75 */
76#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
77/*
78 * PBC Board control register 2 set address.
79 */
80#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
81/*
82 * PBC Board control register 2 clear address.
83 */
84#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
85/*
86 * PBC Board control register 3 set address.
87 */
88#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
89/*
90 * PBC Board control register 3 clear address.
91 */
92#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
93/*
94 * PBC Board control register 3 set address.
95 */
96#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
97/*
98 * PBC Board control register 4 clear address.
99 */
100#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
101/*PBC_ADDR_SH
102 * PBC Board status register 1.
103 */
104#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
105/*
106 * PBC Board interrupt status register.
107 */
108#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
109/*
110 * PBC Board interrupt current status register.
111 */
112#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
113/*
114 * PBC Interrupt mask register set address.
115 */
116#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
117/*
118 * PBC Interrupt mask register clear address.
119 */
120#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
121/*
122 * External UART A.
123 */
124#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
125/*
126 * UART 4 Expanding Signal Status.
127 */
128#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
129/*
130 * UART 4 Expanding Signal Control Set.
131 */
132#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
133/*
134 * UART 4 Expanding Signal Control Clear.
135 */
136#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
137/*
138 * Ethernet Controller IO base address.
139 */
140#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
141/*
142 * Ethernet Controller Memory base address.
143 */
144#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
145/*
146 * Ethernet Controller DMA base address.
147 */
148#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
149
150/* PBC Board Version Register bit definition */
151#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
152#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
153
154/* PBC Board Control Register 1 bit definitions */
155#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
156#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
157#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
158#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
159#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
160
161/* PBC Board Control Register 2 bit definitions */
162#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
163#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
164#define PBC_BCTRL2_ATAFEC_EN 0X0010
165#define PBC_BCTRL2_ATAFEC_SEL 0X0020
166#define PBC_BCTRL2_ATA_EN 0X0040
167#define PBC_BCTRL2_IRDA_SD 0X0080
168#define PBC_BCTRL2_IRDA_EN 0X0100
169#define PBC_BCTRL2_CCTL10 0X0200
170#define PBC_BCTRL2_CCTL11 0X0400
171
172/* PBC Board Control Register 3 bit definitions */
173#define PBC_BCTRL3_HSH_EN 0X0020
174#define PBC_BCTRL3_FSH_MOD 0X0040
175#define PBC_BCTRL3_OTG_HS_EN 0X0080
176#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
177#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
178#define PBC_BCTRL3_USB_OTG_ON 0X0800
179#define PBC_BCTRL3_USB_FSH_ON 0X1000
180
181/* PBC Board Control Register 4 bit definitions */
182#define PBC_BCTRL4_REGEN_SEL 0X0001
183#define PBC_BCTRL4_USER_OFF 0X0002
184#define PBC_BCTRL4_VIB_EN 0X0004
185#define PBC_BCTRL4_PWRGT1_EN 0X0008
186#define PBC_BCTRL4_PWRGT2_EN 0X0010
187#define PBC_BCTRL4_STDBY_PRI 0X0020
188
189#ifndef __ASSEMBLY__
190/*
191 * Enumerations for SD cards and memory stick card. This corresponds to
192 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
193 */
194enum mxc_card_no {
195 MXC_CARD_SD2 = 0,
196 MXC_CARD_SD3,
197 MXC_CARD_MS,
198 MXC_CARD_SD1,
199 MXC_CARD_MIN = MXC_CARD_SD2,
200 MXC_CARD_MAX = MXC_CARD_SD1,
201};
202#endif
203
204#define MXC_CPLD_VER_1_50 0x01
205
206/*
207 * PBC BSTAT Register bit definitions
208 */
209#define PBC_BSTAT_PRI_INT 0X0001
210#define PBC_BSTAT_USB_BYP 0X0002
211#define PBC_BSTAT_ATA_IOCS16 0X0004
212#define PBC_BSTAT_ATA_CBLID 0X0008
213#define PBC_BSTAT_ATA_DASP 0X0010
214#define PBC_BSTAT_PWR_RDY 0X0020
215#define PBC_BSTAT_SD3_WP 0X0100
216#define PBC_BSTAT_SD2_WP 0X0200
217#define PBC_BSTAT_SD1_WP 0X0400
218#define PBC_BSTAT_SD3_DET 0X0800
219#define PBC_BSTAT_SD2_DET 0X1000
220#define PBC_BSTAT_SD1_DET 0X2000
221#define PBC_BSTAT_MS_DET 0X4000
222#define PBC_BSTAT_SD3_DET_BIT 11
223#define PBC_BSTAT_SD2_DET_BIT 12
224#define PBC_BSTAT_SD1_DET_BIT 13
225#define PBC_BSTAT_MS_DET_BIT 14
226#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
227 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
228 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
229 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
230 0x0))))
231
232/*
233 * PBC UART Control Register bit definitions
234 */
235#define PBC_UCTRL_DCE_DCD 0X0001
236#define PBC_UCTRL_DCE_DSR 0X0002
237#define PBC_UCTRL_DCE_RI 0X0004
238#define PBC_UCTRL_DTE_DTR 0X0100
239
240/*
241 * PBC UART Status Register bit definitions
242 */
243#define PBC_USTAT_DTE_DCD 0X0001
244#define PBC_USTAT_DTE_DSR 0X0002
245#define PBC_USTAT_DTE_RI 0X0004
246#define PBC_USTAT_DCE_DTR 0X0100
247
248/*
249 * PBC Interupt mask register bit definitions
250 */
251#define PBC_INTR_SD3_R_EN_BIT 4
252#define PBC_INTR_SD2_R_EN_BIT 0
253#define PBC_INTR_SD1_R_EN_BIT 6
254#define PBC_INTR_MS_R_EN_BIT 5
255#define PBC_INTR_SD3_EN_BIT 13
256#define PBC_INTR_SD2_EN_BIT 12
257#define PBC_INTR_MS_EN_BIT 14
258#define PBC_INTR_SD1_EN_BIT 15
259
260#define PBC_INTR_SD2_R_EN 0x0001
261#define PBC_INTR_LOW_BAT 0X0002
262#define PBC_INTR_OTG_FSOVER 0X0004
263#define PBC_INTR_FSH_OVER 0X0008
264#define PBC_INTR_SD3_R_EN 0x0010
265#define PBC_INTR_MS_R_EN 0x0020
266#define PBC_INTR_SD1_R_EN 0x0040
267#define PBC_INTR_FEC_INT 0X0080
268#define PBC_INTR_ENET_INT 0X0100
269#define PBC_INTR_OTGFS_INT 0X0200
270#define PBC_INTR_XUART_INT 0X0400
271#define PBC_INTR_CCTL12 0X0800
272#define PBC_INTR_SD2_EN 0x1000
273#define PBC_INTR_SD3_EN 0x2000
274#define PBC_INTR_MS_EN 0x4000
275#define PBC_INTR_SD1_EN 0x8000
276
277
278
279/* For interrupts like xuart, enet etc */
280#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
281#define MXC_MAX_EXP_IO_LINES 16
282
283/*
284 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
285 *
286 */
287#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
288#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
289#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
290#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
291#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
292#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
293#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
294#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
295#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
296#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
297#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
298#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
299#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
300#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
301#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
302
303/*
304 * This is System IRQ used by CS8900A for interrupt generation
305 * taken from platform.h
306 */
307#define CS8900AIRQ EXPIO_INT_ENET_INT
308/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
309#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
310
311#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
312
313/*
314* This is used to detect if the CPLD version is for mx27 evb board rev-a
315*/
316#define PBC_CPLD_VERSION_IS_REVA() \
317 ((__raw_readw(PBC_VERSION_REG) & \
318 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
319 == 0)
320
321/* This is used to active or inactive ata signal in CPLD .
322 * It is dependent with hardware
323 */
324#define PBC_ATA_SIGNAL_ACTIVE() \
325 __raw_writew( \
326 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
327 PBC_BCTRL2_CLEAR_REG)
328
329#define PBC_ATA_SIGNAL_INACTIVE() \
330 __raw_writew( \
331 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
332 PBC_BCTRL2_SET_REG)
333
334#define MXC_BD_LED1 (1 << 5)
335#define MXC_BD_LED2 (1 << 6)
336#define MXC_BD_LED_ON(led) \
337 __raw_writew(led, PBC_BCTRL1_SET_REG)
338#define MXC_BD_LED_OFF(led) \
339 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
340
341/* to determine the correct external crystal reference */
342#define CKIH_27MHZ_BIT_SET (1 << 3)
343
344#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
deleted file mode 100644
index ea87551d2736..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
13
14#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
deleted file mode 100644
index fec1bcfa9164..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
12#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
13
14#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
deleted file mode 100644
index da92933a233b..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
13
14/* Definitions for components on the Debug board */
15
16/* Base address of CPLD controller on the Debug board */
17#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR)
18
19/* LAN9217 ethernet base address */
20#define LAN9217_BASE_ADDR CS5_BASE_ADDR
21
22/* CPLD config and interrupt base address */
23#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
24
25/* LED switchs */
26#define CPLD_LED_REG (CPLD_ADDR + 0x00)
27/* buttons */
28#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08)
29/* status, interrupt */
30#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
31#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
32#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
33/* magic word for debug CPLD */
34#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
35#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
36/* CPLD code version */
37#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
38/* magic word for debug CPLD */
39#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
40/* module reset register */
41#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60)
42/* CPU ID and Personality ID */
43#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68)
44
45/* CPLD IRQ line for external uart, external ethernet etc */
46#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
47
48#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
49#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
50
51#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
52#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1)
53#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2)
54#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3)
55#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4)
56
57#define MXC_MAX_EXP_IO_LINES 16
58
59#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 095a199591c6..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14#include <mach/hardware.h>
15
16/* Base address of PBC controller */
17#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
18/* Offsets for the PBC Controller register */
19
20/* PBC Board status register offset */
21#define PBC_BSTAT 0x000002
22
23/* PBC Board control register 1 set address */
24#define PBC_BCTRL1_SET 0x000004
25
26/* PBC Board control register 1 clear address */
27#define PBC_BCTRL1_CLEAR 0x000006
28
29/* PBC Board control register 2 set address */
30#define PBC_BCTRL2_SET 0x000008
31
32/* PBC Board control register 2 clear address */
33#define PBC_BCTRL2_CLEAR 0x00000A
34
35/* PBC Board control register 3 set address */
36#define PBC_BCTRL3_SET 0x00000C
37
38/* PBC Board control register 3 clear address */
39#define PBC_BCTRL3_CLEAR 0x00000E
40
41/* PBC Board control register 4 set address */
42#define PBC_BCTRL4_SET 0x000010
43
44/* PBC Board control register 4 clear address */
45#define PBC_BCTRL4_CLEAR 0x000012
46
47/* PBC Board status register 1 */
48#define PBC_BSTAT1 0x000014
49
50/* PBC Board interrupt status register */
51#define PBC_INTSTATUS 0x000016
52
53/* PBC Board interrupt current status register */
54#define PBC_INTCURR_STATUS 0x000018
55
56/* PBC Interrupt mask register set address */
57#define PBC_INTMASK_SET 0x00001A
58
59/* PBC Interrupt mask register clear address */
60#define PBC_INTMASK_CLEAR 0x00001C
61
62/* External UART A */
63#define PBC_SC16C652_UARTA 0x010000
64
65/* External UART B */
66#define PBC_SC16C652_UARTB 0x010010
67
68/* Ethernet Controller IO base address */
69#define PBC_CS8900A_IOBASE 0x020000
70
71/* Ethernet Controller Memory base address */
72#define PBC_CS8900A_MEMBASE 0x021000
73
74/* Ethernet Controller DMA base address */
75#define PBC_CS8900A_DMABASE 0x022000
76
77/* External chip select 0 */
78#define PBC_XCS0 0x040000
79
80/* LCD Display enable */
81#define PBC_LCD_EN_B 0x060000
82
83/* Code test debug enable */
84#define PBC_CODE_B 0x070000
85
86/* PSRAM memory select */
87#define PBC_PSRAM_B 0x5000000
88
89#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
90#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
91#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
92#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
93#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
94
95#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
96#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
97
98#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
99#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
100#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
101#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
102#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
103#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
104#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
105#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
106#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
107#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
108#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
109#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
110#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
111#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
112#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
113#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
114
115#define MXC_MAX_EXP_IO_LINES 16
116
117#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index eb5a5024622e..0df71bfefbb1 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -31,7 +31,7 @@ enum mx31lilly_boards {
31 31
32/* 32/*
33 * This CPU module needs a baseboard to work. After basic initializing 33 * This CPU module needs a baseboard to work. After basic initializing
34 * its own devices, it calls baseboard's init function. 34 * its own devices, it calls the baseboard's init function.
35 */ 35 */
36 36
37extern void mx31lilly_db_init(void); 37extern void mx31lilly_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 2b2da0367578..c1ad0ae807cc 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -32,7 +32,7 @@ enum mx31lite_boards {
32 32
33/* 33/*
34 * This CPU module needs a baseboard to work. After basic initializing 34 * This CPU module needs a baseboard to work. After basic initializing
35 * its own devices, it calls baseboard's init function. 35 * its own devices, it calls the baseboard's init function.
36 */ 36 */
37 37
38extern void mx31lite_db_init(void); 38extern void mx31lite_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 36ff3cedee1a..de14543891cf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -31,7 +31,7 @@ enum mx31moboard_boards {
31 31
32/* 32/*
33 * This CPU module needs a baseboard to work. After basic initializing 33 * This CPU module needs a baseboard to work. After basic initializing
34 * its own devices, it calls baseboard's init function. 34 * its own devices, it calls the baseboard's init function.
35 */ 35 */
36 36
37extern void mx31moboard_devboard_init(void); 37extern void mx31moboard_devboard_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 410f9786ed22..6f371e35753d 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -22,7 +22,7 @@
22#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
23/* 23/*
24 * This CPU module needs a baseboard to work. After basic initializing 24 * This CPU module needs a baseboard to work. After basic initializing
25 * its own devices, it calls baseboard's init function. 25 * its own devices, it calls the baseboard's init function.
26 * TODO: Add your own baseboard init function and call it from 26 * TODO: Add your own baseboard init function and call it from
27 * inside pcm038_init(). 27 * inside pcm038_init().
28 * 28 *
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
deleted file mode 100644
index 6d88c7af4b23..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
12#define __ASM_ARCH_MXC_BOARD_QONG_H__
13
14/* NOR FLASH */
15#define QONG_NOR_SIZE (128*1024*1024)
16
17#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 0b6e11eaeb8c..25606409aabc 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -23,8 +23,8 @@
23#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 23#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
24#endif 24#endif
25#include <mach/mx25.h> 25#include <mach/mx25.h>
26#define UART_PADDR UART1_BASE_ADDR 26#define UART_PADDR MX25_UART1_BASE_ADDR
27#define UART_VADDR MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR) 27#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
28#endif 28#endif
29 29
30#ifdef CONFIG_ARCH_MX2 30#ifdef CONFIG_ARCH_MX2
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644
index 000000000000..c5f68c587309
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <linux/kernel.h>
10#include <linux/platform_device.h>
11#include <linux/init.h>
12
13struct platform_device *imx_add_platform_device(const char *name, int id,
14 const struct resource *res, unsigned int num_resources,
15 const void *data, size_t size_data);
16
17#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE)
18#include <linux/can/platform/flexcan.h>
19struct platform_device *__init imx_add_flexcan(int id,
20 resource_size_t iobase, resource_size_t iosize,
21 resource_size_t irq,
22 const struct flexcan_platform_data *pdata);
23#else
24/* the ifdef can be removed once the flexcan driver has been merged */
25struct flexcan_platform_data;
26static inline struct platform_device *__init imx_add_flexcan(int id,
27 resource_size_t iobase, resource_size_t iosize,
28 resource_size_t irq,
29 const struct flexcan_platform_data *pdata)
30{
31 return NULL;
32}
33#endif
34
35#include <mach/i2c.h>
36struct platform_device *__init imx_add_imx_i2c(int id,
37 resource_size_t iobase, resource_size_t iosize, int irq,
38 const struct imxi2c_platform_data *pdata);
39
40#include <mach/imx-uart.h>
41struct platform_device *__init imx_add_imx_uart_3irq(int id,
42 resource_size_t iobase, resource_size_t iosize,
43 resource_size_t irqrx, resource_size_t irqtx,
44 resource_size_t irqrts,
45 const struct imxuart_platform_data *pdata);
46struct platform_device *__init imx_add_imx_uart_1irq(int id,
47 resource_size_t iobase, resource_size_t iosize,
48 resource_size_t irq,
49 const struct imxuart_platform_data *pdata);
50
51#include <mach/mxc_nand.h>
52struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
53 int irq, const struct mxc_nand_platform_data *pdata);
54struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
55 int irq, const struct mxc_nand_platform_data *pdata);
56
57#include <mach/spi.h>
58struct platform_device *__init imx_add_spi_imx(int id,
59 resource_size_t iobase, resource_size_t iosize, int irq,
60 const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index a1fd5830af48..634e3f4c454d 100644
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com 2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 * 3 *
4 * Based on board-pcm038.h which is : 4 * Based on board-pcm038.h which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -19,22 +19,29 @@
19 * MA 02110-1301, USA. 19 * MA 02110-1301, USA.
20 */ 20 */
21 21
22#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ 22#ifndef __MACH_EUKREA_BASEBOARDS_H__
23#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ 23#define __MACH_EUKREA_BASEBOARDS_H__
24 24
25#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
26/* 26/*
27 * This CPU module needs a baseboard to work. After basic initializing 27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx27_init(). 30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
31 * eukrea_cpuimx35_init() or eukrea_cpuimx51_init().
31 * 32 *
32 * This example here is for the development board. Refer 33 * This example here is for the development board. Refer
33 * eukrea_mbimx27-baseboard.c 34 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
35 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
36 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
37 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
34 */ 38 */
35 39
40extern void eukrea_mbimx25_baseboard_init(void);
36extern void eukrea_mbimx27_baseboard_init(void); 41extern void eukrea_mbimx27_baseboard_init(void);
42extern void eukrea_mbimx35_baseboard_init(void);
43extern void eukrea_mbimx51_baseboard_init(void);
37 44
38#endif 45#endif
39 46
40#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */ 47#endif /* __MACH_EUKREA_BASEBOARDS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 894d2f87c856..661fbc605759 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -33,9 +33,11 @@
33struct mxc_gpio_port { 33struct mxc_gpio_port {
34 void __iomem *base; 34 void __iomem *base;
35 int irq; 35 int irq;
36 int irq_high;
36 int virtual_irq_start; 37 int virtual_irq_start;
37 struct gpio_chip chip; 38 struct gpio_chip chip;
38 u32 both_edges; 39 u32 both_edges;
40 spinlock_t lock;
39}; 41};
40 42
41int mxc_gpio_init(struct mxc_gpio_port*, int); 43int mxc_gpio_init(struct mxc_gpio_port*, int);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f39220d1b67a..d7f52c91f82e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -252,6 +252,7 @@
252#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) 252#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
253 253
254#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) 254#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
255#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
255#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL) 256#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
256 257
257#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) 258#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
@@ -371,30 +372,41 @@
371#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL) 372#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
372#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) 373#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
373 374
374#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE) 375#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
376#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
377
378#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
375#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL) 379#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
376 380
377#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE) 381#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
378#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL) 382#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
379 383
380#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE) 384#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
381#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL) 385#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
382#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL) 386#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
383 387
384#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE) 388#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
385#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL) 389#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
386#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL) 390#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
387 391
388#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 392#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
393#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
394#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
389#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL) 395#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
390 396
391#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 397#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
398#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
399#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
392#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL) 400#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
393 401
394#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 402#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
403#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
404#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
395#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL) 405#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
396 406
397#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 407#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
408#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
409#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
398#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) 410#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
399 411
400#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL) 412#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d953d0..21bfa46785bb 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
27 IOMUX_CONFIG_ALT5, 27 IOMUX_CONFIG_ALT5,
28 IOMUX_CONFIG_ALT6, 28 IOMUX_CONFIG_ALT6,
29 IOMUX_CONFIG_ALT7, 29 IOMUX_CONFIG_ALT7,
30 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ 30 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
31 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ 31 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
32} iomux_pin_cfg_t; 32} iomux_pin_cfg_t;
33 33
34/* Pad control groupings */ 34/* Pad control groupings */
@@ -38,6 +38,8 @@ typedef enum iomux_config {
38 PAD_CTL_SRE_FAST) 38 PAD_CTL_SRE_FAST)
39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ 39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
40 PAD_CTL_SRE_FAST) 40 PAD_CTL_SRE_FAST)
41#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
42 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
41#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 43#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 44 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_PKE | PAD_CTL_HYS) 45 PAD_CTL_PKE | PAD_CTL_HYS)
@@ -46,289 +48,278 @@ typedef enum iomux_config {
46 48
47/* 49/*
48 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 50 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
49 * If <padname> or <padmode> refers to a GPIO, it is named 51 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
50 * GPIO_<unit>_<num> see also iomux-v3.h 52 * See also iomux-v3.h
51 */ 53 */
52 54
53/* 55/* PAD MUX ALT INPSE PATH PADCTRL */
54 * FIXME: This was converted using scripts from existing Freescale code to 56#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
55 * this form used upstream. Need to verify the name format. 57#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
56 */ 58#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
57 59#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
58/* PAD MUX ALT INPSE PATH PADCTRL */ 60#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
59 61#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) 62#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) 63#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
62#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) 64#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
63#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) 65#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
64#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) 66#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
65#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) 67#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
66#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) 68#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
67#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) 69#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
68#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) 70#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
69 71#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
70/* Babbage UART3 */ 72#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL)
71#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) 73#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \
72#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) 74 0x09b4, 0, MX51_I2C_PAD_CTRL)
73#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) 75#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL)
74#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) 76#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL)
75 77#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
76#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) 78#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \
77#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) 79 0x09b0, 0, MX51_I2C_PAD_CTRL)
78#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) 80#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
79#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) 81#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
80 82#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
81#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) 83#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
82#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) 84#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL)
83#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) 85#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
84#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) 86#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL)
85#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) 87#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL)
86#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) 88#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
87#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) 89#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
88#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) 90#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
89 91#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
90#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) 92#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
91#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) 93#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
92#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) 94#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL)
93#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) 95#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) 96#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL)
95#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) 97#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL)
96#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) 98#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL)
97#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) 99#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL)
98 100#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) 101#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL)
100#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) 102#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL)
101#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) 103#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL)
102#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) 104#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL)
103#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) 105#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL)
104#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) 106#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
105#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) 107#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
106#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) 108#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
107 109#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) 110#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
109#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) 111#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
110#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) 112#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) 113#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) 114#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) 115#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
114#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) 116#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
115#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) 117#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
116#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) 118#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL)
117#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) 119#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
118#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) 120#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
119#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) 121#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
120#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) 122#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
121/* REVISIT: Not sure of these values 123#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
122 124#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
123 #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) 125#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
124 #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 126#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
125 #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 127#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
126*/ 128#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 129#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 130#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
129#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 131#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 132#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) 133#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) 134#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) 135#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) 136#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
135#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) 137#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
136#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 138#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
137#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 139#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
138#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) 140#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
139#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) 141#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
140#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) 142#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
141#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) 143#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) 144#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) 145#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
144#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) 146#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
145#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) 147#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
146#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) 148#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) 149#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
148#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) 150#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
149#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) 151#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) 152#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
151#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) 153#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
152#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) 154#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
153#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) 155#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
154#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) 156#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
155#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) 157#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
156#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) 158#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
157#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) 159#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) 160#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
159#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) 161#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) 162#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
161#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) 163#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) 164#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) 165#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) 166#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
165#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) 167#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) 168#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
167#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 169#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 170#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
169#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 171#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) 172#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
171#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) 173#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) 174#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
173#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) 175#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
174#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) 176#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
175#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) 177#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
176#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) 178#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
177#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) 179#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
178#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) 180#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
179#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) 181#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
180#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) 182#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
181#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) 183#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
182#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) 184#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
183#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) 185#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
184#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) 186#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
185#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) 187#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) 188#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
187#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) 189#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
188#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) 190#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
189#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) 191#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
190#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) 192#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
191#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) 193#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
192#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) 194#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
193#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) 195#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
194 196#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
195/* Babbage UART1 */ 197#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
196#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 198#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
197#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 199#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
198#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) 200#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
199#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) 201#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL)
200 202#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
201/* Babbage UART2 */ 203#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL)
202#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) 204#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
203#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) 205#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
204 206#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL)
205#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) 207#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
206#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) 208#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
207#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) 209#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
208#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) 210#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) 211#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) 212#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) 213#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
212#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) 214#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
213#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) 215#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
214#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) 216#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
215#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) 217#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
216#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) 218#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL)
217#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) 219#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \
218#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 220 0x09b8, 1, MX51_I2C_PAD_CTRL)
219#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 221#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
220#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 222#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL)
221#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL) 223#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \
222#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 224 0x09bc, 1, MX51_I2C_PAD_CTRL)
223#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 225#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
224#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 226#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
225#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 227#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
226#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 228#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL)
227#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 229#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
228#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 230#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
229#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 231#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
230#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) 232#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
231#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 233#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
232#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) 234#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
233#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) 235#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
234#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) 236#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
235#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) 237#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
236#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) 238#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
237#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) 239#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) 240#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) 241#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
240#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) 242#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
241#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) 243#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
242#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) 244#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
243#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) 245#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
244#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) 246#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
245#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) 247#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
246#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) 248#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) 249#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) 250#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) 251#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
250#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) 252#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
251#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) 253#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
252#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) 254#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
253#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) 255#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
254#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) 256#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
255#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) 257#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
256#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) 258#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
257#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) 259#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) 260#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
259#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) 261#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
260#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) 262#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) 263#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
262#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) 264#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
263#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) 265#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) 266#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
265#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) 267#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
266#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) 268#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
267#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) 269#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
268#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) 270#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
269#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) 271#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) 272#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
271#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) 273#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
272#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) 274#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
273#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) 275#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
274#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) 276#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
275#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) 277#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
276#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) 278#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
277#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) 279#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) 280#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
279#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) 281#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
280#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) 282#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
281#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) 283#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
282#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) 284#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
283#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) 285#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
284#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) 286#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
285#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) 287#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
286#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) 288#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
287#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) 289#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
288#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) 290#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
289#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) 291#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
290#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) 292#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
291#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) 293#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
292#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) 294#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
293#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) 295#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
294#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) 296#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) 297#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) 298#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) 299#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
298#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) 300#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
299#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) 301#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) 302#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) 303#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) 304#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
303#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) 305#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
304#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) 306#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
305#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) 307#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
306#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) 308#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
307#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) 309#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
308#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) 310#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
309#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) 311#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
310#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 312#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
311#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ 313 0x9b8, 3, MX51_I2C_PAD_CTRL)
312 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) 314#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
313#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) 315#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
314 316 0x9bc, 3, MX51_I2C_PAD_CTRL)
315/* EIM */ 317#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
316#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) 318#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
317#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) 319#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) 320#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
319#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) 321#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
320#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) 322#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL)
321#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) 323#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
322#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
323#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
324
325#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
326#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
327#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
328#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
329#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
330#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
331#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
332#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
333 324
334#endif /* __MACH_IOMUX_MX51_H__ */ 325#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 3887f3fe29d4..15d59510f597 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#ifndef __MACH_IOMUX_MXC91231_H__ 17#ifndef __MACH_IOMUX_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d31d5ba..0880a4a1aed1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
89#define PAD_CTL_SRE_FAST (1 << 0) 89#define PAD_CTL_SRE_FAST (1 << 0)
90#define PAD_CTL_SRE_SLOW (0 << 0) 90#define PAD_CTL_SRE_SLOW (0 << 0)
91 91
92
93#define MX51_NUM_GPIO_PORT 4
94
95#define GPIO_PIN_MASK 0x1f
96
97#define GPIO_PORT_SHIFT 5
98#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
99
100#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
101#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
102#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
103#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
104#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
105#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
106
92/* 107/*
93 * setups a single pad in the iomuxer 108 * setups a single pad in the iomuxer
94 */ 109 */
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index c4b40c35a6a1..564ec9dbc93d 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -44,12 +44,12 @@
44 */ 44 */
45#define CONSISTENT_DMA_SIZE SZ_8M 45#define CONSISTENT_DMA_SIZE SZ_8M
46 46
47#elif defined(CONFIG_MX1_VIDEO) 47#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT)
48/* 48/*
49 * Increase size of DMA-consistent memory region. 49 * Increase size of DMA-consistent memory region.
50 * This is required for i.MX camera driver to capture at least four VGA frames. 50 * This is required for i.MX camera driver to capture at least four VGA frames.
51 */ 51 */
52#define CONSISTENT_DMA_SIZE SZ_4M 52#define CONSISTENT_DMA_SIZE SZ_4M
53#endif /* CONFIG_MX1_VIDEO */ 53#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */
54 54
55#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ 55#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index de2128dada5c..29115f405af9 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -31,6 +31,9 @@ struct imxmmc_platform_data {
31 31
32 /* adjust slot voltage */ 32 /* adjust slot voltage */
33 void (*setpower)(struct device *, unsigned int vdd); 33 void (*setpower)(struct device *, unsigned int vdd);
34
35 /* enable card detect using DAT3 */
36 int dat3_card_detect;
34}; 37};
35 38
36#endif 39#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 5eba7e6785de..641b24618239 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -91,24 +91,24 @@
91#define MX1_SIM_DATA_INT 16 91#define MX1_SIM_DATA_INT 16
92#define MX1_RTC_INT 17 92#define MX1_RTC_INT 17
93#define MX1_RTC_SAMINT 18 93#define MX1_RTC_SAMINT 18
94#define MX1_UART2_MINT_PFERR 19 94#define MX1_INT_UART2PFERR 19
95#define MX1_UART2_MINT_RTS 20 95#define MX1_INT_UART2RTS 20
96#define MX1_UART2_MINT_DTR 21 96#define MX1_INT_UART2DTR 21
97#define MX1_UART2_MINT_UARTC 22 97#define MX1_INT_UART2UARTC 22
98#define MX1_UART2_MINT_TX 23 98#define MX1_INT_UART2TX 23
99#define MX1_UART2_MINT_RX 24 99#define MX1_INT_UART2RX 24
100#define MX1_UART1_MINT_PFERR 25 100#define MX1_INT_UART1PFERR 25
101#define MX1_UART1_MINT_RTS 26 101#define MX1_INT_UART1RTS 26
102#define MX1_UART1_MINT_DTR 27 102#define MX1_INT_UART1DTR 27
103#define MX1_UART1_MINT_UARTC 28 103#define MX1_INT_UART1UARTC 28
104#define MX1_UART1_MINT_TX 29 104#define MX1_INT_UART1TX 29
105#define MX1_UART1_MINT_RX 30 105#define MX1_INT_UART1RX 30
106#define MX1_VOICE_DAC_INT 31 106#define MX1_VOICE_DAC_INT 31
107#define MX1_VOICE_ADC_INT 32 107#define MX1_VOICE_ADC_INT 32
108#define MX1_PEN_DATA_INT 33 108#define MX1_PEN_DATA_INT 33
109#define MX1_PWM_INT 34 109#define MX1_PWM_INT 34
110#define MX1_SDHC_INT 35 110#define MX1_SDHC_INT 35
111#define MX1_I2C_INT 39 111#define MX1_INT_I2C 39
112#define MX1_CSPI_INT 41 112#define MX1_CSPI_INT 41
113#define MX1_SSI_TX_INT 42 113#define MX1_SSI_TX_INT 42
114#define MX1_SSI_TX_ERR_INT 43 114#define MX1_SSI_TX_ERR_INT 43
@@ -245,7 +245,7 @@
245#define PEN_DATA_INT MX1_PEN_DATA_INT 245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT 246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT 247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_I2C_INT 248#define I2C_INT MX1_INT_I2C
249#define CSPI_INT MX1_CSPI_INT 249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT 250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT 251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4eb6e334bda5..4a6f800990f8 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -11,6 +11,12 @@
11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 12#define MX25_AVIC_SIZE SZ_1M
13 13
14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
15#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
16#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
17#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
18#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
19#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) 20#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
15 21
16#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) 22#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -27,22 +33,48 @@
27 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ 33 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
28 IMX_IO_ADDRESS(x, MX25_AVIC)) 34 IMX_IO_ADDRESS(x, MX25_AVIC))
29 35
36#define MX25_AIPS1_IO_ADDRESS(x) \
37 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
38
30#define MX25_UART1_BASE_ADDR 0x43f90000 39#define MX25_UART1_BASE_ADDR 0x43f90000
31#define MX25_UART2_BASE_ADDR 0x43f94000 40#define MX25_UART2_BASE_ADDR 0x43f94000
41#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
42#define MX25_UART3_BASE_ADDR 0x5000c000
43#define MX25_UART4_BASE_ADDR 0x50008000
44#define MX25_UART5_BASE_ADDR 0x5002c000
32 45
46#define MX25_CSPI3_BASE_ADDR 0x50004000
47#define MX25_CSPI2_BASE_ADDR 0x50010000
33#define MX25_FEC_BASE_ADDR 0x50038000 48#define MX25_FEC_BASE_ADDR 0x50038000
49#define MX25_SSI2_BASE_ADDR 0x50014000
50#define MX25_SSI1_BASE_ADDR 0x50034000
34#define MX25_NFC_BASE_ADDR 0xbb000000 51#define MX25_NFC_BASE_ADDR 0xbb000000
35#define MX25_DRYICE_BASE_ADDR 0x53ffc000 52#define MX25_DRYICE_BASE_ADDR 0x53ffc000
36#define MX25_LCDC_BASE_ADDR 0x53fbc000 53#define MX25_LCDC_BASE_ADDR 0x53fbc000
54#define MX25_KPP_BASE_ADDR 0x43fa8000
55#define MX25_OTG_BASE_ADDR 0x53ff4000
56#define MX25_CSI_BASE_ADDR 0x53ff8000
37 57
38#define MX25_INT_DRYICE 25 58#define MX25_INT_CSPI3 0
39#define MX25_INT_FEC 57 59#define MX25_INT_I2C1 3
40#define MX25_INT_NANDFC 33 60#define MX25_INT_I2C2 4
41#define MX25_INT_LCDC 39 61#define MX25_INT_UART4 5
42 62#define MX25_INT_I2C3 10
43#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) 63#define MX25_INT_SSI2 11
44#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR 64#define MX25_INT_SSI1 12
45#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR 65#define MX25_INT_CSPI2 13
46#endif 66#define MX25_INT_CSPI1 14
67#define MX25_INT_CSI 17
68#define MX25_INT_UART3 18
69#define MX25_INT_KPP 24
70#define MX25_INT_DRYICE 25
71#define MX25_INT_UART2 32
72#define MX25_INT_NANDFC 33
73#define MX25_INT_LCDC 39
74#define MX25_INT_UART5 40
75#define MX25_INT_CAN1 43
76#define MX25_INT_CAN2 44
77#define MX25_INT_UART1 45
78#define MX25_INT_FEC 57
47 79
48#endif /* ifndef __MACH_MX25_H__ */ 80#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index bae9cd75beee..a8ab2e02a8ca 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -48,7 +48,7 @@
48#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) 48#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
49#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) 49#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
50#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) 50#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
51#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) 51#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) 52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) 53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) 54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
@@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs,
150#define MX27_INT_SDHC3 9 150#define MX27_INT_SDHC3 9
151#define MX27_INT_SDHC2 10 151#define MX27_INT_SDHC2 10
152#define MX27_INT_SDHC1 11 152#define MX27_INT_SDHC1 11
153#define MX27_INT_I2C 12 153#define MX27_INT_I2C1 12
154#define MX27_INT_SSI2 13 154#define MX27_INT_SSI2 13
155#define MX27_INT_SSI1 14 155#define MX27_INT_SSI1 14
156#define MX27_INT_CSPI2 15 156#define MX27_INT_CSPI2 15
diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
new file mode 100644
index 000000000000..3c080a32dbf5
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -0,0 +1,46 @@
1/*
2 * mx2-cam.h - i.MX27/i.MX25 camera driver header file
3 *
4 * Copyright (C) 2003, Intel Corporation
5 * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de>
6 * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#ifndef __MACH_MX2_CAM_H_
24#define __MACH_MX2_CAM_H_
25
26#define MX2_CAMERA_SWAP16 (1 << 0)
27#define MX2_CAMERA_EXT_VSYNC (1 << 1)
28#define MX2_CAMERA_CCIR (1 << 2)
29#define MX2_CAMERA_CCIR_INTERLACE (1 << 3)
30#define MX2_CAMERA_HSYNC_HIGH (1 << 4)
31#define MX2_CAMERA_GATED_CLOCK (1 << 5)
32#define MX2_CAMERA_INV_DATA (1 << 6)
33#define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7)
34#define MX2_CAMERA_PACK_DIR_MSB (1 << 8)
35
36/**
37 * struct mx2_camera_platform_data - optional platform data for mx2_camera
38 * @flags: any combination of MX2_CAMERA_*
39 * @clk: clock rate of the csi block / 2
40 */
41struct mx2_camera_platform_data {
42 unsigned long flags;
43 unsigned long clk;
44};
45
46#endif /* __MACH_MX2_CAM_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e119c2b5..afee3ab9d62e 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -23,7 +23,7 @@
23#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) 23#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
24#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) 24#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) 25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
26#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) 26#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) 27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) 28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) 29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
@@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs,
145#define MX31_INT_FIRI 7 145#define MX31_INT_FIRI 7
146#define MX31_INT_MMC_SDHC2 8 146#define MX31_INT_MMC_SDHC2 8
147#define MX31_INT_MMC_SDHC1 9 147#define MX31_INT_MMC_SDHC1 9
148#define MX31_INT_I2C 10 148#define MX31_INT_I2C1 10
149#define MX31_INT_SSI2 11 149#define MX31_INT_SSI2 11
150#define MX31_INT_SSI1 12 150#define MX31_INT_SSI1 12
151#define MX31_INT_CSPI2 13 151#define MX31_INT_CSPI2 13
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae5..af3038c12e39 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) 18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) 19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) 20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
21#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) 21#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) 22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) 23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) 24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -60,6 +60,8 @@
60#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) 60#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
61#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) 61#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
62#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) 62#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
63#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
64#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
63#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) 65#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
64#define MX35_OTG_BASE_ADDR 0x53ff4000 66#define MX35_OTG_BASE_ADDR 0x53ff4000
65 67
@@ -123,7 +125,7 @@
123#define MX35_INT_MMC_SDHC1 7 125#define MX35_INT_MMC_SDHC1 7
124#define MX35_INT_MMC_SDHC2 8 126#define MX35_INT_MMC_SDHC2 8
125#define MX35_INT_MMC_SDHC3 9 127#define MX35_INT_MMC_SDHC3 9
126#define MX35_INT_I2C 10 128#define MX35_INT_I2C1 10
127#define MX35_INT_SSI1 11 129#define MX35_INT_SSI1 11
128#define MX35_INT_SSI2 12 130#define MX35_INT_SSI2 12
129#define MX35_INT_CSPI2 13 131#define MX35_INT_CSPI2 13
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
index 36d7ff27b5e2..f226ee3777e1 100644
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20 16
21#ifndef _MX3_CAMERA_H_ 17#ifndef _MX3_CAMERA_H_
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 5182b986b785..0ca3101ebf36 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 16 */
21#ifndef __MACH_MXC91231_H__ 17#ifndef __MACH_MXC91231_H__
22#define __MACH_MXC91231_H__ 18#define __MACH_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 5d2d21d414e0..04c0d060d814 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -20,9 +20,13 @@
20#ifndef __ASM_ARCH_NAND_H 20#ifndef __ASM_ARCH_NAND_H
21#define __ASM_ARCH_NAND_H 21#define __ASM_ARCH_NAND_H
22 22
23#include <linux/mtd/partitions.h>
24
23struct mxc_nand_platform_data { 25struct mxc_nand_platform_data {
24 int width; /* data bus width in bytes */ 26 unsigned int width; /* data bus width in bytes */
25 int hw_ecc:1; /* 0 if supress hardware ECC */ 27 unsigned int hw_ecc:1; /* 0 if supress hardware ECC */
26 int flash_bbt:1; /* set to 1 to use a flash based bbt */ 28 unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
29 struct mtd_partition *parts; /* partition table */
30 int nr_parts; /* size of parts */
27}; 31};
28#endif /* __ASM_ARCH_NAND_H */ 32#endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index ef00199568de..4acd1143a9bd 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#ifndef __ASM_ARCH_MXC_SYSTEM_H__ 17#ifndef __ASM_ARCH_MXC_SYSTEM_H__
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 024416ed11cd..2d9624697cc9 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19 15
20#ifndef __ASM_ARCH_MXC_TIMEX_H__ 16#ifndef __ASM_ARCH_MXC_TIMEX_H__
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index b6d3d0fddc48..d9bd37e4667a 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 16 */
21#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ 17#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
22#define __ASM_ARCH_MXC_UNCOMPRESS_H__ 18#define __ASM_ARCH_MXC_UNCOMPRESS_H__
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 44243a278434..ef6379c474be 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19 15
20#ifndef __ASM_ARCH_MXC_VMALLOC_H__ 16#ifndef __ASM_ARCH_MXC_VMALLOC_H__
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 778ddfe57d89..7331f2ace5fe 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase)
142 for (i = 0; i < 8; i++) 142 for (i = 0; i < 8; i++)
143 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); 143 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
144 144
145 /* init architectures chained interrupt handler */
146 mxc_register_gpios();
147
148#ifdef CONFIG_FIQ 145#ifdef CONFIG_FIQ
149 /* Initialize FIQ */ 146 /* Initialize FIQ */
150 init_FIQ(); 147 init_FIQ();
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 97f42799fa58..925bce4607e7 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -14,10 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */ 17 */
22 18
23#include <linux/kernel.h> 19#include <linux/kernel.h>
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 9b86d2a60d43..b3da9aad4295 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
145 set_irq_handler(i, handle_level_irq); 145 set_irq_handler(i, handle_level_irq);
146 set_irq_flags(i, IRQF_VALID); 146 set_irq_flags(i, IRQF_VALID);
147 } 147 }
148 mxc_register_gpios();
149
150 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
151} 149}
152 150
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 5a6ef252c38b..977c8f9a07a2 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,7 @@
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/slab.h> 24#include <linux/slab.h>
25 25
26#include <plat/pincfg.h>
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <mach/gpio.h> 28#include <mach/gpio.h>
28 29
@@ -46,28 +47,217 @@ struct nmk_gpio_chip {
46 u32 edge_falling; 47 u32 edge_falling;
47}; 48};
48 49
50static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
51 unsigned offset, int gpio_mode)
52{
53 u32 bit = 1 << offset;
54 u32 afunc, bfunc;
55
56 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
57 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
58 if (gpio_mode & NMK_GPIO_ALT_A)
59 afunc |= bit;
60 if (gpio_mode & NMK_GPIO_ALT_B)
61 bfunc |= bit;
62 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
63 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
64}
65
66static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
67 unsigned offset, enum nmk_gpio_slpm mode)
68{
69 u32 bit = 1 << offset;
70 u32 slpm;
71
72 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
73 if (mode == NMK_GPIO_SLPM_NOCHANGE)
74 slpm |= bit;
75 else
76 slpm &= ~bit;
77 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
78}
79
80static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
81 unsigned offset, enum nmk_gpio_pull pull)
82{
83 u32 bit = 1 << offset;
84 u32 pdis;
85
86 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
87 if (pull == NMK_GPIO_PULL_NONE)
88 pdis |= bit;
89 else
90 pdis &= ~bit;
91 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
92
93 if (pull == NMK_GPIO_PULL_UP)
94 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
95 else if (pull == NMK_GPIO_PULL_DOWN)
96 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
97}
98
99static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
100 unsigned offset)
101{
102 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
103}
104
105static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
106 pin_cfg_t cfg)
107{
108 static const char *afnames[] = {
109 [NMK_GPIO_ALT_GPIO] = "GPIO",
110 [NMK_GPIO_ALT_A] = "A",
111 [NMK_GPIO_ALT_B] = "B",
112 [NMK_GPIO_ALT_C] = "C"
113 };
114 static const char *pullnames[] = {
115 [NMK_GPIO_PULL_NONE] = "none",
116 [NMK_GPIO_PULL_UP] = "up",
117 [NMK_GPIO_PULL_DOWN] = "down",
118 [3] /* illegal */ = "??"
119 };
120 static const char *slpmnames[] = {
121 [NMK_GPIO_SLPM_INPUT] = "input",
122 [NMK_GPIO_SLPM_NOCHANGE] = "no-change",
123 };
124
125 int pin = PIN_NUM(cfg);
126 int pull = PIN_PULL(cfg);
127 int af = PIN_ALT(cfg);
128 int slpm = PIN_SLPM(cfg);
129
130 dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n",
131 pin, afnames[af], pullnames[pull], slpmnames[slpm]);
132
133 __nmk_gpio_make_input(nmk_chip, offset);
134 __nmk_gpio_set_pull(nmk_chip, offset, pull);
135 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
136 __nmk_gpio_set_mode(nmk_chip, offset, af);
137}
138
139/**
140 * nmk_config_pin - configure a pin's mux attributes
141 * @cfg: pin confguration
142 *
143 * Configures a pin's mode (alternate function or GPIO), its pull up status,
144 * and its sleep mode based on the specified configuration. The @cfg is
145 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
146 * are constructed using, and can be further enhanced with, the macros in
147 * plat/pincfg.h.
148 *
149 * If a pin's mode is set to GPIO, it is configured as an input to avoid
150 * side-effects. The gpio can be manipulated later using standard GPIO API
151 * calls.
152 */
153int nmk_config_pin(pin_cfg_t cfg)
154{
155 struct nmk_gpio_chip *nmk_chip;
156 int gpio = PIN_NUM(cfg);
157 unsigned long flags;
158
159 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
160 if (!nmk_chip)
161 return -EINVAL;
162
163 spin_lock_irqsave(&nmk_chip->lock, flags);
164 __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg);
165 spin_unlock_irqrestore(&nmk_chip->lock, flags);
166
167 return 0;
168}
169EXPORT_SYMBOL(nmk_config_pin);
170
171/**
172 * nmk_config_pins - configure several pins at once
173 * @cfgs: array of pin configurations
174 * @num: number of elments in the array
175 *
176 * Configures several pins using nmk_config_pin(). Refer to that function for
177 * further information.
178 */
179int nmk_config_pins(pin_cfg_t *cfgs, int num)
180{
181 int ret = 0;
182 int i;
183
184 for (i = 0; i < num; i++) {
185 int ret = nmk_config_pin(cfgs[i]);
186 if (ret)
187 break;
188 }
189
190 return ret;
191}
192EXPORT_SYMBOL(nmk_config_pins);
193
194/**
195 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
196 * @gpio: pin number
197 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
198 *
199 * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is
200 * changed to an input (with pullup/down enabled) in sleep and deep sleep. If
201 * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
202 * configured even when in sleep and deep sleep.
203 */
204int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
205{
206 struct nmk_gpio_chip *nmk_chip;
207 unsigned long flags;
208
209 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
210 if (!nmk_chip)
211 return -EINVAL;
212
213 spin_lock_irqsave(&nmk_chip->lock, flags);
214 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
215 spin_unlock_irqrestore(&nmk_chip->lock, flags);
216
217 return 0;
218}
219
220/**
221 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
222 * @gpio: pin number
223 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
224 *
225 * Enables/disables pull up/down on a specified pin. This only takes effect if
226 * the pin is configured as an input (either explicitly or by the alternate
227 * function).
228 *
229 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
230 * configured as an input. Otherwise, due to the way the controller registers
231 * work, this function will change the value output on the pin.
232 */
233int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
234{
235 struct nmk_gpio_chip *nmk_chip;
236 unsigned long flags;
237
238 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
239 if (!nmk_chip)
240 return -EINVAL;
241
242 spin_lock_irqsave(&nmk_chip->lock, flags);
243 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
244 spin_unlock_irqrestore(&nmk_chip->lock, flags);
245
246 return 0;
247}
248
49/* Mode functions */ 249/* Mode functions */
50int nmk_gpio_set_mode(int gpio, int gpio_mode) 250int nmk_gpio_set_mode(int gpio, int gpio_mode)
51{ 251{
52 struct nmk_gpio_chip *nmk_chip; 252 struct nmk_gpio_chip *nmk_chip;
53 unsigned long flags; 253 unsigned long flags;
54 u32 afunc, bfunc, bit;
55 254
56 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 255 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
57 if (!nmk_chip) 256 if (!nmk_chip)
58 return -EINVAL; 257 return -EINVAL;
59 258
60 bit = 1 << (gpio - nmk_chip->chip.base);
61
62 spin_lock_irqsave(&nmk_chip->lock, flags); 259 spin_lock_irqsave(&nmk_chip->lock, flags);
63 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; 260 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
64 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
65 if (gpio_mode & NMK_GPIO_ALT_A)
66 afunc |= bit;
67 if (gpio_mode & NMK_GPIO_ALT_B)
68 bfunc |= bit;
69 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
70 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
71 spin_unlock_irqrestore(&nmk_chip->lock, flags); 261 spin_unlock_irqrestore(&nmk_chip->lock, flags);
72 262
73 return 0; 263 return 0;
@@ -111,32 +301,41 @@ static void nmk_gpio_irq_ack(unsigned int irq)
111 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); 301 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
112} 302}
113 303
304enum nmk_gpio_irq_type {
305 NORMAL,
306 WAKE,
307};
308
114static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 309static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
115 int gpio, bool enable) 310 int gpio, enum nmk_gpio_irq_type which,
311 bool enable)
116{ 312{
313 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
314 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
117 u32 bitmask = nmk_gpio_get_bitmask(gpio); 315 u32 bitmask = nmk_gpio_get_bitmask(gpio);
118 u32 reg; 316 u32 reg;
119 317
120 /* we must individually set/clear the two edges */ 318 /* we must individually set/clear the two edges */
121 if (nmk_chip->edge_rising & bitmask) { 319 if (nmk_chip->edge_rising & bitmask) {
122 reg = readl(nmk_chip->addr + NMK_GPIO_RIMSC); 320 reg = readl(nmk_chip->addr + rimsc);
123 if (enable) 321 if (enable)
124 reg |= bitmask; 322 reg |= bitmask;
125 else 323 else
126 reg &= ~bitmask; 324 reg &= ~bitmask;
127 writel(reg, nmk_chip->addr + NMK_GPIO_RIMSC); 325 writel(reg, nmk_chip->addr + rimsc);
128 } 326 }
129 if (nmk_chip->edge_falling & bitmask) { 327 if (nmk_chip->edge_falling & bitmask) {
130 reg = readl(nmk_chip->addr + NMK_GPIO_FIMSC); 328 reg = readl(nmk_chip->addr + fimsc);
131 if (enable) 329 if (enable)
132 reg |= bitmask; 330 reg |= bitmask;
133 else 331 else
134 reg &= ~bitmask; 332 reg &= ~bitmask;
135 writel(reg, nmk_chip->addr + NMK_GPIO_FIMSC); 333 writel(reg, nmk_chip->addr + fimsc);
136 } 334 }
137} 335}
138 336
139static void nmk_gpio_irq_modify(unsigned int irq, bool enable) 337static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
338 bool enable)
140{ 339{
141 int gpio; 340 int gpio;
142 struct nmk_gpio_chip *nmk_chip; 341 struct nmk_gpio_chip *nmk_chip;
@@ -147,26 +346,35 @@ static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
147 nmk_chip = get_irq_chip_data(irq); 346 nmk_chip = get_irq_chip_data(irq);
148 bitmask = nmk_gpio_get_bitmask(gpio); 347 bitmask = nmk_gpio_get_bitmask(gpio);
149 if (!nmk_chip) 348 if (!nmk_chip)
150 return; 349 return -EINVAL;
151 350
152 spin_lock_irqsave(&nmk_chip->lock, flags); 351 spin_lock_irqsave(&nmk_chip->lock, flags);
153 __nmk_gpio_irq_modify(nmk_chip, gpio, enable); 352 __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
154 spin_unlock_irqrestore(&nmk_chip->lock, flags); 353 spin_unlock_irqrestore(&nmk_chip->lock, flags);
354
355 return 0;
155} 356}
156 357
157static void nmk_gpio_irq_mask(unsigned int irq) 358static void nmk_gpio_irq_mask(unsigned int irq)
158{ 359{
159 nmk_gpio_irq_modify(irq, false); 360 nmk_gpio_irq_modify(irq, NORMAL, false);
160}; 361}
161 362
162static void nmk_gpio_irq_unmask(unsigned int irq) 363static void nmk_gpio_irq_unmask(unsigned int irq)
163{ 364{
164 nmk_gpio_irq_modify(irq, true); 365 nmk_gpio_irq_modify(irq, NORMAL, true);
366}
367
368static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
369{
370 return nmk_gpio_irq_modify(irq, WAKE, on);
165} 371}
166 372
167static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) 373static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
168{ 374{
169 bool enabled = !(irq_to_desc(irq)->status & IRQ_DISABLED); 375 struct irq_desc *desc = irq_to_desc(irq);
376 bool enabled = !(desc->status & IRQ_DISABLED);
377 bool wake = desc->wake_depth;
170 int gpio; 378 int gpio;
171 struct nmk_gpio_chip *nmk_chip; 379 struct nmk_gpio_chip *nmk_chip;
172 unsigned long flags; 380 unsigned long flags;
@@ -186,7 +394,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
186 spin_lock_irqsave(&nmk_chip->lock, flags); 394 spin_lock_irqsave(&nmk_chip->lock, flags);
187 395
188 if (enabled) 396 if (enabled)
189 __nmk_gpio_irq_modify(nmk_chip, gpio, false); 397 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
398
399 if (wake)
400 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
190 401
191 nmk_chip->edge_rising &= ~bitmask; 402 nmk_chip->edge_rising &= ~bitmask;
192 if (type & IRQ_TYPE_EDGE_RISING) 403 if (type & IRQ_TYPE_EDGE_RISING)
@@ -197,7 +408,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
197 nmk_chip->edge_falling |= bitmask; 408 nmk_chip->edge_falling |= bitmask;
198 409
199 if (enabled) 410 if (enabled)
200 __nmk_gpio_irq_modify(nmk_chip, gpio, true); 411 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
412
413 if (wake)
414 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
201 415
202 spin_unlock_irqrestore(&nmk_chip->lock, flags); 416 spin_unlock_irqrestore(&nmk_chip->lock, flags);
203 417
@@ -210,6 +424,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
210 .mask = nmk_gpio_irq_mask, 424 .mask = nmk_gpio_irq_mask,
211 .unmask = nmk_gpio_irq_unmask, 425 .unmask = nmk_gpio_irq_unmask,
212 .set_type = nmk_gpio_irq_set_type, 426 .set_type = nmk_gpio_irq_set_type,
427 .set_wake = nmk_gpio_irq_set_wake,
213}; 428};
214 429
215static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 430static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -266,16 +481,6 @@ static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
266 return 0; 481 return 0;
267} 482}
268 483
269static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
270 int val)
271{
272 struct nmk_gpio_chip *nmk_chip =
273 container_of(chip, struct nmk_gpio_chip, chip);
274
275 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
276 return 0;
277}
278
279static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 484static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
280{ 485{
281 struct nmk_gpio_chip *nmk_chip = 486 struct nmk_gpio_chip *nmk_chip =
@@ -298,12 +503,33 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
298 writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 503 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
299} 504}
300 505
506static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
507 int val)
508{
509 struct nmk_gpio_chip *nmk_chip =
510 container_of(chip, struct nmk_gpio_chip, chip);
511
512 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
513 nmk_gpio_set_output(chip, offset, val);
514
515 return 0;
516}
517
518static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
519{
520 struct nmk_gpio_chip *nmk_chip =
521 container_of(chip, struct nmk_gpio_chip, chip);
522
523 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
524}
525
301/* This structure is replicated for each GPIO block allocated at probe time */ 526/* This structure is replicated for each GPIO block allocated at probe time */
302static struct gpio_chip nmk_gpio_template = { 527static struct gpio_chip nmk_gpio_template = {
303 .direction_input = nmk_gpio_make_input, 528 .direction_input = nmk_gpio_make_input,
304 .get = nmk_gpio_get_input, 529 .get = nmk_gpio_get_input,
305 .direction_output = nmk_gpio_make_output, 530 .direction_output = nmk_gpio_make_output,
306 .set = nmk_gpio_set_output, 531 .set = nmk_gpio_set_output,
532 .to_irq = nmk_gpio_to_irq,
307 .ngpio = NMK_GPIO_PER_CHIP, 533 .ngpio = NMK_GPIO_PER_CHIP,
308 .can_sleep = 0, 534 .can_sleep = 0,
309}; 535};
@@ -393,30 +619,12 @@ out:
393 return ret; 619 return ret;
394} 620}
395 621
396static int __exit nmk_gpio_remove(struct platform_device *dev)
397{
398 struct nmk_gpio_chip *nmk_chip;
399 struct resource *res;
400
401 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
402
403 nmk_chip = platform_get_drvdata(dev);
404 gpiochip_remove(&nmk_chip->chip);
405 clk_disable(nmk_chip->clk);
406 clk_put(nmk_chip->clk);
407 kfree(nmk_chip);
408 release_mem_region(res->start, resource_size(res));
409 return 0;
410}
411
412
413static struct platform_driver nmk_gpio_driver = { 622static struct platform_driver nmk_gpio_driver = {
414 .driver = { 623 .driver = {
415 .owner = THIS_MODULE, 624 .owner = THIS_MODULE,
416 .name = "gpio", 625 .name = "gpio",
417 }, 626 },
418 .probe = nmk_gpio_probe, 627 .probe = nmk_gpio_probe,
419 .remove = __exit_p(nmk_gpio_remove),
420 .suspend = NULL, /* to be done */ 628 .suspend = NULL, /* to be done */
421 .resume = NULL, 629 .resume = NULL,
422}; 630};
@@ -426,7 +634,7 @@ static int __init nmk_gpio_init(void)
426 return platform_driver_register(&nmk_gpio_driver); 634 return platform_driver_register(&nmk_gpio_driver);
427} 635}
428 636
429arch_initcall(nmk_gpio_init); 637core_initcall(nmk_gpio_init);
430 638
431MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 639MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
432MODULE_DESCRIPTION("Nomadik GPIO Driver"); 640MODULE_DESCRIPTION("Nomadik GPIO Driver");
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 4200811249ca..aba355101f49 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -55,6 +55,21 @@
55#define NMK_GPIO_ALT_B 2 55#define NMK_GPIO_ALT_B 2
56#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) 56#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
57 57
58/* Pull up/down values */
59enum nmk_gpio_pull {
60 NMK_GPIO_PULL_NONE,
61 NMK_GPIO_PULL_UP,
62 NMK_GPIO_PULL_DOWN,
63};
64
65/* Sleep mode */
66enum nmk_gpio_slpm {
67 NMK_GPIO_SLPM_INPUT,
68 NMK_GPIO_SLPM_NOCHANGE,
69};
70
71extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
72extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
58extern int nmk_gpio_set_mode(int gpio, int gpio_mode); 73extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
59extern int nmk_gpio_get_mode(int gpio); 74extern int nmk_gpio_get_mode(int gpio);
60 75
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 42c907258b14..65704a3d4241 100644
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,6 +1,12 @@
1#ifndef __PLAT_MTU_H 1#ifndef __PLAT_MTU_H
2#define __PLAT_MTU_H 2#define __PLAT_MTU_H
3 3
4/*
5 * Guaranteed runtime conversion range in seconds for
6 * the clocksource and clockevent.
7 */
8#define MTU_MIN_RANGE 4
9
4/* should be set by the platform code */ 10/* should be set by the platform code */
5extern void __iomem *mtu_base; 11extern void __iomem *mtu_base;
6 12
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
new file mode 100644
index 000000000000..7eed11c1038d
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -0,0 +1,72 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 *
7 * Based on arch/arm/mach-pxa/include/mach/mfp.h:
8 * Copyright (C) 2007 Marvell International Ltd.
9 * eric miao <eric.miao@marvell.com>
10 */
11
12#ifndef __PLAT_PINCFG_H
13#define __PLAT_PINCFG_H
14
15/*
16 * pin configurations are represented by 32-bit integers:
17 *
18 * bit 0.. 8 - Pin Number (512 Pins Maximum)
19 * bit 9..10 - Alternate Function Selection
20 * bit 11..12 - Pull up/down state
21 * bit 13 - Sleep mode behaviour
22 *
23 * to facilitate the definition, the following macros are provided
24 *
25 * PIN_CFG_DEFAULT - default config (0):
26 * pull up/down = disabled
27 * sleep mode = input
28 *
29 * PIN_CFG - default config with alternate function
30 * PIN_CFG_PULL - default config with alternate function and pull up/down
31 */
32
33typedef unsigned long pin_cfg_t;
34
35#define PIN_NUM_MASK 0x1ff
36#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
37
38#define PIN_ALT_SHIFT 9
39#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
40#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
41#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
42#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
43#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
44#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
45
46#define PIN_PULL_SHIFT 11
47#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
48#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
49#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
50#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
51#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
52
53#define PIN_SLPM_SHIFT 13
54#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
55#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
56#define PIN_SLPM_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
57#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
58
59#define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT)
60
61#define PIN_CFG(num, alt) \
62 (PIN_CFG_DEFAULT |\
63 (PIN_NUM(num) | PIN_##alt))
64
65#define PIN_CFG_PULL(num, alt, pull) \
66 ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
67 (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
68
69extern int nmk_config_pin(pin_cfg_t cfg);
70extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
71
72#endif
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 08aaa4a7f65f..ea3ca86c5283 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -42,7 +42,6 @@ static struct clocksource nmdk_clksrc = {
42 .rating = 200, 42 .rating = 200,
43 .read = nmdk_read_timer_dummy, 43 .read = nmdk_read_timer_dummy,
44 .mask = CLOCKSOURCE_MASK(32), 44 .mask = CLOCKSOURCE_MASK(32),
45 .shift = 20,
46 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 45 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
47}; 46};
48 47
@@ -82,6 +81,12 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
82 case CLOCK_EVT_MODE_UNUSED: 81 case CLOCK_EVT_MODE_UNUSED:
83 /* disable irq */ 82 /* disable irq */
84 writel(0, mtu_base + MTU_IMSC); 83 writel(0, mtu_base + MTU_IMSC);
84 /* disable timer */
85 cr = readl(mtu_base + MTU_CR(1));
86 cr &= ~MTU_CRn_ENA;
87 writel(cr, mtu_base + MTU_CR(1));
88 /* load some high default value */
89 writel(0xffffffff, mtu_base + MTU_LR(1));
85 break; 90 break;
86 case CLOCK_EVT_MODE_RESUME: 91 case CLOCK_EVT_MODE_RESUME:
87 break; 92 break;
@@ -98,7 +103,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
98static struct clock_event_device nmdk_clkevt = { 103static struct clock_event_device nmdk_clkevt = {
99 .name = "mtu_1", 104 .name = "mtu_1",
100 .features = CLOCK_EVT_FEAT_ONESHOT, 105 .features = CLOCK_EVT_FEAT_ONESHOT,
101 .shift = 32,
102 .rating = 200, 106 .rating = 200,
103 .set_mode = nmdk_clkevt_mode, 107 .set_mode = nmdk_clkevt_mode,
104 .set_next_event = nmdk_clkevt_next, 108 .set_next_event = nmdk_clkevt_next,
@@ -151,6 +155,7 @@ void __init nmdk_timer_init(void)
151 } else { 155 } else {
152 cr |= MTU_CRn_PRESCALE_1; 156 cr |= MTU_CRn_PRESCALE_1;
153 } 157 }
158 clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
154 159
155 /* Timer 0 is the free running clocksource */ 160 /* Timer 0 is the free running clocksource */
156 writel(cr, mtu_base + MTU_CR(0)); 161 writel(cr, mtu_base + MTU_CR(0));
@@ -158,7 +163,6 @@ void __init nmdk_timer_init(void)
158 writel(0, mtu_base + MTU_BGLR(0)); 163 writel(0, mtu_base + MTU_BGLR(0));
159 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); 164 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
160 165
161 nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
162 /* Now the scheduling clock is ready */ 166 /* Now the scheduling clock is ready */
163 nmdk_clksrc.read = nmdk_read_timer; 167 nmdk_clksrc.read = nmdk_read_timer;
164 168
@@ -175,8 +179,10 @@ void __init nmdk_timer_init(void)
175 } else { 179 } else {
176 cr |= MTU_CRn_PRESCALE_1; 180 cr |= MTU_CRn_PRESCALE_1;
177 } 181 }
182 clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
183
178 writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ 184 writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
179 nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift); 185
180 nmdk_clkevt.max_delta_ns = 186 nmdk_clkevt.max_delta_ns =
181 clockevent_delta2ns(0xffffffff, &nmdk_clkevt); 187 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
182 nmdk_clkevt.min_delta_ns = 188 nmdk_clkevt.min_delta_ns =
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 219c01e82bc5..ebed82699eb2 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -22,6 +22,7 @@
22#include <linux/serial_reg.h> 22#include <linux/serial_reg.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/omapfb.h>
25 26
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <asm/system.h> 28#include <asm/system.h>
@@ -35,6 +36,7 @@
35#include <plat/mux.h> 36#include <plat/mux.h>
36#include <plat/fpga.h> 37#include <plat/fpga.h>
37#include <plat/serial.h> 38#include <plat/serial.h>
39#include <plat/vram.h>
38 40
39#include <plat/clock.h> 41#include <plat/clock.h>
40 42
@@ -81,6 +83,12 @@ const void *omap_get_var_config(u16 tag, size_t *len)
81} 83}
82EXPORT_SYMBOL(omap_get_var_config); 84EXPORT_SYMBOL(omap_get_var_config);
83 85
86void __init omap_reserve(void)
87{
88 omapfb_reserve_sdram_memblock();
89 omap_vram_reserve_sdram_memblock();
90}
91
84/* 92/*
85 * 32KHz clocksource ... always available, on pretty most chips except 93 * 32KHz clocksource ... always available, on pretty most chips except
86 * OMAP 730 and 1510. Other timers could be used as clocksources, with 94 * OMAP 730 and 1510. Other timers could be used as clocksources, with
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index d3eea4f47533..0054b9501a53 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -26,7 +26,7 @@
26#include <linux/mm.h> 26#include <linux/mm.h>
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/bootmem.h> 29#include <linux/memblock.h>
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/omapfb.h> 31#include <linux/omapfb.h>
32 32
@@ -171,49 +171,78 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
171 return 0; 171 return 0;
172} 172}
173 173
174static int valid_sdram(unsigned long addr, unsigned long size)
175{
176 struct memblock_property res;
177
178 res.base = addr;
179 res.size = size;
180 return !memblock_find(&res) && res.base == addr && res.size == size;
181}
182
183static int reserve_sdram(unsigned long addr, unsigned long size)
184{
185 if (memblock_is_region_reserved(addr, size))
186 return -EBUSY;
187 if (memblock_reserve(addr, size))
188 return -ENOMEM;
189 return 0;
190}
191
174/* 192/*
175 * Called from map_io. We need to call to this early enough so that we 193 * Called from map_io. We need to call to this early enough so that we
176 * can reserve the fixed SDRAM regions before VM could get hold of them. 194 * can reserve the fixed SDRAM regions before VM could get hold of them.
177 */ 195 */
178void __init omapfb_reserve_sdram(void) 196void __init omapfb_reserve_sdram_memblock(void)
179{ 197{
180 struct bootmem_data *bdata; 198 unsigned long reserved = 0;
181 unsigned long sdram_start, sdram_size; 199 int i;
182 unsigned long reserved;
183 int i;
184 200
185 if (config_invalid) 201 if (config_invalid)
186 return; 202 return;
187 203
188 bdata = NODE_DATA(0)->bdata;
189 sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
190 sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
191 reserved = 0;
192 for (i = 0; ; i++) { 204 for (i = 0; ; i++) {
193 struct omapfb_mem_region rg; 205 struct omapfb_mem_region rg;
194 206
195 if (get_fbmem_region(i, &rg) < 0) 207 if (get_fbmem_region(i, &rg) < 0)
196 break; 208 break;
209
197 if (i == OMAPFB_PLANE_NUM) { 210 if (i == OMAPFB_PLANE_NUM) {
198 printk(KERN_ERR 211 pr_err("Extraneous FB mem configuration entries\n");
199 "Extraneous FB mem configuration entries\n");
200 config_invalid = 1; 212 config_invalid = 1;
201 return; 213 return;
202 } 214 }
215
203 /* Check if it's our memory type. */ 216 /* Check if it's our memory type. */
204 if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SDRAM, 217 if (rg.type != OMAPFB_MEMTYPE_SDRAM)
205 sdram_start, sdram_size) < 0 ||
206 (rg.type != OMAPFB_MEMTYPE_SDRAM))
207 continue; 218 continue;
208 BUG_ON(omapfb_config.mem_desc.region[i].size); 219
209 if (check_fbmem_region(i, &rg, sdram_start, sdram_size) < 0) { 220 /* Check if the region falls within SDRAM */
221 if (rg.paddr && !valid_sdram(rg.paddr, rg.size))
222 continue;
223
224 if (rg.size == 0) {
225 pr_err("Zero size for FB region %d\n", i);
210 config_invalid = 1; 226 config_invalid = 1;
211 return; 227 return;
212 } 228 }
229
213 if (rg.paddr) { 230 if (rg.paddr) {
214 reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT); 231 if (reserve_sdram(rg.paddr, rg.size)) {
232 pr_err("Trying to use reserved memory for FB region %d\n",
233 i);
234 config_invalid = 1;
235 return;
236 }
215 reserved += rg.size; 237 reserved += rg.size;
216 } 238 }
239
240 if (omapfb_config.mem_desc.region[i].size) {
241 pr_err("FB region %d already set\n", i);
242 config_invalid = 1;
243 return;
244 }
245
217 omapfb_config.mem_desc.region[i] = rg; 246 omapfb_config.mem_desc.region[i] = rg;
218 configured_regions++; 247 configured_regions++;
219 } 248 }
@@ -359,7 +388,10 @@ static inline int omap_init_fb(void)
359 388
360arch_initcall(omap_init_fb); 389arch_initcall(omap_init_fb);
361 390
362void omapfb_reserve_sdram(void) {} 391void omapfb_reserve_sdram_memblock(void)
392{
393}
394
363unsigned long omapfb_reserve_sram(unsigned long sram_pstart, 395unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
364 unsigned long sram_vstart, 396 unsigned long sram_vstart,
365 unsigned long sram_size, 397 unsigned long sram_size,
@@ -375,7 +407,10 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data)
375{ 407{
376} 408}
377 409
378void omapfb_reserve_sdram(void) {} 410void omapfb_reserve_sdram_memblock(void)
411{
412}
413
379unsigned long omapfb_reserve_sram(unsigned long sram_pstart, 414unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
380 unsigned long sram_vstart, 415 unsigned long sram_vstart,
381 unsigned long sram_size, 416 unsigned long sram_size,
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index d265018f5e6b..5e4afbee0fd7 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -34,6 +34,8 @@ struct sys_timer;
34extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
36 36
37extern void omap_reserve(void);
38
37/* 39/*
38 * IO bases for various OMAP processors 40 * IO bases for various OMAP processors
39 * Except the tap base, rest all the io bases 41 * Except the tap base, rest all the io bases
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
index edd4987758a6..0aa4ecd12c7d 100644
--- a/arch/arm/plat-omap/include/plat/vram.h
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -38,7 +38,7 @@ extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
38extern void omap_vram_set_sdram_vram(u32 size, u32 start); 38extern void omap_vram_set_sdram_vram(u32 size, u32 start);
39extern void omap_vram_set_sram_vram(u32 size, u32 start); 39extern void omap_vram_set_sram_vram(u32 size, u32 start);
40 40
41extern void omap_vram_reserve_sdram(void); 41extern void omap_vram_reserve_sdram_memblock(void);
42extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart, 42extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
43 unsigned long sram_vstart, 43 unsigned long sram_vstart,
44 unsigned long sram_size, 44 unsigned long sram_size,
@@ -48,7 +48,7 @@ extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
48static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { } 48static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
49static inline void omap_vram_set_sram_vram(u32 size, u32 start) { } 49static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
50 50
51static inline void omap_vram_reserve_sdram(void) { } 51static inline void omap_vram_reserve_sdram_memblock(void) { }
52static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart, 52static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
53 unsigned long sram_vstart, 53 unsigned long sram_vstart,
54 unsigned long sram_size, 54 unsigned long sram_size,
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 54c84a492a0f..779553a1595e 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <asm/mach/pci.h> 14#include <asm/mach/pci.h>
15#include <plat/pcie.h> 15#include <plat/pcie.h>
16#include <linux/delay.h>
16 17
17/* 18/*
18 * PCIe unit register offsets. 19 * PCIe unit register offsets.
@@ -46,6 +47,8 @@
46#define PCIE_STAT_BUS_OFFS 8 47#define PCIE_STAT_BUS_OFFS 8
47#define PCIE_STAT_BUS_MASK 0xff 48#define PCIE_STAT_BUS_MASK 0xff
48#define PCIE_STAT_LINK_DOWN 1 49#define PCIE_STAT_LINK_DOWN 1
50#define PCIE_DEBUG_CTRL 0x1a60
51#define PCIE_DEBUG_SOFT_RESET (1<<20)
49 52
50 53
51u32 __init orion_pcie_dev_id(void __iomem *base) 54u32 __init orion_pcie_dev_id(void __iomem *base)
@@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
85 writel(stat, base + PCIE_STAT_OFF); 88 writel(stat, base + PCIE_STAT_OFF);
86} 89}
87 90
91void __init orion_pcie_reset(void __iomem *base)
92{
93 u32 reg;
94 int i;
95
96 /*
97 * MV-S104860-U0, Rev. C:
98 * PCI Express Unit Soft Reset
99 * When set, generates an internal reset in the PCI Express unit.
100 * This bit should be cleared after the link is re-established.
101 */
102 reg = readl(base + PCIE_DEBUG_CTRL);
103 reg |= PCIE_DEBUG_SOFT_RESET;
104 writel(reg, base + PCIE_DEBUG_CTRL);
105
106 for (i = 0; i < 20; i++) {
107 mdelay(10);
108
109 if (orion_pcie_link_up(base))
110 break;
111 }
112
113 reg &= ~(PCIE_DEBUG_SOFT_RESET);
114 writel(reg, base + PCIE_DEBUG_CTRL);
115}
116
88/* 117/*
89 * Setup PCIE BARs and Address Decode Wins: 118 * Setup PCIE BARs and Address Decode Wins:
90 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 119 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -153,6 +182,11 @@ void __init orion_pcie_setup(void __iomem *base,
153 u32 mask; 182 u32 mask;
154 183
155 /* 184 /*
185 * soft reset PCIe unit
186 */
187 orion_pcie_reset(base);
188
189 /*
156 * Point PCIe unit MBUS decode windows to DRAM space. 190 * Point PCIe unit MBUS decode windows to DRAM space.
157 */ 191 */
158 orion_pcie_setup_wins(base, dram); 192 orion_pcie_setup_wins(base, dram);
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index a1025d38f383..ab211652e4ca 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -58,6 +58,11 @@
58 58
59#define INT_STATUS 0x1 59#define INT_STATUS 0x1
60 60
61/*
62 * Minimum clocksource/clockevent timer range in seconds
63 */
64#define SPEAR_MIN_RANGE 4
65
61static __iomem void *gpt_base; 66static __iomem void *gpt_base;
62static struct clk *gpt_clk; 67static struct clk *gpt_clk;
63 68
@@ -66,44 +71,6 @@ static void clockevent_set_mode(enum clock_event_mode mode,
66static int clockevent_next_event(unsigned long evt, 71static int clockevent_next_event(unsigned long evt,
67 struct clock_event_device *clk_event_dev); 72 struct clock_event_device *clk_event_dev);
68 73
69/*
70 * Following clocksource_set_clock and clockevent_set_clock picked
71 * from arch/mips/kernel/time.c
72 */
73
74void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
75{
76 u64 temp;
77 u32 shift;
78
79 /* Find a shift value */
80 for (shift = 32; shift > 0; shift--) {
81 temp = (u64) NSEC_PER_SEC << shift;
82 do_div(temp, clock);
83 if ((temp >> 32) == 0)
84 break;
85 }
86 cs->shift = shift;
87 cs->mult = (u32) temp;
88}
89
90void __init clockevent_set_clock(struct clock_event_device *cd,
91 unsigned int clock)
92{
93 u64 temp;
94 u32 shift;
95
96 /* Find a shift value */
97 for (shift = 32; shift > 0; shift--) {
98 temp = (u64) clock << shift;
99 do_div(temp, NSEC_PER_SEC);
100 if ((temp >> 32) == 0)
101 break;
102 }
103 cd->shift = shift;
104 cd->mult = (u32) temp;
105}
106
107static cycle_t clocksource_read_cycles(struct clocksource *cs) 74static cycle_t clocksource_read_cycles(struct clocksource *cs)
108{ 75{
109 return (cycle_t) readw(gpt_base + COUNT(CLKSRC)); 76 return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
@@ -138,7 +105,7 @@ static void spear_clocksource_init(void)
138 val |= CTRL_ENABLE ; 105 val |= CTRL_ENABLE ;
139 writew(val, gpt_base + CR(CLKSRC)); 106 writew(val, gpt_base + CR(CLKSRC));
140 107
141 clocksource_set_clock(&clksrc, tick_rate); 108 clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE);
142 109
143 /* register the clocksource */ 110 /* register the clocksource */
144 clocksource_register(&clksrc); 111 clocksource_register(&clksrc);
@@ -233,7 +200,7 @@ static void __init spear_clockevent_init(void)
233 tick_rate = clk_get_rate(gpt_clk); 200 tick_rate = clk_get_rate(gpt_clk);
234 tick_rate >>= CTRL_PRESCALER16; 201 tick_rate >>= CTRL_PRESCALER16;
235 202
236 clockevent_set_clock(&clkevt, tick_rate); 203 clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
237 204
238 clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, 205 clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
239 &clkevt); 206 &clkevt);
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 9b1a66816aa6..5cf88e8427b1 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,3 +2,7 @@ obj-y := clock.o
2obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o 2obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
3obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o 3obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o
4obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o 4obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o
5ifeq ($(CONFIG_LEDS_CLASS),y)
6obj-$(CONFIG_ARCH_REALVIEW) += leds.o
7obj-$(CONFIG_ARCH_VERSATILE) += leds.o
8endif
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
new file mode 100644
index 000000000000..3169fa555ea6
--- /dev/null
+++ b/arch/arm/plat-versatile/leds.c
@@ -0,0 +1,103 @@
1/*
2 * Driver for the 8 user LEDs found on the RealViews and Versatiles
3 * Based on DaVinci's DM365 board code
4 *
5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Linus Walleij <triad@df.lth.se>
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/slab.h>
12#include <linux/leds.h>
13
14#include <mach/hardware.h>
15#include <mach/platform.h>
16
17#ifdef VERSATILE_SYS_BASE
18#define LEDREG (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
19#endif
20
21#ifdef REALVIEW_SYS_BASE
22#define LEDREG (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
23#endif
24
25struct versatile_led {
26 struct led_classdev cdev;
27 u8 mask;
28};
29
30/*
31 * The triggers lines up below will only be used if the
32 * LED triggers are compiled in.
33 */
34static const struct {
35 const char *name;
36 const char *trigger;
37} versatile_leds[] = {
38 { "versatile:0", "heartbeat", },
39 { "versatile:1", "mmc0", },
40 { "versatile:2", },
41 { "versatile:3", },
42 { "versatile:4", },
43 { "versatile:5", },
44 { "versatile:6", },
45 { "versatile:7", },
46};
47
48static void versatile_led_set(struct led_classdev *cdev,
49 enum led_brightness b)
50{
51 struct versatile_led *led = container_of(cdev,
52 struct versatile_led, cdev);
53 u32 reg = readl(LEDREG);
54
55 if (b != LED_OFF)
56 reg |= led->mask;
57 else
58 reg &= ~led->mask;
59 writel(reg, LEDREG);
60}
61
62static enum led_brightness versatile_led_get(struct led_classdev *cdev)
63{
64 struct versatile_led *led = container_of(cdev,
65 struct versatile_led, cdev);
66 u32 reg = readl(LEDREG);
67
68 return (reg & led->mask) ? LED_FULL : LED_OFF;
69}
70
71static int __init versatile_leds_init(void)
72{
73 int i;
74
75 /* All ON */
76 writel(0xff, LEDREG);
77 for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) {
78 struct versatile_led *led;
79
80 led = kzalloc(sizeof(*led), GFP_KERNEL);
81 if (!led)
82 break;
83
84 led->cdev.name = versatile_leds[i].name;
85 led->cdev.brightness_set = versatile_led_set;
86 led->cdev.brightness_get = versatile_led_get;
87 led->cdev.default_trigger = versatile_leds[i].trigger;
88 led->mask = BIT(i);
89
90 if (led_classdev_register(NULL, &led->cdev) < 0) {
91 kfree(led);
92 break;
93 }
94 }
95
96 return 0;
97}
98
99/*
100 * Since we may have triggers on any subsystem, defer registration
101 * until after subsystem_init.
102 */
103fs_initcall(versatile_leds_init);
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 315a540c7ce5..8063a322c790 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -15,6 +15,7 @@
15#include <linux/sched.h> 15#include <linux/sched.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18#include <asm/cputype.h>
18#include <asm/thread_notify.h> 19#include <asm/thread_notify.h>
19#include <asm/vfp.h> 20#include <asm/vfp.h>
20 21
@@ -549,10 +550,13 @@ static int __init vfp_init(void)
549 /* 550 /*
550 * Check for the presence of the Advanced SIMD 551 * Check for the presence of the Advanced SIMD
551 * load/store instructions, integer and single 552 * load/store instructions, integer and single
552 * precision floating point operations. 553 * precision floating point operations. Only check
554 * for NEON if the hardware has the MVFR registers.
553 */ 555 */
554 if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100) 556 if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
555 elf_hwcap |= HWCAP_NEON; 557 if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
558 elf_hwcap |= HWCAP_NEON;
559 }
556#endif 560#endif
557 } 561 }
558 return 0; 562 return 0;